formats
This commit is contained in:
parent
4ddcd40040
commit
f80420d6af
|
@ -1,4 +1,4 @@
|
|||
.\" $Id: x2y.1,v 1.1 2002/04/29 14:15:51 czo Exp $
|
||||
.\" $Id: x2y.1,v 1.2 2003/05/20 13:28:39 czo Exp $
|
||||
.TH X2Y 1 "October 1, 1997" "ASIM/LIP6" "ALLIANCE USER COMMANDS"
|
||||
|
||||
.SH NAME
|
||||
|
@ -12,11 +12,35 @@
|
|||
\f4x2y\fR \fIin_format out_format in_file out_file\fR
|
||||
|
||||
.SH DESCRIPTION
|
||||
\f4x2y\fR is a netlist format converter
|
||||
|
||||
\f4x2y\fR is a netlist format converter
|
||||
|
||||
.PP
|
||||
.br
|
||||
al ALLIANCE netlist
|
||||
.br
|
||||
ap ALLIANCE layout
|
||||
.br
|
||||
cct HILO netlist
|
||||
.br
|
||||
cp VTI layout
|
||||
.br
|
||||
edi EDIF netlist or layout
|
||||
.br
|
||||
fne VTI extracted netlist
|
||||
.br
|
||||
hns VTI netlist
|
||||
.br
|
||||
spi, sp, cir SPICE netlist
|
||||
.br
|
||||
vlg VERILOG netlist
|
||||
.br
|
||||
vst VHDL netlist
|
||||
|
||||
.SH SEE ALSO
|
||||
.PP
|
||||
.BR mbk(1)
|
||||
.br
|
||||
mbk(1)
|
||||
|
||||
.so man1/alc_bug_report.1
|
||||
|
||||
|
|
|
@ -21,31 +21,27 @@
|
|||
* Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#ident "$Id: x2y.c,v 1.2 2002/09/30 16:21:35 czo Exp $"
|
||||
#ident "$Id: x2y.c,v 1.3 2003/05/20 13:28:39 czo Exp $"
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include "mut.h"
|
||||
#include "mlo.h"
|
||||
#include "mph.h"
|
||||
|
||||
/***********************************************************************
|
||||
CP layout VTI
|
||||
HNS netlist VTI
|
||||
FNE extracted netlist VTI
|
||||
?? FDN extracted netlist DAX
|
||||
?? HDN extracted hierarchical netlist DAX
|
||||
/*
|
||||
|
||||
AP layout ALLIANCE
|
||||
AL netlist ALLIANCE
|
||||
|
||||
EDI netlist or layout EDIF
|
||||
|
||||
CCT structurel HILO
|
||||
VST structurel VHDL
|
||||
|
||||
SPI structurel SPICE
|
||||
***********************************************************************/
|
||||
al ALLIANCE netlist
|
||||
ap ALLIANCE layout
|
||||
cct HILO netlist
|
||||
cp VTI layout
|
||||
edi EDIF netlist or layout
|
||||
fne VTI extracted netlist
|
||||
hns VTI netlist
|
||||
spi, sp, cir SPICE netlist
|
||||
vlg VERILOG netlist
|
||||
vst VHDL netlist
|
||||
|
||||
*/
|
||||
|
||||
int main( argc, argv )
|
||||
|
||||
|
@ -67,7 +63,20 @@ int main( argc, argv )
|
|||
|
||||
if ( argc != 5 )
|
||||
{
|
||||
fprintf( stdout, "\tSyntax: x2y in_format out_format in_file out_file\n" );
|
||||
fprintf( stdout, "
|
||||
Syntax: x2y in_format out_format in_file out_file
|
||||
Where format is one of
|
||||
al ALLIANCE netlist
|
||||
ap ALLIANCE layout
|
||||
cct HILO netlist
|
||||
cp VTI layout
|
||||
edi EDIF netlist or layout
|
||||
fne VTI extracted netlist
|
||||
hns VTI netlist
|
||||
spi, sp, cir SPICE netlist
|
||||
vlg VERILOG netlist
|
||||
vst VHDL netlist
|
||||
" );
|
||||
return( 1 );
|
||||
}
|
||||
|
||||
|
|
Loading…
Reference in New Issue