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* rflib.lef : 

- Les fantomes LEF n'etaient pas a jour. D'ou des court-circuits dans
     les routages de la fifo (cellule rf_fifo_clock.ap)
This commit is contained in:
Jean-Paul Chaput 2001-04-10 16:31:57 +00:00
parent 6d3a7a7dfb
commit f64d3d1195
2 changed files with 141 additions and 441 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

64
alliance/share/cells/rflib/CATAL
View File

@ -1,32 +1,32 @@
rf_dec_bufad0 C rf_dec_bufad0 C
rf_dec_bufad1 C rf_dec_bufad1 C
rf_dec_bufad1r C rf_dec_bufad1r C
rf_dec_bufad2 C rf_dec_bufad2 C
rf_dec_bufad2r C rf_dec_bufad2r C
rf_dec_nand2 C rf_dec_nand2 C
rf_dec_nand3 C rf_dec_nand3 C
rf_dec_nand4 C rf_dec_nand4 C
rf_dec_nao3 C rf_dec_nao3 C
rf_dec_nbuf C rf_dec_nbuf C
rf_dec_nor3 C rf_dec_nor3 C
rf_fifo_buf C rf_fifo_buf C
rf_fifo_clock C rf_fifo_clock C
rf_fifo_empty C rf_fifo_empty C
rf_fifo_full C rf_fifo_full C
rf_fifo_inc C rf_fifo_inc C
rf_fifo_nop C rf_fifo_nop C
rf_fifo_ok C rf_fifo_ok C
rf_fifo_orand4 C rf_fifo_orand4 C
rf_fifo_orand5 C rf_fifo_orand5 C
rf_fifo_ptreset C rf_fifo_ptreset C
rf_fifo_ptset C rf_fifo_ptset C
rf_inmux_buf_2 C rf_inmux_buf_2 C
rf_inmux_buf_4 C rf_inmux_buf_4 C
rf_inmux_mem C rf_inmux_mem C
rf_mid_buf_2 C rf_mid_buf_2 C
rf_mid_buf_4 C rf_mid_buf_4 C
rf_mid_mem C rf_mid_mem C
rf_mid_mem_r0 C rf_mid_mem_r0 C
rf_out_buf_2 C rf_out_buf_2 C
rf_out_buf_4 C rf_out_buf_4 C
rf_out_mem C rf_out_mem C

518
alliance/share/cells/rflib/rflib.lef
View File

@ -50,9 +50,6 @@ MACRO rf_dec_bufad0
LAYER L_ALU1 ; LAYER L_ALU1 ;
WIDTH 6.00 ; WIDTH 6.00 ;
PATH 3.00 3.00 42.00 3.00 ; PATH 3.00 3.00 42.00 3.00 ;
LAYER L_ALU3 ;
WIDTH 12.00 ;
PATH 10.00 6.00 10.00 44.00 ;
END END
END vss END vss
OBS OBS
@ -113,8 +110,6 @@ MACRO rf_dec_bufad0
RECT 29.00 39.00 31.00 41.00 ; RECT 29.00 39.00 31.00 41.00 ;
RECT 34.00 39.00 36.00 41.00 ; RECT 34.00 39.00 36.00 41.00 ;
RECT 39.00 39.00 43.50 41.00 ; RECT 39.00 39.00 43.50 41.00 ;
LAYER L_ALU2 ;
RECT 4.00 -1.00 16.00 1.00 ;
END END
END rf_dec_bufad0 END rf_dec_bufad0
@ -125,13 +120,6 @@ MACRO rf_dec_bufad1
SIZE 50.00 BY 50.00 ; SIZE 50.00 BY 50.00 ;
SYMMETRY X Y ; SYMMETRY X Y ;
SITE core ; SITE core ;
PIN nq
DIRECTION OUTPUT ;
PORT
LAYER L_ALU3 ;
RECT 24.00 19.00 26.00 21.00 ;
END
END nq
PIN q PIN q
DIRECTION OUTPUT ; DIRECTION OUTPUT ;
PORT PORT
@ -139,6 +127,13 @@ MACRO rf_dec_bufad1
RECT 29.00 19.00 31.00 21.00 ; RECT 29.00 19.00 31.00 21.00 ;
END END
END q END q
PIN nq
DIRECTION OUTPUT ;
PORT
LAYER L_ALU3 ;
RECT 24.00 19.00 26.00 21.00 ;
END
END nq
PIN i PIN i
DIRECTION INPUT ; DIRECTION INPUT ;
PORT PORT
@ -164,9 +159,6 @@ MACRO rf_dec_bufad1
LAYER L_ALU1 ; LAYER L_ALU1 ;
WIDTH 6.00 ; WIDTH 6.00 ;
PATH 3.00 3.00 47.00 3.00 ; PATH 3.00 3.00 47.00 3.00 ;
LAYER L_ALU3 ;
WIDTH 12.00 ;
PATH 10.00 6.00 10.00 44.00 ;
END END
END vss END vss
OBS OBS
@ -236,146 +228,16 @@ MACRO rf_dec_bufad1
RECT 44.00 39.00 48.50 41.00 ; RECT 44.00 39.00 48.50 41.00 ;
LAYER L_ALU2 ; LAYER L_ALU2 ;
RECT 19.00 19.00 31.00 21.00 ; RECT 19.00 19.00 31.00 21.00 ;
RECT 4.00 -1.00 16.00 1.00 ;
END END
END rf_dec_bufad1 END rf_dec_bufad1
MACRO rf_dec_bufad1r
CLASS CORE ;
ORIGIN 0.00 0.00 ;
SIZE 50.00 BY 50.00 ;
SYMMETRY X Y ;
SITE core ;
PIN q
DIRECTION OUTPUT ;
PORT
LAYER L_ALU3 ;
RECT 29.00 19.00 31.00 21.00 ;
END
END q
PIN nq
DIRECTION OUTPUT ;
PORT
LAYER L_ALU3 ;
RECT 24.00 19.00 26.00 21.00 ;
END
END nq
PIN i
DIRECTION INPUT ;
PORT
LAYER L_ALU3 ;
RECT 19.00 19.00 21.00 21.00 ;
END
END i
PIN vdd
DIRECTION INOUT ;
USE power ;
SHAPE ABUTMENT ;
PORT
LAYER L_ALU1 ;
WIDTH 6.00 ;
PATH 3.00 47.00 47.00 47.00 ;
LAYER L_ALU3 ;
WIDTH 12.00 ;
PATH 10.00 6.00 10.00 44.00 ;
END
END vdd
PIN vss
DIRECTION INOUT ;
USE ground ;
SHAPE ABUTMENT ;
PORT
LAYER L_ALU1 ;
WIDTH 6.00 ;
PATH 3.00 3.00 47.00 3.00 ;
END
END vss
OBS
LAYER L_ALU1 ;
RECT 1.50 9.00 6.00 11.00 ;
RECT 9.00 9.00 11.00 11.00 ;
RECT 14.00 9.00 16.00 11.00 ;
RECT 19.00 9.00 21.00 11.00 ;
RECT 24.00 9.00 26.00 11.00 ;
RECT 29.00 9.00 31.00 11.00 ;
RECT 34.00 9.00 36.00 11.00 ;
RECT 39.00 9.00 41.00 11.00 ;
RECT 44.00 9.00 48.50 11.00 ;
RECT 1.50 14.00 6.00 16.00 ;
RECT 9.00 14.00 11.00 16.00 ;
RECT 14.00 14.00 16.00 16.00 ;
RECT 19.00 14.00 21.00 16.00 ;
RECT 24.00 14.00 26.00 16.00 ;
RECT 29.00 14.00 31.00 16.00 ;
RECT 34.00 14.00 36.00 16.00 ;
RECT 39.00 14.00 41.00 16.00 ;
RECT 44.00 14.00 48.50 16.00 ;
RECT 1.50 19.00 6.00 21.00 ;
RECT 9.00 19.00 11.00 21.00 ;
RECT 14.00 19.00 16.00 21.00 ;
RECT 19.00 19.00 21.00 21.00 ;
RECT 24.00 19.00 26.00 21.00 ;
RECT 29.00 19.00 31.00 21.00 ;
RECT 34.00 19.00 36.00 21.00 ;
RECT 39.00 19.00 41.00 21.00 ;
RECT 44.00 19.00 48.50 21.00 ;
RECT 1.50 24.00 6.00 26.00 ;
RECT 9.00 24.00 11.00 26.00 ;
RECT 14.00 24.00 16.00 26.00 ;
RECT 19.00 24.00 21.00 26.00 ;
RECT 24.00 24.00 26.00 26.00 ;
RECT 29.00 24.00 31.00 26.00 ;
RECT 34.00 24.00 36.00 26.00 ;
RECT 39.00 24.00 41.00 26.00 ;
RECT 44.00 24.00 48.50 26.00 ;
RECT 1.50 29.00 6.00 31.00 ;
RECT 9.00 29.00 11.00 31.00 ;
RECT 14.00 29.00 16.00 31.00 ;
RECT 19.00 29.00 21.00 31.00 ;
RECT 24.00 29.00 26.00 31.00 ;
RECT 29.00 29.00 31.00 31.00 ;
RECT 34.00 29.00 36.00 31.00 ;
RECT 39.00 29.00 41.00 31.00 ;
RECT 44.00 29.00 48.50 31.00 ;
RECT 1.50 34.00 6.00 36.00 ;
RECT 9.00 34.00 11.00 36.00 ;
RECT 14.00 34.00 16.00 36.00 ;
RECT 19.00 34.00 21.00 36.00 ;
RECT 24.00 34.00 26.00 36.00 ;
RECT 29.00 34.00 31.00 36.00 ;
RECT 34.00 34.00 36.00 36.00 ;
RECT 39.00 34.00 41.00 36.00 ;
RECT 44.00 34.00 48.50 36.00 ;
RECT 1.50 39.00 6.00 41.00 ;
RECT 9.00 39.00 11.00 41.00 ;
RECT 14.00 39.00 16.00 41.00 ;
RECT 19.00 39.00 21.00 41.00 ;
RECT 24.00 39.00 26.00 41.00 ;
RECT 29.00 39.00 31.00 41.00 ;
RECT 34.00 39.00 36.00 41.00 ;
RECT 39.00 39.00 41.00 41.00 ;
RECT 44.00 39.00 48.50 41.00 ;
LAYER L_ALU2 ;
RECT 19.00 19.00 31.00 21.00 ;
RECT 4.00 49.00 16.00 51.00 ;
END
END rf_dec_bufad1r
MACRO rf_dec_bufad2 MACRO rf_dec_bufad2
CLASS CORE ; CLASS CORE ;
ORIGIN 0.00 0.00 ; ORIGIN 0.00 0.00 ;
SIZE 50.00 BY 50.00 ; SIZE 50.00 BY 50.00 ;
SYMMETRY X Y ; SYMMETRY X Y ;
SITE core ; SITE core ;
PIN nq1
DIRECTION INOUT ;
PORT
LAYER L_ALU3 ;
RECT 34.00 19.00 36.00 21.00 ;
END
END nq1
PIN nq0 PIN nq0
DIRECTION INOUT ; DIRECTION INOUT ;
PORT PORT
@ -383,13 +245,13 @@ MACRO rf_dec_bufad2
RECT 29.00 19.00 31.00 21.00 ; RECT 29.00 19.00 31.00 21.00 ;
END END
END nq0 END nq0
PIN q1 PIN nq1
DIRECTION OUTPUT ; DIRECTION INOUT ;
PORT PORT
LAYER L_ALU3 ; LAYER L_ALU3 ;
RECT 44.00 19.00 46.00 21.00 ; RECT 34.00 19.00 36.00 21.00 ;
END END
END q1 END nq1
PIN q0 PIN q0
DIRECTION OUTPUT ; DIRECTION OUTPUT ;
PORT PORT
@ -397,13 +259,13 @@ MACRO rf_dec_bufad2
RECT 19.00 19.00 21.00 21.00 ; RECT 19.00 19.00 21.00 21.00 ;
END END
END q0 END q0
PIN i1 PIN q1
DIRECTION INPUT ; DIRECTION OUTPUT ;
PORT PORT
LAYER L_ALU3 ; LAYER L_ALU3 ;
RECT 39.00 19.00 41.00 21.00 ; RECT 44.00 19.00 46.00 21.00 ;
END END
END i1 END q1
PIN i0 PIN i0
DIRECTION INPUT ; DIRECTION INPUT ;
PORT PORT
@ -411,6 +273,13 @@ MACRO rf_dec_bufad2
RECT 24.00 19.00 26.00 21.00 ; RECT 24.00 19.00 26.00 21.00 ;
END END
END i0 END i0
PIN i1
DIRECTION INPUT ;
PORT
LAYER L_ALU3 ;
RECT 39.00 19.00 41.00 21.00 ;
END
END i1
PIN vdd PIN vdd
DIRECTION INOUT ; DIRECTION INOUT ;
USE power ; USE power ;
@ -429,9 +298,6 @@ MACRO rf_dec_bufad2
LAYER L_ALU1 ; LAYER L_ALU1 ;
WIDTH 6.00 ; WIDTH 6.00 ;
PATH 3.00 3.00 47.00 3.00 ; PATH 3.00 3.00 47.00 3.00 ;
LAYER L_ALU3 ;
WIDTH 12.00 ;
PATH 10.00 6.00 10.00 44.00 ;
END END
END vss END vss
OBS OBS
@ -501,154 +367,10 @@ MACRO rf_dec_bufad2
RECT 44.00 39.00 48.50 41.00 ; RECT 44.00 39.00 48.50 41.00 ;
LAYER L_ALU2 ; LAYER L_ALU2 ;
RECT 19.00 19.00 46.00 21.00 ; RECT 19.00 19.00 46.00 21.00 ;
RECT 4.00 -1.00 16.00 1.00 ;
END END
END rf_dec_bufad2 END rf_dec_bufad2
MACRO rf_dec_bufad2r
CLASS CORE ;
ORIGIN 0.00 0.00 ;
SIZE 50.00 BY 50.00 ;
SYMMETRY X Y ;
SITE core ;
PIN nq1
DIRECTION INOUT ;
PORT
LAYER L_ALU3 ;
RECT 34.00 19.00 36.00 21.00 ;
END
END nq1
PIN nq0
DIRECTION INOUT ;
PORT
LAYER L_ALU3 ;
RECT 29.00 19.00 31.00 21.00 ;
END
END nq0
PIN q1
DIRECTION OUTPUT ;
PORT
LAYER L_ALU3 ;
RECT 44.00 19.00 46.00 21.00 ;
END
END q1
PIN q0
DIRECTION OUTPUT ;
PORT
LAYER L_ALU3 ;
RECT 19.00 19.00 21.00 21.00 ;
END
END q0
PIN i1
DIRECTION INPUT ;
PORT
LAYER L_ALU3 ;
RECT 39.00 19.00 41.00 21.00 ;
END
END i1
PIN i0
DIRECTION INPUT ;
PORT
LAYER L_ALU3 ;
RECT 24.00 19.00 26.00 21.00 ;
END
END i0
PIN vdd
DIRECTION INOUT ;
USE power ;
SHAPE ABUTMENT ;
PORT
LAYER L_ALU1 ;
WIDTH 6.00 ;
PATH 3.00 47.00 47.00 47.00 ;
LAYER L_ALU3 ;
WIDTH 12.00 ;
PATH 10.00 6.00 10.00 44.00 ;
END
END vdd
PIN vss
DIRECTION INOUT ;
USE ground ;
SHAPE ABUTMENT ;
PORT
LAYER L_ALU1 ;
WIDTH 6.00 ;
PATH 3.00 3.00 47.00 3.00 ;
END
END vss
OBS
LAYER L_ALU1 ;
RECT 1.50 9.00 6.00 11.00 ;
RECT 9.00 9.00 11.00 11.00 ;
RECT 14.00 9.00 16.00 11.00 ;
RECT 19.00 9.00 21.00 11.00 ;
RECT 24.00 9.00 26.00 11.00 ;
RECT 29.00 9.00 31.00 11.00 ;
RECT 34.00 9.00 36.00 11.00 ;
RECT 39.00 9.00 41.00 11.00 ;
RECT 44.00 9.00 48.50 11.00 ;
RECT 1.50 14.00 6.00 16.00 ;
RECT 9.00 14.00 11.00 16.00 ;
RECT 14.00 14.00 16.00 16.00 ;
RECT 19.00 14.00 21.00 16.00 ;
RECT 24.00 14.00 26.00 16.00 ;
RECT 29.00 14.00 31.00 16.00 ;
RECT 34.00 14.00 36.00 16.00 ;
RECT 39.00 14.00 41.00 16.00 ;
RECT 44.00 14.00 48.50 16.00 ;
RECT 1.50 19.00 6.00 21.00 ;
RECT 9.00 19.00 11.00 21.00 ;
RECT 14.00 19.00 16.00 21.00 ;
RECT 19.00 19.00 21.00 21.00 ;
RECT 24.00 19.00 26.00 21.00 ;
RECT 29.00 19.00 31.00 21.00 ;
RECT 34.00 19.00 36.00 21.00 ;
RECT 39.00 19.00 41.00 21.00 ;
RECT 44.00 19.00 48.50 21.00 ;
RECT 1.50 24.00 6.00 26.00 ;
RECT 9.00 24.00 11.00 26.00 ;
RECT 14.00 24.00 16.00 26.00 ;
RECT 19.00 24.00 21.00 26.00 ;
RECT 24.00 24.00 26.00 26.00 ;
RECT 29.00 24.00 31.00 26.00 ;
RECT 34.00 24.00 36.00 26.00 ;
RECT 39.00 24.00 41.00 26.00 ;
RECT 44.00 24.00 48.50 26.00 ;
RECT 1.50 29.00 6.00 31.00 ;
RECT 9.00 29.00 11.00 31.00 ;
RECT 14.00 29.00 16.00 31.00 ;
RECT 19.00 29.00 21.00 31.00 ;
RECT 24.00 29.00 26.00 31.00 ;
RECT 29.00 29.00 31.00 31.00 ;
RECT 34.00 29.00 36.00 31.00 ;
RECT 39.00 29.00 41.00 31.00 ;
RECT 44.00 29.00 48.50 31.00 ;
RECT 1.50 34.00 6.00 36.00 ;
RECT 9.00 34.00 11.00 36.00 ;
RECT 14.00 34.00 16.00 36.00 ;
RECT 19.00 34.00 21.00 36.00 ;
RECT 24.00 34.00 26.00 36.00 ;
RECT 29.00 34.00 31.00 36.00 ;
RECT 34.00 34.00 36.00 36.00 ;
RECT 39.00 34.00 41.00 36.00 ;
RECT 44.00 34.00 48.50 36.00 ;
RECT 1.50 39.00 6.00 41.00 ;
RECT 9.00 39.00 11.00 41.00 ;
RECT 14.00 39.00 16.00 41.00 ;
RECT 19.00 39.00 21.00 41.00 ;
RECT 24.00 39.00 26.00 41.00 ;
RECT 29.00 39.00 31.00 41.00 ;
RECT 34.00 39.00 36.00 41.00 ;
RECT 39.00 39.00 41.00 41.00 ;
RECT 44.00 39.00 48.50 41.00 ;
LAYER L_ALU2 ;
RECT 19.00 19.00 46.00 21.00 ;
RECT 4.00 49.00 16.00 51.00 ;
END
END rf_dec_bufad2r
MACRO rf_dec_nand2 MACRO rf_dec_nand2
CLASS CORE ; CLASS CORE ;
ORIGIN 0.00 0.00 ; ORIGIN 0.00 0.00 ;
@ -1152,9 +874,6 @@ MACRO rf_dec_nbuf
LAYER L_ALU1 ; LAYER L_ALU1 ;
WIDTH 6.00 ; WIDTH 6.00 ;
PATH 3.00 47.00 52.00 47.00 ; PATH 3.00 47.00 52.00 47.00 ;
LAYER L_ALU3 ;
WIDTH 12.00 ;
PATH 45.00 6.00 45.00 44.00 ;
END END
END vdd END vdd
PIN vss PIN vss
@ -1239,8 +958,6 @@ MACRO rf_dec_nbuf
RECT 39.00 39.00 41.00 41.00 ; RECT 39.00 39.00 41.00 41.00 ;
RECT 44.00 39.00 46.00 41.00 ; RECT 44.00 39.00 46.00 41.00 ;
RECT 49.00 39.00 53.50 41.00 ; RECT 49.00 39.00 53.50 41.00 ;
LAYER L_ALU2 ;
RECT 39.00 49.00 51.00 51.00 ;
END END
END rf_dec_nbuf END rf_dec_nbuf
@ -1626,16 +1343,16 @@ MACRO rf_fifo_clock
DIRECTION INOUT ; DIRECTION INOUT ;
PORT PORT
LAYER L_ALU3 ; LAYER L_ALU3 ;
RECT 9.00 84.00 11.00 86.00 ; RECT 19.00 84.00 21.00 86.00 ;
RECT 9.00 79.00 11.00 81.00 ; RECT 19.00 79.00 21.00 81.00 ;
RECT 9.00 74.00 11.00 76.00 ; RECT 19.00 74.00 21.00 76.00 ;
RECT 9.00 69.00 11.00 71.00 ; RECT 19.00 69.00 21.00 71.00 ;
RECT 9.00 64.00 11.00 66.00 ; RECT 19.00 64.00 21.00 66.00 ;
RECT 9.00 59.00 11.00 61.00 ; RECT 19.00 59.00 21.00 61.00 ;
RECT 9.00 54.00 11.00 56.00 ; RECT 19.00 54.00 21.00 56.00 ;
RECT 9.00 49.00 11.00 51.00 ; RECT 19.00 49.00 21.00 51.00 ;
RECT 9.00 44.00 11.00 46.00 ; RECT 19.00 44.00 21.00 46.00 ;
RECT 9.00 39.00 11.00 41.00 ; RECT 19.00 39.00 21.00 41.00 ;
END END
END ckm END ckm
PIN cks PIN cks
@ -1679,6 +1396,14 @@ MACRO rf_fifo_clock
PIN ck PIN ck
DIRECTION INPUT ; DIRECTION INPUT ;
PORT PORT
LAYER L_ALU2 ;
RECT 49.00 69.00 51.00 71.00 ;
RECT 44.00 69.00 46.00 71.00 ;
RECT 39.00 69.00 41.00 71.00 ;
RECT 34.00 69.00 36.00 71.00 ;
RECT 29.00 69.00 31.00 71.00 ;
RECT 24.00 69.00 26.00 71.00 ;
RECT 19.00 69.00 21.00 71.00 ;
LAYER L_ALU3 ; LAYER L_ALU3 ;
RECT 49.00 69.00 51.00 71.00 ; RECT 49.00 69.00 51.00 71.00 ;
RECT 49.00 64.00 51.00 66.00 ; RECT 49.00 64.00 51.00 66.00 ;
@ -1690,14 +1415,6 @@ MACRO rf_fifo_clock
RECT 49.00 34.00 51.00 36.00 ; RECT 49.00 34.00 51.00 36.00 ;
RECT 49.00 29.00 51.00 31.00 ; RECT 49.00 29.00 51.00 31.00 ;
RECT 49.00 24.00 51.00 26.00 ; RECT 49.00 24.00 51.00 26.00 ;
LAYER L_ALU2 ;
RECT 49.00 69.00 51.00 71.00 ;
RECT 44.00 69.00 46.00 71.00 ;
RECT 39.00 69.00 41.00 71.00 ;
RECT 34.00 69.00 36.00 71.00 ;
RECT 29.00 69.00 31.00 71.00 ;
RECT 24.00 69.00 26.00 71.00 ;
RECT 19.00 69.00 21.00 71.00 ;
END END
END ck END ck
PIN vdd PIN vdd
@ -1855,17 +1572,17 @@ MACRO rf_fifo_clock
RECT 39.00 89.00 41.00 91.00 ; RECT 39.00 89.00 41.00 91.00 ;
RECT 44.00 89.00 48.50 91.00 ; RECT 44.00 89.00 48.50 91.00 ;
LAYER L_ALU2 ; LAYER L_ALU2 ;
RECT 9.00 24.00 51.00 26.00 ; RECT 9.00 39.00 46.00 41.00 ;
RECT 9.00 39.00 16.00 41.00 ;
RECT 24.00 39.00 31.00 41.00 ;
RECT 29.00 19.00 41.00 21.00 ; RECT 29.00 19.00 41.00 21.00 ;
RECT 9.00 24.00 36.00 26.00 ;
RECT 34.00 59.00 41.00 61.00 ;
RECT 9.00 84.00 36.00 86.00 ; RECT 9.00 84.00 36.00 86.00 ;
RECT 29.00 79.00 46.00 81.00 ; RECT 29.00 79.00 46.00 81.00 ;
RECT 9.00 84.00 36.00 86.00 ; RECT 34.00 59.00 41.00 61.00 ;
RECT 9.00 24.00 36.00 26.00 ;
RECT 29.00 19.00 41.00 21.00 ; RECT 29.00 19.00 41.00 21.00 ;
RECT 9.00 39.00 46.00 41.00 ; RECT 24.00 39.00 31.00 41.00 ;
RECT 9.00 24.00 51.00 26.00 ;
RECT 14.00 39.00 21.00 41.00 ;
RECT 19.00 84.00 36.00 86.00 ;
LAYER L_ALU3 ; LAYER L_ALU3 ;
RECT 39.00 19.00 41.00 61.00 ; RECT 39.00 19.00 41.00 61.00 ;
RECT 34.00 24.00 36.00 61.00 ; RECT 34.00 24.00 36.00 61.00 ;
@ -3159,20 +2876,6 @@ MACRO rf_inmux_buf_2
SIZE 45.00 BY 100.00 ; SIZE 45.00 BY 100.00 ;
SYMMETRY Y ; SYMMETRY Y ;
SITE core ; SITE core ;
PIN nck
DIRECTION OUTPUT ;
PORT
LAYER L_ALU2 ;
RECT 34.00 89.00 36.00 91.00 ;
END
END nck
PIN sel0
DIRECTION OUTPUT ;
PORT
LAYER L_ALU3 ;
RECT 34.00 39.00 36.00 41.00 ;
END
END sel0
PIN sel1 PIN sel1
DIRECTION OUTPUT ; DIRECTION OUTPUT ;
PORT PORT
@ -3180,17 +2883,20 @@ MACRO rf_inmux_buf_2
RECT 24.00 14.00 26.00 16.00 ; RECT 24.00 14.00 26.00 16.00 ;
END END
END sel1 END sel1
PIN ck PIN sel0
DIRECTION INPUT ; DIRECTION OUTPUT ;
PORT PORT
LAYER L_ALU1 ; LAYER L_ALU3 ;
RECT 19.00 89.00 21.00 91.00 ; RECT 34.00 39.00 36.00 41.00 ;
RECT 19.00 84.00 21.00 86.00 ;
RECT 19.00 79.00 21.00 81.00 ;
RECT 19.00 74.00 21.00 76.00 ;
RECT 19.00 69.00 21.00 71.00 ;
END END
END ck END sel0
PIN nck
DIRECTION OUTPUT ;
PORT
LAYER L_ALU2 ;
RECT 34.00 89.00 36.00 91.00 ;
END
END nck
PIN sel PIN sel
DIRECTION INPUT ; DIRECTION INPUT ;
PORT PORT
@ -3202,6 +2908,17 @@ MACRO rf_inmux_buf_2
RECT 14.00 69.00 16.00 71.00 ; RECT 14.00 69.00 16.00 71.00 ;
END END
END sel END sel
PIN ck
DIRECTION INPUT ;
PORT
LAYER L_ALU1 ;
RECT 19.00 89.00 21.00 91.00 ;
RECT 19.00 84.00 21.00 86.00 ;
RECT 19.00 79.00 21.00 81.00 ;
RECT 19.00 74.00 21.00 76.00 ;
RECT 19.00 69.00 21.00 71.00 ;
END
END ck
PIN vdd PIN vdd
DIRECTION INOUT ; DIRECTION INOUT ;
USE power ; USE power ;
@ -3226,9 +2943,6 @@ MACRO rf_inmux_buf_2
LAYER L_ALU1 ; LAYER L_ALU1 ;
WIDTH 6.00 ; WIDTH 6.00 ;
PATH 3.00 97.00 42.00 97.00 ; PATH 3.00 97.00 42.00 97.00 ;
LAYER L_ALU3 ;
WIDTH 12.00 ;
PATH 10.00 6.00 10.00 94.00 ;
END END
END vss END vss
OBS OBS
@ -3346,12 +3060,10 @@ MACRO rf_inmux_buf_2
RECT 34.00 89.00 36.00 91.00 ; RECT 34.00 89.00 36.00 91.00 ;
RECT 39.00 89.00 43.50 91.00 ; RECT 39.00 89.00 43.50 91.00 ;
LAYER L_ALU2 ; LAYER L_ALU2 ;
RECT 4.00 99.00 16.00 101.00 ;
RECT 4.00 -1.00 16.00 1.00 ;
RECT 26.00 39.00 40.00 41.00 ;
RECT 8.00 14.00 26.00 16.00 ;
RECT 4.00 14.00 26.00 16.00 ;
RECT 24.00 39.00 41.00 41.00 ; RECT 24.00 39.00 41.00 41.00 ;
RECT 4.00 14.00 26.00 16.00 ;
RECT 8.00 14.00 26.00 16.00 ;
RECT 26.00 39.00 40.00 41.00 ;
END END
END rf_inmux_buf_2 END rf_inmux_buf_2
@ -3760,32 +3472,6 @@ MACRO rf_inmux_mem
RECT 9.00 9.00 11.00 11.00 ; RECT 9.00 9.00 11.00 11.00 ;
END END
END dinx END dinx
PIN sel1
DIRECTION INPUT ;
PORT
LAYER L_ALU3 ;
RECT 24.00 29.00 26.00 31.00 ;
END
END sel1
PIN sel0
DIRECTION INPUT ;
PORT
LAYER L_ALU3 ;
RECT 34.00 29.00 36.00 31.00 ;
END
END sel0
PIN datain0
DIRECTION INPUT ;
PORT
LAYER L_ALU1 ;
RECT 19.00 39.00 21.00 41.00 ;
RECT 19.00 34.00 21.00 36.00 ;
RECT 19.00 29.00 21.00 31.00 ;
RECT 19.00 24.00 21.00 26.00 ;
RECT 19.00 19.00 21.00 21.00 ;
RECT 19.00 14.00 21.00 16.00 ;
END
END datain0
PIN datain1 PIN datain1
DIRECTION INPUT ; DIRECTION INPUT ;
PORT PORT
@ -3798,6 +3484,32 @@ MACRO rf_inmux_mem
RECT 39.00 14.00 41.00 16.00 ; RECT 39.00 14.00 41.00 16.00 ;
END END
END datain1 END datain1
PIN datain0
DIRECTION INPUT ;
PORT
LAYER L_ALU1 ;
RECT 19.00 39.00 21.00 41.00 ;
RECT 19.00 34.00 21.00 36.00 ;
RECT 19.00 29.00 21.00 31.00 ;
RECT 19.00 24.00 21.00 26.00 ;
RECT 19.00 19.00 21.00 21.00 ;
RECT 19.00 14.00 21.00 16.00 ;
END
END datain0
PIN sel0
DIRECTION INPUT ;
PORT
LAYER L_ALU3 ;
RECT 34.00 29.00 36.00 31.00 ;
END
END sel0
PIN sel1
DIRECTION INPUT ;
PORT
LAYER L_ALU3 ;
RECT 24.00 29.00 26.00 31.00 ;
END
END sel1
PIN vdd PIN vdd
DIRECTION INOUT ; DIRECTION INOUT ;
USE power ; USE power ;
@ -3816,9 +3528,6 @@ MACRO rf_inmux_mem
LAYER L_ALU1 ; LAYER L_ALU1 ;
WIDTH 6.00 ; WIDTH 6.00 ;
PATH 3.00 3.00 42.00 3.00 ; PATH 3.00 3.00 42.00 3.00 ;
LAYER L_ALU3 ;
WIDTH 12.00 ;
PATH 10.00 6.00 10.00 44.00 ;
END END
END vss END vss
OBS OBS
@ -3881,7 +3590,6 @@ MACRO rf_inmux_mem
RECT 39.00 39.00 43.50 41.00 ; RECT 39.00 39.00 43.50 41.00 ;
LAYER L_ALU2 ; LAYER L_ALU2 ;
RECT 24.00 29.00 36.00 31.00 ; RECT 24.00 29.00 36.00 31.00 ;
RECT 4.00 -1.00 16.00 1.00 ;
END END
END rf_inmux_mem END rf_inmux_mem
@ -4488,9 +4196,6 @@ MACRO rf_out_buf_2
LAYER L_ALU1 ; LAYER L_ALU1 ;
WIDTH 6.00 ; WIDTH 6.00 ;
PATH 3.00 53.00 52.00 53.00 ; PATH 3.00 53.00 52.00 53.00 ;
LAYER L_ALU3 ;
WIDTH 12.00 ;
PATH 45.00 6.00 45.00 94.00 ;
END END
END vdd END vdd
PIN vss PIN vss
@ -4649,10 +4354,9 @@ MACRO rf_out_buf_2
RECT 44.00 89.00 46.00 91.00 ; RECT 44.00 89.00 46.00 91.00 ;
RECT 49.00 89.00 53.50 91.00 ; RECT 49.00 89.00 53.50 91.00 ;
LAYER L_ALU2 ; LAYER L_ALU2 ;
RECT 39.00 49.00 51.00 51.00 ;
RECT 9.00 14.00 21.00 16.00 ;
RECT 9.00 39.00 21.00 41.00 ;
RECT 9.00 59.00 21.00 61.00 ; RECT 9.00 59.00 21.00 61.00 ;
RECT 9.00 39.00 21.00 41.00 ;
RECT 9.00 14.00 21.00 16.00 ;
END END
END rf_out_buf_2 END rf_out_buf_2
@ -5066,13 +4770,6 @@ MACRO rf_out_mem
RECT 44.00 9.00 46.00 11.00 ; RECT 44.00 9.00 46.00 11.00 ;
END END
END dataout END dataout
PIN rbus
DIRECTION INPUT ;
PORT
LAYER L_ALU2 ;
RECT 4.00 24.00 6.00 26.00 ;
END
END rbus
PIN xcks PIN xcks
DIRECTION INPUT ; DIRECTION INPUT ;
PORT PORT
@ -5080,6 +4777,13 @@ MACRO rf_out_mem
RECT 14.00 24.00 16.00 26.00 ; RECT 14.00 24.00 16.00 26.00 ;
END END
END xcks END xcks
PIN rbus
DIRECTION INPUT ;
PORT
LAYER L_ALU2 ;
RECT 4.00 24.00 6.00 26.00 ;
END
END rbus
PIN vdd PIN vdd
DIRECTION INOUT ; DIRECTION INOUT ;
USE power ; USE power ;
@ -5088,9 +4792,6 @@ MACRO rf_out_mem
LAYER L_ALU1 ; LAYER L_ALU1 ;
WIDTH 6.00 ; WIDTH 6.00 ;
PATH 3.00 47.00 52.00 47.00 ; PATH 3.00 47.00 52.00 47.00 ;
LAYER L_ALU3 ;
WIDTH 12.00 ;
PATH 45.00 6.00 45.00 44.00 ;
END END
END vdd END vdd
PIN vss PIN vss
@ -5176,9 +4877,8 @@ MACRO rf_out_mem
RECT 44.00 39.00 46.00 41.00 ; RECT 44.00 39.00 46.00 41.00 ;
RECT 49.00 39.00 53.50 41.00 ; RECT 49.00 39.00 53.50 41.00 ;
LAYER L_ALU2 ; LAYER L_ALU2 ;
RECT 39.00 49.00 51.00 51.00 ;
RECT 14.00 24.00 24.00 26.00 ;
RECT 14.00 24.00 26.00 26.00 ; RECT 14.00 24.00 26.00 26.00 ;
RECT 14.00 24.00 24.00 26.00 ;
END END
END rf_out_mem END rf_out_mem