diff --git a/alliance/src/cells/src/sxlib/sxlib.lef b/alliance/src/cells/src/sxlib/sxlib.lef index 516b9001..32911934 100644 --- a/alliance/src/cells/src/sxlib/sxlib.lef +++ b/alliance/src/cells/src/sxlib/sxlib.lef @@ -1,4 +1,10 @@ +VERSION 5.2 ; +NAMECASESENSITIVE ON ; +BUSBITCHARS "()" ; +BIVIDERCHAR "." ; + + MACRO a2_x2 CLASS CORE ; ORIGIN 0.00 0.00 ; @@ -18,17 +24,6 @@ MACRO a2_x2 RECT 19.00 9.00 21.00 11.00 ; END END q - PIN i0 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - END - END i0 PIN i1 DIRECTION INPUT ; PORT @@ -42,6 +37,17 @@ MACRO a2_x2 RECT 14.00 9.00 16.00 11.00 ; END END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i0 PIN vdd DIRECTION INOUT ; USE power ; @@ -158,28 +164,6 @@ MACRO a3_x2 RECT 24.00 9.00 26.00 11.00 ; END END q - PIN i2 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END i2 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - END - END i0 PIN i1 DIRECTION INPUT ; PORT @@ -191,6 +175,28 @@ MACRO a3_x2 RECT 9.00 14.00 11.00 16.00 ; END END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i0 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i2 PIN vdd DIRECTION INOUT ; USE power ; @@ -316,30 +322,17 @@ MACRO a4_x2 RECT 29.00 9.00 31.00 11.00 ; END END q - PIN i0 + PIN i3 DIRECTION INPUT ; PORT LAYER L_ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; END - END i0 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - RECT 14.00 9.00 16.00 11.00 ; - END - END i2 + END i3 PIN i1 DIRECTION INPUT ; PORT @@ -352,17 +345,30 @@ MACRO a4_x2 RECT 9.00 9.00 11.00 11.00 ; END END i1 - PIN i3 + PIN i2 DIRECTION INPUT ; PORT LAYER L_ALU1 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; END - END i3 + END i2 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 PIN vdd DIRECTION INOUT ; USE power ; @@ -645,28 +651,6 @@ MACRO ao22_x2 RECT 24.00 9.00 26.00 11.00 ; END END q - PIN i0 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 4.00 39.00 6.00 41.00 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - END - END i1 PIN i2 DIRECTION INPUT ; PORT @@ -680,6 +664,28 @@ MACRO ao22_x2 RECT 19.00 9.00 21.00 11.00 ; END END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + END + END i0 PIN vdd DIRECTION INOUT ; USE power ; @@ -726,6 +732,28 @@ MACRO ao22_x4 RECT 29.00 9.00 31.00 11.00 ; END END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + END + END i0 PIN i2 DIRECTION INPUT ; PORT @@ -739,28 +767,6 @@ MACRO ao22_x4 RECT 19.00 9.00 21.00 11.00 ; END END i2 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 4.00 39.00 6.00 41.00 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - END - END i1 PIN vdd DIRECTION INOUT ; USE power ; @@ -807,39 +813,6 @@ MACRO ao2o22_x2 RECT 39.00 9.00 41.00 11.00 ; END END q - PIN i3 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 24.00 34.00 26.00 36.00 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - END - END i3 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - END - END i2 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - END - END i1 PIN i0 DIRECTION INPUT ; PORT @@ -851,6 +824,39 @@ MACRO ao2o22_x2 RECT 4.00 19.00 6.00 21.00 ; END END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i3 PIN vdd DIRECTION INOUT ; USE power ; @@ -897,39 +903,6 @@ MACRO ao2o22_x4 RECT 39.00 9.00 41.00 11.00 ; END END q - PIN i3 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 24.00 34.00 26.00 36.00 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - END - END i3 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - END - END i2 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - END - END i1 PIN i0 DIRECTION INPUT ; PORT @@ -941,6 +914,39 @@ MACRO ao2o22_x4 RECT 4.00 19.00 6.00 21.00 ; END END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i3 PIN vdd DIRECTION INOUT ; USE power ; @@ -1151,6 +1157,19 @@ MACRO fulladder_x2 SIZE 100.00 BY 50.00 ; SYMMETRY X Y ; SITE core ; + PIN cout + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + LAYER L_ALU1 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END cout PIN sout DIRECTION OUTPUT ; PORT @@ -1163,52 +1182,76 @@ MACRO fulladder_x2 RECT 49.00 9.00 51.00 11.00 ; END END sout - PIN cout - DIRECTION OUTPUT ; - PORT - LAYER L_ALU1 ; - RECT 39.00 14.00 41.00 16.00 ; - RECT 39.00 9.00 41.00 11.00 ; - LAYER L_ALU1 ; - RECT 34.00 29.00 36.00 31.00 ; - RECT 34.00 24.00 36.00 26.00 ; - RECT 34.00 19.00 36.00 21.00 ; - RECT 34.00 14.00 36.00 16.00 ; - END - END cout - PIN b4 + PIN cin1 DIRECTION INPUT ; PORT LAYER L_ALU1 ; - RECT 94.00 34.00 96.00 36.00 ; - RECT 94.00 29.00 96.00 31.00 ; - RECT 94.00 24.00 96.00 26.00 ; - RECT 94.00 19.00 96.00 21.00 ; - RECT 94.00 14.00 96.00 16.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; END - END b4 - PIN a4 + END cin1 + PIN a2 DIRECTION INPUT ; PORT LAYER L_ALU1 ; - RECT 89.00 34.00 91.00 36.00 ; - RECT 89.00 29.00 91.00 31.00 ; - RECT 89.00 24.00 91.00 26.00 ; - RECT 89.00 19.00 91.00 21.00 ; - RECT 89.00 14.00 91.00 16.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; END - END a4 - PIN b1 + END a2 + PIN b2 DIRECTION INPUT ; PORT LAYER L_ALU1 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; END - END b1 + END b2 + PIN a3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 59.00 14.00 61.00 16.00 ; + END + END a3 + PIN b3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 64.00 29.00 66.00 31.00 ; + RECT 64.00 24.00 66.00 26.00 ; + RECT 64.00 19.00 66.00 21.00 ; + RECT 64.00 14.00 66.00 16.00 ; + END + END b3 + PIN cin2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 69.00 29.00 71.00 31.00 ; + RECT 69.00 24.00 71.00 26.00 ; + RECT 69.00 19.00 71.00 21.00 ; + RECT 69.00 14.00 71.00 16.00 ; + END + END cin2 + PIN cin3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 84.00 29.00 86.00 31.00 ; + RECT 84.00 24.00 86.00 26.00 ; + RECT 84.00 19.00 86.00 21.00 ; + RECT 84.00 14.00 86.00 16.00 ; + END + END cin3 PIN a1 DIRECTION INPUT ; PORT @@ -1221,76 +1264,39 @@ MACRO fulladder_x2 RECT 4.00 9.00 6.00 11.00 ; END END a1 - PIN cin3 + PIN b1 DIRECTION INPUT ; PORT LAYER L_ALU1 ; - RECT 84.00 29.00 86.00 31.00 ; - RECT 84.00 24.00 86.00 26.00 ; - RECT 84.00 19.00 86.00 21.00 ; - RECT 84.00 14.00 86.00 16.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; END - END cin3 - PIN cin2 + END b1 + PIN a4 DIRECTION INPUT ; PORT LAYER L_ALU1 ; - RECT 69.00 29.00 71.00 31.00 ; - RECT 69.00 24.00 71.00 26.00 ; - RECT 69.00 19.00 71.00 21.00 ; - RECT 69.00 14.00 71.00 16.00 ; + RECT 89.00 34.00 91.00 36.00 ; + RECT 89.00 29.00 91.00 31.00 ; + RECT 89.00 24.00 91.00 26.00 ; + RECT 89.00 19.00 91.00 21.00 ; + RECT 89.00 14.00 91.00 16.00 ; END - END cin2 - PIN b3 + END a4 + PIN b4 DIRECTION INPUT ; PORT LAYER L_ALU1 ; - RECT 64.00 29.00 66.00 31.00 ; - RECT 64.00 24.00 66.00 26.00 ; - RECT 64.00 19.00 66.00 21.00 ; - RECT 64.00 14.00 66.00 16.00 ; + RECT 94.00 34.00 96.00 36.00 ; + RECT 94.00 29.00 96.00 31.00 ; + RECT 94.00 24.00 96.00 26.00 ; + RECT 94.00 19.00 96.00 21.00 ; + RECT 94.00 14.00 96.00 16.00 ; END - END b3 - PIN a3 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 59.00 29.00 61.00 31.00 ; - RECT 59.00 24.00 61.00 26.00 ; - RECT 59.00 19.00 61.00 21.00 ; - RECT 59.00 14.00 61.00 16.00 ; - END - END a3 - PIN b2 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - RECT 29.00 14.00 31.00 16.00 ; - END - END b2 - PIN a2 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - END - END a2 - PIN cin1 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - END - END cin1 + END b4 PIN vdd DIRECTION INOUT ; USE power ; @@ -1324,18 +1330,6 @@ MACRO fulladder_x4 SIZE 105.00 BY 50.00 ; SYMMETRY X Y ; SITE core ; - PIN cout - DIRECTION OUTPUT ; - PORT - LAYER L_ALU1 ; - RECT 44.00 34.00 46.00 36.00 ; - RECT 44.00 29.00 46.00 31.00 ; - RECT 44.00 24.00 46.00 26.00 ; - RECT 44.00 19.00 46.00 21.00 ; - RECT 44.00 14.00 46.00 16.00 ; - RECT 44.00 9.00 46.00 11.00 ; - END - END cout PIN sout DIRECTION OUTPUT ; PORT @@ -1348,108 +1342,18 @@ MACRO fulladder_x4 RECT 54.00 9.00 56.00 11.00 ; END END sout - PIN a3 - DIRECTION INPUT ; + PIN cout + DIRECTION OUTPUT ; PORT LAYER L_ALU1 ; - RECT 64.00 29.00 66.00 31.00 ; - RECT 64.00 24.00 66.00 26.00 ; - RECT 64.00 19.00 66.00 21.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 44.00 9.00 46.00 11.00 ; END - END a3 - PIN cin2 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 74.00 29.00 76.00 31.00 ; - RECT 74.00 24.00 76.00 26.00 ; - RECT 74.00 19.00 76.00 21.00 ; - RECT 74.00 14.00 76.00 16.00 ; - END - END cin2 - PIN b3 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 69.00 29.00 71.00 31.00 ; - RECT 69.00 24.00 71.00 26.00 ; - RECT 69.00 19.00 71.00 21.00 ; - RECT 69.00 14.00 71.00 16.00 ; - END - END b3 - PIN cin3 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 89.00 29.00 91.00 31.00 ; - RECT 89.00 24.00 91.00 26.00 ; - RECT 89.00 19.00 91.00 21.00 ; - RECT 89.00 14.00 91.00 16.00 ; - END - END cin3 - PIN a4 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 94.00 34.00 96.00 36.00 ; - RECT 94.00 29.00 96.00 31.00 ; - RECT 94.00 24.00 96.00 26.00 ; - RECT 94.00 19.00 96.00 21.00 ; - RECT 94.00 14.00 96.00 16.00 ; - END - END a4 - PIN b4 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 99.00 34.00 101.00 36.00 ; - RECT 99.00 29.00 101.00 31.00 ; - RECT 99.00 24.00 101.00 26.00 ; - RECT 99.00 19.00 101.00 21.00 ; - RECT 99.00 14.00 101.00 16.00 ; - END - END b4 - PIN b2 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - RECT 29.00 14.00 31.00 16.00 ; - END - END b2 - PIN a2 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - END - END a2 - PIN cin1 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - END - END cin1 - PIN b1 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END b1 + END cout PIN a1 DIRECTION INPUT ; PORT @@ -1462,6 +1366,108 @@ MACRO fulladder_x4 RECT 4.00 9.00 6.00 11.00 ; END END a1 + PIN b1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END b1 + PIN cin1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END cin1 + PIN a2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END a2 + PIN b2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END b2 + PIN b4 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 99.00 34.00 101.00 36.00 ; + RECT 99.00 29.00 101.00 31.00 ; + RECT 99.00 24.00 101.00 26.00 ; + RECT 99.00 19.00 101.00 21.00 ; + RECT 99.00 14.00 101.00 16.00 ; + END + END b4 + PIN a4 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 94.00 34.00 96.00 36.00 ; + RECT 94.00 29.00 96.00 31.00 ; + RECT 94.00 24.00 96.00 26.00 ; + RECT 94.00 19.00 96.00 21.00 ; + RECT 94.00 14.00 96.00 16.00 ; + END + END a4 + PIN cin3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 89.00 29.00 91.00 31.00 ; + RECT 89.00 24.00 91.00 26.00 ; + RECT 89.00 19.00 91.00 21.00 ; + RECT 89.00 14.00 91.00 16.00 ; + END + END cin3 + PIN b3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 69.00 29.00 71.00 31.00 ; + RECT 69.00 24.00 71.00 26.00 ; + RECT 69.00 19.00 71.00 21.00 ; + RECT 69.00 14.00 71.00 16.00 ; + END + END b3 + PIN cin2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 74.00 29.00 76.00 31.00 ; + RECT 74.00 24.00 76.00 26.00 ; + RECT 74.00 19.00 76.00 21.00 ; + RECT 74.00 14.00 76.00 16.00 ; + END + END cin2 + PIN a3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 64.00 29.00 66.00 31.00 ; + RECT 64.00 24.00 66.00 26.00 ; + RECT 64.00 19.00 66.00 21.00 ; + END + END a3 PIN vdd DIRECTION INOUT ; USE power ; @@ -1579,19 +1585,6 @@ MACRO halfadder_x4 SIZE 90.00 BY 50.00 ; SYMMETRY X Y ; SITE core ; - PIN cout - DIRECTION OUTPUT ; - PORT - LAYER L_ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END cout PIN sout DIRECTION OUTPUT ; PORT @@ -1605,6 +1598,31 @@ MACRO halfadder_x4 RECT 79.00 9.00 81.00 11.00 ; END END sout + PIN cout + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END cout + PIN b + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END b PIN a DIRECTION INPUT ; PORT @@ -1618,18 +1636,6 @@ MACRO halfadder_x4 RECT 14.00 9.00 16.00 11.00 ; END END a - PIN b - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 39.00 34.00 41.00 36.00 ; - RECT 39.00 29.00 41.00 31.00 ; - RECT 39.00 24.00 41.00 26.00 ; - RECT 39.00 19.00 41.00 21.00 ; - RECT 39.00 14.00 41.00 16.00 ; - RECT 39.00 9.00 41.00 11.00 ; - END - END b PIN vdd DIRECTION INOUT ; USE power ; @@ -1912,6 +1918,30 @@ MACRO mx2_x2 RECT 39.00 9.00 41.00 11.00 ; END END q + PIN cmd + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END cmd + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i0 PIN i1 DIRECTION INPUT ; PORT @@ -1925,30 +1955,6 @@ MACRO mx2_x2 RECT 29.00 9.00 31.00 11.00 ; END END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i0 - PIN cmd - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 14.00 39.00 16.00 41.00 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END cmd PIN vdd DIRECTION INOUT ; USE power ; @@ -2068,50 +2074,16 @@ MACRO mx3_x2 PIN q DIRECTION OUTPUT ; PORT + LAYER L_ALU1 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 59.00 9.00 61.00 11.00 ; LAYER L_ALU1 ; RECT 59.00 39.00 61.00 41.00 ; RECT 59.00 34.00 61.00 36.00 ; RECT 59.00 29.00 61.00 31.00 ; RECT 59.00 24.00 61.00 26.00 ; - LAYER L_ALU1 ; - RECT 59.00 14.00 61.00 16.00 ; - RECT 59.00 9.00 61.00 11.00 ; END END q - PIN i0 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 39.00 29.00 41.00 31.00 ; - LAYER L_ALU1 ; - RECT 44.00 24.00 46.00 26.00 ; - LAYER L_ALU1 ; - RECT 39.00 19.00 41.00 21.00 ; - END - END i0 - PIN cmd0 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 34.00 29.00 36.00 31.00 ; - RECT 34.00 24.00 36.00 26.00 ; - RECT 34.00 19.00 36.00 21.00 ; - END - END cmd0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 24.00 24.00 26.00 26.00 ; - END - END i1 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 14.00 24.00 16.00 26.00 ; - END - END i2 PIN cmd1 DIRECTION INPUT ; PORT @@ -2123,6 +2095,40 @@ MACRO mx3_x2 RECT 4.00 14.00 6.00 16.00 ; END END cmd1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 24.00 16.00 26.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 24.00 26.00 26.00 ; + END + END i1 + PIN cmd0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END cmd0 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 19.00 41.00 21.00 ; + LAYER L_ALU1 ; + RECT 44.00 24.00 46.00 26.00 ; + LAYER L_ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + END + END i0 PIN vdd DIRECTION INOUT ; USE power ; @@ -2160,28 +2166,40 @@ MACRO mx3_x4 DIRECTION OUTPUT ; PORT LAYER L_ALU1 ; - RECT 59.00 39.00 61.00 41.00 ; - RECT 59.00 34.00 61.00 36.00 ; - RECT 59.00 29.00 61.00 31.00 ; - RECT 59.00 24.00 61.00 26.00 ; + RECT 64.00 19.00 66.00 21.00 ; LAYER L_ALU1 ; RECT 59.00 14.00 61.00 16.00 ; RECT 59.00 9.00 61.00 11.00 ; LAYER L_ALU1 ; - RECT 64.00 19.00 66.00 21.00 ; + RECT 59.00 39.00 61.00 41.00 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 59.00 24.00 61.00 26.00 ; END END q - PIN i0 + PIN cmd0 DIRECTION INPUT ; PORT LAYER L_ALU1 ; - RECT 44.00 24.00 46.00 26.00 ; - LAYER L_ALU1 ; - RECT 39.00 29.00 41.00 31.00 ; - LAYER L_ALU1 ; - RECT 39.00 19.00 41.00 21.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; END - END i0 + END cmd0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 24.00 26.00 26.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 24.00 16.00 26.00 ; + END + END i2 PIN cmd1 DIRECTION INPUT ; PORT @@ -2193,29 +2211,17 @@ MACRO mx3_x4 RECT 4.00 14.00 6.00 16.00 ; END END cmd1 - PIN i2 + PIN i0 DIRECTION INPUT ; PORT LAYER L_ALU1 ; - RECT 14.00 24.00 16.00 26.00 ; - END - END i2 - PIN i1 - DIRECTION INPUT ; - PORT + RECT 39.00 19.00 41.00 21.00 ; LAYER L_ALU1 ; - RECT 24.00 24.00 26.00 26.00 ; - END - END i1 - PIN cmd0 - DIRECTION INPUT ; - PORT + RECT 39.00 29.00 41.00 31.00 ; LAYER L_ALU1 ; - RECT 34.00 29.00 36.00 31.00 ; - RECT 34.00 24.00 36.00 26.00 ; - RECT 34.00 19.00 36.00 21.00 ; + RECT 44.00 24.00 46.00 26.00 ; END - END cmd0 + END i0 PIN vdd DIRECTION INOUT ; USE power ; @@ -2332,17 +2338,6 @@ MACRO na2_x4 RECT 19.00 9.00 21.00 11.00 ; END END nq - PIN i0 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - END - END i0 PIN i1 DIRECTION INPUT ; PORT @@ -2354,6 +2349,17 @@ MACRO na2_x4 RECT 9.00 14.00 11.00 16.00 ; END END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i0 PIN vdd DIRECTION INOUT ; USE power ; @@ -2400,30 +2406,6 @@ MACRO na3_x1 RECT 19.00 9.00 21.00 11.00 ; END END nq - PIN i2 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - RECT 14.00 9.00 16.00 11.00 ; - END - END i2 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END i1 PIN i0 DIRECTION INPUT ; PORT @@ -2437,6 +2419,30 @@ MACRO na3_x1 RECT 4.00 9.00 6.00 11.00 ; END END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i2 PIN vdd DIRECTION INOUT ; USE power ; @@ -2482,28 +2488,6 @@ MACRO na3_x4 RECT 24.00 9.00 26.00 11.00 ; END END nq - PIN i0 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END i1 PIN i2 DIRECTION INPUT ; PORT @@ -2515,6 +2499,28 @@ MACRO na3_x4 RECT 9.00 14.00 11.00 16.00 ; END END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i0 PIN vdd DIRECTION INOUT ; USE power ; @@ -2561,42 +2567,6 @@ MACRO na4_x1 RECT 24.00 9.00 26.00 11.00 ; END END nq - PIN i3 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - RECT 19.00 9.00 21.00 11.00 ; - END - END i3 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - RECT 14.00 9.00 16.00 11.00 ; - END - END i2 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END i1 PIN i0 DIRECTION INPUT ; PORT @@ -2609,6 +2579,42 @@ MACRO na4_x1 RECT 4.00 9.00 6.00 11.00 ; END END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i3 PIN vdd DIRECTION INOUT ; USE power ; @@ -3080,38 +3086,17 @@ MACRO nmx2_x1 PIN nq DIRECTION OUTPUT ; PORT - LAYER L_ALU1 ; - RECT 24.00 14.00 26.00 16.00 ; - LAYER L_ALU1 ; - RECT 19.00 9.00 21.00 11.00 ; LAYER L_ALU1 ; RECT 19.00 34.00 21.00 36.00 ; RECT 19.00 29.00 21.00 31.00 ; RECT 19.00 24.00 21.00 26.00 ; RECT 19.00 19.00 21.00 21.00 ; + LAYER L_ALU1 ; + RECT 19.00 9.00 21.00 11.00 ; + LAYER L_ALU1 ; + RECT 24.00 14.00 26.00 16.00 ; END END nq - PIN cmd - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - END - END cmd - PIN i0 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i0 PIN i1 DIRECTION INPUT ; PORT @@ -3125,6 +3110,27 @@ MACRO nmx2_x1 RECT 29.00 9.00 31.00 11.00 ; END END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i0 + PIN cmd + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END cmd PIN vdd DIRECTION INOUT ; USE power ; @@ -3343,17 +3349,29 @@ MACRO nmx3_x4 RECT 59.00 14.00 61.00 16.00 ; END END nq - PIN i0 + PIN cmd0 DIRECTION INPUT ; PORT LAYER L_ALU1 ; - RECT 44.00 24.00 46.00 26.00 ; - LAYER L_ALU1 ; - RECT 39.00 29.00 41.00 31.00 ; - LAYER L_ALU1 ; - RECT 39.00 19.00 41.00 21.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; END - END i0 + END cmd0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 24.00 26.00 26.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 24.00 16.00 26.00 ; + END + END i2 PIN cmd1 DIRECTION INPUT ; PORT @@ -3365,29 +3383,17 @@ MACRO nmx3_x4 RECT 4.00 14.00 6.00 16.00 ; END END cmd1 - PIN i2 + PIN i0 DIRECTION INPUT ; PORT LAYER L_ALU1 ; - RECT 14.00 24.00 16.00 26.00 ; - END - END i2 - PIN i1 - DIRECTION INPUT ; - PORT + RECT 39.00 19.00 41.00 21.00 ; LAYER L_ALU1 ; - RECT 24.00 24.00 26.00 26.00 ; - END - END i1 - PIN cmd0 - DIRECTION INPUT ; - PORT + RECT 39.00 29.00 41.00 31.00 ; LAYER L_ALU1 ; - RECT 34.00 29.00 36.00 31.00 ; - RECT 34.00 24.00 36.00 26.00 ; - RECT 34.00 19.00 36.00 21.00 ; + RECT 44.00 24.00 46.00 26.00 ; END - END cmd0 + END i0 PIN vdd DIRECTION INOUT ; USE power ; @@ -3434,18 +3440,6 @@ MACRO no2_x1 RECT 4.00 9.00 6.00 11.00 ; END END nq - PIN i1 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i1 PIN i0 DIRECTION INPUT ; PORT @@ -3459,6 +3453,18 @@ MACRO no2_x1 RECT 14.00 9.00 16.00 11.00 ; END END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 PIN vdd DIRECTION INOUT ; USE power ; @@ -3504,17 +3510,6 @@ MACRO no2_x4 RECT 19.00 9.00 21.00 11.00 ; END END nq - PIN i1 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - END - END i1 PIN i0 DIRECTION INPUT ; PORT @@ -3526,6 +3521,17 @@ MACRO no2_x4 RECT 9.00 14.00 11.00 16.00 ; END END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i1 PIN vdd DIRECTION INOUT ; USE power ; @@ -3572,30 +3578,6 @@ MACRO no3_x1 RECT 4.00 9.00 6.00 11.00 ; END END nq - PIN i1 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 14.00 39.00 16.00 41.00 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END i0 PIN i2 DIRECTION INPUT ; PORT @@ -3609,6 +3591,30 @@ MACRO no3_x1 RECT 19.00 9.00 21.00 11.00 ; END END i2 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 PIN vdd DIRECTION INOUT ; USE power ; @@ -3654,28 +3660,6 @@ MACRO no3_x4 RECT 24.00 9.00 26.00 11.00 ; END END nq - PIN i0 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i1 PIN i2 DIRECTION INPUT ; PORT @@ -3687,6 +3671,28 @@ MACRO no3_x4 RECT 4.00 14.00 6.00 16.00 ; END END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i0 PIN vdd DIRECTION INOUT ; USE power ; @@ -3733,42 +3739,6 @@ MACRO no4_x1 RECT 4.00 9.00 6.00 11.00 ; END END nq - PIN i2 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 19.00 39.00 21.00 41.00 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - END - END i2 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 14.00 39.00 16.00 41.00 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i1 PIN i3 DIRECTION INPUT ; PORT @@ -3781,6 +3751,42 @@ MACRO no4_x1 RECT 24.00 14.00 26.00 16.00 ; END END i3 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i0 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i2 PIN vdd DIRECTION INOUT ; USE power ; @@ -3826,42 +3832,6 @@ MACRO no4_x4 RECT 34.00 14.00 36.00 16.00 ; END END nq - PIN i2 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 19.00 39.00 21.00 41.00 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - END - END i2 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 14.00 39.00 16.00 41.00 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i1 PIN i3 DIRECTION INPUT ; PORT @@ -3874,6 +3844,42 @@ MACRO no4_x4 RECT 24.00 14.00 26.00 16.00 ; END END i3 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i0 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i2 PIN vdd DIRECTION INOUT ; USE power ; @@ -4000,6 +4006,28 @@ MACRO noa22_x4 RECT 39.00 9.00 41.00 11.00 ; END END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i1 PIN i2 DIRECTION INPUT ; PORT @@ -4013,28 +4041,6 @@ MACRO noa22_x4 RECT 4.00 9.00 6.00 11.00 ; END END i2 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - RECT 14.00 9.00 16.00 11.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - RECT 19.00 9.00 21.00 11.00 ; - END - END i0 PIN vdd DIRECTION INOUT ; USE power ; @@ -4172,39 +4178,6 @@ MACRO noa2a22_x4 RECT 44.00 9.00 46.00 11.00 ; END END nq - PIN i2 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - RECT 24.00 9.00 26.00 11.00 ; - END - END i2 - PIN i3 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - RECT 19.00 9.00 21.00 11.00 ; - END - END i3 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END i1 PIN i0 DIRECTION INPUT ; PORT @@ -4216,6 +4189,39 @@ MACRO noa2a22_x4 RECT 4.00 9.00 6.00 11.00 ; END END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END i2 PIN vdd DIRECTION INOUT ; USE power ; @@ -4367,36 +4373,26 @@ MACRO noa2a2a23_x4 RECT 49.00 14.00 51.00 16.00 ; END END nq - PIN i5 + PIN i1 DIRECTION INPUT ; PORT LAYER L_ALU1 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; END - END i5 - PIN i3 + END i1 + PIN i0 DIRECTION INPUT ; PORT LAYER L_ALU1 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; END - END i3 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - END - END i2 + END i0 PIN i4 DIRECTION INPUT ; PORT @@ -4408,26 +4404,36 @@ MACRO noa2a2a23_x4 RECT 14.00 14.00 16.00 16.00 ; END END i4 - PIN i0 + PIN i2 DIRECTION INPUT ; PORT LAYER L_ALU1 ; - RECT 39.00 29.00 41.00 31.00 ; - RECT 39.00 24.00 41.00 26.00 ; - RECT 39.00 19.00 41.00 21.00 ; - RECT 39.00 14.00 41.00 16.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; END - END i0 - PIN i1 + END i2 + PIN i3 DIRECTION INPUT ; PORT LAYER L_ALU1 ; - RECT 34.00 29.00 36.00 31.00 ; - RECT 34.00 24.00 36.00 26.00 ; - RECT 34.00 19.00 36.00 21.00 ; - RECT 34.00 14.00 36.00 16.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; END - END i1 + END i3 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i5 PIN vdd DIRECTION INOUT ; USE power ; @@ -4601,27 +4607,56 @@ MACRO noa2a2a2a24_x4 RECT 69.00 14.00 71.00 16.00 ; END END nq - PIN i0 + PIN i2 DIRECTION INPUT ; PORT LAYER L_ALU1 ; - RECT 64.00 34.00 66.00 36.00 ; - RECT 64.00 29.00 66.00 31.00 ; - RECT 64.00 24.00 66.00 26.00 ; - RECT 64.00 19.00 66.00 21.00 ; - RECT 64.00 14.00 66.00 16.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; END - END i0 - PIN i1 + END i2 + PIN i3 DIRECTION INPUT ; PORT LAYER L_ALU1 ; - RECT 54.00 29.00 56.00 31.00 ; - RECT 54.00 24.00 56.00 26.00 ; - RECT 54.00 19.00 56.00 21.00 ; - RECT 54.00 14.00 56.00 16.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; END - END i1 + END i3 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END i4 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i5 + PIN i6 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i6 PIN i7 DIRECTION INPUT ; PORT @@ -4633,56 +4668,27 @@ MACRO noa2a2a2a24_x4 RECT 4.00 9.00 6.00 11.00 ; END END i7 - PIN i6 + PIN i1 DIRECTION INPUT ; PORT LAYER L_ALU1 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; END - END i6 - PIN i5 + END i1 + PIN i0 DIRECTION INPUT ; PORT LAYER L_ALU1 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; + RECT 64.00 34.00 66.00 36.00 ; + RECT 64.00 29.00 66.00 31.00 ; + RECT 64.00 24.00 66.00 26.00 ; + RECT 64.00 19.00 66.00 21.00 ; + RECT 64.00 14.00 66.00 16.00 ; END - END i5 - PIN i4 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - RECT 29.00 14.00 31.00 16.00 ; - END - END i4 - PIN i3 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 34.00 29.00 36.00 31.00 ; - RECT 34.00 24.00 36.00 26.00 ; - RECT 34.00 19.00 36.00 21.00 ; - RECT 34.00 14.00 36.00 16.00 ; - END - END i3 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 39.00 29.00 41.00 31.00 ; - RECT 39.00 24.00 41.00 26.00 ; - RECT 39.00 19.00 41.00 21.00 ; - RECT 39.00 14.00 41.00 16.00 ; - END - END i2 + END i0 PIN vdd DIRECTION INOUT ; USE power ; @@ -4919,82 +4925,17 @@ MACRO noa3ao322_x1 PIN nq DIRECTION OUTPUT ; PORT + LAYER L_ALU1 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; LAYER L_ALU1 ; RECT 24.00 34.00 26.00 36.00 ; RECT 24.00 29.00 26.00 31.00 ; RECT 24.00 24.00 26.00 26.00 ; RECT 24.00 19.00 26.00 21.00 ; RECT 24.00 14.00 26.00 16.00 ; - LAYER L_ALU1 ; - RECT 19.00 14.00 21.00 16.00 ; - RECT 19.00 9.00 21.00 11.00 ; END END nq - PIN i0 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END i0 - PIN i5 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 39.00 34.00 41.00 36.00 ; - RECT 39.00 29.00 41.00 31.00 ; - RECT 39.00 24.00 41.00 26.00 ; - RECT 39.00 19.00 41.00 21.00 ; - RECT 39.00 14.00 41.00 16.00 ; - END - END i5 - PIN i4 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 34.00 34.00 36.00 36.00 ; - RECT 34.00 29.00 36.00 31.00 ; - RECT 34.00 24.00 36.00 26.00 ; - RECT 34.00 19.00 36.00 21.00 ; - RECT 34.00 14.00 36.00 16.00 ; - END - END i4 - PIN i3 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - RECT 29.00 14.00 31.00 16.00 ; - END - END i3 - PIN i6 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - END - END i6 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END i2 PIN i1 DIRECTION INPUT ; PORT @@ -5007,6 +4948,71 @@ MACRO noa3ao322_x1 RECT 9.00 9.00 11.00 11.00 ; END END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i2 + PIN i6 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + END + END i6 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END i3 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END i4 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i5 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 PIN vdd DIRECTION INOUT ; USE power ; @@ -5174,19 +5180,6 @@ MACRO nts_x1 RECT 14.00 9.00 16.00 11.00 ; END END nq - PIN i - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 4.00 39.00 6.00 41.00 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END i PIN cmd DIRECTION INPUT ; PORT @@ -5200,6 +5193,19 @@ MACRO nts_x1 RECT 9.00 9.00 11.00 11.00 ; END END cmd + PIN i + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i PIN vdd DIRECTION INOUT ; USE power ; @@ -5388,18 +5394,6 @@ MACRO nxr2_x4 RECT 49.00 9.00 51.00 11.00 ; END END nq - PIN i1 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 34.00 39.00 36.00 41.00 ; - RECT 34.00 34.00 36.00 36.00 ; - RECT 34.00 29.00 36.00 31.00 ; - RECT 34.00 24.00 36.00 26.00 ; - RECT 34.00 19.00 36.00 21.00 ; - RECT 34.00 14.00 36.00 16.00 ; - END - END i1 PIN i0 DIRECTION INPUT ; PORT @@ -5413,6 +5407,18 @@ MACRO nxr2_x4 RECT 9.00 9.00 11.00 11.00 ; END END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END i1 PIN vdd DIRECTION INOUT ; USE power ; @@ -5459,6 +5465,17 @@ MACRO o2_x2 RECT 19.00 9.00 21.00 11.00 ; END END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i1 PIN i0 DIRECTION INPUT ; PORT @@ -5472,17 +5489,6 @@ MACRO o2_x2 RECT 14.00 9.00 16.00 11.00 ; END END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - END - END i1 PIN vdd DIRECTION INOUT ; USE power ; @@ -5529,6 +5535,17 @@ MACRO o2_x4 RECT 19.00 9.00 21.00 11.00 ; END END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i1 PIN i0 DIRECTION INPUT ; PORT @@ -5542,17 +5559,6 @@ MACRO o2_x4 RECT 14.00 9.00 16.00 11.00 ; END END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - END - END i1 PIN vdd DIRECTION INOUT ; USE power ; @@ -5599,28 +5605,6 @@ MACRO o3_x2 RECT 24.00 9.00 26.00 11.00 ; END END q - PIN i0 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i1 PIN i2 DIRECTION INPUT ; PORT @@ -5632,6 +5616,28 @@ MACRO o3_x2 RECT 4.00 14.00 6.00 16.00 ; END END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i0 PIN vdd DIRECTION INOUT ; USE power ; @@ -5757,39 +5763,6 @@ MACRO o4_x2 RECT 29.00 9.00 31.00 11.00 ; END END q - PIN i3 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - END - END i3 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - END - END i2 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END i0 PIN i1 DIRECTION INPUT ; PORT @@ -5801,6 +5774,39 @@ MACRO o4_x2 RECT 9.00 14.00 11.00 16.00 ; END END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i0 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i3 PIN vdd DIRECTION INOUT ; USE power ; @@ -5942,6 +5948,28 @@ MACRO oa22_x2 RECT 24.00 9.00 26.00 11.00 ; END END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 PIN i2 DIRECTION INPUT ; PORT @@ -5955,28 +5983,6 @@ MACRO oa22_x2 RECT 19.00 9.00 21.00 11.00 ; END END i2 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END i0 PIN vdd DIRECTION INOUT ; USE power ; @@ -6023,28 +6029,6 @@ MACRO oa22_x4 RECT 29.00 9.00 31.00 11.00 ; END END q - PIN i0 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END i1 PIN i2 DIRECTION INPUT ; PORT @@ -6058,6 +6042,28 @@ MACRO oa22_x4 RECT 19.00 9.00 21.00 11.00 ; END END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 PIN vdd DIRECTION INOUT ; USE power ; @@ -6104,39 +6110,6 @@ MACRO oa2a22_x2 RECT 39.00 9.00 41.00 11.00 ; END END q - PIN i0 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END i1 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - RECT 19.00 9.00 21.00 11.00 ; - END - END i2 PIN i3 DIRECTION INPUT ; PORT @@ -6148,6 +6121,39 @@ MACRO oa2a22_x2 RECT 24.00 9.00 26.00 11.00 ; END END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 PIN vdd DIRECTION INOUT ; USE power ; @@ -6194,39 +6200,6 @@ MACRO oa2a22_x4 RECT 39.00 9.00 41.00 11.00 ; END END q - PIN i0 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END i1 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - RECT 19.00 9.00 21.00 11.00 ; - END - END i2 PIN i3 DIRECTION INPUT ; PORT @@ -6238,6 +6211,39 @@ MACRO oa2a22_x4 RECT 24.00 9.00 26.00 11.00 ; END END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 PIN vdd DIRECTION INOUT ; USE power ; @@ -6498,27 +6504,56 @@ MACRO oa2a2a2a24_x2 RECT 69.00 9.00 71.00 11.00 ; END END q - PIN i1 + PIN i2 DIRECTION INPUT ; PORT LAYER L_ALU1 ; - RECT 54.00 29.00 56.00 31.00 ; - RECT 54.00 24.00 56.00 26.00 ; - RECT 54.00 19.00 56.00 21.00 ; - RECT 54.00 14.00 56.00 16.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; END - END i1 - PIN i0 + END i2 + PIN i3 DIRECTION INPUT ; PORT LAYER L_ALU1 ; - RECT 64.00 34.00 66.00 36.00 ; - RECT 64.00 29.00 66.00 31.00 ; - RECT 64.00 24.00 66.00 26.00 ; - RECT 64.00 19.00 66.00 21.00 ; - RECT 64.00 14.00 66.00 16.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; END - END i0 + END i3 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END i4 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i5 + PIN i6 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i6 PIN i7 DIRECTION INPUT ; PORT @@ -6530,56 +6565,27 @@ MACRO oa2a2a2a24_x2 RECT 4.00 9.00 6.00 11.00 ; END END i7 - PIN i6 + PIN i0 DIRECTION INPUT ; PORT LAYER L_ALU1 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; + RECT 64.00 34.00 66.00 36.00 ; + RECT 64.00 29.00 66.00 31.00 ; + RECT 64.00 24.00 66.00 26.00 ; + RECT 64.00 19.00 66.00 21.00 ; + RECT 64.00 14.00 66.00 16.00 ; END - END i6 - PIN i5 + END i0 + PIN i1 DIRECTION INPUT ; PORT LAYER L_ALU1 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; END - END i5 - PIN i4 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - RECT 29.00 14.00 31.00 16.00 ; - END - END i4 - PIN i3 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 34.00 29.00 36.00 31.00 ; - RECT 34.00 24.00 36.00 26.00 ; - RECT 34.00 19.00 36.00 21.00 ; - RECT 34.00 14.00 36.00 16.00 ; - END - END i3 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 39.00 29.00 41.00 31.00 ; - RECT 39.00 24.00 41.00 26.00 ; - RECT 39.00 19.00 41.00 21.00 ; - RECT 39.00 14.00 41.00 16.00 ; - END - END i2 + END i1 PIN vdd DIRECTION INOUT ; USE power ; @@ -6853,6 +6859,47 @@ MACRO oa2ao222_x4 RECT 44.00 9.00 46.00 11.00 ; END END q + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i2 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END i4 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 PIN i0 DIRECTION INPUT ; PORT @@ -6865,47 +6912,6 @@ MACRO oa2ao222_x4 RECT 4.00 9.00 6.00 11.00 ; END END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i1 - PIN i4 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - END - END i4 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - END - END i2 - PIN i3 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - RECT 29.00 14.00 31.00 16.00 ; - END - END i3 PIN vdd DIRECTION INOUT ; USE power ; @@ -7194,6 +7200,18 @@ MACRO on12_x1 RECT 14.00 9.00 16.00 11.00 ; END END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i0 PIN i1 DIRECTION INPUT ; PORT @@ -7207,18 +7225,6 @@ MACRO on12_x1 RECT 9.00 9.00 11.00 11.00 ; END END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 19.00 39.00 21.00 41.00 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - END - END i0 PIN vdd DIRECTION INOUT ; USE power ; @@ -7265,19 +7271,6 @@ MACRO on12_x4 RECT 29.00 9.00 31.00 11.00 ; END END q - PIN i1 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 24.00 39.00 26.00 41.00 ; - RECT 24.00 34.00 26.00 36.00 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - RECT 24.00 9.00 26.00 11.00 ; - END - END i1 PIN i0 DIRECTION INPUT ; PORT @@ -7291,6 +7284,19 @@ MACRO on12_x4 RECT 9.00 9.00 11.00 11.00 ; END END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END i1 PIN vdd DIRECTION INOUT ; USE power ; @@ -7399,9 +7405,6 @@ MACRO powmid_x0 OBS LAYER L_ALU1 ; RECT 1.50 9.00 33.50 41.00 ; - LAYER L_ALU2 ; - RECT 4.00 49.00 16.00 51.00 ; - RECT 19.00 -1.00 31.00 1.00 ; END END powmid_x0 @@ -7458,6 +7461,21 @@ MACRO sff1_x4 RECT 79.00 9.00 81.00 11.00 ; END END q + PIN i + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + LAYER L_ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + LAYER L_ALU1 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END i PIN ck DIRECTION INPUT ; PORT @@ -7471,21 +7489,6 @@ MACRO sff1_x4 RECT 9.00 9.00 11.00 11.00 ; END END ck - PIN i - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 29.00 9.00 31.00 11.00 ; - LAYER L_ALU1 ; - RECT 29.00 39.00 31.00 41.00 ; - LAYER L_ALU1 ; - RECT 24.00 34.00 26.00 36.00 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - END - END i PIN vdd DIRECTION INOUT ; USE power ; @@ -7532,30 +7535,16 @@ MACRO sff2_x4 RECT 109.00 9.00 111.00 11.00 ; END END q - PIN ck + PIN cmd DIRECTION INPUT ; PORT LAYER L_ALU1 ; - RECT 44.00 34.00 46.00 36.00 ; - RECT 44.00 29.00 46.00 31.00 ; - RECT 44.00 24.00 46.00 26.00 ; - RECT 44.00 19.00 46.00 21.00 ; - RECT 44.00 14.00 46.00 16.00 ; - RECT 44.00 9.00 46.00 11.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; END - END ck - PIN i0 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i0 + END cmd PIN i1 DIRECTION INPUT ; PORT @@ -7568,16 +7557,30 @@ MACRO sff2_x4 RECT 29.00 9.00 31.00 11.00 ; END END i1 - PIN cmd + PIN i0 DIRECTION INPUT ; PORT LAYER L_ALU1 ; - RECT 14.00 39.00 16.00 41.00 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; END - END cmd + END i0 + PIN ck + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 44.00 9.00 46.00 11.00 ; + END + END ck PIN vdd DIRECTION INOUT ; USE power ; @@ -7624,51 +7627,6 @@ MACRO sff3_x4 RECT 129.00 9.00 131.00 11.00 ; END END q - PIN i0 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 44.00 24.00 46.00 26.00 ; - LAYER L_ALU1 ; - RECT 39.00 29.00 41.00 31.00 ; - LAYER L_ALU1 ; - RECT 39.00 19.00 41.00 21.00 ; - END - END i0 - PIN cmd0 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 34.00 29.00 36.00 31.00 ; - RECT 34.00 24.00 36.00 26.00 ; - RECT 34.00 19.00 36.00 21.00 ; - END - END cmd0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 24.00 24.00 26.00 26.00 ; - END - END i1 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 14.00 24.00 16.00 26.00 ; - END - END i2 - PIN cmd1 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - END - END cmd1 PIN ck DIRECTION INPUT ; PORT @@ -7681,6 +7639,51 @@ MACRO sff3_x4 RECT 59.00 9.00 61.00 11.00 ; END END ck + PIN cmd1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END cmd1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 24.00 16.00 26.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 24.00 26.00 26.00 ; + END + END i1 + PIN cmd0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END cmd0 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 19.00 41.00 21.00 ; + LAYER L_ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + LAYER L_ALU1 ; + RECT 44.00 24.00 46.00 26.00 ; + END + END i0 PIN vdd DIRECTION INOUT ; USE power ; @@ -7760,17 +7763,6 @@ MACRO ts_x4 RECT 9.00 9.00 11.00 11.00 ; END END q - PIN i - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 39.00 34.00 41.00 36.00 ; - RECT 39.00 29.00 41.00 31.00 ; - RECT 39.00 24.00 41.00 26.00 ; - RECT 39.00 19.00 41.00 21.00 ; - RECT 39.00 14.00 41.00 16.00 ; - END - END i PIN cmd DIRECTION INPUT ; PORT @@ -7784,6 +7776,17 @@ MACRO ts_x4 RECT 14.00 9.00 16.00 11.00 ; END END cmd + PIN i + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i PIN vdd DIRECTION INOUT ; USE power ; @@ -7830,17 +7833,6 @@ MACRO ts_x8 RECT 24.00 9.00 26.00 11.00 ; END END q - PIN i - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 54.00 34.00 56.00 36.00 ; - RECT 54.00 29.00 56.00 31.00 ; - RECT 54.00 24.00 56.00 26.00 ; - RECT 54.00 19.00 56.00 21.00 ; - RECT 54.00 14.00 56.00 16.00 ; - END - END i PIN cmd DIRECTION INPUT ; PORT @@ -7854,6 +7846,17 @@ MACRO ts_x8 RECT 29.00 9.00 31.00 11.00 ; END END cmd + PIN i + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 54.00 34.00 56.00 36.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + END + END i PIN vdd DIRECTION INOUT ; USE power ;