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.\" $Id: vasy.1,v 1.1 1999/11/26 13:55:57 syf Exp $
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.\" $Id: vasy.1,v 1.2 1999/12/15 18:40:02 syf Exp $
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.\" @(#)Labo.l 2.2 95/09/24 UPMC; Author: Jacomme L.
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.pl -.4
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.TH VASY 1 "November 26, 1999" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
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@ -8,7 +8,7 @@ VASY \- VHDL Analyzer for Synthesis
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.so man1/alc_origin.1
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.SH SYNOPSIS
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.TP
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\f4vasy [-I input_format] \-V|v|a|s input_name [output_name]
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\f4vasy \-V|v|a|s|S [-I input_format] input_name [output_name]
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.br
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.SH DESCRIPTION
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.br
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.SH OPTIONS
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.TP 10
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\f4\-I\fP
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Specifies the VHDL input format such as Alliance VHDL format \fBvbe\fP(5) or
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industrial VHDL format \fBvhd\fP.
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\f4\-V\fP
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Verbose mode on.
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Each step of the analysis is displayed on the standard output.
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.TP 10
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\f4\-v\fP
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Drives an equivalent description in \fBVerilog\fP format.
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@ -43,12 +43,15 @@ Drives an equivalent description in \fBVerilog\fP format.
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Drives an equivalent description in Alliance VHDL format \fBvbe\fP(5)
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.TP 10
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\f4\-s\fP
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Drives an equivalent VHDL description (with the extention \fB.syn\fP)
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Drives an equivalent VHDL description (with the extention \fB.vhd\fP)
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accepted by most of industrial synthesis tools.
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.TP 10
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\f4\-V\fP
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Verbose mode on.
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Each step of the analysis is displayed on the standard output.
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\f4\-S\fP
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Uses Std_logic instead of Bit (taken into account only with option -s).
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.TP 10
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\f4\-I\fP
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Specifies the VHDL input format such as Alliance VHDL format \fBvbe\fP(5) or
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industrial VHDL format \fBvhd\fP.
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.ti 7
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.SH SEE ALSO
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