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importing ALLIANCE documentation ....

This commit is contained in:
Christophe Alexandre 2002-10-21 17:01:28 +00:00
parent 94ed9f1a45
commit e7d6a5dd67
11 changed files with 2465 additions and 0 deletions
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233
alliance/src/documentation/alliance-run/Makefile Normal file
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ALLIANCE_TOP = /asim/alliance
TECHNO_REAL = prol10
#
# /------------------------------------------------------------------\
# | Macros definitions |
# \------------------------------------------------------------------/
#
# Standart System binary access paths.
STANDART_BIN = /usr/local/bin:/labo/gnu/bin:/usr/bin:/bin
STANDART_PATH = PATH=$(STANDART_BIN); export PATH
# Standart Alliance binary access paths.
ALLIANCE_BIN = $(ALLIANCE_TOP)/bin
# --------------------------------------------------------------------
# Standarts binaries.
LS = PATH=$(STANDART_BIN); ls
CD = PATH=$(STANDART_BIN); cd
CP = PATH=$(STANDART_BIN); cp
LN = PATH=$(STANDART_BIN); ln
MV = PATH=$(STANDART_BIN); mv
RM = PATH=$(STANDART_BIN); rm
SED = PATH=$(STANDART_BIN); sed
CAT = PATH=$(STANDART_BIN); cat
TOUCH = PATH=$(STANDART_BIN); touch
GREP = PATH=$(STANDART_BIN); grep
ECHO = PATH=$(STANDART_BIN); echo
# Alliance paths and formats settings.
GENERAT_LO = vst
EXTRACT_LO = al
GENERAT_PH = ap
EXTRACT_PH = ap
GENERAT_SP = .
EXTRACT_SP = .
CATA_LIB0 = $(ALLIANCE_TOP)/cells/sxlib
CATA_LIB1 = $(ALLIANCE_TOP)/cells/dp_sxlib
CATA_LIB2 = $(ALLIANCE_TOP)/cells/padlib
CATA_LIB = .:$(CATA_LIB0):$(CATA_LIB1):$(CATA_LIB2)
TARGET_LIB = $(MBK_TARGET_LIB)
RDS_TECHNO = $(ALLIANCE_TOP)/etc/cmos.rds
GRAAL_TECHNO = $(ALLIANCE_TOP)/etc/cmos.graal
MBK_GENERAT_ENV = MBK_TARGET_LIB=$(TARGET_LIB); export MBK_TARGET_LIB; \
MBK_WORK_LIB=.; export MBK_WORK_LIB; \
MBK_CATA_LIB=$(CATA_LIB); export MBK_CATA_LIB; \
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME; \
MBK_OUT_LO=$(GENERAT_LO); export MBK_OUT_LO; \
MBK_OUT_PH=$(GENERAT_PH); export MBK_OUT_PH; \
MBK_IN_LO=$(GENERAT_LO); export MBK_IN_LO; \
MBK_IN_PH=$(GENERAT_PH); export MBK_IN_PH; \
MBK_SEPAR=$(GENERAT_SP); export MBK_SEPAR; \
MBK_VDD=vdd; export MBK_VDD; \
MBK_VSS=vss; export MBK_VSS; \
RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME; \
GRAAL_TECHNO_NAME=$(GRAAL_TECHNO); export GRAAL_TECHNO_NAME
# MBK extracting environment.
MBK_EXTRACT_ENV = MBK_TARGET_LIB=$(TARGET_LIB); export MBK_TARGET_LIB; \
MBK_WORK_LIB=.; export MBK_WORK_LIB; \
MBK_CATA_LIB=$(CATA_LIB); export MBK_CATA_LIB; \
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME; \
MBK_OUT_LO=$(EXTRACT_LO); export MBK_OUT_LO; \
MBK_OUT_PH=$(EXTRACT_PH); export MBK_OUT_PH; \
MBK_IN_LO=$(EXTRACT_LO); export MBK_IN_LO; \
MBK_IN_PH=$(EXTRACT_PH); export MBK_IN_PH; \
MBK_SEPAR=$(EXTRACT_SP); export MBK_SEPAR; \
MBK_VDD=vdd; export MBK_VDD; \
MBK_VSS=vss; export MBK_VSS; \
RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME;\
GRAAL_TECHNO_NAME=$(GRAAL_TECHNO); export GRAAL_TECHNO_NAME
# --------------------------------------------------------------------
# Alliance binaries & environment.
BOOM = $(ALLIANCE_BIN)/boom -V
BOOG = $(ALLIANCE_BIN)/boog
LOON = $(ALLIANCE_BIN)/loon
ASIMUT1 = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/asimut
ASIMUT2 = $(MBK_EXTRACT_ENV); $(ALLIANCE_BIN)/asimut
COUGAR = $(ALLIANCE_BIN)/cougar
DRUC = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/druc
LVX = $(MBK_EXTRACT_ENV); $(ALLIANCE_BIN)/lvx
PROOF = $(MBK_EXTRACT_ENV); $(ALLIANCE_BIN)/proof
GENLIB = $(MBK_GENERAT_ENV);$(ALLIANCE_BIN)/genlib
GENPAT = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/genpat
OCP = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/ocp
NERO = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/nero
RING = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/ring
GRAAL = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/graal
XSCH = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/xsch
XPAT = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/xpat
#
# /------------------------------------------------------------------\
# | Rules |
# \------------------------------------------------------------------/
#
all: nb_transistors
ctl_part: amd2901_ctl.vst
view_ctl_logic: amd2901_ctl.vst
$(XSCH) -l amd2901_ctl
dpt_part: amd2901_dpt.ap amd2901_dpt.vst
view_dpt_physic: amd2901_dpt.ap
$(GRAAL) -l amd2901_dpt
chip_part: amd2901_chip.ap
view_chip_physic: amd2901_chip.ap
$(GRAAL) -l amd2901_chip
chip_verification: druc_chip lvx_chip test_chip_final.pat
view_chip_simulation: test_chip_final.pat
$(XPAT) -l test_chip_final
amd2901_core.vst amd2901_core_place.ap: amd2901_core.c amd2901_ctl.vst amd2901_ctl.vbe amd2901_dpt.vst amd2901_dpt.ap
$(GENLIB) -v amd2901_core
amd2901_chip.vst: amd2901_core.vst
$(GENLIB) -v amd2901_chip
test_chip.pat: amd2901_chip.vst pattern.pat
$(ASIMUT1) -zd amd2901_chip pattern test_chip
pattern.pat: pattern.c
$(GENPAT) -v pattern
amd2901_dpt.ap amd2901_dpt.vst: amd2901_dpt.c
$(GENLIB) -v amd2901_dpt
amd2901_ctl_boom.vbe : amd2901_ctl.vbe
$(BOOM) amd2901_ctl amd2901_ctl_boom
amd2901_ctl_boog.vst : amd2901_ctl_boom.vbe amd2901_ctl.lax
$(BOOG) amd2901_ctl_boom amd2901_ctl_boog amd2901_ctl
amd2901_ctl.vst : amd2901_ctl_boog.vst
$(LOON) amd2901_ctl_boog amd2901_ctl
amd2901_core_p.ap: amd2901_core.vst amd2901_core_place.ap amd2901_core.ioc
$(OCP) -v -gnuplot -partial amd2901_core_place -ioc amd2901_core amd2901_core amd2901_core_p
#$(OCP) -v -gnuplot -partial amd2901_core_place -ring amd2901_core amd2901_core_p
druc_ocp: amd2901_core_p.ap
$(DRUC) amd2901_core_p
$(TOUCH) druc_ocp
amd2901_core.ap: druc_ocp
$(NERO) -v -2 -p amd2901_core_p amd2901_core amd2901_core
amd2901_core.al: amd2901_core.ap
$(MBK_EXTRACT_ENV); $(COUGAR) -v -f amd2901_core amd2901_core
lvx_core: amd2901_core.al amd2901_core.vst
$(LVX) al vst amd2901_core amd2901_core -f
$(TOUCH) lvx_core
druc_core: amd2901_core.ap
$(DRUC) amd2901_core
$(TOUCH) druc_core
amd2901_chip.ap: test_chip.pat amd2901_core.ap amd2901_chip.rin druc_core lvx_core
$(MBK_GENERAT_ENV); $(RING) amd2901_chip amd2901_chip
amd2901_chip.al: amd2901_chip.ap
$(MBK_EXTRACT_ENV); $(COUGAR) -v -f amd2901_chip amd2901_chip
lvx_chip: amd2901_chip.al amd2901_chip.vst
$(LVX) al vst amd2901_chip amd2901_chip -f
$(TOUCH) lvx_chip
druc_chip: amd2901_chip.ap
$(DRUC) amd2901_chip
$(TOUCH) druc_chip
test_chip_final.pat: pattern.pat druc_chip lvx_chip
$(ASIMUT2) -zd amd2901_chip pattern test_chip_final
nb_transistors: amd2901_chip_tr.al amd2901_core_tr.al
@$(ECHO) "Number of transistors for the core: ";\
$(GREP) -c "^T" amd2901_core_tr.al
@$(ECHO) "Number of transistors for the chip: ";\
$(GREP) -c "^T" amd2901_chip_tr.al
amd2901_chip_tr.al: test_chip_final.pat
$(MBK_EXTRACT_ENV); $(COUGAR) -v -t amd2901_chip amd2901_chip_tr
amd2901_core_tr.al: lvx_core druc_core
$(MBK_EXTRACT_ENV); $(COUGAR) -v -t amd2901_core amd2901_core_tr
graal:
$(GRAAL) -install
clean :
rm -f Makefile-* \
amd2901_core.vst \
amd2901_chip.vst \
amd2901_ctl.vst \
amd2901_dpt.vst \
amd2901_ctl_boog.vst \
amd2901_ctl_boom.vbe \
*.ap \
res.pat \
*.frr \
*.log \
*.drc \
*.gds \
*.def \
*.gpl \
*.xsc \
*.al \
*.pat \
*~ \
*cif \
lvx_core druc_core \
lvx_chip druc_chip \
druc_ocp \
alldata* \
model_*

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# Alliance VLSI CAD System
# Copyright (C) 1990, 2002 ASIM/LIP6/UPMC
#
# Home page : http://asim.lip6.fr/alliance/
# E-mail : mailto:alliance-users@asim.lip6.fr
# ftp site : ftp://asim.lip6.fr/pub/alliance/
#
# What is this bench for ??
# ===================================================================
This bench constructs an amd2901 from the logical view to the
physical view to the logical view (verifying each stage)
whith ALLIANCE tools.
This bench is meant to run most of ALLIANCE_TOOL to test them.
For more documentation about ALLIANCE, please read the tutorials
and the man pages.
If you are interested in ALLIANCE, subscribe to the
alliance-users@asim.lip6.fr mailing list.
# How to run this bench ? :
# ===================================================================
First of all, edit the Makefile and set the ALLIANCE_TOP variable to
the directory where ALLIANCE is installed: /usr/local, /opt
or whatever.
This done, you can run the entire process by typing:
> make clean
> make
# Special targets
# ===================================================================
Run the following targets (make [target]):
view_ctl_logic: generates amd2901_ctl.vst and visualizes it with xsch
view_dpt_physic: generates amd2901_dpt.vst and amd2901_dpt.ap
and visualizes amd2901_dpt.ap with graal.
view_chip_physic: generates amd2901_chip.ap and visualizes it with graal.
view_chip_simulation: generates test_chip_final.pat and visualizes it with xpat.
Edit the Makefile for more targets ....
# What are the files coming with this bench ??
# ===================================================================
pattern.c:
test patterns of the amd2901 described in C and using the
genpat MACROS. Has to be processed with genpat to create
the pattern.pat file.
amd2901_ctl.vbe:
Description of the amd2901 control part in vbe format.
Processed by boom (boolean optimization) ->
which is processed by boog (synthesis) ->
which is proceesed by loon (power optimization) ->
amd2901_ctl.lax:
Parameter file for logic synthesis. Used by boom and boog.
amd2901_dpt.c:
Description of the amd2901 data-path in genlib format.
Uses the data-path library dp_sxlib.
Has to be processed by genlib, to create:
*amd2901_dpt.vst:
logical description of the amd2901 datapath
*amd2901_dpt.ap:
physical description of the amd2901 datapath
amd2901_core.c:
Description of the amd2901 core in genlib format.
Has to be processed by genlib, to create
*amd2901_core.vst:
logical description of amd2901 core which instanciates
amd2901_dpt.vst and amd2901_ctl.vst.
*amd2901_core.ap:
physical description of amd2901 core which instanciates
amd2901_dpt.ap and expand the abutment box in order
to give enough room to place the control part.
amd2901_core.ioc:
amd2901_core connectors placement description, used by ocp.
amd2901_chip.c:
amd2901_chip description in genlib format.
instanciates amd2901_core.vst and the pads from the padlib
library.
amd2901_chip.rin:
pads placement file, used by ring.
bench.zsh:
simple zsh script, used for ad lib use of this bench to detect
bugs ...

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alliance/src/documentation/alliance-run/amd2901_chip.c Normal file
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#include <genlib.h>
#define POWER "vdde","vdd","vsse","vss",0
int main ()
{
int i;
GENLIB_DEF_LOFIG("amd2901_chip");
GENLIB_LOCON("ck", IN ,"ck");
GENLIB_LOCON( "cin", IN, "cin");
GENLIB_LOCON( "cout", OUT, "cout");
GENLIB_LOCON( "np", OUT , "np");
GENLIB_LOCON( "ng", OUT , "ng");
GENLIB_LOCON( "ovr", OUT , "ovr");
GENLIB_LOCON( "zero", OUT , "zero");
GENLIB_LOCON("signe", UNKNOWN,"signe");
GENLIB_LOCON("r0", UNKNOWN, "r0");
GENLIB_LOCON("r3", UNKNOWN, "r3");
GENLIB_LOCON("q0", UNKNOWN, "q0");
GENLIB_LOCON("q3", UNKNOWN, "q3");
GENLIB_LOCON( "fonc", IN , "fonc");
GENLIB_LOCON( "test", IN , "test");
GENLIB_LOCON( "scin", IN , "scin");
GENLIB_LOCON("scout", OUT ,"scout");
GENLIB_LOCON("a[3:0]", IN , "a[3:0]");
GENLIB_LOCON("b[3:0]", IN , "b[3:0]");
GENLIB_LOCON("d[3:0]", IN , "d[3:0]");
GENLIB_LOCON("i[8:0]", IN , "i[8:0]");
GENLIB_LOCON("noe" , IN , "noe" );
GENLIB_LOCON("y[3:0]", UNKNOWN, "y[3:0]");
GENLIB_LOCON("vdd" , IN , "vdd" );
GENLIB_LOCON("vss" , IN , "vss" );
GENLIB_LOCON("vdde", IN , "vdde");
GENLIB_LOCON("vsse", IN , "vsse");
GENLIB_LOINSE ( "amd2901_core", "core",
"cin => cin_i",
"cout => cout_i",
"np => np_i",
"ng => ng_i",
"over => ovr_i",
"zero => zero_i",
"sh_right => sh_right",
"sh_left => sh_left",
"ram_o_down => ram_o_down",
"ram_o_up => ram_o_up",
"ram_i_down => ram_i_down",
"ram_i_up => ram_i_up",
"acc_o_down => acc_o_down",
"acc_o_up => acc_o_up",
"acc_i_down => acc_i_down",
"acc_i_up => acc_i_up",
"fonc => fonc_i",
"test => test_i",
"scin => scin_i",
"ck => ckc",
"a[3:0] => a_i[3:0]",
"b[3:0] => b_i[3:0]",
"d[3:0] => d_i[3:0]",
"i[8:0] => i_i[8:0]",
"y[3:0] => y_i[3:0]",
"noe => noe_i",
"oe => oe",
"vdd => vdd",
"vss => vss",
0);
GENLIB_LOINS("pck_sp","p_ck","ck","cki", POWER);
GENLIB_LOINS("pi_sp","p_fonc","fonc","fonc_i","cki", POWER );
GENLIB_LOINS("pi_sp","p_test","test","test_i","cki", POWER );
GENLIB_LOINS("pi_sp","p_scin","scin","scin_i","cki", POWER );
GENLIB_LOINS("pi_sp","p_cin","cin","cin_i","cki", POWER );
GENLIB_LOINS("pi_sp","p_noe","noe","noe_i","cki", POWER );
for (i=0;i<4;i++)
{
GENLIB_LOINS("pi_sp",GENLIB_NAME("p_a%d",i), GENLIB_ELM("a",i), GENLIB_ELM("a_i",i), "cki", POWER );
GENLIB_LOINS("pi_sp",GENLIB_NAME("p_b%d",i), GENLIB_ELM("b",i), GENLIB_ELM("b_i",i), "cki", POWER );
GENLIB_LOINS("pi_sp",GENLIB_NAME("p_d%d",i), GENLIB_ELM("d",i), GENLIB_ELM("d_i",i), "cki", POWER );
}
for (i=0;i<9;i++)
GENLIB_LOINS("pi_sp",GENLIB_NAME("p_i%d",i), GENLIB_ELM("i",i), GENLIB_ELM("i_i",i), "cki", POWER );
GENLIB_LOINS("po_sp","p_cout","cout_i","cout","cki", POWER );
GENLIB_LOINS("po_sp","p_np","np_i","np","cki", POWER );
GENLIB_LOINS("po_sp","p_ng","ng_i","ng","cki", POWER );
GENLIB_LOINS("po_sp","p_ovr","ovr_i","ovr","cki", POWER );
GENLIB_LOINS("po_sp","p_zero","zero_i","zero","cki", POWER );
GENLIB_LOINS("po_sp","p_signe","ram_o_up","signe","cki", POWER );
GENLIB_LOINS("po_sp","p_scout","acc_o_up","scout","cki", POWER );
for (i=0;i<4;i++)
GENLIB_LOINS ("pot_sp",GENLIB_NAME("p_y%d",i),
GENLIB_ELM("y_i",i), "oe", GENLIB_ELM("y",i), "cki", POWER );
GENLIB_LOINS ("piot_sp","p_q0",
"acc_o_down","sh_right","acc_i_down","q0","cki", POWER );
GENLIB_LOINS ("piot_sp","p_q3",
"acc_o_up","sh_left","acc_i_up","q3","cki", POWER );
GENLIB_LOINS ("piot_sp","p_r0",
"ram_o_down","sh_right","ram_i_down","r0","cki", POWER );
GENLIB_LOINS ("piot_sp","p_r3",
"ram_o_up","sh_left","ram_i_up","r3","cki", POWER );
GENLIB_LOINS("pvddick_sp","p_vddick0","ckc","cki","vdde","vdd","vsse","vss",0);
GENLIB_LOINS("pvssick_sp","p_vssick0","ckc","cki","vdde","vdd","vsse","vss",0);
GENLIB_LOINS("pvddeck_sp","p_vddeck0","ckc","cki","vdde","vdd","vsse","vss",0);
GENLIB_LOINS("pvddeck_sp","p_vddeck1","ckc","cki","vdde","vdd","vsse","vss",0);
GENLIB_LOINS("pvsseck_sp","p_vsseck0","ckc","cki","vdde","vdd","vsse","vss",0);
GENLIB_LOINS("pvsseck_sp","p_vsseck1","ckc","cki","vdde","vdd","vsse","vss",0);
GENLIB_SAVE_LOFIG();
exit (0);
}

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alliance/src/documentation/alliance-run/amd2901_chip.rin Normal file
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east (p_q0 p_q3 p_b0 p_b1 p_b2 p_vddeck0 p_vsseck0 p_zero p_scout p_signe p_y2 p_y3 )
west (p_b3 p_cin p_ck p_cout p_vddick0 p_vssick0 p_vddeck1 p_vsseck1 p_i3 p_i4 p_i5 p_i6 )
north ( p_d0 p_d1 p_d2 p_d3 p_fonc p_i0 p_i1 p_i2 p_a0 p_a1 p_a2 p_a3 )
south ( p_i7 p_i8 p_ng p_noe p_np p_ovr p_r0 p_r3 p_scin p_test p_y0 p_y1 )

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#include <genlib.h>
main()
{
GENLIB_DEF_LOFIG ("amd2901_core");
GENLIB_DEF_PHFIG ("amd2901_core_place");
/* ***************** Terminal Declarations ****************** */
/* Pin terminals associated with ALU. */
GENLIB_LOCON("cin", UNKNOWN, "cin" );
GENLIB_LOCON("cout", UNKNOWN, "cout");
GENLIB_LOCON("np", OUT , "np" );
GENLIB_LOCON("ng", OUT , "ng" );
GENLIB_LOCON("over", OUT , "over");
GENLIB_LOCON("zero", OUT , "zero");
/* Pin terminals associated with the RAM and ACCU shifter. */
/* RAM and ACCU I/O plots controls. */
GENLIB_LOCON( "sh_right", OUT, "sh_right");
GENLIB_LOCON( "sh_left" , OUT, "sh_left" );
/* RAM shifter I/O. */
GENLIB_LOCON("ram_o_down" , OUT, "alu_f[0]" );
GENLIB_LOCON("ram_o_up" , OUT, "alu_f[3]" );
GENLIB_LOCON("ram_i_down" , IN , "ram_i_down" );
GENLIB_LOCON("ram_i_up" , IN , "ram_i_up" );
/* ACC shifter I/O. */
GENLIB_LOCON("acc_o_down" , OUT, "acc_o_down" );
GENLIB_LOCON("acc_o_up" , OUT, "acc_scout" );
GENLIB_LOCON("acc_i_down" , IN , "acc_i_down" );
GENLIB_LOCON("acc_i_up" , IN , "acc_i_up" );
/* ACCU controls terminals. */
GENLIB_LOCON( "fonc", IN , "fonc");
GENLIB_LOCON( "test", IN , "test");
GENLIB_LOCON( "scin", IN , "scin");
GENLIB_LOCON( "ck", IN , "ck");
/* Data bus terminals. */
GENLIB_LOCON( "a[3:0]", IN , "a[3:0]");
GENLIB_LOCON( "b[3:0]", IN , "b[3:0]");
GENLIB_LOCON( "d[3:0]", IN , "d[3:0]");
GENLIB_LOCON( "i[8:0]", IN , "i[8:0]");
GENLIB_LOCON( "y[3:0]", OUT , "y[3:0]");
GENLIB_LOCON( "noe", IN, "noe");
GENLIB_LOCON( "oe", OUT, "oe");
/* Power suplies terminals. */
GENLIB_LOCON("vdd", IN ,"vdd");
GENLIB_LOCON("vss", IN ,"vss");
/* **************** Data-Path Instanciation ***************** */
GENLIB_LOINSE("amd2901_dpt", "amd2901_dpt",
/* ck */
"ram_ck[0] => ck",
"ram_ck[1] => ck",
"ram_ck[2] => ck",
"ram_ck[3] => ck",
"ram_ck[4] => ck",
"ram_ck[5] => ck",
"ram_ck[6] => ck",
"ram_ck[7] => ck",
"ram_ck[8] => ck",
"ram_ck[9] => ck",
"ram_ck[10] => ck",
"ram_ck[11] => ck",
"ram_ck[12] => ck",
"ram_ck[13] => ck",
"ram_ck[14] => ck",
"ram_ck[15] => ck",
"ops_mx[2:0] => ops_mx[2:0]",
"opr_mx[1:0] => opr_mx[1:0]",
"alu_k[4:0] => alu_k[4:0]",
"alu_cin => cin", /* plot */
"alu_cout => cout",
"alu_over => alu_over",
"ram_sh[1:0] => ram_sh[1:0]",
"acc_sh[1:0] => ram_sh[1:0]",
"ram_i_up => ram_i_up",
"ram_i_down => ram_i_down",
"acc_i_up => acc_i_up",
"acc_i_down => acc_i_down",
"acc_q_down => acc_o_down",
"out_mx => out_mx",
"acc_ck => ck",
"acc_wen => acc_wen",
"acc_test => test", /* plot */
"acc_scin => scin", /* plot */
"acc_scout => acc_scout",
"a[15:0] => deca[15:0]",
"b[15:0] => decb[15:0]",
"b_w[15:0] => decwb[15:0]",
"opr_d[3:0] => d[3:0]",
"alu_f[3:0] => alu_f[3:0]",
"alu_np[3:0] => alu_np[3:0]",
"alu_ng[3:0] => alu_ng[3:0]",
"out_x[3:0] => y[3:0]",
"vdd => vdd",
"vss => vss", 0);
/* ***************** Control Instanciation ****************** */
GENLIB_LOINSE("amd2901_ctl", "ctl",
"ops_mx[2:0] => ops_mx[2:0]",
"opr_mx[1:0] => opr_mx[1:0]",
"alu_k[4:0] => alu_k[4:0]",
"alu_cout => cout",
"alu_over => alu_over",
/******************************/
"deca[15:0] => deca[15:0]",
"decb[15:0] => decb[15:0]",
"decwb[15:0] => decwb[15:0]",
"a[3:0] => a[3:0]",
"b[3:0] => b[3:0]", // bw == b
/**********************************/
"ram_sh[1:0] => ram_sh[1:0]",
"out_mx => out_mx",
"acc_wen => acc_wen",
"alu_f[3:0] => alu_f[3:0]",
"alu_np[3:0] => alu_np[3:0]",
"alu_ng[3:0] => alu_ng[3:0]",
"core_test => test", /* plot */
"core_fonc => fonc", /* plot */
"core_np => np", /* plot */
"core_ng => ng", /* plot */
"core_over => over", /* plot */
"core_zero => zero", /* plot */
"core_sh_right => sh_right",
"core_sh_left => sh_left",
"i[8:0] => i[8:0]",
// "ram_wri => ram_wri",
"noe => noe",
"oe => oe",
"vdd => vdd",
"vss => vss", 0);
GENLIB_PLACE ("amd2901_dpt", "amd2901_dpt", NOSYM, 0, 0);
GENLIB_DEF_AB (0, 0, 0, 100);
GENLIB_SAVE_LOFIG();
GENLIB_SAVE_PHFIG();
exit(0);
}

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# Copyright (c) 1997 by Cadence. All rights reserved.
###################################################################
# In each of TOP()/BOTTOM()/LEFT()/RIGHT() section, there are #
# placed IOs. In the IGNORE() section, the IOs are ignored #
# by the IOPlacer. In every section, the IO syntax could be: #
# for pin: (IOPIN iopinName.0 ); #
# for pad: iopadName orientation ; #
# for space: SPACE value; #
# The capital words are keywords. orientation is not required. #
# The value is the space between the IO above and the IO below it.#
###################################################################
TOP ( # IOs are ordered from left to right
(IOPIN b(3).0 );
(IOPIN cin.0 );
(IOPIN ck.0 );
(IOPIN cout.0 );
(IOPIN d(0).0 );
(IOPIN d(1).0 );
(IOPIN d(2).0 );
(IOPIN d(3).0 );
(IOPIN fonc.0 );
(IOPIN i(0).0 );
(IOPIN i(1).0 );
(IOPIN i(2).0 );
(IOPIN a(0).0 );
(IOPIN a(1).0 );
(IOPIN a(2).0 );
(IOPIN a(3).0 );
(IOPIN ng.0 );
(IOPIN acc_i_down.0 );
(IOPIN acc_i_up.0 );
(IOPIN acc_o_down.0 );
(IOPIN acc_o_up.0 );
(IOPIN b(0).0 );
(IOPIN b(1).0 );
(IOPIN b(2).0 );
)
BOTTOM ( # IOs are ordered from left to right
(IOPIN i(3).0 );
(IOPIN i(4).0 );
(IOPIN i(5).0 );
(IOPIN i(6).0 );
(IOPIN i(7).0 );
(IOPIN i(8).0 );
(IOPIN noe.0 );
(IOPIN np.0 );
(IOPIN oe.0 );
(IOPIN over.0 );
(IOPIN ram_i_down.0 );
(IOPIN ram_i_up.0 );
(IOPIN ram_o_down.0 );
(IOPIN ram_o_up.0 );
(IOPIN scin.0 );
(IOPIN sh_left.0 );
(IOPIN sh_right.0 );
(IOPIN test.0 );
(IOPIN y(0).0 );
(IOPIN y(1).0 );
(IOPIN y(2).0 );
(IOPIN y(3).0 );
(IOPIN zero.0 );
)
IGNORE ( # IOs are ignored(not placed) by IO Placer
)

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##Used by boog and loon
#M{4}
## Set the Optimisation Level (1..5)
## 1 : poor optimisation - small computation time
## 5 : best optimisation - long computation time
#L{5}

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ENTITY amd2901_ctl IS
PORT(
-- Input/Output from and to the data-path.
-- Command for selecting operands R and S.
ops_mx : out BIT_VECTOR(2 downto 0);
opr_mx : out BIT_VECTOR(1 downto 0);
-- ALU commands and auxiliary terminals.
alu_k : out BIT_VECTOR(4 downto 0);
alu_cout : in BIT;
alu_over : in BIT;
-- RAM, ACCU shifter commands and auxiliary terminals.
-- ("acc_sh" is same as "ram_sh")
ram_sh : out BIT_VECTOR(1 downto 0);
-- Output multiplexer commnand (for X bus).
out_mx : out BIT;
-- ACCU controls terminals.
-- ("acc_ck", "acc_test" and "acc_scin" directly comes from the plots)
acc_wen : out BIT;
-- Data bus terminals.
alu_f : in BIT_VECTOR(3 downto 0);
alu_np : in BIT_VECTOR(3 downto 0);
alu_ng : in BIT_VECTOR(3 downto 0);
-- Input/Output from and to the plots.
-- Test terminals from/to plots.
core_test : in BIT;
core_fonc : in BIT;
-- ALU terminals from/to plots.
-- core_ncout : out BIT;
core_np : out BIT;
core_ng : out BIT;
core_over : out BIT;
core_zero : out BIT;
-- core_nsign : out BIT;
-- RAM, ACCU shifter terminals from/to plots.
-- RAM and ACCU I/O plots controls.
core_sh_right : out BIT;
core_sh_left : out BIT;
-- Data bus terminals from/to the plots.
i : in BIT_VECTOR(8 downto 0);
noe : in BIT;
oe : out BIT;
-- -
-- ram_wri : out BIT;
-- +
a : in BIT_VECTOR(3 downto 0);
b : in BIT_VECTOR(3 downto 0);
deca : out BIT_VECTOR(15 downto 0);
decb : out BIT_VECTOR(15 downto 0);
decwb : out BIT_VECTOR(15 downto 0);
-- Power supply connectors.
vdd : in BIT;
vss : in BIT
-- -
);
END amd2901_ctl;
ARCHITECTURE behavior_data_flow OF amd2901_ctl IS
-- Internals bus.
SIGNAL alu_p : BIT_VECTOR(3 downto 0);
SIGNAL alu_g : BIT_VECTOR(3 downto 0);
-- Internals signals.
SIGNAL fonc_mode : BIT;
SIGNAL ram_wri : BIT;
SIGNAL interm : BIT_VECTOR (15 downto 0);
BEGIN
-- ******************** Miscellaneous controls *******************
-- Select between normal and test mode.
fonc_mode <= core_fonc and (not core_test);
-- *************** ACCU and RAM multiplexer control **************
WITH i(8 DOWNTO 6) SELECT
ram_sh <= "00" WHEN B"110"
| B"111",
"01" WHEN B"100"
| B"101",
"11" WHEN OTHERS;
-- ******************** S multiplexer control ********************
WITH i(2 downto 0) SELECT
ops_mx <= "000" WHEN B"110",
"000" WHEN B"010",
"000" WHEN B"000",
"010" WHEN B"101"
| B"100",
"001" WHEN B"001",
"001" WHEN B"011",
"100" WHEN B"111";
-- ******************** R multiplexer control ********************
WITH i(2 downto 0) SELECT
opr_mx <= "11" WHEN B"100"
| B"010"
| B"011",
"01" WHEN B"101"
| B"110"
| B"111",
"00" WHEN B"000"
| B"001";
-- ******************** X multiplexer control ********************
WITH i(8 downto 6) SELECT
out_mx <= "1" WHEN B"010",
"0" WHEN OTHERS;
-- ************************* ALU control *************************
-- ALU commands.
alu_k(4) <= ( i(5) or ( i(4) and i(3)));
alu_k(3) <= (not i(5) and ( i(4) and i(3)));
alu_k(2) <= ( i(5) and not i(4)) ;
alu_k(1) <= i(5) xor i(4);
alu_k(0) <= i(5) xor i(3);
-- Compute of ALU flags.
-- Propagate.
alu_p(3 downto 0) <= not alu_np(3 downto 0);
core_np <= not ( alu_p(0)
and alu_p(1)
and alu_p(2)
and alu_p(3));
-- Generate.
alu_g(3 downto 0) <= not alu_ng(3 downto 0);
core_ng <= not ( alu_g(3)
or (alu_p(3) and alu_g(2))
or (alu_p(3) and alu_p(2) and alu_g(1))
or (alu_p(3) and alu_p(2) and alu_p(1) and alu_g(0)));
-- Sign, zero, overflow and carry out.
-- core_nsign <= not alu_f(3);
core_zero <= not ( alu_f(3)
or alu_f(2)
or alu_f(1)
or alu_f(0));
core_over <= alu_cout xor alu_over;
-- ************************* ACCU control ************************
-- Compute of ACCU write enable.
acc_wen <= (not i(6)) and ((not i(7)) or i(8));
-- ACCU shifter I/O.
-- acc_i_up <= not core_acc_i_nup;
-- acc_i_down <= not core_acc_i_ndown;
-- core_acc_o_nup <= not acc_scout;
-- core_acc_o_ndown <= not acc_q_down;
-- ************************** RAM control ************************
-- Compute of RAM write enable.
ram_wri <= fonc_mode and (i(8) or i(7));
-- RAM and ACCU I/O plots controls.
core_sh_right <= i(8) and (not i(7));
core_sh_left <= i(8) and i(7) ;
-- RAM shifter I/O.
-- ram_i_up <= not core_ram_i_nup;
-- ram_i_down <= not core_ram_i_ndown;
-- core_ram_o_ndown <= not alu_f(0);
-- core_ram_o_nup <= not alu_f(3);
oe <= not noe;
-- +
WITH a(3 downto 0) SELECT
deca<= B"0000000000000001" WHEN X"0",
B"0000000000000010" WHEN X"1",
B"0000000000000100" WHEN X"2",
B"0000000000001000" WHEN X"3",
B"0000000000010000" WHEN X"4",
B"0000000000100000" WHEN X"5",
B"0000000001000000" WHEN X"6",
B"0000000010000000" WHEN X"7",
B"0000000100000000" WHEN X"8",
B"0000001000000000" WHEN X"9",
B"0000010000000000" WHEN X"A",
B"0000100000000000" WHEN X"B",
B"0001000000000000" WHEN X"C",
B"0010000000000000" WHEN X"D",
B"0100000000000000" WHEN X"E",
B"1000000000000000" WHEN OTHERS;
WITH b(3 downto 0) SELECT
interm<= B"0000000000000001" WHEN X"0",
B"0000000000000010" WHEN X"1",
B"0000000000000100" WHEN X"2",
B"0000000000001000" WHEN X"3",
B"0000000000010000" WHEN X"4",
B"0000000000100000" WHEN X"5",
B"0000000001000000" WHEN X"6",
B"0000000010000000" WHEN X"7",
B"0000000100000000" WHEN X"8",
B"0000001000000000" WHEN X"9",
B"0000010000000000" WHEN X"A",
B"0000100000000000" WHEN X"B",
B"0001000000000000" WHEN X"C",
B"0010000000000000" WHEN X"D",
B"0100000000000000" WHEN X"E",
B"1000000000000000" WHEN OTHERS;
decb <= interm;
WITH ram_wri SELECT
decwb<= interm WHEN B"1",
B"0000000000000000" WHEN OTHERS;
END behavior_data_flow;

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# include <genlib.h>
#define getbit(val,bit) (((val) >> (bit))%2)
extern int main()
{
long i;
/* Generate all the operators required for the register file. */
GENLIB_MACRO (DPGEN_INV , "model_inv_x8", F_PLACE, 4, 8);
GENLIB_MACRO (DPGEN_DFF , "model_dff" , F_PLACE, 4);
GENLIB_MACRO (DPGEN_NBUSE, "model_nbuse" , F_PLACE, 4);
/* Generate all the operators required */
GENLIB_MACRO (DPGEN_MUX2 , "model_mux2", F_PLACE, 4, 2);
GENLIB_MACRO (DPGEN_NAND2MASK, "model_nand2mask_0000", F_PLACE, 4,"0b0000");
GENLIB_MACRO (DPGEN_XNOR2MASK, "model_xnor2mask_1111", F_PLACE, 4, "0b1111");
GENLIB_MACRO (DPGEN_NAND2 , "model_nand2", F_PLACE, 4, 4); /* 1 ou 4 */
GENLIB_MACRO (DPGEN_NOR2MASK , "model_nor2mask_1111", F_PLACE, 4,"0b1111");
GENLIB_MACRO (DPGEN_NMUX2 , "model_nmux2", F_PLACE, 4,2);
GENLIB_MACRO (DPGEN_INV , "model_inv", F_PLACE, 4,1);
GENLIB_MACRO (DPGEN_NOR2 , "model_nor2", F_PLACE, 4, 4); /* 1 ou 4 */
GENLIB_MACRO (DPGEN_XOR2 , "model_xor2", F_PLACE, 4, 4); /* 1 ou 4 */
GENLIB_MACRO (DPGEN_XNOR2 , "model_xnor2", F_PLACE, 4, 4); /* 1 ou 4 */
GENLIB_MACRO (DPGEN_DFFT , "model_dfft", F_PLACE, 4); /* 1 ou 4 */
/* Netlist description. */
GENLIB_DEF_LOFIG ("amd2901_dpt");
/* Command for selecting operands R and S.*/
GENLIB_LOCON ("ops_mx[2:0]" , IN , "ops_mx[2:0]");
GENLIB_LOCON ("opr_mx[1:0]" , IN , "opr_mx[1:0]");
/* ALU commands and auxiliary terminals. */
GENLIB_LOCON ("alu_k[4:0]" , IN , "alu_k[4:0]");
GENLIB_LOCON ("alu_cin" , IN , "alu_cin") ;
GENLIB_LOCON ("alu_cout", OUT , "alu_cout") ;
GENLIB_LOCON ("alu_over" , INOUT , "alu_over");
/* RAM, ACCU shifter commands and auxiliary terminals.*/
GENLIB_LOCON ("ram_sh[1:0]" , IN , "ram_sh[1:0]") ;
GENLIB_LOCON ("acc_sh[1:0]" , IN , "acc_sh[1:0]") ;
/* RAM shifter inputs.*/
GENLIB_LOCON ("ram_i_up" , IN , "ram_i_up");
GENLIB_LOCON ("ram_i_down" , IN , "ram_i_down");
/* ACCU shifter inputs.*/
GENLIB_LOCON ("acc_i_up" , IN , "acc_i_up" ) ;
GENLIB_LOCON ("acc_i_down" , IN , "acc_i_down") ;
/* ACCU shifter outputs ("acc_scout" is "acc_q_up").*/
GENLIB_LOCON ("acc_q_down" , OUT , "acc_q_down");
/* Output multiplexer commnand (for X bus).*/
GENLIB_LOCON ("out_mx" , IN , "out_mx");
/* ACCU controls terminals.*/
GENLIB_LOCON ("acc_ck" , IN , "acc_ck" );
GENLIB_LOCON ("acc_wen" , IN , "acc_wen" );
GENLIB_LOCON ("acc_test" , IN , "acc_test" );
GENLIB_LOCON ("acc_scin" , IN , "acc_scin") ; /* Scan-Path input.*/
GENLIB_LOCON ("acc_scout", INOUT ,"acc_scout"); /* Scan-Path output.*/
/* Register file controls terminals.*/
GENLIB_LOCON ("ram_ck[15:0]", IN ,"ram_ck[15:0]") ; /* Register clocks (ck) */
GENLIB_LOCON ("b_w[15:0]" , IN , "b_w[15:0]") ; /* Write enable */
GENLIB_LOCON ("a[15:0]" , IN , "a[15:0]") ; /* Register A address. */
GENLIB_LOCON ("b[15:0]" , IN , "b[15:0]") ; /* Register B address. */
/* Data buses terminals.*/
GENLIB_LOCON ("opr_d[3:0]" , IN ,"opr_d[3:0]");
GENLIB_LOCON ("alu_f[3:0]" , INOUT ,"alu_f[3:0]");
GENLIB_LOCON ("alu_np[3:0]" , OUT ,"alu_np[3:0]");
GENLIB_LOCON ("alu_ng[3:0]" , OUT , "alu_ng[3:0]");
GENLIB_LOCON ("out_x[3:0]" ,OUT , "out_x[3:0]");
/* Power supply connectors. */
GENLIB_LOCON ("vdd", IN , "vdd");
GENLIB_LOCON ("vss", IN , "vss");
/* Register file description. */
for (i = 0; i < 16; i++)
{
/* Register part. */
GENLIB_LOINS ("model_dff", GENLIB_NAME("ram_reg%ld",i),
GENLIB_ELM ("b_w", i),
GENLIB_ELM ("ram_ck" , i),
"ram_d[3:0]",
GENLIB_NAME ("ram_q%ld[3:0]", i),
"vdd", "vss", NULL);
/* Tristate for A output. */
GENLIB_LOINS ("model_nbuse", GENLIB_NAME ("ram_ntsa%ld",i),
GENLIB_ELM ("a", i),
GENLIB_NAME ("ram_q%ld[3:0]", i),
"ram_nra[3:0]",
"vdd", "vss", NULL);
/* Tristate for B output. */
GENLIB_LOINS ("model_nbuse", GENLIB_NAME("ram_ntsb%ld",i),
GENLIB_ELM ("b", i),
GENLIB_NAME ("ram_q%ld[3:0]", i),
"ram_nrb[3:0]",
"vdd", "vss", NULL);
}
/* Output drivers for A & B output. */
GENLIB_LOINS ("model_inv_x8", "inv_ra",
"ram_nra[3:0]",
"ram_ra[3:0]",
"vdd", "vss", NULL);
GENLIB_LOINS ("model_inv_x8", "inv_rb",
"ram_nrb[3:0]",
"ram_rb[3:0]",
"vdd", "vss", NULL);
/* --------------------------------------------------------------
* RAM shifter.
*/
GENLIB_LOINS ("model_nmux2", "ram_nmux_0",
"ram_sh[0]",
"ram_i_up", "alu_f[3:1]", /* i1 */
"alu_f[2:0]", "ram_i_down", /* i0 */
"ram_nmux_0[3:0]",
"vdd", "vss", NULL);
GENLIB_LOINS ("model_inv", "ram_inv_1",
"alu_f[3:0]", /* i2 */
"ram_inv_1[3:0]",
"vdd", "vss", NULL);
GENLIB_LOINS ("model_nmux2", "ram_nmux_1",
"ram_sh[1]",
"ram_inv_1[3:0]",
"ram_nmux_0[3:0]",
"ram_d[3:0]",
"vdd", "vss", NULL);
/* *********************** Operand S ************************ */
GENLIB_LOINS ("model_nmux2", "ops_nmux_0",
"ops_mx[0]",
"ram_rb[3:0]", /* i1 */
"acc_scout", "acc_q[2:1]", "acc_q_down", /* i0 */
"ops_nmux_0[3:0]",
"vdd", "vss", NULL);
GENLIB_LOINS ("model_inv", "ops_inv_1",
"ram_ra[3:0]", /* i2 */
"ops_inv_1[3:0]",
"vdd", "vss", NULL);
GENLIB_LOINS ("model_nmux2", "ops_nmux_1",
"ops_mx[1]",
"ops_inv_1[3:0]",
"ops_nmux_0[3:0]",
"ops_it[3:0]",
"vdd", "vss", NULL);
GENLIB_LOINS ("model_nand2mask_0000", "ops_na2mask_0b0000",
"ops_mx[2]" ,
"ops_it[3:0]",
"ops_ns[3:0]",
"vdd", "vss", NULL);
/* *********************** Operand R ************************ */
GENLIB_LOINS ("model_mux2", "opr_mux",
"opr_mx[0]",
"opr_d[3:0]", /* i1 */
"ram_ra[3:0]", /* i0 */
"opr_it[3:0]",
"vdd", "vss", NULL);
GENLIB_LOINS ("model_nand2mask_0000", "opr_na2mask_0b0000",
"opr_mx[1]" ,
"opr_it[3:0]",
"opr_nr[3:0]",
"vdd", "vss", NULL);
/* *********************** ALU Description ****************** */
GENLIB_LOINS ("model_xnor2mask_1111", "alu_xr2_opnr",
"alu_k[0]" ,
"opr_nr[3:0]",
"alu_xr[3:0]",
"vdd", "vss", NULL);
GENLIB_LOINS ("model_xnor2mask_1111", "alu_xr2_opns",
"alu_k[1]" ,
"ops_ns[3:0]",
"alu_xs[3:0]",
"vdd", "vss", NULL);
/* Compute of "generate". */
GENLIB_LOINS ("model_nand2", "alu_na2_ng",
"alu_xr[3:0]",
"alu_xs[3:0]",
"alu_ng[3:0]",
"vdd", "vss", NULL);
/* Compute of "propagate". */
GENLIB_LOINS ("model_nor2", "alu_no2_np",
"alu_xr[3:0]",
"alu_xs[3:0]",
"alu_np[3:0]",
"vdd", "vss", NULL);
GENLIB_LOINS ("model_inv", "alu_n1_p" ,
"alu_np[3:0]",
"alu_p[3:0]",
"vdd", "vss", NULL);
/* Compute of carry. */
GENLIB_LOINS ("model_nand2", "alu_na2_npc" ,
"alu_p[3:0]",
"alu_over", "alu_carry[2:1]", "alu_cin",
"alu_npc[3:0]",
"vdd", "vss", NULL);
GENLIB_LOINS ("model_nand2", "alu_na2_carry",
"alu_ng[3:0]",
"alu_npc[3:0]",
"alu_cout", "alu_over", "alu_carry[2:1]",
"vdd", "vss", NULL);
/* Logical and arithmetical operators. */
GENLIB_LOINS ("model_nor2mask_1111", "alu_no2_and",
"alu_k[2]" ,
"alu_ng[3:0]",
"alu_r_and_s[3:0]",
"vdd", "vss", NULL);
GENLIB_LOINS ("model_nor2mask_1111", "alu_no2_or" ,
"alu_k[3]" ,
"alu_np[3:0]",
"alu_r_or_s[3:0]",
"vdd", "vss", NULL);
GENLIB_LOINS ("model_nor2mask_1111", "alu_no2_add",
"alu_k[4]" ,
"alu_over", "alu_carry[2:1]", "alu_cin",
"alu_r_add_s[3:0]",
"vdd", "vss", NULL);
/* Output. */
GENLIB_LOINS ("model_xor2", "alu_nxr2_op",
"alu_r_and_s[3:0]",
"alu_r_or_s[3:0]",
"alu_r_op_s[3:0]",
"vdd", "vss", NULL);
GENLIB_LOINS ("model_xnor2", "alu_nxr2_f" ,
"alu_r_op_s[3:0]",
"alu_r_add_s[3:0]",
"alu_f[3:0]",
"vdd", "vss", NULL);
/* ******************** ACCU Description ******************** */
GENLIB_LOINS ("model_nmux2", "accu_nmux_0",
"acc_sh[0]",
"acc_i_up", "acc_scout", "acc_q[2:1]", /* i1 : down */
"acc_q[2:1]", "acc_q_down", "acc_i_down", /* i0 : up */
"accu_nmux_0[3:0]",
"vdd", "vss", NULL);
GENLIB_LOINS ("model_inv", "accu_inv_1",
"alu_f[3:0]", /* i2: no */
"accu_inv_1[3:0]",
"vdd", "vss", NULL);
GENLIB_LOINS ("model_nmux2", "accu_nmux_1",
"acc_sh[1]",
"accu_inv_1[3:0]",
"accu_nmux_0[3:0]",
"acc_d[3:0]",
"vdd", "vss", NULL);
GENLIB_LOINS ("model_dfft", "acc_reg",
"acc_test" ,
"acc_scin" ,
"acc_wen",
"acc_ck" ,
"acc_d[3:0]",
"acc_scout", "acc_q[2:1]", "acc_q_down",
"vdd", "vss", NULL);
/* ******************* Output Multiplexer ******************* */
GENLIB_LOINS ("model_mux2", "out_mx",
"out_mx" ,
"ram_ra[3:0]", /* i1 */
"alu_f[3:0]", /* i0 */
"out_x[3:0]",
"vdd", "vss", NULL);
/* End of netlist description. */
GENLIB_SAVE_LOFIG ();
/* Partial placement description. */
GENLIB_DEF_PHFIG ("amd2901_dpt");
for (i = 0; i < 16; i++)
{
/* Register part. */
if (!(i % 8)) {
if (!i) {
GENLIB_PLACE ("model_dff", GENLIB_NAME ("ram_reg%ld",i), NOSYM, 0, 0);
} else {
GENLIB_DEF_PHINS (GENLIB_NAME ("ram_reg%ld", i - 8));
GENLIB_PLACE_TOP ("model_dff", GENLIB_NAME ("ram_reg%ld",i), NOSYM);
}
} else {
GENLIB_PLACE_RIGHT ("model_dff", GENLIB_NAME ("ram_reg%ld",i), NOSYM);
}
GENLIB_PLACE_RIGHT ("model_nbuse", GENLIB_NAME ("ram_ntsa%ld",i), NOSYM);
GENLIB_PLACE_RIGHT ("model_nbuse", GENLIB_NAME ("ram_ntsb%ld",i), NOSYM);
}
// GENLIB_PLACE_RIGHT ("model_inv_x8", "inv_ra", NOSYM);
// GENLIB_DEF_PHINS ("ram_ntsb7");
// GENLIB_PLACE_RIGHT ("model_inv_x8", "inv_rb", NOSYM);
GENLIB_PLACE("model_nmux2","ram_nmux_0",NOSYM, 500,700);
//GENLIB_PLACE_TOP ("model_nmux2", "ram_nmux_0", NOSYM);
GENLIB_PLACE_RIGHT ("model_nmux2", "ram_nmux_1", NOSYM);
GENLIB_PLACE_RIGHT ("model_nmux2", "ops_nmux_0", NOSYM);
GENLIB_PLACE_RIGHT ("model_nmux2", "ops_nmux_1", NOSYM);
GENLIB_PLACE_RIGHT ("model_mux2", "opr_mux", NOSYM);
#if 0
GENLIB_PLACE_RIGHT ("model_inv", "ram_inv_1", NOSYM);
/* *********************** Operand S ************************ */
GENLIB_PLACE_RIGHT ("model_inv", "ops_inv_1", NOSYM);
GENLIB_PLACE_RIGHT ("model_nand2mask_0000", "ops_na2mask_0b0000", NOSYM);
/* *********************** Operand R ************************ */
GENLIB_PLACE_RIGHT ("model_nand2mask_0000", "opr_na2mask_0b0000", NOSYM);
/* *********************** ALU Description ****************** */
GENLIB_PLACE_RIGHT ("model_xnor2mask_1111", "alu_xr2_opnr", NOSYM);
GENLIB_PLACE_RIGHT ("model_xnor2mask_1111", "alu_xr2_opns", NOSYM);
/* Compute of "generate". */
// GENLIB_PLACE_RIGHT ("model_nand2", "alu_na2_ng", NOSYM);
/* Compute of "propagate". */
// GENLIB_PLACE_RIGHT ("model_nor2", "alu_no2_np", NOSYM);
// GENLIB_PLACE_RIGHT ("model_inv", "alu_n1_p" , NOSYM);
/* Compute of carry. */
// GENLIB_PLACE_RIGHT ("model_nand2", "alu_na2_npc" , NOSYM);
/* Logical and arithmetical operators. */
//GENLIB_PLACE_RIGHT ("model_nor2mask_1111", "alu_no2_and", NOSYM);
//GENLIB_PLACE_RIGHT ("model_nor2mask_1111", "alu_no2_or" , NOSYM);
//GENLIB_PLACE_RIGHT ("model_nor2mask_1111", "alu_no2_add", NOSYM);
/* Output. */
GENLIB_PLACE_RIGHT ("model_xor2", "alu_nxr2_op", NOSYM);
GENLIB_PLACE_RIGHT ("model_xnor2", "alu_nxr2_f" , NOSYM);
/* ******************** ACCU Description ******************** */
#endif
GENLIB_PLACE_RIGHT ("model_nmux2", "accu_nmux_0", NOSYM);
//GENLIB_PLACE_RIGHT ("model_inv", "accu_inv_1", NOSYM);
GENLIB_PLACE_RIGHT ("model_nmux2", "accu_nmux_1", NOSYM);
GENLIB_PLACE_RIGHT ("model_dfft", "acc_reg", NOSYM);
/* ******************* Output Multiplexer ******************* */
GENLIB_PLACE_RIGHT ("model_mux2", "out_mx", NOSYM);
GENLIB_DEF_AB (0, 0, 0, 0);
/* End of placement description. */
GENLIB_SAVE_PHFIG ();
/* A good C program must always terminate by an "exit(0)". */
exit(0);
}

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#!/bin/zsh
true
while [ $? -eq 0 ]
do
make clean && make
done

1109
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