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reference sur les nouveaux outils

This commit is contained in:
Francois Donnet 2001-04-04 13:19:58 +00:00
parent 0fb92a822d
commit e68b783a12
3 changed files with 12 additions and 9 deletions
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7
alliance/share/man/man1/bop.1
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@ -1,7 +1,7 @@
.\" $Id: bop.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
.\" $Id: bop.1,v 1.2 2001/04/04 13:19:57 francois Exp $
.\"
.\"
.\" $Id: bop.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
.\" $Id: bop.1,v 1.2 2001/04/04 13:19:57 francois Exp $
.\"
.\"
.pl -.4
@ -26,6 +26,7 @@ bop
.br
.br
You should rather use the newest version of \fBboom\fP.
The logic level behavioural description (.vbe file) uses the same VHDL subset as the logic simulator \fBasimut\fP, the FSM synthesizer \fBsyf\fP, the functional abstractor \fByagle\fP and the formal prover \fBproof\fP (for further information about the subset of VHDL, see the "vbe" manual).
.br
A special feature has been introduced in the VHDL subset in order to allow the don't care description for external outputs and internal registers : A bit signal can take the 'd' value.
@ -121,7 +122,7 @@ You can call \fBbop\fP as follows :
.SH SEE ALSO
.br
scmap(1), c4map(1), xlmap(1), proof(1), yagle(1), asimut(1), vhdl(5), scr(1), sclib(1).
scmap(1), c4map(1), xlmap(1), proof(1), yagle(1), asimut(1), vhdl(5), scr(1), sclib(1), boom(1), boog(1), loon(1), scapin(1), sxlib(1).
.br

7
alliance/share/man/man1/glop.1
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@ -1,7 +1,7 @@
.\" $Id: glop.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
.\" $Id: glop.1,v 1.2 2001/04/04 13:19:58 francois Exp $
.\"
.\"
.\" $Id: glop.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
.\" $Id: glop.1,v 1.2 2001/04/04 13:19:58 francois Exp $
.\"
.\"
.pl -.4
@ -20,6 +20,7 @@ glop
.SH DESCRIPTION
.br
You should rather use the newest version of \fBloon\fP.
\fBglop\fP is a CAD tool that permits to remove fanout problems within a gates netlist and to optimize the delay. The netlist can be hierarchical and is flattened if necessary. \fBglop\fP run in batch mode and a parameter file can be used (see man \fBlax\fP) to parametrize optimization by adding informations on outputs (fanin), inputs (fanout, delay) and by setting general parameters such as fanout factor.
\fBglop\fP permits to compute delays of gates in the netlist and gives the critical path in the netlist. The global optimization of \fBglop\fP performs gate repowering and buffer inserting to decrease the critical path delay.
@ -71,7 +72,7 @@ You can call \fBglop\fP as follows :
.SH SEE ALSO
.br
genlib(1), scmap(1), sclib(1), scr(1)
loon(1), boom(1), boog(1), genlib(1), scmap(1), sclib(1), sxlib(1), scr(1).
.br
.SH DIAGNOSTICS

7
alliance/share/man/man1/scmap.1
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@ -1,7 +1,7 @@
.\" $Id: scmap.1,v 1.1 1999/05/31 17:30:14 alliance Exp $
.\" $Id: scmap.1,v 1.2 2001/04/04 13:19:58 francois Exp $
.\"
.\"
.\" $Id: scmap.1,v 1.1 1999/05/31 17:30:14 alliance Exp $
.\" $Id: scmap.1,v 1.2 2001/04/04 13:19:58 francois Exp $
.\"
.\"
.pl -.4
@ -27,6 +27,7 @@ scmap
.br
.br
You should rather use the newest version of \fBboog\fP.
The logic level behavioural description (.vbe file) uses the same VHDL subset as the logic simulator \fBasimut\fP, the FSM synthesizer \fBsyf\fP, the functional abstractor \fByagle\fP and the formal prover \fBproof\fP (for further information about the subset of VHDL, see the "vbe" manual).
.br
A special feature has been introduced in the VHDL subset in order to allow the don't care description for external outputs and internal registers : A bit signal can take the 'd' value.
@ -114,7 +115,7 @@ You can call \fBscmap\fP as follows :
.SH SEE ALSO
.br
scmap(1), c4map(1), xlmap(1), proof(1), yagle(1), asimut(1), vhdl(5), scr(1), sclib(1).
scmap(1), lax(1), c4map(1), xlmap(1), proof(1), yagle(1), asimut(1), vhdl(5), scr(1), sclib(1), boog(1), boom(1), loon(1), scapin(1), sxlib(1).
.br