Hello
This commit is contained in:
Ludovic Jacomme
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8812619071
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SUBDIRS = src
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SUBDIRS = src man1 man5
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@ -26,7 +26,7 @@ dnl Almost ten years since I wrote this stuff, I just can't
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dnl believe it
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dnl Date : 01/02/2002
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dnl Author : Frederic Petrot <Frederic.Petrot@lip6.fr>
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dnl $Id: configure.in,v 1.1 2002/03/20 14:21:51 ludo Exp $
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dnl $Id: configure.in,v 1.2 2002/03/20 14:26:41 ludo Exp $
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dnl
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dnl
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AC_INIT(src/fsm.h)
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@ -42,4 +42,6 @@ AM_ALLIANCE
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AC_OUTPUT([
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Makefile
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src/Makefile
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man1/Makefile
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man5/Makefile
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])
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man_MANS = fsm.1
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.\" $Id: fsm.1,v 1.1 2002/03/20 14:26:43 ludo Exp $
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.\" @(#)fsm.1 1.01 96/02/07 UPMC; Fsmhor : Jacomme Ludovic
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.TH FSM101 1 "October 1, 1997" "ASIM/LIP6" "ALLIANCE FSM LIBRARY"
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.SH NAME
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fsm \- Finite State Machine representation.
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.so man1/alc_origin.1
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.SH DESCRIPTION
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\fBfsm\fP is a library that enables to represent finite state machine.
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.TP
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Types :
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.TP 20
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.br
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\fBfsmin_list\fP
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\- inputs of a FSM.
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.TP
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\fBfsmout_list\fP
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\- outputs of a FSM.
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.TP
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\fBfsmport_list\fP
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\- ports of a FSM.
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.TP
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\fBfsmlocout_list\fP
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\- state output assign.
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.TP
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\fBfsmtrans_list\fP
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\- transition of a FSM.
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.TP
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\fBfsmstate_list\fP
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\- state of a FSM.
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.TP
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\fBfsmstack_list\fP
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\- stack of a FSM.
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.TP
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\fBfsmfig_list\fP
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\- FSM figure.
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.TP
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Functions :
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.TP 20
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.br
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...
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.TP 0
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libFsm101.a :
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.so man1/alc_bug_report.1
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man_MANS = fsm.5
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@ -0,0 +1,242 @@
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.\" $Id: fsm.5,v 1.1 2002/03/20 14:26:45 ludo Exp $
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.\" @(#)FSM.5 2.1 Sep 24 1995 UPMC ; Jacomme L.
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.TH FSM 5 "October 1, 1997" "ASIM/LIP6" "VHDL subset of ASIM/LIP6/CAO-VLSI lab."
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.SH NAME
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.PP
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\fBfsm\fP - Alliance VHDL Finite State Machine description subset.
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.so man1/alc_origin.1
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.SH DESCRIPTION
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.PP
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This document describes the Alliance VHDL subset for Finite State Machine description.
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.br
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This FSM subset is neither accepted by the logic simulator \fBasimut\fP(1),
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nor the formal prover \fBproof\fP(1).
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.br
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This VHDL subset is defined to enable classical MOORE and MEALEY synchronous
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finite state machine description as well as stack FSM description (see \fBsyf\fP(1)
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for further information about this kind of FSM).
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.br
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A FSM description is made of two and only two processes.
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Connectors and signals can only be of \fBin\fP, \fBout\fP, and two user defined
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enumerated types.
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Vectors of \fBin\fP and \fBout\fP types are also allowed.
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.br
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FSM's states and stack control signals must be declared as enumerated type.
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.br
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For the scan-path, three more signals are required :
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.RS
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- scan_test: in bit
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.br
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- scan_in: in bit
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.br
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- scan_out: out bit
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.RE
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.br
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For a ROM implementation, the vdd and vss signals must be explicitely declared as :
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.RS
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.br
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- rom_vdd : in bit
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.br
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- rom_vss : in bit
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.SH
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These signals, declared in the interface, are not used or assigned in the FSM description.
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The '-P' option of \fBsyf\fP(1) allows scan-path implementation.
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.br
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.PP
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Pragmas :
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.br
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.RS
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A pragma is a comment that gives necessary informations to the synthesis and formal
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proof tools.
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.br
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Three pragmas are used, their generic names are :
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.br
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.RS
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- CLOCK : External clock signal name.
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.br
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- CURRENT_STATE : Current State name.
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.br
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- NEXT_STATE : Next State name.
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.SH
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Ten other pragmas are optional.
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.br
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Three pragmas are required only for scan-path implementation.
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.br
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.RS
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- SCAN_TEST : Enable test mode (scan-path).
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.br
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- SCAN_IN : scan-path input.
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.br
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- SCAN_OUT : scan-path output.
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.br
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.SH
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Five others are used only in a STACK FSM.
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.br
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.RS
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- RETURN_STATE : Return State name.
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.br
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- CONTROL : Stack Control signal name.
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.br
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- POP : POP operation on the stack.
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.br
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- PUSH : PUSH operation on the stack.
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.br
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- NOP : NOP operation on the stack.
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.SH
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The last ones for ROM implementation
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.RS
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- ROM_VDD : Name of the vdd signal of the ROM.
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.br
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- ROM_VSS :Name of the vss signal of the ROM.
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.SH
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.br
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Two different processes are used : The first process, called state process,
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allows to describe state transition and outputs generation.
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It is not controlled by the clock.
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The second process is controlled by the clock and descibes the state
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register and stack registers modifications.
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.br
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State process sensitivity list contains inputs and CURRENT_STATE, it means
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that the state process is activated when the CURRENT_STATE or an input signal changes.
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A case statement is used to describe, for each state, the next state and outputs.
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.br
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The second process sensitivity list contains the clock signal, so this process
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is enabled whenever clock changes.
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Both Level sensitive latches, and edge triggered flip flops can be used for
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state registers and stack implementation.
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.br
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.SH EXAMPLES
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.PP
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.nf
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Entity FSM_EX is
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port(
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ck : in bit ;
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reset :in bit;
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t_mode:in bit;
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s_in :in bit;
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i :in bit;
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s_out :out bit;
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o :out bit
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);
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End FSM_EX;
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architecture auto of FSM_EX is
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type STATE_TYPE is (S0,S1,S2,S3,S4,S5);
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type CONTROL is (PUSH,POP,NOP);
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-- pragma CLOCK ck
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-- pragma CURRENT_STATE CURRENT_STATE
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-- pragma NEXT_STATE NEXT_STATE
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-- pragma RETURN_STATE RETURN_STATE
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-- pragma CONTROL CTRL
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-- pragma PUSH PUSH
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-- pragma POP POP
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-- pragma NOP NOP
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-- pragma SCAN_TEST t_mode
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-- pragma SCAN_IN s_in
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-- pragma SCAN_OUT s_out
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signal CURRENT_STATE, NEXT_STATE, RETURN_STATE : STATE_TYPE;
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signal CTRL : CONTROL;
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signal STACK_0, STACK_1 : STATE_TYPE ;
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begin
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PROCESS(CURRENT_STATE,I,reset)
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begin
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if(reset) then
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NEXT_STATE <= S0 ;
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o <= '0' ;
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else
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case CURRENT_STATE is
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WHEN S0 =>
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NEXT_STATE <= S1;
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RETURN_STATE <= S5;
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CTRL <= PUSH;
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o <= '0';
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WHEN S1 =>
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if (I = '1') then
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NEXT_STATE <= S2;
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CTRL <= NOP;
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else
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NEXT_STATE <= S3;
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CTRL <= NOP;
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end if;
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o <= '0';
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WHEN S2 =>
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NEXT_STATE <= S4;
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CTRL <= NOP;
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o <= '0';
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WHEN S3 =>
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NEXT_STATE <= S4;
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CTRL <= NOP;
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o <= '0';
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WHEN S4 =>
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NEXT_STATE <= STACK_0;
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CTRL <= POP;
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o <= '1';
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WHEN S5 =>
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if (I = '1') then
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NEXT_STATE <= S1;
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RETURN_STATE <= S0 ;
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CTRL <= PUSH;
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else
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NEXT_STATE <= S5;
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CTRL <= NOP;
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end if ;
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o <= '0';
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WHEN others =>
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assert ('1')
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report "illegal state";
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end case;
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end if ;
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end process;
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process(ck)
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begin
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if(ck = '0' and not ck' stable) then
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CURRENT_STATE <= NEXT_STATE;
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case CTRL is
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WHEN POP =>
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STACK_0 <= STACK_1;
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WHEN PUSH =>
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STACK_1 <= STACK_0;
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STACK_0 <= RETURN_STATE;
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WHEN NOP =>
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NULL;
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end case;
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end if;
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end process;
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end auto;
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.SH SEE ALSO
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.PP
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\fBvbe\fP(5), \fBsyf\fP(1)
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.so man1/alc_bug_report.1
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