diff --git a/alliance/src/cells/src/ramlib/ram_mem_deci.ap b/alliance/src/cells/src/ramlib/ram_mem_deci.ap
index 5bf3ddfc..f2440002 100644
--- a/alliance/src/cells/src/ramlib/ram_mem_deci.ap
+++ b/alliance/src/cells/src/ramlib/ram_mem_deci.ap
@@ -1,67 +1,67 @@
 V ALLIANCE : 6
-H ram_mem_deci,P, 7/ 5/2002,100
+H ram_mem_deci,P, 1/10/2002,100
 A 0,0,2500,5000
-S 200,300,2200,300,300,*,RIGHT,PTIE
-S 2100,300,2100,1000,200,*,DOWN,ALU1
-S 900,300,900,1000,200,*,DOWN,ALU1
-S 2100,3500,2100,4500,200,*,DOWN,ALU1
-S 2100,800,2100,1200,300,*,UP,NDIF
-S 900,800,900,1200,300,*,UP,NDIF
-S 500,2800,500,4700,300,*,DOWN,PDIF
-S 700,2800,700,4700,300,*,DOWN,PDIF
-S 1500,1000,1500,1500,200,*,DOWN,ALU1
-S 500,1500,1500,1500,200,*,LEFT,ALU1
-S 300,1000,500,1000,200,*,LEFT,ALU1
-S 1500,1000,1500,1000,200,seli,LEFT,CALU3
-S 0,0,0,5000,1200,vdd,UP,CALU3
-S 2500,0,2500,5000,1200,vss,UP,CALU3
-S 1000,1000,1500,1000,200,*,RIGHT,TALU2
-S 1000,1000,1500,1000,200,*,LEFT,ALU2
-S 1000,3500,1500,3500,200,i0,LEFT,CALU2
-S 1000,4000,1500,4000,200,i1,RIGHT,CALU2
-S 1000,2500,1000,4000,200,*,UP,ALU1
-S 0,4700,2500,4700,600,vdd,RIGHT,CALU1
-S 500,1000,500,4000,200,*,DOWN,ALU1
-S 1500,2000,1500,3500,200,*,UP,ALU1
-S 0,300,2500,300,600,vss,RIGHT,CALU1
-S 2100,1400,2100,2600,100,*,DOWN,POLY
-S 1800,2600,2100,2600,100,*,RIGHT,POLY
-S 1200,2000,1600,2000,300,*,LEFT,POLY
-S 1800,1500,2100,1500,300,*,RIGHT,POLY
-S 1200,1400,1200,1900,100,*,DOWN,POLY
-S 1400,2000,1400,2600,100,*,DOWN,POLY
-S 600,1400,600,2400,100,*,DOWN,POLY
-S 600,2400,1100,2400,100,*,LEFT,POLY
-S 300,800,300,1200,300,*,UP,NDIF
-S 1500,800,1500,1200,300,*,UP,NDIF
-S 1200,600,1200,1400,100,*,DOWN,NTRANS
-S 1800,600,1800,1400,100,*,DOWN,NTRANS
-S 600,600,600,1400,100,*,DOWN,NTRANS
-S 0,3900,2500,3900,2400,*,RIGHT,NWELL
-S 1800,2600,1800,4900,100,*,UP,PTRANS
-S 1000,2600,1000,4900,100,*,UP,PTRANS
-S 1400,2600,1400,4900,100,*,UP,PTRANS
-S 2100,2800,2100,4700,300,*,DOWN,PDIF
+S 300,1000,300,1500,200,*,DOWN,ALU1
+S 300,1500,1500,1500,200,*,LEFT,ALU1
+S 500,1500,500,4000,200,*,DOWN,ALU1
 S 2000,1500,2000,3000,200,i2,UP,CALU1
-V 2100,300,CONT_BODY_P,*
-V 900,300,CONT_BODY_P,*
-V 2100,3500,CONT_DIF_P,*
-V 2100,4000,CONT_DIF_P,*
-V 900,1000,CONT_DIF_N,*
-V 2100,1000,CONT_DIF_N,*
-V 1500,1000,CONT_VIA2,*
-V 1500,3500,CONT_VIA,*
-V 1000,4000,CONT_VIA,*
-V 1500,1000,CONT_VIA,*
-V 2000,1500,CONT_POLY,*
-V 1000,2500,CONT_POLY,*
-V 1500,2000,CONT_POLY,*
-V 300,300,CONT_BODY_P,*
-V 1500,300,CONT_BODY_P,*
-V 1500,1000,CONT_DIF_N,*
-V 300,1000,CONT_DIF_N,*
-V 2100,4500,CONT_DIF_P,*
-V 500,4000,CONT_DIF_P,*
-V 500,3500,CONT_DIF_P,*
+S 2100,2800,2100,4700,300,*,DOWN,PDIF
+S 1400,2600,1400,4900,100,*,UP,PTRANS
+S 1000,2600,1000,4900,100,*,UP,PTRANS
+S 1800,2600,1800,4900,100,*,UP,PTRANS
+S 0,3900,2500,3900,2400,*,RIGHT,NWELL
+S 600,600,600,1400,100,*,DOWN,NTRANS
+S 1800,600,1800,1400,100,*,DOWN,NTRANS
+S 1200,600,1200,1400,100,*,DOWN,NTRANS
+S 1500,800,1500,1200,300,*,UP,NDIF
+S 300,800,300,1200,300,*,UP,NDIF
+S 600,2400,1100,2400,100,*,LEFT,POLY
+S 600,1400,600,2400,100,*,DOWN,POLY
+S 1400,2000,1400,2600,100,*,DOWN,POLY
+S 1200,1400,1200,1900,100,*,DOWN,POLY
+S 1800,1500,2100,1500,300,*,RIGHT,POLY
+S 1200,2000,1600,2000,300,*,LEFT,POLY
+S 1800,2600,2100,2600,100,*,RIGHT,POLY
+S 2100,1400,2100,2600,100,*,DOWN,POLY
+S 0,300,2500,300,600,vss,RIGHT,CALU1
+S 1500,2000,1500,3500,200,*,UP,ALU1
+S 0,4700,2500,4700,600,vdd,RIGHT,CALU1
+S 1000,2500,1000,4000,200,*,UP,ALU1
+S 1000,4000,1500,4000,200,i1,RIGHT,CALU2
+S 1000,3500,1500,3500,200,i0,LEFT,CALU2
+S 1000,1000,1500,1000,200,*,LEFT,ALU2
+S 1000,1000,1500,1000,200,*,RIGHT,TALU2
+S 2500,0,2500,5000,1200,vss,UP,CALU3
+S 0,0,0,5000,1200,vdd,UP,CALU3
+S 1500,1000,1500,1000,200,seli,LEFT,CALU3
+S 1500,1000,1500,1500,200,*,DOWN,ALU1
+S 700,2800,700,4700,300,*,DOWN,PDIF
+S 500,2800,500,4700,300,*,DOWN,PDIF
+S 900,800,900,1200,300,*,UP,NDIF
+S 2100,800,2100,1200,300,*,UP,NDIF
+S 2100,3500,2100,4500,200,*,DOWN,ALU1
+S 900,300,900,1000,200,*,DOWN,ALU1
+S 2100,300,2100,1000,200,*,DOWN,ALU1
+S 200,300,2200,300,300,*,RIGHT,PTIE
 V 500,3000,CONT_DIF_P,*
+V 500,3500,CONT_DIF_P,*
+V 500,4000,CONT_DIF_P,*
+V 2100,4500,CONT_DIF_P,*
+V 300,1000,CONT_DIF_N,*
+V 1500,1000,CONT_DIF_N,*
+V 1500,300,CONT_BODY_P,*
+V 300,300,CONT_BODY_P,*
+V 1500,2000,CONT_POLY,*
+V 1000,2500,CONT_POLY,*
+V 2000,1500,CONT_POLY,*
+V 1500,1000,CONT_VIA,*
+V 1000,4000,CONT_VIA,*
+V 1500,3500,CONT_VIA,*
+V 1500,1000,CONT_VIA2,*
+V 2100,1000,CONT_DIF_N,*
+V 900,1000,CONT_DIF_N,*
+V 2100,4000,CONT_DIF_P,*
+V 2100,3500,CONT_DIF_P,*
+V 900,300,CONT_BODY_P,*
+V 2100,300,CONT_BODY_P,*
 EOF
diff --git a/alliance/src/cells/src/ramlib/ramlib.lef b/alliance/src/cells/src/ramlib/ramlib.lef
index a9cdcb54..11a61917 100644
--- a/alliance/src/cells/src/ramlib/ramlib.lef
+++ b/alliance/src/cells/src/ramlib/ramlib.lef
@@ -49,10 +49,10 @@ MACRO ram_mem_buf0
         LAYER L_ALU1 ;
         RECT 1.50 9.00 23.50 41.00 ;
         LAYER L_ALU2 ;
-        RECT 5.00 19.00 19.00 21.00 ;
         RECT 10.00 24.00 16.00 26.00 ;
         RECT 5.00 19.00 19.00 21.00 ;
         RECT 10.00 24.00 16.00 26.00 ;
+        RECT 5.00 19.00 19.00 21.00 ;
     END
 END ram_mem_buf0
 
@@ -137,42 +137,13 @@ MACRO ram_mem_data
     SIZE      25.00 BY 50.00 ;
     SYMMETRY  X Y ;
     SITE      core ;
-    PIN bit1
+    PIN selxi
         DIRECTION INPUT ;
         PORT
-            LAYER L_ALU2 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT -1.00 29.00 1.00 31.00 ;
+            LAYER L_ALU3 ;
+            RECT 9.00 44.00 11.00 46.00 ;
         END
-    END bit1
-    PIN nbit1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 24.00 39.00 26.00 41.00 ;
-            RECT 19.00 39.00 21.00 41.00 ;
-            RECT 14.00 39.00 16.00 41.00 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 4.00 39.00 6.00 41.00 ;
-            RECT -1.00 39.00 1.00 41.00 ;
-        END
-    END nbit1
-    PIN nbit0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT -1.00 19.00 1.00 21.00 ;
-        END
-    END nbit0
+    END selxi
     PIN bit0
         DIRECTION INPUT ;
         PORT
@@ -185,13 +156,42 @@ MACRO ram_mem_data
             RECT -1.00 9.00 1.00 11.00 ;
         END
     END bit0
-    PIN selxi
+    PIN nbit0
         DIRECTION INPUT ;
         PORT
-            LAYER L_ALU3 ;
-            RECT 9.00 44.00 11.00 46.00 ;
+            LAYER L_ALU2 ;
+            RECT 24.00 19.00 26.00 21.00 ;
+            RECT 19.00 19.00 21.00 21.00 ;
+            RECT 14.00 19.00 16.00 21.00 ;
+            RECT 9.00 19.00 11.00 21.00 ;
+            RECT 4.00 19.00 6.00 21.00 ;
+            RECT -1.00 19.00 1.00 21.00 ;
         END
-    END selxi
+    END nbit0
+    PIN nbit1
+        DIRECTION INPUT ;
+        PORT
+            LAYER L_ALU2 ;
+            RECT 24.00 39.00 26.00 41.00 ;
+            RECT 19.00 39.00 21.00 41.00 ;
+            RECT 14.00 39.00 16.00 41.00 ;
+            RECT 9.00 39.00 11.00 41.00 ;
+            RECT 4.00 39.00 6.00 41.00 ;
+            RECT -1.00 39.00 1.00 41.00 ;
+        END
+    END nbit1
+    PIN bit1
+        DIRECTION INPUT ;
+        PORT
+            LAYER L_ALU2 ;
+            RECT 24.00 29.00 26.00 31.00 ;
+            RECT 19.00 29.00 21.00 31.00 ;
+            RECT 14.00 29.00 16.00 31.00 ;
+            RECT 9.00 29.00 11.00 31.00 ;
+            RECT 4.00 29.00 6.00 31.00 ;
+            RECT -1.00 29.00 1.00 31.00 ;
+        END
+    END bit1
     PIN vss
         DIRECTION INOUT ;
         USE ground ;
@@ -214,16 +214,16 @@ MACRO ram_mem_data
     END vdd
     OBS
         LAYER L_ALU2 ;
-        RECT 9.00 44.00 16.00 46.00 ;
-        RECT 19.00 44.00 26.00 46.00 ;
-        RECT -1.00 14.00 6.00 16.00 ;
-        RECT -1.00 24.00 6.00 26.00 ;
-        RECT 19.00 24.00 26.00 26.00 ;
-        RECT 19.00 4.00 26.00 6.00 ;
-        RECT -1.00 4.00 26.00 46.00 ;
-        RECT 24.00 9.00 26.00 15.00 ;
-        RECT 24.00 29.00 26.00 33.00 ;
         RECT 24.00 37.00 26.00 41.00 ;
+        RECT 24.00 29.00 26.00 33.00 ;
+        RECT 24.00 9.00 26.00 15.00 ;
+        RECT -1.00 4.00 26.00 46.00 ;
+        RECT 19.00 4.00 26.00 6.00 ;
+        RECT 19.00 24.00 26.00 26.00 ;
+        RECT -1.00 24.00 6.00 26.00 ;
+        RECT -1.00 14.00 6.00 16.00 ;
+        RECT 19.00 44.00 26.00 46.00 ;
+        RECT 9.00 44.00 16.00 46.00 ;
     END
 END ram_mem_data
 
@@ -234,13 +234,6 @@ MACRO ram_mem_dec2
     SIZE      100.00 BY 50.00 ;
     SYMMETRY  X Y ;
     SITE      core ;
-    PIN ndecb
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 84.00 19.00 86.00 21.00 ;
-        END
-    END ndecb
     PIN ndeca
         DIRECTION OUTPUT ;
         PORT
@@ -248,13 +241,13 @@ MACRO ram_mem_dec2
             RECT 34.00 19.00 36.00 21.00 ;
         END
     END ndeca
-    PIN i0
-        DIRECTION INPUT ;
+    PIN ndecb
+        DIRECTION OUTPUT ;
         PORT
             LAYER L_ALU3 ;
-            RECT 9.00 19.00 11.00 21.00 ;
+            RECT 84.00 19.00 86.00 21.00 ;
         END
-    END i0
+    END ndecb
     PIN i1
         DIRECTION INPUT ;
         PORT
@@ -262,6 +255,13 @@ MACRO ram_mem_dec2
             RECT 59.00 19.00 61.00 21.00 ;
         END
     END i1
+    PIN i0
+        DIRECTION INPUT ;
+        PORT
+            LAYER L_ALU3 ;
+            RECT 9.00 19.00 11.00 21.00 ;
+        END
+    END i0
     PIN vdd
         DIRECTION INOUT ;
         USE power ;
@@ -301,11 +301,11 @@ MACRO ram_mem_dec2
         LAYER L_ALU1 ;
         RECT 1.50 9.00 98.50 41.00 ;
         LAYER L_ALU2 ;
-        RECT 9.00 19.00 86.00 21.00 ;
-        RECT 9.00 19.00 16.00 21.00 ;
-        RECT 59.00 19.00 66.00 21.00 ;
-        RECT 79.00 19.00 86.00 21.00 ;
         RECT 29.00 19.00 36.00 21.00 ;
+        RECT 79.00 19.00 86.00 21.00 ;
+        RECT 59.00 19.00 66.00 21.00 ;
+        RECT 9.00 19.00 16.00 21.00 ;
+        RECT 9.00 19.00 86.00 21.00 ;
     END
 END ram_mem_dec2
 
@@ -316,13 +316,6 @@ MACRO ram_mem_dec3
     SIZE      100.00 BY 50.00 ;
     SYMMETRY  X Y ;
     SITE      core ;
-    PIN ndecb
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 84.00 19.00 86.00 21.00 ;
-        END
-    END ndecb
     PIN ndeca
         DIRECTION OUTPUT ;
         PORT
@@ -330,20 +323,13 @@ MACRO ram_mem_dec3
             RECT 34.00 19.00 36.00 21.00 ;
         END
     END ndeca
-    PIN i0
-        DIRECTION INPUT ;
+    PIN ndecb
+        DIRECTION OUTPUT ;
         PORT
             LAYER L_ALU3 ;
-            RECT 9.00 19.00 11.00 21.00 ;
+            RECT 84.00 19.00 86.00 21.00 ;
         END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-        END
-    END i1
+    END ndecb
     PIN i2
         DIRECTION INPUT ;
         PORT
@@ -351,6 +337,20 @@ MACRO ram_mem_dec3
             RECT 59.00 19.00 61.00 21.00 ;
         END
     END i2
+    PIN i1
+        DIRECTION INPUT ;
+        PORT
+            LAYER L_ALU3 ;
+            RECT 14.00 19.00 16.00 21.00 ;
+        END
+    END i1
+    PIN i0
+        DIRECTION INPUT ;
+        PORT
+            LAYER L_ALU3 ;
+            RECT 9.00 19.00 11.00 21.00 ;
+        END
+    END i0
     PIN vdd
         DIRECTION INOUT ;
         USE power ;
@@ -390,12 +390,12 @@ MACRO ram_mem_dec3
         LAYER L_ALU1 ;
         RECT 1.50 9.00 98.50 41.00 ;
         LAYER L_ALU2 ;
-        RECT 4.00 19.00 86.00 21.00 ;
-        RECT 79.00 19.00 86.00 21.00 ;
-        RECT 54.00 19.00 61.00 21.00 ;
-        RECT 29.00 19.00 36.00 21.00 ;
-        RECT 14.00 19.00 21.00 21.00 ;
         RECT 4.00 19.00 11.00 21.00 ;
+        RECT 14.00 19.00 21.00 21.00 ;
+        RECT 29.00 19.00 36.00 21.00 ;
+        RECT 54.00 19.00 61.00 21.00 ;
+        RECT 79.00 19.00 86.00 21.00 ;
+        RECT 4.00 19.00 86.00 21.00 ;
     END
 END ram_mem_dec3
 
@@ -406,13 +406,6 @@ MACRO ram_mem_dec4
     SIZE      100.00 BY 50.00 ;
     SYMMETRY  X Y ;
     SITE      core ;
-    PIN ndecb
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 84.00 19.00 86.00 21.00 ;
-        END
-    END ndecb
     PIN ndeca
         DIRECTION OUTPUT ;
         PORT
@@ -420,27 +413,13 @@ MACRO ram_mem_dec4
             RECT 34.00 19.00 36.00 21.00 ;
         END
     END ndeca
-    PIN i0
-        DIRECTION INPUT ;
+    PIN ndecb
+        DIRECTION OUTPUT ;
         PORT
             LAYER L_ALU3 ;
-            RECT 9.00 19.00 11.00 21.00 ;
+            RECT 84.00 19.00 86.00 21.00 ;
         END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-        END
-    END i1
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 59.00 19.00 61.00 21.00 ;
-        END
-    END i2
+    END ndecb
     PIN i3
         DIRECTION INPUT ;
         PORT
@@ -448,6 +427,27 @@ MACRO ram_mem_dec4
             RECT 64.00 19.00 66.00 21.00 ;
         END
     END i3
+    PIN i2
+        DIRECTION INPUT ;
+        PORT
+            LAYER L_ALU3 ;
+            RECT 59.00 19.00 61.00 21.00 ;
+        END
+    END i2
+    PIN i1
+        DIRECTION INPUT ;
+        PORT
+            LAYER L_ALU3 ;
+            RECT 14.00 19.00 16.00 21.00 ;
+        END
+    END i1
+    PIN i0
+        DIRECTION INPUT ;
+        PORT
+            LAYER L_ALU3 ;
+            RECT 9.00 19.00 11.00 21.00 ;
+        END
+    END i0
     PIN vdd
         DIRECTION INOUT ;
         USE power ;
@@ -487,13 +487,13 @@ MACRO ram_mem_dec4
         LAYER L_ALU1 ;
         RECT 1.50 9.00 98.50 41.00 ;
         LAYER L_ALU2 ;
-        RECT 4.00 19.00 86.00 21.00 ;
-        RECT 4.00 19.00 11.00 21.00 ;
-        RECT 14.00 19.00 21.00 21.00 ;
-        RECT 29.00 19.00 36.00 21.00 ;
-        RECT 54.00 19.00 61.00 21.00 ;
-        RECT 64.00 19.00 71.00 21.00 ;
         RECT 79.00 19.00 86.00 21.00 ;
+        RECT 64.00 19.00 71.00 21.00 ;
+        RECT 54.00 19.00 61.00 21.00 ;
+        RECT 29.00 19.00 36.00 21.00 ;
+        RECT 14.00 19.00 21.00 21.00 ;
+        RECT 4.00 19.00 11.00 21.00 ;
+        RECT 4.00 19.00 86.00 21.00 ;
     END
 END ram_mem_dec4
 
@@ -504,13 +504,6 @@ MACRO ram_mem_dec5
     SIZE      100.00 BY 50.00 ;
     SYMMETRY  X Y ;
     SITE      core ;
-    PIN ndeca
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-        END
-    END ndeca
     PIN ndecb
         DIRECTION OUTPUT ;
         PORT
@@ -518,34 +511,13 @@ MACRO ram_mem_dec5
             RECT 84.00 19.00 86.00 21.00 ;
         END
     END ndecb
-    PIN i0
-        DIRECTION INPUT ;
+    PIN ndeca
+        DIRECTION OUTPUT ;
         PORT
             LAYER L_ALU3 ;
-            RECT 9.00 19.00 11.00 21.00 ;
+            RECT 14.00 19.00 16.00 21.00 ;
         END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-        END
-    END i1
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-        END
-    END i2
-    PIN i3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 59.00 19.00 61.00 21.00 ;
-        END
-    END i3
+    END ndeca
     PIN i4
         DIRECTION INPUT ;
         PORT
@@ -553,6 +525,34 @@ MACRO ram_mem_dec5
             RECT 64.00 19.00 66.00 21.00 ;
         END
     END i4
+    PIN i3
+        DIRECTION INPUT ;
+        PORT
+            LAYER L_ALU3 ;
+            RECT 59.00 19.00 61.00 21.00 ;
+        END
+    END i3
+    PIN i2
+        DIRECTION INPUT ;
+        PORT
+            LAYER L_ALU3 ;
+            RECT 39.00 19.00 41.00 21.00 ;
+        END
+    END i2
+    PIN i1
+        DIRECTION INPUT ;
+        PORT
+            LAYER L_ALU3 ;
+            RECT 34.00 19.00 36.00 21.00 ;
+        END
+    END i1
+    PIN i0
+        DIRECTION INPUT ;
+        PORT
+            LAYER L_ALU3 ;
+            RECT 9.00 19.00 11.00 21.00 ;
+        END
+    END i0
     PIN vdd
         DIRECTION INOUT ;
         USE power ;
@@ -592,14 +592,14 @@ MACRO ram_mem_dec5
         LAYER L_ALU1 ;
         RECT 1.50 9.00 98.50 41.00 ;
         LAYER L_ALU2 ;
-        RECT 4.00 19.00 11.00 21.00 ;
-        RECT 14.00 19.00 21.00 21.00 ;
-        RECT 4.00 19.00 86.00 21.00 ;
-        RECT 29.00 19.00 36.00 21.00 ;
-        RECT 39.00 19.00 46.00 21.00 ;
-        RECT 54.00 19.00 61.00 21.00 ;
-        RECT 64.00 19.00 71.00 21.00 ;
         RECT 79.00 19.00 86.00 21.00 ;
+        RECT 64.00 19.00 71.00 21.00 ;
+        RECT 54.00 19.00 61.00 21.00 ;
+        RECT 39.00 19.00 46.00 21.00 ;
+        RECT 29.00 19.00 36.00 21.00 ;
+        RECT 4.00 19.00 86.00 21.00 ;
+        RECT 14.00 19.00 21.00 21.00 ;
+        RECT 4.00 19.00 11.00 21.00 ;
     END
 END ram_mem_dec5
 
@@ -779,13 +779,13 @@ MACRO ram_prech_buf1
         LAYER L_ALU1 ;
         RECT 1.50 9.00 28.50 41.00 ;
         LAYER L_ALU2 ;
-        RECT 4.00 -6.00 31.00 6.00 ;
+        RECT 9.00 34.00 21.00 36.00 ;
+        RECT 9.00 34.00 21.00 36.00 ;
         RECT 4.00 44.00 31.00 56.00 ;
-        RECT 9.00 34.00 21.00 36.00 ;
-        RECT 9.00 34.00 21.00 36.00 ;
+        RECT 4.00 -6.00 31.00 6.00 ;
         LAYER L_ALU3 ;
-        RECT 4.00 -1.00 16.00 51.00 ;
         RECT 24.00 -1.00 36.00 51.00 ;
+        RECT 4.00 -1.00 16.00 51.00 ;
     END
 END ram_prech_buf1
 
@@ -796,6 +796,38 @@ MACRO ram_prech_data
     SIZE      30.00 BY 50.00 ;
     SYMMETRY  X Y ;
     SITE      core ;
+    PIN nbit0
+        DIRECTION INPUT ;
+        PORT
+            LAYER L_ALU2 ;
+            RECT 29.00 19.00 31.00 21.00 ;
+            RECT 24.00 19.00 26.00 21.00 ;
+        END
+    END nbit0
+    PIN nbit1
+        DIRECTION INPUT ;
+        PORT
+            LAYER L_ALU2 ;
+            RECT 29.00 39.00 31.00 41.00 ;
+            RECT 24.00 39.00 26.00 41.00 ;
+        END
+    END nbit1
+    PIN bit1
+        DIRECTION INPUT ;
+        PORT
+            LAYER L_ALU2 ;
+            RECT 29.00 29.00 31.00 31.00 ;
+            RECT 24.00 29.00 26.00 31.00 ;
+        END
+    END bit1
+    PIN bit0
+        DIRECTION INPUT ;
+        PORT
+            LAYER L_ALU2 ;
+            RECT 29.00 9.00 31.00 11.00 ;
+            RECT 24.00 9.00 26.00 11.00 ;
+        END
+    END bit0
     PIN prech
         DIRECTION INPUT ;
         PORT
@@ -808,38 +840,6 @@ MACRO ram_prech_data
             RECT 19.00 14.00 21.00 16.00 ;
         END
     END prech
-    PIN bit0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 29.00 9.00 31.00 11.00 ;
-            RECT 24.00 9.00 26.00 11.00 ;
-        END
-    END bit0
-    PIN bit1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 29.00 29.00 31.00 31.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-        END
-    END bit1
-    PIN nbit1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 29.00 39.00 31.00 41.00 ;
-            RECT 24.00 39.00 26.00 41.00 ;
-        END
-    END nbit1
-    PIN nbit0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-        END
-    END nbit0
     PIN vdd
         DIRECTION INOUT ;
         USE power ;
@@ -867,16 +867,16 @@ MACRO ram_prech_data
         RECT 1.50 9.00 28.50 41.00 ;
         RECT 13.00 44.00 28.50 50.00 ;
         LAYER L_ALU2 ;
-        RECT 9.00 9.00 15.00 11.00 ;
-        RECT 9.00 27.00 15.00 29.00 ;
-        RECT 4.00 33.00 21.00 35.00 ;
-        RECT 4.00 15.00 21.00 17.00 ;
-        RECT 4.00 21.00 21.00 23.00 ;
-        RECT 4.00 39.00 21.00 41.00 ;
         RECT 4.00 9.00 21.00 41.00 ;
+        RECT 4.00 39.00 21.00 41.00 ;
+        RECT 4.00 21.00 21.00 23.00 ;
+        RECT 4.00 15.00 21.00 17.00 ;
+        RECT 4.00 33.00 21.00 35.00 ;
+        RECT 9.00 27.00 15.00 29.00 ;
+        RECT 9.00 9.00 15.00 11.00 ;
         LAYER L_ALU3 ;
-        RECT 24.00 -1.00 36.00 51.00 ;
         RECT 4.00 -1.00 16.00 51.00 ;
+        RECT 24.00 -1.00 36.00 51.00 ;
     END
 END ram_prech_data
 
@@ -1048,6 +1048,45 @@ MACRO ram_sense_buf1
     SIZE      170.00 BY 50.00 ;
     SYMMETRY  X Y ;
     SITE      core ;
+    PIN nwrite
+        DIRECTION OUTPUT ;
+        PORT
+            LAYER L_ALU3 ;
+            RECT 94.00 29.00 96.00 31.00 ;
+        END
+    END nwrite
+    PIN nckx
+        DIRECTION OUTPUT ;
+        PORT
+            LAYER L_ALU3 ;
+            RECT 104.00 29.00 106.00 31.00 ;
+        END
+    END nckx
+    PIN nsense
+        DIRECTION OUTPUT ;
+        PORT
+            LAYER L_ALU3 ;
+            RECT 69.00 29.00 71.00 31.00 ;
+        END
+    END nsense
+    PIN selramx
+        DIRECTION OUTPUT ;
+        PORT
+            LAYER L_ALU2 ;
+            RECT 59.00 29.00 61.00 31.00 ;
+            RECT 54.00 29.00 56.00 31.00 ;
+            RECT 49.00 29.00 51.00 31.00 ;
+            RECT 44.00 29.00 46.00 31.00 ;
+            RECT 39.00 29.00 41.00 31.00 ;
+            RECT 34.00 29.00 36.00 31.00 ;
+            RECT 29.00 29.00 31.00 31.00 ;
+            RECT 24.00 29.00 26.00 31.00 ;
+            RECT 19.00 29.00 21.00 31.00 ;
+            RECT 14.00 29.00 16.00 31.00 ;
+            RECT 9.00 29.00 11.00 31.00 ;
+            RECT 4.00 29.00 6.00 31.00 ;
+        END
+    END selramx
     PIN nck
         DIRECTION OUTPUT ;
         PORT
@@ -1074,58 +1113,17 @@ MACRO ram_sense_buf1
             RECT 59.00 24.00 61.00 26.00 ;
         END
     END nck
-    PIN selramx
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 59.00 29.00 61.00 31.00 ;
-            RECT 54.00 29.00 56.00 31.00 ;
-            RECT 49.00 29.00 51.00 31.00 ;
-            RECT 44.00 29.00 46.00 31.00 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-            RECT 34.00 29.00 36.00 31.00 ;
-            RECT 29.00 29.00 31.00 31.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-        END
-    END selramx
-    PIN nsense
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 69.00 29.00 71.00 31.00 ;
-        END
-    END nsense
-    PIN nckx
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 104.00 29.00 106.00 31.00 ;
-        END
-    END nckx
-    PIN nwrite
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 94.00 29.00 96.00 31.00 ;
-        END
-    END nwrite
-    PIN ck
+    PIN w
         DIRECTION INPUT ;
         PORT
             LAYER L_ALU1 ;
-            RECT 159.00 39.00 161.00 41.00 ;
-            RECT 159.00 34.00 161.00 36.00 ;
-            RECT 159.00 29.00 161.00 31.00 ;
-            RECT 159.00 24.00 161.00 26.00 ;
-            RECT 159.00 19.00 161.00 21.00 ;
-            RECT 159.00 14.00 161.00 16.00 ;
-            RECT 159.00 9.00 161.00 11.00 ;
+            RECT 84.00 34.00 86.00 36.00 ;
+            RECT 84.00 29.00 86.00 31.00 ;
+            RECT 84.00 24.00 86.00 26.00 ;
+            RECT 84.00 19.00 86.00 21.00 ;
+            RECT 84.00 14.00 86.00 16.00 ;
         END
-    END ck
+    END w
     PIN selram
         DIRECTION INPUT ;
         PORT
@@ -1139,17 +1137,19 @@ MACRO ram_sense_buf1
             RECT 49.00 9.00 51.00 11.00 ;
         END
     END selram
-    PIN w
+    PIN ck
         DIRECTION INPUT ;
         PORT
             LAYER L_ALU1 ;
-            RECT 84.00 34.00 86.00 36.00 ;
-            RECT 84.00 29.00 86.00 31.00 ;
-            RECT 84.00 24.00 86.00 26.00 ;
-            RECT 84.00 19.00 86.00 21.00 ;
-            RECT 84.00 14.00 86.00 16.00 ;
+            RECT 159.00 39.00 161.00 41.00 ;
+            RECT 159.00 34.00 161.00 36.00 ;
+            RECT 159.00 29.00 161.00 31.00 ;
+            RECT 159.00 24.00 161.00 26.00 ;
+            RECT 159.00 19.00 161.00 21.00 ;
+            RECT 159.00 14.00 161.00 16.00 ;
+            RECT 159.00 9.00 161.00 11.00 ;
         END
-    END w
+    END ck
     PIN vdd
         DIRECTION INOUT ;
         USE power ;
@@ -1174,15 +1174,15 @@ MACRO ram_sense_buf1
         LAYER L_ALU1 ;
         RECT 1.50 9.00 168.50 41.00 ;
         LAYER L_ALU2 ;
-        RECT 89.00 29.00 96.00 31.00 ;
-        RECT 69.00 29.00 111.00 31.00 ;
-        RECT 104.00 29.00 111.00 31.00 ;
-        RECT 69.00 29.00 76.00 31.00 ;
-        RECT -1.00 44.00 131.00 56.00 ;
         RECT -1.00 -6.00 131.00 6.00 ;
+        RECT -1.00 44.00 131.00 56.00 ;
+        RECT 69.00 29.00 76.00 31.00 ;
+        RECT 104.00 29.00 111.00 31.00 ;
+        RECT 69.00 29.00 111.00 31.00 ;
+        RECT 89.00 29.00 96.00 31.00 ;
         LAYER L_ALU3 ;
-        RECT -6.00 -1.00 6.00 51.00 ;
         RECT 119.00 -1.00 131.00 51.00 ;
+        RECT -6.00 -1.00 6.00 51.00 ;
     END
 END ram_sense_buf1
 
@@ -1206,6 +1206,16 @@ MACRO ram_sense_data
             RECT 99.00 9.00 101.00 11.00 ;
         END
     END dout
+    PIN din
+        DIRECTION INPUT ;
+        PORT
+            LAYER L_ALU1 ;
+            RECT 164.00 34.00 166.00 36.00 ;
+            RECT 164.00 29.00 166.00 31.00 ;
+            RECT 164.00 24.00 166.00 26.00 ;
+            RECT 164.00 19.00 166.00 21.00 ;
+        END
+    END din
     PIN prechx
         DIRECTION INPUT ;
         PORT
@@ -1311,17 +1321,6 @@ MACRO ram_sense_data
             RECT 29.00 19.00 31.00 21.00 ;
         END
     END ad0x
-    PIN din
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 164.00 34.00 166.00 36.00 ;
-            RECT 164.00 29.00 166.00 31.00 ;
-            RECT 164.00 24.00 166.00 26.00 ;
-            RECT 164.00 19.00 166.00 21.00 ;
-            RECT 164.00 14.00 166.00 16.00 ;
-        END
-    END din
     PIN vdd
         DIRECTION INOUT ;
         USE power ;
@@ -1380,30 +1379,6 @@ MACRO ram_sense_decad12
     SIZE      170.00 BY 50.00 ;
     SYMMETRY  X Y ;
     SITE      core ;
-    PIN ndec00
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-        END
-    END ndec00
-    PIN ndec01
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-        END
-    END ndec01
-    PIN ndec10
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 69.00 24.00 71.00 26.00 ;
-            RECT 64.00 24.00 66.00 26.00 ;
-        END
-    END ndec10
     PIN ndec11
         DIRECTION OUTPUT ;
         PORT
@@ -1412,19 +1387,30 @@ MACRO ram_sense_decad12
             RECT 94.00 29.00 96.00 31.00 ;
         END
     END ndec11
-    PIN ad1
-        DIRECTION INPUT ;
+    PIN ndec10
+        DIRECTION OUTPUT ;
         PORT
-            LAYER L_ALU1 ;
-            RECT 164.00 39.00 166.00 41.00 ;
-            RECT 164.00 34.00 166.00 36.00 ;
-            RECT 164.00 29.00 166.00 31.00 ;
-            RECT 164.00 24.00 166.00 26.00 ;
-            RECT 164.00 19.00 166.00 21.00 ;
-            RECT 164.00 14.00 166.00 16.00 ;
-            RECT 164.00 9.00 166.00 11.00 ;
+            LAYER L_ALU2 ;
+            RECT 69.00 24.00 71.00 26.00 ;
+            RECT 64.00 24.00 66.00 26.00 ;
         END
-    END ad1
+    END ndec10
+    PIN ndec01
+        DIRECTION OUTPUT ;
+        PORT
+            LAYER L_ALU2 ;
+            RECT 39.00 19.00 41.00 21.00 ;
+            RECT 34.00 19.00 36.00 21.00 ;
+        END
+    END ndec01
+    PIN ndec00
+        DIRECTION OUTPUT ;
+        PORT
+            LAYER L_ALU2 ;
+            RECT 9.00 14.00 11.00 16.00 ;
+            RECT 4.00 14.00 6.00 16.00 ;
+        END
+    END ndec00
     PIN ad2
         DIRECTION INPUT ;
         PORT
@@ -1438,6 +1424,19 @@ MACRO ram_sense_decad12
             RECT 139.00 9.00 141.00 11.00 ;
         END
     END ad2
+    PIN ad1
+        DIRECTION INPUT ;
+        PORT
+            LAYER L_ALU1 ;
+            RECT 164.00 39.00 166.00 41.00 ;
+            RECT 164.00 34.00 166.00 36.00 ;
+            RECT 164.00 29.00 166.00 31.00 ;
+            RECT 164.00 24.00 166.00 26.00 ;
+            RECT 164.00 19.00 166.00 21.00 ;
+            RECT 164.00 14.00 166.00 16.00 ;
+            RECT 164.00 9.00 166.00 11.00 ;
+        END
+    END ad1
     PIN vdd
         DIRECTION INOUT ;
         USE power ;
@@ -1464,15 +1463,15 @@ MACRO ram_sense_decad12
         LAYER L_ALU2 ;
         RECT 76.00 9.00 146.00 11.00 ;
         RECT 16.00 14.00 141.00 16.00 ;
-        RECT 52.00 34.00 161.00 36.00 ;
         RECT 22.00 39.00 166.00 41.00 ;
         RECT 52.00 34.00 161.00 36.00 ;
         RECT 22.00 39.00 166.00 41.00 ;
+        RECT 52.00 34.00 161.00 36.00 ;
         RECT 16.00 14.00 141.00 16.00 ;
         RECT 76.00 9.00 146.00 11.00 ;
         LAYER L_ALU3 ;
-        RECT 119.00 -1.00 131.00 51.00 ;
         RECT -6.00 -1.00 6.00 51.00 ;
+        RECT 119.00 -1.00 131.00 51.00 ;
     END
 END ram_sense_decad12