From e39a99d9926768c49cdffbe2282111a2c41ea006 Mon Sep 17 00:00:00 2001 From: Frederic Petrot Date: Mon, 26 Jul 2004 11:32:54 +0000 Subject: [PATCH] Result of merges. Note that an LC_CTYPE of iso_8859_1 make this (an other) man pages to fail on iconv. --- alliance/src/loon/doc/loon.1 | 16 +++++++++++++--- alliance/src/loon/src/lon_lib_utils.c | 7 ++++++- 2 files changed, 19 insertions(+), 4 deletions(-) diff --git a/alliance/src/loon/doc/loon.1 b/alliance/src/loon/doc/loon.1 index 5743eb6f..880a4d76 100644 --- a/alliance/src/loon/doc/loon.1 +++ b/alliance/src/loon/doc/loon.1 @@ -36,7 +36,7 @@ .TH LOON 1 "Sept 01 2000" "ASIM/LIP6" "CAO\-VLSI Reference Manual" .SH NAME .TP -LooN \- Light optimizing on Nets. +LooN \- Local optimizations of Nets. .so man1/alc_origin.1 @@ -48,8 +48,18 @@ LooN \- Light optimizing on Nets. .SH DESCRIPTION .br -\f4loon\fP is a CAD tool that permits to remove fanout problems within a gates netlist and to optimize the delay. The netlist can be hierarchical and is flattened if necessary. \f4loon\fP run in batch mode and a parameter file can be used (see man \f4lax\fP) to parametrize optimization by adding informations on outputs (fanin), inputs (fanout, delay) and by setting general parameters such as optimization level. -\f4loon\fP permits to compute delays of gates in the netlist and gives the critical path in the netlist. The global optimization of \f4loon\fP performs gate repowering to decrease the critical path delay and global capacitance. Buffers are only inserted in critical path. +\f4loon\fP is a CAD tool that allows to remove fanout problems within a +gate netlist and also to optimize the delay. +The netlist can be hierarchical and is flattened if necessary. +\f4loon\fP runs in batch mode and a parameter file can be used +(see man \f4lax\fP) to parametrize optimization by adding informations +on outputs (fanin), inputs (fanout, delay) and by setting general +parameters such as optimization level. +\f4loon\fP permits to compute delays of gates in the netlist and gives +the critical path in the netlist. +The global optimization of \f4loon\fP performs gate repowering to +decrease the critical path delay and global capacitance. +Buffers are only inserted in critical path. .br diff --git a/alliance/src/loon/src/lon_lib_utils.c b/alliance/src/loon/src/lon_lib_utils.c index 5d5f84b8..5bfb0e6b 100644 --- a/alliance/src/loon/src/lon_lib_utils.c +++ b/alliance/src/loon/src/lon_lib_utils.c @@ -357,8 +357,13 @@ extern void addCell(befig_list* befig) /*search same behaviour*/ for (chain=CELLS; chain; chain=chain->NEXT) { + int x; cell= (cell_list*) chain->DATA; - if (compare_befig(cell->BEFIG,befig)) break; +printf("+ %s %s\n", cell->BEFIG->NAME, befig->NAME); + x = compare_befig(cell->BEFIG, + befig); +printf("- %s %s\n", cell->BEFIG->NAME, befig->NAME); + if (x) break; } /*insert cell*/