- a 4 bits divisor example
This commit is contained in:
Ludovic Jacomme
parent
3385117a7d
commit
ddf92b81fa
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cas C
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divcas4_model C
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# /*------------------------------------------------------------\
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# | |
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# | File : Makefile |
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# | |
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# | Author : Jacomme Ludovic |
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# | |
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# \------------------------------------------------------------*/
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# /*------------------------------------------------------------\
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# | |
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# | Cells |
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# | |
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# \------------------------------------------------------------*/
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# /*------------------------------------------------------------\
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# | |
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# | Binary |
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# | |
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# \------------------------------------------------------------*/
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ALLIANCE_BIN = $(ALLIANCE_TOP)/bin
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VASY = $(ALLIANCE_BIN)/vasy
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ASIMUT = $(ALLIANCE_BIN)/asimut
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BOOM = $(ALLIANCE_BIN)/boom
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BOOG = $(ALLIANCE_BIN)/boog
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LOON = $(ALLIANCE_BIN)/loon
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OCP = $(ALLIANCE_BIN)/ocp
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OCR = $(ALLIANCE_BIN)/ocr
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NERO = $(ALLIANCE_BIN)/nero
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COUGAR = $(ALLIANCE_BIN)/cougar
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LVX = $(ALLIANCE_BIN)/lvx
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DRUC = $(ALLIANCE_BIN)/druc
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S2R = $(ALLIANCE_BIN)/s2r
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DREAL = $(ALLIANCE_BIN)/dreal
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GRAAL = $(ALLIANCE_BIN)/graal
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XSCH = $(ALLIANCE_BIN)/xsch
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XPAT = $(ALLIANCE_BIN)/xpat
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XFSM = $(ALLIANCE_BIN)/xfsm
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TOUCH = touch
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TARGET_LIB = $(ALLIANCE_TOP)/cells/sxlib
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RDS_TECHNO_SYMB = ../etc/techno-symb.rds
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RDS_TECHNO = ../etc/techno-035.rds
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SPI_MODEL = $(ALLIANCE_TOP)/etc/spimodel.cfg
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METAL_LEVEL = 2
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# /*------------------------------------------------------------\
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# | |
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# | Environement |
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# | |
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# \------------------------------------------------------------*/
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ENV_VASY = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
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MBK_CATAL_NAME=NO_CATAL; export MBK_CATAL_NAME
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ENV_BOOM = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
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ENV_BOOG = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
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MBK_IN_LO=vst; export MBK_IN_LO; \
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MBK_OUT_LO=vst; export MBK_OUT_LO; \
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MBK_TARGET_LIB=$(TARGET_LIB); export MBK_TARGET_LIB; \
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
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ENV_LOON = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
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MBK_IN_LO=vst; export MBK_IN_LO; \
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MBK_OUT_LO=vst; export MBK_OUT_LO; \
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MBK_TARGET_LIB=$(TARGET_LIB); export MBK_TARGET_LIB; \
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MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
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ENV_ASIMUT_VASY = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
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MBK_CATAL_NAME=CATAL_ASIMUT_VASY; export MBK_CATAL_NAME;\
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MBK_IN_LO=vst; export MBK_IN_LO;\
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MBK_OUT_LO=vst; export MBK_OUT_LO
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ENV_ASIMUT_SYNTH = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME;\
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MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
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MBK_IN_LO=vst; export MBK_IN_LO;\
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MBK_OUT_LO=vst; export MBK_OUT_LO
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ENV_OCP = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
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MBK_IN_LO=vst; export MBK_IN_LO; \
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MBK_OUT_LO=vst; export MBK_OUT_LO; \
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MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
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MBK_IN_PH=ap; export MBK_IN_PH; \
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MBK_OUT_PH=ap; export MBK_OUT_PH; \
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
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ENV_OCR = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
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MBK_IN_LO=vst; export MBK_IN_LO; \
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MBK_OUT_LO=vst; export MBK_OUT_LO; \
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MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
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MBK_IN_PH=ap; export MBK_IN_PH; \
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MBK_OUT_PH=ap; export MBK_OUT_PH; \
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
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ENV_COUGAR_SPI = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
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MBK_IN_LO=spi; export MBK_IN_LO; \
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MBK_OUT_LO=spi; export MBK_OUT_LO; \
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MBK_SPI_NAMEDNODES="true"; export MBK_SPI_NAMEDNODES; \
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MBK_SPI_MODEL=$(SPI_MODEL); export MBK_SPI_MODEL; \
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RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME; \
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RDS_IN=cif; export RDS_IN; \
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RDS_OUT=cif; export RDS_OUT; \
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MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
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MBK_IN_PH=ap; export MBK_IN_PH; \
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MBK_OUT_PH=ap; export MBK_OUT_PH; \
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
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ENV_COUGAR = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
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MBK_IN_LO=al; export MBK_IN_LO; \
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MBK_OUT_LO=al; export MBK_OUT_LO; \
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RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME; \
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RDS_IN=cif; export RDS_IN; \
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RDS_OUT=cif; export RDS_OUT; \
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MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
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MBK_IN_PH=ap; export MBK_IN_PH; \
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MBK_OUT_PH=ap; export MBK_OUT_PH; \
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
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ENV_LVX = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
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MBK_IN_LO=vst; export MBK_IN_LO; \
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MBK_OUT_LO=vst; export MBK_OUT_LO; \
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MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
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ENV_DRUC = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
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RDS_TECHNO_NAME=$(RDS_TECHNO_SYMB); export RDS_TECHNO_NAME; \
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MBK_IN_PH=ap; export MBK_IN_PH; \
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MBK_OUT_PH=ap; export MBK_OUT_PH; \
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MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
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ENV_S2R = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
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RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME; \
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RDS_IN=cif; export RDS_IN; \
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RDS_OUT=cif; export RDS_OUT; \
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MBK_IN_PH=ap; export MBK_IN_PH; \
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MBK_OUT_PH=ap; export MBK_OUT_PH; \
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MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
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all : divcas4_er.al
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# /*------------------------------------------------------------\
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# | |
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# | Vasy |
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# | |
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# \------------------------------------------------------------*/
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divcas4.vst cas.vbe divcas4_model.vbe : divcas4.vhdl
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$(ENV_VASY); $(VASY) -a -B -o -p -I vhdl -H divcas4
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# /*------------------------------------------------------------\
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# | |
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# | Asimut |
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# | |
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# \------------------------------------------------------------*/
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res_vasy_1.pat : divcas4.vst cas.vbe divcas4_model.vbe
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$(ENV_ASIMUT_VASY); $(ASIMUT) divcas4 divcas4 res_vasy_1
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res_synth_1.pat : divcas4.vst cas.vst divcas4_model.vst
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$(ENV_ASIMUT_SYNTH); $(ASIMUT) divcas4 divcas4 res_synth_1
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# /*------------------------------------------------------------\
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# | Boom |
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# | |
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# \------------------------------------------------------------*/
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boom.done : cas_o.vbe divcas4_model_o.vbe
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@$(TOUCH) boom.done
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cas_o.vbe : cas.vbe res_vasy_1.pat
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$(ENV_BOOM); $(BOOM) -VP cas cas_o
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divcas4_model_o.vbe : divcas4_model.vbe res_vasy_1.pat
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$(ENV_BOOM); $(BOOM) -VP divcas4_model divcas4_model_o
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# /*------------------------------------------------------------\
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# | |
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# | Boog |
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# | |
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# \------------------------------------------------------------*/
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boog.done : cas_o.vst divcas4_model_o.vst
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@$(TOUCH) boog.done
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cas_o.vst : cas_o.vbe
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$(ENV_BOOG); $(BOOG) cas_o
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divcas4_model_o.vst : divcas4_model_o.vbe
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$(ENV_BOOG); $(BOOG) divcas4_model_o
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# /*------------------------------------------------------------\
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# | |
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# | Loon |
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# | |
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# \------------------------------------------------------------*/
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loon.done : cas.vst divcas4_model.vst
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@$(TOUCH) loon.done
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cas.vst : cas_o.vst
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$(ENV_LOON); $(LOON) cas_o cas
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divcas4_model.vst : divcas4_model_o.vst
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$(ENV_LOON); $(LOON) divcas4_model_o divcas4_model
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# /*------------------------------------------------------------\
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# | |
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# | OCP |
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# | |
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# \------------------------------------------------------------*/
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divcas4_p.ap : res_synth_1.pat
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$(ENV_OCP); $(OCP) -v -ioc divcas4 -gnuplot divcas4 divcas4_p
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# /*------------------------------------------------------------\
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# | |
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# | OCR |
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# | |
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# \------------------------------------------------------------*/
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divcas4.ap : divcas4_p.ap divcas4.vst
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$(ENV_OCR); $(OCR) -v -l $(METAL_LEVEL) -L divcas4 -P divcas4_p -O divcas4
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#
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# /*------------------------------------------------------------\
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# | |
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# | NERO |
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# | |
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# \------------------------------------------------------------*/
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divcas4_nero.ap : divcas4_p.ap divcas4.vst
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$(ENV_OCR); $(NERO) -V -$(METAL_LEVEL) -p divcas4_p divcas4 divcas4
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# /*------------------------------------------------------------\
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# | |
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# | Cougar |
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# | |
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# \------------------------------------------------------------*/
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divcas4_e.al : divcas4.ap
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$(ENV_COUGAR); $(COUGAR) -v -ac divcas4 divcas4_e
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divcas4_et.al : divcas4.ap
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$(ENV_COUGAR); $(COUGAR) -v -t -ac divcas4 divcas4_et
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divcas4_e.spi : divcas4.ap divcas4_e.al
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$(ENV_COUGAR_SPI); $(COUGAR) -v -ac divcas4 divcas4_e
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divcas4_et.spi : divcas4.ap divcas4_e.al
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$(ENV_COUGAR_SPI); $(COUGAR) -v -t -ac divcas4 divcas4_et
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divcas4_er.al : divcas4.cif
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$(ENV_COUGAR); $(COUGAR) -v -r -t divcas4 divcas4_er
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# /*------------------------------------------------------------\
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# | |
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# | Lvx |
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# | |
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# \------------------------------------------------------------*/
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lvx.done : divcas4.vst divcas4_e.al
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$(ENV_LVX); $(LVX) vst al divcas4 divcas4_e -f
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$(TOUCH) lvx.done
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# /*------------------------------------------------------------\
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# | |
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# | Druc |
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# | |
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# \------------------------------------------------------------*/
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druc.done : lvx.done divcas4.ap
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$(ENV_DRUC); $(DRUC) divcas4
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$(TOUCH) druc.done
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# /*------------------------------------------------------------\
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# | |
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# | S2R |
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# | |
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# \------------------------------------------------------------*/
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divcas4.cif : druc.done
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$(ENV_S2R); $(S2R) -v -t divcas4
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# /*------------------------------------------------------------\
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# | |
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# | TOOLS |
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# | |
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# \------------------------------------------------------------*/
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graal: divcas4.ap
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$(ENV_S2R); $(GRAAL) -l divcas4
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xsch: divcas4.vst
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$(ENV_LOON); $(XSCH) -l divcas4
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xscht: divcas4_et.al
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$(ENV_COUGAR); $(XSCH) -l divcas4_et
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xpat: res_synth_1.pat
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$(ENV_ASIMUT_SYNTH); $(XPAT) -l res_synth_1
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dreal: divcas4.cif
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$(ENV_S2R); $(DREAL) -l divcas4
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# /*------------------------------------------------------------\
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# | |
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# | Clean |
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# | |
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# \------------------------------------------------------------*/
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realclean : clean
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clean :
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$(RM) -f *.vst *.vbe *.boom *.done *.xsc *.al *.ap *.gpl *.gds \
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*.log *.drc *.cif *.fin *.dat *.out divcas4_e.spi res_synth_1.pat \
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res_vasy_1.pat
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@ -0,0 +1,18 @@
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# /*------------------------------------------------------------\
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# | |
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# | File : README |
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# | |
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# | Author : Jacomme Ludovic |
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# | |
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# \------------------------------------------------------------*/
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This directory contains the VHDL description of an 4 bits divisor and
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the associated stimuli file, and also a configuration file for IO
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placement (used during the Place and Route step).
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The Makefile set environement variables properly and run Alliance tools,
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following each step of the design flow from VHDL up to real layout in a
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pseudo 0.35 techno.
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The environement variable ALLIANCE_TOP as to be set.
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@ -0,0 +1,3 @@
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##
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## Generated by VASY
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##
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@ -0,0 +1,21 @@
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
entity cas is -- Controlled Add/Subtract cell
|
||||||
|
port (
|
||||||
|
divisor : in std_logic;
|
||||||
|
T : in std_logic;
|
||||||
|
remainder_in : in std_logic;
|
||||||
|
cin : in std_logic;
|
||||||
|
remainder_out : out std_logic;
|
||||||
|
cout : out std_logic);
|
||||||
|
end cas;
|
||||||
|
|
||||||
|
architecture circuits of cas is
|
||||||
|
signal tt : std_logic;
|
||||||
|
begin
|
||||||
|
tt <= T xor divisor;
|
||||||
|
remainder_out <= tt xor remainder_in xor cin;
|
||||||
|
cout <= (tt and remainder_in) or (tt and cin) or
|
||||||
|
(remainder_in and cin);
|
||||||
|
end circuits;
|
||||||
|
|
@ -0,0 +1,37 @@
|
||||||
|
# Copyright (c) 1997 by Cadence. All rights reserved.
|
||||||
|
###################################################################
|
||||||
|
# In each of TOP()/BOTTOM()/LEFT()/RIGHT() section, there are #
|
||||||
|
# placed IOs. In the IGNORE() section, the IOs are ignored #
|
||||||
|
# by the IOPlacer. In every section, the IO syntax could be: #
|
||||||
|
# for pin: (IOPIN iopinName.0 ); #
|
||||||
|
# for pad: iopadName orientation ; #
|
||||||
|
# for space: SPACE value; #
|
||||||
|
# The capital words are keywords. orientation is not required. #
|
||||||
|
# The value is the space between the IO above and the IO below it.#
|
||||||
|
###################################################################
|
||||||
|
|
||||||
|
TOP ( # IOs are ordered from left to right
|
||||||
|
(IOPIN dividend(6).0 );
|
||||||
|
(IOPIN dividend(5).0 );
|
||||||
|
(IOPIN dividend(4).0 );
|
||||||
|
(IOPIN dividend(3).0 );
|
||||||
|
(IOPIN dividend(2).0 );
|
||||||
|
(IOPIN dividend(1).0 );
|
||||||
|
(IOPIN dividend(0).0 );
|
||||||
|
(IOPIN divisor(3).0 );
|
||||||
|
(IOPIN divisor(2).0 );
|
||||||
|
(IOPIN divisor(1).0 );
|
||||||
|
(IOPIN divisor(0).0 );
|
||||||
|
)
|
||||||
|
BOTTOM ( # IOs are ordered from left to right
|
||||||
|
(IOPIN remainder(3).0 );
|
||||||
|
(IOPIN remainder(2).0 );
|
||||||
|
(IOPIN remainder(1).0 );
|
||||||
|
(IOPIN remainder(0).0 );
|
||||||
|
(IOPIN quotient(3).0 );
|
||||||
|
(IOPIN quotient(2).0 );
|
||||||
|
(IOPIN quotient(1).0 );
|
||||||
|
(IOPIN quotient(0).0 );
|
||||||
|
)
|
||||||
|
IGNORE ( # IOs are ignored(not placed) by IO Placer
|
||||||
|
)
|
||||||
|
|
@ -0,0 +1,23 @@
|
||||||
|
|
||||||
|
in dividend (6 downto 0) X;;;
|
||||||
|
in divisor (3 downto 0) X;;;
|
||||||
|
out quotient (3 downto 0) X;;;
|
||||||
|
out remainder (3 downto 0) X;;;
|
||||||
|
in vss B;;
|
||||||
|
in vdd B;;
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
-- Pattern description :
|
||||||
|
-- d d q r V V
|
||||||
|
-- i i u e V V
|
||||||
|
-- v v o m V V
|
||||||
|
-- i i t a V V
|
||||||
|
-- d s i i V V
|
||||||
|
|
||||||
|
< +10ns>: 12 3 ?* ?* 0 1;
|
||||||
|
< +10ns>: 12 3 ?* ?* 0 1;
|
||||||
|
< +10ns>: 17 3 ?* ?* 0 1;
|
||||||
|
< +10ns>: 17 3 ?* ?* 0 1;
|
||||||
|
|
||||||
|
end;
|
||||||
|
|
@ -0,0 +1,78 @@
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
entity divcas4 is -- 8 bit dividend, 4 bit divisor
|
||||||
|
port (
|
||||||
|
dividend : in std_logic_vector(6 downto 0);
|
||||||
|
divisor : in std_logic_vector(3 downto 0);
|
||||||
|
quotient : out std_logic_vector(3 downto 0);
|
||||||
|
remainder : out std_logic_vector(3 downto 0));
|
||||||
|
end divcas4;
|
||||||
|
|
||||||
|
use IEEE.std_logic_textio.all;
|
||||||
|
use STD.textio.all;
|
||||||
|
|
||||||
|
architecture circuits of divcas4 is
|
||||||
|
|
||||||
|
component cas
|
||||||
|
port (
|
||||||
|
divisor : in std_logic;
|
||||||
|
T : in std_logic;
|
||||||
|
remainder_in : in std_logic;
|
||||||
|
cin : in std_logic;
|
||||||
|
remainder_out : out std_logic;
|
||||||
|
cout : out std_logic);
|
||||||
|
end component;
|
||||||
|
|
||||||
|
signal T : std_logic_vector(3 downto 0);
|
||||||
|
signal c36, c35, c34, c33, c25, c24, c23, c22 : std_logic;
|
||||||
|
signal c14, c13, c12, c11, c03, c02, c01, c00 : std_logic;
|
||||||
|
signal r36, r35, r34, r33, r25, r24, r23, r22 : std_logic;
|
||||||
|
signal r14, r13, r12, r11, r03, r02, r01, r00 : std_logic;
|
||||||
|
begin
|
||||||
|
T(3) <= '1';
|
||||||
|
cas36: cas port map(
|
||||||
|
divisor(3), T(3), dividend(6), c35, r36, c36);
|
||||||
|
cas35: cas port map(
|
||||||
|
divisor(2), T(3), dividend(5), c34, r35, c35);
|
||||||
|
cas34: cas port map(
|
||||||
|
divisor(1), T(3), dividend(4), c33, r34, c34);
|
||||||
|
cas33: cas port map(
|
||||||
|
divisor(0), T(3), dividend(3), T(3), r33, c33);
|
||||||
|
T(2) <= not r36;
|
||||||
|
|
||||||
|
cas25: cas port map(
|
||||||
|
divisor(3), T(2), r35 , c24, r25, c25);
|
||||||
|
cas24: cas port map(
|
||||||
|
divisor(2), T(2), r34 , c23, r24, c24);
|
||||||
|
cas23: cas port map(
|
||||||
|
divisor(1), T(2), r33 , c22, r23, c23);
|
||||||
|
cas22: cas port map(
|
||||||
|
divisor(0), T(2), dividend(2), T(2), r22, c22);
|
||||||
|
T(1) <= not r25;
|
||||||
|
|
||||||
|
cas14: cas port map(
|
||||||
|
divisor(3), T(1), r24 , c13, r14, c14);
|
||||||
|
cas13: cas port map(
|
||||||
|
divisor(2), T(1), r23 , c12, r13, c13);
|
||||||
|
cas12: cas port map(
|
||||||
|
divisor(1), T(1), r22 , c11, r12, c12);
|
||||||
|
cas11: cas port map(
|
||||||
|
divisor(0), T(1), dividend(1), T(1), r11, c11);
|
||||||
|
T(0) <= not r14;
|
||||||
|
|
||||||
|
cas03: cas port map( divisor(3), T(0), r13 , c02, r03, c03);
|
||||||
|
cas02: cas port map( divisor(2), T(0), r12 , c01, r02, c02);
|
||||||
|
cas01: cas port map( divisor(1), T(0), r11 , c00, r01, c01);
|
||||||
|
cas00: cas port map( divisor(0), T(0), dividend(0), T(0), r00, c00);
|
||||||
|
|
||||||
|
quotient(3) <= T(2);
|
||||||
|
quotient(2) <= T(1);
|
||||||
|
quotient(1) <= T(0);
|
||||||
|
quotient(0) <= not r03;
|
||||||
|
remainder(3) <= r03;
|
||||||
|
remainder(2) <= r02;
|
||||||
|
remainder(1) <= r01;
|
||||||
|
remainder(0) <= r00;
|
||||||
|
|
||||||
|
end circuits;
|
||||||
|
|
@ -0,0 +1,3 @@
|
||||||
|
##
|
||||||
|
## Generated by VASY
|
||||||
|
##
|
||||||
Loading…
Reference in New Issue