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- a 4 bits divisor example

This commit is contained in:
Ludovic Jacomme 2004-05-23 17:52:11 +00:00
parent 3385117a7d
commit ddf92b81fa
9 changed files with 512 additions and 0 deletions
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2
alliance/src/documentation/alliance-examples/divcas4/CATAL_ASIMUT_VASY Normal file
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cas C
divcas4_model C

327
alliance/src/documentation/alliance-examples/divcas4/Makefile Normal file
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# /*------------------------------------------------------------\
# | |
# | File : Makefile |
# | |
# | Author : Jacomme Ludovic |
# | |
# \------------------------------------------------------------*/
# /*------------------------------------------------------------\
# | |
# | Cells |
# | |
# \------------------------------------------------------------*/
# /*------------------------------------------------------------\
# | |
# | Binary |
# | |
# \------------------------------------------------------------*/
ALLIANCE_BIN = $(ALLIANCE_TOP)/bin
VASY = $(ALLIANCE_BIN)/vasy
ASIMUT = $(ALLIANCE_BIN)/asimut
BOOM = $(ALLIANCE_BIN)/boom
BOOG = $(ALLIANCE_BIN)/boog
LOON = $(ALLIANCE_BIN)/loon
OCP = $(ALLIANCE_BIN)/ocp
OCR = $(ALLIANCE_BIN)/ocr
NERO = $(ALLIANCE_BIN)/nero
COUGAR = $(ALLIANCE_BIN)/cougar
LVX = $(ALLIANCE_BIN)/lvx
DRUC = $(ALLIANCE_BIN)/druc
S2R = $(ALLIANCE_BIN)/s2r
DREAL = $(ALLIANCE_BIN)/dreal
GRAAL = $(ALLIANCE_BIN)/graal
XSCH = $(ALLIANCE_BIN)/xsch
XPAT = $(ALLIANCE_BIN)/xpat
XFSM = $(ALLIANCE_BIN)/xfsm
TOUCH = touch
TARGET_LIB = $(ALLIANCE_TOP)/cells/sxlib
RDS_TECHNO_SYMB = ../etc/techno-symb.rds
RDS_TECHNO = ../etc/techno-035.rds
SPI_MODEL = $(ALLIANCE_TOP)/etc/spimodel.cfg
METAL_LEVEL = 2
# /*------------------------------------------------------------\
# | |
# | Environement |
# | |
# \------------------------------------------------------------*/
ENV_VASY = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
MBK_CATAL_NAME=NO_CATAL; export MBK_CATAL_NAME
ENV_BOOM = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
ENV_BOOG = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
MBK_IN_LO=vst; export MBK_IN_LO; \
MBK_OUT_LO=vst; export MBK_OUT_LO; \
MBK_TARGET_LIB=$(TARGET_LIB); export MBK_TARGET_LIB; \
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
ENV_LOON = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
MBK_IN_LO=vst; export MBK_IN_LO; \
MBK_OUT_LO=vst; export MBK_OUT_LO; \
MBK_TARGET_LIB=$(TARGET_LIB); export MBK_TARGET_LIB; \
MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
ENV_ASIMUT_VASY = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
MBK_CATAL_NAME=CATAL_ASIMUT_VASY; export MBK_CATAL_NAME;\
MBK_IN_LO=vst; export MBK_IN_LO;\
MBK_OUT_LO=vst; export MBK_OUT_LO
ENV_ASIMUT_SYNTH = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME;\
MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
MBK_IN_LO=vst; export MBK_IN_LO;\
MBK_OUT_LO=vst; export MBK_OUT_LO
ENV_OCP = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
MBK_IN_LO=vst; export MBK_IN_LO; \
MBK_OUT_LO=vst; export MBK_OUT_LO; \
MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
MBK_IN_PH=ap; export MBK_IN_PH; \
MBK_OUT_PH=ap; export MBK_OUT_PH; \
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
ENV_OCR = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
MBK_IN_LO=vst; export MBK_IN_LO; \
MBK_OUT_LO=vst; export MBK_OUT_LO; \
MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
MBK_IN_PH=ap; export MBK_IN_PH; \
MBK_OUT_PH=ap; export MBK_OUT_PH; \
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
ENV_COUGAR_SPI = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
MBK_IN_LO=spi; export MBK_IN_LO; \
MBK_OUT_LO=spi; export MBK_OUT_LO; \
MBK_SPI_NAMEDNODES="true"; export MBK_SPI_NAMEDNODES; \
MBK_SPI_MODEL=$(SPI_MODEL); export MBK_SPI_MODEL; \
RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME; \
RDS_IN=cif; export RDS_IN; \
RDS_OUT=cif; export RDS_OUT; \
MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
MBK_IN_PH=ap; export MBK_IN_PH; \
MBK_OUT_PH=ap; export MBK_OUT_PH; \
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
ENV_COUGAR = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
MBK_IN_LO=al; export MBK_IN_LO; \
MBK_OUT_LO=al; export MBK_OUT_LO; \
RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME; \
RDS_IN=cif; export RDS_IN; \
RDS_OUT=cif; export RDS_OUT; \
MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
MBK_IN_PH=ap; export MBK_IN_PH; \
MBK_OUT_PH=ap; export MBK_OUT_PH; \
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
ENV_LVX = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
MBK_IN_LO=vst; export MBK_IN_LO; \
MBK_OUT_LO=vst; export MBK_OUT_LO; \
MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
ENV_DRUC = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
RDS_TECHNO_NAME=$(RDS_TECHNO_SYMB); export RDS_TECHNO_NAME; \
MBK_IN_PH=ap; export MBK_IN_PH; \
MBK_OUT_PH=ap; export MBK_OUT_PH; \
MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
ENV_S2R = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME; \
RDS_IN=cif; export RDS_IN; \
RDS_OUT=cif; export RDS_OUT; \
MBK_IN_PH=ap; export MBK_IN_PH; \
MBK_OUT_PH=ap; export MBK_OUT_PH; \
MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
all : divcas4_er.al
# /*------------------------------------------------------------\
# | |
# | Vasy |
# | |
# \------------------------------------------------------------*/
divcas4.vst cas.vbe divcas4_model.vbe : divcas4.vhdl
$(ENV_VASY); $(VASY) -a -B -o -p -I vhdl -H divcas4
# /*------------------------------------------------------------\
# | |
# | Asimut |
# | |
# \------------------------------------------------------------*/
res_vasy_1.pat : divcas4.vst cas.vbe divcas4_model.vbe
$(ENV_ASIMUT_VASY); $(ASIMUT) divcas4 divcas4 res_vasy_1
res_synth_1.pat : divcas4.vst cas.vst divcas4_model.vst
$(ENV_ASIMUT_SYNTH); $(ASIMUT) divcas4 divcas4 res_synth_1
# /*------------------------------------------------------------\
# | |
# | Boom |
# | |
# \------------------------------------------------------------*/
boom.done : cas_o.vbe divcas4_model_o.vbe
@$(TOUCH) boom.done
cas_o.vbe : cas.vbe res_vasy_1.pat
$(ENV_BOOM); $(BOOM) -VP cas cas_o
divcas4_model_o.vbe : divcas4_model.vbe res_vasy_1.pat
$(ENV_BOOM); $(BOOM) -VP divcas4_model divcas4_model_o
# /*------------------------------------------------------------\
# | |
# | Boog |
# | |
# \------------------------------------------------------------*/
boog.done : cas_o.vst divcas4_model_o.vst
@$(TOUCH) boog.done
cas_o.vst : cas_o.vbe
$(ENV_BOOG); $(BOOG) cas_o
divcas4_model_o.vst : divcas4_model_o.vbe
$(ENV_BOOG); $(BOOG) divcas4_model_o
# /*------------------------------------------------------------\
# | |
# | Loon |
# | |
# \------------------------------------------------------------*/
loon.done : cas.vst divcas4_model.vst
@$(TOUCH) loon.done
cas.vst : cas_o.vst
$(ENV_LOON); $(LOON) cas_o cas
divcas4_model.vst : divcas4_model_o.vst
$(ENV_LOON); $(LOON) divcas4_model_o divcas4_model
# /*------------------------------------------------------------\
# | |
# | OCP |
# | |
# \------------------------------------------------------------*/
divcas4_p.ap : res_synth_1.pat
$(ENV_OCP); $(OCP) -v -ioc divcas4 -gnuplot divcas4 divcas4_p
# /*------------------------------------------------------------\
# | |
# | OCR |
# | |
# \------------------------------------------------------------*/
divcas4.ap : divcas4_p.ap divcas4.vst
$(ENV_OCR); $(OCR) -v -l $(METAL_LEVEL) -L divcas4 -P divcas4_p -O divcas4
#
# /*------------------------------------------------------------\
# | |
# | NERO |
# | |
# \------------------------------------------------------------*/
divcas4_nero.ap : divcas4_p.ap divcas4.vst
$(ENV_OCR); $(NERO) -V -$(METAL_LEVEL) -p divcas4_p divcas4 divcas4
# /*------------------------------------------------------------\
# | |
# | Cougar |
# | |
# \------------------------------------------------------------*/
divcas4_e.al : divcas4.ap
$(ENV_COUGAR); $(COUGAR) -v -ac divcas4 divcas4_e
divcas4_et.al : divcas4.ap
$(ENV_COUGAR); $(COUGAR) -v -t -ac divcas4 divcas4_et
divcas4_e.spi : divcas4.ap divcas4_e.al
$(ENV_COUGAR_SPI); $(COUGAR) -v -ac divcas4 divcas4_e
divcas4_et.spi : divcas4.ap divcas4_e.al
$(ENV_COUGAR_SPI); $(COUGAR) -v -t -ac divcas4 divcas4_et
divcas4_er.al : divcas4.cif
$(ENV_COUGAR); $(COUGAR) -v -r -t divcas4 divcas4_er
# /*------------------------------------------------------------\
# | |
# | Lvx |
# | |
# \------------------------------------------------------------*/
lvx.done : divcas4.vst divcas4_e.al
$(ENV_LVX); $(LVX) vst al divcas4 divcas4_e -f
$(TOUCH) lvx.done
# /*------------------------------------------------------------\
# | |
# | Druc |
# | |
# \------------------------------------------------------------*/
druc.done : lvx.done divcas4.ap
$(ENV_DRUC); $(DRUC) divcas4
$(TOUCH) druc.done
# /*------------------------------------------------------------\
# | |
# | S2R |
# | |
# \------------------------------------------------------------*/
divcas4.cif : druc.done
$(ENV_S2R); $(S2R) -v -t divcas4
# /*------------------------------------------------------------\
# | |
# | TOOLS |
# | |
# \------------------------------------------------------------*/
graal: divcas4.ap
$(ENV_S2R); $(GRAAL) -l divcas4
xsch: divcas4.vst
$(ENV_LOON); $(XSCH) -l divcas4
xscht: divcas4_et.al
$(ENV_COUGAR); $(XSCH) -l divcas4_et
xpat: res_synth_1.pat
$(ENV_ASIMUT_SYNTH); $(XPAT) -l res_synth_1
dreal: divcas4.cif
$(ENV_S2R); $(DREAL) -l divcas4
# /*------------------------------------------------------------\
# | |
# | Clean |
# | |
# \------------------------------------------------------------*/
realclean : clean
clean :
$(RM) -f *.vst *.vbe *.boom *.done *.xsc *.al *.ap *.gpl *.gds \
*.log *.drc *.cif *.fin *.dat *.out divcas4_e.spi res_synth_1.pat \
res_vasy_1.pat

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# /*------------------------------------------------------------\
# | |
# | File : README |
# | |
# | Author : Jacomme Ludovic |
# | |
# \------------------------------------------------------------*/
This directory contains the VHDL description of an 4 bits divisor and
the associated stimuli file, and also a configuration file for IO
placement (used during the Place and Route step).
The Makefile set environement variables properly and run Alliance tools,
following each step of the design flow from VHDL up to real layout in a
pseudo 0.35 techno.
The environement variable ALLIANCE_TOP as to be set.

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alliance/src/documentation/alliance-examples/divcas4/cas.lax Normal file
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##
## Generated by VASY
##

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alliance/src/documentation/alliance-examples/divcas4/cas.vhdl Normal file
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library IEEE;
use IEEE.std_logic_1164.all;
entity cas is -- Controlled Add/Subtract cell
port (
divisor : in std_logic;
T : in std_logic;
remainder_in : in std_logic;
cin : in std_logic;
remainder_out : out std_logic;
cout : out std_logic);
end cas;
architecture circuits of cas is
signal tt : std_logic;
begin
tt <= T xor divisor;
remainder_out <= tt xor remainder_in xor cin;
cout <= (tt and remainder_in) or (tt and cin) or
(remainder_in and cin);
end circuits;

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alliance/src/documentation/alliance-examples/divcas4/divcas4.ioc Normal file
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# Copyright (c) 1997 by Cadence. All rights reserved.
###################################################################
# In each of TOP()/BOTTOM()/LEFT()/RIGHT() section, there are #
# placed IOs. In the IGNORE() section, the IOs are ignored #
# by the IOPlacer. In every section, the IO syntax could be: #
# for pin: (IOPIN iopinName.0 ); #
# for pad: iopadName orientation ; #
# for space: SPACE value; #
# The capital words are keywords. orientation is not required. #
# The value is the space between the IO above and the IO below it.#
###################################################################
TOP ( # IOs are ordered from left to right
(IOPIN dividend(6).0 );
(IOPIN dividend(5).0 );
(IOPIN dividend(4).0 );
(IOPIN dividend(3).0 );
(IOPIN dividend(2).0 );
(IOPIN dividend(1).0 );
(IOPIN dividend(0).0 );
(IOPIN divisor(3).0 );
(IOPIN divisor(2).0 );
(IOPIN divisor(1).0 );
(IOPIN divisor(0).0 );
)
BOTTOM ( # IOs are ordered from left to right
(IOPIN remainder(3).0 );
(IOPIN remainder(2).0 );
(IOPIN remainder(1).0 );
(IOPIN remainder(0).0 );
(IOPIN quotient(3).0 );
(IOPIN quotient(2).0 );
(IOPIN quotient(1).0 );
(IOPIN quotient(0).0 );
)
IGNORE ( # IOs are ignored(not placed) by IO Placer
)

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in dividend (6 downto 0) X;;;
in divisor (3 downto 0) X;;;
out quotient (3 downto 0) X;;;
out remainder (3 downto 0) X;;;
in vss B;;
in vdd B;;
begin
-- Pattern description :
-- d d q r V V
-- i i u e V V
-- v v o m V V
-- i i t a V V
-- d s i i V V
< +10ns>: 12 3 ?* ?* 0 1;
< +10ns>: 12 3 ?* ?* 0 1;
< +10ns>: 17 3 ?* ?* 0 1;
< +10ns>: 17 3 ?* ?* 0 1;
end;

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alliance/src/documentation/alliance-examples/divcas4/divcas4.vhdl Normal file
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library IEEE;
use IEEE.std_logic_1164.all;
entity divcas4 is -- 8 bit dividend, 4 bit divisor
port (
dividend : in std_logic_vector(6 downto 0);
divisor : in std_logic_vector(3 downto 0);
quotient : out std_logic_vector(3 downto 0);
remainder : out std_logic_vector(3 downto 0));
end divcas4;
use IEEE.std_logic_textio.all;
use STD.textio.all;
architecture circuits of divcas4 is
component cas
port (
divisor : in std_logic;
T : in std_logic;
remainder_in : in std_logic;
cin : in std_logic;
remainder_out : out std_logic;
cout : out std_logic);
end component;
signal T : std_logic_vector(3 downto 0);
signal c36, c35, c34, c33, c25, c24, c23, c22 : std_logic;
signal c14, c13, c12, c11, c03, c02, c01, c00 : std_logic;
signal r36, r35, r34, r33, r25, r24, r23, r22 : std_logic;
signal r14, r13, r12, r11, r03, r02, r01, r00 : std_logic;
begin
T(3) <= '1';
cas36: cas port map(
divisor(3), T(3), dividend(6), c35, r36, c36);
cas35: cas port map(
divisor(2), T(3), dividend(5), c34, r35, c35);
cas34: cas port map(
divisor(1), T(3), dividend(4), c33, r34, c34);
cas33: cas port map(
divisor(0), T(3), dividend(3), T(3), r33, c33);
T(2) <= not r36;
cas25: cas port map(
divisor(3), T(2), r35 , c24, r25, c25);
cas24: cas port map(
divisor(2), T(2), r34 , c23, r24, c24);
cas23: cas port map(
divisor(1), T(2), r33 , c22, r23, c23);
cas22: cas port map(
divisor(0), T(2), dividend(2), T(2), r22, c22);
T(1) <= not r25;
cas14: cas port map(
divisor(3), T(1), r24 , c13, r14, c14);
cas13: cas port map(
divisor(2), T(1), r23 , c12, r13, c13);
cas12: cas port map(
divisor(1), T(1), r22 , c11, r12, c12);
cas11: cas port map(
divisor(0), T(1), dividend(1), T(1), r11, c11);
T(0) <= not r14;
cas03: cas port map( divisor(3), T(0), r13 , c02, r03, c03);
cas02: cas port map( divisor(2), T(0), r12 , c01, r02, c02);
cas01: cas port map( divisor(1), T(0), r11 , c00, r01, c01);
cas00: cas port map( divisor(0), T(0), dividend(0), T(0), r00, c00);
quotient(3) <= T(2);
quotient(2) <= T(1);
quotient(1) <= T(0);
quotient(0) <= not r03;
remainder(3) <= r03;
remainder(2) <= r02;
remainder(1) <= r01;
remainder(0) <= r00;
end circuits;

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alliance/src/documentation/alliance-examples/divcas4/divcas4_model.lax Normal file
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##
## Generated by VASY
##