diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/CATAL b/alliance/src/documentation/alliance-examples/mipsR3000/asm/CATAL new file mode 100644 index 00000000..68c75b34 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/CATAL @@ -0,0 +1,9 @@ +mips_dec C +mips_seqo C +mips_sts C +timer C +rome C +romr C +romu C +roms C +sr64_1a C diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/CATAL_VBE b/alliance/src/documentation/alliance-examples/mipsR3000/asm/CATAL_VBE new file mode 100644 index 00000000..b44e160a --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/CATAL_VBE @@ -0,0 +1,10 @@ +mips_dec C +mips_seqo C +mips_sts C +mips_dpt C +timer C +rome C +romr C +romu C +roms C +sr64_1a C diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/CATAL_VBE_DPT b/alliance/src/documentation/alliance-examples/mipsR3000/asm/CATAL_VBE_DPT new file mode 100644 index 00000000..68c75b34 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/CATAL_VBE_DPT @@ -0,0 +1,9 @@ +mips_dec C +mips_seqo C +mips_sts C +timer C +rome C +romr C +romu C +roms C +sr64_1a C diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/CATAL_VST_FSM b/alliance/src/documentation/alliance-examples/mipsR3000/asm/CATAL_VST_FSM new file mode 100644 index 00000000..d13045fc --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/CATAL_VST_FSM @@ -0,0 +1,9 @@ +mips_dec C +mips_sts C +mips_dpt C +timer C +rome C +romr C +romu C +roms C +sr64_1a C diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/CATAL_VST_FSM_STS b/alliance/src/documentation/alliance-examples/mipsR3000/asm/CATAL_VST_FSM_STS new file mode 100644 index 00000000..ed9ba63b --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/CATAL_VST_FSM_STS @@ -0,0 +1,8 @@ +mips_dec C +mips_dpt C +timer C +rome C +romr C +romu C +roms C +sr64_1a C diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/CATAL_VST_FSM_STS_DPT b/alliance/src/documentation/alliance-examples/mipsR3000/asm/CATAL_VST_FSM_STS_DPT new file mode 100644 index 00000000..325a138a --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/CATAL_VST_FSM_STS_DPT @@ -0,0 +1,7 @@ +mips_dec C +timer C +rome C +romr C +romu C +roms C +sr64_1a C diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/CATAL_VST_STS b/alliance/src/documentation/alliance-examples/mipsR3000/asm/CATAL_VST_STS new file mode 100644 index 00000000..04daf90f --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/CATAL_VST_STS @@ -0,0 +1,9 @@ +mips_dec C +mips_seqo C +mips_dpt C +timer C +rome C +romr C +romu C +roms C +sr64_1a C diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/Makefile_alu b/alliance/src/documentation/alliance-examples/mipsR3000/asm/Makefile_alu new file mode 100644 index 00000000..47d7ad3e --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/Makefile_alu @@ -0,0 +1,290 @@ +# Pierre Nguyen Tuong +# 19 octobre 1999 +# Makefile pour l'automate ; verification de l'alu +# +# Derniere modification : 19 octobre 1999 +# Version : 1.0 +# + + +tests : alu + +alu : add0 add1 add2 add3 add4 add5 addu0 addu1 addu2 addu3 \ + and0 and1 lhi0 lhi1 nor0 or0 or1 or2 reg0 sle0 \ + sle1 sle2 sle3 sle4 sle5 sle6 sle7 sll0 sll1 sra0 \ + sra1 srl0 srl1 sub0 sub1 xor0 xor1 xor2 + + +add0 : + @echo "**********************************************************************" >> res_test ; \ + ./go-bench.sh add000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de add et de addi" ; \ + echo "Test de add et de addi" >> res_test + +add1 : + @./go-bench.sh add001 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de add et de addi (bis)" ; \ + echo "Test de add et de addi (bis)" >> res_test + + +add2 : + @./go-bench.sh add002 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de add et de addi (bis bis)" ; \ + echo "Test de add et de addi (bis bis)" >> res_test + +add3 : + @./go-bench.sh add003 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de add et de addi bis bis bis" ; \ + echo "Test de add et de addi bis bis bis" >> res_test + +add4 : + @./go-bench.sh add004 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de sub, loadi, addi" ; \ + echo "Test de sub, loadi, addi" >> res_test + +add5 : + @./go-bench.sh add005 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de addi, initialisation des registres avec leurs propres numeros" ; \ + echo "Test de addi, initialisation des registres avec leurs propres numeros" >> res_test + +addu0 : + @./go-bench.sh addu000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de addui " ; \ + echo "Test de addui " >> res_test + +addu1 : + @./go-bench.sh addu001 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de addui " ; \ + echo "Test de addui " >> res_test + +addu2 : + @./go-bench.sh addu002 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de addui, addu" ; \ + echo "Test de addui, addu" >> res_test + +addu3 : + @./go-bench.sh addu003 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de addui, addu" ; \ + echo "Test de addui, addu" >> res_test + +and0 : + @./go-bench.sh and000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de addui, seqi, and " ; \ + echo "Test de addui, seqi, and " >> res_test + +and1 : + @./go-bench.sh and001 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de addui, loadi, andi " ; \ + echo "Test de addui, loadi, andi " >> res_test + +lhi0 : + @./go-bench.sh lhi000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de addui, lui, sll" ; \ + echo "Test de addui, lui, sll" >> res_test + + +lhi1 : + @./go-bench.sh lhi001 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de addui, lui, sll " ; \ + echo "Test de addui, lui, sll " >> res_test + + +nor0 : + @./go-bench.sh nor000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de loadi, nor " ; \ + echo "Test de loadi, nor " >> res_test + +or0 : + @./go-bench.sh or000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de loadi, or " ; \ + echo "Test de loadi, or " >> res_test + + +or1 : + @./go-bench.sh or001 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de loadi, or " ; \ + echo "Test de loadi, or " >> res_test + + +or2 : + @./go-bench.sh or002 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de loadi, ori, addui " ; \ + echo "Test de loadi, ori, addui " >> res_test + + + +reg0 : + @./go-bench.sh or002 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de l'addition signee" ; \ + echo "Test de l'addition signee" >> res_test + +sle0: + @./go-bench.sh sle000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de slt " ; \ + echo "Test de slt " >> res_test + +sle1: + @./go-bench.sh sle000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de slt bis" ; \ + echo "Test de slt bis" >> res_test + +sle2: + @./go-bench.sh sle000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de loadi, addui, slt " ; \ + echo "Test de loadi, addui, slt " >> res_test + +sle3: + @./go-bench.sh sle000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de loadi, addui, slti " ; \ + echo "Test de loadi, addui, slti " >> res_test + +sle4: + @./go-bench.sh sle000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de loadi, addui, slt " ; \ + echo "Test de loadi, addui, slt " >> res_test + +sle5: + @./go-bench.sh sle000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de loadi, addui, slti " ; \ + echo "Test de loadi, addui, slti " >> res_test + +sle6: + @./go-bench.sh sle000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de loadi, addui, sltu " ; \ + echo "Test de loadi, addui, sltu " >> res_test + +sle7: + @./go-bench.sh sle000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de loadi, addui, sltu" ; \ + echo "Test de loadi, addui, sltu" >> res_test + +sll0: + @./go-bench.sh sll000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de addui, sllv " ; \ + echo "Test de addui, sllv " >> res_test + +sll1: + @./go-bench.sh sll001 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de addui, loadi,sll " ; \ + echo "Test de addui, loadi,sll " >> res_test + +sra0: + @./go-bench.sh sra000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de addui, srav " ; \ + echo "Test de addui, srav " >> res_test + +sra1: + @./go-bench.sh sra001 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de addui, sra " ; \ + echo "Test de addui, sra " >> res_test + +srl0: + @./go-bench.sh srl000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de addui, srlv" ; \ + echo "Test de addui, srlv" >> res_test + +srl1: + @./go-bench.sh srl001 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de addui, srl " ; \ + echo "Test de addui, srl " >> res_test + +sub0: + @./go-bench.sh sub000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de addi, sub " ; \ + echo "Test de addi, sub " >> res_test + +sub1: + @./go-bench.sh sub001 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de loadi, subu " ; \ + echo "Test de loadi, subu " >> res_test + +xor0: + @./go-bench.sh xor000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de loadi, xor " ; \ + echo "Test de loadi, xor " >> res_test + +xor1: + @./go-bench.sh xor001 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de loadi, xor " ; \ + echo "Test de loadi, xor " >> res_test + +xor2: + @./go-bench.sh xor002 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de slti, xori " ; \ + echo "Test de slti, xori " >> res_test diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/Makefile_bm b/alliance/src/documentation/alliance-examples/mipsR3000/asm/Makefile_bm new file mode 100644 index 00000000..f2bdeaab --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/Makefile_bm @@ -0,0 +1,391 @@ +# Pierre Nguyen Tuong +# 19 octobre 1999 +# Makefile pour l'automate +# +# Derniere modification : 19 octobre 1999 +# Version : 1.0 +# + + +tests : bm + + +bm : beq0 beq1 bgez0 bgez1 bgezal bgtz blez bltz bltzal bne0 bne1 \ + lhi0 lhi1 jal0 jal1 jalr0 jalr1 lsb0 lsb1 lsb2 lsb3 lsb4 lsb5 lsb6 lsb7 \ + lsbu0 lsbu1 lsbu2 lsbu3 lsh0 lsh1 lsh2 lsh3 lshu0 lshu1 lsw0 lsw1 sltu0 \ + sltu1 sltu2 sltu3 sltu4 sltiu0 sltiu1 sltiu2 sltiu3 sltiu4 + + +beq0 : + @echo "**************************************************************************" >> res_test ; \ + ./go-bench.sh beq000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de beq 0" >> res_test ; \ + echo "Test de beq 0" + +beq1 : + @./go-bench.sh beq001 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de beq 1" >> res_test ; \ + echo "Test de beq 1" + +bgez0 : + @./go-bench.sh bgez000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de bgez0" >> res_test ; \ + echo "Test de bgez0" + + +bgez1 : + @./go-bench.sh bgez001 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de bgez1" >> res_test ; \ + echo "Test de bgez1" + + +bgezal : + @./go-bench.sh bgezal000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de bgezal" >> res_test ; \ + echo "Test de bgezal" + + +bgtz : + @./go-bench.sh bgtz000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de bgtz" >> res_test ; \ + echo "Test de bgtz" + +blez : + @./go-bench.sh blez000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de blez" >> res_test ; \ + echo "Test de blez" + + +bltz : + @./go-bench.sh bltz000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de bltz" >> res_test ; \ + echo "Test de bltz" + + +bltzal : + @./go-bench.sh bltzal000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de bltzal" >> res_test ; \ + echo "Test de bltzal" + + +bne0 : + @./go-bench.sh bne000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de bne0" >> res_test ; \ + echo "Test de bne0" + + +bne1 : + @./go-bench.sh bne001 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de bne1" >> res_test ; \ + echo "Test de bne1" + + +jal0 : + @./go-bench.sh jal000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de jal0" >> res_test ; \ + echo "Test de jal0" + + +jal1 : + @./go-bench.sh jal001 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de jal1" >> res_test ; \ + echo "Test de jal1" + + +jalr0 : + @./go-bench.sh jalr000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de jalr0" >> res_test ; \ + echo "Test de jalr0" + + +jalr1 : + @./go-bench.sh jalr001 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de jalr1" >> res_test ; \ + echo "Test de jalr1" + + +lhi0 : + @./go-bench.sh lhi000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de lhi0" >> res_test ; \ + echo "Test de lhi0" + + +lhi1 : + @./go-bench.sh lhi001 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de lhi1" >> res_test ; \ + echo "Test de lhi1" + + +lsb0 : + @./go-bench.sh lsb000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de lsb0" >> res_test ; \ + echo "Test de lsb0" + + +lsb1 : + @./go-bench.sh lsb001 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de lsb1" >> res_test ; \ + echo "Test de lsb1" + + +lsb2 : + @./go-bench.sh lsb002 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de lsb2" >> res_test ; \ + echo "Test de lsb2" + + +lsb3 : + @./go-bench.sh lsb003 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de lsb3" >> res_test ; \ + echo "Test de lsb3" + + +lsb4 : + @./go-bench.sh lsb004 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de lsb4" >> res_test ; \ + echo "Test de lsb4" + + +lsb5 : + @./go-bench.sh lsb005 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de lsb5" >> res_test ; \ + echo "Test de lsb5" + + +lsb6 : + @./go-bench.sh lsb006 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de lsb6" >> res_test ; \ + echo "Test de lsb6" + + +lsb7 : + @./go-bench.sh lsb007 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de lsb7" >> res_test ; \ + echo "Test de lsb7" + + +lsbu0 : + @./go-bench.sh lsbu000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de lsbu0" >> res_test ; \ + echo "Test de lsbu0" + + +lsbu1 : + @./go-bench.sh lsbu001 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de lsbu1" >> res_test ; \ + echo "Test de lsbu1" + + +lsbu2 : + @./go-bench.sh lsbu002 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de lsbu2" >> res_test ; \ + echo "Test de lsbu2" + + +lsbu3 : + @./go-bench.sh lsbu003 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de lsbu3" >> res_test ; \ + echo "Test de lsbu3" + + +lsh0 : + @./go-bench.sh lsh000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de lsh0" >> res_test ; \ + echo "Test de lsh0" + + +lsh1 : + @./go-bench.sh lsh001 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de lsh1 " >> res_test ; \ + echo "Test de lsh1" + + +lsh2 : + @./go-bench.sh lsh002 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de lsh2" >> res_test ; \ + echo "Test de lsh2" + + +lsh3 : + @./go-bench.sh lsh003 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de lsh3" >> res_test ; \ + echo "Test de lsh3" + + +lshu0 : + @./go-bench.sh lshu000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de lshu0" >> res_test ; \ + echo "Test de lshu0" + + +lshu1 : + @./go-bench.sh lshu001 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de lshu1" >> res_test ; \ + echo "Test de lshu1" + + +lsw0 : + @./go-bench.sh lsw000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de lsw0" >> res_test ; \ + echo "Test de lsw0" + + +lsw1 : + @./go-bench.sh lsw001 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de lsw1" >> res_test ; \ + echo "Test de lsw1" + + +sltu0 : + @./go-bench.sh sltu000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de sltu0" >> res_test ; \ + echo "Test de sltu0" + + +sltu1 : + @./go-bench.sh sltu001 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de sltu1" >> res_test ; \ + echo "Test de sltu1" + + + +sltu2 : + @./go-bench.sh sltu002 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de sltu2" >> res_test ; \ + echo "Test de sltu2" + + +sltu3 : + @./go-bench.sh sltu003 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de sltu3" >> res_test ; \ + echo "Test de sltu3" + + +sltu4 : + @./go-bench.sh sltu004 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de sltu4" >> res_test ; \ + echo "Test de sltu4" + + +sltiu0 : + @./go-bench.sh sltiu000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de sltiu0" >> res_test ; \ + echo "Test de sltiu0" + + +sltiu1 : + @./go-bench.sh sltiu001 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de sltiu1" >> res_test ; \ + echo "Test de sltiu1" + + +sltiu2 : + @./go-bench.sh sltiu002 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de sltiu2" >> res_test ; \ + echo "Test de sltiu2" + + +sltiu3 : + @./go-bench.sh sltiu003 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de sltiu3" >> res_test ; \ + echo "Test de sltiu3" + + +sltiu4 : + @./go-bench.sh sltiu004 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de sltiu4" >> res_test ; \ + echo "Test de sltiu4" diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/Makefile_excp b/alliance/src/documentation/alliance-examples/mipsR3000/asm/Makefile_excp new file mode 100644 index 00000000..704dcf21 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/Makefile_excp @@ -0,0 +1,318 @@ +# Pierre Nguyen Tuong +# 19 octobre 1999 +# Makefile pour l'automate ; verification des exceptions +# +# Derniere modification : 19 octobre 1999 +# Version : 1.0 +# + + +tests : excp + +excp : exc00 exc01 exc02 exc03 \ + exc04 exc05 exc06 exc07 \ + exc08 exc09 exc10 exc11 \ + exc12 exc13 exc14 exc15 \ + exc16 exc17 exc18 exc19 \ + exc20 exc21 exc22 exc23 \ + exc24 + + +exc00 : + @echo "**************************************************************************" >> res_test ; \ + cp exc000.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp exc000.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh exc000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de mauvais alignement de data " >> res_test ; \ + echo "Test de mauvais alignement de data " + +exc01: + @cp exc001.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp exc001.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh exc001 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de ADES" >> res_test ; \ + echo "Test de ADES" + + +exc02: + @cp exc002.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp exc002.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh exc002 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test d'OVERFLOW de sum de nb >0" >> res_test ; \ + echo "Test d'OVERFLOW de sum de nb >0" + + +exc03: + @cp exc003.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp exc003.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh exc003 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test d'OVERFLOW de sum de nb >0" >> res_test ; \ + echo "Test d'OVERFLOW de sum de nb >0" + + +exc04: + @cp exc004.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp exc004.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh exc004 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test d'OVERFLOW de sum de nb >0" >> res_test ; \ + echo "Test d'OVERFLOW de sum de nb >0" + + +exc05: + @cp exc005.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp exc005.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh exc005 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test d'OVERFLOW de sum de nb >0" >> res_test ; \ + echo "Test d'OVERFLOW de sum de nb >0" + + +exc06: + @cp exc006.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp exc006.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh exc006 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo " illegal instruction address" >> res_test ; \ + echo " illegal instruction address" + + +exc07: + @cp exc007.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp exc007.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh exc007 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo " Test de ADEL" >> res_test ; \ + echo " Test de ADEL" + + +exc08: + @cp exc008.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp exc008.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh exc008 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo " Test de ADEL" >> res_test ; \ + echo " Test de ADEL" + + +exc09: + @cp exc009.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp exc009.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh exc009 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo " ri (when executing a mfc0)" >> res_test ; \ + echo " ri (when executing a mfc0)" + + +exc10: + @cp exc010.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp exc010.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh exc010 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo " ri" >> res_test ; \ + echo " ri" + + +exc11: + @cp exc011.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp exc012.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh exc011 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "adel (when loading a half-word) " >> res_test ; \ + echo "adel (when loading a half-word) " + + +exc12: + @cp exc012.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp exc012.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh exc012 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "ades (when storing a word) " >> res_test ; \ + echo "ades (when storing a word) " + + +exc13: + @cp exc013.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp exc013.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh exc013 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "sleep" >> res_test ; \ + echo "sleep" + + +exc14: + @cp exc014.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp exc014.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh exc014 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo " data bus error" >> res_test ; \ + echo " data bus error" + + +exc15: + @cp exc015.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp exc015.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh exc015 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo " overflow (when adding positive numbers)" >> res_test ; \ + echo " overflow (when adding positive numbers)" + + +exc16: + @cp exc016.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp exc016.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh exc016 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo " overflow (when adding positive numbers)" >> res_test ; \ + echo " overflow (when adding positive numbers)" + + +exc17: + @cp exc017.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp exc017.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh exc017 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "data bus error" >> res_test ; \ + echo "data bus error" + + +exc18: + @cp exc018.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp exc018.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh exc018 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "data bus error" >> res_test ; \ + echo "data bus error" + + +exc19: + @cp exc019.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp exc019.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh exc019 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "data bus error" >> res_test ; \ + echo "data bus error" + + +exc20: + @cp exc020.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp exc020.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh exc020 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "data bus error" >> res_test ; \ + echo "data bus error" + + +exc21: + @cp exc021.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp exc021.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh exc021 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "data bus error" >> res_test ; \ + echo "data bus error" + + +exc22: + @cp exc022.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp exc022.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh exc022 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "data bus error" >> res_test ; \ + echo "data bus error" + + +exc23: + @cp exc023.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp exc023.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh exc023 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "data bus error" >> res_test ; \ + echo "data bus error" + + +exc24: + @cp exc024.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp exc024.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh exc024 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "instruction bus error" >> res_test ; \ + echo "instruction bus error" diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/Makefile_int b/alliance/src/documentation/alliance-examples/mipsR3000/asm/Makefile_int new file mode 100644 index 00000000..e6370b57 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/Makefile_int @@ -0,0 +1,100 @@ +# Pierre Nguyen Tuong +# 19 octobre 1999 +# Makefile pour l'automate ; verification des interruptions +# +# Derniere modification : 19 octobre 1999 +# Version : 1.0 +# + +tests : int + +int : it00 it01 it02 it03 \ + it04 it05 it06 + +it00: + @echo "**************************************************************************" >> res_test ; \ + cp it000.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp it000.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh it000 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "test int 00" >> res_test ; \ + echo "test int 00" + + +it01: + @cp it001.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp it001.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh it001 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test int 01" >> res_test ; \ + echo "Test int 01" + + +it02: + @cp it002.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp it002.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh it002 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de int 02" >> res_test ; \ + echo "Test de int 02" + + +it03: + @cp it003.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp it003.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh it003 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de int 03" >> res_test ; \ + echo "Test de int 03" + + +it04: + @cp it004.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp it004.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh it004 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de int 04" >> res_test ; \ + echo "Test de int 04" + + + +it05: + @cp it005.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp it005.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh it005 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "Test de int 05" >> res_test ; \ + echo "Test de int 05" + + + +it06: + @cp it006.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp it006.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh it006 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "test int 06" >> res_test ; \ + echo "test int 06" + + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/Makefile_misc b/alliance/src/documentation/alliance-examples/mipsR3000/asm/Makefile_misc new file mode 100644 index 00000000..f7b0e682 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/Makefile_misc @@ -0,0 +1,75 @@ +# Pierre Nguyen Tuong +# 19 octobre 1999 +# Makefile pour l'automate ; verification des misc +# +# Derniere modification : 19 octobre 1999 +# Version : 1.0 +# + +tests : misc + +misc : brk mftc0 mfthi mftlo syscall + +brk: + @echo "**************************************************************************" >> res_test ; \ + cp break_00.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp break_00.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh break_00 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "test de break" >> res_test ; \ + echo "test de break" + + + +mftc0: + @cp mftc0_00.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp mftc0_00.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh mftc0_00 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "test de mftc0" >> res_test ; \ + echo "test de mftc0" + + +mfthi: + @cp mfthi_00.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp mfthi_00.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh mfthi_00 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "test de mfthi" >> res_test ; \ + echo "test de mfthi" + + + +mftlo: + @cp mftlo_00.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp mftlo_00.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh mftlo_00 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "test de mftlo" >> res_test ; \ + echo "test de mftlo" + + + +syscall: + @cp syscall_00.e rome.e ; \ + mips_asm rome.e rome toto > /dev/null ; \ + cp syscall_00.u rome.u ; \ + mips_asm rome.u romu toto > /dev/null ; \ + ./go-bench.sh syscall_00 > tmp_test ; \ + cat tmp_test ; \ + cat tmp_test >> res_test ; \ + echo "test de syscall" >> res_test ; \ + echo "test de syscall" + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/add000.pat b/alliance/src/documentation/alliance-examples/mipsR3000/asm/add000.pat new file mode 100644 index 00000000..037d8f25 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/add000.pat @@ -0,0 +1,363 @@ + +-- description generated by Pat driver + +-- date : Mon May 24 00:00:10 2004 +-- revision : v109 + +-- sequence : mips_cpu + +-- input / output list : +in ck B;; +in reset B;; +in frz B;; +in scin B;; +in test B;; +in vdd B;; +in vss B;; +out rw B;; +out w (0 to 1) B;; +out scout B;; +inout data (31 downto 0) X;; +inout data_adr (31 downto 0) X;; +signal mips1.adr_c (31 downto 0) X spy ;; +signal mips1.datain_c (31 downto 0) X spy ;; +signal mips1.dataout_c (31 downto 0) X spy ;; +signal mips1.int_c (5 downto 0) B spy ;; +signal mips1.scin_c B spy ;; +signal mips1.scout_c B spy ;; +signal mips1.test_c B spy ;; +signal mips1.reset_c B spy ;; +signal mips1.frz_c B spy ;; +signal mips1.w_c (0 to 1) B spy ;; +signal mips1.rw_c B spy ;; +signal mips1.berr_c B spy ;; +signal mips1.rw_ctl_c (15 downto 0) B spy ;; +signal mips1.frz_ctl_c (15 downto 0) B spy ;; +signal mips1.ck_ctl_c B spy ;; +signal mips1.ck_dpt_c B spy ;; + +begin + +-- Pattern description : + +-- c r f s t v v r w s d d m m m m m m m m m m m m m m m m +-- k e r c e d s w c a a i i i i i i i i i i i i i i i i +-- s z i s d s o t t p p p p p p p p p p p p p p p p +-- e n t u a a s s s s s s s s s s s s s s s s +-- t t _ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 +-- a . . . . . . . . . . . . . . . . +-- d a d d i s s t r f w r b r f c c +-- r d a a n c c e e r _ w e w r k k +-- r t t t i o s s z c _ r _ z _ _ +-- _ a a _ n u t e _ c r c _ c d +-- c i o c _ t _ t c _ t c t p +-- n u c _ c _ c l t l t +-- _ t c c _ l _ _ +-- c _ c _ c c +-- c c + +< 0 ps> : 1 1 0 0 0 1 0 ?1 ?00 ?0 ?uuuuuuuu ?00000000 ?00000000 ?uuuuuuuu ?3fc00080 ?111111 ?0 ?0 ?0 ?1 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?1 ?1 ; +< 50000 ps> : 1 1 0 0 0 1 0 ?1 ?00 ?0 ?uuuuuuuu ?00000000 ?00000000 ?uuuuuuuu ?3fc00080 ?111111 ?0 ?0 ?0 ?1 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?1 ?1 ; +< 100000 ps> : 0 1 0 0 0 1 0 ?1 ?00 ?0 ?uuuuuuuu ?00000000 ?00000000 ?uuuuuuuu ?3fc00080 ?111111 ?0 ?0 ?0 ?1 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?0 ?0 ; +< 150000 ps> : 0 1 0 0 0 1 0 ?1 ?00 ?0 ?uuuuuuuu ?00000000 ?00000000 ?uuuuuuuu ?3fc00080 ?111111 ?0 ?0 ?0 ?1 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?0 ?0 ; +< 200000 ps> : 1 1 0 0 0 1 0 ?1 ?00 ?0 ?uuuuuuuu ?00000000 ?00000000 ?uuuuuuuu ?bfc00000 ?111111 ?0 ?0 ?0 ?1 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?1 ?1 ; +< 250000 ps> : 1 1 0 0 0 1 0 ?1 ?00 ?0 ?uuuuuuuu ?00000000 ?00000000 ?uuuuuuuu ?bfc00000 ?111111 ?0 ?0 ?0 ?1 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?1 ?1 ; +< 300000 ps> : 0 1 0 0 0 1 0 ?1 ?00 ?0 ?uuuuuuuu ?00000000 ?00000000 ?uuuuuuuu ?bfc00000 ?111111 ?0 ?0 ?0 ?1 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?0 ?0 ; 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+< 10850000 ps> : 1 0 0 0 0 1 0 ?1 ?00 ?0 ?2005000c ?0040000c ?0040000c ?2005000c ?00400010 ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?1 ?1 ; +< 10900000 ps> : 0 0 0 0 0 1 0 ?1 ?00 ?0 ?2005000c ?0040000c ?0040000c ?2005000c ?00400010 ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?0 ?0 ; +< 10950000 ps> : 0 0 0 0 0 1 0 ?1 ?00 ?0 ?2005000c ?0040000c ?0040000c ?2005000c ?00400010 ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?0 ?0 ; +< 11000000 ps> : 1 0 0 0 0 1 0 ?1 ?00 ?0 ?10a3002f ?00400010 ?00400010 ?10a3002f ?0000000c ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?1 ?1 ; +< 11050000 ps> : 1 0 0 0 0 1 0 ?1 ?00 ?0 ?10a3002f ?00400010 ?00400010 ?10a3002f ?0000000c ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?1 ?1 ; +< 11100000 ps> : 0 0 0 0 0 1 0 ?1 ?00 ?0 ?10a3002f ?00400010 ?00400010 ?10a3002f ?0000000c ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?0 ?0 ; +< 11150000 ps> : 0 0 0 0 0 1 0 ?1 ?00 ?0 ?10a3002f ?00400010 ?00400010 ?10a3002f ?0000000c ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?0 ?0 ; +< 11200000 ps> : 1 0 0 0 0 1 0 ?1 ?00 ?0 ?10a3002f ?00400010 ?00400010 ?10a3002f ?0000000c ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?1 ?1 ; +< 11250000 ps> : 1 0 0 0 0 1 0 ?1 ?00 ?0 ?10a3002f ?00400010 ?00400010 ?10a3002f ?0000000c ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?1 ?1 ; +< 11300000 ps> : 0 0 0 0 0 1 0 ?1 ?00 ?0 ?10a3002f ?00400010 ?00400010 ?10a3002f ?0000000c ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?0 ?0 ; +< 11350000 ps> : 0 0 0 0 0 1 0 ?1 ?00 ?0 ?10a3002f ?00400010 ?00400010 ?10a3002f ?0000000c ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?0 ?0 ; +< 11400000 ps> : 1 0 0 0 0 1 0 ?1 ?00 ?0 ?10a3002f ?00400010 ?00400010 ?10a3002f ?0000000c ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?1 ?1 ; +< 11450000 ps> : 1 0 0 0 0 1 0 ?1 ?00 ?0 ?10a3002f ?00400010 ?00400010 ?10a3002f ?0000000c ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?1 ?1 ; +< 11500000 ps> : 0 0 0 0 0 1 0 ?1 ?00 ?0 ?10a3002f ?00400010 ?00400010 ?10a3002f ?0000000c ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?0 ?0 ; +< 11550000 ps> : 0 0 0 0 0 1 0 ?1 ?00 ?0 ?10a3002f ?00400010 ?00400010 ?10a3002f ?0000000c ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?0 ?0 ; +< 11600000 ps> : 1 0 0 0 0 1 0 ?1 ?00 ?0 ?10a3002f ?00400010 ?00400010 ?10a3002f ?00400014 ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?1 ?1 ; +< 11650000 ps> : 1 0 0 0 0 1 0 ?1 ?00 ?0 ?10a3002f ?00400010 ?00400010 ?10a3002f ?00400014 ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?1 ?1 ; +< 11700000 ps> : 0 0 0 0 0 1 0 ?1 ?00 ?0 ?10a3002f ?00400010 ?00400010 ?10a3002f ?00400014 ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?0 ?0 ; +< 11750000 ps> : 0 0 0 0 0 1 0 ?1 ?00 ?0 ?10a3002f ?00400010 ?00400010 ?10a3002f ?00400014 ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?0 ?0 ; +< 11800000 ps> : 1 0 0 0 0 1 0 ?1 ?00 ?0 ?08100036 ?00400014 ?00400014 ?08100036 ?0000000c ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?1 ?1 ; +< 11850000 ps> : 1 0 0 0 0 1 0 ?1 ?00 ?0 ?08100036 ?00400014 ?00400014 ?08100036 ?0000000c ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?1 ?1 ; +< 11900000 ps> : 0 0 0 0 0 1 0 ?1 ?00 ?0 ?08100036 ?00400014 ?00400014 ?08100036 ?0000000c ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?0 ?0 ; +< 11950000 ps> : 0 0 0 0 0 1 0 ?1 ?00 ?0 ?08100036 ?00400014 ?00400014 ?08100036 ?0000000c ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?0 ?0 ; +< 12000000 ps> : 1 0 0 0 0 1 0 ?1 ?00 ?0 ?08100036 ?00400014 ?00400014 ?08100036 ?00000000 ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?1 ?1 ; +< 12050000 ps> : 1 0 0 0 0 1 0 ?1 ?00 ?0 ?08100036 ?00400014 ?00400014 ?08100036 ?00000000 ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?1 ?1 ; +< 12100000 ps> : 0 0 0 0 0 1 0 ?1 ?00 ?0 ?08100036 ?00400014 ?00400014 ?08100036 ?00000000 ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?0 ?0 ; +< 12150000 ps> : 0 0 0 0 0 1 0 ?1 ?00 ?0 ?08100036 ?00400014 ?00400014 ?08100036 ?00000000 ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?0 ?0 ; +< 12200000 ps> : 1 0 0 0 0 1 0 ?1 ?00 ?0 ?08100036 ?00400014 ?00400014 ?08100036 ?004000d0 ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?1 ?1 ; +< 12250000 ps> : 1 0 0 0 0 1 0 ?1 ?00 ?0 ?08100036 ?00400014 ?00400014 ?08100036 ?004000d0 ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?1 ?1 ; +< 12300000 ps> : 0 0 0 0 0 1 0 ?1 ?00 ?0 ?08100036 ?00400014 ?00400014 ?08100036 ?004000d0 ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?0 ?0 ; +< 12350000 ps> : 0 0 0 0 0 1 0 ?1 ?00 ?0 ?08100036 ?00400014 ?00400014 ?08100036 ?004000d0 ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?0 ?0 ; +< 12400000 ps> : 1 0 0 0 0 1 0 ?1 ?00 ?0 ?08100034 ?004000d0 ?004000d0 ?08100034 ?00000000 ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?1 ?1 ; +< 12450000 ps> : 1 0 0 0 0 1 0 ?1 ?00 ?0 ?08100034 ?004000d0 ?004000d0 ?08100034 ?00000000 ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?1 ?1 ; +< 12500000 ps> : 0 0 0 0 0 1 0 ?1 ?00 ?0 ?08100034 ?004000d0 ?004000d0 ?08100034 ?00000000 ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?0 ?0 ; +< 12550000 ps> : 0 0 0 0 0 1 0 ?1 ?00 ?0 ?08100034 ?004000d0 ?004000d0 ?08100034 ?00000000 ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?0 ?0 ; +< 12600000 ps> : 1 0 0 0 0 1 0 ?1 ?00 ?0 ?08100034 ?004000d0 ?004000d0 ?08100034 ?004000d4 ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?1 ?1 ; +< 12650000 ps> : 1 0 0 0 0 1 0 ?1 ?00 ?0 ?08100034 ?004000d0 ?004000d0 ?08100034 ?004000d4 ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?1 ?1 ; +< 12700000 ps> : 0 0 0 0 0 1 0 ?1 ?00 ?0 ?08100034 ?004000d0 ?004000d0 ?08100034 ?004000d4 ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?0 ?0 ; +< 12750000 ps> : 0 0 0 0 0 1 0 ?1 ?00 ?0 ?08100034 ?004000d0 ?004000d0 ?08100034 ?004000d4 ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?0 ?0 ; +< 12800000 ps> : 1 0 0 0 0 1 0 ?1 ?00 ?0 ?00000021 ?004000d4 ?004000d4 ?00000021 ?004000d0 ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?1 ?1 ; +< 12850000 ps> : 1 0 0 0 0 1 0 ?1 ?00 ?0 ?00000021 ?004000d4 ?004000d4 ?00000021 ?004000d0 ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?1 ?1 ; +< 12900000 ps> : 0 0 0 0 0 1 0 ?1 ?00 ?0 ?00000021 ?004000d4 ?004000d4 ?00000021 ?004000d0 ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?0 ?0 ; +< 12950000 ps> : 0 0 0 0 0 1 0 ?1 ?00 ?0 ?00000021 ?004000d4 ?004000d4 ?00000021 ?004000d0 ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?0 ?0 ; +< 13000000 ps> : 1 0 0 0 0 1 0 ?1 ?00 ?0 ?08100034 ?004000d0 ?004000d0 ?08100034 ?00000000 ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?1 ?1 ; +< 13050000 ps> : 1 0 0 0 0 1 0 ?1 ?00 ?0 ?08100034 ?004000d0 ?004000d0 ?08100034 ?00000000 ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?1 ?1 ; +< 13100000 ps> : 0 0 0 0 0 1 0 ?1 ?00 ?0 ?08100034 ?004000d0 ?004000d0 ?08100034 ?00000000 ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?0 ?0 ; +< 13150000 ps> : 0 0 0 0 0 1 0 ?1 ?00 ?0 ?08100034 ?004000d0 ?004000d0 ?08100034 ?00000000 ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?0 ?0 ; +< 13200000 ps> : 1 0 0 0 0 1 0 ?1 ?00 ?0 ?08100034 ?004000d0 ?004000d0 ?08100034 ?004000d4 ?111111 ?0 ?0 ?0 ?0 ?0 ?00 ?1 ?1 ?0000000000000000 ?1111111111111111 ?1 ?1 ; + +-- Beware : unprocessed patterns + +< 13250000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; +< 13300000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; +< 13350000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; +< 13400000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; +< 13450000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; +< 13500000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; +< 13550000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; +< 13600000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; +< 13650000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; +< 13700000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; +< 13750000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; +< 13800000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; +< 13850000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; +< 13900000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; +< 13950000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; +< 14000000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; +< 14050000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; +< 14100000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; +< 14150000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; +< 14200000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; +< 14250000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; +< 14300000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; +< 14350000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; +< 14400000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; +< 14450000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; +< 14500000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; +< 14550000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; +< 14600000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; +< 14650000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; +< 14700000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; +< 14750000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; +< 14800000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; +< 14850000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; +< 14900000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; +< 14950000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ?******** ?******** ?******** ?****** ?* ?* ?* ?* ?* ?** ?* ?* ?**************** ?**************** ?* ?* ; + +end; diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/add000.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/add000.u new file mode 100644 index 00000000..39cc6db3 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/add000.u @@ -0,0 +1,35 @@ +; ###----------------------------------------------------------------### +; # file : add000.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # signed addition # + ; ###--------------------------------------------------------### + +val1 .equ 0x000a +val2 .equ 0x0002 + + .org 0x00400000 + .start init + +init: + + addi r1 , r0 , val1 + addi r2 , r0 , val2 + add r3 , r2 , r1 + + addi r5 , r0 , (val1 + val2) + beq r5 ,r3 , good +; nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/add001.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/add001.u new file mode 100644 index 00000000..85a49a48 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/add001.u @@ -0,0 +1,33 @@ +; ###----------------------------------------------------------------### +; # file : add001.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # signed addition # + ; ###--------------------------------------------------------### + +val .equ 0x0002 + + .org 0x00400000 + .start init + +init: + addi r1 , r0 , val + addi r2 , r0 , val + add r3 , r2 , r1 + + addi r11, r0 , (val + val) + beq r11, r3, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/add002.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/add002.u new file mode 100644 index 00000000..6baa5fe1 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/add002.u @@ -0,0 +1,34 @@ +; ###----------------------------------------------------------------### +; # file : add002.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # signed addition # + ; ###--------------------------------------------------------### + +val1 .equ 0x1000 +val2 .equ 0xf000 + + .org 0x00400000 + .start init + +init: + addi r11, r0 , val1 + addi r12, r0 , val2 + add r13, r12, r11 + + addi r6 , r0, (val1 + val2) + beq r6 , r13,good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/add003.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/add003.u new file mode 100644 index 00000000..c2840850 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/add003.u @@ -0,0 +1,39 @@ +; ###----------------------------------------------------------------### +; # file : add003.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # signed addition # + ; ###--------------------------------------------------------### + +val1 .equ 0xf1c1 +val2 .equ 0x1112 + + .org 0x00400000 + .start init + +init: + addi r1 , r0 , val1 + addi r2 , r0 , val2 + + addi r3 , r1 , 1 + addi r4 , r2 , 2 + add r17, r3 , r4 + + lui r29 , (val1 + val2) + 3 + sra r29, r29, 16 + + beq r29,r17, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/add004.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/add004.u new file mode 100644 index 00000000..2dd35062 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/add004.u @@ -0,0 +1,39 @@ +; ###----------------------------------------------------------------### +; # file : add004.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # signed subtraction # + ; ###--------------------------------------------------------### + +vai .equ 1 +limit .equ 7 +first .equ 10 + + .org 0x00400000 + .start init + +init : + loadi r1 , limit + loadi r2 , first + +loop : + addi r4,r0,vai + sub r2 , r2 ,r4 + bne r2 , r1,loop + nop + + beq r1,r2,good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/add005.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/add005.u new file mode 100644 index 00000000..9635ecd9 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/add005.u @@ -0,0 +1,63 @@ +; ###----------------------------------------------------------------### +; # file : add005.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # signed addition # + ; # each register is initialized with its number # + ; ###--------------------------------------------------------### + +increment .equ 1 + + .org 0x00400000 + .start init + +init: + addi r1 , r0 , increment + addi r2 , r1 , increment + addi r3 , r2 , increment + addi r4 , r3 , increment + addi r5 , r4 , increment + addi r6 , r5 , increment + addi r7 , r6 , increment + addi r8 , r7 , increment + addi r9 , r8 , increment + addi r10, r9 , increment + addi r11, r10, increment + addi r12, r11, increment + addi r13, r12, increment + addi r14, r13, increment + addi r15, r14, increment + addi r16, r15, increment + addi r17, r16, increment + addi r18, r17, increment + addi r19, r18, increment + addi r20, r19, increment + addi r21, r20, increment + addi r22, r21, increment + addi r23, r22, increment + addi r24, r23, increment + addi r25, r24, increment + addi r26, r25, increment + addi r27, r26, increment + addi r28, r27, increment + addi r29, r28, increment + addi r30, r29, increment + addi r31, r30, increment + + addi r30, r0, (increment * 31) + beq r31 ,r30 , good + nop + j bad + nop + + .org 0x004000d0 + +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/addu000.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/addu000.u new file mode 100644 index 00000000..96bc3026 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/addu000.u @@ -0,0 +1,30 @@ +; ###----------------------------------------------------------------### +; # file : addu000.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # unsigned addition # + ; ###--------------------------------------------------------### + + .org 0x00400000 +const .equ 0x07cb + .start init + +init: + addiu r13, r0, const + addiu r14, r0, const + 1 + + bne r14, r13,good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/addu001.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/addu001.u new file mode 100644 index 00000000..819cb599 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/addu001.u @@ -0,0 +1,30 @@ +; ###----------------------------------------------------------------### +; # file : addu001.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # unsigned addition # + ; ###--------------------------------------------------------### + + .org 0x00400000 +const .equ 0x34ae + .start init + +init: + addiu r18, r0, const + addiu r17, r0, const + + beq r18, r17,good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/addu002.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/addu002.u new file mode 100644 index 00000000..a01ddfc8 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/addu002.u @@ -0,0 +1,36 @@ +; ###----------------------------------------------------------------### +; # file : addu002.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # unsigned addition # + ; ###--------------------------------------------------------### + +const .equ 0x1acb + + .org 0x00400000 + .start init + +init: + addiu r13, r0, const + addiu r14, r0, const + nop + nop + nop + addu r15, r13, r14 + + addiu r30, r0, (const + const) + beq r30, r15,good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/addu003.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/addu003.u new file mode 100644 index 00000000..6a799155 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/addu003.u @@ -0,0 +1,30 @@ +; ###----------------------------------------------------------------### +; # file : addu000.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # unsigned addition # + ; ###--------------------------------------------------------### + + .org 0x00400000 +const1 .equ 0x07cb +const2 .equ 0xffff07cb + .start init + +init: + addiu r13, r0, const1 + addiu r14, r0, const2 + + bne r14, r13,bad + nop + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/and000.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/and000.u new file mode 100644 index 00000000..0c42d2ac --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/and000.u @@ -0,0 +1,63 @@ +; ###----------------------------------------------------------------### +; # file : and000.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + .org 0x00400000 + .start init + + ; ###--------------------------------------------------------### + ; # Test of AND instruction in 4 steps # + ; ###--------------------------------------------------------### + +un .equ 1 +deux .equ 2 +trois .equ 3 +mask .equ 0xffff ;mask = -1 +mask1 .equ 0x00ff ;mask = -1 +mask2 .equ 0xff00 ;mask = -1 + +init: + addiu r5 , r0 , mask ;r5 = -1 + addiu r6 , r0 , un ;r6 = 1 + + and r7 , r6 , r5 ;r7 = 1 + + bne r6 , r7, bad + nop + + addiu r8 , r0 , mask1 + addiu r3 , r0 , mask2 + + and r9 , r3 , r8 ;r9 = 0 + + bne r0, r9, bad + nop + + addiu r5 , r0 , un ;r5 = 1 + addiu r6 , r0 , trois ;r6 = 3 + + and r8 , r6 , r5 ;r8 = 1 + + bne r5,r8, bad + nop + + addiu r7 , r0 , deux ;r7 = 2 + addiu r9 , r0 , trois ;r9 = 3 + + and r6 , r9 , r7 ;r6 = 2 + + bne r6,r7, bad + nop + + j good + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/and001.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/and001.u new file mode 100644 index 00000000..4dc450d8 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/and001.u @@ -0,0 +1,33 @@ +; ###----------------------------------------------------------------### +; # file : and001.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # and immediate # + ; ###--------------------------------------------------------### + +data1 .equ 0xd6f2 +data2 .equ 0xc451 + + .org 0x00400000 + .start init + +init: + addiu r6 , r0 , data1 ; r6 = data2 + andi r7 , r6 , data2 ; r7 = data1 & data2 + + loadi r3 , (data1 & data2) ; good if r7 correct + bne r3 , r7 , bad + + j good + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/beq000.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/beq000.u new file mode 100644 index 00000000..c4b98355 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/beq000.u @@ -0,0 +1,37 @@ + +; ###----------------------------------------------------------------### +; # file : beq000.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # conditional branch # + ; ###--------------------------------------------------------### + +val1 .equ 0x000057a1 +val2 .equ 0x00000001 +val3 .equ 0x000057a2 + + .org 0x00400000 + .start init + +init : + loadi r7 , val1 + loadi r8 , val2 + addu r9 , r8 , r7 + + loadi r10 , val3 + + beq r10 , r9 , good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/beq001.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/beq001.u new file mode 100644 index 00000000..94d5c957 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/beq001.u @@ -0,0 +1,36 @@ + +; ###----------------------------------------------------------------### +; # file : beq001.u # +; # date : nov 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # conditional branch # + ; ###--------------------------------------------------------### + +val1 .equ 0xa7a1 +val2 .equ 0x2339 + + .org 0x00400000 + .start init + +init : + addi r7 ,r0 , val1 + addi r8 ,r0 , val2 + addi r9 ,r0 , (val1 - val2) + + sub r10 , r7 , r8 + + beq r10 , r9 , good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/bgez000.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/bgez000.u new file mode 100644 index 00000000..bbc4784e --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/bgez000.u @@ -0,0 +1,50 @@ + +; ###----------------------------------------------------------------### +; # file : bgez000.u # +; # date : Nov 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # conditional branch # + ; # tests if it doesn't branch when it's not greater or # + ; # equal. Then it tests greater # + ; ###--------------------------------------------------------### + +val1 .equ 0xffffffff +val2 .equ 0x0000ffff +val3 .equ 0x00000001 + + .org 0x00400000 + .start init + +init : + lui r7 , val1 + addiu r8 , r0 , val2 + + or r10 , r7 , r8 + + bgez r10 , bad + nop + + addiu r9 , r10 , val3 + bgez r9 , inter + nop + + j bad + nop + + .org 0x004000d0 + + +good: j good + nop +bad: j bad + nop +inter: addiu r9 , r9 , val3 + bgez r9 , good + nop + j bad + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/bgez001.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/bgez001.u new file mode 100644 index 00000000..a86520fa --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/bgez001.u @@ -0,0 +1,46 @@ + +; ###----------------------------------------------------------------### +; # file : bgez001.u # +; # date : Nov 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # conditional branch # + ; # test if equal # + ; ###--------------------------------------------------------### + + + +val1 .equ 0x000057a1 +val2 .equ 0x000057a4 +val3 .equ 0x00000003 + + .org 0x00400000 + .start init + +init : + loadi r7 , val1 + loadi r8 , val2 + + sub r10 , r7 , r8 + + bgez r10 , bad + nop + + addiu r9 , r10 , val3 + bgez r9 , good + nop + + j bad + nop + + .org 0x004000d0 + + +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/bgezal000.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/bgezal000.u new file mode 100644 index 00000000..5999c47c --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/bgezal000.u @@ -0,0 +1,57 @@ + +; ###----------------------------------------------------------------### +; # file : bgezal000.u # +; # date : nov 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # Branch if greater or equal and link # + ; # We test when it's greater , when it's lower or equal and # + ; # if it puts pc + 4 in r31 in all cases # + ; ###--------------------------------------------------------### + +const .equ 0x00000002 +val1 .equ 0x00000001 +val2 .equ 0x00000002 +val3 .equ 0x00000008 +mask .equ 0xffffffff +mask1 .equ 0x0000ffff + + .org 0x00400000 + + .start init + +init: + loadi r23, const + loadi r24, (4 * const) + + bgezal r0, mul2 + nop + addiu r1 , r0 , val1 + bgezal r1 , mul2 + nop + + lui r1 , mask + addiu r16, r0 , mask1 + or r1 , r1 , r16 + bgezal r1 , bad + addiu r31, r31, val3 + jr r31 + beq r24 ,r23, good + nop + j bad + nop + +mul2 : + addu r23, r23, r23 + jr r31 + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/bgtz000.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/bgtz000.u new file mode 100644 index 00000000..1dc38339 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/bgtz000.u @@ -0,0 +1,47 @@ + +; ###----------------------------------------------------------------### +; # file : bgtz000.u # +; # date : Nov 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # conditional branch # + ; # Branch if register is greater to zero # + ; # the 3 cases are tested: greater or equal or lower # + ; ###--------------------------------------------------------### + +val3 .equ 0xffffffff +val4 .equ 0x0000ffff +val5 .equ 0x00000005 + + .org 0x00400000 + .start init + +init : + lui r11, val3 + addiu r16, r0 , val4 + or r11, r11 , r16 + + bgtz r0 , bad + nop + + bgtz r11 , bad + nop + + addiu r10 , r0 , val5 + bgtz r10 , good + nop + + j bad + nop + + .org 0x004000d0 + + +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/blez000.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/blez000.u new file mode 100644 index 00000000..b1a033b7 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/blez000.u @@ -0,0 +1,47 @@ + +; ###----------------------------------------------------------------### +; # file : blez000.u # +; # date : Nov 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # conditional branch # + ; ###--------------------------------------------------------### + +mask .equ 0xffffffff +mask1 .equ 0x0000ffff +val1 .equ 0x00000001 + + .org 0x00400000 + .start init + +init : + loadi r10, val1 + + blez r10 , bad + nop + + blez r0 , test + nop + + j bad + nop + +test : + lui r10 , mask + addiu r16 , r0 , mask1 + or r10 , r10 , r16 + blez r10 , good + j bad + nop + + .org 0x004000d0 + + +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/bltz000.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/bltz000.u new file mode 100644 index 00000000..7592042b --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/bltz000.u @@ -0,0 +1,47 @@ + +; ###----------------------------------------------------------------### +; # file : bltz000.u # +; # date : Nov 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # conditional branch # + ; ###--------------------------------------------------------### + +mask .equ 0xffffffff +mask1 .equ 0x0000ffff +val1 .equ 0x00000001 + + .org 0x00400000 + .start init + +init : + loadi r10 , val1 + + bltz r10 , bad + nop + + bltz r0 , bad + j test + nop + +test : + lui r10 , mask + addiu r16 , r0 , mask1 + or r10 , r10 , r16 + bltz r10 , good + nop + + j bad + nop + + .org 0x004000d0 + + +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/bltzal000.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/bltzal000.u new file mode 100644 index 00000000..5923ac84 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/bltzal000.u @@ -0,0 +1,62 @@ + +; ###----------------------------------------------------------------### +; # file : bltzal000.u # +; # date : Nov 1996 # +; # descr. : functional test for dlx # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # conditional branch # + ; ###--------------------------------------------------------### + +mask .equ 0xffffffff +mask1 .equ 0x0000fffe +mask2 .equ 0x0000ffff +const .equ 0x00000002 +val1 .equ 0x00000001 +val2 .equ 0x00000008 + + .org 0x00400000 + + .start init + +init: + loadi r23, const + loadi r24, (4 * const) + + lui r1 , mask + addiu r16, r0 , mask1 + or r1 , r1 , r16 + bltzal r1 , mul2 + nop + + lui r1 , mask + addiu r16, r0 , mask2 + or r1 , r1 , r16 + bltzal r1 , mul2 + nop + + loadi r1 , val1 + bltzal r1 , bad + bltzal r0 , bad + addiu r31 , r31 , val2 + jr r31 + + beq r24 , r23 , good + nop + + j bad + nop + +mul2 : + addu r23 , r23 , r23 + jr r31 + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/bne000.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/bne000.u new file mode 100644 index 00000000..c88e028c --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/bne000.u @@ -0,0 +1,35 @@ + +; ###----------------------------------------------------------------### +; # file : bne000.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # conditional branch # + ; ###--------------------------------------------------------### + +val1 .equ 0x00000001 +val2 .equ 0x00000002 + + .org 0x00400000 + .start init + +init : + loadi r7 , val1 + addu r7 , r7 , r7 + loadi r8 , val2 + + + bne r7 , r8 , bad + nop + j good + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/bne001.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/bne001.u new file mode 100644 index 00000000..e7c0c709 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/bne001.u @@ -0,0 +1,36 @@ + +; ###----------------------------------------------------------------### +; # file : bne000.u # +; # date : nov 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # conditional branch # + ; ###--------------------------------------------------------### + +val1 .equ 0xa7a1 +val2 .equ 0x2339 + + .org 0x00400000 + .start init + +init : + addi r7 ,r0 , val1 + addi r8 ,r0 , val2 + addi r9 ,r0 , (val1 - val2) + + sub r10 , r7 , r8 + + bne r10 , r9 , bad + nop + j good + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/break_00.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/break_00.e new file mode 100644 index 00000000..67728128 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/break_00.e @@ -0,0 +1,61 @@ + +; ###----------------------------------------------------------------### +; # file : break_00.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - break # + ; ###--------------------------------------------------------### + +val1 .equ 0x3C + +val .equ 0x24 + + .org 0x80000080 + .start it_handler + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + +it_handler: + + sw r29, 0 (r30) + sw r28, 4 (r30) + + addi r28, r0, val1 + mfc0 r29, cause + nop + and r29, r29, r28 + addi r27, r0, val + bne r29, r27, not_good + nop + + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from EXCEPTION) # + ; # to the user program (address must be saved by the user # + ; # prior to the EXCEPTION in epc) # + ; ###--------------------------------------------------------### + +restore_return_adr: + mfc0 r31,epc + nop + addi r31,r31,8 + jr r31 + rfe + +not_good: + mfc0 r31,epc + nop + addi r31,r31,4 + jr r31 + rfe + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/break_00.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/break_00.u new file mode 100644 index 00000000..3bbf1222 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/break_00.u @@ -0,0 +1,41 @@ +; ###----------------------------------------------------------------### +; # # +; # file : break_00.u # +; # date : Apr 21 1995 # +; # descr. : functional test for mips # +; # # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # software interrupt : # + ; ###--------------------------------------------------------### + + + .org 0x00400000 + .start init + +init: + + ; ###--------------------------------------------------------### + ; # sotware interrupt # + ; ###--------------------------------------------------------### + + break 1 + j bad + + ; ###--------------------------------------------------------### + ; # check that the the trap has been done (r1 must contain # + ; # the trap number) # + ; ###--------------------------------------------------------### + +back_from_exception: + j good ; jump to good if OK + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc000.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc000.e new file mode 100644 index 00000000..abc5b602 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc000.e @@ -0,0 +1,64 @@ + +; ###----------------------------------------------------------------### +; # file : exc000.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - data miss alignement # + ; ###--------------------------------------------------------### + +val1 .equ 0x3C ; arithmetic overflow + +val .equ 0x10 + + .org 0x80000080 + .start it_handler + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + +it_handler: + + sw r29, 0(r30) + sw r28, 4(r30) + + addiu r28,r0,val1 + mfc0 r29,cause + nop + and r29, r29, r28 ; data address violation ? + addiu r27,r0,val + bne r29,r27, other_causes + nop + + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from EXCEPTION) # + ; # to the user program (address must be saved by the user # + ; # prior to the EXCEPTION in epc) # + ; ###--------------------------------------------------------### + +restore_return_adr: + mfc0 r31,epc + nop + addiu r31,r31,4 + j return + nop + +other_causes: j other_causes + nop + + ; ###--------------------------------------------------------### + ; # return to the interrupted program # + ; ###--------------------------------------------------------### + .org 0x800000d0 +return: + rfe + jr r31 + + .end diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc000.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc000.u new file mode 100644 index 00000000..098ecad8 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc000.u @@ -0,0 +1,52 @@ + +; ###----------------------------------------------------------------### +; # file : exc100.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - data address miss alignment (when loading a word) # + ; ###--------------------------------------------------------### + +adr .equ 0x40000050 ; word address +data .equ 0x9043ad6b ; data + + .org 0x00400000 + .start init + +init: + loadi r31, back_from_exception + loadi r1 , adr ; word's address + loadi r2 , data ; init. r2 with a data + loadi r3 , data ; init. r3 with the same value + + ; ###--------------------------------------------------------### + ; # load a word at a miss aligned address (data address # + ; # alignment exception) # + ; ###--------------------------------------------------------### + + lw r2 , 1 (r1 ) ; EXCEPTION (alignement) + nop + + ; ###--------------------------------------------------------### + ; # check that the load has faild and the content of the # + ; # register has not been altered # + ; ###--------------------------------------------------------### + +back_from_exception: + ; check that the lw has failed + beq r3 ,r2, good ; jump to good if OK + nop + j bad + nop + + .org 0x004000D0 +good: j good + nop + .org 0x004000D8 +bad: j bad + nop + + .end diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc001.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc001.e new file mode 100644 index 00000000..0aa0ff12 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc001.e @@ -0,0 +1,64 @@ + +; ###----------------------------------------------------------------### +; # file : exc000.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - ades # + ; ###--------------------------------------------------------### + +val1 .equ 0x3C +val .equ 0x14 + + .org 0x80000080 + .start it_handler + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + +it_handler: + + sw r29, 0(r30) + sw r28, 4(r30) + + addiu r28,r0,val1 + mfc0 r29,cause + nop + and r29, r29, r28 ; data address violation ? + addiu r27,r0,val + bne r29,r27, other_causes + nop + + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from EXCEPTION) # + ; # to the user program (address must be saved by the user # + ; # prior to the EXCEPTION in epc) # + ; ###--------------------------------------------------------### + +restore_return_adr: + mfc0 r31,epc + nop + addiu r31,r31,4 + j return + nop + +other_causes: j other_causes + nop + + ; ###--------------------------------------------------------### + ; # return to the interrupted program # + ; ###--------------------------------------------------------### + .org 0x800000d0 +return: + rfe + jr r31 + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc001.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc001.u new file mode 100644 index 00000000..e2014012 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc001.u @@ -0,0 +1,61 @@ + +; ###----------------------------------------------------------------### +; # file : exc001.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - data address miss alignment (when storing a word) # + ; ###--------------------------------------------------------### + +adr .equ 0x40000050 +data .equ 0x9043ad6b ; data + + .org 0x00400000 + .start init + +init: + loadi r31, back_from_exception + loadi r1 , adr ; word's address in r1 + loadi r2 , data ; data in r2 + loadi r3 , data ; same data in r3 + loadi r4 , data ^ 0xffffffff ; complemented data in r4 + + ; ###--------------------------------------------------------### + ; # store the word to initialize the memory location # + ; ###--------------------------------------------------------### + + sw r2, 0 (r1 ) + sw r2, 4 (r1 ) + + ; ###--------------------------------------------------------### + ; # store word at a miss aligned address # + ; ###--------------------------------------------------------### + + sw r4, 1 (r1 ) ; EXCEPTION (alignment) + + ; ###--------------------------------------------------------### + ; # after returning from exception, read the memory location # + ; # and check that the faulty store word has not modified the # + ; # memory # + ; ###--------------------------------------------------------### + +back_from_exception: + lw r5 , 0 (r1 ) + bne r5,r3, bad + nop + lw r5 , 4 (r1 ) + bne r5,r3, bad + nop + j good + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc002.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc002.e new file mode 100644 index 00000000..0b1b0880 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc002.e @@ -0,0 +1,66 @@ + +; ###----------------------------------------------------------------### +; # file : exc002.s # +; # date : Mar 26 1996 # +; # descr. : functional test for dlx # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - overflow (when adding positive numbers) # + ; ###--------------------------------------------------------### + +val1 .equ 0x3C ; arithmetic overflow + +user_prog .equ 0x00400000 +val .equ 0x30 + + .org 0x80000080 + .start it_handler + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + +it_handler: + + sw r29, 0 (r30) + sw r28, 4 (r30) + + addiu r28, r0 ,val1 + mfc0 r29,cause + nop + and r29, r29, r28 ; data address violation ? + addiu r27,r0,val + bne r29,r27, other_causes + nop + + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from EXCEPTION) # + ; # to the user program (address must be saved by the user # + ; # prior to the EXCEPTION in epc) # + ; ###--------------------------------------------------------### + +restore_return_adr: + mfc0 r1,epc + nop + addiu r1,r1,4 + j return + nop + +other_causes: j other_causes + nop + + ; ###--------------------------------------------------------### + ; # return to the interrupted program # + ; ###--------------------------------------------------------### + .org 0x800000d0 +return: + rfe + jr r1 + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc002.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc002.u new file mode 100644 index 00000000..6a7f3197 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc002.u @@ -0,0 +1,46 @@ + +; ###----------------------------------------------------------------### +; # file : exc002.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - overflow (when adding positive numbers) # + ; ###--------------------------------------------------------### + +data .equ 0x6234fe80 ; a big positive data + + .org 0x00400000 + .start init + +init: + loadi r31, back_from_exception + loadi r10, data ; big positive data in r10 + loadi r11, data ; same data in r11 + + ; ###--------------------------------------------------------### + ; # addition generating an overflow # + ; ###--------------------------------------------------------### + + add r10, r10, r10 ; EXCEPTION (overflow) + + ; ###--------------------------------------------------------### + ; # after returning from exception check that r10 has not # + ; # been altered # + ; ###--------------------------------------------------------### + +back_from_exception: + beq r10, r11, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc003.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc003.e new file mode 100644 index 00000000..3418a948 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc003.e @@ -0,0 +1,68 @@ + +; ###----------------------------------------------------------------### +; # file : exc003.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - overflow (when adding positive numbers) # + ; ###--------------------------------------------------------### + +val1 .equ 0x3C ; arithmetic overflow + +system_stack .equ 0xC0000000 ; system stack address + +user_prog .equ 0x00400000 +val .equ 0x30 + + .org 0x80000080 + .start it_handler + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + +it_handler: + + sw r29, 0 (r30) + sw r28, 4 (r30) + + addi r28, r0 ,val1 + mfc0 r29,cause + nop + and r29, r29, r28 ; data address violation ? + addiu r27,r0,val + bne r29,r27, other_causes + nop + + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from EXCEPTION) # + ; # to the user program (address must be saved by the user # + ; # prior to the EXCEPTION in epc) # + ; ###--------------------------------------------------------### + +restore_return_adr: + mfc0 r1,epc + nop + addiu r1,r1,4 + j return + nop + +other_causes: j other_causes + nop + + ; ###--------------------------------------------------------### + ; # return to the interrupted program # + ; ###--------------------------------------------------------### + .org 0x800000d0 +return: + rfe + jr r1 + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc003.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc003.u new file mode 100644 index 00000000..342160cf --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc003.u @@ -0,0 +1,47 @@ + +; ###----------------------------------------------------------------### +; # file : exc003.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - overflow (when subtracting from a positive number) # + ; ###--------------------------------------------------------### + +data .equ 0x52d4aec6 ; a big positive data + + .org 0x00400000 + .start init + +init: + loadi r31, back_from_exception + loadi r10, data ; big positive data in r10 + loadi r11, data ; same data in r11 + + ; ###--------------------------------------------------------### + ; # substract generating an overflow # + ; ###--------------------------------------------------------### + + sub r12, r0 , r10 + sub r10, r12, r10 ; EXCEPTION (overflow) + + ; ###--------------------------------------------------------### + ; # after returning from exception check that r10 has not # + ; # been altered # + ; ###--------------------------------------------------------### + +back_from_exception: + bne r10, r11,bad + nop + j good + nop + + .org 0x004000D0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc004.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc004.e new file mode 100644 index 00000000..77b1305d --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc004.e @@ -0,0 +1,66 @@ + +; ###----------------------------------------------------------------### +; # file : exc004.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - overflow (when adding positive numbers) # + ; ###--------------------------------------------------------### + +val1 .equ 0x3C ; arithmetic overflow + +user_prog .equ 0x00400000 +val .equ 0x30 + + .org 0x80000080 + .start it_handler + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + +it_handler: + + sw r29, 0 (r30) + sw r28, 4 (r30) + + addi r28, r0 ,val1 + mfc0 r29,cause + nop + and r29, r29, r28 ; data address violation ? + addiu r27,r0,val + bne r29,r27, other_causes + nop + + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from EXCEPTION) # + ; # to the user program (address must be saved by the user # + ; # prior to the EXCEPTION in epc) # + ; ###--------------------------------------------------------### + +restore_return_adr: + mfc0 r1,epc + nop + addiu r1,r1,4 + j return + nop + +other_causes: j other_causes + nop + + ; ###--------------------------------------------------------### + ; # return to the interrupted program # + ; ###--------------------------------------------------------### + .org 0x800000d0 +return: + rfe + jr r1 + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc004.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc004.u new file mode 100644 index 00000000..2dd99147 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc004.u @@ -0,0 +1,46 @@ + +; ###----------------------------------------------------------------### +; # file : exc004.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - overflow (when adding negative numbers) # + ; ###--------------------------------------------------------### + +data .equ 0xb2305ec0 ; a big negative data + + .org 0x00400000 + .start init + +init: + loadi r31, back_from_exception + loadi r10, data ; big positive data in r10 + loadi r11, data ; same data in r11 + + ; ###--------------------------------------------------------### + ; # addtion generating an overflow # + ; ###--------------------------------------------------------### + + add r10, r10, r10 ; EXCEPTION (overflow) + + ; ###--------------------------------------------------------### + ; # after returning from exception check that r10 has not # + ; # been altered # + ; ###--------------------------------------------------------### + +back_from_exception: + bne r10,r11, bad + nop + j good + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc005.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc005.e new file mode 100644 index 00000000..f179c918 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc005.e @@ -0,0 +1,66 @@ + +; ###----------------------------------------------------------------### +; # file : exc005.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - overflow (when adding positive numbers) # + ; ###--------------------------------------------------------### + +val1 .equ 0x3C ; arithmetic overflow + +user_prog .equ 0x00400000 +val .equ 0x30 + + .org 0x80000080 + .start it_handler + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + +it_handler: + + sw r29, 0 (r30) + sw r28, 4 (r30) + + addi r28, r0 ,val1 + mfc0 r29,cause + nop + and r29, r29, r28 ; data address violation ? + addiu r27,r0,val + bne r29,r27, other_causes + nop + + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from EXCEPTION) # + ; # to the user program (address must be saved by the user # + ; # prior to the EXCEPTION in epc) # + ; ###--------------------------------------------------------### + +restore_return_adr: + mfc0 r1,epc + nop + addiu r1,r1,4 + j return + nop + +other_causes: j other_causes + nop + + ; ###--------------------------------------------------------### + ; # return to the interrupted program # + ; ###--------------------------------------------------------### + .org 0x800000d0 +return: + rfe + jr r1 + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc005.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc005.u new file mode 100644 index 00000000..fff96169 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc005.u @@ -0,0 +1,47 @@ + +; ###----------------------------------------------------------------### +; # file : exc005.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - overflow (when subtracting from a negative number) # + ; ###--------------------------------------------------------### + +data .equ 0x946e3d0f ; a big negative data + + .org 0x00400000 + .start init + +init: + loadi r31, back_from_exception + loadi r10, data ; big negative data in r10 + loadi r11, data ; same data in r11 + + ; ###--------------------------------------------------------### + ; # substract generating an overflow # + ; ###--------------------------------------------------------### + + sub r12, r0 , r10 + sub r10, r12, r10 ; EXCEPTION (overflow) + + ; ###--------------------------------------------------------### + ; # after returning from exception check that r10 has not # + ; # been altered # + ; ###--------------------------------------------------------### + +back_from_exception: + bne r10,r11, bad + nop + j good + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc006.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc006.e new file mode 100644 index 00000000..1a27df99 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc006.e @@ -0,0 +1,66 @@ + +; ###----------------------------------------------------------------### +; # file : exc006.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - illegal instruction address (alignment) # + ; ###--------------------------------------------------------### + +val1 .equ 0x3C + +val .equ 0x10 ; adel + + .org 0x80000080 + .start it_handler + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + +it_handler: + + sw r29, 0 (r30) + sw r28, 4 (r30) + + addiu r28, r0 ,val1 + mfc0 r29,cause + nop + and r29, r29, r28 ; data address violation ? + addiu r27,r0,val + bne r29,r27, other_causes + nop + + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from EXCEPTION) # + ; # to the user program (address saved by the user in epc # + ; # can't be used: it's misaligned !! ) => jump at good. # + ; ###--------------------------------------------------------### + +restore_return_adr: + ;mfc0 r31,epc + ;nop + ;addiu r31,r31,4 + loadi r31, 0x004000d0 + j return + nop + +other_causes: j other_causes + nop + + ; ###--------------------------------------------------------### + ; # return to the interrupted program # + ; ###--------------------------------------------------------### + .org 0x800000d0 +return: + rfe + jr r31 + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc006.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc006.u new file mode 100644 index 00000000..999cbaa9 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc006.u @@ -0,0 +1,37 @@ + +; ###----------------------------------------------------------------### +; # file : exc006.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - illegal instruction address (alignment) # + ; ###--------------------------------------------------------### + + .org 0x00400000 + .start init + +init: + loadi r31, back_from_exception + loadi r20, target_adr + 1 ; missaligned address in r20 +target_adr: + jr r20 ; EXCEPTION (alignment) + nop + + ; ###--------------------------------------------------------### + ; # jump to good if returned from exception # + ; ###--------------------------------------------------------### + +back_from_exception: + j good + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc007.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc007.e new file mode 100644 index 00000000..7789b6db --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc007.e @@ -0,0 +1,62 @@ + +; ###----------------------------------------------------------------### +; # file : exc007.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - adel # + ; ###--------------------------------------------------------### + +val1 .equ 0x3C + +user_prog .equ 0x00400000 +val .equ 0x10 ; adel + + .org 0x80000080 + .start it_handler + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + +it_handler: + + sw r29, 0 (r30) + sw r28, 4 (r30) + + addiu r28, r0 ,val1 + addiu r27,r0,val + mfc0 r29,cause + nop + and r29, r29, r28 ; data address violation ? + bne r27,r29, other_causes + nop + + lw r29, 0 (r30) + lw r28, 4 (r30) + + j return + ; ###--------------------------------------------------------### + ; # restore return address before returning (from EXCEPTION) # + ; # to the user program (address must be saved by the user # + ; # prior to the EXCEPTION in epc) # + ; ###--------------------------------------------------------### + +restore_return_adr: + +other_causes: j other_causes + nop + + ; ###--------------------------------------------------------### + ; # return to the interrupted program # + ; ###--------------------------------------------------------### + .org 0x800000d0 +return: + rfe + jr r31 + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc007.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc007.u new file mode 100644 index 00000000..4e4ec867 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc007.u @@ -0,0 +1,36 @@ +; ###----------------------------------------------------------------### +; # file : exc007.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - illegal instruction address (segment) # + ; ###--------------------------------------------------------### +it_handler .equ 0x80000080 + + .org 0x00400000 + .start init + +init: + loadi r31, back_from_exception + loadi r20, it_handler + jr r20 ; EXCEPTION (segment) + nop + + ; ###--------------------------------------------------------### + ; # jump to good if returned from exception # + ; ###--------------------------------------------------------### + +back_from_exception: + j good + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc008.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc008.e new file mode 100644 index 00000000..08014faf --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc008.e @@ -0,0 +1,64 @@ + +; ###----------------------------------------------------------------### +; # file : exc008.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - adel # + ; ###--------------------------------------------------------### + +val1 .equ 0x3C +val .equ 0x10 ; adel + + .org 0x80000080 + .start it_handler + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + +it_handler: + + sw r29, 0 (r30) + sw r28, 4 (r30) + + addiu r28, r0 ,val1 + mfc0 r29,cause + nop + and r29, r29, r28 ; data address violation ? + addiu r27,r0,val + bne r29,r27, other_causes + nop + + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from EXCEPTION) # + ; # to the user program (address must be saved by the user # + ; # prior to the EXCEPTION in epc) # + ; ###--------------------------------------------------------### + +restore_return_adr: + mfc0 r31,epc + nop + addiu r31,r31,4 + j return + nop + +other_causes: j other_causes + nop + + ; ###--------------------------------------------------------### + ; # return to the interrupted program # + ; ###--------------------------------------------------------### + .org 0x800000d0 +return: + rfe + jr r31 + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc008.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc008.u new file mode 100644 index 00000000..cf4a59a8 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc008.u @@ -0,0 +1,51 @@ + +; ###----------------------------------------------------------------### +; # file : exc008.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - illegal data address (segment when loading) # + ; ###--------------------------------------------------------### + +adr .equ 0xC000003c ; data adr in system segment +data .equ 0x9043ad6b ; data + + .org 0x00400000 + .start init + +init: + loadi r31, back_from_exception + loadi r1 , adr ; word's address + loadi r2 , data ; init. r2 with a data + loadi r3 , data ; init. r3 with the same value + + ; ###--------------------------------------------------------### + ; # load a word at a miss segmented address (data address # + ; # segment exception) # + ; ###--------------------------------------------------------### + + lw r2 , 0 (r1 ) ; EXCEPTION (segment) + + ; ###--------------------------------------------------------### + ; # check that the load has faild and the content of the # + ; # register has not been altered # + ; ###--------------------------------------------------------### + +back_from_exception: + ; check that the lw has failed + beq r2 ,r3, good ; jump to good if OK + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc009.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc009.e new file mode 100644 index 00000000..2d965899 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc009.e @@ -0,0 +1,64 @@ + +; ###----------------------------------------------------------------### +; # file : exc009.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - ri (when executing a mfc0) # + ; ###--------------------------------------------------------### + +val1 .equ 0x3C +val .equ 0x2C ; cpu + + .org 0x80000080 + .start it_handler + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + +it_handler: + + sw r29, 0 (r30) + sw r28, 4 (r30) + + addiu r28, r0 ,val1 + mfc0 r29,cause + nop + and r29, r29, r28 ; data address violation ? + addiu r27,r0,val + bne r29,r27, other_causes + nop + + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from EXCEPTION) # + ; # to the user program (address must be saved by the user # + ; # prior to the EXCEPTION in epc) # + ; ###--------------------------------------------------------### + +restore_return_adr: + mfc0 r31,epc + nop + addiu r31,r31,8 + j return + nop + +other_causes: j other_causes + nop + + ; ###--------------------------------------------------------### + ; # return to the interrupted program # + ; ###--------------------------------------------------------### + .org 0x800000d0 +return: + rfe + jr r31 + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc009.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc009.u new file mode 100644 index 00000000..ef3da94c --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc009.u @@ -0,0 +1,49 @@ + +; ###----------------------------------------------------------------### +; # file : exc009.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - illegal instruction (when executing a mfc0) # + ; ###--------------------------------------------------------### + +data .equ 0x324f6b71 + .org 0x00400000 + .start init + +init: + loadi r31, back_from_exception + loadi r1 , data ; init. r2 with a data + loadi r2 , data ; init. r3 with the same value + + ; ###--------------------------------------------------------### + ; # move SR into r1. This must generate an exception # + ; # (coprocesseur inaccessible) # + ; ###--------------------------------------------------------### + + mfc0 r1 , status ; EXCEPTION (privileged) + nop + + ; ###--------------------------------------------------------### + ; # check that the load has faild and the content of the # + ; # register has not been altered # + ; ###--------------------------------------------------------### + +back_from_exception: + ; check that the move has failed + beq r1 , r2 ,good ; jump to good if OK + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc010.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc010.e new file mode 100644 index 00000000..9a50e0b8 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc010.e @@ -0,0 +1,61 @@ + +; ###----------------------------------------------------------------### +; # file : exc010.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - ri # + ; ###--------------------------------------------------------### + +val1 .equ 0x3C +val .equ 0x2C ; cpu (copro inaccessible..) + + .org 0x80000080 + .start it_handler + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + +it_handler: + + sw r29, 0 (r30) + sw r28, 4 (r30) + + addiu r28, r0 ,val1 + mfc0 r29,cause + nop + and r29, r29, r28 ; data address violation ? + addiu r27,r0,val + bne r29,r27, other_causes + nop + + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from EXCEPTION) # + ; # to the user program (address must be saved by the user # + ; # prior to the EXCEPTION in epc) # + ; ###--------------------------------------------------------### + +restore_return_adr: + j return + nop + +other_causes: j other_causes + nop + + ; ###--------------------------------------------------------### + ; # return to the interrupted program # + ; ###--------------------------------------------------------### + .org 0x800000d0 +return: + rfe + jr r31 + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc010.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc010.u new file mode 100644 index 00000000..82aba7bd --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc010.u @@ -0,0 +1,45 @@ + +; ###----------------------------------------------------------------### +; # file : exc010.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - illegal instruction (when executing a mtc0) # + ; ###--------------------------------------------------------### + +new_sr .equ 0x00000000 ; try to set system mode + .org 0x00400000 + .start init + +init: + loadi r1 , new_sr ; init. r2 with the desired + ;+value of sr + + ; ###--------------------------------------------------------### + ; # move r1 into sr. This must generate an exception # + ; # (privileged instruction) # + ; ###--------------------------------------------------------### + loadi r31,back_from_exception + mtc0 r1, status ; EXCEPTION (privileged) + nop + j bad + nop + +back_from_exception: + loadi r31,good + rfe ; EXCEPTION (privileged) + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc011.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc011.e new file mode 100644 index 00000000..a2bec16a --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc011.e @@ -0,0 +1,64 @@ + +; ###----------------------------------------------------------------### +; # file : exc011.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - adel (when loading a half-word) # + ; ###--------------------------------------------------------### + +val1 .equ 0x3C +val .equ 0x10 ; adel + + .org 0x80000080 + .start it_handler + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + +it_handler: + + sw r29, 0 (r30) + sw r28, 4 (r30) + + addiu r28, r0 ,val1 + mfc0 r29,cause + nop + and r29, r29, r28 ; data address violation ? + addiu r27,r0,val + bne r29,r27, other_causes + nop + + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from EXCEPTION) # + ; # to the user program (address must be saved by the user # + ; # prior to the EXCEPTION in epc) # + ; ###--------------------------------------------------------### + +restore_return_adr: + mfc0 r31,epc + nop + addiu r31,r31,4 + j return + nop + +other_causes: j other_causes + nop + + ; ###--------------------------------------------------------### + ; # return to the interrupted program # + ; ###--------------------------------------------------------### + .org 0x800000d0 +return: + rfe + jr r31 + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc011.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc011.u new file mode 100644 index 00000000..d583aea2 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc011.u @@ -0,0 +1,51 @@ + +; ###----------------------------------------------------------------### +; # file : exc011.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - data address miss alignment (when loading a half-word) # + ; ###--------------------------------------------------------### + +adr .equ 0x40000050 ; miss aligned word address +data .equ 0x9043ad6b ; data + + .org 0x00400000 + .start init + +init: + loadi r31, back_from_exception + loadi r1 , adr ; half word's address + loadi r2 , data ; init. r2 with a data + loadi r3 , data ; init. r3 with the same value + + ; ###--------------------------------------------------------### + ; # load a half-word at a miss aligned address (data address # + ; # alignment exception) # + ; ###--------------------------------------------------------### + + lh r2 , 1 (r1 ) ; EXCEPTION (alignement) + + ; ###--------------------------------------------------------### + ; # check that the load has faild and the content of the # + ; # register has not been altered # + ; ###--------------------------------------------------------### + +back_from_exception: + ; check that the lh has failed + beq r2 ,r3, good ; jump to good if OK + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc012.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc012.e new file mode 100644 index 00000000..801fbcbe --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc012.e @@ -0,0 +1,64 @@ + +; ###----------------------------------------------------------------### +; # file : exc012.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - ades (when storing a word) # + ; ###--------------------------------------------------------### + +val1 .equ 0x3C +val .equ 0x14 ; ades + + .org 0x80000080 + .start it_handler + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + +it_handler: + + sw r29, 0 (r30) + sw r28, 4 (r30) + + addiu r28, r0 ,val1 + mfc0 r29,cause + nop + and r29, r29, r28 ; data address violation ? + addiu r27,r0,val + bne r29,r27, other_causes + nop + + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from EXCEPTION) # + ; # to the user program (address must be saved by the user # + ; # prior to the EXCEPTION in epc) # + ; ###--------------------------------------------------------### + +restore_return_adr: + mfc0 r31,epc + nop + addiu r31,r31,4 + j return + nop + +other_causes: j other_causes + nop + + ; ###--------------------------------------------------------### + ; # return to the interrupted program # + ; ###--------------------------------------------------------### + .org 0x800000d0 +return: + rfe + jr r31 + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc012.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc012.u new file mode 100644 index 00000000..cc466b5c --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc012.u @@ -0,0 +1,62 @@ + +; ###----------------------------------------------------------------### +; # file : exc012.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - data address miss alignment (storing a half-word) # + ; ###--------------------------------------------------------### + +adr .equ 0x40000050 +data .equ 0x616b ; data + + .org 0x00400000 + .start init + +init: + loadi r31, back_from_exception + loadi r1 , adr ; half word's address in r1 + loadi r2 , data ; data in r2 + loadi r3 , data ; same data in r3 + loadi r4 , data ^ 0xffffffff ; complemented data in r4 + + ; ###--------------------------------------------------------### + ; # store the word to initialize the memory location # + ; ###--------------------------------------------------------### + + sw r2, 0 (r1 ) + + ; ###--------------------------------------------------------### + ; # store half-word at a miss aligned address # + ; ###--------------------------------------------------------### + + sh r4, 1 (r1 ) ; EXCEPTION (alignment) + + ; ###--------------------------------------------------------### + ; # after returning from exception, read the memory # + ; # location and check that the faulty store word has not # + ; # modified the memory # + ; ###--------------------------------------------------------### + +back_from_exception: + lw r5 , 0 (r1 ) + + ; ###--------------------------------------------------------### + ; # if the read word is correct branch to good # + ; ###--------------------------------------------------------### + + bne r5, r3,bad + nop + j good + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc013.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc013.e new file mode 100644 index 00000000..39fda2b4 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc013.e @@ -0,0 +1,68 @@ + +; ###----------------------------------------------------------------### +; # file : exc013.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - sleep # + ; ###--------------------------------------------------------### + +val1 .equ 0x3C + +system_stack .equ 0xC0000000 ; system stack address + +user_prog .equ 0x00400000 +val .equ 0x28 ; ri + + .org 0x80000080 + .start it_handler + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + +it_handler: + + sw r29, 0 (r30) + sw r28, 4 (r30) + + addiu r28, r0 ,val1 + mfc0 r29,cause + nop + and r29, r29, r28 ; data address violation ? + addiu r27,r0,val + bne r29,r27, other_causes + nop + + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from EXCEPTION) # + ; # to the user program (address must be saved by the user # + ; # prior to the EXCEPTION in epc) # + ; ###--------------------------------------------------------### + +restore_return_adr: + mfc0 r1,epc + nop + addiu r1,r1,8 + j return + nop + +other_causes: j other_causes + nop + + ; ###--------------------------------------------------------### + ; # return to the interrupted program # + ; ###--------------------------------------------------------### + .org 0x800000d0 +return: + rfe + jr r1 + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc013.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc013.u new file mode 100644 index 00000000..cd6fe5cc --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc013.u @@ -0,0 +1,41 @@ + +; ###----------------------------------------------------------------### +; # file : exc013.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - illegal instruction (when executing a sleep) # + ; ###--------------------------------------------------------### + + .org 0x00400000 + .start init + +init: + + ; ###--------------------------------------------------------### + ; # Put the processor in SLEEP mode. This must generate an # + ; # exception (privileged instruction) # + ; ###--------------------------------------------------------### + + nop + sleep ; EXCEPTION (privileged) + + j bad + nop + + +back_from_exception: + j good + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc014.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc014.e new file mode 100644 index 00000000..d2b3ebdf --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc014.e @@ -0,0 +1,60 @@ +; ###----------------------------------------------------------------### +; # file : exc014.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - data bus error # + ; ###--------------------------------------------------------### + +val1 .equ 0x3C ; exc mask +val .equ 0x1C ; data bus error + + .org 0x80000080 + .start it_handler + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + +it_handler: + + sw r29, 0 (r30) + sw r28, 4 (r30) + + addiu r28,r0,val1 + mfc0 r29,cause + nop + and r29, r29, r28 ; data bus error ? + addiu r27,r0,val + bne r29,r27, other_causes + nop + + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from EXCEPTION) # + ; ###--------------------------------------------------------### + +restore_return_adr: + mfc0 r31,epc + nop + addiu r31,r31,4 + j return + nop + +other_causes: j other_causes + nop + + ; ###--------------------------------------------------------### + ; # return to the interrupted program # + ; ###--------------------------------------------------------### + .org 0x800000d0 +return: + rfe + jr r31 + + .end diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc014.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc014.u new file mode 100644 index 00000000..34ba44ab --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc014.u @@ -0,0 +1,50 @@ + +; ###----------------------------------------------------------------### +; # file : exc014.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - data bus error (when loading a word) # + ; ###--------------------------------------------------------### + +adr .equ 0x400000C8 ; data bus error address +data .equ 0x9043ad6b ; data + + .org 0x00400000 + .start init + +init: + loadi r1 , adr ; word's address + loadi r2 , data ; init. r2 with a data + loadi r3 , data ; init. r3 with the same value + + ; ###--------------------------------------------------------### + ; # load a word and dbe low (data bus error exception) # + ; # berr is driven by mips_dec.vbe... # + ; ###--------------------------------------------------------### + + lw r2 , 0 (r1 ) ; EXCEPTION (data bus error) + nop + + ; ###--------------------------------------------------------### + ; # check that the load has faild and the content of the # + ; # register has not been altered # + ; ###--------------------------------------------------------### + +back_from_exception: + beq r3 ,r2, good + nop + j bad + nop + + .org 0x004000D0 +good: j good + nop + .org 0x004000D8 +bad: j bad + nop + + .end diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc015.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc015.e new file mode 100644 index 00000000..53ab3b51 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc015.e @@ -0,0 +1,66 @@ + +; ###----------------------------------------------------------------### +; # file : exc015.s # +; # date : Mar 26 1996 # +; # descr. : functional test for dlx # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - overflow (when adding positive numbers) # + ; ###--------------------------------------------------------### + +val1 .equ 0x3C ; arithmetic overflow + +user_prog .equ 0x00400000 +val .equ 0x30 + + .org 0x80000080 + .start it_handler + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + +it_handler: + + sw r29, 0 (r30) + sw r28, 4 (r30) + + addiu r28, r0 ,val1 + mfc0 r29,cause + nop + and r29, r29, r28 ; data address violation ? + addiu r27,r0,val + bne r29,r27, other_causes + nop + + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from EXCEPTION) # + ; # to the user program (address must be saved by the user # + ; # prior to the EXCEPTION in epc) # + ; ###--------------------------------------------------------### + +restore_return_adr: + mfc0 r1,epc + nop + addiu r1,r1,4 + j return + nop + +other_causes: j other_causes + nop + + ; ###--------------------------------------------------------### + ; # return to the interrupted program # + ; ###--------------------------------------------------------### + .org 0x800000d0 +return: + rfe + jr r1 + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc015.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc015.u new file mode 100644 index 00000000..b7d484c8 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc015.u @@ -0,0 +1,46 @@ + +; ###----------------------------------------------------------------### +; # file : exc015.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - overflow (when adding positive numbers) # + ; ###--------------------------------------------------------### + +data .equ 0x7FFFFFFF; a big positive data +imd_data .equ 0x6234 + + .org 0x00400000 + .start init + +init: + loadi r10, data ; big positive data in r10 + loadi r11, data ; same data in r11 + + ; ###--------------------------------------------------------### + ; # addition generating an overflow # + ; ###--------------------------------------------------------### + + addi r10, r10, imd_data ; EXCEPTION (overflow) + + ; ###--------------------------------------------------------### + ; # after returning from exception check that r10 has not # + ; # been altered # + ; ###--------------------------------------------------------### + +back_from_exception: + beq r10, r11, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc016.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc016.e new file mode 100644 index 00000000..65641787 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc016.e @@ -0,0 +1,66 @@ + +; ###----------------------------------------------------------------### +; # file : exc016.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - overflow (when adding positive numbers) # + ; ###--------------------------------------------------------### + +val1 .equ 0x3C ; arithmetic overflow + +user_prog .equ 0x00400000 +val .equ 0x30 + + .org 0x80000080 + .start it_handler + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + +it_handler: + + sw r29, 0 (r30) + sw r28, 4 (r30) + + addi r28, r0 ,val1 + mfc0 r29,cause + nop + and r29, r29, r28 ; data address violation ? + addiu r27,r0,val + bne r29,r27, other_causes + nop + + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from EXCEPTION) # + ; # to the user program (address must be saved by the user # + ; # prior to the EXCEPTION in epc) # + ; ###--------------------------------------------------------### + +restore_return_adr: + mfc0 r1,epc + nop + addiu r1,r1,4 + j return + nop + +other_causes: j other_causes + nop + + ; ###--------------------------------------------------------### + ; # return to the interrupted program # + ; ###--------------------------------------------------------### + .org 0x800000d0 +return: + rfe + jr r1 + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc016.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc016.u new file mode 100644 index 00000000..3f86271d --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc016.u @@ -0,0 +1,46 @@ + +; ###----------------------------------------------------------------### +; # file : exc016.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - overflow (when adding negative numbers) # + ; ###--------------------------------------------------------### + +data .equ 0xb2305ec0 ; a big negative data + + .org 0x00400000 + .start init + +init: + loadi r31, back_from_exception + loadi r10, data ; big positive data in r10 + loadi r11, data ; same data in r11 + + ; ###--------------------------------------------------------### + ; # addtion generating an overflow # + ; ###--------------------------------------------------------### + + add r10, r10, r10 ; EXCEPTION (overflow) + + ; ###--------------------------------------------------------### + ; # after returning from exception check that r10 has not # + ; # been altered # + ; ###--------------------------------------------------------### + +back_from_exception: + bne r10,r11, bad + nop + j good + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc017.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc017.e new file mode 100644 index 00000000..67ea40d8 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc017.e @@ -0,0 +1,61 @@ +; ###----------------------------------------------------------------### +; # file : exc017.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - data bus error # + ; ###--------------------------------------------------------### + +val1 .equ 0x3C ; exc mask +val .equ 0x1C ; data bus error + + .org 0x80000080 + .start it_handler + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + +it_handler: + + sw r29, 0 (r30) + sw r28, 4 (r30) + + addiu r28,r0,val1 + mfc0 r29,cause + nop + and r29, r29, r28 ; data bus error ? + addiu r27,r0,val + bne r29,r27, other_causes + nop + + addu r3 , r0, r2 + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from EXCEPTION) # + ; ###--------------------------------------------------------### + +restore_return_adr: + mfc0 r31,epc + nop + addiu r31,r31,4 + j return + nop + +other_causes: j other_causes + nop + + ; ###--------------------------------------------------------### + ; # return to the interrupted program # + ; ###--------------------------------------------------------### + .org 0x800000d0 +return: + rfe + jr r31 + + .end diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc017.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc017.u new file mode 100644 index 00000000..1a71da30 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc017.u @@ -0,0 +1,49 @@ + +; ###----------------------------------------------------------------### +; # file : exc017.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - data bus error (when storing a word) # + ; ###--------------------------------------------------------### + +adr .equ 0x400000C8 ; data bus error address +data .equ 0x9043ad6b ; data + + .org 0x00400000 + .start init + +init: + loadi r1 , adr ; word's address + loadi r2 , data ; init. r2 with a data + + ; ###--------------------------------------------------------### + ; # store a word and dbe low (data bus error exception) # + ; # berr is driven by mips_dec.vbe... # + ; ###--------------------------------------------------------### + + sw r2, 0 (r1 ) ; EXCEPTION (data bus error) + nop + + ; ###--------------------------------------------------------### + ; # If exception has been trapped, exception handler had # + ; # copy r2 in r3. # + ; ###--------------------------------------------------------### + +back_from_exception: + beq r3 ,r2, good + nop + j bad + nop + + .org 0x004000D0 +good: j good + nop + .org 0x004000D8 +bad: j bad + nop + + .end diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc018.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc018.e new file mode 100644 index 00000000..9c89f69e --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc018.e @@ -0,0 +1,60 @@ +; ###----------------------------------------------------------------### +; # file : exc018.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - data bus error # + ; ###--------------------------------------------------------### + +val1 .equ 0x3C ; exc mask +val .equ 0x1C ; data bus error + + .org 0x80000080 + .start it_handler + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + +it_handler: + + sw r29, 0 (r30) + sw r28, 4 (r30) + + addiu r28,r0,val1 + mfc0 r29,cause + nop + and r29, r29, r28 ; data bus error ? + addiu r27,r0,val + bne r29,r27, other_causes + nop + + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from EXCEPTION) # + ; ###--------------------------------------------------------### + +restore_return_adr: + mfc0 r31,epc + nop + addiu r31,r31,4 + j return + nop + +other_causes: j other_causes + nop + + ; ###--------------------------------------------------------### + ; # return to the interrupted program # + ; ###--------------------------------------------------------### + .org 0x800000d0 +return: + rfe + jr r31 + + .end diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc018.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc018.u new file mode 100644 index 00000000..213545f0 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc018.u @@ -0,0 +1,50 @@ + +; ###----------------------------------------------------------------### +; # file : exc018.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - data bus error (when loading a half) # + ; ###--------------------------------------------------------### + +adr .equ 0x400000C8 ; data bus error address +data .equ 0x9043ad6b ; data + + .org 0x00400000 + .start init + +init: + loadi r1 , adr ; word's address + loadi r2 , data ; init. r2 with a data + loadi r3 , data ; init. r3 with the same value + + ; ###--------------------------------------------------------### + ; # load an half and dbe low (data bus error exception) # + ; # berr is driven by mips_dec.vbe... # + ; ###--------------------------------------------------------### + + lh r2 , 0 (r1 ) ; EXCEPTION (data bus error) + nop + + ; ###--------------------------------------------------------### + ; # check that the load has faild and the content of the # + ; # register has not been altered # + ; ###--------------------------------------------------------### + +back_from_exception: + beq r3 ,r2, good + nop + j bad + nop + + .org 0x004000D0 +good: j good + nop + .org 0x004000D8 +bad: j bad + nop + + .end diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc019.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc019.e new file mode 100644 index 00000000..a17f9890 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc019.e @@ -0,0 +1,60 @@ +; ###----------------------------------------------------------------### +; # file : exc019.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - data bus error # + ; ###--------------------------------------------------------### + +val1 .equ 0x3C ; exc mask +val .equ 0x1C ; data bus error + + .org 0x80000080 + .start it_handler + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + +it_handler: + + sw r29, 0 (r30) + sw r28, 4 (r30) + + addiu r28,r0,val1 + mfc0 r29,cause + nop + and r29, r29, r28 ; data bus error ? + addiu r27,r0,val + bne r29,r27, other_causes + nop + + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from EXCEPTION) # + ; ###--------------------------------------------------------### + +restore_return_adr: + mfc0 r31,epc + nop + addiu r31,r31,4 + j return + nop + +other_causes: j other_causes + nop + + ; ###--------------------------------------------------------### + ; # return to the interrupted program # + ; ###--------------------------------------------------------### + .org 0x800000d0 +return: + rfe + jr r31 + + .end diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc019.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc019.u new file mode 100644 index 00000000..0c3c28f4 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc019.u @@ -0,0 +1,50 @@ + +; ###----------------------------------------------------------------### +; # file : exc019.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - data bus error (when loading an unsigned half) # + ; ###--------------------------------------------------------### + +adr .equ 0x400000C8 ; data bus error address +data .equ 0x9043ad6b ; data + + .org 0x00400000 + .start init + +init: + loadi r1 , adr ; word's address + loadi r2 , data ; init. r2 with a data + loadi r3 , data ; init. r3 with the same value + + ; ###--------------------------------------------------------### + ; # load an unsigned half and dbe low (data bus error # + ; # exception) berr is driven by mips_dec.vbe... # + ; ###--------------------------------------------------------### + + lhu r2 , 0 (r1 ) ; EXCEPTION (data bus error) + nop + + ; ###--------------------------------------------------------### + ; # check that the load has faild and the content of the # + ; # register has not been altered # + ; ###--------------------------------------------------------### + +back_from_exception: + beq r3 ,r2, good + nop + j bad + nop + + .org 0x004000D0 +good: j good + nop + .org 0x004000D8 +bad: j bad + nop + + .end diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc020.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc020.e new file mode 100644 index 00000000..e89af742 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc020.e @@ -0,0 +1,62 @@ +; ###----------------------------------------------------------------### +; # file : exc020.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - data bus error # + ; ###--------------------------------------------------------### + +val1 .equ 0x3C ; exc mask +val .equ 0x1C ; data bus error + + .org 0x80000080 + .start it_handler + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + +it_handler: + + sw r29, 0 (r30) + sw r28, 4 (r30) + + addiu r28,r0,val1 + mfc0 r29,cause + nop + and r29, r29, r28 ; data bus error ? + addiu r27,r0,val + bne r29,r27, other_causes + nop + + addu r3 , r0 , r2 + + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from EXCEPTION) # + ; ###--------------------------------------------------------### + +restore_return_adr: + mfc0 r31,epc + nop + addiu r31,r31,4 + j return + nop + +other_causes: j other_causes + nop + + ; ###--------------------------------------------------------### + ; # return to the interrupted program # + ; ###--------------------------------------------------------### + .org 0x800000d0 +return: + rfe + jr r31 + + .end diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc020.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc020.u new file mode 100644 index 00000000..a50938e4 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc020.u @@ -0,0 +1,48 @@ + +; ###----------------------------------------------------------------### +; # file : exc020.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - data bus error (when storing an half) # + ; ###--------------------------------------------------------### + +adr .equ 0x400000C8 ; data bus error address +data .equ 0x9043ad6b ; data + + .org 0x00400000 + .start init + +init: + loadi r1 , adr ; word's address + loadi r2 , data ; init. r2 with a data + + ; ###--------------------------------------------------------### + ; # store an half and dbe low (data bus error exception) # + ; # berr is driven by mips_dec.vbe... # + ; ###--------------------------------------------------------### + + sh r2, 0 (r1 ) ; EXCEPTION (data bus error) + nop + + ; ###--------------------------------------------------------### + ; # If exception had been trapped, r2 == r3. # + ; ###--------------------------------------------------------### + +back_from_exception: + beq r3 ,r2, good + nop + j bad + nop + + .org 0x004000D0 +good: j good + nop + .org 0x004000D8 +bad: j bad + nop + + .end diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc021.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc021.e new file mode 100644 index 00000000..7e1ca7ec --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc021.e @@ -0,0 +1,60 @@ +; ###----------------------------------------------------------------### +; # file : exc021.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - data bus error # + ; ###--------------------------------------------------------### + +val1 .equ 0x3C ; exc mask +val .equ 0x1C ; data bus error + + .org 0x80000080 + .start it_handler + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + +it_handler: + + sw r29, 0 (r30) + sw r28, 4 (r30) + + addiu r28,r0,val1 + mfc0 r29,cause + nop + and r29, r29, r28 ; data bus error ? + addiu r27,r0,val + bne r29,r27, other_causes + nop + + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from EXCEPTION) # + ; ###--------------------------------------------------------### + +restore_return_adr: + mfc0 r31,epc + nop + addiu r31,r31,4 + j return + nop + +other_causes: j other_causes + nop + + ; ###--------------------------------------------------------### + ; # return to the interrupted program # + ; ###--------------------------------------------------------### + .org 0x800000d0 +return: + rfe + jr r31 + + .end diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc021.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc021.u new file mode 100644 index 00000000..fefc44b2 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc021.u @@ -0,0 +1,50 @@ + +; ###----------------------------------------------------------------### +; # file : exc021.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - data bus error (when loading a byte) # + ; ###--------------------------------------------------------### + +adr .equ 0x400000C8 ; data bus error address +data .equ 0x9043ad6b ; data + + .org 0x00400000 + .start init + +init: + loadi r1 , adr ; word's address + loadi r2 , data ; init. r2 with a data + loadi r3 , data ; init. r3 with the same value + + ; ###--------------------------------------------------------### + ; # load a word and dbe low (data bus error exception) # + ; # berr is driven by mips_dec.vbe... # + ; ###--------------------------------------------------------### + + lb r2 , 0 (r1 ) ; EXCEPTION (data bus error) + nop + + ; ###--------------------------------------------------------### + ; # check that the load has faild and the content of the # + ; # register has not been altered # + ; ###--------------------------------------------------------### + +back_from_exception: + beq r3 ,r2, good + nop + j bad + nop + + .org 0x004000D0 +good: j good + nop + .org 0x004000D8 +bad: j bad + nop + + .end diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc022.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc022.e new file mode 100644 index 00000000..f91087c2 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc022.e @@ -0,0 +1,60 @@ +; ###----------------------------------------------------------------### +; # file : exc022.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - data bus error # + ; ###--------------------------------------------------------### + +val1 .equ 0x3C ; exc mask +val .equ 0x1C ; data bus error + + .org 0x80000080 + .start it_handler + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + +it_handler: + + sw r29, 0 (r30) + sw r28, 4 (r30) + + addiu r28,r0,val1 + mfc0 r29,cause + nop + and r29, r29, r28 ; data bus error ? + addiu r27,r0,val + bne r29,r27, other_causes + nop + + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from EXCEPTION) # + ; ###--------------------------------------------------------### + +restore_return_adr: + mfc0 r31,epc + nop + addiu r31,r31,4 + j return + nop + +other_causes: j other_causes + nop + + ; ###--------------------------------------------------------### + ; # return to the interrupted program # + ; ###--------------------------------------------------------### + .org 0x800000d0 +return: + rfe + jr r31 + + .end diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc022.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc022.u new file mode 100644 index 00000000..97187052 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc022.u @@ -0,0 +1,50 @@ + +; ###----------------------------------------------------------------### +; # file : exc022.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - data bus error (when loading an unsigned bute) # + ; ###--------------------------------------------------------### + +adr .equ 0x400000C8 ; data bus error address +data .equ 0x9043ad6b ; data + + .org 0x00400000 + .start init + +init: + loadi r1 , adr ; word's address + loadi r2 , data ; init. r2 with a data + loadi r3 , data ; init. r3 with the same value + + ; ###--------------------------------------------------------### + ; # load a word and dbe low (data bus error exception) # + ; # berr is driven by mips_dec.vbe... # + ; ###--------------------------------------------------------### + + lbu r2 , 0 (r1 ) ; EXCEPTION (data bus error) + nop + + ; ###--------------------------------------------------------### + ; # check that the load has faild and the content of the # + ; # register has not been altered # + ; ###--------------------------------------------------------### + +back_from_exception: + beq r3 ,r2, good + nop + j bad + nop + + .org 0x004000D0 +good: j good + nop + .org 0x004000D8 +bad: j bad + nop + + .end diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc023.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc023.e new file mode 100644 index 00000000..4a8ad5e5 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc023.e @@ -0,0 +1,62 @@ +; ###----------------------------------------------------------------### +; # file : exc023.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - data bus error # + ; ###--------------------------------------------------------### + +val1 .equ 0x3C ; exc mask +val .equ 0x1C ; data bus error + + .org 0x80000080 + .start it_handler + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + +it_handler: + + sw r29, 0 (r30) + sw r28, 4 (r30) + + addiu r28,r0,val1 + mfc0 r29,cause + nop + and r29, r29, r28 ; data bus error ? + addiu r27,r0,val + bne r29,r27, other_causes + nop + + addu r3 , r0 , r2 + + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from EXCEPTION) # + ; ###--------------------------------------------------------### + +restore_return_adr: + mfc0 r31,epc + nop + addiu r31,r31,4 + j return + nop + +other_causes: j other_causes + nop + + ; ###--------------------------------------------------------### + ; # return to the interrupted program # + ; ###--------------------------------------------------------### + .org 0x800000d0 +return: + rfe + jr r31 + + .end diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc023.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc023.u new file mode 100644 index 00000000..a0b7304e --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc023.u @@ -0,0 +1,49 @@ + +; ###----------------------------------------------------------------### +; # file : exc023.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - data bus error (when storing a byte) # + ; ###--------------------------------------------------------### + +adr .equ 0x400000C8 ; data bus error address +data .equ 0x9043ad6b ; data + + .org 0x00400000 + .start init + +init: + loadi r1 , adr ; word's address + loadi r2 , data ; init. r2 with a data + + ; ###--------------------------------------------------------### + ; # store a byte and dbe low (data bus error exception) # + ; # berr is driven by mips_dec.vbe... # + ; ###--------------------------------------------------------### + + sb r2, 0 (r1 ) ; EXCEPTION (data bus error) + nop + + ; ###--------------------------------------------------------### + ; # check that the load has faild and the content of the # + ; # register has not been altered # + ; ###--------------------------------------------------------### + +back_from_exception: + beq r3 ,r2, good + nop + j bad + nop + + .org 0x004000D0 +good: j good + nop + .org 0x004000D8 +bad: j bad + nop + + .end diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc024.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc024.e new file mode 100644 index 00000000..b76f9ff4 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc024.e @@ -0,0 +1,53 @@ +; ###----------------------------------------------------------------### +; # file : exc024.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - instruction bus error # + ; ###--------------------------------------------------------### + +xcode_mask .equ 0x3C ; exc mask +xcode_ibe .equ 0x18 ; instruction bus error + + .org 0x80000080 + .start it_handler + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + +it_handler: + + sw r29, 0 (r30) + sw r28, 4 (r30) + + mfc0 r29,cause + nop + addiu r28,r0,xcode_mask + and r29, r29, r28 ; instruction bus error ? + addiu r27,r0,xcode_ibe + bne r29,r27, other_causes + nop + + lw r29, 0 (r30) + lw r28, 4 (r30) + +restore_return_adr: + j return + nop + +other_causes: j other_causes + nop + + ; ###--------------------------------------------------------### + ; # return to the interrupted program # + ; ###--------------------------------------------------------### + .org 0x800000d0 +return: + rfe + jr r31 + + .end diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc024.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc024.u new file mode 100644 index 00000000..5d1fba65 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/exc024.u @@ -0,0 +1,40 @@ + +; ###----------------------------------------------------------------### +; # file : exc024.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - instruction bus error # + ; ###--------------------------------------------------------### + +adr .equ 0x400000C8 ; bus error address + + .org 0x00400000 + .start init + +init: + loadi r31 , good + + ; ###--------------------------------------------------------### + ; # jump at adr and dbe low (instruction bus error exception)# + ; # berr is driven by mips_dec.vbe... # + ; ###--------------------------------------------------------### + + loadi r1, adr + jr r1 ; EXCEPTION (instruction bus error) + nop + + j bad + nop + + .org 0x004000D0 +good: j good + nop + .org 0x004000D8 +bad: j bad + nop + + .end diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/foo.vbe b/alliance/src/documentation/alliance-examples/mipsR3000/asm/foo.vbe new file mode 100644 index 00000000..573fb7bf --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/foo.vbe @@ -0,0 +1,25 @@ +entity foo is + port ( + address : in bit_vector (5 downto 0); + e_n : in bit; + data : out mux_vector (7 downto 0) bus; + vdd : in bit; + vss : in bit); +end foo; + +architecture VBE of foo is + + signal rom_out : bit_vector (7 downto 0); + +begin + + write_out : block (e_n = '0') + begin + data <= guarded rom_out; + end block; + + with address (5 downto 0) select + rom_out <= + X"00" when others; + +end; diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/go-all.sh b/alliance/src/documentation/alliance-examples/mipsR3000/asm/go-all.sh new file mode 100755 index 00000000..238eede8 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/go-all.sh @@ -0,0 +1,9 @@ +#!/bin/sh + +for I in *0*.u +do + BENCH=`basename $I .u` + echo $BENCH + ./go-bench.sh $BENCH +done + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/go-bench.sh b/alliance/src/documentation/alliance-examples/mipsR3000/asm/go-bench.sh new file mode 100755 index 00000000..800a0590 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/go-bench.sh @@ -0,0 +1,157 @@ +#!/bin/sh + +LOG_RES=/tmp/res_mips_"$$" +LOG_MSG=/tmp/msg_mips_"$$" + +if [ $# -lt 1 ]; then + echo "usage: $0 " + exit 1 +fi +if [ ! -f $1.u ]; then + echo "error: can't find '$1.u'" + exit 1 +fi + +TOP=$ALLIANCE_TOP +MBK_CATA_LIB=.:$TOP/cells/sclib:$TOP/cells/sxlib:$TOP/cells/padlib:$TOP/cells/dplib:$TOP/cells/dp_sxlib +MBK_CATA_LIB=$MBK_CATA_LIB:$TOP/cells/fplib:$TOP/cells/rfg:$TOP/cells/dplib:$TOP/cells/rflib +MBK_CATA_LIB=$MBK_CATA_LIB:../sce/ +export MBK_CATA_LIB +MBK_IN_LO=vst +export MBK_IN_LO + +rm -f $LOG_RES $LOG_MSG + +echo "################# ---- Test de : $1 ---- #################" + +if [ -f $1.e ]; then + cp -f $1.e rome.e + $TOP/bin/mips_asm rome.e rome foo 1> /dev/null +fi + +if [ -f $1.u ]; then + cp -f $1.u romu.u + $TOP/bin/mips_asm romu.u romu foo 1> /dev/null +fi + + + +$TOP/bin/asimut -zerodelay -i 0 -bdd -p 100 mips_cpu mips_cpu $1 1> $LOG_MSG 2> $LOG_RES + +#asimut -zerodelay -bdd -p 100 mips_cpu mips_cpu $1 2>$LOG_RES + +#asimut -zerodelay -bdd -p 100 mips_cpu mips_cpu $1 + + + +grep -i bad $LOG_RES >/dev/null + +#grep -i bad $LOG_RES + +if [ $? -eq 0 ] ; then + echo "ERROR !" +fi + + +grep -i good $LOG_RES > /dev/null + +#grep -i good $LOG_RES + +if [ $? -eq 0 ] ; then + echo "No error, you're lucky !" +fi + + + + +grep -i "No such file or directory" $LOG_RES > /dev/null + +if [ $? -eq 0 ] ; then + echo "================= By jove ! a file is missing (asimut) ... ============== " + grep -i "No such file or directory" $LOG_RES +fi + + +grep -i "No such file or directory" $LOG_MSG > /dev/null + +if [ $? -eq 0 ] ; then + echo "================= By jove ! Il manque un fichier (asimut) ... ============== " + grep -i "No such file or directory" $LOG_MSG +fi + + + + +grep -i "core dump" $LOG_RES > /dev/null + +if [ $? -eq 0 ] ; then + echo "================= core dump (asimut) ... ========= " +fi + +grep -i "core dump" $LOG_MSG > /dev/null + +if [ $? -eq 0 ] ; then + echo "================= core dump (asimut) ... ========= " +fi + + + +grep "Error" $LOG_RES > /dev/null + +if [ $? -eq 0 ] ; then + echo "================= Error (asimut) ... ==== " + grep -i "Error" $LOG_RES +fi + +grep "Error" $LOG_MSG > /dev/null + +if [ $? -eq 0 ] ; then + echo "================= Error ! (asimut) ... ==== " + grep -i "Error" $LOG_MSG +fi + + + +grep "can't open file" $LOG_RES > /dev/null + +if [ $? -eq 0 ] ; then + echo "================= A file is missing (asimut) ... ========== " + grep -i "can't open file" $LOG_RES +fi + +grep "can't open file" $LOG_MSG > /dev/null + +if [ $? -eq 0 ] ; then + echo "================= A file is missing (asimut) ... ========== " + grep -i "can't open file" $LOG_MSG +fi + + + +grep "exception occured" $LOG_RES > /dev/null + +if [ $? -eq 0 ] ; then +grep "exc" $1.u > /dev/null +if [ ! $? -eq 0 ] ; then + echo "================= Exception (asimut) ... ======== " +fi +fi + +grep "exception occured" $LOG_MSG > /dev/null + +if [ $? -eq 0 ] ; then +grep "exc" $1.u > /dev/null +if [ ! $? -eq 0 ] ; then + echo "================= Exception (asimut) ... ======== " +fi +fi + +rm -f toto.vbe +rm -f romu.u +rm -f rome.e +rm -f $LOG_RES +rm -f $LOG_MSG + + + + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/it000.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/it000.e new file mode 100644 index 00000000..a7bef7cd --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/it000.e @@ -0,0 +1,73 @@ +; ###----------------------------------------------------------------### +; # file : it000.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # hardware interrupt # + ; ###--------------------------------------------------------### + +hardware_it0 .equ 0x00000400 +hardware_it1 .equ 0x00000800 +hardware_it2 .equ 0x00001000 +hardware_it3 .equ 0x00002000 +hardware_it4 .equ 0x00004000 +hardware_it5 .equ 0x00008000 + +timer_0 .equ 0x40000100 +timer_1 .equ 0x40000104 +timer_2 .equ 0x40000108 +timer_3 .equ 0x4000010C +timer_4 .equ 0x40000110 +timer_5 .equ 0x40000114 +timer_rst .equ 0x40000118 +timer_sts .equ 0x4000011C + + .org 0x80000080 + .start handler_body + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + + +handler_body: + sw r29, 0 (r30) + sw r28, 4 (r30) + + loadi r28, hardware_it0 + mfc0 r29, cause + nop + and r29, r29, r28 ; hardware interrupt 0 ? + bne r29, r28,other_causes + nop + ; ###---------------------------------------------### + ; # On releve la ligne it # + ; ###---------------------------------------------### + loadi r28, timer_sts + sw r0, 0(r28) + + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from INTERRUPT) # + ; # to the user program (address must be saved by the user # + ; # prior to the EXCEPTION in r31) # + ; ###--------------------------------------------------------### + +return: + rfe ; return from exception + jr r31 + +other_causes: j other_causes + nop + + ; ###--------------------------------------------------------### + ; # return to the interrupted program # + ; ###--------------------------------------------------------### + + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/it000.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/it000.u new file mode 100644 index 00000000..f5f25b81 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/it000.u @@ -0,0 +1,56 @@ +; ###----------------------------------------------------------------### +; # file : it000.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # decrementation loop (with a hardware interrupt) # + ; ###--------------------------------------------------------### + +timer_0 .equ 0x40000100 +timer_1 .equ 0x40000104 +timer_2 .equ 0x40000108 +timer_3 .equ 0x4000010C +timer_4 .equ 0x40000110 +timer_5 .equ 0x40000114 +timer_rst .equ 0x40000118 +timer_sts .equ 0x4000011C + +value .equ 0x0008 +v_sts .equ 0x0001 + + .org 0x00400000 + .start init + +init: + loadi r31, back_from_int + loadi r1 , timer_0 + addiu r2 , r0 , value + sw r2,0(r1) + loadi r1 , timer_sts + addiu r2 , r0 , v_sts + sw r2, 0(r1) + + addiu r10, r0 , v_sts + lui r20, 0xffff + addiu r16, r0 , 0xfffa + or r20, r16, r20 +loop: + addu r20,r10,r20 + bne r20,r0, loop + nop + j bad + nop + +back_from_int: + j good + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/it001.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/it001.e new file mode 100644 index 00000000..21607bb2 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/it001.e @@ -0,0 +1,73 @@ +; ###----------------------------------------------------------------### +; # file : it001.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # hardware interrupt # + ; ###--------------------------------------------------------### + +hardware_it0 .equ 0x00000400 +hardware_it1 .equ 0x00000800 +hardware_it2 .equ 0x00001000 +hardware_it3 .equ 0x00002000 +hardware_it4 .equ 0x00004000 +hardware_it5 .equ 0x00008000 + +timer_0 .equ 0x40000100 +timer_1 .equ 0x40000104 +timer_2 .equ 0x40000108 +timer_3 .equ 0x4000010C +timer_4 .equ 0x40000110 +timer_5 .equ 0x40000114 +timer_rst .equ 0x40000118 +timer_sts .equ 0x4000011C + + .org 0x80000080 + .start handler_body + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + + +handler_body: + sw r29, 0 (r30) + sw r28, 4 (r30) + + loadi r28, hardware_it1 + mfc0 r29, cause + nop + and r29, r29, r28 ; hardware interrupt 1 ? + bne r29, r28,other_causes + nop + ; ###---------------------------------------------### + ; # On releve la ligne it # + ; ###---------------------------------------------### + loadi r28, timer_sts + sw r0, 0(r28) + + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from INTERRUPT) # + ; # to the user program (address must be saved by the user # + ; # prior to the EXCEPTION in r31) # + ; ###--------------------------------------------------------### + +return: + rfe ; return from exception + jr r31 + +other_causes: j other_causes + nop + + ; ###--------------------------------------------------------### + ; # return to the interrupted program # + ; ###--------------------------------------------------------### + + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/it001.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/it001.u new file mode 100644 index 00000000..3d0786a5 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/it001.u @@ -0,0 +1,56 @@ +; ###----------------------------------------------------------------### +; # file : it001.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # decrementation loop (with a hardware interrupt) # + ; ###--------------------------------------------------------### + +timer_0 .equ 0x40000100 +timer_1 .equ 0x40000104 +timer_2 .equ 0x40000108 +timer_3 .equ 0x4000010C +timer_4 .equ 0x40000110 +timer_5 .equ 0x40000114 +timer_rst .equ 0x40000118 +timer_sts .equ 0x4000011C + +value .equ 0x0008 +v_sts .equ 0x0002 + + .org 0x00400000 + .start init + +init: + loadi r31, back_from_int + loadi r1 , timer_1 + addiu r2 , r0 , value + sw r2, 0(r1) + loadi r1 , timer_sts + addiu r2 , r0 , v_sts + sw r2, 0(r1) + + addiu r10, r0 , 0x0001 + lui r20, 0xffff + addiu r16, r0, 0xfffb + or r20, r20, r16 +loop: + addu r20,r10,r20 + bne r20,r10, loop + nop + j bad + nop + +back_from_int: + j good + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/it002.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/it002.e new file mode 100644 index 00000000..0777cd3f --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/it002.e @@ -0,0 +1,73 @@ +; ###----------------------------------------------------------------### +; # file : it002.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # hardware interrupt # + ; ###--------------------------------------------------------### + +hardware_it0 .equ 0x00000400 +hardware_it1 .equ 0x00000800 +hardware_it2 .equ 0x00001000 +hardware_it3 .equ 0x00002000 +hardware_it4 .equ 0x00004000 +hardware_it5 .equ 0x00008000 + +timer_0 .equ 0x40000100 +timer_1 .equ 0x40000104 +timer_2 .equ 0x40000108 +timer_3 .equ 0x4000010C +timer_4 .equ 0x40000110 +timer_5 .equ 0x40000114 +timer_rst .equ 0x40000118 +timer_sts .equ 0x4000011C + + .org 0x80000080 + .start handler_body + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + + +handler_body: + sw r29, 0 (r30) + sw r28, 4 (r30) + + loadi r28, hardware_it2 + mfc0 r29, cause + nop + and r29, r29, r28 ; hardware interrupt 2 ? + bne r29, r28,other_causes + nop + ; ###---------------------------------------------### + ; # On releve la ligne it # + ; ###---------------------------------------------### + loadi r28, timer_sts + sw r0, 0(r28) + + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from INTERRUPT) # + ; # to the user program (address must be saved by the user # + ; # prior to the EXCEPTION in r31) # + ; ###--------------------------------------------------------### + +return: + rfe ; return from exception + jr r31 + +other_causes: j other_causes + nop + + ; ###--------------------------------------------------------### + ; # return to the interrupted program # + ; ###--------------------------------------------------------### + + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/it002.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/it002.u new file mode 100644 index 00000000..7cac0a87 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/it002.u @@ -0,0 +1,56 @@ +; ###----------------------------------------------------------------### +; # file : it002.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # decrementation loop (with a hardware interrupt) # + ; ###--------------------------------------------------------### + +timer_0 .equ 0x40000100 +timer_1 .equ 0x40000104 +timer_2 .equ 0x40000108 +timer_3 .equ 0x4000010C +timer_4 .equ 0x40000110 +timer_5 .equ 0x40000114 +timer_rst .equ 0x40000118 +timer_sts .equ 0x4000011C + +value .equ 0x0008 +v_sts .equ 0x0004 + + .org 0x00400000 + .start init + +init: + loadi r31, back_from_int + loadi r1 , timer_2 + addiu r2 , r0 , value + sw r2, 0(r1) + loadi r1 , timer_sts + addiu r2 , r0 , v_sts + sw r2, 0(r1) + + addiu r10, r0 , 0x0001 + lui r20, 0xffff + addiu r16, r0, 0xfffa + or r20, r20, r16 +loop: + addu r20,r10,r20 + bne r20,r0, loop + nop + j bad + nop + +back_from_int: + j good + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/it003.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/it003.e new file mode 100644 index 00000000..c8ed867f --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/it003.e @@ -0,0 +1,73 @@ +; ###----------------------------------------------------------------### +; # file : it003.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # hardware interrupt # + ; ###--------------------------------------------------------### + +hardware_it0 .equ 0x00000400 +hardware_it1 .equ 0x00000800 +hardware_it2 .equ 0x00001000 +hardware_it3 .equ 0x00002000 +hardware_it4 .equ 0x00004000 +hardware_it5 .equ 0x00008000 + +timer_0 .equ 0x40000100 +timer_1 .equ 0x40000104 +timer_2 .equ 0x40000108 +timer_3 .equ 0x4000010C +timer_4 .equ 0x40000110 +timer_5 .equ 0x40000114 +timer_rst .equ 0x40000118 +timer_sts .equ 0x4000011C + + .org 0x80000080 + .start handler_body + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + + +handler_body: + sw r29, 0 (r30) + sw r28, 4 (r30) + + loadi r28, hardware_it3 + mfc0 r29, cause + nop + and r29, r29, r28 ; hardware interrupt 3 ? + bne r29, r28,other_causes + nop + ; ###---------------------------------------------### + ; # On releve la ligne it # + ; ###---------------------------------------------### + loadi r28, timer_sts + sw r0, 0(r28) + + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from INTERRUPT) # + ; # to the user program (address must be saved by the user # + ; # prior to the EXCEPTION in r31) # + ; ###--------------------------------------------------------### + +return: + rfe ; return from exception + jr r31 + +other_causes: j other_causes + nop + + ; ###--------------------------------------------------------### + ; # return to the interrupted program # + ; ###--------------------------------------------------------### + + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/it003.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/it003.u new file mode 100644 index 00000000..3ecc138e --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/it003.u @@ -0,0 +1,56 @@ +; ###----------------------------------------------------------------### +; # file : it003.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # decrementation loop (with a hardware interrupt) # + ; ###--------------------------------------------------------### + +timer_0 .equ 0x40000100 +timer_1 .equ 0x40000104 +timer_2 .equ 0x40000108 +timer_3 .equ 0x4000010C +timer_4 .equ 0x40000110 +timer_5 .equ 0x40000114 +timer_rst .equ 0x40000118 +timer_sts .equ 0x4000011C + +value .equ 0x0008 +v_sts .equ 0x0008 + + .org 0x00400000 + .start init + +init: + loadi r31, back_from_int + loadi r1 , timer_3 + addiu r2 , r0 , value + sw r2, 0(r1) + loadi r1 , timer_sts + addiu r2 , r0 , v_sts + sw r2, 0(r1) + + addiu r10, r0 , 0x0001 + lui r20, 0xffff + addiu r16, r0, 0xfffa + or r20, r20, r16 +loop: + addu r20,r10,r20 + bne r20,r0, loop + nop + j bad + nop + +back_from_int: + j good + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/it004.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/it004.e new file mode 100644 index 00000000..0b5b9850 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/it004.e @@ -0,0 +1,73 @@ +; ###----------------------------------------------------------------### +; # file : it004.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # hardware interrupt # + ; ###--------------------------------------------------------### + +hardware_it0 .equ 0x00000400 +hardware_it1 .equ 0x00000800 +hardware_it2 .equ 0x00001000 +hardware_it3 .equ 0x00002000 +hardware_it4 .equ 0x00004000 +hardware_it5 .equ 0x00008000 + +timer_0 .equ 0x40000100 +timer_1 .equ 0x40000104 +timer_2 .equ 0x40000108 +timer_3 .equ 0x4000010C +timer_4 .equ 0x40000110 +timer_5 .equ 0x40000114 +timer_rst .equ 0x40000118 +timer_sts .equ 0x4000011C + + .org 0x80000080 + .start handler_body + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + + +handler_body: + sw r29, 0 (r30) + sw r28, 4 (r30) + + loadi r28, hardware_it4 + mfc0 r29, cause + nop + and r29, r29, r28 ; hardware interrupt 4 ? + bne r29, r28,other_causes + nop + ; ###---------------------------------------------### + ; # On releve la ligne it # + ; ###---------------------------------------------### + loadi r28, timer_sts + sw r0, 0(r28) + + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from INTERRUPT) # + ; # to the user program (address must be saved by the user # + ; # prior to the EXCEPTION in r31) # + ; ###--------------------------------------------------------### + +return: + rfe ; return from exception + jr r31 + +other_causes: j other_causes + nop + + ; ###--------------------------------------------------------### + ; # return to the interrupted program # + ; ###--------------------------------------------------------### + + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/it004.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/it004.u new file mode 100644 index 00000000..5efa1638 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/it004.u @@ -0,0 +1,56 @@ +; ###----------------------------------------------------------------### +; # file : it004.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # decrementation loop (with a hardware interrupt) # + ; ###--------------------------------------------------------### + +timer_0 .equ 0x40000100 +timer_1 .equ 0x40000104 +timer_2 .equ 0x40000108 +timer_3 .equ 0x4000010C +timer_4 .equ 0x40000110 +timer_5 .equ 0x40000114 +timer_rst .equ 0x40000118 +timer_sts .equ 0x4000011C + +value .equ 0x0008 +v_sts .equ 0x0010 + + .org 0x00400000 + .start init + +init: + loadi r31, back_from_int + loadi r1 , timer_4 + addiu r2 , r0 , value + sw r2, 0(r1) + loadi r1 , timer_sts + addiu r2 , r0 , v_sts + sw r2, 0(r1) + + addiu r10, r0 , 0x0001 + lui r20, 0xffff + addiu r16, r0, 0xfffa + or r20, r20, r16 +loop: + addu r20,r10,r20 + bne r20,r0, loop + nop + j bad + nop + +back_from_int: + j good + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/it005.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/it005.e new file mode 100644 index 00000000..a8632a46 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/it005.e @@ -0,0 +1,73 @@ +; ###----------------------------------------------------------------### +; # file : it005.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # hardware interrupt # + ; ###--------------------------------------------------------### + +hardware_it0 .equ 0x00000400 +hardware_it1 .equ 0x00000800 +hardware_it2 .equ 0x00001000 +hardware_it3 .equ 0x00002000 +hardware_it4 .equ 0x00004000 +hardware_it5 .equ 0x00008000 + +timer_0 .equ 0x40000100 +timer_1 .equ 0x40000104 +timer_2 .equ 0x40000108 +timer_3 .equ 0x4000010C +timer_4 .equ 0x40000110 +timer_5 .equ 0x40000114 +timer_rst .equ 0x40000118 +timer_sts .equ 0x4000011C + + .org 0x80000080 + .start handler_body + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + + +handler_body: + sw r29, 0 (r30) + sw r28, 4 (r30) + + loadi r28, hardware_it5 + mfc0 r29, cause + nop + and r29, r29, r28 ; hardware interrupt 5 ? + bne r29, r28,other_causes + nop + ; ###---------------------------------------------### + ; # On releve la ligne it # + ; ###---------------------------------------------### + loadi r28, timer_sts + sw r0, 0(r28) + + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from INTERRUPT) # + ; # to the user program (address must be saved by the user # + ; # prior to the EXCEPTION in r31) # + ; ###--------------------------------------------------------### + +return: + rfe ; return from exception + jr r31 + +other_causes: j other_causes + nop + + ; ###--------------------------------------------------------### + ; # return to the interrupted program # + ; ###--------------------------------------------------------### + + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/it005.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/it005.u new file mode 100644 index 00000000..265fdab8 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/it005.u @@ -0,0 +1,56 @@ +; ###----------------------------------------------------------------### +; # file : it005.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # decrementation loop (with a hardware interrupt) # + ; ###--------------------------------------------------------### + +timer_0 .equ 0x40000100 +timer_1 .equ 0x40000104 +timer_2 .equ 0x40000108 +timer_3 .equ 0x4000010C +timer_4 .equ 0x40000110 +timer_5 .equ 0x40000114 +timer_rst .equ 0x40000118 +timer_sts .equ 0x4000011C + +value .equ 0x0008 +v_sts .equ 0x0020 + + .org 0x00400000 + .start init + +init: + loadi r31, back_from_int + loadi r1 , timer_5 + addiu r2 , r0 , value + sw r2, 0(r1) + loadi r1 , timer_sts + addiu r2 , r0 , v_sts + sw r2, 0(r1) + + addiu r10, r0 , 0x0001 + lui r20, 0xffff + addiu r16, r0, 0xfffa + or r20, r20, r16 +loop: + addu r20,r10,r20 + bne r20,r0, loop + nop + j bad + nop + +back_from_int: + j good + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/it006.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/it006.e new file mode 100644 index 00000000..b614cd0b --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/it006.e @@ -0,0 +1,73 @@ +; ###----------------------------------------------------------------### +; # file : it006.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # hardware interrupt # + ; ###--------------------------------------------------------### + +hardware_it0 .equ 0x00000400 +hardware_it1 .equ 0x00000800 +hardware_it2 .equ 0x00001000 +hardware_it3 .equ 0x00002000 +hardware_it4 .equ 0x00004000 +hardware_it5 .equ 0x00008000 + +timer_0 .equ 0x40000100 +timer_1 .equ 0x40000104 +timer_2 .equ 0x40000108 +timer_3 .equ 0x4000010C +timer_4 .equ 0x40000110 +timer_5 .equ 0x40000114 +timer_rst .equ 0x40000118 +timer_sts .equ 0x4000011C + + .org 0x80000080 + .start handler_body + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + + +handler_body: + sw r29, 0 (r30) + sw r28, 4 (r30) + + loadi r28, hardware_it0 + mfc0 r29, cause + nop + and r29, r29, r28 ; hardware interrupt 0 ? + bne r29, r28,other_causes + nop + ; ###---------------------------------------------### + ; # On releve la ligne it # + ; ###---------------------------------------------### + loadi r28, timer_sts + sw r0, 0(r28) + + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from INTERRUPT) # + ; # to the user program (address must be saved by the user # + ; # prior to the EXCEPTION in r31) # + ; ###--------------------------------------------------------### + +return: + rfe ; return from exception + jr r31 + +other_causes: j other_causes + nop + + ; ###--------------------------------------------------------### + ; # return to the interrupted program # + ; ###--------------------------------------------------------### + + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/it006.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/it006.u new file mode 100644 index 00000000..b11b239a --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/it006.u @@ -0,0 +1,66 @@ +; ###----------------------------------------------------------------### +; # file : it006.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # decrementation loop (with a hardware interrupt) # + ; ###--------------------------------------------------------### + +timer_0 .equ 0x40000100 +timer_1 .equ 0x40000104 +timer_2 .equ 0x40000108 +timer_3 .equ 0x4000010C +timer_4 .equ 0x40000110 +timer_5 .equ 0x40000114 +timer_rst .equ 0x40000118 +timer_sts .equ 0x4000011C + +timer_rst0 .equ 0x4000000C +timer_sts0 .equ 0x40000008 + +value .equ 0x0008 +v_sts .equ 0x0040 + + .org 0x00400000 + .start init + +init: + loadi r31, back_from_int + + loadi r1 , timer_rst + addiu r2 , r0 , value + sw r2, 0(r1) + loadi r1 , timer_sts + addiu r2 , r0 , v_sts + sw r2, 0(r1) + + + + + addiu r10, r0 , 0x0001 + lui r20, 0xffff + addiu r16, r0, 0xffaa + or r20, r20, r16 +loop: + addu r20,r10,r20 + bne r20,r0, loop + nop + loadi r9 , timer_sts0 + loadi r8,0 + sw r8, 0(r9) + j bad + nop + +back_from_int: + j good + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/jal000.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/jal000.u new file mode 100644 index 00000000..64099a63 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/jal000.u @@ -0,0 +1,43 @@ + +; ###----------------------------------------------------------------### +; # file : jal000.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # jump and link # + ; ###--------------------------------------------------------### + +const .equ 0x00000002 + + .org 0x00400000 + + .start init + +init: + loadi r23, const + loadi r24, (4 * const) + + jal mul2 + nop + jal mul2 + nop + + beq r24 ,r23, good + nop + j bad + nop + +mul2 : + addu r23, r23, r23 + jr r31 + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/jal001.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/jal001.u new file mode 100644 index 00000000..127aeca8 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/jal001.u @@ -0,0 +1,42 @@ + +; ###----------------------------------------------------------------### +; # file : jal001.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # jump and link # + ; ###--------------------------------------------------------### + +data .equ 0x14feb445 + + .org 0x00400000 + .start init + +init: + loadi r16, data + loadi r17, (data << 2) + + jal sub_prog + nop + jal sub_prog + nop + + bne r16, r17,bad + nop + j good + nop + +sub_prog : + sll r16, r16, 1 + jr r31 + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/jalr000.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/jalr000.u new file mode 100644 index 00000000..70dbe5d7 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/jalr000.u @@ -0,0 +1,44 @@ + +; ###----------------------------------------------------------------### +; # file : jalr000.u # +; # date : Nov 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # jump and link resgister # + ; ###--------------------------------------------------------### + +const .equ 0x14feb445 +adr2 .equ 0x004000a0 + .org 0x00400000 + + .start init + +init: + loadi r23, const + loadi r24, (4 * const) + loadi r2, adr2 + jalr r1, r2 + + jalr r1, r2 + + nop + beq r24 ,r23, good + nop + j bad + nop + + + .org 0x004000a0 + addu r23, r23, r23 + jr r1 + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/jalr001.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/jalr001.u new file mode 100644 index 00000000..d8f99971 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/jalr001.u @@ -0,0 +1,45 @@ + +; ###----------------------------------------------------------------### +; # file : jalr0001u # +; # date : Nov 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # jump and link register # + ; ###--------------------------------------------------------### + +const .equ 0x14feb445 +const1 .equ 0x004000a0 + .org 0x00400000 + + .start init + +init: + loadi r23, const + loadi r24, (4 * const) + loadi r1 , const1 + jalr r1 + + nop + jalr r1 + + nop + beq r24 ,r23, good + nop + j bad + nop + + + .org 0x004000a0 + addu r23, r23, r23 + jr r31 + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/jr000.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/jr000.u new file mode 100644 index 00000000..f56451aa --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/jr000.u @@ -0,0 +1,53 @@ + +; ###----------------------------------------------------------------### +; # file : jr000.u # +; # date : nov 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # jump register # + ; ###--------------------------------------------------------### + +const .equ 0x14feb445 +const1 .equ 0x004000a0 +const2 .equ 0x004000c0 +const3 .equ 0x00400070 +const4 .equ 0x00400080 + + .org 0x00400000 + + .start init + +init: + loadi r23, const + loadi r24, (4 * const) + loadi r1 , const1 + loadi r2 , const2 + loadi r3 , const3 + loadi r4 , const4 + jr r1 + + .org 0x00400070 + jr r2 + + .org 0x00400080 + beq r24 ,r23, good + j bad + + .org 0x004000a0 + addu r23, r23, r23 + jr r3 + + .org 0x004000c0 + addu r23, r23, r23 + jr r4 + + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/jr001.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/jr001.u new file mode 100644 index 00000000..ab10361f --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/jr001.u @@ -0,0 +1,53 @@ + +; ###----------------------------------------------------------------### +; # file : jr001.u # +; # date : Nov 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # jump resgister # + ; ###--------------------------------------------------------### + +const .equ 0x14feb445 +const1 .equ 0x004000a0 +const2 .equ 0x004000c0 +const3 .equ 0x00400070 +const4 .equ 0x00400080 + + .org 0x00400000 + + .start init + +init: + loadi r23, const + loadi r24, (4 * const) + loadi r1 , const1 + loadi r2 , const2 + loadi r3 , const3 + loadi r4 , const4 + jr r1 + + .org 0x00400070 + jr r2 + + .org 0x00400080 + beq r24 ,r23, good + j bad + + .org 0x004000a0 + addu r23, r23, r23 + jr r3 + + .org 0x004000c0 + addu r23, r23, r23 + jr r4 + + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/lhi000.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lhi000.u new file mode 100644 index 00000000..34ecb379 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lhi000.u @@ -0,0 +1,33 @@ +; ### -------------------------------------------------------------- ### +; # file : lhi000.u # +; # date : Mar 30 1993 # +; # descr. : functional test for mips # +; ### -------------------------------------------------------------- ### + + ; ### ------------------------------------------------------ ### + ; # lhi # + ; ### ------------------------------------------------------ ### + + .org 0x00400000 +const .equ 0x1234 + .start init + +init: + lui r1 , const ; load high a constant into r1 + + addiu r2 , r0 , const ; load the same value into r2 + sll r2 , r2 , 16 ; + + beq r2, r1, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/lhi001.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lhi001.u new file mode 100644 index 00000000..81f04163 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lhi001.u @@ -0,0 +1,34 @@ +; ###----------------------------------------------------------------### +; # file : lhi001.u # +; # date : Jul 10 1995 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # load high immediate # + ; ###--------------------------------------------------------### + +const .equ 0x00ac + + .org 0x00400000 + .start init + +init: + addiu r24, r0 , const + sll r25, r24, 16 + + lui r23, const + + bne r25, r23, good + nop + j good + nop + + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/lhi2000.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lhi2000.u new file mode 100644 index 00000000..101c1ad8 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lhi2000.u @@ -0,0 +1,34 @@ + +; ### -------------------------------------------------------------- ### +; # file : lhi000.u # +; # date : Mar 30 1993 # +; # descr. : functional test for mips # +; ### -------------------------------------------------------------- ### + + ; ### ------------------------------------------------------ ### + ; # lhi # + ; ### ------------------------------------------------------ ### + + .org 0x00400000 +const .equ 0x1234 + .start init + +init: + lui r1 , const ; load high a constant into r1 + + addiu r2 , r0 , const ; load the same value into r2 + sll r2 , r2 , 16 ; + + beq r2, r1, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/lhi2001.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lhi2001.u new file mode 100644 index 00000000..aeff14f9 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lhi2001.u @@ -0,0 +1,35 @@ + +; ###----------------------------------------------------------------### +; # file : lhi001.u # +; # date : Jul 10 1995 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # load high immediate # + ; ###--------------------------------------------------------### + +const .equ 0x00ac + + .org 0x00400000 + .start init + +init: + addiu r24, r0 , const + sll r25, r24, 16 + + lui r23, const + + bne r25, r23, good + nop + j good + nop + + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsb000.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsb000.u new file mode 100644 index 00000000..51d8877b --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsb000.u @@ -0,0 +1,38 @@ +; ###----------------------------------------------------------------### +; # # +; # file : lsb000.u # +; # date : Sep 10 1995 # +; # descr. : functional test for mips # +; # # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # load/store byte # + ; ###--------------------------------------------------------### + +data .equ 0x26 +address .equ 0x400000c4 + + .org 0x00400000 + .start init + +init: + + addiu r1 , r0 , data + loadi r2 , address + + sb r1, 0(r2) + lb r3, 0(r2) + nop + beq r1,r3, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsb001.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsb001.u new file mode 100644 index 00000000..3ea6086c --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsb001.u @@ -0,0 +1,38 @@ +; ###----------------------------------------------------------------### +; # # +; # file : lsb001.u # +; # date : Sep 10 1995 # +; # descr. : functional test for mips # +; # # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # load/store byte # + ; ###--------------------------------------------------------### + +data .equ 0x26 +address .equ 0x400000c4 + + .org 0x00400000 + .start init + +init: + + addiu r1 , r0 , data + loadi r2 , address + + sb r1, 1(r2) + lb r3, 1(r2) + nop + beq r1,r3, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsb002.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsb002.u new file mode 100644 index 00000000..ba3f4d19 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsb002.u @@ -0,0 +1,38 @@ +; ###----------------------------------------------------------------### +; # # +; # file : lsb002.u # +; # date : Sep 10 1995 # +; # descr. : functional test for mips # +; # # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # load/store byte # + ; ###--------------------------------------------------------### + +data .equ 0x26 +address .equ 0x400000c4 + + .org 0x00400000 + .start init + +init: + + addiu r1 , r0 , data + loadi r2 , address + + sb r1, 2(r2) + lb r3, 2(r2) + nop + beq r1,r3, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsb003.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsb003.u new file mode 100644 index 00000000..9c6f6f44 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsb003.u @@ -0,0 +1,38 @@ +; ###----------------------------------------------------------------### +; # # +; # file : lsb003.u # +; # date : Sep 10 1995 # +; # descr. : functional test for mips # +; # # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # load/store byte # + ; ###--------------------------------------------------------### + +data .equ 0x26 +address .equ 0x400000c4 + + .org 0x00400000 + .start init + +init: + + addiu r1 , r0 , data + loadi r2 , address + + sb r1, 3(r2) + lb r3, 3(r2) + nop + beq r1,r3, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsb004.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsb004.u new file mode 100644 index 00000000..33741ba4 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsb004.u @@ -0,0 +1,43 @@ +; ###----------------------------------------------------------------### +; # # +; # file : lsb004.u # +; # date : Sep 10 1995 # +; # descr. : functional test for mips # +; # # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # load/store byte # + ; ###--------------------------------------------------------### + +data .equ 0xffffffff +mask1 .equ 0x0000fff6 +mask .equ 0xffffff00 +address .equ 0x400000c4 + + .org 0x00400000 + .start init + +init: + lui r1 , data + addiu r16, r0 , mask1 + or r1 , r1 , r16 + loadi r2 , address + + sb r1, 0(r2) + lb r3, 0(r2) + nop + loadi r4, mask + or r1, r1, r4 + beq r1, r3, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsb005.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsb005.u new file mode 100644 index 00000000..472e8d41 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsb005.u @@ -0,0 +1,43 @@ +; ###----------------------------------------------------------------### +; # # +; # file : lsb005.u # +; # date : Sep 10 1995 # +; # descr. : functional test for mips # +; # # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # load/store byte # + ; ###--------------------------------------------------------### + +data .equ 0xffffffff +mask1 .equ 0x0000fff6 +mask .equ 0xffffff00 +address .equ 0x400000c4 + + .org 0x00400000 + .start init + +init: + lui r1 , data + addiu r16, r0 , mask1 + or r1 , r1 , r16 + loadi r2 , address + + sb r1, 0(r2) + lb r3, 0(r2) + nop + loadi r4, mask + or r1, r1, r4 + beq r1, r3, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsb006.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsb006.u new file mode 100644 index 00000000..25216435 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsb006.u @@ -0,0 +1,43 @@ +; ###----------------------------------------------------------------### +; # # +; # file : lsb006.u # +; # date : Sep 10 1995 # +; # descr. : functional test for mips # +; # # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # load/store byte # + ; ###--------------------------------------------------------### + +data .equ 0xffffffff +mask1 .equ 0x0000fff6 +mask .equ 0xffffff00 +address .equ 0x400000c4 + + .org 0x00400000 + .start init + +init: + lui r1 , data + addiu r16, r0 , mask1 + or r1 , r1 , r16 + loadi r2 , address + + sb r1, 0(r2) + lb r3, 0(r2) + nop + loadi r4, mask + or r1, r1, r4 + beq r1, r3, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsb007.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsb007.u new file mode 100644 index 00000000..502377db --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsb007.u @@ -0,0 +1,43 @@ +; ###----------------------------------------------------------------### +; # # +; # file : lsb007.u # +; # date : Sep 10 1995 # +; # descr. : functional test for mips # +; # # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # load/store byte # + ; ###--------------------------------------------------------### + +data .equ 0xffffffff +mask1 .equ 0x0000fff6 +mask .equ 0xffffff00 +address .equ 0x400000c4 + + .org 0x00400000 + .start init + +init: + lui r1 , data + addiu r16, r0 , mask1 + or r1 , r1 , r16 + loadi r2 , address + + sb r1, 0(r2) + lb r3, 0(r2) + nop + loadi r4, mask + or r1, r1, r4 + beq r1, r3, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsbu000.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsbu000.u new file mode 100644 index 00000000..fdfcb2a8 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsbu000.u @@ -0,0 +1,38 @@ +; ###----------------------------------------------------------------### +; # # +; # file : lsbu000.u # +; # date : Sep 10 1995 # +; # descr. : functional test for mips # +; # # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # load/store (unsigned) byte # + ; ###--------------------------------------------------------### + +data .equ 0x26 +address .equ 0x400000c4 + + .org 0x00400000 + .start init + +init: + + addiu r1 , r0 , data + loadi r2 , address + + sb r1, 0(r2) + lbu r3, 0(r2) + nop + beq r1,r3, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsbu001.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsbu001.u new file mode 100644 index 00000000..10080702 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsbu001.u @@ -0,0 +1,38 @@ +; ###----------------------------------------------------------------### +; # # +; # file : lsbu001.u # +; # date : Sep 10 1995 # +; # descr. : functional test for mips # +; # # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # load/store (unsigned) byte # + ; ###--------------------------------------------------------### + +data .equ 0x26 +address .equ 0x400000c4 + + .org 0x00400000 + .start init + +init: + + addiu r1 , r0 , data + loadi r2 , address + + sb r1, 1(r2) + lbu r3, 1(r2) + nop + beq r1,r3, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsbu002.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsbu002.u new file mode 100644 index 00000000..088d6bed --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsbu002.u @@ -0,0 +1,38 @@ +; ###----------------------------------------------------------------### +; # # +; # file : lsbu002.u # +; # date : Sep 10 1995 # +; # descr. : functional test for mips # +; # # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # load/store (unsigned) byte # + ; ###--------------------------------------------------------### + +data .equ 0x26 +address .equ 0x400000c4 + + .org 0x00400000 + .start init + +init: + + addiu r1 , r0 , data + loadi r2 , address + + sb r1, 2(r2) + lbu r3, 2(r2) + nop + beq r1,r3, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsbu003.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsbu003.u new file mode 100644 index 00000000..a6dd2be0 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsbu003.u @@ -0,0 +1,38 @@ +; ###----------------------------------------------------------------### +; # # +; # file : lsbu003.u # +; # date : Sep 10 1995 # +; # descr. : functional test for mips # +; # # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # load/store (unsigned) byte # + ; ###--------------------------------------------------------### + +data .equ 0x26 +address .equ 0x400000c4 + + .org 0x00400000 + .start init + +init: + + addiu r1 , r0 , data + loadi r2 , address + + sb r1, 3(r2) + lbu r3, 3(r2) + nop + beq r1,r3, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsh000.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsh000.u new file mode 100644 index 00000000..f83ba8cb --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsh000.u @@ -0,0 +1,39 @@ +; ###----------------------------------------------------------------### +; # # +; # file : lsh000.u # +; # date : Sep 10 1995 # +; # descr. : functional test for mips # +; # # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # load/store half word # + ; ###--------------------------------------------------------### + +data .equ 0x263a +address .equ 0x400000c4 + + .org 0x00400000 + .start init + +init: + + addiu r1 , r0 , data + loadi r2 , address + + sh r1, 0(r2) + lh r3, 0(r2) + nop + + beq r1,r3, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsh001.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsh001.u new file mode 100644 index 00000000..7f14447c --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsh001.u @@ -0,0 +1,39 @@ +; ###----------------------------------------------------------------### +; # # +; # file : lsh001.u # +; # date : Sep 10 1995 # +; # descr. : functional test for mips # +; # # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # load/store half word # + ; ###--------------------------------------------------------### + +data .equ 0x263a +address .equ 0x400000c4 + + .org 0x00400000 + .start init + +init: + + addiu r1 , r0 , data + loadi r2 , address + + sh r1, 2(r2) + lh r3, 2(r2) + nop + + beq r1,r3, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsh002.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsh002.u new file mode 100644 index 00000000..10a7583e --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsh002.u @@ -0,0 +1,41 @@ +; ###----------------------------------------------------------------### +; # # +; # file : lsh002.u # +; # date : Sep 10 1995 # +; # descr. : functional test for mips # +; # # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # load/store half word # + ; ###--------------------------------------------------------### + +data .equ 0xf63a +mask .equ 0xffffffff +address .equ 0x400000c4 + + .org 0x00400000 + .start init + +init: + lui r1 , mask + addiu r16, r0 , data + or r1 , r1 , r16 + loadi r2 , address + + sh r1, 0(r2) + lh r3, 0(r2) + nop + + beq r1,r3, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsh003.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsh003.u new file mode 100644 index 00000000..d0d3a9fd --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsh003.u @@ -0,0 +1,41 @@ +; ###----------------------------------------------------------------### +; # # +; # file : lsh003.u # +; # date : Sep 10 1995 # +; # descr. : functional test for mips # +; # # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # load/store half word # + ; ###--------------------------------------------------------### + +data .equ 0xf63a +mask .equ 0xffffffff +address .equ 0x400000c4 + + .org 0x00400000 + .start init + +init: + lui r1 , mask + addiu r16, r0 , data + or r1 , r1 , r16 + loadi r2 , address + + sh r1, 2(r2) + lh r3, 2(r2) + nop + + beq r1,r3, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/lshu000.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lshu000.u new file mode 100644 index 00000000..9cada31d --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lshu000.u @@ -0,0 +1,38 @@ +; ###----------------------------------------------------------------### +; # # +; # file : lshu000.u # +; # date : Sep 10 1995 # +; # descr. : functional test for dlx # +; # # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # load/store (unsigned) half word # + ; ###--------------------------------------------------------### + +data .equ 0x263a +address .equ 0x400000c4 + + .org 0x00400000 + .start init + +init: + + addiu r1 , r0 , data + loadi r2 , address + + sh r1, 0(r2) + lhu r3, 0(r2) + nop + beq r1,r3, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/lshu001.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lshu001.u new file mode 100644 index 00000000..2d69b7e2 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lshu001.u @@ -0,0 +1,41 @@ +; ###----------------------------------------------------------------### +; # # +; # file : lshu001.u # +; # date : Sep 10 1995 # +; # descr. : functional test for dlx # +; # # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # load/store (unsigned) half word # + ; ###--------------------------------------------------------### + +data .equ 0xf63a +mask .equ 0xffffffff +address .equ 0x400000c4 + + .org 0x00400000 + .start init + +init: + lui r1 , mask + addiu r16, r0 , data + or r1 , r1 , r16 + loadi r2 , address + + sh r1, 2(r2) + lhu r3, 2(r2) + nop + loadi r1, data + beq r1,r3, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsw000.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsw000.u new file mode 100644 index 00000000..501c22cc --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsw000.u @@ -0,0 +1,61 @@ +; ### --------------------------------------------------------------- ### +; # # +; # file : lsw000.u # +; # date : Jan 5 1993 # +; # description : functional test for mips # +; # # +; ### --------------------------------------------------------------- ### + + ; ### ------------------------------------------------------- ### + ; # store data, data+1, data+2, ... in successive addresses # + ; # then load the stored data in an accumulator # + ; ### ------------------------------------------------------- ### + +address .equ 0x40000004 +data .equ 6976 ; short data +mask .equ 0xffffffff ; short data +loop_iter .equ 3 ; loop iteration number + + .org 0x00400000 + .start init + +init: + loadi r1 , address + addiu r3 , r0 , loop_iter + addiu r2 , r0 , data + +write_loop: sw r2, 0(r1 ) + addiu r2 , r2 , 1 + lui r13 , mask + addiu r16, r0 , mask + or r13 , r13 , r16 + addu r3 , r3 , r13 + addiu r1 , r1 , 4 + bne r3 , r0,write_loop + + loadi r1 , address + addu r5 , r0 , r0 + addiu r3 , r0 , loop_iter + +read_loop: lw r4 , 0(r1 ) + nop + addiu r5, r5, data + addu r3 , r3 , r13 + bne r3 , r0 ,read_loop + addiu r1 , r1 , 4 + + loadi r6 , ( 3 * data) + + beq r6, r5 , good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsw001.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsw001.u new file mode 100644 index 00000000..8b2eb59d --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/lsw001.u @@ -0,0 +1,42 @@ +; ### --------------------------------------------------------------- ### +; # # +; # file : lsw001.u # +; # date : Nov 1996 # +; # description : functional test for mips # +; # # +; ### --------------------------------------------------------------- ### + + ; ### ------------------------------------------------------- ### + ; # store data, data+1, data+2, ... in successive addresses # + ; # then load the stored data in an accumulator # + ; ### ------------------------------------------------------- ### + +address .equ 0x40000004 +data .equ 6976 ; short data +loop_iter .equ 7 ; loop iteration number + + .org 0x00400000 + .start init + +init: + loadi r1 , address + addiu r2 , r0 , data + +write_loop: sw r2, 0(r1 ) + +read_loop: lw r4 , 0(r1 ) + addiu r1, r1, 4 + beq r4 , r2 , good + + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/mftc0_00.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/mftc0_00.e new file mode 100644 index 00000000..fef88feb --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/mftc0_00.e @@ -0,0 +1,72 @@ + +; ###----------------------------------------------------------------### +; # file : mftc0_00.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - break # + ; ###--------------------------------------------------------### + +value .equ 0x12344444 +ill_codop .equ 0x28 +mask .equ 0x3C + + .org 0x80000080 + .start it_handler + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + +it_handler: + + sw r29, 0 (r30) + sw r28, 4 (r30) + + ;addiu r28, r0, mask + ;mfc0 r29, cause + ;nop + ;and r29, r29, r28 + ;addiu r28, r0, ill_codop + ;bne r28, r29, not_good + + loadi r28, value + loadi r29, value + mtc0 r28, cause + nop + mtc0 r29, status + nop + mfc0 r29, cause + nop + mfc0 r28, status + nop + bne r28, r29, not_good + + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from EXCEPTION) # + ; # to the user program (address must be saved by the user # + ; # prior to the EXCEPTION in epc) # + ; ###--------------------------------------------------------### + +restore_return_adr: + mfc0 r31, epc + nop + addiu r31, r31, 8 + jr r31 + rfe + +not_good: + mfc0 r31, epc + nop + addiu r31, r31, 4 + jr r31 + rfe + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/mftc0_00.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/mftc0_00.u new file mode 100644 index 00000000..a5f79649 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/mftc0_00.u @@ -0,0 +1,41 @@ +; ###----------------------------------------------------------------### +; # # +; # file : mftc0_00.u # +; # date : Apr 21 1995 # +; # descr. : functional test for mips # +; # # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # software interrupt : # + ; ###--------------------------------------------------------### + + + .org 0x00400000 + .start init + +init: + + ; ###--------------------------------------------------------### + ; # sotware interrupt # + ; ###--------------------------------------------------------### + + break 1 + j bad + + ; ###--------------------------------------------------------### + ; # check that the the trap has been done (r1 must contain # + ; # the trap number) # + ; ###--------------------------------------------------------### + +back_from_exception: + j good ; jump to good if OK + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/mfthi_00.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/mfthi_00.e new file mode 100644 index 00000000..631e5ede --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/mfthi_00.e @@ -0,0 +1,66 @@ + +; ###----------------------------------------------------------------### +; # file : mfthi_00.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # test de mfhi et de mthi # + ; ###--------------------------------------------------------### + +value .equ 0x12344444 +ill_codop .equ 0x28 +mask .equ 0x3C + + .org 0x80000080 + .start it_handler + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + +it_handler: + + sw r29, 0 (r30) + sw r28, 4 (r30) + + ;addiu r28, r0, mask + ;mfc0 r29, cause + ;nop + ;and r29, r29, r28 + ;addiu r28, r0, ill_codop + ;bne r28, r29, not_good + + loadi r28, value + mthi r28 + nop + mfhi r29 + nop + bne r28, r29, not_good + + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from EXCEPTION) # + ; # to the user program (address must be saved by the user # + ; # prior to the EXCEPTION in epc) # + ; ###--------------------------------------------------------### + +restore_return_adr: + mfc0 r31, epc + nop + addiu r31, r31, 8 + jr r31 + rfe + +not_good: + mfc0 r31, epc + nop + addiu r31, r31, 4 + jr r31 + rfe + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/mfthi_00.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/mfthi_00.u new file mode 100644 index 00000000..9bb339c0 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/mfthi_00.u @@ -0,0 +1,41 @@ +; ###----------------------------------------------------------------### +; # # +; # file : mfthi_00.u # +; # date : Apr 21 1995 # +; # descr. : functional test for mips # +; # # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # software interrupt : # + ; ###--------------------------------------------------------### + + + .org 0x00400000 + .start init + +init: + + ; ###--------------------------------------------------------### + ; # sotware interrupt # + ; ###--------------------------------------------------------### + + break 1 + j bad + + ; ###--------------------------------------------------------### + ; # check that the the trap has been done (r1 must contain # + ; # the trap number) # + ; ###--------------------------------------------------------### + +back_from_exception: + j good ; jump to good if OK + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/mftlo_00.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/mftlo_00.e new file mode 100644 index 00000000..b7259f02 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/mftlo_00.e @@ -0,0 +1,67 @@ + +; ###----------------------------------------------------------------### +; # file : mftlo_00.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - break # + ; ###--------------------------------------------------------### + +value .equ 0x12344444 +ill_codop .equ 0x28 +mask .equ 0x3C + + .org 0x80000080 + .start it_handler + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + +it_handler: + + sw r29, 0 (r30) + sw r28, 4 (r30) + + ;addiu r28, r0, mask + ;mfc0 r29, cause + ;nop + ;and r29, r29, r28 + ;addiu r28, r0, ill_codop + ;bne r28, r29, not_good + + loadi r28, value + mtlo r28 + nop + mflo r29 + nop + bne r28, r29, not_good + + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from EXCEPTION) # + ; # to the user program (address must be saved by the user # + ; # prior to the EXCEPTION in epc) # + ; ###--------------------------------------------------------### + +restore_return_adr: + mfc0 r31, epc + nop + addiu r31, r31, 8 + jr r31 + rfe + +not_good: + mfc0 r31, epc + nop + addiu r31, r31, 4 + jr r31 + rfe + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/mftlo_00.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/mftlo_00.u new file mode 100644 index 00000000..28044b8e --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/mftlo_00.u @@ -0,0 +1,41 @@ +; ###----------------------------------------------------------------### +; # # +; # file : mftlo_00.u # +; # date : Apr 21 1995 # +; # descr. : functional test for mips # +; # # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # software interrupt : # + ; ###--------------------------------------------------------### + + + .org 0x00400000 + .start init + +init: + + ; ###--------------------------------------------------------### + ; # sotware interrupt # + ; ###--------------------------------------------------------### + + break 1 + j bad + + ; ###--------------------------------------------------------### + ; # check that the the trap has been done (r1 must contain # + ; # the trap number) # + ; ###--------------------------------------------------------### + +back_from_exception: + j good ; jump to good if OK + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/mips_defs.h b/alliance/src/documentation/alliance-examples/mipsR3000/asm/mips_defs.h new file mode 100644 index 00000000..d1b610bd --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/mips_defs.h @@ -0,0 +1,169 @@ +/* + * This file is part of the Alliance CAD System + * Copyright (C) Laboratoire LIP6 - Département ASIM + * Universite Pierre et Marie Curie + * + * Home page : http://www-asim.lip6.fr/alliance/ + * E-mail support : mailto:alliance-support@asim.lip6.fr + * + * This progam is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Alliance VLSI CAD System is distributed in the hope that it will be + * useful, but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the GNU C Library; see the file COPYING. If not, write to the Free + * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + + +/* ###--------------------------------------------------------------### */ +/* file : mips_defs.h */ +/* date : Dec 6 1999 */ +/* version : v0.3 */ +/* author : Pirouz BAZARGAN SABET */ +/* description : MIPS assembler - defines (operation codes) */ +/* ###--------------------------------------------------------------### */ + +#define MPS_PLSDFN 0 /* add */ +#define MPS_MNSDFN 1 /* subtract */ +#define MPS_SHLDFN 2 /* shift left */ +#define MPS_SHRDFN 3 /* shift right */ +#define MPS_ORDFN 4 /* logical or */ +#define MPS_ANDDFN 5 /* logical and */ +#define MPS_XORDFN 6 /* logical exclusive or */ +#define MPS_MULDFN 7 /* multiply */ +#define MPS_DIVDFN 8 /* divide */ + + /* ### ---------------------------------------------------- ### */ + /* instruction set table: */ + /* Opcods in lower case are MIPS instructions */ + /* Opcods in upper case are application specific */ + /* */ + /* */ + /* primary opcod (31 downto 26): */ + /* | 0 1 2 3 4 5 6 7 */ + /* --+-----+-----+-----+-----+-----+-----+-----+-----+ */ + /* 0 |speci|bcond| j | jal | beq | bne |blez |bgtz | */ + /* 1 |addi |addui|slti |sltui|andi | ori |xori | lui | */ + /* 2 |cop0 | + | + | + | | + | | | */ + /* 3 | | | | | | | | | */ + /* 4 | lb | lh | + | lw | lbu | lhu | + |SWAP | */ + /* 5 | sb | sh | + | sw | | | + | | */ + /* 6 | + | + | + | + |Seqi |Snei |Slei |Sgti | */ + /* 7 | + | + | + | + |Sgei |Sgeui|Sleui|Sgtui| */ + /* */ + /* */ + /* special opcod extension (5 downto 0): */ + /* | 0 1 2 3 4 5 6 7 */ + /* --+-----+-----+-----+-----+-----+-----+-----+-----+ */ + /* 0 | sll | | srl | sra |sllv | |srlv |srav | */ + /* 1 | jr |jalr | | |sysca|break| |SLEEP| */ + /* 2 |mfhi |mthi |mflo |mtlo | | | | | */ + /* 3 | + | + | + | + | | | | | */ + /* 4 | add |addu | sub |subu | and | or | xor | nor | */ + /* 5 | | | slt |sltu | | | | | */ + /* 6 | | | | | + | + | + | + | */ + /* 7 | | | | | + | + | + | + | */ + /* */ + /* */ + /* bcond opcod extension (20 downto 16): */ + /* | 0 1 2 3 4 5 6 7 */ + /* --+-----+-----+-----+-----+-----+-----+-----+-----+ */ + /* 0 |bltz |bgez | | | | | | | */ + /* 1 | | | | | | | | | */ + /* 2 |bltza|bgeza| | | | | | | */ + /* 3 | | | | | | | | | */ + /* */ + /* */ + /* cop0 opcod extension (22, 21, 16, 25, 24, 23): */ + /* | 0 1 2 3 4 5 6 7 */ + /* --+-----+-----+-----+-----+-----+-----+-----+-----+ */ + /* 0 | mf | mt | + | + | c0 | c0 | c0 | c0 | */ + /* 1 | mf | mt | + | + | c0 | c0 | c0 | c0 | */ + /* 2 | | | | | c0 | c0 | c0 | c0 | */ + /* 3 | | | | | c0 | c0 | c0 | c0 | */ + /* 4 | + | + | | | c0 | c0 | c0 | c0 | */ + /* 5 | + | + | | | c0 | c0 | c0 | c0 | */ + /* 6 | | | | | c0 | c0 | c0 | c0 | */ + /* 7 | | | | | c0 | c0 | c0 | c0 | */ + /* */ + /* */ + /* c0 cop0 extension extension (4 downto 0): */ + /* | 0 1 2 3 4 5 6 7 */ + /* --+-----+-----+-----+-----+-----+-----+-----+-----+ */ + /* 0 | + | + | + | | | | + | | */ + /* 1 | + | | | | | | | | */ + /* 2 |rstfe| | | | | | | | */ + /* 3 | + | | | | | | | | */ + /* */ + /* ### ---------------------------------------------------- ### */ + +#define _ADD 0x00000020 /* Mips architecture */ +#define _ADDI 0x20000000 /* Mips architecture */ +#define _ADDU 0x00000021 /* Mips architecture */ +#define _ADDIU 0x24000000 /* Mips architecture */ +#define _AND 0x00000024 /* Mips architecture */ +#define _ANDI 0x30000000 /* Mips architecture */ +#define _BEQ 0x10000000 /* Mips architecture */ +#define _BGEZ 0x04010000 /* Mips architecture */ +#define _BGEZAL 0x04110000 /* Mips architecture */ +#define _BGTZ 0x1C000000 /* Mips architecture */ +#define _BLEZ 0x18000000 /* Mips architecture */ +#define _BLTZ 0x04000000 /* Mips architecture */ +#define _BLTZAL 0x04100000 /* Mips architecture */ +#define _BNE 0x14000000 /* Mips architecture */ +#define _BREAK 0x0000000D /* Mips architecture */ +#define _J 0x08000000 /* Mips architecture */ +#define _JAL 0x0C000000 /* Mips architecture */ +#define _JALR 0x00000009 /* Mips architecture */ +#define _JR 0x00000008 /* Mips architecture */ +#define _LB 0x80000000 /* Mips architecture */ +#define _LBU 0x90000000 /* Mips architecture */ +#define _LH 0x84000000 /* Mips architecture */ +#define _LHU 0x94000000 /* Mips architecture */ +#define _LUI 0x3C000000 /* Mips architecture */ +#define _LW 0x8C000000 /* Mips architecture */ +#define _MFC0 0x40000000 /* Mips architecture */ +#define _MFHI 0x00000010 /* Mips architecture */ +#define _MFLO 0x00000012 /* Mips architecture */ +#define _MTC0 0x40800000 /* Mips architecture */ +#define _MTHI 0x00000011 /* Mips architecture */ +#define _MTLO 0x00000013 /* Mips architecture */ +#define _NOR 0x00000027 /* Mips architecture */ +#define _OR 0x00000025 /* Mips architecture */ +#define _ORI 0x34000000 /* Mips architecture */ +#define _RSTFE 0x42000010 /* Mips architecture */ +#define _SB 0xA0000000 /* Mips architecture */ +#define _SH 0xA4000000 /* Mips architecture */ +#define _SLEEP 0x0000000F /* Mips architecture */ +#define _SLL 0x00000000 /* Mips architecture */ +#define _SLLV 0x00000004 /* Mips architecture */ +#define _SLT 0x0000002A /* Mips architecture */ +#define _SLTI 0x28000000 /* Mips architecture */ +#define _SLTU 0x0000002B /* Mips architecture */ +#define _SLTIU 0x2C000000 /* Mips architecture */ +#define _SRA 0x00000003 /* Mips architecture */ +#define _SRAV 0x00000007 /* Mips architecture */ +#define _SRL 0x00000002 /* Mips architecture */ +#define _SRLV 0x00000006 /* Mips architecture */ +#define _SUB 0x00000022 /* Mips architecture */ +#define _SUBU 0x00000023 /* Mips architecture */ +#define _SW 0xAC000000 /* Mips architecture */ +#define _SWAP 0x9C000000 /* Mips architecture */ +#define _SYSCALL 0x0000000C /* Mips architecture */ +#define _XOR 0x00000026 /* Mips architecture */ +#define _XORI 0x38000000 /* Mips architecture */ + +#define _NOP 0x00000001 /* Mips macro */ +#define _LOADI 0x00000002 /* Mips macro */ + +#define _BADVADDR 8 +#define _STATUS 12 +#define _CAUSE 13 +#define _EPC 14 diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/nor000.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/nor000.u new file mode 100644 index 00000000..3a0db6ff --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/nor000.u @@ -0,0 +1,40 @@ +; ###----------------------------------------------------------------### +; # file : nor000.u # +; # date : Apr 1 1993 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # logic nor # + ; ###--------------------------------------------------------### + +const1 .equ 0xa5de56457 +const2 .equ 0x878f0105b +const3 .equ 0x820a8ba0 +const4 .equ -1 + + .org 0x00400000 + .start init + +init: + loadi r14, const1 + loadi r19, const2 + loadi r9 , const3 + + nor r20, r14, r19 + bne r9 , r20, bad + nop + nor r9, r0, r0 + loadi r20, const4 + beq r9, r20, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/or000.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/or000.u new file mode 100644 index 00000000..b60cd069 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/or000.u @@ -0,0 +1,34 @@ +; ###----------------------------------------------------------------### +; # file : or000.u # +; # date : Apr 1 1993 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # logic or # + ; ###--------------------------------------------------------### + +const1 .equ 0xa5de56457 +const2 .equ 0x878f0105b + + .org 0x00400000 + .start init + +init: + loadi r14, const1 + loadi r19, const2 + loadi r9 , (const1 | const2) + + or r20, r14, r19 + beq r9 , r20, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/or001.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/or001.u new file mode 100644 index 00000000..7272b089 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/or001.u @@ -0,0 +1,34 @@ +; ###----------------------------------------------------------------### +; # file : or001.u # +; # date : Apr 1 1993 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # logic or # + ; ###--------------------------------------------------------### + +const1 .equ 0x5555 +const2 .equ 0xaaaa + + .org 0x00400000 + .start init + +init: + loadi r14, const1 + loadi r19, const2 + loadi r9 , (const1 | const2) + + or r20, r14, r19 + beq r9 , r20, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/or002.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/or002.u new file mode 100644 index 00000000..1f69d20d --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/or002.u @@ -0,0 +1,33 @@ +; ###----------------------------------------------------------------### +; # file : or002.u # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # logic or immediate # + ; ###--------------------------------------------------------### + +data1 .equ 0xd6f2 +data2 .equ 0xc451 + + .org 0x00400000 + .start init + +init: + addiu r6 , r0 , data1 ; r6 = data2 + ori r7 , r6 , data2 ; r7 = data1 | data2 + + addiu r3 , r0, (data1 | data2) ; good if r7 correct + bne r3 , r7 , bad + nop + j good + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/reg000.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/reg000.u new file mode 100644 index 00000000..cc3b74a2 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/reg000.u @@ -0,0 +1,36 @@ +; ###----------------------------------------------------------------### +; # file : reg000.u # +; # date : Apr 1 1993 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # signed addition # + ; ###--------------------------------------------------------### + +val .equ 3429 + + .org 0x00400000 + .start init + +init: + add r25, r0 , r0 + addi r26, r0, val + bne r25, r0,bad + nop + + sub r25, r25, r26 + addi r25, r25, val + bne r25, r0,bad + nop + j good + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/res_test b/alliance/src/documentation/alliance-examples/mipsR3000/asm/res_test new file mode 100644 index 00000000..309e5d23 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/res_test @@ -0,0 +1,799 @@ +************************************************************************** +################# ---- Test de : exc000 ---- ################# +Test de mauvais alignement de data +################# ---- Test de : exc001 ---- ################# +Test de ADES +################# ---- Test de : exc002 ---- ################# +Test d'OVERFLOW de sum de nb >0 +********************************************************************** +Test de add et de addi +Test de add et de addi (bis) +Test de add et de addi (bis bis) +Test de add et de addi bis bis bis +Test de sub, loadi, addi +Test de addi, initialisation des registres avec leurs propres numeros +Test de addui +Test de addui +Test de addui, addu +Test de addui, addu +Test de addui, seqi, and +Test de addui, loadi, andi +Test de addui, lui, sll +Test de addui, lui, sll +Test de loadi, nor +Test de loadi, or +Test de loadi, or +Test de loadi, ori, addui +Test de l'addition signee +Test de slt +Test de slt bis +Test de loadi, addui, slt +Test de loadi, addui, slti +Test de loadi, addui, slt +Test de loadi, addui, slti +Test de loadi, addui, sltu +Test de loadi, addui, sltu +Test de addui, sllv +Test de addui, loadi,sll +Test de addui, srav +Test de addui, sra +Test de addui, srlv +Test de addui, srl +Test de addi, sub +Test de loadi, subu +Test de loadi, xor +Test de loadi, xor +Test de slti, xori +********************************************************************** +################# ---- Test de : add000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de add et de addi +################# ---- Test de : add001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de add et de addi (bis) +################# ---- Test de : add002 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de add et de addi (bis bis) +################# ---- Test de : add003 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de add et de addi bis bis bis +################# ---- Test de : add004 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de sub, loadi, addi +################# ---- Test de : add005 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addi, initialisation des registres avec leurs propres numeros +################# ---- Test de : addu000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui +################# ---- Test de : addu001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui +################# ---- Test de : addu002 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, addu +################# ---- Test de : addu003 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, addu +################# ---- Test de : and000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, seqi, and +################# ---- Test de : and001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, loadi, andi +################# ---- Test de : lhi000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, lui, sll +################# ---- Test de : lhi001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, lui, sll +################# ---- Test de : nor000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, nor +################# ---- Test de : or000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, or +################# ---- Test de : or001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, or +################# ---- Test de : or002 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, ori, addui +################# ---- Test de : or002 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de l'addition signee +################# ---- Test de : sle000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de slt +################# ---- Test de : sle000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de slt bis +################# ---- Test de : sle000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, addui, slt +################# ---- Test de : sle000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, addui, slti +################# ---- Test de : sle000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, addui, slt +################# ---- Test de : sle000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, addui, slti +################# ---- Test de : sle000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, addui, sltu +################# ---- Test de : sle000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, addui, sltu +################# ---- Test de : sll000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, sllv +################# ---- Test de : sll001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, loadi,sll +################# ---- Test de : sra000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, srav +################# ---- Test de : sra001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, sra +################# ---- Test de : srl000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, srlv +################# ---- Test de : srl001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, srl +################# ---- Test de : sub000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addi, sub +################# ---- Test de : sub001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, subu +################# ---- Test de : xor000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, xor +################# ---- Test de : xor001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, xor +################# ---- Test de : xor002 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de slti, xori +********************************************************************** +################# ---- Test de : add000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de add et de addi +################# ---- Test de : add001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de add et de addi (bis) +################# ---- Test de : add002 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de add et de addi (bis bis) +################# ---- Test de : add003 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de add et de addi bis bis bis +################# ---- Test de : add004 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de sub, loadi, addi +################# ---- Test de : add005 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addi, initialisation des registres avec leurs propres numeros +################# ---- Test de : addu000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui +################# ---- Test de : addu001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui +################# ---- Test de : addu002 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, addu +################# ---- Test de : addu003 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, addu +################# ---- Test de : and000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, seqi, and +################# ---- Test de : and001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, loadi, andi +################# ---- Test de : lhi000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, lui, sll +################# ---- Test de : lhi001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, lui, sll +################# ---- Test de : nor000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, nor +################# ---- Test de : or000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, or +################# ---- Test de : or001 ---- ################# +Test de loadi, or +################# ---- Test de : or002 ---- ################# +Test de loadi, ori, addui +################# ---- Test de : or002 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de l'addition signee +################# ---- Test de : sle000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de slt +################# ---- Test de : sle000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de slt bis +################# ---- Test de : sle000 ---- ################# +Test de loadi, addui, slt +################# ---- Test de : sle000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, addui, slti +################# ---- Test de : sle000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, addui, slt +********************************************************************** +################# ---- Test de : add000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de add et de addi +################# ---- Test de : add001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de add et de addi (bis) +################# ---- Test de : add002 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de add et de addi (bis bis) +################# ---- Test de : add003 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de add et de addi bis bis bis +################# ---- Test de : add004 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de sub, loadi, addi +################# ---- Test de : add005 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addi, initialisation des registres avec leurs propres numeros +################# ---- Test de : addu000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui +################# ---- Test de : addu001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui +################# ---- Test de : addu002 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, addu +################# ---- Test de : addu003 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, addu +################# ---- Test de : and000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, seqi, and +################# ---- Test de : and001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, loadi, andi +################# ---- Test de : lhi000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, lui, sll +################# ---- Test de : lhi001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, lui, sll +################# ---- Test de : nor000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, nor +################# ---- Test de : or000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, or +################# ---- Test de : or001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, or +################# ---- Test de : or002 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, ori, addui +################# ---- Test de : or002 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de l'addition signee +################# ---- Test de : sle000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de slt +################# ---- Test de : sle000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de slt bis +################# ---- Test de : sle000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, addui, slt +################# ---- Test de : sle000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, addui, slti +################# ---- Test de : sle000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, addui, slt +################# ---- Test de : sle000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, addui, slti +################# ---- Test de : sle000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, addui, sltu +################# ---- Test de : sle000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, addui, sltu +################# ---- Test de : sll000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, sllv +################# ---- Test de : sll001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, loadi,sll +################# ---- Test de : sra000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, srav +################# ---- Test de : sra001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, sra +################# ---- Test de : srl000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, srlv +################# ---- Test de : srl001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, srl +################# ---- Test de : sub000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addi, sub +################# ---- Test de : sub001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, subu +################# ---- Test de : xor000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, xor +################# ---- Test de : xor001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, xor +################# ---- Test de : xor002 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de slti, xori +************************************************************************** +Test de beq 0 +Test de beq 1 +Test de bgez0 +Test de bgez1 +Test de bgezal +Test de bgtz +Test de blez +Test de bltz +Test de bltzal +Test de bne0 +Test de bne1 +Test de lhi0 +Test de lhi1 +Test de jal0 +Test de jal1 +Test de jalr0 +Test de jalr1 +Test de lsb0 +Test de lsb1 +Test de lsb2 +Test de lsb3 +Test de lsb4 +Test de lsb5 +Test de lsb6 +Test de lsb7 +Test de lsbu0 +Test de lsbu1 +Test de lsbu2 +Test de lsbu3 +Test de lsh0 +Test de lsh1 +Test de lsh2 +Test de lsh3 +Test de lshu0 +Test de lshu1 +Test de lsw0 +Test de lsw1 +Test de sltu0 +Test de sltu1 +Test de sltu2 +Test de sltu3 +Test de sltu4 +Test de sltiu0 +Test de sltiu1 +Test de sltiu2 +Test de sltiu3 +Test de sltiu4 +************************************************************************** +Test de mauvais alignement de data +Test de ADES +Test d'OVERFLOW de sum de nb >0 +Test d'OVERFLOW de sum de nb >0 +Test d'OVERFLOW de sum de nb >0 +Test d'OVERFLOW de sum de nb >0 + illegal instruction address + Test de ADEL + Test de ADEL + ri (when executing a mfc0) +************************************************************************** +********************************************************************** +################# ---- Test de : add000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de add et de addi +################# ---- Test de : add001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de add et de addi (bis) +################# ---- Test de : add002 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de add et de addi (bis bis) +################# ---- Test de : add003 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de add et de addi bis bis bis +################# ---- Test de : add004 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de sub, loadi, addi +################# ---- Test de : add005 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addi, initialisation des registres avec leurs propres numeros +################# ---- Test de : addu000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui +################# ---- Test de : addu001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui +################# ---- Test de : addu002 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, addu +################# ---- Test de : addu003 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, addu +################# ---- Test de : and000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, seqi, and +################# ---- Test de : and001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, loadi, andi +################# ---- Test de : lhi000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, lui, sll +################# ---- Test de : lhi001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, lui, sll +################# ---- Test de : nor000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, nor +################# ---- Test de : or000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, or +################# ---- Test de : or001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, or +################# ---- Test de : or002 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, ori, addui +################# ---- Test de : or002 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de l'addition signee +################# ---- Test de : sle000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de slt +################# ---- Test de : sle000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de slt bis +################# ---- Test de : sle000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, addui, slt +################# ---- Test de : sle000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, addui, slti +################# ---- Test de : sle000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, addui, slt +################# ---- Test de : sle000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, addui, slti +################# ---- Test de : sle000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, addui, sltu +################# ---- Test de : sle000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, addui, sltu +################# ---- Test de : sll000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, sllv +################# ---- Test de : sll001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, loadi,sll +################# ---- Test de : sra000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, srav +################# ---- Test de : sra001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, sra +################# ---- Test de : srl000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, srlv +################# ---- Test de : srl001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addui, srl +################# ---- Test de : sub000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de addi, sub +################# ---- Test de : sub001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, subu +################# ---- Test de : xor000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, xor +################# ---- Test de : xor001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de loadi, xor +################# ---- Test de : xor002 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de slti, xori +************************************************************************** +################# ---- Test de : beq000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de beq 0 +################# ---- Test de : beq001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de beq 1 +################# ---- Test de : bgez000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de bgez0 +################# ---- Test de : bgez001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de bgez1 +################# ---- Test de : bgezal000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de bgezal +################# ---- Test de : bgtz000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de bgtz +################# ---- Test de : blez000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de blez +################# ---- Test de : bltz000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de bltz +################# ---- Test de : bltzal000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de bltzal +################# ---- Test de : bne000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de bne0 +################# ---- Test de : bne001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de bne1 +################# ---- Test de : lhi000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de lhi0 +################# ---- Test de : lhi001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de lhi1 +################# ---- Test de : jal000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de jal0 +################# ---- Test de : jal001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de jal1 +################# ---- Test de : jalr000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de jalr0 +################# ---- Test de : jalr001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de jalr1 +################# ---- Test de : lsb000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de lsb0 +################# ---- Test de : lsb001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de lsb1 +################# ---- Test de : lsb002 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de lsb2 +################# ---- Test de : lsb003 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de lsb3 +################# ---- Test de : lsb004 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de lsb4 +################# ---- Test de : lsb005 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de lsb5 +################# ---- Test de : lsb006 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de lsb6 +################# ---- Test de : lsb007 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de lsb7 +################# ---- Test de : lsbu000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de lsbu0 +################# ---- Test de : lsbu001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de lsbu1 +################# ---- Test de : lsbu002 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de lsbu2 +################# ---- Test de : lsbu003 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de lsbu3 +################# ---- Test de : lsh000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de lsh0 +################# ---- Test de : lsh001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de lsh1 +################# ---- Test de : lsh002 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de lsh2 +################# ---- Test de : lsh003 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de lsh3 +################# ---- Test de : lshu000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de lshu0 +################# ---- Test de : lshu001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de lshu1 +################# ---- Test de : lsw000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de lsw0 +################# ---- Test de : lsw001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de lsw1 +################# ---- Test de : sltu000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de sltu0 +################# ---- Test de : sltu001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de sltu1 +################# ---- Test de : sltu002 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de sltu2 +################# ---- Test de : sltu003 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de sltu3 +################# ---- Test de : sltu004 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de sltu4 +################# ---- Test de : sltiu000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de sltiu0 +################# ---- Test de : sltiu001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de sltiu1 +################# ---- Test de : sltiu002 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de sltiu2 +################# ---- Test de : sltiu003 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de sltiu3 +################# ---- Test de : sltiu004 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de sltiu4 +************************************************************************** +################# ---- Test de : exc000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de mauvais alignement de data +################# ---- Test de : exc001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de ADES +################# ---- Test de : exc002 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test d'OVERFLOW de sum de nb >0 +################# ---- Test de : exc003 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test d'OVERFLOW de sum de nb >0 +################# ---- Test de : exc004 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test d'OVERFLOW de sum de nb >0 +################# ---- Test de : exc005 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test d'OVERFLOW de sum de nb >0 +################# ---- Test de : exc006 ---- ################# +Pas d'erreur ! La chance est avec vous... + illegal instruction address +################# ---- Test de : exc007 ---- ################# +Pas d'erreur ! La chance est avec vous... + Test de ADEL +################# ---- Test de : exc008 ---- ################# +Pas d'erreur ! La chance est avec vous... + Test de ADEL +################# ---- Test de : exc009 ---- ################# +Pas d'erreur ! La chance est avec vous... + ri (when executing a mfc0) +################# ---- Test de : exc010 ---- ################# +Pas d'erreur ! La chance est avec vous... + ri +################# ---- Test de : exc011 ---- ################# +Pas d'erreur ! La chance est avec vous... +adel (when loading a half-word) +################# ---- Test de : exc012 ---- ################# +Pas d'erreur ! La chance est avec vous... +ades (when storing a word) +################# ---- Test de : exc013 ---- ################# +Pas d'erreur ! La chance est avec vous... +sleep +################# ---- Test de : exc014 ---- ################# +Pas d'erreur ! La chance est avec vous... + data bus error +################# ---- Test de : exc015 ---- ################# +Pas d'erreur ! La chance est avec vous... + overflow (when adding positive numbers) +################# ---- Test de : exc016 ---- ################# +Pas d'erreur ! La chance est avec vous... + overflow (when adding positive numbers) +################# ---- Test de : exc017 ---- ################# +Pas d'erreur ! La chance est avec vous... +data bus error +################# ---- Test de : exc018 ---- ################# +Pas d'erreur ! La chance est avec vous... +data bus error +################# ---- Test de : exc019 ---- ################# +Pas d'erreur ! La chance est avec vous... +data bus error +################# ---- Test de : exc020 ---- ################# +Pas d'erreur ! La chance est avec vous... +data bus error +################# ---- Test de : exc021 ---- ################# +Pas d'erreur ! La chance est avec vous... +data bus error +################# ---- Test de : exc022 ---- ################# +Pas d'erreur ! La chance est avec vous... +data bus error +################# ---- Test de : exc023 ---- ################# +Pas d'erreur ! La chance est avec vous... +data bus error +################# ---- Test de : exc024 ---- ################# +Pas d'erreur ! La chance est avec vous... +instruction bus error +************************************************************************** +################# ---- Test de : it000 ---- ################# +Pas d'erreur ! La chance est avec vous... +================= Damned ! Une exception (asimut) ... ======== +test int 00 +################# ---- Test de : it001 ---- ################# +Pas d'erreur ! La chance est avec vous... +================= Damned ! Une exception (asimut) ... ======== +Test int 01 +################# ---- Test de : it002 ---- ################# +Pas d'erreur ! La chance est avec vous... +================= Damned ! Une exception (asimut) ... ======== +Test de int 02 +################# ---- Test de : it003 ---- ################# +Pas d'erreur ! La chance est avec vous... +================= Damned ! Une exception (asimut) ... ======== +Test de int 03 +################# ---- Test de : it004 ---- ################# +Pas d'erreur ! La chance est avec vous... +================= Damned ! Une exception (asimut) ... ======== +Test de int 04 +################# ---- Test de : it005 ---- ################# +Pas d'erreur ! La chance est avec vous... +================= Damned ! Une exception (asimut) ... ======== +Test de int 05 +################# ---- Test de : it006 ---- ################# +test int 06 +************************************************************************** +################# ---- Test de : break_00 ---- ################# +Pas d'erreur ! La chance est avec vous... +test de break +################# ---- Test de : mftc0_00 ---- ################# +Pas d'erreur ! La chance est avec vous... +test de mftc0 +################# ---- Test de : mfthi_00 ---- ################# +Pas d'erreur ! La chance est avec vous... +test de mfthi +################# ---- Test de : mftlo_00 ---- ################# +Pas d'erreur ! La chance est avec vous... +test de mftlo +################# ---- Test de : syscall_00 ---- ################# +Pas d'erreur ! La chance est avec vous... +test de syscall +********************************************************************** +################# ---- Test de : add000 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de add et de addi +################# ---- Test de : add001 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de add et de addi (bis) +################# ---- Test de : add002 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de add et de addi (bis bis) +################# ---- Test de : add003 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de add et de addi bis bis bis +################# ---- Test de : add004 ---- ################# +Pas d'erreur ! La chance est avec vous... +Test de sub, loadi, addi +********************************************************************** diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/rome.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/rome.u new file mode 100644 index 00000000..1d13e9eb --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/rome.u @@ -0,0 +1,41 @@ +; ###----------------------------------------------------------------### +; # # +; # file : syscall_00.u # +; # date : Apr 21 1995 # +; # descr. : functional test for mips # +; # # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # software interrupt : # + ; ###--------------------------------------------------------### + + + .org 0x00400000 + .start init + +init: + + ; ###--------------------------------------------------------### + ; # sotware interrupt # + ; ###--------------------------------------------------------### + + syscall + j bad + + ; ###--------------------------------------------------------### + ; # check that the the trap has been done (r1 must contain # + ; # the trap number) # + ; ###--------------------------------------------------------### + +back_from_exception: + j good ; jump to good if OK + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/rome.vbe b/alliance/src/documentation/alliance-examples/mipsR3000/asm/rome.vbe new file mode 100644 index 00000000..4fc76291 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/rome.vbe @@ -0,0 +1,46 @@ +entity rome is + port ( + address : in bit_vector (5 downto 0); + e_n : in bit; + data : out mux_vector (31 downto 0) bus; + vdd : in bit; + vss : in bit); +end rome; + +architecture VBE of rome is + + signal rom_out : bit_vector (31 downto 0); + +begin + + write_out : block (e_n = '0') + begin + data <= guarded rom_out; + end block; + + with address (5 downto 0) select + rom_out <= + X"afdd0000" when B"100000", + X"afdc0004" when B"100001", + X"201c003c" when B"100010", + X"401d6800" when B"100011", + X"00000021" when B"100100", + X"03bce824" when B"100101", + X"201b0020" when B"100110", + X"17bb0008" when B"100111", + X"00000021" when B"101000", + X"8fdd0000" when B"101001", + X"8fdc0004" when B"101010", + X"401f7000" when B"101011", + X"00000021" when B"101100", + X"23ff0008" when B"101101", + X"03e00008" when B"101110", + X"42000010" when B"101111", + X"401f7000" when B"110000", + X"00000021" when B"110001", + X"23ff0004" when B"110010", + X"03e00008" when B"110011", + X"42000010" when B"110100", + X"00000000" when others; + +end; diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/romr.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/romr.e new file mode 100644 index 00000000..6d13d113 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/romr.e @@ -0,0 +1,40 @@ +; ###----------------------------------------------------------------### +; # file : romr.e # +; # date : 14 novembre 1997 # +; # descr. : rom reset ; remplace romr.vbe # +; ###----------------------------------------------------------------### + +system_stack .equ 0xc0000000 + +reset_sw_int .equ 0x00000000 + +user_status .equ 0x0000ff3c +user_prog .equ 0x00400000 + + .org 0xbfc00000 + + ; ###--------------------------------------------------------### + ; # initialization prgram (hardware RESET) # + ; ###--------------------------------------------------------### + +hardware_reset: + loadi r30, system_stack ; init system stack pointer + + loadi r1 , user_status + mtc0 r1 , status + + loadi r1 , reset_sw_int + mtc0 r1 , cause + + loadi r26, user_prog + + rfe ; return from reset + jr r26 + + + .end + + + + + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/roms.vbe.orig b/alliance/src/documentation/alliance-examples/mipsR3000/asm/roms.vbe.orig new file mode 100644 index 00000000..4f52f257 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/roms.vbe.orig @@ -0,0 +1,32 @@ +entity roms is + port ( + address : in bit_vector (5 downto 0); + e_n : in bit; + data : out mux_vector (31 downto 0) bus; + vdd : in bit; + vss : in bit); +end roms; + +architecture data_flow of roms is + + signal rom_out : bit_vector (31 downto 0); + +begin + + write_out : block (e_n = '0') + begin + data <= guarded rom_out; + end block; + + with address (5 downto 0) select + rom_out <= + X"08000001" when B"100000", + X"00000021" when B"100001", + X"400ef800" when B"100010", + X"00000021" when B"100011", + X"23ff0004" when B"100100", + X"03e00008" when B"100101", + X"42000010" when B"100110", + X"00000000" when others; + +end; diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/romu.vbe b/alliance/src/documentation/alliance-examples/mipsR3000/asm/romu.vbe new file mode 100644 index 00000000..725fbf11 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/romu.vbe @@ -0,0 +1,36 @@ +entity romu is + port ( + address : in bit_vector (5 downto 0); + e_n : in bit; + data : out mux_vector (31 downto 0) bus; + vdd : in bit; + vss : in bit); +end romu; + +architecture VBE of romu is + + signal rom_out : bit_vector (31 downto 0); + +begin + + write_out : block (e_n = '0') + begin + data <= guarded rom_out; + end block; + + with address (5 downto 0) select + rom_out <= + X"2001000a" when B"000000", + X"20020002" when B"000001", + X"00411820" when B"000010", + X"2005000c" when B"000011", + X"10a3002f" when B"000100", + X"08100036" when B"000101", + X"00000021" when B"000110", + X"08100034" when B"110100", + X"00000021" when B"110101", + X"08100036" when B"110110", + X"00000021" when B"110111", + X"00000000" when others; + +end; diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/sle000.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sle000.u new file mode 100644 index 00000000..834d8776 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sle000.u @@ -0,0 +1,33 @@ +; ###----------------------------------------------------------------### +; # file : sle000.u # +; # date : May 20 1995 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # set if less or equal (signed) # + ; ###--------------------------------------------------------### + +data1 .equ 0x809065c0 ; big negative data +data2 .equ 0x60004d23 ; positive data (d1 < d2) + + .org 0x00400000 + .start init + +init: + loadi r11, data1 + loadi r12, data2 + slt r14, r11, r12 ; ri < rj => 1 + addiu r1, r0, 1 + beq r14, r1, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/sle001.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sle001.u new file mode 100644 index 00000000..34b45893 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sle001.u @@ -0,0 +1,32 @@ +; ###----------------------------------------------------------------### +; # file : sle001.u # +; # date : May 20 1995 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # set if less or equal (signed) # + ; ###--------------------------------------------------------### + +data1 .equ 0x60004d23 +data2 .equ 0x809065c0 ; (d2 < d1) + + .org 0x00400000 + .start init + +init: + loadi r11, data1 + loadi r12, data2 + slt r14, r11, r12 ; ri > rj => 0 + beq r14, r0, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/sle002.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sle002.u new file mode 100644 index 00000000..7c2948ef --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sle002.u @@ -0,0 +1,31 @@ +; ###----------------------------------------------------------------### +; # file : sle002.u # +; # date : Apr 1 1993 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # set if less or equal immediate # + ; ###--------------------------------------------------------### + +data .equ 4907 + + .org 0x00400000 + .start init + +init: + addiu r11, r0 , 4906 + slti r14, r11, data ; ri < rj => 1 + addiu r1, r0, 1 + beq r14, r1, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/sle003.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sle003.u new file mode 100644 index 00000000..106c4e84 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sle003.u @@ -0,0 +1,30 @@ +; ###----------------------------------------------------------------### +; # file : sle003.u # +; # date : Apr 1 1993 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # set if less or equal immediate # + ; ###--------------------------------------------------------### + +data .equ 4907 + + .org 0x00400000 + .start init + +init: + addiu r11, r0 , 4907 + slti r14, r11, (data - 1) ; ri > rj => 0 + beq r14, r0, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/sle004.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sle004.u new file mode 100644 index 00000000..c98a3617 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sle004.u @@ -0,0 +1,31 @@ +; ###----------------------------------------------------------------### +; # file : sle004.u # +; # date : May 20 1995 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # set if less or equal mmediate (signed) # + ; ###--------------------------------------------------------### + +data .equ 0x587dcb32 ; big negative data + + .org 0x00400000 + .start init + +init: + loadi r11, data + loadi r12, data + slt r14, r11, r12 ; ri = rj => 0 + beq r14, r0, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/sle005.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sle005.u new file mode 100644 index 00000000..779fa728 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sle005.u @@ -0,0 +1,30 @@ +; ###----------------------------------------------------------------### +; # file : sle005.u # +; # date : Apr 1 1993 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # set if less or equal immediate (signed) # + ; ###--------------------------------------------------------### + +data .equ 4907 + + .org 0x00400000 + .start init + +init: + addiu r11, r0 , 4907 + slti r14, r11, data ; ri = rj => 0 + beq r14, r0, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/sle006.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sle006.u new file mode 100644 index 00000000..16a0a6a1 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sle006.u @@ -0,0 +1,33 @@ +; ###----------------------------------------------------------------### +; # file : sle006.u # +; # date : May 20 1995 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # set if less or equal (unsigned) # + ; ###--------------------------------------------------------### + +data1 .equ 0x60004d23 +data2 .equ 0x809065c0 ; (d2 > d1) + + .org 0x00400000 + .start init + +init: + loadi r11, data1 + loadi r12, data2 + sltu r14, r11, r12 ; ri < rj => 1 + addiu r1, r0, 1 + beq r14, r1, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/sle007.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sle007.u new file mode 100644 index 00000000..6b1d282f --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sle007.u @@ -0,0 +1,32 @@ +; ###----------------------------------------------------------------### +; # file : sle007.u # +; # date : May 20 1995 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # set if less or equal (unsigned) # + ; ###--------------------------------------------------------### + +data1 .equ 0x60004d23 +data2 .equ 0x809065c0 ; (d2 > d1) + + .org 0x00400000 + .start init + +init: + loadi r11, data2 + loadi r12, data1 + sltu r14, r11, r12 ; ri < rj => 0 + beq r14, r0, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/sll000.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sll000.u new file mode 100644 index 00000000..1706a299 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sll000.u @@ -0,0 +1,34 @@ +; ###----------------------------------------------------------------### +; # file : sll000.u # +; # date : Jul 7 1995 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # shift left logical # + ; ###--------------------------------------------------------### + +shift_nbr .equ 4 ; shift number +data .equ 0x045f + + .org 0x00400000 + .start init + +init: + addiu r13, r0 , shift_nbr + addiu r14, r0 , data + + sllv r14, r14, r13 + addiu r12, r0, (data << shift_nbr) + beq r14, r12,good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/sll001.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sll001.u new file mode 100644 index 00000000..6db16f6d --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sll001.u @@ -0,0 +1,33 @@ +; ###----------------------------------------------------------------### +; # file : sll001.u # +; # date : Jul 7 1995 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # shift left logical immediate # + ; ###--------------------------------------------------------### + +shift_nbr .equ 7 +data .equ 0xf5c0 + + .org 0x00400000 + .start init + +init: + loadi r14, data + sll r14, r14, shift_nbr + + loadi r18, (data << shift_nbr) + beq r18, r14,good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/sltiu000.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sltiu000.u new file mode 100644 index 00000000..3de67f7e --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sltiu000.u @@ -0,0 +1,41 @@ +; ###----------------------------------------------------------------### +; # # +; # file : sltiu000.u # +; # date : Nov 1996 # +; # descr. : functional test for mips # +; # # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # set if less than immediate unsigned # + ; ###--------------------------------------------------------### + +data .equ 8 +mask .equ 0xffff +mask1 .equ 0xfff9 +mask2 .equ 0xfffd +cste .equ 1 + .org 0x00400000 + .start init + +init: + addiu r1 , r0, cste + lui r13, mask + addiu r16, r0 , mask1 + or r13, r13, r16 + lui r14, mask + addiu r16, r0 , mask2 + or r14, r14, r16 + sltiu r14, r13, mask2 + beq r14, r1 ,good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/sltiu001.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sltiu001.u new file mode 100644 index 00000000..b1eb1634 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sltiu001.u @@ -0,0 +1,38 @@ +; ###----------------------------------------------------------------### +; # # +; # file : sltiu001.u # +; # date : Nov 1996 # +; # descr. : functional test for mips # +; # # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # set if less than immediate unsigned # + ; ###--------------------------------------------------------### + +data .equ 8 +mask .equ 0xffff +mask1 .equ 0xfffd +mask2 .equ 0xfff9 +cste .equ 1 + .org 0x00400000 + .start init + +init: + addiu r1 , r0 , cste + lui r13, mask + addiu r16, r0 , mask1 + or r13, r13, r16 + sltiu r14, r13, mask2 + beq r14, r0 ,good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/sltiu002.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sltiu002.u new file mode 100644 index 00000000..806ea346 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sltiu002.u @@ -0,0 +1,34 @@ +; ###----------------------------------------------------------------### +; # # +; # file : sltiu002.u # +; # date : Nov 1996 # +; # descr. : functional test for mips # +; # # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # set if less than immediate unsigned # + ; ###--------------------------------------------------------### + +data .equ 8 +cste .equ 1 + .org 0x00400000 + .start init + +init: + addiu r1 , r0, cste + addiu r13, r0 , ( data - 2 ) + addiu r14, r0 , data + sltiu r14, r13, data + beq r14, r1 ,good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/sltiu003.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sltiu003.u new file mode 100644 index 00000000..b5bde7a3 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sltiu003.u @@ -0,0 +1,33 @@ +; ###----------------------------------------------------------------### +; # # +; # file : sltiu003.u # +; # date : Nov 1996 # +; # descr. : functional test for mips # +; # # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # set if less than immediate # + ; ###--------------------------------------------------------### + +data .equ 8 +cste .equ 1 + .org 0x00400000 + .start init + +init: + addiu r1 , r0 , cste + addiu r13, r0 , data + sltiu r14, r13, ( data - 2) + beq r14, r0 ,good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/sltiu004.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sltiu004.u new file mode 100644 index 00000000..2d026660 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sltiu004.u @@ -0,0 +1,33 @@ +; ###----------------------------------------------------------------### +; # # +; # file : sltiu004.u # +; # date : Nov 1996 # +; # descr. : functional test for mips # +; # # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # set if less than immediate unsigned # + ; ###--------------------------------------------------------### + +data .equ 8 +cste .equ 1 + .org 0x00400000 + .start init + +init: + addiu r1 , r0 , cste + addiu r13, r0 , data + sltiu r14, r13, data + beq r14, r0 ,good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/sltu000.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sltu000.u new file mode 100644 index 00000000..780247e1 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sltu000.u @@ -0,0 +1,41 @@ +; ###----------------------------------------------------------------### +; # # +; # file : sltu000.u # +; # date : Nov 1996 # +; # descr. : functional test for mips # +; # # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # set if less than unsigned register # + ; ###--------------------------------------------------------### + +data .equ 8 +data1 .equ 0xfffd ; -3 +data2 .equ 0xfff9 ; -7 +mask .equ 0xffff +cste .equ 1 + .org 0x00400000 + .start init + +init: + addiu r1 , r0, cste + lui r13, mask + addiu r16, r0 , data2 + or r13, r13, r16 + lui r14, mask + addiu r16, r0 , data1 + or r14, r14, r16 + sltu r14, r13, r14 + beq r14, r1 ,good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/sltu001.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sltu001.u new file mode 100644 index 00000000..7293befc --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sltu001.u @@ -0,0 +1,41 @@ +; ###----------------------------------------------------------------### +; # # +; # file : sltu001.u # +; # date : Nov 1996 # +; # descr. : functional test for mips # +; # # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # set if less than unsigned register # + ; ###--------------------------------------------------------### + +data .equ 8 +data1 .equ 0xfff9 +data2 .equ 0xfffd +mask .equ 0xffff +cste .equ 1 + .org 0x00400000 + .start init + +init: + addiu r1 , r0 , cste + lui r13, mask + addiu r16, r0 , data2 + or r13, r13, r16 + lui r14, mask + addiu r16, r0 , data1 + or r14, r14, r16 + sltu r14, r13, r14 + beq r14, r0 ,good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/sltu002.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sltu002.u new file mode 100644 index 00000000..15cf48bb --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sltu002.u @@ -0,0 +1,34 @@ +; ###----------------------------------------------------------------### +; # # +; # file : sltu002.u # +; # date : Nov 1996 # +; # descr. : functional test for mips # +; # # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # set if less than unsigned register # + ; ###--------------------------------------------------------### + +data .equ 8 +cste .equ 1 + .org 0x00400000 + .start init + +init: + addiu r1 , r0, cste + addiu r13, r0 , ( data - 2 ) + addiu r14, r0 , data + sltu r14, r13, r14 + beq r14, r1 ,good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/sltu003.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sltu003.u new file mode 100644 index 00000000..f002a41f --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sltu003.u @@ -0,0 +1,34 @@ +; ###----------------------------------------------------------------### +; # # +; # file : sltu003.u # +; # date : Nov 1996 # +; # descr. : functional test for mips # +; # # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # set if less than unsigned register # + ; ###--------------------------------------------------------### + +data .equ 8 +cste .equ 1 + .org 0x00400000 + .start init + +init: + addiu r1 , r0 , cste + addiu r13, r0 , data + addiu r14, r0, (data -2 ) + sltu r14, r13, r14 + beq r14, r0 ,good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/sltu004.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sltu004.u new file mode 100644 index 00000000..f8767165 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sltu004.u @@ -0,0 +1,34 @@ +; ###----------------------------------------------------------------### +; # # +; # file : sltu004.u # +; # date : Nov 1996 # +; # descr. : functional test for mips # +; # # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # set if less than unsigned register # + ; ###--------------------------------------------------------### + +data .equ 8 +cste .equ 1 + .org 0x00400000 + .start init + +init: + addiu r1 , r0 , cste + addiu r13, r0 , data + addiu r14, r0, data + sltu r14, r13, r14 + beq r14, r0 ,good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/sra000.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sra000.u new file mode 100644 index 00000000..4183224b --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sra000.u @@ -0,0 +1,34 @@ +; ###----------------------------------------------------------------### +; # file : sra000.u # +; # date : Jul 7 1995 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # shift right arithmetical # + ; ###--------------------------------------------------------### + +shift_nbr .equ 5 +data .equ 0xcb09 + + .org 0x00400000 + .start init + +init: + addiu r13, r0 , shift_nbr + loadi r14, data + + srav r14, r14, r13 + addiu r12, r0, (data >> shift_nbr) + beq r14, r12,good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/sra001.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sra001.u new file mode 100644 index 00000000..c1243f7a --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sra001.u @@ -0,0 +1,33 @@ +; ###----------------------------------------------------------------### +; # file : sra001.u # +; # date : Jul 7 1995 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # shift right arithmetical immediate # + ; ###--------------------------------------------------------### + +shift_nbr .equ 12 +data .equ 0x4570 + + .org 0x00400000 + .start init + +init: + addiu r14, r0 , data + sra r14, r14, shift_nbr + + addiu r12, r0, (data >> shift_nbr) + beq r12, r14,good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/srl000.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/srl000.u new file mode 100644 index 00000000..5a8e7f3f --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/srl000.u @@ -0,0 +1,34 @@ +; ###----------------------------------------------------------------### +; # file : srl000.u # +; # date : Jul 7 1995 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # shift right logical # + ; ###--------------------------------------------------------### + +shift_nbr .equ 13 +data .equ 0x6479 + + .org 0x00400000 + .start init + +init: + addiu r13, r0 , shift_nbr + addiu r14, r0 , data + + srlv r14, r14, r13 + addiu r12, r0, (data & 0x0000ffff) >> shift_nbr + beq r12, r14,good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/srl001.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/srl001.u new file mode 100644 index 00000000..02e7e28a --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/srl001.u @@ -0,0 +1,33 @@ +; ###----------------------------------------------------------------### +; # file : srl001.u # +; # date : Jul 7 1995 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # shift right logical immediate # + ; ###--------------------------------------------------------### + +shift_nbr .equ 9 +data .equ 0xfd71 + + .org 0x00400000 + .start init + +init: + loadi r14, data + srl r14, r14, shift_nbr + + addiu r12, r0, (data & 0x0000ffff) >> shift_nbr + beq r12, r14,good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/sub000.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sub000.u new file mode 100644 index 00000000..2e808e27 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sub000.u @@ -0,0 +1,32 @@ +; ###----------------------------------------------------------------### +; # file : sub000.u # +; # date : Apr 1 1993 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # signed substraction # + ; ###--------------------------------------------------------### + + .org 0x00400000 +const .equ 0xfb49 + .start init + +init: + addi r25, r0, const + addi r26, r0, const + 1 + + sub r30, r26, r25 + bne r30, r0,good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/sub001.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sub001.u new file mode 100644 index 00000000..c4fab718 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/sub001.u @@ -0,0 +1,33 @@ +; ###----------------------------------------------------------------### +; # file : sub001.u # +; # date : Apr 1 1993 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # unsigned substraction # + ; ###--------------------------------------------------------### + + .org 0x00400000 +const1 .equ 0xfb491234 +const2 .equ 0xfb491235 + .start init + +init: + loadi r25, const1 + loadi r26, const2 + + subu r30, r25, r26 + bne r30, r0, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/syscall_00.e b/alliance/src/documentation/alliance-examples/mipsR3000/asm/syscall_00.e new file mode 100644 index 00000000..3c1e6135 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/syscall_00.e @@ -0,0 +1,61 @@ + +; ###----------------------------------------------------------------### +; # file : syscall_00.s # +; # date : Mar 26 1996 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # exceptions : # + ; # - syscall # + ; ###--------------------------------------------------------### + +val1 .equ 0x3C + +val .equ 0x20 + + .org 0x80000080 + .start it_handler + + ; ###--------------------------------------------------------### + ; # interrupt and exception handler # + ; ###--------------------------------------------------------### + +it_handler: + + sw r29, 0 (r30) + sw r28, 4 (r30) + + addi r28, r0, val1 + mfc0 r29, cause + nop + and r29, r29, r28 + addi r27, r0, val + bne r29, r27, not_good + nop + + lw r29, 0 (r30) + lw r28, 4 (r30) + + ; ###--------------------------------------------------------### + ; # restore return address before returning (from EXCEPTION) # + ; # to the user program (address must be saved by the user # + ; # prior to the EXCEPTION in epc) # + ; ###--------------------------------------------------------### + +restore_return_adr: + mfc0 r31,epc + nop + addi r31,r31,8 + jr r31 + rfe + +not_good: + mfc0 r31,epc + nop + addi r31,r31,4 + jr r31 + rfe + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/syscall_00.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/syscall_00.u new file mode 100644 index 00000000..1d13e9eb --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/syscall_00.u @@ -0,0 +1,41 @@ +; ###----------------------------------------------------------------### +; # # +; # file : syscall_00.u # +; # date : Apr 21 1995 # +; # descr. : functional test for mips # +; # # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # software interrupt : # + ; ###--------------------------------------------------------### + + + .org 0x00400000 + .start init + +init: + + ; ###--------------------------------------------------------### + ; # sotware interrupt # + ; ###--------------------------------------------------------### + + syscall + j bad + + ; ###--------------------------------------------------------### + ; # check that the the trap has been done (r1 must contain # + ; # the trap number) # + ; ###--------------------------------------------------------### + +back_from_exception: + j good ; jump to good if OK + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/xor000.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/xor000.u new file mode 100644 index 00000000..827b9053 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/xor000.u @@ -0,0 +1,34 @@ +; ###----------------------------------------------------------------### +; # file : xor000.u # +; # date : Apr 1 1993 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # logical exclusive or # + ; ###--------------------------------------------------------### + +data1 .equ 0x11111111 +data2 .equ 0x00000000 + + .org 0x00400000 + .start init +init: + loadi r1 , data1 + loadi r2 , data2 + loadi r4 , (data1 ^ data2) + + xor r3 , r1 , r2 + + bne r4,r3, bad + nop + j good + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/xor001.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/xor001.u new file mode 100644 index 00000000..6bc19e65 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/xor001.u @@ -0,0 +1,34 @@ +; ###----------------------------------------------------------------### +; # file : xor000.u # +; # date : Apr 1 1993 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # logical exclusive or # + ; ###--------------------------------------------------------### + +data1 .equ 0x1234db11 +data2 .equ 0x0089dac0 + + .org 0x00400000 + .start init +init: + loadi r1 , data1 + loadi r2 , data2 + loadi r4 , (data1 ^ data2) + + xor r3 , r1 , r2 + + bne r4,r3, bad + nop + j good + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/asm/xor002.u b/alliance/src/documentation/alliance-examples/mipsR3000/asm/xor002.u new file mode 100644 index 00000000..49b6aae6 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/asm/xor002.u @@ -0,0 +1,30 @@ +; ###----------------------------------------------------------------### +; # file : xor002.u # +; # date : Apr 1 1993 # +; # descr. : functional test for mips # +; ###----------------------------------------------------------------### + + ; ###--------------------------------------------------------### + ; # logical exclusive or # + ; ###--------------------------------------------------------### + +const .equ 45 + + .org 0x00400000 + .start init + +init: + xori r1 , r0 , const + slti r30, r1 , const + beq r30, r0, good + nop + j bad + nop + + .org 0x004000d0 +good: j good + nop +bad: j bad + nop + .end + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/CATAL_CTL b/alliance/src/documentation/alliance-examples/mipsR3000/sce/CATAL_CTL new file mode 100644 index 00000000..f82929fd --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/CATAL_CTL @@ -0,0 +1,8 @@ +romu C +rome C +romr C +roms C +sr64_1a C +timer C +mips_dec C +mips_dpt C diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/CATAL_VBE b/alliance/src/documentation/alliance-examples/mipsR3000/sce/CATAL_VBE new file mode 100644 index 00000000..5c988833 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/CATAL_VBE @@ -0,0 +1,10 @@ +romu C +rome C +romr C +roms C +sr64_1a C +timer C +mips_dec C +mips_dpt C +mips_seqo C +mips_sts C diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/CATAL_VST b/alliance/src/documentation/alliance-examples/mipsR3000/sce/CATAL_VST new file mode 100644 index 00000000..2f7cca22 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/CATAL_VST @@ -0,0 +1,7 @@ +romu C +rome C +romr C +roms C +sr64_1a C +timer C +mips_dec C diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/Makefile b/alliance/src/documentation/alliance-examples/mipsR3000/sce/Makefile new file mode 100644 index 00000000..1560ac84 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/Makefile @@ -0,0 +1,288 @@ + + +# Standart System binary access paths. + STANDART_BIN = /bin:/usr/local/bin:/usr/bin + STANDART_PATH = PATH=$(STANDART_BIN); export PATH + +# Standart Alliance binary access paths. +# ALLIANCE_BIN = $(ALLIANCE_TOP)/bin + +# FitPath Alliance binary access paths. +# DEVEL_BIN = /users/soft5/newlabo/alliance-4.5.0/archi/Solaris/bin + +# -------------------------------------------------------------------- +# Standarts binaries. + + LS = /bin/ls + CD = PATH=$(STANDART_BIN); cd + CP = PATH=$(STANDART_BIN); cp -f + LN = PATH=$(STANDART_BIN); ln + MV = PATH=$(STANDART_BIN); mv + RM = PATH=$(STANDART_BIN); rm -f + SED = PATH=$(STANDART_BIN); sed + AWK = PATH=$(STANDART_BIN); gawk + CAT = PATH=$(STANDART_BIN); cat + MAKE = PATH=$(STANDART_BIN); make + ECHO = /bin/echo +# Alliance paths and formats settings. + GENERAT_LO = vst + EXTRACT_LO = al + CARAC_LO = spi + GENERAT_PH = ap + EXTRACT_PH = ap + GENERAT_SP = . + EXTRACT_SP = . + CATA_LIB0 = $(ALLIANCE_TOP)/cells/sxlib + CATA_LIB1 = $(ALLIANCE_TOP)/cells/dp_sxlib + CATA_LIB2 = $(ALLIANCE_TOP)/cells/padlib + CATA_LIB3 = $(ALLIANCE_TOP)/cells/rflib + CATA_LIB = .:$(CATA_LIB0):$(CATA_LIB1):$(CATA_LIB2):$(CATA_LIB3) + TARGET_LIB = $(ALLIANCE_TOP)/cells/sxlib + FPGEN_LIB = $(CATA_LIB0):$(CATA_LIB1) + TECHNO_NAME = local-cmos + CARAC_TECHNO_NAME = local-cmos-035 +CARAC_SPI_MODEL = ./model + +SPI_MODEL = $(ALLIANCE_TOP)/etc/spimodel.cfg +RDS_TECHNO = local-cmos-035.rds + +ENV_COUGAR_SPI = MBK_WORK_LIB=.; export MBK_WORK_LIB; \ + MBK_IN_LO=spi; export MBK_IN_LO; \ + MBK_OUT_LO=spi; export MBK_OUT_LO; \ + MBK_SPI_MODEL=$(SPI_MODEL); export MBK_SPI_MODEL; \ + MBK_SPI_NAMEDNODES="true"; export MBK_SPI_NAMEDNODES; \ + RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME; \ + RDS_IN=cif; export RDS_IN; \ + RDS_OUT=cif; export RDS_OUT; \ + MBK_CATA_LIB=$(CATA_LIB); export MBK_CATA_LIB; \ + MBK_IN_PH=ap; export MBK_IN_PH; \ + MBK_OUT_PH=ap; export MBK_OUT_PH; \ + MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME + + + MBK_GENERAT_ENV = MBK_TARGET_LIB=$(TARGET_LIB); export MBK_TARGET_LIB;\ + MBK_WORK_LIB=.; export MBK_WORK_LIB; \ + MBK_CATA_LIB=$(CATA_LIB); export MBK_CATA_LIB; \ + MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME;\ + MBK_OUT_LO=$(GENERAT_LO); export MBK_OUT_LO; \ + MBK_OUT_PH=$(GENERAT_PH); export MBK_OUT_PH; \ + MBK_IN_LO=$(GENERAT_LO); export MBK_IN_LO; \ + MBK_IN_PH=$(GENERAT_PH); export MBK_IN_PH; \ + MBK_SEPAR=$(GENERAT_SP); export MBK_SEPAR; \ + MBK_VDD=vdd; export MBK_VDD; \ + MBK_VSS=vss; export MBK_VSS; \ + FPGEN_LIB=$(FPGEN_LIB); export FPGEN_LIB; \ + RDS_TECHNO_NAME=$(TECHNO_NAME).rds; export RDS_TECHNO_NAME + +# MBK extracting environment. + MBK_EXTRACT_ENV = MBK_TARGET_LIB=$(TARGET_LIB); export MBK_TARGET_LIB; \ + MBK_WORK_LIB=.; export MBK_WORK_LIB; \ + MBK_CATA_LIB=$(CATA_LIB); export MBK_CATA_LIB; \ + MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME; \ + MBK_OUT_LO=$(EXTRACT_LO); export MBK_OUT_LO; \ + MBK_OUT_PH=$(EXTRACT_PH); export MBK_OUT_PH; \ + MBK_IN_LO=$(EXTRACT_LO); export MBK_IN_LO; \ + MBK_IN_PH=$(EXTRACT_PH); export MBK_IN_PH; \ + MBK_SEPAR=$(EXTRACT_SP); export MBK_SEPAR; \ + MBK_VDD=vdd; export MBK_VDD; \ + MBK_VSS=vss; export MBK_VSS; \ + RDS_TECHNO_NAME=$(TECHNO_NAME).rds; export RDS_TECHNO_NAME + +# MBK caracterisation. + MBK_CARAC_ENV = MBK_TARGET_LIB=$(TARGET_LIB); export MBK_TARGET_LIB; \ + MBK_WORK_LIB=.; export MBK_WORK_LIB; \ + MBK_CATA_LIB=$(CATA_LIB); export MBK_CATA_LIB; \ + MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME; \ + MBK_OUT_LO=$(CARAC_LO); export MBK_OUT_LO; \ + MBK_SPI_MODEL=$(CARAC_SPI_MODEL); export MBK_SPI_MODEL; \ + MBK_OUT_PH=$(EXTRACT_PH); export MBK_OUT_PH; \ + MBK_IN_LO=$(EXTRACT_LO); export MBK_IN_LO; \ + MBK_IN_PH=$(EXTRACT_PH); export MBK_IN_PH; \ + MBK_SEPAR=$(EXTRACT_SP); export MBK_SEPAR; \ + MBK_VDD=vdd; export MBK_VDD; \ + MBK_VSS=vss; export MBK_VSS; \ + RDS_IN=cif; export RDS_IN; RDS_OUT=cif; export RDS_OUT;\ + RDS_TECHNO_NAME=$(CARAC_TECHNO_NAME).rds; export RDS_TECHNO_NAME + + +# -------------------------------------------------------------------- +# Alliance binaries & environment. + + GRAAL = $(MBK_GENERAT_ENV); GRAAL_TECHNO_NAME=$(TECHNO_NAME).graal; export GRAAL_TECHNO_NAME;$(ALLIANCE_BIN)/graal + ASIMUT = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/asimut -zd -bdd +# ASIMUT = $(MBK_GENERAT_ENV); /users/enseig/mips4/new_asimut -zd -bdd + FLATBEH = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/flatbeh + FLATLO = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/flatlo + LYNX = $(MBK_EXTRACT_ENV); $(ALLIANCE_BIN)/cougar -v + LYNX3 = $(ENV_COUGAR_SPI); $(ALLIANCE_BIN)/cougar -v + DRUC = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/druc + LVX = $(MBK_EXTRACT_ENV); $(ALLIANCE_BIN)/lvx + PROOF = $(MBK_EXTRACT_ENV); $(ALLIANCE_BIN)/proof + RING = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/ring + DPGEN = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/genlib + OCP = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/ocp -v -gnuplot + OCR = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/ocr + NERO = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/nero -V + S2R = $(MBK_CARAC_ENV); $(ALLIANCE_BIN)/s2r -v + + + + +GENPAT = $(ALLIANCE_BIN)/genpat +GENLIB = $(MBK_GENERAT_ENV);$(ALLIANCE_BIN)/genlib +SYF = $(MBK_GENERAT_ENV);$(ALLIANCE_BIN)/syf -a -CVE +BOOM = $(MBK_GENERAT_ENV);$(ALLIANCE_BIN)/boom -A -V -l 2 -s +BOOG = $(MBK_GENERAT_ENV);$(ALLIANCE_BIN)/boog +LOON = $(MBK_GENERAT_ENV);$(ALLIANCE_BIN)/loon +SCAPIN = $(MBK_GENERAT_ENV);$(ALLIANCE_BIN)/scapin -VRB +MIPS_ASM = $(ALLIANCE_BIN)/mips_asm +# pour un bench (test en cours de creation on pourra l'enlever apres) +BENCH = ./bench.sh add000 CONF +# pour tester l'ensemble des programmes (confirmation finale) +ALLBENCH = ./allbench.sh DEFINITIF + +# /*------------------------------------------------------------\ +# | | +# | Alliance Tools | +# | | +# \------------------------------------------------------------*/ + + +# /*------------------------------------------------------------\ +# | | +# | Environement Variables | +# | | +# \------------------------------------------------------------*/ +# /*------------------------------------------------------------\ +# | | +# | Unix Command | +# | | +# \------------------------------------------------------------*/ + +# /*------------------------------------------------------------\ +# | | +# | | +# | | +# \------------------------------------------------------------*/ + +mips_chip.cif : mips_chip.ap + $(S2R) -r mips_chip mips_chip + +mips_chip_t.al : mips_chip.ap + $(LYNX) -t -ac -ar mips_chip mips_chip_t + +mips_core_t.al : mips_core.ap + $(LYNX) -c -t -ac -ar mips_core mips_core_t + +mips_chip.ap : mips_core.ap mips_chip.vst mips_chip.rin mips_core.vst mips_core.al + $(CP) CATAL_VST CATAL + $(RING) mips_chip mips_chip + +mips_core.al : mips_core.ap + $(CP) CATAL_VST CATAL + $(LYNX) -c -f mips_core mips_core + $(LVX) vst al mips_core mips_core -f + +mips_core.spi : mips_core.ap + $(LYNX3) -ac -f mips_core mips_core + +mips_core_et.spi : mips_core.ap + $(LYNX3) -ac -t mips_core mips_core_et + +# mips_core.ap : mips_core_p.ap mips_ctl.vst +# $(CP) CATAL_VST CATAL +# $(OCR) -P mips_core_p -L mips_core -O mips_core_p_ocr -v -w 1 -l 5 -i 100 +# cat mips_core_p_ocr.ap | sed s/core_p_ocr/core/ > mips_core.ap +# $(DRUC) mips_core + +mips_core.ap : mips_core_p.ap mips_ctl.vst + $(CP) CATAL_VST CATAL + $(NERO) -6 -p mips_core_p mips_core mips_core_p_nero + cat mips_core_p_nero.ap | sed s/core_p_nero/core/ > mips_core.ap + $(DRUC) mips_core + +mips_core_p.ap : mips_core_place.ap mips_ctl.vst mips_core.ioc + $(CP) CATAL_VST CATAL + $(OCP) -partial mips_core_place -ioc mips_core mips_core mips_core_p + +mips_core_place.ap : mips_core.c mips_dpt.ap + $(DPGEN) mips_core + +mips_ctl.vst : mips_ctl_loon.vst mips_ctl.path + $(SCAPIN) -P mips_ctl.scapin mips_ctl_loon mips_ctl mips_ctl + +mips_ctl_loon.vst : mips_sts.vst mips_seqo.vst mips_ctl.lax + $(CP) CATAL_CTL CATAL + $(FLATLO) -r mips_ctl_nt mips_ctl_flat + $(LOON) mips_ctl_flat mips_ctl_loon -l mips_ctl + +mips_seqo.vst : mips_seqo_optim.vbe mips_ctl.lax + $(BOOG) mips_seqo_optim mips_seqo -l mips_ctl + +mips_sts.vst : mips_sts_optim.vbe mips_ctl.lax + $(BOOG) mips_sts_optim mips_sts -l mips_ctl + +mips_seqo_optim.vbe : mips_seqo.vbe + $(BOOM) mips_seqo mips_seqo_optim + +mips_sts_optim.vbe : mips_sts.vbe + $(BOOM) mips_sts mips_sts_optim + +mips_bench : mips_cpu.pat mips_cpu.vst + $(BENCH) + @echo "<---------- resultat a regarder dans CONF ---------------->" + + +mips_dpt.ap model_shift.ap : mips_dpt.c + $(DPGEN) mips_dpt + +mips_seqo.vbe : mips_seq.fsm + $(SYF) mips_seq mips_seqo + +mips_allbench : + $(CP) CATAL_VST CATAL + $(ALLBENCH) + @echo "<---------- resultat a regarder dans DEFINITIF ---------------->" + +mips_test : mips_ctl.vst mips_scan.pat + $(ASIMUT) -p 50 mips_cpu mips_scan resultat 2> ajeter + +mips_scan.pat : mips_scan.c + $(GENPAT) mips_scan + +graal : + $(GRAAL) + +clean : + $(RM) mips_dpt.vst; + $(RM) *.dtx; + $(RM) *.ttx; + $(RM) *.drc; + $(RM) *.rcx; + $(RM) *.cif; + $(RM) *.spi; + $(RM) *.rep; + $(RM) *.ap; + $(RM) *.al; + $(RM) mips_ctl.vst; + $(RM) mips_ctl_flat.vst; + $(RM) mips_ctl_loon.vst; + $(RM) res.pat + $(RM) resultat.pat + $(RM) res2 + $(RM) mips_sts.xsc + $(RM) mips_sts.vst + $(RM) mips_sts_optim.vbe + $(RM) mips_seqo_optim.vbe + $(RM) machin + $(RM) bench/*.good + $(RM) CONF + $(RM) CATAL + $(RM) dat* + $(RM) DEFINITIF + $(RM) mips_seqo* + $(RM) *.xsc + $(RM) *.gpl + $(RM) *.gds + $(RM) model* + $(RM) alldata.dat diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/local-cmos-035.rds b/alliance/src/documentation/alliance-examples/mipsR3000/sce/local-cmos-035.rds new file mode 100644 index 00000000..39800e15 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/local-cmos-035.rds @@ -0,0 +1,417 @@ +# +# Virtual 0.35 techno with 8 metal layers for the MIPS tutorial +# +DEFINE PHYSICAL_GRID 0.025 + +DEFINE LAMBDA 0.300 + +TABLE MBK_TO_RDS_SEGMENT + + NWELL RDS_NWELL VW 0.950 1.900 0.000 ALL + PWELL RDS_PWELL VW 0.950 1.900 0.000 ALL + NDIF RDS_NDIF VW 0.100 -0.100 0.000 EXT\ + RDS_ACTIV VW 0.100 -0.100 0.000 DRC\ + RDS_NIMP VW 0.400 0.500 0.000 DRC\ + RDS_PWELL VW 1.200 2.100 0.000 DRC + PDIF RDS_PDIF VW 0.100 -0.100 0.000 EXT\ + RDS_ACTIV VW 0.100 -0.100 0.000 DRC\ + RDS_PIMP VW 0.400 0.500 0.000 DRC\ + RDS_NWELL VW 1.200 2.100 0.000 DRC + NTIE RDS_NTIE VW 0.100 -0.100 0.000 EXT\ + RDS_ACTIV VW 0.100 -0.100 0.000 DRC\ + RDS_NIMP VW 0.400 0.500 0.000 EXT\ + RDS_NWELL VW 1.200 2.100 0.000 DRC + PTIE RDS_PTIE VW 0.100 -0.100 0.000 EXT\ + RDS_ACTIV VW 0.100 -0.100 0.000 DRC\ + RDS_PIMP VW 0.400 0.500 0.000 DRC\ + RDS_PWELL VW 1.200 2.100 0.000 DRC + NTRANS RDS_POLY VW 0.000 0.050 0.000 ALL\ + RDS_NDIF LCW -0.500 0.750 0.025 EXT\ + RDS_NDIF RCW -0.500 0.750 0.025 EXT\ + RDS_ACTIV VW -0.500 1.350 0.000 DRC\ + RDS_NIMP VW -0.200 1.950 0.000 DRC\ + RDS_PWELL VW 0.600 3.550 0.000 ALL + PTRANS RDS_POLY VW 0.000 0.050 0.000 ALL\ + RDS_PDIF LCW -0.500 0.750 0.025 EXT\ + RDS_PDIF RCW -0.500 0.750 0.025 EXT\ + RDS_ACTIV VW -0.500 1.350 0.000 DRC\ + RDS_PIMP VW -0.200 1.950 0.000 DRC\ + RDS_NWELL VW 0.600 3.550 0.000 ALL + POLY RDS_POLY VW 0.175 0.050 0.000 ALL + ALU1 RDS_ALU1 VW 0.300 0.300 0.000 ALL + ALU2 RDS_ALU2 VW 0.350 0.100 0.000 ALL + ALU3 RDS_ALU3 VW 0.450 0.000 0.000 ALL + ALU4 RDS_ALU4 VW 0.450 0.000 0.000 ALL + ALU5 RDS_ALU5 VW 0.450 0.000 0.000 ALL + ALU6 RDS_ALU6 VW 0.450 0.000 0.000 ALL + ALU7 RDS_ALU7 VW 0.450 0.000 0.000 ALL + ALU8 RDS_ALU8 VW 0.450 0.000 0.000 ALL + CALU1 RDS_ALU1 VW 0.300 0.300 0.000 ALL + CALU2 RDS_ALU2 VW 0.350 0.100 0.000 ALL + CALU3 RDS_ALU3 VW 0.450 0.000 0.000 ALL + CALU4 RDS_ALU4 VW 0.450 0.000 0.000 ALL + CALU5 RDS_ALU5 VW 0.450 0.000 0.000 ALL + CALU6 RDS_ALU6 VW 0.450 0.000 0.000 ALL + CALU7 RDS_ALU7 VW 0.450 0.000 0.000 ALL + CALU8 RDS_ALU8 VW 0.450 0.000 0.000 ALL +END +TABLE MBK_TO_RDS_CONNECTOR + POLY RDS_POLY 0.175 0.050 + ALU1 RDS_ALU1 0.300 0.300 + ALU2 RDS_ALU2 0.350 0.100 + ALU3 RDS_ALU3 0.450 0.000 + ALU4 RDS_ALU4 0.450 0.000 + ALU5 RDS_ALU5 0.450 0.000 + ALU6 RDS_ALU6 0.450 0.000 + ALU7 RDS_ALU7 0.450 0.000 + ALU8 RDS_ALU8 0.450 0.000 +END +TABLE MBK_TO_RDS_REFERENCE + REF_REF RDS_REF 0.600 + REF_CON RDS_REF 0.600 +END +TABLE MBK_TO_RDS_VIA + CONT_BODY_N \ + RDS_ALU1 0.900 ALL\ + RDS_CONT 0.400 ALL\ + RDS_ACTIV 0.800 DRC\ + RDS_NIMP 1.400 DRC\ + RDS_NWELL 3.000 DRC\ + RDS_NTIE 0.800 EXT + CONT_BODY_P \ + RDS_ALU1 0.900 ALL\ + RDS_CONT 0.400 ALL\ + RDS_ACTIV 0.800 DRC\ + RDS_PIMP 1.400 DRC\ + RDS_PWELL 3.000 DRC\ + RDS_PTIE 0.800 EXT + CONT_DIF_N \ + RDS_ALU1 0.900 ALL\ + RDS_CONT 0.400 ALL\ + RDS_ACTIV 0.800 DRC\ + RDS_NIMP 1.400 DRC\ + RDS_PWELL 3.000 DRC\ + RDS_NDIF 0.800 EXT + CONT_DIF_P \ + RDS_ALU1 0.900 ALL\ + RDS_CONT 0.400 ALL\ + RDS_ACTIV 0.800 DRC\ + RDS_PIMP 1.400 DRC\ + RDS_NWELL 3.000 DRC\ + RDS_PDIF 0.800 EXT + CONT_POLY \ + RDS_ALU1 0.900 ALL\ + RDS_CONT 0.400 ALL\ + RDS_POLY 0.950 ALL + CONT_VIA \ + RDS_ALU1 0.900 ALL\ + RDS_VIA1 0.400 ALL\ + RDS_ALU2 1.000 ALL + CONT_VIA2 \ + RDS_ALU2 1.000 ALL\ + RDS_VIA2 0.400 ALL\ + RDS_ALU3 0.900 ALL + CONT_VIA3 \ + RDS_ALU3 0.900 ALL\ + RDS_VIA3 0.400 ALL\ + RDS_ALU4 0.900 ALL + CONT_VIA4 \ + RDS_ALU4 0.900 ALL\ + RDS_VIA4 0.400 ALL\ + RDS_ALU5 0.900 ALL + CONT_VIA5 \ + RDS_ALU5 0.900 ALL\ + RDS_VIA5 0.400 ALL\ + RDS_ALU6 0.900 ALL + CONT_VIA6 \ + RDS_ALU6 0.900 ALL\ + RDS_VIA6 0.400 ALL\ + RDS_ALU7 0.900 ALL + CONT_VIA7 \ + RDS_ALU7 0.900 ALL\ + RDS_VIA7 0.400 ALL\ + RDS_ALU8 0.900 ALL + C_X_N \ + RDS_POLY 0.350 ALL\ + RDS_ACTIV 1.650 DRC\ + RDS_NIMP 2.250 DRC\ + RDS_PWELL 3.850 DRC\ + RDS_NDIF 1.650 EXT + C_X_P \ + RDS_POLY 0.350 ALL\ + RDS_ACTIV 1.650 DRC\ + RDS_PIMP 2.250 DRC\ + RDS_NWELL 3.850 DRC\ + RDS_PDIF 1.650 EXT +END +TABLE CIF_LAYER + RDS_NWELL NWEL + RDS_POLY POLY + RDS_CONT CONTACT + RDS_ALU1 METAL1 + RDS_TALU1 ? + RDS_VIA1 VIA1 + RDS_ALU2 METAL2 + RDS_TALU2 ? + RDS_ACTIV ACTIVE + RDS_NIMP NPLUS + RDS_PIMP PPLUS + RDS_CPAS PAD + RDS_ALU3 METAL3 + RDS_VIA2 VIA2 + RDS_VIA3 VIA3 + RDS_VIA4 VIA4 + RDS_VIA5 VIA5 + RDS_VIA6 VIA6 + RDS_VIA7 VIA7 + RDS_ALU4 METAL4 + RDS_ALU5 METAL5 + RDS_ALU6 METAL6 + RDS_ALU7 METAL7 + RDS_ALU8 METAL8 +END +TABLE GDS_LAYER + RDS_NWELL 1 + RDS_POLY 13 + RDS_CONT 19 + RDS_ALU1 23 + RDS_VIA1 25 + RDS_ALU2 27 + RDS_ACTIV 2 + RDS_NIMP 16 + RDS_PIMP 17 + RDS_CPAS 31 + RDS_ALU3 34 + RDS_VIA2 32 + RDS_VIA3 35 + RDS_VIA4 37 + RDS_VIA5 39 + RDS_VIA6 41 + RDS_VIA7 43 + RDS_ALU4 36 + RDS_ALU5 38 + RDS_ALU5 40 + RDS_ALU6 42 + RDS_ALU7 44 + RDS_ALU8 46 +END +TABLE S2R_OVERSIZE_DENOTCH + RDS_NWELL 0.700 + RDS_PWELL 0.000 + RDS_POLY 0.250 + RDS_ALU1 -0.025 + RDS_ALU2 -0.025 + RDS_ACTIV 0.325 + RDS_NIMP 0.250 + RDS_PIMP 0.250 + RDS_ALU3 -0.025 + RDS_ALU4 -0.025 + RDS_ALU5 -0.025 + RDS_ALU6 -0.025 + RDS_ALU7 -0.025 + RDS_ALU8 -0.025 +END +TABLE S2R_BLOC_RING_WIDTH + RDS_NWELL 1.400 + RDS_PWELL 0.000 + RDS_POLY 0.550 + RDS_ALU1 0.000 + RDS_ALU2 0.000 + RDS_ACTIV 0.700 + RDS_NIMP 0.500 + RDS_PIMP 0.500 + RDS_ALU3 0.000 + RDS_ALU4 0.000 + RDS_ALU5 0.000 + RDS_ALU6 0.000 + RDS_ALU7 0.000 + RDS_ALU8 0.000 +END +TABLE S2R_MINIMUM_LAYER_WIDTH + RDS_NWELL 1.700 + RDS_PWELL 1.700 + RDS_POLY 0.350 + RDS_ALU1 0.600 + RDS_ALU2 0.700 + RDS_ACTIV 0.500 + RDS_NIMP 0.500 + RDS_PIMP 0.500 + RDS_ALU3 0.900 + RDS_ALU3 0.900 + RDS_ALU4 0.900 + RDS_ALU5 0.900 + RDS_ALU6 0.900 + RDS_ALU7 0.900 + RDS_ALU8 0.900 +END +TABLE S2R_POST_TREAT + RDS_NWELL TREAT NULL + RDS_PWELL TREAT NULL + RDS_POLY TREAT NULL + RDS_CONT NOTREAT NULL + RDS_ALU1 TREAT NULL + RDS_VIA1 NOTREAT NULL + RDS_ALU2 TREAT NULL + RDS_ACTIV TREAT NULL + RDS_NIMP TREAT RDS_PIMP + RDS_PIMP TREAT RDS_NIMP + RDS_ABOX NOTREAT NULL + RDS_VIA2 NOTREAT NULL + RDS_ALU3 TREAT NULL + RDS_VIA3 NOTREAT NULL + RDS_VIA4 NOTREAT NULL + RDS_VIA5 NOTREAT NULL + RDS_VIA6 NOTREAT NULL + RDS_VIA7 NOTREAT NULL + RDS_ALU4 TREAT NULL + RDS_ALU5 TREAT NULL + RDS_ALU6 TREAT NULL + RDS_ALU7 TREAT NULL + RDS_ALU8 TREAT NULL +END +TABLE LYNX_TRANSISTOR +NTRANS NTRANS C_X_N RDS_POLY RDS_NDIF RDS_ACTIV RDS_PWELL +PTRANS PTRANS C_X_P RDS_POLY RDS_PDIF RDS_ACTIV RDS_NWELL +END +TABLE LYNX_DIFFUSION + RDS_PDIF RDS_ACTIV 1 RDS_PIMP 1 RDS_NWELL 1 + RDS_PTIE RDS_ACTIV 1 RDS_PIMP 1 RDS_PWELL 1 + RDS_NDIF RDS_ACTIV 1 RDS_NIMP 1 RDS_PWELL 1 + RDS_NTIE RDS_ACTIV 1 RDS_NIMP 1 RDS_NWELL 1 +END +TABLE LYNX_RESISTOR + RDS_POLY 6 + RDS_ALU1 0.087 + RDS_ALU2 0.066 + RDS_ALU3 0.066 + RDS_ALU3 0.066 + RDS_ALU4 0.066 + RDS_ALU5 0.066 + RDS_ALU6 0.066 + RDS_ALU7 0.066 + RDS_ALU8 0.066 + RDS_CONT 12 + RDS_VIA1 4 + RDS_VIA2 4 + RDS_VIA3 4 + RDS_VIA4 4 + RDS_VIA5 4 + RDS_VIA6 4 + RDS_VIA7 4 +END +TABLE LYNX_GRAPH + +##--------------------------- +# +# Modifie par L.Jacomme (Pb Bulk/Alim avec Lynx) +# 23.11.99 +# +# RDS_NWELL RDS_NTIE RDS_NWELL +# RDS_PWELL RDS_PTIE RDS_PWELL +# RDS_NTIE RDS_CONT RDS_NTIE RDS_NWELL +# RDS_PTIE RDS_CONT RDS_PTIE RDS_PWELL +# RDS_NDIF RDS_CONT RDS_NDIF +# RDS_PDIF RDS_CONT RDS_PDIF + + RDS_NDIF RDS_CONT RDS_NDIF + RDS_PDIF RDS_CONT RDS_PDIF + RDS_NTIE RDS_CONT RDS_NTIE + RDS_PTIE RDS_CONT RDS_PTIE + + RDS_POLY RDS_CONT RDS_POLY + RDS_CONT RDS_PDIF RDS_NDIF RDS_POLY RDS_PTIE RDS_NTIE RDS_ALU1 RDS_CONT + RDS_ALU1 RDS_CONT RDS_VIA1 RDS_REF RDS_ALU1 + RDS_REF RDS_CONT RDS_VIA1 RDS_ALU1 RDS_REF + RDS_VIA1 RDS_ALU1 RDS_ALU2 RDS_VIA1 + RDS_ALU2 RDS_VIA1 RDS_VIA2 RDS_ALU2 + RDS_VIA2 RDS_ALU2 RDS_ALU3 RDS_VIA2 + RDS_ALU3 RDS_VIA2 RDS_VIA3 RDS_ALU3 + RDS_VIA3 RDS_ALU3 RDS_ALU4 RDS_VIA3 + RDS_ALU4 RDS_VIA3 RDS_VIA4 RDS_ALU4 + RDS_VIA4 RDS_ALU4 RDS_ALU5 RDS_VIA4 + RDS_ALU5 RDS_VIA4 RDS_VIA5 RDS_ALU5 + RDS_VIA5 RDS_ALU5 RDS_ALU6 RDS_VIA5 + RDS_ALU6 RDS_VIA5 RDS_VIA6 RDS_ALU6 + RDS_VIA6 RDS_ALU6 RDS_ALU7 RDS_VIA6 + RDS_ALU7 RDS_VIA6 RDS_VIA7 RDS_ALU7 + RDS_VIA7 RDS_ALU7 RDS_ALU8 RDS_VIA7 + RDS_ALU8 RDS_VIA7 RDS_ALU8 +END +TABLE LYNX_CAPA + RDS_POLY 0.000101 9.8e-05 + RDS_ALU1 2.65e-05 8.6e-05 + RDS_ALU2 1.3e-05 7.6e-05 + RDS_ALU3 8.4e-06 6.8e-05 + RDS_ALU4 6.2e-06 6.34e-05 + RDS_ALU5 6.2e-06 6.34e-05 + RDS_ALU6 6.2e-06 6.34e-05 + RDS_ALU7 6.2e-06 6.34e-05 + RDS_ALU8 6.2e-06 6.34e-05 +END +##------------------------------------------------------------------- +# TABLE LYNX_BULK_IMPLICIT : +# +# RDS layer Bulk type +# name EXPLICIT/IMPLICIT +##------------------------------------------------------------------- + +TABLE LYNX_BULK_IMPLICIT + +##--------------------------- +# +# Modifie par L.Jacomme (Pb Bulk/Alim avec Lynx) +# 23.11.99 +# +# NWELL EXPLICIT +# PWELL IMPLICIT + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_BIGVIA_HOLE : +# +# MBK via RDS Hole +# name name side step mode +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_BIGVIA_HOLE + +CONT_VIA RDS_VIA1 .4 1.1 ALL +CONT_VIA2 RDS_VIA2 .4 1.1 ALL + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_BIGVIA_METAL : +# +# MBK via RDS layer 1 ... +# name name delta-width overlap mode +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_BIGVIA_METAL + +CONT_VIA RDS_ALU1 .3 .0 ALL RDS_ALU2 .1 .0 ALL +CONT_VIA2 RDS_ALU2 .1 .0 ALL RDS_ALU3 .0 .0 ALL + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_TURNVIA : +# +# MBK via RDS layer 1 ... +# name name delta-width overlap mode +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_TURNVIA + +CONT_TURN1 RDS_ALU1 .3 ALL +CONT_TURN2 RDS_ALU2 .1 ALL +CONT_TURN3 RDS_ALU3 .0 ALL +CONT_TURN3 RDS_ALU4 .0 ALL +CONT_TURN3 RDS_ALU5 .0 ALL +CONT_TURN3 RDS_ALU6 .0 ALL +CONT_TURN3 RDS_ALU7 .0 ALL +CONT_TURN3 RDS_ALU8 .0 ALL + +END + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/local-cmos.graal b/alliance/src/documentation/alliance-examples/mipsR3000/sce/local-cmos.graal new file mode 100644 index 00000000..fb257c9c --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/local-cmos.graal @@ -0,0 +1,370 @@ +# /*------------------------------------------------------------\ +# | | +# | Title : Parameters File for Graal | +# | | +# | Technology : Cmos V7 | +# | | +# | Date : 27/06/95 | +# | | +# \------------------------------------------------------------*/ +# /*------------------------------------------------------------\ +# | | +# | Graal Peek Bound in lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_PEEK_BOUND 7 + +# /*------------------------------------------------------------\ +# | | +# | Lower Grid Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_GRID_STEP 10 + +# /*------------------------------------------------------------\ +# | | +# | Lower Figure Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_FIGURE_STEP 1 + +# /*------------------------------------------------------------\ +# | | +# | Lower Instance Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_INSTANCE_STEP 1 + +# /*------------------------------------------------------------\ +# | | +# | Lower Connector Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_CONNECTOR_STEP 5 + +# /*------------------------------------------------------------\ +# | | +# | Lower Segment Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_SEGMENT_STEP 7 + +# /*------------------------------------------------------------\ +# | | +# | Lower Reference Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_REFERENCE_STEP 10 + +# /*------------------------------------------------------------\ +# | | +# | Graal Cursor Color Name | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_CURSOR_COLOR_NAME Gray + +# /*------------------------------------------------------------\ +# | | +# | Graal Cursor Size in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_CURSOR_SIZE 10 + +# /*------------------------------------------------------------\ +# | | +# | Segment Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_SEGMENT_NAME + + NWELL Nwell tan Black + PWELL Pwell light_yellow Black + NDIF Ndif lawn_green Black + PDIF Pdif yellow Black + NTIE Ntie spring_green Black + PTIE Ptie light_goldenrod Black + POLY Poly red Black + POLY2 Poly2 orange Black + ALU1 Alu1 royal_blue Black + ALU2 Alu2 Cyan Black + ALU3 Alu3 light_pink Black + ALU4 Alu4 green Black + ALU5 Alu5 yellow Black + ALU6 Alu6 violet Black + ALU7 Alu7 red Black + ALU8 Alu7 blue Black + TPOLY Tpoly hot_pink Black + TALU1 Talu1 royal_blue Black + TALU2 Talu2 turquoise Black + TALU3 Talu3 light_pink Black + TALU4 Talu4 green Black + TALU5 Talu5 yellow Black + TALU6 Talu6 violet Black + TALU7 Talu7 red Black + TALU8 Talu7 blue Black + CALU1 CAlu1 royal_blue Black + CALU2 CAlu2 Cyan Black + CALU3 CAlu3 light_pink Black + CALU4 CAlu4 green Black + CALU5 CAlu5 yellow Black + CALU6 CAlu6 violet Black + CALU7 CAlu7 red Black + CALU8 CAlu8 blue Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Transistor Panel Button Label, Foreground, Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_TRANSISTOR_NAME + + NTRANS Ntrans lawn_green Black + PTRANS Ptrans yellow Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Connector Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_CONNECTOR_NAME + + POLY Poly red Black + POLY2 Poly2 orange Black + ALU1 Alu1 royal_blue Black + ALU2 Alu2 Cyan Black + ALU3 Alu3 light_pink Black + ALU4 Alu4 green Black + ALU5 Alu5 yellow Black + ALU6 Alu6 violet Black + ALU7 Alu7 red Black + ALU8 Alu8 blue Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Minimun Length and Width for a symbolic Segment | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_SEGMENT_VALUE + + NWELL 4 4 + PWELL 4 4 + NDIF 2 2 + PDIF 2 2 + NTIE 2 2 + PTIE 2 2 + NTRANS 1 4 + PTRANS 1 4 + POLY 1 1 + POLY2 1 1 + ALU1 1 1 + ALU2 2 1 + ALU3 2 1 + ALU4 2 1 + ALU5 2 1 + ALU6 2 1 + ALU7 2 1 + ALU8 2 1 + TPOLY 1 1 + TALU1 1 1 + TALU2 2 2 + TALU3 2 2 + TALU4 2 2 + TALU5 2 2 + TALU6 2 2 + TALU7 2 2 + TALU8 2 2 + CALU1 2 0 + CALU2 2 0 + CALU3 2 0 + CALU4 2 0 + CALU5 2 0 + CALU6 2 0 + CALU7 2 0 + CALU8 2 0 + +END + +# /*------------------------------------------------------------\ +# | | +# | Reference Panel Button Label, Foreground, Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_REFERENCE_NAME + + REF_REF Ref_Ref red Black + REF_CON Ref_Con Cyan Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Via Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_VIA_NAME + + CONT_DIF_N Cont_NDif lawn_green Black + CONT_DIF_P Cont_PDif yellow Black + CONT_BODY_N Cont_NTie spring_green Black + CONT_BODY_P Cont_PTie light_goldenrod Black + CONT_POLY Cont_Poly red Black + CONT_POLY2 Cont_Poly2 orange Black + CONT_VIA Via_1-2 cyan Black + CONT_VIA2 Via_2-3 light_pink Black + CONT_VIA3 Via_3-4 green Black + CONT_VIA4 Via_4-5 yellow Black + CONT_VIA5 Via_5-6 violet Black + CONT_VIA6 Via_6-7 red Black + CONT_VIA7 Via_7-8 blue Black + C_X_N Cont_CxN orange Black + C_X_P Cont_CxP orange Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Big Via Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_BIGVIA_NAME + + CONT_VIA Big_Via_1-2 cyan Black + CONT_VIA2 Big_Via_2-3 light_pink Black + CONT_VIA3 Big_Via_3-4 green Black + + CONT_TURN1 Turn_Via_1 royal_blue Black + CONT_TURN2 Turn_Via_2 Cyan Black + CONT_TURN3 Turn_Via_3 light_pink Black + CONT_TURN4 Turn_Via_4 green Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Minimun Size for a symbolic Big Via | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_BIGVIA_VALUE + + CONT_VIA 2 + CONT_VIA2 2 + CONT_VIA3 2 + + CONT_TURN1 2 + CONT_TURN2 2 + CONT_TURN3 2 + CONT_TURN4 2 + +END + +# /*------------------------------------------------------------\ +# | | +# | Orient Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_ORIENT_NAME + + NORTH North lawn_green Black + SOUTH South yellow Black + EAST East tan Black + WEST West red Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Symmetry Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_SYMMETRY_NAME + + NOSYM No_Sym LightBlue Black + SYM_X Sym_X turquoise Black + SYM_Y Sym_Y cyan Black + SYMXY Sym_XY LightCyan Black + ROT_P Rot_P MediumAquamarine Black + ROT_M Rot_M aquamarine Black + SY_RP Sym_RP green Black + SY_RM Sym_RM MediumSpringGreen Black + +END + +# /*------------------------------------------------------------\ +# | | +# | View Layer Panel Button Label, Foreground, Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_RDS_LAYER_NAME + + RDS_NWELL Nwell tan Black + RDS_PWELL Pwell light_yellow Black + RDS_NIMP Nimp forest_green Black + RDS_PIMP Pimp goldenrod Black + RDS_ACTIV Activ brown Black + RDS_NDIF Ndif lawn_green Black + RDS_PDIF Pdif yellow Black + RDS_NTIE Ntie spring_green Black + RDS_PTIE Ptie light_goldenrod Black + RDS_POLY Poly red Black + RDS_POLY2 Poly2 orange Black + RDS_VPOLY VPoly coral Black + RDS_GATE Gate orange Black + RDS_TPOLY Tpoly hot_pink Black + RDS_CONT Cont dark_violet Black + RDS_TCONT TCont orchid Black + RDS_ALU1 Alu1 royal_blue Black + RDS_VALU1 VAlu1 sky_blue Black + RDS_TALU1 Talu1 royal_blue Black + RDS_VIA1 Via1 deep_sky_blue Black + RDS_TVIA1 TVia1 dodger_blue Black + RDS_ALU2 Alu2 cyan Black + RDS_TALU2 Talu2 turquoise Black + RDS_VIA2 Via2 deep_pink Black + RDS_ALU3 Alu3 light_pink Black + RDS_TALU3 Talu3 light_pink Black + RDS_VIA3 Via3 sea_green Black + RDS_ALU4 Alu4 green Black + RDS_TALU4 Talu4 green Black + RDS_VIA4 Via4 gold Black + RDS_ALU5 Alu5 yellow Black + RDS_TALU5 Talu5 yellow Black + RDS_VIA5 Via5 violet_red Black + RDS_ALU6 Alu6 violet Black + RDS_TALU6 Talu6 violet Black + RDS_VIA6 Via6 red Black + RDS_ALU7 Alu7 red Black + RDS_TALU7 Talu7 red Black + RDS_VIA7 Via7 blue Black + RDS_ALU8 Alu8 blue Black + RDS_TALU8 Talu8 blue Black + RDS_CPAS Cpas gray Black + RDS_REF Ref coral Black + RDS_ABOX Abox pink Black + +END diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/local-cmos.rds b/alliance/src/documentation/alliance-examples/mipsR3000/sce/local-cmos.rds new file mode 100644 index 00000000..a66a712a --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/local-cmos.rds @@ -0,0 +1,990 @@ +# Modified version of the cmos.rds file +# usable for the mips tutorial +#===================================================================== +# +# ALLIANCE VLSI CAD +# (R)eal (D)ata (S)tructure parameter file +# (c) copyright 1992 Laboratory UPMC/MASI/CAO-VLSI +# all rights reserved +# e-mail : cao-vlsi@masi.ibp.fr +# +# file : cmos.rds +# version : 12 +# last modif : Apr 4, 2002 +# +##------------------------------------------------------------------- +# Symbolic to micron on a 'one lambda equals one micron' basis +##------------------------------------------------------------------- +# Refer to the documentation for more precise information. +#===================================================================== +# 01/11/09 ALU5/6 pitch 10 +# +# 99/11/3 ALU5/6 rules +# . theses rules are preliminary rules, we hope that they wil change +# in future. For now, ALU5/6 are dedicated to supplies an clock. +# +# 99/3/22 new symbolics rules +# . ALU1 width remains 1, ALU2/3/4 is 2 +# . ALU1/2/3/4 distance (edge to edge) is now 3 for all +# . GATE to GATE distance is 3 but POLY wire to POLY wire remains 2 +# . All via stacking are allowed +# +# 98/12/1 drc rules were updated +# distance VIA to POLY or gate is one rather 2 +# VIA2 and ALU3 appeared +# . ALU3 width is 3 +# . ALU2/VIA2/ALU3 is resp. 3/1/3 +# . ALU3 edge distance is 2 +# . stacked VIA/VIA2 is allowed +# . if they are not stacked they must distant of 2 +# . CONT/VIA2 is free +# note +# . stacked CONT/VIA is always not allowed +# NWELL is automatically drawn with the DIFN and NTIE layers +#===================================================================== + +##------------------------------------------------------------------- +# PHYSICAL_GRID : +##------------------------------------------------------------------- + +DEFINE PHYSICAL_GRID .5 + +##------------------------------------------------------------------- +# LAMBDA : +##------------------------------------------------------------------- + +DEFINE LAMBDA 1 + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_SEGMENT : +# +# MBK RDS layer 1 RDS layer 2 +# name name TRANS DLR DWR OFFSET name TRANS DLR DWR OFFSET ... +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_SEGMENT + + PWELL RDS_PWELL VW 0.0 0.0 0.0 EXT + NWELL RDS_NWELL VW 0.0 0.0 0.0 ALL + NDIF RDS_NDIF VW 0.5 0.0 0.0 ALL + PDIF RDS_PDIF VW 0.5 0.0 0.0 ALL \ + RDS_NWELL VW 1.0 1.0 0.0 ALL + NTIE RDS_NTIE VW 0.5 0.0 0.0 ALL \ + RDS_NWELL VW 1.0 1.0 0.0 ALL + PTIE RDS_PTIE VW 0.5 0.0 0.0 ALL + NTRANS RDS_POLY VW 0.0 0.0 0.0 ALL \ + RDS_NDIF LCW -1.5 2.0 0.0 EXT \ + RDS_NDIF RCW -1.5 2.0 0.0 EXT \ + RDS_NDIF VW -1.5 4.0 0.0 DRC \ + RDS_ACTIV VW -1.5 5.0 0.0 ALL \ + RDS_PWELL VW -1.5 0.0 0.0 EXT + PTRANS RDS_POLY VW 0.0 0.0 0.0 ALL \ + RDS_PDIF LCW -1.5 2.0 0.0 EXT \ + RDS_PDIF RCW -1.5 2.0 0.0 EXT \ + RDS_PDIF VW -1.5 4.0 0.0 DRC \ + RDS_ACTIV VW -1.5 5.0 0.0 ALL \ + RDS_NWELL VW -1.0 5.0 0.0 ALL + POLY RDS_POLY VW 0.5 0.0 0.0 ALL + POLY2 RDS_POLY2 VW 0.5 0.0 0.0 ALL + ALU1 RDS_ALU1 VW 0.5 0.0 0.0 ALL + ALU2 RDS_ALU2 VW 1.0 0.0 0.0 ALL + ALU3 RDS_ALU3 VW 1.0 0.0 0.0 ALL + ALU4 RDS_ALU4 VW 1.0 0.0 0.0 ALL + ALU5 RDS_ALU5 VW 1.0 0.0 0.0 ALL + ALU6 RDS_ALU6 VW 1.0 0.0 0.0 ALL + ALU7 RDS_ALU7 VW 1.0 0.0 0.0 ALL + ALU8 RDS_ALU8 VW 1.0 0.0 0.0 ALL + CALU1 RDS_ALU1 VW 1.0 0.0 0.0 ALL + CALU2 RDS_ALU2 VW 1.0 0.0 0.0 ALL + CALU3 RDS_ALU3 VW 1.0 0.0 0.0 ALL + CALU4 RDS_ALU4 VW 1.0 0.0 0.0 ALL + CALU5 RDS_ALU5 VW 1.0 0.0 0.0 ALL + CALU6 RDS_ALU6 VW 1.0 0.0 0.0 ALL + CALU7 RDS_ALU7 VW 1.0 0.0 0.0 ALL + CALU8 RDS_ALU8 VW 1.0 0.0 0.0 ALL + TPOLY RDS_TPOLY VW 0.5 0.0 0.0 ALL + TALU1 RDS_TALU1 VW 0.5 0.0 0.0 ALL + TALU2 RDS_TALU2 VW 1.0 0.0 0.0 ALL + TALU3 RDS_TALU3 VW 1.0 0.0 0.0 ALL + TALU4 RDS_TALU4 VW 1.0 0.0 0.0 ALL + TALU5 RDS_TALU5 VW 1.0 0.0 0.0 ALL + TALU6 RDS_TALU6 VW 1.0 0.0 0.0 ALL + TALU7 RDS_TALU7 VW 1.0 0.0 0.0 ALL + TALU8 RDS_TALU8 VW 1.0 0.0 0.0 ALL + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_CONNECTOR : +# +# MBK RDS layer +# name name DER DWR +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_CONNECTOR + + POLY RDS_POLY .5 0 + POLY2 RDS_POLY2 .5 0 + ALU1 RDS_ALU1 .5 0 + ALU2 RDS_ALU2 1.0 0 + ALU3 RDS_ALU3 1.0 0 + ALU4 RDS_ALU4 1.0 0 + ALU5 RDS_ALU5 1.0 0 + ALU6 RDS_ALU6 1.0 0 + ALU7 RDS_ALU7 1.0 0 + ALU8 RDS_ALU8 1.0 0 + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_REFERENCE : +# +# MBK ref RDS layer +# name name width +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_REFERENCE + + REF_REF RDS_REF 1 + REF_CON RDS_VALU1 2 RDS_TVIA1 1 RDS_TALU2 2 + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_VIA1 : +# +# MBK via RDS layer 1 RDS layer 2 RDS layer 3 RDS layer 4 +# name name width name width name width name width +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_VIA + + CONT_BODY_P RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_PTIE 3 ALL + CONT_BODY_N RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_NTIE 3 ALL RDS_NWELL 4 ALL + CONT_DIF_N RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_NDIF 3 ALL + CONT_DIF_P RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_PDIF 3 ALL RDS_NWELL 4 ALL + CONT_POLY RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_POLY 3 ALL + CONT_POLY2 RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_POLY2 3 ALL + CONT_VIA RDS_ALU1 2 ALL RDS_VIA1 1 ALL RDS_ALU2 2 ALL + CONT_VIA2 RDS_ALU2 2 ALL RDS_VIA2 1 ALL RDS_ALU3 2 ALL + CONT_VIA3 RDS_ALU3 2 ALL RDS_VIA3 1 ALL RDS_ALU4 2 ALL + CONT_VIA4 RDS_ALU4 2 ALL RDS_VIA4 1 ALL RDS_ALU5 2 ALL + CONT_VIA5 RDS_ALU5 2 ALL RDS_VIA5 1 ALL RDS_ALU6 2 ALL + CONT_VIA6 RDS_ALU6 2 ALL RDS_VIA6 1 ALL RDS_ALU7 2 ALL + CONT_VIA7 RDS_ALU7 2 ALL RDS_VIA7 1 ALL RDS_ALU8 2 ALL + C_X_N RDS_POLY 1 ALL RDS_NDIF 5 ALL RDS_ACTIV 6 ALL + C_X_P RDS_POLY 1 ALL RDS_PDIF 5 ALL RDS_NWELL 6 ALL RDS_ACTIV 6 ALL + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_BIGVIA_HOLE : +# +# MBK via RDS Hole +# name name side step mode +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_BIGVIA_HOLE + +CONT_VIA RDS_VIA1 1 4 ALL +CONT_VIA2 RDS_VIA2 1 4 ALL +CONT_VIA3 RDS_VIA3 1 4 ALL +CONT_VIA5 RDS_VIA3 1 9 ALL +CONT_VIA6 RDS_VIA3 1 9 ALL +CONT_VIA7 RDS_VIA3 1 9 ALL + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_BIGVIA_METAL : +# +# MBK via RDS layer 1 ... +# name name delta-width overlap mode +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_BIGVIA_METAL + +CONT_VIA RDS_ALU1 0.0 0.5 ALL RDS_ALU2 0.0 0.5 ALL +CONT_VIA2 RDS_ALU2 0.0 0.5 ALL RDS_ALU3 0.0 0.5 ALL +CONT_VIA3 RDS_ALU3 0.0 0.5 ALL RDS_ALU4 0.0 0.5 ALL +CONT_VIA4 RDS_ALU4 0.0 0.5 ALL RDS_ALU5 0.0 0.5 ALL +CONT_VIA5 RDS_ALU5 0.0 0.5 ALL RDS_ALU6 0.0 0.5 ALL + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_TURNVIA : +# +# MBK via RDS layer 1 ... +# name name DWR MODE +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_TURNVIA + +CONT_TURN1 RDS_ALU1 0 ALL +CONT_TURN2 RDS_ALU2 0 ALL +CONT_TURN3 RDS_ALU3 0 ALL +CONT_TURN4 RDS_ALU4 0 ALL +CONT_TURN5 RDS_ALU5 0 ALL +CONT_TURN6 RDS_ALU6 0 ALL + +END + + +##------------------------------------------------------------------- +# TABLE LYNX_GRAPH : +# +# RDS layer Rds layer 1 Rds layer 2 ... +# name name name ... +##------------------------------------------------------------------- + +TABLE LYNX_GRAPH + +##--------------------------- +# +# Modifie par L.Jacomme (Pb Bulk/Alim avec Lynx) +# 23.11.99 +# +# RDS_NWELL RDS_NTIE RDS_NWELL +# RDS_PWELL RDS_PTIE RDS_PWELL +# RDS_NDIF RDS_CONT RDS_NDIF +# RDS_PDIF RDS_CONT RDS_PDIF +# RDS_NTIE RDS_CONT RDS_NTIE RDS_NWELL +# RDS_PTIE RDS_CONT RDS_PTIE RDS_PWELL + + RDS_NDIF RDS_CONT RDS_NDIF + RDS_PDIF RDS_CONT RDS_PDIF + RDS_NTIE RDS_CONT RDS_NTIE + RDS_PTIE RDS_CONT RDS_PTIE + + RDS_POLY RDS_CONT RDS_POLY + RDS_POLY2 RDS_CONT RDS_POLY2 + RDS_CONT RDS_PDIF RDS_NDIF RDS_POLY RDS_PTIE RDS_NTIE RDS_ALU1 RDS_CONT + RDS_ALU1 RDS_CONT RDS_VIA1 RDS_ALU1 RDS_VALU1 RDS_ALU1 + RDS_VALU1 RDS_CONT RDS_VIA1 RDS_ALU1 RDS_VALU1 + RDS_VIA1 RDS_ALU1 RDS_ALU2 RDS_VIA1 + RDS_VIA2 RDS_ALU2 RDS_ALU3 RDS_VIA2 + RDS_VIA3 RDS_ALU3 RDS_ALU4 RDS_VIA3 + RDS_VIA4 RDS_ALU4 RDS_ALU5 RDS_VIA4 + RDS_VIA5 RDS_ALU5 RDS_ALU6 RDS_VIA5 + RDS_VIA6 RDS_ALU6 RDS_ALU7 RDS_VIA6 + RDS_VIA7 RDS_ALU7 RDS_ALU8 RDS_VIA7 + RDS_ALU2 RDS_VIA1 RDS_VIA2 RDS_ALU2 + RDS_ALU3 RDS_VIA2 RDS_VIA3 RDS_ALU3 + RDS_ALU4 RDS_VIA3 RDS_VIA4 RDS_ALU4 + RDS_ALU5 RDS_VIA4 RDS_VIA5 RDS_ALU5 + RDS_ALU6 RDS_VIA5 RDS_VIA6 RDS_ALU6 + RDS_ALU7 RDS_VIA6 RDS_VIA7 RDS_ALU7 + RDS_ALU8 RDS_VIA7 RDS_ALU8 + +END + +##------------------------------------------------------------------- +# TABLE LYNX_CAPA : +# +# RDS layer Surface capacitance Perimetric capacitance +# name piF / Micron^2 piF / Micron +##------------------------------------------------------------------- + +TABLE LYNX_CAPA + + RDS_POLY 1.00e-04 1.00e-04 + RDS_POLY2 1.00e-04 1.00e-04 + RDS_ALU1 0.50e-04 0.90e-04 + RDS_ALU2 0.25e-04 0.95e-04 + RDS_ALU3 0.25e-04 0.95e-04 + RDS_ALU4 0.25e-04 0.95e-04 + RDS_ALU5 0.25e-04 0.95e-04 + RDS_ALU6 0.25e-04 0.95e-04 + RDS_ALU7 0.25e-04 0.95e-04 + RDS_ALU8 0.25e-04 0.95e-04 + +END + +##------------------------------------------------------------------- +# TABLE LYNX_RESISTOR : +# +# RDS layer Surface resistor +# name Ohm / Micron^2 +##------------------------------------------------------------------- + +TABLE LYNX_RESISTOR + + RDS_POLY 50.0 + RDS_POLY2 50.0 + RDS_ALU1 0.1 + RDS_ALU2 0.05 + RDS_ALU3 0.05 + RDS_ALU4 0.05 + RDS_ALU5 0.05 + RDS_ALU6 0.05 + RDS_ALU7 0.05 + RDS_ALU8 0.05 + +END + +##------------------------------------------------------------------- +# TABLE LYNX_TRANSISTOR : +# +# MBK layer Transistor Type MBK via +# name name name +##------------------------------------------------------------------- + +TABLE LYNX_TRANSISTOR + + NTRANS NTRANS C_X_N RDS_POLY RDS_NDIF RDS_NDIF RDS_PWELL + PTRANS PTRANS C_X_P RDS_POLY RDS_PDIF RDS_PDIF RDS_NWELL + +END + +##------------------------------------------------------------------- +# TABLE LYNX_DIFFUSION : +# +# RDS layer RDS layer +# name name +##------------------------------------------------------------------- + +TABLE LYNX_DIFFUSION +END + +##------------------------------------------------------------------- +# TABLE LYNX_BULK_IMPLICIT : +# +# RDS layer Bulk type +# name EXPLICIT/IMPLICIT +##------------------------------------------------------------------- + +TABLE LYNX_BULK_IMPLICIT + +##--------------------------- +# +# Modifie par L.Jacomme (Pb Bulk/Alim avec Lynx) +# 23.11.99 +# +# NWELL EXPLICIT +# PWELL IMPLICIT + +END + + + +##------------------------------------------------------------------- +# TABLE S2R_OVERSIZE_DENOTCH : +##------------------------------------------------------------------- + +TABLE S2R_OVERSIZE_DENOTCH +END + +##------------------------------------------------------------------- +# TABLE S2R_BLOC_RING_WIDTH : +##------------------------------------------------------------------- + +TABLE S2R_BLOC_RING_WIDTH +END + +##------------------------------------------------------------------- +# TABLE S2R_MINIMUM_LAYER_WIDTH : +##------------------------------------------------------------------- + +TABLE S2R_MINIMUM_LAYER_WIDTH + + RDS_NWELL 4 + RDS_PDIF 2 + RDS_NTIE 2 + RDS_PTIE 2 + RDS_POLY 1 + RDS_POLY2 1 + RDS_TPOLY 1 + RDS_CONT 1 + RDS_ALU1 1 + RDS_TALU1 1 + RDS_VIA1 1 + RDS_ALU2 2 + RDS_TALU2 2 + RDS_VIA2 1 + RDS_ALU3 2 + RDS_TALU3 2 + RDS_VIA3 1 + RDS_ALU4 2 + RDS_TALU4 2 + RDS_VIA4 1 + RDS_ALU5 2 + RDS_TALU5 2 + RDS_VIA5 1 + RDS_ALU6 2 + RDS_TALU6 2 + RDS_VIA6 1 + RDS_ALU7 2 + RDS_TALU7 2 + RDS_VIA7 1 + RDS_ALU8 2 + RDS_TALU8 2 + +END + +##------------------------------------------------------------------- +# TABLE CIF_LAYER : +##------------------------------------------------------------------- + +TABLE CIF_LAYER + + RDS_NWELL LNWELL + RDS_NDIF LNDIF + RDS_PDIF LPDIF + RDS_NTIE LNTIE + RDS_PTIE LPTIE + RDS_POLY LPOLY + RDS_POLY2 LPOLY2 + RDS_TPOLY LTPOLY + RDS_CONT LCONT + RDS_ALU1 LALU1 + RDS_VALU1 LVALU1 + RDS_TALU1 LTALU1 + RDS_VIA1 LVIA + RDS_TVIA1 LTVIA1 + RDS_ALU2 LALU2 + RDS_TALU2 LTALU2 + RDS_VIA2 LVIA2 + RDS_ALU3 LALU3 + RDS_TALU3 LTALU3 + RDS_VIA3 LVIA3 + RDS_ALU4 LALU4 + RDS_TALU4 LTALU4 + RDS_VIA4 LVIA4 + RDS_ALU5 LALU5 + RDS_TALU5 LTALU5 + RDS_VIA5 LVIA5 + RDS_ALU6 LALU6 + RDS_TALU6 LTALU6 + RDS_VIA6 LVIA6 + RDS_ALU7 LALU7 + RDS_TALU7 LTALU7 + RDS_VIA7 LVIA7 + RDS_ALU8 LALU8 + RDS_TALU8 LTALU8 + RDS_REF LREF + +END + +##------------------------------------------------------------------- +# TABLE GDS_LAYER : +##------------------------------------------------------------------- + +TABLE GDS_LAYER + + RDS_NWELL 1 + RDS_NDIF 3 + RDS_PDIF 4 + RDS_NTIE 5 + RDS_PTIE 6 + RDS_POLY 7 + RDS_POLY2 8 + RDS_TPOLY 9 + RDS_CONT 10 + RDS_ALU1 11 + RDS_VALU1 12 + RDS_TALU1 13 + RDS_VIA1 14 + RDS_TVIA1 15 + RDS_ALU2 16 + RDS_TALU2 17 + RDS_VIA2 18 + RDS_ALU3 19 + RDS_TALU3 20 + RDS_VIA3 21 + RDS_ALU4 22 + RDS_TALU4 23 + RDS_VIA4 25 + RDS_ALU5 26 + RDS_TALU5 27 + RDS_VIA5 28 + RDS_ALU6 29 + RDS_TALU6 30 + RDS_VIA6 31 + RDS_ALU7 32 + RDS_TALU7 33 + RDS_VIA7 34 + RDS_ALU8 35 + RDS_TALU8 36 + RDS_REF 37 + +END + +##------------------------------------------------------------------- +# TABLE S2R_POST_TREAT : +##------------------------------------------------------------------- + +TABLE S2R_POST_TREAT + +END +DRC_RULES + +layer RDS_NWELL 4.; +layer RDS_NTIE 2.; +layer RDS_PTIE 2.; +layer RDS_NDIF 2.; +layer RDS_PDIF 2.; +layer RDS_ACTIV 2.; +layer RDS_CONT 1.; +layer RDS_VIA1 1.; +layer RDS_VIA2 1.; +layer RDS_VIA3 1.; +layer RDS_VIA4 1.; +layer RDS_VIA5 1.; +layer RDS_VIA6 1.; +layer RDS_VIA7 1.; +layer RDS_POLY 1.; +layer RDS_POLY2 1.; +layer RDS_ALU1 1.; +layer RDS_ALU2 2.; +layer RDS_ALU3 2.; +layer RDS_ALU4 2.; +layer RDS_ALU5 2.; +layer RDS_ALU6 2.; +layer RDS_ALU7 2.; +layer RDS_ALU8 2.; +layer RDS_USER0 1.; +layer RDS_USER1 1.; +layer RDS_USER2 1.; + +regles + +# Note : ``min'' is different from ``>=''. +# min is applied on polygons and >= is applied on rectangles. +# There is the same difference between max and <=. +# >= is faster than min, but min must be used where it is +# required to consider polygons, for example distance of +# two objects in the same layer +# +# There is no rule to check NTIE and PDIF are included in NWELL +# since this is necessarily true +#----------------------------------------------------------- + +# Check the NWELL shapes +#----------------------- +caracterise RDS_NWELL ( + regle 1 : largeur >= 4. ; + regle 2 : longueur_inter min 4. ; + regle 3 : notch >= 12. ; +); +relation RDS_NWELL , RDS_NWELL ( + regle 4 : distance axiale min 12. ; +); + +# Check RDS_PTIE is really excluded outside NWELL +#------------------------------------------------ +relation RDS_PTIE , RDS_NWELL ( + regle 5 : distance axiale >= 7.5; + regle 6 : enveloppe longueur_inter < 0. ; + regle 7 : marge longueur_inter < 0. ; + regle 8 : croix longueur_inter < 0. ; + regle 9 : intersection longueur_inter < 0. ; + regle 10 : extension longueur_inter < 0. ; + regle 11 : inclusion longueur_inter < 0. ; +); + +# Check RDS_NDIF is really excluded outside NWELL +#------------------------------------------------ +relation RDS_NDIF , RDS_NWELL ( + regle 12 : distance axiale >= 7.5; + regle 13 : enveloppe longueur_inter < 0. ; + regle 14 : marge longueur_inter < 0. ; + regle 15 : croix longueur_inter < 0. ; + regle 16 : intersection longueur_inter < 0. ; + regle 17 : extension longueur_inter < 0. ; + regle 18 : inclusion longueur_inter < 0. ; +); + +# Check the RDS_PDIF shapes +#-------------------------- +caracterise RDS_PDIF ( + regle 19 : largeur >= 2. ; + regle 20 : longueur_inter min 2. ; + regle 21 : notch >= 3. ; +); +relation RDS_PDIF , RDS_PDIF ( + regle 22 : distance axiale min 3. ; +); + +# Check the RDS_NDIF shapes +#-------------------------- +caracterise RDS_NDIF ( + regle 23 : largeur >= 2. ; + regle 24 : longueur_inter min 2. ; + regle 25 : notch >= 3. ; +); +relation RDS_NDIF , RDS_NDIF ( + regle 26 : distance axiale min 3. ; +); + +# Check the RDS_PTIE shapes +#-------------------------- +caracterise RDS_PTIE ( + regle 27 : largeur >= 2. ; + regle 28 : longueur_inter min 2. ; + regle 29 : notch >= 3. ; +); +relation RDS_PTIE , RDS_PTIE ( + regle 30 : distance axiale min 3. ; +); + +# Check the RDS_NTIE shapes +#-------------------------- +caracterise RDS_NTIE ( + regle 31 : largeur >= 2. ; + regle 32 : longueur_inter min 2. ; + regle 33 : notch >= 3. ; +); +relation RDS_NTIE , RDS_NTIE ( + regle 34 : distance axiale min 3. ; +); + +define RDS_PDIF , RDS_PTIE union -> ANY_P_DIF; +define RDS_NDIF , RDS_NTIE union -> ANY_N_DIF; + +# Check the ANY_N_DIF ANY_P_DIFF exclusion +#-------------------------------------- +relation ANY_N_DIF , ANY_P_DIF ( + regle 35 : distance axiale >= 3. ; + regle 36 : enveloppe longueur_inter < 0. ; + regle 37 : marge longueur_inter < 0. ; + regle 38 : croix longueur_inter < 0. ; + regle 39 : intersection longueur_inter < 0. ; + regle 40 : extension longueur_inter < 0. ; + regle 41 : inclusion longueur_inter < 0. ; +); + +undefine ANY_P_DIF; +undefine ANY_N_DIF; + +define RDS_NDIF , RDS_PDIF union -> NP_DIF; + +# Check RDS_POLY related to NP_DIF +#--------------------------------- +relation RDS_POLY , NP_DIF ( + regle 42 : distance axiale >= 1. ; + regle 43 : intersection longueur_inter < 0. ; +); + +define NP_DIF , RDS_POLY intersection -> CHANNEL; + +# Check the RDS_POLY shapes +#-------------------------- +caracterise RDS_POLY ( + regle 44 : largeur >= 1. ; + regle 45 : longueur_inter min 1. ; + regle 46 : notch >= 2. ; +); +relation RDS_POLY , RDS_POLY ( + regle 47 : distance axiale min 2.; +); + +define NP_DIF , RDS_CONT intersection -> CONT_DIFF; +# Check the CHANNEL shapes +#-------------------------- +caracterise CHANNEL ( + regle 48 : notch >= 3. ; +); +relation CHANNEL , CHANNEL ( + regle 49 : distance axiale min 3.; +); + +undefine CHANNEL; + +# Check RDS_POLY is distant from ACTIV ZONE of TRANSISTOR +#-------------------------------------------------------- +relation RDS_POLY , RDS_ACTIV ( + regle 79 : distance axiale >= 1. ; +); + +relation RDS_POLY , CONT_DIFF ( + regle 50 : distance axiale >= 2. ; +); + +undefine CONT_DIFF; +undefine NP_DIF; + + +# Check RDS_ALU1 shapes +#---------------------- +caracterise RDS_ALU1 ( + regle 51 : largeur >= 1. ; + regle 52 : longueur_inter min 1. ; + regle 53 : notch >= 3. ; +); +relation RDS_ALU1 , RDS_ALU1 ( + regle 54 : distance axiale min 3. ; +); + +# Check RDS_ALU2 shapes +#---------------------- +caracterise RDS_ALU2 ( + regle 55 : largeur >= 2. ; + regle 56 : longueur_inter min 2. ; + regle 57 : notch >= 3. ; +); +relation RDS_ALU2 , RDS_ALU2 ( + regle 58 : distance axiale min 3. ; +); + +# Check RDS_ALU3 shapes +#---------------------- +caracterise RDS_ALU3 ( + regle 59 : largeur >= 2. ; + regle 60 : longueur_inter min 2. ; + regle 61 : notch >= 3. ; +); +relation RDS_ALU3 , RDS_ALU3 ( + regle 62 : distance axiale min 3. ; +); + +# Check RDS_ALU4 shapes +#---------------------- +caracterise RDS_ALU4 ( + regle 63 : largeur >= 2. ; + regle 64 : longueur_inter min 2. ; + regle 65 : notch >= 3. ; +); +relation RDS_ALU4 , RDS_ALU4 ( + regle 66 : distance axiale min 3. ; +); + +# Check RDS_ALU5 shapes +#---------------------- +# caracterise RDS_ALU5 ( +# regle 80 : largeur >= 2. ; +# regle 81 : longueur_inter min 2. ; +# regle 82 : notch >= 8. ; +#); +#relation RDS_ALU5 , RDS_ALU5 ( +# regle 83 : distance axiale min 8. ; +#); + +# Check RDS_ALU5 shapes +# it is not true !! LUDO +# Only to work with OCR +#---------------------- +caracterise RDS_ALU5 ( + regle 80 : largeur >= 2. ; + regle 81 : longueur_inter min 2. ; + regle 82 : notch >= 3. ; +); +relation RDS_ALU5 , RDS_ALU5 ( + regle 83 : distance axiale min 3. ; +); + +# Check RDS_ALU6 shapes +#---------------------- +#caracterise RDS_ALU6 ( +# regle 84 : largeur >= 2. ; +# regle 85 : longueur_inter min 2. ; +# regle 86 : notch >= 8. ; +#); +#relation RDS_ALU6 , RDS_ALU6 ( +# regle 87 : distance axiale min 8. ; +#); + +# Check RDS_ALU6 shapes +# it is not true !! LUDO +# Only to work with OCR +#---------------------- +caracterise RDS_ALU6 ( + regle 84 : largeur >= 2. ; + regle 85 : longueur_inter min 2. ; + regle 86 : notch >= 3. ; +); +relation RDS_ALU6 , RDS_ALU6 ( + regle 87 : distance axiale min 3. ; +); + +# Check ANY_VIA layers, stacking are free +#---------------------------------------- +relation RDS_CONT , RDS_CONT ( + regle 67 : distance axiale >= 3. ; +); +relation RDS_VIA , RDS_VIA ( + regle 68 : distance axiale >= 4. ; +); +relation RDS_VIA2 , RDS_VIA2 ( + regle 69 : distance axiale >= 4. ; +); +relation RDS_VIA3 , RDS_VIA3 ( + regle 70 : distance axiale >= 4. ; +); + +# It's not true !! LUDO +# only to work with OCR +relation RDS_VIA4 , RDS_VIA4 ( + regle 88 : distance axiale >= 4. ; +); + +# relation RDS_VIA4 , RDS_VIA4 ( +# regle 88 : distance axiale >= 9. ; +#); + +# It's not true !! LUDO +# only to work with OCR +relation RDS_VIA5 , RDS_VIA5 ( + regle 89 : distance axiale >= 4. ; +); + +# relation RDS_VIA5 , RDS_VIA5 ( +# regle 89 : distance axiale >= 9. ; +# ); +caracterise RDS_CONT ( + regle 71 : largeur >= 1. ; + regle 72 : longueur <= 1. ; +); +caracterise RDS_VIA ( + regle 73 : largeur >= 1. ; + regle 74 : longueur <= 1. ; +); +caracterise RDS_VIA2 ( + regle 75 : largeur >= 1. ; + regle 76 : longueur <= 1. ; +); +caracterise RDS_VIA3 ( + regle 77 : largeur >= 1. ; + regle 78 : longueur <= 1. ; +); +caracterise RDS_VIA4 ( + regle 90 : largeur >= 1. ; + regle 91 : longueur <= 1. ; +); +caracterise RDS_VIA5 ( + regle 92 : largeur >= 1. ; + regle 93 : longueur <= 1. ; +); + +# Check the POLY2 shapes +#----------------------- +caracterise RDS_POLY2 ( + regle 94 : largeur >= 1. ; + regle 95 : longueur_inter min 1. ; + regle 96 : notch >= 5. ; +); +relation RDS_POLY2 , RDS_POLY2 ( + regle 97 : distance axiale min 5. ; +); + +# Check RDS_POLY2 is really included inside RDS_POLY1 +#---------------------------------------------------- +relation RDS_POLY , RDS_POLY2 ( + regle 98 : distance axiale < 0.; + regle 99 : enveloppe inferieure min 5. ; + regle 100 : marge longueur_inter < 0. ; + regle 101 : croix longueur_inter < 0. ; + regle 102 : intersection longueur_inter < 0. ; + regle 103 : extension longueur_inter < 0. ; + regle 104 : inclusion longueur_inter < 0. ; +); + + +fin regles +DRC_COMMENT +1 (RDS_NWELL) minimum width 4. +2 (RDS_NWELL) minimum width 4. +3 (RDS_NWELL) Manhatan distance min 12. +4 (RDS_NWELL,RDS_NWELL) Manhatan distance min 12. +5 (RDS_PTIE,RDS_NWELL) Manhatan distance min 7.5 +6 (RDS_PTIE,RDS_NWELL) must never been in contact +7 (RDS_PTIE,RDS_NWELL) must never been in contact +8 (RDS_PTIE,RDS_NWELL) must never been in contact +9 (RDS_PTIE,RDS_NWELL) must never been in contact +10 (RDS_PTIE,RDS_NWELL) must never been in contact +11 (RDS_PTIE,RDS_NWELL) must never been in contact +12 (RDS_NDIF,RDS_NWELL) Manhatan distance min 7.5 +13 (RDS_NDIF,RDS_NWELL) must never been in contact +14 (RDS_NDIF,RDS_NWELL) must never been in contact +15 (RDS_NDIF,RDS_NWELL) must never been in contact +16 (RDS_NDIF,RDS_NWELL) must never been in contact +17 (RDS_NDIF,RDS_NWELL) must never been in contact +18 (RDS_NDIF,RDS_NWELL) must never been in contact +19 (RDS_PDIF) minimum width 2. +20 (RDS_PDIF) minimum width 2. +21 (RDS_PDIF) Manhatan distance min 3. +22 (RDS_PDIF,RDS_PDIF) Manhatan distance min 3. +23 (RDS_NDIF) minimum width 2. +24 (RDS_NDIF) minimum width 2. +25 (RDS_NDIF) Manhatan distance min 3. +26 (RDS_NDIF,RDS_NDIF) Manhatan distance min 3. +27 (RDS_PTIE) minimum width 2. +28 (RDS_PTIE) minimum width 2. +29 (RDS_PTIE) Manhatan distance min 3. +30 (RDS_PTIE,RDS_PTIE) Manhatan distance min 3. +31 (RDS_NTIE) minimum width 2. +32 (RDS_NTIE) minimum width 2. +33 (RDS_NTIE) Manhatan distance min 3. +34 (RDS_NTIE,RDS_NTIE) Manhatan distance min 3. +35 (ANY_N_DIF,ANY_P_DIF) Manhatan distance min 3. +36 (ANY_N_DIF,ANY_P_DIF) must never been in contact +37 (ANY_N_DIF,ANY_P_DIF) must never been in contact +38 (ANY_N_DIF,ANY_P_DIF) must never been in contact +39 (ANY_N_DIF,ANY_P_DIF) must never been in contact +40 (ANY_N_DIF,ANY_P_DIF) must never been in contact +41 (ANY_N_DIF,ANY_P_DIF) must never been in contact +42 (RDS_POLY,ANY_N_DIF) Manhatan distance min 1. +43 (RDS_POLY,NP_DIF) bad intersection +44 (RDS_POLY) minimum width 1. +45 (RDS_POLY) minimum width 1. +46 (RDS_POLY) Manhatan distance min 2. +47 (RDS_POLY,RDS_POLY) Manhatan distance min 2. +48 (CHANNEL) Manhatan distance min 3. +49 (CHANNEL,CHANNEL) Manhatan distance min 3. +50 (RDS_POLY,CONT_DIFF) Manhatan distance min 2. +51 (RDS_ALU1) minimum width 1. +52 (RDS_ALU1) minimum width 1. +53 (RDS_ALU1) Manhatan distance min 3. +54 (RDS_ALU1,RDS_ALU1) Manhatan distance min 3. +55 (RDS_ALU2) minimum width 2. +56 (RDS_ALU2) minimum width 2. +57 (RDS_ALU2) Manhatan distance min 3. +58 (RDS_ALU2,RDS_ALU2) Manhatan distance min 3. +59 (RDS_ALU3) minimum width 2. +60 (RDS_ALU3) minimum width 2. +61 (RDS_ALU3) Manhatan distance min 3. +62 (RDS_ALU3,RDS_ALU3) Manhatan distance min 3. +63 (RDS_ALU4) minimum width 2. +64 (RDS_ALU4) minimum width 2. +65 (RDS_ALU4) Manhatan distance min 3. +66 (RDS_ALU4,RDS_ALU4) Manhatan distance min 3. +67 (RDS_CONT,RDS_CONT) Manhatan distance min 3. +68 (RDS_VIA,RDS_VIA) Manhatan distance min 4. +69 (RDS_VIA2,RDS_VIA2) Manhatan distance min 4. +70 (RDS_VIA3,RDS_VIA3) Manhatan distance min 4. +71 (RDS_CONT) minimum width 1. +72 (RDS_CONT) maximum length 1. +73 (RDS_VIA) minimum width 1. +74 (RDS_VIA) maximum length 1. +75 (RDS_VIA2) minimum width 1. +76 (RDS_VIA2) maximum length 1. +77 (RDS_VIA3) minimum width 1. +78 (RDS_VIA3) maximum length 1. +79 (RDS_POLY,RDS_ACTIV) Manhatan distance min 1. +80 (RDS_ALU5) minimum width 2. +81 (RDS_ALU5) minimum width 2. +82 (RDS_ALU5) Manhatan distance min 8. +83 (RDS_ALU5,RDS_ALU5) Manhatan distance min 8. +84 (RDS_ALU6) minimum width 2. +85 (RDS_ALU6) minimum width 2. +86 (RDS_ALU6) Manhatan distance min 8. +87 (RDS_ALU6,RDS_ALU6) Manhatan distance min 8. +88 (RDS_VIA4,RDS_VIA4) Manhatan distance min 9. +89 (RDS_VIA5,RDS_VIA5) Manhatan distance min 9. +90 (RDS_VIA4) minimum width 1. +91 (RDS_VIA4) maximum length 1. +92 (RDS_VIA5) minimum width 1. +93 (RDS_VIA5) maximum length 1. +94 (RDS_POLY2) minimum width 1. +95 (RDS_POLY2) minimum width 1. +96 (RDS_POLY2) Manhatan distance min 5. +97 (RDS_POLY2,POLY2) Manhatan distance min 5. +98 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +99 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +100 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +101 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +102 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +103 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +104 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +END_DRC_COMMENT +END_DRC_RULES diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_chip.rin b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_chip.rin new file mode 100644 index 00000000..4d2d88f3 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_chip.rin @@ -0,0 +1,40 @@ +north ( + ad_out_pl31 ad_out_pl30 ad_out_pl29 ad_out_pl28 + ad_out_pl27 ad_out_pl26 ad_out_pl25 ad_out_pl24 + it_in_pl0 it_in_pl1 it_in_pl2 it_in_pl3 + clock_ring ck_vsse_pl_0 vssi_pl_0 vddi_pl_0 vdde_pl_0 + vdde_pl_4 vsse_pl_4 it_in_pl4 it_in_pl5 it_in_pl6 + reset_pl byte_pl1 + byte_pl0 frz_pl + test_pl +) +south ( + ad_out_pl5 ad_out_pl4 + ad_out_pl3 ad_out_pl2 ad_out_pl1 ad_out_pl0 + dat_inout_pl31 dat_inout_pl30 dat_inout_pl29 dat_inout_pl28 + dat_inout_pl27 dat_inout_pl26 dat_inout_pl25 dat_inout_pl24 + scin_pl + vddi_pl_3 ck_vssi_pl_3 vdde_pl_3 vsse_pl_3 + vdde_pl_7 vsse_pl_7 + dat_inout_pl23 dat_inout_pl22 dat_inout_pl21 dat_inout_pl20 + dat_inout_pl19 dat_inout_pl18 dat_inout_pl17 dat_inout_pl16 + +) +east ( + scout_pl rw_pl + dat_inout_pl15 dat_inout_pl14 dat_inout_pl13 dat_inout_pl12 + dat_inout_pl11 dat_inout_pl10 dat_inout_pl9 dat_inout_pl8 + vdde_pl_1 + vddi_pl_1 vsse_pl_1 vssi_pl_1 vdde_pl_5 vsse_pl_5 + dat_inout_pl7 dat_inout_pl6 dat_inout_pl5 dat_inout_pl4 + dat_inout_pl3 dat_inout_pl2 dat_inout_pl1 dat_inout_pl0 +) +west ( + ad_out_pl23 ad_out_pl22 ad_out_pl21 ad_out_pl20 + ad_out_pl19 ad_out_pl18 ad_out_pl17 ad_out_pl16 + ad_out_pl15 ad_out_pl14 ad_out_pl13 ad_out_pl12 + vssi_pl_2 vddi_pl_2 vdde_pl_2 vsse_pl_2 vdde_pl_6 vsse_pl_6 + ad_out_pl11 ad_out_pl10 ad_out_pl9 ad_out_pl8 + ad_out_pl7 ad_out_pl6 +) + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_chip.vst b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_chip.vst new file mode 100644 index 00000000..c1c0f52c --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_chip.vst @@ -0,0 +1,1326 @@ +-------------------------------------------------------------- +-- Structural description if the DLXm chip -- +-- instantiating core and symbolic pads -- +-- input symbolic pads done -- +-- modif plot ck +-- modif chemin de test +-- scin : datapath --> control : scout +-- control scin : sequencer --> status: scout +-- modif byte (0 to 3) pour conformite a la carte et sortie non inversee +-- modif rw non inverse +-- datain_dpt : plot non inverse +-- dataout_dpt : plot non inverse +-- rw_ctl : ctl plot tristate data non inverse +-- frz_ctl : ctl plot tristate adresse non inverse +-- adr : plot non inverse +-- 2 horloeges ck_ctl vers le controle et ck_dpr vers le datapath +-- version v0.2 -- +-- January 1995 -- +--------------------------------------------------------------- + + +ENTITY mips_chip IS + PORT ( + ck : in bit; -- external clock + reset : in bit; -- external reset + frz : in bit; -- freeze + int : in bit_vector(5 downto 0); -- external interrupts + data : inout mux_vector(31 downto 0) bus; -- inout data + W : out bit_vector(0 to 1); -- select data byte + rw : out bit; -- read or write + berr : in bit; -- bus error + adr : out mux_vector(31 downto 0) bus; -- address word + scin : in bit; -- scan in + test : in bit; -- test mode + scout : out bit; -- scan out + vdd : in bit; -- core supply + vss : in bit; -- core supply + vddp : in bit; -- pad supply + vssp : in bit -- pad supply + ); +END mips_chip; + + +ARCHITECTURE structural_view OF mips_chip IS + COMPONENT mips_core + port ( + adr : out BIT_VECTOR(31 DOWNTO 0); + datain : in BIT_VECTOR(31 DOWNTO 0); + dataout : out BIT_VECTOR(31 DOWNTO 0); + int : in BIT_VECTOR(5 DOWNTO 0); + scin : in BIT; + scout : out BIT; + test : in BIT; + reset : in BIT; + frz : in BIT; + W : out BIT_VECTOR(0 to 1); + rw : out BIT; + berr : in BIT; + rw_ctl : out BIT_VECTOR(15 downto 0); + frz_ctl : out BIT_VECTOR(15 downto 0); + ck_ctl : in BIT; + ck_dpt : in BIT; + vdd : in BIT; + vss : in BIT + ); + END COMPONENT; + + COMPONENT piot_sp + port ( + i : in BIT; + b : in BIT; + t : out BIT; + pad : inout MUX_BIT bus; + ck : in BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); + END COMPONENT; + + COMPONENT pot_sp + port ( + i : in BIT; + b : in BIT; + pad : out MUX_BIT BUS; + ck : in BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); + END COMPONENT; + + COMPONENT po_sp + port ( + i : in BIT; + pad : out BIT; + ck : in BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); + END COMPONENT; + + COMPONENT pi_sp + port ( + pad : in BIT; + t : out BIT; + ck : in BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); + END COMPONENT; + + COMPONENT pck_sp + port ( + pad : in BIT; + ck : out BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); + END COMPONENT; + + COMPONENT pvddi_sp + port ( + ck : in BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); + END COMPONENT; + + COMPONENT pvssick_sp + port ( + cko : out WOR_BIT BUS; + ck : in BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); + END COMPONENT; + + COMPONENT pvssi_sp + port ( + ck : in BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); + END COMPONENT; + + COMPONENT pvdde_sp + port ( + ck : in BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); + END COMPONENT; + + COMPONENT pvsse_sp + port ( + ck : in BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); + END COMPONENT; + + COMPONENT pvsseck_sp + port ( + cko : out WOR_BIT BUS; + ck : in BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); + END COMPONENT; + + SIGNAL ck_ctl_c : bit; -- core clock + SIGNAL ck_dpt_c : bit; -- core clock + SIGNAL frz_c : bit; + SIGNAL int_c : bit_vector(5 downto 0); + SIGNAL adr_c : bit_vector(31 downto 0); -- core address signal + SIGNAL W_c : bit_vector(0 to 1); + SIGNAL datain_c : bit_vector(31 downto 0); + SIGNAL dataout_c : bit_vector(31 downto 0); + SIGNAL rw_c : bit; + SIGNAL berr_c : bit; + SIGNAL scout_c : bit; + SIGNAL reset_c : bit; + SIGNAL rw_ctl_c : bit_vector(15 downto 0); -- data tristate control + SIGNAL frz_ctl_c : bit_vector(15 downto 0); -- address tristate control + SIGNAL scin_c : bit; + SIGNAL test_c : bit; + SIGNAL ck_ring : bit; -- pad ring clock + +BEGIN + + core : mips_core + PORT MAP ( + vss => vss, -- core supply + vdd => vdd, -- core supply + ck_ctl => ck_ctl_c, -- core control clock + ck_dpt => ck_dpt_c, -- core dpt clock + rw_ctl => rw_ctl_c, -- inout data cntrol + frz_ctl => frz_ctl_c, -- out address control + rw => rw_c, + W => W_c, + berr => berr_c, + frz => frz_c, + reset => reset_c, + test => test_c, + scout => scout_c, + scin => scin_c, + int => int_c, + dataout => dataout_c, + datain => datain_c, + adr => adr_c + ); + + clock_ring : pck_sp + PORT MAP ( + pad => ck, + ck => ck_ring, + vdde => vddp, + vddi => vdd, + vsse => vssp, + vssi => vss); + + ad_out_pl0 : pot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => adr(0), + b => frz_ctl_c(0), + i => adr_c(0)); + + ad_out_pl1 : pot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => adr(1), + b => frz_ctl_c(0), + i => adr_c(1)); + + ad_out_pl2 : pot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => adr(2), + b => frz_ctl_c(1), + i => adr_c(2)); + + ad_out_pl3 : pot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => adr(3), + b => frz_ctl_c(1), + i => adr_c(3)); + + ad_out_pl4 : pot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => adr(4), + b => frz_ctl_c(2), + i => adr_c(4)); + + ad_out_pl5 : pot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => adr(5), + b => frz_ctl_c(2), + i => adr_c(5)); + + ad_out_pl6 : pot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => adr(6), + b => frz_ctl_c(3), + i => adr_c(6)); + + ad_out_pl7 : pot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => adr(7), + b => frz_ctl_c(3), + i => adr_c(7)); + + ad_out_pl8 : pot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => adr(8), + b => frz_ctl_c(4), + i => adr_c(8)); + + ad_out_pl9 : pot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => adr(9), + b => frz_ctl_c(4), + i => adr_c(9)); + + ad_out_pl10 : pot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => adr(10), + b => frz_ctl_c(5), + i => adr_c(10)); + + ad_out_pl11 : pot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => adr(11), + b => frz_ctl_c(5), + i => adr_c(11)); + + ad_out_pl12 : pot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => adr(12), + b => frz_ctl_c(6), + i => adr_c(12)); + + ad_out_pl13 : pot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => adr(13), + b => frz_ctl_c(6), + i => adr_c(13)); + + ad_out_pl14 : pot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => adr(14), + b => frz_ctl_c(7), + i => adr_c(14)); + + ad_out_pl15 : pot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => adr(15), + b => frz_ctl_c(7), + i => adr_c(15)); + + ad_out_pl16 : pot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => adr(16), + b => frz_ctl_c(8), + i => adr_c(16)); + + ad_out_pl17 : pot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => adr(17), + b => frz_ctl_c(8), + i => adr_c(17)); + + ad_out_pl18 : pot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => adr(18), + b => frz_ctl_c(9), + i => adr_c(18)); + + ad_out_pl19 : pot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => adr(19), + b => frz_ctl_c(9), + i => adr_c(19)); + + ad_out_pl20 : pot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => adr(20), + b => frz_ctl_c(10), + i => adr_c(20)); + + ad_out_pl21 : pot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => adr(21), + b => frz_ctl_c(10), + i => adr_c(21)); + + ad_out_pl22 : pot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => adr(22), + b => frz_ctl_c(11), + i => adr_c(22)); + + ad_out_pl23 : pot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => adr(23), + b => frz_ctl_c(11), + i => adr_c(23)); + + ad_out_pl24 : pot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => adr(24), + b => frz_ctl_c(12), + i => adr_c(24)); + + ad_out_pl25 : pot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => adr(25), + b => frz_ctl_c(12), + i => adr_c(25)); + + ad_out_pl26 : pot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => adr(26), + b => frz_ctl_c(13), + i => adr_c(26)); + + ad_out_pl27 : pot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => adr(27), + b => frz_ctl_c(13), + i => adr_c(27)); + + ad_out_pl28 : pot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => adr(28), + b => frz_ctl_c(14), + i => adr_c(28)); + + ad_out_pl29 : pot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => adr(29), + b => frz_ctl_c(14), + i => adr_c(29)); + + ad_out_pl30 : pot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => adr(30), + b => frz_ctl_c(15), + i => adr_c(30)); + + ad_out_pl31 : pot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => adr(31), + b => frz_ctl_c(15), + i => adr_c(31)); + + dat_inout_pl0 : piot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => data(0), + t => datain_c(0), + b => rw_ctl_c(0), + i => dataout_c(0)); + + dat_inout_pl1 : piot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => data(1), + t => datain_c(1), + b => rw_ctl_c(0), + i => dataout_c(1)); + + dat_inout_pl2 : piot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => data(2), + t => datain_c(2), + b => rw_ctl_c(1), + i => dataout_c(2)); + + dat_inout_pl3 : piot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => data(3), + t => datain_c(3), + b => rw_ctl_c(1), + i => dataout_c(3)); + + dat_inout_pl4 : piot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => data(4), + t => datain_c(4), + b => rw_ctl_c(2), + i => dataout_c(4)); + + dat_inout_pl5 : piot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => data(5), + t => datain_c(5), + b => rw_ctl_c(2), + i => dataout_c(5)); + + dat_inout_pl6 : piot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => data(6), + t => datain_c(6), + b => rw_ctl_c(3), + i => dataout_c(6)); + + dat_inout_pl7 : piot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => data(7), + t => datain_c(7), + b => rw_ctl_c(3), + i => dataout_c(7)); + + dat_inout_pl8 : piot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => data(8), + t => datain_c(8), + b => rw_ctl_c(4), + i => dataout_c(8)); + + dat_inout_pl9 : piot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => data(9), + t => datain_c(9), + b => rw_ctl_c(4), + i => dataout_c(9)); + + dat_inout_pl10 : piot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => data(10), + t => datain_c(10), + b => rw_ctl_c(5), + i => dataout_c(10)); + + dat_inout_pl11 : piot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => data(11), + t => datain_c(11), + b => rw_ctl_c(5), + i => dataout_c(11)); + + dat_inout_pl12 : piot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => data(12), + t => datain_c(12), + b => rw_ctl_c(6), + i => dataout_c(12)); + + dat_inout_pl13 : piot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => data(13), + t => datain_c(13), + b => rw_ctl_c(6), + i => dataout_c(13)); + + dat_inout_pl14 : piot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => data(14), + t => datain_c(14), + b => rw_ctl_c(7), + i => dataout_c(14)); + + dat_inout_pl15 : piot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => data(15), + t => datain_c(15), + b => rw_ctl_c(7), + i => dataout_c(15)); + + dat_inout_pl16 : piot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => data(16), + t => datain_c(16), + b => rw_ctl_c(8), + i => dataout_c(16)); + + dat_inout_pl17 : piot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => data(17), + t => datain_c(17), + b => rw_ctl_c(8), + i => dataout_c(17)); + + dat_inout_pl18 : piot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => data(18), + t => datain_c(18), + b => rw_ctl_c(9), + i => dataout_c(18)); + + dat_inout_pl19 : piot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => data(19), + t => datain_c(19), + b => rw_ctl_c(9), + i => dataout_c(19)); + + dat_inout_pl20 : piot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => data(20), + t => datain_c(20), + b => rw_ctl_c(10), + i => dataout_c(20)); + + dat_inout_pl21 : piot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => data(21), + t => datain_c(21), + b => rw_ctl_c(10), + i => dataout_c(21)); + + dat_inout_pl22 : piot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => data(22), + t => datain_c(22), + b => rw_ctl_c(11), + i => dataout_c(22)); + + dat_inout_pl23 : piot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => data(23), + t => datain_c(23), + b => rw_ctl_c(11), + i => dataout_c(23)); + + dat_inout_pl24 : piot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => data(24), + t => datain_c(24), + b => rw_ctl_c(12), + i => dataout_c(24)); + + dat_inout_pl25 : piot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => data(25), + t => datain_c(25), + b => rw_ctl_c(12), + i => dataout_c(25)); + + dat_inout_pl26 : piot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => data(26), + t => datain_c(26), + b => rw_ctl_c(13), + i => dataout_c(26)); + + dat_inout_pl27 : piot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => data(27), + t => datain_c(27), + b => rw_ctl_c(13), + i => dataout_c(27)); + + dat_inout_pl28 : piot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => data(28), + t => datain_c(28), + b => rw_ctl_c(14), + i => dataout_c(28)); + + dat_inout_pl29 : piot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => data(29), + t => datain_c(29), + b => rw_ctl_c(14), + i => dataout_c(29)); + + dat_inout_pl30 : piot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => data(30), + t => datain_c(30), + b => rw_ctl_c(15), + i => dataout_c(30)); + + dat_inout_pl31 : piot_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => data(31), + t => datain_c(31), + b => rw_ctl_c(15), + i => dataout_c(31)); + + it_in_pl0 : pi_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + t => int_c(0), + pad => int(0)); + + it_in_pl1 : pi_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + t => int_c(1), + pad => int(1)); + + it_in_pl2 : pi_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + t => int_c(2), + pad => int(2)); + + it_in_pl3 : pi_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + t => int_c(3), + pad => int(3)); + + it_in_pl4 : pi_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + t => int_c(4), + pad => int(4)); + + it_in_pl5 : pi_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + t => int_c(5), + pad => int(5)); + +it_in_pl6 : pi_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + t => berr_c, + pad => berr); + + + scin_pl : pi_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + t => scin_c, + pad => scin); + + scout_pl : po_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => scout, + i => scout_c); + + test_pl : pi_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + t => test_c, + pad => test); + + reset_pl : pi_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + t => reset_c, + pad => reset); + + frz_pl : pi_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + t => frz_c, + pad => frz); + + byte_pl0 : po_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => W(0), + i => W_c(0)); + + byte_pl1 : po_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => W(1), + i => W_c(1)); + + + + rw_pl : po_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp, + pad => rw, + i => rw_c); + + vddi_pl_0 : pvddi_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp); + + vddi_pl_1 : pvddi_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp); + + vddi_pl_2 : pvddi_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp); + + vddi_pl_3 : pvddi_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp); + + ck_vssi_pl_3 : pvssick_sp + PORT MAP ( + cko => ck_dpt_c, + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp); + + vssi_pl_1 : pvssi_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp); + + vssi_pl_2 : pvssi_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp); + + vssi_pl_0 : pvssi_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vddi => vdd, + vdde => vddp); + + vdde_pl_0 : pvdde_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vdde => vddp, + vddi => vdd); + + vdde_pl_1 : pvdde_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vdde => vddp, + vddi => vdd); + + vdde_pl_2 : pvdde_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vdde => vddp, + vddi => vdd); + + vdde_pl_3 : pvdde_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vdde => vddp, + vddi => vdd); + + vdde_pl_4 : pvdde_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vdde => vddp, + vddi => vdd); + + vdde_pl_5 : pvdde_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vdde => vddp, + vddi => vdd); + + vdde_pl_6 : pvdde_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vdde => vddp, + vddi => vdd); + + vdde_pl_7 : pvdde_sp + PORT MAP ( + ck => ck_ring, + vssi => vss, + vsse => vssp, + vdde => vddp, + vddi => vdd); + +ck_vsse_pl_0 : pvsseck_sp + PORT MAP ( + ck => ck_ring, + cko => ck_ctl_c, + vsse => vssp, + vddi => vdd, + vdde => vddp, + vssi => vss); + + vsse_pl_1 : pvsse_sp + PORT MAP ( + ck => ck_ring, + vsse => vssp, + vddi => vdd, + vdde => vddp, + vssi => vss); + + vsse_pl_2 : pvsse_sp + PORT MAP ( + ck => ck_ring, + vsse => vssp, + vddi => vdd, + vdde => vddp, + vssi => vss); + + vsse_pl_3 : pvsse_sp + PORT MAP ( + ck => ck_ring, + vsse => vssp, + vssi => vss, + vddi => vdd, + vdde => vddp); + + vsse_pl_4 : pvsse_sp + PORT MAP ( + ck => ck_ring, + vsse => vssp, + vssi => vss, + vddi => vdd, + vdde => vddp); + + vsse_pl_5 : pvsse_sp + PORT MAP ( + ck => ck_ring, + vsse => vssp, + vssi => vss, + vddi => vdd, + vdde => vddp); + + vsse_pl_6 : pvsse_sp + PORT MAP ( + ck => ck_ring, + vsse => vssp, + vssi => vss, + vddi => vdd, + vdde => vddp); + + vsse_pl_7 : pvsse_sp + PORT MAP ( + ck => ck_ring, + vsse => vssp, + vssi => vss, + vddi => vdd, + vdde => vddp); + +end structural_view; diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_core.c b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_core.c new file mode 100644 index 00000000..19bb3d9d --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_core.c @@ -0,0 +1,17 @@ +# include +# include + +int main() +{ +/*Preplacement du coeur*/ +GENLIB_DEF_PHFIG("mips_core_place"); + +GENLIB_PLACE("mips_dpt","dpt",NOSYM,0,0); + +/* boite d'aboutement */ +GENLIB_DEF_AB(-150,-150,150,2000); + +GENLIB_SAVE_PHFIG(); + +return 0; +} diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_core.ioc b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_core.ioc new file mode 100644 index 00000000..6f10fa39 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_core.ioc @@ -0,0 +1,166 @@ +# Copyright (c) 1997 by Cadence. All rights reserved. +################################################################### +# In each of TOP()/BOTTOM()/LEFT()/RIGHT() section, there are # +# placed IOs. In the IGNORE() section, the IOs are ignored # +# by the IOPlacer. In every section, the IO syntax could be: # +# for pin: (IOPIN iopinName.0 ); # +# for pad: iopadName orientation ; # +# for space: SPACE value; # +# The capital words are keywords. orientation is not required. # +# The value is the space between the IO above and the IO below it.# +################################################################### + +BOTTOM ( # IOs are ordered from left to right + (IOPIN ck_ctl.0 ); + (IOPIN test.0 ); + (IOPIN ck_dpt.0 ); + (IOPIN adr(31).0); + (IOPIN adr(30).0); + (IOPIN adr(29).0); + (IOPIN adr(28).0); + (IOPIN adr(27).0); + (IOPIN adr(26).0); + (IOPIN adr(25).0); + (IOPIN adr(24).0); + (IOPIN adr(23).0); + (IOPIN adr(22).0); + (IOPIN adr(21).0); + (IOPIN adr(20).0); + (IOPIN adr(19).0); + (IOPIN adr(18).0); + (IOPIN adr(17).0); + (IOPIN adr(16).0); + (IOPIN adr(15).0); + (IOPIN adr(14).0); + (IOPIN adr(13).0); + (IOPIN adr(12).0); + (IOPIN adr(11).0); + (IOPIN adr(10).0); + (IOPIN adr(9).0); + (IOPIN adr(8).0); + (IOPIN adr(7).0); + (IOPIN adr(6).0); + (IOPIN adr(5).0); + (IOPIN adr(4).0); + (IOPIN adr(3).0); + (IOPIN adr(2).0); + (IOPIN adr(1).0); + (IOPIN adr(0).0); + (IOPIN dataout(31).0); + (IOPIN dataout(30).0); + (IOPIN dataout(29).0); + (IOPIN dataout(28).0); + (IOPIN dataout(27).0); + (IOPIN dataout(26).0); + (IOPIN dataout(25).0); + (IOPIN dataout(24).0); + (IOPIN dataout(23).0); + (IOPIN dataout(22).0); + (IOPIN dataout(21).0); + (IOPIN dataout(20).0); + (IOPIN dataout(19).0); + (IOPIN dataout(18).0); + (IOPIN dataout(17).0); + (IOPIN dataout(16).0); + (IOPIN dataout(15).0); + (IOPIN dataout(14).0); + (IOPIN dataout(13).0); + (IOPIN dataout(12).0); + (IOPIN dataout(11).0); + (IOPIN dataout(10).0); + (IOPIN dataout(9).0); + (IOPIN dataout(8).0); + (IOPIN dataout(7).0); + (IOPIN dataout(6).0); + (IOPIN dataout(5).0); + (IOPIN dataout(4).0); + (IOPIN dataout(3).0); + (IOPIN dataout(2).0); + (IOPIN dataout(1).0); + (IOPIN dataout(0).0); + (IOPIN datain(31).0); + (IOPIN datain(30).0); + (IOPIN datain(29).0); + (IOPIN datain(28).0); + (IOPIN datain(27).0); + (IOPIN datain(26).0); + (IOPIN datain(25).0); + (IOPIN datain(24).0); + (IOPIN datain(23).0); + (IOPIN datain(22).0); + (IOPIN datain(21).0); + (IOPIN datain(20).0); + (IOPIN datain(19).0); + (IOPIN datain(18).0); + (IOPIN datain(17).0); + (IOPIN datain(16).0); + (IOPIN datain(15).0); + (IOPIN datain(14).0); + (IOPIN datain(13).0); + (IOPIN datain(12).0); + (IOPIN datain(11).0); + (IOPIN datain(10).0); + (IOPIN datain(9).0); + (IOPIN datain(8).0); + (IOPIN datain(7).0); + (IOPIN datain(6).0); + (IOPIN datain(5).0); + (IOPIN datain(4).0); + (IOPIN datain(3).0); + (IOPIN datain(2).0); + (IOPIN datain(1).0); + (IOPIN datain(0).0); + (IOPIN scout.0 ); +) + +TOP ( # IOs are ordered from left to right + (IOPIN int(0).0 ); + (IOPIN int(1).0 ); + (IOPIN int(2).0 ); + (IOPIN int(3).0 ); + (IOPIN int(4).0 ); + (IOPIN int(5).0 ); + (IOPIN scin.0 ); + (IOPIN reset.0 ); + (IOPIN frz.0 ); + (IOPIN w(0).0 ); + (IOPIN w(1).0 ); + (IOPIN rw.0 ); + (IOPIN berr.0 ); + (IOPIN rw_ctl(0).0 ); + (IOPIN rw_ctl(1).0 ); + (IOPIN rw_ctl(2).0 ); + (IOPIN rw_ctl(3).0 ); + (IOPIN rw_ctl(4).0 ); + (IOPIN rw_ctl(5).0 ); + (IOPIN rw_ctl(6).0 ); + (IOPIN rw_ctl(7).0 ); + (IOPIN rw_ctl(8).0 ); + (IOPIN rw_ctl(9).0 ); + (IOPIN rw_ctl(10).0 ); + (IOPIN rw_ctl(11).0 ); + (IOPIN rw_ctl(12).0 ); + (IOPIN rw_ctl(13).0 ); + (IOPIN rw_ctl(14).0 ); + (IOPIN rw_ctl(15).0 ); + (IOPIN frz_ctl(0).0 ); + (IOPIN frz_ctl(1).0 ); + (IOPIN frz_ctl(2).0 ); + (IOPIN frz_ctl(3).0 ); + (IOPIN frz_ctl(4).0 ); + (IOPIN frz_ctl(5).0 ); + (IOPIN frz_ctl(6).0 ); + (IOPIN frz_ctl(7).0 ); + (IOPIN frz_ctl(8).0 ); + (IOPIN frz_ctl(9).0 ); + (IOPIN frz_ctl(10).0 ); + (IOPIN frz_ctl(11).0 ); + (IOPIN frz_ctl(12).0 ); + (IOPIN frz_ctl(13).0 ); + (IOPIN frz_ctl(14).0 ); + (IOPIN frz_ctl(15).0 ); + +) +IGNORE ( # IOs are ignored(not placed) by IO Placer +) + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_core.vst b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_core.vst new file mode 100644 index 00000000..2d840b74 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_core.vst @@ -0,0 +1,408 @@ +-- VHDL structural description generated from `mips_core` +-- date : Mon Jul 30 17:18:35 2001 + + +-- Entity Declaration + +ENTITY mips_core IS + PORT ( + adr : out BIT_VECTOR (31 DOWNTO 0); -- adr + datain : in BIT_VECTOR (31 DOWNTO 0); -- datain + dataout : out BIT_VECTOR (31 DOWNTO 0); -- dataout + int : in BIT_VECTOR (5 DOWNTO 0); -- int + scin : in BIT; -- scin + scout : out BIT; -- scout + test : in BIT; -- test + reset : in BIT; -- reset + frz : in BIT; -- frz + w : out BIT_VECTOR (0 TO 1); -- w + rw : out BIT; -- rw + berr : in BIT; -- berr + rw_ctl : out BIT_VECTOR (15 DOWNTO 0); -- rw_ctl + frz_ctl : out BIT_VECTOR (15 DOWNTO 0); -- frz_ctl + ck_ctl : in BIT; -- ck_ctl + ck_dpt : in BIT; -- ck_dpt + vdd : in BIT; -- vdd + vss : in BIT -- vss + ); +END mips_core; + +-- Architecture Declaration + +ARCHITECTURE VST OF mips_core IS + COMPONENT mips_ctl + port ( + ck : in BIT; -- ck + frz : in BIT; -- frz + reset : in BIT; -- reset + scin : in BIT; -- scin + scout : out BIT; -- scout + test : in BIT; -- test + berr : in BIT; -- berr + w : out BIT_VECTOR(0 TO 1); -- w + int : in BIT_VECTOR(5 DOWNTO 0); -- int + rw_ctl : out BIT_VECTOR(15 DOWNTO 0); -- rw_ctl + frz_ctl : out BIT_VECTOR(15 DOWNTO 0); -- frz_ctl + wenable : out BIT_VECTOR(6 DOWNTO 0); -- wenable + rf_aw : out BIT_VECTOR(4 DOWNTO 0); -- rf_aw + rf_ar : out BIT_VECTOR(4 DOWNTO 0); -- rf_ar + ctlopx : out BIT_VECTOR(8 DOWNTO 0); -- ctlopx + ctlopy : out BIT_VECTOR(6 DOWNTO 0); -- ctlopy + ctlalu : out BIT_VECTOR(5 DOWNTO 0); -- ctlalu + ctlrw : out BIT_VECTOR(4 DOWNTO 1); -- ctlrw + ctladr : out BIT; -- ctladr + crsrout : out BIT_VECTOR(15 DOWNTO 0); -- crsrout + alu_31_n : in BIT; -- alu_31_n + alu_1_n : in BIT; -- alu_1_n + alu_0_n : in BIT; -- alu_0_n + adr_1_n : in BIT; -- adr_1_n + adr_0_n : in BIT; -- adr_0_n + crsrin : in BIT_VECTOR(15 DOWNTO 0); -- crsrin + opx_sign : in BIT; -- opx_sign + opy_sign : in BIT; -- opy_sign + codop : in BIT_VECTOR(18 DOWNTO 0); -- codop + rs : in BIT_VECTOR(4 DOWNTO 0); -- rs + rd : in BIT_VECTOR(4 DOWNTO 0); -- rd + rdrt : in BIT_VECTOR(4 DOWNTO 0); -- rdrt + alu_test_n : out BIT; -- alu_test_n + alu_c31_n : in BIT; -- alu_c31_n + alu_c30_n : in BIT; -- alu_c30_n + alu_nul : in BIT; -- alu_nul + alu_sign : in BIT; -- alu_sign + rw : out BIT; -- rw + vdd : in BIT; -- vdd + vss : in BIT -- vss + ); + END COMPONENT; + + COMPONENT mips_dpt + port ( + vdd : in BIT; -- vdd + vss : in BIT; -- vss + test : in BIT; -- test + dpt_scin : in BIT; -- dpt_scin + dpt_scout : out BIT; -- dpt_scout + ck : in BIT; -- ck + pc_wen : in BIT; -- pc_wen + ad_wen : in BIT; -- ad_wen + epc_wen : in BIT; -- epc_wen + bar_wen : in BIT; -- bar_wen + ir_wen : in BIT; -- ir_wen + dt_wen : in BIT; -- dt_wen + hi_wen : in BIT; -- hi_wen + lo_wen : in BIT; -- lo_wen + rf_wen : in BIT; -- rf_wen + rf_aw : in BIT_VECTOR(4 DOWNTO 0); -- rf_aw + rf_ar : in BIT_VECTOR(4 DOWNTO 0); -- rf_ar + opx_ts7 : in BIT; -- opx_ts7 + opx_ts6 : in BIT; -- opx_ts6 + opx_ts5 : in BIT; -- opx_ts5 + opx_ts4 : in BIT; -- opx_ts4 + opx_ts3 : in BIT; -- opx_ts3 + opx_ts2 : in BIT; -- opx_ts2 + opx_ts1 : in BIT; -- opx_ts1 + opx_ts0 : in BIT; -- opx_ts0 + opx_mx7 : in BIT; -- opx_mx7 + opx_mx6 : in BIT; -- opx_mx6 + opx_mx5 : in BIT; -- opx_mx5 + opx_mx4 : in BIT; -- opx_mx4 + opx_mx3 : in BIT; -- opx_mx3 + opx_mx2 : in BIT; -- opx_mx2 + opx_mx1 : in BIT; -- opx_mx1 + opx_sign : out BIT; -- opx_sign + crsr_dpt_out : out BIT_VECTOR(15 DOWNTO 0); -- crsr_dpt_out + crsr_sts_in : in BIT_VECTOR(15 DOWNTO 0); -- crsr_sts_in + opy_ts6 : in BIT; -- opy_ts6 + opy_ts5 : in BIT; -- opy_ts5 + opy_ts4 : in BIT; -- opy_ts4 + opy_ts3 : in BIT; -- opy_ts3 + opy_ts2 : in BIT; -- opy_ts2 + opy_ts1 : in BIT; -- opy_ts1 + opy_mx6 : in BIT; -- opy_mx6 + opy_mx5 : in BIT; -- opy_mx5 + opy_mx4 : in BIT; -- opy_mx4 + opy_mx3 : in BIT; -- opy_mx3 + opy_mx2 : in BIT; -- opy_mx2 + opy_mx1 : in BIT; -- opy_mx1 + opy_codop : out BIT_VECTOR(18 DOWNTO 0); -- opy_codop + opy_rs : out BIT_VECTOR(4 DOWNTO 0); -- opy_rs + opy_rdrt : out BIT_VECTOR(4 DOWNTO 0); -- opy_rdrt + opy_rd : out BIT_VECTOR(4 DOWNTO 0); -- opy_rd + opy_sign : out BIT; -- opy_sign + data_in_dpt : in BIT_VECTOR(31 DOWNTO 0); -- data_in_dpt + alu_mx5i0 : in BIT; -- alu_mx5i0 + alu_mx4i0 : in BIT; -- alu_mx4i0 + alu_mx3i0 : in BIT; -- alu_mx3i0 + alu_mx2i0 : in BIT; -- alu_mx2i0 + alu_mx2i1 : in BIT; -- alu_mx2i1 + alu_mx1i2 : in BIT; -- alu_mx1i2 + alu_mx1i1 : in BIT; -- alu_mx1i1 + alu_mx1i0 : in BIT; -- alu_mx1i0 + alu_mx0i0 : in BIT; -- alu_mx0i0 + alu_byte : in BIT; -- alu_byte + alu_half : in BIT; -- alu_half + alu_test_n : in BIT; -- alu_test_n + alu_c31 : out BIT; -- alu_c31 + alu_c30 : out BIT; -- alu_c30 + alu_nul : out BIT; -- alu_nul + alu_sign : out BIT; -- alu_sign + data_out_dpt : out BIT_VECTOR(31 DOWNTO 0); -- data_out_dpt + out_mx0i0 : in BIT; -- out_mx0i0 + out_adr : out BIT_VECTOR(31 DOWNTO 0); -- out_adr + alu_n_31 : inout BIT; -- alu_n_31 + alu_n_1 : inout BIT; -- alu_n_1 + alu_n_0 : inout BIT; -- alu_n_0 + adr_n_1 : inout BIT; -- adr_n_1 + adr_n_0 : inout BIT -- adr_n_0 + ); + END COMPONENT; + + SIGNAL adr_0_n : BIT; -- adr_0_n + SIGNAL adr_1_n : BIT; -- adr_1_n + SIGNAL alu_0_n : BIT; -- alu_0_n + SIGNAL alu_1_n : BIT; -- alu_1_n + SIGNAL alu_31_n : BIT; -- alu_31_n + SIGNAL alu_c30_n : BIT; -- alu_c30_n + SIGNAL alu_c31_n : BIT; -- alu_c31_n + SIGNAL alu_nul : BIT; -- alu_nul + SIGNAL alu_sign : BIT; -- alu_sign + SIGNAL alu_test_n : BIT; -- alu_test_n + SIGNAL codop_0 : BIT; -- codop 0 + SIGNAL codop_1 : BIT; -- codop 1 + SIGNAL codop_2 : BIT; -- codop 2 + SIGNAL codop_3 : BIT; -- codop 3 + SIGNAL codop_4 : BIT; -- codop 4 + SIGNAL codop_5 : BIT; -- codop 5 + SIGNAL codop_6 : BIT; -- codop 6 + SIGNAL codop_7 : BIT; -- codop 7 + SIGNAL codop_8 : BIT; -- codop 8 + SIGNAL codop_9 : BIT; -- codop 9 + SIGNAL codop_10 : BIT; -- codop 10 + SIGNAL codop_11 : BIT; -- codop 11 + SIGNAL codop_12 : BIT; -- codop 12 + SIGNAL codop_13 : BIT; -- codop 13 + SIGNAL codop_14 : BIT; -- codop 14 + SIGNAL codop_15 : BIT; -- codop 15 + SIGNAL codop_16 : BIT; -- codop 16 + SIGNAL codop_17 : BIT; -- codop 17 + SIGNAL codop_18 : BIT; -- codop 18 + SIGNAL crsrin_0 : BIT; -- crsrin 0 + SIGNAL crsrin_1 : BIT; -- crsrin 1 + SIGNAL crsrin_2 : BIT; -- crsrin 2 + SIGNAL crsrin_3 : BIT; -- crsrin 3 + SIGNAL crsrin_4 : BIT; -- crsrin 4 + SIGNAL crsrin_5 : BIT; -- crsrin 5 + SIGNAL crsrin_6 : BIT; -- crsrin 6 + SIGNAL crsrin_7 : BIT; -- crsrin 7 + SIGNAL crsrin_8 : BIT; -- crsrin 8 + SIGNAL crsrin_9 : BIT; -- crsrin 9 + SIGNAL crsrin_10 : BIT; -- crsrin 10 + SIGNAL crsrin_11 : BIT; -- crsrin 11 + SIGNAL crsrin_12 : BIT; -- crsrin 12 + SIGNAL crsrin_13 : BIT; -- crsrin 13 + SIGNAL crsrin_14 : BIT; -- crsrin 14 + SIGNAL crsrin_15 : BIT; -- crsrin 15 + SIGNAL crsrout_0 : BIT; -- crsrout 0 + SIGNAL crsrout_1 : BIT; -- crsrout 1 + SIGNAL crsrout_2 : BIT; -- crsrout 2 + SIGNAL crsrout_3 : BIT; -- crsrout 3 + SIGNAL crsrout_4 : BIT; -- crsrout 4 + SIGNAL crsrout_5 : BIT; -- crsrout 5 + SIGNAL crsrout_6 : BIT; -- crsrout 6 + SIGNAL crsrout_7 : BIT; -- crsrout 7 + SIGNAL crsrout_8 : BIT; -- crsrout 8 + SIGNAL crsrout_9 : BIT; -- crsrout 9 + SIGNAL crsrout_10 : BIT; -- crsrout 10 + SIGNAL crsrout_11 : BIT; -- crsrout 11 + SIGNAL crsrout_12 : BIT; -- crsrout 12 + SIGNAL crsrout_13 : BIT; -- crsrout 13 + SIGNAL crsrout_14 : BIT; -- crsrout 14 + SIGNAL crsrout_15 : BIT; -- crsrout 15 + SIGNAL ctl_scout : BIT; -- ctl_scout + SIGNAL ctladr : BIT; -- ctladr + SIGNAL ctlalu_0 : BIT; -- ctlalu 0 + SIGNAL ctlalu_1 : BIT; -- ctlalu 1 + SIGNAL ctlalu_2 : BIT; -- ctlalu 2 + SIGNAL ctlalu_3 : BIT; -- ctlalu 3 + SIGNAL ctlalu_4 : BIT; -- ctlalu 4 + SIGNAL ctlalu_5 : BIT; -- ctlalu 5 + SIGNAL ctlopx_0 : BIT; -- ctlopx 0 + SIGNAL ctlopx_1 : BIT; -- ctlopx 1 + SIGNAL ctlopx_2 : BIT; -- ctlopx 2 + SIGNAL ctlopx_3 : BIT; -- ctlopx 3 + SIGNAL ctlopx_4 : BIT; -- ctlopx 4 + SIGNAL ctlopx_5 : BIT; -- ctlopx 5 + SIGNAL ctlopx_6 : BIT; -- ctlopx 6 + SIGNAL ctlopx_7 : BIT; -- ctlopx 7 + SIGNAL ctlopx_8 : BIT; -- ctlopx 8 + SIGNAL ctlopy_0 : BIT; -- ctlopy 0 + SIGNAL ctlopy_1 : BIT; -- ctlopy 1 + SIGNAL ctlopy_2 : BIT; -- ctlopy 2 + SIGNAL ctlopy_3 : BIT; -- ctlopy 3 + SIGNAL ctlopy_4 : BIT; -- ctlopy 4 + SIGNAL ctlopy_5 : BIT; -- ctlopy 5 + SIGNAL ctlopy_6 : BIT; -- ctlopy 6 + SIGNAL ctlrw_1 : BIT; -- ctlrw 1 + SIGNAL ctlrw_2 : BIT; -- ctlrw 2 + SIGNAL ctlrw_3 : BIT; -- ctlrw 3 + SIGNAL ctlrw_4 : BIT; -- ctlrw 4 + SIGNAL opx_sign : BIT; -- opx_sign + SIGNAL opy_sign : BIT; -- opy_sign + SIGNAL rd_0 : BIT; -- rd 0 + SIGNAL rd_1 : BIT; -- rd 1 + SIGNAL rd_2 : BIT; -- rd 2 + SIGNAL rd_3 : BIT; -- rd 3 + SIGNAL rd_4 : BIT; -- rd 4 + SIGNAL rdrt_0 : BIT; -- rdrt 0 + SIGNAL rdrt_1 : BIT; -- rdrt 1 + SIGNAL rdrt_2 : BIT; -- rdrt 2 + SIGNAL rdrt_3 : BIT; -- rdrt 3 + SIGNAL rdrt_4 : BIT; -- rdrt 4 + SIGNAL rf_ar_0 : BIT; -- rf_ar 0 + SIGNAL rf_ar_1 : BIT; -- rf_ar 1 + SIGNAL rf_ar_2 : BIT; -- rf_ar 2 + SIGNAL rf_ar_3 : BIT; -- rf_ar 3 + SIGNAL rf_ar_4 : BIT; -- rf_ar 4 + SIGNAL rf_aw_0 : BIT; -- rf_aw 0 + SIGNAL rf_aw_1 : BIT; -- rf_aw 1 + SIGNAL rf_aw_2 : BIT; -- rf_aw 2 + SIGNAL rf_aw_3 : BIT; -- rf_aw 3 + SIGNAL rf_aw_4 : BIT; -- rf_aw 4 + SIGNAL rs_0 : BIT; -- rs 0 + SIGNAL rs_1 : BIT; -- rs 1 + SIGNAL rs_2 : BIT; -- rs 2 + SIGNAL rs_3 : BIT; -- rs 3 + SIGNAL rs_4 : BIT; -- rs 4 + SIGNAL wenable_0 : BIT; -- wenable 0 + SIGNAL wenable_1 : BIT; -- wenable 1 + SIGNAL wenable_2 : BIT; -- wenable 2 + SIGNAL wenable_3 : BIT; -- wenable 3 + SIGNAL wenable_4 : BIT; -- wenable 4 + SIGNAL wenable_5 : BIT; -- wenable 5 + SIGNAL wenable_6 : BIT; -- wenable 6 + +BEGIN + + ctl : mips_ctl + PORT MAP ( + vss => vss, + vdd => vdd, + rw => rw, + alu_sign => alu_sign, + alu_nul => alu_nul, + alu_c30_n => alu_c30_n, + alu_c31_n => alu_c31_n, + alu_test_n => alu_test_n, + rdrt => rdrt_4& rdrt_3& rdrt_2& rdrt_1& rdrt_0, + rd => rd_4& rd_3& rd_2& rd_1& rd_0, + rs => rs_4& rs_3& rs_2& rs_1& rs_0, + codop => codop_18& codop_17& codop_16& codop_15& codop_14& codop_13& codop_12& codop_11& codop_10& codop_9& codop_8& codop_7& codop_6& codop_5& codop_4& codop_3& codop_2& codop_1& codop_0, + opy_sign => opy_sign, + opx_sign => opx_sign, + crsrin => crsrin_15& crsrin_14& crsrin_13& crsrin_12& crsrin_11& crsrin_10& crsrin_9& crsrin_8& crsrin_7& crsrin_6& crsrin_5& crsrin_4& crsrin_3& crsrin_2& crsrin_1& crsrin_0, + adr_0_n => adr_0_n, + adr_1_n => adr_1_n, + alu_0_n => alu_0_n, + alu_1_n => alu_1_n, + alu_31_n => alu_31_n, + crsrout => crsrout_15& crsrout_14& crsrout_13& crsrout_12& crsrout_11& crsrout_10& crsrout_9& crsrout_8& crsrout_7& crsrout_6& crsrout_5& crsrout_4& crsrout_3& crsrout_2& crsrout_1& crsrout_0, + ctladr => ctladr, + ctlrw => ctlrw_4& ctlrw_3& ctlrw_2& ctlrw_1, + ctlalu => ctlalu_5& ctlalu_4& ctlalu_3& ctlalu_2& ctlalu_1& ctlalu_0, + ctlopy => ctlopy_6& ctlopy_5& ctlopy_4& ctlopy_3& ctlopy_2& ctlopy_1& ctlopy_0, + ctlopx => ctlopx_8& ctlopx_7& ctlopx_6& ctlopx_5& ctlopx_4& ctlopx_3& ctlopx_2& ctlopx_1& ctlopx_0, + rf_ar => rf_ar_4& rf_ar_3& rf_ar_2& rf_ar_1& rf_ar_0, + rf_aw => rf_aw_4& rf_aw_3& rf_aw_2& rf_aw_1& rf_aw_0, + wenable => wenable_6& wenable_5& wenable_4& wenable_3& wenable_2& wenable_1& wenable_0, + frz_ctl => frz_ctl(15)& frz_ctl(14)& frz_ctl(13)& frz_ctl(12)& frz_ctl(11)& frz_ctl(10)& frz_ctl(9)& frz_ctl(8)& frz_ctl(7)& frz_ctl(6)& frz_ctl(5)& frz_ctl(4)& frz_ctl(3)& frz_ctl(2)& frz_ctl(1)& frz_ctl(0), + rw_ctl => rw_ctl(15)& rw_ctl(14)& rw_ctl(13)& rw_ctl(12)& rw_ctl(11)& rw_ctl(10)& rw_ctl(9)& rw_ctl(8)& rw_ctl(7)& rw_ctl(6)& rw_ctl(5)& rw_ctl(4)& rw_ctl(3)& rw_ctl(2)& rw_ctl(1)& rw_ctl(0), + int => int(5)& int(4)& int(3)& int(2)& int(1)& int(0), + w => w(0)& w(1), + berr => berr, + test => test, + scout => ctl_scout, + scin => scin, + reset => reset, + frz => frz, + ck => ck_ctl); + dpt : mips_dpt + PORT MAP ( + adr_n_0 => adr_0_n, + adr_n_1 => adr_1_n, + alu_n_0 => alu_0_n, + alu_n_1 => alu_1_n, + alu_n_31 => alu_31_n, + out_adr => adr(31)& adr(30)& adr(29)& adr(28)& adr(27)& adr(26)& adr(25)& adr(24)& adr(23)& adr(22)& adr(21)& adr(20)& adr(19)& adr(18)& adr(17)& adr(16)& adr(15)& adr(14)& adr(13)& adr(12)& adr(11)& adr(10)& adr(9)& adr(8)& adr(7)& adr(6)& adr(5)& adr(4)& adr(3)& adr(2)& adr(1)& adr(0), + out_mx0i0 => ctladr, + data_out_dpt => dataout(31)& dataout(30)& dataout(29)& dataout(28)& dataout(27)& dataout(26)& dataout(25)& dataout(24)& dataout(23)& dataout(22)& dataout(21)& dataout(20)& dataout(19)& dataout(18)& dataout(17)& dataout(16)& dataout(15)& dataout(14)& dataout(13)& dataout(12)& dataout(11)& dataout(10)& dataout(9)& dataout(8)& dataout(7)& dataout(6)& dataout(5)& dataout(4)& dataout(3)& dataout(2)& dataout(1)& dataout(0), + alu_sign => alu_sign, + alu_nul => alu_nul, + alu_c30 => alu_c30_n, + alu_c31 => alu_c31_n, + alu_test_n => alu_test_n, + alu_half => ctlrw_2, + alu_byte => ctlrw_1, + alu_mx0i0 => ctlalu_0, + alu_mx1i0 => ctlalu_1, + alu_mx1i1 => ctlalu_1, + alu_mx1i2 => ctlalu_1, + alu_mx2i1 => ctlalu_2, + alu_mx2i0 => ctlalu_2, + alu_mx3i0 => ctlalu_3, + alu_mx4i0 => ctlalu_4, + alu_mx5i0 => ctlalu_5, + data_in_dpt => datain(31)& datain(30)& datain(29)& datain(28)& datain(27)& datain(26)& datain(25)& datain(24)& datain(23)& datain(22)& datain(21)& datain(20)& datain(19)& datain(18)& datain(17)& datain(16)& datain(15)& datain(14)& datain(13)& datain(12)& datain(11)& datain(10)& datain(9)& datain(8)& datain(7)& datain(6)& datain(5)& datain(4)& datain(3)& datain(2)& datain(1)& datain(0), + opy_sign => opy_sign, + opy_rd => rd_4& rd_3& rd_2& rd_1& rd_0, + opy_rdrt => rdrt_4& rdrt_3& rdrt_2& rdrt_1& rdrt_0, + opy_rs => rs_4& rs_3& rs_2& rs_1& rs_0, + opy_codop => codop_18& codop_17& codop_16& codop_15& codop_14& codop_13& codop_12& codop_11& codop_10& codop_9& codop_8& codop_7& codop_6& codop_5& codop_4& codop_3& codop_2& codop_1& codop_0, + opy_mx1 => ctlopy_0, + opy_mx2 => ctlopy_0, + opy_mx3 => ctlopy_0, + opy_mx4 => ctlopy_0, + opy_mx5 => ctlopy_0, + opy_mx6 => ctlopy_0, + opy_ts1 => ctlopy_1, + opy_ts2 => ctlopy_2, + opy_ts3 => ctlopy_3, + opy_ts4 => ctlopy_4, + opy_ts5 => ctlopy_5, + opy_ts6 => ctlopy_6, + crsr_sts_in => crsrout_15& crsrout_14& crsrout_13& crsrout_12& crsrout_11& crsrout_10& crsrout_9& crsrout_8& crsrout_7& crsrout_6& crsrout_5& crsrout_4& crsrout_3& crsrout_2& crsrout_1& crsrout_0, + crsr_dpt_out => crsrin_15& crsrin_14& crsrin_13& crsrin_12& crsrin_11& crsrin_10& crsrin_9& crsrin_8& crsrin_7& crsrin_6& crsrin_5& crsrin_4& crsrin_3& crsrin_2& crsrin_1& crsrin_0, + opx_sign => opx_sign, + opx_mx1 => ctlopx_0, + opx_mx2 => ctlopx_0, + opx_mx3 => ctlopx_0, + opx_mx4 => ctlopx_0, + opx_mx5 => ctlopx_0, + opx_mx6 => ctlopx_0, + opx_mx7 => ctlopx_0, + opx_ts0 => ctlopx_1, + opx_ts1 => ctlopx_2, + opx_ts2 => ctlopx_3, + opx_ts3 => ctlopx_4, + opx_ts4 => ctlopx_5, + opx_ts5 => ctlopx_6, + opx_ts6 => ctlopx_7, + opx_ts7 => ctlopx_8, + rf_ar => rf_ar_4& rf_ar_3& rf_ar_2& rf_ar_1& rf_ar_0, + rf_aw => rf_aw_4& rf_aw_3& rf_aw_2& rf_aw_1& rf_aw_0, + rf_wen => wenable_6, + lo_wen => wenable_2, + hi_wen => wenable_3, + dt_wen => ctlrw_3, + ir_wen => ctlrw_4, + bar_wen => wenable_1, + epc_wen => wenable_0, + ad_wen => wenable_4, + pc_wen => wenable_5, + ck => ck_dpt, + dpt_scout => scout, + dpt_scin => ctl_scout, + test => test, + vss => vss, + vdd => vdd); + +end VST; diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_cpu-orig.pat b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_cpu-orig.pat new file mode 100644 index 00000000..83f518fe --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_cpu-orig.pat @@ -0,0 +1,769 @@ +in ck B;; +in reset B;; +in frz B;; +in scin B;; +in test B;; +in vdd B;; +in vss B;; +out rw B;; +out W (0 to 1) B;; +out scout B;; +inout data(31 downto 0) X;; +inout data_adr(31 downto 0) X;; + +begin + +<0ns> : 1 1 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 1 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 1 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 1 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; 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+<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; + +end; diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_cpu.pat b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_cpu.pat new file mode 100644 index 00000000..3dbfa785 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_cpu.pat @@ -0,0 +1,1160 @@ +in ck B;; +in reset B;; +in frz B;; +in scin B;; +in test B;; +in vdd B;; +in vss B;; +out rw B;; +out W (0 to 1) B;; +out scout B;; +inout data(31 downto 0) X;; +inout data_adr(31 downto 0) X;; + +signal mips1.adr_c (31 downto 0) X SPY TRACE;; +signal mips1.datain_c (31 downto 0) X SPY TRACE;; +signal mips1.dataout_c(31 downto 0) X SPY TRACE;; +signal mips1.int_c ( 5 downto 0) B SPY TRACE;; +signal mips1.scin_c B SPY TRACE;; +signal mips1.scout_c B SPY TRACE;; +signal mips1.test_c B SPY TRACE;; +signal mips1.reset_c B SPY TRACE;; +signal mips1.frz_c B SPY TRACE;; +signal mips1.w_c (0 to 1) B SPY TRACE;; +signal mips1.rw_c B SPY TRACE;; +signal mips1.berr_c B SPY TRACE;; +signal mips1.rw_ctl_c (15 downto 0) B SPY TRACE;; +signal mips1.frz_ctl_c(15 downto 0) B SPY TRACE;; +signal mips1.ck_ctl_c B SPY TRACE;; +signal mips1.ck_dpt_c B SPY TRACE;; + +begin + +< 0ns> : 1 1 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 1 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 1 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 1 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 1 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 1 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 1 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 1 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 1 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 1 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; 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+<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 0 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; +<+50ns>: 1 0 0 0 0 1 0 * ** * ******** ********; + +end; diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_cpu.vst b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_cpu.vst new file mode 100644 index 00000000..13400692 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_cpu.vst @@ -0,0 +1,261 @@ +-- ### -------------------------------------------------------------- ### +-- # # +-- # file : mips_cpu.vst # +-- # date : september 25 1996 # +-- # version : v0.2 # +-- # author : fahim RAHIM # +-- # descr. : mips cpu board with on board ram (512 bytes), rom # +-- # (512 bytes = 128 instructions) and, timer # +-- # # +-- ### -------------------------------------------------------------- ### + +entity mips_cpu is + port ( + CK : in bit ; + TEST : in bit ; + SCIN : in bit ; + SCOUT : out bit ; + RESET : in bit ; + FRZ : in bit ; + RW : inout bit ; + W : inout bit_vector ( 0 to 1) ; + DATA : inout mux_vector (31 downto 0) bus; + DATA_ADR : inout mux_vector (31 downto 0) bus; + VDD : in bit ; + VSS : in bit + ); + +end mips_cpu; + +architecture structral of mips_cpu is + + signal E_RAMU_N : bit_vector ( 0 to 3) ; + signal E_RAMS_N : bit_vector ( 0 to 3) ; + signal E_ROMU_N : bit ; + signal E_ROMS_N : bit ; + signal E_TIME_N : bit ; + signal E_ROMR_N : bit ; + signal E_ROME_N : bit ; + + signal rst : bit ; + signal berr : bit ; + signal IRQ_N : bit_vector( 5 downto 0) ; + + component mips_chip + port ( + CK : in bit ; + RESET : in bit ; + FRZ : in bit ; + INT : in bit_vector ( 5 downto 0) ; + DATA : inout mux_vector (31 downto 0) bus ; + W : out bit_vector ( 0 to 1) ; + RW : out bit ; + ADR : out mux_vector (31 downto 0) bus ; + SCIN : in bit ; + BERR : in bit ; + TEST : in bit ; + SCOUT : out bit ; + VDD : in bit ; + VSS : in bit ; + VDDP : in bit ; + VSSP : in bit + ) ; + end component; + + component mips_dec + port ( + CK : in bit ; + mips_DADR : in bit_vector (31 downto 0) ; + RW : in bit ; + W : in bit_vector ( 0 to 1) ; + berr : out bit ; + SEL_ROMU_N : out bit ; + SEL_RAMU_N : out bit_vector ( 0 to 3) ; + SEL_ROMS_N : out bit ; + SEL_RAMS_N : out bit_vector ( 0 to 3) ; + SEL_TIMER_N : out bit ; + SEL_ROMR_N : OUT BIT ; + SEL_ROME_N : OUT BIT ; + VDD : in bit ; + VSS : in bit + ); + end component; + + component sr64_32a + port ( + E_N : in bit_vector ( 0 to 3) ; + W_N : in bit ; + DAT : inout mux_vector (31 downto 0) bus; + ADR : in bit_vector ( 5 downto 0) ; + VDD : in bit ; + VSS : in bit + ); + end component; + + component romu + port ( + ADDRESS : in bit_vector (5 downto 0) ; + E_N : in bit ; + DATA : out mux_vector (31 downto 0) bus; + VDD : in bit ; + VSS : in bit + ); + end component; + + component roms + port ( + ADDRESS : in bit_vector (5 downto 0) ; + E_N : in bit ; + DATA : out mux_vector (31 downto 0) bus; + VDD : in bit ; + VSS : in bit + ); + end component; + + component romr + port ( + ADDRESS : in bit_vector (5 downto 0) ; + E_N : in bit ; + DATA : out mux_vector (31 downto 0) bus; + VDD : in bit ; + VSS : in bit + ); + end component; + + component rome + port ( + ADDRESS : in bit_vector (5 downto 0) ; + E_N : in bit ; + DATA : out mux_vector (31 downto 0) bus; + VDD : in bit ; + VSS : in bit + ); + end component; + + component timer + port ( + CK : in bit ; -- external clock + FRZ : in bit ; -- freeze + RESET_I : in bit ; -- reset input + SEL : in bit_vector ( 2 downto 0) ; -- register selection + DATA : inout mux_vector (31 downto 0) bus; -- data + RW : in bit ; -- access mode + E_N : in bit ; -- chip enable + RESET_O : out bit ; -- reset output (= TIMER_RESET OR RESET_I) + IRQ_N : out bit_vector(5 downto 0) ; -- interrupt request + VDD : in bit ; -- + VSS : in bit -- + ); + end component; + +begin + + mips1 : mips_chip + port map ( + INT => IRQ_N , + TEST => TEST , + SCIN => SCIN , + SCOUT => SCOUT , + FRZ => FRZ , + RESET => RST , + ADR => DATA_ADR , + W => W , + RW => RW , + CK => CK , + BERR => BERR , + DATA => DATA , + VDDP => VDD , + VSSP => VSS , + VDD => VDD , + VSS => VSS + ); + + mips_dec : mips_dec + port map ( + CK => CK , + MIPS_DADR => DATA_ADR , + RW => RW , + W => W , + berr => berr , + SEL_ROMU_N => E_ROMU_N , + SEL_RAMU_N => E_RAMU_N , + SEL_ROMS_N => E_ROMS_N , + SEL_RAMS_N => E_RAMS_N , + SEL_TIMER_N => E_TIME_N , + SEL_ROMR_N => E_ROMR_N , + SEL_ROME_N => E_ROME_N , + VDD => VDD , + VSS => VSS + ); + + timer : timer + port map ( + CK => CK, + FRZ => VSS, + RESET_I => RESET, + SEL => DATA_ADR(4 downto 2), + DATA => DATA, + RW => RW, + E_N => E_TIME_N, + RESET_O => RST, + IRQ_N => IRQ_N, + VDD => VDD, + VSS => VSS + ); + + ramu : sr64_32a + port map ( + E_N => E_RAMU_N , + W_N => RW , + DAT => DATA , + ADR => DATA_ADR ( 7 downto 2) , + VDD => VDD , + VSS => VSS + ); + + romu : romu + port map ( + ADDRESS => DATA_ADR (7 downto 2) , + E_N => E_ROMU_N , + DATA => DATA , + VDD => VDD , + VSS => VSS + ); + + rams : sr64_32a + port map ( + E_N => E_RAMS_N , + W_N => RW , + DAT => DATA , + ADR => DATA_ADR ( 7 downto 2) , + VDD => VDD , + VSS => VSS + ); + + roms : roms + port map ( + ADDRESS => DATA_ADR (7 downto 2) , + E_N => E_ROMS_N , + DATA => DATA , + VDD => VDD , + VSS => VSS + ); + + romr : romr + port map ( + ADDRESS => DATA_ADR (7 downto 2) , + E_N => E_ROMR_N , + DATA => DATA , + VDD => VDD , + VSS => VSS + ); +rome : rome + port map ( + ADDRESS => DATA_ADR (7 downto 2) , + E_N => E_ROME_N , + DATA => DATA , + VDD => VDD , + VSS => VSS + ); + +end; diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_ctl.lax b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_ctl.lax new file mode 100644 index 00000000..a39d1b27 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_ctl.lax @@ -0,0 +1,4 @@ +#M{2} + +#L{5} + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_ctl.path b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_ctl.path new file mode 100644 index 00000000..016f8629 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_ctl.path @@ -0,0 +1,56 @@ +BEGIN_PATH_REG +sts_sr_s_0_ins +sts_sr_s_1_ins +sts_sr_s_2_ins +sts_sr_s_3_ins +sts_sr_s_4_ins +sts_sr_s_5_ins +sts_sr_s_6_ins +sts_sr_s_7_ins +sts_sr_s_8_ins +sts_sr_s_9_ins +sts_sr_s_10_ins +sts_sr_s_11_ins +sts_sr_s_12_ins +sts_sr_s_13_ins +sts_sr_s_14_ins +sts_sr_s_15_ins +sts_cr_s_0_ins +sts_cr_s_1_ins +sts_cr_s_2_ins +sts_cr_s_3_ins +sts_cr_s_4_ins +sts_cr_s_5_ins +sts_cr_s_6_ins +sts_cr_s_7_ins +sts_cr_s_8_ins +sts_cr_s_9_ins +sts_cr_s_10_ins +sts_cr_s_11_ins +sts_cr_s_12_ins +sts_cr_s_13_ins +sts_cr_s_14_ins +sts_cr_s_15_ins +sts_intrqs_br_r_ins +sts_intrqs_sys_r_ins +sts_ades_r_ins +sts_cpu_r_ins +sts_adel_r_ins +sts_dbe_r_ins +sts_ri_r_ins +sts_ibe_r_ins +sts_ovf_r_ins +seq_mips_seq_ep_0_ins +seq_mips_seq_ep_1_ins +seq_mips_seq_ep_2_ins +seq_mips_seq_ep_3_ins +seq_mips_seq_ep_4_ins +seq_mips_seq_ep_5_ins +seq_mips_seq_ep_6_ins +END_PATH_REG + +BEGIN_CONNECTOR +SCAN_IN scin +SCAN_OUT scout +SCAN_TEST test +END_CONNECTOR diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_ctl.scapin b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_ctl.scapin new file mode 100644 index 00000000..07c112f8 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_ctl.scapin @@ -0,0 +1,49 @@ + BEGIN_MUX + + MUX_MODEL mx2_x2 + MUX_SEL cmd + MUX_INPUT_SEL i1 + MUX_INPUT_NSEL i0 + MUX_VDD vdd + MUX_VSS vss + MUX_OUTPUT q + + END_MUX + + BEGIN_REG + + REG_MODEL sff1_x4 + REG_CLK ck + REG_INPUT i + REG_VDD vdd + REG_VSS vss + REG_OUTPUT q + REG_MUX mx2_x2 + REG_REG_MUX sff2_x4 + + END_REG + + BEGIN_REG_MUX + + REG_MUX_MODEL sff2_x4 + REG_MUX_SEL cmd + REG_MUX_INPUT_SEL i1 + REG_MUX_INPUT_NSEL i0 + REG_MUX_CLK ck + REG_MUX_VDD vdd + REG_MUX_VSS vss + REG_MUX_OUTPUT q + REG_MUX_MUX mx2_x2 + REG_MUX_REG sff1_x4 + + END_REG_MUX + + BEGIN_BUF + + BUF_MODEL buf_x2 + BUF_INPUT i + BUF_VDD vdd + BUF_VSS vss + BUF_OUTPUT q + + END_BUF diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_ctl_nt.vst b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_ctl_nt.vst new file mode 100644 index 00000000..1169b289 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_ctl_nt.vst @@ -0,0 +1,230 @@ +-- VHDL structural description generated from `mips_ctl` +-- date : Fri Oct 31 12:01:00 1997 + + +-- Entity Declaration + +ENTITY mips_ctl IS + PORT ( + ck : in BIT; -- ck + frz : in BIT; -- frz + reset : in BIT; -- reset + scin : in BIT; -- scin + scout : out BIT; -- scout + test : in BIT; -- test + berr : in BIT; -- berr + w : out BIT_VECTOR (0 TO 1); -- w + int : in BIT_VECTOR (5 DOWNTO 0); -- int + rw_ctl : out BIT_VECTOR (15 DOWNTO 0); -- rw_ctl + frz_ctl : out BIT_VECTOR (15 DOWNTO 0); -- frz_ctl + wenable : out BIT_VECTOR (6 DOWNTO 0); -- wenable + rf_aw : out BIT_VECTOR (4 DOWNTO 0); -- rf_aw + rf_ar : out BIT_VECTOR (4 DOWNTO 0); -- rf_ar + ctlopx : out BIT_VECTOR (8 DOWNTO 0); -- ctlopx + ctlopy : out BIT_VECTOR (6 DOWNTO 0); -- ctlopy + ctlalu : out BIT_VECTOR (5 DOWNTO 0); -- ctlalu + ctlrw : out BIT_VECTOR (4 DOWNTO 1); -- ctlrw + ctladr : out BIT; -- ctladr + crsrout : out BIT_VECTOR (15 DOWNTO 0); -- crsrout + alu_31_n : in BIT; -- alu_31_n + alu_1_n : in BIT; -- alu_1_n + alu_0_n : in BIT; -- alu_0_n + adr_1_n : in BIT; -- adr_1_n + adr_0_n : in BIT; -- adr_0_n + crsrin : in BIT_VECTOR (15 DOWNTO 0); -- crsrin + opx_sign : in BIT; -- opx_sign + opy_sign : in BIT; -- opy_sign + codop : in BIT_VECTOR (18 DOWNTO 0); -- codop + rs : in BIT_VECTOR (4 DOWNTO 0); -- rs + rd : in BIT_VECTOR (4 DOWNTO 0); -- rd + rdrt : in BIT_VECTOR (4 DOWNTO 0); -- rdrt + alu_test_n : out BIT; -- alu_test_n + alu_c31_n : in BIT; -- alu_c31_n + alu_c30_n : in BIT; -- alu_c30_n + alu_nul : in BIT; -- alu_nul + alu_sign : in BIT; -- alu_sign + rw : out BIT; -- rw + vdd : in BIT; -- vdd + vss : in BIT -- vss + ); +END mips_ctl; + +-- Architecture Declaration + +ARCHITECTURE structural_view OF mips_ctl IS + COMPONENT mips_seqo + port ( + ck : in BIT; -- ck + frz : in BIT; -- frz + rqs : in BIT; -- rqs + reset : in BIT; -- reset + resnul : in BIT; -- resnul + alu_sign : in BIT; -- alu_sign + ir_opcod : in BIT_VECTOR(18 DOWNTO 0); -- ir_opcod + vdd : in BIT; -- vdd + vss : in BIT; -- vss + scin : in BIT; -- scin + test : in BIT; -- test + itrqs : in BIT; -- itrqs + adrs : in BIT_VECTOR(1 DOWNTO 0); -- adrs + exrqs : in BIT; -- exrqs + ctlopx : out BIT_VECTOR(8 DOWNTO 0); -- ctlopx + ctlopy : out BIT_VECTOR(6 DOWNTO 0); -- ctlopy + ctlalu : out BIT_VECTOR(5 DOWNTO 0); -- ctlalu + wenable : out BIT_VECTOR(10 DOWNTO 0); -- wenable + ctlrw : out BIT_VECTOR(4 DOWNTO 0); -- ctlrw + ctladr : out BIT; -- ctladr + excp : out BIT_VECTOR(6 DOWNTO 0); -- excp + scout : out BIT -- scout + ); + END COMPONENT; + + COMPONENT mips_sts + port ( + ck : in BIT; -- ck + reset : in BIT; -- reset + frz : in BIT; -- frz + test : in BIT; -- test + opx_sign : in BIT; -- opx_sign + opy_sign : in BIT; -- opy_sign + alu_sign : in BIT; -- alu_sign + alu_nul : in BIT; -- alu_nul + alu_c31 : in BIT; -- alu_c31 + alu_c30 : in BIT; -- alu_c30 + ctlalu : in BIT_VECTOR(5 DOWNTO 0); -- ctlalu + rs : in BIT_VECTOR(4 DOWNTO 0); -- rs + rd : in BIT_VECTOR(4 DOWNTO 0); -- rd + rdrt : in BIT_VECTOR(4 DOWNTO 0); -- rdrt + mxrs_rdrt : in BIT; -- mxrs_rdrt + wenable_in : in BIT_VECTOR(10 DOWNTO 0); -- wenable_in + ctlrw_in : in BIT_VECTOR(4 DOWNTO 0); -- ctlrw_in + ctlrw_out : inout BIT_VECTOR(4 DOWNTO 1); -- ctlrw_out + adr0 : in BIT; -- adr0 + adr1 : in BIT; -- adr1 + adr31 : in BIT; -- adr31 + intrqs : in BIT_VECTOR(5 DOWNTO 0); -- intrqs + intrqs_seq : out BIT; -- intrqs_seq + berr_s : in BIT; -- berr_s + scin : in BIT; -- scin + alu_test : out BIT; -- alu_test + redpnt : out BIT_VECTOR(4 DOWNTO 0); -- redpnt + wrtpnt : out BIT_VECTOR(4 DOWNTO 0); -- wrtpnt + wenable_out : out BIT_VECTOR(6 DOWNTO 0); -- wenable_out + crsr_dpt : in BIT_VECTOR(15 DOWNTO 0); -- crsr_dpt + crsr_out : out BIT_VECTOR(15 DOWNTO 0); -- crsr_out + crsr_mx : in BIT; -- crsr_mx + excp : in BIT_VECTOR(6 DOWNTO 0); -- excp + rqs : out BIT; -- rqs + exq : out BIT; -- exq + rw : out BIT; -- rw + rw_ctl : out BIT_VECTOR(15 DOWNTO 0); -- rw_ctl + frz_ctl : out BIT_VECTOR(15 DOWNTO 0); -- frz_ctl + w : out BIT_VECTOR(1 DOWNTO 0); -- w + scout : out BIT; -- scout + vdd : in BIT; -- vdd + vss : in BIT -- vss + ); + END COMPONENT; + + SIGNAL ctlrw_int_0 : BIT; -- ctlrw_int 0 + SIGNAL ctlrw_int_1 : BIT; -- ctlrw_int 1 + SIGNAL ctlrw_int_2 : BIT; -- ctlrw_int 2 + SIGNAL ctlrw_int_3 : BIT; -- ctlrw_int 3 + SIGNAL ctlrw_int_4 : BIT; -- ctlrw_int 4 + SIGNAL excp_0 : BIT; -- excp 0 + SIGNAL excp_1 : BIT; -- excp 1 + SIGNAL excp_2 : BIT; -- excp 2 + SIGNAL excp_3 : BIT; -- excp 3 + SIGNAL excp_4 : BIT; -- excp 4 + SIGNAL excp_5 : BIT; -- excp 5 + SIGNAL excp_6 : BIT; -- excp 6 + SIGNAL exq : BIT; -- exq + SIGNAL intrqs : BIT; -- intrqs + SIGNAL rqs : BIT; -- rqs + SIGNAL scan : BIT; -- scan + SIGNAL wenable_int_0 : BIT; -- wenable_int 0 + SIGNAL wenable_int_1 : BIT; -- wenable_int 1 + SIGNAL wenable_int_2 : BIT; -- wenable_int 2 + SIGNAL wenable_int_3 : BIT; -- wenable_int 3 + SIGNAL wenable_int_4 : BIT; -- wenable_int 4 + SIGNAL wenable_int_5 : BIT; -- wenable_int 5 + SIGNAL wenable_int_6 : BIT; -- wenable_int 6 + SIGNAL wenable_int_7 : BIT; -- wenable_int 7 + SIGNAL wenable_int_8 : BIT; -- wenable_int 8 + SIGNAL wenable_int_9 : BIT; -- wenable_int 9 + SIGNAL wenable_int_10 : BIT; -- wenable_int 10 + +BEGIN + + seq : mips_seqo + PORT MAP ( + scout => scan, + excp => excp_6& excp_5& excp_4& excp_3& excp_2& excp_1& excp_0, + ctladr => ctladr, + ctlrw => ctlrw_int_4& ctlrw_int_3& ctlrw_int_2& ctlrw_int_1& ctlrw_int_0, + wenable => wenable_int_10& wenable_int_9& wenable_int_8& wenable_int_7& wenable_int_6& wenable_int_5& wenable_int_4& wenable_int_3& wenable_int_2& wenable_int_1& wenable_int_0, + ctlalu => ctlalu(5)& ctlalu(4)& ctlalu(3)& ctlalu(2)& ctlalu(1)& ctlalu(0), + ctlopy => ctlopy(6)& ctlopy(5)& ctlopy(4)& ctlopy(3)& ctlopy(2)& ctlopy(1)& ctlopy(0), + ctlopx => ctlopx(8)& ctlopx(7)& ctlopx(6)& ctlopx(5)& ctlopx(4)& ctlopx(3)& ctlopx(2)& ctlopx(1)& ctlopx(0), + exrqs => exq, + adrs => adr_1_n& adr_0_n, + itrqs => intrqs, + test => test, + scin => scin, + vss => vss, + vdd => vdd, + ir_opcod => codop(18)& codop(17)& codop(16)& codop(15)& codop(14)& codop(13)& codop(12)& codop(11)& codop(10)& codop(9)& codop(8)& codop(7)& codop(6)& codop(5)& codop(4)& codop(3)& codop(2)& codop(1)& codop(0), + alu_sign => alu_sign, + resnul => alu_nul, + reset => reset, + rqs => rqs, + frz => frz, + ck => ck); + + + sts : mips_sts + PORT MAP ( + vss => vss, + vdd => vdd, + scout => scout, + w => w(1)& w(0), + frz_ctl => frz_ctl(15)& frz_ctl(14)& frz_ctl(13)& frz_ctl(12)& frz_ctl(11)& frz_ctl(10)& frz_ctl(9)& frz_ctl(8)& frz_ctl(7)& frz_ctl(6)& frz_ctl(5)& frz_ctl(4)& frz_ctl(3)& frz_ctl(2)& frz_ctl(1)& frz_ctl(0), + rw_ctl => rw_ctl(15)& rw_ctl(14)& rw_ctl(13)& rw_ctl(12)& rw_ctl(11)& rw_ctl(10)& rw_ctl(9)& rw_ctl(8)& rw_ctl(7)& rw_ctl(6)& rw_ctl(5)& rw_ctl(4)& rw_ctl(3)& rw_ctl(2)& rw_ctl(1)& rw_ctl(0), + rw => rw, + reset => reset, + exq => exq, + rqs => rqs, + excp => excp_6& excp_5& excp_4& excp_3& excp_2& excp_1& excp_0, + crsr_mx => ctlopx(0), + crsr_out => crsrout(15)& crsrout(14)& crsrout(13)& crsrout(12)& crsrout(11)& crsrout(10)& crsrout(9)& crsrout(8)& crsrout(7)& crsrout(6)& crsrout(5)& crsrout(4)& crsrout(3)& crsrout(2)& crsrout(1)& crsrout(0), + crsr_dpt => crsrin(15)& crsrin(14)& crsrin(13)& crsrin(12)& crsrin(11)& crsrin(10)& crsrin(9)& crsrin(8)& crsrin(7)& crsrin(6)& crsrin(5)& crsrin(4)& crsrin(3)& crsrin(2)& crsrin(1)& crsrin(0), + wenable_out => wenable(6)& wenable(5)& wenable(4)& wenable(3)& wenable(2)& wenable(1)& wenable(0), + wrtpnt => rf_aw(4)& rf_aw(3)& rf_aw(2)& rf_aw(1)& rf_aw(0), + redpnt => rf_ar(4)& rf_ar(3)& rf_ar(2)& rf_ar(1)& rf_ar(0), + alu_test => alu_test_n, + scin => scan, + berr_s => berr, + intrqs_seq => intrqs, + intrqs => int(5)& int(4)& int(3)& int(2)& int(1)& int(0), + adr31 => alu_31_n, + adr1 => alu_1_n, + adr0 => alu_0_n, + ctlrw_out => ctlrw(4)& ctlrw(3)& ctlrw(2)& ctlrw(1), + ctlrw_in => ctlrw_int_4& ctlrw_int_3& ctlrw_int_2& ctlrw_int_1& ctlrw_int_0, + wenable_in => wenable_int_10& wenable_int_9& wenable_int_8& wenable_int_7& wenable_int_6& wenable_int_5& wenable_int_4& wenable_int_3& wenable_int_2& wenable_int_1& wenable_int_0, + mxrs_rdrt => ctlopx(0), + rdrt => rdrt(4)& rdrt(3)& rdrt(2)& rdrt(1)& rdrt(0), + rd => rd(4)& rd(3)& rd(2)& rd(1)& rd(0), + rs => rs(4)& rs(3)& rs(2)& rs(1)& rs(0), + ctlalu => ctlalu(5)& ctlalu(4)& ctlalu(3)& ctlalu(2)& ctlalu(1)& ctlalu(0), + alu_c30 => alu_c30_n, + alu_c31 => alu_c31_n, + alu_nul => alu_nul, + alu_sign => alu_sign, + opy_sign => opy_sign, + opx_sign => opx_sign, + test => test, + frz => frz, + ck => ck); + +end structural_view; diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_dec.vbe b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_dec.vbe new file mode 100644 index 00000000..cf385fe5 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_dec.vbe @@ -0,0 +1,232 @@ +-- ### -------------------------------------------------------------- ### +-- # # +-- # file : mips_dec.vbe # +-- # date : Mar 29 1993 # +-- # version : v0.1 # +-- # author : Pirouz BAZARGAN SABET # +-- # modif : Thu Oct 31 12:26:31 WET 1996 # +-- # descr. : data flow description of an address decoder for DLXp. # +-- # # +-- ### -------------------------------------------------------------- ### + +entity mips_dec is + +port ( + ck : in bit ; -- external clock + mips_dadr : in bit_vector (31 downto 0) ; -- data address + rw : in bit ; -- read write + W : in bit_vector ( 0 to 1) ; -- valid bytes + berr : out bit ; -- Bus Error (activ low) + sel_romu_n : out bit ; -- user rom + sel_ramu_n : out bit_vector ( 0 to 3) ; -- user ram + sel_roms_n : out bit ; -- system rom + sel_rams_n : out bit_vector ( 0 to 3) ; -- system ram + sel_timer_n : out bit ; -- timer + sel_rome_n : out bit ; + sel_romr_n : out bit ; + vdd : in bit ; -- + vss : in bit -- + ); + +end mips_dec; + +architecture FUNCTIONAL of mips_dec is + + signal notCk : bit ; + + signal rams : bit ; -- select system ram + signal ramu : bit ; -- select user ram + signal roms : bit ; -- select system rom + signal romu : bit ; -- select user rom + signal romr : bit ; + signal rome : bit ; + signal timer : bit ; -- select system timer + signal dly0_ck : bit ; -- delayed clock + signal dly1_ck : bit ; -- delayed clock + signal dly2_ck : bit ; -- delayed clock + signal dly3_ck : bit ; -- delayed clock + signal dly4_ck : bit ; -- delayed clock + signal dly5_ck : bit ; -- delayed clock + signal dlyd_ck : bit ; -- delayed clock + + signal bad_cry : bit_vector ( 3 downto 0) ; -- adder's carry + signal bad_add : bit_vector ( 2 downto 0) ; -- bad counter's adder + signal bad_in : bit_vector ( 2 downto 0) ; -- bad counter's adder + signal bad_cnt : reg_vector ( 2 downto 0) register; -- bad address counter + signal good_cry : bit_vector ( 3 downto 0) ; -- adder's carry + signal good_add : bit_vector ( 2 downto 0) ; -- good counter's adder + signal good_in : bit_vector ( 2 downto 0) ; -- good counter's adder + signal good_cnt : reg_vector ( 2 downto 0) register; -- good address counter + + constant RST : bit_vector (31 downto 0) := X"BFC00000"; -- reset address + constant BAD : bit_vector (31 downto 0) := X"004000D8"; -- bad address + constant GOOD : bit_vector (31 downto 0) := X"004000D0"; -- good address + constant BUSERR : bit_vector (31 downto 0) := X"400000C8"; -- berr address + signal byte : bit_vector(3 downto 0); +begin + + notCk <= NOT(ck) ; + + dly0_ck <= notCk; + dly1_ck <= dly0_ck; + dly2_ck <= dly1_ck; + dly3_ck <= dly2_ck; + dly4_ck <= dly3_ck; + dly5_ck <= dly4_ck; + dlyd_ck <= dly5_ck; + + -- ### ------------------------------------------------------ ### + -- # select on board user/system ram-rom depending on data # + -- # addresses : # + -- # # + -- # 0000_0000 - user ram # + -- # 0000_00FF - user ram # + -- # # + -- # 0000_0100 - off board ram extension # + -- # 7FFF_FEFF - off board ram extension # + -- # # + -- # 0040_0000 - user rom # + -- # 0040_00FF - user rom # + -- # # + -- # 8000_0000 - system ram # + -- # 8000_00FF - system ram # + -- # # + -- # 4000_00C8 - Bus Error... # + -- # # + -- # 4000_0100 - system timer # + -- # 4000_011F - system timer # + -- # # + -- # 8000_0200 - off board ram extension # + -- # FFFF_FFFF - off board ram extension # + -- # # + -- # 8000_0000 - system rom # + -- # 8000_00FF - system rom # + -- # # + -- # BFC0_0000 - reset rom # + -- # BFC0_00FF - reset rom # + -- # # + -- # 8000_0080 - exception rom # + -- # 8000_017F - exception rom # + -- ### ------------------------------------------------------ ### + + with mips_dadr (31 downto 8) select + romu <= '1' when X"0040_00", + '0' when others; + + with mips_dadr (31 downto 7) select + roms <= '1' when B"1000_0000_0000_0000_0000_0000_0", + '0' when others; + + with mips_dadr (31 downto 8) select + romr <= '1' when X"bfc0_00", + '0' when others; + + with mips_dadr (31 downto 7) select + rome <= '1' when B"1000_0000_0000_0000_0000_0000_1", + '0' when others; + with mips_dadr (31 downto 8) select + ramu <= '1' when X"4000_00", + '0' when others; + with mips_dadr (31 downto 8) select + rams <= '1' when X"c000_00", + '0' when others; + + with mips_dadr (31 downto 5) select + timer <= '1' when B"0100_0000_0000_0000_0000_0001_000", + '0' when others; + + berr <= '0' when (mips_dadr = BUSERR) else '1'; + + -- ### ------------------------------------------------------ ### + -- # assign outputs # + -- # - effective selection of ram chips (on high level of # + -- # clock to avoid conflicts) # + -- # - effective selection of rom chips # + -- # - effective selection of timer # + -- ### ------------------------------------------------------ ### + + byte <= B"1111" when (W = "11" and not(rw)) ELSE + B"1100" when (W = "10" and not(rw) and mips_dadr(1) = '0') ELSE + B"0011" when (W = "10" and not(rw) and mips_dadr(1) = '1') ELSE + B"1000" when (W = "01" and not(rw) and mips_dadr(1) = '0' and mips_dadr(0) ='0') ELSE + B"0100" when (W = "01" and not(rw) and mips_dadr(1) = '0' and mips_dadr(0) ='1') ELSE + B"0010" when (W = "01" and not(rw) and mips_dadr(1) = '1' and mips_dadr(0) ='0') ELSE + B"0001" when (W = "01" and not(rw) and mips_dadr(1) = '1' and mips_dadr(0) = '1') ELSE + B"1111" when (rw = '1') ELSE + B"0000"; + + + sel_ramu_n (0) <= not (ramu and notCk and byte (0)); + sel_ramu_n (1) <= not (ramu and notCk and byte (1)); + sel_ramu_n (2) <= not (ramu and notCk and byte (2)); + sel_ramu_n (3) <= not (ramu and notCk and byte (3)); + + sel_rams_n (0) <= not (rams and notCk and byte (0)); + sel_rams_n (1) <= not (rams and notCk and byte (1)); + sel_rams_n (2) <= not (rams and notCk and byte (2)); + sel_rams_n (3) <= not (rams and notCk and byte (3)); + + sel_timer_n <= not (timer); -- and ck); + assert (timer) + report "==== timer enabled ====" + severity WARNING; + + +-- sel_romu_n <= not (romu and notCk); +-- sel_roms_n <= not (roms and notCk); +-- sel_romr_n <= not (romr and notCk); +-- sel_rome_n <= not (rome and notCk); + + sel_romu_n <= not (romu ); + sel_roms_n <= not (roms ); + sel_romr_n <= not (romr ); + sel_rome_n <= not (rome ); + + -- ### ------------------------------------------------------ ### + -- # watching the address bus to detect the fetch of the # + -- # GOOD or the BAD address (simulation aborts when the # + -- # instruction has been fetched 3 times) # + -- ### ------------------------------------------------------ ### + + bad_cry (0) <= '1'; + bad_cry (3 downto 1) <= bad_cnt and bad_cry (2 downto 0); + bad_add <= bad_cnt xor bad_cry (2 downto 0); + + good_cry (0) <= '1'; + good_cry (3 downto 1) <= good_cnt and good_cry (2 downto 0); + good_add <= good_cnt xor good_cry (2 downto 0); + + -- bad : block (notCk = '0' and not notCk'STABLE and rw = '1' and byte = "1111") + with ((mips_dadr = BAD) & (mips_dadr = RST)) select + bad_in <= bad_add when B"10", + B"000" when B"01" | B"11", + bad_cnt when others; + + with ((mips_dadr = GOOD) & (mips_dadr = RST)) select + good_in <= good_add when B"10", + B"000" when B"01" | B"11", + good_cnt when others; + + bad : block (notCk = '0' and not notCk'STABLE and rw = '1') + begin + bad_cnt <= guarded bad_in; + good_cnt <= guarded good_in; + end block; + + assert (not (bad_cnt = "011")) + report "==== functional test bad ====" + severity ERROR; + + assert (not (good_cnt = "011")) + report "==== functional test good ====" + severity ERROR; + + assert (not (mips_dadr = X"BFC00000")) + report "==== reset occured ====" + severity WARNING; + + assert (not (mips_dadr = X"80000080")) + report "==== exception occured ====" + severity WARNING; + +end FUNCTIONAL; diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_dpt.c b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_dpt.c new file mode 100644 index 00000000..d83d3d93 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_dpt.c @@ -0,0 +1,1215 @@ +# include +# include +# define POWER "vdd", "vss", NULL + +extern int main() +{ + + int i; + + /*************Définition des MACROS**************************/ + + GENLIB_MACRO(DPGEN_INV, "model_inv_32", F_PLACE, 32, 1); + GENLIB_MACRO(DPGEN_MUX2, "model_mux2_32", F_PLACE, 32, 2); + GENLIB_MACRO(DPGEN_NMUX2, "model_nmux2_32", F_PLACE, 32); + GENLIB_MACRO(DPGEN_NBUSE, "model_nbuse_32", F_PLACE, 32); + GENLIB_MACRO(DPGEN_BUSE, "model_buse_32", F_PLACE, 32,4); + + GENLIB_MACRO(DPGEN_BUFF, "model_buff_32", F_PLACE, 32, 2); + GENLIB_MACRO(DPGEN_BUFF, "model_buff_27", F_PLACE, 27, 2); + GENLIB_MACRO(DPGEN_BUFF, "model_buff_26", F_PLACE, 26, 2); + GENLIB_MACRO(DPGEN_BUFF, "model_buff_19", F_PLACE, 19, 2); + GENLIB_MACRO(DPGEN_BUFF, "model_buff_16", F_PLACE, 16, 2); + GENLIB_MACRO(DPGEN_BUFF, "model_buff_14", F_PLACE, 14, 2); + GENLIB_MACRO(DPGEN_BUFF, "model_buff_5", F_PLACE, 5, 2); + GENLIB_MACRO(DPGEN_BUFF, "model_buff_4", F_PLACE, 4, 2); + GENLIB_MACRO(DPGEN_BUFF, "model_buff_2", F_PLACE, 2, 2); + + GENLIB_MACRO(DPGEN_CONST, "model_0_0000", F_PLACE, 16, "0x0000"); + GENLIB_MACRO(DPGEN_CONST, "model_0_00000000", F_PLACE, 32, "0x00000000"); + GENLIB_MACRO(DPGEN_CONST, "model_0_0000FFFF", F_PLACE, 32, "0x0000FFFF"); + GENLIB_MACRO(DPGEN_CONST, "model_0_BFC00000", F_PLACE, 32, "0xBFC00000"); + + GENLIB_MACRO(DPGEN_ROM2, "model_opx_its5", F_PLACE, 32, "0xFFFFFFFF", "0x7FFFFF7F"); + GENLIB_MACRO(DPGEN_ROM2, "model_shamt", F_PLACE, 27, "000000000000000000000000000", "111111111111111111111111111"); + GENLIB_MACRO(DPGEN_ROM2, "model_ir16", F_PLACE, 16, "0X0000", "0xFFFF"); + GENLIB_MACRO(DPGEN_ROM2, "model_ir18", F_PLACE, 14, "00000000000000", "11111111111111"); + GENLIB_MACRO(DPGEN_ROM2, "model_opy_its6", F_PLACE, 32, "0xFFFFFFF7", "0xFFFFFFE7"); + GENLIB_MACRO(DPGEN_ROM2, "model_opy_its4", F_PLACE, 32, "0xFFFFFFFB", "0xFFFFFFEF"); + + GENLIB_MACRO(DPGEN_NUL, "model_nul", F_PLACE, 32); + + GENLIB_MACRO(DPGEN_SHIFT, "model_shift", F_PLACE, 32); + + GENLIB_MACRO(DPGEN_RF1DR0,"model_banc_reg", F_PLACE, 32, 32); + GENLIB_MACRO(DPGEN_SFFT, "model_sfft", F_PLACE, 32); + + GENLIB_MACRO(DPGEN_AND2, "model_and2_32", F_PLACE, 32, 2); + GENLIB_MACRO(DPGEN_NOR2, "model_nor2_32", F_PLACE, 32, 1); + GENLIB_MACRO(DPGEN_OR2, "model_or2_32", F_PLACE, 32, 2); + GENLIB_MACRO(DPGEN_XOR2, "model_xor2_32", F_PLACE, 32, 1); + GENLIB_MACRO(DPGEN_XNOR2, "model_xnor2_32", F_PLACE, 32, 1); + + GENLIB_MACRO(DPGEN_ADSB2F, "model_addition_32", F_PLACE, 32); + + + + + /************FIN définition des MACROS***********************/ + + GENLIB_DEF_LOFIG("mips_dpt"); + + /**************Définition de l'interface*********************/ + + /* Déclaration des signaux d'alimentation */ + GENLIB_LOCON("vdd", IN, "vdd"); + GENLIB_LOCON("vss", IN, "vss"); + + /* Ajout du scanpath */ + GENLIB_LOCON("test", IN, "test"); + GENLIB_LOCON("dpt_scin", IN, "dpt_scin"); + GENLIB_LOCON("dpt_scout", OUT, "dpt_scout"); + + /* Définition du signal d'horloge*/ + GENLIB_LOCON("ck", IN, "ck"); + + /* Signaux de commandes d'écriture dans les registres */ + GENLIB_LOCON("pc_wen", IN, "pc_wen"); + GENLIB_LOCON("ad_wen", IN, "ad_wen"); + GENLIB_LOCON("epc_wen", IN, "epc_wen"); + GENLIB_LOCON("bar_wen", IN, "bar_wen"); + GENLIB_LOCON("ir_wen", IN, "ir_wen"); + GENLIB_LOCON("dt_wen", IN, "dt_wen"); + GENLIB_LOCON("hi_wen", IN, "hi_wen"); + GENLIB_LOCON("lo_wen", IN, "lo_wen"); + GENLIB_LOCON("rf_wen", IN, "rf_wen"); + GENLIB_LOCON("rf_aw[4:0]", IN, "rf_aw[4:0]"); + GENLIB_LOCON("rf_ar[4:0]", IN, "rf_ar[4:0]"); + + /* Autorisation d'écriture sur le bus X */ + GENLIB_LOCON("opx_ts7", IN, "opx_ts7"); + GENLIB_LOCON("opx_ts6", IN, "opx_ts6"); + GENLIB_LOCON("opx_ts5", IN, "opx_ts5"); + GENLIB_LOCON("opx_ts4", IN, "opx_ts4"); + GENLIB_LOCON("opx_ts3", IN, "opx_ts3"); + GENLIB_LOCON("opx_ts2", IN, "opx_ts2"); + GENLIB_LOCON("opx_ts1", IN, "opx_ts1"); + GENLIB_LOCON("opx_ts0", IN, "opx_ts0"); + + GENLIB_LOCON("opx_mx7", IN, "opx_mx7"); + GENLIB_LOCON("opx_mx6", IN, "opx_mx6"); + GENLIB_LOCON("opx_mx5", IN, "opx_mx5"); + GENLIB_LOCON("opx_mx4", IN, "opx_mx4"); + GENLIB_LOCON("opx_mx3", IN, "opx_mx3"); + GENLIB_LOCON("opx_mx2", IN, "opx_mx2"); + GENLIB_LOCON("opx_mx1", IN, "opx_mx1"); + + /* Signe de l'opérande X */ + GENLIB_LOCON("opx_sign", OUT, "opx_sign"); + + /* Signaux d'indication */ + GENLIB_LOCON("crsr_dpt_out[15:0]", OUT, "crsr_dpt_out[15:0]"); + + /* Signaux de commandes */ + GENLIB_LOCON("crsr_sts_in[15:0]", IN, "crsr_sts_in[15:0]"); + + /* Autorisation d'écriture sur le bus Y */ + GENLIB_LOCON("opy_ts6", IN, "opy_ts6"); + GENLIB_LOCON("opy_ts5", IN, "opy_ts5"); + GENLIB_LOCON("opy_ts4", IN, "opy_ts4"); + GENLIB_LOCON("opy_ts3", IN, "opy_ts3"); + GENLIB_LOCON("opy_ts2", IN, "opy_ts2"); + GENLIB_LOCON("opy_ts1", IN, "opy_ts1"); + + GENLIB_LOCON("opy_mx6", IN, "opy_mx6"); + GENLIB_LOCON("opy_mx5", IN, "opy_mx5"); + GENLIB_LOCON("opy_mx4", IN, "opy_mx4"); + GENLIB_LOCON("opy_mx3", IN, "opy_mx3"); + GENLIB_LOCON("opy_mx2", IN, "opy_mx2"); + GENLIB_LOCON("opy_mx1", IN, "opy_mx1"); + + GENLIB_LOCON("opy_codop[18:0]", OUT, "opy_codop[18:0]"); + GENLIB_LOCON("opy_rs[4:0]", OUT, "opy_rs[4:0]"); + GENLIB_LOCON("opy_rdrt[4:0]", OUT, "opy_rdrt[4:0]"); + GENLIB_LOCON("opy_rd[4:0]", OUT, "opy_rd[4:0]"); + GENLIB_LOCON("opy_sign", OUT, "opy_sign"); + + /* Données en entrée */ + GENLIB_LOCON("data_in_dpt[31:0]", IN, "data_in_dpt[31:0]"); + + /* Données en sortie */ + GENLIB_LOCON("data_out_dpt[31:0]", OUT, "data_out_dpt[31:0]"); + + /* Commandes des multiplexeurs de l'ALU */ + GENLIB_LOCON("alu_mx5i0", IN, "alu_mx5i0"); + GENLIB_LOCON("alu_mx4i0", IN, "alu_mx4i0"); + GENLIB_LOCON("alu_mx3i0", IN, "alu_mx3i0"); + GENLIB_LOCON("alu_mx2i0", IN, "alu_mx2i0"); + GENLIB_LOCON("alu_mx2i1", IN, "alu_mx2i1"); + GENLIB_LOCON("alu_mx1i2", IN, "alu_mx1i2"); + GENLIB_LOCON("alu_mx1i1", IN, "alu_mx1i1"); + GENLIB_LOCON("alu_mx1i0", IN, "alu_mx1i0"); + GENLIB_LOCON("alu_mx0i0", IN, "alu_mx0i0"); + + /* Signaux de l'ALU */ + GENLIB_LOCON("alu_byte", IN, "alu_byte"); + GENLIB_LOCON("alu_half", IN, "alu_half"); + GENLIB_LOCON("alu_test_n", IN, "alu_test_n"); + GENLIB_LOCON("alu_c31", OUT, "alu_c31"); + GENLIB_LOCON("alu_c30", OUT, "alu_c30"); + GENLIB_LOCON("alu_nul", OUT, "alu_nul"); + GENLIB_LOCON("alu_sign", OUT, "alu_sign"); + GENLIB_LOCON("alu_n_31", INOUT, "alu_n_31"); + GENLIB_LOCON("alu_n_1", INOUT, "alu_n_1"); + GENLIB_LOCON("alu_n_0", INOUT, "alu_n_0"); + GENLIB_LOCON("adr_n_1", INOUT, "adr_n_1"); + GENLIB_LOCON("adr_n_0", INOUT, "adr_n_0"); + + /* Commande de selection entre adresse PC et adresse memoire */ + GENLIB_LOCON("out_mx0i0", IN, "out_mx0i0"); + + /* Adresse en sortie */ + GENLIB_LOCON("out_adr[31:0]", OUT, "out_adr[31:0]"); + + /**********FIN de la définition de l'interface*****************/ + + + + + /*****************Implémentation du DATA-PATH******************/ + + /***************** Description de l'opérande de X ****************/ + /* Affectation de la valeur du registre sélectionné sur le bus X */ + GENLIB_LOINS("model_buff_32","buff_opx_ots", + "opx_ots[31:0]", + "opx_out[31:0]", + POWER); + + /* Récupération du signe du signal opx_out dans dans opx_sign*/ + GENLIB_LOINS("buf_x2","buff_opx_sign", + "opx_out[31]", + "opx_sign", + POWER); + + + /* Création de pc4 */ + + GENLIB_LOINS("model_0_00000000", + "ox00000000pc4", + "pc4_zero[31:0]", + POWER); + + GENLIB_LOINS("model_buff_32","buff_pc4", + "pc[31:28]", + "pc4_zero[27:0]", + "pc4[31:0]", + POWER); + + /* + * Descriptions des MUX de X + */ + GENLIB_LOINS("model_0_0000FFFF","ox0000FFFF", + "const_0x0000FFFF[31:0]", + POWER); + + GENLIB_LOINS("model_nmux2_32", "nmux2_32_7", + "opx_mx7", + "pc4_zero[31:0]", "pc4[31:0]", + "opx_its7[31:0]", + POWER); + + GENLIB_LOINS("model_nmux2_32", "nmux2_32_6", + "opx_mx6", + "const_0x0000FFFF[31:0]", "dt[31:0]", + "opx_its6[31:0]", + POWER); + + GENLIB_LOINS("model_opx_its5", "mux2_32_5", + "opx_mx5", + "opx_its5[31:0]", + POWER); + + GENLIB_LOINS("model_nmux2_32", "nmux2_32_4", + "opx_mx4", + "epc[31:0]", "bar[31:0]", + "opx_its4[31:0]", + POWER); + + GENLIB_LOINS("model_nmux2_32", "nmux2_32_3", + "opx_mx3", + "cr_s[31:0]", "sr_s[31:0]", + "opx_its3[31:0]", + POWER); + + GENLIB_LOINS("model_nmux2_32", "nmux2_32_2", + "opx_mx2", + "lo[31:0]", "hi[31:0]", + "opx_its2[31:0]", + POWER); + + GENLIB_LOINS("model_nmux2_32", "nmux2_32_1", + "opx_mx1", + "ad[31:0]", "pc[31:0]", + "opx_its1[31:0]", + POWER); + + /* + * Définition des signaux TRI STATE de X + */ + GENLIB_LOINS("model_nbuse_32", "nbuse_32_7", + "opx_ts7", + "opx_its7[31:0]", + "opx_ots[31:0]", + POWER); + + GENLIB_LOINS("model_nbuse_32", "nbuse_32_6", + "opx_ts6", + "opx_its6[31:0]", + "opx_ots[31:0]", + POWER); + + GENLIB_LOINS("model_nbuse_32", "nbuse_32_5", + "opx_ts5", + "opx_its5[31:0]", + "opx_ots[31:0]", + POWER); + + GENLIB_LOINS("model_nbuse_32", "nbuse_32_4", + "opx_ts4", + "opx_its4[31:0]", + "opx_ots[31:0]", + POWER); + + GENLIB_LOINS("model_nbuse_32", "nbuse_32_3", + "opx_ts3", + "opx_its3[31:0]", + "opx_ots[31:0]", + POWER); + + GENLIB_LOINS("model_nbuse_32", "nbuse_32_2", + "opx_ts2", + "opx_its2[31:0]", + "opx_ots[31:0]", + POWER); + + GENLIB_LOINS("model_nbuse_32", "nbuse_32_1", + "opx_ts1", + "opx_its1[31:0]", + "opx_ots[31:0]", + POWER); + + GENLIB_LOINS("model_buse_32" , "buse_32_0" , + "opx_ts0", + "rf_o[31:0]", + "opx_ots[31:0]", + POWER); + + + + /**********************Description des opérandes Y*********************/ + + /* Chargement du code opération dans opy_codop à partir du registre ir */ + GENLIB_LOINS("model_buff_19", "buff_19_opy_codop", + "ir[31:25]", "ir[23]", "ir[13:11]", "ir[16]", "ir[20]", "ir[5:0]", + "opy_codop[18:0]", + POWER); + + /* Affectation de la valeur au signal opy_rs*/ + GENLIB_LOINS("model_buff_5", "buff_5_opy_rs", + "ir[25:21]", + "opy_rs[4:0]", + POWER); + + /* Affectation de la valeur au signal opy_rdrt*/ + GENLIB_LOINS("model_buff_5", "buff_5_opy_rdrt", + "ir[20:16]", + "opy_rdrt[4:0]", + POWER); + + /* Affectation de la valeur au signal opy_rd*/ + GENLIB_LOINS("model_buff_5", "buff_5_opy_rd", + "ir[15:11]", + "opy_rd[4:0]", + POWER); + + /* Affectation de la valeur au signal opy_shamt*/ + GENLIB_LOINS("model_buff_5", "buff_5_opy_shamt", + "ir[10:6]", + "opy_shamt[4:0]", + POWER); + GENLIB_LOINS("model_buff_27", "buff_27_shamt", + "ir[10]","ir[10]","ir[10]","ir[10]","ir[10]","ir[10]","ir[10]","ir[10]","ir[10]","ir[10]","ir[10]","ir[10]","ir[10]","ir[10]","ir[10]","ir[10]","ir[10]","ir[10]","ir[10]","ir[10]","ir[10]","ir[10]","ir[10]","ir[10]","ir[10]","ir[10]","ir[10]", + "opy_shamt[31:5]", + POWER); + + /* Affectation de la valeur au signal opy_ir16 */ + GENLIB_LOINS("model_buff_16", "buff_16_opy_ir16", + "ir[15:0]", + "opy_ir16[15:0]", + POWER); + GENLIB_LOINS("model_buff_16", "buff_16_opy_ir16_2", + "ir[15]","ir[15]","ir[15]","ir[15]","ir[15]","ir[15]","ir[15]","ir[15]","ir[15]","ir[15]","ir[15]","ir[15]","ir[15]","ir[15]","ir[15]","ir[15]", + "opy_ir16[31:16]", + POWER); + + /* Affectation de la valeur au signal opy_ir18 */ + GENLIB_LOINS("model_buff_2","buff_2_opy_ir18", + "const_0x00000000[1:0]", + "opy_ir18[1:0]", + POWER); + GENLIB_LOINS("model_buff_16","buff_16_opy_ir18", + "ir[15:0]", + "opy_ir18[17:2]", + POWER); + GENLIB_LOINS("model_buff_14", "buff_14_opy_ir18", + "ir[15]","ir[15]","ir[15]","ir[15]","ir[15]","ir[15]","ir[15]","ir[15]","ir[15]","ir[15]","ir[15]","ir[15]","ir[15]","ir[15]", + "opy_ir18[31:18]", + POWER); + + /* Affectation de la valeur au signal opy_iru28 */ + GENLIB_LOINS("model_buff_2","buff_2_opy_iru28", + "const_0x00000000[1:0]", + "opy_iru28[1:0]", + POWER); + GENLIB_LOINS("model_buff_26","buff_26_opy_iru28", + "ir[25:0]", + "opy_iru28[27:2]", + POWER); + GENLIB_LOINS("model_buff_4","buff_4_opy_iru28", + "const_0x00000000[31:28]", + "opy_iru28[31:28]", + POWER); + + + /* + * Définition des MUX de Y + */ + + GENLIB_LOINS("model_opy_its6", "mux2_6", + "opy_mx6", + "opy_its6[31:0]", + POWER); + + GENLIB_LOINS("model_0_BFC00000","oxBFC00000", + "const_0xBFC00000[31:0]", + POWER); + + GENLIB_LOINS("model_nmux2_32", "nmux2_5", + "opy_mx5", + "const_0xBFC00000[31:0]", "opy_shamt[31:0]", + "opy_its5[31:0]", + POWER); + + GENLIB_LOINS("model_opy_its4", "mux2_4", + "opy_mx4", + "opy_its4[31:0]", + POWER); + + GENLIB_LOINS("model_0_00000000","ox00000000", + "const_0x00000000[31:0]", + POWER); + + GENLIB_LOINS("model_nmux2_32", "nmux2_3", + "opy_mx3", + "const_0x00000000[31:0]", "opy_ir16[31:0]", + "opy_its3[31:0]", + POWER); + + GENLIB_LOINS("model_nmux2_32", "nmux2_2", + "opy_mx2", + "opy_ir18[31:0]", "opy_iru28[31:0]", + "opy_its2[31:0]", + POWER); + + GENLIB_LOINS("model_nmux2_32","nmux2_1", + "opy_mx1", + "dt[31:0]", "ad[31:0]", + "opy_its1[31:0]", + POWER); + + /* + * Définition des TRI STATE Y + */ + + GENLIB_LOINS("model_nbuse_32", "nbusey_32_6", + "opy_ts6", + "opy_its6[31:0]", + "opy_ots[31:0]", + POWER); + + GENLIB_LOINS("model_nbuse_32", "nbusey_32_5", + "opy_ts5", + "opy_its5[31:0]", + "opy_ots[31:0]", + POWER); + + GENLIB_LOINS("model_nbuse_32", "nbusey_32_4", + "opy_ts4", + "opy_its4[31:0]", + "opy_ots[31:0]", + POWER); + + GENLIB_LOINS("model_nbuse_32", "nbusey_32_3", + "opy_ts3", + "opy_its3[31:0]", + "opy_ots[31:0]", + POWER); + + GENLIB_LOINS("model_nbuse_32", "nbusey_32_2", + "opy_ts2", + "opy_its2[31:0]", + "opy_ots[31:0]", + POWER); + + GENLIB_LOINS("model_nbuse_32", "nbusey_32_1", + "opy_ts1", + "opy_its1[31:0]", + "opy_ots[31:0]", + POWER); + + /* + * Définition des signaux opy_out et opy_sign + */ + GENLIB_LOINS("model_buff_32", "buff_32_opy_out", + "opy_ots[31:0]", + "opy_out[31:0]", + POWER); + GENLIB_LOINS("buf_x2", "buff_1_opy_sign", + "opy_ots[31]", + "opy_sign", + POWER); + + +/********************************************* ALU ************************************************/ + + +/* DECALEUR DE L'ALU */ + +/* inversion de la commande decalage a droite ou gauche */ +GENLIB_LOINS("inv_x1", + "inv_x1_nmx2i0", + "alu_mx2i0", + "nalu_mx2i0", + "vdd","vss",NULL); + +/* decalage a gauche et a droite*/ +GENLIB_LOINS("model_shift", + "shift_alu", + "alu_mx1i0","nalu_mx2i0", + "opy_out[4:0]", + "opx_out[31:0]", + "alu_shout[31:0]", + "vdd","vss",NULL); + + +/* OPERATIONS ARITHMETIQUES DE L'ALU */ + +/* nor de X et Y */ + +GENLIB_LOINS("model_nor2_32", + "nor_alu_1", + "opx_out[31:0]", "opy_out[31:0]", + "alu_nor[31:0]", + "vdd","vss",NULL); + +/* or de X et Y */ + +GENLIB_LOINS("model_or2_32", + "or_alu_1", + "opx_out[31:0]", "opy_out[31:0]", + "alu_or[31:0]", + "vdd","vss",NULL); + +/* and de X et Y */ + +GENLIB_LOINS("model_and2_32", + "and_alu_1", + "opx_out[31:0]", "opy_out[31:0]", + "alu_and[31:0]", + "vdd","vss",NULL); + +/* xor de X et Y */ + +GENLIB_LOINS("model_xnor2_32", + "xnor_alu_1", + "opx_out[31:0]", "opy_out[31:0]", + "alu_xnor[31:0]", + "vdd","vss",NULL); + +/* additionneur */ + +/*GENLIB_LOINS( "inv_x2", "inv_alu_mx0i0", "alu_mx0i0", "nalu_mx0i0", POWER); +*/ + +GENLIB_LOINS( + "model_addition_32", + "additionneur", + "alu_mx0i0", + "alu_cry[32]", + "alu_cry[31]", + "opx_out[31:0]", "opy_out[31:0]", "alu_sum[31:0]", + "vdd", "vss", NULL); + +/* alu_yop: inversion de opy_out si on veut soustraire */ + + /* inversion de opy_out */ +/* + GENLIB_LOINS("model_inv_32", + "inv_opy_out", + "opy_out[31:0]", + "nopy_out[31:0]", + "vdd","vss",NULL); +*/ + /* alu_yop */ +/* + GENLIB_LOINS("model_nmux2_32", + "mux_alu_yop", + "alu_mx0i0", + "opy_out[31:0]","nopy_out[31:0]", + "alu_yop[31:0]", + "vdd","vss",NULL); +*/ +/* alu_cry: propagation de la carry */ + + /* remplissage de alu_cry(0) */ +/* + GENLIB_LOINS("buf_x2", + "buf_alu_cry0", + "alu_mx0i0", + "alu_cry[0]", + "vdd","vss",NULL); + */ + /* remplissage de alu_cry[32:1] */ +/* + for (i=0; i<32; i++) { + + GENLIB_LOINS("oa2a2a23_x2", + GENLIB_NAME("sortie_alu_cry%d",i), + GENLIB_NAME("opx_out[%d]",i), GENLIB_NAME("alu_yop[%d]",i), GENLIB_NAME("opx_out[%d]",i), GENLIB_NAME("alu_cry[%d]",i), + GENLIB_NAME("alu_yop[%d]",i), GENLIB_NAME("alu_cry[%d]",i), + GENLIB_NAME("alu_cry[%d]",i+1), + "vdd","vss",NULL); + + } +*/ +/* somme de X et Y (ou not(Y)) */ +/* + GENLIB_LOINS("model_xor2_32", + "xor_1_alu_1", + "opx_out[31:0]", "alu_cry[31:0]", + "sortie_xor_1_alu_1[31:0]", + "vdd","vss",NULL); + + GENLIB_LOINS("model_xor2_32", + "xor_2_alu_1", + "sortie_xor_1_alu_1[31:0]", "alu_yop[31:0]", + "alu_sum[31:0]", + "vdd","vss",NULL); +*/ +/* MULTIPLEXAGE DE SORTIE DE L'ALU */ + +/* inversion de alu_test_n */ + + GENLIB_LOINS("inv_x1", + "inv_alu_test_n", + "alu_test_n", + "nalu_test_n", + "vdd","vss",NULL); + +/* constante qui servira au signal de mode test */ + +/* signal rempli si mode test */ + + GENLIB_LOINS("model_inv_32", + "inv_32_nzalu_out", + "const_0x00000000[31:1]","nalu_test_n", + "nzalu_out[31:0]", + POWER); + +/* serie de multiplexages pour obtenir le signal alu_out */ + + +GENLIB_LOINS("model_nmux2_32", + "mux_nalu_s1", + "alu_mx1i2", + "alu_and[31:0]","alu_or[31:0]", + "nalu_s1[31:0]", + "vdd","vss",NULL); + +GENLIB_LOINS("model_mux2_32", + "mux_alu_s3", + "alu_mx2i1", + "alu_sum[31:0]","alu_nor[31:0]", + "alu_s3[31:0]", + "vdd","vss",NULL); + +GENLIB_LOINS("model_nmux2_32", + "mux_alu_s2", + "alu_mx2i1", + "alu_xnor[31:0]","nalu_s1[31:0]", + "alu_s2[31:0]", + "vdd","vss",NULL); + +GENLIB_LOINS("model_mux2_32", + "mux_alu_s4", + "alu_mx3i0", + "alu_s3[31:0]","alu_s2[31:0]", + "alu_s4[31:0]", + "vdd","vss",NULL); + +GENLIB_LOINS("model_nmux2_32", + "mux_nalu_s5", + "alu_mx4i0", + "alu_s4[31:0]","alu_shout[31:0]", + "nalu_s5[31:0]", + "vdd","vss",NULL); + +GENLIB_LOINS("model_nmux2_32", + "mux_alu_out", + "alu_mx5i0", + "nalu_s5[31:0]","nzalu_out[31:0]", + "alu_out[31:0]", + "vdd","vss",NULL); + +/* SORTIES AUXILIAIRES DE L'ALU */ + +/* alu_nul */ + +GENLIB_LOINS("model_nul", + "m_alu_nul", + "alu_sum[31:0]", + "alu_nul", + "vdd","vss",NULL); + +/* alu_sign */ + +GENLIB_LOINS("buf_x2", + "buf_x2_sign", + "alu_sum[31]", + "alu_sign", + "vdd","vss",NULL); + +/* alu_c31 */ + +GENLIB_LOINS("inv_x1", + "inv_x1_c31", + "alu_cry[32]", + "alu_c31", + "vdd","vss",NULL); + +/* alu_c30 */ + +GENLIB_LOINS("inv_x1", + "inv_x1_c30", + "alu_cry[31]", + "alu_c30", + "vdd","vss",NULL); + +/* SELECTION DE BYTE HALF OU WORD */ + + /* selection de byte */ + + GENLIB_LOINS("model_nmux2_32", + "nmux2_byte", + "alu_byte", + "alu_out[7:0]","alu_out[7:0]","alu_out[7:0]","alu_out[7:0]","alu_out[31:0]", + "data_outb_n[31:0]", + "vdd","vss",NULL); + + /*selection de half */ + + GENLIB_LOINS("model_inv_32", + "inv_32_half", + "alu_out[15:0]","alu_out[15:0]", + "data_outh_n[31:0]", + "vdd","vss",NULL); + + /* sortie finale de l'alu */ + + + GENLIB_LOINS("model_nmux2_32", + "nmux2_word", + "alu_half", + "data_outh_n[31:0]","data_outb_n[31:0]", + "data_out_dpt[31:0]", + "vdd","vss",NULL); + +/************************************************* FIN DE L'ALU *****************************************/ + +/* ADROUT Multiplexer Description */ + + /* multiplexer */ + + GENLIB_LOINS("model_nmux2_32", + "nmux2_adrout", + "out_mx0i0", + "pc[31:0]","ad[31:0]", + "out_adr_n[31:0]", + "vdd","vss",NULL); + + /* autres sorties */ + + GENLIB_LOINS("model_inv_32", + "inv_32_adr", + "out_adr_n[31:0]", + "out_adr[31:0]", + "vdd","vss",NULL); + + GENLIB_LOINS("inv_x1", + "inv_alun0", + "alu_out[0]", + "alu_n_0", + "vdd","vss",NULL); + + + GENLIB_LOINS("inv_x1", + "inv_alun1", + "alu_out[1]", + "alu_n_1", + "vdd","vss",NULL); + + + GENLIB_LOINS("inv_x1", + "inv_alun31", + "alu_out[31]", + "alu_n_31", + "vdd","vss",NULL); + + GENLIB_LOINS("buf_x2", + "buf_adrn0", + "out_adr_n[0]", + "adr_n_0", + "vdd","vss",NULL); + + GENLIB_LOINS("buf_x2", + "buf_adrn1", + "out_adr_n[1]", + "adr_n_1", + "vdd","vss",NULL); + +/* FIN DE ADROUT Multiplexer Description */ + + + +/* PC Register Description */ + + GENLIB_LOINS("a2_x2","testpc", + "test","pc_wen", + "test_pc", + POWER); + + GENLIB_LOINS("model_sfft", + "sfft_pc", + "test_pc", + "dpt_scin", + "pc_wen", + "ck", + "alu_out[31:0]", + "pc[31:0]", + "vdd","vss",NULL); + +/* FIN PC Register Description */ + + +/* AD Register Description */ + + GENLIB_LOINS("a2_x2","testad", + "test","ad_wen", + "test_ad", + POWER); + + GENLIB_LOINS("model_sfft", + "sfft_ad", + "test_ad", + "pc[31]", + "ad_wen", + "ck", + "alu_out[31:0]", + "ad[31:0]", + "vdd","vss",NULL); + +/* FIN AD Register Description */ + + +/* EPC Register Description */ + + GENLIB_LOINS("a2_x2","testepc", + "test","epc_wen", + "test_epc", + POWER); + + GENLIB_LOINS("model_sfft", + "sfft_epc", + "test_epc", + "ad[31]", + "epc_wen", + "ck", + "alu_out[31:0]", + "epc[31:0]", + "vdd","vss",NULL); + +/* FIN EPC Register Description */ + + +/* BAR Register Description */ + + GENLIB_LOINS("a2_x2","testbar", + "test","bar_wen", + "test_bar", + POWER); + + GENLIB_LOINS("model_sfft", + "sfft_bar", + "test_bar", + "epc[31]", + "bar_wen", + "ck", + "alu_out[31:0]", + "bar[31:0]", + "vdd","vss",NULL); + +/* FIN BAR Register Description */ + + +/* SR/CR register Description */ + + GENLIB_LOINS("model_0_0000", + "ox0000", + "const_0x0000[15:0]", + POWER); + + GENLIB_LOINS("model_buff_32", + "buff_32_sr", + "const_0x0000[15:0]","crsr_sts_in[15:0]", + "sr_s[31:0]", + "vdd","vss",NULL); + + GENLIB_LOINS("model_buff_32", + "buff_32_cr", + "sr_s[31:0]", + "cr_s[31:0]", + "vdd","vss",NULL); + + GENLIB_LOINS("model_buff_16", + "buff_16_dpt", + "alu_out[15:0]", + "crsr_dpt_out[15:0]", + "vdd","vss",NULL); + +/* HI Register Description */ + + GENLIB_LOINS("a2_x2","testhi", + "test","hi_wen", + "test_hi", + POWER); + + GENLIB_LOINS("model_sfft", + "sfft_hi", + "test_hi", + "bar[31]", + "hi_wen", + "ck", + "alu_out[31:0]", + "hi[31:0]", + "vdd","vss",NULL); + +/* FIN HI Register Description */ + + +/* LO Register Description */ + + GENLIB_LOINS("a2_x2","testlo", + "test","lo_wen", + "test_lo", + POWER); + + GENLIB_LOINS("model_sfft", + "sfft_lo", + "test_lo", + "hi[31]", + "lo_wen", + "ck", + "alu_out[31:0]", + "lo[31:0]", + "vdd","vss",NULL); + +/* FIN LO Register Description */ + + +/* IR Register Description */ + + GENLIB_LOINS("a2_x2","testir", + "test","ir_wen", + "test_ir", + POWER); + + GENLIB_LOINS("model_sfft", + "sfft_ir", + "test_ir", + "lo[31]", + "ir_wen", + "ck", + "data_in_dpt[31:0]", + "ir[31:0]", + "vdd","vss",NULL); + +/* FIN IR Register Description */ + + +/* DT Register Description */ + + GENLIB_LOINS("a2_x2","testdt", + "test","dt_wen", + "test_dt", + POWER); + + GENLIB_LOINS("model_sfft", + "sfft_dt", + "test_dt", + "ir[31]", + "dt_wen", + "ck", + "data_in_dpt[31:0]", + "dt[31:0]", + "vdd","vss",NULL); + + + GENLIB_LOINS("buf_x2", "scout", "dt[31]", "dpt_scout",POWER); + /* FIN DT Register Description */ + + /* Banc de registres */ + GENLIB_LOINS("model_banc_reg", "rf_i", + "ck", + "un_1", + "rf_wen", "un_1", + "rf_ar[4:0]", "rf_aw[4:0]", + "alu_out[31:0]", "alu_out[31:0]", + "rf_o[31:0]", + POWER); + + GENLIB_LOINS("one_x0","un", + "un_1", + POWER); + +/***********FIN de l'implémentation du DATA-PATH***************/ + + /* End of netlist description. */ + GENLIB_SAVE_LOFIG (); + +/*******************DEBUT DU PREPLACEMENT**********************/ +GENLIB_DEF_PHFIG("mips_dpt"); +GENLIB_DEF_PHSC("mips_dpt"); + + +/**************Placement du banc de registres******************/ +GENLIB_SC_PLACE("rf_i",NOSYM,0,0); + +/**************Placement de l'opérande X***********************/ + +/* tristate rf_o */ +GENLIB_SC_RIGHT("buse_32_0",NOSYM); +/* epc mux bar */ +GENLIB_SC_RIGHT("sfft_epc",NOSYM); +GENLIB_SC_TOP("un",NOSYM); +GENLIB_SC_TOP("testepc",SYM_Y); +GENLIB_DEF_PHINS("sfft_epc"); +GENLIB_SC_RIGHT("nmux2_32_4",NOSYM); +GENLIB_SC_RIGHT("nbuse_32_4",NOSYM); +GENLIB_SC_TOP("testbar",NOSYM); +GENLIB_DEF_PHINS("nbuse_32_4"); +GENLIB_SC_RIGHT("sfft_bar",SYM_X); +GENLIB_SC_TOP("testhi",SYM_X); +GENLIB_DEF_PHINS("sfft_bar"); +/* hi mux lo */ +GENLIB_SC_RIGHT("sfft_hi",NOSYM); +GENLIB_SC_RIGHT("nmux2_32_2",SYM_X); +GENLIB_SC_RIGHT("nbuse_32_2",NOSYM); +GENLIB_SC_TOP("testlo",NOSYM); +GENLIB_DEF_PHINS("nbuse_32_2"); +GENLIB_SC_RIGHT("sfft_lo",SYM_X); +/********************************************* ALU *****************************************************/ +GENLIB_SC_RIGHT("inv_32_half",SYM_X); +GENLIB_SC_RIGHT("nmux2_word",SYM_X); +GENLIB_PLACE_RIGHT("tie_x0","tie_alu_5",NOSYM); +GENLIB_SC_RIGHT("nmux2_byte",SYM_X); +GENLIB_SC_RIGHT("inv_alun0",SYM_X); +GENLIB_SC_TOP("inv_alun1",SYMXY); +GENLIB_SC_TOP("mux_alu_out",SYM_X); +GENLIB_SC_TOP("inv_alun31",SYM_X); +GENLIB_DEF_PHINS("inv_alun0"); +GENLIB_PLACE_RIGHT("tie_x0","tie_alun_1",NOSYM); +GENLIB_PLACE_RIGHT("tie_x0","tie_alun_2",NOSYM); +GENLIB_SC_RIGHT("inv_32_nzalu_out",SYM_X); +GENLIB_SC_TOP("inv_alu_test_n",SYM_X); +GENLIB_DEF_PHINS("inv_32_nzalu_out"); +GENLIB_SC_RIGHT("mux_nalu_s5",SYM_X); +GENLIB_SC_RIGHT("shift_alu",SYM_X); +GENLIB_SC_TOP("inv_x1_nmx2i0",SYMXY); +GENLIB_DEF_PHINS("shift_alu"); +GENLIB_SC_RIGHT("mux_alu_s4",SYM_X); +GENLIB_SC_RIGHT("mux_alu_s3",SYM_X); +GENLIB_SC_RIGHT("nor_alu_1",SYM_X); +GENLIB_SC_RIGHT("m_alu_nul",SYM_X); +GENLIB_SC_TOP("buf_x2_sign",SYMXY); +GENLIB_DEF_PHINS("m_alu_nul"); +GENLIB_SC_RIGHT("additionneur",SYM_X); +/*GENLIB_SC_RIGHT("xor_2_alu_1",SYM_X); +GENLIB_SC_RIGHT("xor_1_alu_1",SYM_X); +GENLIB_SC_RIGHT("mux_alu_yop",SYM_X); +GENLIB_SC_RIGHT("inv_opy_out",SYM_X); +GENLIB_SC_TOP("buf_alu_cry0",SYM_X);*/ +GENLIB_SC_TOP("inv_x1_c30",SYM_X); +GENLIB_SC_TOP("inv_x1_c31",SYMXY); +/*GENLIB_SC_TOP("inv_alu_mx0i0",SYM_X);*/ +GENLIB_DEF_PHINS("additionneur"); +/*GENLIB_DEF_PHINS("inv_opy_out");*/ +/*GENLIB_SC_RIGHT("sortie_alu_cry0",SYM_X); +for (i=1;i<16;i++){ + GENLIB_PLACE_TOP("tie_x0",GENLIB_NAME("tie_alu_cry_%d",i),SYM_Y); + GENLIB_SC_TOP(GENLIB_NAME("sortie_alu_cry%d",i),SYM_X); +} +GENLIB_DEF_PHINS("sortie_alu_cry0"); +GENLIB_SC_RIGHT("sortie_alu_cry16",SYM_X); +for (i=17;i<32;i++){ + GENLIB_PLACE_TOP("tie_x0",GENLIB_NAME("tie_alu_cry_%d",i),SYM_Y); + GENLIB_SC_TOP(GENLIB_NAME("sortie_alu_cry%d",i),SYM_X); +} +GENLIB_DEF_PHINS("sortie_alu_cry16");*/ +GENLIB_SC_RIGHT("mux_alu_s2",SYM_X); +GENLIB_PLACE_RIGHT("tie_x0","tie_alu_4",NOSYM); +GENLIB_SC_RIGHT("xnor_alu_1",SYM_X); +GENLIB_PLACE_RIGHT("tie_x0","tie_alu_3",NOSYM); +GENLIB_SC_RIGHT("mux_nalu_s1",SYM_X); +GENLIB_PLACE_RIGHT("tie_x0","tie_alu_2",NOSYM); +GENLIB_SC_RIGHT("and_alu_1",SYM_X); +GENLIB_PLACE_RIGHT("tie_x0","tie_alu_1",NOSYM); +GENLIB_SC_RIGHT("or_alu_1",SYM_X); +/* buff opx_out */ +GENLIB_SC_RIGHT("buff_opx_ots",NOSYM); +GENLIB_SC_TOP("buff_opx_sign",SYM_X); +GENLIB_DEF_PHINS("buff_opx_ots"); +/* rom opx_mx5 */ +GENLIB_SC_RIGHT("mux2_32_5",NOSYM); +GENLIB_SC_RIGHT("nbuse_32_5",NOSYM); +/* sr_s mux cr_s */ +GENLIB_SC_RIGHT("ox0000",NOSYM); +GENLIB_SC_RIGHT("buff_32_sr",NOSYM); +GENLIB_SC_RIGHT("buff_32_cr",NOSYM); +GENLIB_SC_RIGHT("nmux2_32_3",NOSYM); +GENLIB_SC_RIGHT("nbuse_32_3",NOSYM); +/* pc4 */ +GENLIB_SC_RIGHT("nbuse_32_7",SYM_X); +GENLIB_SC_RIGHT("nmux2_32_7",SYM_X); +GENLIB_SC_RIGHT("buff_pc4",SYM_X); +GENLIB_SC_RIGHT("ox00000000pc4",SYM_X); +/* pc mux ad */ +GENLIB_SC_RIGHT("sfft_pc",NOSYM); +GENLIB_SC_TOP("testpc",SYM_X); +GENLIB_DEF_PHINS("sfft_pc"); +GENLIB_SC_RIGHT("nmux2_32_1",SYM_X); +GENLIB_SC_RIGHT("nbuse_32_1",NOSYM); +GENLIB_SC_TOP("testad",SYM_X); +GENLIB_DEF_PHINS("nbuse_32_1"); +GENLIB_SC_RIGHT("sfft_ad",SYM_X); +/* out_adr */ +GENLIB_SC_RIGHT("buf_adrn0",SYM_X); +GENLIB_SC_TOP("buf_adrn1",SYMXY); +GENLIB_SC_TOP("nmux2_adrout",SYM_X); +GENLIB_DEF_PHINS("buf_adrn0"); +GENLIB_PLACE_RIGHT("tie_x0","tie_adrn_1",NOSYM); +GENLIB_PLACE_RIGHT("tie_x0","tie_adrn_2",NOSYM); +GENLIB_SC_RIGHT("inv_32_adr",SYM_X); +/* dt mux */ +GENLIB_SC_RIGHT("ox0000FFFF",NOSYM); +GENLIB_SC_RIGHT("nmux2_32_6",SYM_X); +GENLIB_SC_RIGHT("nbuse_32_6",SYM_X); +GENLIB_SC_TOP("testdt",SYM_X); +GENLIB_DEF_PHINS("nbuse_32_6"); +GENLIB_SC_RIGHT("sfft_dt",SYM_X); +GENLIB_SC_TOP("scout",SYM_X); +GENLIB_DEF_PHINS("sfft_dt"); + +/**************Placement de l'opérande Y***********************/ +/* dt mux ad */ +GENLIB_SC_RIGHT("nmux2_1",NOSYM); +GENLIB_SC_RIGHT("nbusey_32_1",NOSYM); +/* mux 4 */ +GENLIB_SC_RIGHT("mux2_4",NOSYM); +GENLIB_SC_RIGHT("nbusey_32_4",NOSYM); +/* opy_out */ +GENLIB_SC_RIGHT("buff_32_opy_out",NOSYM); +GENLIB_SC_TOP("buff_1_opy_sign",NOSYM); +GENLIB_DEF_PHINS("buff_32_opy_out"); + +/* mux 6 */ +GENLIB_SC_RIGHT("mux2_6",NOSYM); +GENLIB_SC_RIGHT("nbusey_32_6",NOSYM); + +/* mux 5 */ +GENLIB_SC_RIGHT("nbusey_32_5",SYM_X); +GENLIB_SC_RIGHT("nmux2_5",SYM_X); +GENLIB_SC_RIGHT("oxBFC00000",NOSYM); +GENLIB_PLACE_RIGHT("tie_x0","tie_shamt_rom_1",NOSYM); +GENLIB_PLACE_TOP("tie_x0","tie_shamt_rom_2",SYM_Y); +GENLIB_PLACE_TOP("tie_x0","tie_shamt_rom_3",NOSYM); +GENLIB_PLACE_TOP("tie_x0","tie_shamt_rom_4",SYM_Y); +GENLIB_SC_TOP("buff_27_shamt",SYM_X); +GENLIB_DEF_PHINS("tie_shamt_rom_1"); +GENLIB_PLACE_RIGHT("tie_x0","tie_shamt_rom_5",NOSYM); +GENLIB_PLACE_RIGHT("tie_x0","tie_shamt_rom_6",NOSYM); +//GENLIB_PLACE_RIGHT("tie_x0","tie_shamt",SYM_X); + +/* mux 3 */ +GENLIB_SC_RIGHT("ox00000000",NOSYM); +GENLIB_SC_RIGHT("nbusey_32_3",SYM_X); +GENLIB_SC_RIGHT("nmux2_3",SYM_X); +GENLIB_SC_RIGHT("buff_16_opy_ir16",SYM_X); +GENLIB_SC_TOP("buff_16_opy_ir16_2",SYM_X); +GENLIB_SC_TOP("testir",SYM_X); +GENLIB_DEF_PHINS("buff_16_opy_ir16"); +GENLIB_PLACE_RIGHT("tie_x0","tie_opy_ir16",NOSYM); +/* ir */ +GENLIB_SC_RIGHT("sfft_ir",SYM_X); +/* mux2 */ +GENLIB_SC_RIGHT("nbusey_32_2",SYM_X); +GENLIB_SC_RIGHT("nmux2_2",SYM_X); +GENLIB_SC_RIGHT("buff_2_opy_ir18",SYM_X); +GENLIB_SC_TOP("buff_16_opy_ir18",SYM_X); +GENLIB_SC_TOP("buff_14_opy_ir18",SYM_X); +GENLIB_DEF_PHINS("buff_2_opy_ir18"); +GENLIB_PLACE_RIGHT("tie_x0","tie_opy_ir18_1",NOSYM); +GENLIB_SC_RIGHT("buff_2_opy_iru28",SYM_X); +GENLIB_SC_TOP("buff_26_opy_iru28",SYM_X); +GENLIB_SC_TOP("buff_4_opy_iru28",SYM_X); +GENLIB_DEF_PHINS("buff_2_opy_iru28"); +/* opy_codop */ +GENLIB_PLACE_RIGHT("tie_x0","tie_codop_1",NOSYM); +GENLIB_PLACE_TOP("tie_x0","tie_codop_2",SYM_Y); +GENLIB_SC_TOP("buff_19_opy_codop",SYM_X); +/* opy_shamt */ +GENLIB_DEF_PHINS("tie_codop_1"); +GENLIB_PLACE_RIGHT("tie_x0","tie_codop_3",NOSYM); +GENLIB_PLACE_RIGHT("tie_x0","tie_shamt_1",NOSYM); +GENLIB_PLACE_TOP("tie_x0","tie_shamt_2",SYM_Y); +GENLIB_PLACE_TOP("tie_x0","tie_shamt_3",NOSYM); +GENLIB_PLACE_TOP("tie_x0","tie_shamt_4",SYM_Y); +GENLIB_SC_TOP("buff_5_opy_shamt",SYM_X); +GENLIB_PLACE_TOP("tie_x0","tie_opy_rd",SYM_Y); +/* opy_rd */ +GENLIB_SC_TOP("buff_5_opy_rd",SYM_X); +GENLIB_PLACE_TOP("tie_x0","tie_opy_rdrt",SYM_Y); +/* opy_rdrt */ +GENLIB_SC_TOP("buff_5_opy_rdrt",SYM_X); +GENLIB_PLACE_TOP("tie_x0","tie_opy_rs",SYM_Y); +/* opy_rs */ +GENLIB_SC_TOP("buff_5_opy_rs",SYM_X); + +/* boite d'aboutement */ +GENLIB_DEF_AB(0,0,0,0); + + +GENLIB_SAVE_PHFIG(); +/********************FIN DU PREPLACEMENT***********************/ + + return 0; +} diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_dpt.vbe b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_dpt.vbe new file mode 100644 index 00000000..8c333c6f --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_dpt.vbe @@ -0,0 +1,689 @@ +-- ###-------------------------------------------------------------### +-- # # +-- # File : "mips_dpt.vbe" # +-- # Date : July 30, 2001. # +-- # # +-- ###-------------------------------------------------------------### + + +ENTITY mips_dpt IS +PORT( + vdd : in bit; + vss : in bit; + test : in bit; + dpt_scin : in bit; + dpt_scout : out bit; + ck : in bit; + pc_wen : in bit; + ad_wen : in bit; + epc_wen : in bit; + bar_wen : in bit; + ir_wen : in bit; + dt_wen : in bit; + hi_wen : in bit; + lo_wen : in bit; + rf_wen : in bit; + rf_aw : in bit_vector(4 downto 0); + rf_ar : in bit_vector(4 downto 0); + opx_ts7 : in bit; + opx_ts6 : in bit; + opx_ts5 : in bit; + opx_ts4 : in bit; + opx_ts3 : in bit; + opx_ts2 : in bit; + opx_ts1 : in bit; + opx_ts0 : in bit; + opx_mx7 : in bit; + opx_mx6 : in bit; + opx_mx5 : in bit; + opx_mx4 : in bit; + opx_mx3 : in bit; + opx_mx2 : in bit; + opx_mx1 : in bit; + opx_sign : out bit; + crsr_dpt_out : out bit_vector(15 downto 0); + crsr_sts_in : in bit_vector(15 downto 0); + opy_ts6 : in bit; + opy_ts5 : in bit; + opy_ts4 : in bit; + opy_ts3 : in bit; + opy_ts2 : in bit; + opy_ts1 : in bit; + opy_mx6 : in bit; + opy_mx5 : in bit; + opy_mx4 : in bit; + opy_mx3 : in bit; + opy_mx2 : in bit; + opy_mx1 : in bit; + opy_codop : out bit_vector(18 downto 0); + opy_rs : out bit_vector( 4 downto 0); + opy_rdrt : out bit_vector( 4 downto 0); + opy_rd : out bit_vector( 4 downto 0); + opy_sign : out bit; + data_in_dpt : in bit_vector(31 downto 0); + alu_mx5i0 : in bit; + alu_mx4i0 : in bit; + alu_mx3i0 : in bit; + alu_mx2i0 : in bit; + alu_mx2i1 : in bit; + alu_mx1i2 : in bit; + alu_mx1i1 : in bit; + alu_mx1i0 : in bit; + alu_mx0i0 : in bit; + alu_byte : in bit; + alu_half : in bit; + alu_test_n : in bit; + alu_c31 : out bit; + alu_c30 : out bit; + alu_nul : out bit; + alu_sign : out bit; + data_out_dpt : out bit_vector(31 downto 0); + out_mx0i0 : in bit; + out_adr : out bit_vector(31 downto 0); + alu_n_31 : inout bit; + alu_n_1 : inout bit; + alu_n_0 : inout bit; + adr_n_1 : inout bit; + adr_n_0 : inout bit +); +END mips_dpt; +ARCHITECTURE fonctional OF mips_dpt IS + signal out_adr_n : bit_vector(31 downto 0); + signal data_in_n : bit_vector(31 downto 0); + signal data_outh_n : bit_vector(31 downto 0); + signal data_outb_n : bit_vector(31 downto 0); + constant r0 : bit_vector(31 downto 0) :=X"00000000"; + signal rf_1 : reg_vector(31 downto 0) register; + signal rf_2 : reg_vector(31 downto 0) register; + signal rf_3 : reg_vector(31 downto 0) register; + signal rf_4 : reg_vector(31 downto 0) register; + signal rf_5 : reg_vector(31 downto 0) register; + signal rf_6 : reg_vector(31 downto 0) register; + signal rf_7 : reg_vector(31 downto 0) register; + signal rf_8 : reg_vector(31 downto 0) register; + signal rf_9 : reg_vector(31 downto 0) register; + signal rf_10 : reg_vector(31 downto 0) register; + signal rf_11 : reg_vector(31 downto 0) register; + signal rf_12 : reg_vector(31 downto 0) register; + signal rf_13 : reg_vector(31 downto 0) register; + signal rf_14 : reg_vector(31 downto 0) register; + signal rf_15 : reg_vector(31 downto 0) register; + signal rf_16 : reg_vector(31 downto 0) register; + signal rf_17 : reg_vector(31 downto 0) register; + signal rf_18 : reg_vector(31 downto 0) register; + signal rf_19 : reg_vector(31 downto 0) register; + signal rf_20 : reg_vector(31 downto 0) register; + signal rf_21 : reg_vector(31 downto 0) register; + signal rf_22 : reg_vector(31 downto 0) register; + signal rf_23 : reg_vector(31 downto 0) register; + signal rf_24 : reg_vector(31 downto 0) register; + signal rf_25 : reg_vector(31 downto 0) register; + signal rf_26 : reg_vector(31 downto 0) register; + signal rf_27 : reg_vector(31 downto 0) register; + signal rf_28 : reg_vector(31 downto 0) register; + signal rf_29 : reg_vector(31 downto 0) register; + signal rf_30 : reg_vector(31 downto 0) register; + signal rf_31 : reg_vector(31 downto 0) register; + signal rf_o : bit_vector(31 downto 0); + signal pc : reg_vector (31 downto 0) register; + signal epc : reg_vector (31 downto 0) register; + signal bar : reg_vector (31 downto 0) register; + signal pc4 : bit_vector (31 downto 0); + signal cr_s : bit_vector (31 downto 0); + signal sr_s : bit_vector (31 downto 0); + signal ad : reg_vector (31 downto 0) register; + signal ir : reg_vector (31 downto 0) register; + signal dt : reg_vector (31 downto 0) register; + signal hi : reg_vector (31 downto 0) register; + signal lo : reg_vector (31 downto 0) register; + signal opy_conflict : bit; + signal opy_nodriver : bit; + signal opy_its6 : bit_vector(31 downto 0); + signal opy_its5 : bit_vector(31 downto 0); + signal opy_its4 : bit_vector(31 downto 0); + signal opy_its3 : bit_vector(31 downto 0); + signal opy_its2 : bit_vector(31 downto 0); + signal opy_its1 : bit_vector(31 downto 0); + signal opy_ots : bit_vector(31 downto 0); + signal opy_out : bit_vector(31 downto 0); + signal opy_dt : bit_vector(31 downto 0); + signal opy_ir16 : bit_vector(31 downto 0); + signal opy_ir18 : bit_vector(31 downto 0); + signal opy_iru28 : bit_vector(31 downto 0); + signal opy_shamt : bit_vector(31 downto 0); + signal opx_conflict : bit; + signal opx_nodriver : bit; + signal opx_its7 : bit_vector(31 downto 0); + signal opx_its6 : bit_vector(31 downto 0); + signal opx_its5 : bit_vector(31 downto 0); + signal opx_its4 : bit_vector(31 downto 0); + signal opx_its3 : bit_vector(31 downto 0); + signal opx_its2 : bit_vector(31 downto 0); + signal opx_its1 : bit_vector(31 downto 0); + signal opx_ots : bit_vector(31 downto 0); + signal opx_out : bit_vector(31 downto 0); + signal alu_out : bit_vector(31 downto 0); + signal alu_nor : bit_vector(31 downto 0); + signal alu_yop : bit_vector(31 downto 0); + signal alu_cry : bit_vector(32 downto 0); + signal alu_sum : bit_vector(31 downto 0); + signal alu_shsign : bit_vector(31 downto 0); + signal alu_shright : bit_vector(31 downto 0); + signal alu_shleft : bit_vector(31 downto 0); + signal alu_shout : bit_vector(31 downto 0); + signal rf_aw_wenabled : bit_vector(5 downto 0); + signal dt_mux_out : bit_vector(31 downto 0); + signal ir_mux_out : bit_vector(31 downto 0); + signal lo_mux_out : bit_vector(31 downto 0); + signal bar_mux_out : bit_vector(31 downto 0); + signal pc_mux_out : bit_vector(31 downto 0); + signal epc_mux_out : bit_vector(31 downto 0); + signal ad_mux_out : bit_vector(31 downto 0); + signal hi_mux_out : bit_vector(31 downto 0); + +BEGIN + + + -- ###--------------------------------------------------------### + -- # checking power supplies # + -- ###--------------------------------------------------------### + + power : assert (vdd = '1' and vss = '0') + report "power supply missing on `mips` processor" + severity WARNING; + + data_in_n <= NOT data_in_dpt; + + -- ******************* X Operand Description ******************** + + WITH opx_ts7 & opx_ts6 & opx_ts5 & opx_ts4 & opx_ts3 & opx_ts2 & + opx_ts1 & opx_ts0 SELECT + + opx_conflict <= '1' WHEN B"00000000" + |B"00000001" + |B"00000010" + |B"00000100" + |B"00001000" + |B"00010000" + |B"00100000" + |B"01000000" + |B"10000000", + '0' WHEN OTHERS; + + opx_nodriver <= '0' WHEN opx_ts7 + & opx_ts6 + & opx_ts5 + & opx_ts4 + & opx_ts3 + & opx_ts2 + & opx_ts1 + & opx_ts0 = B"00000000" ELSE '1'; + + ASSERT(opx_conflict) + REPORT "More than one driver on the X operand three-state." + SEVERITY WARNING; + ASSERT(opx_nodriver) + REPORT "No driver on the X operand three-state." + SEVERITY WARNING; + + opx_out <= opx_ots; + opx_sign <= opx_out(31); + pc4 <= pc(31 downto 28 ) & X"0000000"; + + opx_its7 <= X"FFFFFFFF" WHEN opx_mx7 ELSE not pc4; + opx_its6 <= X"FFFF0000" WHEN opx_mx6 ELSE not dt; + opx_its5 <= X"7FFFFF7F" WHEN opx_mx5 ELSE X"FFFFFFFF"; + opx_its4 <= not epc WHEN opx_mx4 ELSE not bar; + opx_its3 <= not cr_s WHEN opx_mx3 ELSE not sr_s; + opx_its2 <= not lo WHEN opx_mx2 ELSE not hi; + opx_its1 <= not ad WHEN opx_mx1 ELSE not pc; + + opx_ots <= not opx_its7 WHEN opx_ts7='1' ELSE + not opx_its6 WHEN opx_ts6='1' ELSE + not opx_its5 WHEN opx_ts5='1' ELSE + not opx_its4 WHEN opx_ts4='1' ELSE + not opx_its3 WHEN opx_ts3='1' ELSE + not opx_its2 WHEN opx_ts2='1' ELSE + not opx_its1 WHEN opx_ts1='1' ELSE + rf_o; + + -- ******************** Y Operand Description ******************** + WITH opy_ts6 & opy_ts5 & opy_ts4 & opy_ts3 & opy_ts2 & opy_ts1 SELECT + opy_conflict <= '1' WHEN B"000000" + |B"000001" + |B"000010" + |B"000100" + |B"001000" + |B"010000" + |B"100000", + '0' WHEN OTHERS; + + opy_nodriver <= '0' WHEN opy_ts6 & opy_ts5 & opy_ts4 & opy_ts3 + & opy_ts2 & opy_ts1 = B"000000" ELSE + '1'; + + ASSERT(opy_conflict) + REPORT "More than one driver on the Y operand three-state." + SEVERITY WARNING; + ASSERT(opy_nodriver) + REPORT "No driver on the Y operand three-state." + SEVERITY WARNING; + + opy_codop(18 downto 0) <= ir(31 downto 26) & ir(25 ) & ir(23) + & ir(13) & ir(12) & ir(11) & ir(16) + & ir(20) & ir(5 downto 0); + opy_rs (4 downto 0) <= ir(25 downto 21); + opy_rdrt (4 downto 0) <= ir(20 downto 16); + opy_rd (4 downto 0) <= ir(15 downto 11); + + opy_shamt(4 downto 0) <= ir(10 downto 6); + opy_shamt(31 downto 5) <= X"FFFFFF" & B"111" when ir(10) = '1' ELSE + X"000000" & B"000"; + + opy_ir16(15 downto 0) <= ir(15 downto 0); + opy_ir16(31 downto 16) <= X"FFFF" WHEN ir(15) = '1' ELSE + X"0000"; + + opy_ir18( 1 downto 0) <= B"00"; + opy_ir18(17 downto 2) <= ir(15 downto 0); + opy_ir18(31 downto 18) <= X"FFF" & B"11" WHEN ir(15) = '1' ELSE + X"000" & B"00"; + + opy_iru28( 1 downto 0) <= B"00"; + opy_iru28(27 downto 2) <= ir(25 downto 0); + opy_iru28(31 downto 28) <= X"0"; + + opy_dt <= not data_in_n; + + opy_its6 <= X"FFFFFFE7" WHEN opy_mx6 ELSE X"FFFFFFF7"; + opy_its5 <= X"403FFFFF" WHEN opy_mx5 ELSE not opy_shamt; + opy_its4 <= X"FFFFFFEF" WHEN opy_mx4 ELSE X"FFFFFFFB"; + opy_its3 <= X"FFFFFFFF" WHEN opy_mx3 ELSE not opy_ir16; + opy_its2 <= not opy_ir18 WHEN opy_mx2 ELSE not opy_iru28; + opy_its1 <= not dt WHEN opy_mx1 ELSE not ad; + + opy_ots <= not opy_its6 WHEN opy_ts6 ELSE + not opy_its5 WHEN opy_ts5 ELSE + not opy_its4 WHEN opy_ts4 ELSE + not opy_its3 WHEN opy_ts3 ELSE + not opy_its2 WHEN opy_ts2 ELSE + not opy_its1; + + opy_out <= opy_ots; + opy_sign <= opy_ots(31); + + -- ******************* ALU Shifter Description ******************* + WITH alu_mx1i0 & opx_out(31) SELECT + alu_shsign <= X"00000000" WHEN B"00" + | B"01" + | B"10", + X"FFFFFFFF" WHEN B"11"; + + WITH opy_out(4 downto 0) SELECT + alu_shleft <= + opx_out(31 downto 0) WHEN B"00000", + opx_out(30 downto 0) & B"0" WHEN B"00001", + opx_out(29 downto 0) & B"00" WHEN B"00010", + opx_out(28 downto 0) & B"000" WHEN B"00011", + opx_out(27 downto 0) & X"0" WHEN B"00100", + opx_out(26 downto 0) & X"0" & B"0" WHEN B"00101", + opx_out(25 downto 0) & X"0" & B"00" WHEN B"00110", + opx_out(24 downto 0) & X"0" & B"000" WHEN B"00111", + opx_out(23 downto 0) & X"00" WHEN B"01000", + opx_out(22 downto 0) & X"00" & B"0" WHEN B"01001", + opx_out(21 downto 0) & X"00" & B"00" WHEN B"01010", + opx_out(20 downto 0) & X"00" & B"000" WHEN B"01011", + opx_out(19 downto 0) & X"000" WHEN B"01100", + opx_out(18 downto 0) & X"000" & B"0" WHEN B"01101", + opx_out(17 downto 0) & X"000" & B"00" WHEN B"01110", + opx_out(16 downto 0) & X"000" & B"000" WHEN B"01111", + opx_out(15 downto 0) & X"0000" WHEN B"10000", + opx_out(14 downto 0) & X"0000" & B"0" WHEN B"10001", + opx_out(13 downto 0) & X"0000" & B"00" WHEN B"10010", + opx_out(12 downto 0) & X"0000" & B"000" WHEN B"10011", + opx_out(11 downto 0) & X"00000" WHEN B"10100", + opx_out(10 downto 0) & X"00000" & B"0" WHEN B"10101", + opx_out(9 downto 0) & X"00000" & B"00" WHEN B"10110", + opx_out(8 downto 0) & X"00000" & B"000" WHEN B"10111", + opx_out(7 downto 0) & X"000000" WHEN B"11000", + opx_out(6 downto 0) & X"000000" & B"0" WHEN B"11001", + opx_out(5 downto 0) & X"000000" & B"00" WHEN B"11010", + opx_out(4 downto 0) & X"000000" & B"000" WHEN B"11011", + opx_out(3 downto 0) & X"0000000" WHEN B"11100", + opx_out(2 downto 0) & X"0000000" & B"0" WHEN B"11101", + opx_out(1 downto 0) & X"0000000" & B"00" WHEN B"11110", + opx_out(0) & X"0000000" & B"000" WHEN B"11111"; + + WITH opy_out(4 downto 0) SELECT + alu_shright <= + opx_out(31 downto 0) WHEN B"00000", + alu_shsign(0) & opx_out(31 downto 1) WHEN B"00001", + alu_shsign(0 to 1) & opx_out(31 downto 2) WHEN B"00010", + alu_shsign(0 to 2) & opx_out(31 downto 3) WHEN B"00011", + alu_shsign(0 to 3) & opx_out(31 downto 4) WHEN B"00100", + alu_shsign(0 to 4) & opx_out(31 downto 5) WHEN B"00101", + alu_shsign(0 to 5) & opx_out(31 downto 6) WHEN B"00110", + alu_shsign(0 to 6) & opx_out(31 downto 7) WHEN B"00111", + alu_shsign(0 to 7) & opx_out(31 downto 8) WHEN B"01000", + alu_shsign(0 to 8) & opx_out(31 downto 9) WHEN B"01001", + alu_shsign(0 to 9) & opx_out(31 downto 10) WHEN B"01010", + alu_shsign(0 to 10) & opx_out(31 downto 11) WHEN B"01011", + alu_shsign(0 to 11) & opx_out(31 downto 12) WHEN B"01100", + alu_shsign(0 to 12) & opx_out(31 downto 13) WHEN B"01101", + alu_shsign(0 to 13) & opx_out(31 downto 14) WHEN B"01110", + alu_shsign(0 to 14) & opx_out(31 downto 15) WHEN B"01111", + alu_shsign(0 to 15) & opx_out(31 downto 16) WHEN B"10000", + alu_shsign(0 to 16) & opx_out(31 downto 17) WHEN B"10001", + alu_shsign(0 to 17) & opx_out(31 downto 18) WHEN B"10010", + alu_shsign(0 to 18) & opx_out(31 downto 19) WHEN B"10011", + alu_shsign(0 to 19) & opx_out(31 downto 20) WHEN B"10100", + alu_shsign(0 to 20) & opx_out(31 downto 21) WHEN B"10101", + alu_shsign(0 to 21) & opx_out(31 downto 22) WHEN B"10110", + alu_shsign(0 to 22) & opx_out(31 downto 23) WHEN B"10111", + alu_shsign(0 to 23) & opx_out(31 downto 24) WHEN B"11000", + alu_shsign(0 to 24) & opx_out(31 downto 25) WHEN B"11001", + alu_shsign(0 to 25) & opx_out(31 downto 26) WHEN B"11010", + alu_shsign(0 to 26) & opx_out(31 downto 27) WHEN B"11011", + alu_shsign(0 to 27) & opx_out(31 downto 28) WHEN B"11100", + alu_shsign(0 to 28) & opx_out(31 downto 29) WHEN B"11101", + alu_shsign(0 to 29) & opx_out(31 downto 30) WHEN B"11110", + alu_shsign(0 to 30) & opx_out(31) WHEN B"11111"; + + alu_shout <= alu_shleft WHEN alu_mx2i0 = '1' ELSE alu_shright; + + -- ************ ALU Arythmetic Operations Description ************ + alu_nor(31 downto 0) <= not(opx_out or opy_out); + alu_yop(31 downto 0) <= not opy_out WHEN alu_mx0i0 ELSE opy_out; + alu_cry(0) <= alu_mx0i0; + alu_cry(32 downto 1) <= (opx_out and alu_yop ) + or (opx_out and alu_cry(31 downto 0)) + or (alu_yop and alu_cry(31 downto 0)); + alu_sum(31 downto 0) <= opx_out xor alu_cry(31 downto 0) xor alu_yop; + + -- ***************** ALU Multiplexer Description ***************** + ASSERT(not (alu_mx2i1 xor alu_mx2i0)) + REPORT "alu_mx2i1:0 must have the same value." + SEVERITY WARNING; + ASSERT(not((alu_mx1i2 xor alu_mx1i1) and (alu_mx1i1 xor alu_mx1i0)) ) + REPORT "alu_mx1i2:1:0 must have the same value." + SEVERITY WARNING; + + WITH alu_mx5i0 & alu_mx4i0 & alu_mx3i0 & alu_mx2i1 & alu_mx1i2 & alu_mx1i1 SELECT + alu_out <= X"0000000" & B"000" & ( not alu_test_n ) + WHEN B"000000" + |B"000001" + |B"000010" + |B"000011" + |B"000100" + |B"000101" + |B"000110" + |B"000111" + |B"001000" + |B"001001" + |B"001010" + |B"001011" + |B"001100" + |B"001101" + |B"001110" + |B"001111" + |B"010000" + |B"010001" + |B"010010" + |B"010011" + |B"010100" + |B"010101" + |B"010110" + |B"010111" + |B"011000" + |B"011001" + |B"011010" + |B"011011" + |B"011100" + |B"011101" + |B"011110" + |B"011111", + alu_shout WHEN B"100000" + |B"100001" + |B"100010" + |B"100011" + |B"100100" + |B"100101" + |B"100110" + |B"100111" + |B"101000" + |B"101001" + |B"101010" + |B"101011" + |B"101100" + |B"101101" + |B"101110" + |B"101111", + opx_out or opy_out WHEN B"110000" + |B"110001", + opx_out and opy_out WHEN B"110010" + |B"110011", + opx_out xor opy_out WHEN B"110100" + |B"110101" + |B"110110" + |B"110111", + alu_nor WHEN B"111000" + |B"111001" + |B"111010" + |B"111011", + alu_sum WHEN B"111110" + |B"111100" + |B"111101" + |B"111111"; + + -- ************* ALU Auxiliary Outputs Affectations ************** + alu_nul <= '1' WHEN (alu_sum(31 downto 0) = X"00000000") ELSE '0'; + alu_sign <= alu_sum(31); + alu_c31 <= not alu_cry(32); + alu_c30 <= not alu_cry(31); + + WITH alu_byte SELECT + data_outb_n <= not ( alu_out( 7 downto 0) + & alu_out( 7 downto 0) + & alu_out( 7 downto 0) + & alu_out( 7 downto 0)) WHEN '1', + not alu_out(31 downto 0) WHEN '0'; + WITH alu_half SELECT + data_outh_n <= not ( alu_out( 15 downto 0) + & alu_out( 15 downto 0)) WHEN '1', + not alu_out(31 downto 0) WHEN '0'; + + data_out_dpt <= not data_outh_n when (alu_half = '1') ELSE + not data_outb_n; + + -- *************** ADROUT Multiplexer Description **************** + WITH out_mx0i0 SELECT + out_adr_n <= not pc WHEN B"1", + not ad WHEN B"0"; + + out_adr <= not out_adr_n; + alu_n_0 <= not alu_out(0); -- out_adr_n(0); + alu_n_1 <= not alu_out(1); -- out_adr_n(1); + alu_n_31 <= not alu_out(31); -- out_adr_n(31); + adr_n_0 <= out_adr_n(0); + adr_n_1 <= out_adr_n(1); + + -- ******************* PC register Description ******************* + + WITH test & pc_wen SELECT + pc_mux_out <= pc(30 downto 0) & dpt_scin WHEN B"11", + alu_out WHEN B"01", + pc WHEN OTHERS; + + ws_pc:BLOCK(ck='1' AND NOT ck'STABLE) + BEGIN + pc <= GUARDED pc_mux_out; + END BLOCK ws_pc; + + -- ******************* AD register Description ******************* + + WITH test & ad_wen SELECT + ad_mux_out <= ad(30 downto 0) & pc(31) WHEN B"11", + alu_out WHEN B"01", + ad WHEN OTHERS; + + ws_ad:BLOCK(ck='1' AND NOT ck'STABLE) + BEGIN + ad <= GUARDED ad_mux_out; + END BLOCK ws_ad; + + -- ******************* EPC register Description ******************* + + WITH test & epc_wen SELECT + epc_mux_out <= epc(30 downto 0) & ad(31) WHEN B"11", + alu_out WHEN B"01", + epc WHEN OTHERS; + + ws_epc:BLOCK(ck='1' AND NOT ck'STABLE) + BEGIN + epc <= GUARDED epc_mux_out; + END BLOCK ws_epc; + + -- ******************* BAR register Description ******************* + + WITH test & bar_wen SELECT + bar_mux_out <= bar(30 downto 0) & epc(31) WHEN B"11", + alu_out WHEN B"01", + bar WHEN OTHERS; + + ws_bar:BLOCK(ck='1' AND NOT ck'STABLE) + BEGIN + bar <= GUARDED bar_mux_out; + END BLOCK ws_bar; + + -- ******************* SR/CR register Description ******************* + + sr_s <= X"0000" & crsr_sts_in; + cr_s <= X"0000" & crsr_sts_in; + crsr_dpt_out <= alu_out(15 downto 0); + + -- ******************* HI register Description ******************* + + WITH test & hi_wen SELECT + hi_mux_out <= hi(30 downto 0) & bar(31) WHEN B"11", + alu_out WHEN B"01", + hi WHEN OTHERS; + + ws_hi:BLOCK(ck='1' AND NOT ck'STABLE) + BEGIN + hi <= GUARDED hi_mux_out; + END BLOCK ws_hi; + + -- ******************* LO register Description ******************* + + WITH test & lo_wen SELECT + lo_mux_out <= lo(30 downto 0) & hi(31) WHEN B"11", + alu_out WHEN B"01", + lo WHEN OTHERS; + + ws_lo:BLOCK(ck='1' AND NOT ck'STABLE) + BEGIN + lo <= GUARDED lo_mux_out; + END BLOCK ws_lo; + + -- ******************* IR register Description ******************* + + WITH test & ir_wen SELECT + ir_mux_out <= ir(30 downto 0) & lo(31) WHEN B"11", + not data_in_n WHEN B"01", + ir WHEN OTHERS; + + ws_ir:BLOCK(ck='1' AND NOT ck'STABLE) + BEGIN + ir <= GUARDED ir_mux_out; + END BLOCK ws_ir; + + -- ******************* DT register Description ******************* + + WITH test & dt_wen SELECT + dt_mux_out <= dt(30 downto 0) & ir(31) WHEN B"11", + opy_dt WHEN B"01", + dt WHEN OTHERS; + + ws_dt:BLOCK(ck='1' AND NOT ck'STABLE) + BEGIN + dt <= GUARDED dt_mux_out; + END BLOCK ws_dt; + + dpt_scout <= dt(31); + + -- *************** register File (RF) Description **************** + + rf_aw_wenabled <= rf_aw & rf_wen; + + + wm_rf:BLOCK(ck = '1' AND NOT ck'STABLE) + BEGIN + rf_1 <= GUARDED alu_out WHEN rf_aw_wenabled = B"000011" ELSE rf_1; + rf_2 <= GUARDED alu_out WHEN rf_aw_wenabled = B"000101" ELSE rf_2; + rf_3 <= GUARDED alu_out WHEN rf_aw_wenabled = B"000111" ELSE rf_3; + rf_4 <= GUARDED alu_out WHEN rf_aw_wenabled = B"001001" ELSE rf_4; + rf_5 <= GUARDED alu_out WHEN rf_aw_wenabled = B"001011" ELSE rf_5; + rf_6 <= GUARDED alu_out WHEN rf_aw_wenabled = B"001101" ELSE rf_6; + rf_7 <= GUARDED alu_out WHEN rf_aw_wenabled = B"001111" ELSE rf_7; + rf_8 <= GUARDED alu_out WHEN rf_aw_wenabled = B"010001" ELSE rf_8; + rf_9 <= GUARDED alu_out WHEN rf_aw_wenabled = B"010011" ELSE rf_9; + rf_10 <= GUARDED alu_out WHEN rf_aw_wenabled = B"010101" ELSE rf_10; + rf_11 <= GUARDED alu_out WHEN rf_aw_wenabled = B"010111" ELSE rf_11; + rf_12 <= GUARDED alu_out WHEN rf_aw_wenabled = B"011001" ELSE rf_12; + rf_13 <= GUARDED alu_out WHEN rf_aw_wenabled = B"011011" ELSE rf_13; + rf_14 <= GUARDED alu_out WHEN rf_aw_wenabled = B"011101" ELSE rf_14; + rf_15 <= GUARDED alu_out WHEN rf_aw_wenabled = B"011111" ELSE rf_15; + rf_16 <= GUARDED alu_out WHEN rf_aw_wenabled = B"100001" ELSE rf_16; + rf_17 <= GUARDED alu_out WHEN rf_aw_wenabled = B"100011" ELSE rf_17; + rf_18 <= GUARDED alu_out WHEN rf_aw_wenabled = B"100101" ELSE rf_18; + rf_19 <= GUARDED alu_out WHEN rf_aw_wenabled = B"100111" ELSE rf_19; + rf_20 <= GUARDED alu_out WHEN rf_aw_wenabled = B"101001" ELSE rf_20; + rf_21 <= GUARDED alu_out WHEN rf_aw_wenabled = B"101011" ELSE rf_21; + rf_22 <= GUARDED alu_out WHEN rf_aw_wenabled = B"101101" ELSE rf_22; + rf_23 <= GUARDED alu_out WHEN rf_aw_wenabled = B"101111" ELSE rf_23; + rf_24 <= GUARDED alu_out WHEN rf_aw_wenabled = B"110001" ELSE rf_24; + rf_25 <= GUARDED alu_out WHEN rf_aw_wenabled = B"110011" ELSE rf_25; + rf_26 <= GUARDED alu_out WHEN rf_aw_wenabled = B"110101" ELSE rf_26; + rf_27 <= GUARDED alu_out WHEN rf_aw_wenabled = B"110111" ELSE rf_27; + rf_28 <= GUARDED alu_out WHEN rf_aw_wenabled = B"111001" ELSE rf_28; + rf_29 <= GUARDED alu_out WHEN rf_aw_wenabled = B"111011" ELSE rf_29; + rf_30 <= GUARDED alu_out WHEN rf_aw_wenabled = B"111101" ELSE rf_30; + rf_31 <= GUARDED alu_out WHEN rf_aw_wenabled = B"111111" ELSE rf_31; + END BLOCK wm_rf; + + WITH rf_ar SELECT + rf_o <= X"00000000" WHEN B"00000", + rf_1 WHEN B"00001", + rf_2 WHEN B"00010", + rf_3 WHEN B"00011", + rf_4 WHEN B"00100", + rf_5 WHEN B"00101", + rf_6 WHEN B"00110", + rf_7 WHEN B"00111", + rf_8 WHEN B"01000", + rf_9 WHEN B"01001", + rf_10 WHEN B"01010", + rf_11 WHEN B"01011", + rf_12 WHEN B"01100", + rf_13 WHEN B"01101", + rf_14 WHEN B"01110", + rf_15 WHEN B"01111", + rf_16 WHEN B"10000", + rf_17 WHEN B"10001", + rf_18 WHEN B"10010", + rf_19 WHEN B"10011", + rf_20 WHEN B"10100", + rf_21 WHEN B"10101", + rf_22 WHEN B"10110", + rf_23 WHEN B"10111", + rf_24 WHEN B"11000", + rf_25 WHEN B"11001", + rf_26 WHEN B"11010", + rf_27 WHEN B"11011", + rf_28 WHEN B"11100", + rf_29 WHEN B"11101", + rf_30 WHEN B"11110", + rf_31 WHEN B"11111"; +END fonctional; + + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_scan.c b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_scan.c new file mode 100644 index 00000000..b14892d5 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_scan.c @@ -0,0 +1,747 @@ +#include +#include "genpat.h" + +#define UNIT_TIME 50 + +char *inttostr(entier) +int entier; +{ + char *str; + str = (char *) mbkalloc (32 * sizeof (char)); + sprintf (str, "%d",entier); + return(str); +} + +main () +{ +int i; +int j; +int vect_date=0; /* this date is an absolute date, in ps */ +int decalage; /* conservation de vect_date */ + + +/* WARNING : begin by the end */ +int tab_in[] = +{ +0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, /* dt */ //32 +0,0,1,1,0,1, 0,0,0,0,0, 0,0,0,1,0, 0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1, /* ir */ //32 +0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, /* lo */ //32 +0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, /* hi */ //32 +0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, /* bar */ //32 +0,0,0,0, 0,0,0,0, 0,1,0,0, 1,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, /* epc */ //32 +0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, /* ad */ //32 +0,0,0,0, 0,0,0,0, 0,1,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, /* pc */ //32 +1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, +0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, +0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ep */ //99 +0, /* ovf */ // 1 +0, /* ibe */ // 1 +0, /* ri */ // 1 +0, /* dbe */ // 1 +0, /* adel */ // 1 +0, /* cpu */ // 1 +0, /* ades */ // 1 +0, /* intrqs_sys */ // 1 +0, /* intrqs_br */ // 1 +0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, /* cr */ //16 +0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0 /* sr */ //16 +}; //396 + +int tab_out[] = +{ +0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, /* dt */ //32 +0,0,1,1,0,1, 0,0,0,0,0, 0,0,0,1,0, 0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1, /* ir */ //32 +0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, /* lo */ //32 +0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, /* hi */ //32 +0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, /* bar */ //32 +0,0,0,0, 0,0,0,0, 0,1,0,0, 1,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, /* epc */ //32 +0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 1,1,1,1, 0,0,0,0, 1,1,1,1, /* ad */ //32 +0,0,0,0, 0,0,0,0, 0,1,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,1,0,0, /* pc */ //32 +0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, +0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, +0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ep */ //99 +0, /* ovf */ // 1 +0, /* ibe */ // 1 +0, /* ri */ // 1 +0, /* dbe */ // 1 +0, /* adel */ // 1 +0, /* cpu */ // 1 +0, /* ades */ // 1 +0, /* intrqs_sys */ // 1 +0, /* intrqs_br */ // 1 +0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cr */ //16 +0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 /* sr */ //16 +}; //396 + + +DEF_GENPAT("mips_scan"); + +SETTUNIT ("ns"); + +/* interface */ + +DECLAR ("vdd",":2","B",IN,"",""); +DECLAR ("vss",":2","B",IN,"",""); +DECLAR ("ck", ":2", "B", IN, "", ""); +DECLAR ("reset", ":2", "B", IN, "", ""); +DECLAR ("frz", ":2", "B", IN, "", ""); +DECLAR ("test", ":2", "B", IN, "", ""); +DECLAR ("scin",":2","B",IN,"",""); +DECLAR ("scout",":2","B",OUT,"",""); + +ARRAY ( + "mips1.core.dpt.dt_31", + "mips1.core.dpt.dt_30", + "mips1.core.dpt.dt_29", + "mips1.core.dpt.dt_28", + "mips1.core.dpt.dt_27", + "mips1.core.dpt.dt_26", + "mips1.core.dpt.dt_25", + "mips1.core.dpt.dt_24", + "mips1.core.dpt.dt_23", + "mips1.core.dpt.dt_22", + "mips1.core.dpt.dt_21", + "mips1.core.dpt.dt_20", + "mips1.core.dpt.dt_19", + "mips1.core.dpt.dt_18", + "mips1.core.dpt.dt_17", + "mips1.core.dpt.dt_16", + "mips1.core.dpt.dt_15", + "mips1.core.dpt.dt_14", + "mips1.core.dpt.dt_13", + "mips1.core.dpt.dt_12", + "mips1.core.dpt.dt_11", + "mips1.core.dpt.dt_10", + "mips1.core.dpt.dt_9", + "mips1.core.dpt.dt_8", + "mips1.core.dpt.dt_7", + "mips1.core.dpt.dt_6", + "mips1.core.dpt.dt_5", + "mips1.core.dpt.dt_4", + "mips1.core.dpt.dt_3", + "mips1.core.dpt.dt_2", + "mips1.core.dpt.dt_1", + "mips1.core.dpt.dt_0", + ":1","X",SIGNAL,"","dt",0); + + +ARRAY ( + "mips1.core.dpt.ir_31", + "mips1.core.dpt.ir_30", + "mips1.core.dpt.ir_29", + "mips1.core.dpt.ir_28", + "mips1.core.dpt.ir_27", + "mips1.core.dpt.ir_26", + "mips1.core.dpt.ir_25", + "mips1.core.dpt.ir_24", + "mips1.core.dpt.ir_23", + "mips1.core.dpt.ir_22", + "mips1.core.dpt.ir_21", + "mips1.core.dpt.ir_20", + "mips1.core.dpt.ir_19", + "mips1.core.dpt.ir_18", + "mips1.core.dpt.ir_17", + "mips1.core.dpt.ir_16", + "mips1.core.dpt.ir_15", + "mips1.core.dpt.ir_14", + "mips1.core.dpt.ir_13", + "mips1.core.dpt.ir_12", + "mips1.core.dpt.ir_11", + "mips1.core.dpt.ir_10", + "mips1.core.dpt.ir_9", + "mips1.core.dpt.ir_8", + "mips1.core.dpt.ir_7", + "mips1.core.dpt.ir_6", + "mips1.core.dpt.ir_5", + "mips1.core.dpt.ir_4", + "mips1.core.dpt.ir_3", + "mips1.core.dpt.ir_2", + "mips1.core.dpt.ir_1", + "mips1.core.dpt.ir_0", + ":1","X",SIGNAL,"","ir",0); + +ARRAY ( + "mips1.core.dpt.lo_31", + "mips1.core.dpt.lo_30", + "mips1.core.dpt.lo_29", + "mips1.core.dpt.lo_28", + "mips1.core.dpt.lo_27", + "mips1.core.dpt.lo_26", + "mips1.core.dpt.lo_25", + "mips1.core.dpt.lo_24", + "mips1.core.dpt.lo_23", + "mips1.core.dpt.lo_22", + "mips1.core.dpt.lo_21", + "mips1.core.dpt.lo_20", + "mips1.core.dpt.lo_19", + "mips1.core.dpt.lo_18", + "mips1.core.dpt.lo_17", + "mips1.core.dpt.lo_16", + "mips1.core.dpt.lo_15", + "mips1.core.dpt.lo_14", + "mips1.core.dpt.lo_13", + "mips1.core.dpt.lo_12", + "mips1.core.dpt.lo_11", + "mips1.core.dpt.lo_10", + "mips1.core.dpt.lo_9", + "mips1.core.dpt.lo_8", + "mips1.core.dpt.lo_7", + "mips1.core.dpt.lo_6", + "mips1.core.dpt.lo_5", + "mips1.core.dpt.lo_4", + "mips1.core.dpt.lo_3", + "mips1.core.dpt.lo_2", + "mips1.core.dpt.lo_1", + "mips1.core.dpt.lo_0", + ":1","X",SIGNAL,"","lo",0); + +ARRAY ( + "mips1.core.dpt.hi_31", + "mips1.core.dpt.hi_30", + "mips1.core.dpt.hi_29", + "mips1.core.dpt.hi_28", + "mips1.core.dpt.hi_27", + "mips1.core.dpt.hi_26", + "mips1.core.dpt.hi_25", + "mips1.core.dpt.hi_24", + "mips1.core.dpt.hi_23", + "mips1.core.dpt.hi_22", + "mips1.core.dpt.hi_21", + "mips1.core.dpt.hi_20", + "mips1.core.dpt.hi_19", + "mips1.core.dpt.hi_18", + "mips1.core.dpt.hi_17", + "mips1.core.dpt.hi_16", + "mips1.core.dpt.hi_15", + "mips1.core.dpt.hi_14", + "mips1.core.dpt.hi_13", + "mips1.core.dpt.hi_12", + "mips1.core.dpt.hi_11", + "mips1.core.dpt.hi_10", + "mips1.core.dpt.hi_9", + "mips1.core.dpt.hi_8", + "mips1.core.dpt.hi_7", + "mips1.core.dpt.hi_6", + "mips1.core.dpt.hi_5", + "mips1.core.dpt.hi_4", + "mips1.core.dpt.hi_3", + "mips1.core.dpt.hi_2", + "mips1.core.dpt.hi_1", + "mips1.core.dpt.hi_0", + ":1","X",SIGNAL,"","hi",0); + +ARRAY ( + "mips1.core.dpt.bar_31", + "mips1.core.dpt.bar_30", + "mips1.core.dpt.bar_29", + "mips1.core.dpt.bar_28", + "mips1.core.dpt.bar_27", + "mips1.core.dpt.bar_26", + "mips1.core.dpt.bar_25", + "mips1.core.dpt.bar_24", + "mips1.core.dpt.bar_23", + "mips1.core.dpt.bar_22", + "mips1.core.dpt.bar_21", + "mips1.core.dpt.bar_20", + "mips1.core.dpt.bar_19", + "mips1.core.dpt.bar_18", + "mips1.core.dpt.bar_17", + "mips1.core.dpt.bar_16", + "mips1.core.dpt.bar_15", + "mips1.core.dpt.bar_14", + "mips1.core.dpt.bar_13", + "mips1.core.dpt.bar_12", + "mips1.core.dpt.bar_11", + "mips1.core.dpt.bar_10", + "mips1.core.dpt.bar_9", + "mips1.core.dpt.bar_8", + "mips1.core.dpt.bar_7", + "mips1.core.dpt.bar_6", + "mips1.core.dpt.bar_5", + "mips1.core.dpt.bar_4", + "mips1.core.dpt.bar_3", + "mips1.core.dpt.bar_2", + "mips1.core.dpt.bar_1", + "mips1.core.dpt.bar_0", + ":1","X",SIGNAL,"","bar",0); + +ARRAY ( + "mips1.core.dpt.epc_31", + "mips1.core.dpt.epc_30", + "mips1.core.dpt.epc_29", + "mips1.core.dpt.epc_28", + "mips1.core.dpt.epc_27", + "mips1.core.dpt.epc_26", + "mips1.core.dpt.epc_25", + "mips1.core.dpt.epc_24", + "mips1.core.dpt.epc_23", + "mips1.core.dpt.epc_22", + "mips1.core.dpt.epc_21", + "mips1.core.dpt.epc_20", + "mips1.core.dpt.epc_19", + "mips1.core.dpt.epc_18", + "mips1.core.dpt.epc_17", + "mips1.core.dpt.epc_16", + "mips1.core.dpt.epc_15", + "mips1.core.dpt.epc_14", + "mips1.core.dpt.epc_13", + "mips1.core.dpt.epc_12", + "mips1.core.dpt.epc_11", + "mips1.core.dpt.epc_10", + "mips1.core.dpt.epc_9", + "mips1.core.dpt.epc_8", + "mips1.core.dpt.epc_7", + "mips1.core.dpt.epc_6", + "mips1.core.dpt.epc_5", + "mips1.core.dpt.epc_4", + "mips1.core.dpt.epc_3", + "mips1.core.dpt.epc_2", + "mips1.core.dpt.epc_1", + "mips1.core.dpt.epc_0", + ":1","X",SIGNAL,"","epc",0); + +ARRAY ( + "mips1.core.dpt.ad_31", + "mips1.core.dpt.ad_30", + "mips1.core.dpt.ad_29", + "mips1.core.dpt.ad_28", + "mips1.core.dpt.ad_27", + "mips1.core.dpt.ad_26", + "mips1.core.dpt.ad_25", + "mips1.core.dpt.ad_24", + "mips1.core.dpt.ad_23", + "mips1.core.dpt.ad_22", + "mips1.core.dpt.ad_21", + "mips1.core.dpt.ad_20", + "mips1.core.dpt.ad_19", + "mips1.core.dpt.ad_18", + "mips1.core.dpt.ad_17", + "mips1.core.dpt.ad_16", + "mips1.core.dpt.ad_15", + "mips1.core.dpt.ad_14", + "mips1.core.dpt.ad_13", + "mips1.core.dpt.ad_12", + "mips1.core.dpt.ad_11", + "mips1.core.dpt.ad_10", + "mips1.core.dpt.ad_9", + "mips1.core.dpt.ad_8", + "mips1.core.dpt.ad_7", + "mips1.core.dpt.ad_6", + "mips1.core.dpt.ad_5", + "mips1.core.dpt.ad_4", + "mips1.core.dpt.ad_3", + "mips1.core.dpt.ad_2", + "mips1.core.dpt.ad_1", + "mips1.core.dpt.ad_0", + ":1","X",SIGNAL,"","ad",0); + +ARRAY ( + "mips1.core.dpt.pc_31", + "mips1.core.dpt.pc_30", + "mips1.core.dpt.pc_29", + "mips1.core.dpt.pc_28", + "mips1.core.dpt.pc_27", + "mips1.core.dpt.pc_26", + "mips1.core.dpt.pc_25", + "mips1.core.dpt.pc_24", + "mips1.core.dpt.pc_23", + "mips1.core.dpt.pc_22", + "mips1.core.dpt.pc_21", + "mips1.core.dpt.pc_20", + "mips1.core.dpt.pc_19", + "mips1.core.dpt.pc_18", + "mips1.core.dpt.pc_17", + "mips1.core.dpt.pc_16", + "mips1.core.dpt.pc_15", + "mips1.core.dpt.pc_14", + "mips1.core.dpt.pc_13", + "mips1.core.dpt.pc_12", + "mips1.core.dpt.pc_11", + "mips1.core.dpt.pc_10", + "mips1.core.dpt.pc_9", + "mips1.core.dpt.pc_8", + "mips1.core.dpt.pc_7", + "mips1.core.dpt.pc_6", + "mips1.core.dpt.pc_5", + "mips1.core.dpt.pc_4", + "mips1.core.dpt.pc_3", + "mips1.core.dpt.pc_2", + "mips1.core.dpt.pc_1", + "mips1.core.dpt.pc_0", + ":1","X",SIGNAL,"","pc",0); + +ARRAY ( + "mips1.core.ctl.seq_ep_98", + "mips1.core.ctl.seq_ep_97", + "mips1.core.ctl.seq_ep_96", + "mips1.core.ctl.seq_ep_95", + "mips1.core.ctl.seq_ep_94", + "mips1.core.ctl.seq_ep_93", + "mips1.core.ctl.seq_ep_92", + "mips1.core.ctl.seq_ep_91", + "mips1.core.ctl.seq_ep_90", + "mips1.core.ctl.seq_ep_89", + "mips1.core.ctl.seq_ep_88", + "mips1.core.ctl.seq_ep_87", +// "mips1.core.ctl.seq_ep_86", +// "mips1.core.ctl.seq_ep_85", +// "mips1.core.ctl.seq_ep_84", +// "mips1.core.ctl.seq_ep_83", +// "mips1.core.ctl.seq_ep_82", +// "mips1.core.ctl.seq_ep_81", +// "mips1.core.ctl.seq_ep_80", +// "mips1.core.ctl.seq_ep_79", +// "mips1.core.ctl.seq_ep_78", +// "mips1.core.ctl.seq_ep_77", +// "mips1.core.ctl.seq_ep_76", +// "mips1.core.ctl.seq_ep_75", +// "mips1.core.ctl.seq_ep_74", +// "mips1.core.ctl.seq_ep_73", +// "mips1.core.ctl.seq_ep_72", +// "mips1.core.ctl.seq_ep_71", +// "mips1.core.ctl.seq_ep_70", +// "mips1.core.ctl.seq_ep_69", +// "mips1.core.ctl.seq_ep_68", +// "mips1.core.ctl.seq_ep_67", +// "mips1.core.ctl.seq_ep_66", +// "mips1.core.ctl.seq_ep_65", +// "mips1.core.ctl.seq_ep_64", +// "mips1.core.ctl.seq_ep_63", +// "mips1.core.ctl.seq_ep_62", +// "mips1.core.ctl.seq_ep_61", +// "mips1.core.ctl.seq_ep_60", +// "mips1.core.ctl.seq_ep_59", +// "mips1.core.ctl.seq_ep_58", +// "mips1.core.ctl.seq_ep_57", +// "mips1.core.ctl.seq_ep_56", +// "mips1.core.ctl.seq_ep_55", +// "mips1.core.ctl.seq_ep_54", +// "mips1.core.ctl.seq_ep_53", +// "mips1.core.ctl.seq_ep_52", +// "mips1.core.ctl.seq_ep_51", +// "mips1.core.ctl.seq_ep_50", +// "mips1.core.ctl.seq_ep_49", +// "mips1.core.ctl.seq_ep_48", +// "mips1.core.ctl.seq_ep_47", +// "mips1.core.ctl.seq_ep_46", +// "mips1.core.ctl.seq_ep_45", +// "mips1.core.ctl.seq_ep_44", +// "mips1.core.ctl.seq_ep_43", +// "mips1.core.ctl.seq_ep_42", +// "mips1.core.ctl.seq_ep_41", +// "mips1.core.ctl.seq_ep_40", +// "mips1.core.ctl.seq_ep_39", +// "mips1.core.ctl.seq_ep_38", +// "mips1.core.ctl.seq_ep_37", +// "mips1.core.ctl.seq_ep_36", +// "mips1.core.ctl.seq_ep_35", +// "mips1.core.ctl.seq_ep_34", +// "mips1.core.ctl.seq_ep_33", +// "mips1.core.ctl.seq_ep_32", +// "mips1.core.ctl.seq_ep_31", +// "mips1.core.ctl.seq_ep_30", +// "mips1.core.ctl.seq_ep_29", +// "mips1.core.ctl.seq_ep_28", +// "mips1.core.ctl.seq_ep_27", +// "mips1.core.ctl.seq_ep_26", +// "mips1.core.ctl.seq_ep_25", +// "mips1.core.ctl.seq_ep_24", +// "mips1.core.ctl.seq_ep_23", +// "mips1.core.ctl.seq_ep_22", +// "mips1.core.ctl.seq_ep_21", +// "mips1.core.ctl.seq_ep_20", +// "mips1.core.ctl.seq_ep_19", +// "mips1.core.ctl.seq_ep_18", +// "mips1.core.ctl.seq_ep_17", +// "mips1.core.ctl.seq_ep_16", +// "mips1.core.ctl.seq_ep_15", +// "mips1.core.ctl.seq_ep_14", +// "mips1.core.ctl.seq_ep_13", +// "mips1.core.ctl.seq_ep_12", +// "mips1.core.ctl.seq_ep_11", +// "mips1.core.ctl.seq_ep_10", +// "mips1.core.ctl.seq_ep_9", +// "mips1.core.ctl.seq_ep_8", +// +// "mips1.core.ctl.seq_ep_7", +// "mips1.core.ctl.seq_ep_6", +// "mips1.core.ctl.seq_ep_5", +// "mips1.core.ctl.seq_ep_4", + // "mips1.core.ctl.seq_ep_3", + // "mips1.core.ctl.seq_ep_2", + // "mips1.core.ctl.seq_ep_1", + // "mips1.core.ctl.seq_ep_0", + ":1","B",SIGNAL,"","ep",0); + + +DECLAR ("mips1.core.ctl.sts_ovf_r",":1","B",SIGNAL,"",""); +DECLAR ("mips1.core.ctl.sts_ibe_r",":1","B",SIGNAL,"",""); +DECLAR ("mips1.core.ctl.sts_ri_r",":1","B",SIGNAL,"",""); +DECLAR ("mips1.core.ctl.sts_dbe_r",":1","B",SIGNAL,"",""); +DECLAR ("mips1.core.ctl.sts_adel_r",":1","B",SIGNAL,"",""); +DECLAR ("mips1.core.ctl.sts_cpu_r",":1","B",SIGNAL,"",""); +DECLAR ("mips1.core.ctl.sts_ades_r",":1","B",SIGNAL,"",""); +DECLAR ("mips1.core.ctl.sts_intrqs_sys_r",":1","B",SIGNAL,"",""); +DECLAR ("mips1.core.ctl.sts_intrqs_br_r",":1","B",SIGNAL,"",""); + +ARRAY ( + "mips1.core.ctl.sts_cr_s_15", + "mips1.core.ctl.sts_cr_s_14", + "mips1.core.ctl.sts_cr_s_13", + "mips1.core.ctl.sts_cr_s_12", + "mips1.core.ctl.sts_cr_s_11", + "mips1.core.ctl.sts_cr_s_10", + "mips1.core.ctl.sts_cr_s_9", + "mips1.core.ctl.sts_cr_s_8", + "mips1.core.ctl.sts_cr_s_7", + "mips1.core.ctl.sts_cr_s_6", + "mips1.core.ctl.sts_cr_s_5", + "mips1.core.ctl.sts_cr_s_4", + "mips1.core.ctl.sts_cr_s_3", + "mips1.core.ctl.sts_cr_s_2", + "mips1.core.ctl.sts_cr_s_1", + "mips1.core.ctl.sts_cr_s_0", + ":1","X",SIGNAL,"","cr",0); + + +ARRAY ( + "mips1.core.ctl.sts_sr_s_15", + "mips1.core.ctl.sts_sr_s_14", + "mips1.core.ctl.sts_sr_s_13", + "mips1.core.ctl.sts_sr_s_12", + "mips1.core.ctl.sts_sr_s_11", + "mips1.core.ctl.sts_sr_s_10", + "mips1.core.ctl.sts_sr_s_9", + "mips1.core.ctl.sts_sr_s_8", + "mips1.core.ctl.sts_sr_s_7", + "mips1.core.ctl.sts_sr_s_6", + "mips1.core.ctl.sts_sr_s_5", + "mips1.core.ctl.sts_sr_s_4", + "mips1.core.ctl.sts_sr_s_3", + "mips1.core.ctl.sts_sr_s_2", + "mips1.core.ctl.sts_sr_s_1", + "mips1.core.ctl.sts_sr_s_0", + ":1","X",SIGNAL,"","sr",0); + +ARRAY ( + "mips1.core.dpt.rf_o_31", + "mips1.core.dpt.rf_o_30", + "mips1.core.dpt.rf_o_29", + "mips1.core.dpt.rf_o_28", + "mips1.core.dpt.rf_o_27", + "mips1.core.dpt.rf_o_26", + "mips1.core.dpt.rf_o_25", + "mips1.core.dpt.rf_o_24", + "mips1.core.dpt.rf_o_23", + "mips1.core.dpt.rf_o_22", + "mips1.core.dpt.rf_o_21", + "mips1.core.dpt.rf_o_20", + "mips1.core.dpt.rf_o_19", + "mips1.core.dpt.rf_o_18", + "mips1.core.dpt.rf_o_17", + "mips1.core.dpt.rf_o_16", + "mips1.core.dpt.rf_o_15", + "mips1.core.dpt.rf_o_14", + "mips1.core.dpt.rf_o_13", + "mips1.core.dpt.rf_o_12", + "mips1.core.dpt.rf_o_11", + "mips1.core.dpt.rf_o_10", + "mips1.core.dpt.rf_o_9", + "mips1.core.dpt.rf_o_8", + "mips1.core.dpt.rf_o_7", + "mips1.core.dpt.rf_o_6", + "mips1.core.dpt.rf_o_5", + "mips1.core.dpt.rf_o_4", + "mips1.core.dpt.rf_o_3", + "mips1.core.dpt.rf_o_2", + "mips1.core.dpt.rf_o_1", + ":1","B",SIGNAL,"","rf",0); + + + +DECLAR ("rw",":2","B",OUT,"",""); +DECLAR ("w",":2","B",OUT,"1 DOWNTO 0",""); +DECLAR ("data", ":2", "X", INOUT, "31 DOWNTO 0", ""); +DECLAR ("data_adr", ":2", "X", INOUT, "31 DOWNTO 0", ""); + + + +//ARRAY ( +// "mips1.core.dpt.dt_31", +// "mips1.core.dpt.dt_30", +// "mips1.core.dpt.dt_29", +// "mips1.core.dpt.dt_28", +// "mips1.core.dpt.dt_27", +// "mips1.core.dpt.dt_26", +// "mips1.core.dpt.dt_25", +// "mips1.core.dpt.dt_24", +// "mips1.core.dpt.dt_23", +// "mips1.core.dpt.dt_22", +// "mips1.core.dpt.dt_21", +// "mips1.core.dpt.dt_20", +// "mips1.core.dpt.dt_19", +// "mips1.core.dpt.dt_18", +// "mips1.core.dpt.dt_17", +// "mips1.core.dpt.dt_16", +// "mips1.core.dpt.dt_15", +// "mips1.core.dpt.dt_14", +// "mips1.core.dpt.dt_13", +// "mips1.core.dpt.dt_12", +// "mips1.core.dpt.dt_11", +// "mips1.core.dpt.dt_10", +// "mips1.core.dpt.dt_9", +// "mips1.core.dpt.dt_8", +// "mips1.core.dpt.dt_7", +// "mips1.core.dpt.dt_6", +// "mips1.core.dpt.dt_5", +// "mips1.core.dpt.dt_4", +// "mips1.core.dpt.dt_3", +// "mips1.core.dpt.dt_2", +// "mips1.core.dpt.dt_1", +// "mips1.core.dpt.dt_0", +// ":1","X",SIGNAL,"","dt",0); + + AFFECT ("0", "vdd", "0b1"); + AFFECT ("0", "vss", "0b0"); + AFFECT ("0", "frz", "0b0"); + AFFECT ("0", "test", "0b0"); + AFFECT ("0","reset","0b1"); + AFFECT ("0", "ck", "0b1"); + AFFECT ("0", "scin", "0b0"); + + vect_date += UNIT_TIME; + AFFECT (inttostr(vect_date), "ck", "0b0"); + vect_date += UNIT_TIME; + AFFECT (inttostr(vect_date), "ck", "0b1"); + vect_date += UNIT_TIME; + AFFECT (inttostr(vect_date), "ck", "0b0"); + +for (i=2;i<42;i++) +{ + vect_date=(i*2)*UNIT_TIME; + AFFECT (inttostr(vect_date),"reset","0b0"); + AFFECT (inttostr(vect_date), "ck", "0b1"); + vect_date=(i*2+1)*UNIT_TIME; + AFFECT (inttostr(vect_date), "ck", "0b0"); +} + +LABEL("fin de reset"); + +decalage = vect_date + UNIT_TIME; +AFFECT (inttostr(decalage), "test", "0b1"); + +for (i=0;i<396;i++) +{ + vect_date = ( 2 * i ) * UNIT_TIME + decalage; + AFFECT (inttostr(vect_date), "ck", "0b0"); + AFFECT (inttostr(vect_date), "scin", inttostr(tab_in[i]) ); + + vect_date = ( 2 * i + 1) * UNIT_TIME + decalage; + AFFECT (inttostr(vect_date), "ck", "0b1"); + AFFECT (inttostr(vect_date), "scin", inttostr(tab_in[i]) ); + +} +LABEL("fin_de_l_init"); + +vect_date += UNIT_TIME; +/* on fait un cycle */ + +AFFECT (inttostr(vect_date), "test", "0b0"); +AFFECT (inttostr(vect_date), "scin", "0b0"); +AFFECT (inttostr(vect_date), "ck", "0b0"); + +vect_date += UNIT_TIME; +AFFECT (inttostr(vect_date), "ck", "0b1"); + +vect_date += UNIT_TIME; +AFFECT (inttostr(vect_date), "ck", "0b0"); +vect_date += UNIT_TIME; +AFFECT (inttostr(vect_date), "ck", "0b1"); + +LABEL("fin_du_cycle"); + +decalage = vect_date + UNIT_TIME; + +for (i=0;i<396;i++) +{ + if (i == 0) AFFECT (inttostr(( 2 * i ) * UNIT_TIME + decalage), "test", "0b1"); + vect_date = ( 2 * i ) * UNIT_TIME + decalage; + AFFECT (inttostr(vect_date), "ck", "0b0"); + AFFECT (inttostr(vect_date), "scout", inttostr(tab_out[i]) ); + + vect_date = ( 2 * i + 1) * UNIT_TIME + decalage; + AFFECT (inttostr(vect_date), "ck", "0b1"); + AFFECT (inttostr(vect_date), "scout", inttostr(tab_out[i+1]) ); + +} + + + + + + + + + + + + + + + + +/* +for (i=0; i<16; i++) + for (j=0; j<16; j++) + { + vect_date = 2 * (i*16 + j) * UNIT_TIME; + AFFECT (inttostr(vect_date), "ck", "0b0"); + AFFECT (inttostr(vect_date), "a", inttostr(i)); + AFFECT (inttostr(vect_date), "b", inttostr(j)); + + vect_date = (2 * (i*16 + j) + 1) * UNIT_TIME; + AFFECT (inttostr(vect_date), "ck", "0b1"); + AFFECT (inttostr(vect_date), "a", inttostr(i)); + AFFECT (inttostr(vect_date), "b", inttostr(j)); + } + +vect_date += UNIT_TIME; +orig_vect_date = vect_date; + +AFFECT (inttostr(vect_date), "sel", "0b1"); +AFFECT (inttostr(vect_date), "b", "0b1"); + + +for (i=0; i<16; i++) +{ + vect_date = (2 * i) * UNIT_TIME + orig_vect_date; + AFFECT (inttostr(vect_date), "ck", "0b0"); + AFFECT (inttostr(vect_date), "a", inttostr(i)); + + vect_date = (2 * i + 1) * UNIT_TIME + orig_vect_date; + AFFECT (inttostr(vect_date), "ck", "0b1"); + AFFECT (inttostr(vect_date), "a", inttostr(i)); + +} + +vect_date += UNIT_TIME ; +orig_vect_date = vect_date; + +AFFECT (inttostr(vect_date), "sel", "0b1"); +AFFECT (inttostr(vect_date), "a", "0b1"); + +for (i=0; i<16; i++) +{ + vect_date = (2 * i) * UNIT_TIME + orig_vect_date; + AFFECT (inttostr(vect_date), "ck", "0b0"); + AFFECT (inttostr(vect_date), "b", inttostr(i)); + + vect_date = (2 * i + 1) * UNIT_TIME + orig_vect_date; + AFFECT (inttostr(vect_date), "ck", "0b1"); + AFFECT (inttostr(vect_date), "b", inttostr(i)); +}*/ + +SAV_GENPAT (); +exit(0); +} + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_scan.pat b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_scan.pat new file mode 100644 index 00000000..46a791b7 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_scan.pat @@ -0,0 +1,1756 @@ + +-- description generated by Pat driver + +-- date : Wed Nov 14 17:15:10 2001 +-- revision : v109 + +-- sequence : mips_scan + +-- input / output list : +in vdd B;;; +in vss B;;; +in ck B;;; +in reset B;;; +in frz B;;; +in test B;;; +in scin B;;; +out scout B;;; +signal dt ( mips1.core.dpt.dt_31, mips1.core.dpt.dt_30, mips1.core.dpt.dt_29, mips1.core.dpt.dt_28, mips1.core.dpt.dt_27, mips1.core.dpt.dt_26, mips1.core.dpt.dt_25, mips1.core.dpt.dt_24, mips1.core.dpt.dt_23, mips1.core.dpt.dt_22, mips1.core.dpt.dt_21, mips1.core.dpt.dt_20, mips1.core.dpt.dt_19, mips1.core.dpt.dt_18, mips1.core.dpt.dt_17, mips1.core.dpt.dt_16, mips1.core.dpt.dt_15, mips1.core.dpt.dt_14, mips1.core.dpt.dt_13, mips1.core.dpt.dt_12, mips1.core.dpt.dt_11, mips1.core.dpt.dt_10, mips1.core.dpt.dt_9, mips1.core.dpt.dt_8, mips1.core.dpt.dt_7, mips1.core.dpt.dt_6, mips1.core.dpt.dt_5, mips1.core.dpt.dt_4, mips1.core.dpt.dt_3, mips1.core.dpt.dt_2, mips1.core.dpt.dt_1, mips1.core.dpt.dt_0 ) X;; +signal ir ( mips1.core.dpt.ir_31, mips1.core.dpt.ir_30, mips1.core.dpt.ir_29, mips1.core.dpt.ir_28, mips1.core.dpt.ir_27, mips1.core.dpt.ir_26, mips1.core.dpt.ir_25, mips1.core.dpt.ir_24, mips1.core.dpt.ir_23, mips1.core.dpt.ir_22, mips1.core.dpt.ir_21, mips1.core.dpt.ir_20, mips1.core.dpt.ir_19, mips1.core.dpt.ir_18, mips1.core.dpt.ir_17, mips1.core.dpt.ir_16, mips1.core.dpt.ir_15, mips1.core.dpt.ir_14, mips1.core.dpt.ir_13, mips1.core.dpt.ir_12, mips1.core.dpt.ir_11, mips1.core.dpt.ir_10, mips1.core.dpt.ir_9, mips1.core.dpt.ir_8, mips1.core.dpt.ir_7, mips1.core.dpt.ir_6, mips1.core.dpt.ir_5, mips1.core.dpt.ir_4, mips1.core.dpt.ir_3, mips1.core.dpt.ir_2, mips1.core.dpt.ir_1, mips1.core.dpt.ir_0 ) X;; +signal lo ( mips1.core.dpt.lo_31, mips1.core.dpt.lo_30, mips1.core.dpt.lo_29, mips1.core.dpt.lo_28, mips1.core.dpt.lo_27, mips1.core.dpt.lo_26, mips1.core.dpt.lo_25, mips1.core.dpt.lo_24, mips1.core.dpt.lo_23, mips1.core.dpt.lo_22, mips1.core.dpt.lo_21, mips1.core.dpt.lo_20, mips1.core.dpt.lo_19, mips1.core.dpt.lo_18, mips1.core.dpt.lo_17, mips1.core.dpt.lo_16, mips1.core.dpt.lo_15, mips1.core.dpt.lo_14, mips1.core.dpt.lo_13, mips1.core.dpt.lo_12, mips1.core.dpt.lo_11, mips1.core.dpt.lo_10, mips1.core.dpt.lo_9, mips1.core.dpt.lo_8, mips1.core.dpt.lo_7, mips1.core.dpt.lo_6, mips1.core.dpt.lo_5, mips1.core.dpt.lo_4, mips1.core.dpt.lo_3, mips1.core.dpt.lo_2, mips1.core.dpt.lo_1, mips1.core.dpt.lo_0 ) X;; +signal hi ( mips1.core.dpt.hi_31, mips1.core.dpt.hi_30, mips1.core.dpt.hi_29, mips1.core.dpt.hi_28, mips1.core.dpt.hi_27, mips1.core.dpt.hi_26, mips1.core.dpt.hi_25, mips1.core.dpt.hi_24, mips1.core.dpt.hi_23, mips1.core.dpt.hi_22, mips1.core.dpt.hi_21, mips1.core.dpt.hi_20, mips1.core.dpt.hi_19, mips1.core.dpt.hi_18, mips1.core.dpt.hi_17, mips1.core.dpt.hi_16, mips1.core.dpt.hi_15, mips1.core.dpt.hi_14, mips1.core.dpt.hi_13, mips1.core.dpt.hi_12, mips1.core.dpt.hi_11, mips1.core.dpt.hi_10, mips1.core.dpt.hi_9, mips1.core.dpt.hi_8, mips1.core.dpt.hi_7, mips1.core.dpt.hi_6, mips1.core.dpt.hi_5, mips1.core.dpt.hi_4, mips1.core.dpt.hi_3, mips1.core.dpt.hi_2, mips1.core.dpt.hi_1, mips1.core.dpt.hi_0 ) X;; +signal bar ( mips1.core.dpt.bar_31, mips1.core.dpt.bar_30, mips1.core.dpt.bar_29, mips1.core.dpt.bar_28, mips1.core.dpt.bar_27, mips1.core.dpt.bar_26, mips1.core.dpt.bar_25, mips1.core.dpt.bar_24, mips1.core.dpt.bar_23, mips1.core.dpt.bar_22, mips1.core.dpt.bar_21, mips1.core.dpt.bar_20, mips1.core.dpt.bar_19, mips1.core.dpt.bar_18, mips1.core.dpt.bar_17, mips1.core.dpt.bar_16, mips1.core.dpt.bar_15, mips1.core.dpt.bar_14, mips1.core.dpt.bar_13, mips1.core.dpt.bar_12, mips1.core.dpt.bar_11, mips1.core.dpt.bar_10, mips1.core.dpt.bar_9, mips1.core.dpt.bar_8, mips1.core.dpt.bar_7, mips1.core.dpt.bar_6, mips1.core.dpt.bar_5, mips1.core.dpt.bar_4, mips1.core.dpt.bar_3, mips1.core.dpt.bar_2, mips1.core.dpt.bar_1, mips1.core.dpt.bar_0 ) X;; +signal epc ( mips1.core.dpt.epc_31, mips1.core.dpt.epc_30, mips1.core.dpt.epc_29, mips1.core.dpt.epc_28, mips1.core.dpt.epc_27, mips1.core.dpt.epc_26, mips1.core.dpt.epc_25, mips1.core.dpt.epc_24, mips1.core.dpt.epc_23, mips1.core.dpt.epc_22, mips1.core.dpt.epc_21, mips1.core.dpt.epc_20, mips1.core.dpt.epc_19, mips1.core.dpt.epc_18, mips1.core.dpt.epc_17, mips1.core.dpt.epc_16, mips1.core.dpt.epc_15, mips1.core.dpt.epc_14, mips1.core.dpt.epc_13, mips1.core.dpt.epc_12, mips1.core.dpt.epc_11, mips1.core.dpt.epc_10, mips1.core.dpt.epc_9, mips1.core.dpt.epc_8, mips1.core.dpt.epc_7, mips1.core.dpt.epc_6, mips1.core.dpt.epc_5, mips1.core.dpt.epc_4, mips1.core.dpt.epc_3, mips1.core.dpt.epc_2, mips1.core.dpt.epc_1, mips1.core.dpt.epc_0 ) X;; +signal ad ( mips1.core.dpt.ad_31, mips1.core.dpt.ad_30, mips1.core.dpt.ad_29, mips1.core.dpt.ad_28, mips1.core.dpt.ad_27, mips1.core.dpt.ad_26, mips1.core.dpt.ad_25, mips1.core.dpt.ad_24, mips1.core.dpt.ad_23, mips1.core.dpt.ad_22, mips1.core.dpt.ad_21, mips1.core.dpt.ad_20, mips1.core.dpt.ad_19, mips1.core.dpt.ad_18, mips1.core.dpt.ad_17, mips1.core.dpt.ad_16, mips1.core.dpt.ad_15, mips1.core.dpt.ad_14, mips1.core.dpt.ad_13, mips1.core.dpt.ad_12, mips1.core.dpt.ad_11, mips1.core.dpt.ad_10, mips1.core.dpt.ad_9, mips1.core.dpt.ad_8, mips1.core.dpt.ad_7, mips1.core.dpt.ad_6, mips1.core.dpt.ad_5, mips1.core.dpt.ad_4, mips1.core.dpt.ad_3, mips1.core.dpt.ad_2, mips1.core.dpt.ad_1, mips1.core.dpt.ad_0 ) X;; +signal pc ( mips1.core.dpt.pc_31, mips1.core.dpt.pc_30, mips1.core.dpt.pc_29, mips1.core.dpt.pc_28, mips1.core.dpt.pc_27, mips1.core.dpt.pc_26, mips1.core.dpt.pc_25, mips1.core.dpt.pc_24, mips1.core.dpt.pc_23, mips1.core.dpt.pc_22, mips1.core.dpt.pc_21, mips1.core.dpt.pc_20, mips1.core.dpt.pc_19, mips1.core.dpt.pc_18, mips1.core.dpt.pc_17, mips1.core.dpt.pc_16, mips1.core.dpt.pc_15, mips1.core.dpt.pc_14, mips1.core.dpt.pc_13, mips1.core.dpt.pc_12, mips1.core.dpt.pc_11, mips1.core.dpt.pc_10, mips1.core.dpt.pc_9, mips1.core.dpt.pc_8, mips1.core.dpt.pc_7, mips1.core.dpt.pc_6, mips1.core.dpt.pc_5, mips1.core.dpt.pc_4, mips1.core.dpt.pc_3, mips1.core.dpt.pc_2, mips1.core.dpt.pc_1, mips1.core.dpt.pc_0 ) X;; +signal ep ( mips1.core.ctl.seq_ep_98, mips1.core.ctl.seq_ep_97, mips1.core.ctl.seq_ep_96, mips1.core.ctl.seq_ep_95, mips1.core.ctl.seq_ep_94, mips1.core.ctl.seq_ep_93, mips1.core.ctl.seq_ep_92, mips1.core.ctl.seq_ep_91, mips1.core.ctl.seq_ep_90, mips1.core.ctl.seq_ep_89, mips1.core.ctl.seq_ep_88, mips1.core.ctl.seq_ep_87 ) B;; +signal mips1.core.ctl.sts_ovf_r B;; +signal mips1.core.ctl.sts_ibe_r B;; +signal mips1.core.ctl.sts_ri_r B;; +signal mips1.core.ctl.sts_dbe_r B;; +signal mips1.core.ctl.sts_adel_r B;; +signal mips1.core.ctl.sts_cpu_r B;; +signal mips1.core.ctl.sts_ades_r B;; +signal mips1.core.ctl.sts_intrqs_sys_r B;; +signal mips1.core.ctl.sts_intrqs_br_r B;; +signal cr ( mips1.core.ctl.sts_cr_s_15, mips1.core.ctl.sts_cr_s_14, mips1.core.ctl.sts_cr_s_13, mips1.core.ctl.sts_cr_s_12, mips1.core.ctl.sts_cr_s_11, mips1.core.ctl.sts_cr_s_10, mips1.core.ctl.sts_cr_s_9, mips1.core.ctl.sts_cr_s_8, mips1.core.ctl.sts_cr_s_7, mips1.core.ctl.sts_cr_s_6, mips1.core.ctl.sts_cr_s_5, mips1.core.ctl.sts_cr_s_4, mips1.core.ctl.sts_cr_s_3, mips1.core.ctl.sts_cr_s_2, mips1.core.ctl.sts_cr_s_1, mips1.core.ctl.sts_cr_s_0 ) X;; +signal sr ( mips1.core.ctl.sts_sr_s_15, mips1.core.ctl.sts_sr_s_14, mips1.core.ctl.sts_sr_s_13, mips1.core.ctl.sts_sr_s_12, mips1.core.ctl.sts_sr_s_11, mips1.core.ctl.sts_sr_s_10, mips1.core.ctl.sts_sr_s_9, mips1.core.ctl.sts_sr_s_8, mips1.core.ctl.sts_sr_s_7, mips1.core.ctl.sts_sr_s_6, mips1.core.ctl.sts_sr_s_5, mips1.core.ctl.sts_sr_s_4, mips1.core.ctl.sts_sr_s_3, mips1.core.ctl.sts_sr_s_2, mips1.core.ctl.sts_sr_s_1, mips1.core.ctl.sts_sr_s_0 ) X;; +signal rf ( mips1.core.dpt.rf_o_31, mips1.core.dpt.rf_o_30, mips1.core.dpt.rf_o_29, mips1.core.dpt.rf_o_28, mips1.core.dpt.rf_o_27, mips1.core.dpt.rf_o_26, mips1.core.dpt.rf_o_25, mips1.core.dpt.rf_o_24, mips1.core.dpt.rf_o_23, mips1.core.dpt.rf_o_22, mips1.core.dpt.rf_o_21, mips1.core.dpt.rf_o_20, mips1.core.dpt.rf_o_19, mips1.core.dpt.rf_o_18, mips1.core.dpt.rf_o_17, mips1.core.dpt.rf_o_16, mips1.core.dpt.rf_o_15, mips1.core.dpt.rf_o_14, mips1.core.dpt.rf_o_13, mips1.core.dpt.rf_o_12, mips1.core.dpt.rf_o_11, mips1.core.dpt.rf_o_10, mips1.core.dpt.rf_o_9, mips1.core.dpt.rf_o_8, mips1.core.dpt.rf_o_7, mips1.core.dpt.rf_o_6, mips1.core.dpt.rf_o_5, mips1.core.dpt.rf_o_4, mips1.core.dpt.rf_o_3, mips1.core.dpt.rf_o_2, mips1.core.dpt.rf_o_1 ) B;; +out rw B;;; +out w (1 downto 0) B;;; +inout data (31 downto 0) X;;; +inout data_adr (31 downto 0) X;;; + +begin + +-- Pattern description : + +-- v v c r f t s s d i l h b e a p e m m m m m m m m m c s r r w d d +-- d s k e r e c c t r o i a p d c p i i i i i i i i i r r f w a a +-- d s s z s i o r c p p p p p p p p p t t +-- e t n u s s s s s s s s s a a +-- t t 1 1 1 1 1 1 1 1 1 _ +-- . . . . . . . . . a +-- c c c c c c c c c d +-- o o o o o o o o o r +-- r r r r r r r r r +-- e e e e e e e e e +-- . . . . . . . . . +-- c c c c c c c c c +-- t t t t t t t t t +-- l l l l l l l l l +-- . . . . . . . . . +-- s s s s s s s s s +-- t t t t t t t t t +-- s s s s s s s s s +-- _ _ _ _ _ _ _ _ _ +-- o i r d a c a i i +-- v b i b d p d n n +-- f e _ e e u e t t +-- _ _ r _ l _ s r r +-- r r r _ r _ q q +-- r r s s +-- _ _ +-- s b +-- y r +-- s _ +-- _ r +-- r + + +-- Beware : unprocessed patterns + +< 0 ns> : 1 0 1 1 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 50 ns> : 1 0 0 1 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 100 ns> : 1 0 1 1 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 150 ns> : 1 0 0 1 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 200 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 250 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 300 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 350 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 400 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 450 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 500 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 550 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 600 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 650 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 700 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 750 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 800 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 850 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 900 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 950 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 1000 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 1050 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 1100 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 1150 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 1200 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 1250 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 1300 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 1350 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 1400 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 1450 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 1500 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 1550 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 1600 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 1650 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 1700 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 1750 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 1800 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 1850 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 1900 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 1950 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 2000 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 2050 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 2100 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 2150 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 2200 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 2250 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 2300 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 2350 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 2400 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 2450 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 2500 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 2550 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 2600 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 2650 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 2700 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 2750 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 2800 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 2850 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 2900 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 2950 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 3000 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 3050 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 3100 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 3150 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 3200 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 3250 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 3300 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 3350 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 3400 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 3450 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 3500 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 3550 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 3600 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 3650 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 3700 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 3750 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 3800 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 3850 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 3900 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 3950 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 4000 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 4050 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 4100 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 4150 ns>findereset_4150 : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 4200 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 4250 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 4300 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 4350 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 4400 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 4450 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 4500 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 4550 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 4600 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 4650 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 4700 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 4750 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 4800 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 4850 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 4900 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 4950 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 5000 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 5050 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 5100 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 5150 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 5200 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 5250 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 5300 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 5350 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 5400 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 5450 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 5500 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 5550 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 5600 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 5650 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 5700 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 5750 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 5800 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 5850 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 5900 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 5950 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 6000 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 6050 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 6100 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 6150 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 6200 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 6250 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 6300 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 6350 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 6400 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 6450 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 6500 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 6550 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 6600 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 6650 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 6700 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 6750 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 6800 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 6850 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 6900 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 6950 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 7000 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 7050 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 7100 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 7150 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 7200 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 7250 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 7300 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 7350 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 7400 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 7450 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 7500 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 7550 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 7600 ns> : 1 0 0 0 0 1 1 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 7650 ns> : 1 0 1 0 0 1 1 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 7700 ns> : 1 0 0 0 0 1 1 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 7750 ns> : 1 0 1 0 0 1 1 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 7800 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 7850 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 7900 ns> : 1 0 0 0 0 1 1 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 7950 ns> : 1 0 1 0 0 1 1 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 8000 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 8050 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 8100 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 8150 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 8200 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 8250 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 8300 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 8350 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 8400 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 8450 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 8500 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 8550 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 8600 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 8650 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 8700 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 8750 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 8800 ns> : 1 0 0 0 0 1 1 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 8850 ns> : 1 0 1 0 0 1 1 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 8900 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 8950 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 9000 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 9050 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 9100 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 9150 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 9200 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 9250 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 9300 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 9350 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 9400 ns> : 1 0 0 0 0 1 1 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 9450 ns> : 1 0 1 0 0 1 1 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 9500 ns> : 1 0 0 0 0 1 1 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 9550 ns> : 1 0 1 0 0 1 1 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 9600 ns> : 1 0 0 0 0 1 1 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 9650 ns> : 1 0 1 0 0 1 1 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 9700 ns> : 1 0 0 0 0 1 1 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 9750 ns> : 1 0 1 0 0 1 1 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 9800 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 9850 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 9900 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 9950 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 10000 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 10050 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 10100 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 10150 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 10200 ns> : 1 0 0 0 0 1 1 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 10250 ns> : 1 0 1 0 0 1 1 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 10300 ns> : 1 0 0 0 0 1 1 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 10350 ns> : 1 0 1 0 0 1 1 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 10400 ns> : 1 0 0 0 0 1 1 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 10450 ns> : 1 0 1 0 0 1 1 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 10500 ns> : 1 0 0 0 0 1 1 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 10550 ns> : 1 0 1 0 0 1 1 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 10600 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 10650 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 10700 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 10750 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 10800 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 10850 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 10900 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 10950 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 11000 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 11050 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 11100 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 11150 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 11200 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 11250 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 11300 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 11350 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 11400 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 11450 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 11500 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 11550 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 11600 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 11650 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 11700 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 11750 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 11800 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 11850 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 11900 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 11950 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 12000 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 12050 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 12100 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 12150 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 12200 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 12250 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 12300 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 12350 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 12400 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 12450 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 12500 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 12550 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 12600 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 12650 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 12700 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 12750 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 12800 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 12850 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 12900 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 12950 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 13000 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 13050 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 13100 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 13150 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 13200 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 13250 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 13300 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 13350 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 13400 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 13450 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 13500 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 13550 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 13600 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 13650 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 13700 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 13750 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 13800 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 13850 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 13900 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 13950 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 14000 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 14050 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 14100 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 14150 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 14200 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 14250 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 14300 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 14350 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 14400 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 14450 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 14500 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 14550 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 14600 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 14650 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 14700 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 14750 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 14800 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 14850 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 14900 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 14950 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 15000 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 15050 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 15100 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 15150 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 15200 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 15250 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 15300 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 15350 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 15400 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 15450 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 15500 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 15550 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 15600 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 15650 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 15700 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 15750 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 15800 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 15850 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 15900 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 15950 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 16000 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 16050 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 16100 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 16150 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 16200 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 16250 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 16300 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 16350 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 16400 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 16450 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 16500 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 16550 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 16600 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 16650 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 16700 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 16750 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 16800 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 16850 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 16900 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 16950 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 17000 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 17050 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 17100 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 17150 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 17200 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 17250 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 17300 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 17350 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 17400 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 17450 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 17500 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 17550 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 17600 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 17650 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 17700 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 17750 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 17800 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 17850 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 17900 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 17950 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 18000 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 18050 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 18100 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 18150 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 18200 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 18250 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 18300 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 18350 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 18400 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 18450 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 18500 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 18550 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 18600 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 18650 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 18700 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 18750 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 18800 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 18850 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 18900 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 18950 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 19000 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 19050 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 19100 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 19150 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 19200 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 19250 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 19300 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 19350 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 19400 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 19450 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 19500 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 19550 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 19600 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 19650 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 19700 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 19750 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 19800 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 19850 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 19900 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 19950 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 20000 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 20050 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 20100 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 20150 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 20200 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 20250 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 20300 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 20350 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 20400 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 20450 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 20500 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 20550 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 20600 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 20650 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 20700 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 20750 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 20800 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 20850 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 20900 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 20950 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 21000 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 21050 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 21100 ns> : 1 0 0 0 0 1 1 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 21150 ns> : 1 0 1 0 0 1 1 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 21200 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 21250 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 21300 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 21350 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 21400 ns> : 1 0 0 0 0 1 1 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 21450 ns> : 1 0 1 0 0 1 1 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 21500 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 21550 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 21600 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 21650 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 21700 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 21750 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 21800 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 21850 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 21900 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 21950 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 22000 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; 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+< 26800 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 26850 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 26900 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 26950 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 27000 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; 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+< 30550 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 30600 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 30650 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 30700 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 30750 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; 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+< 31050 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 31100 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 31150 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 31200 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 31250 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; 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+< 31550 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 31600 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 31650 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 31700 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 31750 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 31800 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 31850 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 31900 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 31950 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 32000 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; 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+< 37550 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 37600 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 37650 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 37700 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 37750 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; 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+< 39550 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 39600 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 39650 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 39700 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 39750 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; 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+< 41050 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 41100 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 41150 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 41200 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 41250 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 41300 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 41350 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 41400 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 41450 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 41500 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 41550 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 41600 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 41650 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 41700 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 41750 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 41800 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 41850 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 41900 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 41950 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 42000 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 42050 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 42100 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 42150 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 42200 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 42250 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 42300 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 42350 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 42400 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 42450 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 42500 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 42550 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 42600 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 42650 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 42700 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 42750 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 42800 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 42850 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 42900 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 42950 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 43000 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 43050 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 43100 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 43150 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 43200 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 43250 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 43300 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 43350 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 43400 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 43450 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 43500 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 43550 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 43600 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 43650 ns> : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 43700 ns> : 1 0 0 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 43750 ns>fin_de_l_init_43750 : 1 0 1 0 0 1 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 43800 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 43850 ns> : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 43900 ns> : 1 0 0 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 43950 ns>fin_du_cycle_43950 : 1 0 1 0 0 0 0 ?* ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 44000 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 44050 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 44100 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 44150 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 44200 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 44250 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 44300 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 44350 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 44400 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 44450 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 44500 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 44550 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 44600 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 44650 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 44700 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 44750 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 44800 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 44850 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 44900 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 44950 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 45000 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 45050 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 45100 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 45150 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 45200 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 45250 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 45300 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 45350 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 45400 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 45450 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 45500 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 45550 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 45600 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 45650 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 45700 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 45750 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 45800 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 45850 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 45900 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 45950 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 46000 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 46050 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 46100 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 46150 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 46200 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 46250 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 46300 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 46350 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 46400 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 46450 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 46500 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 46550 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 46600 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 46650 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 46700 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 46750 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 46800 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 46850 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 46900 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 46950 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 47000 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 47050 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 47100 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 47150 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 47200 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 47250 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 47300 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 47350 ns> : 1 0 1 0 0 1 0 ?1 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 47400 ns> : 1 0 0 0 0 1 0 ?1 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 47450 ns> : 1 0 1 0 0 1 0 ?1 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 47500 ns> : 1 0 0 0 0 1 0 ?1 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 47550 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 47600 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 47650 ns> : 1 0 1 0 0 1 0 ?1 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 47700 ns> : 1 0 0 0 0 1 0 ?1 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 47750 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 47800 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 47850 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 47900 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 47950 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 48000 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 48050 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 48100 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 48150 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 48200 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 48250 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; 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+< 50050 ns> : 1 0 1 0 0 1 0 ?1 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 50100 ns> : 1 0 0 0 0 1 0 ?1 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 50150 ns> : 1 0 1 0 0 1 0 ?1 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 50200 ns> : 1 0 0 0 0 1 0 ?1 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 50250 ns> : 1 0 1 0 0 1 0 ?1 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; 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+< 50550 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 50600 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 50650 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 50700 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 50750 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; 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+< 51550 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 51600 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 51650 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 51700 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 51750 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 51800 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 51850 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 51900 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 51950 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 52000 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 52050 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 52100 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 52150 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 52200 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 52250 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 52300 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 52350 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 52400 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 52450 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 52500 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 52550 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 52600 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 52650 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 52700 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 52750 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 52800 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 52850 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 52900 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 52950 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 53000 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; 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+< 63300 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 63350 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 63400 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 63450 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 63500 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; 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+< 72800 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 72850 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 72900 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 72950 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 73000 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 73050 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 73100 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 73150 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 73200 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 73250 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 73300 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 73350 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 73400 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 73450 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 73500 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 73550 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 73600 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 73650 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 73700 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 73750 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 73800 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 73850 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 73900 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 73950 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 74000 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; 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+< 79300 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 79350 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 79400 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 79450 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 79500 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 79550 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 79600 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 79650 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 79700 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 79750 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 79800 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 79850 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 79900 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 79950 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 80000 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 80050 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 80100 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 80150 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 80200 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 80250 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 80300 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 80350 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 80400 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 80450 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 80500 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 80550 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 80600 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 80650 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 80700 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 80750 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 80800 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 80850 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 80900 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 80950 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 81000 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 81050 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 81100 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 81150 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 81200 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 81250 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 81300 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 81350 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 81400 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 81450 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 81500 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 81550 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 81600 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 81650 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 81700 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 81750 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 81800 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 81850 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 81900 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 81950 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 82000 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 82050 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 82100 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 82150 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 82200 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 82250 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 82300 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 82350 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 82400 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 82450 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 82500 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 82550 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 82600 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 82650 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 82700 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 82750 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 82800 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 82850 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 82900 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 82950 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 83000 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 83050 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 83100 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 83150 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 83200 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 83250 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 83300 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 83350 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 83400 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 83450 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 83500 ns> : 1 0 0 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; +< 83550 ns> : 1 0 1 0 0 1 0 ?0 ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?******** ?************ ?* ?* ?* ?* ?* ?* ?* ?* ?* ?**** ?**** ?******************************* ?* ?** ?******** ?******** ; + +end; diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_seq.fsm b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_seq.fsm new file mode 100644 index 00000000..ed7b55cd --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_seq.fsm @@ -0,0 +1,2825 @@ + +-- ### -------------------------------------------------------------- ### +-- # # +-- # file : mips_seq.fsm # +-- # date : 05 august 1996 # +-- # version : v0.0 # +-- # # +-- # origin : this description has been developed by CAO-VLSI team # +-- # at MASI laboratory, University Pierre et Marie Curie # +-- # URA CNRS 818, Institut Blaise Pascal # +-- # 4 Place Jussieu 75252 Paris Cedex 05 - France # +-- # E-mail : fahim RAHIM_SARWARY # +-- # cao-vlsi@masi.ibp.fr # +-- # descr. : Finite State Machine desciption of the sequencer # +-- # Reset input is coming from the status # +-- # # +-- # SOLUTION 3 pour le PORBLEME RFE/JUMP :pas de verification dans # +-- # l'etat init # +-- ### -------------------------------------------------------------- ### + + +entity mips_seq is + +-- Declaration de l'interface ( copie par coeur.vst ) + + PORT ( + ck : in BIT; -- ck + frz : in BIT; -- frz + rqs : in BIT; -- int,rqs,reset + reset : in BIT; -- status reset register + resnul : in BIT; -- resnul + alu_sign : in BIT; --alu_signe + ir_opcod : in BIT_VECTOR(18 DOWNTO 0) ; -- ir_opcod + vdd : in BIT; -- vdd + vss : in BIT; -- vss + scin : in BIT; -- scin + test : in BIT; -- test + itrqs : in BIT; -- it reqst + adrs : in BIT_VECTOR(1 downto 0); -- adr1 and adr2 + exrqs : in BIT; -- exeption reqst + + ctlopx : out bit_vector(8 DOWNTO 0) ; -- ctlopx + ctlopy : out bit_vector(6 DOWNTO 0) ; -- ctlopy + ctlalu : out bit_vector(5 DOWNTO 0) ; -- ctlalu + wenable : out bit_vector(10 DOWNTO 0) ; -- wenable + ctlrw : out bit_vector(4 DOWNTO 0) ; -- ctlrw + ctladr : out bit ; -- ctladr + excp : out bit_vector(6 downto 0) ; -- e_cpu + scout : out BIT -- scout + ); + +end mips_seq; + + +architecture STATE_MACHINE of mips_seq is + +-- Declaration des etats du microsequencer possibles ( un etat pour chaque m-instr ) + + +type ETAT_TYPE is ( init, init_rfe, ico_e, imdu, rfe_e_2, reg1, reg2, imd, lor_e, + lori_e, lb1_e, lb2_e, mfc0_e, mtc0_e, lxori_e, epc1, epc2, + ifetch1, ifetch1_e, sr2i_e, cr2i_e, epc2i_e, bar2i_e, i2sr_e, + i2cr_e, i2bar_e, i2epc_e, landi_e, land_e, lxor_e, lnor_e, sllv_e, + slti_e,sltiu_e, sll_e, srl_e, sra_e, srlv_e, srav_e, lui_e, sltu_e, slt_e, + beq, bne, blez, bgtz, bltz, bgez, bltzal, bgezal, branch_e, + jal, j_e, jalr, jr, jalre, jr_e, rfe_e, syscall_e, mfhi_e, mthi_e, + mtlo_e, mflo_e, lw_e,lh_e,lb_e,sw_e,sh_e,sb_e, lw1_e, lh1_e, lw2_e, lh2_e, + lbu2_e, lhu2_e, lhad1, lhad0, lbad00, lbad01, lbad10, lbad11, + sw1_e, sb1_e, sh1_e, irq, pct, ifetch_e, brk_e, reset0, reset1, +-- ajout des etats arithmetiques + addiu_e, addi_e, addi1_e, addu_e, sub_e, sub1_e, subu_e, add_e, add1_e ); + + + + +signal EF, EP:ETAT_TYPE; + + --pragma CURRENT_STATE EP + --pragma NEXT_STATE EF + --pragma SCAN_TEST test + --pragma SCAN_IN scin + --pragma SCAN_OUT scout + --pragma CLOCK ck + + -- Declaration des OPCODES des instructions + constant spec : bit_vector (5 downto 0) := B"000_000" ; --spec + constant bcond : bit_vector (5 downto 0) := B"000_001" ; --bcond + constant cop0 : bit_vector (5 downto 0) := B"010_000" ; --cop0 + constant j_i : bit_vector (5 downto 0) := B"000_010" ; -- j + constant jal_i : bit_vector (5 downto 0) := B"000_011" ; -- jal + constant beq_i : bit_vector (5 downto 0) := B"000_100" ; -- beq + constant bne_i : bit_vector (5 downto 0) := B"000_101" ; -- bne + constant blez_i : bit_vector (5 downto 0) := B"000_110" ; -- blez + constant bgtz_i : bit_vector (5 downto 0) := B"000_111" ; -- bgtz + constant sll_i : bit_vector (5 downto 0) := B"000_000" ; -- sll + constant srl_i : bit_vector (5 downto 0) := B"000_010" ; -- srl + constant sra_i : bit_vector (5 downto 0) := B"000_011" ; -- sra + constant sllv_i : bit_vector (5 downto 0) := B"000_100" ; -- sllv + constant srlv_i : bit_vector (5 downto 0) := B"000_110" ; -- srlv + constant srav_i : bit_vector (5 downto 0) := B"000_111" ; -- srav + constant and_i : bit_vector (5 downto 0) := B"100_100" ; -- and + constant or_i : bit_vector (5 downto 0) := B"100_101" ; -- or + constant xor_i : bit_vector (5 downto 0) := B"100_110" ; -- xor + constant nor_i : bit_vector (5 downto 0) := B"100_111" ; -- nor + constant slti_i : bit_vector (5 downto 0) := B"001_010" ; -- slti + constant sltiu_i : bit_vector (5 downto 0) := B"001_011" ; -- sltiu + constant andi_i : bit_vector (5 downto 0) := B"001_100" ; -- andi + constant ori_i : bit_vector (5 downto 0) := B"001_101" ; -- ori + constant xori_i : bit_vector (5 downto 0) := B"001_110" ; -- xori + constant lui_i : bit_vector (5 downto 0) := B"001_111" ; -- lui + constant jr_i : bit_vector (5 downto 0) := B"001_000" ; -- jr + constant jalr_i : bit_vector (5 downto 0) := B"001_001" ; -- jalr + constant syscall_i: bit_vector (5 downto 0) := B"001_100" ; -- syscall + constant break_i : bit_vector (5 downto 0) := B"001_101" ; -- break + constant mfhi_i : bit_vector (5 downto 0) := B"010_000" ; -- mfhi + constant mthi_i : bit_vector (5 downto 0) := B"010_001" ; -- mthi + constant mflo_i : bit_vector (5 downto 0) := B"010_010" ; -- mflo + constant mtlo_i : bit_vector (5 downto 0) := B"010_011" ; -- mtlo + constant lb_i : bit_vector (5 downto 0) := B"100_000" ; -- lb + constant lh_i : bit_vector (5 downto 0) := B"100_001" ; -- lh + constant lw_i : bit_vector (5 downto 0) := B"100_011" ; -- lw + constant lbu_i : bit_vector (5 downto 0) := B"100_100" ; -- lbu + constant lhu_i : bit_vector (5 downto 0) := B"100_101" ; -- lhu + constant slt_i : bit_vector (5 downto 0) := B"101_010" ; -- slt + constant sltu_i : bit_vector (5 downto 0) := B"101_011" ; -- sltu + constant sb_i : bit_vector (5 downto 0) := B"101_000" ; -- sb + constant sh_i : bit_vector (5 downto 0) := B"101_001" ; -- sh + constant sw_i : bit_vector (5 downto 0) := B"101_011" ; -- sw + constant sr : bit_vector (2 downto 0) := B"100" ; -- sr + constant cr : bit_vector (2 downto 0) := B"101" ; -- cr + constant epc : bit_vector (2 downto 0) := B"110" ; -- epc + constant bar : bit_vector (2 downto 0) := B"000" ; -- bar + constant bltz_i : bit_vector (1 downto 0) := B"00" ; -- bltz + constant bgez_i : bit_vector (1 downto 0) := B"10" ; -- bgez + constant bltzal_i : bit_vector (1 downto 0) := B"01" ; -- bltzal + constant bgezal_i : bit_vector (1 downto 0) := B"11" ; -- bgezal + + +-- ajout des commandes add, addi, sub, addu, addiu, subu + constant add_i : bit_vector (5 downto 0) := B"100_000" ; -- add + constant addi_i : bit_vector (5 downto 0) := B"001_000" ; -- addi + constant addu_i : bit_vector (5 downto 0) := B"100_001" ; -- addu + constant addiu_i : bit_vector (5 downto 0) := B"001_001" ; -- addiu + constant sub_i : bit_vector (5 downto 0) := B"100_010" ; -- sub + constant subu_i : bit_vector (5 downto 0) := B"100_011" ; -- subu + + + + + + -- Description des operations de l'Alu + + constant a_sum : bit_vector (5 downto 0) := B"111110" ; + constant a_sumv : bit_vector (5 downto 0) := B"111110" ; + constant a_dif : bit_vector (5 downto 0) := B"111111" ; + constant a_difv : bit_vector (5 downto 0) := B"111111" ; + constant a_and : bit_vector (5 downto 0) := B"110010" ; + constant a_or : bit_vector (5 downto 0) := B"110000" ; + constant a_xor : bit_vector (5 downto 0) := B"110100" ; + constant a_nor : bit_vector (5 downto 0) := B"111000" ; + constant a_sll : bit_vector (5 downto 0) := B"100100" ; + constant a_srl : bit_vector (5 downto 0) := B"100000" ; + constant a_sra : bit_vector (5 downto 0) := B"100010" ; + constant a_slt : bit_vector (5 downto 0) := B"001101" ; + constant a_sltu : bit_vector (5 downto 0) := B"001111" ; + + -- Description de l'operande X + + constant x_rs : bit_vector (8 downto 0) := B"000000011" ; + constant x_rt : bit_vector (8 downto 0) := B"000000010" ; + constant x_pc : bit_vector (8 downto 0) := B"000000100" ; + constant x_ad : bit_vector (8 downto 0) := B"000000101" ; + constant x_hi : bit_vector (8 downto 0) := B"000001000" ; + constant x_lo : bit_vector (8 downto 0) := B"000001001" ; + -- Modif : Inversion des microcodes de x_cr et x_sr + constant x_cr : bit_vector (8 downto 0) := B"000010000" ; + constant x_sr : bit_vector (8 downto 0) := B"000010001" ; + constant x_bar : bit_vector (8 downto 0) := B"000100000" ; + constant x_epc : bit_vector (8 downto 0) := B"000100001" ; + constant x_c0 : bit_vector (8 downto 0) := B"001000000" ; + constant x_c1 : bit_vector (8 downto 0) := B"001000001" ; + constant x_dt : bit_vector (8 downto 0) := B"010000000" ; + constant x_ch : bit_vector (8 downto 0) := B"010000001" ; + constant x_pc4 : bit_vector (8 downto 0) := B"100000000"; + + -- Description de l'operande Y + + constant y_i16 : bit_vector (6 downto 0) := B"0001000" ; + constant y_i18 : bit_vector (6 downto 0) := B"0000101" ; + constant y_iu28 : bit_vector (6 downto 0) := B"0000100" ; + constant y_sham : bit_vector (6 downto 0) := B"0100000" ; + constant y_dt : bit_vector (6 downto 0) := B"0000011" ; + constant y_ad : bit_vector (6 downto 0) := B"0000010" ; + constant y_c0 : bit_vector (6 downto 0) := B"0001001" ; + constant y_c4 : bit_vector (6 downto 0) := B"0010000" ; + constant y_c16 : bit_vector (6 downto 0) := B"0010001" ; + constant y_cad : bit_vector (6 downto 0) := B"0100001" ; + constant y_c24 : bit_vector (6 downto 0) := B"1000001" ; + constant y_c8 : bit_vector (6 downto 0) := B"1000000" ; + + -- Description du registre destination + + constant r_no : bit_vector (10 downto 0) := B"00000000000" ; + constant r_pc : bit_vector (10 downto 0) := B"01000000000" ; + constant r_ad : bit_vector (10 downto 0) := B"00100000000" ; + constant r_rd : bit_vector (10 downto 0) := B"10000000001" ; + constant r_r31 : bit_vector (10 downto 0) := B"10000000010" ; + constant r_epc : bit_vector (10 downto 0) := B"00000010000" ; + constant r_bar : bit_vector (10 downto 0) := B"00000100000" ; + constant r_hi : bit_vector (10 downto 0) := B"00010000000" ; + constant r_lo : bit_vector (10 downto 0) := B"00001000000" ; + constant r_cr : bit_vector (10 downto 0) := B"00000000101" ; + constant r_sr : bit_vector (10 downto 0) := B"00000001000" ; + constant r_erq : bit_vector (10 downto 0) := B"00000001110" ; + constant r_rfe : bit_vector (10 downto 0) := B"00000001011" ; + constant r_rt : bit_vector (10 downto 0) := B"10000000000" ; + constant r_scan : bit_vector (10 downto 0) := B"01111111101" ; + + -- Description des modes d'acces memoire + + constant m_no : bit_vector (4 downto 0) := B"00001" ; + constant m_fetch : bit_vector (4 downto 0) := B"10001" ; + constant m_rw : bit_vector (4 downto 0) := B"01001" ; + constant m_ww : bit_vector (4 downto 0) := B"00000" ; + constant m_wh : bit_vector (4 downto 0) := B"00100" ; + constant m_wb : bit_vector (4 downto 0) := B"00010" ; + constant m_scan : bit_vector (4 downto 0) := B"11000" ; + + constant o_no : bit := '1'; + constant o_fetch : bit := '1'; + constant o_rw : bit := '0'; + constant o_ww : bit := '0'; + constant o_rb : bit := '0'; + constant o_wb : bit := '0'; + constant o_wh : bit := '0'; + constant o_rh : bit := '0'; + + constant e_sys : bit_vector (6 downto 0) := B"0010000"; + constant e_brk : bit_vector (6 downto 0) := B"0001000"; + constant e_ri : bit_vector (6 downto 0) := B"0000010"; + constant e_cpu : bit_vector (6 downto 0) := B"0000001"; + constant e_nop : bit_vector (6 downto 0) := B"0000000"; + constant e_lw : bit_vector (6 downto 0) := B"0010001"; + constant e_lh : bit_vector (6 downto 0) := B"0010010"; + constant e_lb : bit_vector (6 downto 0) := B"0010100"; + constant e_sw : bit_vector (6 downto 0) := B"0011000"; + constant e_sh : bit_vector (6 downto 0) := B"0011100"; + constant e_sb : bit_vector (6 downto 0) := B"0011110"; + constant e_ifetch : bit_vector (6 downto 0):= B"0011111"; + constant e_ibe : bit_vector (6 downto 0):= B"0100000"; + constant e_dbe : bit_vector (6 downto 0):= B"1000000"; + constant e_ovf : bit_vector (6 downto 0):= B"1111111"; + constant e_clr : bit_vector (6 downto 0):= B"1010101"; + + +-- Description de l'automate + +begin +process ( EP , ir_opcod, resnul, frz , rqs, reset ) +begin + +-- FONCTION DE TRANSITION + + if (reset = '1') then + EF <= reset0; + + else case EP is + + when reset0 => + EF <= reset1; + + when reset1 => + EF <= ifetch1; + + when init => + if frz then EF <= init; + elsif ir_opcod(18 downto 13) = ori_i then EF <= imdu; + elsif ir_opcod(18 downto 13) = andi_i then EF <= imdu; + elsif ir_opcod(18 downto 13) = xori_i then EF <= imdu; + elsif(ir_opcod(18 downto 13) = spec and ir_opcod(5 downto 0) = or_i) then EF <= reg1; + elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = and_i) then EF <= reg1; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = xor_i) then EF <= reg1; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = slt_i) then EF <= reg1; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = sltu_i) then EF <= reg1; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = sllv_i) then EF <= reg2; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = srlv_i) then EF <= reg2; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = srav_i) then EF <= reg2; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = nor_i) then EF <= reg1; + +-- ajout de l'arithmetique avec registre +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = add_i) then EF <= reg1; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = addu_i) then EF <= reg1; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = sub_i) then EF <= reg1; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = subu_i) then EF <= reg1; +-- + +elsif (ir_opcod (18 downto 13) = spec and ir_opcod(5 downto 0) = sll_i) then EF <= sll_e ; +elsif (ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = srl_i) then EF <= srl_e ; +elsif (ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = sra_i) then EF <= sra_e ; + + +elsif ir_opcod (18 downto 13)= lui_i then EF <= imd ; + +elsif ir_opcod (18 downto 13) = slti_i then EF <= imd ; +elsif ir_opcod (18 downto 13) = sltiu_i then EF <= imd ; + +-- ajout de l'arithmetique (immediat) +elsif ir_opcod (18 downto 13) = addiu_i then EF <= imd ; +elsif ir_opcod (18 downto 13) = addi_i then EF <= imd ; +-- + + +elsif ir_opcod (18 downto 13) = jal_i then EF <= jal ; +elsif ir_opcod (18 downto 13) = j_i then EF <= j_e ; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = jalr_i) then EF <= jalre; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = jr_i) then EF <= jr_e; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = syscall_i) then EF <= syscall_e; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = break_i) then EF <= brk_e; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = mfhi_i) then EF <= mfhi_e; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = mflo_i) then EF <= mflo_e; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = mthi_i) then EF <= mthi_e; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = mtlo_i) then EF <= mtlo_e; +elsif ir_opcod (18 downto 13)= beq_i then EF <= reg1; +elsif ir_opcod (18 downto 13)= bne_i then EF <= reg1; +elsif ir_opcod (18 downto 13)= blez_i then EF <= blez; +elsif ir_opcod (18 downto 13)= bgtz_i then EF <= bgtz; +elsif (ir_opcod (18 downto 13)= bcond and ir_opcod(7 downto 6) = bltz_i) then EF <= bltz; +elsif (ir_opcod (18 downto 13)= bcond and ir_opcod(7 downto 6) = bgez_i) then EF <= bgez; +elsif (ir_opcod (18 downto 13)= bcond and ir_opcod(7 downto 6) = bltzal_i) then EF <= bltzal; +elsif (ir_opcod (18 downto 13)= bcond and ir_opcod(7 downto 6) = bgezal_i) then EF <= bgezal; +elsif ir_opcod (18 downto 13)= lb_i then EF <= lb_e ; +elsif ir_opcod (18 downto 13) = lbu_i then EF <= lb_e ; +elsif ir_opcod (18 downto 13) = lhu_i then EF <= lh_e ; +elsif ir_opcod (18 downto 13) = lh_i then EF <= lh_e ; +elsif ir_opcod (18 downto 13) = lw_i then EF <= lw_e ; +elsif ir_opcod (18 downto 13) = sh_i then EF <= sh_e ; +elsif ir_opcod (18 downto 13) = sw_i then EF <= sw_e ; +elsif ir_opcod (18 downto 13) = sb_i then EF <= sb_e ; +elsif (ir_opcod (18 downto 13) = cop0 and ir_opcod(12)='1') then EF <= rfe_e; +elsif (ir_opcod (18 downto 13) = cop0 and ir_opcod(12 downto 11) = B"00") then EF <= mfc0_e; +elsif (ir_opcod (18 downto 13) = cop0 and ir_opcod(12 downto 11) = B"01") then EF <= mtc0_e; +else EF <= ico_e; + + end if; + +--********************************************************************** +when init_rfe => + if frz then EF <= init_rfe; +elsif ir_opcod(18 downto 13) = ori_i then EF <= imdu; +elsif ir_opcod(18 downto 13) = andi_i then EF <= imdu; +elsif ir_opcod(18 downto 13) = xori_i then EF <= imdu; +elsif(ir_opcod(18 downto 13) = spec and ir_opcod(5 downto 0) = or_i) then EF <= reg1; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = and_i) then EF <= reg1; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = xor_i) then EF <= reg1; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = slt_i) then EF <= reg1; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = sltu_i) then EF <= reg1; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = sllv_i) then EF <= reg2; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = srlv_i) then EF <= reg2; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = srav_i) then EF <= reg2; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = nor_i) then EF <= reg1; + +-- ajout de l'arithmetique avec registre +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = add_i) then EF <= reg1; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = addu_i) then EF <= reg1; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = sub_i) then EF <= reg1; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = subu_i) then EF <= reg1; +-- + +elsif (ir_opcod (18 downto 13) = spec and ir_opcod(5 downto 0) = sll_i) then EF <= sll_e ; +elsif (ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = srl_i) then EF <= srl_e ; +elsif (ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = sra_i) then EF <= sra_e ; +elsif ir_opcod (18 downto 13)= lui_i then EF <= imd ; +elsif ir_opcod (18 downto 13) = slti_i then EF <= imd ; +elsif ir_opcod (18 downto 13) = sltiu_i then EF <= imd ; + +-- ajout de l'arithmetique (immediat) +elsif ir_opcod (18 downto 13) = addiu_i then EF <= imd ; +elsif ir_opcod (18 downto 13) = addi_i then EF <= imd ; +-- + +elsif ir_opcod (18 downto 13) = jal_i then EF <= jal ; +elsif ir_opcod (18 downto 13) = j_i then EF <= j_e ; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = jalr_i) then EF <= jalre; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = jr_i) then EF <= jr_e; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = syscall_i) then EF <= syscall_e; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = break_i) then EF <= brk_e; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = mfhi_i) then EF <= mfhi_e; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = mflo_i) then EF <= mflo_e; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = mthi_i) then EF <= mthi_e; +elsif(ir_opcod (18 downto 13)= spec and ir_opcod(5 downto 0) = mtlo_i) then EF <= mtlo_e; +elsif ir_opcod (18 downto 13)= beq_i then EF <= reg1; +elsif ir_opcod (18 downto 13)= bne_i then EF <= reg1; +elsif ir_opcod (18 downto 13)= blez_i then EF <= blez; +elsif ir_opcod (18 downto 13)= bgtz_i then EF <= bgtz; +elsif (ir_opcod (18 downto 13)= bcond and ir_opcod(7 downto 6) = bltz_i) then EF <= bltz; +elsif (ir_opcod (18 downto 13)= bcond and ir_opcod(7 downto 6) = bgez_i) then EF <= bgez; +elsif (ir_opcod (18 downto 13)= bcond and ir_opcod(7 downto 6) = bltzal_i) then EF <= bltzal; +elsif (ir_opcod (18 downto 13)= bcond and ir_opcod(7 downto 6) = bgezal_i) then EF <= bgezal; +elsif ir_opcod (18 downto 13)= lb_i then EF <= lb_e ; +elsif ir_opcod (18 downto 13) = lbu_i then EF <= lb_e ; +elsif ir_opcod (18 downto 13) = lhu_i then EF <= lh_e ; +elsif ir_opcod (18 downto 13) = lh_i then EF <= lh_e ; +elsif ir_opcod (18 downto 13) = lw_i then EF <= lw_e ; +elsif ir_opcod (18 downto 13) = sh_i then EF <= sh_e ; +elsif ir_opcod (18 downto 13) = sw_i then EF <= sw_e ; +elsif ir_opcod (18 downto 13) = sb_i then EF <= sb_e ; +elsif (ir_opcod (18 downto 13) = cop0 and ir_opcod(12)='1') then EF <= rfe_e; +elsif (ir_opcod (18 downto 13) = cop0 and ir_opcod(12 downto 11) = B"00") then EF <= mfc0_e; +elsif (ir_opcod (18 downto 13) = cop0 and ir_opcod(12 downto 11) = B"01") then EF <= mtc0_e; +else EF <= ico_e; + + end if; + +--************************************************************************** + when imdu => + if frz then EF <= imdu; + + elsif ir_opcod(18 downto 13) = ori_i then EF <= lori_e ; + elsif ir_opcod(18 downto 13) = andi_i then EF <= landi_e ; + elsif ir_opcod(18 downto 13) = xori_i then EF <= lxori_e ; + + -- Modif sltu_e et non slti_e + -- Modif Si on passe par imdu l immediat ne sera pas signe sur 32 bits. + -- elsif ir_opcod(18 downto 13) = sltiu_i then EF <= sltu_e ; + else EF <= ico_e; + end if; + +-- *********************************************************************** + +when reg1 => + if frz then EF <= reg1; + +elsif (ir_opcod(5 downto 0) = or_i and ir_opcod(18 downto 13) = spec) then EF <= lor_e ; +elsif (ir_opcod(5 downto 0) = and_i and ir_opcod(18 downto 13) = spec) then EF <= land_e ; +elsif (ir_opcod(5 downto 0) = xor_i and ir_opcod(18 downto 13) =spec) then EF <= lxor_e ; +elsif (ir_opcod(5 downto 0) = slt_i and ir_opcod(18 downto 13) = spec) then EF <= slt_e ; +elsif (ir_opcod(5 downto 0) = sltu_i and ir_opcod(18 downto 13)= spec) then EF <= sltu_e ; +elsif (ir_opcod(5 downto 0) = nor_i and ir_opcod(18 downto 13) = spec) then EF <= lnor_e ; + +--insertion des etats add ... +elsif (ir_opcod(5 downto 0) = add_i and ir_opcod(18 downto 13) = spec) then EF <= add_e ; +elsif (ir_opcod(5 downto 0) = addu_i and ir_opcod(18 downto 13) = spec) then EF <= addu_e ; +elsif (ir_opcod(5 downto 0) = sub_i and ir_opcod(18 downto 13) = spec) then EF <= sub_e ; +elsif (ir_opcod(5 downto 0) = subu_i and ir_opcod(18 downto 13) = spec) then EF <= subu_e ; +-- + +elsif ir_opcod(18 downto 13) = beq_i then EF <= beq ; +elsif ir_opcod(18 downto 13) = bne_i then Ef <= bne ; +else EF <= ico_e; + + end if; + + +when reg2 => + if frz then EF <= reg2; + +elsif (ir_opcod(5 downto 0) = sllv_i and ir_opcod(18 downto 13) = spec) then EF <= sllv_e ; +elsif (ir_opcod(5 downto 0) = srlv_i and ir_opcod(18 downto 13) =spec ) then EF <= srlv_e ; +elsif (ir_opcod(5 downto 0) = srav_i and ir_opcod(18 downto 13) =spec) then EF <= srav_e ; +elsif ir_opcod(18 downto 13) = beq_i then EF <= beq ; +elsif ir_opcod(18 downto 13) = bne_i then Ef <= bne ; +else EF <= ico_e; + + end if; + +-- *********************************************************************** + + +when imd => + if frz then EF <= imd; + + elsif ir_opcod(18 downto 13) = lui_i then EF <= lui_e ; + elsif ir_opcod(18 downto 13) = slti_i then EF <= slti_e ; + elsif ir_opcod(18 downto 13) = sltiu_i then EF <= sltiu_e ; +-- insertion des immediats add ... + elsif ir_opcod(18 downto 13) = addiu_i then EF <= addiu_e ; + elsif ir_opcod(18 downto 13) = addi_i then EF <= addi_e ; + + else EF <= ico_e; + end if; + +-- *********************************************************************** + + when lor_e => + if frz then EF <= lor_e; + + elsif rqs then + EF <= irq; + + + else EF <= init ; + end if; + +-- *********************************************************************** + + when lori_e => + if frz then EF <= lori_e; + + elsif rqs then + EF <= irq; + + else EF <= init ; + end if; + +--************************************************************************************ + when land_e => + if frz then EF <= land_e; + + elsif rqs then + EF <= irq; + + + else EF <= init; + + end if; + + +--************************************************************************************ + when landi_e => + if frz then EF <= landi_e; + + elsif rqs then + EF <= irq; + + + else EF <= init ; + end if; + + +-- *********************************************************************** + when lxor_e => + if frz then + EF <= lxor_e; + elsif rqs then + EF <= irq; + else + EF <= init ; + end if; + + +-- *********************************************************************** + + when lxori_e => + if frz then EF <= lxori_e; + + elsif rqs then + EF <= irq; + + + else EF <= init ; + end if; + + +-- *********************************************************************** + + when lnor_e => + if frz then EF <= lnor_e; + + elsif rqs then + EF <= irq; + + + else EF <= init ; + end if; + + +-- *********************************************************************** + when sllv_e => + if frz then EF <= sllv_e; + + elsif rqs then + EF <= irq; + + + else EF <= init ; + end if; + + +-- *********************************************************************** + + when sll_e => + if frz then EF <= sll_e; + + elsif rqs then + EF <= irq; + + + else EF <= init ; + end if; + + +--***************************************************************************************************************** + + when srl_e => + if frz then EF <= srl_e; + + elsif rqs then + EF <= irq; + + + else EF <= init ; + end if; + + +--*********************************************************************************************************** + + when sra_e => + if frz then + EF <= sra_e; + elsif rqs then + EF <= irq; + else + EF <= init ; + end if; + +--******************************************************************************************************** + when srlv_e => + if frz then EF <= srlv_e; + + elsif rqs then + EF <= irq; + + + else EF <= init ; + end if; + + +-- *********************************************************************** + + when srav_e => + if frz then EF <= srav_e; + + elsif rqs then + EF <= irq; + + + else EF <= init ; + end if; + +-- *********************************************************************** + + when lui_e => + if frz then EF <= lui_e; + + elsif rqs then + EF <= irq; + + + else EF <= init ; + end if; + + +-- *********************************************************************** + + when sltiu_e => + if frz then EF <= sltiu_e; + + elsif rqs then + EF <= irq; + + + else EF <= init ; + end if; + +-- *********************************************************************** +-- insertion de l'etat de addiu + when addiu_e => + if frz then EF <= addiu_e; + + elsif rqs then + EF <= irq; + + + else EF <= init ; + end if; + +-- *********************************************************************** +-- insertion des etats de addi + when addi_e => + if frz then EF <= addi_e; + + else EF <= addi1_e; + + end if; + + +-- *********************************************************************** + when addi1_e => + if frz then + EF <= addi1_e; + elsif rqs then + EF <= irq; + else + EF <= init ; + end if; + +-- *********************************************************************** +-- insertion de l'etat de addu + when addu_e => + if frz then EF <= addu_e; + + elsif rqs then + EF <= irq; + + + else EF <= init ; + end if; + +-- *********************************************************************** +-- insertion des etats de add + when add_e => + if frz then EF <= add_e; + + else EF <= add1_e; + + end if; + + +-- *********************************************************************** + when add1_e => + if frz then + EF <= add1_e; + elsif rqs then + EF <= irq; + else + EF <= init ; + end if; + +-- *********************************************************************** +-- insertion de l'etat de subu + when subu_e => + if frz then EF <= subu_e; + + elsif rqs then + EF <= irq; + + + else EF <= init ; + end if; + +-- *********************************************************************** +-- insertion des etats de sub + when sub_e => + if frz then EF <= sub_e; + + else EF <= sub1_e; + + end if; + + +-- *********************************************************************** + when sub1_e => + if frz then + EF <= sub1_e; + elsif rqs then + EF <= irq; + else + EF <= init ; + end if; + +-- *********************************************************************** + when sltu_e => + if frz then EF <= sltu_e; + + elsif rqs then + EF <= irq; + + + else EF <= init ; + end if; + + +-- *********************************************************************** + + when slt_e => + if frz then EF <= slt_e; + + elsif rqs then + EF <= irq; + + + else EF <= init ; + end if; + +-- *********************************************************************** + + when slti_e => + if frz then EF <= slti_e; + + elsif rqs then + EF <= irq; + + + else EF <= init ; + end if; + + +-- *********************************************************************** + when beq => + if frz then EF <= beq; + else + if resnul = '1' then EF <= branch_e ; end if; + if resnul = '0' then EF <= ifetch_e ; end if; + end if; + + + -- *********************************************************************** + + when bne => + if frz then EF <= bne; + else + if resnul='0' then EF <= branch_e ; end if; + if resnul='1' then EF <= ifetch_e ; end if; + end if; + +-- *********************************************************************** + + when blez => + if frz then EF <= blez; + else + if (resnul = '1' or alu_sign = '1') then EF <= branch_e ; + else + EF <= ifetch_e ; end if; + + end if; + +-- *********************************************************************** + + when bgtz => + if frz then EF <= bgtz; + else + if (alu_sign = '0' and resnul = '0') then EF <= branch_e ; + else + EF <= ifetch_e ; end if; + end if; + + +-- *********************************************************************** + + when bltz => + if frz then EF <= bltz; + else + if (resnul = '0' and alu_sign = '1') then EF <= branch_e ; + else + EF <= ifetch_e ; end if; + end if; + +--************************************************************************************************************** + + when bgez => + if frz then EF <= bgez; + else + if (resnul = '1' or alu_sign = '0') then EF <= branch_e ; + else + EF <= ifetch_e ; end if; + end if; + +--************************************************************************************************************** + + when bltzal => + if frz then EF <= bltzal; + else + EF <= bltz; + end if; + + +--************************************************************************************************************** + + when bgezal => + if frz then EF <= bgezal; + else + EF <= bgez; + end if; + + +-- *********************************************************************** + when branch_e => + if frz then EF <= branch_e; + else + EF <= ifetch_e ; + end if; + + +-- *********************************************************************** + + when jal => + if frz then EF <= jal; + else + EF <= j_e ; + end if; + +-- *********************************************************************** + + when j_e => + if frz then EF <= j_e; + else + + EF <= ifetch_e ; + end if; + + +-- *********************************************************************** + when jalre => + if frz then EF <= jalre; + else + EF <= jalr; + + + end if; + + +-- *********************************************************************** + + when jalr => + if frz then EF <= jalr; + else + EF <= jr ; + end if; + + +-- *********************************************************************** + when jr_e => + if frz then + EF <= jr_e; + else + EF <= jr ; + end if; + +-- *********************************************************************** + + when jr => + if frz then + EF <= jr; + elsif rqs then + EF <= irq ; + else + EF <= ifetch_e ; + end if; + +-- *********************************************************************** + + + when rfe_e => + if frz then EF <= rfe_e; + elsif rqs then EF <= irq; + else + EF <= rfe_e_2 ; + end if; + + +-- *********************************************************************** + + when rfe_e_2 => + if frz then EF <= rfe_e_2; + else + EF <= init_rfe ; + end if; + + +-- *********************************************************************** + + when syscall_e => + if frz then + EF <= syscall_e; + else + EF <= irq ; + end if; + + +-- *********************************************************************** + + when brk_e => + if frz then EF <= brk_e; + else + EF <= irq ; + end if; + + +-- *********************************************************************** + + when mfhi_e => + if frz then EF <= mfhi_e; + else + EF <= init; + end if; + +-- *********************************************************************** + + when mthi_e => + if frz then EF <= mthi_e; + else + EF <= init; + end if; + +-- *********************************************************************** + + when mtlo_e => + if frz then EF <= mtlo_e; + else + EF <= init; + end if; + + +-- *********************************************************************** + + when mflo_e => + if frz then EF <= mflo_e; + else + EF <= init; + end if; + +-- *********************************************************************** + + + when lw1_e => + if frz then + EF <= lw1_e; + else + EF <= lw2_e ; + end if; + + +-- *********************************************************************** + when lw_e => + if frz then + EF <= lw_e; + else + EF <= lw1_e ; + end if; + + +-- *********************************************************************** + when lh1_e => + if frz then + EF <= lh1_e; + elsif adrs(1) = '0' then + EF <= lhad1; + else + EF <= lhad0 ; + end if; + + +-- *********************************************************************** + when lh_e => + if frz then + EF <= lh_e; + else + EF <= lh1_e; + + end if; + + +-- *********************************************************************** + when lw2_e => + if frz then + EF <= lw2_e; + elsif rqs then + EF <= irq; + else + EF <= init ; + end if; + + +-- *********************************************************************** + when lhad1 => + if frz then + EF <= lhad1; + elsif rqs then + EF <= irq; + elsif ir_opcod(18 downto 13)= lh_i then + EF <= lh2_e ; + else + EF <= lhu2_e; + end if; + +-- *********************************************************************** + when lhad0 => + if frz then + EF <= lhad0; + elsif rqs then + EF <= irq; + elsif ir_opcod(18 downto 13)= lh_i then + EF <= lh2_e ; + else + EF <= lhu2_e; + end if; + +-- *********************************************************************** + when lh2_e => + if frz then EF <= lh2_e; + elsif rqs then EF <= irq; + else EF <= init ; + end if; + + +-- *********************************************************************** + + when lhu2_e => + if frz then EF <= lhu2_e; + elsif rqs then EF <= irq; + else + EF <= init ; + end if; + + +-- *********************************************************************** + when lb_e => + if frz then + EF <= lb_e; + else + EF <= lb1_e; + end if; + + +-- *********************************************************************** + when lb1_e => + if frz then + EF <= lb1_e; + elsif adrs(1 downto 0) = B"11" then + EF <= lbad00 ; + elsif adrs( 1 downto 0) = B"10" then + EF <= lbad01; + elsif adrs( 1 downto 0) = B"01" then + EF <= lbad10; + else + EF <= lbad11; + end if; + +-- *********************************************************************** + when lbad00 => + if frz then + EF <= lbad00; + elsif ir_opcod(18 downto 13) = lb_i then + EF <= lb2_e; + else + EF <= lbu2_e; + end if; + +-- *********************************************************************** + when lbad01 => + if frz then EF <= lbad01; + elsif + ir_opcod(18 downto 13) = lb_i then EF <= lb2_e; + else EF <= lbu2_e; + + end if; + + +-- *********************************************************************** + when lbad10 => + if frz then EF <= lbad10; + elsif + ir_opcod(18 downto 13) = lb_i then EF <= lb2_e; + else EF <= lbu2_e; + + end if; + +-- *********************************************************************** + when lbad11 => + if frz then EF <= lbad11; + elsif + ir_opcod(18 downto 13) = lb_i then EF <= lb2_e; + else EF <= lbu2_e; + + end if; + +-- *********************************************************************** + when lbu2_e => + if frz then EF <= lbu2_e; + elsif rqs then EF <= irq; + + else EF <= init; + + end if; + +-- *********************************************************************** + when lb2_e => + if frz then EF <= lb2_e; + elsif rqs then EF <= irq; + + + else EF <= init; + + end if; + + +-- *********************************************************************** + + when sw_e => + if frz then EF <= sw_e; + else + + EF <= sw1_e; + end if; + +-- *********************************************************************** + + when sw1_e => + if frz then EF <= sw1_e; + else + EF <= ifetch_e ; + end if; + +-- *********************************************************************** + + when sb_e => + if frz then EF <= sb_e; + else + + EF <= sb1_e; + end if; + +-- *********************************************************************** + when sb1_e => + if frz then EF <= sb1_e; + else + EF <= ifetch_e ; + end if; + +-- *********************************************************************** + + when sh_e => + if frz then EF <= sh_e; + else + + EF <= sh1_e; + end if; + +-- *********************************************************************** + when sh1_e => + if frz then EF <= sh1_e; + else + EF <= ifetch_e ; + end if; + +-- *********************************************************************** + + when mfc0_e => + if frz then EF <= mfc0_e; + + elsif ir_opcod(10 downto 8) = sr then EF <= sr2i_e ; + elsif ir_opcod(10 downto 8) = cr then EF <= cr2i_e ; + elsif ir_opcod(10 downto 8) = epc then EF <= epc2i_e ; + elsif ir_opcod(10 downto 8) = bar then EF <= bar2i_e ; + else EF <= ico_e; + end if; + + +-- *********************************************************************** + + when mtc0_e => + if frz then EF <= mtc0_e; + + elsif ir_opcod(10 downto 8) = sr then EF <= i2sr_e ; + elsif ir_opcod(10 downto 8) = cr then EF <= i2cr_e ; + elsif ir_opcod(10 downto 8) = bar then EF <= i2bar_e ; + elsif ir_opcod(10 downto 8) = epc then EF <= i2epc_e ; + else EF <= ico_e ; + end if; + + +-- *********************************************************************** + + when sr2i_e => + if frz then EF <= sr2i_e; + + elsif rqs then + EF <= irq; + + + else EF <= init ; + end if; + + +-- *********************************************************************** + + when i2sr_e => + if frz then + EF <= i2sr_e; + + elsif rqs then + EF <= irq; + else + EF <= init; + end if; + +-- *********************************************************************** + + when cr2i_e => + if frz then EF <= cr2i_e; + + elsif rqs then + EF <= irq; + + + else EF <= init ; + end if; + + +-- *********************************************************************** + + when i2cr_e => + if frz then EF <= i2cr_e; + + elsif rqs then + EF <= irq; + + + else EF <= init ; + end if; + + +-- *********************************************************************** + + when i2epc_e => + if frz then EF <= i2epc_e; + + elsif rqs then + EF <= irq; + + + else EF <= init ; + end if; + + +-- *********************************************************************** + + when epc2i_e => + if frz then EF <= epc2i_e; + + elsif rqs then + EF <= irq; + + + else EF <= init ; + end if; + + +-- *********************************************************************** + + when i2bar_e => + if frz then EF <= i2bar_e; + + elsif rqs then + EF <= irq; + + + else EF <= init ; + end if; + + +-- *********************************************************************** + + when bar2i_e => + if frz then EF <= bar2i_e; + + elsif rqs then + EF <= irq; + + + else EF <= init; + end if; + + +-- *********************************************************************** + + + + when ico_e => + if frz then EF <= ico_e; + else + EF <= irq; + end if; + + +-- *********************************************************************** + + when irq => + if frz then + EF <= irq; + elsif itrqs = '1' then + EF <= epc1 ; + else + EF <= epc2 ; + end if; + + +-- *********************************************************************** + + when epc1 => + if frz then + EF <= epc1; + else + EF <= pct ; + end if; + +-- *********************************************************************** + + when epc2 => + if frz then + EF <= epc2; + else + EF <= pct ; + end if; + +-- *********************************************************************** + + when pct => + if frz then + EF <= pct; + else + EF <= ifetch1_e ; + end if; + + +-- *********************************************************************** + + when ifetch_e => + if frz then EF <= ifetch_e; + + elsif rqs then + EF <= irq; + else EF <= init ; + end if; + +-- *********************************************************************** + when ifetch1_e => + if frz then EF <= ifetch1_e; + else EF<= init ; + end if; + +--************************************************************************* + when ifetch1 => + if frz then EF <= ifetch1; + else + EF <= init ; + end if; + + + end case; + + end if; -- end if of reset = '1' + +--FONCTION DE GENERATION + + IF (test ='1') THEN + excp <= e_nop; + ctlopx <= x_c0; + ctlopy <= y_c0; + ctlalu <= a_sum; + ctlrw <= m_scan; + ctladr <= o_no; + wenable <= r_scan; + ELSE + + case EP is + + when reset0 => + excp <= e_clr; + ctlopx <= x_c0 ; + ctlopy <= y_cad ; + ctlalu <= a_sum ; + wenable <= r_pc ; + ctlrw <= m_no ; + ctladr <= o_no ; + + when reset1 => + excp <= e_clr; + ctlopx <= x_c0 ; + ctlopy <= y_c0 ; + ctlalu <= a_sum ; + wenable <= r_sr ; + ctlrw <= m_no ; + ctladr <= o_no ; + + when init => + excp <= e_ifetch; + ctlopx <= x_pc ; + ctlopy <= y_c4 ; + ctlalu <= a_sum ; + ctlrw <= m_no; + ctladr <= o_no; + if NOT frz then + wenable <= r_pc; + else + wenable <= r_no; + end if; + + when init_rfe => + excp <=e_nop; + ctlopx <= x_pc ; + ctlopy <= y_c4 ; + ctlalu <= a_sum ; + ctlrw <= m_no; + ctladr <= o_no; + if NOT frz then + wenable <= r_pc; + else + wenable <= r_no; + end if; + + when imdu => + excp <= e_nop; + ctlopx <= x_ch ; + ctlopy <= y_i16 ; + ctlalu <= a_and ; + ctlrw <= m_no; + ctladr <= o_no; + if NOT frz then + wenable <= r_ad; + else + wenable <= r_no; + end if; + + when reg1 => + excp <= e_nop; + ctlopx <= x_rt ; + ctlopy <= y_c0 ; + ctlalu <= a_sum ; + ctlrw <= m_no; + ctladr <= o_no; + if NOT frz then + wenable <= r_ad; + else + wenable <= r_no; + end if; + + when reg2 => + excp <= e_nop; + ctlopx <= x_rs ; + ctlopy <= y_c0 ; + ctlalu <= a_sum ; + ctlrw <= m_no; + ctladr <= o_no; + if NOT frz then + wenable <= r_ad; + else + wenable <= r_no; + end if; + + when imd => + excp <= e_nop; + ctlopx <= x_c0 ; + ctlopy <= y_i16 ; + ctlalu <= a_sum ; + ctlrw <= m_no; + ctladr <= o_no; + if NOT frz then + wenable <= r_ad; + else + wenable <= r_no; + end if; + + when lor_e => + excp <= e_ibe ; + ctlopx <= x_rs ; + ctlopy <= y_ad ; + ctlalu <= a_or ; + if frz='0' then + wenable <= r_rd ; + ctlrw <= m_fetch ; + ctladr <= o_fetch ; + else + wenable <= r_no ; + ctlrw <= m_no ; + ctladr <= o_no; + end if; + + when lori_e => + excp <= e_ibe ; + ctlopx <= x_rs ; + ctlopy <= y_ad ; + ctlalu <= a_or ; + if frz='0' then + wenable <= r_rt ; + ctlrw <= m_fetch ; + ctladr <= o_fetch ; + else + wenable <= r_no ; + ctlrw <= m_no ; + ctladr <= o_no; + end if; + + when land_e => + excp<= e_ibe; + ctlopx <= x_rs; + ctlopy <= y_ad; + ctlalu <= a_and; + if NOT frz then + wenable <= r_rd; + ctlrw <= m_fetch; + ctladr <= o_fetch ; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when landi_e => + excp <= e_ibe; + ctlopx <= x_rs; + ctlopy <= y_ad; + ctlalu <= a_and; + if NOT frz then + wenable <= r_rt; + ctlrw <= m_fetch; + ctladr <= o_fetch ; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when lxor_e => + excp<= e_ibe; + ctlopx <= x_rs ; + ctlopy <= y_ad ; + ctlalu <= a_xor ; + if NOT frz then + wenable <= r_rd; + ctlrw <= m_fetch; + ctladr <= o_fetch ; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when lxori_e => + excp<= e_ibe; + ctlopx <= x_rs ; + ctlopy <= y_ad ; + ctlalu <= a_xor ; + if NOT frz then + wenable <= r_rt; + ctlrw <= m_fetch; + ctladr <= o_fetch ; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when lnor_e => + excp <= e_ibe ; + ctlopx <= x_rs ; + ctlopy <= y_ad ; + ctlalu <= a_nor ; + if NOT frz then + wenable <= r_rd; + ctlrw <= m_fetch; + ctladr <= o_fetch ; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when sllv_e => + excp<= e_ibe; + ctlopx <= x_rt ; + ctlopy <= y_ad ; + ctlalu <= a_sll ; + if NOT frz then + wenable <= r_rd; + ctlrw <= m_fetch; + ctladr <= o_fetch ; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when sll_e => + excp<= e_ibe; + ctlopx <= x_rt ; + ctlopy <= y_sham ; + ctlalu <= a_sll ; + if NOT frz then + wenable <= r_rd; + ctlrw <= m_fetch; + ctladr <= o_fetch ; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when srl_e => + excp<= e_ibe; + ctlopx <= x_rt ; + ctlopy <= y_sham ; + ctlalu <= a_srl ; + if NOT frz then + wenable <= r_rd; + ctlrw <= m_fetch; + ctladr <= o_fetch ; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when sra_e => + excp<= e_ibe; + ctlopx <= x_rt ; + ctlopy <= y_sham ; + ctlalu <= a_sra ; + if NOT frz then + wenable <= r_rd; + ctlrw <= m_fetch; + ctladr <= o_fetch ; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + when srlv_e => + excp<= e_ibe; + ctlopx <= x_rt ; + ctlopy <= y_ad ; + ctlalu <= a_srl; + if NOT frz then + wenable <= r_rd; + ctlrw <= m_fetch; + ctladr <= o_fetch ; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when srav_e => + excp<= e_ibe; + ctlopx <= x_rt ; + ctlopy <= y_ad ; + ctlalu <= a_sra ; + if NOT frz then + wenable <= r_rd; + ctlrw <= m_fetch; + ctladr <= o_fetch ; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when lui_e => + excp<= e_ibe; + ctlopx <= x_ad; + ctlopy <= y_c16; + ctlalu <= a_sll; + if NOT frz then + wenable <= r_rt; + ctlrw <= m_fetch; + ctladr <= o_fetch ; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when sltiu_e => + excp<= e_ibe; + ctlopx <= x_rs ; + ctlopy <= y_ad ; + ctlalu <= a_sltu ; + if NOT frz then + wenable <= r_rt; + ctlrw <= m_fetch; + ctladr <= o_fetch ; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when sltu_e => + excp<= e_ibe; + ctlopx <= x_rs ; + ctlopy <= y_ad ; + ctlalu <= a_sltu ; + if NOT frz then + wenable <= r_rd; + ctlrw <= m_fetch; + ctladr <= o_fetch ; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when slt_e => + excp<= e_ibe; + ctlopx <= x_rs ; + ctlopy <= y_ad ; + ctlalu <= a_slt ; + if NOT frz then + wenable <= r_rd; + ctlrw <= m_fetch; + ctladr <= o_fetch ; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when slti_e => + excp<= e_ibe; + ctlopx <= x_rs ; + ctlopy <= y_ad ; + ctlalu <= a_slt ; + if NOT frz then + wenable <= r_rt; + ctlrw <= m_fetch; + ctladr <= o_fetch ; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when beq => + excp<= e_nop; + ctlopx <= x_rs ; + ctlopy <= y_ad ; + ctlalu <= a_dif; + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + + when bne => + excp<= e_nop; + ctlopx <= x_rs ; + ctlopy <= y_ad ; + ctlalu <= a_dif; + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + + when blez => + excp<= e_nop; + ctlopx <= x_rs ; + ctlopy <= y_c0 ; + ctlalu <= a_dif ; + ctlrw <= m_no; + ctladr <= o_no; + wenable <= r_no; + + when bgtz => + excp<= e_nop; + ctlopx <= x_rs ; + ctlopy <= y_c0 ; + ctlalu <= a_dif; + + ctlrw <= m_no; + ctladr <= o_no; + wenable <= r_no; + + when bltz => + excp<= e_nop; + ctlopx <= x_rs ; + ctlopy <= y_c0 ; + ctlalu <= a_dif; + ctlrw <= m_no; + ctladr <= o_no; + wenable <= r_no; + + when bgez => + excp<= e_nop; + ctlopx <= x_rs ; + ctlopy <= y_c0 ; + ctlalu <= a_sum; + ctlrw <= m_no; + ctladr <= o_no; + wenable <= r_no; + + when bltzal => + excp<= e_nop; + ctlopx <= x_pc ; + ctlopy <= y_c0 ; + ctlalu <= a_sum; + ctlrw <= m_no; + ctladr <= o_no; + if NOT frz then + wenable <= r_r31; + else + wenable <= r_no; + end if; + + when bgezal => + excp<= e_nop; + ctlopx <= x_pc ; + ctlopy <= y_c0 ; + ctlalu <= a_sum; + ctlrw <= m_no; + ctladr <= o_no; + if NOT frz then + wenable <= r_r31; + else + wenable <= r_no; + end if; + + when branch_e => + excp<= e_nop; + ctlopx <= x_pc ; + ctlopy <= y_i18 ; + ctlalu <= a_sum; + ctlrw <= m_no; + ctladr <= o_no; + if NOT frz then + wenable <= r_pc; + else + wenable <= r_no; + end if; + + when jal => + excp<= e_nop; + ctlopx <= x_pc ; + ctlopy <= y_c0 ; + ctlalu <= a_sum ; + ctlrw <= m_no; + ctladr <= o_no; + if NOT frz then + wenable <= r_r31; + else + wenable <= r_no; + end if; + + when j_e => + excp<= e_nop; + + ctlopx <= x_pc4 ; + ctlopy <= y_iu28 ; + ctlalu <= a_or ; + ctlrw <= m_no; + ctladr <= o_no; + if NOT frz then + wenable <= r_pc; + else + wenable <= r_no; + end if; + + when jalre => + excp<= e_ifetch; + ctlopx <= x_rs; + ctlopy <= y_c0; + ctlalu <= a_sum; + ctlrw <= m_no; + ctladr <= o_no; + if NOT frz then + wenable <= r_ad; + else + wenable <= r_no; + end if; + + when jalr => + excp<= e_nop; + ctlopx <= x_pc ; + ctlopy <= y_c0 ; + ctlalu <= a_sum ; + ctlrw <= m_no; + ctladr <= o_no; + if NOT frz then + wenable <= r_rd; + else + wenable <= r_no; + end if; + + when jr_e => + excp<= e_nop; + ctlopx <= x_rs; + ctlopy <= y_c0; + ctlalu <= a_sum; + ctlrw <= m_no; + ctladr <= o_no; + if NOT frz then + wenable <= r_ad; + else + wenable <= r_no; + end if; + + when jr => + excp<= e_nop; + ctlopx <= x_ad; + ctlopy <= y_c0 ; + ctlalu <= a_sum ; + ctladr <= o_no; + ctlrw <= m_no; + + if NOT frz then + wenable <= r_pc; + else + wenable <= r_no; + end if; + + when rfe_e => + excp<= e_cpu; + ctlopx <= x_c0 ; + ctlopy <= y_c0 ; + ctlalu <= a_sum ; + wenable <= r_no; + if NOT frz then + ctladr <= o_fetch; + ctlrw <= m_fetch; + else + ctladr <= o_no; + ctlrw <= m_no; + end if; + + when rfe_e_2 => + excp<= e_nop; + ctlopx <= x_c0 ; + ctlopy <= y_c0 ; + ctlalu <= a_sum ; + ctlrw <= m_no; + ctladr <= o_no; + if NOT frz then + wenable <= r_rfe; + else + wenable <= r_no; + end if; + + when syscall_e => + excp<= e_sys; + ctlopx <= x_c0 ; + ctlopy <= y_c0 ; + ctlalu <= a_sum; + ctlrw <= m_no; + ctladr <= o_no; + wenable <= r_no; + + when brk_e => + excp<= e_brk; + ctlopx <= x_c0 ; + ctlopy <= y_c0 ; + ctlalu <= a_sum ; + ctlrw <= m_no; + ctladr <= o_no; + wenable <= r_no; + + when mfhi_e => + excp<= e_cpu; + ctlopx <= x_hi ; + ctlopy <= y_c0 ; + ctlalu <= a_sum ; + if NOT frz then + ctlrw <= m_fetch; + ctladr <= o_fetch; + wenable <= r_rd; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when mthi_e => + excp<= e_cpu; + ctlopx <= x_rs ; + ctlopy <= y_c0 ; + ctlalu <= a_sum ; + if NOT frz then + ctlrw <= m_fetch; + ctladr <= o_fetch; + wenable <= r_hi; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when mtlo_e => + excp<= e_cpu; + ctlopx <= x_rs ; + ctlopy <= y_c0 ; + ctlalu <= a_sum ; + if NOT frz then + ctlrw <= m_fetch; + ctladr <= o_fetch; + wenable <= r_lo; + else + ctlrw <= m_no; + ctladr <= o_no; + wenable <= r_no; + end if; + + when mflo_e => + excp<= e_cpu; + ctlopx <= x_lo ; + ctlopy <= y_c0 ; + ctlalu <= a_sum ; + if NOT frz then + ctlrw <= m_fetch; + ctladr <= o_fetch; + wenable <= r_rd; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when lw1_e => + excp<= e_dbe; + ctlopx <= x_c0; + ctlopy <= y_c0; + ctlalu <= a_sum; + wenable <= r_no; + if NOT frz then + ctlrw <= m_rw; + ctladr <= o_rw; + else + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when lw_e => + excp<= e_lw; + ctlopx <= x_rs; + ctlopy <= y_i16; + ctlalu <= a_sum; + ctlrw <= m_no; + ctladr <= o_no; + if not FRZ then + wenable <= r_ad; + else + wenable <= r_no; + end if; + + when lh1_e => + excp<= e_dbe; + ctlopx <= x_c0; + ctlopy <= y_c0; + ctlalu <= a_sum; + wenable <= r_no; + if NOT frz then + ctlrw <= m_rw; + ctladr <= o_rh; + else + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when lh_e => + excp<= e_lh; + ctlopx <= x_rs; + ctlopy <= y_i16; + ctlalu <= a_sum; + ctlrw <= m_no; + ctladr <= o_no; + if not FRZ then + wenable <= r_ad; + else + wenable <= r_no; + end if; + + when lw2_e => + excp<= e_ibe; + ctlopx <= x_c0 ; + ctlopy <= y_dt ; + ctlalu <= a_sum ; + if NOT frz then + wenable <= r_rt; + ctlrw <= m_fetch; + ctladr <= o_fetch ; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when lhad1 => + excp<= e_nop; + ctlopx <= x_c0; + ctlopy <= y_dt ; + ctlalu <= a_sum; + ctlrw <= m_no; + ctladr <= o_no; + if NOT frz then + wenable <= r_ad; + else + wenable <= r_no; + end if; + + when lhad0 => + excp<= e_nop; + ctlopx <= x_dt; + ctlopy <= y_c16 ; + ctlalu <= a_sll; + ctlrw <= m_no; + ctladr <= o_no; + if NOT frz then + wenable <= r_ad; + else + wenable <= r_no; + end if; + + when lh2_e => + excp<= e_ibe; + ctlopx <= x_ad; + ctlopy <= y_c16; + ctlalu <= a_sra; + if NOT frz then + wenable <= r_rt; + ctlrw <= m_fetch; + ctladr <= o_fetch; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when lhu2_e => + excp<= e_ibe; + ctlopx <= x_ad; + ctlopy <= y_c16; + ctlalu <= a_srl; + if NOT frz then + wenable <= r_rt; + ctlrw <= m_fetch; + ctladr <= o_fetch; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when lb_e => + excp<= e_lb; + ctlopx<= x_rs; + ctlopy<= y_i16; + ctlalu<= a_sum; + ctlrw<= m_no; + ctladr<= o_no; + if NOT frz then + wenable <= r_ad; + else + wenable <= r_no; + end if; + + when lb1_e => + excp<= e_dbe; + ctlopx<= x_c0; + ctlopy<= y_c0; + ctlalu<= a_sum; + wenable<= r_no; + if NOT frz then + ctlrw <= m_rw; + ctladr <= o_rb; + else + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when lbad00 => + excp<= e_nop; + ctlopx <= x_dt; + ctlopy <= y_c24; + ctlalu <= a_sll; + ctlrw <= m_no; + ctladr <= o_no; + if NOT frz then + wenable <= r_ad; + else + wenable <= r_no; + end if; + + when lbad01 => + excp<= e_nop; + ctlopx <= x_dt; + ctlopy <= y_c16; + ctlalu <= a_sll; + ctlrw <= m_no; + ctladr <= o_no; + if NOT frz then + wenable <= r_ad; + else + wenable <= r_no; + end if; + + when lbad10 => + excp<= e_nop; + ctlopx <= x_dt; + ctlopy <= y_c8; + ctlalu <= a_sll; + ctlrw <= m_no; + ctladr <= o_no; + if NOT frz then + wenable <= r_ad; + else + wenable <= r_no; + end if; + when lbad11 => + excp<= e_nop; + ctlopx <= x_dt; + ctlopy <= y_c0; + ctlalu <= a_sum; + ctlrw <= m_no; + ctladr <= o_no; + if NOT frz then + wenable <= r_ad; + else + wenable <= r_no; + end if; + + when lbu2_e => + excp<= e_ibe; + ctlopx <= x_ad; + ctlopy <= y_c24; + ctlalu <= a_srl; + if NOT frz then + wenable <= r_rt; + ctlrw <= m_fetch; + ctladr <= o_no; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when lb2_e => + excp<= e_ibe; + ctlopx <= x_ad; + ctlopy <= y_c24; + ctlalu <= a_sra; + if NOT frz then + wenable <= r_rt; + ctlrw <= m_fetch; + ctladr <= o_no; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when sw_e => + excp<= e_sw; + ctlopx <= x_rs ; + ctlopy <= y_i16 ; + ctlalu <= a_sum ; + ctlrw <= m_no; + ctladr <= o_no; + if NOT frz then + wenable <= r_ad; + else + wenable <= r_no; + + end if; + + when sw1_e => + excp<= e_dbe; + ctlopx <= x_rt ; + ctlopy <= y_c0 ; + ctlalu <= a_sum ; + wenable <= r_no; + if NOT frz then + ctlrw <= m_ww; + ctladr <= o_ww; + else + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when sb_e => + excp<= e_sb; + ctlopx <= x_rs ; + ctlopy <= y_i16 ; + ctlalu <= a_sum ; + ctlrw <= m_no; + ctladr <= o_no; + if NOT frz then + wenable <= r_ad; + else + wenable <= r_no; + end if; + + when sb1_e => + excp<= e_dbe; + ctlopx <= x_rt ; + ctlopy <= y_c0 ; + ctlalu <= a_sum ; + wenable <= r_no; + if NOT frz then + ctlrw <= m_wb; + ctladr <= o_wb; + else + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when sh_e => + excp<= e_sh; + ctlopx <= x_rs ; + ctlopy <= y_i16 ; + ctlalu <= a_sum ; + ctlrw <= m_no; + ctladr <= o_no; + if NOT frz then + wenable <= r_ad; + else + wenable <= r_no; + end if; + + when sh1_e => + excp<= e_dbe; + ctlopx <= x_rt ; + ctlopy <= y_c0; + ctlalu <= a_sum ; + wenable <= r_no; + if NOT frz then + ctlrw <= m_wh; + ctladr <= o_wh; + else + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when mfc0_e => + excp<= e_cpu; + ctlopx <= x_c0 ; + ctlopy <= y_c0 ; + ctlalu <= a_sum ; + ctlrw <= m_no; + ctladr <= o_no; + wenable <= r_no; + + when mtc0_e => + excp<= e_cpu; + ctlopx <= x_c0 ; + ctlopy <= y_c0 ; + ctlalu <= a_sum ; + ctlrw <= m_no; + ctladr <= o_no; + wenable <= r_no; + + when sr2i_e => + excp<= e_ibe; + ctlopx <= x_sr ; + ctlopy <= y_c0 ; + ctlalu <= a_sum ; + if NOT frz then + wenable <= r_rt; + ctlrw <= m_fetch; + ctladr <= o_fetch ; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when i2sr_e => + excp<= e_ibe; + ctlopx <= x_rt ; + ctlopy <= y_c0 ; + ctlalu <= a_sum ; + if NOT frz then + wenable <= r_sr; + ctlrw <= m_fetch; + ctladr <= o_fetch ; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when cr2i_e => + excp<= e_ibe; + ctlopx <= x_cr ; + ctlopy <= y_c0 ; + ctlalu <= a_sum ; + if NOT frz then + wenable <= r_rt; + ctlrw <= m_fetch; + ctladr <= o_fetch ; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when i2cr_e => + excp<= e_ibe; + ctlopx <= x_rt ; + ctlopy <= y_c0 ; + ctlalu <= a_sum ; + if NOT frz then + wenable <= r_cr; + ctlrw <= m_fetch; + ctladr <= o_fetch ; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + + when i2epc_e => + excp<= e_ibe; + ctlopx <= x_rt ; + ctlopy <= y_c0 ; + ctlalu <= a_sum ; + if NOT frz then + wenable <= r_epc; + ctlrw <= m_fetch; + ctladr <= o_fetch ; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when epc2i_e => + excp<= e_ibe; + ctlopx <= x_epc; + ctlopy <= y_c0 ; + ctlalu <= a_sum ; + if NOT frz then + wenable <= r_rt; + ctlrw <= m_fetch; + ctladr <= o_fetch ; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + + when i2bar_e => + excp<= e_ibe; + ctlopx <= x_rt ; + ctlopy <= y_c0 ; + ctlalu <= a_sum ; + if NOT frz then + wenable <= r_bar; + ctlrw <= m_fetch; + ctladr <= o_fetch ; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when bar2i_e => + excp<= e_ibe; + ctlopx <= x_bar; + ctlopy <= y_c0 ; + ctlalu <= a_sum ; + if NOT frz then + wenable <= r_rt; + ctlrw <= m_fetch; + ctladr <= o_fetch ; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when addiu_e => + excp <= e_ibe; + ctlopx <= x_rs; + ctlopy <= y_ad; + ctlalu <= a_sum; + if NOT frz then + wenable <= r_rt; + ctlrw <= m_fetch; + ctladr <= o_fetch; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when addu_e => + excp <= e_ibe; + ctlopx <= x_rs; + ctlopy <= y_ad; + ctlalu <= a_sum; + if NOT frz then + wenable <= r_rd; + ctlrw <= m_fetch; + ctladr <= o_fetch; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when addi_e => + excp <= e_ovf; + ctlopx <= x_rs; + ctlopy <= y_ad; + ctlalu <= a_sum; + + if NOT frz then + wenable <= r_ad; + ctlrw <= m_no; + ctladr <= o_no; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when addi1_e => + excp <= e_ibe; + ctlopx <= x_c0; + ctlopy <= y_ad; + ctlalu <= a_sum; + + if NOT frz then + wenable <= r_rt; + ctlrw <= m_fetch; + ctladr <= o_fetch; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when add_e => + excp <= e_ovf; + ctlopx <= x_rs; + ctlopy <= y_ad; + ctlalu <= a_sum; + + if NOT frz then + wenable <= r_ad; + ctlrw <= m_no; + ctladr <= o_no; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when add1_e => + excp <= e_ibe; + ctlopx <= x_c0; + ctlopy <= y_ad; + ctlalu <= a_sum; + + if NOT frz then + wenable <= r_rd; + ctlrw <= m_fetch; + ctladr <= o_fetch; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when subu_e => + excp <= e_ibe; + ctlopx <= x_rs; + ctlopy <= y_ad; + ctlalu <= a_dif; + if NOT frz then + wenable <= r_rd; + ctlrw <= m_fetch; + ctladr <= o_fetch; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when sub_e => + excp <= e_ovf; + ctlopx <= x_rs; + ctlopy <= y_ad; + ctlalu <= a_dif; + + if NOT frz then + wenable <= r_ad; + ctlrw <= m_no; + ctladr <= o_no; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when sub1_e => + excp <= e_ibe; + ctlopx <= x_c0; + ctlopy <= y_ad; + ctlalu <= a_sum; + + if NOT frz then + wenable <= r_rd; + ctlrw <= m_fetch; + ctladr <= o_fetch; + else + wenable <= r_no; + ctlrw <= m_no; + ctladr <= o_no; + end if; + + + + + + + when ico_e => + excp<= e_ri; + ctlopx <= x_c0 ; + ctlopy <= y_c0 ; + ctlalu <= a_sum ; + ctlrw <= m_no ; + ctladr <= o_no; + wenable <= r_no; + + when irq => + excp <= e_clr; + ctlopx <= x_c0 ; + ctlopy <= y_c0 ; + ctlalu <= a_sum ; + ctlrw <= m_no ; + ctladr <= o_no; + if frz='0' then + wenable <= r_erq ; + else + wenable <= r_no; + end if; + + when epc1 => + excp<= e_nop; + ctlopx <= x_pc ; + ctlopy <= y_c0 ; + ctlalu <= a_sum ; + ctlrw <= m_no ; + ctladr <= o_no; + if NOT frz then + wenable <= r_epc; + else + wenable <= r_no; + end if; + + when epc2 => + excp<= e_nop; + ctlopx <= x_pc; + ctlopy <= y_c4; + ctlalu <= a_dif; + ctlrw <= m_no ; + ctladr <= o_no; + if NOT frz then + wenable <= r_epc; + else + wenable <= r_no; + end if; + + when pct => + excp<= e_nop; + ctlopx <= x_c1; + ctlopy <= y_c0; + ctlalu <= a_sum; + ctlrw <= m_no ; + ctladr <= o_no; + if NOT frz then + wenable <= r_pc; + else + wenable <= r_no; + end if; + + when ifetch_e => + excp<= e_ibe; + ctlopx <= x_c0; + ctlopy <= y_c0 ; + ctlalu <= a_sum ; + wenable <= r_no ; + if NOT frz then + ctlrw <= m_fetch; + ctladr <= o_fetch ; + else + ctlrw <= m_no; + ctladr <= o_no; + end if; + + when ifetch1_e => + excp<= e_ibe; + ctlopx <= x_c0; + ctlopy <= y_ad; + ctlalu <= a_sum; + if NOT frz then + ctlrw <= m_fetch ; + ctladr <= o_fetch; + wenable <= r_bar ; + else + ctlrw <= m_no; + ctladr <= o_no; + wenable <= r_no; + end if; + + when ifetch1 => + excp<= e_ibe; + ctlopx <= x_c0; + ctlopy <= y_c0 ; + ctlalu <= a_sum ; + if NOT frz then + ctlrw <= m_fetch; + ctladr <= o_fetch ; + wenable <= r_erq ; + else + ctlrw <= m_no; + ctladr <= o_no; + wenable <= r_no; + end if; + + + end case; + + END IF; + + + end process; + + process (ck) + begin + + if (ck = '1' and not ck'stable) then + EP <= EF; + end if; + + end process; + +end STATE_MACHINE; diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_sts.vbe b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_sts.vbe new file mode 100644 index 00000000..5be099c1 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/mips_sts.vbe @@ -0,0 +1,567 @@ +-- ### -------------------------------------------------------------- ### +-- # # +-- # file : mips_sts.vbe # +-- # date : august 1996 # +-- # version : v0.0 # +-- # # +-- # origin : this description has been developed by CAO-VLSI team # +-- # at MASI laboratory, University Pierre et Marie Curie # +-- # URA CNRS 818, Institut Blaise Pascal # +-- # 4 Place Jussieu 75252 Paris Cedex 05 - France # +-- # E-mail : cao-vlsi@masi.ibp.fr # +-- # Author : fahim RAHIM_SARWARY # +-- # Modif : Arnaud Caron & Fahim Rahim # +-- # descr. : Behavioural description for status and interrupts # +-- # # +-- # Modif : Tue Nov 19 12:50:15 WET 1996 # +-- # suppression du scan path "maison..." # +-- ### -------------------------------------------------------------- ### + +ENTITY mips_sts IS + PORT( ck : IN BIT ; -- clock + frz : IN BIT ; -- external freeze + test : IN BIT ; -- test mode + opx_sign : IN BIT ; -- operdan's signs and + opy_sign : IN BIT ; -- result sign to + alu_sign : IN BIT ; -- check the + alu_nul : IN BIT ; -- alu result + alu_c31 : IN BIT ; + alu_c30 : IN BIT ; + ctlalu : IN BIT_VECTOR(5 DOWNTO 0); + rs : IN BIT_VECTOR(4 DOWNTO 0); -- register RS + rd : IN BIT_VECTOR(4 DOWNTO 0); -- register RD + rdrt : IN BIT_VECTOR(4 DOWNTO 0); -- register RD or RT + mxrs_rdrt : IN BIT ; -- RD or RT selection + wenable_in : IN BIT_VECTOR(10 DOWNTO 0) ; -- wenable from sequencer + ctlrw_in : IN BIT_VECTOR(4 DOWNTO 0) ; -- MEM from SEQ + ctlrw_out : inout bit_vector(4 downto 1); + adr0 : IN BIT ; -- adr(0) + adr1 : IN BIT ; -- adr(1) + adr31 : IN BIT ; -- adr(31) + + intrqs : IN BIT_VECTOR(5 DOWNTO 0) ; -- external interrupts + intrqs_seq : OUT BIT ; -- intr request to seq + + berr_s : IN BIT; -- bus error + + scin : IN BIT ; -- seq_scout + + alu_test : OUT BIT ; -- check the alu result + + redpnt : OUT BIT_VECTOR(4 DOWNTO 0) ; -- read register + wrtpnt : OUT BIT_VECTOR(4 DOWNTO 0) ; -- write register + + wenable_out : OUT BIT_VECTOR(6 DOWNTO 0) ; -- wenable to datapath + crsr_dpt : IN BIT_VECTOR (15 DOWNTO 0); -- registre satus and cause register from data-path + crsr_out : OUT BIT_VECTOR (15 DOWNTO 0); -- register sataus and cause to data-path + + crsr_mx : IN BIT ; + excp : in bit_vector(6 downto 0); + rqs : OUT BIT ; -- request to SEQ + exq : OUT BIT ; -- exp to SEQ + rw : OUT BIT ; -- ext read write + rw_ctl : OUT BIT_VECTOR(15 DOWNTO 0) ; -- inout data ctl + frz_ctl : OUT BIT_VECTOR(15 DOWNTO 0) ; -- out address ctl + + W : OUT BIT_VECTOR(1 downto 0); + scout : OUT BIT ; -- scout ext + + vdd : IN BIT ; + vss : IN BIT ); + +END mips_sts; + +ARCHITECTURE behavioural of mips_sts is + + SIGNAL wrtpnt1 : BIT_VECTOR(4 downto 0) ; + + SIGNAL ctlrw_out_i : BIT_VECTOR(4 downto 0) ; + + + + -- signals to alu_test output + + SIGNAL slt_s : BIT; + SIGNAL sgt_s : BIT; + SIGNAL sltu_s : BIT; + +-- Modif suppression du signal sgtu_s +--SIGNAL sgtu_s : BIT; + + + -- exceptions + + --SIGNAL unkopc_s : BIT; + --SIGNaL prvins_s : BIT; + SIGNAL if_adderr_s : BIT; + SIGNAL lh_adderr_s : BIT; + SIGNAL lw_adderr_s : BIT; + SIGNAL sgmterr_s : BIT; + SIGNAL sw_adderr_s : BIT; + SIGNAL sh_adderr_s : BIT; + SIGNAL sw_adderr_en : BIT; + SIGNAL sh_adderr_en : BIT; + SIGNAL lw_adderr_en : BIT; + SIGNAL lh_adderr_en : BIT; + SIGNAL if_adderr_en : BIT; + SIGNAL sgmterr_en : BIT; + SIGNAL dbe_en : BIT; + SIGNAL ibe_en : BIT; + SIGNAL adel_x : BIT; + SIGNAL ades_x : BIT; + SIGNAL ibe_s : BIT; + SIGNAL dbe_s : BIT; + SIGNAL ri_x : BIT; + SIGNAL cpu_x : BIT; +-- ajout pour l'ovf + SIGNAL ovf_x : BIT; +-- + SIGNAL rireg_t : BIT; + SIGNAL ibereg_t : BIT; + SIGNAL dbereg_t : BIT; + SIGNAL adelreg_t : BIT; + SIGNAL adesreg_t : BIT; + SIGNAL cpureg_t : BIT; + SIGNAL intrqs_sysreg_t : BIT; + SIGNAL intrqs_brreg_t : BIT; + SIGNAL rireg_x : BIT; + SIGNAL ibereg_x : BIT; + SIGNAL dbereg_x : BIT; + SIGNAL adelreg_x : BIT; + SIGNAL adesreg_x : BIT; + SIGNAL cpureg_x : BIT; + +-- ajout pour ovf + SIGNAL ovfreg_x : BIT; +-- + + SIGNAL intrqs_sysreg : BIT; + SIGNAL intrqs_brreg : BIT; +-- ajout ovfreg_t + SIGNAL ovfreg_t : BIT; +-- + SIGNAL ibe_r : REG_BIT REGISTER; + SIGNAL ri_r : REG_BIT REGISTER; + SIGNAL dbe_r : REG_BIT REGISTER; + SIGNAL adel_r : REG_BIT REGISTER; + SIGNAL cpu_r : REG_BIT REGISTER; + SIGNAL ades_r : REG_BIT REGISTER; + SIGNAL intrqs_sys_r : REG_BIT REGISTER; + SIGNAL intrqs_br_r : REG_BIT REGISTER; +-- ajout registre ovf + SIGNAL ovf_r : REG_BIT REGISTER; + + -- wenable and mux for cause and status registers + SIGNAL wen_cr : BIT; --cr wenable fro writing + SIGNAL wen_erq : BIT; --erq state + + -- cause register + + SIGNAL cr_excod : BIT_VECTOR(3 downto 0); + SIGNAL cr_ip : BIT_VECTOR(5 downto 0); + SIGNAL cr_s : REG_VECTOR(15 downto 0) REGISTER; + SIGNAL cr_out : BIT_VECTOR(15 downto 0) ; + + -- clock and wenable for cause and status register + SIGNAL sr_ckd : BIT; + SIGNAL sr_cke : BIT; + --SIGNAL sr_ckr : BIT; + SIGNAL cr_ckd : BIT; + SIGNAL cr_cke : BIT; + SIGNAL wen_rfe : BIT; + -- status register + + SIGNAL sr_s : REG_VECTOR(15 downto 0) REGISTER; + SIGNAL sr_out : BIT_VECTOR(15 downto 0) ; + SIGNAL wen_sr : BIT; + SIGNAL sr_int : bit_vector(15 downto 0); + SIGNAL cr_int : bit_vector(15 downto 0); + + -- interrupt and exception and reset request ... + + SIGNAL intrqs_s : BIT; + SIGNAL excrqs_s : BIT; + + -- byte + + SIGNAL W_s : BIT_VECTOR( 0 to 1); + + + -- Inout data and out address control + + SIGNAL rw_ctl_n : BIT; + SIGNAL frz_ctl_n : BIT; + + + constant e_sys : bit_vector (6 downto 0) := B"0010000"; + constant e_brk : bit_vector (6 downto 0) := B"0001000"; + constant e_ri : bit_vector (6 downto 0):= B"0000010"; + constant e_cpu : bit_vector (6 downto 0) := B"0000001"; + constant e_nop : bit_vector (6 downto 0) := B"0000000"; + constant e_lw : bit_vector (6 downto 0) := B"0010001"; + constant e_lh : bit_vector (6 downto 0) := B"0010010"; + constant e_lb : bit_vector (6 downto 0) := B"0010100"; + constant e_sw : bit_vector (6 downto 0) := B"0011000"; + constant e_sh : bit_vector (6 downto 0) := B"0011100"; + constant e_sb : bit_vector (6 downto 0) := B"0011110"; + constant e_ifetch : bit_vector (6 downto 0):= B"0011111"; + constant e_ibe : bit_vector (6 downto 0):= B"0100000"; + constant e_dbe : bit_vector (6 downto 0):= B"1000000"; + constant e_clr : bit_vector (6 downto 0):= B"1010101"; + constant e_ovf : bit_vector (6 downto 0):= B"1111111"; + + + + -- Description of the memory access modes + + -- Modif: Thu Nov 7 15:05:10 WET 1996 + -- Voir mips_seq ... + -- constant m_wh : bit_vector (4 downto 0) := B"01101" ; + -- constant m_rh : bit_vector (4 downto 0) := B"00100" ; + constant m_no : bit_vector (4 downto 0) := B"00001" ; + constant m_fetch : bit_vector (4 downto 0) := B"10001" ; + constant m_ww : bit_vector (4 downto 0) := B"00000" ; + constant m_wh : bit_vector (4 downto 0) := B"00100" ; + constant m_wb : bit_vector (4 downto 0) := B"00010" ; + constant m_rw : bit_vector (4 downto 0) := B"01001" ; +-- ajout perso + constant m_scan : bit_vector (4 downto 0) := B"11000" ; + + +BEGIN + + -- alu_test + + sgt_s <= '1' WHEN ( ( opx_sign ='1' XOR opy_sign = '0' ) + AND ( alu_sign = '0' ) + AND ( alu_nul = '0' ) ) ELSE + '1' WHEN ( opx_sign = '0' AND opy_sign = '1' ) ELSE + '0'; + + -- Modif alu_c31 au lieu de sgtu_s + + sltu_s <= '1' when ( alu_c31 = '1' ) else + '0'; + + + slt_s <= NOT(alu_nul) AND NOT(sgt_s); + + + + -- alu_test output + + + -- WITH ctlalu SELECT + -- Modif erreur de constante 001100 au lieu de 001110 + -- Modif syntaxe avec des else au lieu du with select + alu_test <= NOT sltu_s WHEN (ctlalu = "001111") ELSE + NOT slt_s WHEN (ctlalu = "001101") ELSE + '1' ; + + + + -- register file addresses + + redpnt <= rs WHEN mxrs_rdrt = '1' ELSE + rdrt; + + + + + wrtpnt1 <= rdrt WHEN (wenable_in(10) & wenable_in(1 downto 0) = B"100") ELSE + rd WHEN (wenable_in(10) & wenable_in(1 downto 0) = B"101") ELSE + B"11111" WHEN (wenable_in(10) & wenable_in(1 downto 0) = B"110") ELSE + B"00000"; + + + wrtpnt <= wrtpnt1 ; + + -- wenable_out output + + wenable_out <= wenable_in( 10 DOWNTO 4 ) + WHEN ( excrqs_s = '0' ) ELSE + "0000000"; + + -- ctlrw_out output + ctlrw_out_i <= ctlrw_in when(excrqs_s = '0' OR wenable_in(3) OR wenable_in(2)) + else "00001"; + ctlrw_out <= ctlrw_out_i(4 downto 1); + + ri_x <= excp = e_ri ; --illegale codop + -- Modif: Wed Nov 6 15:36:11 WET 1996 + cpu_x <=( sr_s(1) AND (excp=e_cpu)); --coprossor unasable exeption + +-- modif pour l'ovf + ovf_x <= ((alu_c30 XOR alu_c31) AND (excp=e_ovf)); +-- + if_adderr_s <= not (adr0 and adr1); --ifetch or load word non algined address + lh_adderr_s <= not adr0; --load half non algined address + lw_adderr_s <= not(adr0 and adr1); --load word non aligned error + sgmterr_s <= (sr_s(1)) AND not(adr31); --adress error segment + sw_adderr_s <= not(adr0 and adr1); --store word address error + sh_adderr_s <= not(adr0); --store half address error + + -- exceptions enable + + + sw_adderr_en <= excp = e_sw; + sh_adderr_en <= excp = e_sh; + lw_adderr_en <= excp = e_lw; + lh_adderr_en <= excp = e_lh; + if_adderr_en <= excp = e_ifetch; + sgmterr_en <= excp=e_sw OR excp=e_sh OR excp=e_sb OR excp=e_lb OR excp=e_lh OR excp=e_lw OR excp=e_ifetch ; + dbe_en <= excp = e_dbe ; + ibe_en <= excp = e_ibe OR excp = e_ifetch; + + + adel_x <= (lw_adderr_s AND lw_adderr_en) + OR (lh_adderr_en AND lh_adderr_s) + OR (if_adderr_s AND if_adderr_en) + OR (sgmterr_s AND sgmterr_en); + ades_x <= (sw_adderr_s AND sw_adderr_en) + OR (sh_adderr_en AND sh_adderr_s) + OR (sgmterr_en and sgmterr_s); + + ibe_s <= NOT(berr_s) AND ibe_en; + dbe_s <= NOT(berr_s) AND dbe_en; + + -- exception signals for registers + + rireg_x <= ri_x OR ( ri_r AND not( wenable_in( 3 ) AND wenable_in(2 )) ); + ibereg_x <= ibe_s OR ( ibe_r AND not( wenable_in( 3 ) AND wenable_in(2 )) ); + dbereg_x <= dbe_s OR ( dbe_r AND not( wenable_in( 3 ) AND wenable_in(2 )) ); + adelreg_x <= adel_x OR ( adel_r AND not( wenable_in( 3 ) AND wenable_in(2 )) ); + adesreg_x <= ades_x OR ( ades_r AND not( wenable_in( 3 ) AND wenable_in(2 )) ); + cpureg_x <= cpu_x OR ( cpu_r AND not( wenable_in( 3 ) AND wenable_in(2 )) ); +-- ajout pour ovf + ovfreg_x <= ovf_x OR ( ovf_r AND not( wenable_in( 3 ) AND wenable_in(2 )) ); +-- + -- software interrupt for registers + + intrqs_sysreg <= (excp=e_sys) OR (intrqs_sys_r AND not( wenable_in( 3 ) AND wenable_in(2 )) ); + intrqs_brreg <= (excp=e_brk) OR (intrqs_br_r AND not( wenable_in( 3 ) AND wenable_in(2 )) ); + + + intrqs_sysreg_t <= intrqs_sysreg when (frz = '0') else intrqs_sys_r; + intrqs_brreg_t <= intrqs_brreg when (frz ='0') else intrqs_br_r; + rireg_t <= ri_x when(frz ='0') else ri_r ; + ibereg_t <= ibereg_x when(frz ='0') else ibe_r; + dbereg_t <= dbereg_x when(frz ='0') else dbe_r; + adesreg_t <= adesreg_x when(frz = '0') else ades_r; + adelreg_t <= adelreg_x when(frz ='0') else adel_r; + cpureg_t <= cpureg_x when(frz = '0') else cpu_r; +-- ajout pour ovf + ovfreg_t <= ovfreg_x when(frz = '0') else ovf_r; +-- + --software interupt registers + + syscall : BLOCK(ck = '1' AND NOT ck'STABLE) + BEGIN + intrqs_sys_r <= GUARDED '0' when (excp = e_clr) else intrqs_sysreg_t; + END BLOCK; + + break : BLOCK(ck = '1' AND NOT ck'STABLE) + BEGIN + intrqs_br_r <= GUARDED '0' when (excp = e_clr) else intrqs_brreg_t ; + END BLOCK; + + -- exception's registers + + + + ri : BLOCK( ck = '1' AND NOT ck'STABLE ) + BEGIN + ri_r <= GUARDED '0' when (excp = e_clr) else rireg_t ; + END BLOCK; + + + ibe : BLOCK( ck = '1' AND NOT ck'STABLE ) + BEGIN + ibe_r <= GUARDED '0' when (excp = e_clr) else ibereg_t ; + END BLOCK; + + + dbe : BLOCK( ck = '1' AND NOT ck'STABLE ) + BEGIN + dbe_r <= GUARDED '0' when (excp = e_clr) else dbereg_t ; + END BLOCK; + + ades : BLOCK( ck = '1' AND NOT ck'STABLE ) + BEGIN + ades_r <= GUARDED '0' when (excp = e_clr) else adesreg_t ; + END BLOCK; + + adel : BLOCK( ck = '1' AND NOT ck'STABLE ) + BEGIN + adel_r <= GUARDED '0' when (excp = e_clr) else adelreg_t ; + END BLOCK; + + cpu : BLOCK( ck = '1' AND NOT ck'STABLE ) + BEGIN + cpu_r <= GUARDED '0' when (excp = e_clr) else cpureg_t ; + END BLOCK; + + + ovf : BLOCK( ck = '1' AND NOT ck'STABLE ) + BEGIN + ovf_r <= GUARDED '0' when (excp = e_clr) else ovfreg_t ; + END BLOCK; + +-- exception's output in cause register + cr_ip(0) <= NOT(intrqs(0)) AND sr_s(0) AND sr_s(10); + cr_ip(1) <= NOT(intrqs(1)) AND sr_s(0) AND sr_s(11); + cr_ip(2) <= NOT(intrqs(2)) AND sr_s(0) AND sr_s(12); + cr_ip(3) <= NOT(intrqs(3)) AND sr_s(0) AND sr_s(13); + cr_ip(4) <= NOT(intrqs(4)) AND sr_s(0) AND sr_s(14); + cr_ip(5) <= NOT(intrqs(5)) AND sr_s(0) AND sr_s(15); + + + cr_excod <= B"0000" when (cr_ip(0) or cr_ip(1) or cr_ip(2) or cr_ip(3) + or cr_ip(4) or cr_ip(5)) and not(excrqs_s) else + B"1010" when ri_r = '1' else + B"1011" when cpu_r = '1' else + B"0100" when adel_r = '1' else + B"0101" when ades_r = '1' else + B"0110" when ibe_r = '1' else + B"0111" when dbe_r = '1' else + B"1000" when intrqs_sys_r = '1' else + B"1001" when intrqs_br_r = '1' else + -- ajout pour ovf + B"1100" when ovf_r = '1' else + + -- + B"1111"; + + + wen_erq <= (wenable_in(3) AND wenable_in(2) AND wenable_in(1) AND NOT(wenable_in(0))); + wen_cr <= (NOT(wenable_in(3)) AND (wenable_in(2)) AND NOT(wenable_in(1))) and not(excrqs_s) ; + wen_sr <= (wenable_in(3) AND NOT(wenable_in(2)) AND NOT(wenable_in(1))) and not(excrqs_s) ; + wen_rfe <= (wenable_in (3) AND NOT(wenable_in(2)) AND wenable_in(1) AND wenable_in(0)) and not(excrqs_s); + + + + crsr_out <= sr_out when(crsr_mx ='1') ELSE + cr_out; + + +--***************************cause register************************************************************-- + + cr_ckd <= wen_erq; + cr_cke <= wen_cr; + +cr_int <= cr_ip & cr_s(9 downto 6)& cr_excod & B"00" when (cr_ckd) else + cr_ip & crsr_dpt(9 downto 8) & B"00" & cr_s(5 downto 0) when (cr_cke) else + cr_s ; + cr_it : BLOCK(ck = '1' and not ck'stable ) + BEGIN + cr_s <= GUARDED cr_int; + END BLOCK cr_it; + + cr_out <= cr_s; + +--****************************status register******************************-- + + sr_ckd <= wen_erq; + sr_cke <= wen_sr; + sr_int <= sr_s(15 downto 6) & sr_s(3 downto 0) & B"00" when(sr_ckd) else + crsr_dpt when(sr_cke) else + sr_s(15 downto 4) & sr_s (5 downto 2) when (wen_rfe ) + else sr_s; + + sr_rfe : BLOCK(ck = '1' and not ck'stable) + BEGIN + sr_s <= GUARDED sr_int; + END BLOCK sr_rfe; + + sr_out <= sr_s ; + +--**********************************************************************-- + + -- rqs output + intrqs_s <= NOT test AND ( + (cr_s(8) AND sr_s(8) AND sr_s(0)) + OR (cr_s(9) AND sr_s(9) AND sr_s(0)) + OR (NOT(intrqs(0)) AND sr_s(10) AND sr_s(0)) + OR (NOT(intrqs(1)) AND sr_s(11) AND sr_s(0)) + OR (NOT(intrqs(2)) AND sr_s(12) AND sr_s(0)) + OR (NOT(intrqs(3)) AND sr_s(13) AND sr_s(0)) + OR (NOT(intrqs(4)) AND sr_s(14) AND sr_s(0)) + OR (NOT(intrqs(5)) AND sr_s(15) AND sr_s(0)) + OR intrqs_sys_r + OR intrqs_br_r ); + -- Modif: syscall et break sont des interruptions !!! + + excrqs_s <= NOT test AND ( + ibe_r OR ibe_s OR + dbe_r OR dbe_s OR adel_r OR adel_x OR + ades_r OR ades_x OR ri_r OR ri_x OR + cpu_r OR cpu_x OR ovf_r OR ovf_x ); + + --rqs <= (excp = e_clr) OR excrqs_s OR intrqs_s; + rqs <= excrqs_s OR intrqs_s; + exq <= excrqs_s; + intrqs_seq <= intrqs_s; + + -- rw, frz_ctl and rw_ctl output + + rw_ctl_n <= ctlrw_out_i(0) OR frz OR ck OR test; + frz_ctl_n <= frz OR test; + + rw_ctl(15) <= NOT rw_ctl_n ; + rw_ctl(14) <= NOT rw_ctl_n ; + rw_ctl(13) <= NOT rw_ctl_n ; + rw_ctl(12) <= NOT rw_ctl_n ; + rw_ctl(11) <= NOT rw_ctl_n ; + rw_ctl(10) <= NOT rw_ctl_n ; + rw_ctl(9) <= NOT rw_ctl_n ; + rw_ctl(8) <= NOT rw_ctl_n ; + rw_ctl(7) <= NOT rw_ctl_n ; + rw_ctl(6) <= NOT rw_ctl_n ; + rw_ctl(5) <= NOT rw_ctl_n ; + rw_ctl(4) <= NOT rw_ctl_n ; + rw_ctl(3) <= NOT rw_ctl_n ; + rw_ctl(2) <= NOT rw_ctl_n ; + rw_ctl(1) <= NOT rw_ctl_n ; + rw_ctl(0) <= NOT rw_ctl_n ; + + frz_ctl(15) <= NOT frz_ctl_n ; + frz_ctl(14) <= NOT frz_ctl_n ; + frz_ctl(13) <= NOT frz_ctl_n ; + frz_ctl(12) <= NOT frz_ctl_n ; + frz_ctl(11) <= NOT frz_ctl_n ; + frz_ctl(10) <= NOT frz_ctl_n ; + frz_ctl(9) <= NOT frz_ctl_n ; + frz_ctl(8) <= NOT frz_ctl_n ; + frz_ctl(7) <= NOT frz_ctl_n ; + frz_ctl(6) <= NOT frz_ctl_n ; + frz_ctl(5) <= NOT frz_ctl_n ; + frz_ctl(4) <= NOT frz_ctl_n ; + frz_ctl(3) <= NOT frz_ctl_n ; + frz_ctl(2) <= NOT frz_ctl_n ; + frz_ctl(1) <= NOT frz_ctl_n ; + frz_ctl(0) <= NOT frz_ctl_n ; + + -- byte + rw <= ctlrw_out_i(0); + W_s <= "11" WHEN (ctlrw_in = m_ww ) ELSE + "01" WHEN (ctlrw_in = m_wh ) ELSE + "10" WHEN (ctlrw_in = m_wb ) ELSE + "00" ; + + W <= W_s WHEN excrqs_s = '0' ELSE B"00"; + + -- scout output ( non inverted ) + scout <= scin ; + +END behavioural; + + + + + + + + + + + diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/res_vst.pat b/alliance/src/documentation/alliance-examples/mipsR3000/sce/res_vst.pat new file mode 100644 index 00000000..e3276f5d --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/res_vst.pat @@ -0,0 +1,792 @@ + +-- description generated by Pat driver + +-- date : Wed Sep 17 17:20:53 2003 +-- revision : v109 + +-- sequence : mips_cpu + +-- input / output list : +in ck B;; +in reset B;; +in frz B;; +in scin B;; +in test B;; +in vdd B;; +in vss B;; +out rw B;; +out w (0 to 1) B;; +out scout B;; +inout data (31 downto 0) X;; +inout data_adr (31 downto 0) X;; + +begin + +-- Pattern description : + +-- c r f s t v v r w s d d +-- k e r c e d s w c a a +-- s z i s d s o t t +-- e n t u a a +-- t t _ +-- a +-- d +-- r + +< 0 ps> : 1 1 0 0 0 1 0 ?u ?uu ?u ?uuuuuuuu ?uuuuuuuu ; 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+< 35300000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 35350000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 35400000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 35450000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 35500000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 35550000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 35600000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 35650000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 35700000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 35750000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 35800000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 35850000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 35900000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 35950000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 36000000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 36050000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 36100000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 36150000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 36200000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 36250000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 36300000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 36350000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 36400000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 36450000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 36500000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 36550000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 36600000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 36650000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 36700000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 36750000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 36800000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 36850000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 36900000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 36950000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 37000000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 37050000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 37100000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 37150000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 37200000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 37250000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 37300000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 37350000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 37400000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 37450000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 37500000 ps> : 1 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; +< 37550000 ps> : 0 0 0 0 0 1 0 ?* ?** ?* ?******** ?******** ; + +end; diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/rome.vbe b/alliance/src/documentation/alliance-examples/mipsR3000/sce/rome.vbe new file mode 100644 index 00000000..0b5f20d1 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/rome.vbe @@ -0,0 +1,45 @@ +entity rome is + port ( + address : in bit_vector (5 downto 0); + e_n : in bit; + data : out mux_vector (31 downto 0) bus; + vdd : in bit; + vss : in bit); +end rome; + +architecture VBE of rome is + + signal rom_out : bit_vector (31 downto 0); + +begin + + write_out : block (e_n = '0') + begin + data <= guarded rom_out; + end block; + + with address (5 downto 0) select + rom_out <= + X"afdd0000" when B"100000", + X"afdc0004" when B"100001", + X"241c003c" when B"100010", + X"401d6800" when B"100011", + X"00000021" when B"100100", + X"03bce824" when B"100101", + X"241b0010" when B"100110", + X"17bb0008" when B"100111", + X"00000021" when B"101000", + X"8fdd0000" when B"101001", + X"8fdc0004" when B"101010", + X"401f7000" when B"101011", + X"00000021" when B"101100", + X"27ff0004" when B"101101", + X"08000034" when B"101110", + X"00000021" when B"101111", + X"08000030" when B"110000", + X"00000021" when B"110001", + X"42000010" when B"110100", + X"03e00008" when B"110101", + X"00000000" when others; + +end; diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/romr.vbe b/alliance/src/documentation/alliance-examples/mipsR3000/sce/romr.vbe new file mode 100644 index 00000000..1a47038a --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/romr.vbe @@ -0,0 +1,37 @@ +entity romr is + port ( + address : in bit_vector (5 downto 0); + e_n : in bit; + data : out mux_vector (31 downto 0) bus; + vdd : in bit; + vss : in bit); +end romr; + +architecture VBE of romr is + + signal rom_out : bit_vector (31 downto 0); + +begin + + write_out : block (e_n = '0') + begin + data <= guarded rom_out; + end block; + + with address (5 downto 0) select + rom_out <= + X"3c1ec000" when B"000000", + X"37de0000" when B"000001", + X"3c010000" when B"000010", + X"3421ff3c" when B"000011", + X"40816000" when B"000100", + X"3c010000" when B"000101", + X"34210000" when B"000110", + X"40816800" when B"000111", + X"3c1a0040" when B"001000", + X"375a0000" when B"001001", + X"42000010" when B"001010", + X"03400008" when B"001011", + X"00000000" when others; + +end; diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/roms.vbe b/alliance/src/documentation/alliance-examples/mipsR3000/sce/roms.vbe new file mode 100644 index 00000000..4f52f257 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/roms.vbe @@ -0,0 +1,32 @@ +entity roms is + port ( + address : in bit_vector (5 downto 0); + e_n : in bit; + data : out mux_vector (31 downto 0) bus; + vdd : in bit; + vss : in bit); +end roms; + +architecture data_flow of roms is + + signal rom_out : bit_vector (31 downto 0); + +begin + + write_out : block (e_n = '0') + begin + data <= guarded rom_out; + end block; + + with address (5 downto 0) select + rom_out <= + X"08000001" when B"100000", + X"00000021" when B"100001", + X"400ef800" when B"100010", + X"00000021" when B"100011", + X"23ff0004" when B"100100", + X"03e00008" when B"100101", + X"42000010" when B"100110", + X"00000000" when others; + +end; diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/romu.vbe b/alliance/src/documentation/alliance-examples/mipsR3000/sce/romu.vbe new file mode 100644 index 00000000..9ee96800 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/romu.vbe @@ -0,0 +1,43 @@ +entity romu is + port ( + address : in bit_vector (5 downto 0); + e_n : in bit; + data : out mux_vector (31 downto 0) bus; + vdd : in bit; + vss : in bit); +end romu; + +architecture VBE of romu is + + signal rom_out : bit_vector (31 downto 0); + +begin + + write_out : block (e_n = '0') + begin + data <= guarded rom_out; + end block; + + with address (5 downto 0) select + rom_out <= + X"3c1f0040" when B"000000", + X"37ff0028" when B"000001", + X"3c014000" when B"000010", + X"34210050" when B"000011", + X"3c029043" when B"000100", + X"3442ad6b" when B"000101", + X"3c039043" when B"000110", + X"3463ad6b" when B"000111", + X"8c220001" when B"001000", + X"00000021" when B"001001", + X"10620029" when B"001010", + X"00000021" when B"001011", + X"08100036" when B"001100", + X"00000021" when B"001101", + X"08100034" when B"110100", + X"00000021" when B"110101", + X"08100036" when B"110110", + X"00000021" when B"110111", + X"00000000" when others; + +end; diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/sr64_1a.vbe b/alliance/src/documentation/alliance-examples/mipsR3000/sce/sr64_1a.vbe new file mode 100644 index 00000000..3efe7200 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/sr64_1a.vbe @@ -0,0 +1,431 @@ +entity sr64_1a is + + port ( + E_N : in bit ; + W_N : in bit ; + D : in bit ; + Q : out mux_bit bus; + A : in bit_vector (5 downto 0) ; + VDD : in bit ; + VSS : in bit + ); + +end sr64_1a; + + +architecture FUNCTIONAL of sr64_1a is + + signal RAM0_RX , RAM1_RX , RAM2_RX , RAM3_RX , RAM4_RX : reg_bit register; + signal RAM5_RX , RAM6_RX , RAM7_RX , RAM8_RX , RAM9_RX : reg_bit register; + signal RAM10_RX, RAM11_RX, RAM12_RX, RAM13_RX, RAM14_RX : reg_bit register; + signal RAM15_RX, RAM16_RX, RAM17_RX, RAM18_RX, RAM19_RX : reg_bit register; + signal RAM20_RX, RAM21_RX, RAM22_RX, RAM23_RX, RAM24_RX : reg_bit register; + signal RAM25_RX, RAM26_RX, RAM27_RX, RAM28_RX, RAM29_RX : reg_bit register; + signal RAM30_RX, RAM31_RX, RAM32_RX, RAM33_RX, RAM34_RX : reg_bit register; + signal RAM35_RX, RAM36_RX, RAM37_RX, RAM38_RX, RAM39_RX : reg_bit register; + signal RAM40_RX, RAM41_RX, RAM42_RX, RAM43_RX, RAM44_RX : reg_bit register; + signal RAM45_RX, RAM46_RX, RAM47_RX, RAM48_RX, RAM49_RX : reg_bit register; + signal RAM50_RX, RAM51_RX, RAM52_RX, RAM53_RX, RAM54_RX : reg_bit register; + signal RAM55_RX, RAM56_RX, RAM57_RX, RAM58_RX, RAM59_RX : reg_bit register; + signal RAM60_RX, RAM61_RX, RAM62_RX, RAM63_RX : reg_bit register; + + signal READ_SX : bit; + signal WRTEN_SX : bit; + +begin + + WRTEN_SX <= E_N nor W_N; + + wr_0 : block (WRTEN_SX = '1' and A = "000000") + begin + RAM0_RX <= guarded D; + end block; + + wr_1 : block (WRTEN_SX = '1' and A = "000001") + begin + RAM1_RX <= guarded D; + end block; + + wr_2 : block (WRTEN_SX = '1' and A = "000010") + begin + RAM2_RX <= guarded D; + end block; + + wr_3: block (WRTEN_SX = '1' and A = "000011") + begin + RAM3_RX <= guarded D; + end block; + + wr_4: block (WRTEN_SX = '1' and A = "000100") + begin + RAM4_RX <= guarded D; + end block; + + wr_5: block (WRTEN_SX = '1' and A = "000101") + begin + RAM5_RX <= guarded D; + end block; + + wr_6: block (WRTEN_SX = '1' and A = "000110") + begin + RAM6_RX <= guarded D; + end block; + + wr_7: block (WRTEN_SX = '1' and A = "000111") + begin + RAM7_RX <= guarded D; + end block; + + wr_8: block (WRTEN_SX = '1' and A = "001000") + begin + RAM8_RX <= guarded D; + end block; + + wr_9: block (WRTEN_SX = '1' and A = "001001") + begin + RAM9_RX <= guarded D; + end block; + + wr_10: block (WRTEN_SX = '1' and A = "001010") + begin + RAM10_RX <= guarded D; + end block; + + wr_11: block (WRTEN_SX = '1' and A = "001011") + begin + RAM11_RX <= guarded D; + end block; + + wr_12: block (WRTEN_SX = '1' and A = "001100") + begin + RAM12_RX <= guarded D; + end block; + + wr_13: block (WRTEN_SX = '1' and A = "001101") + begin + RAM13_RX <= guarded D; + end block; + + wr_14: block (WRTEN_SX = '1' and A = "001110") + begin + RAM14_RX <= guarded D; + end block; + + wr_15: block (WRTEN_SX = '1' and A = "001111") + begin + RAM15_RX <= guarded D; + end block; + + wr_16: block (WRTEN_SX = '1' and A = "010000") + begin + RAM16_RX <= guarded D; + end block; + + wr_17: block (WRTEN_SX = '1' and A = "010001") + begin + RAM17_RX <= guarded D; + end block; + + wr_18: block (WRTEN_SX = '1' and A = "010010") + begin + RAM18_RX <= guarded D; + end block; + + wr_19: block (WRTEN_SX = '1' and A = "010011") + begin + RAM19_RX <= guarded D; + end block; + + wr_20: block (WRTEN_SX = '1' and A = "010100") + + begin + RAM20_RX <= guarded D; + end block; + + wr_21: block (WRTEN_SX = '1' and A = "010101") + begin + RAM21_RX <= guarded D; + end block; + + wr_22: block (WRTEN_SX = '1' and A = "010110") + begin + RAM22_RX <= guarded D; + end block; + + wr_23: block (WRTEN_SX = '1' and A = "010111") + begin + RAM23_RX <= guarded D; + end block; + + wr_24: block (WRTEN_SX = '1' and A = "011000") + begin + RAM24_RX <= guarded D; + end block; + + wr_25: block (WRTEN_SX = '1' and A = "011001") + begin + RAM25_RX <= guarded D; + end block; + + wr_26: block (WRTEN_SX = '1' and A = "011010") + begin + RAM26_RX <= guarded D; + end block; + + wr_27: block (WRTEN_SX = '1' and A = "011011") + begin + RAM27_RX <= guarded D; + end block; + + wr_28: block (WRTEN_SX = '1' and A = "011100") + begin + RAM28_RX <= guarded D; + end block; + + wr_29: block (WRTEN_SX = '1' and A = "011101") + begin + RAM29_RX <= guarded D; + end block; + + wr_30: block (WRTEN_SX = '1' and A = "011110") + begin + RAM30_RX <= guarded D; + end block; + + wr_31: block (WRTEN_SX = '1' and A = "011111") + begin + RAM31_RX <= guarded D; + end block; + + wr_32: block (WRTEN_SX = '1' and A = "100000") + begin + RAM32_RX <= guarded D; + end block; + + wr_33: block (WRTEN_SX = '1' and A = "100001") + begin + RAM33_RX <= guarded D; + end block; + + wr_34: block (WRTEN_SX = '1' and A = "100010") + begin + RAM34_RX <= guarded D; + end block; + + wr_35: block (WRTEN_SX = '1' and A = "100011") + begin + RAM35_RX <= guarded D; + end block; + + wr_36: block (WRTEN_SX = '1' and A = "100100") + begin + RAM36_RX <= guarded D; + end block; + + wr_37: block (WRTEN_SX = '1' and A = "100101") + begin + RAM37_RX <= guarded D; + end block; + + wr_38: block (WRTEN_SX = '1' and A = "100110") + begin + RAM38_RX <= guarded D; + end block; + + wr_39: block (WRTEN_SX = '1' and A = "100111") + begin + RAM39_RX <= guarded D; + end block; + + wr_40: block (WRTEN_SX = '1' and A = "101000") + begin + RAM40_RX <= guarded D; + end block; + + wr_41: block (WRTEN_SX = '1' and A = "101001") + begin + RAM41_RX <= guarded D; + end block; + + wr_42: block (WRTEN_SX = '1' and A = "101010") + begin + RAM42_RX <= guarded D; + end block; + + wr_43: block (WRTEN_SX = '1' and A = "101011") + begin + RAM43_RX <= guarded D; + end block; + + wr_44: block (WRTEN_SX = '1' and A = "101100") + begin + RAM44_RX <= guarded D; + end block; + + wr_45: block (WRTEN_SX = '1' and A = "101101") + begin + RAM45_RX <= guarded D; + end block; + + wr_46: block (WRTEN_SX = '1' and A = "101110") + begin + RAM46_RX <= guarded D; + end block; + + wr_47: block (WRTEN_SX = '1' and A = "101111") + begin + RAM47_RX <= guarded D; + end block; + + wr_48: block (WRTEN_SX = '1' and A = "110000") + begin + RAM48_RX <= guarded D; + end block; + + wr_49: block (WRTEN_SX = '1' and A = "110001") + begin + RAM49_RX <= guarded D; + end block; + wr_50: block (WRTEN_SX = '1' and A = "110010") + begin + RAM50_RX <= guarded D; + end block; + + wr_51: block (WRTEN_SX = '1' and A = "110011") + begin + RAM51_RX <= guarded D; + end block; + + wr_52: block (WRTEN_SX = '1' and A = "110100") + begin + RAM52_RX <= guarded D; + end block; + + wr_53: block (WRTEN_SX = '1' and A = "110101") + begin + RAM53_RX <= guarded D; + end block; + + wr_54: block (WRTEN_SX = '1' and A = "110110") + begin + RAM54_RX <= guarded D; + end block; + + wr_55: block (WRTEN_SX = '1' and A = "110111") + begin + RAM55_RX <= guarded D; + end block; + + wr_56: block (WRTEN_SX = '1' and A = "111000") + begin + RAM56_RX <= guarded D; + end block; + + wr_57: block (WRTEN_SX = '1' and A = "111001") + begin + RAM57_RX <= guarded D; + end block; + + wr_58: block (WRTEN_SX = '1' and A = "111010") + begin + RAM58_RX <= guarded D; + end block; + + wr_59: block (WRTEN_SX = '1' and A = "111011") + begin + RAM59_RX <= guarded D; + end block; + + wr_60: block (WRTEN_SX = '1' and A = "111100") + begin + RAM60_RX <= guarded D; + end block; + + wr_61: block (WRTEN_SX = '1' and A = "111101") + begin + RAM61_RX <= guarded D; + end block; + + wr_62: block (WRTEN_SX = '1' and A = "111110") + begin + RAM62_RX <= guarded D; + end block; + + wr_63: block (WRTEN_SX = '1' and A = "111111") + begin + RAM63_RX <= guarded D; + end block; + + with A (5 downto 0) select + READ_SX <= RAM0_RX when "000000", + RAM1_RX when "000001", + RAM2_RX when "000010", + RAM3_RX when "000011", + RAM4_RX when "000100", + RAM5_RX when "000101", + RAM6_RX when "000110", + RAM7_RX when "000111", + RAM8_RX when "001000", + RAM9_RX when "001001", + RAM10_RX when "001010", + RAM11_RX when "001011", + RAM12_RX when "001100", + RAM13_RX when "001101", + RAM14_RX when "001110", + RAM15_RX when "001111", + RAM16_RX when "010000", + RAM17_RX when "010001", + RAM18_RX when "010010", + RAM19_RX when "010011", + RAM20_RX when "010100", + RAM21_RX when "010101", + RAM22_RX when "010110", + RAM23_RX when "010111", + RAM24_RX when "011000", + RAM25_RX when "011001", + RAM26_RX when "011010", + RAM27_RX when "011011", + RAM28_RX when "011100", + RAM29_RX when "011101", + RAM30_RX when "011110", + RAM31_RX when "011111", + RAM32_RX when "100000", + RAM33_RX when "100001", + RAM34_RX when "100010", + RAM35_RX when "100011", + RAM36_RX when "100100", + RAM37_RX when "100101", + RAM38_RX when "100110", + RAM39_RX when "100111", + RAM40_RX when "101000", + RAM41_RX when "101001", + RAM42_RX when "101010", + RAM43_RX when "101011", + RAM44_RX when "101100", + RAM45_RX when "101101", + RAM46_RX when "101110", + RAM47_RX when "101111", + RAM48_RX when "110000", + RAM49_RX when "110001", + RAM50_RX when "110010", + RAM51_RX when "110011", + RAM52_RX when "110100", + RAM53_RX when "110101", + RAM54_RX when "110110", + RAM55_RX when "110111", + RAM56_RX when "111000", + RAM57_RX when "111001", + RAM58_RX when "111010", + RAM59_RX when "111011", + RAM60_RX when "111100", + RAM61_RX when "111101", + RAM62_RX when "111110", + RAM63_RX when "111111", + '0' when others; + + wr_q : block (E_N = '0' and W_N = '1') + begin + Q <= guarded READ_SX; + end block; + +end FUNCTIONAL ; diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/sr64_32a.vst b/alliance/src/documentation/alliance-examples/mipsR3000/sce/sr64_32a.vst new file mode 100644 index 00000000..bf6164ce --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/sr64_32a.vst @@ -0,0 +1,69 @@ +entity sr64_32a is + + port ( + E_N : in bit_vector ( 0 to 3) ; + W_N : in bit ; + DAT : inout mux_vector (31 downto 0) bus; + ADR : in bit_vector ( 5 downto 0) ; + VDD : in bit ; + VSS : in bit + ); + +end sr64_32a; + +architecture STRUCTURAL of sr64_32a is + + component sr64_8a + port ( + E_N : in bit ; + W_N : in bit ; + DAT : inout mux_vector (7 downto 0) bus; + ADR : in bit_vector (5 downto 0) ; + VDD : in bit ; + VSS : in bit + ); + end component; + +begin + + byte0 : sr64_8a + port map( + E_N => E_N (0) , + W_N => W_N , + DAT => DAT (31 downto 24) , + ADR => ADR , + VDD => VDD , + VSS => VSS + ); + + byte1 : sr64_8a + port map( + E_N => E_N (1) , + W_N => W_N , + DAT => DAT (23 downto 16) , + ADR => ADR , + VDD => VDD , + VSS => VSS + ); + + byte2 : sr64_8a + port map( + E_N => E_N (2) , + W_N => W_N , + DAT => DAT (15 downto 8) , + ADR => ADR , + VDD => VDD , + VSS => VSS + ); + + byte3 : sr64_8a + port map( + E_N => E_N (3) , + W_N => W_N , + DAT => DAT ( 7 downto 0) , + ADR => ADR , + VDD => VDD , + VSS => VSS + ); + +end ; diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/sr64_8a.vst b/alliance/src/documentation/alliance-examples/mipsR3000/sce/sr64_8a.vst new file mode 100644 index 00000000..4b26af02 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/sr64_8a.vst @@ -0,0 +1,118 @@ +entity sr64_8a is + + port ( + E_N : in bit ; + W_N : in bit ; + DAT : inout mux_vector ( 7 downto 0) bus; + ADR : in bit_vector ( 5 downto 0) ; + VDD : in bit ; + VSS : in bit + ); + +end sr64_8a; + +architecture STRUCTURAL of sr64_8a is + + component sr64_1a + port ( + E_N : in bit ; + W_N : in bit ; + D : in bit ; + Q : out mux_bit bus; + A : in bit_vector (5 downto 0) ; + VDD : in bit ; + VSS : in bit + ); + end component; + +begin + + bit7 : sr64_1a + port map ( + E_N => E_N , + W_N => W_N , + D => DAT (7) , + Q => DAT (7) , + A => ADR , + VDD => VDD , + VSS => VSS + ); + + bit6 : sr64_1a + port map ( + E_N => E_N , + W_N => W_N , + D => DAT (6) , + Q => DAT (6) , + A => ADR , + VDD => VDD , + VSS => VSS + ); + + bit5 : sr64_1a + port map ( + E_N => E_N , + W_N => W_N , + D => DAT (5) , + Q => DAT (5) , + A => ADR , + VDD => VDD , + VSS => VSS + ); + + bit4 : sr64_1a + port map ( + E_N => E_N , + W_N => W_N , + D => DAT (4) , + Q => DAT (4) , + A => ADR , + VDD => VDD , + VSS => VSS + ); + + bit3 : sr64_1a + port map ( + E_N => E_N , + W_N => W_N , + D => DAT (3) , + Q => DAT (3) , + A => ADR , + VDD => VDD , + VSS => VSS + ); + + bit2 : sr64_1a + port map ( + E_N => E_N , + W_N => W_N , + D => DAT (2) , + Q => DAT (2) , + A => ADR , + VDD => VDD , + VSS => VSS + ); + + bit1 : sr64_1a + port map ( + E_N => E_N , + W_N => W_N , + D => DAT (1) , + Q => DAT (1) , + A => ADR , + VDD => VDD , + VSS => VSS + ); + + bit0 : sr64_1a + port map ( + E_N => E_N , + W_N => W_N , + D => DAT (0) , + Q => DAT (0) , + A => ADR , + VDD => VDD , + VSS => VSS + ); + +end ; diff --git a/alliance/src/documentation/alliance-examples/mipsR3000/sce/timer.vbe b/alliance/src/documentation/alliance-examples/mipsR3000/sce/timer.vbe new file mode 100644 index 00000000..0ddf6591 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/mipsR3000/sce/timer.vbe @@ -0,0 +1,320 @@ +-- ### -------------------------------------------------------------- ### +-- # # +-- # file : timer.vbe # +-- # date : Jul 21 1995 # +-- # version : v0.1 # +-- # # +-- # origin : this description has been developed by CAO-VLSI team # +-- # at MASI laboratory, University Pierre et Marie Curie # +-- # 4 Place Jussieu 75252 Paris Cedex 05 - France # +-- # # +-- # descr. : data flow description of a programable timer. # +-- # - 7 compteurs 32 bits (6 int. et le reset) # +-- # - un registre status # +-- # Fonctionnement: On met le nombre de cycles dans le # +-- # compteur associe, puis on passe le status a 1. # +-- # Mis a part le reset qui reste actif seulement un # +-- # cycle, les autre lignes restent a l'etat bas tant # +-- # que leur statut est a 1. # +-- ### -------------------------------------------------------------- ### + +entity TIMER is + + port ( + CK : in bit ; -- external clock + FRZ : in bit ; -- freeze + RESET_I : in bit ; -- reset input + SEL : in bit_vector ( 2 downto 0) ; -- register selection + DATA : inout mux_vector (31 downto 0) bus; -- data + RW : in bit ; -- access mode + E_N : in bit ; -- chip enable + RESET_O : out bit ; -- reset output (= TIMER_RESET OR RESET_I) + IRQ_N : out bit_vector(5 downto 0) ; -- interrupt request + VDD : in bit ; -- + VSS : in bit -- + ); + +end; + +architecture FUNCTIONAL of TIMER is + + signal NOT_CK : bit ; + + signal CLK_SX : bit ; + -- Status Register + signal status_r : reg_vector( 6 downto 0) register ; + signal status_wen : bit ; + -- Int Register 0 to 6 + signal reg_0 : reg_vector(31 downto 0) register ; + signal reg_1 : reg_vector(31 downto 0) register ; + signal reg_2 : reg_vector(31 downto 0) register ; + signal reg_3 : reg_vector(31 downto 0) register ; + signal reg_4 : reg_vector(31 downto 0) register ; + signal reg_5 : reg_vector(31 downto 0) register ; + + -- Write enable pour reg_0 a reg_5 + signal reg0_wen : bit ; + signal reg1_wen : bit ; + signal reg2_wen : bit ; + signal reg3_wen : bit ; + signal reg4_wen : bit ; + signal reg5_wen : bit ; + + -- Decrementation des registres + signal dec_0 : bit_vector( 31 downto 0) ; + signal dec_1 : bit_vector( 31 downto 0) ; + signal dec_2 : bit_vector( 31 downto 0) ; + signal dec_3 : bit_vector( 31 downto 0) ; + signal dec_4 : bit_vector( 31 downto 0) ; + signal dec_5 : bit_vector( 31 downto 0) ; + signal cry_0 : bit_vector( 32 downto 0) ; + signal cry_1 : bit_vector( 32 downto 0) ; + signal cry_2 : bit_vector( 32 downto 0) ; + signal cry_3 : bit_vector( 32 downto 0) ; + signal cry_4 : bit_vector( 32 downto 0) ; + signal cry_5 : bit_vector( 32 downto 0) ; + + signal reset_dec: bit_vector( 31 downto 0) ; + signal reset_cry: bit_vector( 32 downto 0) ; + + -- Reset register + signal reset_r : reg_vector(31 downto 0) register ; + signal reset_wen: bit ; + signal reset : bit ; + + -- IRQ : Pour visualiser dans le res.pat !!! + signal IRQ : bit_vector(5 downto 0) ; + + signal reg0_in : bit_vector( 31 downto 0) ; + signal reg1_in : bit_vector( 31 downto 0) ; + signal reg2_in : bit_vector( 31 downto 0) ; + signal reg3_in : bit_vector( 31 downto 0) ; + signal reg4_in : bit_vector( 31 downto 0) ; + signal reg5_in : bit_vector( 31 downto 0) ; + signal reg_reset_in : bit_vector( 31 downto 0) ; +begin + + NOT_CK <= NOT(CK) ; + + CLK_SX <= NOT_CK and not FRZ; + + reg0_wen <= '1' when ((sel(2 downto 0)) = B"000" and (E_N = '0') and (rw = '0') and (status_r(0) = '0')) + else '0' ; + reg1_wen <= '1' when ((sel(2 downto 0)) = B"001" and (E_N = '0') and (rw = '0') and (status_r(1) = '0')) + else '0' ; + reg2_wen <= '1' when ((sel(2 downto 0)) = B"010" and (E_N = '0') and (rw = '0') and (status_r(2) = '0')) + else '0' ; + reg3_wen <= '1' when ((sel(2 downto 0)) = B"011" and (E_N = '0') and (rw = '0') and (status_r(3) = '0')) + else '0' ; + reg4_wen <= '1' when ((sel(2 downto 0)) = B"100" and (E_N = '0') and (rw = '0') and (status_r(4) = '0')) + else '0' ; + reg5_wen <= '1' when ((sel(2 downto 0)) = B"101" and (E_N = '0') and (rw = '0') and (status_r(5) = '0')) + else '0' ; + reset_wen <= '1' when ((sel(2 downto 0)) = B"110" and (E_N = '0') and (rw = '0') and (status_r(6) = '0')) + else '0' ; + + status_wen <= '1' when ((sel(2 downto 0)) = B"111" and (E_N = '0') and (rw = '0')) else '0' ; + + dec_0 (31 downto 0) <= not reg_0 xor cry_0 (31 downto 0); + cry_0 (32 downto 1) <= reg_0 or cry_0 (31 downto 0); + cry_0 (0) <= '0'; + + assert (not(reg0_wen)) + report "==== writing data to reg_0 ====" + severity WARNING; + + with (((status_r(0) = '1') and not(reg_0 = X"00000000")) & reg0_wen & reset) select + reg0_in <= dec_0 when B"100", + data when B"010", + X"00000000" when B"001" | B"011" | B"101" | B"111", + reg_0 when others; + + count0 : block (CLK_SX = '0' and not CLK_SX'STABLE) + begin + reg_0 <= guarded reg0_in; + end block ; + + --count00 : block (CLK_SX = '0' and not CLK_SX'STABLE and status_r(0) = '1' and not(reg_0 = X"00000000")) + --begin + -- reg_0 <= guarded dec_0 ; + --end block; + --count01 : block (CLK_SX = '0' and not CLK_SX'STABLE and (reg0_wen = '1')) + --begin + -- reg_0 <= guarded data; + --end block ; + + dec_1 (31 downto 0) <= not reg_1 xor cry_1 (31 downto 0); + cry_1 (32 downto 1) <= reg_1 or cry_1 (31 downto 0); + cry_1 (0) <= '0'; + + with (((status_r(1) = '1') and not(reg_1 = X"00000000")) & reg1_wen & reset) select + reg1_in <= dec_1 when B"100", + data when B"010", + X"00000000" when B"001" | B"011" | B"101" | B"111", + reg_1 when others; + + count1 : block (CLK_SX = '0' and not CLK_SX'STABLE) + begin + reg_1 <= guarded reg1_in; + end block ; + + + --count10 : block (CLK_SX = '0' and not CLK_SX'STABLE and status_r(1) = '1' and not(reg_1 = X"00000000")) + --begin + -- reg_1 <= guarded dec_1 ; + --end block; + --count11 : block (CLK_SX = '0' and not CLK_SX'STABLE and (reg1_wen = '1')) + --begin + -- reg_1 <= guarded data; + --end block ; + + dec_2 (31 downto 0) <= not reg_2 xor cry_2 (31 downto 0); + cry_2 (32 downto 1) <= reg_2 or cry_2 (31 downto 0); + cry_2 (0) <= '0'; + + with (((status_r(2) = '1') and not(reg_2 = X"00000000")) & reg2_wen & reset) select + reg2_in <= dec_2 when B"100", + data when B"010", + X"00000000" when B"001" | B"011" | B"101" | B"111", + reg_2 when others; + + count2 : block (CLK_SX = '0' and not CLK_SX'STABLE) + begin + reg_2 <= guarded reg2_in; + end block ; + + --count20 : block (CLK_SX = '0' and not CLK_SX'STABLE and status_r(2) = '1' and not(reg_2 = X"00000000")) + --begin + -- reg_2 <= guarded dec_2 ; + --end block; + --count21 : block (CLK_SX = '0' and not CLK_SX'STABLE and (reg2_wen = '1')) + --begin + -- reg_2 <= guarded data; + --end block ; + + dec_3 (31 downto 0) <= not reg_3 xor cry_3 (31 downto 0); + cry_3 (32 downto 1) <= reg_3 or cry_3 (31 downto 0); + cry_3 (0) <= '0'; + + with (((status_r(3) = '1') and not(reg_3 = X"00000000")) & reg3_wen & reset) select + reg3_in <= dec_3 when B"100", + data when B"010", + X"00000000" when B"001" | B"011" | B"101" | B"111", + reg_3 when others; + + count3 : block (CLK_SX = '0' and not CLK_SX'STABLE) + begin + reg_3 <= guarded reg3_in; + end block ; + + --count30 : block (CLK_SX = '0' and not CLK_SX'STABLE and status_r(3) = '1' and not(reg_3 = X"00000000")) + --begin + -- reg_3 <= guarded dec_3 ; + --end block; + --count31 : block (CLK_SX = '0' and not CLK_SX'STABLE and (reg3_wen = '1')) + --begin + -- reg_3 <= guarded data; + --end block ; + + dec_4 (31 downto 0) <= not reg_4 xor cry_4 (31 downto 0); + cry_4 (32 downto 1) <= reg_4 or cry_4 (31 downto 0); + cry_4 (0) <= '0'; + + with (((status_r(4) = '1') and not(reg_4 = X"00000000")) & reg4_wen & reset) select + reg4_in <= dec_4 when B"100", + data when B"010", + X"00000000" when B"001" | B"011" | B"101" | B"111", + reg_4 when others; + + count4 : block (CLK_SX = '0' and not CLK_SX'STABLE) + begin + reg_4 <= guarded reg4_in; + end block ; + + --count40 : block (CLK_SX = '0' and not CLK_SX'STABLE and status_r(4) = '1' and not(reg_4 = X"00000000")) + --begin + -- reg_4 <= guarded dec_4 ; + --end block; + --count41 : block (CLK_SX = '0' and not CLK_SX'STABLE and (reg4_wen = '1')) + --begin + -- reg_4 <= guarded data; + --end block ; + + dec_5 (31 downto 0) <= not reg_5 xor cry_5 (31 downto 0); + cry_5 (32 downto 1) <= reg_5 or cry_5 (31 downto 0); + cry_5 (0) <= '0'; + + with (((status_r(5) = '1') and not(reg_5 = X"00000000")) & reg5_wen & reset) select + reg5_in <= dec_5 when B"100", + data when B"010", + X"00000000" when B"001" | B"011" | B"101" | B"111", + reg_5 when others; + + count5 : block (CLK_SX = '0' and not CLK_SX'STABLE) + begin + reg_5 <= guarded reg5_in; + end block ; + + --count50 : block (CLK_SX = '0' and not CLK_SX'STABLE and status_r(5) = '1' and not(reg_5 = X"00000000")) + --begin + -- reg_5 <= guarded dec_5 ; + --end block; + --count51 : block (CLK_SX = '0' and not CLK_SX'STABLE and (reg5_wen = '1')) + --begin + -- reg_5 <= guarded data; + --end block ; + + reset_dec (31 downto 0) <= not reset_r xor reset_cry (31 downto 0); + reset_cry (32 downto 1) <= reset_r or reset_cry (31 downto 0); + reset_cry (0) <= '0'; + + with ((status_r(6) = '1') & reset_wen & reset) select + reg_reset_in <= reset_dec when B"100", + data when B"010", + X"00000000" when B"001" | B"011" | B"101" | B"111", + reset_r when others; + + reset_dec : block (CLK_SX = '0' and not CLK_SX'STABLE) + begin + reset_r <= guarded reg_reset_in; + end block ; + + --reset_dec : block (CLK_SX = '0' and not CLK_SX'STABLE and status_r(6) = '1') + --begin + -- reset_r <= guarded reset_dec ; + --end block; + --reset_wri : block (CLK_SX = '0' and not CLK_SX'STABLE and (reset_wen = '1')) + --begin + -- reset_r <= guarded data; + --end block ; + + -- reset du timer.... + reset <= RESET_I or ((reset_r = X"0000_0000") and (status_r(6) = '1')) ; + --status_reset : block (CLK_SX = '0' and not CLK_SX'STABLE and status_wen and reset) + status_reset : block (CLK_SX = '0' and not CLK_SX'STABLE and reset) + begin + status_r <= guarded B"0000000" ; + end block ; + + -- Ecriture du status + status_write : block (CLK_SX = '0' and not CLK_SX'STABLE and status_wen and not reset) + begin + status_r <= guarded data(6 downto 0) ; + end block ; + + -- Affectation des sorties + status_read : block ((sel(2 downto 0)) = B"111" and (E_N = '0') and (rw = '1')) + begin + data <= guarded (B"0000_0000_0000_0000_0000_0000_0" & status_r) ; + end block ; + + IRQ(0) <= '0' when ((reg_0 = X"0000_0000") and (status_r(0) = '1')) else '1' ; + IRQ(1) <= '0' when ((reg_1 = X"0000_0000") and (status_r(1) = '1')) else '1' ; + IRQ(2) <= '0' when ((reg_2 = X"0000_0000") and (status_r(2) = '1')) else '1' ; + IRQ(3) <= '0' when ((reg_3 = X"0000_0000") and (status_r(3) = '1')) else '1' ; + IRQ(4) <= '0' when ((reg_4 = X"0000_0000") and (status_r(4) = '1')) else '1' ; + IRQ(5) <= '0' when ((reg_5 = X"0000_0000") and (status_r(5) = '1')) else '1' ; + + IRQ_N <= IRQ ; + RESET_O <= reset ; +end;