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- Cells, for compliance with the Coriolis2 router Kite. 

+ Change: In dp_sxlib, dp_mux_x4 & dp_nmux_x1 removes METAL2 blockages
      under METAL3 terminals and replace them by strips of METAL2 belonging
      to the relevelant net. The previous configuration was generating
      impossible cases for Kite to solve.
This commit is contained in:
Jean-Paul Chaput 2013-12-11 14:20:08 +00:00
parent 7f331cf5e4
commit d4125cb8d1
2 changed files with 78 additions and 76 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
alliance/src/cells/src/dp_sxlib/dp_mux_x4.ap
View File

@ -1,5 +1,5 @@
V ALLIANCE : 6
H dp_mux_x4,P,10/11/2000,100
H dp_mux_x4,P,12/11/2013,100
A 0,0,4500,5000
R 3500,2000,ref_ref,sel0
R 2500,2000,ref_ref,sel1
@ -23,6 +23,8 @@ R 2000,2500,ref_ref,i1_25
R 2000,3000,ref_ref,i1_30
R 2000,3500,ref_ref,i1_35
R 2000,4000,ref_ref,i1_40
S 3000,2000,3500,2000,200,sel0,LEFT,CALU2
S 2000,2000,2500,2000,200,sel1,RIGHT,CALU2
S 3800,3000,4000,3000,100,*,RIGHT,POLY
S 3800,3000,3800,3100,100,*,DOWN,POLY
S 3400,2000,3400,3100,100,*,DOWN,POLY
@ -66,7 +68,6 @@ S 2900,300,2900,1100,300,*,UP,NDIF
S 3800,900,4000,900,100,*,LEFT,POLY
S 3500,1500,3500,4000,100,*,UP,ALU1
S 3400,900,3400,1600,100,*,UP,POLY
S 2500,2000,3500,2000,200,*,RIGHT,TALU2
S 2500,2000,2500,2000,200,sel1,LEFT,CALU3
S 3500,2000,3500,2000,200,sel0,LEFT,CALU3
S 1000,1000,1000,4000,200,q,UP,CALU1

149
alliance/src/cells/src/dp_sxlib/dp_nmux_x1.ap
View File

@ -1,80 +1,81 @@
V ALLIANCE : 6
H dp_nmux_x1,P,15/11/2000,100
H dp_nmux_x1,P,11/12/2013,100
A 0,0,3000,5000
R 500,1500,ref_ref,i1_15
R 500,1000,ref_ref,i1_10
R 1500,1000,ref_ref,nq_10
R 1500,1500,ref_ref,nq_15
R 2500,1000,ref_ref,i0_10
R 2500,1500,ref_ref,i0_15
R 2500,2000,ref_ref,i0_20
R 500,2000,ref_ref,i1_20
R 500,2500,ref_ref,i1_25
R 500,3000,ref_ref,i1_30
R 500,3500,ref_ref,i1_35
R 500,4000,ref_ref,i1_40
R 2500,2500,ref_ref,i0_25
R 2500,4000,ref_ref,i0_40
R 2500,3500,ref_ref,i0_35
R 2500,3000,ref_ref,i0_30
R 1500,3500,ref_ref,nq_35
R 1500,3000,ref_ref,nq_30
R 1500,2500,ref_ref,nq_25
R 1500,2000,ref_ref,nq_20
R 1000,2000,ref_ref,sel1
R 2000,2000,ref_ref,sel0
S 2400,2600,2400,4400,100,*,UP,PTRANS
S 1500,2800,1500,4200,500,*,UP,PDIF
S 1900,2600,1900,4400,100,*,UP,PTRANS
S 1100,2600,1100,4400,100,*,UP,PTRANS
S 600,2600,600,4400,100,*,UP,PTRANS
S 2000,2000,2000,2000,200,sel0,LEFT,CALU3
S 1000,2000,1000,2000,200,sel1,LEFT,CALU3
S 600,1900,600,2600,100,*,UP,POLY
S 2400,1900,2400,2600,100,*,UP,POLY
S 300,400,300,1700,300,*,DOWN,NDIF
S 2700,400,2700,1700,300,*,DOWN,NDIF
S 1900,600,1900,1900,100,*,DOWN,NTRANS
S 1500,800,1500,1700,500,*,UP,NDIF
S 1100,600,1100,1900,100,*,DOWN,NTRANS
S 2400,600,2400,1900,100,*,DOWN,NTRANS
S 600,600,600,1900,100,*,DOWN,NTRANS
S 1500,2600,1900,2600,100,*,RIGHT,POLY
S 1500,2100,1500,2600,100,*,UP,POLY
S 900,2100,1500,2100,100,*,RIGHT,POLY
S 2000,2000,2000,4000,100,*,UP,ALU1
S 1000,4000,2000,4000,100,*,LEFT,ALU1
S 1000,2500,1000,4000,100,*,DOWN,ALU1
S 2700,2800,2700,4500,300,*,UP,PDIF
S 300,2800,300,4500,300,*,UP,PDIF
S 0,4000,3000,4000,2600,*,RIGHT,NWELL
S 1000,2000,2000,2000,200,*,RIGHT,TALU2
S 0,300,3000,300,600,vss,RIGHT,CALU1
S 0,4700,3000,4700,600,vdd,RIGHT,CALU1
S 2500,1000,2500,4000,200,i0,UP,CALU1
S 500,1000,500,4000,200,i1,UP,CALU1
R 1000,2000,ref_ref,sel1
R 1500,2000,ref_ref,nq_20
R 1500,2500,ref_ref,nq_25
R 1500,3000,ref_ref,nq_30
R 1500,3500,ref_ref,nq_35
R 2500,3000,ref_ref,i0_30
R 2500,3500,ref_ref,i0_35
R 2500,4000,ref_ref,i0_40
R 2500,2500,ref_ref,i0_25
R 500,4000,ref_ref,i1_40
R 500,3500,ref_ref,i1_35
R 500,3000,ref_ref,i1_30
R 500,2500,ref_ref,i1_25
R 500,2000,ref_ref,i1_20
R 2500,2000,ref_ref,i0_20
R 2500,1500,ref_ref,i0_15
R 2500,1000,ref_ref,i0_10
R 1500,1500,ref_ref,nq_15
R 1500,1000,ref_ref,nq_10
R 500,1000,ref_ref,i1_10
R 500,1500,ref_ref,i1_15
S 1800,2000,2000,2000,200,sel0,LEFT,ALU2
S 1000,2000,1200,2000,200,sel1,RIGHT,ALU2
S 1500,1000,1500,3500,200,nq,UP,CALU1
V 1500,4700,CONT_BODY_N,*
V 2100,4700,CONT_BODY_N,*
V 900,4700,CONT_BODY_N,*
V 1500,1500,CONT_DIF_N,*
V 300,500,CONT_DIF_N,*
V 2700,500,CONT_DIF_N,*
V 1500,1000,CONT_DIF_N,*
V 1500,300,CONT_BODY_P,*
V 2000,2000,CONT_POLY,*
V 1000,2000,CONT_VIA2,*
V 1000,2000,CONT_VIA,*
V 2000,2000,CONT_VIA2,*
V 2000,2000,CONT_VIA,*
V 1000,2500,CONT_POLY,*
V 2700,4500,CONT_DIF_P,*
V 1500,3500,CONT_DIF_P,*
V 1500,3000,CONT_DIF_P,*
V 300,4500,CONT_DIF_P,*
V 1000,2000,CONT_POLY,*
V 2500,2000,CONT_POLY,*
V 500,2000,CONT_POLY,*
V 900,300,CONT_BODY_P,*
S 500,1000,500,4000,200,i1,UP,CALU1
S 2500,1000,2500,4000,200,i0,UP,CALU1
S 0,4700,3000,4700,600,vdd,RIGHT,CALU1
S 0,300,3000,300,600,vss,RIGHT,CALU1
S 0,4000,3000,4000,2600,*,RIGHT,NWELL
S 300,2800,300,4500,300,*,UP,PDIF
S 2700,2800,2700,4500,300,*,UP,PDIF
S 1000,2500,1000,4000,100,*,DOWN,ALU1
S 1000,4000,2000,4000,100,*,LEFT,ALU1
S 2000,2000,2000,4000,100,*,UP,ALU1
S 900,2100,1500,2100,100,*,RIGHT,POLY
S 1500,2100,1500,2600,100,*,UP,POLY
S 1500,2600,1900,2600,100,*,RIGHT,POLY
S 600,600,600,1900,100,*,DOWN,NTRANS
S 2400,600,2400,1900,100,*,DOWN,NTRANS
S 1100,600,1100,1900,100,*,DOWN,NTRANS
S 1500,800,1500,1700,500,*,UP,NDIF
S 1900,600,1900,1900,100,*,DOWN,NTRANS
S 2700,400,2700,1700,300,*,DOWN,NDIF
S 300,400,300,1700,300,*,DOWN,NDIF
S 2400,1900,2400,2600,100,*,UP,POLY
S 600,1900,600,2600,100,*,UP,POLY
S 1000,2000,1000,2000,200,sel1,LEFT,CALU3
S 2000,2000,2000,2000,200,sel0,LEFT,CALU3
S 600,2600,600,4400,100,*,UP,PTRANS
S 1100,2600,1100,4400,100,*,UP,PTRANS
S 1900,2600,1900,4400,100,*,UP,PTRANS
S 1500,2800,1500,4200,500,*,UP,PDIF
S 2400,2600,2400,4400,100,*,UP,PTRANS
V 2100,300,CONT_BODY_P,*
V 900,300,CONT_BODY_P,*
V 500,2000,CONT_POLY,*
V 2500,2000,CONT_POLY,*
V 1000,2000,CONT_POLY,*
V 300,4500,CONT_DIF_P,*
V 1500,3000,CONT_DIF_P,*
V 1500,3500,CONT_DIF_P,*
V 2700,4500,CONT_DIF_P,*
V 1000,2500,CONT_POLY,*
V 2000,2000,CONT_VIA,*
V 2000,2000,CONT_VIA2,*
V 1000,2000,CONT_VIA,*
V 1000,2000,CONT_VIA2,*
V 2000,2000,CONT_POLY,*
V 1500,300,CONT_BODY_P,*
V 1500,1000,CONT_DIF_N,*
V 2700,500,CONT_DIF_N,*
V 300,500,CONT_DIF_N,*
V 1500,1500,CONT_DIF_N,*
V 900,4700,CONT_BODY_N,*
V 2100,4700,CONT_BODY_N,*
V 1500,4700,CONT_BODY_N,*
EOF