renaming lynx to cougar ....
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man_MANS = lynx.1
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man_MANS = cougar.1
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EXTRA_DIST = $(man_MANS)
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EXTRA_DIST = $(man_MANS)
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.\" $Id: lynx.1,v 1.1 2002/03/29 17:43:39 ludo Exp $
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.\" $Id: cougar.1,v 1.1 2002/05/21 06:52:00 xtof Exp $
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.\" @(#)lynx 1.09 94/10/10 UPMC/ASIM/LIP6/CAO-VLSI " Ludovic Jacomme, Frederic Petrot
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.\" @(#)lynx 1.09 94/10/10 UPMC/ASIM/LIP6/CAO-VLSI " Ludovic Jacomme, Frederic Petrot
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.TH LYNX 1 "October 1, 1997" "ASIM/LIP6" "ALLIANCE USER COMMANDS"
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.TH COUGAR 1 "October 1, 1997" "ASIM/LIP6" "ALLIANCE USER COMMANDS"
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.SH NAME
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.SH NAME
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lynx \- Hierarchical netlist extractor
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cougar \- Hierarchical netlist extractor
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.SH SYNOPSIS
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.SH SYNOPSIS
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.B lynx
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.B cougar
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[
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[
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.I \-v
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.I \-v
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]
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]
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@ -30,7 +30,8 @@ lynx \- Hierarchical netlist extractor
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.br
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.br
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.so man1/alc_origin.1
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.so man1/alc_origin.1
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.SH DESCRIPTION
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.SH DESCRIPTION
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\fBLynx\fP is a hierarchical layout extractor.
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\fBLynx\fP changed its name to \fBCougar\fP during May 2002 in order to avoid name conflict with the famous text-mode Web browser.
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\fBCougar\fP is a hierarchical layout extractor.
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It builds a netlist of interconnections from a symbolic layout view.
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It builds a netlist of interconnections from a symbolic layout view.
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The \fIinput\fP argument is the name of the symbolic layout cell to
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The \fIinput\fP argument is the name of the symbolic layout cell to
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be extracted, using as input format the one selected by the
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be extracted, using as input format the one selected by the
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@ -40,7 +41,7 @@ If no \fIoutput\fP is given, then \fIinput\fP will also be the generated
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netlist name.
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netlist name.
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The output format is specified by the \fBMBK_OUT_LO\fP(1) environment variable.
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The output format is specified by the \fBMBK_OUT_LO\fP(1) environment variable.
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.br
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.br
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As most of the Alliance cad tools, \fBlynx\fP uses \fBmbk\fP(1) environment
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As most of the Alliance cad tools, \fBcougar\fP uses \fBmbk\fP(1) environment
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variables.
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variables.
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.BR MBK_CATA_LIB (1),
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.BR MBK_CATA_LIB (1),
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.BR MBK_WORK_LIB (1),
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.BR MBK_WORK_LIB (1),
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@ -48,7 +49,7 @@ variables.
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.BR MBK_OUT_LO (1),
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.BR MBK_OUT_LO (1),
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.BR RDS_TECHNO_NAME (1).
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.BR RDS_TECHNO_NAME (1).
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.PP
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.PP
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\fBLynx\fP computes capacitances attached to the signals if
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\fBCougar\fP computes capacitances attached to the signals if
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the -ac option is set. At the moment,
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the -ac option is set. At the moment,
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the value of these capacitances is computed for a typical one micron
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the value of these capacitances is computed for a typical one micron
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technology, and cannot be changed by the user through a technology file.
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technology, and cannot be changed by the user through a technology file.
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@ -65,7 +66,7 @@ ALU1
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ALU2
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ALU2
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25
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25
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.SH OPTIONS
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.SH OPTIONS
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\fBLynx\fP checks the two basic \fBALLIANCE\fP rules regarding connector names:
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\fBCougar\fP checks the two basic \fBALLIANCE\fP rules regarding connector names:
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.br
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.br
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.RS
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.RS
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If two physical connectors are connected to the same net, they must have
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If two physical connectors are connected to the same net, they must have
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@ -82,7 +83,7 @@ and ground connectors )
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When no options are specified, the current hierarchical level is extracted.
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When no options are specified, the current hierarchical level is extracted.
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The resulting netlist is the list of interconnections of the current
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The resulting netlist is the list of interconnections of the current
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layout hierarchy level.
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layout hierarchy level.
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Three options are available to change \fBlynx\fP behaviour :
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Three options are available to change \fBcougar\fP behaviour :
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.TP
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.TP
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\-t
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\-t
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Notifies a transistor level extraction, the symbolic layout cell is flattened to
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Notifies a transistor level extraction, the symbolic layout cell is flattened to
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@ -102,7 +103,7 @@ along with some statistics.
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.TP
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.TP
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\-c
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\-c
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Generates a \fBcore\fP file representing the conflictuel net, when
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Generates a \fBcore\fP file representing the conflictuel net, when
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\fBlynx\fP detects two external connectors with different names on
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\fBcougar\fP detects two external connectors with different names on
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the same signal, or when it finds two external connectors having
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the same signal, or when it finds two external connectors having
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the same name but not internally connected to the same net, or when
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the same name but not internally connected to the same net, or when
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it cannot correctly extract an L shaped transistor.
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it cannot correctly extract an L shaped transistor.
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@ -117,7 +118,7 @@ resistance foreach layer can be changed in the RDS file.
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.ie t \{\
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.ie t \{\
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.ft CR \}
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.ft CR \}
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.el \fB
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.el \fB
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prompt> lynx -v amd2901
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prompt> cougar -v amd2901
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.ft R
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.ft R
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.RS
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.RS
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Gives a logical netlist of the chip amd2901, for one hierarchical
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Gives a logical netlist of the chip amd2901, for one hierarchical
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@ -135,7 +136,7 @@ a2_y
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a2p_y
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a2p_y
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.
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.
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.
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.
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prompt> lynx -f amd2901
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prompt> cougar -f amd2901
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.fi
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.fi
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.ft R
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.ft R
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.RS
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.RS
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@ -146,7 +147,7 @@ on the cells specified in the catalog ( the standard cell library in our case ).
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.ft CR \}
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.ft CR \}
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.el \fB
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.el \fB
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.nf
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.nf
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prompt> lynx -t amd2901
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prompt> cougar -t amd2901
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.fi
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.fi
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.ft R
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.ft R
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.RS
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.RS
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