riscv
/
alliance
mirror of https://gitlab.lip6.fr/vlsi-eda/alliance.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Idem

This commit is contained in:
The Syf Tool 2000-03-02 17:15:49 +00:00
parent 61bdf990d4
commit ceb74f1000
1 changed files with 2 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
alliance/share/man/man5/vasy.5
View File

@ -1,4 +1,4 @@
.\" $Id: vasy.5,v 1.3 2000/02/29 14:33:33 syf Exp $ .\" $Id: vasy.5,v 1.4 2000/03/02 17:15:49 syf Exp $
.\" @(#)VASY.5 1.0 Jan 28 1992 UPMC ; Ludovic Jacomme .\" @(#)VASY.5 1.0 Jan 28 1992 UPMC ; Ludovic Jacomme
.TH VASY 5 "December 11, 1999" "ASIM/LIP6" "VHDL subset of VASY." .TH VASY 5 "December 11, 1999" "ASIM/LIP6" "VHDL subset of VASY."
@ -14,8 +14,7 @@ This document describes the VHDL subset accepted by VASY for RTL descriptions.
.PP .PP
\fBCONCURRENT STATEMENTS\fP \fBCONCURRENT STATEMENTS\fP
.br .br
In an RTL architecture most of the concurrent statements are supported, In an RTL architecture most of the concurrent statements are supported.
but generate constructs and port map clauses are not allowed.
.PP .PP
Allowed concurrent statements are: Allowed concurrent statements are: