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correction du comportement des cellules noa2ao222 et noa3ao322

This commit is contained in:
Franck Wajsburt 2000-12-21 11:39:24 +00:00
parent f165431682
commit c7ce4e39e1
10 changed files with 131 additions and 131 deletions
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alliance/share/cells/sxlib/sxlib.db
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10
alliance/share/cells/sxlib/sxlib.lib
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@ -19,7 +19,7 @@
library (sxlib) {
date : "Sat Oct 30 22:31:32 MET DST 1999";
date : "Thu Dec 21 11:24:55 MET 2000";
revision : 1.2;
/* --------------------------------------------- */
@ -1674,7 +1674,7 @@ library (sxlib) {
pin(nq) {
direction : output;
max_fanout : 0.055;
function : "((i0'*i1')+((i2'+i3')*i4'))";
function : "((i0'+i1')*((i2'*i3')+i4'))";
timing() {
timing_sense : negative_unate;
intrinsic_rise : 0.348;
@ -1748,7 +1748,7 @@ library (sxlib) {
pin(nq) {
direction : output;
max_fanout : 0.327;
function : "((i0'*i1')+((i2'+i3')*i4'))";
function : "((i0'+i1')*((i2'*i3')+i4'))";
timing() {
timing_sense : negative_unate;
intrinsic_rise : 0.684;
@ -2006,7 +2006,7 @@ library (sxlib) {
pin(nq) {
direction : output;
max_fanout : 0.043;
function : "((i0'*i1'*i2')+(((i3'+i4')+i5')*i6'))";
function : "((i0'+i1'+i2')*(((i3'*i4')*i5')+i6'))";
timing() {
timing_sense : negative_unate;
intrinsic_rise : 0.396;
@ -2106,7 +2106,7 @@ library (sxlib) {
pin(nq) {
direction : output;
max_fanout : 0.327;
function : "((i0'*i1'*i2')+(((i3'+i4')+i5')*i6'))";
function : "((i0'+i1'+i2')*(((i3'*i4')*i5')+i6'))";
timing() {
timing_sense : negative_unate;
intrinsic_rise : 0.819;

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alliance/share/cells/sxlib/sxlib.sdb
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16
alliance/share/cells/sxlib/sxlib_FTGS.vhd
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@ -5,10 +5,10 @@
-- FILENAME : sxlib_FTGS.vhd
-- FILE CONTENTS: Entity, Structural Architecture(FTGS),
-- and Configuration
-- DATE CREATED : Mon May 29 15:16:04 2000
-- DATE CREATED : Thu Dec 21 11:59:30 2000
--
-- LIBRARY : sxlib
-- DATE ENTERED : Sat Oct 30 22:31:32 MET DST 1999
-- DATE ENTERED : Thu Dec 21 11:24:55 MET 2000
-- REVISION : 1.200000
-- TECHNOLOGY : cmos
-- TIME SCALE : 1 ns
@ -6825,7 +6825,7 @@ begin
U6 : TLU
generic map(
N => 5,
TruthTable => "11111111101010001010100010101000",
TruthTable => "11101010111010101110101000000000",
TT_size => nil_integer_vector,
Node_index => nil_integer_vector,
pin_names => "i0 i1 i2 i3 i4 nq",
@ -6997,7 +6997,7 @@ begin
U6 : TLU
generic map(
N => 5,
TruthTable => "11111111101010001010100010101000",
TruthTable => "11101010111010101110101000000000",
TT_size => nil_integer_vector,
Node_index => nil_integer_vector,
pin_names => "i0 i1 i2 i3 i4 nq",
@ -7206,8 +7206,8 @@ begin
U8 : TLU
generic map(
N => 7,
TruthTable => "1010101010101000" &
"1101010101010101",
TruthTable => "0001010101010101" &
"1010101010101000",
TT_size => (4, 4),
Node_Index => (0, 1, 2, 3,
4, 5, 6, -1),
@ -7421,8 +7421,8 @@ begin
U8 : TLU
generic map(
N => 7,
TruthTable => "1010101010101000" &
"1101010101010101",
TruthTable => "0001010101010101" &
"1010101010101000",
TT_size => (4, 4),
Node_Index => (0, 1, 2, 3,
4, 5, 6, -1),

108
alliance/share/cells/sxlib/sxlib_FTSM.vhd
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@ -5,10 +5,10 @@
-- FILENAME : sxlib_FTSM.vhd
-- FILE CONTENTS: Entity, Structural Architecture(FTSM),
-- and Configuration
-- DATE CREATED : Mon May 29 15:16:04 2000
-- DATE CREATED : Thu Dec 21 11:59:30 2000
--
-- LIBRARY : sxlib
-- DATE ENTERED : Sat Oct 30 22:31:32 MET DST 1999
-- DATE ENTERED : Thu Dec 21 11:24:55 MET 2000
-- REVISION : 1.200000
-- TECHNOLOGY : cmos
-- TIME SCALE : 1 ns
@ -6209,17 +6209,6 @@ architecture FTSM of noa2ao222_x1 is
signal prop_nq : STD_LOGIC_VECTOR (0 to 4) := (others => 'U');
signal n1, n2, n3 : STD_LOGIC;
component NAND2MAC
generic(
tpdY_R : Time := 0 ns;
tpdY_F : Time := 0 ns;
strn : STRENGTH := strn_X01);
port(
I0 : in STD_LOGIC;
I1 : in STD_LOGIC;
Y : out STD_LOGIC);
end component;
component AND2MAC
generic(
tpdY_R : Time := 0 ns;
@ -6242,6 +6231,17 @@ architecture FTSM of noa2ao222_x1 is
Y : out STD_LOGIC);
end component;
component NAND2MAC
generic(
tpdY_R : Time := 0 ns;
tpdY_F : Time := 0 ns;
strn : STRENGTH := strn_X01);
port(
I0 : in STD_LOGIC;
I1 : in STD_LOGIC;
Y : out STD_LOGIC);
end component;
begin
-- Extrinsic delay buffers
@ -6287,16 +6287,16 @@ begin
port map( Input => connect(4), Output => prop_nq(4));
-- Netlist
U11 : NAND2MAC
U11 : AND2MAC
port map( I0 => n1, I1 => n2, Y => nq);
U12 : AND2MAC
U12 : OR2MAC
port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n3);
U13 : OR2MAC
U13 : NAND2MAC
port map( I0 => prop_nq(4), I1 => n3, Y => n2);
U14 : OR2MAC
U14 : NAND2MAC
port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1);
@ -6388,17 +6388,6 @@ architecture FTSM of noa2ao222_x4 is
signal prop_nq : STD_LOGIC_VECTOR (0 to 4) := (others => 'U');
signal n1, n2, n3 : STD_LOGIC;
component NAND2MAC
generic(
tpdY_R : Time := 0 ns;
tpdY_F : Time := 0 ns;
strn : STRENGTH := strn_X01);
port(
I0 : in STD_LOGIC;
I1 : in STD_LOGIC;
Y : out STD_LOGIC);
end component;
component AND2MAC
generic(
tpdY_R : Time := 0 ns;
@ -6421,6 +6410,17 @@ architecture FTSM of noa2ao222_x4 is
Y : out STD_LOGIC);
end component;
component NAND2MAC
generic(
tpdY_R : Time := 0 ns;
tpdY_F : Time := 0 ns;
strn : STRENGTH := strn_X01);
port(
I0 : in STD_LOGIC;
I1 : in STD_LOGIC;
Y : out STD_LOGIC);
end component;
begin
-- Extrinsic delay buffers
@ -6466,16 +6466,16 @@ begin
port map( Input => connect(4), Output => prop_nq(4));
-- Netlist
U11 : NAND2MAC
U11 : AND2MAC
port map( I0 => n1, I1 => n2, Y => nq);
U12 : AND2MAC
U12 : OR2MAC
port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n3);
U13 : OR2MAC
U13 : NAND2MAC
port map( I0 => prop_nq(4), I1 => n3, Y => n2);
U14 : OR2MAC
U14 : NAND2MAC
port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1);
@ -6585,7 +6585,7 @@ architecture FTSM of noa3ao322_x1 is
signal prop_nq : STD_LOGIC_VECTOR (0 to 6) := (others => 'U');
signal n1, n2, n3 : STD_LOGIC;
component NAND2MAC
component AND2MAC
generic(
tpdY_R : Time := 0 ns;
tpdY_F : Time := 0 ns;
@ -6596,7 +6596,7 @@ architecture FTSM of noa3ao322_x1 is
Y : out STD_LOGIC);
end component;
component AND3MAC
component NAND3MAC
generic(
tpdY_R : Time := 0 ns;
tpdY_F : Time := 0 ns;
@ -6620,7 +6620,7 @@ architecture FTSM of noa3ao322_x1 is
Y : out STD_LOGIC);
end component;
component OR2MAC
component NAND2MAC
generic(
tpdY_R : Time := 0 ns;
tpdY_F : Time := 0 ns;
@ -6692,18 +6692,18 @@ begin
port map( Input => connect(6), Output => prop_nq(6));
-- Netlist
U15 : NAND2MAC
U15 : AND2MAC
port map( I0 => n1, I1 => n2, Y => nq);
U16 : AND3MAC
port map( I0 => prop_nq(4), I1 => prop_nq(5), I2 => prop_nq(3), Y =>
n3);
U17 : OR3MAC
port map( I0 => prop_nq(0), I1 => prop_nq(1), I2 => prop_nq(2), Y =>
U16 : NAND3MAC
port map( I0 => prop_nq(1), I1 => prop_nq(2), I2 => prop_nq(0), Y =>
n2);
U18 : OR2MAC
U17 : OR3MAC
port map( I0 => prop_nq(3), I1 => prop_nq(4), I2 => prop_nq(5), Y =>
n3);
U18 : NAND2MAC
port map( I0 => prop_nq(6), I1 => n3, Y => n1);
@ -6813,7 +6813,7 @@ architecture FTSM of noa3ao322_x4 is
signal prop_nq : STD_LOGIC_VECTOR (0 to 6) := (others => 'U');
signal n1, n2, n3 : STD_LOGIC;
component NAND2MAC
component AND2MAC
generic(
tpdY_R : Time := 0 ns;
tpdY_F : Time := 0 ns;
@ -6824,7 +6824,7 @@ architecture FTSM of noa3ao322_x4 is
Y : out STD_LOGIC);
end component;
component AND3MAC
component NAND3MAC
generic(
tpdY_R : Time := 0 ns;
tpdY_F : Time := 0 ns;
@ -6848,7 +6848,7 @@ architecture FTSM of noa3ao322_x4 is
Y : out STD_LOGIC);
end component;
component OR2MAC
component NAND2MAC
generic(
tpdY_R : Time := 0 ns;
tpdY_F : Time := 0 ns;
@ -6920,18 +6920,18 @@ begin
port map( Input => connect(6), Output => prop_nq(6));
-- Netlist
U15 : NAND2MAC
U15 : AND2MAC
port map( I0 => n1, I1 => n2, Y => nq);
U16 : AND3MAC
port map( I0 => prop_nq(4), I1 => prop_nq(5), I2 => prop_nq(3), Y =>
n3);
U17 : OR3MAC
port map( I0 => prop_nq(0), I1 => prop_nq(1), I2 => prop_nq(2), Y =>
U16 : NAND3MAC
port map( I0 => prop_nq(1), I1 => prop_nq(2), I2 => prop_nq(0), Y =>
n2);
U18 : OR2MAC
U17 : OR3MAC
port map( I0 => prop_nq(3), I1 => prop_nq(4), I2 => prop_nq(5), Y =>
n3);
U18 : NAND2MAC
port map( I0 => prop_nq(6), I1 => n3, Y => n1);

96
alliance/share/cells/sxlib/sxlib_UDSM.vhd
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@ -5,10 +5,10 @@
-- FILENAME : sxlib_UDSM.vhd
-- FILE CONTENTS: Entity, Structural Architecture(UDSM),
-- and Configuration
-- DATE CREATED : Mon May 29 15:16:04 2000
-- DATE CREATED : Thu Dec 21 11:59:30 2000
--
-- LIBRARY : sxlib
-- DATE ENTERED : Sat Oct 30 22:31:32 MET DST 1999
-- DATE ENTERED : Thu Dec 21 11:24:55 MET 2000
-- REVISION : 1.200000
-- TECHNOLOGY : cmos
-- TIME SCALE : 1 ns
@ -3946,17 +3946,6 @@ architecture UDSM of noa2ao222_x1 is
signal n1, n2, n3 : STD_LOGIC;
component NAND2MAC
generic(
tpdY_R : Time := 0 ns;
tpdY_F : Time := 0 ns;
strn : STRENGTH := strn_X01);
port(
I0 : in STD_LOGIC;
I1 : in STD_LOGIC;
Y : out STD_LOGIC);
end component;
component AND2MAC
generic(
tpdY_R : Time := 0 ns;
@ -3979,20 +3968,31 @@ architecture UDSM of noa2ao222_x1 is
Y : out STD_LOGIC);
end component;
component NAND2MAC
generic(
tpdY_R : Time := 0 ns;
tpdY_F : Time := 0 ns;
strn : STRENGTH := strn_X01);
port(
I0 : in STD_LOGIC;
I1 : in STD_LOGIC;
Y : out STD_LOGIC);
end component;
begin
-- Netlist
U1 : NAND2MAC
U1 : AND2MAC
generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
port map( I0 => n1, I1 => n2, Y => nq);
U2 : AND2MAC
U2 : OR2MAC
port map( I0 => i2, I1 => i3, Y => n3);
U3 : OR2MAC
U3 : NAND2MAC
port map( I0 => i4, I1 => n3, Y => n2);
U4 : OR2MAC
U4 : NAND2MAC
port map( I0 => i0, I1 => i1, Y => n1);
@ -4059,17 +4059,6 @@ architecture UDSM of noa2ao222_x4 is
signal n1, n2, n3 : STD_LOGIC;
component NAND2MAC
generic(
tpdY_R : Time := 0 ns;
tpdY_F : Time := 0 ns;
strn : STRENGTH := strn_X01);
port(
I0 : in STD_LOGIC;
I1 : in STD_LOGIC;
Y : out STD_LOGIC);
end component;
component AND2MAC
generic(
tpdY_R : Time := 0 ns;
@ -4092,20 +4081,31 @@ architecture UDSM of noa2ao222_x4 is
Y : out STD_LOGIC);
end component;
component NAND2MAC
generic(
tpdY_R : Time := 0 ns;
tpdY_F : Time := 0 ns;
strn : STRENGTH := strn_X01);
port(
I0 : in STD_LOGIC;
I1 : in STD_LOGIC;
Y : out STD_LOGIC);
end component;
begin
-- Netlist
U1 : NAND2MAC
U1 : AND2MAC
generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
port map( I0 => n1, I1 => n2, Y => nq);
U2 : AND2MAC
U2 : OR2MAC
port map( I0 => i2, I1 => i3, Y => n3);
U3 : OR2MAC
U3 : NAND2MAC
port map( I0 => i4, I1 => n3, Y => n2);
U4 : OR2MAC
U4 : NAND2MAC
port map( I0 => i0, I1 => i1, Y => n1);
@ -4182,7 +4182,7 @@ architecture UDSM of noa3ao322_x1 is
signal n1, n2, n3 : STD_LOGIC;
component NAND2MAC
component AND2MAC
generic(
tpdY_R : Time := 0 ns;
tpdY_F : Time := 0 ns;
@ -4193,7 +4193,7 @@ architecture UDSM of noa3ao322_x1 is
Y : out STD_LOGIC);
end component;
component AND3MAC
component NAND3MAC
generic(
tpdY_R : Time := 0 ns;
tpdY_F : Time := 0 ns;
@ -4217,7 +4217,7 @@ architecture UDSM of noa3ao322_x1 is
Y : out STD_LOGIC);
end component;
component OR2MAC
component NAND2MAC
generic(
tpdY_R : Time := 0 ns;
tpdY_F : Time := 0 ns;
@ -4231,17 +4231,17 @@ architecture UDSM of noa3ao322_x1 is
begin
-- Netlist
U1 : NAND2MAC
U1 : AND2MAC
generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
port map( I0 => n1, I1 => n2, Y => nq);
U2 : AND3MAC
port map( I0 => i4, I1 => i5, I2 => i3, Y => n3);
U2 : NAND3MAC
port map( I0 => i1, I1 => i2, I2 => i0, Y => n2);
U3 : OR3MAC
port map( I0 => i0, I1 => i1, I2 => i2, Y => n2);
port map( I0 => i3, I1 => i4, I2 => i5, Y => n3);
U4 : OR2MAC
U4 : NAND2MAC
port map( I0 => i6, I1 => n3, Y => n1);
@ -4318,7 +4318,7 @@ architecture UDSM of noa3ao322_x4 is
signal n1, n2, n3 : STD_LOGIC;
component NAND2MAC
component AND2MAC
generic(
tpdY_R : Time := 0 ns;
tpdY_F : Time := 0 ns;
@ -4329,7 +4329,7 @@ architecture UDSM of noa3ao322_x4 is
Y : out STD_LOGIC);
end component;
component AND3MAC
component NAND3MAC
generic(
tpdY_R : Time := 0 ns;
tpdY_F : Time := 0 ns;
@ -4353,7 +4353,7 @@ architecture UDSM of noa3ao322_x4 is
Y : out STD_LOGIC);
end component;
component OR2MAC
component NAND2MAC
generic(
tpdY_R : Time := 0 ns;
tpdY_F : Time := 0 ns;
@ -4367,17 +4367,17 @@ architecture UDSM of noa3ao322_x4 is
begin
-- Netlist
U1 : NAND2MAC
U1 : AND2MAC
generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
port map( I0 => n1, I1 => n2, Y => nq);
U2 : AND3MAC
port map( I0 => i4, I1 => i5, I2 => i3, Y => n3);
U2 : NAND3MAC
port map( I0 => i1, I1 => i2, I2 => i0, Y => n2);
U3 : OR3MAC
port map( I0 => i0, I1 => i1, I2 => i2, Y => n2);
port map( I0 => i3, I1 => i4, I2 => i5, Y => n3);
U4 : OR2MAC
U4 : NAND2MAC
port map( I0 => i6, I1 => n3, Y => n1);

20
alliance/share/cells/sxlib/sxlib_VITAL.vhd
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@ -5,10 +5,10 @@
-- FILENAME : sxlib_VITAL.vhd
-- FILE CONTENTS: Entity, Structural Architecture(VITAL),
-- and Configuration
-- DATE CREATED : Mon May 29 15:16:04 2000
-- DATE CREATED : Thu Dec 21 11:59:30 2000
--
-- LIBRARY : sxlib
-- DATE ENTERED : Sat Oct 30 22:31:32 MET DST 1999
-- DATE ENTERED : Thu Dec 21 11:24:55 MET 2000
-- REVISION : 1.200000
-- TECHNOLOGY : cmos
-- TIME SCALE : 1 ns
@ -5029,8 +5029,8 @@ begin
-- Functionality Section
-------------------------
nq_zd :=
(((NOT i4_ipd)) AND (((NOT i3_ipd)) OR ((NOT i2_ipd)))) OR (((NOT
i1_ipd)) AND ((NOT i0_ipd)));
(((NOT i4_ipd)) OR (((NOT i3_ipd)) AND ((NOT i2_ipd)))) AND (((NOT
i1_ipd)) OR ((NOT i0_ipd)));
----------------------
-- Path Delay Section
@ -5141,8 +5141,8 @@ begin
-- Functionality Section
-------------------------
nq_zd :=
(((NOT i4_ipd)) AND (((NOT i3_ipd)) OR ((NOT i2_ipd)))) OR (((NOT
i1_ipd)) AND ((NOT i0_ipd)));
(((NOT i4_ipd)) OR (((NOT i3_ipd)) AND ((NOT i2_ipd)))) AND (((NOT
i1_ipd)) OR ((NOT i0_ipd)));
----------------------
-- Path Delay Section
@ -5263,8 +5263,8 @@ begin
-- Functionality Section
-------------------------
nq_zd :=
(((NOT i6_ipd)) AND (((NOT i4_ipd)) OR ((NOT i3_ipd)) OR ((NOT
i5_ipd)))) OR (((NOT i1_ipd)) AND ((NOT i0_ipd)) AND ((NOT i2_ipd)));
(((NOT i6_ipd)) OR (((NOT i4_ipd)) AND ((NOT i3_ipd)) AND ((NOT
i5_ipd)))) AND (((NOT i1_ipd)) OR ((NOT i0_ipd)) OR ((NOT i2_ipd)));
----------------------
-- Path Delay Section
@ -5387,8 +5387,8 @@ begin
-- Functionality Section
-------------------------
nq_zd :=
(((NOT i6_ipd)) AND (((NOT i4_ipd)) OR ((NOT i3_ipd)) OR ((NOT
i5_ipd)))) OR (((NOT i1_ipd)) AND ((NOT i0_ipd)) AND ((NOT i2_ipd)));
(((NOT i6_ipd)) OR (((NOT i4_ipd)) AND ((NOT i3_ipd)) AND ((NOT
i5_ipd)))) AND (((NOT i1_ipd)) OR ((NOT i0_ipd)) OR ((NOT i2_ipd)));
----------------------
-- Path Delay Section

4
alliance/share/cells/sxlib/sxlib_Vcomponents.vhd
View File

@ -4,10 +4,10 @@
-- Created by the Synopsys Library Compiler 1999.10
-- FILENAME : sxlib_Vcomponents.vhd
-- FILE CONTENTS: VITAL Component Package
-- DATE CREATED : Mon May 29 15:16:04 2000
-- DATE CREATED : Thu Dec 21 11:59:30 2000
--
-- LIBRARY : sxlib
-- DATE ENTERED : Sat Oct 30 22:31:32 MET DST 1999
-- DATE ENTERED : Thu Dec 21 11:24:55 MET 2000
-- REVISION : 1.200000
-- TECHNOLOGY : cmos
-- TIME SCALE : 1 ns

4
alliance/share/cells/sxlib/sxlib_Vtables.vhd
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@ -4,10 +4,10 @@
-- Created by the Synopsys Library Compiler 1999.10
-- FILENAME : sxlib_Vtables.vhd
-- FILE CONTENTS: VITAL Table Package
-- DATE CREATED : Mon May 29 15:16:04 2000
-- DATE CREATED : Thu Dec 21 11:59:30 2000
--
-- LIBRARY : sxlib
-- DATE ENTERED : Sat Oct 30 22:31:32 MET DST 1999
-- DATE ENTERED : Thu Dec 21 11:24:55 MET 2000
-- REVISION : 1.200000
-- TECHNOLOGY : cmos
-- TIME SCALE : 1 ns

4
alliance/share/cells/sxlib/sxlib_components.vhd
View File

@ -4,10 +4,10 @@
-- Created by the Synopsys Library Compiler 1999.10
-- FILENAME : sxlib_components.vhd
-- FILE CONTENTS: Component Package
-- DATE CREATED : Mon May 29 15:16:04 2000
-- DATE CREATED : Thu Dec 21 11:59:30 2000
--
-- LIBRARY : sxlib
-- DATE ENTERED : Sat Oct 30 22:31:32 MET DST 1999
-- DATE ENTERED : Thu Dec 21 11:24:55 MET 2000
-- REVISION : 1.200000
-- TECHNOLOGY : cmos
-- TIME SCALE : 1 ns