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.\"
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.\" This file is part of the Alliance CAD System
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.\" Copyright (C) Laboratoire LIP6 - Département ASIM
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.\" Universite Pierre et Marie Curie
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.\"
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.\" Home page : http://www-asim.lip6.fr/alliance/
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.\" E-mail support : mailto:alliance-support@asim.lip6.fr
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.\"
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.\" This progam is free software; you can redistribute it and/or modify it
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.\" under the terms of the GNU General Public License as published by the
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.\" Free Software Foundation; either version 2 of the License, or (at your
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.\" option) any later version.
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.\"
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.\" Alliance VLSI CAD System is distributed in the hope that it will be
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.\" useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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.\" MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
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.\" Public License for more details.
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.\"
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.\" You should have received a copy of the GNU General Public License along
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.\" with the GNU C Library; see the file COPYING. If not, write to the Free
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.\" Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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.\"
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.\"
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.\" Tool : Man pages
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.\" Date : 1991,92,2000
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.\" Author : Luc Burgun, Pascale Allegre, Nathalie Dictus
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.\" Modified by Czo <Olivier.Sirol@lip6.fr> 1996,97
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.\" Modified by francois Donnet 2000
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.\"
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.\"
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.\"
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.\"
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.\"
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.pl -.4
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.TH BOOG 1 "Jun 29 2000" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
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.SH NAME
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.TP
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BooG \- Binding and Optimizing On Gates.
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.so man1/alc_origin.1
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.SH SYNOPSIS
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.TP
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\f4boog\fP \fIinput_file\fP \fIoutput_file\fP [\fIlax_file\fP]
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\f4boog\fP \-h
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\f4boog\fP [\-v] [\-m \fImode\fP] \fIinput_file\fP [\-o \fIoutput_file\fP] [\-l \fIlax_file\fP]
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\f4boog\fP [\-m \fImode\fP] \fIinput_file\fP \-d \fIdebug_file\fP\n\
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.br
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.SH DESCRIPTION
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.br
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Boog is a mapper of a behavioural description onto a standard cell library.
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.br
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\fB Input description\fP
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.br
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.br
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The logic level behavioural description (.vbe file) uses the same VHDL subset as the logic simulator \fBasimut\fP, the FSM synthesizer \fBsyf\fP, the functional abstractor \fByagle\fP and the formal prover \fBproof\fP (for further information about the subset of VHDL, see the "vbe" manual).
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.br
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A special feature has been introduced in the VHDL subset in order to allow the don't care description for external outputs and internal registers : A bit signal can take the 'd' value.
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This value is interpreted as a '0' by the logic simulator \fBasimut\fP.
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Don't Cares are automatically generated by \fBsyf\fP in the resulting '.vbe' file.
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.br
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For the register signal, only one signal can appear in a guarded expression since the STABLE attribute is used. This attribute is only supported by technology mapping onto a standard cell library as \fBsxlib\fP. Indeed you can associate a write enable signal in condition register. To resume only 2 descriptions are accepted as followed:
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\fIlabel: BLOCK (NOT ck 'STABLE and ck='1')
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.nf
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# Example
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BEGIN
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reg <= expr;
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END BLOCK;\fP
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or
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\fIlabel: BLOCK (NOT ck 'STABLE and ck='1' and wen='1')
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BEGIN
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reg <= expr;
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END BLOCK;\fP
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.fi
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.ti 7
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\fBboog\fP is the second step of the logic synthesis : it builds a gate network using
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a predefined standard cell library as SXLIB.
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.br
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.br
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\fB Mapping with a standard cell library\fP
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.br
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.br
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Every cell appearing in the directory defined by the environment variable MBK_TARGET_LIB may be used by \fBboog\fP since they are described as a '.vbe' file. There are some restrictions about the type of the cell used. Every cell has to have only one output.
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The cell must be characterized. The timing and area informations required by \fBboog\fP are specified in the "generic" clause of the ".vbe" file.
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.br
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.br
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\fB Parameter file '.lax'\fP
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.br
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The lax file is common with other logic synthesis tools and is used
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for driving the synthesis process.
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See \fBlax\fP(5) manual for more detail.
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.br
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\fBlax\fP uses a lot of parameters to guide every step of the synthesis process.
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Some parameters are globally used (for example, \fIoptimization level\fP whereas others are specifically used (\fBload capacitance\fP for the netlist optimization only).
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Here is the default lax file (see the user's manual for further information about the syntax of the '.lax' file):
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.br
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.br
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Optimization mode = 3 (25% area - 75% delay)
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.br
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Delayed input = 0
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.br
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Early output = 0
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.br
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Auxiliary signal saved = 0
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.br
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.SH OPTION
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.TP 10
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\f4\-h\fP
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Help mode. Displays possible uses of \fBboog\fP.
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.TP 10
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\f4\-v\fP
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Verbose mode. Displays timing and area informations.
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.TP 10
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\f4\-m mode\fP
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Optimization mode. Can be defined in lax file, it's only a shortcut to define it on command line. This mode number has an array defined between \fI0\fP and \fI4\fP. It indicates the way of optimization the user wants. If \fI0\fP is chosen, the circuit area will be improved. On the other hand, \fI4\fP will improve circuit delays. \fI2\fP is a medium value for optimization.
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.TP 10
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\f4\-o output_file\fP
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Just another way to show explicitely the \fBVST\fP output file name.
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.TP 10
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\f4\-l lax_file\fP
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Just another way to show explicitely the \fBLAX\fP parameter file name.
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.TP 10
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\f4\-d debug_file\fP
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Generates a \fBVBE\f debug file. It comes from internal result algorithm. Users aren't concerned.
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.br
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.SH ENVIRONMENT VARIABLES
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.br
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The following environment variables have to be set before using \fBboog\fP :
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.HP
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.ti 7
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\fIMBK_CATA_LIB\fP gives the auxiliary paths of the directories of input files (behavioural description).
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.HP
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.ti 7
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\fIMBK_TARGET_LIB\fP gives the path (single) of the directory of the selected standard cell library.
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.HP
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.ti 7
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\fIMBK_IN_LO\fP gives the format of models instantiated in the structural description.
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.HP
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.ti 7
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\fIMBK_OUT_LO\fP gives the output format of the structural description.
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.SH EXAMPLE
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.br
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You can call \fBboog\fP as follows :
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.br
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.br
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boog alu alu
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.SH SEE ALSO
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.br
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boog(1), scmap(1), c4map(1), xlmap(1), proof(1), yagle(1), asimut(1), vhdl(5), scr(1), sclib(1), sxlib(1).
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.br
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.SH DIAGNOSTICS
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.br
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"VHDL : Error - bad usage of the 'stable' attribut"
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.br
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The stable attribut must be used with only one signal in a guarded expression
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.br
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.so man1/alc_bug_rprt.1
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