Doc d'install...
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Olivier Sirol
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# Alliance VLSI CAD System
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#
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# Home page : http://www-asim.lip6.fr/alliance/
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# E-mail support : mailto:alliance-support@asim.lip6.fr
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# ftp sites : ftp://ftp.lip6.fr/lip6/softs/alliance/
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# or ftp://ftp-asim.lip6.fr/pub/alliance/
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#
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# $Id: CHANGES,v 1.1 1999/05/31 17:11:53 czo Exp $
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--------------------------------------------------------------------------------
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ALLIANCE release 3.2b (15/12/97)
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1/ Easy install
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A "configure" script is now available to configure
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Alliance on any UNIX system
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2/ New driver :
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Support to VERILOG netlist as been added.
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Only driver exits. This means you can save your
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netlists to VERILOG format 'vlg'
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3/ New names :
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- Logic has been splited in 3 parts,
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. bop : boolean optimizer (logic -o)
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. scmap : Std cell mapping (logic -s)
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. c4map : CCCC mapping (logic -c)
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- Desb is replaced by yagle
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- Alligator is replaced by fpmap (X4000)
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- Netoptim is replaced glop
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4/ Cells libraries
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The tree of directories containing the cells
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libraries has been simplified
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--------------------------------------------------------------------------------
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ALLIANCE release 3.2 (17/05/97)
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1/ GRAPHICAL PATTERN VIEWER
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In order to see the patterns resulting from a simulation,
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the XPAT tools has been developped.
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2/ GRAPHICAL FSM VIEWER
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In order to see the state's graph of an FSM the XFSM tools has
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been developped.
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3/ RECTANGLE LAYOUT VIEWER
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Now, DREAL is also a real layout editor.
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--------------------------------------------------------------------------------
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ALLIANCE release 3.0 (17/05/94)
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1/ FPGA SYNTHESIS
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A logic synthesis tools that maps on FPGA is now available.
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It works for X3000 devices
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2/ FLOOR-PLAN ROUTING
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Binaries of the CHEOPS router from BULL are available for sparc.
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3/ TIMING ANALYSIS
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The static timing analisys tools TAS is finally available.
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It can be targetted to several processes though the use of a technological
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file suffixed `elp'.
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4/ RECTANGLE LAYOUT VIEWER
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In order to see the layout resulting from a symbolic to real translation,
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the DREAL tools has been developped.
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--------------------------------------------------------------------------------
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ALLIANCE release 2.0 (14/02/94) versus ALLIANCE 1.2
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1/ SYMBOLIC LAYOUT EDITOR
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The symbolic layout editor ALC has been replaced by GRAAL.
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GRAAL provides the same functionnalities than ALC, but is much
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more reliable. GRAAL support both CMOS and GaAs symbolic layout.
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> man graal
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2/ DESIGN RULE CHECKER
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The Design Rule Checker VERSATIL has been replaced by DRUC.
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DRUC provides the same functionnalities than VERSATIL.
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A hierarchical version will be distributed in the next ALLIANCE release.
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> man druc
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3/ LOGIC SYNTHESIS
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The logic synthesis tool LOGIC has been strongly improved.
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The new tool NETOPTIM is a gate-level net-list optimiser
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that allows to minimize delays in a synthesized gate net-list.
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The Finite-state-machine synthesizer SYF allows to describe and
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synthesize high complexity FSM (more than 100 states)
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It is possible to describe hierachical FSM using stack (subroutines).
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> man logic
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> man syf
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> man netoptim
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4/ DATA-PATH COMPILER
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FPGEN is a data-path compiler using a dedicated macro-cells library.
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DPR is the place and route tool that creates optimized data-path blocks
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from the gate net-list generated by FPGEN.
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> man fpgen
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> man dpr
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5/ PARAMETERIZED MACRO-CELLS
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Six parametrized generators are part of this release:
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> man rsa # fast adder generator
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> man bsg # barrel shifter generator
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> man amg # multiplier generator
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> man rfg # register file generator
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> man grog # high speed ROM generator
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> man rage # static RAM generator
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6/ PROCEDURAL LAYOUT DEBUGGER
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The graphic debugger GENVIEW allows to debug custom blocks
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described with the procedural language GENLIB.
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It makes possible to design new parameterized generators, using the
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GENLIB language.
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> man genview
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7/ POSTSCIPT DRIVER
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The postscript driver MBK2PS has been replaced by L2P, in order to
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obtain a printable postscript file from a cell layout.
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This tool accept not only symbolic layout (.ap files) but also
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physical layout (.cif or .gds files).
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> man l2p
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8/ FLOOR-PLAN ROUTER
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There is no floor-plan router in this release.
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If you need to interconnect two blocks, you can use the BBR tool
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that is actually a simple gridless channel router.
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> man bbr
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9/ FILE FORMATS
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Both file formats .ap (symbolic layout) and .al (net-list)
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have been modified, with upward compatibility: all files
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created with ALLIANCE release 1.2 are readable and usable with
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ALLIANCE release 2.0.
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> man ap
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> man al
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10/ PROCESS MAPPING
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The S2R tool that performs the physical mapping to a target process
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has been documented: the procedure to parameterize the technology
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file is described in the doc/misc/process_mapping.ps file.
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The technology file format has been modified.
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> man s2r
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> man prol
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# EOF
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@ -0,0 +1,288 @@
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# Alliance VLSI CAD System
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#
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# Home page : http://www-asim.lip6.fr/alliance/
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# E-mail support : mailto:alliance-support@asim.lip6.fr
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# ftp sites : ftp://ftp.lip6.fr/lip6/softs/alliance/
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# or ftp://ftp-asim.lip6.fr/pub/alliance/
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#
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# $Id: FAQ,v 1.1 1999/05/31 17:11:53 czo Exp $
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--------------------------------------------------------------------------------
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FAQ (Frequently Asked Questions)
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This file contains the basic pointers to
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the different documents or manuals found in this release.
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Question 1: What is ALLIANCE ?
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Question 2: What is ALLIANCE general copyright policy ?
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Question 3: How to install ALLIANCE ?
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Question 4: How to get started ?
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Question 5: What are the differences with the previous releases ?
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Question 6: What is the supported VHDL subset ?
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Question 7: What is the available online documentation ?
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Question 8: Where are defined the symbolic layout rules ?
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Question 9: How is performed the mapping to a target process ?
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Question 10: How can I get a complete paper documentation ?
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Question 11: What are the supported file formats ?
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Question 12: How can I get in touch with the ALLIANCE team ?
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Question 1: What is ALLIANCE ?
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------------------------------
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You can read a general description of the ALLIANCE tools and libraries
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by printing the PostScript files overview.ps located in the root
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directory:
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> lpr overview.ps
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Question 2: What is ALLIANCE general copyright policy ?
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-------------------------------------------------------
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"Alliance VLSI CAD System" is free Software.
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Unlike versions of Alliance up to 3.1 that where released
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including sources, version 3.2 and up will not be available
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with the source code.
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Source is however still available, but only upon request to
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alliance-support@lip6.fr. The release of the source is now
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subject to a non disclosure agreement.
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You are welcome to use the software package even for commercial
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designs whithout any fee. You are just required to mention :
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"Designed with Alliance CAD system"
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> more LICENCE
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Question 3: How to install ALLIANCE ?
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-------------------------------------
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Binary packcages are available for :
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- i386 Linux_elf
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- sparc SunOS 4.1.1
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- sparc Solaris 5.5.1
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To install Alliance follow the steps written in README
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> more README
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Question 4: How to get started ?
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--------------------------------
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You can find 3 separate tutorials in the tutorials directory:
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(Read overview.ps)
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1/ ADDACCU
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The design of a very simple chip (adder/accumulator) to get started
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with the ALLIANCE tools.
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>cd tutorials/addaccu
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2/ AMD2901
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The design of the 4 bits AMD2901 processor, from the VHDL specification to
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the CIF layout, using the ALLIANCE portable standard cells library.
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>cd tutorials/amd2901
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3/ Data Path
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Building simple data paths using on a procedural data path generator
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(fpgen) and a data path place and route tool (dpr).
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>cd tutorials/fitpath
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Question 5: What are the differences with the previous releases ?
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----------------------------------------------------------------
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The new features of this release are described in the CHANGES file:
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> more CHANGES
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Question 6: What is the supported VHDL subset ?
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-----------------------------------------------
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You can find a general presentation of the VHDL subset by issuing the
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following commands:
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> man vhdl
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This gives you an hint about the supported VHDL subset.
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There is actually three separate architectures types: "Structural",
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"Data-flow", and "Finite-State-Machine"
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> man vst
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This gives you the VHDL subset supported for structural descriptions.
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> man vbe
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This gives you the data-flow behavioral subset supported by the simulator
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ASIMUT, the logic synthesis tools BOP and SCMAP and the formal prover PROOF.
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> man fsm
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This gives you the VHDL subset used for Finite-State-Machine description
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and supported by the FSM synthesis tool SYF.
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Question 7: What is the available online documentation ?
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--------------------------------------------------------
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Each tools has its own manual.
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All the tools rely on the use of environment variables: all the relevant
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variables are listed in the `ENVIRONMENT VARIABLES' section of the manual
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page.
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1) tools
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--------
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> man asimut # VHDL simulator
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> man bbr # channel router
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> man dpr # data-path place & route
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> man dreal # real layout viewer
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> man druc # design rule checker
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> man fpgen # procedural data-path generation language
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> man fpmap # logic synthesis tool for FPGA
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> man genlib # procedural net-list generation language
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> man genpat # procedural pattern generation language
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> man genview # interactive block genreator debugger
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> man graal # graphic layout editor
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> man l2p # layout to postcript translation tool
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> man bop # boolean optimizer
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> man lvx # net-list comparator
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> man lynx # layout extractor
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> man glop # net-list optimiser
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> man proof # VHDL description's formal proover
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> man ring # router between core & pads
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> man s2r # symbolic layout to real mask expander
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> man scmap # standard cell mapping
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> man scr # standard cells place & route
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> man syf # finite state machine synthesis tool
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> man tas # static timing analyser
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> man yagle # functional abstractor
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2) cell libraries
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-----------------
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> man sclib # standard cells library
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> man dplib # data path cells library
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> man fplib # data path cells library
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> man padlib # pad library
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> man rsa # fast adder generator
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> man bsg # barrel shifter generator
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> man amg # multiplier generator
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> man rfg # register file generator
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> man grog # high speed ROM generator
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> man rage # static RAM generator
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3) ALLIANCE file formats
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------------------------
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> man vhdl # VHDL overview
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> man vst # VHDL subset for net-list
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> man vbe # VHDL subset for data-flow
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> man fsm # VHDL subset for finite-state-machine
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> man al # internal ALLIANCE netlist
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> man ap # internal ALLIANCE symbolic layout
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> man pat # internal ALLIANCE pattern description
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4) miscellaneous
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----------------
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> man catal # use of the catalog file
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> man prol # technology file
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> man mbkenv # main environement variables
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Question 8: Where are defined the symbolic layout rules ?
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----------------------------------------------------------
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The symbolic layout rules are specified in the Design Rule Checker
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documentation:
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> man druc
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Question 9: How is performed the mapping to a target process ?
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||||||
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---------------------------------------------------------------
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The actual conversion is performed by the s2r tool:
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> man s2r
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If you want to parameterize the S2R tool to a new target technology,
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you must write a technology file. The method is described in the
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postscript file doc/misc/process_mapping.ps
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||||||
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> lpr doc/misc/process_mapping.ps
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||||||
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||||||
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Question 10: How can I get a complete paper documentation ?
|
||||||
|
-----------------------------------------------------------
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||||||
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|
||||||
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We are making a printed documentation of all manuals of the
|
||||||
|
ALLIANCE tools. It will be available soon.
|
||||||
|
|
||||||
|
|
||||||
|
Question 11: What are the supported file formats ?
|
||||||
|
--------------------------------------------------
|
||||||
|
|
||||||
|
ALLIANCE tools are interfaced to generic data-structures that
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||||||
|
support various standard file formats, thanks to a set of
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||||||
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specialized parsers/drivers.
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||||||
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UNIX environment variables are used to select one particular file format.
|
||||||
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For a given entity, the file format is defined by the file extension.
|
||||||
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||||||
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1/ symbolic layout view
|
||||||
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||||||
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ALLIANCE .ap INPUT OUTPUT
|
||||||
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COMPASS .cp INPUT OUTPUT
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||||||
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2/ physical layout view
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||||||
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||||||
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CIF .cif OUTPUT
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||||||
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GDSII .gds OUTPUT
|
||||||
|
|
||||||
|
3/ netlist view
|
||||||
|
|
||||||
|
ALLIANCE .al INPUT OUTPUT
|
||||||
|
SPICE .spi INPUT OUTPUT
|
||||||
|
EDIF 2.0 .edi INPUT OUTPUT
|
||||||
|
VHDL .vst INPUT OUTPUT
|
||||||
|
COMPASS .hns INPUT OUTPUT
|
||||||
|
HILO .cct OUTPUT
|
||||||
|
VERILOG .vlg OUTPUT
|
||||||
|
|
||||||
|
4/ behavioural view
|
||||||
|
|
||||||
|
VHDL (data-flow) .vbe INPUT OUTPUT
|
||||||
|
VHDL (FSM) .fsm INPUT
|
||||||
|
|
||||||
|
|
||||||
|
Question 12: How can I get in touch with the ALLIANCE team ?
|
||||||
|
------------------------------------------------------------
|
||||||
|
|
||||||
|
Look at the Alliance support Web pages
|
||||||
|
at http://www-asim.lip6.fr/alliance/support
|
||||||
|
|
||||||
|
You may get ALLIANCE by two distinct means:
|
||||||
|
|
||||||
|
1) by anonymous FTP at ftp://ftp.lip6.fr/lip6/softs/alliance/
|
||||||
|
|
||||||
|
2) by sending a blank tape (we can write DC 600A 60 MBytes,
|
||||||
|
DC 6150 150 MBytes and ExaByte 8mm 2,3 GBytes) or a ZIP 100
|
||||||
|
or blank CD-ROM with your complete affiliation to the
|
||||||
|
following address:
|
||||||
|
|
||||||
|
Laboratoire ASIM/LIP6
|
||||||
|
Tour 55-65, 2eme etage
|
||||||
|
Université Pierre et Marie Curie
|
||||||
|
4, Place Jussieu 75252 Paris Cedex 05,
|
||||||
|
France
|
||||||
|
|
||||||
|
Fax : 33 1 44 27 62 86
|
||||||
|
Home page : http://www-asim.lip6.fr/alliance/support
|
||||||
|
E-mail support : mailto:alliance-support@asim.lip6.fr
|
||||||
|
ftp sites : ftp://ftp.lip6.fr/lip6/softs/alliance/ (faster mirror site)
|
||||||
|
: ftp://asim.lip6.fr/pub/alliance/ (primary site)
|
||||||
|
|
||||||
|
|
||||||
|
# EOF
|
||||||
|
|
@ -0,0 +1,101 @@
|
||||||
|
# Alliance VLSI CAD System
|
||||||
|
#
|
||||||
|
# Home page : http://www-asim.lip6.fr/alliance/
|
||||||
|
# E-mail support : mailto:alliance-support@asim.lip6.fr
|
||||||
|
# ftp sites : ftp://ftp.lip6.fr/lip6/softs/alliance/
|
||||||
|
# or ftp://ftp-asim.lip6.fr/pub/alliance/
|
||||||
|
#
|
||||||
|
# $Id: LICENCE,v 1.1 1999/05/31 17:11:53 czo Exp $
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
ALLIANCE BINARY PACKAGE LICENCE AGREEMENT
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
Copyright 1990,97 ASIM/LIP6/UPMC
|
||||||
|
|
||||||
|
"Alliance VLSI CAD System" is free Software.
|
||||||
|
|
||||||
|
Unlike versions of Alliance up to 3.1 that where released including
|
||||||
|
sources, version 3.2 and up will not be available with the source
|
||||||
|
code.
|
||||||
|
|
||||||
|
Source is however still available, but only upon request to
|
||||||
|
alliance-support@lip6.fr. The release of the source is now subject to
|
||||||
|
a non disclosure agreement.
|
||||||
|
|
||||||
|
You are welcome to use the software package even for commercial
|
||||||
|
designs whithout any fee. You are just required to mention : "Designed
|
||||||
|
with Alliance CAD system"
|
||||||
|
|
||||||
|
Permission to use, copy, and distribute this software and its
|
||||||
|
documentation for any purpose is hereby granted without fee, provided
|
||||||
|
that the above copyright notice appear in all copies and that the
|
||||||
|
package is not modified.
|
||||||
|
|
||||||
|
|
||||||
|
DISCLAIMER OF WARRANTY. Free of charge Software is provided on an "AS
|
||||||
|
IS" basis, without warranty of any kind, including without limitation
|
||||||
|
the warranties that the Software is free of defects, merchantable, fit
|
||||||
|
for a particular purpose or non-infringing. The entire risk as to the
|
||||||
|
quality and performance of the Software is borne by you. Should the
|
||||||
|
Software prove defective in any respect, you and not Licensor or its
|
||||||
|
suppliers assume the entire cost of any service and repair. In
|
||||||
|
addition, the security mechanisms implemented by the Software have
|
||||||
|
inherent limitations, and you must determine that the Software
|
||||||
|
sufficiently meets your requirements. This disclaimer of warranty
|
||||||
|
constitutes an essential part of this Agreement.
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
Contents copyrighted by
|
||||||
|
|
||||||
|
Nizar ABDALLAH
|
||||||
|
Pascale ALLEGRE
|
||||||
|
Amara AMARA
|
||||||
|
Gregoire AVOT
|
||||||
|
Pirouz BAZARGAN-SABET
|
||||||
|
Lotfi BEN-AMMAR
|
||||||
|
Abdelhafid BOUARAOUA
|
||||||
|
Luc BURGUN
|
||||||
|
Jean-Paul CHAPUT
|
||||||
|
Arnaud CARON
|
||||||
|
Stephane DAYRAS
|
||||||
|
Anne DERIEUX
|
||||||
|
Gilles-Eric DESCAMPS
|
||||||
|
Nathalie DICTUS
|
||||||
|
Karim DIOURY
|
||||||
|
Julien DUNOYER
|
||||||
|
Olivier FLORENT
|
||||||
|
Alain GREINER
|
||||||
|
Amjad HAJJAR
|
||||||
|
Mokhtar HIRECH
|
||||||
|
Ludovic JACOMME
|
||||||
|
Payam KIANI
|
||||||
|
Marc LAURENTIN
|
||||||
|
Anthony LESTER
|
||||||
|
Marie-Minerve LOUERAT
|
||||||
|
Luis LUCAS
|
||||||
|
Francois PECHEUX
|
||||||
|
Frederic PETROT
|
||||||
|
Vincent POUILLEY
|
||||||
|
Eudes PRADO
|
||||||
|
El-Housseine REJOUAN
|
||||||
|
Pascal REMY
|
||||||
|
Patrick RENAUD
|
||||||
|
Philippe ROYANNEZ
|
||||||
|
Mohamed-Chaker SARWARY
|
||||||
|
Olivier SIROL
|
||||||
|
Huu-Nghia VUONG
|
||||||
|
Franck WAJSBURT
|
||||||
|
Laurent WINCKEL
|
||||||
|
|
||||||
|
Special thanks to
|
||||||
|
All the members of the Architecture Team of the ASIM Laboratory
|
||||||
|
All the users of the Alliance CAD system that
|
||||||
|
help us in providing VLSI tools for free.
|
||||||
|
|
||||||
|
|
||||||
|
# EOF
|
||||||
|
|
||||||
|
|
@ -0,0 +1,115 @@
|
||||||
|
# Alliance VLSI CAD System
|
||||||
|
#
|
||||||
|
# Home page : http://www-asim.lip6.fr/alliance/
|
||||||
|
# E-mail support : mailto:alliance-support@asim.lip6.fr
|
||||||
|
# ftp sites : ftp://ftp.lip6.fr/lip6/softs/alliance/
|
||||||
|
# or ftp://ftp-asim.lip6.fr/pub/alliance/
|
||||||
|
#
|
||||||
|
# $Id: README,v 1.1 1999/05/31 17:11:53 czo Exp $
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
# Alliance
|
||||||
|
# ===================================================================
|
||||||
|
|
||||||
|
"Alliance VLSI CAD System" is free Software.
|
||||||
|
|
||||||
|
Unlike versions of Alliance up to 3.1 that where released
|
||||||
|
including sources, version 3.2 and up will not be available
|
||||||
|
with the source code.
|
||||||
|
|
||||||
|
Source is however still available, but only upon request to
|
||||||
|
alliance-support@lip6.fr. The release of the source is now
|
||||||
|
subject to a non disclosure agreement.
|
||||||
|
|
||||||
|
You are welcome to use the software package even for commercial
|
||||||
|
designs whithout any fee. You are just required to mention :
|
||||||
|
"Designed with Alliance CAD system"
|
||||||
|
|
||||||
|
You can get Alliance via anonymous FTP from ftp.lip6.fr
|
||||||
|
|
||||||
|
ftp://ftp.lip6.fr/lip6/softs/alliance/
|
||||||
|
|
||||||
|
or ftp://ftp-asim.lip6.fr/pub/alliance/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
# Downloading
|
||||||
|
# ===================================================================
|
||||||
|
|
||||||
|
|
||||||
|
You will have to download at least two files : one for the common files
|
||||||
|
of Alliance (like cells library) and another containing binaries for
|
||||||
|
your specific platform. Actually only Linux_elf, SunOS and Solaris
|
||||||
|
are supported.
|
||||||
|
|
||||||
|
alliance-3.2b-common.tar.gz Files common to each platform *required*
|
||||||
|
|
||||||
|
alliance-3.2b-i386-linux-2.0.30.tar.gz Binaries Linux_elf
|
||||||
|
|
||||||
|
alliance-3.2b-sparc-sunos-4.1.1.tar.gz Binaries SunOS
|
||||||
|
|
||||||
|
alliance-3.2b-sparc-solaris-2.5.1.tar.gz Binaries Solaris
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
# Installation :
|
||||||
|
# ===================================================================
|
||||||
|
|
||||||
|
You *dont* need to be root to install Alliance in a directory you *own*
|
||||||
|
|
||||||
|
In the example above I assume you have logged as root
|
||||||
|
|
||||||
|
1/ cd to the directory where you want to install Alliance
|
||||||
|
|
||||||
|
> cd /usr/local
|
||||||
|
|
||||||
|
2/ Unpack the common package
|
||||||
|
|
||||||
|
> gunzip -c alliance-3.2b-common.tgz | tar -pvxf -
|
||||||
|
|
||||||
|
3/ Unpack one of the platform specific package
|
||||||
|
|
||||||
|
> gunzip -c alliance-3.2b-Linux_elf.tgz | tar -pvxf -
|
||||||
|
|
||||||
|
4/ cd to alliance/share/etc and run the 'configure' script
|
||||||
|
(This is the *only* script you need to run)
|
||||||
|
|
||||||
|
> cd alliance/share/etc
|
||||||
|
> ./configure
|
||||||
|
|
||||||
|
If you install Alliance on different platforms you'll
|
||||||
|
need to run the 'configure' script on each of them
|
||||||
|
|
||||||
|
|
||||||
|
# Usage :
|
||||||
|
# ===================================================================
|
||||||
|
|
||||||
|
Each user has to source alc_env.[c]sh to set Alliance environment
|
||||||
|
variables to be able to run the Alliance tools.
|
||||||
|
|
||||||
|
in sh > . [where you have installed Alliance]/alliance/share/etc/alc_env.sh
|
||||||
|
|
||||||
|
in csh > source [where you have installed Alliance]/alliance/share/etc/alc_env.csh
|
||||||
|
|
||||||
|
This could be done in system's profile (/etc/profile)...
|
||||||
|
so that it would be done at user login
|
||||||
|
|
||||||
|
This sets various default environement variables which could be changed by user
|
||||||
|
later (Like MBK_OUT_LO to set the netlist output file format).
|
||||||
|
|
||||||
|
If you encounter problems, check the value of these variables in alc_env.[c]sh
|
||||||
|
|
||||||
|
$MACHINE : actually Linux_elf
|
||||||
|
or SunOS
|
||||||
|
or Solaris
|
||||||
|
|
||||||
|
$TOP : actually [where you have installed Alliance]/alliance/archi/Linux_elf
|
||||||
|
or [where you have installed Alliance]/alliance/archi/SunOS
|
||||||
|
or [where you have installed Alliance]/alliance/archi/Solaris
|
||||||
|
|
||||||
|
That's all :-)
|
||||||
|
|
||||||
|
|
||||||
|
# EOF
|
||||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue