From bcd0c009c6ca0b6cb52122bc554c036ac2635992 Mon Sep 17 00:00:00 2001 From: Ludovic Jacomme Date: Sun, 23 May 2004 18:06:11 +0000 Subject: [PATCH] - synchronous 8 bits multiplier with a FSM --- .../multi8/CATAL_ASIMUT_VASY | 5 + .../alliance-examples/multi8/Makefile | 349 ++++++++++++++++++ .../alliance-examples/multi8/README | 19 + .../alliance-examples/multi8/addaccu.vhdl | 34 ++ .../alliance-examples/multi8/controller.vhdl | 59 +++ .../alliance-examples/multi8/multi8.ioc | 43 +++ .../alliance-examples/multi8/multi8.pat | 79 ++++ .../alliance-examples/multi8/multi8.vhdl | 121 ++++++ .../alliance-examples/multi8/sra.vhdl | 55 +++ .../alliance-examples/multi8/srb.vhdl | 41 ++ 10 files changed, 805 insertions(+) create mode 100644 alliance/src/documentation/alliance-examples/multi8/CATAL_ASIMUT_VASY create mode 100644 alliance/src/documentation/alliance-examples/multi8/Makefile create mode 100644 alliance/src/documentation/alliance-examples/multi8/README create mode 100644 alliance/src/documentation/alliance-examples/multi8/addaccu.vhdl create mode 100644 alliance/src/documentation/alliance-examples/multi8/controller.vhdl create mode 100644 alliance/src/documentation/alliance-examples/multi8/multi8.ioc create mode 100644 alliance/src/documentation/alliance-examples/multi8/multi8.pat create mode 100644 alliance/src/documentation/alliance-examples/multi8/multi8.vhdl create mode 100644 alliance/src/documentation/alliance-examples/multi8/sra.vhdl create mode 100644 alliance/src/documentation/alliance-examples/multi8/srb.vhdl diff --git a/alliance/src/documentation/alliance-examples/multi8/CATAL_ASIMUT_VASY b/alliance/src/documentation/alliance-examples/multi8/CATAL_ASIMUT_VASY new file mode 100644 index 00000000..a420b11d --- /dev/null +++ b/alliance/src/documentation/alliance-examples/multi8/CATAL_ASIMUT_VASY @@ -0,0 +1,5 @@ +addaccu C +multi8_model C +srb C +controller C +sra C diff --git a/alliance/src/documentation/alliance-examples/multi8/Makefile b/alliance/src/documentation/alliance-examples/multi8/Makefile new file mode 100644 index 00000000..9cc97b17 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/multi8/Makefile @@ -0,0 +1,349 @@ +# /*------------------------------------------------------------\ +# | | +# | File : Makefile | +# | | +# | Author : Jacomme Ludovic | +# | | +# \------------------------------------------------------------*/ +# /*------------------------------------------------------------\ +# | | +# | Cells | +# | | +# \------------------------------------------------------------*/ +# /*------------------------------------------------------------\ +# | | +# | Binary | +# | | +# \------------------------------------------------------------*/ + +ALLIANCE_BIN=$(ALLIANCE_TOP)/bin + +VASY = $(ALLIANCE_BIN)/vasy +ASIMUT = $(ALLIANCE_BIN)/asimut +BOOM = $(ALLIANCE_BIN)/boom +BOOG = $(ALLIANCE_BIN)/boog +LOON = $(ALLIANCE_BIN)/loon +OCP = $(ALLIANCE_BIN)/ocp +NERO = $(ALLIANCE_BIN)/nero +COUGAR = $(ALLIANCE_BIN)/cougar +LVX = $(ALLIANCE_BIN)/lvx +DRUC = $(ALLIANCE_BIN)/druc +S2R = $(ALLIANCE_BIN)/s2r + +DREAL = $(ALLIANCE_BIN)/dreal +GRAAL = $(ALLIANCE_BIN)/graal +XSCH = $(ALLIANCE_BIN)/xsch +XPAT = $(ALLIANCE_BIN)/xpat +XFSM = $(ALLIANCE_BIN)/xfsm + +TOUCH = touch + +TARGET_LIB = $(ALLIANCE_TOP)/cells/sxlib +RDS_TECHNO_SYMB = ../etc/techno-symb.rds +RDS_TECHNO = ../etc/techno-035.rds +SPI_MODEL = $(ALLIANCE_TOP)/etc/spimodel.cfg +METAL_LEVEL = 2 + +# /*------------------------------------------------------------\ +# | | +# | Environement | +# | | +# \------------------------------------------------------------*/ + +ENV_VASY = MBK_WORK_LIB=.; export MBK_WORK_LIB;\ + MBK_CATAL_NAME=NO_CATAL; export MBK_CATAL_NAME + +ENV_BOOM = MBK_WORK_LIB=.; export MBK_WORK_LIB;\ + MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME + +ENV_BOOG = MBK_WORK_LIB=.; export MBK_WORK_LIB; \ + MBK_IN_LO=vst; export MBK_IN_LO; \ + MBK_OUT_LO=vst; export MBK_OUT_LO; \ + MBK_TARGET_LIB=$(TARGET_LIB); export MBK_TARGET_LIB; \ + MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME + +ENV_LOON = MBK_WORK_LIB=.; export MBK_WORK_LIB; \ + MBK_IN_LO=vst; export MBK_IN_LO; \ + MBK_OUT_LO=vst; export MBK_OUT_LO; \ + MBK_TARGET_LIB=$(TARGET_LIB); export MBK_TARGET_LIB; \ + MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \ + MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME + +ENV_ASIMUT_VASY = MBK_WORK_LIB=.; export MBK_WORK_LIB;\ + MBK_CATAL_NAME=CATAL_ASIMUT_VASY; export MBK_CATAL_NAME;\ + MBK_IN_LO=vst; export MBK_IN_LO;\ + MBK_OUT_LO=vst; export MBK_OUT_LO + +ENV_ASIMUT_SYNTH = MBK_WORK_LIB=.; export MBK_WORK_LIB;\ + MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME;\ + MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \ + MBK_IN_LO=vst; export MBK_IN_LO;\ + MBK_OUT_LO=vst; export MBK_OUT_LO + +ENV_OCP = MBK_WORK_LIB=.; export MBK_WORK_LIB; \ + MBK_IN_LO=vst; export MBK_IN_LO; \ + MBK_OUT_LO=vst; export MBK_OUT_LO; \ + MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \ + MBK_IN_PH=ap; export MBK_IN_PH; \ + MBK_OUT_PH=ap; export MBK_OUT_PH; \ + MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME + +ENV_NERO = MBK_WORK_LIB=.; export MBK_WORK_LIB; \ + MBK_IN_LO=vst; export MBK_IN_LO; \ + MBK_OUT_LO=vst; export MBK_OUT_LO; \ + MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \ + MBK_IN_PH=ap; export MBK_IN_PH; \ + MBK_OUT_PH=ap; export MBK_OUT_PH; \ + MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME + +ENV_COUGAR_SPI = MBK_WORK_LIB=.; export MBK_WORK_LIB; \ + MBK_IN_LO=spi; export MBK_IN_LO; \ + MBK_OUT_LO=spi; export MBK_OUT_LO; \ + MBK_SPI_NAMEDNODES="true"; export MBK_SPI_NAMEDNODES; \ + MBK_SPI_MODEL=$(SPI_MODEL); export MBK_SPI_MODEL; \ + RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME; \ + RDS_IN=cif; export RDS_IN; \ + RDS_OUT=cif; export RDS_OUT; \ + MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \ + MBK_IN_PH=ap; export MBK_IN_PH; \ + MBK_OUT_PH=ap; export MBK_OUT_PH; \ + MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME + +ENV_COUGAR = MBK_WORK_LIB=.; export MBK_WORK_LIB; \ + MBK_IN_LO=al; export MBK_IN_LO; \ + MBK_OUT_LO=al; export MBK_OUT_LO; \ + RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME; \ + RDS_IN=cif; export RDS_IN; \ + RDS_OUT=cif; export RDS_OUT; \ + MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \ + MBK_IN_PH=ap; export MBK_IN_PH; \ + MBK_OUT_PH=ap; export MBK_OUT_PH; \ + MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME + +ENV_LVX = MBK_WORK_LIB=.; export MBK_WORK_LIB; \ + MBK_IN_LO=vst; export MBK_IN_LO; \ + MBK_OUT_LO=vst; export MBK_OUT_LO; \ + MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \ + MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME + +ENV_DRUC = MBK_WORK_LIB=.; export MBK_WORK_LIB; \ + RDS_TECHNO_NAME=$(RDS_TECHNO_SYMB); export RDS_TECHNO_NAME; \ + MBK_IN_PH=ap; export MBK_IN_PH; \ + MBK_OUT_PH=ap; export MBK_OUT_PH; \ + MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \ + MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME + +ENV_S2R = MBK_WORK_LIB=.; export MBK_WORK_LIB; \ + RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME; \ + RDS_IN=cif; export RDS_IN; \ + RDS_OUT=cif; export RDS_OUT; \ + MBK_IN_PH=ap; export MBK_IN_PH; \ + MBK_OUT_PH=ap; export MBK_OUT_PH; \ + MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \ + MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME + + +all : multi8.cif + +# /*------------------------------------------------------------\ +# | | +# | Vasy | +# | | +# \------------------------------------------------------------*/ + +multi8.vst addaccu.vbe controller.vbe sra.vbe srb.vbe multi8_model.vbe : multi8.vhdl addaccu.vhdl \ + controller.vhdl multi8.vhdl sra.vhdl srb.vhdl + $(ENV_VASY); $(VASY) -a -B -o -p -I vhdl -H multi8 + +# /*------------------------------------------------------------\ +# | | +# | Asimut | +# | | +# \------------------------------------------------------------*/ + +res_vasy_1.pat : multi8.vst addaccu.vbe sra.vbe srb.vbe \ + controller.vbe multi8_model.vbe + $(ENV_ASIMUT_VASY); $(ASIMUT) multi8 multi8 res_vasy_1 + +res_synth_1.pat : multi8.vst addaccu.vst sra.vst srb.vst \ + controller.vst multi8_model.vst + $(ENV_ASIMUT_SYNTH); $(ASIMUT) multi8 multi8 res_synth_1 + +# /*------------------------------------------------------------\ +# | | +# | Boom | +# | | +# \------------------------------------------------------------*/ + +boom.done : addaccu_o.vbe sra_o.vbe srb_o.vbe controller_o.vbe \ + multi8_model_o.vbe + @$(TOUCH) boom.done + +addaccu_o.vbe : addaccu.vbe addaccu.boom res_vasy_1.pat + $(ENV_BOOM); $(BOOM) -VP addaccu addaccu_o + +sra_o.vbe : sra.vbe sra.boom res_vasy_1.pat + $(ENV_BOOM); $(BOOM) -VP sra sra_o + +srb_o.vbe : srb.vbe srb.boom res_vasy_1.pat + $(ENV_BOOM); $(BOOM) -VP srb srb_o + +controller_o.vbe : controller.vbe controller.boom res_vasy_1.pat + $(ENV_BOOM); $(BOOM) -VP controller controller_o + +multi8_model_o.vbe : multi8_model.vbe multi8_model.boom res_vasy_1.pat + $(ENV_BOOM); $(BOOM) -VP multi8_model multi8_model_o + +# /*------------------------------------------------------------\ +# | | +# | Boog | +# | | +# \------------------------------------------------------------*/ + +boog.done : addaccu_o.vst sra_o.vst srb_o.vst controller_o.vst \ + multi8_model_o.vst + @$(TOUCH) boog.done + +addaccu_o.vst : addaccu_o.vbe + $(ENV_BOOG); $(BOOG) addaccu_o + +sra_o.vst : sra_o.vbe + $(ENV_BOOG); $(BOOG) sra_o + +srb_o.vst : srb_o.vbe + $(ENV_BOOG); $(BOOG) srb_o + +controller_o.vst : controller_o.vbe + $(ENV_BOOG); $(BOOG) controller_o + +multi8_model_o.vst : multi8_model_o.vbe + $(ENV_BOOG); $(BOOG) multi8_model_o + +# /*------------------------------------------------------------\ +# | | +# | Loon | +# | | +# \------------------------------------------------------------*/ + +loon.done : addaccu.vst sra.vst srb.vst controller.vst \ + multi8_model.vst + @$(TOUCH) loon.done + +addaccu.vst : addaccu_o.vst + $(ENV_LOON); $(LOON) addaccu_o addaccu + +sra.vst : sra_o.vst + $(ENV_LOON); $(LOON) sra_o sra + +srb.vst : srb_o.vst + $(ENV_LOON); $(LOON) srb_o srb + +controller.vst : controller_o.vst + $(ENV_LOON); $(LOON) controller_o controller + +multi8_model.vst : multi8_model_o.vst + $(ENV_LOON); $(LOON) multi8_model_o multi8_model + +# /*------------------------------------------------------------\ +# | | +# | OCP | +# | | +# \------------------------------------------------------------*/ + +multi8_p.ap : res_synth_1.pat + $(ENV_OCP); $(OCP) -v -ioc multi8 -gnuplot multi8 multi8_p + +# /*------------------------------------------------------------\ +# | | +# | NERO | +# | | +# \------------------------------------------------------------*/ + +multi8.ap : multi8_p.ap multi8.vst + $(ENV_NERO); $(NERO) -$(METAL_LEVEL) -p multi8_p multi8 multi8 + +# /*------------------------------------------------------------\ +# | | +# | Cougar | +# | | +# \------------------------------------------------------------*/ + +multi8_e.spi : multi8.ap + $(ENV_COUGAR_SPI); $(COUGAR) -v multi8 multi8_e + +multi8_e.al : multi8.ap + $(ENV_COUGAR); $(COUGAR) -v -ac multi8 multi8_e + +multi8_et.al : multi8.ap + $(ENV_COUGAR); $(COUGAR) -v -ac -t multi8 multi8_et + +multi8_et.spi : multi8.ap + $(ENV_COUGAR_SPI); $(COUGAR) -v -ac -t multi8 multi8_et + +multi8_er.spi : multi8.cif + $(ENV_COUGAR); $(COUGAR) -v -r -t multi8 multi8_er + +# /*------------------------------------------------------------\ +# | | +# | Lvx | +# | | +# \------------------------------------------------------------*/ + +lvx.done : multi8.vst multi8_e.al multi8_e.spi + $(ENV_LVX); $(LVX) vst al multi8 multi8_e -f + $(TOUCH) lvx.done + +# /*------------------------------------------------------------\ +# | | +# | Druc | +# | | +# \------------------------------------------------------------*/ + +druc.done : lvx.done multi8.ap + $(ENV_DRUC); $(DRUC) multi8 + $(TOUCH) druc.done + +# /*------------------------------------------------------------\ +# | | +# | S2R | +# | | +# \------------------------------------------------------------*/ + +multi8.cif : druc.done + $(ENV_S2R); $(S2R) -v -t multi8 + +# /*------------------------------------------------------------\ +# | | +# | TOOLS | +# | | +# \------------------------------------------------------------*/ + + +graal: multi8.ap + $(ENV_S2R); $(GRAAL) -l multi8 + +xsch: multi8.vst + $(ENV_LOON); $(XSCH) -l multi8 + +xscht: multi8_et.al + $(ENV_COUGAR); $(XSCH) -l multi8_et + +xpat: res_synth_1.pat + $(ENV_ASIMUT_SYNTH); $(XPAT) -l res_synth_1 + +dreal: multi8.cif + $(ENV_S2R); $(DREAL) -l multi8 + +# /*------------------------------------------------------------\ +# | | +# | Clean | +# | | +# \------------------------------------------------------------*/ + +realclean : clean + +clean : + $(RM) -f *.vst multi8_et.spi *.vbe res_*.pat *.boom *.done *.xsc *.gpl \ + *.ap *.drc *.dat *.gds blast.fin *.cif *.rep \ + *.log *.out *.raw *.al + diff --git a/alliance/src/documentation/alliance-examples/multi8/README b/alliance/src/documentation/alliance-examples/multi8/README new file mode 100644 index 00000000..dc83bab4 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/multi8/README @@ -0,0 +1,19 @@ +# /*------------------------------------------------------------\ +# | | +# | File : README | +# | | +# | Author : Jacomme Ludovic | +# | | +# \------------------------------------------------------------*/ + +This directory contains hierarchical VHDL descriptions of a synchronous 8 bits multiplier +(with a finite state machine and data part). +It contains also the associated stimuli file, and configuration file for IO +placement (used during the Place and Route step). + +The Makefile set environement variables properly and run Alliance tools, +following each step of the design flow from VHDL up to real layout in a + pseudo 0.35 techno. + +The environement variable ALLIANCE_TOP as to be set. + diff --git a/alliance/src/documentation/alliance-examples/multi8/addaccu.vhdl b/alliance/src/documentation/alliance-examples/multi8/addaccu.vhdl new file mode 100644 index 00000000..4701fa7d --- /dev/null +++ b/alliance/src/documentation/alliance-examples/multi8/addaccu.vhdl @@ -0,0 +1,34 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_arith.ALL; +use IEEE.STD_LOGIC_unsigned.ALL; + + +entity AddAccu is + + port ( CLR : in Std_Logic; + LD : in Std_Logic; + OUTS : in Std_Logic_Vector(15 downto 0) ; + CLK : in Std_Logic; + + RESULT : out Std_Logic_Vector(15 downto 0) ); + +end AddAccu; + + +---------------------------------------------------------------------- + +architecture DataFlow OF AddAccu is +signal resultint : Std_Logic_Vector(15 downto 0) ; +begin +process (CLK) +begin + if CLK'event and CLK='1' then + if CLR = '1' then resultint <= ( others => '0' ); + elsif LD = '1' then resultint <= resultint + OUTS; + end if; + end if; +end process; +RESULT <= resultint; +end DataFlow; +---------------------------------------------------------------------- diff --git a/alliance/src/documentation/alliance-examples/multi8/controller.vhdl b/alliance/src/documentation/alliance-examples/multi8/controller.vhdl new file mode 100644 index 00000000..e27e1eec --- /dev/null +++ b/alliance/src/documentation/alliance-examples/multi8/controller.vhdl @@ -0,0 +1,59 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity Controller is + port (STB, CLK, LSB, Done, RST: in STD_LOGIC; + Init, Shift, Add: out STD_LOGIC); +end Controller; + +--------------------------------------------------- + +architecture FSM of Controller is + + type States is (EndS,InitS, CheckS, AddS, ShiftS); + signal State: States ; +begin + + -- Drive control outputs based upon State + + Init <= '1' when State = InitS else '0'; + Add <= '1' when State = AddS else '0'; + Shift <= '1' when State = ShiftS else '0'; + + -- Determine Next State from control inputs + + StateMachine: + + process (CLK) + begin + --compass stateMachine adj State + if CLK'Event and CLK = '1' then + if RST = '1' then State <= EndS; + else + case State is + when InitS => + State <= CheckS; + when CheckS => + if LSB = '1' then + State <= AddS; + elsif Done = '0' then + State <= ShiftS; + else + State <= EndS; + end if; + when AddS => + State <= ShiftS; + when ShiftS => + State <= CheckS; + when EndS => + if STB = '1' then + State <= InitS; + end if; + end case; + end if; + end if; + end process; + +end FSM; + +--------------------------------------------------- diff --git a/alliance/src/documentation/alliance-examples/multi8/multi8.ioc b/alliance/src/documentation/alliance-examples/multi8/multi8.ioc new file mode 100644 index 00000000..51f4ce50 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/multi8/multi8.ioc @@ -0,0 +1,43 @@ + +TOP ( # IOs are ordered from left to right + (IOPIN clk.0 ); + (IOPIN rst.0 ); + (IOPIN stb.0 ); + (IOPIN a(7).0 ); + (IOPIN a(6).0 ); + (IOPIN a(5).0 ); + (IOPIN a(4).0 ); + (IOPIN a(3).0 ); + (IOPIN a(2).0 ); + (IOPIN a(1).0 ); + (IOPIN a(0).0 ); + (IOPIN b(7).0 ); + (IOPIN b(6).0 ); + (IOPIN b(5).0 ); + (IOPIN b(4).0 ); + (IOPIN b(3).0 ); + (IOPIN b(2).0 ); + (IOPIN b(1).0 ); + (IOPIN b(0).0 ); +) +BOTTOM ( # IOs are ordered from left to right + (IOPIN result(15).0 ); + (IOPIN result(14).0 ); + (IOPIN result(13).0 ); + (IOPIN result(12).0 ); + (IOPIN result(11).0 ); + (IOPIN result(10).0 ); + (IOPIN result(9).0 ); + (IOPIN result(8).0 ); + (IOPIN result(7).0 ); + (IOPIN result(6).0 ); + (IOPIN result(5).0 ); + (IOPIN result(4).0 ); + (IOPIN result(3).0 ); + (IOPIN result(2).0 ); + (IOPIN result(1).0 ); + (IOPIN result(0).0 ); + (IOPIN done.0 ); +) +IGNORE ( # IOs are ignored(not placed) by IO Placer +) diff --git a/alliance/src/documentation/alliance-examples/multi8/multi8.pat b/alliance/src/documentation/alliance-examples/multi8/multi8.pat new file mode 100644 index 00000000..667ddf9a --- /dev/null +++ b/alliance/src/documentation/alliance-examples/multi8/multi8.pat @@ -0,0 +1,79 @@ +-- input / output list : + +in clk B;; +in rst B;; +in stb B;; +in a (7 downto 0) X;; +in b (7 downto 0) X;; +out result (15 downto 0) X;; +out done B; + +begin + +-- Pattern description : + +-- C R S A B R D +-- L S T E O +-- K T B S N +-- U E +-- L +-- T + +< 0ns>: 0 1 0 00 00 ?**** ?*; +<+ 10ns>: 0 1 0 00 00 ?**** ?*; +<+ 10ns>: 1 1 0 00 00 ?**** ?*; +<+ 10ns>: 1 1 0 00 00 ?**** ?*; +<+ 10ns>: 0 1 0 00 00 ?**** ?*; +<+ 10ns>: 0 1 0 00 00 ?**** ?*; +<+ 10ns>: 0 0 0 00 00 ?**** ?*; +<+ 10ns>: 0 0 0 00 00 ?**** ?*; +<+ 10ns>: 0 0 1 00 00 ?**** ?*; +<+ 10ns>: 0 0 1 00 00 ?**** ?*; +<+ 10ns>: 1 0 1 00 00 ?**** ?*; +<+ 10ns>: 1 0 1 00 00 ?**** ?*; +<+ 10ns>: 0 0 1 00 00 ?**** ?*; +<+ 10ns>: 0 0 1 00 00 ?**** ?*; +<+ 10ns>: 0 0 0 02 03 ?**** ?*; +<+ 10ns>: 0 0 0 02 03 ?**** ?*; +<+ 10ns>: 1 0 0 02 03 ?**** ?*; +<+ 10ns>: 1 0 0 02 03 ?**** ?*; +<+ 10ns>: 0 0 0 02 03 ?0000 ?0; +<+ 10ns>: 0 0 0 02 03 ?0000 ?0; +<+ 10ns>: 0 0 0 00 00 ?0000 ?0; +<+ 10ns>: 0 0 0 00 00 ?0000 ?0; +<+ 10ns>: 1 0 0 00 00 ?0000 ?0; +<+ 10ns>: 1 0 0 00 00 ?0000 ?0; +<+ 10ns>: 0 0 0 00 00 ?0000 ?0; +<+ 10ns>: 0 0 0 00 00 ?0000 ?0; +<+ 10ns>: 0 0 0 00 00 ?0000 ?0; +<+ 10ns>: 0 0 0 00 00 ?0000 ?0; +<+ 10ns>: 1 0 0 00 00 ?0000 ?0; +<+ 10ns>: 1 0 0 00 00 ?0000 ?0; +<+ 10ns>: 0 0 0 00 00 ?0000 ?0; +<+ 10ns>: 0 0 0 00 00 ?0000 ?0; +<+ 10ns>: 0 0 0 00 00 ?0000 ?0; +<+ 10ns>: 0 0 0 00 00 ?0000 ?0; +<+ 10ns>: 1 0 0 00 00 ?0000 ?0; +<+ 10ns>: 1 0 0 00 00 ?0000 ?0; +<+ 10ns>: 0 0 0 00 00 ?0000 ?0; +<+ 10ns>: 0 0 0 00 00 ?0000 ?0; +<+ 10ns>: 0 0 0 00 00 ?0000 ?0; +<+ 10ns>: 0 0 0 00 00 ?0000 ?0; +<+ 10ns>: 1 0 0 00 00 ?**** ?0; +<+ 10ns>: 1 0 0 00 00 ?0006 ?0; +<+ 10ns>: 0 0 0 00 00 ?0006 ?0; +<+ 10ns>: 0 0 0 00 00 ?0006 ?0; +<+ 10ns>: 0 0 0 00 00 ?0006 ?0; +<+ 10ns>: 0 0 0 00 00 ?0006 ?0; +<+ 10ns>: 1 0 0 00 00 ?0006 ?*; +<+ 10ns>: 1 0 0 00 00 ?0006 ?1; +<+ 10ns>: 0 0 0 00 00 ?0006 ?1; +<+ 10ns>: 0 0 0 00 00 ?0006 ?1; +<+ 10ns>: 0 0 0 00 00 ?0006 ?1; +<+ 10ns>: 0 0 0 00 00 ?0006 ?1; +<+ 10ns>: 1 0 0 00 00 ?0006 ?1; +<+ 10ns>: 1 0 0 00 00 ?0006 ?1; +<+ 10ns>: 0 0 0 00 00 ?0006 ?1; +<+ 10ns>: 0 0 0 00 00 ?0006 ?1; + +end; diff --git a/alliance/src/documentation/alliance-examples/multi8/multi8.vhdl b/alliance/src/documentation/alliance-examples/multi8/multi8.vhdl new file mode 100644 index 00000000..32c4a68c --- /dev/null +++ b/alliance/src/documentation/alliance-examples/multi8/multi8.vhdl @@ -0,0 +1,121 @@ +-- Date of netlist generation: Dec-6-95 +---------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity Multi8 is + + + port ( A : in Std_Logic_Vector(7 downto 0) ; + B : in Std_Logic_Vector(7 downto 0) ; + CLK : in Std_Logic ; + RST : in Std_Logic ; + STB : in Std_Logic ; + + RESULT : out Std_Logic_Vector(15 downto 0) ; + DONE : out Std_Logic ); + +end Multi8; + +---------------------------------------------------------------------- + +architecture Structural OF Multi8 is + + component Controller + port ( STB : in Std_Logic; + CLK : in Std_Logic; + LSB : in Std_Logic; + DONE : in Std_Logic; + RST : in Std_Logic; + + INIT : out Std_Logic; + SHIFT : out Std_Logic; + ADD : out Std_Logic ); + end component; + + component Srb + port ( SHIFT : in Std_Logic; + LD : in Std_Logic; + CLK : in Std_Logic; + B : in Std_Logic_Vector(7 downto 0) ; + + OUTS : out Std_Logic_Vector(15 downto 0) ); + end component; + + component AddAccu + port ( CLR : in Std_Logic; + LD : in Std_Logic; + OUTS : in Std_Logic_Vector(15 downto 0) ; + CLK : in Std_Logic; + + RESULT : out Std_Logic_Vector(15 downto 0) ); + end component; + + component Sra + port ( SHIFT : in Std_Logic; + LD : in Std_Logic; + CLK : in Std_Logic; + RST : in Std_Logic; + A : in Std_Logic_Vector(7 downto 0) ; + + DONE : out Std_Logic; + LSB : out Std_Logic ); + end component; + + + signal DONE_local: Std_Logic; + signal U1_LSB : Std_Logic; + signal U3_INIT : Std_Logic; + signal U3_SHIFT : Std_Logic; + signal U3_ADD : Std_Logic; + signal OUT_INT : Std_Logic_vector(15 downto 0); + +begin + + + U3: Controller + port map ( STB => STB, + CLK => CLK, + LSB => U1_LSB, + DONE => DONE_local, + RST => RST, + INIT => U3_INIT, + SHIFT => U3_SHIFT, + ADD => U3_ADD ); + + U2: Srb + port map ( SHIFT => U3_SHIFT, + LD => U3_INIT, + CLK => CLK, + B => B, + OUTS => OUT_INT ); + + U5: AddAccu + port map ( CLR => U3_INIT, + LD => U3_ADD, + OUTS => OUT_INT, + CLK => CLK, + RESULT => RESULT ); + + U1: Sra + port map ( SHIFT => U3_SHIFT, + LD => U3_INIT, + RST => RST, + CLK => CLK, + A => A, + DONE => DONE_local, + LSB => U1_LSB ); + + DONE <= DONE_local; + +end Structural; + +configuration CFG_Multi8 of Multi8 is + for Structural + + end for; +end CFG_Multi8; + + +---------------------------------------------------------------------- diff --git a/alliance/src/documentation/alliance-examples/multi8/sra.vhdl b/alliance/src/documentation/alliance-examples/multi8/sra.vhdl new file mode 100644 index 00000000..c58c89d5 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/multi8/sra.vhdl @@ -0,0 +1,55 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_arith.ALL; +use IEEE.STD_LOGIC_unsigned.ALL; + +entity Sra is + + port ( Shift : in Std_Logic ; + LD : in Std_Logic ; + RST : in Std_Logic; + CLK : in Std_Logic ; + A : in Std_Logic_Vector(7 downto 0); + + Done : out Std_Logic ; + LSB : out Std_Logic ); + +end Sra; + + +---------------------------------------------------------------------- + +architecture DataFlow OF Sra is + +signal outsint : Std_Logic_Vector(7 downto 0); +begin +process (CLK) +begin + if CLK'event and CLK='1' then + if RST ='1' then outsint <= (others => '0'); + elsif LD = '1' then outsint <= A ; + elsif Shift= '1' then + outsint(7 downto 0) <= '0' & outsint(7 downto 1); + else outsint <= outsint; + end if; + end if; +end process; + +process( outsint ) + variable RESULT : Std_Logic; +begin + RESULT := '0'; + for j in outsint'range loop + RESULT := outsint(j) or RESULT; + exit when RESULT = '1'; + end loop; + RESULT := not(RESULT); + + Done <= RESULT; +end process; +LSB <= outsint(0); + +end DataFlow; + + +---------------------------------------------------------------------- diff --git a/alliance/src/documentation/alliance-examples/multi8/srb.vhdl b/alliance/src/documentation/alliance-examples/multi8/srb.vhdl new file mode 100644 index 00000000..9f7a4dfe --- /dev/null +++ b/alliance/src/documentation/alliance-examples/multi8/srb.vhdl @@ -0,0 +1,41 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_arith.ALL; +use IEEE.STD_LOGIC_unsigned.ALL; + +entity Srb is + + port ( Shift : in Std_Logic ; + LD : in Std_Logic ; + CLK : in Std_Logic ; + B : in Std_Logic_Vector(7 downto 0); + + OUTS : out Std_Logic_Vector(15 downto 0)); + +end Srb; + + +---------------------------------------------------------------------- + +architecture DataFlow OF Srb is +signal outsint : Std_Logic_Vector(15 downto 0); + +begin +process (CLK) +begin + if CLK'event and CLK='1' then + if LD = '1' then outsint <= + B(7)&B(7)&B(7)&B(7)&B(7)&B(7)&B(7)&B(7)&B ; + elsif Shift= '1' then + outsint(15 downto 0) <= outsint(14 downto 0) & '0'; + else outsint <= outsint; + end if; + end if; +end process; + +OUTS <= outsint; + +end DataFlow; + + +----------------------------------------------------------------------