From bb4fde1c1b9518a35fa2d584d068c1e2e670df42 Mon Sep 17 00:00:00 2001 From: The Syf Tool Date: Fri, 3 Mar 2000 15:07:52 +0000 Subject: [PATCH] Correction du Tutorial pour le nouveau Genlib --- alliance/share/tutorials/addaccu/Makefile | 14 ++--- alliance/share/tutorials/addaccu/addaccu.c | 50 ++++++++-------- alliance/share/tutorials/addaccu/core.c | 66 +++++++++++----------- 3 files changed, 65 insertions(+), 65 deletions(-) diff --git a/alliance/share/tutorials/addaccu/Makefile b/alliance/share/tutorials/addaccu/Makefile index f53572ef..68af2ed6 100644 --- a/alliance/share/tutorials/addaccu/Makefile +++ b/alliance/share/tutorials/addaccu/Makefile @@ -96,7 +96,7 @@ core.ap : core.vst core.al : core.ap MBK_IN_PH=ap ;\ MBK_OUT_LO=al ;\ - RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/cmos_8.rds ;\ + RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/cmos_11.rds ;\ MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/padlib ;\ export MBK_IN_PH MBK_OUT_LO RDS_TECHNO_NAME MBK_CATA_LIB ;\ $(LYNX) -v core core @@ -132,7 +132,7 @@ addaccu.ap : core.ap core.lvx addaccu.vst addaccu.al : addaccu.ap MBK_IN_PH=ap ;\ MBK_OUT_LO=al ;\ - RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/cmos_8.rds ;\ + RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/cmos_11.rds ;\ MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/padlib ;\ export MBK_IN_PH MBK_OUT_LO RDS_TECHNO_NAME MBK_CATA_LIB ;\ $(LYNX) -v addaccu addaccu @@ -165,7 +165,7 @@ addaccue.vbe : addaccu.ap addaccue.inf MBK_IN_PH=ap ;\ MBK_IN_LO=al ;\ MBK_OUT_LO=al ;\ - RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/cmos_8.rds ;\ + RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/cmos_11.rds ;\ MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/padlib ;\ export MBK_IN_PH MBK_IN_LO MBK_OUT_LO RDS_TECHNO_NAME MBK_CATA_LIB ;\ $(LYNX) -v -t addaccu addaccue ;\ @@ -198,7 +198,7 @@ addaccu.proof : addaccue.vbe addaccu.vbe addaccu.drc : addaccu.ap MBK_IN_PH=ap ;\ RDS_OUT=cif ;\ - RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/cmos_8.rds ;\ + RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/cmos_11.rds ;\ MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/padlib ;\ export MBK_IN_PH RDS_OUT RDS_TECHNO_NAME MBK_CATA_LIB ;\ $(DRUC) addaccu @@ -210,7 +210,7 @@ addaccu.drc : addaccu.ap addaccu.cif : addaccu.ap addaccu.drc MBK_IN_PH=ap ;\ MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/padlib ;\ - RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/prol10_8.rds ;\ + RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/prol10_11.rds ;\ RDS_OUT=cif ;\ RDS_IN=cif ;\ export MBK_IN_PH RDS_IN RDS_OUT RDS_TECHNO_NAME MBK_CATA_LIB ;\ @@ -234,7 +234,7 @@ clean: graal : addaccu.ap MBK_IN_PH=ap ;\ - RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/cmos_8.rds ;\ + RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/cmos_11.rds ;\ MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/padlib ;\ export MBK_IN_PH RDS_TECHNO_NAME MBK_CATA_LIB ;\ $(GRAAL) -l addaccu @@ -246,7 +246,7 @@ graal : addaccu.ap dreal : addaccu.cif MBK_IN_PH=ap ;\ MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/padlib ;\ - RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/prol10_8.rds ;\ + RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/prol10_11.rds ;\ RDS_OUT=cif ;\ RDS_IN=cif ;\ export MBK_IN_PH RDS_IN RDS_OUT RDS_TECHNO_NAME MBK_CATA_LIB ;\ diff --git a/alliance/share/tutorials/addaccu/addaccu.c b/alliance/share/tutorials/addaccu/addaccu.c index f6291285..a86b02e0 100644 --- a/alliance/share/tutorials/addaccu/addaccu.c +++ b/alliance/share/tutorials/addaccu/addaccu.c @@ -4,17 +4,17 @@ main() { int i; - DEF_LOFIG("addaccu"); + GENLIB_DEF_LOFIG("addaccu"); - LOCON("a[0:3]", IN, "a[0:3]"); /* input bus a */ - LOCON("b[0:3]", IN, "b[0:3]"); /* input bus b */ - LOCON("sel", IN, "sel" ); /* selection switch */ - LOCON("ck", IN, "ck" ); /* clock */ - LOCON("vdd", IN, "vdd" ); /* core power supply */ - LOCON("vss", IN, "vss" ); /* core ground */ - LOCON("vdde", IN, "vdde" ); /* pads power supply */ - LOCON("vsse", IN, "vsse" ); /* pads ground */ - LOCON("s[0:3]", OUT, "s[0:3]"); /* output */ + GENLIB_LOCON("a[0:3]", IN, "a[0:3]"); /* input bus a */ + GENLIB_LOCON("b[0:3]", IN, "b[0:3]"); /* input bus b */ + GENLIB_LOCON("sel", IN, "sel" ); /* selection switch */ + GENLIB_LOCON("ck", IN, "ck" ); /* clock */ + GENLIB_LOCON("vdd", IN, "vdd" ); /* core power supply */ + GENLIB_LOCON("vss", IN, "vss" ); /* core ground */ + GENLIB_LOCON("vdde", IN, "vdde" ); /* pads power supply */ + GENLIB_LOCON("vsse", IN, "vsse" ); /* pads ground */ + GENLIB_LOCON("s[0:3]", OUT, "s[0:3]"); /* output */ /* power supplies: @@ -23,11 +23,11 @@ int i; pxxxi_p are internal power supplies, for core logic only. */ - LOINS ("pvsse_sp", "p15", "cki", "vdde", "vdd", "vsse", "vss", 0); - LOINS ("pvdde_sp", "p16", "cki", "vdde", "vdd", "vsse", "vss", 0); - LOINS ("pvddeck_sp", "p17", "clock", "cki", "vdde", "vdd", "vsse", "vss", 0); - LOINS ("pvssi_sp", "p18", "cki", "vdde", "vdd", "vsse", "vss", 0); - LOINS ("pvddi_sp", "p19", "cki", "vdde", "vdd", "vsse", "vss", 0); + GENLIB_LOINS ("pvsse_sp", "p15", "cki", "vdde", "vdd", "vsse", "vss", 0); + GENLIB_LOINS ("pvdde_sp", "p16", "cki", "vdde", "vdd", "vsse", "vss", 0); + GENLIB_LOINS ("pvddeck_sp", "p17", "clock", "cki", "vdde", "vdd", "vsse", "vss", 0); + GENLIB_LOINS ("pvssi_sp", "p18", "cki", "vdde", "vdd", "vsse", "vss", 0); + GENLIB_LOINS ("pvddi_sp", "p19", "cki", "vdde", "vdd", "vsse", "vss", 0); /* core to pads connections are point to point connections in the case @@ -36,33 +36,33 @@ int i; errors easilly. */ for (i = 0; i < 4; i++) - LOINS("pi_sp", NAME("p%d", i), - NAME("a[%d]", i), NAME("aa[%d]", i), + GENLIB_LOINS("pi_sp", GENLIB_NAME("p%d", i), + GENLIB_NAME("a[%d]", i), GENLIB_NAME("aa[%d]", i), "cki", "vdde", "vdd", "vsse", "vss", 0); for (i = 0; i < 4; i++) - LOINS("pi_sp", NAME("p%d", i + 4), - NAME("b[%d]", i), NAME("bb[%d]", i), + GENLIB_LOINS("pi_sp", GENLIB_NAME("p%d", i + 4), + GENLIB_NAME("b[%d]", i), GENLIB_NAME("bb[%d]", i), "cki", "vdde", "vdd", "vsse", "vss", 0); for (i = 0; i < 4; i++) - LOINS("po_sp", NAME("p%d", i + 8), - NAME("ss[%d]", i), NAME("s[%d]", i), + GENLIB_LOINS("po_sp", GENLIB_NAME("p%d", i + 8), + GENLIB_NAME("ss[%d]", i), GENLIB_NAME("s[%d]", i), "cki", "vdde", "vdd", "vsse", "vss", 0); - LOINS("pi_sp", "p12", + GENLIB_LOINS("pi_sp", "p12", "sel", "selsel", "cki", "vdde", "vdd", "vsse", "vss", 0); - LOINS("pck_sp", "p13", + GENLIB_LOINS("pck_sp", "p13", "ck", "cki", "vdde", "vdd", "vsse", "vss", 0); - LOINS("core", "core", + GENLIB_LOINS("core", "core", "aa[0:3]", "bb[0:3]", "selsel", "clock", "ss[0:3]", "vdd", "vss", 0); - SAVE_LOFIG(); + GENLIB_SAVE_LOFIG(); exit(0); /* necessary for the proper run of the Makefile */ } diff --git a/alliance/share/tutorials/addaccu/core.c b/alliance/share/tutorials/addaccu/core.c index a478c878..150f453d 100644 --- a/alliance/share/tutorials/addaccu/core.c +++ b/alliance/share/tutorials/addaccu/core.c @@ -19,7 +19,7 @@ int i; /* We will build regular structure using a loop, i is its index */ taken into account. */ - DEF_LOFIG("core"); + GENLIB_DEF_LOFIG("core"); /* The description of the addaccu netlist begins with the @@ -29,27 +29,27 @@ int i; /* We will build regular structure using a loop, i is its index */ /* We start with the input terminals. Note that `a[0:3]' defines a[0], a[1], a[2] and a[3] as if three - calls to `LOCON' had been performed. + calls to `GENLIB_LOCON' had been performed. Only signals and connectors can be vectorized. */ - LOCON("a[0:3]", IN, "a[0:3]"); /* input bus a */ - LOCON("b[0:3]", IN, "b[0:3]"); /* input bus b */ - LOCON("sel", IN, "sel" ); /* selection switch */ - LOCON("ck", IN, "ck" ); /* clock */ + GENLIB_LOCON("a[0:3]", IN, "a[0:3]"); /* input bus a */ + GENLIB_LOCON("b[0:3]", IN, "b[0:3]"); /* input bus b */ + GENLIB_LOCON("sel", IN, "sel" ); /* selection switch */ + GENLIB_LOCON("ck", IN, "ck" ); /* clock */ /* Then, the output terminals. */ - LOCON("s[0:3]", INOUT, "s[0:3]"); /* output bus */ + GENLIB_LOCON("s[0:3]", INOUT, "s[0:3]"); /* output bus */ /* Then the supplies. They are inputs, but we like them better at the end of the description. */ - LOCON("vdd", IN, "vdd" ); /* power supply */ - LOCON("vss", IN, "vss" ); /* ground */ + GENLIB_LOCON("vdd", IN, "vdd" ); /* power supply */ + GENLIB_LOCON("vss", IN, "vss" ); /* ground */ /* Now we describe the circuit's schematic in instanciating @@ -60,11 +60,11 @@ int i; /* We will build regular structure using a loop, i is its index */ /* bit 0 */ - LOINS("xr2_y", "xr0", + GENLIB_LOINS("xr2_y", "xr0", "mux[0]", "b[0]", "s[0]", "vdd", "vss", 0); - LOINS("a2_y", "an0", + GENLIB_LOINS("a2_y", "an0", "mux[0]", "b[0]", "carry[0]", "vdd", "vss", 0); @@ -72,27 +72,27 @@ int i; /* We will build regular structure using a loop, i is its index */ bit 1 */ - LOINS("xr2_y", "xr1", + GENLIB_LOINS("xr2_y", "xr1", "mux[1]", "b[1]", "int[1]", "vdd", "vss", 0); - LOINS("xr2_y", "xr2", + GENLIB_LOINS("xr2_y", "xr2", "int[1]", "carry[0]", "s[1]", "vdd", "vss", 0); - LOINS("a2_y", "an1", + GENLIB_LOINS("a2_y", "an1", "mux[1]", "b[1]", "int[2]", "vdd", "vss", 0); - LOINS("a2_y", "an2", + GENLIB_LOINS("a2_y", "an2", "mux[1]", "carry[0]", "int[3]", "vdd", "vss", 0); - LOINS("a2_y", "an3", + GENLIB_LOINS("a2_y", "an3", "b[1]", "carry[0]", "int[4]", "vdd", "vss", 0); - LOINS("o3_y", "an4", + GENLIB_LOINS("o3_y", "an4", "int[2]", "int[3]", "int[4]", "carry[1]", "vdd", "vss", 0); @@ -100,60 +100,60 @@ int i; /* We will build regular structure using a loop, i is its index */ bit 2 */ - LOINS("xr2_y", "xr3", + GENLIB_LOINS("xr2_y", "xr3", "mux[2]", "b[2]", "int[5]", "vdd", "vss", 0); - LOINS("xr2_y", "xr4", + GENLIB_LOINS("xr2_y", "xr4", "int[5]", "carry[1]", "s[2]", "vdd", "vss", 0); - LOINS("a2_y", "an5", + GENLIB_LOINS("a2_y", "an5", "mux[2]", "b[2]", "int[6]", "vdd", "vss", 0); - LOINS("a2_y", "an6", + GENLIB_LOINS("a2_y", "an6", "mux[2]", "carry[1]", "int[7]", "vdd", "vss", 0); - LOINS("a2_y", "an7", + GENLIB_LOINS("a2_y", "an7", "b[2]", "carry[1]", "int[8]", "vdd", "vss", 0); - LOINS("o3_y", "an8", + GENLIB_LOINS("o3_y", "an8", "int[6]", "int[7]", "int[8]", "carry[2]", "vdd", "vss", 0); /* bit 3 */ - LOINS("xr2_y", "xr5", + GENLIB_LOINS("xr2_y", "xr5", "mux[3]", "b[3]", "int[9]", "vdd", "vss", 0); - LOINS("xr2_y", "xr6", + GENLIB_LOINS("xr2_y", "xr6", "int[9]", "carry[2]", "s[3]", "vdd", "vss", 0); /* mux 2 to 1 */ - LOINS("n1_y", "n10", "sel", "nsel", "vdd", "vss", 0); + GENLIB_LOINS("n1_y", "n10", "sel", "nsel", "vdd", "vss", 0); /* - The `NAME' function allows to indice a name automatically + The `GENLIB_NAME' function allows to indice a name automatically */ for (i = 0; i < 4; i++) { - LOINS("mx2_y", NAME("mux%d", i), - NAME("a[%d]", i), "nsel", NAME("regout[%d]", i), - "sel", NAME("mux[%d]", i), + GENLIB_LOINS("mx2_y", GENLIB_NAME("mux%d", i), + GENLIB_NAME("a[%d]", i), "nsel", GENLIB_NAME("regout[%d]", i), + "sel", GENLIB_NAME("mux[%d]", i), "vdd", "vss", 0); - LOINS("msdp2_y", NAME("l%d", i), - NAME("s[%d]", i), "ck", NAME("regout[%d]", i), + GENLIB_LOINS("msdp2_y", GENLIB_NAME("l%d", i), + GENLIB_NAME("s[%d]", i), "ck", GENLIB_NAME("regout[%d]", i), "vdd", "vss", 0); } - SAVE_LOFIG(); + GENLIB_SAVE_LOFIG(); exit(0); /* necessary for the proper run of the Makefile */ }