From b53f260246865bc4dd8a74905a2346c75bb6f631 Mon Sep 17 00:00:00 2001 From: Jean-Paul Chaput Date: Fri, 25 Feb 2000 10:32:21 +0000 Subject: [PATCH] Ajout du plot de coin "corner_sp" pour faire plaisir a Silicon Ensemble. --- alliance/share/cells/padlib/CATAL | 1 + alliance/share/cells/padlib/corner_sp.ap | 24 ++++++++++++++++++++ alliance/share/cells/padlib/corner_sp.vbe | 27 +++++++++++++++++++++++ 3 files changed, 52 insertions(+) create mode 100644 alliance/share/cells/padlib/corner_sp.ap create mode 100644 alliance/share/cells/padlib/corner_sp.vbe diff --git a/alliance/share/cells/padlib/CATAL b/alliance/share/cells/padlib/CATAL index 51668e8d..34c210f8 100644 --- a/alliance/share/cells/padlib/CATAL +++ b/alliance/share/cells/padlib/CATAL @@ -32,3 +32,4 @@ palvsse_sp C palvsseck_sp C palvssi_sp C palvssick_sp C +corner_sp C diff --git a/alliance/share/cells/padlib/corner_sp.ap b/alliance/share/cells/padlib/corner_sp.ap new file mode 100644 index 00000000..9a7c35ee --- /dev/null +++ b/alliance/share/cells/padlib/corner_sp.ap @@ -0,0 +1,24 @@ +V ALLIANCE : 5 +H corner_sp,P,17/ 2/2000,100 +A 0,0,50000,50000 +C 50000,1300,1200,ck,2,EAST,ALU2 +C 50000,17500,12000,vdde,4,EAST,ALU2 +C 50000,30300,12000,vsse,4,EAST,ALU2 +C 50000,9100,4000,vddi,2,EAST,ALU2 +C 50000,4700,4000,vssi,1,EAST,ALU2 +C 32500,0,12000,vdde,1,SOUTH,ALU2 +C 19700,0,12000,vsse,1,SOUTH,ALU2 +C 40900,0,4000,vddi,0,SOUTH,ALU2 +C 45300,0,4000,vssi,0,SOUTH,ALU2 +C 48700,0,1200,ck,0,SOUTH,ALU2 +S 19700,300,19700,36200,12000,*,UP,ALU2 +S 13800,30300,50000,30300,12000,*,LEFT,ALU2 +S 32500,0,32500,23400,12000,*,UP,ALU2 +S 26600,17500,50000,17500,12000,*,LEFT,ALU2 +S 40900,0,40900,11000,4000,*,UP,ALU2 +S 39000,9100,50000,9100,4000,*,LEFT,ALU2 +S 45300,0,45300,6600,4000,*,UP,ALU2 +S 43400,4700,50000,4700,4000,*,LEFT,ALU2 +S 48700,100,48700,1800,1200,*,UP,ALU2 +S 48200,1300,50000,1300,1200,*,RIGHT,ALU2 +EOF diff --git a/alliance/share/cells/padlib/corner_sp.vbe b/alliance/share/cells/padlib/corner_sp.vbe new file mode 100644 index 00000000..bd9d7ca6 --- /dev/null +++ b/alliance/share/cells/padlib/corner_sp.vbe @@ -0,0 +1,27 @@ +-- VHDL data flow description generated from `corner_sp` +-- date : Thu Feb 23 17:06:23 1995 + + +-- Entity Declaration + +ENTITY corner_sp IS + PORT ( + ck : in BIT; -- ck + vdde : in BIT; -- vdde + vddi : in BIT; -- vddi + vsse : in BIT; -- vsse + vssi : in BIT -- vssi + ); +END corner_sp; + + +-- Architecture Declaration + +ARCHITECTURE behaviour_data_flow OF corner_sp IS + +BEGIN + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on corner_sp" + SEVERITY WARNING; + +END;