diff --git a/alliance/share/cells/dp_sxlib/CATAL b/alliance/share/cells/dp_sxlib/CATAL
deleted file mode 100644
index b3999ee5..00000000
--- a/alliance/share/cells/dp_sxlib/CATAL
+++ /dev/null
@@ -1,24 +0,0 @@
-dp_dff_scan_x4      C
-dp_dff_scan_x4_buf  C
-dp_dff_x4           C
-dp_dff_x4_buf       C
-dp_mux_x2           C
-dp_mux_x2_buf       C
-dp_mux_x4           C
-dp_mux_x4_buf       C
-dp_nmux_x1          C
-dp_nmux_x1_buf      C
-dp_nts_x2           C
-dp_nts_x2_buf       C
-dp_rom2_buf         C
-dp_rom4_buf         C
-dp_rom4_nxr2_x4     C
-dp_rom4_xr2_x4      C
-dp_sff_scan_x4      C
-dp_sff_scan_x4_buf  C
-dp_sff_x4           C
-dp_sff_x4_buf       C
-dp_ts_x4            C
-dp_ts_x4_buf        C
-dp_ts_x8            C
-dp_ts_x8_buf        C
diff --git a/alliance/share/cells/dp_sxlib/dp_dff_scan_x4.ap b/alliance/share/cells/dp_sxlib/dp_dff_scan_x4.ap
deleted file mode 100644
index 27ebd1a4..00000000
--- a/alliance/share/cells/dp_sxlib/dp_dff_scan_x4.ap
+++ /dev/null
@@ -1,234 +0,0 @@
-V ALLIANCE : 6
-H dp_dff_scan_x4,P,14/11/2000,10
-A 0,0,1000,500
-R 600,200,ref_ref,nckx
-R 750,200,ref_ref,ckx
-R 500,200,ref_ref,scanx
-R 400,200,ref_ref,nscanx
-R 250,200,ref_ref,nwenx
-R 150,200,ref_ref,wenx
-R 100,300,ref_ref,i_30
-R 100,250,ref_ref,i_25
-R 100,200,ref_ref,i_20
-R 100,150,ref_ref,i_15
-R 100,100,ref_ref,i_10
-R 100,400,ref_ref,i_40
-R 100,350,ref_ref,i_35
-R 900,350,ref_ref,q_35
-R 900,200,ref_ref,q_20
-R 900,300,ref_ref,q_30
-R 900,400,ref_ref,q_40
-R 900,100,ref_ref,q_10
-R 900,150,ref_ref,q_15
-R 900,250,ref_ref,q_25
-S 150,200,750,200,20,*,RIGHT,TALU2
-S 600,150,640,150,20,*,RIGHT,ALU1
-S 600,300,690,300,10,*,RIGHT,ALU1
-S 600,150,600,300,10,*,DOWN,ALU1
-S 600,200,600,200,20,nckx,LEFT,CALU3
-S 740,250,740,350,10,*,DOWN,ALU1
-S 670,350,670,400,10,*,DOWN,ALU1
-S 670,350,740,350,10,*,RIGHT,ALU1
-S 570,50,570,100,20,*,UP,ALU1
-S 160,400,260,400,10,*,LEFT,ALU1
-S 260,150,260,400,10,*,UP,ALU1
-S 310,150,310,300,10,*,UP,ALU1
-S 0,400,1000,400,260,*,RIGHT,NWELL
-S 220,30,220,110,30,*,DOWN,NDIF
-S 210,100,210,350,10,*,UP,ALU1
-S 330,50,330,100,20,*,DOWN,ALU1
-S 300,90,300,150,10,*,DOWN,POLY
-S 250,90,250,150,10,*,DOWN,POLY
-S 60,90,60,140,10,*,DOWN,POLY
-S 60,140,210,140,10,*,LEFT,POLY
-S 60,290,60,340,10,*,DOWN,POLY
-S 90,100,120,100,30,*,RIGHT,POLY
-S 200,30,200,110,30,*,DOWN,NDIF
-S 330,30,330,120,30,*,DOWN,NDIF
-S 90,30,90,70,30,*,DOWN,NDIF
-S 30,30,30,110,30,*,DOWN,NDIF
-S 60,10,60,90,10,*,DOWN,NTRANS
-S 250,10,250,90,10,*,DOWN,NTRANS
-S 120,10,120,90,10,*,DOWN,NTRANS
-S 170,10,170,90,10,*,DOWN,NTRANS
-S 300,10,300,90,10,*,DOWN,NTRANS
-S 30,200,360,200,10,*,LEFT,POLY
-S 150,250,250,250,10,*,RIGHT,POLY
-S 60,340,60,470,10,*,UP,PTRANS
-S 30,360,30,450,30,*,UP,PDIF
-S 90,360,90,450,30,*,UP,PDIF
-S 170,340,170,470,10,*,UP,PTRANS
-S 120,340,120,470,10,*,UP,PTRANS
-S 960,280,960,470,30,*,DOWN,PDIF
-S 930,260,930,490,10,*,DOWN,PTRANS
-S 810,260,810,490,10,*,DOWN,PTRANS
-S 740,280,740,470,30,*,DOWN,PDIF
-S 830,280,830,470,30,*,DOWN,PDIF
-S 770,260,770,490,10,*,DOWN,PTRANS
-S 900,280,900,470,30,*,DOWN,PDIF
-S 870,260,870,490,10,*,DOWN,PTRANS
-S 330,40,330,120,30,*,DOWN,NDIF
-S 740,30,740,120,30,*,DOWN,NDIF
-S 930,10,930,140,10,*,UP,NTRANS
-S 900,30,900,120,30,*,DOWN,NDIF
-S 840,30,840,120,30,*,DOWN,NDIF
-S 770,10,770,140,10,*,UP,NTRANS
-S 810,10,810,140,10,*,UP,NTRANS
-S 870,10,870,140,10,*,UP,NTRANS
-S 960,30,960,120,30,*,DOWN,NDIF
-S 360,60,360,140,10,*,DOWN,NTRANS
-S 600,60,600,140,10,*,UP,NTRANS
-S 570,40,570,120,30,*,DOWN,NDIF
-S 640,60,640,140,10,*,UP,NTRANS
-S 670,80,670,120,30,*,DOWN,NDIF
-S 450,80,450,120,50,*,UP,NDIF
-S 410,60,410,140,10,*,DOWN,NTRANS
-S 540,60,540,140,10,*,DOWN,NTRANS
-S 490,60,490,140,10,*,DOWN,NTRANS
-S 60,290,210,290,10,*,RIGHT,POLY
-S 90,330,120,330,30,*,RIGHT,POLY
-S 250,250,250,350,10,*,UP,POLY
-S 690,250,770,250,10,*,LEFT,POLY
-S 730,140,770,140,10,*,LEFT,POLY
-S 930,140,930,260,10,*,DOWN,POLY
-S 850,200,930,200,10,*,RIGHT,POLY
-S 810,140,810,260,10,*,DOWN,POLY
-S 770,250,770,260,10,*,DOWN,POLY
-S 870,140,870,260,10,*,DOWN,POLY
-S 410,250,490,250,10,*,RIGHT,POLY
-S 410,140,410,250,10,*,UP,POLY
-S 450,200,600,200,10,*,RIGHT,POLY
-S 30,100,30,400,10,*,DOWN,ALU1
-S 160,330,160,400,10,*,DOWN,ALU1
-S 670,100,690,100,20,*,RIGHT,ALU1
-S 740,400,790,400,10,*,RIGHT,ALU1
-S 960,300,960,450,20,*,DOWN,ALU1
-S 960,50,960,100,20,*,DOWN,ALU1
-S 450,100,450,350,10,*,UP,ALU1
-S 500,150,500,400,10,*,UP,ALU1
-S 400,400,500,400,10,*,LEFT,ALU1
-S 790,250,790,400,10,*,DOWN,ALU1
-S 690,250,740,250,10,*,RIGHT,ALU1
-S 690,100,690,250,10,*,DOWN,ALU1
-S 640,200,730,200,10,*,RIGHT,POLY
-S 730,140,730,200,10,*,DOWN,POLY
-S 690,250,690,300,10,*,UP,POLY
-S 690,150,800,150,10,*,RIGHT,ALU1
-S 800,150,800,190,10,*,UP,ALU1
-S 850,100,850,250,10,*,DOWN,ALU1
-S 740,100,850,100,10,*,LEFT,ALU1
-S 790,250,850,250,10,*,RIGHT,ALU1
-S 840,300,840,450,20,*,DOWN,ALU1
-S 150,100,150,250,10,*,UP,ALU1
-S 410,310,410,440,10,*,UP,PTRANS
-S 490,310,490,440,10,*,UP,PTRANS
-S 540,310,540,440,10,*,UP,PTRANS
-S 450,330,450,420,50,*,UP,PDIF
-S 360,310,360,440,10,*,UP,PTRANS
-S 300,310,300,440,10,*,UP,PTRANS
-S 330,330,330,420,30,*,UP,PDIF
-S 330,350,330,450,20,*,DOWN,ALU1
-S 330,360,330,420,30,*,UP,PDIF
-S 250,310,250,440,10,*,UP,PTRANS
-S 360,140,360,310,10,*,DOWN,POLY
-S 490,250,490,310,10,*,DOWN,POLY
-S 210,330,210,450,50,*,UP,PDIF
-S 570,350,570,450,20,*,DOWN,ALU1
-S 640,360,640,490,10,*,DOWN,PTRANS
-S 600,360,600,490,10,*,DOWN,PTRANS
-S 570,330,570,470,30,*,UP,PDIF
-S 670,380,670,470,30,*,DOWN,PDIF
-S 600,90,600,360,10,*,DOWN,POLY
-S 640,200,640,360,10,*,DOWN,POLY
-S 400,300,400,400,10,*,DOWN,ALU1
-S 100,100,100,400,20,i,UP,CALU1
-S 900,100,900,400,20,q,DOWN,CALU1
-S 0,30,1000,30,60,vss,RIGHT,CALU1
-S 0,470,1000,470,60,vdd,RIGHT,CALU1
-S 550,150,550,300,10,scin,UP,CALU1
-S 150,200,150,200,20,wenx,LEFT,CALU3
-S 250,200,250,200,20,nwenx,LEFT,CALU3
-S 400,200,400,200,20,nscanx,LEFT,CALU3
-S 500,200,500,200,20,scanx,LEFT,CALU3
-S 750,200,750,200,20,ckx,LEFT,CALU3
-S 300,250,900,250,20,q,RIGHT,CALU2
-V 600,200,CONT_VIA,*
-V 600,200,CONT_VIA2,*
-V 150,200,CONT_VIA,*
-V 150,200,CONT_VIA2,*
-V 670,30,CONT_BODY_P,*
-V 570,100,CONT_DIF_N,*
-V 570,400,CONT_DIF_P,*
-V 330,400,CONT_DIF_P,*
-V 260,150,CONT_POLY,*
-V 310,150,CONT_POLY,*
-V 310,300,CONT_POLY,*
-V 310,250,CONT_VIA,*
-V 210,100,CONT_DIF_N,*
-V 210,150,CONT_POLY,*
-V 210,350,CONT_DIF_P,*
-V 330,100,CONT_DIF_N,*
-V 160,100,CONT_POLY,*
-V 100,100,CONT_POLY,*
-V 30,200,CONT_POLY,*
-V 150,250,CONT_POLY,*
-V 90,450,CONT_DIF_P,*
-V 30,400,CONT_DIF_P,*
-V 840,350,CONT_DIF_P,*
-V 960,300,CONT_DIF_P,*
-V 960,450,CONT_DIF_P,*
-V 840,450,CONT_DIF_P,*
-V 840,400,CONT_DIF_P,*
-V 900,300,CONT_DIF_P,*
-V 960,400,CONT_DIF_P,*
-V 960,350,CONT_DIF_P,*
-V 740,400,CONT_DIF_P,*
-V 570,450,CONT_DIF_P,*
-V 450,350,CONT_DIF_P,*
-V 90,50,CONT_DIF_N,*
-V 30,100,CONT_DIF_N,*
-V 330,50,CONT_DIF_N,*
-V 960,100,CONT_DIF_N,*
-V 960,50,CONT_DIF_N,*
-V 840,50,CONT_DIF_N,*
-V 900,100,CONT_DIF_N,*
-V 740,100,CONT_DIF_N,*
-V 570,50,CONT_DIF_N,*
-V 450,100,CONT_DIF_N,*
-V 330,50,CONT_DIF_N,*
-V 670,100,CONT_DIF_N,*
-V 510,30,CONT_BODY_P,*
-V 390,30,CONT_BODY_P,*
-V 450,30,CONT_BODY_P,*
-V 210,300,CONT_POLY,*
-V 100,330,CONT_POLY,*
-V 160,330,CONT_POLY,*
-V 550,300,CONT_POLY,*
-V 550,150,CONT_POLY,*
-V 500,150,CONT_POLY,*
-V 850,200,CONT_POLY,*
-V 640,150,CONT_POLY,*
-V 450,200,CONT_POLY,*
-V 900,250,CONT_VIA,*
-V 800,200,CONT_POLY,*
-V 690,300,CONT_POLY,*
-V 750,200,CONT_VIA2,*
-V 750,200,CONT_VIA,*
-V 740,200,CONT_POLY,*
-V 840,300,CONT_DIF_P,*
-V 400,200,CONT_VIA2,*
-V 400,200,CONT_VIA,*
-V 400,200,CONT_POLY,*
-V 500,200,CONT_VIA2,*
-V 500,200,CONT_VIA,*
-V 250,200,CONT_VIA2,*
-V 260,200,CONT_VIA,*
-V 400,300,CONT_POLY,*
-V 450,470,CONT_BODY_N,*
-V 510,470,CONT_BODY_N,*
-V 390,470,CONT_BODY_N,*
-V 330,350,CONT_DIF_P,*
-V 330,470,CONT_BODY_N,*
-V 570,350,CONT_DIF_P,*
-V 670,400,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/dp_sxlib/dp_dff_scan_x4.vbe b/alliance/share/cells/dp_sxlib/dp_dff_scan_x4.vbe
deleted file mode 100644
index 3b5ea227..00000000
--- a/alliance/share/cells/dp_sxlib/dp_dff_scan_x4.vbe
+++ /dev/null
@@ -1,43 +0,0 @@
-ENTITY dp_dff_scan_x4 IS
-PORT (
-  ckx		: in  BIT;
-  nckx		: in  BIT;
-  wenx		: in  BIT;
-  nwenx		: in  BIT;
-  scanx		: in  BIT;
-  nscanx	: in  BIT;
-  i   		: in  BIT;
-  scin		: in  BIT;
-  q			: out BIT;
-  vdd		: in  BIT;
-  vss		: in  BIT
-);
-END dp_dff_scan_x4;
-
-ARCHITECTURE vbe OF dp_dff_scan_x4 IS
-  SIGNAL ff : REG_BIT REGISTER;
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on dp_dff_scan_x4"
-  SEVERITY WARNING;
-
-  ASSERT (ckx xor nckx)
-  REPORT "wrong values for ckx and nckx in dp_dff_scan_x4"
-  SEVERITY WARNING;
-
-  ASSERT (wenx xor nwenx)
-  REPORT "wrong values for wenx and nwenx in dp_dff_scan_x4"
-  SEVERITY WARNING;
-
-  ASSERT (scanx xor nscanx)
-  REPORT "wrong values for scanx and nscanx in dp_dff_scan_x4"
-  SEVERITY WARNING;
-
-  label0 : BLOCK ((ckx and not (ckx'STABLE)) = '1')
-  BEGIN
-    ff <= GUARDED ((scanx and scin) or (nscanx and ((wenx and i) or (nwenx and ff))));
-  END BLOCK label0;
-
-  q <= ff;
-END;
diff --git a/alliance/share/cells/dp_sxlib/dp_dff_scan_x4_buf.ap b/alliance/share/cells/dp_sxlib/dp_dff_scan_x4_buf.ap
deleted file mode 100644
index 096dd820..00000000
--- a/alliance/share/cells/dp_sxlib/dp_dff_scan_x4_buf.ap
+++ /dev/null
@@ -1,392 +0,0 @@
-V ALLIANCE : 6
-H dp_dff_scan_x4_buf,P,14/11/2000,10
-A 0,0,1000,1000
-R 650,400,ref_ref,nckx
-R 750,400,ref_ref,ckx
-R 500,400,ref_ref,scanx
-R 400,400,ref_ref,nscanx
-R 250,400,ref_ref,nwenx
-R 150,400,ref_ref,wenx
-R 950,700,ref_ref,scin
-R 900,300,ref_ref,scout
-R 900,250,ref_ref,scout
-R 900,200,ref_ref,scout
-R 900,150,ref_ref,scout
-R 900,100,ref_ref,scout
-R 900,350,ref_ref,scout
-R 900,400,ref_ref,scout
-S 150,150,750,150,20,*,RIGHT,TALU2
-S 150,400,750,400,20,*,LEFT,TALU2
-S 150,600,750,600,20,*,RIGHT,TALU2
-S 650,150,650,600,20,nckx,DOWN,CALU3
-S 500,150,500,600,20,scanx,DOWN,CALU3
-S 400,150,400,600,20,nscanx,DOWN,CALU3
-S 250,150,250,600,20,nwenx,DOWN,CALU3
-S 150,150,150,600,20,wenx,DOWN,CALU3
-S 200,850,200,850,10,wen,LEFT,CALU1
-S 450,850,450,850,10,scan,LEFT,CALU1
-S 700,850,700,850,10,ck,LEFT,CALU1
-S 900,100,900,400,20,scout,UP,CALU1
-S 0,470,1000,470,60,vdd,RIGHT,CALU1
-S 0,530,1000,530,60,vdd,RIGHT,CALU1
-S 0,30,1000,30,60,vss,RIGHT,CALU1
-S 0,970,1000,970,60,vss,RIGHT,CALU1
-S 950,700,950,700,10,scin,LEFT,CALU1
-S 140,220,210,220,20,*,RIGHT,ALU1
-S 210,220,290,220,30,*,RIGHT,POLY
-S 110,220,170,220,30,*,RIGHT,POLY
-S 260,740,260,790,20,*,DOWN,ALU1
-S 140,660,140,900,20,*,UP,ALU1
-S 110,660,170,660,30,*,RIGHT,POLY
-S 320,900,320,970,20,*,UP,ALU1
-S 320,50,320,150,20,*,UP,ALU1
-S 80,900,80,970,20,*,DOWN,ALU1
-S 200,50,200,150,20,*,UP,ALU1
-S 80,50,80,150,20,*,UP,ALU1
-S 320,280,320,680,20,*,UP,ALU1
-S 200,900,200,940,20,*,UP,ALU1
-S 140,790,260,790,20,*,RIGHT,ALU1
-S 570,280,570,680,20,*,UP,ALU1
-S 450,50,450,150,20,*,UP,ALU1
-S 570,50,570,150,20,*,UP,ALU1
-S 820,50,820,150,20,*,UP,ALU1
-S 700,50,700,150,20,*,UP,ALU1
-S 390,790,510,790,20,*,RIGHT,ALU1
-S 450,900,450,940,20,*,UP,ALU1
-S 570,900,570,970,20,*,UP,ALU1
-S 700,900,700,940,20,*,UP,ALU1
-S 640,790,760,790,20,*,RIGHT,ALU1
-S 170,190,170,320,10,*,UP,POLY
-S 290,190,290,320,10,*,UP,POLY
-S 230,190,230,320,10,*,DOWN,POLY
-S 170,850,230,850,30,*,RIGHT,POLY
-S 230,820,230,860,10,*,DOWN,POLY
-S 170,820,170,870,10,*,DOWN,POLY
-S 110,190,110,320,10,*,DOWN,POLY
-S 360,190,360,320,10,*,DOWN,POLY
-S 480,190,480,320,10,*,DOWN,POLY
-S 540,190,540,320,10,*,UP,POLY
-S 420,190,420,320,10,*,UP,POLY
-S 790,190,790,320,10,*,UP,POLY
-S 730,190,730,320,10,*,DOWN,POLY
-S 610,190,610,320,10,*,DOWN,POLY
-S 670,190,670,320,10,*,UP,POLY
-S 420,820,420,870,10,*,DOWN,POLY
-S 480,820,480,860,10,*,DOWN,POLY
-S 420,850,480,850,30,*,RIGHT,POLY
-S 670,850,730,850,30,*,RIGHT,POLY
-S 730,820,730,860,10,*,DOWN,POLY
-S 670,820,670,870,10,*,DOWN,POLY
-S 140,30,140,170,30,*,UP,NDIF
-S 200,30,200,170,30,*,UP,NDIF
-S 110,10,110,190,10,*,UP,NTRANS
-S 170,10,170,190,10,*,DOWN,NTRANS
-S 320,30,320,170,30,*,UP,NDIF
-S 80,30,80,170,30,*,UP,NDIF
-S 290,10,290,190,10,*,DOWN,NTRANS
-S 260,30,260,170,30,*,UP,NDIF
-S 230,10,230,190,10,*,DOWN,NTRANS
-S 140,890,140,960,30,*,UP,NDIF
-S 200,890,200,960,30,*,UP,NDIF
-S 170,870,170,980,10,*,UP,NTRANS
-S 570,30,570,170,30,*,UP,NDIF
-S 420,10,420,190,10,*,DOWN,NTRANS
-S 360,10,360,190,10,*,UP,NTRANS
-S 450,30,450,170,30,*,UP,NDIF
-S 390,30,390,170,30,*,UP,NDIF
-S 480,10,480,190,10,*,DOWN,NTRANS
-S 510,30,510,170,30,*,UP,NDIF
-S 540,10,540,190,10,*,DOWN,NTRANS
-S 820,30,820,170,30,*,UP,NDIF
-S 640,30,640,170,30,*,UP,NDIF
-S 700,30,700,170,30,*,UP,NDIF
-S 610,10,610,190,10,*,UP,NTRANS
-S 670,10,670,190,10,*,DOWN,NTRANS
-S 790,10,790,190,10,*,DOWN,NTRANS
-S 760,30,760,170,30,*,UP,NDIF
-S 730,10,730,190,10,*,DOWN,NTRANS
-S 450,890,450,960,30,*,UP,NDIF
-S 390,890,390,960,30,*,UP,NDIF
-S 640,890,640,960,30,*,UP,NDIF
-S 700,890,700,960,30,*,UP,NDIF
-S 420,870,420,980,10,*,UP,NTRANS
-S 670,870,670,980,10,*,UP,NTRANS
-S 260,730,260,800,30,*,UP,PDIF
-S 80,340,80,630,30,*,UP,PDIF
-S 110,320,110,650,10,*,UP,PTRANS
-S 200,340,200,630,30,*,UP,PDIF
-S 140,340,140,630,30,*,UP,PDIF
-S 170,320,170,650,10,*,UP,PTRANS
-S 320,340,320,630,30,*,DOWN,PDIF
-S 290,320,290,650,10,*,DOWN,PTRANS
-S 260,340,260,630,30,*,UP,PDIF
-S 230,320,230,650,10,*,UP,PTRANS
-S 140,730,140,800,30,*,UP,PDIF
-S 170,710,170,820,10,*,DOWN,PTRANS
-S 210,730,210,800,30,*,UP,PDIF
-S 230,710,230,820,10,*,DOWN,PTRANS
-S 570,340,570,630,30,*,DOWN,PDIF
-S 420,320,420,650,10,*,UP,PTRANS
-S 390,340,390,630,30,*,UP,PDIF
-S 450,340,450,630,30,*,UP,PDIF
-S 360,320,360,650,10,*,UP,PTRANS
-S 0,500,1000,500,460,*,RIGHT,NWELL
-S 480,320,480,650,10,*,UP,PTRANS
-S 510,340,510,630,30,*,UP,PDIF
-S 540,320,540,650,10,*,DOWN,PTRANS
-S 700,340,700,630,30,*,UP,PDIF
-S 640,340,640,630,30,*,UP,PDIF
-S 670,320,670,650,10,*,UP,PTRANS
-S 820,340,820,630,30,*,DOWN,PDIF
-S 610,320,610,650,10,*,UP,PTRANS
-S 790,320,790,650,10,*,DOWN,PTRANS
-S 760,340,760,630,30,*,UP,PDIF
-S 730,320,730,650,10,*,UP,PTRANS
-S 390,730,390,800,30,*,UP,PDIF
-S 510,730,510,800,30,*,UP,PDIF
-S 640,730,640,800,30,*,UP,PDIF
-S 480,710,480,820,10,*,DOWN,PTRANS
-S 460,730,460,800,30,*,UP,PDIF
-S 420,710,420,820,10,*,DOWN,PTRANS
-S 710,730,710,800,30,*,UP,PDIF
-S 730,710,730,820,10,*,DOWN,PTRANS
-S 760,730,760,800,30,*,UP,PDIF
-S 670,710,670,820,10,*,DOWN,PTRANS
-S 510,660,510,790,20,*,DOWN,ALU1
-S 760,660,760,790,20,*,DOWN,ALU1
-S 640,740,640,900,20,*,UP,ALU1
-S 390,740,390,900,20,*,UP,ALU1
-S 480,660,540,660,30,*,RIGHT,POLY
-S 730,660,790,660,30,*,RIGHT,POLY
-S 110,770,830,770,80,*,RIGHT,NWELL
-S 440,220,510,220,20,*,RIGHT,ALU1
-S 690,220,760,220,20,*,RIGHT,ALU1
-S 360,220,440,220,30,*,RIGHT,POLY
-S 480,220,540,220,30,*,RIGHT,POLY
-S 610,220,690,220,30,*,RIGHT,POLY
-S 730,220,790,220,30,*,RIGHT,POLY
-S 80,290,80,680,20,*,UP,ALU1
-S 510,100,510,400,20,*,UP,ALU1
-S 390,100,390,400,20,*,UP,ALU1
-S 140,100,140,400,20,*,UP,ALU1
-S 260,100,260,400,20,*,UP,ALU1
-S 640,100,640,400,20,*,UP,ALU1
-S 760,100,760,400,20,*,UP,ALU1
-S 700,280,700,740,20,*,DOWN,ALU1
-S 450,290,450,740,20,*,UP,ALU1
-S 200,290,200,740,20,*,DOWN,ALU1
-S 850,820,850,870,10,*,DOWN,POLY
-S 820,890,820,960,30,*,UP,NDIF
-S 850,710,850,820,10,*,DOWN,PTRANS
-S 820,730,820,800,30,*,UP,PDIF
-S 820,900,820,950,20,*,UP,ALU1
-S 820,280,820,790,20,*,UP,ALU1
-S 880,730,880,800,30,*,UP,PDIF
-S 880,660,880,900,20,*,DOWN,ALU1
-S 850,710,950,710,10,*,RIGHT,POLY
-S 850,870,850,940,10,*,UP,NTRANS
-S 880,890,880,920,30,*,UP,NDIF
-S 870,190,870,320,10,*,DOWN,POLY
-S 870,320,870,650,10,*,UP,PTRANS
-S 900,30,900,170,30,*,UP,NDIF
-S 870,10,870,190,10,*,DOWN,NTRANS
-S 900,340,900,630,30,*,UP,PDIF
-S 840,30,840,170,30,*,UP,NDIF
-S 840,340,840,630,30,*,DOWN,PDIF
-S 750,150,750,600,20,ckx,DOWN,CALU3
-V 950,700,CONT_POLY,*
-V 210,220,CONT_POLY,*
-V 140,660,CONT_POLY,*
-V 150,400,CONT_VIA2,*
-V 150,600,CONT_VIA2,*
-V 250,600,CONT_VIA2,*
-V 150,150,CONT_VIA2,*
-V 250,400,CONT_VIA2,*
-V 500,400,CONT_VIA2,*
-V 400,150,CONT_VIA2,*
-V 500,600,CONT_VIA2,*
-V 400,600,CONT_VIA2,*
-V 400,400,CONT_VIA2,*
-V 750,600,CONT_VIA2,*
-V 650,150,CONT_VIA2,*
-V 750,400,CONT_VIA2,*
-V 650,400,CONT_VIA2,*
-V 650,600,CONT_VIA2,*
-V 150,150,CONT_VIA,*
-V 150,400,CONT_VIA,*
-V 150,600,CONT_VIA,*
-V 250,600,CONT_VIA,*
-V 250,400,CONT_VIA,*
-V 400,150,CONT_VIA,*
-V 500,400,CONT_VIA,*
-V 500,600,CONT_VIA,*
-V 400,600,CONT_VIA,*
-V 400,400,CONT_VIA,*
-V 650,150,CONT_VIA,*
-V 650,600,CONT_VIA,*
-V 750,600,CONT_VIA,*
-V 750,400,CONT_VIA,*
-V 650,400,CONT_VIA,*
-V 200,850,CONT_POLY,*
-V 450,850,CONT_POLY,*
-V 700,850,CONT_POLY,*
-V 570,970,CONT_BODY_P,*
-V 320,970,CONT_BODY_P,*
-V 80,970,CONT_BODY_P,*
-V 320,900,CONT_BODY_P,*
-V 80,900,CONT_BODY_P,*
-V 570,900,CONT_BODY_P,*
-V 320,100,CONT_DIF_N,*
-V 260,100,CONT_DIF_N,*
-V 320,50,CONT_DIF_N,*
-V 320,150,CONT_DIF_N,*
-V 260,150,CONT_DIF_N,*
-V 80,50,CONT_DIF_N,*
-V 80,150,CONT_DIF_N,*
-V 80,100,CONT_DIF_N,*
-V 200,100,CONT_DIF_N,*
-V 200,50,CONT_DIF_N,*
-V 200,150,CONT_DIF_N,*
-V 140,900,CONT_DIF_N,*
-V 140,150,CONT_DIF_N,*
-V 140,100,CONT_DIF_N,*
-V 200,900,CONT_DIF_N,*
-V 200,950,CONT_DIF_N,*
-V 570,50,CONT_DIF_N,*
-V 510,100,CONT_DIF_N,*
-V 570,100,CONT_DIF_N,*
-V 390,100,CONT_DIF_N,*
-V 390,150,CONT_DIF_N,*
-V 450,150,CONT_DIF_N,*
-V 450,50,CONT_DIF_N,*
-V 450,100,CONT_DIF_N,*
-V 510,150,CONT_DIF_N,*
-V 570,150,CONT_DIF_N,*
-V 760,100,CONT_DIF_N,*
-V 820,50,CONT_DIF_N,*
-V 640,150,CONT_DIF_N,*
-V 640,100,CONT_DIF_N,*
-V 820,100,CONT_DIF_N,*
-V 820,150,CONT_DIF_N,*
-V 760,150,CONT_DIF_N,*
-V 700,100,CONT_DIF_N,*
-V 700,50,CONT_DIF_N,*
-V 700,150,CONT_DIF_N,*
-V 700,900,CONT_DIF_N,*
-V 700,950,CONT_DIF_N,*
-V 450,950,CONT_DIF_N,*
-V 450,900,CONT_DIF_N,*
-V 390,900,CONT_DIF_N,*
-V 640,900,CONT_DIF_N,*
-V 140,790,CONT_DIF_P,*
-V 200,740,CONT_DIF_P,*
-V 140,740,CONT_DIF_P,*
-V 200,290,CONT_BODY_N,*
-V 80,290,CONT_BODY_N,*
-V 320,290,CONT_BODY_N,*
-V 80,600,CONT_DIF_P,*
-V 80,350,CONT_DIF_P,*
-V 80,550,CONT_DIF_P,*
-V 80,500,CONT_DIF_P,*
-V 80,450,CONT_DIF_P,*
-V 80,400,CONT_DIF_P,*
-V 200,350,CONT_DIF_P,*
-V 200,450,CONT_DIF_P,*
-V 200,550,CONT_DIF_P,*
-V 200,400,CONT_DIF_P,*
-V 200,500,CONT_DIF_P,*
-V 320,400,CONT_DIF_P,*
-V 320,350,CONT_DIF_P,*
-V 320,450,CONT_DIF_P,*
-V 320,500,CONT_DIF_P,*
-V 320,550,CONT_DIF_P,*
-V 320,600,CONT_DIF_P,*
-V 260,400,CONT_DIF_P,*
-V 260,350,CONT_DIF_P,*
-V 140,350,CONT_DIF_P,*
-V 140,400,CONT_DIF_P,*
-V 140,600,CONT_DIF_P,*
-V 260,600,CONT_DIF_P,*
-V 260,790,CONT_DIF_P,*
-V 260,740,CONT_DIF_P,*
-V 200,680,CONT_BODY_N,*
-V 320,680,CONT_BODY_N,*
-V 80,680,CONT_BODY_N,*
-V 450,550,CONT_DIF_P,*
-V 450,450,CONT_DIF_P,*
-V 450,350,CONT_DIF_P,*
-V 570,290,CONT_BODY_N,*
-V 450,290,CONT_BODY_N,*
-V 570,600,CONT_DIF_P,*
-V 570,550,CONT_DIF_P,*
-V 570,500,CONT_DIF_P,*
-V 570,450,CONT_DIF_P,*
-V 570,350,CONT_DIF_P,*
-V 570,400,CONT_DIF_P,*
-V 450,500,CONT_DIF_P,*
-V 450,400,CONT_DIF_P,*
-V 570,680,CONT_BODY_N,*
-V 450,680,CONT_BODY_N,*
-V 510,600,CONT_DIF_P,*
-V 390,600,CONT_DIF_P,*
-V 390,400,CONT_DIF_P,*
-V 390,350,CONT_DIF_P,*
-V 510,350,CONT_DIF_P,*
-V 510,400,CONT_DIF_P,*
-V 700,350,CONT_DIF_P,*
-V 700,450,CONT_DIF_P,*
-V 700,550,CONT_DIF_P,*
-V 820,500,CONT_DIF_P,*
-V 820,550,CONT_DIF_P,*
-V 820,600,CONT_DIF_P,*
-V 700,290,CONT_BODY_N,*
-V 820,290,CONT_BODY_N,*
-V 760,600,CONT_DIF_P,*
-V 700,680,CONT_BODY_N,*
-V 820,680,CONT_BODY_N,*
-V 700,400,CONT_DIF_P,*
-V 700,500,CONT_DIF_P,*
-V 820,400,CONT_DIF_P,*
-V 820,350,CONT_DIF_P,*
-V 820,450,CONT_DIF_P,*
-V 390,790,CONT_DIF_P,*
-V 760,400,CONT_DIF_P,*
-V 760,350,CONT_DIF_P,*
-V 640,350,CONT_DIF_P,*
-V 640,400,CONT_DIF_P,*
-V 640,600,CONT_DIF_P,*
-V 510,740,CONT_DIF_P,*
-V 510,790,CONT_DIF_P,*
-V 390,740,CONT_DIF_P,*
-V 450,740,CONT_DIF_P,*
-V 700,740,CONT_DIF_P,*
-V 640,740,CONT_DIF_P,*
-V 760,790,CONT_DIF_P,*
-V 760,740,CONT_DIF_P,*
-V 640,790,CONT_DIF_P,*
-V 510,660,CONT_POLY,*
-V 760,660,CONT_POLY,*
-V 700,600,CONT_DIF_P,*
-V 450,600,CONT_DIF_P,*
-V 200,600,CONT_DIF_P,*
-V 440,220,CONT_POLY,*
-V 690,220,CONT_POLY,*
-V 750,150,CONT_VIA2,*
-V 750,150,CONT_VIA,*
-V 500,150,CONT_VIA2,*
-V 500,150,CONT_VIA,*
-V 250,150,CONT_VIA2,*
-V 250,150,CONT_VIA,*
-V 880,900,CONT_DIF_N,*
-V 820,900,CONT_DIF_N,*
-V 820,790,CONT_DIF_P,*
-V 880,740,CONT_DIF_P,*
-V 820,740,CONT_DIF_P,*
-V 820,950,CONT_DIF_N,*
-V 880,660,CONT_POLY,*
-V 880,790,CONT_DIF_P,*
-V 900,150,CONT_DIF_N,*
-V 900,100,CONT_DIF_N,*
-V 900,400,CONT_DIF_P,*
-V 900,350,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/dp_sxlib/dp_dff_scan_x4_buf.vbe b/alliance/share/cells/dp_sxlib/dp_dff_scan_x4_buf.vbe
deleted file mode 100644
index 4c54ffef..00000000
--- a/alliance/share/cells/dp_sxlib/dp_dff_scan_x4_buf.vbe
+++ /dev/null
@@ -1,33 +0,0 @@
-ENTITY dp_dff_scan_x4_buf IS
-PORT (
-  ck		: in  BIT;
-  wen		: in  BIT;
-  scan		: in  BIT;
-  scin		: in  BIT;
-  ckx		: out BIT;
-  nckx		: out BIT;
-  wenx		: out BIT;
-  nwenx		: out BIT;
-  scanx		: out BIT;
-  nscanx	: out BIT;
-  scout 	: out BIT;
-  vdd		: in  BIT;
-  vss		: in  BIT
-);
-END dp_dff_scan_x4_buf;
-
-ARCHITECTURE vbe OF dp_dff_scan_x4_buf IS
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on dp_dff_scan_x4_buf"
-  SEVERITY WARNING;
-
-  ckx <= ck;
-  nckx <= not ck;
-  wenx <= wen;
-  nwenx <= not wen;
-  scanx <= scan;
-  nscanx <= not scan;
-  scout <= scin;
-END;
diff --git a/alliance/share/cells/dp_sxlib/dp_dff_x4.ap b/alliance/share/cells/dp_sxlib/dp_dff_x4.ap
deleted file mode 100644
index bb6f7200..00000000
--- a/alliance/share/cells/dp_sxlib/dp_dff_x4.ap
+++ /dev/null
@@ -1,170 +0,0 @@
-V ALLIANCE : 6
-H dp_dff_x4,P,26/ 9/2000,100
-A 0,0,7000,5000
-R 3000,2000,ref_ref,nckx
-R 500,4000,ref_ref,i_40
-R 500,1000,ref_ref,i_10
-R 500,1500,ref_ref,i_15
-R 500,2000,ref_ref,i_20
-R 500,3500,ref_ref,i_35
-R 500,3000,ref_ref,i_30
-R 6000,1500,ref_ref,q_15
-R 6000,1000,ref_ref,q_10
-R 6000,4000,ref_ref,q_40
-R 6000,3000,ref_ref,q_30
-R 6000,2000,ref_ref,q_20
-R 6000,3500,ref_ref,q_35
-R 500,2500,ref_ref,i_25
-R 6000,2500,ref_ref,q_25
-R 1000,2000,ref_ref,wenx
-R 2000,2000,ref_ref,nwenx
-R 4500,2000,ref_ref,ckx
-S 3000,1500,3400,1500,200,*,RIGHT,ALU1
-S 3000,3000,3900,3000,200,*,RIGHT,ALU1
-S 3000,1500,3000,3000,100,*,DOWN,ALU1
-S 3000,2000,3000,2000,200,nckx,LEFT,CALU3
-S 4400,2500,4400,3500,100,*,DOWN,ALU1
-S 3700,3500,3700,4000,100,*,DOWN,ALU1
-S 3700,3500,4400,3500,100,*,RIGHT,ALU1
-S 300,3300,300,4600,300,*,UP,PDIF
-S 5100,2600,5100,4900,100,*,DOWN,PTRANS
-S 6300,2600,6300,4900,100,*,DOWN,PTRANS
-S 6600,2800,6600,4700,300,*,DOWN,PDIF
-S 0,4000,7000,4000,2600,*,RIGHT,NWELL
-S 2400,3100,2400,4400,100,*,UP,PTRANS
-S 1900,3100,1900,4400,100,*,UP,PTRANS
-S 1100,3100,1100,4400,100,*,UP,PTRANS
-S 5700,2600,5700,4900,100,*,DOWN,PTRANS
-S 6000,2800,6000,4700,300,*,DOWN,PDIF
-S 4700,2600,4700,4900,100,*,DOWN,PTRANS
-S 5300,2800,5300,4700,300,*,DOWN,PDIF
-S 4400,2800,4400,4700,300,*,DOWN,PDIF
-S 3700,3800,3700,4700,300,*,DOWN,PDIF
-S 2700,3300,2700,4700,300,*,UP,PDIF
-S 3000,3600,3000,4900,100,*,DOWN,PTRANS
-S 3400,3600,3400,4900,100,*,DOWN,PTRANS
-S 600,3100,600,4400,100,*,UP,PTRANS
-S 1500,3300,1500,4200,500,*,UP,PDIF
-S 4700,100,4700,1400,100,*,UP,NTRANS
-S 6300,100,6300,1400,100,*,UP,NTRANS
-S 1900,600,1900,1400,100,*,DOWN,NTRANS
-S 2400,600,2400,1400,100,*,DOWN,NTRANS
-S 1100,600,1100,1400,100,*,DOWN,NTRANS
-S 3400,600,3400,1400,100,*,UP,NTRANS
-S 3000,600,3000,1400,100,*,UP,NTRANS
-S 600,600,600,1400,100,*,DOWN,NTRANS
-S 5700,100,5700,1400,100,*,UP,NTRANS
-S 5100,100,5100,1400,100,*,UP,NTRANS
-S 4400,300,4400,1200,300,*,DOWN,NDIF
-S 300,400,300,1200,300,*,DOWN,NDIF
-S 300,300,300,1200,300,*,DOWN,NDIF
-S 5400,300,5400,1200,300,*,DOWN,NDIF
-S 6000,300,6000,1200,300,*,DOWN,NDIF
-S 2700,400,2700,1200,300,*,DOWN,NDIF
-S 6600,300,6600,1200,300,*,DOWN,NDIF
-S 1500,800,1500,1200,500,*,UP,NDIF
-S 3700,800,3700,1200,300,*,DOWN,NDIF
-S 5700,1400,5700,2600,100,*,DOWN,POLY
-S 4700,2500,4700,2600,100,*,DOWN,POLY
-S 5100,1400,5100,2600,100,*,DOWN,POLY
-S 5500,2000,6300,2000,100,*,RIGHT,POLY
-S 6300,1400,6300,2600,100,*,DOWN,POLY
-S 4300,1400,4700,1400,100,*,LEFT,POLY
-S 3900,2500,4700,2500,100,*,LEFT,POLY
-S 3900,2500,3900,3000,100,*,UP,POLY
-S 4300,1400,4300,2000,100,*,DOWN,POLY
-S 3400,2000,4300,2000,100,*,RIGHT,POLY
-S 1500,2000,3000,2000,100,*,RIGHT,POLY
-S 1100,1400,1100,2500,100,*,UP,POLY
-S 1100,2500,1900,2500,100,*,RIGHT,POLY
-S 3400,2000,3400,3600,100,*,DOWN,POLY
-S 3000,900,3000,3600,100,*,DOWN,POLY
-S 1900,2500,1900,3100,100,*,DOWN,POLY
-S 600,1400,600,3100,100,*,DOWN,POLY
-S 2500,1500,2500,3000,100,*,UP,ALU1
-S 2700,500,2700,1000,200,*,UP,ALU1
-S 1000,4000,2000,4000,100,*,LEFT,ALU1
-S 2000,1500,2000,4000,100,*,UP,ALU1
-S 1500,1000,1500,3500,100,*,UP,ALU1
-S 6600,500,6600,1000,200,*,DOWN,ALU1
-S 6600,3000,6600,4500,200,*,DOWN,ALU1
-S 4400,4000,4900,4000,100,*,RIGHT,ALU1
-S 3700,1000,3900,1000,200,*,RIGHT,ALU1
-S 3900,1500,5000,1500,100,*,RIGHT,ALU1
-S 3900,1000,3900,2500,100,*,DOWN,ALU1
-S 3900,2500,4400,2500,100,*,RIGHT,ALU1
-S 4900,2500,4900,4000,100,*,DOWN,ALU1
-S 1000,3000,1000,4000,100,*,DOWN,ALU1
-S 2700,3500,2700,4500,200,*,DOWN,ALU1
-S 5400,3000,5400,4500,200,*,DOWN,ALU1
-S 4900,2500,5500,2500,100,*,RIGHT,ALU1
-S 4400,1000,5500,1000,100,*,LEFT,ALU1
-S 5500,1000,5500,2500,100,*,DOWN,ALU1
-S 5000,1500,5000,1900,100,*,UP,ALU1
-S 1000,2000,4500,2000,200,*,RIGHT,TALU2
-S 0,300,7000,300,600,vss,RIGHT,CALU1
-S 0,4700,7000,4700,600,vdd,RIGHT,CALU1
-S 500,1000,500,4000,200,i,UP,CALU1
-S 6000,1000,6000,4000,200,q,DOWN,CALU1
-S 2500,2500,6000,2500,200,q,RIGHT,CALU2
-S 1000,2000,1000,2000,200,wenx,LEFT,CALU3
-S 2000,2000,2000,2000,200,nwenx,LEFT,CALU3
-S 4500,2000,4500,2000,200,ckx,LEFT,CALU3
-V 3000,2000,CONT_VIA,*
-V 3000,2000,CONT_VIA2,*
-V 5400,4000,CONT_DIF_P,*
-V 5400,4500,CONT_DIF_P,*
-V 6600,4500,CONT_DIF_P,*
-V 6600,3000,CONT_DIF_P,*
-V 5400,3500,CONT_DIF_P,*
-V 900,4700,CONT_BODY_N,*
-V 2100,4700,CONT_BODY_N,*
-V 1500,4700,CONT_BODY_N,*
-V 5400,3000,CONT_DIF_P,*
-V 1500,3500,CONT_DIF_P,*
-V 2700,4500,CONT_DIF_P,*
-V 4400,4000,CONT_DIF_P,*
-V 6600,3500,CONT_DIF_P,*
-V 3700,4000,CONT_DIF_P,*
-V 2700,3500,CONT_DIF_P,*
-V 300,4500,CONT_DIF_P,*
-V 2700,4000,CONT_DIF_P,*
-V 6000,3000,CONT_DIF_P,*
-V 6600,4000,CONT_DIF_P,*
-V 2700,500,CONT_DIF_N,*
-V 4400,1000,CONT_DIF_N,*
-V 6000,1000,CONT_DIF_N,*
-V 5400,500,CONT_DIF_N,*
-V 6600,500,CONT_DIF_N,*
-V 6600,1000,CONT_DIF_N,*
-V 300,500,CONT_DIF_N,*
-V 2700,1000,CONT_DIF_N,*
-V 3700,1000,CONT_DIF_N,*
-V 300,500,CONT_DIF_N,*
-V 1500,1000,CONT_DIF_N,*
-V 1500,300,CONT_BODY_P,*
-V 900,300,CONT_BODY_P,*
-V 2100,300,CONT_BODY_P,*
-V 3700,300,CONT_BODY_P,*
-V 500,3000,CONT_POLY,*
-V 500,1500,CONT_POLY,*
-V 3900,3000,CONT_POLY,*
-V 5000,2000,CONT_POLY,*
-V 1500,2000,CONT_POLY,*
-V 3400,1500,CONT_POLY,*
-V 5500,2000,CONT_POLY,*
-V 2000,1500,CONT_POLY,*
-V 2500,1500,CONT_POLY,*
-V 2500,3000,CONT_POLY,*
-V 1000,3000,CONT_POLY,*
-V 1000,2000,CONT_POLY,*
-V 4400,2000,CONT_POLY,*
-V 4500,2000,CONT_VIA,*
-V 6000,2500,CONT_VIA,*
-V 2000,2000,CONT_VIA,*
-V 1000,2000,CONT_VIA,*
-V 2500,2500,CONT_VIA,*
-V 2000,2000,CONT_VIA2,*
-V 1000,2000,CONT_VIA2,*
-V 4500,2000,CONT_VIA2,*
-EOF
diff --git a/alliance/share/cells/dp_sxlib/dp_dff_x4.vbe b/alliance/share/cells/dp_sxlib/dp_dff_x4.vbe
deleted file mode 100644
index 8a10f8e4..00000000
--- a/alliance/share/cells/dp_sxlib/dp_dff_x4.vbe
+++ /dev/null
@@ -1,36 +0,0 @@
-ENTITY dp_dff_x4 IS
-PORT (
-  ckx		: in  BIT;
-  nckx		: in  BIT;
-  wenx		: in  BIT;
-  nwenx		: in  BIT;
-  i   		: in  BIT;
-  q			: out BIT;
-  vdd		: in  BIT;
-  vss		: in  BIT
-);
-END dp_dff_x4;
-
-ARCHITECTURE vbe OF dp_dff_x4 IS
-  SIGNAL ff : REG_BIT REGISTER;
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on dp_dff_x4"
-  SEVERITY WARNING;
-
-  ASSERT (ckx xor nckx)
-  REPORT "wrong values for ckx and nckx in dp_dff_x4"
-  SEVERITY WARNING;
-
-  ASSERT (wenx xor nwenx)
-  REPORT "wrong values for wenx and nwenx in dp_dff_x4"
-  SEVERITY WARNING;
-
-  label0 : BLOCK ((ckx and not (ckx'STABLE)) = '1')
-  BEGIN
-    ff <= GUARDED ((wenx and i) or (nwenx and ff));
-  END BLOCK label0;
-
-  q <= ff;
-END;
diff --git a/alliance/share/cells/dp_sxlib/dp_dff_x4_buf.ap b/alliance/share/cells/dp_sxlib/dp_dff_x4_buf.ap
deleted file mode 100644
index 2636e48c..00000000
--- a/alliance/share/cells/dp_sxlib/dp_dff_x4_buf.ap
+++ /dev/null
@@ -1,252 +0,0 @@
-V ALLIANCE : 6
-H dp_dff_x4_buf,P,14/11/2000,10
-A 0,0,700,1000
-R 100,400,ref_ref,wenx
-R 200,400,ref_ref,nwenx
-R 350,400,ref_ref,nckx
-R 450,400,ref_ref,ckx
-S 100,600,450,600,20,*,RIGHT,TALU2
-S 100,400,450,400,20,*,LEFT,TALU2
-S 100,150,450,150,20,*,RIGHT,TALU2
-S 450,150,460,150,20,*,RIGHT,ALU1
-S 150,220,240,220,30,*,RIGHT,POLY
-S 100,220,160,220,20,*,RIGHT,ALU1
-S 60,220,120,220,30,*,RIGHT,POLY
-S 90,660,90,900,20,*,UP,ALU1
-S 210,740,210,790,20,*,DOWN,ALU1
-S 60,660,120,660,30,*,RIGHT,POLY
-S 0,500,700,500,460,*,RIGHT,NWELL
-S 70,770,480,770,80,*,RIGHT,NWELL
-S 90,340,90,630,30,*,UP,PDIF
-S 120,320,120,650,10,*,UP,PTRANS
-S 270,340,270,630,30,*,DOWN,PDIF
-S 30,340,30,630,30,*,UP,PDIF
-S 210,730,210,800,30,*,UP,PDIF
-S 60,320,60,650,10,*,UP,PTRANS
-S 180,710,180,820,10,*,DOWN,PTRANS
-S 160,730,160,800,30,*,UP,PDIF
-S 120,710,120,820,10,*,DOWN,PTRANS
-S 90,730,90,800,30,*,UP,PDIF
-S 180,320,180,650,10,*,UP,PTRANS
-S 210,340,210,630,30,*,UP,PDIF
-S 240,320,240,650,10,*,DOWN,PTRANS
-S 310,320,310,650,10,*,UP,PTRANS
-S 400,340,400,630,30,*,UP,PDIF
-S 340,340,340,630,30,*,UP,PDIF
-S 370,320,370,650,10,*,UP,PTRANS
-S 520,340,520,630,30,*,DOWN,PDIF
-S 490,320,490,650,10,*,DOWN,PTRANS
-S 460,340,460,630,30,*,UP,PDIF
-S 430,320,430,650,10,*,UP,PTRANS
-S 340,730,340,800,30,*,UP,PDIF
-S 460,730,460,800,30,*,UP,PDIF
-S 370,710,370,820,10,*,DOWN,PTRANS
-S 410,730,410,800,30,*,UP,PDIF
-S 430,710,430,820,10,*,DOWN,PTRANS
-S 150,340,150,630,30,*,UP,PDIF
-S 60,10,60,190,10,*,UP,NTRANS
-S 120,10,120,190,10,*,DOWN,NTRANS
-S 150,30,150,170,30,*,UP,NDIF
-S 180,10,180,190,10,*,DOWN,NTRANS
-S 210,30,210,170,30,*,UP,NDIF
-S 240,10,240,190,10,*,DOWN,NTRANS
-S 30,30,30,170,30,*,UP,NDIF
-S 270,30,270,170,30,*,UP,NDIF
-S 90,30,90,170,30,*,UP,NDIF
-S 150,890,150,960,30,*,UP,NDIF
-S 90,890,90,960,30,*,UP,NDIF
-S 120,870,120,980,10,*,UP,NTRANS
-S 310,10,310,190,10,*,UP,NTRANS
-S 370,10,370,190,10,*,DOWN,NTRANS
-S 520,30,520,170,30,*,UP,NDIF
-S 430,10,430,190,10,*,DOWN,NTRANS
-S 400,30,400,170,30,*,UP,NDIF
-S 340,30,340,170,30,*,UP,NDIF
-S 490,10,490,190,10,*,DOWN,NTRANS
-S 460,30,460,170,30,*,UP,NDIF
-S 340,890,340,960,30,*,UP,NDIF
-S 400,890,400,960,30,*,UP,NDIF
-S 370,870,370,980,10,*,UP,NTRANS
-S 490,190,490,320,10,*,UP,POLY
-S 120,820,120,870,10,*,DOWN,POLY
-S 430,190,430,320,10,*,DOWN,POLY
-S 60,190,60,320,10,*,DOWN,POLY
-S 370,190,370,320,10,*,UP,POLY
-S 120,190,120,320,10,*,UP,POLY
-S 370,820,370,870,10,*,DOWN,POLY
-S 370,850,430,850,30,*,RIGHT,POLY
-S 430,820,430,860,10,*,DOWN,POLY
-S 180,820,180,860,10,*,DOWN,POLY
-S 120,850,180,850,30,*,RIGHT,POLY
-S 310,190,310,320,10,*,DOWN,POLY
-S 180,190,180,320,10,*,DOWN,POLY
-S 240,190,240,320,10,*,UP,POLY
-S 430,660,490,660,30,*,RIGHT,POLY
-S 430,220,490,220,30,*,RIGHT,POLY
-S 310,220,390,220,30,*,RIGHT,POLY
-S 400,280,400,740,20,*,UP,ALU1
-S 30,50,30,150,20,*,UP,ALU1
-S 210,100,210,400,20,*,UP,ALU1
-S 30,350,30,680,20,*,UP,ALU1
-S 270,280,270,680,20,*,UP,ALU1
-S 270,50,270,150,20,*,UP,ALU1
-S 150,900,150,940,20,*,UP,ALU1
-S 90,790,210,790,20,*,RIGHT,ALU1
-S 340,100,340,400,20,*,UP,ALU1
-S 150,50,150,150,20,*,UP,ALU1
-S 150,280,150,740,20,*,UP,ALU1
-S 30,900,30,970,20,*,DOWN,ALU1
-S 520,50,520,150,20,*,UP,ALU1
-S 400,50,400,150,20,*,UP,ALU1
-S 520,280,520,680,20,*,UP,ALU1
-S 460,100,460,400,20,*,UP,ALU1
-S 90,100,90,400,20,*,UP,ALU1
-S 460,660,460,790,20,*,DOWN,ALU1
-S 340,740,340,900,20,*,UP,ALU1
-S 520,900,520,970,20,*,UP,ALU1
-S 400,900,400,940,20,*,UP,ALU1
-S 340,790,460,790,20,*,RIGHT,ALU1
-S 270,900,270,970,20,*,UP,ALU1
-S 390,220,460,220,20,*,RIGHT,ALU1
-S 600,50,600,150,20,*,UP,ALU1
-S 0,970,700,970,60,vss,RIGHT,CALU1
-S 0,30,700,30,60,vss,RIGHT,CALU1
-S 0,530,700,530,60,vdd,RIGHT,CALU1
-S 0,470,700,470,60,vdd,RIGHT,CALU1
-S 150,850,150,850,10,wen,LEFT,CALU1
-S 400,850,400,850,10,ck,LEFT,CALU1
-S 100,150,100,600,20,wenx,DOWN,CALU3
-S 200,150,200,600,20,nwenx,DOWN,CALU3
-S 350,150,350,600,20,nckx,DOWN,CALU3
-S 450,150,450,600,20,ckx,DOWN,CALU3
-S 200,150,210,150,20,*,RIGHT,ALU1
-V 450,150,CONT_VIA,*
-V 450,150,CONT_VIA2,*
-V 160,220,CONT_POLY,*
-V 90,660,CONT_POLY,*
-V 90,790,CONT_DIF_P,*
-V 30,550,CONT_DIF_P,*
-V 30,350,CONT_DIF_P,*
-V 30,600,CONT_DIF_P,*
-V 270,290,CONT_BODY_N,*
-V 30,290,CONT_BODY_N,*
-V 150,290,CONT_BODY_N,*
-V 90,740,CONT_DIF_P,*
-V 150,740,CONT_DIF_P,*
-V 150,500,CONT_DIF_P,*
-V 150,400,CONT_DIF_P,*
-V 150,550,CONT_DIF_P,*
-V 150,450,CONT_DIF_P,*
-V 150,350,CONT_DIF_P,*
-V 30,400,CONT_DIF_P,*
-V 30,450,CONT_DIF_P,*
-V 30,500,CONT_DIF_P,*
-V 210,350,CONT_DIF_P,*
-V 210,400,CONT_DIF_P,*
-V 270,600,CONT_DIF_P,*
-V 270,550,CONT_DIF_P,*
-V 270,500,CONT_DIF_P,*
-V 270,450,CONT_DIF_P,*
-V 270,350,CONT_DIF_P,*
-V 270,400,CONT_DIF_P,*
-V 270,680,CONT_BODY_N,*
-V 150,680,CONT_BODY_N,*
-V 210,740,CONT_DIF_P,*
-V 210,790,CONT_DIF_P,*
-V 210,600,CONT_DIF_P,*
-V 90,600,CONT_DIF_P,*
-V 90,400,CONT_DIF_P,*
-V 90,350,CONT_DIF_P,*
-V 400,550,CONT_DIF_P,*
-V 30,680,CONT_BODY_N,*
-V 520,600,CONT_DIF_P,*
-V 400,290,CONT_BODY_N,*
-V 520,290,CONT_BODY_N,*
-V 400,350,CONT_DIF_P,*
-V 400,450,CONT_DIF_P,*
-V 520,680,CONT_BODY_N,*
-V 400,400,CONT_DIF_P,*
-V 400,500,CONT_DIF_P,*
-V 520,400,CONT_DIF_P,*
-V 520,350,CONT_DIF_P,*
-V 520,450,CONT_DIF_P,*
-V 520,500,CONT_DIF_P,*
-V 520,550,CONT_DIF_P,*
-V 460,400,CONT_DIF_P,*
-V 460,350,CONT_DIF_P,*
-V 340,350,CONT_DIF_P,*
-V 340,400,CONT_DIF_P,*
-V 340,600,CONT_DIF_P,*
-V 400,600,CONT_DIF_P,*
-V 460,600,CONT_DIF_P,*
-V 400,680,CONT_BODY_N,*
-V 340,790,CONT_DIF_P,*
-V 400,740,CONT_DIF_P,*
-V 340,740,CONT_DIF_P,*
-V 460,790,CONT_DIF_P,*
-V 460,740,CONT_DIF_P,*
-V 150,600,CONT_DIF_P,*
-V 30,50,CONT_DIF_N,*
-V 210,150,CONT_DIF_N,*
-V 270,150,CONT_DIF_N,*
-V 270,50,CONT_DIF_N,*
-V 210,100,CONT_DIF_N,*
-V 270,100,CONT_DIF_N,*
-V 90,900,CONT_DIF_N,*
-V 150,150,CONT_DIF_N,*
-V 150,100,CONT_DIF_N,*
-V 150,50,CONT_DIF_N,*
-V 30,100,CONT_DIF_N,*
-V 30,150,CONT_DIF_N,*
-V 150,900,CONT_DIF_N,*
-V 90,100,CONT_DIF_N,*
-V 90,150,CONT_DIF_N,*
-V 520,100,CONT_DIF_N,*
-V 460,100,CONT_DIF_N,*
-V 520,50,CONT_DIF_N,*
-V 150,950,CONT_DIF_N,*
-V 400,50,CONT_DIF_N,*
-V 340,150,CONT_DIF_N,*
-V 400,150,CONT_DIF_N,*
-V 340,100,CONT_DIF_N,*
-V 520,150,CONT_DIF_N,*
-V 460,150,CONT_DIF_N,*
-V 400,100,CONT_DIF_N,*
-V 400,900,CONT_DIF_N,*
-V 400,950,CONT_DIF_N,*
-V 340,900,CONT_DIF_N,*
-V 520,970,CONT_BODY_P,*
-V 270,970,CONT_BODY_P,*
-V 30,900,CONT_BODY_P,*
-V 270,900,CONT_BODY_P,*
-V 520,900,CONT_BODY_P,*
-V 30,970,CONT_BODY_P,*
-V 400,850,CONT_POLY,*
-V 150,850,CONT_POLY,*
-V 460,660,CONT_POLY,*
-V 390,220,CONT_POLY,*
-V 200,400,CONT_VIA,*
-V 200,600,CONT_VIA,*
-V 100,600,CONT_VIA,*
-V 100,400,CONT_VIA,*
-V 100,150,CONT_VIA,*
-V 350,400,CONT_VIA,*
-V 350,600,CONT_VIA,*
-V 350,150,CONT_VIA,*
-V 450,600,CONT_VIA,*
-V 450,400,CONT_VIA,*
-V 450,600,CONT_VIA2,*
-V 350,150,CONT_VIA2,*
-V 350,600,CONT_VIA2,*
-V 100,150,CONT_VIA2,*
-V 100,400,CONT_VIA2,*
-V 200,400,CONT_VIA2,*
-V 450,400,CONT_VIA2,*
-V 350,400,CONT_VIA2,*
-V 100,600,CONT_VIA2,*
-V 200,600,CONT_VIA2,*
-V 600,50,CONT_BODY_P,*
-V 600,150,CONT_BODY_P,*
-V 200,150,CONT_VIA2,*
-V 200,150,CONT_VIA,*
-EOF
diff --git a/alliance/share/cells/dp_sxlib/dp_dff_x4_buf.vbe b/alliance/share/cells/dp_sxlib/dp_dff_x4_buf.vbe
deleted file mode 100644
index 150e050f..00000000
--- a/alliance/share/cells/dp_sxlib/dp_dff_x4_buf.vbe
+++ /dev/null
@@ -1,25 +0,0 @@
-ENTITY dp_dff_x4_buf IS
-PORT (
-  ck		: in  BIT;
-  wen		: in  BIT;
-  ckx		: out BIT;
-  nckx		: out BIT;
-  wenx		: out BIT;
-  nwenx		: out BIT;
-  vdd		: in  BIT;
-  vss		: in  BIT
-);
-END dp_dff_x4_buf;
-
-ARCHITECTURE vbe OF dp_dff_x4_buf IS
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on dp_dff_x4_buf"
-  SEVERITY WARNING;
-
-  ckx <= ck;
-  nckx <= not ck;
-  wenx <= wen;
-  nwenx <= not wen;
-END;
diff --git a/alliance/share/cells/dp_sxlib/dp_mux_x2.ap b/alliance/share/cells/dp_sxlib/dp_mux_x2.ap
deleted file mode 100644
index a97864eb..00000000
--- a/alliance/share/cells/dp_sxlib/dp_mux_x2.ap
+++ /dev/null
@@ -1,109 +0,0 @@
-V ALLIANCE : 6
-H dp_mux_x2,P,10/11/2000,100
-A 0,0,4000,5000
-R 500,4000,ref_ref,q_40
-R 500,3500,ref_ref,q_35
-R 500,3000,ref_ref,q_30
-R 500,2500,ref_ref,q_25
-R 500,1500,ref_ref,q_15
-R 500,1000,ref_ref,q_10
-R 500,2000,ref_ref,q_20
-R 1500,2500,ref_ref,i1_25
-R 1500,2000,ref_ref,i1_20
-R 1500,1500,ref_ref,i1_15
-R 3500,1500,ref_ref,i0_15
-R 3500,2000,ref_ref,i0_20
-R 3500,3500,ref_ref,i0_35
-R 3500,3000,ref_ref,i0_30
-R 3500,1000,ref_ref,i0_10
-R 1500,1000,ref_ref,i1_10
-R 1500,4000,ref_ref,i1_40
-R 1500,3500,ref_ref,i1_35
-R 1500,3000,ref_ref,i1_30
-R 3500,2500,ref_ref,i0_25
-R 3000,2000,ref_ref,sel0
-R 2000,2000,ref_ref,sel1
-S 3300,3000,3500,3000,100,*,RIGHT,POLY
-S 3300,3000,3300,3100,100,*,DOWN,POLY
-S 2900,2000,2900,3100,100,*,DOWN,POLY
-S 3600,3300,3600,4200,300,*,UP,PDIF
-S 2900,3100,2900,4400,100,*,UP,PTRANS
-S 3300,3100,3300,4400,100,*,UP,PTRANS
-S 2500,3500,2600,3500,100,*,LEFT,ALU1
-S 3000,1500,3000,4000,100,*,UP,ALU1
-S 2000,4000,3000,4000,100,*,RIGHT,ALU1
-S 2500,3300,2500,4200,500,*,UP,PDIF
-S 1700,2900,1700,3100,100,*,DOWN,POLY
-S 1700,3100,1700,4400,100,*,UP,PTRANS
-S 2100,3100,2100,4400,100,*,UP,PTRANS
-S 1500,1000,1500,4000,200,i1,UP,CALU1
-S 2000,2000,2000,2000,200,sel1,LEFT,CALU3
-S 3000,2000,3000,2000,200,sel0,LEFT,CALU3
-S 0,4700,4000,4700,600,vdd,RIGHT,CALU1
-S 0,300,4000,300,600,vss,RIGHT,CALU1
-S 1000,500,1000,1700,200,*,UP,ALU1
-S 1000,3000,1000,4500,200,*,DOWN,ALU1
-S 2100,900,2100,2000,100,*,UP,POLY
-S 1400,1400,1700,1400,100,*,RIGHT,POLY
-S 700,1400,700,2600,100,*,UP,POLY
-S 1700,900,1700,1400,100,*,UP,POLY
-S 2100,2000,2900,2000,100,*,RIGHT,POLY
-S 1200,300,1200,1200,700,*,UP,NDIF
-S 700,100,700,1400,100,*,DOWN,NTRANS
-S 400,300,400,1200,300,*,UP,NDIF
-S 1700,100,1700,900,100,*,DOWN,NTRANS
-S 2100,100,2100,900,100,*,DOWN,NTRANS
-S 3600,300,3600,700,300,*,DOWN,NDIF
-S 2900,100,2900,900,100,*,DOWN,NTRANS
-S 3300,100,3300,900,100,*,DOWN,NTRANS
-S 2500,300,2500,700,500,*,UP,NDIF
-S 400,2800,400,4700,300,*,DOWN,PDIF
-S 1000,2800,1000,3300,300,*,UP,PDIF
-S 700,2600,700,4900,100,*,UP,PTRANS
-S 2500,300,2500,1100,300,*,UP,NDIF
-S 3300,900,3500,900,100,*,LEFT,POLY
-S 2900,900,2900,1600,100,*,DOWN,POLY
-S 2000,2000,3000,2000,200,*,RIGHT,TALU2
-S 0,4000,4000,4000,2600,*,RIGHT,NWELL
-S 500,1000,500,4000,200,q,UP,CALU1
-S 700,2400,2500,2400,100,*,RIGHT,POLY
-S 1500,2900,1700,2900,100,*,LEFT,POLY
-S 1200,3200,1200,4700,700,*,DOWN,PDIF
-S 3500,1000,3500,3500,200,i0,UP,CALU1
-S 3600,4000,3600,4700,200,*,DOWN,ALU1
-S 2500,1000,2500,2500,100,*,UP,ALU1
-S 2000,3000,2100,3000,100,*,RIGHT,ALU1
-S 2100,3000,2100,3200,100,*,DOWN,POLY
-S 2000,3000,2000,4000,100,*,UP,ALU1
-S 2500,2500,2600,2500,100,*,RIGHT,ALU1
-S 2600,2500,2600,3500,100,*,UP,ALU1
-V 2000,4700,CONT_BODY_N,*
-V 3500,3000,CONT_POLY,*
-V 3700,4700,CONT_BODY_N,*
-V 400,4000,CONT_DIF_P,*
-V 400,3500,CONT_DIF_P,*
-V 400,3000,CONT_DIF_P,*
-V 400,1000,CONT_DIF_N,*
-V 3000,2000,CONT_VIA2,*
-V 2000,2000,CONT_VIA2,*
-V 2000,2000,CONT_VIA,*
-V 3000,2000,CONT_VIA,*
-V 1500,1500,CONT_POLY,*
-V 2000,2000,CONT_POLY,*
-V 1000,1700,CONT_BODY_P,*
-V 3600,500,CONT_DIF_N,*
-V 1000,1000,CONT_DIF_N,*
-V 1000,500,CONT_DIF_N,*
-V 1000,4000,CONT_DIF_P,*
-V 1000,3500,CONT_DIF_P,*
-V 1000,3000,CONT_DIF_P,*
-V 1000,4500,CONT_DIF_P,*
-V 2500,1000,CONT_DIF_N,*
-V 3000,1500,CONT_POLY,*
-V 3500,1000,CONT_POLY,*
-V 2500,2400,CONT_POLY,*
-V 1500,2900,CONT_POLY,*
-V 3600,4000,CONT_DIF_P,*
-V 2500,3500,CONT_DIF_P,*
-V 2100,3000,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/dp_sxlib/dp_mux_x2.vbe b/alliance/share/cells/dp_sxlib/dp_mux_x2.vbe
deleted file mode 100644
index 9e9d29c4..00000000
--- a/alliance/share/cells/dp_sxlib/dp_mux_x2.vbe
+++ /dev/null
@@ -1,26 +0,0 @@
-ENTITY dp_mux_x2 IS
-PORT (
-  sel0	: in  BIT;
-  sel1	: in  BIT;
-  i0	: in  BIT;
-  i1	: in  BIT;
-  q	: out BIT;
-  vdd	: in  BIT;
-  vss	: in  BIT
-);
-END dp_mux_x2;
-
-ARCHITECTURE vbe OF dp_mux_x2 IS
-
-BEGIN
-  ASSERT (vdd and not vss)
-  REPORT "power supply is missing on dp_mux_x2"
-  SEVERITY WARNING;
-
-  ASSERT (sel0 xor sel1)
-  REPORT "wrong control signals on dp_mux_x2"
-  SEVERITY WARNING;
-
-  q <= (sel0 and i0) or (sel1 and i1);
-
-END;
diff --git a/alliance/share/cells/dp_sxlib/dp_mux_x2_buf.ap b/alliance/share/cells/dp_sxlib/dp_mux_x2_buf.ap
deleted file mode 100644
index 8252b3ad..00000000
--- a/alliance/share/cells/dp_sxlib/dp_mux_x2_buf.ap
+++ /dev/null
@@ -1,141 +0,0 @@
-V ALLIANCE : 6
-H dp_mux_x2_buf,P,14/11/2000,10
-A 0,0,400,1000
-R 200,400,ref_ref,sel1
-R 300,400,ref_ref,sel0
-S 200,600,300,600,20,*,RIGHT,TALU2
-S 200,400,300,400,20,*,RIGHT,TALU2
-S 200,150,300,150,20,*,RIGHT,TALU2
-S 250,850,250,850,10,sel,LEFT,CALU1
-S 60,30,60,150,20,*,DOWN,ALU1
-S 370,50,370,150,20,*,UP,ALU1
-S 190,100,190,400,20,*,UP,ALU1
-S 190,660,190,900,20,*,UP,ALU1
-S 310,100,310,400,20,*,UP,ALU1
-S 190,220,260,220,20,*,RIGHT,ALU1
-S 370,900,370,970,20,*,UP,ALU1
-S 310,740,310,790,20,*,DOWN,ALU1
-S 190,790,310,790,20,*,RIGHT,ALU1
-S 250,900,250,940,20,*,UP,ALU1
-S 130,350,130,680,20,*,UP,ALU1
-S 370,280,370,680,20,*,UP,ALU1
-S 130,50,130,150,20,*,UP,ALU1
-S 250,50,250,150,20,*,UP,ALU1
-S 250,280,250,740,20,*,UP,ALU1
-S 130,900,130,970,20,*,DOWN,ALU1
-S 250,220,340,220,30,*,RIGHT,POLY
-S 160,220,220,220,30,*,RIGHT,POLY
-S 280,820,280,860,10,*,DOWN,POLY
-S 220,850,280,850,30,*,RIGHT,POLY
-S 160,660,220,660,30,*,RIGHT,POLY
-S 280,190,280,320,10,*,DOWN,POLY
-S 340,190,340,320,10,*,UP,POLY
-S 220,190,220,320,10,*,UP,POLY
-S 160,190,160,320,10,*,DOWN,POLY
-S 220,820,220,870,10,*,DOWN,POLY
-S 130,30,130,170,30,*,UP,NDIF
-S 370,30,370,170,30,*,UP,NDIF
-S 220,10,220,190,10,*,DOWN,NTRANS
-S 160,10,160,190,10,*,UP,NTRANS
-S 250,30,250,170,30,*,UP,NDIF
-S 190,30,190,170,30,*,UP,NDIF
-S 250,890,250,960,30,*,UP,NDIF
-S 190,890,190,960,30,*,UP,NDIF
-S 280,10,280,190,10,*,DOWN,NTRANS
-S 310,30,310,170,30,*,UP,NDIF
-S 340,10,340,190,10,*,DOWN,NTRANS
-S 220,870,220,980,10,*,UP,NTRANS
-S 340,320,340,650,10,*,DOWN,PTRANS
-S 370,340,370,630,30,*,DOWN,PDIF
-S 220,320,220,650,10,*,UP,PTRANS
-S 190,340,190,630,30,*,UP,PDIF
-S 250,340,250,630,30,*,UP,PDIF
-S 160,320,160,650,10,*,UP,PTRANS
-S 130,340,130,630,30,*,UP,PDIF
-S 310,730,310,800,30,*,UP,PDIF
-S 280,710,280,820,10,*,DOWN,PTRANS
-S 260,730,260,800,30,*,UP,PDIF
-S 220,710,220,820,10,*,DOWN,PTRANS
-S 190,730,190,800,30,*,UP,PDIF
-S 280,320,280,650,10,*,UP,PTRANS
-S 310,340,310,630,30,*,UP,PDIF
-S 0,500,400,500,460,*,RIGHT,NWELL
-S 200,150,200,600,20,sel1,UP,CALU3
-S 300,150,300,600,20,sel0,DOWN,CALU3
-S 0,30,400,30,60,vss,RIGHT,CALU1
-S 0,970,400,970,60,vss,RIGHT,CALU1
-S 0,530,400,530,60,vdd,RIGHT,CALU1
-S 0,470,400,470,60,vdd,RIGHT,CALU1
-V 300,150,CONT_VIA,*
-V 300,150,CONT_VIA2,*
-V 60,150,CONT_BODY_P,*
-V 60,30,CONT_BODY_P,*
-V 200,150,CONT_VIA2,*
-V 300,600,CONT_VIA2,*
-V 200,600,CONT_VIA2,*
-V 200,400,CONT_VIA2,*
-V 300,400,CONT_VIA2,*
-V 200,150,CONT_VIA,*
-V 300,400,CONT_VIA,*
-V 300,600,CONT_VIA,*
-V 200,600,CONT_VIA,*
-V 200,400,CONT_VIA,*
-V 190,660,CONT_POLY,*
-V 260,220,CONT_POLY,*
-V 250,850,CONT_POLY,*
-V 130,900,CONT_BODY_P,*
-V 370,900,CONT_BODY_P,*
-V 130,970,CONT_BODY_P,*
-V 370,970,CONT_BODY_P,*
-V 130,150,CONT_DIF_N,*
-V 130,50,CONT_DIF_N,*
-V 310,150,CONT_DIF_N,*
-V 370,150,CONT_DIF_N,*
-V 370,50,CONT_DIF_N,*
-V 310,100,CONT_DIF_N,*
-V 370,100,CONT_DIF_N,*
-V 250,900,CONT_DIF_N,*
-V 190,100,CONT_DIF_N,*
-V 190,150,CONT_DIF_N,*
-V 190,900,CONT_DIF_N,*
-V 250,150,CONT_DIF_N,*
-V 250,50,CONT_DIF_N,*
-V 250,100,CONT_DIF_N,*
-V 130,100,CONT_DIF_N,*
-V 250,950,CONT_DIF_N,*
-V 190,790,CONT_DIF_P,*
-V 130,550,CONT_DIF_P,*
-V 130,350,CONT_DIF_P,*
-V 130,600,CONT_DIF_P,*
-V 370,290,CONT_BODY_N,*
-V 130,290,CONT_BODY_N,*
-V 250,290,CONT_BODY_N,*
-V 190,740,CONT_DIF_P,*
-V 250,740,CONT_DIF_P,*
-V 250,500,CONT_DIF_P,*
-V 250,400,CONT_DIF_P,*
-V 250,550,CONT_DIF_P,*
-V 250,450,CONT_DIF_P,*
-V 250,350,CONT_DIF_P,*
-V 130,400,CONT_DIF_P,*
-V 130,450,CONT_DIF_P,*
-V 130,500,CONT_DIF_P,*
-V 310,350,CONT_DIF_P,*
-V 310,400,CONT_DIF_P,*
-V 370,600,CONT_DIF_P,*
-V 370,550,CONT_DIF_P,*
-V 370,500,CONT_DIF_P,*
-V 370,450,CONT_DIF_P,*
-V 370,350,CONT_DIF_P,*
-V 370,400,CONT_DIF_P,*
-V 370,680,CONT_BODY_N,*
-V 250,680,CONT_BODY_N,*
-V 310,740,CONT_DIF_P,*
-V 310,790,CONT_DIF_P,*
-V 310,600,CONT_DIF_P,*
-V 190,600,CONT_DIF_P,*
-V 190,400,CONT_DIF_P,*
-V 190,350,CONT_DIF_P,*
-V 130,680,CONT_BODY_N,*
-V 60,90,CONT_BODY_P,*
-EOF
diff --git a/alliance/share/cells/dp_sxlib/dp_mux_x2_buf.vbe b/alliance/share/cells/dp_sxlib/dp_mux_x2_buf.vbe
deleted file mode 100644
index 7e5711b7..00000000
--- a/alliance/share/cells/dp_sxlib/dp_mux_x2_buf.vbe
+++ /dev/null
@@ -1,21 +0,0 @@
-ENTITY dp_mux_x2_buf IS
-PORT (
-  sel	: in  BIT;
-  sel0	: out BIT;
-  sel1	: out BIT;
-  vdd	: in  BIT;
-  vss	: in  BIT
-);
-END dp_mux_x2_buf;
-
-ARCHITECTURE vbe OF dp_mux_x2_buf IS
-
-BEGIN
-  ASSERT (vdd and not vss)
-  REPORT "power supply is missing on dp_mux_x2_buf"
-  SEVERITY WARNING;
-
-  sel1 <= sel;
-  sel0 <= not sel;
-
-END;
diff --git a/alliance/share/cells/dp_sxlib/dp_mux_x4.ap b/alliance/share/cells/dp_sxlib/dp_mux_x4.ap
deleted file mode 100644
index c16ab830..00000000
--- a/alliance/share/cells/dp_sxlib/dp_mux_x4.ap
+++ /dev/null
@@ -1,124 +0,0 @@
-V ALLIANCE : 6
-H dp_mux_x4,P,10/11/2000,100
-A 0,0,4500,5000
-R 3500,2000,ref_ref,sel0
-R 2500,2000,ref_ref,sel1
-R 1000,4000,ref_ref,q_40
-R 1000,3500,ref_ref,q_35
-R 1000,3000,ref_ref,q_30
-R 1000,2500,ref_ref,q_25
-R 1000,2000,ref_ref,q_20
-R 1000,1500,ref_ref,q_15
-R 1000,1000,ref_ref,q_10
-R 4000,2500,ref_ref,i0_25
-R 4000,3000,ref_ref,i0_30
-R 4000,1000,ref_ref,i0_10
-R 2000,1000,ref_ref,i1_10
-R 4000,3500,ref_ref,i0_35
-R 4000,2000,ref_ref,i0_20
-R 4000,1500,ref_ref,i0_15
-R 2000,1500,ref_ref,i1_15
-R 2000,2000,ref_ref,i1_20
-R 2000,2500,ref_ref,i1_25
-R 2000,3000,ref_ref,i1_30
-R 2000,3500,ref_ref,i1_35
-R 2000,4000,ref_ref,i1_40
-S 3800,3000,4000,3000,100,*,RIGHT,POLY
-S 3800,3000,3800,3100,100,*,DOWN,POLY
-S 3400,2000,3400,3100,100,*,DOWN,POLY
-S 4100,3300,4100,4200,300,*,UP,PDIF
-S 3800,3100,3800,4400,100,*,UP,PTRANS
-S 3400,3100,3400,4400,100,*,UP,PTRANS
-S 2000,2900,2200,2900,100,*,LEFT,POLY
-S 4100,4000,4100,4700,200,*,UP,ALU1
-S 1700,3200,1700,4700,700,*,DOWN,PDIF
-S 4000,1000,4000,3500,200,i0,UP,CALU1
-S 2500,4000,3500,4000,100,*,RIGHT,ALU1
-S 300,500,300,1700,200,*,UP,ALU1
-S 300,3000,300,4500,200,*,DOWN,ALU1
-S 300,300,300,1200,300,*,UP,NDIF
-S 600,100,600,1400,100,*,DOWN,NTRANS
-S 900,300,900,1200,300,*,UP,NDIF
-S 1200,100,1200,1400,100,*,DOWN,NTRANS
-S 1700,300,1700,1200,700,*,UP,NDIF
-S 1500,3000,1500,4500,200,*,DOWN,ALU1
-S 1900,1400,2200,1400,100,*,RIGHT,POLY
-S 3800,100,3800,900,100,*,DOWN,NTRANS
-S 3400,100,3400,900,100,*,DOWN,NTRANS
-S 1500,500,1500,1700,200,*,UP,ALU1
-S 4100,300,4100,700,300,*,DOWN,NDIF
-S 2600,100,2600,900,100,*,DOWN,NTRANS
-S 2200,100,2200,900,100,*,DOWN,NTRANS
-S 2600,900,2600,2000,100,*,UP,POLY
-S 2200,900,2200,1400,100,*,UP,POLY
-S 3000,300,3000,700,500,*,UP,NDIF
-S 600,1400,600,2600,100,*,UP,POLY
-S 1200,1400,1200,2600,100,*,UP,POLY
-S 600,2600,600,4900,100,*,UP,PTRANS
-S 1200,2600,1200,4900,100,*,UP,PTRANS
-S 300,2800,300,4700,300,*,DOWN,PDIF
-S 1500,2800,1500,3300,300,*,UP,PDIF
-S 900,2800,900,4700,300,*,DOWN,PDIF
-S 2600,2000,3400,2000,100,*,RIGHT,POLY
-S 0,4000,4500,4000,2600,*,LEFT,NWELL
-S 3000,300,3000,1100,300,*,UP,NDIF
-S 2900,300,2900,1100,300,*,UP,NDIF
-S 3800,900,4000,900,100,*,LEFT,POLY
-S 3500,1500,3500,4000,100,*,UP,ALU1
-S 3400,900,3400,1600,100,*,UP,POLY
-S 2500,2000,3500,2000,200,*,RIGHT,TALU2
-S 2500,2000,2500,2000,200,sel1,LEFT,CALU3
-S 3500,2000,3500,2000,200,sel0,LEFT,CALU3
-S 1000,1000,1000,4000,200,q,UP,CALU1
-S 2000,1000,2000,4000,200,i1,UP,CALU1
-S 0,300,4500,300,600,vss,RIGHT,CALU1
-S 0,4700,4500,4700,600,vdd,RIGHT,CALU1
-S 600,2400,3000,2400,100,*,RIGHT,POLY
-S 2200,3100,2200,4400,100,*,UP,PTRANS
-S 2600,3100,2600,4400,100,*,UP,PTRANS
-S 2200,2900,2200,3100,100,*,DOWN,POLY
-S 2600,2900,2600,3200,100,*,DOWN,POLY
-S 2500,3000,2500,4000,100,*,UP,ALU1
-S 2500,3000,2600,3000,100,*,RIGHT,ALU1
-S 3000,3300,3000,4200,500,*,UP,PDIF
-S 3000,3500,3100,3500,100,*,LEFT,ALU1
-S 3100,2500,3100,3500,100,*,UP,ALU1
-S 3000,1000,3000,2500,100,*,UP,ALU1
-S 3000,2500,3100,2500,100,*,RIGHT,ALU1
-V 4000,3000,CONT_POLY,*
-V 4200,4700,CONT_BODY_N,*
-V 2500,4700,CONT_BODY_N,*
-V 4100,4000,CONT_DIF_P,*
-V 2000,2900,CONT_POLY,*
-V 900,4000,CONT_DIF_P,*
-V 900,3500,CONT_DIF_P,*
-V 900,3000,CONT_DIF_P,*
-V 900,1000,CONT_DIF_N,*
-V 3000,3500,CONT_DIF_P,*
-V 3500,2000,CONT_VIA,*
-V 3500,2000,CONT_VIA2,*
-V 2500,2000,CONT_POLY,*
-V 2500,2000,CONT_VIA,*
-V 2500,2000,CONT_VIA2,*
-V 300,1000,CONT_DIF_N,*
-V 300,500,CONT_DIF_N,*
-V 300,1700,CONT_BODY_P,*
-V 300,4000,CONT_DIF_P,*
-V 300,4500,CONT_DIF_P,*
-V 300,3000,CONT_DIF_P,*
-V 300,3500,CONT_DIF_P,*
-V 2000,1500,CONT_POLY,*
-V 4100,500,CONT_DIF_N,*
-V 1500,3500,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 1500,500,CONT_DIF_N,*
-V 1500,4500,CONT_DIF_P,*
-V 1500,1000,CONT_DIF_N,*
-V 1500,3000,CONT_DIF_P,*
-V 1500,1700,CONT_BODY_P,*
-V 3000,1000,CONT_DIF_N,*
-V 3500,1500,CONT_POLY,*
-V 4000,1000,CONT_POLY,*
-V 3000,2400,CONT_POLY,*
-V 2600,3000,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/dp_sxlib/dp_mux_x4.vbe b/alliance/share/cells/dp_sxlib/dp_mux_x4.vbe
deleted file mode 100644
index 470bc377..00000000
--- a/alliance/share/cells/dp_sxlib/dp_mux_x4.vbe
+++ /dev/null
@@ -1,26 +0,0 @@
-ENTITY dp_mux_x4 IS
-PORT (
-  sel0	: in  BIT;
-  sel1	: in  BIT;
-  i0	: in  BIT;
-  i1	: in  BIT;
-  q	: out BIT;
-  vdd	: in  BIT;
-  vss	: in  BIT
-);
-END dp_mux_x4;
-
-ARCHITECTURE vbe OF dp_mux_x4 IS
-
-BEGIN
-  ASSERT (vdd and not vss)
-  REPORT "power supply is missing on dp_mux_x4"
-  SEVERITY WARNING;
-
-  ASSERT (sel0 xor sel1)
-  REPORT "wrong control signals on dp_mux_x4"
-  SEVERITY WARNING;
-
-  q <= (sel0 and i0) or (sel1 and i1);
-
-END;
diff --git a/alliance/share/cells/dp_sxlib/dp_mux_x4_buf.ap b/alliance/share/cells/dp_sxlib/dp_mux_x4_buf.ap
deleted file mode 100644
index 3d8636b4..00000000
--- a/alliance/share/cells/dp_sxlib/dp_mux_x4_buf.ap
+++ /dev/null
@@ -1,141 +0,0 @@
-V ALLIANCE : 6
-H dp_mux_x4_buf,P,14/11/2000,10
-A 0,0,450,1000
-R 250,400,ref_ref,sel1
-R 350,400,ref_ref,sel0
-S 250,600,350,600,20,*,RIGHT,TALU2
-S 250,400,350,400,20,*,LEFT,TALU2
-S 250,150,350,150,20,*,RIGHT,TALU2
-S 300,850,300,850,10,sel,LEFT,CALU1
-S 250,150,250,600,20,sel1,UP,CALU3
-S 350,150,350,600,20,sel0,DOWN,CALU3
-S 0,530,450,530,60,vdd,RIGHT,CALU1
-S 0,470,450,470,60,vdd,RIGHT,CALU1
-S 0,30,450,30,60,vss,RIGHT,CALU1
-S 0,970,450,970,60,vss,RIGHT,CALU1
-S 0,500,450,500,460,*,RIGHT,NWELL
-S 330,710,330,820,10,*,DOWN,PTRANS
-S 310,730,310,800,30,*,UP,PDIF
-S 270,710,270,820,10,*,DOWN,PTRANS
-S 240,730,240,800,30,*,UP,PDIF
-S 330,320,330,650,10,*,UP,PTRANS
-S 360,340,360,630,30,*,UP,PDIF
-S 390,320,390,650,10,*,DOWN,PTRANS
-S 420,340,420,630,30,*,DOWN,PDIF
-S 270,320,270,650,10,*,UP,PTRANS
-S 240,340,240,630,30,*,UP,PDIF
-S 300,340,300,630,30,*,UP,PDIF
-S 210,320,210,650,10,*,UP,PTRANS
-S 180,340,180,630,30,*,UP,PDIF
-S 360,730,360,800,30,*,UP,PDIF
-S 270,870,270,980,10,*,UP,NTRANS
-S 300,890,300,960,30,*,UP,NDIF
-S 240,890,240,960,30,*,UP,NDIF
-S 330,10,330,190,10,*,DOWN,NTRANS
-S 360,30,360,170,30,*,UP,NDIF
-S 390,10,390,190,10,*,DOWN,NTRANS
-S 180,30,180,170,30,*,UP,NDIF
-S 420,30,420,170,30,*,UP,NDIF
-S 270,10,270,190,10,*,DOWN,NTRANS
-S 210,10,210,190,10,*,UP,NTRANS
-S 300,30,300,170,30,*,UP,NDIF
-S 240,30,240,170,30,*,UP,NDIF
-S 210,190,210,320,10,*,DOWN,POLY
-S 270,820,270,870,10,*,DOWN,POLY
-S 300,220,390,220,30,*,RIGHT,POLY
-S 210,220,270,220,30,*,RIGHT,POLY
-S 330,820,330,860,10,*,DOWN,POLY
-S 270,850,330,850,30,*,RIGHT,POLY
-S 210,660,270,660,30,*,RIGHT,POLY
-S 330,190,330,320,10,*,DOWN,POLY
-S 390,190,390,320,10,*,UP,POLY
-S 270,190,270,320,10,*,UP,POLY
-S 300,900,300,940,20,*,UP,ALU1
-S 180,350,180,680,20,*,UP,ALU1
-S 420,280,420,680,20,*,UP,ALU1
-S 180,50,180,150,20,*,UP,ALU1
-S 300,50,300,150,20,*,UP,ALU1
-S 300,280,300,740,20,*,UP,ALU1
-S 180,900,180,970,20,*,DOWN,ALU1
-S 420,50,420,150,20,*,UP,ALU1
-S 240,100,240,400,20,*,UP,ALU1
-S 240,660,240,900,20,*,UP,ALU1
-S 360,100,360,400,20,*,UP,ALU1
-S 240,220,310,220,20,*,RIGHT,ALU1
-S 420,900,420,970,20,*,UP,ALU1
-S 360,740,360,790,20,*,DOWN,ALU1
-S 240,790,360,790,20,*,RIGHT,ALU1
-S 70,30,70,150,20,*,DOWN,ALU1
-V 180,680,CONT_BODY_N,*
-V 420,680,CONT_BODY_N,*
-V 300,680,CONT_BODY_N,*
-V 360,740,CONT_DIF_P,*
-V 360,790,CONT_DIF_P,*
-V 360,600,CONT_DIF_P,*
-V 240,600,CONT_DIF_P,*
-V 240,400,CONT_DIF_P,*
-V 240,350,CONT_DIF_P,*
-V 360,350,CONT_DIF_P,*
-V 360,400,CONT_DIF_P,*
-V 420,600,CONT_DIF_P,*
-V 420,550,CONT_DIF_P,*
-V 420,500,CONT_DIF_P,*
-V 420,450,CONT_DIF_P,*
-V 420,350,CONT_DIF_P,*
-V 420,400,CONT_DIF_P,*
-V 300,500,CONT_DIF_P,*
-V 300,400,CONT_DIF_P,*
-V 300,550,CONT_DIF_P,*
-V 300,450,CONT_DIF_P,*
-V 300,350,CONT_DIF_P,*
-V 180,400,CONT_DIF_P,*
-V 180,450,CONT_DIF_P,*
-V 180,500,CONT_DIF_P,*
-V 180,550,CONT_DIF_P,*
-V 180,350,CONT_DIF_P,*
-V 180,600,CONT_DIF_P,*
-V 420,290,CONT_BODY_N,*
-V 180,290,CONT_BODY_N,*
-V 300,290,CONT_BODY_N,*
-V 240,740,CONT_DIF_P,*
-V 300,740,CONT_DIF_P,*
-V 240,790,CONT_DIF_P,*
-V 300,950,CONT_DIF_N,*
-V 300,900,CONT_DIF_N,*
-V 240,100,CONT_DIF_N,*
-V 240,150,CONT_DIF_N,*
-V 240,900,CONT_DIF_N,*
-V 300,150,CONT_DIF_N,*
-V 300,50,CONT_DIF_N,*
-V 300,100,CONT_DIF_N,*
-V 180,100,CONT_DIF_N,*
-V 180,150,CONT_DIF_N,*
-V 180,50,CONT_DIF_N,*
-V 360,150,CONT_DIF_N,*
-V 420,150,CONT_DIF_N,*
-V 420,50,CONT_DIF_N,*
-V 360,100,CONT_DIF_N,*
-V 420,100,CONT_DIF_N,*
-V 180,900,CONT_BODY_P,*
-V 420,900,CONT_BODY_P,*
-V 180,970,CONT_BODY_P,*
-V 420,970,CONT_BODY_P,*
-V 240,660,CONT_POLY,*
-V 310,220,CONT_POLY,*
-V 300,850,CONT_POLY,*
-V 250,400,CONT_VIA,*
-V 250,150,CONT_VIA,*
-V 350,400,CONT_VIA,*
-V 350,600,CONT_VIA,*
-V 250,600,CONT_VIA,*
-V 350,400,CONT_VIA2,*
-V 250,150,CONT_VIA2,*
-V 350,600,CONT_VIA2,*
-V 250,600,CONT_VIA2,*
-V 250,400,CONT_VIA2,*
-V 70,30,CONT_BODY_P,*
-V 70,150,CONT_BODY_P,*
-V 70,90,CONT_BODY_P,*
-V 350,150,CONT_VIA2,*
-V 350,150,CONT_VIA,*
-EOF
diff --git a/alliance/share/cells/dp_sxlib/dp_mux_x4_buf.vbe b/alliance/share/cells/dp_sxlib/dp_mux_x4_buf.vbe
deleted file mode 100644
index 51882792..00000000
--- a/alliance/share/cells/dp_sxlib/dp_mux_x4_buf.vbe
+++ /dev/null
@@ -1,21 +0,0 @@
-ENTITY dp_mux_x4_buf IS
-PORT (
-  sel	: in  BIT;
-  sel0	: out BIT;
-  sel1	: out BIT;
-  vdd	: in  BIT;
-  vss	: in  BIT
-);
-END dp_mux_x4_buf;
-
-ARCHITECTURE vbe OF dp_mux_x4_buf IS
-
-BEGIN
-  ASSERT (vdd and not vss)
-  REPORT "power supply is missing on dp_mux_x4_buf"
-  SEVERITY WARNING;
-
-  sel1 <= sel;
-  sel0 <= not sel;
-
-END;
diff --git a/alliance/share/cells/dp_sxlib/dp_nmux_x1.ap b/alliance/share/cells/dp_sxlib/dp_nmux_x1.ap
deleted file mode 100644
index 556c969f..00000000
--- a/alliance/share/cells/dp_sxlib/dp_nmux_x1.ap
+++ /dev/null
@@ -1,80 +0,0 @@
-V ALLIANCE : 6
-H dp_nmux_x1,P,15/11/2000,100
-A 0,0,3000,5000
-R 500,1500,ref_ref,i1_15
-R 500,1000,ref_ref,i1_10
-R 1500,1000,ref_ref,nq_10
-R 1500,1500,ref_ref,nq_15
-R 2500,1000,ref_ref,i0_10
-R 2500,1500,ref_ref,i0_15
-R 2500,2000,ref_ref,i0_20
-R 500,2000,ref_ref,i1_20
-R 500,2500,ref_ref,i1_25
-R 500,3000,ref_ref,i1_30
-R 500,3500,ref_ref,i1_35
-R 500,4000,ref_ref,i1_40
-R 2500,2500,ref_ref,i0_25
-R 2500,4000,ref_ref,i0_40
-R 2500,3500,ref_ref,i0_35
-R 2500,3000,ref_ref,i0_30
-R 1500,3500,ref_ref,nq_35
-R 1500,3000,ref_ref,nq_30
-R 1500,2500,ref_ref,nq_25
-R 1500,2000,ref_ref,nq_20
-R 1000,2000,ref_ref,sel1
-R 2000,2000,ref_ref,sel0
-S 2400,2600,2400,4400,100,*,UP,PTRANS
-S 1500,2800,1500,4200,500,*,UP,PDIF
-S 1900,2600,1900,4400,100,*,UP,PTRANS
-S 1100,2600,1100,4400,100,*,UP,PTRANS
-S 600,2600,600,4400,100,*,UP,PTRANS
-S 2000,2000,2000,2000,200,sel0,LEFT,CALU3
-S 1000,2000,1000,2000,200,sel1,LEFT,CALU3
-S 600,1900,600,2600,100,*,UP,POLY
-S 2400,1900,2400,2600,100,*,UP,POLY
-S 300,400,300,1700,300,*,DOWN,NDIF
-S 2700,400,2700,1700,300,*,DOWN,NDIF
-S 1900,600,1900,1900,100,*,DOWN,NTRANS
-S 1500,800,1500,1700,500,*,UP,NDIF
-S 1100,600,1100,1900,100,*,DOWN,NTRANS
-S 2400,600,2400,1900,100,*,DOWN,NTRANS
-S 600,600,600,1900,100,*,DOWN,NTRANS
-S 1500,2600,1900,2600,100,*,RIGHT,POLY
-S 1500,2100,1500,2600,100,*,UP,POLY
-S 900,2100,1500,2100,100,*,RIGHT,POLY
-S 2000,2000,2000,4000,100,*,UP,ALU1
-S 1000,4000,2000,4000,100,*,LEFT,ALU1
-S 1000,2500,1000,4000,100,*,DOWN,ALU1
-S 2700,2800,2700,4500,300,*,UP,PDIF
-S 300,2800,300,4500,300,*,UP,PDIF
-S 0,4000,3000,4000,2600,*,RIGHT,NWELL
-S 1000,2000,2000,2000,200,*,RIGHT,TALU2
-S 0,300,3000,300,600,vss,RIGHT,CALU1
-S 0,4700,3000,4700,600,vdd,RIGHT,CALU1
-S 2500,1000,2500,4000,200,i0,UP,CALU1
-S 500,1000,500,4000,200,i1,UP,CALU1
-S 1500,1000,1500,3500,200,nq,UP,CALU1
-V 1500,4700,CONT_BODY_N,*
-V 2100,4700,CONT_BODY_N,*
-V 900,4700,CONT_BODY_N,*
-V 1500,1500,CONT_DIF_N,*
-V 300,500,CONT_DIF_N,*
-V 2700,500,CONT_DIF_N,*
-V 1500,1000,CONT_DIF_N,*
-V 1500,300,CONT_BODY_P,*
-V 2000,2000,CONT_POLY,*
-V 1000,2000,CONT_VIA2,*
-V 1000,2000,CONT_VIA,*
-V 2000,2000,CONT_VIA2,*
-V 2000,2000,CONT_VIA,*
-V 1000,2500,CONT_POLY,*
-V 2700,4500,CONT_DIF_P,*
-V 1500,3500,CONT_DIF_P,*
-V 1500,3000,CONT_DIF_P,*
-V 300,4500,CONT_DIF_P,*
-V 1000,2000,CONT_POLY,*
-V 2500,2000,CONT_POLY,*
-V 500,2000,CONT_POLY,*
-V 900,300,CONT_BODY_P,*
-V 2100,300,CONT_BODY_P,*
-EOF
diff --git a/alliance/share/cells/dp_sxlib/dp_nmux_x1.vbe b/alliance/share/cells/dp_sxlib/dp_nmux_x1.vbe
deleted file mode 100644
index e9b7bfed..00000000
--- a/alliance/share/cells/dp_sxlib/dp_nmux_x1.vbe
+++ /dev/null
@@ -1,26 +0,0 @@
-ENTITY dp_nmux_x1 IS
-PORT (
-  sel0	: in  BIT;
-  sel1	: in  BIT;
-  i0	: in  BIT;
-  i1	: in  BIT;
-  nq	: out BIT;
-  vdd	: in  BIT;
-  vss	: in  BIT
-);
-END dp_nmux_x1;
-
-ARCHITECTURE vbe OF dp_nmux_x1 IS
-
-BEGIN
-  ASSERT (vdd and not vss) 
-  REPORT "power supply is missing on dp_nmux_x1"
-  SEVERITY WARNING;
-
-  ASSERT (sel0 xor sel1) 
-  REPORT "wrong control signals on dp_nmux_x1"
-  SEVERITY WARNING;
-
-  nq <= not ((sel0 and i0) or (sel1 and i1));
-
-END;
diff --git a/alliance/share/cells/dp_sxlib/dp_nmux_x1_buf.ap b/alliance/share/cells/dp_sxlib/dp_nmux_x1_buf.ap
deleted file mode 100644
index 08289ecb..00000000
--- a/alliance/share/cells/dp_sxlib/dp_nmux_x1_buf.ap
+++ /dev/null
@@ -1,137 +0,0 @@
-V ALLIANCE : 6
-H dp_nmux_x1_buf,P,14/11/2000,10
-A 0,0,300,1000
-R 100,400,ref_ref,sel1
-R 200,400,ref_ref,sel0
-S 100,600,200,600,20,*,RIGHT,TALU2
-S 100,400,200,400,20,*,RIGHT,TALU2
-S 100,150,200,150,20,*,RIGHT,TALU2
-S 150,850,150,850,10,sel,LEFT,CALU1
-S 180,190,180,320,10,*,DOWN,POLY
-S 240,190,240,320,10,*,UP,POLY
-S 120,190,120,320,10,*,UP,POLY
-S 60,190,60,320,10,*,DOWN,POLY
-S 150,280,150,740,20,*,UP,ALU1
-S 30,900,30,970,20,*,DOWN,ALU1
-S 270,900,270,970,20,*,UP,ALU1
-S 210,740,210,790,20,*,DOWN,ALU1
-S 90,790,210,790,20,*,RIGHT,ALU1
-S 120,820,120,870,10,*,DOWN,POLY
-S 180,820,180,860,10,*,DOWN,POLY
-S 120,850,180,850,30,*,RIGHT,POLY
-S 120,870,120,980,10,*,UP,NTRANS
-S 150,890,150,960,30,*,UP,NDIF
-S 90,890,90,960,30,*,UP,NDIF
-S 150,900,150,940,20,*,UP,ALU1
-S 210,730,210,800,30,*,UP,PDIF
-S 180,710,180,820,10,*,DOWN,PTRANS
-S 160,730,160,800,30,*,UP,PDIF
-S 120,710,120,820,10,*,DOWN,PTRANS
-S 90,730,90,800,30,*,UP,PDIF
-S 60,660,120,660,30,*,RIGHT,POLY
-S 30,350,30,680,20,*,UP,ALU1
-S 270,280,270,680,20,*,UP,ALU1
-S 180,320,180,650,10,*,UP,PTRANS
-S 210,340,210,630,30,*,UP,PDIF
-S 240,320,240,650,10,*,DOWN,PTRANS
-S 270,340,270,630,30,*,DOWN,PDIF
-S 120,320,120,650,10,*,UP,PTRANS
-S 90,340,90,630,30,*,UP,PDIF
-S 150,340,150,630,30,*,UP,PDIF
-S 60,320,60,650,10,*,UP,PTRANS
-S 30,340,30,630,30,*,UP,PDIF
-S 30,50,30,150,20,*,UP,ALU1
-S 150,50,150,150,20,*,UP,ALU1
-S 270,50,270,150,20,*,UP,ALU1
-S 180,10,180,190,10,*,DOWN,NTRANS
-S 210,30,210,170,30,*,UP,NDIF
-S 240,10,240,190,10,*,DOWN,NTRANS
-S 30,30,30,170,30,*,UP,NDIF
-S 270,30,270,170,30,*,UP,NDIF
-S 120,10,120,190,10,*,DOWN,NTRANS
-S 60,10,60,190,10,*,UP,NTRANS
-S 150,30,150,170,30,*,UP,NDIF
-S 90,30,90,170,30,*,UP,NDIF
-S 0,500,300,500,460,*,RIGHT,NWELL
-S 90,100,90,400,20,*,UP,ALU1
-S 90,660,90,900,20,*,UP,ALU1
-S 210,100,210,400,20,*,UP,ALU1
-S 90,220,160,220,20,*,RIGHT,ALU1
-S 150,220,240,220,30,*,RIGHT,POLY
-S 60,220,120,220,30,*,RIGHT,POLY
-S 0,970,300,970,60,vss,RIGHT,CALU1
-S 0,30,300,30,60,vss,RIGHT,CALU1
-S 0,530,300,530,60,vdd,RIGHT,CALU1
-S 0,470,300,470,60,vdd,RIGHT,CALU1
-S 100,150,100,600,20,sel1,UP,CALU3
-S 200,150,200,600,20,sel0,DOWN,CALU3
-V 200,150,CONT_VIA,*
-V 200,150,CONT_VIA2,*
-V 30,900,CONT_BODY_P,*
-V 270,900,CONT_BODY_P,*
-V 90,660,CONT_POLY,*
-V 30,680,CONT_BODY_N,*
-V 270,680,CONT_BODY_N,*
-V 150,680,CONT_BODY_N,*
-V 30,970,CONT_BODY_P,*
-V 150,950,CONT_DIF_N,*
-V 150,900,CONT_DIF_N,*
-V 210,740,CONT_DIF_P,*
-V 210,790,CONT_DIF_P,*
-V 210,600,CONT_DIF_P,*
-V 200,600,CONT_VIA,*
-V 200,600,CONT_VIA2,*
-V 90,600,CONT_DIF_P,*
-V 100,600,CONT_VIA,*
-V 100,600,CONT_VIA2,*
-V 90,400,CONT_DIF_P,*
-V 90,350,CONT_DIF_P,*
-V 100,400,CONT_VIA,*
-V 100,400,CONT_VIA2,*
-V 210,350,CONT_DIF_P,*
-V 210,400,CONT_DIF_P,*
-V 200,400,CONT_VIA,*
-V 200,400,CONT_VIA2,*
-V 270,600,CONT_DIF_P,*
-V 270,550,CONT_DIF_P,*
-V 270,500,CONT_DIF_P,*
-V 270,450,CONT_DIF_P,*
-V 270,350,CONT_DIF_P,*
-V 270,400,CONT_DIF_P,*
-V 150,500,CONT_DIF_P,*
-V 150,400,CONT_DIF_P,*
-V 150,550,CONT_DIF_P,*
-V 150,450,CONT_DIF_P,*
-V 150,350,CONT_DIF_P,*
-V 30,400,CONT_DIF_P,*
-V 30,450,CONT_DIF_P,*
-V 30,500,CONT_DIF_P,*
-V 30,550,CONT_DIF_P,*
-V 30,350,CONT_DIF_P,*
-V 30,600,CONT_DIF_P,*
-V 270,290,CONT_BODY_N,*
-V 30,290,CONT_BODY_N,*
-V 150,290,CONT_BODY_N,*
-V 90,100,CONT_DIF_N,*
-V 90,150,CONT_DIF_N,*
-V 90,900,CONT_DIF_N,*
-V 150,150,CONT_DIF_N,*
-V 150,50,CONT_DIF_N,*
-V 150,100,CONT_DIF_N,*
-V 30,100,CONT_DIF_N,*
-V 30,150,CONT_DIF_N,*
-V 30,50,CONT_DIF_N,*
-V 90,740,CONT_DIF_P,*
-V 150,740,CONT_DIF_P,*
-V 100,150,CONT_VIA2,*
-V 100,150,CONT_VIA,*
-V 210,150,CONT_DIF_N,*
-V 270,150,CONT_DIF_N,*
-V 270,50,CONT_DIF_N,*
-V 210,100,CONT_DIF_N,*
-V 270,100,CONT_DIF_N,*
-V 90,790,CONT_DIF_P,*
-V 270,970,CONT_BODY_P,*
-V 160,220,CONT_POLY,*
-V 150,850,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/dp_sxlib/dp_nmux_x1_buf.vbe b/alliance/share/cells/dp_sxlib/dp_nmux_x1_buf.vbe
deleted file mode 100644
index ad2647df..00000000
--- a/alliance/share/cells/dp_sxlib/dp_nmux_x1_buf.vbe
+++ /dev/null
@@ -1,21 +0,0 @@
-ENTITY dp_nmux_x1_buf IS
-PORT (
-  sel	: in  BIT;
-  sel0	: out BIT;
-  sel1	: out BIT;
-  vdd	: in  BIT;
-  vss	: in  BIT
-);
-END dp_nmux_x1_buf;
-
-ARCHITECTURE vbe OF dp_nmux_x1_buf IS
-
-BEGIN
-  ASSERT (vdd and not vss)
-  REPORT "power supply is missing on dp_nmux_x1_buf"
-  SEVERITY WARNING;
-
-  sel1 <= sel;
-  sel0 <= not sel;
-
-END;
diff --git a/alliance/share/cells/dp_sxlib/dp_nts_x2.ap b/alliance/share/cells/dp_sxlib/dp_nts_x2.ap
deleted file mode 100644
index 58976d1d..00000000
--- a/alliance/share/cells/dp_sxlib/dp_nts_x2.ap
+++ /dev/null
@@ -1,75 +0,0 @@
-V ALLIANCE : 6
-H dp_nts_x2,P,10/11/2000,100
-A 0,0,3000,5000
-R 1000,2000,ref_ref,nenx
-R 2000,2000,ref_ref,enx
-R 1500,2500,ref_ref,nq_25
-R 500,3500,ref_ref,i_35
-R 500,3000,ref_ref,i_30
-R 500,1500,ref_ref,i_15
-R 500,1000,ref_ref,i_10
-R 500,2500,ref_ref,i_25
-R 500,2000,ref_ref,i_20
-R 500,4000,ref_ref,i_40
-R 1500,1500,ref_ref,nq_15
-R 1500,1000,ref_ref,nq_10
-R 1500,4000,ref_ref,nq_40
-R 1500,3500,ref_ref,nq_35
-R 1500,3000,ref_ref,nq_30
-R 1500,2000,ref_ref,nq_20
-S 2700,3000,2700,4700,200,*,UP,ALU1
-S 2700,2800,2700,4200,300,*,DOWN,PDIF
-S 2400,2600,2400,4400,100,*,DOWN,PTRANS
-S 2700,500,2700,1700,200,*,DOWN,ALU1
-S 1000,2000,1000,2500,200,*,DOWN,ALU1
-S 2000,1500,2000,2000,200,*,UP,ALU1
-S 1000,2500,1800,2500,300,*,RIGHT,POLY
-S 500,2000,2400,2000,300,*,RIGHT,POLY
-S 600,1400,600,2600,100,*,DOWN,POLY
-S 1200,2600,1200,4900,100,*,DOWN,PTRANS
-S 300,2800,300,4700,300,*,DOWN,PDIF
-S 900,2800,900,4700,300,*,DOWN,PDIF
-S 2100,2800,2100,4700,300,*,DOWN,PDIF
-S 600,2600,600,4900,100,*,DOWN,PTRANS
-S 1500,300,1500,1200,300,*,UP,NDIF
-S 900,300,900,1200,300,*,UP,NDIF
-S 300,300,300,1200,300,*,UP,NDIF
-S 2700,300,2700,1200,300,*,UP,NDIF
-S 2100,300,2100,1200,300,*,UP,NDIF
-S 600,100,600,1400,100,*,UP,NTRANS
-S 2400,100,2400,1400,100,*,UP,NTRANS
-S 1200,1500,2000,1500,300,*,RIGHT,POLY
-S 1200,100,1200,1400,100,*,UP,NTRANS
-S 1800,2600,1800,4900,100,*,DOWN,PTRANS
-S 1800,100,1800,1400,100,*,UP,NTRANS
-S 0,3900,3000,3900,2400,*,RIGHT,NWELL
-S 1400,2800,1400,4700,300,*,DOWN,PDIF
-S 1000,2000,2000,2000,200,*,RIGHT,TALU2
-S 0,300,3000,300,600,vss,RIGHT,CALU1
-S 1500,1000,1500,4000,200,nq,DOWN,CALU1
-S 500,1000,500,4000,200,i,UP,CALU1
-S 0,4700,3000,4700,600,vdd,RIGHT,CALU1
-S 2000,2000,2000,2000,200,enx,LEFT,CALU3
-S 1000,2000,1000,2000,200,nenx,LEFT,CALU3
-S 2400,1400,2400,2600,100,*,DOWN,POLY
-V 2700,4700,CONT_BODY_N,*
-V 2700,1000,CONT_DIF_N,*
-V 2700,3500,CONT_DIF_P,*
-V 2700,4000,CONT_DIF_P,*
-V 2700,1700,CONT_BODY_P,*
-V 300,4500,CONT_DIF_P,*
-V 2000,2000,CONT_VIA,*
-V 2000,2000,CONT_VIA2,*
-V 1000,2000,CONT_VIA2,*
-V 1000,2000,CONT_VIA,*
-V 1000,2500,CONT_POLY,*
-V 500,2000,CONT_POLY,*
-V 2700,500,CONT_DIF_N,*
-V 300,500,CONT_DIF_N,*
-V 2000,1500,CONT_POLY,*
-V 1500,3500,CONT_DIF_P,*
-V 1500,3000,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 1500,1000,CONT_DIF_N,*
-V 2700,3000,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/dp_sxlib/dp_nts_x2.vbe b/alliance/share/cells/dp_sxlib/dp_nts_x2.vbe
deleted file mode 100644
index 75679a4f..00000000
--- a/alliance/share/cells/dp_sxlib/dp_nts_x2.vbe
+++ /dev/null
@@ -1,28 +0,0 @@
-ENTITY dp_nts_x2 IS
-PORT (
-  enx	 : in  BIT;
-  nenx	 : in  BIT;
-  i	 : in  BIT;
-  nq	 : out MUX_BIT BUS;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END dp_nts_x2;
-
-ARCHITECTURE vbe OF dp_nts_x2 IS
-
-BEGIN
-  ASSERT (vdd and not vss)
-  REPORT "power supply is missing on dp_nts_x2"
-  SEVERITY WARNING;
-
-  ASSERT (enx xor  nenx)
-  REPORT "wrong control signals on dp_nts_x2"
-  SEVERITY WARNING;
-
-  label0 : BLOCK (enx = '1')
-  BEGIN
-    nq <= GUARDED not i;
-  END BLOCK label0;
-
-END;
diff --git a/alliance/share/cells/dp_sxlib/dp_nts_x2_buf.ap b/alliance/share/cells/dp_sxlib/dp_nts_x2_buf.ap
deleted file mode 100644
index 49f920b9..00000000
--- a/alliance/share/cells/dp_sxlib/dp_nts_x2_buf.ap
+++ /dev/null
@@ -1,137 +0,0 @@
-V ALLIANCE : 6
-H dp_nts_x2_buf,P,14/11/2000,10
-A 0,0,300,1000
-R 200,400,ref_ref,enx
-R 100,400,ref_ref,nenx
-S 100,600,200,600,20,*,RIGHT,TALU2
-S 100,400,200,400,20,*,RIGHT,TALU2
-S 100,150,200,150,20,*,RIGHT,TALU2
-S 100,150,100,600,20,nenx,UP,CALU3
-S 200,150,200,600,20,enx,DOWN,CALU3
-S 0,30,300,30,60,vss,RIGHT,CALU1
-S 0,530,300,530,60,vdd,RIGHT,CALU1
-S 0,470,300,470,60,vdd,RIGHT,CALU1
-S 0,970,300,970,60,vss,RIGHT,CALU1
-S 140,220,210,220,20,*,RIGHT,ALU1
-S 60,220,150,220,30,*,RIGHT,POLY
-S 180,220,240,220,30,*,RIGHT,POLY
-S 210,660,210,790,20,*,DOWN,ALU1
-S 90,740,90,900,20,*,UP,ALU1
-S 180,660,240,660,30,*,RIGHT,POLY
-S 180,190,180,320,10,*,DOWN,POLY
-S 240,190,240,320,10,*,UP,POLY
-S 120,190,120,320,10,*,UP,POLY
-S 60,190,60,320,10,*,DOWN,POLY
-S 150,280,150,740,20,*,UP,ALU1
-S 30,900,30,970,20,*,DOWN,ALU1
-S 270,900,270,970,20,*,UP,ALU1
-S 90,790,210,790,20,*,RIGHT,ALU1
-S 120,820,120,870,10,*,DOWN,POLY
-S 180,820,180,860,10,*,DOWN,POLY
-S 120,850,180,850,30,*,RIGHT,POLY
-S 120,870,120,980,10,*,UP,NTRANS
-S 150,890,150,960,30,*,UP,NDIF
-S 90,890,90,960,30,*,UP,NDIF
-S 150,900,150,940,20,*,UP,ALU1
-S 210,730,210,800,30,*,UP,PDIF
-S 180,710,180,820,10,*,DOWN,PTRANS
-S 160,730,160,800,30,*,UP,PDIF
-S 120,710,120,820,10,*,DOWN,PTRANS
-S 90,730,90,800,30,*,UP,PDIF
-S 30,350,30,680,20,*,UP,ALU1
-S 270,280,270,680,20,*,UP,ALU1
-S 180,320,180,650,10,*,UP,PTRANS
-S 210,340,210,630,30,*,UP,PDIF
-S 240,320,240,650,10,*,DOWN,PTRANS
-S 270,340,270,630,30,*,DOWN,PDIF
-S 120,320,120,650,10,*,UP,PTRANS
-S 90,340,90,630,30,*,UP,PDIF
-S 150,340,150,630,30,*,UP,PDIF
-S 60,320,60,650,10,*,UP,PTRANS
-S 30,340,30,630,30,*,UP,PDIF
-S 30,50,30,150,20,*,UP,ALU1
-S 150,50,150,150,20,*,UP,ALU1
-S 270,50,270,150,20,*,UP,ALU1
-S 180,10,180,190,10,*,DOWN,NTRANS
-S 210,30,210,170,30,*,UP,NDIF
-S 240,10,240,190,10,*,DOWN,NTRANS
-S 30,30,30,170,30,*,UP,NDIF
-S 270,30,270,170,30,*,UP,NDIF
-S 120,10,120,190,10,*,DOWN,NTRANS
-S 60,10,60,190,10,*,UP,NTRANS
-S 150,30,150,170,30,*,UP,NDIF
-S 90,30,90,170,30,*,UP,NDIF
-S 0,500,300,500,460,*,RIGHT,NWELL
-S 90,100,90,400,20,*,UP,ALU1
-S 210,100,210,400,20,*,UP,ALU1
-S 150,850,150,850,10,en,LEFT,CALU1
-V 140,220,CONT_POLY,*
-V 210,660,CONT_POLY,*
-V 200,150,CONT_VIA,*
-V 200,150,CONT_VIA2,*
-V 30,900,CONT_BODY_P,*
-V 270,900,CONT_BODY_P,*
-V 30,680,CONT_BODY_N,*
-V 270,680,CONT_BODY_N,*
-V 150,680,CONT_BODY_N,*
-V 30,970,CONT_BODY_P,*
-V 150,950,CONT_DIF_N,*
-V 150,900,CONT_DIF_N,*
-V 210,740,CONT_DIF_P,*
-V 210,790,CONT_DIF_P,*
-V 210,600,CONT_DIF_P,*
-V 200,600,CONT_VIA,*
-V 200,600,CONT_VIA2,*
-V 90,600,CONT_DIF_P,*
-V 100,600,CONT_VIA,*
-V 100,600,CONT_VIA2,*
-V 90,400,CONT_DIF_P,*
-V 90,350,CONT_DIF_P,*
-V 100,400,CONT_VIA,*
-V 100,400,CONT_VIA2,*
-V 210,350,CONT_DIF_P,*
-V 210,400,CONT_DIF_P,*
-V 200,400,CONT_VIA,*
-V 200,400,CONT_VIA2,*
-V 270,600,CONT_DIF_P,*
-V 270,550,CONT_DIF_P,*
-V 270,500,CONT_DIF_P,*
-V 270,450,CONT_DIF_P,*
-V 270,350,CONT_DIF_P,*
-V 270,400,CONT_DIF_P,*
-V 150,500,CONT_DIF_P,*
-V 150,400,CONT_DIF_P,*
-V 150,550,CONT_DIF_P,*
-V 150,450,CONT_DIF_P,*
-V 150,350,CONT_DIF_P,*
-V 30,400,CONT_DIF_P,*
-V 30,450,CONT_DIF_P,*
-V 30,500,CONT_DIF_P,*
-V 30,550,CONT_DIF_P,*
-V 30,350,CONT_DIF_P,*
-V 30,600,CONT_DIF_P,*
-V 270,290,CONT_BODY_N,*
-V 30,290,CONT_BODY_N,*
-V 150,290,CONT_BODY_N,*
-V 90,100,CONT_DIF_N,*
-V 90,150,CONT_DIF_N,*
-V 90,900,CONT_DIF_N,*
-V 150,150,CONT_DIF_N,*
-V 150,50,CONT_DIF_N,*
-V 150,100,CONT_DIF_N,*
-V 30,100,CONT_DIF_N,*
-V 30,150,CONT_DIF_N,*
-V 30,50,CONT_DIF_N,*
-V 90,740,CONT_DIF_P,*
-V 150,740,CONT_DIF_P,*
-V 100,150,CONT_VIA2,*
-V 100,150,CONT_VIA,*
-V 210,150,CONT_DIF_N,*
-V 270,150,CONT_DIF_N,*
-V 270,50,CONT_DIF_N,*
-V 210,100,CONT_DIF_N,*
-V 270,100,CONT_DIF_N,*
-V 90,790,CONT_DIF_P,*
-V 270,970,CONT_BODY_P,*
-V 150,850,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/dp_sxlib/dp_nts_x2_buf.vbe b/alliance/share/cells/dp_sxlib/dp_nts_x2_buf.vbe
deleted file mode 100644
index a853ddec..00000000
--- a/alliance/share/cells/dp_sxlib/dp_nts_x2_buf.vbe
+++ /dev/null
@@ -1,21 +0,0 @@
-ENTITY dp_nts_x2_buf IS
-PORT (
-  en	 : in  BIT;
-  enx	 : out BIT;
-  nenx	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END dp_nts_x2_buf;
-
-ARCHITECTURE vbe OF dp_nts_x2_buf IS
-
-BEGIN
-  ASSERT (vdd and not vss)
-  REPORT "power supply is missing on dp_nts_x2_buf"
-  SEVERITY WARNING;
-
-  enx <= en;
-  nenx <= not en;
-
-END;
diff --git a/alliance/share/cells/dp_sxlib/dp_rom2_buf.ap b/alliance/share/cells/dp_sxlib/dp_rom2_buf.ap
deleted file mode 100644
index 92dbe197..00000000
--- a/alliance/share/cells/dp_sxlib/dp_rom2_buf.ap
+++ /dev/null
@@ -1,73 +0,0 @@
-V ALLIANCE : 6
-H dp_rom2_buf,P,14/11/2000,10
-A 0,0,250,1000
-R 100,400,ref_ref,wenx
-S 40,600,160,600,20,*,RIGHT,TALU2
-S 40,400,160,400,20,*,RIGHT,TALU2
-S 40,150,160,150,20,*,RIGHT,TALU2
-S 160,340,160,630,30,*,UP,PDIF
-S 70,320,70,650,10,*,UP,PTRANS
-S 40,340,40,630,30,*,UP,PDIF
-S 130,320,130,650,10,*,UP,PTRANS
-S 100,340,100,630,30,*,UP,PDIF
-S 130,10,130,190,10,*,DOWN,NTRANS
-S 70,10,70,190,10,*,UP,NTRANS
-S 100,30,100,170,30,*,UP,NDIF
-S 40,30,40,170,30,*,UP,NDIF
-S 160,30,160,170,30,*,UP,NDIF
-S 70,650,70,710,10,*,DOWN,POLY
-S 130,650,130,710,10,*,UP,POLY
-S 130,190,130,320,10,*,UP,POLY
-S 70,190,70,320,10,*,DOWN,POLY
-S 70,220,130,220,30,*,RIGHT,POLY
-S 100,100,100,400,20,*,UP,ALU1
-S 160,50,160,150,20,*,UP,ALU1
-S 40,50,40,150,20,*,UP,ALU1
-S 160,280,160,680,20,*,UP,ALU1
-S 40,290,40,680,20,*,UP,ALU1
-S 100,150,100,600,20,nix,DOWN,CALU3
-S 0,470,250,470,60,vdd,RIGHT,CALU1
-S 0,530,250,530,60,vdd,RIGHT,CALU1
-S 0,500,250,500,460,*,RIGHT,NWELL
-S 0,30,250,30,60,vss,RIGHT,CALU1
-S 0,970,250,970,60,vss,RIGHT,CALU1
-S 220,50,220,150,20,*,UP,ALU1
-S 100,700,100,700,10,i,LEFT,CALU1
-S 70,700,130,700,30,*,RIGHT,POLY
-V 40,550,CONT_DIF_P,*
-V 160,450,CONT_DIF_P,*
-V 160,550,CONT_DIF_P,*
-V 160,400,CONT_DIF_P,*
-V 160,500,CONT_DIF_P,*
-V 160,290,CONT_BODY_N,*
-V 40,290,CONT_BODY_N,*
-V 40,600,CONT_DIF_P,*
-V 40,350,CONT_DIF_P,*
-V 100,350,CONT_DIF_P,*
-V 100,400,CONT_DIF_P,*
-V 100,600,CONT_DIF_P,*
-V 160,680,CONT_BODY_N,*
-V 40,500,CONT_DIF_P,*
-V 40,450,CONT_DIF_P,*
-V 40,400,CONT_DIF_P,*
-V 160,350,CONT_DIF_P,*
-V 160,600,CONT_DIF_P,*
-V 40,680,CONT_BODY_N,*
-V 100,100,CONT_DIF_N,*
-V 40,150,CONT_DIF_N,*
-V 40,100,CONT_DIF_N,*
-V 160,50,CONT_DIF_N,*
-V 160,100,CONT_DIF_N,*
-V 160,150,CONT_DIF_N,*
-V 40,50,CONT_DIF_N,*
-V 100,150,CONT_DIF_N,*
-V 100,600,CONT_VIA,*
-V 100,400,CONT_VIA,*
-V 100,150,CONT_VIA,*
-V 100,600,CONT_VIA2,*
-V 100,150,CONT_VIA2,*
-V 100,400,CONT_VIA2,*
-V 220,30,CONT_BODY_P,*
-V 220,150,CONT_BODY_P,*
-V 100,700,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/dp_sxlib/dp_rom2_buf.vbe b/alliance/share/cells/dp_sxlib/dp_rom2_buf.vbe
deleted file mode 100644
index 2ba6597a..00000000
--- a/alliance/share/cells/dp_sxlib/dp_rom2_buf.vbe
+++ /dev/null
@@ -1,19 +0,0 @@
-ENTITY dp_rom2_buf IS
-PORT (
-  i	: in  BIT;
-  nix	: out BIT;
-  vdd	: in  BIT;
-  vss	: in  BIT
-);
-END dp_rom2_buf;
-
-ARCHITECTURE vbe OF dp_rom2_buf IS
-
-BEGIN
-  ASSERT (vdd and not vss)
-  REPORT "power supply is missing on dp_rom2_buf"
-  SEVERITY WARNING;
-
-  nix <= not i;
-
-END;
diff --git a/alliance/share/cells/dp_sxlib/dp_rom4_buf.ap b/alliance/share/cells/dp_sxlib/dp_rom4_buf.ap
deleted file mode 100644
index f2171b4a..00000000
--- a/alliance/share/cells/dp_sxlib/dp_rom4_buf.ap
+++ /dev/null
@@ -1,248 +0,0 @@
-V ALLIANCE : 6
-H dp_rom4_buf,P, 4/ 8/2000,10
-A 0,0,550,1000
-R 100,400,ref_ref,i0
-R 450,400,ref_ref,ni0
-R 350,400,ref_ref,i1
-R 200,400,ref_ref,ni1
-S 400,850,400,850,10,i1,LEFT,CALU1
-S 150,850,150,850,10,i0,LEFT,CALU1
-S 400,50,400,150,20,*,UP,ALU1
-S 280,50,280,150,20,*,UP,ALU1
-S 520,280,520,680,20,*,UP,ALU1
-S 400,900,400,940,20,*,UP,ALU1
-S 520,900,520,970,20,*,UP,ALU1
-S 460,100,460,400,20,*,UP,ALU1
-S 340,660,340,900,20,*,UP,ALU1
-S 340,100,340,400,20,*,UP,ALU1
-S 520,50,520,150,20,*,UP,ALU1
-S 280,900,280,970,20,*,DOWN,ALU1
-S 400,280,400,740,20,*,UP,ALU1
-S 340,790,460,790,20,*,RIGHT,ALU1
-S 460,740,460,790,20,*,DOWN,ALU1
-S 150,50,150,150,20,*,UP,ALU1
-S 30,50,30,150,20,*,UP,ALU1
-S 430,820,430,860,10,*,DOWN,POLY
-S 370,820,370,870,10,*,DOWN,POLY
-S 310,190,310,320,10,*,DOWN,POLY
-S 370,190,370,320,10,*,UP,POLY
-S 490,190,490,320,10,*,UP,POLY
-S 430,190,430,320,10,*,DOWN,POLY
-S 310,660,370,660,30,*,RIGHT,POLY
-S 370,850,430,850,30,*,RIGHT,POLY
-S 460,30,460,170,30,*,UP,NDIF
-S 340,890,340,960,30,*,UP,NDIF
-S 400,890,400,960,30,*,UP,NDIF
-S 400,30,400,170,30,*,UP,NDIF
-S 520,30,520,170,30,*,UP,NDIF
-S 280,30,280,170,30,*,UP,NDIF
-S 340,30,340,170,30,*,UP,NDIF
-S 210,30,210,170,30,*,UP,NDIF
-S 150,30,150,170,30,*,UP,NDIF
-S 30,30,30,170,30,*,UP,NDIF
-S 90,30,90,170,30,*,UP,NDIF
-S 310,10,310,190,10,*,UP,NTRANS
-S 370,10,370,190,10,*,DOWN,NTRANS
-S 490,10,490,190,10,*,DOWN,NTRANS
-S 430,10,430,190,10,*,DOWN,NTRANS
-S 370,870,370,980,10,*,UP,NTRANS
-S 120,10,120,190,10,*,DOWN,NTRANS
-S 240,10,240,190,10,*,DOWN,NTRANS
-S 180,10,180,190,10,*,DOWN,NTRANS
-S 60,10,60,190,10,*,UP,NTRANS
-S 490,320,490,650,10,*,DOWN,PTRANS
-S 460,340,460,630,30,*,UP,PDIF
-S 430,320,430,650,10,*,UP,PTRANS
-S 340,730,340,800,30,*,UP,PDIF
-S 370,710,370,820,10,*,DOWN,PTRANS
-S 410,730,410,800,30,*,UP,PDIF
-S 430,710,430,820,10,*,DOWN,PTRANS
-S 460,730,460,800,30,*,UP,PDIF
-S 280,340,280,630,30,*,UP,PDIF
-S 310,320,310,650,10,*,UP,PTRANS
-S 400,340,400,630,30,*,UP,PDIF
-S 340,340,340,630,30,*,UP,PDIF
-S 370,320,370,650,10,*,UP,PTRANS
-S 520,340,520,630,30,*,DOWN,PDIF
-S 0,500,550,500,460,*,RIGHT,NWELL
-S 60,660,120,660,30,*,RIGHT,POLY
-S 180,320,180,650,10,*,UP,PTRANS
-S 210,340,210,630,30,*,UP,PDIF
-S 240,320,240,650,10,*,DOWN,PTRANS
-S 90,340,90,630,30,*,UP,PDIF
-S 150,340,150,630,30,*,UP,PDIF
-S 60,320,60,650,10,*,UP,PTRANS
-S 30,340,30,630,30,*,UP,PDIF
-S 270,340,270,630,30,*,DOWN,PDIF
-S 120,320,120,650,10,*,UP,PTRANS
-S 150,900,150,940,20,*,UP,ALU1
-S 210,740,210,790,20,*,DOWN,ALU1
-S 90,790,210,790,20,*,RIGHT,ALU1
-S 30,900,30,970,20,*,DOWN,ALU1
-S 180,820,180,860,10,*,DOWN,POLY
-S 120,820,120,870,10,*,DOWN,POLY
-S 120,850,180,850,30,*,RIGHT,POLY
-S 150,890,150,960,30,*,UP,NDIF
-S 90,890,90,960,30,*,UP,NDIF
-S 120,870,120,980,10,*,UP,NTRANS
-S 120,710,120,820,10,*,DOWN,PTRANS
-S 90,730,90,800,30,*,UP,PDIF
-S 210,730,210,800,30,*,UP,PDIF
-S 180,710,180,820,10,*,DOWN,PTRANS
-S 160,730,160,800,30,*,UP,PDIF
-S 90,660,90,900,20,*,UP,ALU1
-S 60,190,60,320,10,*,DOWN,POLY
-S 120,190,120,320,10,*,DOWN,POLY
-S 180,190,180,320,10,*,DOWN,POLY
-S 240,190,240,320,10,*,DOWN,POLY
-S 450,150,450,600,20,ni0x,DOWN,CALU3
-S 350,150,350,600,20,i1x,UP,CALU3
-S 100,150,100,600,20,i0x,UP,CALU3
-S 200,150,200,600,20,ni1x,UP,CALU3
-S 90,100,90,400,20,*,UP,ALU1
-S 210,100,210,400,20,*,UP,ALU1
-S 30,290,30,680,20,*,UP,ALU1
-S 150,280,150,740,20,*,UP,ALU1
-S 180,250,270,250,30,*,RIGHT,POLY
-S 270,250,340,250,20,*,RIGHT,ALU1
-S 400,200,490,200,30,*,RIGHT,POLY
-S 100,200,400,200,20,*,RIGHT,ALU2
-S 60,250,120,250,30,*,RIGHT,POLY
-S 310,200,370,200,30,*,RIGHT,POLY
-S 70,580,480,580,460,*,RIGHT,NWELL
-S 280,350,280,680,20,*,UP,ALU1
-S 0,970,550,970,60,vss,RIGHT,CALU1
-S 0,30,550,30,60,vss,RIGHT,CALU1
-S 0,470,550,470,60,vdd,RIGHT,CALU1
-S 0,530,550,530,60,vdd,RIGHT,CALU1
-S 100,600,450,600,20,*,RIGHT,TALU2
-S 100,400,450,400,20,*,RIGHT,TALU2
-S 100,200,400,200,20,*,RIGHT,TALU2
-S 100,150,450,150,20,*,RIGHT,TALU2
-V 450,600,CONT_VIA2,*
-V 350,150,CONT_VIA2,*
-V 450,400,CONT_VIA2,*
-V 450,150,CONT_VIA2,*
-V 350,400,CONT_VIA2,*
-V 350,600,CONT_VIA2,*
-V 200,150,CONT_VIA2,*
-V 100,150,CONT_VIA2,*
-V 450,600,CONT_VIA,*
-V 450,400,CONT_VIA,*
-V 350,150,CONT_VIA,*
-V 350,400,CONT_VIA,*
-V 450,150,CONT_VIA,*
-V 350,600,CONT_VIA,*
-V 200,150,CONT_VIA,*
-V 100,150,CONT_VIA,*
-V 400,850,CONT_POLY,*
-V 340,660,CONT_POLY,*
-V 520,970,CONT_BODY_P,*
-V 280,970,CONT_BODY_P,*
-V 520,900,CONT_BODY_P,*
-V 280,900,CONT_BODY_P,*
-V 400,50,CONT_DIF_N,*
-V 400,150,CONT_DIF_N,*
-V 340,900,CONT_DIF_N,*
-V 340,150,CONT_DIF_N,*
-V 340,100,CONT_DIF_N,*
-V 400,900,CONT_DIF_N,*
-V 400,950,CONT_DIF_N,*
-V 460,100,CONT_DIF_N,*
-V 520,50,CONT_DIF_N,*
-V 520,150,CONT_DIF_N,*
-V 460,150,CONT_DIF_N,*
-V 280,50,CONT_DIF_N,*
-V 280,150,CONT_DIF_N,*
-V 280,100,CONT_DIF_N,*
-V 400,100,CONT_DIF_N,*
-V 520,100,CONT_DIF_N,*
-V 210,100,CONT_DIF_N,*
-V 210,150,CONT_DIF_N,*
-V 150,100,CONT_DIF_N,*
-V 150,50,CONT_DIF_N,*
-V 150,150,CONT_DIF_N,*
-V 90,150,CONT_DIF_N,*
-V 90,100,CONT_DIF_N,*
-V 30,150,CONT_DIF_N,*
-V 30,50,CONT_DIF_N,*
-V 30,100,CONT_DIF_N,*
-V 280,680,CONT_BODY_N,*
-V 340,350,CONT_DIF_P,*
-V 340,400,CONT_DIF_P,*
-V 340,600,CONT_DIF_P,*
-V 460,600,CONT_DIF_P,*
-V 460,790,CONT_DIF_P,*
-V 460,740,CONT_DIF_P,*
-V 400,680,CONT_BODY_N,*
-V 520,680,CONT_BODY_N,*
-V 520,400,CONT_DIF_P,*
-V 520,350,CONT_DIF_P,*
-V 520,450,CONT_DIF_P,*
-V 520,500,CONT_DIF_P,*
-V 520,550,CONT_DIF_P,*
-V 520,600,CONT_DIF_P,*
-V 460,400,CONT_DIF_P,*
-V 460,350,CONT_DIF_P,*
-V 280,500,CONT_DIF_P,*
-V 280,450,CONT_DIF_P,*
-V 280,400,CONT_DIF_P,*
-V 400,350,CONT_DIF_P,*
-V 400,450,CONT_DIF_P,*
-V 400,550,CONT_DIF_P,*
-V 400,400,CONT_DIF_P,*
-V 400,500,CONT_DIF_P,*
-V 400,740,CONT_DIF_P,*
-V 340,740,CONT_DIF_P,*
-V 400,290,CONT_BODY_N,*
-V 520,290,CONT_BODY_N,*
-V 280,600,CONT_DIF_P,*
-V 280,350,CONT_DIF_P,*
-V 280,550,CONT_DIF_P,*
-V 340,790,CONT_DIF_P,*
-V 200,400,CONT_VIA2,*
-V 200,600,CONT_VIA2,*
-V 100,600,CONT_VIA2,*
-V 100,400,CONT_VIA2,*
-V 200,400,CONT_VIA,*
-V 200,600,CONT_VIA,*
-V 100,600,CONT_VIA,*
-V 100,400,CONT_VIA,*
-V 90,660,CONT_POLY,*
-V 30,680,CONT_BODY_N,*
-V 210,600,CONT_DIF_P,*
-V 90,600,CONT_DIF_P,*
-V 90,400,CONT_DIF_P,*
-V 90,350,CONT_DIF_P,*
-V 150,680,CONT_BODY_N,*
-V 150,550,CONT_DIF_P,*
-V 150,450,CONT_DIF_P,*
-V 150,350,CONT_DIF_P,*
-V 30,400,CONT_DIF_P,*
-V 30,450,CONT_DIF_P,*
-V 30,500,CONT_DIF_P,*
-V 210,350,CONT_DIF_P,*
-V 210,400,CONT_DIF_P,*
-V 30,600,CONT_DIF_P,*
-V 30,290,CONT_BODY_N,*
-V 150,290,CONT_BODY_N,*
-V 150,500,CONT_DIF_P,*
-V 150,400,CONT_DIF_P,*
-V 30,550,CONT_DIF_P,*
-V 30,350,CONT_DIF_P,*
-V 150,850,CONT_POLY,*
-V 30,900,CONT_BODY_P,*
-V 30,970,CONT_BODY_P,*
-V 150,950,CONT_DIF_N,*
-V 150,900,CONT_DIF_N,*
-V 90,900,CONT_DIF_N,*
-V 210,740,CONT_DIF_P,*
-V 210,790,CONT_DIF_P,*
-V 90,740,CONT_DIF_P,*
-V 150,740,CONT_DIF_P,*
-V 90,790,CONT_DIF_P,*
-V 260,250,CONT_POLY,*
-V 410,200,CONT_POLY,*
-V 400,200,CONT_VIA,*
-V 100,200,CONT_VIA,*
-EOF
diff --git a/alliance/share/cells/dp_sxlib/dp_rom4_buf.vbe b/alliance/share/cells/dp_sxlib/dp_rom4_buf.vbe
deleted file mode 100644
index e19f8fc2..00000000
--- a/alliance/share/cells/dp_sxlib/dp_rom4_buf.vbe
+++ /dev/null
@@ -1,26 +0,0 @@
-ENTITY dp_rom4_buf IS
-PORT (
-  i0	: in  BIT;
-  i1	: in  BIT;
-  i0x	: out BIT;
-  i1x	: out BIT;
-  ni0x	: out BIT;
-  ni1x	: out BIT;
-  vdd	: in  BIT;
-  vss	: in  BIT
-);
-END dp_rom4_buf;
-
-ARCHITECTURE vbe OF dp_rom4_buf IS
-
-BEGIN
-  ASSERT (vdd and not vss)
-  REPORT "power supply is missing on dp_rom4_buf"
-  SEVERITY WARNING;
-
-  i0x <= i0;
-  i1x <= i1;
-  ni0x <= not i0;
-  ni1x <= not i1;
-
-END;
diff --git a/alliance/share/cells/dp_sxlib/dp_rom4_nxr2_x4.ap b/alliance/share/cells/dp_sxlib/dp_rom4_nxr2_x4.ap
deleted file mode 100644
index 3007651c..00000000
--- a/alliance/share/cells/dp_sxlib/dp_rom4_nxr2_x4.ap
+++ /dev/null
@@ -1,124 +0,0 @@
-V ALLIANCE : 6
-H dp_rom4_nxr2_x4,P,27/10/2000,100
-A 0,0,5500,5000
-R 3500,2500,ref_ref,i1x
-R 2000,2000,ref_ref,ni1x
-R 4500,2000,ref_ref,ni0x
-R 1000,2500,ref_ref,i0x
-R 5000,3500,ref_ref,q_35
-R 5000,4000,ref_ref,q_40
-R 5000,2500,ref_ref,q_25
-R 5000,2000,ref_ref,q_20
-R 5000,1500,ref_ref,q_15
-R 5000,1000,ref_ref,q_10
-R 5000,3000,ref_ref,q_30
-S 1700,1500,2000,1500,200,*,LEFT,ALU1
-S 2000,2500,2400,2500,200,*,RIGHT,ALU1
-S 2000,1500,2000,2500,100,*,DOWN,ALU1
-S 3400,2500,3400,3000,100,*,UP,ALU1
-S 3400,2500,3500,2500,100,*,LEFT,ALU1
-S 3500,1500,3500,2500,100,*,UP,ALU1
-S 3400,1500,3500,1500,100,*,RIGHT,ALU1
-S 3400,1000,3400,1500,100,*,DOWN,ALU1
-S 2100,3000,3400,3000,100,*,RIGHT,ALU1
-S 2100,1000,3400,1000,100,*,RIGHT,ALU1
-S 3000,400,3000,1400,100,*,DOWN,NTRANS
-S 2400,400,2400,1400,100,*,DOWN,NTRANS
-S 1800,400,1800,1400,100,*,DOWN,NTRANS
-S 1200,400,1200,1400,100,*,DOWN,NTRANS
-S 2100,600,2100,1200,300,*,UP,NDIF
-S 1500,600,1500,1200,300,*,UP,NDIF
-S 2700,600,2700,1200,300,*,UP,NDIF
-S 3900,1000,5000,1000,200,*,LEFT,ALU1
-S 3900,3000,5000,3000,200,*,RIGHT,ALU1
-S 3900,3000,3900,4000,200,*,DOWN,ALU1
-S 3000,2000,4500,2000,200,*,RIGHT,ALU2
-S 2000,2000,4500,2000,200,*,RIGHT,TALU2
-S 4500,2800,4500,4700,300,*,DOWN,PDIF
-S 4200,2600,4200,4900,100,*,UP,PTRANS
-S 3600,2600,3600,4900,100,*,UP,PTRANS
-S 3900,2800,3900,4700,300,*,DOWN,PDIF
-S 3600,100,3600,1400,100,*,DOWN,NTRANS
-S 4200,100,4200,1400,100,*,DOWN,NTRANS
-S 3900,300,3900,1200,300,*,UP,NDIF
-S 4500,300,4500,1200,300,*,UP,NDIF
-S 3400,1500,4200,1500,300,*,RIGHT,POLY
-S 3600,1400,3600,2600,100,*,DOWN,POLY
-S 4200,1400,4200,2600,100,*,DOWN,POLY
-S 4500,3500,4500,4500,200,*,DOWN,ALU1
-S 5000,1000,5000,4000,200,q,DOWN,CALU1
-S 2500,2500,3500,2500,200,*,RIGHT,ALU2
-S 1000,2500,3500,2500,200,*,RIGHT,TALU2
-S 0,300,5500,300,600,vss,RIGHT,CALU1
-S 0,3900,5500,3900,2400,*,LEFT,NWELL
-S 0,4700,5500,4700,600,vdd,RIGHT,CALU1
-S 900,2800,900,4700,300,*,DOWN,PDIF
-S 1800,2600,1800,4400,100,*,UP,PTRANS
-S 1500,2800,1500,4200,300,*,DOWN,PDIF
-S 2100,2800,2100,4200,300,*,DOWN,PDIF
-S 2400,2600,2400,4400,100,*,UP,PTRANS
-S 2700,2800,2700,4200,300,*,DOWN,PDIF
-S 3000,2600,3000,4400,100,*,UP,PTRANS
-S 1200,2600,1200,4400,100,*,UP,PTRANS
-S 3300,2800,3300,4700,300,*,DOWN,PDIF
-S 3300,300,3300,1200,300,*,UP,NDIF
-S 900,300,900,1200,300,*,UP,NDIF
-S 3000,1400,3000,2600,100,*,DOWN,POLY
-S 1800,2000,1800,2600,100,*,DOWN,POLY
-S 1800,2000,2400,2000,100,*,LEFT,POLY
-S 2400,1400,2400,2000,100,*,DOWN,POLY
-S 1200,1400,1200,2600,100,*,DOWN,POLY
-S 900,3000,900,4500,200,*,DOWN,ALU1
-S 2100,3000,2100,4000,100,*,DOWN,ALU1
-S 900,500,900,1700,200,*,DOWN,ALU1
-S 3300,3500,3300,4500,200,*,DOWN,ALU1
-S 2000,2000,2500,2000,200,*,RIGHT,ALU2
-S 4500,2000,4500,2000,200,ni0x,LEFT,CALU3
-S 2000,2000,2000,2000,200,ni1x,LEFT,CALU3
-S 1000,2500,1000,2500,200,i0x,LEFT,CALU3
-S 3500,2500,3500,2500,200,i1x,LEFT,CALU3
-V 300,300,CONT_BODY_P,*
-V 5200,300,CONT_BODY_P,*
-V 5200,4700,CONT_BODY_N,*
-V 300,4700,CONT_BODY_N,*
-V 4500,2000,CONT_VIA2,*
-V 3500,2500,CONT_VIA2,*
-V 3900,3000,CONT_DIF_P,*
-V 4500,4500,CONT_DIF_P,*
-V 4500,3500,CONT_DIF_P,*
-V 4500,4000,CONT_DIF_P,*
-V 3900,3500,CONT_DIF_P,*
-V 3900,4000,CONT_DIF_P,*
-V 4500,500,CONT_DIF_N,*
-V 3900,1000,CONT_DIF_N,*
-V 3400,1500,CONT_POLY,*
-V 900,3000,CONT_DIF_P,*
-V 2100,3000,CONT_DIF_P,*
-V 3300,4500,CONT_DIF_P,*
-V 3300,4000,CONT_DIF_P,*
-V 3300,3500,CONT_DIF_P,*
-V 900,4500,CONT_DIF_P,*
-V 900,3500,CONT_DIF_P,*
-V 900,4000,CONT_DIF_P,*
-V 2100,4000,CONT_DIF_P,*
-V 2700,4700,CONT_BODY_N,*
-V 2100,4700,CONT_BODY_N,*
-V 1500,4700,CONT_BODY_N,*
-V 2100,3500,CONT_DIF_P,*
-V 900,500,CONT_DIF_N,*
-V 900,1000,CONT_DIF_N,*
-V 2100,1000,CONT_DIF_N,*
-V 3300,500,CONT_DIF_N,*
-V 900,1700,CONT_BODY_P,*
-V 3000,2000,CONT_POLY,*
-V 1100,2500,CONT_POLY,*
-V 1700,1500,CONT_POLY,*
-V 2500,2500,CONT_POLY,*
-V 2500,2000,CONT_POLY,*
-V 3000,2000,CONT_VIA,*
-V 2500,2000,CONT_VIA,*
-V 2500,2500,CONT_VIA,*
-V 1000,2500,CONT_VIA,*
-V 2000,2000,CONT_VIA2,*
-V 1000,2500,CONT_VIA2,*
-EOF
diff --git a/alliance/share/cells/dp_sxlib/dp_rom4_nxr2_x4.vbe b/alliance/share/cells/dp_sxlib/dp_rom4_nxr2_x4.vbe
deleted file mode 100644
index f7c6d3b2..00000000
--- a/alliance/share/cells/dp_sxlib/dp_rom4_nxr2_x4.vbe
+++ /dev/null
@@ -1,30 +0,0 @@
-ENTITY dp_rom4_nxr2_x4 IS
-PORT (
-  i0x	: in  BIT;
-  i1x	: in  BIT;
-  ni0x	: in  BIT;
-  ni1x	: in  BIT;
-  q	: out BIT;
-  vdd	: in  BIT;
-  vss	: in  BIT
-);
-END dp_rom4_nxr2_x4;
-
-ARCHITECTURE vbe OF dp_rom4_nxr2_x4 IS
-
-BEGIN
-  ASSERT (vdd and not vss)
-  REPORT "power supply is missing on dp_rom4_nxr2_x4"
-  SEVERITY WARNING;
-
-  ASSERT (i0x xor ni0x)
-  REPORT "wrong control signals on dp_rom4_nxr2_x4"
-  SEVERITY WARNING;
-
-  ASSERT (i1x xor ni1x)
-  REPORT "wrong control signals on dp_rom4_nxr2_x4"
-  SEVERITY WARNING;
-
-  q <= not (i0x xor i1x);
-
-END;
diff --git a/alliance/share/cells/dp_sxlib/dp_rom4_xr2_x4.ap b/alliance/share/cells/dp_sxlib/dp_rom4_xr2_x4.ap
deleted file mode 100644
index e86dd575..00000000
--- a/alliance/share/cells/dp_sxlib/dp_rom4_xr2_x4.ap
+++ /dev/null
@@ -1,124 +0,0 @@
-V ALLIANCE : 6
-H dp_rom4_xr2_x4,P,27/10/2000,100
-A 0,0,5500,5000
-R 4500,2000,ref_ref,ni0x
-R 2100,2000,ref_ref,ni1x
-R 3500,2500,ref_ref,i1x
-R 1000,2500,ref_ref,i0x
-R 5000,3000,ref_ref,q_30
-R 5000,1000,ref_ref,q_10
-R 5000,1500,ref_ref,q_15
-R 5000,2000,ref_ref,q_20
-R 5000,2500,ref_ref,q_25
-R 5000,4000,ref_ref,q_40
-R 5000,3500,ref_ref,q_35
-S 3400,2500,3400,3000,100,*,UP,ALU1
-S 3400,2500,3500,2500,100,*,RIGHT,ALU1
-S 3500,1500,3500,2500,100,*,UP,ALU1
-S 3400,1500,3500,1500,100,*,RIGHT,ALU1
-S 3400,1000,3400,1500,100,*,DOWN,ALU1
-S 2000,1500,2500,1500,200,*,LEFT,ALU1
-S 1700,2500,2000,2500,200,*,RIGHT,ALU1
-S 2000,1500,2000,2500,100,*,DOWN,ALU1
-S 2000,2000,2000,2000,200,ni1x,LEFT,CALU3
-S 4500,2000,4500,2000,200,ni0x,LEFT,CALU3
-S 2000,2000,2500,2000,200,*,RIGHT,ALU2
-S 3300,3500,3300,4500,200,*,DOWN,ALU1
-S 900,500,900,1700,200,*,DOWN,ALU1
-S 2100,3000,2100,4000,100,*,DOWN,ALU1
-S 900,3000,900,4500,200,*,DOWN,ALU1
-S 1200,1400,1200,2600,100,*,DOWN,POLY
-S 1800,2000,2400,2000,100,*,LEFT,POLY
-S 3000,1400,3000,2600,100,*,DOWN,POLY
-S 900,300,900,1200,300,*,UP,NDIF
-S 3300,300,3300,1200,300,*,UP,NDIF
-S 3300,2800,3300,4700,300,*,DOWN,PDIF
-S 1200,2600,1200,4400,100,*,UP,PTRANS
-S 3000,2600,3000,4400,100,*,UP,PTRANS
-S 2700,2800,2700,4200,300,*,DOWN,PDIF
-S 2400,2600,2400,4400,100,*,UP,PTRANS
-S 2100,2800,2100,4200,300,*,DOWN,PDIF
-S 1500,2800,1500,4200,300,*,DOWN,PDIF
-S 1800,2600,1800,4400,100,*,UP,PTRANS
-S 900,2800,900,4700,300,*,DOWN,PDIF
-S 0,4700,5500,4700,600,vdd,RIGHT,CALU1
-S 0,3900,5500,3900,2400,*,LEFT,NWELL
-S 0,300,5500,300,600,vss,RIGHT,CALU1
-S 1000,2500,3500,2500,200,*,RIGHT,TALU2
-S 5000,1000,5000,4000,200,q,DOWN,CALU1
-S 4500,3500,4500,4500,200,*,DOWN,ALU1
-S 4200,1400,4200,2600,100,*,DOWN,POLY
-S 3600,1400,3600,2600,100,*,DOWN,POLY
-S 3400,1500,4200,1500,300,*,RIGHT,POLY
-S 4500,300,4500,1200,300,*,UP,NDIF
-S 3900,300,3900,1200,300,*,UP,NDIF
-S 4200,100,4200,1400,100,*,DOWN,NTRANS
-S 3600,100,3600,1400,100,*,DOWN,NTRANS
-S 3900,2800,3900,4700,300,*,DOWN,PDIF
-S 3600,2600,3600,4900,100,*,UP,PTRANS
-S 4200,2600,4200,4900,100,*,UP,PTRANS
-S 4500,2800,4500,4700,300,*,DOWN,PDIF
-S 2000,2000,4500,2000,200,*,RIGHT,TALU2
-S 3000,2000,4500,2000,200,*,RIGHT,ALU2
-S 2100,1000,3400,1000,100,*,RIGHT,ALU1
-S 2100,3000,3400,3000,100,*,RIGHT,ALU1
-S 3900,3000,3900,4000,200,*,DOWN,ALU1
-S 3900,3000,5000,3000,200,*,RIGHT,ALU1
-S 3900,1000,5000,1000,200,*,LEFT,ALU1
-S 2700,600,2700,1200,300,*,UP,NDIF
-S 1500,600,1500,1200,300,*,UP,NDIF
-S 2100,600,2100,1200,300,*,UP,NDIF
-S 1200,400,1200,1400,100,*,DOWN,NTRANS
-S 1800,400,1800,1400,100,*,DOWN,NTRANS
-S 2400,400,2400,1400,100,*,DOWN,NTRANS
-S 3000,400,3000,1400,100,*,DOWN,NTRANS
-S 2400,2000,2400,2600,100,*,DOWN,POLY
-S 1800,1400,1800,2000,100,*,DOWN,POLY
-S 1700,2500,3500,2500,200,*,RIGHT,ALU2
-S 3500,2500,3500,2500,200,i1x,LEFT,CALU3
-S 1000,2500,1000,2500,200,i0x,LEFT,CALU3
-V 1000,2500,CONT_VIA2,*
-V 2000,2000,CONT_VIA2,*
-V 1000,2500,CONT_VIA,*
-V 2500,2000,CONT_VIA,*
-V 3000,2000,CONT_VIA,*
-V 2500,2000,CONT_POLY,*
-V 1100,2500,CONT_POLY,*
-V 3000,2000,CONT_POLY,*
-V 900,1700,CONT_BODY_P,*
-V 3300,500,CONT_DIF_N,*
-V 2100,1000,CONT_DIF_N,*
-V 900,1000,CONT_DIF_N,*
-V 900,500,CONT_DIF_N,*
-V 2100,3500,CONT_DIF_P,*
-V 1500,4700,CONT_BODY_N,*
-V 2100,4700,CONT_BODY_N,*
-V 2700,4700,CONT_BODY_N,*
-V 2100,4000,CONT_DIF_P,*
-V 900,4000,CONT_DIF_P,*
-V 900,3500,CONT_DIF_P,*
-V 900,4500,CONT_DIF_P,*
-V 3300,3500,CONT_DIF_P,*
-V 3300,4000,CONT_DIF_P,*
-V 3300,4500,CONT_DIF_P,*
-V 2100,3000,CONT_DIF_P,*
-V 900,3000,CONT_DIF_P,*
-V 3400,1500,CONT_POLY,*
-V 3900,1000,CONT_DIF_N,*
-V 4500,500,CONT_DIF_N,*
-V 3900,4000,CONT_DIF_P,*
-V 3900,3500,CONT_DIF_P,*
-V 4500,4000,CONT_DIF_P,*
-V 4500,3500,CONT_DIF_P,*
-V 4500,4500,CONT_DIF_P,*
-V 3900,3000,CONT_DIF_P,*
-V 3500,2500,CONT_VIA2,*
-V 4500,2000,CONT_VIA2,*
-V 300,4700,CONT_BODY_N,*
-V 5200,4700,CONT_BODY_N,*
-V 5200,300,CONT_BODY_P,*
-V 300,300,CONT_BODY_P,*
-V 1700,2500,CONT_POLY,*
-V 2500,1500,CONT_POLY,*
-V 1700,2500,CONT_VIA,*
-EOF
diff --git a/alliance/share/cells/dp_sxlib/dp_rom4_xr2_x4.vbe b/alliance/share/cells/dp_sxlib/dp_rom4_xr2_x4.vbe
deleted file mode 100644
index ff955028..00000000
--- a/alliance/share/cells/dp_sxlib/dp_rom4_xr2_x4.vbe
+++ /dev/null
@@ -1,30 +0,0 @@
-ENTITY dp_rom4_xr2_x4 IS
-PORT (
-  i0x	: in  BIT;
-  i1x	: in  BIT;
-  ni0x	: in  BIT;
-  ni1x	: in  BIT;
-  q	: out BIT;
-  vdd	: in  BIT;
-  vss	: in  BIT
-);
-END dp_rom4_xr2_x4;
-
-ARCHITECTURE vbe OF dp_rom4_xr2_x4 IS
-
-BEGIN
-  ASSERT (vdd and not vss)
-  REPORT "power supply is missing on dp_rom4_xr2_x4"
-  SEVERITY WARNING;
-
-  ASSERT (i0x xor ni0x)
-  REPORT "wrong control signals on dp_rom4_xr2_x4"
-  SEVERITY WARNING;
-
-  ASSERT (i1x xor ni1x)
-  REPORT "wrong control signals on dp_rom4_xr2_x4"
-  SEVERITY WARNING;
-
-  q <= i0x xor i1x;
-
-END;
diff --git a/alliance/share/cells/dp_sxlib/dp_sff_scan_x4.ap b/alliance/share/cells/dp_sxlib/dp_sff_scan_x4.ap
deleted file mode 100644
index bd78b215..00000000
--- a/alliance/share/cells/dp_sxlib/dp_sff_scan_x4.ap
+++ /dev/null
@@ -1,277 +0,0 @@
-V ALLIANCE : 6
-H dp_sff_scan_x4,P,14/11/2000,10
-A 0,0,1200,500
-R 1100,200,ref_ref,q_20
-R 1100,100,ref_ref,q_10
-R 1100,400,ref_ref,q_40
-R 1100,350,ref_ref,q_35
-R 1100,300,ref_ref,q_30
-R 1100,250,ref_ref,q_25
-R 1100,150,ref_ref,q_15
-R 100,100,ref_ref,i_10
-R 100,300,ref_ref,i_30
-R 100,350,ref_ref,i_35
-R 100,200,ref_ref,i_20
-R 100,150,ref_ref,i_15
-R 100,400,ref_ref,i_40
-R 150,200,ref_ref,nwenx
-R 250,200,ref_ref,wenx
-R 400,250,ref_ref,nscanx
-R 500,250,ref_ref,scanx
-R 650,250,ref_ref,nckx
-R 750,250,ref_ref,ckx
-S 150,200,250,200,20,*,RIGHT,TALU2
-S 250,200,250,200,20,wenx,LEFT,CALU3
-S 150,200,150,200,20,nwenx,LEFT,CALU3
-S 400,250,400,250,20,nscanx,LEFT,CALU3
-S 500,250,500,250,20,scanx,LEFT,CALU3
-S 650,250,650,250,20,nckx,LEFT,CALU3
-S 750,250,750,250,20,ckx,LEFT,CALU3
-S 50,250,350,250,20,*,RIGHT,ALU2
-S 1170,300,1170,450,20,*,DOWN,ALU1
-S 650,300,700,300,10,*,RIGHT,ALU1
-S 700,200,700,300,10,*,UP,ALU1
-S 600,150,600,400,10,u,DOWN,ALU1
-S 690,350,750,350,10,*,RIGHT,ALU1
-S 1170,50,1170,100,20,*,DOWN,ALU1
-S 930,400,990,400,10,*,RIGHT,ALU1
-S 750,150,820,150,10,*,LEFT,ALU1
-S 930,200,930,350,10,*,DOWN,ALU1
-S 750,300,820,300,10,*,RIGHT,ALU1
-S 1050,300,1050,450,20,*,DOWN,ALU1
-S 990,100,990,400,10,z,DOWN,ALU1
-S 930,100,990,100,10,*,RIGHT,ALU1
-S 690,100,750,100,10,*,RIGHT,ALU1
-S 800,100,870,100,10,*,RIGHT,ALU1
-S 750,100,750,350,10,x,DOWN,ALU1
-S 870,100,870,400,10,y,DOWN,ALU1
-S 800,350,870,350,10,*,LEFT,ALU1
-S 1050,50,1050,100,20,*,DOWN,ALU1
-S 400,100,500,100,10,*,RIGHT,ALU1
-S 450,400,600,400,10,*,RIGHT,ALU1
-S 500,100,500,300,10,*,DOWN,ALU1
-S 450,150,450,400,10,*,DOWN,ALU1
-S 800,200,800,250,10,*,DOWN,ALU1
-S 400,100,400,150,10,*,UP,ALU1
-S 350,150,350,300,10,*,DOWN,ALU1
-S 250,300,250,400,10,*,UP,ALU1
-S 300,150,300,300,10,*,UP,ALU1
-S 150,400,250,400,10,*,RIGHT,ALU1
-S 200,100,200,350,10,*,UP,ALU1
-S 150,150,150,400,10,*,DOWN,ALU1
-S 30,100,30,350,10,*,DOWN,ALU1
-S 30,250,50,250,30,*,RIGHT,ALU1
-S 810,300,840,300,30,*,RIGHT,POLY
-S 930,350,960,350,30,*,RIGHT,POLY
-S 780,350,810,350,30,*,RIGHT,POLY
-S 810,150,840,150,30,*,RIGHT,POLY
-S 720,250,720,310,10,*,DOWN,POLY
-S 1140,140,1140,260,10,*,DOWN,POLY
-S 900,140,900,200,10,*,DOWN,POLY
-S 840,300,840,360,10,*,DOWN,POLY
-S 1020,250,1050,250,30,*,RIGHT,POLY
-S 900,250,900,360,10,*,DOWN,POLY
-S 720,140,720,200,10,*,DOWN,POLY
-S 900,200,930,200,30,*,RIGHT,POLY
-S 690,200,720,200,30,*,RIGHT,POLY
-S 960,140,960,250,10,*,DOWN,POLY
-S 1080,140,1080,260,10,*,DOWN,POLY
-S 840,90,840,150,10,*,UP,POLY
-S 780,100,810,100,30,*,RIGHT,POLY
-S 1020,150,1050,150,30,*,RIGHT,POLY
-S 500,140,500,250,10,*,DOWN,POLY
-S 400,250,500,250,10,*,RIGHT,POLY
-S 650,250,960,250,10,nckx,RIGHT,POLY
-S 700,200,900,200,10,ckx,RIGHT,POLY
-S 660,140,660,250,10,*,UP,POLY
-S 400,250,400,310,10,*,DOWN,POLY
-S 160,90,160,150,10,*,DOWN,POLY
-S 90,300,120,300,30,*,RIGHT,POLY
-S 260,90,260,250,10,*,DOWN,POLY
-S 90,100,120,100,30,*,RIGHT,POLY
-S 300,90,300,150,10,*,DOWN,POLY
-S 160,250,160,310,10,*,DOWN,POLY
-S 160,250,260,250,10,*,RIGHT,POLY
-S 60,200,200,200,10,*,RIGHT,POLY
-S 60,90,60,310,10,*,DOWN,POLY
-S 1110,30,1110,120,30,*,DOWN,NDIF
-S 1170,30,1170,120,30,*,DOWN,NDIF
-S 990,80,990,120,30,*,DOWN,NDIF
-S 930,80,930,120,30,*,DOWN,NDIF
-S 690,80,690,120,30,*,DOWN,NDIF
-S 750,30,750,120,30,*,DOWN,NDIF
-S 630,80,630,120,30,*,DOWN,NDIF
-S 570,40,570,120,30,*,DOWN,NDIF
-S 450,80,450,160,30,*,DOWN,NDIF
-S 570,40,570,120,30,*,UP,NDIF
-S 870,30,870,70,30,*,DOWN,NDIF
-S 810,30,810,70,30,*,DOWN,NDIF
-S 870,30,870,120,30,*,DOWN,NDIF
-S 1050,30,1050,120,30,*,DOWN,NDIF
-S 330,30,330,120,30,*,UP,NDIF
-S 450,80,450,120,60,*,DOWN,NDIF
-S 30,30,30,110,30,*,UP,NDIF
-S 200,30,200,110,30,*,DOWN,NDIF
-S 90,30,90,70,30,*,DOWN,NDIF
-S 220,30,220,70,50,*,DOWN,NDIF
-S 720,60,720,140,10,*,UP,NTRANS
-S 600,60,600,140,10,*,UP,NTRANS
-S 1080,10,1080,140,10,*,UP,NTRANS
-S 900,60,900,140,10,*,UP,NTRANS
-S 660,60,660,140,10,*,UP,NTRANS
-S 1140,10,1140,140,10,*,UP,NTRANS
-S 1020,60,1020,140,10,*,UP,NTRANS
-S 960,60,960,140,10,*,UP,NTRANS
-S 400,60,400,140,10,*,UP,NTRANS
-S 360,60,360,140,10,*,UP,NTRANS
-S 500,60,500,140,10,*,UP,NTRANS
-S 540,60,540,140,10,*,UP,NTRANS
-S 840,10,840,90,10,*,UP,NTRANS
-S 780,10,780,90,10,*,UP,NTRANS
-S 260,10,260,90,10,*,UP,NTRANS
-S 300,10,300,90,10,*,UP,NTRANS
-S 160,10,160,90,10,*,UP,NTRANS
-S 120,10,120,90,10,*,UP,NTRANS
-S 60,10,60,90,10,*,UP,NTRANS
-S 1140,260,1140,490,10,*,DOWN,PTRANS
-S 1170,280,1170,470,30,*,DOWN,PDIF
-S 660,310,660,440,10,*,DOWN,PTRANS
-S 690,330,690,420,30,*,UP,PDIF
-S 720,310,720,440,10,*,DOWN,PTRANS
-S 750,330,750,470,30,*,UP,PDIF
-S 1080,260,1080,490,10,*,DOWN,PTRANS
-S 1050,280,1050,470,30,*,DOWN,PDIF
-S 930,380,930,470,30,*,DOWN,PDIF
-S 960,360,960,490,10,*,DOWN,PTRANS
-S 800,380,800,470,30,*,DOWN,PDIF
-S 990,380,990,470,30,*,UP,PDIF
-S 1020,360,1020,490,10,*,DOWN,PTRANS
-S 780,360,780,490,10,*,DOWN,PTRANS
-S 840,360,840,490,10,*,UP,PTRANS
-S 1110,280,1110,470,30,*,DOWN,PDIF
-S 600,310,600,440,10,*,DOWN,PTRANS
-S 630,330,630,420,30,*,UP,PDIF
-S 540,310,540,440,10,*,DOWN,PTRANS
-S 570,330,570,460,30,*,DOWN,PDIF
-S 500,310,500,440,10,*,DOWN,PTRANS
-S 860,380,860,470,30,*,DOWN,PDIF
-S 900,360,900,490,10,*,DOWN,PTRANS
-S 450,330,450,420,60,*,DOWN,PDIF
-S 400,310,400,440,10,*,DOWN,PTRANS
-S 360,310,360,440,10,*,DOWN,PTRANS
-S 330,330,330,460,30,*,DOWN,PDIF
-S 160,310,160,440,10,*,DOWN,PTRANS
-S 120,310,120,440,10,*,DOWN,PTRANS
-S 60,310,60,440,10,*,DOWN,PTRANS
-S 30,330,30,420,30,*,DOWN,PDIF
-S 0,390,1200,390,240,*,RIGHT,NWELL
-S 260,310,260,440,10,*,DOWN,PTRANS
-S 300,310,300,440,10,*,DOWN,PTRANS
-S 90,330,90,460,30,*,DOWN,PDIF
-S 210,330,210,420,60,*,UP,PDIF
-S 750,250,800,250,20,*,RIGHT,ALU2
-S 1020,240,1020,360,10,*,DOWN,POLY
-S 990,200,1040,200,10,*,RIGHT,ALU1
-S 1040,200,1140,200,30,*,RIGHT,POLY
-S 0,30,1200,30,60,vss,RIGHT,CALU1
-S 0,470,1200,470,60,vdd,RIGHT,CALU1
-S 50,250,800,250,20,*,RIGHT,TALU2
-S 300,200,1100,200,20,q,RIGHT,CALU2
-S 550,150,550,300,10,scin,DOWN,CALU1
-S 100,100,100,400,20,i,DOWN,CALU1
-S 1100,100,1100,400,20,q,DOWN,CALU1
-S 1040,150,1100,150,10,*,RIGHT,ALU1
-S 1040,250,1100,250,10,*,RIGHT,ALU1
-V 650,250,CONT_VIA2,*
-V 500,250,CONT_VIA2,*
-V 400,250,CONT_VIA2,*
-V 250,200,CONT_VIA2,*
-V 150,200,CONT_VIA2,*
-V 400,250,CONT_VIA,*
-V 650,250,CONT_VIA,*
-V 800,250,CONT_VIA,*
-V 350,250,CONT_VIA,*
-V 500,250,CONT_VIA,*
-V 300,200,CONT_VIA,*
-V 50,250,CONT_VIA,*
-V 150,200,CONT_VIA,*
-V 250,200,CONT_VIA,*
-V 650,300,CONT_POLY,*
-V 1040,250,CONT_POLY,*
-V 1040,150,CONT_POLY,*
-V 820,150,CONT_POLY,*
-V 920,200,CONT_POLY,*
-V 820,300,CONT_POLY,*
-V 700,200,CONT_POLY,*
-V 940,350,CONT_POLY,*
-V 600,150,CONT_POLY,*
-V 650,250,CONT_POLY,*
-V 550,300,CONT_POLY,*
-V 600,300,CONT_POLY,*
-V 550,150,CONT_POLY,*
-V 500,300,CONT_POLY,*
-V 800,100,CONT_POLY,*
-V 800,350,CONT_POLY,*
-V 350,150,CONT_POLY,*
-V 800,200,CONT_POLY,*
-V 400,250,CONT_POLY,*
-V 400,150,CONT_POLY,*
-V 350,300,CONT_POLY,*
-V 250,200,CONT_POLY,*
-V 200,200,CONT_POLY,*
-V 300,300,CONT_POLY,*
-V 150,150,CONT_POLY,*
-V 100,300,CONT_POLY,*
-V 300,150,CONT_POLY,*
-V 250,300,CONT_POLY,*
-V 100,100,CONT_POLY,*
-V 650,30,CONT_BODY_P,*
-V 400,30,CONT_BODY_P,*
-V 500,30,CONT_BODY_P,*
-V 930,30,CONT_BODY_P,*
-V 990,30,CONT_BODY_P,*
-V 330,50,CONT_DIF_N,*
-V 1050,100,CONT_DIF_N,*
-V 1110,100,CONT_DIF_N,*
-V 570,50,CONT_DIF_N,*
-V 450,150,CONT_DIF_N,*
-V 930,100,CONT_DIF_N,*
-V 810,50,CONT_DIF_N,*
-V 690,100,CONT_DIF_N,*
-V 870,100,CONT_DIF_N,*
-V 1170,50,CONT_DIF_N,*
-V 1050,50,CONT_DIF_N,*
-V 1170,100,CONT_DIF_N,*
-V 200,100,CONT_DIF_N,*
-V 90,50,CONT_DIF_N,*
-V 30,100,CONT_DIF_N,*
-V 650,470,CONT_BODY_N,*
-V 1050,350,CONT_DIF_P,*
-V 1050,400,CONT_DIF_P,*
-V 1170,450,CONT_DIF_P,*
-V 1050,450,CONT_DIF_P,*
-V 1050,300,CONT_DIF_P,*
-V 1170,400,CONT_DIF_P,*
-V 1170,350,CONT_DIF_P,*
-V 1110,400,CONT_DIF_P,*
-V 930,400,CONT_DIF_P,*
-V 810,450,CONT_DIF_P,*
-V 1110,350,CONT_DIF_P,*
-V 690,350,CONT_DIF_P,*
-V 330,450,CONT_DIF_P,*
-V 400,470,CONT_BODY_N,*
-V 450,350,CONT_DIF_P,*
-V 570,450,CONT_DIF_P,*
-V 500,470,CONT_BODY_N,*
-V 870,400,CONT_DIF_P,*
-V 1170,300,CONT_DIF_P,*
-V 1110,300,CONT_DIF_P,*
-V 30,350,CONT_DIF_P,*
-V 250,470,CONT_BODY_N,*
-V 150,470,CONT_BODY_N,*
-V 200,350,CONT_DIF_P,*
-V 90,450,CONT_DIF_P,*
-V 750,250,CONT_VIA2,*
-V 1040,200,CONT_POLY,*
-V 1100,200,CONT_VIA,*
-EOF
diff --git a/alliance/share/cells/dp_sxlib/dp_sff_scan_x4.vbe b/alliance/share/cells/dp_sxlib/dp_sff_scan_x4.vbe
deleted file mode 100644
index ed25a65d..00000000
--- a/alliance/share/cells/dp_sxlib/dp_sff_scan_x4.vbe
+++ /dev/null
@@ -1,43 +0,0 @@
-ENTITY dp_sff_scan_x4 IS
-PORT (
-  ckx		: in  BIT;
-  nckx		: in  BIT;
-  wenx		: in  BIT;
-  nwenx		: in  BIT;
-  scanx		: in  BIT;
-  nscanx	: in  BIT;
-  i   		: in  BIT;
-  scin		: in  BIT;
-  q		: out BIT;
-  vdd		: in  BIT;
-  vss		: in  BIT
-);
-END dp_sff_scan_x4;
-
-ARCHITECTURE vbe OF dp_sff_scan_x4 IS
-  SIGNAL ff : REG_BIT REGISTER;
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on dp_sff_scan_x4"
-  SEVERITY WARNING;
-
-  ASSERT (ckx xor nckx)
-  REPORT "wrong values for ckx and nckx in dp_sff_scan_x4"
-  SEVERITY WARNING;
-
-  ASSERT (wenx xor nwenx)
-  REPORT "wrong values for wenx and nwenx in dp_sff_scan_x4"
-  SEVERITY WARNING;
-
-  ASSERT (scanx xor nscanx)
-  REPORT "wrong values for scanx and nscanx in dp_sff_scan_x4"
-  SEVERITY WARNING;
-
-  label0 : BLOCK ((ckx and not (ckx'STABLE)) = '1')
-  BEGIN
-    ff <= GUARDED ((scanx and scin) or (nscanx and ((wenx and i) or (nwenx and ff))));
-  END BLOCK label0;
-
-  q <= ff;
-END;
diff --git a/alliance/share/cells/dp_sxlib/dp_sff_scan_x4_buf.ap b/alliance/share/cells/dp_sxlib/dp_sff_scan_x4_buf.ap
deleted file mode 100644
index ef9bd6df..00000000
--- a/alliance/share/cells/dp_sxlib/dp_sff_scan_x4_buf.ap
+++ /dev/null
@@ -1,403 +0,0 @@
-V ALLIANCE : 6
-H dp_sff_scan_x4_buf,P,16/11/2000,100
-A 0,0,12000,10000
-R 9000,6500,ref_ref,scin
-R 10500,4000,ref_ref,scout_40
-R 10500,3500,ref_ref,scout_35
-R 10500,3000,ref_ref,scout_30
-R 10500,2500,ref_ref,scout_25
-R 10500,2000,ref_ref,scout_20
-R 10500,1500,ref_ref,scout_15
-R 10500,1000,ref_ref,scout_10
-R 1500,4000,ref_ref,nwenx
-R 2500,4000,ref_ref,wenx
-R 4000,4000,ref_ref,nscanx
-R 5000,4000,ref_ref,scanx
-R 6500,4000,ref_ref,nckx
-R 7500,4000,ref_ref,ckx
-S 7500,1500,7500,6000,200,ckx,DOWN,CALU3
-S 9000,6500,9000,6500,100,scin,LEFT,CALU1
-S 2000,8500,2000,8500,100,wen,LEFT,CALU1
-S 4500,8500,4500,8500,100,scan,LEFT,CALU1
-S 7000,8500,7000,8500,100,ck,LEFT,CALU1
-S 9000,6500,9600,6500,100,*,RIGHT,POLY
-S 9600,4300,9600,6500,100,*,DOWN,POLY
-S 9300,1400,9300,1700,300,*,UP,NDIF
-S 9600,1200,9600,1900,100,*,DOWN,NTRANS
-S 9300,3400,9300,4100,300,*,DOWN,PDIF
-S 9600,3200,9600,4300,100,*,UP,PTRANS
-S 1900,2200,2600,2200,200,*,RIGHT,ALU1
-S 1100,2200,1900,2200,300,*,RIGHT,POLY
-S 2300,2200,2900,2200,300,*,RIGHT,POLY
-S 2600,6600,2600,7900,200,*,DOWN,ALU1
-S 1400,7400,1400,9000,200,*,UP,ALU1
-S 2300,6600,2900,6600,300,*,RIGHT,POLY
-S 0,5000,12000,5000,4600,*,RIGHT,NWELL
-S 3200,9000,3200,9700,200,*,UP,ALU1
-S 2600,1000,2600,4000,200,*,UP,ALU1
-S 1400,1000,1400,4000,200,*,UP,ALU1
-S 3200,500,3200,1500,200,*,UP,ALU1
-S 800,9000,800,9700,200,*,DOWN,ALU1
-S 2000,2800,2000,7400,200,*,UP,ALU1
-S 2000,500,2000,1500,200,*,UP,ALU1
-S 800,500,800,1500,200,*,UP,ALU1
-S 3200,2800,3200,6800,200,*,UP,ALU1
-S 800,3500,800,6800,200,*,UP,ALU1
-S 2000,9000,2000,9400,200,*,UP,ALU1
-S 1400,7900,2600,7900,200,*,RIGHT,ALU1
-S 5700,2800,5700,6800,200,*,UP,ALU1
-S 4500,500,4500,1500,200,*,UP,ALU1
-S 5700,500,5700,1500,200,*,UP,ALU1
-S 3900,1000,3900,4000,200,*,UP,ALU1
-S 5100,1000,5100,4000,200,*,UP,ALU1
-S 8200,2800,8200,6800,200,*,UP,ALU1
-S 7600,1000,7600,4000,200,*,UP,ALU1
-S 6400,1000,6400,4000,200,*,UP,ALU1
-S 8200,500,8200,1500,200,*,UP,ALU1
-S 7000,500,7000,1500,200,*,UP,ALU1
-S 3900,7900,5100,7900,200,*,RIGHT,ALU1
-S 4500,9000,4500,9400,200,*,UP,ALU1
-S 5700,9000,5700,9700,200,*,UP,ALU1
-S 7000,9000,7000,9400,200,*,UP,ALU1
-S 6400,7900,7600,7900,200,*,RIGHT,ALU1
-S 1700,1900,1700,3200,100,*,UP,POLY
-S 2900,1900,2900,3200,100,*,UP,POLY
-S 2300,1900,2300,3200,100,*,DOWN,POLY
-S 1700,8500,2300,8500,300,*,RIGHT,POLY
-S 2300,8200,2300,8600,100,*,DOWN,POLY
-S 1700,8200,1700,8700,100,*,DOWN,POLY
-S 1100,1900,1100,3200,100,*,DOWN,POLY
-S 3600,1900,3600,3200,100,*,DOWN,POLY
-S 4800,1900,4800,3200,100,*,DOWN,POLY
-S 5400,1900,5400,3200,100,*,UP,POLY
-S 4200,1900,4200,3200,100,*,UP,POLY
-S 7900,1900,7900,3200,100,*,UP,POLY
-S 7300,1900,7300,3200,100,*,DOWN,POLY
-S 6100,1900,6100,3200,100,*,DOWN,POLY
-S 6700,1900,6700,3200,100,*,UP,POLY
-S 4200,8200,4200,8700,100,*,DOWN,POLY
-S 4800,8200,4800,8600,100,*,DOWN,POLY
-S 4200,8500,4800,8500,300,*,RIGHT,POLY
-S 6700,8500,7300,8500,300,*,RIGHT,POLY
-S 7300,8200,7300,8600,100,*,DOWN,POLY
-S 6700,8200,6700,8700,100,*,DOWN,POLY
-S 1400,300,1400,1700,300,*,UP,NDIF
-S 2000,300,2000,1700,300,*,UP,NDIF
-S 1100,100,1100,1900,100,*,UP,NTRANS
-S 1700,100,1700,1900,100,*,DOWN,NTRANS
-S 3200,300,3200,1700,300,*,UP,NDIF
-S 800,300,800,1700,300,*,UP,NDIF
-S 2900,100,2900,1900,100,*,DOWN,NTRANS
-S 2600,300,2600,1700,300,*,UP,NDIF
-S 2300,100,2300,1900,100,*,DOWN,NTRANS
-S 1400,8900,1400,9600,300,*,UP,NDIF
-S 2000,8900,2000,9600,300,*,UP,NDIF
-S 1700,8700,1700,9800,100,*,UP,NTRANS
-S 5700,300,5700,1700,300,*,UP,NDIF
-S 4200,100,4200,1900,100,*,DOWN,NTRANS
-S 3600,100,3600,1900,100,*,UP,NTRANS
-S 4500,300,4500,1700,300,*,UP,NDIF
-S 3900,300,3900,1700,300,*,UP,NDIF
-S 4800,100,4800,1900,100,*,DOWN,NTRANS
-S 5100,300,5100,1700,300,*,UP,NDIF
-S 5400,100,5400,1900,100,*,DOWN,NTRANS
-S 8200,300,8200,1700,300,*,UP,NDIF
-S 6400,300,6400,1700,300,*,UP,NDIF
-S 7000,300,7000,1700,300,*,UP,NDIF
-S 6100,100,6100,1900,100,*,UP,NTRANS
-S 6700,100,6700,1900,100,*,DOWN,NTRANS
-S 7900,100,7900,1900,100,*,DOWN,NTRANS
-S 7600,300,7600,1700,300,*,UP,NDIF
-S 7300,100,7300,1900,100,*,DOWN,NTRANS
-S 4500,8900,4500,9600,300,*,UP,NDIF
-S 3900,8900,3900,9600,300,*,UP,NDIF
-S 6400,8900,6400,9600,300,*,UP,NDIF
-S 7000,8900,7000,9600,300,*,UP,NDIF
-S 4200,8700,4200,9800,100,*,UP,NTRANS
-S 6700,8700,6700,9800,100,*,UP,NTRANS
-S 2600,7300,2600,8000,300,*,UP,PDIF
-S 800,3400,800,6300,300,*,UP,PDIF
-S 1100,3200,1100,6500,100,*,UP,PTRANS
-S 2000,3400,2000,6300,300,*,UP,PDIF
-S 1400,3400,1400,6300,300,*,UP,PDIF
-S 1700,3200,1700,6500,100,*,UP,PTRANS
-S 3200,3400,3200,6300,300,*,DOWN,PDIF
-S 2900,3200,2900,6500,100,*,DOWN,PTRANS
-S 2600,3400,2600,6300,300,*,UP,PDIF
-S 2300,3200,2300,6500,100,*,UP,PTRANS
-S 1400,7300,1400,8000,300,*,UP,PDIF
-S 1700,7100,1700,8200,100,*,DOWN,PTRANS
-S 2100,7300,2100,8000,300,*,UP,PDIF
-S 2300,7100,2300,8200,100,*,DOWN,PTRANS
-S 5700,3400,5700,6300,300,*,DOWN,PDIF
-S 4200,3200,4200,6500,100,*,UP,PTRANS
-S 3900,3400,3900,6300,300,*,UP,PDIF
-S 4500,3400,4500,6300,300,*,UP,PDIF
-S 3600,3200,3600,6500,100,*,UP,PTRANS
-S 4800,3200,4800,6500,100,*,UP,PTRANS
-S 5100,3400,5100,6300,300,*,UP,PDIF
-S 5400,3200,5400,6500,100,*,DOWN,PTRANS
-S 7000,3400,7000,6300,300,*,UP,PDIF
-S 6400,3400,6400,6300,300,*,UP,PDIF
-S 6700,3200,6700,6500,100,*,UP,PTRANS
-S 8200,3400,8200,6300,300,*,DOWN,PDIF
-S 6100,3200,6100,6500,100,*,UP,PTRANS
-S 7900,3200,7900,6500,100,*,DOWN,PTRANS
-S 7600,3400,7600,6300,300,*,UP,PDIF
-S 7300,3200,7300,6500,100,*,UP,PTRANS
-S 3900,7300,3900,8000,300,*,UP,PDIF
-S 5100,7300,5100,8000,300,*,UP,PDIF
-S 6400,7300,6400,8000,300,*,UP,PDIF
-S 4800,7100,4800,8200,100,*,DOWN,PTRANS
-S 4600,7300,4600,8000,300,*,UP,PDIF
-S 4200,7100,4200,8200,100,*,DOWN,PTRANS
-S 7100,7300,7100,8000,300,*,UP,PDIF
-S 7300,7100,7300,8200,100,*,DOWN,PTRANS
-S 7600,7300,7600,8000,300,*,UP,PDIF
-S 6700,7100,6700,8200,100,*,DOWN,PTRANS
-S 5100,6600,5100,7900,200,*,DOWN,ALU1
-S 7600,6600,7600,7900,200,*,DOWN,ALU1
-S 6400,7400,6400,9000,200,*,UP,ALU1
-S 3900,7400,3900,9000,200,*,UP,ALU1
-S 4800,6600,5400,6600,300,*,RIGHT,POLY
-S 7300,6600,7900,6600,300,*,RIGHT,POLY
-S 4500,2800,4500,7400,200,*,UP,ALU1
-S 7000,2800,7000,7400,200,*,UP,ALU1
-S 1100,7700,8300,7700,800,*,RIGHT,NWELL
-S 8200,9000,8200,9700,200,*,UP,ALU1
-S 4400,2200,5100,2200,200,*,RIGHT,ALU1
-S 6900,2200,7600,2200,200,*,RIGHT,ALU1
-S 3600,2200,4400,2200,300,*,RIGHT,POLY
-S 4800,2200,5400,2200,300,*,RIGHT,POLY
-S 6100,2200,6900,2200,300,*,RIGHT,POLY
-S 7300,2200,7900,2200,300,*,RIGHT,POLY
-S 9300,1500,9300,4000,200,*,UP,ALU1
-S 9900,2800,9900,6800,200,*,UP,ALU1
-S 9900,500,9900,1500,200,*,UP,ALU1
-S 9300,2200,10000,2200,200,*,RIGHT,ALU1
-S 10200,1900,10200,3200,100,*,DOWN,POLY
-S 9600,1900,9600,3200,100,*,UP,POLY
-S 10500,300,10500,1700,300,*,UP,NDIF
-S 9900,300,9900,1700,300,*,UP,NDIF
-S 10200,100,10200,1900,100,*,DOWN,NTRANS
-S 10500,3400,10500,6300,300,*,UP,PDIF
-S 10200,3200,10200,6500,100,*,UP,PTRANS
-S 9900,3400,9900,6300,300,*,UP,PDIF
-S 0,9700,12000,9700,600,vss,RIGHT,CALU1
-S 0,300,12000,300,600,vss,RIGHT,CALU1
-S 0,4700,12000,4700,600,vdd,RIGHT,CALU1
-S 0,5300,12000,5300,600,vdd,RIGHT,CALU1
-S 1500,1500,1500,6000,200,nwenx,DOWN,CALU3
-S 2500,1500,2500,6000,200,wenx,DOWN,CALU3
-S 4000,1500,4000,6000,200,nscanx,DOWN,CALU3
-S 5000,1500,5000,6000,200,scanx,DOWN,CALU3
-S 6500,1500,6500,6000,200,nckx,DOWN,CALU3
-S 10500,1000,10500,4000,200,scout,UP,CALU1
-S 1500,1500,7500,1500,200,*,RIGHT,TALU2
-S 1500,4000,7500,4000,200,*,LEFT,TALU2
-S 1500,6000,7500,6000,200,*,RIGHT,TALU2
-V 9000,6500,CONT_POLY,*
-V 7500,1500,CONT_VIA,*
-V 7500,1500,CONT_VIA2,*
-V 5000,1500,CONT_VIA,*
-V 5000,1500,CONT_VIA2,*
-V 2500,1500,CONT_VIA,*
-V 2500,1500,CONT_VIA2,*
-V 1900,2200,CONT_POLY,*
-V 2600,6600,CONT_POLY,*
-V 1500,4000,CONT_VIA2,*
-V 1500,6000,CONT_VIA2,*
-V 2500,6000,CONT_VIA2,*
-V 1500,1500,CONT_VIA2,*
-V 2500,4000,CONT_VIA2,*
-V 5000,4000,CONT_VIA2,*
-V 4000,1500,CONT_VIA2,*
-V 5000,6000,CONT_VIA2,*
-V 4000,6000,CONT_VIA2,*
-V 4000,4000,CONT_VIA2,*
-V 7500,6000,CONT_VIA2,*
-V 6500,1500,CONT_VIA2,*
-V 7500,4000,CONT_VIA2,*
-V 6500,4000,CONT_VIA2,*
-V 6500,6000,CONT_VIA2,*
-V 1500,1500,CONT_VIA,*
-V 1500,4000,CONT_VIA,*
-V 1500,6000,CONT_VIA,*
-V 2500,6000,CONT_VIA,*
-V 2500,4000,CONT_VIA,*
-V 4000,1500,CONT_VIA,*
-V 5000,4000,CONT_VIA,*
-V 5000,6000,CONT_VIA,*
-V 4000,6000,CONT_VIA,*
-V 4000,4000,CONT_VIA,*
-V 6500,1500,CONT_VIA,*
-V 6500,6000,CONT_VIA,*
-V 7500,6000,CONT_VIA,*
-V 7500,4000,CONT_VIA,*
-V 6500,4000,CONT_VIA,*
-V 2000,8500,CONT_POLY,*
-V 4500,8500,CONT_POLY,*
-V 7000,8500,CONT_POLY,*
-V 5700,9700,CONT_BODY_P,*
-V 3200,9700,CONT_BODY_P,*
-V 800,9700,CONT_BODY_P,*
-V 3200,9000,CONT_BODY_P,*
-V 800,9000,CONT_BODY_P,*
-V 5700,9000,CONT_BODY_P,*
-V 3200,1000,CONT_DIF_N,*
-V 2600,1000,CONT_DIF_N,*
-V 3200,500,CONT_DIF_N,*
-V 3200,1500,CONT_DIF_N,*
-V 2600,1500,CONT_DIF_N,*
-V 800,500,CONT_DIF_N,*
-V 800,1500,CONT_DIF_N,*
-V 800,1000,CONT_DIF_N,*
-V 2000,1000,CONT_DIF_N,*
-V 2000,500,CONT_DIF_N,*
-V 2000,1500,CONT_DIF_N,*
-V 1400,9000,CONT_DIF_N,*
-V 1400,1500,CONT_DIF_N,*
-V 1400,1000,CONT_DIF_N,*
-V 2000,9000,CONT_DIF_N,*
-V 2000,9500,CONT_DIF_N,*
-V 5700,500,CONT_DIF_N,*
-V 5100,1000,CONT_DIF_N,*
-V 5700,1000,CONT_DIF_N,*
-V 3900,1000,CONT_DIF_N,*
-V 3900,1500,CONT_DIF_N,*
-V 4500,1500,CONT_DIF_N,*
-V 4500,500,CONT_DIF_N,*
-V 4500,1000,CONT_DIF_N,*
-V 5100,1500,CONT_DIF_N,*
-V 5700,1500,CONT_DIF_N,*
-V 7600,1000,CONT_DIF_N,*
-V 8200,500,CONT_DIF_N,*
-V 6400,1500,CONT_DIF_N,*
-V 6400,1000,CONT_DIF_N,*
-V 8200,1000,CONT_DIF_N,*
-V 8200,1500,CONT_DIF_N,*
-V 7600,1500,CONT_DIF_N,*
-V 7000,1000,CONT_DIF_N,*
-V 7000,500,CONT_DIF_N,*
-V 7000,1500,CONT_DIF_N,*
-V 7000,9000,CONT_DIF_N,*
-V 7000,9500,CONT_DIF_N,*
-V 4500,9500,CONT_DIF_N,*
-V 4500,9000,CONT_DIF_N,*
-V 3900,9000,CONT_DIF_N,*
-V 6400,9000,CONT_DIF_N,*
-V 1400,7900,CONT_DIF_P,*
-V 2000,7400,CONT_DIF_P,*
-V 1400,7400,CONT_DIF_P,*
-V 2000,2900,CONT_BODY_N,*
-V 800,2900,CONT_BODY_N,*
-V 3200,2900,CONT_BODY_N,*
-V 800,6000,CONT_DIF_P,*
-V 800,3500,CONT_DIF_P,*
-V 800,5500,CONT_DIF_P,*
-V 800,5000,CONT_DIF_P,*
-V 800,4500,CONT_DIF_P,*
-V 800,4000,CONT_DIF_P,*
-V 2000,3500,CONT_DIF_P,*
-V 2000,4500,CONT_DIF_P,*
-V 2000,5500,CONT_DIF_P,*
-V 2000,4000,CONT_DIF_P,*
-V 2000,5000,CONT_DIF_P,*
-V 3200,4000,CONT_DIF_P,*
-V 3200,3500,CONT_DIF_P,*
-V 3200,4500,CONT_DIF_P,*
-V 3200,5000,CONT_DIF_P,*
-V 3200,5500,CONT_DIF_P,*
-V 3200,6000,CONT_DIF_P,*
-V 2600,4000,CONT_DIF_P,*
-V 2600,3500,CONT_DIF_P,*
-V 1400,3500,CONT_DIF_P,*
-V 1400,4000,CONT_DIF_P,*
-V 1400,6000,CONT_DIF_P,*
-V 2600,6000,CONT_DIF_P,*
-V 2600,7900,CONT_DIF_P,*
-V 2600,7400,CONT_DIF_P,*
-V 2000,6800,CONT_BODY_N,*
-V 3200,6800,CONT_BODY_N,*
-V 800,6800,CONT_BODY_N,*
-V 4500,5500,CONT_DIF_P,*
-V 4500,4500,CONT_DIF_P,*
-V 4500,3500,CONT_DIF_P,*
-V 5700,2900,CONT_BODY_N,*
-V 4500,2900,CONT_BODY_N,*
-V 5700,6000,CONT_DIF_P,*
-V 5700,5500,CONT_DIF_P,*
-V 5700,5000,CONT_DIF_P,*
-V 5700,4500,CONT_DIF_P,*
-V 5700,3500,CONT_DIF_P,*
-V 5700,4000,CONT_DIF_P,*
-V 4500,5000,CONT_DIF_P,*
-V 4500,4000,CONT_DIF_P,*
-V 5700,6800,CONT_BODY_N,*
-V 4500,6800,CONT_BODY_N,*
-V 5100,6000,CONT_DIF_P,*
-V 3900,6000,CONT_DIF_P,*
-V 3900,4000,CONT_DIF_P,*
-V 3900,3500,CONT_DIF_P,*
-V 5100,3500,CONT_DIF_P,*
-V 5100,4000,CONT_DIF_P,*
-V 7000,3500,CONT_DIF_P,*
-V 7000,4500,CONT_DIF_P,*
-V 7000,5500,CONT_DIF_P,*
-V 8200,5000,CONT_DIF_P,*
-V 8200,5500,CONT_DIF_P,*
-V 8200,6000,CONT_DIF_P,*
-V 7000,2900,CONT_BODY_N,*
-V 8200,2900,CONT_BODY_N,*
-V 7600,6000,CONT_DIF_P,*
-V 7000,6800,CONT_BODY_N,*
-V 8200,6800,CONT_BODY_N,*
-V 7000,4000,CONT_DIF_P,*
-V 7000,5000,CONT_DIF_P,*
-V 8200,4000,CONT_DIF_P,*
-V 8200,3500,CONT_DIF_P,*
-V 8200,4500,CONT_DIF_P,*
-V 3900,7900,CONT_DIF_P,*
-V 7600,4000,CONT_DIF_P,*
-V 7600,3500,CONT_DIF_P,*
-V 6400,3500,CONT_DIF_P,*
-V 6400,4000,CONT_DIF_P,*
-V 6400,6000,CONT_DIF_P,*
-V 5100,7400,CONT_DIF_P,*
-V 5100,7900,CONT_DIF_P,*
-V 3900,7400,CONT_DIF_P,*
-V 4500,7400,CONT_DIF_P,*
-V 7000,7400,CONT_DIF_P,*
-V 6400,7400,CONT_DIF_P,*
-V 7600,7900,CONT_DIF_P,*
-V 7600,7400,CONT_DIF_P,*
-V 6400,7900,CONT_DIF_P,*
-V 5100,6600,CONT_POLY,*
-V 7600,6600,CONT_POLY,*
-V 7000,6000,CONT_DIF_P,*
-V 4500,6000,CONT_DIF_P,*
-V 2000,6000,CONT_DIF_P,*
-V 8200,9700,CONT_BODY_P,*
-V 8200,9000,CONT_BODY_P,*
-V 4400,2200,CONT_POLY,*
-V 6900,2200,CONT_POLY,*
-V 10000,2200,CONT_POLY,*
-V 9300,1500,CONT_DIF_N,*
-V 10500,1500,CONT_DIF_N,*
-V 9900,1000,CONT_DIF_N,*
-V 9900,500,CONT_DIF_N,*
-V 9900,1500,CONT_DIF_N,*
-V 10500,1000,CONT_DIF_N,*
-V 9900,2900,CONT_BODY_N,*
-V 9300,3500,CONT_DIF_P,*
-V 9300,4000,CONT_DIF_P,*
-V 9900,4000,CONT_DIF_P,*
-V 9900,5000,CONT_DIF_P,*
-V 9900,3500,CONT_DIF_P,*
-V 9900,4500,CONT_DIF_P,*
-V 9900,5500,CONT_DIF_P,*
-V 9900,6800,CONT_BODY_N,*
-V 9900,6000,CONT_DIF_P,*
-V 10500,4000,CONT_DIF_P,*
-V 10500,3500,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/dp_sxlib/dp_sff_scan_x4_buf.vbe b/alliance/share/cells/dp_sxlib/dp_sff_scan_x4_buf.vbe
deleted file mode 100644
index 42cea450..00000000
--- a/alliance/share/cells/dp_sxlib/dp_sff_scan_x4_buf.vbe
+++ /dev/null
@@ -1,33 +0,0 @@
-ENTITY dp_sff_scan_x4_buf IS
-PORT (
-  ck		: in  BIT;
-  wen		: in  BIT;
-  scan		: in  BIT;
-  scin		: in  BIT;
-  ckx		: out BIT;
-  nckx		: out BIT;
-  wenx		: out BIT;
-  nwenx		: out BIT;
-  scanx		: out BIT;
-  nscanx	: out BIT;
-  scout 	: out BIT;
-  vdd		: in  BIT;
-  vss		: in  BIT
-);
-END dp_sff_scan_x4_buf;
-
-ARCHITECTURE vbe OF dp_sff_scan_x4_buf IS
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on dp_sff_scan_x4_buf"
-  SEVERITY WARNING;
-
-  ckx <= ck;
-  nckx <= not ck;
-  wenx <= wen;
-  nwenx <= not wen;
-  scanx <= scan;
-  nscanx <= not scan;
-  scout <= scin;
-END;
diff --git a/alliance/share/cells/dp_sxlib/dp_sff_x4.ap b/alliance/share/cells/dp_sxlib/dp_sff_x4.ap
deleted file mode 100644
index 986e4abc..00000000
--- a/alliance/share/cells/dp_sxlib/dp_sff_x4.ap
+++ /dev/null
@@ -1,217 +0,0 @@
-V ALLIANCE : 6
-H dp_sff_x4,P, 6/ 9/2000,10
-A 0,0,900,500
-R 450,250,ref_ref,ckx
-R 350,250,ref_ref,nckx
-R 200,250,ref_ref,wenx
-R 100,250,ref_ref,nwenx
-R 800,150,ref_ref,q_15
-R 800,250,ref_ref,q_25
-R 800,300,ref_ref,q_30
-R 800,350,ref_ref,q_35
-R 800,400,ref_ref,q_40
-R 800,100,ref_ref,q_10
-R 50,400,ref_ref,i_40
-R 50,100,ref_ref,i_10
-R 50,300,ref_ref,i_30
-R 50,350,ref_ref,i_35
-R 50,250,ref_ref,i_25
-R 50,200,ref_ref,i_20
-R 50,150,ref_ref,i_15
-S 740,150,800,150,10,*,RIGHT,ALU1
-S 740,250,800,250,10,*,RIGHT,ALU1
-S 690,200,740,200,10,*,RIGHT,ALU1
-S 740,200,840,200,30,*,RIGHT,POLY
-S 250,200,800,200,20,*,RIGHT,ALU2
-S 720,240,720,360,10,*,DOWN,POLY
-S 450,250,500,250,20,*,RIGHT,ALU2
-S 390,350,450,350,10,*,RIGHT,ALU1
-S 300,150,300,400,10,u,DOWN,ALU1
-S 400,200,400,300,10,*,UP,ALU1
-S 350,300,400,300,10,*,RIGHT,ALU1
-S 870,300,870,450,20,*,DOWN,ALU1
-S 750,300,750,450,20,*,DOWN,ALU1
-S 450,300,520,300,10,*,RIGHT,ALU1
-S 630,200,630,350,10,*,DOWN,ALU1
-S 450,150,520,150,10,*,LEFT,ALU1
-S 630,400,690,400,10,*,RIGHT,ALU1
-S 870,50,870,100,20,*,DOWN,ALU1
-S 750,50,750,100,20,*,DOWN,ALU1
-S 500,350,570,350,10,*,LEFT,ALU1
-S 570,100,570,400,10,y,DOWN,ALU1
-S 450,100,450,350,10,x,DOWN,ALU1
-S 500,100,570,100,10,*,RIGHT,ALU1
-S 390,100,450,100,10,*,RIGHT,ALU1
-S 630,100,690,100,10,*,RIGHT,ALU1
-S 690,100,690,400,10,z,DOWN,ALU1
-S 150,150,150,400,10,*,DOWN,ALU1
-S 200,100,200,300,10,*,DOWN,ALU1
-S 150,400,300,400,10,*,RIGHT,ALU1
-S 100,100,200,100,10,*,RIGHT,ALU1
-S 540,300,540,360,10,*,DOWN,POLY
-S 600,140,600,200,10,*,DOWN,POLY
-S 840,140,840,260,10,*,DOWN,POLY
-S 420,250,420,310,10,*,DOWN,POLY
-S 510,150,540,150,30,*,RIGHT,POLY
-S 480,350,510,350,30,*,RIGHT,POLY
-S 630,350,660,350,30,*,RIGHT,POLY
-S 510,300,540,300,30,*,RIGHT,POLY
-S 780,140,780,260,10,*,DOWN,POLY
-S 660,140,660,250,10,*,DOWN,POLY
-S 390,200,420,200,30,*,RIGHT,POLY
-S 600,200,630,200,30,*,RIGHT,POLY
-S 420,140,420,200,10,*,DOWN,POLY
-S 600,250,600,360,10,*,DOWN,POLY
-S 720,250,750,250,30,*,RIGHT,POLY
-S 720,150,750,150,30,*,RIGHT,POLY
-S 480,100,510,100,30,*,RIGHT,POLY
-S 540,90,540,150,10,*,UP,POLY
-S 270,40,270,120,30,*,DOWN,NDIF
-S 330,80,330,120,30,*,DOWN,NDIF
-S 450,30,450,120,30,*,DOWN,NDIF
-S 390,80,390,120,30,*,DOWN,NDIF
-S 630,80,630,120,30,*,DOWN,NDIF
-S 690,80,690,120,30,*,DOWN,NDIF
-S 870,30,870,120,30,*,DOWN,NDIF
-S 810,30,810,120,30,*,DOWN,NDIF
-S 750,30,750,120,30,*,DOWN,NDIF
-S 570,30,570,120,30,*,DOWN,NDIF
-S 510,30,510,70,30,*,DOWN,NDIF
-S 570,30,570,70,30,*,DOWN,NDIF
-S 160,80,160,160,50,*,DOWN,NDIF
-S 270,40,270,120,30,*,UP,NDIF
-S 140,80,140,120,30,*,UP,NDIF
-S 660,60,660,140,10,*,UP,NTRANS
-S 720,60,720,140,10,*,UP,NTRANS
-S 840,10,840,140,10,*,UP,NTRANS
-S 360,60,360,140,10,*,UP,NTRANS
-S 600,60,600,140,10,*,UP,NTRANS
-S 780,10,780,140,10,*,UP,NTRANS
-S 300,60,300,140,10,*,UP,NTRANS
-S 420,60,420,140,10,*,UP,NTRANS
-S 480,10,480,90,10,*,UP,NTRANS
-S 540,10,540,90,10,*,UP,NTRANS
-S 240,60,240,140,10,*,UP,NTRANS
-S 200,60,200,140,10,*,UP,NTRANS
-S 750,280,750,470,30,*,DOWN,PDIF
-S 780,260,780,490,10,*,DOWN,PTRANS
-S 450,330,450,470,30,*,UP,PDIF
-S 420,310,420,440,10,*,DOWN,PTRANS
-S 390,330,390,420,30,*,UP,PDIF
-S 360,310,360,440,10,*,DOWN,PTRANS
-S 870,280,870,470,30,*,DOWN,PDIF
-S 840,260,840,490,10,*,DOWN,PTRANS
-S 810,280,810,470,30,*,DOWN,PDIF
-S 540,360,540,490,10,*,UP,PTRANS
-S 480,360,480,490,10,*,DOWN,PTRANS
-S 720,360,720,490,10,*,DOWN,PTRANS
-S 690,380,690,470,30,*,UP,PDIF
-S 500,380,500,470,30,*,DOWN,PDIF
-S 660,360,660,490,10,*,DOWN,PTRANS
-S 630,380,630,470,30,*,DOWN,PDIF
-S 600,360,600,490,10,*,DOWN,PTRANS
-S 560,380,560,470,30,*,DOWN,PDIF
-S 200,310,200,440,10,*,DOWN,PTRANS
-S 270,330,270,460,30,*,DOWN,PDIF
-S 240,310,240,440,10,*,DOWN,PTRANS
-S 0,390,900,390,240,*,RIGHT,NWELL
-S 330,330,330,420,30,*,UP,PDIF
-S 300,310,300,440,10,*,DOWN,PTRANS
-S 250,150,250,300,10,*,DOWN,ALU1
-S 100,100,100,150,10,*,UP,ALU1
-S 30,40,30,120,30,*,UP,NDIF
-S 60,60,60,140,10,*,UP,NTRANS
-S 30,330,30,460,30,*,DOWN,PDIF
-S 60,310,60,440,10,*,DOWN,PTRANS
-S 100,200,200,200,10,*,RIGHT,POLY
-S 200,140,200,200,10,*,DOWN,POLY
-S 100,310,100,440,10,*,DOWN,PTRANS
-S 100,200,100,310,10,*,DOWN,POLY
-S 100,60,100,140,10,*,UP,NTRANS
-S 150,330,150,420,60,*,DOWN,PDIF
-S 150,80,150,160,50,*,DOWN,NDIF
-S 500,200,500,250,10,*,DOWN,ALU1
-S 360,140,360,250,10,*,UP,POLY
-S 400,200,600,200,10,ckx,RIGHT,POLY
-S 350,250,660,250,10,nckx,RIGHT,POLY
-S 0,30,900,30,60,vss,RIGHT,CALU1
-S 0,470,900,470,60,vdd,RIGHT,CALU1
-S 250,200,800,200,20,*,RIGHT,TALU2
-S 100,250,500,250,20,*,RIGHT,TALU2
-S 100,250,100,250,20,nwenx,LEFT,CALU3
-S 350,250,350,250,20,nckx,LEFT,CALU3
-S 450,250,450,250,20,ckx,LEFT,CALU3
-S 200,250,200,250,20,wenx,LEFT,CALU3
-S 800,100,800,400,20,q,DOWN,CALU1
-S 50,100,50,400,20,i,DOWN,CALU1
-V 200,250,CONT_VIA,*
-V 200,250,CONT_VIA2,*
-V 100,250,CONT_POLY,*
-V 100,250,CONT_VIA,*
-V 100,250,CONT_VIA2,*
-V 800,200,CONT_VIA,*
-V 740,200,CONT_POLY,*
-V 450,250,CONT_VIA2,*
-V 740,250,CONT_POLY,*
-V 350,300,CONT_POLY,*
-V 350,250,CONT_POLY,*
-V 300,150,CONT_POLY,*
-V 640,350,CONT_POLY,*
-V 400,200,CONT_POLY,*
-V 520,300,CONT_POLY,*
-V 620,200,CONT_POLY,*
-V 520,150,CONT_POLY,*
-V 740,150,CONT_POLY,*
-V 500,350,CONT_POLY,*
-V 500,100,CONT_POLY,*
-V 200,300,CONT_POLY,*
-V 50,300,CONT_POLY,*
-V 50,150,CONT_POLY,*
-V 300,300,CONT_POLY,*
-V 690,30,CONT_BODY_P,*
-V 630,30,CONT_BODY_P,*
-V 200,30,CONT_BODY_P,*
-V 100,30,CONT_BODY_P,*
-V 270,50,CONT_DIF_N,*
-V 810,100,CONT_DIF_N,*
-V 750,100,CONT_DIF_N,*
-V 870,100,CONT_DIF_N,*
-V 750,50,CONT_DIF_N,*
-V 870,50,CONT_DIF_N,*
-V 570,100,CONT_DIF_N,*
-V 390,100,CONT_DIF_N,*
-V 510,50,CONT_DIF_N,*
-V 630,100,CONT_DIF_N,*
-V 150,150,CONT_DIF_N,*
-V 750,450,CONT_DIF_P,*
-V 870,450,CONT_DIF_P,*
-V 750,400,CONT_DIF_P,*
-V 750,350,CONT_DIF_P,*
-V 390,350,CONT_DIF_P,*
-V 810,350,CONT_DIF_P,*
-V 510,450,CONT_DIF_P,*
-V 630,400,CONT_DIF_P,*
-V 810,400,CONT_DIF_P,*
-V 870,350,CONT_DIF_P,*
-V 870,400,CONT_DIF_P,*
-V 750,300,CONT_DIF_P,*
-V 810,300,CONT_DIF_P,*
-V 870,300,CONT_DIF_P,*
-V 570,400,CONT_DIF_P,*
-V 200,470,CONT_BODY_N,*
-V 270,450,CONT_DIF_P,*
-V 150,350,CONT_DIF_P,*
-V 100,470,CONT_BODY_N,*
-V 250,300,CONT_POLY,*
-V 250,150,CONT_POLY,*
-V 250,200,CONT_VIA,*
-V 100,150,CONT_POLY,*
-V 30,50,CONT_DIF_N,*
-V 30,450,CONT_DIF_P,*
-V 500,250,CONT_VIA,*
-V 500,200,CONT_POLY,*
-V 350,250,CONT_VIA2,*
-V 350,250,CONT_VIA,*
-V 350,30,CONT_BODY_P,*
-V 350,470,CONT_BODY_N,*
-EOF
diff --git a/alliance/share/cells/dp_sxlib/dp_sff_x4.vbe b/alliance/share/cells/dp_sxlib/dp_sff_x4.vbe
deleted file mode 100644
index 22300f6a..00000000
--- a/alliance/share/cells/dp_sxlib/dp_sff_x4.vbe
+++ /dev/null
@@ -1,36 +0,0 @@
-ENTITY dp_sff_x4 IS
-PORT (
-  ckx		: in  BIT;
-  nckx		: in  BIT;
-  wenx		: in  BIT;
-  nwenx		: in  BIT;
-  i   		: in  BIT;
-  q		: out BIT;
-  vdd		: in  BIT;
-  vss		: in  BIT
-);
-END dp_sff_x4;
-
-ARCHITECTURE vbe OF dp_sff_x4 IS
-  SIGNAL ff : REG_BIT REGISTER;
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on dp_sff_x4"
-  SEVERITY WARNING;
-
-  ASSERT (ckx xor nckx)
-  REPORT "wrong values for ckx and nckx in dp_sff_x4"
-  SEVERITY WARNING;
-
-  ASSERT (wenx xor nwenx)
-  REPORT "wrong values for wenx and nwenx in dp_sff_x4"
-  SEVERITY WARNING;
-
-  label0 : BLOCK ((ckx and not (ckx'STABLE)) = '1')
-  BEGIN
-    ff <= GUARDED ((wenx and i) or (nwenx and ff));
-  END BLOCK label0;
-
-  q <= ff;
-END;
diff --git a/alliance/share/cells/dp_sxlib/dp_sff_x4_buf.ap b/alliance/share/cells/dp_sxlib/dp_sff_x4_buf.ap
deleted file mode 100644
index c077bb72..00000000
--- a/alliance/share/cells/dp_sxlib/dp_sff_x4_buf.ap
+++ /dev/null
@@ -1,250 +0,0 @@
-V ALLIANCE : 6
-H dp_sff_x4_buf,P,14/11/2000,10
-A 0,0,900,1000
-R 100,400,ref_ref,nwenx
-R 200,400,ref_ref,wenx
-R 350,400,ref_ref,nckx
-R 450,400,ref_ref,ckx
-S 100,600,450,600,20,*,RIGHT,TALU2
-S 100,400,450,400,20,*,LEFT,TALU2
-S 100,150,450,150,20,*,RIGHT,TALU2
-S 150,850,150,850,10,wen,LEFT,CALU1
-S 400,850,400,850,10,ck,LEFT,CALU1
-S 350,150,350,600,20,nckx,DOWN,CALU3
-S 450,150,450,600,20,ckx,UP,CALU3
-S 70,770,480,770,80,*,RIGHT,NWELL
-S 90,340,90,630,30,*,UP,PDIF
-S 120,320,120,650,10,*,UP,PTRANS
-S 270,340,270,630,30,*,DOWN,PDIF
-S 30,340,30,630,30,*,UP,PDIF
-S 210,730,210,800,30,*,UP,PDIF
-S 60,320,60,650,10,*,UP,PTRANS
-S 180,710,180,820,10,*,DOWN,PTRANS
-S 160,730,160,800,30,*,UP,PDIF
-S 120,710,120,820,10,*,DOWN,PTRANS
-S 90,730,90,800,30,*,UP,PDIF
-S 180,320,180,650,10,*,UP,PTRANS
-S 210,340,210,630,30,*,UP,PDIF
-S 240,320,240,650,10,*,DOWN,PTRANS
-S 310,320,310,650,10,*,UP,PTRANS
-S 400,340,400,630,30,*,UP,PDIF
-S 340,340,340,630,30,*,UP,PDIF
-S 370,320,370,650,10,*,UP,PTRANS
-S 520,340,520,630,30,*,DOWN,PDIF
-S 490,320,490,650,10,*,DOWN,PTRANS
-S 460,340,460,630,30,*,UP,PDIF
-S 430,320,430,650,10,*,UP,PTRANS
-S 340,730,340,800,30,*,UP,PDIF
-S 460,730,460,800,30,*,UP,PDIF
-S 370,710,370,820,10,*,DOWN,PTRANS
-S 410,730,410,800,30,*,UP,PDIF
-S 430,710,430,820,10,*,DOWN,PTRANS
-S 150,340,150,630,30,*,UP,PDIF
-S 60,10,60,190,10,*,UP,NTRANS
-S 120,10,120,190,10,*,DOWN,NTRANS
-S 150,30,150,170,30,*,UP,NDIF
-S 180,10,180,190,10,*,DOWN,NTRANS
-S 210,30,210,170,30,*,UP,NDIF
-S 240,10,240,190,10,*,DOWN,NTRANS
-S 30,30,30,170,30,*,UP,NDIF
-S 270,30,270,170,30,*,UP,NDIF
-S 90,30,90,170,30,*,UP,NDIF
-S 150,890,150,960,30,*,UP,NDIF
-S 90,890,90,960,30,*,UP,NDIF
-S 120,870,120,980,10,*,UP,NTRANS
-S 310,10,310,190,10,*,UP,NTRANS
-S 370,10,370,190,10,*,DOWN,NTRANS
-S 520,30,520,170,30,*,UP,NDIF
-S 430,10,430,190,10,*,DOWN,NTRANS
-S 400,30,400,170,30,*,UP,NDIF
-S 340,30,340,170,30,*,UP,NDIF
-S 490,10,490,190,10,*,DOWN,NTRANS
-S 460,30,460,170,30,*,UP,NDIF
-S 340,890,340,960,30,*,UP,NDIF
-S 400,890,400,960,30,*,UP,NDIF
-S 370,870,370,980,10,*,UP,NTRANS
-S 490,190,490,320,10,*,UP,POLY
-S 120,820,120,870,10,*,DOWN,POLY
-S 430,190,430,320,10,*,DOWN,POLY
-S 60,190,60,320,10,*,DOWN,POLY
-S 370,190,370,320,10,*,UP,POLY
-S 120,190,120,320,10,*,UP,POLY
-S 370,820,370,870,10,*,DOWN,POLY
-S 370,850,430,850,30,*,RIGHT,POLY
-S 430,820,430,860,10,*,DOWN,POLY
-S 180,820,180,860,10,*,DOWN,POLY
-S 120,850,180,850,30,*,RIGHT,POLY
-S 310,190,310,320,10,*,DOWN,POLY
-S 180,190,180,320,10,*,DOWN,POLY
-S 240,190,240,320,10,*,UP,POLY
-S 430,660,490,660,30,*,RIGHT,POLY
-S 430,220,490,220,30,*,RIGHT,POLY
-S 310,220,390,220,30,*,RIGHT,POLY
-S 400,280,400,740,20,*,UP,ALU1
-S 30,50,30,150,20,*,UP,ALU1
-S 210,100,210,400,20,*,UP,ALU1
-S 30,350,30,680,20,*,UP,ALU1
-S 270,280,270,680,20,*,UP,ALU1
-S 270,50,270,150,20,*,UP,ALU1
-S 150,900,150,940,20,*,UP,ALU1
-S 90,790,210,790,20,*,RIGHT,ALU1
-S 340,100,340,400,20,*,UP,ALU1
-S 150,50,150,150,20,*,UP,ALU1
-S 150,280,150,740,20,*,UP,ALU1
-S 30,900,30,970,20,*,DOWN,ALU1
-S 520,50,520,150,20,*,UP,ALU1
-S 400,50,400,150,20,*,UP,ALU1
-S 520,280,520,680,20,*,UP,ALU1
-S 460,100,460,400,20,*,UP,ALU1
-S 90,100,90,400,20,*,UP,ALU1
-S 460,660,460,790,20,*,DOWN,ALU1
-S 340,740,340,900,20,*,UP,ALU1
-S 520,900,520,970,20,*,UP,ALU1
-S 400,900,400,940,20,*,UP,ALU1
-S 340,790,460,790,20,*,RIGHT,ALU1
-S 270,900,270,970,20,*,UP,ALU1
-S 390,220,460,220,20,*,RIGHT,ALU1
-S 600,50,600,150,20,*,UP,ALU1
-S 0,500,900,500,460,*,RIGHT,NWELL
-S 180,660,240,660,30,*,RIGHT,POLY
-S 90,740,90,900,20,*,UP,ALU1
-S 210,660,210,790,20,*,DOWN,ALU1
-S 180,220,240,220,30,*,RIGHT,POLY
-S 60,220,140,220,30,*,RIGHT,POLY
-S 150,220,210,220,20,*,RIGHT,ALU1
-S 100,150,100,600,20,nwenx,UP,CALU3
-S 0,30,900,30,60,vss,RIGHT,CALU1
-S 0,530,900,530,60,vdd,RIGHT,CALU1
-S 0,470,900,470,60,vdd,RIGHT,CALU1
-S 0,970,900,970,60,vss,RIGHT,CALU1
-S 200,150,200,600,20,wenx,DOWN,CALU3
-V 450,150,CONT_VIA,*
-V 450,150,CONT_VIA2,*
-V 200,150,CONT_VIA,*
-V 200,150,CONT_VIA2,*
-V 90,790,CONT_DIF_P,*
-V 30,550,CONT_DIF_P,*
-V 30,350,CONT_DIF_P,*
-V 30,600,CONT_DIF_P,*
-V 270,290,CONT_BODY_N,*
-V 30,290,CONT_BODY_N,*
-V 150,290,CONT_BODY_N,*
-V 90,740,CONT_DIF_P,*
-V 150,740,CONT_DIF_P,*
-V 150,500,CONT_DIF_P,*
-V 150,400,CONT_DIF_P,*
-V 150,550,CONT_DIF_P,*
-V 150,450,CONT_DIF_P,*
-V 150,350,CONT_DIF_P,*
-V 30,400,CONT_DIF_P,*
-V 30,450,CONT_DIF_P,*
-V 30,500,CONT_DIF_P,*
-V 210,350,CONT_DIF_P,*
-V 210,400,CONT_DIF_P,*
-V 270,600,CONT_DIF_P,*
-V 270,550,CONT_DIF_P,*
-V 270,500,CONT_DIF_P,*
-V 270,450,CONT_DIF_P,*
-V 270,350,CONT_DIF_P,*
-V 270,400,CONT_DIF_P,*
-V 270,680,CONT_BODY_N,*
-V 150,680,CONT_BODY_N,*
-V 210,740,CONT_DIF_P,*
-V 210,790,CONT_DIF_P,*
-V 210,600,CONT_DIF_P,*
-V 90,600,CONT_DIF_P,*
-V 90,400,CONT_DIF_P,*
-V 90,350,CONT_DIF_P,*
-V 400,550,CONT_DIF_P,*
-V 30,680,CONT_BODY_N,*
-V 520,600,CONT_DIF_P,*
-V 400,290,CONT_BODY_N,*
-V 520,290,CONT_BODY_N,*
-V 400,350,CONT_DIF_P,*
-V 400,450,CONT_DIF_P,*
-V 520,680,CONT_BODY_N,*
-V 400,400,CONT_DIF_P,*
-V 400,500,CONT_DIF_P,*
-V 520,400,CONT_DIF_P,*
-V 520,350,CONT_DIF_P,*
-V 520,450,CONT_DIF_P,*
-V 520,500,CONT_DIF_P,*
-V 520,550,CONT_DIF_P,*
-V 460,400,CONT_DIF_P,*
-V 460,350,CONT_DIF_P,*
-V 340,350,CONT_DIF_P,*
-V 340,400,CONT_DIF_P,*
-V 340,600,CONT_DIF_P,*
-V 400,600,CONT_DIF_P,*
-V 460,600,CONT_DIF_P,*
-V 400,680,CONT_BODY_N,*
-V 340,790,CONT_DIF_P,*
-V 400,740,CONT_DIF_P,*
-V 340,740,CONT_DIF_P,*
-V 460,790,CONT_DIF_P,*
-V 460,740,CONT_DIF_P,*
-V 150,600,CONT_DIF_P,*
-V 30,50,CONT_DIF_N,*
-V 210,150,CONT_DIF_N,*
-V 270,150,CONT_DIF_N,*
-V 270,50,CONT_DIF_N,*
-V 210,100,CONT_DIF_N,*
-V 270,100,CONT_DIF_N,*
-V 90,900,CONT_DIF_N,*
-V 150,150,CONT_DIF_N,*
-V 150,100,CONT_DIF_N,*
-V 150,50,CONT_DIF_N,*
-V 30,100,CONT_DIF_N,*
-V 30,150,CONT_DIF_N,*
-V 150,900,CONT_DIF_N,*
-V 90,100,CONT_DIF_N,*
-V 90,150,CONT_DIF_N,*
-V 520,100,CONT_DIF_N,*
-V 460,100,CONT_DIF_N,*
-V 520,50,CONT_DIF_N,*
-V 150,950,CONT_DIF_N,*
-V 400,50,CONT_DIF_N,*
-V 340,150,CONT_DIF_N,*
-V 400,150,CONT_DIF_N,*
-V 340,100,CONT_DIF_N,*
-V 520,150,CONT_DIF_N,*
-V 460,150,CONT_DIF_N,*
-V 400,100,CONT_DIF_N,*
-V 400,900,CONT_DIF_N,*
-V 400,950,CONT_DIF_N,*
-V 340,900,CONT_DIF_N,*
-V 520,970,CONT_BODY_P,*
-V 270,970,CONT_BODY_P,*
-V 30,900,CONT_BODY_P,*
-V 270,900,CONT_BODY_P,*
-V 520,900,CONT_BODY_P,*
-V 30,970,CONT_BODY_P,*
-V 400,850,CONT_POLY,*
-V 150,850,CONT_POLY,*
-V 460,660,CONT_POLY,*
-V 390,220,CONT_POLY,*
-V 200,400,CONT_VIA,*
-V 200,600,CONT_VIA,*
-V 100,600,CONT_VIA,*
-V 100,400,CONT_VIA,*
-V 100,150,CONT_VIA,*
-V 350,400,CONT_VIA,*
-V 350,600,CONT_VIA,*
-V 350,150,CONT_VIA,*
-V 450,600,CONT_VIA,*
-V 450,400,CONT_VIA,*
-V 450,600,CONT_VIA2,*
-V 350,150,CONT_VIA2,*
-V 350,600,CONT_VIA2,*
-V 100,150,CONT_VIA2,*
-V 100,400,CONT_VIA2,*
-V 200,400,CONT_VIA2,*
-V 450,400,CONT_VIA2,*
-V 350,400,CONT_VIA2,*
-V 100,600,CONT_VIA2,*
-V 200,600,CONT_VIA2,*
-V 600,50,CONT_BODY_P,*
-V 600,150,CONT_BODY_P,*
-V 210,660,CONT_POLY,*
-V 140,220,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/dp_sxlib/dp_sff_x4_buf.vbe b/alliance/share/cells/dp_sxlib/dp_sff_x4_buf.vbe
deleted file mode 100644
index dc202748..00000000
--- a/alliance/share/cells/dp_sxlib/dp_sff_x4_buf.vbe
+++ /dev/null
@@ -1,25 +0,0 @@
-ENTITY dp_sff_x4_buf IS
-PORT (
-  ck		: in  BIT;
-  wen		: in  BIT;
-  ckx		: out BIT;
-  nckx		: out BIT;
-  wenx		: out BIT;
-  nwenx		: out BIT;
-  vdd		: in  BIT;
-  vss		: in  BIT
-);
-END dp_sff_x4_buf;
-
-ARCHITECTURE vbe OF dp_sff_x4_buf IS
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on dp_sff_x4_buf"
-  SEVERITY WARNING;
-
-  ckx <= ck;
-  nckx <= not ck;
-  wenx <= wen;
-  nwenx <= not wen;
-END;
diff --git a/alliance/share/cells/dp_sxlib/dp_sxlib.lef b/alliance/share/cells/dp_sxlib/dp_sxlib.lef
deleted file mode 100644
index e6336083..00000000
--- a/alliance/share/cells/dp_sxlib/dp_sxlib.lef
+++ /dev/null
@@ -1,2395 +0,0 @@
-
-MACRO dp_dff_scan_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      100.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 89.00 24.00 91.00 26.00 ;
-            RECT 84.00 24.00 86.00 26.00 ;
-            RECT 79.00 24.00 81.00 26.00 ;
-            RECT 74.00 24.00 76.00 26.00 ;
-            RECT 69.00 24.00 71.00 26.00 ;
-            RECT 64.00 24.00 66.00 26.00 ;
-            RECT 59.00 24.00 61.00 26.00 ;
-            RECT 54.00 24.00 56.00 26.00 ;
-            RECT 49.00 24.00 51.00 26.00 ;
-            RECT 44.00 24.00 46.00 26.00 ;
-            RECT 39.00 24.00 41.00 26.00 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-            RECT 29.00 24.00 31.00 26.00 ;
-            LAYER L_ALU1 ;
-            RECT 89.00 39.00 91.00 41.00 ;
-            RECT 89.00 34.00 91.00 36.00 ;
-            RECT 89.00 29.00 91.00 31.00 ;
-            RECT 89.00 24.00 91.00 26.00 ;
-            RECT 89.00 19.00 91.00 21.00 ;
-            RECT 89.00 14.00 91.00 16.00 ;
-            RECT 89.00 9.00 91.00 11.00 ;
-        END
-    END q
-    PIN nckx
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 59.00 19.00 61.00 21.00 ;
-        END
-    END nckx
-    PIN i
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END i
-    PIN scin
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 54.00 29.00 56.00 31.00 ;
-            RECT 54.00 24.00 56.00 26.00 ;
-            RECT 54.00 19.00 56.00 21.00 ;
-            RECT 54.00 14.00 56.00 16.00 ;
-        END
-    END scin
-    PIN wenx
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-        END
-    END wenx
-    PIN nwenx
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-        END
-    END nwenx
-    PIN nscanx
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-        END
-    END nscanx
-    PIN scanx
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 49.00 19.00 51.00 21.00 ;
-        END
-    END scanx
-    PIN ckx
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 74.00 19.00 76.00 21.00 ;
-        END
-    END ckx
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 97.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 97.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 98.50 41.00 ;
-        LAYER L_ALU2 ;
-        RECT 14.00 19.00 76.00 21.00 ;
-    END
-END dp_dff_scan_x4
-
-
-MACRO dp_dff_scan_x4_buf
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      100.00 BY 100.00 ;
-    SYMMETRY  Y ;
-    SITE      core ;
-    PIN nckx
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 64.00 59.00 66.00 61.00 ;
-            RECT 64.00 54.00 66.00 56.00 ;
-            RECT 64.00 49.00 66.00 51.00 ;
-            RECT 64.00 44.00 66.00 46.00 ;
-            RECT 64.00 39.00 66.00 41.00 ;
-            RECT 64.00 34.00 66.00 36.00 ;
-            RECT 64.00 29.00 66.00 31.00 ;
-            RECT 64.00 24.00 66.00 26.00 ;
-            RECT 64.00 19.00 66.00 21.00 ;
-            RECT 64.00 14.00 66.00 16.00 ;
-        END
-    END nckx
-    PIN scanx
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 49.00 59.00 51.00 61.00 ;
-            RECT 49.00 54.00 51.00 56.00 ;
-            RECT 49.00 49.00 51.00 51.00 ;
-            RECT 49.00 44.00 51.00 46.00 ;
-            RECT 49.00 39.00 51.00 41.00 ;
-            RECT 49.00 34.00 51.00 36.00 ;
-            RECT 49.00 29.00 51.00 31.00 ;
-            RECT 49.00 24.00 51.00 26.00 ;
-            RECT 49.00 19.00 51.00 21.00 ;
-            RECT 49.00 14.00 51.00 16.00 ;
-        END
-    END scanx
-    PIN nscanx
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 39.00 59.00 41.00 61.00 ;
-            RECT 39.00 54.00 41.00 56.00 ;
-            RECT 39.00 49.00 41.00 51.00 ;
-            RECT 39.00 44.00 41.00 46.00 ;
-            RECT 39.00 39.00 41.00 41.00 ;
-            RECT 39.00 34.00 41.00 36.00 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-            RECT 39.00 24.00 41.00 26.00 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-            RECT 39.00 14.00 41.00 16.00 ;
-        END
-    END nscanx
-    PIN nwenx
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 24.00 59.00 26.00 61.00 ;
-            RECT 24.00 54.00 26.00 56.00 ;
-            RECT 24.00 49.00 26.00 51.00 ;
-            RECT 24.00 44.00 26.00 46.00 ;
-            RECT 24.00 39.00 26.00 41.00 ;
-            RECT 24.00 34.00 26.00 36.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-        END
-    END nwenx
-    PIN wenx
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 14.00 59.00 16.00 61.00 ;
-            RECT 14.00 54.00 16.00 56.00 ;
-            RECT 14.00 49.00 16.00 51.00 ;
-            RECT 14.00 44.00 16.00 46.00 ;
-            RECT 14.00 39.00 16.00 41.00 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-        END
-    END wenx
-    PIN scout
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 89.00 39.00 91.00 41.00 ;
-            RECT 89.00 34.00 91.00 36.00 ;
-            RECT 89.00 29.00 91.00 31.00 ;
-            RECT 89.00 24.00 91.00 26.00 ;
-            RECT 89.00 19.00 91.00 21.00 ;
-            RECT 89.00 14.00 91.00 16.00 ;
-            RECT 89.00 9.00 91.00 11.00 ;
-        END
-    END scout
-    PIN ckx
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 74.00 59.00 76.00 61.00 ;
-            RECT 74.00 54.00 76.00 56.00 ;
-            RECT 74.00 49.00 76.00 51.00 ;
-            RECT 74.00 44.00 76.00 46.00 ;
-            RECT 74.00 39.00 76.00 41.00 ;
-            RECT 74.00 34.00 76.00 36.00 ;
-            RECT 74.00 29.00 76.00 31.00 ;
-            RECT 74.00 24.00 76.00 26.00 ;
-            RECT 74.00 19.00 76.00 21.00 ;
-            RECT 74.00 14.00 76.00 16.00 ;
-        END
-    END ckx
-    PIN wen
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 84.00 21.00 86.00 ;
-        END
-    END wen
-    PIN scan
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 44.00 84.00 46.00 86.00 ;
-        END
-    END scan
-    PIN ck
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 69.00 84.00 71.00 86.00 ;
-        END
-    END ck
-    PIN scin
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 94.00 69.00 96.00 71.00 ;
-        END
-    END scin
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 97.00 47.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 53.00 97.00 53.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 97.00 3.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 97.00 97.00 97.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 98.50 41.00 ;
-        RECT 1.50 59.00 98.50 91.00 ;
-        LAYER L_ALU2 ;
-        RECT 14.00 59.00 76.00 61.00 ;
-        RECT 14.00 39.00 76.00 41.00 ;
-        RECT 14.00 14.00 76.00 16.00 ;
-    END
-END dp_dff_scan_x4_buf
-
-
-MACRO dp_dff_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      70.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 59.00 24.00 61.00 26.00 ;
-            RECT 54.00 24.00 56.00 26.00 ;
-            RECT 49.00 24.00 51.00 26.00 ;
-            RECT 44.00 24.00 46.00 26.00 ;
-            RECT 39.00 24.00 41.00 26.00 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-            RECT 29.00 24.00 31.00 26.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            LAYER L_ALU1 ;
-            RECT 59.00 39.00 61.00 41.00 ;
-            RECT 59.00 34.00 61.00 36.00 ;
-            RECT 59.00 29.00 61.00 31.00 ;
-            RECT 59.00 24.00 61.00 26.00 ;
-            RECT 59.00 19.00 61.00 21.00 ;
-            RECT 59.00 14.00 61.00 16.00 ;
-            RECT 59.00 9.00 61.00 11.00 ;
-        END
-    END q
-    PIN nckx
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-        END
-    END nckx
-    PIN i
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 39.00 6.00 41.00 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END i
-    PIN wenx
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-        END
-    END wenx
-    PIN nwenx
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-        END
-    END nwenx
-    PIN ckx
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 44.00 19.00 46.00 21.00 ;
-        END
-    END ckx
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 67.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 67.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 68.50 41.00 ;
-        LAYER L_ALU2 ;
-        RECT 9.00 19.00 46.00 21.00 ;
-    END
-END dp_dff_x4
-
-
-MACRO dp_dff_x4_buf
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      70.00 BY 100.00 ;
-    SYMMETRY  Y ;
-    SITE      core ;
-    PIN wenx
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 9.00 59.00 11.00 61.00 ;
-            RECT 9.00 54.00 11.00 56.00 ;
-            RECT 9.00 49.00 11.00 51.00 ;
-            RECT 9.00 44.00 11.00 46.00 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END wenx
-    PIN nwenx
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 19.00 59.00 21.00 61.00 ;
-            RECT 19.00 54.00 21.00 56.00 ;
-            RECT 19.00 49.00 21.00 51.00 ;
-            RECT 19.00 44.00 21.00 46.00 ;
-            RECT 19.00 39.00 21.00 41.00 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-        END
-    END nwenx
-    PIN nckx
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 34.00 59.00 36.00 61.00 ;
-            RECT 34.00 54.00 36.00 56.00 ;
-            RECT 34.00 49.00 36.00 51.00 ;
-            RECT 34.00 44.00 36.00 46.00 ;
-            RECT 34.00 39.00 36.00 41.00 ;
-            RECT 34.00 34.00 36.00 36.00 ;
-            RECT 34.00 29.00 36.00 31.00 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-            RECT 34.00 14.00 36.00 16.00 ;
-        END
-    END nckx
-    PIN ckx
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 44.00 59.00 46.00 61.00 ;
-            RECT 44.00 54.00 46.00 56.00 ;
-            RECT 44.00 49.00 46.00 51.00 ;
-            RECT 44.00 44.00 46.00 46.00 ;
-            RECT 44.00 39.00 46.00 41.00 ;
-            RECT 44.00 34.00 46.00 36.00 ;
-            RECT 44.00 29.00 46.00 31.00 ;
-            RECT 44.00 24.00 46.00 26.00 ;
-            RECT 44.00 19.00 46.00 21.00 ;
-            RECT 44.00 14.00 46.00 16.00 ;
-        END
-    END ckx
-    PIN wen
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 84.00 16.00 86.00 ;
-        END
-    END wen
-    PIN ck
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 39.00 84.00 41.00 86.00 ;
-        END
-    END ck
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 67.00 47.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 53.00 67.00 53.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 67.00 3.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 97.00 67.00 97.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 68.50 41.00 ;
-        RECT 1.50 59.00 68.50 91.00 ;
-        LAYER L_ALU2 ;
-        RECT 9.00 14.00 46.00 16.00 ;
-        RECT 9.00 39.00 46.00 41.00 ;
-        RECT 9.00 59.00 46.00 61.00 ;
-    END
-END dp_dff_x4_buf
-
-
-MACRO dp_mux_x2
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      40.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 39.00 6.00 41.00 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END q
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 39.00 16.00 41.00 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-            RECT 14.00 9.00 16.00 11.00 ;
-        END
-    END i1
-    PIN sel1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-        END
-    END sel1
-    PIN sel0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-        END
-    END sel0
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 34.00 34.00 36.00 36.00 ;
-            RECT 34.00 29.00 36.00 31.00 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-            RECT 34.00 14.00 36.00 16.00 ;
-            RECT 34.00 9.00 36.00 11.00 ;
-        END
-    END i0
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 37.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 37.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 38.50 41.00 ;
-        LAYER L_ALU2 ;
-        RECT 19.00 19.00 31.00 21.00 ;
-    END
-END dp_mux_x2
-
-
-MACRO dp_mux_x2_buf
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      40.00 BY 100.00 ;
-    SYMMETRY  Y ;
-    SITE      core ;
-    PIN sel1
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 19.00 59.00 21.00 61.00 ;
-            RECT 19.00 54.00 21.00 56.00 ;
-            RECT 19.00 49.00 21.00 51.00 ;
-            RECT 19.00 44.00 21.00 46.00 ;
-            RECT 19.00 39.00 21.00 41.00 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-        END
-    END sel1
-    PIN sel0
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 29.00 59.00 31.00 61.00 ;
-            RECT 29.00 54.00 31.00 56.00 ;
-            RECT 29.00 49.00 31.00 51.00 ;
-            RECT 29.00 44.00 31.00 46.00 ;
-            RECT 29.00 39.00 31.00 41.00 ;
-            RECT 29.00 34.00 31.00 36.00 ;
-            RECT 29.00 29.00 31.00 31.00 ;
-            RECT 29.00 24.00 31.00 26.00 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-            RECT 29.00 14.00 31.00 16.00 ;
-        END
-    END sel0
-    PIN sel
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 84.00 26.00 86.00 ;
-        END
-    END sel
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 37.00 47.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 53.00 37.00 53.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 37.00 3.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 97.00 37.00 97.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 38.50 41.00 ;
-        RECT 1.50 59.00 38.50 91.00 ;
-        LAYER L_ALU2 ;
-        RECT 19.00 14.00 31.00 16.00 ;
-        RECT 19.00 39.00 31.00 41.00 ;
-        RECT 19.00 59.00 31.00 61.00 ;
-    END
-END dp_mux_x2_buf
-
-
-MACRO dp_mux_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      45.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END q
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 39.00 34.00 41.00 36.00 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-            RECT 39.00 24.00 41.00 26.00 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-            RECT 39.00 14.00 41.00 16.00 ;
-            RECT 39.00 9.00 41.00 11.00 ;
-        END
-    END i0
-    PIN sel1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-        END
-    END sel1
-    PIN sel0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-        END
-    END sel0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 39.00 21.00 41.00 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-            RECT 19.00 9.00 21.00 11.00 ;
-        END
-    END i1
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 42.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 42.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 43.50 41.00 ;
-        LAYER L_ALU2 ;
-        RECT 24.00 19.00 36.00 21.00 ;
-    END
-END dp_mux_x4
-
-
-MACRO dp_mux_x4_buf
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      45.00 BY 100.00 ;
-    SYMMETRY  Y ;
-    SITE      core ;
-    PIN sel1
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 24.00 59.00 26.00 61.00 ;
-            RECT 24.00 54.00 26.00 56.00 ;
-            RECT 24.00 49.00 26.00 51.00 ;
-            RECT 24.00 44.00 26.00 46.00 ;
-            RECT 24.00 39.00 26.00 41.00 ;
-            RECT 24.00 34.00 26.00 36.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-        END
-    END sel1
-    PIN sel0
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 34.00 59.00 36.00 61.00 ;
-            RECT 34.00 54.00 36.00 56.00 ;
-            RECT 34.00 49.00 36.00 51.00 ;
-            RECT 34.00 44.00 36.00 46.00 ;
-            RECT 34.00 39.00 36.00 41.00 ;
-            RECT 34.00 34.00 36.00 36.00 ;
-            RECT 34.00 29.00 36.00 31.00 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-            RECT 34.00 14.00 36.00 16.00 ;
-        END
-    END sel0
-    PIN sel
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 84.00 31.00 86.00 ;
-        END
-    END sel
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 42.00 47.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 53.00 42.00 53.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 42.00 3.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 97.00 42.00 97.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 43.50 41.00 ;
-        RECT 1.50 59.00 43.50 91.00 ;
-        LAYER L_ALU2 ;
-        RECT 24.00 14.00 36.00 16.00 ;
-        RECT 24.00 39.00 36.00 41.00 ;
-        RECT 24.00 59.00 36.00 61.00 ;
-    END
-END dp_mux_x4_buf
-
-
-MACRO dp_nmux_x1
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      30.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-            RECT 14.00 9.00 16.00 11.00 ;
-        END
-    END nq
-    PIN sel0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-        END
-    END sel0
-    PIN sel1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-        END
-    END sel1
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 39.00 26.00 41.00 ;
-            RECT 24.00 34.00 26.00 36.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-            RECT 24.00 9.00 26.00 11.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 39.00 6.00 41.00 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END i1
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 27.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 27.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 28.50 41.00 ;
-        LAYER L_ALU2 ;
-        RECT 9.00 19.00 21.00 21.00 ;
-    END
-END dp_nmux_x1
-
-
-MACRO dp_nmux_x1_buf
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      30.00 BY 100.00 ;
-    SYMMETRY  Y ;
-    SITE      core ;
-    PIN sel1
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 9.00 59.00 11.00 61.00 ;
-            RECT 9.00 54.00 11.00 56.00 ;
-            RECT 9.00 49.00 11.00 51.00 ;
-            RECT 9.00 44.00 11.00 46.00 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END sel1
-    PIN sel0
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 19.00 59.00 21.00 61.00 ;
-            RECT 19.00 54.00 21.00 56.00 ;
-            RECT 19.00 49.00 21.00 51.00 ;
-            RECT 19.00 44.00 21.00 46.00 ;
-            RECT 19.00 39.00 21.00 41.00 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-        END
-    END sel0
-    PIN sel
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 84.00 16.00 86.00 ;
-        END
-    END sel
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 27.00 47.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 53.00 27.00 53.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 27.00 3.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 97.00 27.00 97.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 28.50 41.00 ;
-        RECT 1.50 59.00 28.50 91.00 ;
-        LAYER L_ALU2 ;
-        RECT 9.00 14.00 21.00 16.00 ;
-        RECT 9.00 39.00 21.00 41.00 ;
-        RECT 9.00 59.00 21.00 61.00 ;
-    END
-END dp_nmux_x1_buf
-
-
-MACRO dp_nts_x2
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      30.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT TRISTATE ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 39.00 16.00 41.00 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-            RECT 14.00 9.00 16.00 11.00 ;
-        END
-    END nq
-    PIN i
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 39.00 6.00 41.00 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END i
-    PIN enx
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-        END
-    END enx
-    PIN nenx
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-        END
-    END nenx
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 27.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 27.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 28.50 41.00 ;
-        LAYER L_ALU2 ;
-        RECT 9.00 19.00 21.00 21.00 ;
-    END
-END dp_nts_x2
-
-
-MACRO dp_nts_x2_buf
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      30.00 BY 100.00 ;
-    SYMMETRY  Y ;
-    SITE      core ;
-    PIN nenx
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 9.00 59.00 11.00 61.00 ;
-            RECT 9.00 54.00 11.00 56.00 ;
-            RECT 9.00 49.00 11.00 51.00 ;
-            RECT 9.00 44.00 11.00 46.00 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END nenx
-    PIN enx
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 19.00 59.00 21.00 61.00 ;
-            RECT 19.00 54.00 21.00 56.00 ;
-            RECT 19.00 49.00 21.00 51.00 ;
-            RECT 19.00 44.00 21.00 46.00 ;
-            RECT 19.00 39.00 21.00 41.00 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-        END
-    END enx
-    PIN en
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 84.00 16.00 86.00 ;
-        END
-    END en
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 27.00 47.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 53.00 27.00 53.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 27.00 3.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 97.00 27.00 97.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 28.50 41.00 ;
-        RECT 1.50 59.00 28.50 91.00 ;
-        LAYER L_ALU2 ;
-        RECT 9.00 14.00 21.00 16.00 ;
-        RECT 9.00 39.00 21.00 41.00 ;
-        RECT 9.00 59.00 21.00 61.00 ;
-    END
-END dp_nts_x2_buf
-
-
-MACRO dp_rom2_buf
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      25.00 BY 100.00 ;
-    SYMMETRY  Y ;
-    SITE      core ;
-    PIN nix
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 9.00 59.00 11.00 61.00 ;
-            RECT 9.00 54.00 11.00 56.00 ;
-            RECT 9.00 49.00 11.00 51.00 ;
-            RECT 9.00 44.00 11.00 46.00 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END nix
-    PIN i
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 69.00 11.00 71.00 ;
-        END
-    END i
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 22.00 47.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 53.00 22.00 53.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 22.00 3.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 97.00 22.00 97.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 23.50 41.00 ;
-        RECT 1.50 59.00 23.50 91.00 ;
-        LAYER L_ALU2 ;
-        RECT 3.00 14.00 17.00 16.00 ;
-        RECT 3.00 39.00 17.00 41.00 ;
-        RECT 3.00 59.00 17.00 61.00 ;
-    END
-END dp_rom2_buf
-
-
-MACRO dp_rom4_buf
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      55.00 BY 100.00 ;
-    SYMMETRY  Y ;
-    SITE      core ;
-    PIN ni0x
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 44.00 59.00 46.00 61.00 ;
-            RECT 44.00 54.00 46.00 56.00 ;
-            RECT 44.00 49.00 46.00 51.00 ;
-            RECT 44.00 44.00 46.00 46.00 ;
-            RECT 44.00 39.00 46.00 41.00 ;
-            RECT 44.00 34.00 46.00 36.00 ;
-            RECT 44.00 29.00 46.00 31.00 ;
-            RECT 44.00 24.00 46.00 26.00 ;
-            RECT 44.00 19.00 46.00 21.00 ;
-            RECT 44.00 14.00 46.00 16.00 ;
-        END
-    END ni0x
-    PIN i1x
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 34.00 59.00 36.00 61.00 ;
-            RECT 34.00 54.00 36.00 56.00 ;
-            RECT 34.00 49.00 36.00 51.00 ;
-            RECT 34.00 44.00 36.00 46.00 ;
-            RECT 34.00 39.00 36.00 41.00 ;
-            RECT 34.00 34.00 36.00 36.00 ;
-            RECT 34.00 29.00 36.00 31.00 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-            RECT 34.00 14.00 36.00 16.00 ;
-        END
-    END i1x
-    PIN i0x
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 9.00 59.00 11.00 61.00 ;
-            RECT 9.00 54.00 11.00 56.00 ;
-            RECT 9.00 49.00 11.00 51.00 ;
-            RECT 9.00 44.00 11.00 46.00 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END i0x
-    PIN ni1x
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 19.00 59.00 21.00 61.00 ;
-            RECT 19.00 54.00 21.00 56.00 ;
-            RECT 19.00 49.00 21.00 51.00 ;
-            RECT 19.00 44.00 21.00 46.00 ;
-            RECT 19.00 39.00 21.00 41.00 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-        END
-    END ni1x
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 39.00 84.00 41.00 86.00 ;
-        END
-    END i1
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 84.00 16.00 86.00 ;
-        END
-    END i0
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 52.00 47.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 53.00 52.00 53.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 52.00 3.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 97.00 52.00 97.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 53.50 41.00 ;
-        RECT 1.50 59.00 53.50 91.00 ;
-        LAYER L_ALU2 ;
-        RECT 9.00 14.00 46.00 16.00 ;
-        RECT 9.00 19.00 41.00 21.00 ;
-        RECT 9.00 39.00 46.00 41.00 ;
-        RECT 9.00 59.00 46.00 61.00 ;
-        RECT 9.00 19.00 41.00 21.00 ;
-    END
-END dp_rom4_buf
-
-
-MACRO dp_rom4_nxr2_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      55.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 49.00 39.00 51.00 41.00 ;
-            RECT 49.00 34.00 51.00 36.00 ;
-            RECT 49.00 29.00 51.00 31.00 ;
-            RECT 49.00 24.00 51.00 26.00 ;
-            RECT 49.00 19.00 51.00 21.00 ;
-            RECT 49.00 14.00 51.00 16.00 ;
-            RECT 49.00 9.00 51.00 11.00 ;
-        END
-    END q
-    PIN ni0x
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 44.00 19.00 46.00 21.00 ;
-        END
-    END ni0x
-    PIN ni1x
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-        END
-    END ni1x
-    PIN i0x
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-        END
-    END i0x
-    PIN i1x
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-        END
-    END i1x
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 52.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 52.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 53.50 41.00 ;
-        LAYER L_ALU2 ;
-        RECT 19.00 19.00 26.00 21.00 ;
-        RECT 9.00 24.00 36.00 26.00 ;
-        RECT 24.00 24.00 36.00 26.00 ;
-        RECT 19.00 19.00 46.00 21.00 ;
-        RECT 29.00 19.00 46.00 21.00 ;
-    END
-END dp_rom4_nxr2_x4
-
-
-MACRO dp_rom4_xr2_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      55.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 49.00 39.00 51.00 41.00 ;
-            RECT 49.00 34.00 51.00 36.00 ;
-            RECT 49.00 29.00 51.00 31.00 ;
-            RECT 49.00 24.00 51.00 26.00 ;
-            RECT 49.00 19.00 51.00 21.00 ;
-            RECT 49.00 14.00 51.00 16.00 ;
-            RECT 49.00 9.00 51.00 11.00 ;
-        END
-    END q
-    PIN ni1x
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-        END
-    END ni1x
-    PIN ni0x
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 44.00 19.00 46.00 21.00 ;
-        END
-    END ni0x
-    PIN i1x
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-        END
-    END i1x
-    PIN i0x
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-        END
-    END i0x
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 52.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 52.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 53.50 41.00 ;
-        LAYER L_ALU2 ;
-        RECT 16.00 24.00 36.00 26.00 ;
-        RECT 29.00 19.00 46.00 21.00 ;
-        RECT 19.00 19.00 46.00 21.00 ;
-        RECT 9.00 24.00 36.00 26.00 ;
-        RECT 19.00 19.00 26.00 21.00 ;
-    END
-END dp_rom4_xr2_x4
-
-
-MACRO dp_sff_scan_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      120.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 109.00 39.00 111.00 41.00 ;
-            RECT 109.00 34.00 111.00 36.00 ;
-            RECT 109.00 29.00 111.00 31.00 ;
-            RECT 109.00 24.00 111.00 26.00 ;
-            RECT 109.00 19.00 111.00 21.00 ;
-            RECT 109.00 14.00 111.00 16.00 ;
-            RECT 109.00 9.00 111.00 11.00 ;
-            LAYER L_ALU2 ;
-            RECT 109.00 19.00 111.00 21.00 ;
-            RECT 104.00 19.00 106.00 21.00 ;
-            RECT 99.00 19.00 101.00 21.00 ;
-            RECT 94.00 19.00 96.00 21.00 ;
-            RECT 89.00 19.00 91.00 21.00 ;
-            RECT 84.00 19.00 86.00 21.00 ;
-            RECT 79.00 19.00 81.00 21.00 ;
-            RECT 74.00 19.00 76.00 21.00 ;
-            RECT 69.00 19.00 71.00 21.00 ;
-            RECT 64.00 19.00 66.00 21.00 ;
-            RECT 59.00 19.00 61.00 21.00 ;
-            RECT 54.00 19.00 56.00 21.00 ;
-            RECT 49.00 19.00 51.00 21.00 ;
-            RECT 44.00 19.00 46.00 21.00 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-        END
-    END q
-    PIN wenx
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-        END
-    END wenx
-    PIN nwenx
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-        END
-    END nwenx
-    PIN nscanx
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 39.00 24.00 41.00 26.00 ;
-        END
-    END nscanx
-    PIN scanx
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 49.00 24.00 51.00 26.00 ;
-        END
-    END scanx
-    PIN nckx
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 64.00 24.00 66.00 26.00 ;
-        END
-    END nckx
-    PIN ckx
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 74.00 24.00 76.00 26.00 ;
-        END
-    END ckx
-    PIN scin
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 54.00 29.00 56.00 31.00 ;
-            RECT 54.00 24.00 56.00 26.00 ;
-            RECT 54.00 19.00 56.00 21.00 ;
-            RECT 54.00 14.00 56.00 16.00 ;
-        END
-    END scin
-    PIN i
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END i
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 117.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 117.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 118.50 41.00 ;
-        LAYER L_ALU2 ;
-        RECT 4.00 24.00 81.00 26.00 ;
-        RECT 74.00 24.00 81.00 26.00 ;
-        RECT 4.00 24.00 36.00 26.00 ;
-        RECT 14.00 19.00 26.00 21.00 ;
-    END
-END dp_sff_scan_x4
-
-
-MACRO dp_sff_scan_x4_buf
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      120.00 BY 100.00 ;
-    SYMMETRY  Y ;
-    SITE      core ;
-    PIN ckx
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 74.00 59.00 76.00 61.00 ;
-            RECT 74.00 54.00 76.00 56.00 ;
-            RECT 74.00 49.00 76.00 51.00 ;
-            RECT 74.00 44.00 76.00 46.00 ;
-            RECT 74.00 39.00 76.00 41.00 ;
-            RECT 74.00 34.00 76.00 36.00 ;
-            RECT 74.00 29.00 76.00 31.00 ;
-            RECT 74.00 24.00 76.00 26.00 ;
-            RECT 74.00 19.00 76.00 21.00 ;
-            RECT 74.00 14.00 76.00 16.00 ;
-        END
-    END ckx
-    PIN nwenx
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 14.00 59.00 16.00 61.00 ;
-            RECT 14.00 54.00 16.00 56.00 ;
-            RECT 14.00 49.00 16.00 51.00 ;
-            RECT 14.00 44.00 16.00 46.00 ;
-            RECT 14.00 39.00 16.00 41.00 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-        END
-    END nwenx
-    PIN wenx
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 24.00 59.00 26.00 61.00 ;
-            RECT 24.00 54.00 26.00 56.00 ;
-            RECT 24.00 49.00 26.00 51.00 ;
-            RECT 24.00 44.00 26.00 46.00 ;
-            RECT 24.00 39.00 26.00 41.00 ;
-            RECT 24.00 34.00 26.00 36.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-        END
-    END wenx
-    PIN nscanx
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 39.00 59.00 41.00 61.00 ;
-            RECT 39.00 54.00 41.00 56.00 ;
-            RECT 39.00 49.00 41.00 51.00 ;
-            RECT 39.00 44.00 41.00 46.00 ;
-            RECT 39.00 39.00 41.00 41.00 ;
-            RECT 39.00 34.00 41.00 36.00 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-            RECT 39.00 24.00 41.00 26.00 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-            RECT 39.00 14.00 41.00 16.00 ;
-        END
-    END nscanx
-    PIN scanx
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 49.00 59.00 51.00 61.00 ;
-            RECT 49.00 54.00 51.00 56.00 ;
-            RECT 49.00 49.00 51.00 51.00 ;
-            RECT 49.00 44.00 51.00 46.00 ;
-            RECT 49.00 39.00 51.00 41.00 ;
-            RECT 49.00 34.00 51.00 36.00 ;
-            RECT 49.00 29.00 51.00 31.00 ;
-            RECT 49.00 24.00 51.00 26.00 ;
-            RECT 49.00 19.00 51.00 21.00 ;
-            RECT 49.00 14.00 51.00 16.00 ;
-        END
-    END scanx
-    PIN nckx
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 64.00 59.00 66.00 61.00 ;
-            RECT 64.00 54.00 66.00 56.00 ;
-            RECT 64.00 49.00 66.00 51.00 ;
-            RECT 64.00 44.00 66.00 46.00 ;
-            RECT 64.00 39.00 66.00 41.00 ;
-            RECT 64.00 34.00 66.00 36.00 ;
-            RECT 64.00 29.00 66.00 31.00 ;
-            RECT 64.00 24.00 66.00 26.00 ;
-            RECT 64.00 19.00 66.00 21.00 ;
-            RECT 64.00 14.00 66.00 16.00 ;
-        END
-    END nckx
-    PIN scout
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 104.00 39.00 106.00 41.00 ;
-            RECT 104.00 34.00 106.00 36.00 ;
-            RECT 104.00 29.00 106.00 31.00 ;
-            RECT 104.00 24.00 106.00 26.00 ;
-            RECT 104.00 19.00 106.00 21.00 ;
-            RECT 104.00 14.00 106.00 16.00 ;
-            RECT 104.00 9.00 106.00 11.00 ;
-        END
-    END scout
-    PIN scin
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 89.00 64.00 91.00 66.00 ;
-        END
-    END scin
-    PIN wen
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 84.00 21.00 86.00 ;
-        END
-    END wen
-    PIN scan
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 44.00 84.00 46.00 86.00 ;
-        END
-    END scan
-    PIN ck
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 69.00 84.00 71.00 86.00 ;
-        END
-    END ck
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 117.00 47.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 53.00 117.00 53.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 117.00 3.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 97.00 117.00 97.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 118.50 41.00 ;
-        RECT 1.50 59.00 118.50 91.00 ;
-        LAYER L_ALU2 ;
-        RECT 14.00 59.00 76.00 61.00 ;
-        RECT 14.00 39.00 76.00 41.00 ;
-        RECT 14.00 14.00 76.00 16.00 ;
-    END
-END dp_sff_scan_x4_buf
-
-
-MACRO dp_sff_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      90.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 79.00 39.00 81.00 41.00 ;
-            RECT 79.00 34.00 81.00 36.00 ;
-            RECT 79.00 29.00 81.00 31.00 ;
-            RECT 79.00 24.00 81.00 26.00 ;
-            RECT 79.00 19.00 81.00 21.00 ;
-            RECT 79.00 14.00 81.00 16.00 ;
-            RECT 79.00 9.00 81.00 11.00 ;
-        END
-    END q
-    PIN nwenx
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-        END
-    END nwenx
-    PIN nckx
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-        END
-    END nckx
-    PIN ckx
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 44.00 24.00 46.00 26.00 ;
-        END
-    END ckx
-    PIN wenx
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-        END
-    END wenx
-    PIN i
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 39.00 6.00 41.00 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END i
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 87.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 87.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 88.50 41.00 ;
-        LAYER L_ALU2 ;
-        RECT 9.00 24.00 51.00 26.00 ;
-        RECT 24.00 19.00 81.00 21.00 ;
-        RECT 44.00 24.00 51.00 26.00 ;
-        RECT 24.00 19.00 81.00 21.00 ;
-    END
-END dp_sff_x4
-
-
-MACRO dp_sff_x4_buf
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      90.00 BY 100.00 ;
-    SYMMETRY  Y ;
-    SITE      core ;
-    PIN nckx
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 34.00 59.00 36.00 61.00 ;
-            RECT 34.00 54.00 36.00 56.00 ;
-            RECT 34.00 49.00 36.00 51.00 ;
-            RECT 34.00 44.00 36.00 46.00 ;
-            RECT 34.00 39.00 36.00 41.00 ;
-            RECT 34.00 34.00 36.00 36.00 ;
-            RECT 34.00 29.00 36.00 31.00 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-            RECT 34.00 14.00 36.00 16.00 ;
-        END
-    END nckx
-    PIN ckx
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 44.00 59.00 46.00 61.00 ;
-            RECT 44.00 54.00 46.00 56.00 ;
-            RECT 44.00 49.00 46.00 51.00 ;
-            RECT 44.00 44.00 46.00 46.00 ;
-            RECT 44.00 39.00 46.00 41.00 ;
-            RECT 44.00 34.00 46.00 36.00 ;
-            RECT 44.00 29.00 46.00 31.00 ;
-            RECT 44.00 24.00 46.00 26.00 ;
-            RECT 44.00 19.00 46.00 21.00 ;
-            RECT 44.00 14.00 46.00 16.00 ;
-        END
-    END ckx
-    PIN nwenx
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 9.00 59.00 11.00 61.00 ;
-            RECT 9.00 54.00 11.00 56.00 ;
-            RECT 9.00 49.00 11.00 51.00 ;
-            RECT 9.00 44.00 11.00 46.00 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END nwenx
-    PIN wenx
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 19.00 59.00 21.00 61.00 ;
-            RECT 19.00 54.00 21.00 56.00 ;
-            RECT 19.00 49.00 21.00 51.00 ;
-            RECT 19.00 44.00 21.00 46.00 ;
-            RECT 19.00 39.00 21.00 41.00 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-        END
-    END wenx
-    PIN wen
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 84.00 16.00 86.00 ;
-        END
-    END wen
-    PIN ck
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 39.00 84.00 41.00 86.00 ;
-        END
-    END ck
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 87.00 47.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 53.00 87.00 53.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 87.00 3.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 97.00 87.00 97.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 88.50 41.00 ;
-        RECT 1.50 59.00 88.50 91.00 ;
-        LAYER L_ALU2 ;
-        RECT 9.00 14.00 46.00 16.00 ;
-        RECT 9.00 39.00 46.00 41.00 ;
-        RECT 9.00 59.00 46.00 61.00 ;
-    END
-END dp_sff_x4_buf
-
-
-MACRO dp_ts_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      45.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT TRISTATE ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END q
-    PIN enx
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-        END
-    END enx
-    PIN nenx
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-        END
-    END nenx
-    PIN i
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 39.00 16.00 41.00 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-            RECT 14.00 9.00 16.00 11.00 ;
-        END
-    END i
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 42.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 42.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 43.50 41.00 ;
-        LAYER L_ALU2 ;
-        RECT 24.00 19.00 36.00 21.00 ;
-    END
-END dp_ts_x4
-
-
-MACRO dp_ts_x4_buf
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      45.00 BY 100.00 ;
-    SYMMETRY  Y ;
-    SITE      core ;
-    PIN enx
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 34.00 59.00 36.00 61.00 ;
-            RECT 34.00 54.00 36.00 56.00 ;
-            RECT 34.00 49.00 36.00 51.00 ;
-            RECT 34.00 44.00 36.00 46.00 ;
-            RECT 34.00 39.00 36.00 41.00 ;
-            RECT 34.00 34.00 36.00 36.00 ;
-            RECT 34.00 29.00 36.00 31.00 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-            RECT 34.00 14.00 36.00 16.00 ;
-        END
-    END enx
-    PIN nenx
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 24.00 59.00 26.00 61.00 ;
-            RECT 24.00 54.00 26.00 56.00 ;
-            RECT 24.00 49.00 26.00 51.00 ;
-            RECT 24.00 44.00 26.00 46.00 ;
-            RECT 24.00 39.00 26.00 41.00 ;
-            RECT 24.00 34.00 26.00 36.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-        END
-    END nenx
-    PIN en
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 84.00 31.00 86.00 ;
-        END
-    END en
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 42.00 47.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 53.00 42.00 53.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 42.00 3.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 97.00 42.00 97.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 43.50 41.00 ;
-        RECT 1.50 59.00 43.50 91.00 ;
-        LAYER L_ALU2 ;
-        RECT 24.00 59.00 36.00 61.00 ;
-        RECT 24.00 39.00 36.00 41.00 ;
-        RECT 24.00 14.00 37.00 16.00 ;
-        RECT 33.00 14.00 37.00 16.00 ;
-    END
-END dp_ts_x4_buf
-
-
-MACRO dp_ts_x8
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      55.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT TRISTATE ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END q
-    PIN i
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 39.00 6.00 41.00 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END i
-    PIN enx
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 44.00 19.00 46.00 21.00 ;
-        END
-    END enx
-    PIN nenx
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-        END
-    END nenx
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 52.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 52.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 53.50 41.00 ;
-        LAYER L_ALU2 ;
-        RECT 34.00 19.00 46.00 21.00 ;
-    END
-END dp_ts_x8
-
-
-MACRO dp_ts_x8_buf
-    CLASS     CORE ;
-    ORIGIN    10.00 0.00 ;
-    SIZE      55.00 BY 100.00 ;
-    SYMMETRY  Y ;
-    SITE      core ;
-    PIN nenx
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 24.00 59.00 26.00 61.00 ;
-            RECT 24.00 54.00 26.00 56.00 ;
-            RECT 24.00 49.00 26.00 51.00 ;
-            RECT 24.00 44.00 26.00 46.00 ;
-            RECT 24.00 39.00 26.00 41.00 ;
-            RECT 24.00 34.00 26.00 36.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-        END
-    END nenx
-    PIN enx
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 34.00 59.00 36.00 61.00 ;
-            RECT 34.00 54.00 36.00 56.00 ;
-            RECT 34.00 49.00 36.00 51.00 ;
-            RECT 34.00 44.00 36.00 46.00 ;
-            RECT 34.00 39.00 36.00 41.00 ;
-            RECT 34.00 34.00 36.00 36.00 ;
-            RECT 34.00 29.00 36.00 31.00 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-            RECT 34.00 14.00 36.00 16.00 ;
-        END
-    END enx
-    PIN en
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 84.00 31.00 86.00 ;
-        END
-    END en
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH -7.00 47.00 42.00 47.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH -7.00 53.00 42.00 53.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH -7.00 3.00 42.00 3.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH -7.00 97.00 42.00 97.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT -8.50 9.00 43.50 41.00 ;
-        RECT -8.50 59.00 43.50 91.00 ;
-        LAYER L_ALU2 ;
-        RECT 24.00 14.00 36.00 16.00 ;
-        RECT 24.00 39.00 36.00 41.00 ;
-        RECT 24.00 59.00 36.00 61.00 ;
-    END
-END dp_ts_x8_buf
-
-
-END LIBRARY
diff --git a/alliance/share/cells/dp_sxlib/dp_ts_x4.ap b/alliance/share/cells/dp_sxlib/dp_ts_x4.ap
deleted file mode 100644
index 53102cbe..00000000
--- a/alliance/share/cells/dp_sxlib/dp_ts_x4.ap
+++ /dev/null
@@ -1,110 +0,0 @@
-V ALLIANCE : 6
-H dp_ts_x4,P,26/ 9/2000,100
-A 0,0,4500,5000
-R 1000,1000,ref_ref,q_10
-R 1000,1500,ref_ref,q_15
-R 1000,2000,ref_ref,q_20
-R 1000,2500,ref_ref,q_25
-R 1000,3000,ref_ref,q_30
-R 1000,3500,ref_ref,q_35
-R 1000,4000,ref_ref,q_40
-R 1500,1000,ref_ref,i_10
-R 1500,3000,ref_ref,i_30
-R 1500,3500,ref_ref,i_35
-R 1500,4000,ref_ref,i_40
-R 1500,1500,ref_ref,i_15
-R 1500,2000,ref_ref,i_20
-R 1500,2500,ref_ref,i_25
-R 2500,2000,ref_ref,nenx
-R 3500,2000,ref_ref,enx
-S 2000,3500,2400,3500,200,*,RIGHT,ALU1
-S 2000,1000,3600,1000,200,*,RIGHT,ALU1
-S 3500,2000,3500,2000,200,enx,LEFT,CALU3
-S 2500,2000,2500,2000,200,nenx,LEFT,CALU3
-S 2000,1000,2000,3500,100,*,DOWN,ALU1
-S 2500,1500,2500,3000,100,*,DOWN,ALU1
-S 3500,1500,3500,3000,100,*,DOWN,ALU1
-S 2000,4000,4200,4000,100,*,RIGHT,ALU1
-S 4200,1000,4200,4000,100,*,DOWN,ALU1
-S 3500,1500,3700,1500,200,*,RIGHT,ALU1
-S 3700,1500,3900,1500,300,*,RIGHT,POLY
-S 3300,3000,3500,3000,300,*,RIGHT,POLY
-S 2500,3000,2700,3000,300,*,RIGHT,POLY
-S 2500,1500,2700,1500,300,*,RIGHT,POLY
-S 3900,2000,3900,3100,100,*,UP,POLY
-S 3300,1400,3300,2000,100,*,DOWN,POLY
-S 1500,2000,3900,2000,100,*,RIGHT,POLY
-S 600,1400,2000,1400,100,*,RIGHT,POLY
-S 600,2600,1900,2600,100,*,LEFT,POLY
-S 1900,2600,1900,4000,100,*,DOWN,POLY
-S 0,3900,4500,3900,2400,*,LEFT,NWELL
-S 2700,3100,2700,4400,100,*,UP,PTRANS
-S 3600,3300,3600,4700,300,*,UP,PDIF
-S 4200,3300,4200,4200,300,*,UP,PDIF
-S 3900,3100,3900,4400,100,*,UP,PTRANS
-S 3000,3300,3000,4200,300,*,UP,PDIF
-S 3300,3100,3300,4400,100,*,UP,PTRANS
-S 2400,3300,2400,4200,300,*,UP,PDIF
-S 2400,800,2400,1200,300,*,UP,NDIF
-S 3600,800,3600,1200,300,*,UP,NDIF
-S 3000,400,3000,1200,300,*,UP,NDIF
-S 3300,600,3300,1400,100,*,UP,NTRANS
-S 2700,600,2700,1400,100,*,UP,NTRANS
-S 4200,800,4200,1200,300,*,UP,NDIF
-S 3900,600,3900,1400,100,*,UP,NTRANS
-S 300,500,300,1000,200,*,DOWN,ALU1
-S 300,3000,300,4500,200,*,DOWN,ALU1
-S 900,2800,900,4700,300,*,UP,PDIF
-S 1500,2800,1500,4700,300,*,UP,PDIF
-S 1200,2600,1200,4900,100,*,UP,PTRANS
-S 300,2800,300,4700,300,*,UP,PDIF
-S 600,2600,600,4900,100,*,UP,PTRANS
-S 300,300,300,1200,300,*,UP,NDIF
-S 1200,100,1200,1400,100,*,UP,NTRANS
-S 600,100,600,1400,100,*,UP,NTRANS
-S 1500,300,1500,1200,300,*,UP,NDIF
-S 900,300,900,1200,300,*,UP,NDIF
-S 2500,2000,3500,2000,200,*,RIGHT,TALU2
-S 0,300,4500,300,600,vss,RIGHT,CALU1
-S 0,4700,4500,4700,600,vdd,LEFT,CALU1
-S 1000,1000,1000,4000,200,q,UP,CALU1
-S 1500,1000,1500,4000,200,i,UP,CALU1
-V 3500,3000,CONT_POLY,*
-V 3700,1500,CONT_POLY,*
-V 3500,2000,CONT_VIA,*
-V 3500,2000,CONT_VIA2,*
-V 2500,3000,CONT_POLY,*
-V 2500,1500,CONT_POLY,*
-V 2500,2000,CONT_VIA,*
-V 2500,2000,CONT_VIA2,*
-V 1500,2000,CONT_POLY,*
-V 2000,1500,CONT_POLY,*
-V 2000,1500,CONT_POLY,*
-V 2000,4000,CONT_POLY,*
-V 2400,3500,CONT_DIF_P,*
-V 3000,4000,CONT_DIF_P,*
-V 3600,4500,CONT_DIF_P,*
-V 4200,4000,CONT_DIF_P,*
-V 3000,4700,CONT_BODY_N,*
-V 2200,4700,CONT_BODY_N,*
-V 4200,4700,CONT_BODY_N,*
-V 4200,1000,CONT_DIF_N,*
-V 2400,1000,CONT_DIF_N,*
-V 3600,1000,CONT_DIF_N,*
-V 3000,500,CONT_DIF_N,*
-V 3600,300,CONT_BODY_P,*
-V 4200,300,CONT_BODY_P,*
-V 900,3000,CONT_DIF_P,*
-V 2100,300,CONT_BODY_P,*
-V 300,1000,CONT_DIF_N,*
-V 900,1000,CONT_DIF_N,*
-V 900,3500,CONT_DIF_P,*
-V 900,4000,CONT_DIF_P,*
-V 300,3000,CONT_DIF_P,*
-V 1500,4500,CONT_DIF_P,*
-V 300,500,CONT_DIF_N,*
-V 1500,500,CONT_DIF_N,*
-V 300,4500,CONT_DIF_P,*
-V 300,3500,CONT_DIF_P,*
-V 300,4000,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/dp_sxlib/dp_ts_x4.vbe b/alliance/share/cells/dp_sxlib/dp_ts_x4.vbe
deleted file mode 100644
index 5793ced9..00000000
--- a/alliance/share/cells/dp_sxlib/dp_ts_x4.vbe
+++ /dev/null
@@ -1,28 +0,0 @@
-ENTITY dp_ts_x4 IS
-PORT (
-  enx	 : in  BIT;
-  nenx	 : in  BIT;
-  i	 : in  BIT;
-  q	 : out MUX_BIT BUS;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END dp_ts_x4;
-
-ARCHITECTURE vbe OF dp_ts_x4 IS
-
-BEGIN
-  ASSERT (vdd and not vss)
-  REPORT "power supply is missing on dp_ts_x4"
-  SEVERITY WARNING;
-
-  ASSERT (enx xor  nenx)
-  REPORT "wrong control signals on dp_ts_x4"
-  SEVERITY WARNING;
-
-  label0 : BLOCK (enx = '1')
-  BEGIN
-    q <= GUARDED i;
-  END BLOCK label0;
-
-END;
diff --git a/alliance/share/cells/dp_sxlib/dp_ts_x4_buf.ap b/alliance/share/cells/dp_sxlib/dp_ts_x4_buf.ap
deleted file mode 100644
index f7eda45d..00000000
--- a/alliance/share/cells/dp_sxlib/dp_ts_x4_buf.ap
+++ /dev/null
@@ -1,142 +0,0 @@
-V ALLIANCE : 6
-H dp_ts_x4_buf,P,15/11/2000,100
-A 0,0,4500,10000
-R 3500,4000,ref_ref,enx
-R 2500,4000,ref_ref,nenx
-S 3400,1500,3600,1500,200,*,LEFT,ALU2
-S 0,9700,4500,9700,600,vss,RIGHT,CALU1
-S 0,300,4500,300,600,vss,RIGHT,CALU1
-S 0,4700,4500,4700,600,vdd,RIGHT,CALU1
-S 0,5300,4500,5300,600,vdd,RIGHT,CALU1
-S 3500,1500,3500,6000,200,enx,DOWN,CALU3
-S 2500,1500,2500,6000,200,nenx,DOWN,CALU3
-S 0,5000,4500,5000,4600,*,RIGHT,NWELL
-S 3300,7100,3300,8200,100,*,DOWN,PTRANS
-S 3300,3200,3300,6500,100,*,UP,PTRANS
-S 3600,3400,3600,6300,300,*,UP,PDIF
-S 3900,3200,3900,6500,100,*,DOWN,PTRANS
-S 2400,7300,2400,8000,300,*,UP,PDIF
-S 4200,3400,4200,6300,300,*,DOWN,PDIF
-S 2700,3200,2700,6500,100,*,UP,PTRANS
-S 2400,3400,2400,6300,300,*,UP,PDIF
-S 3000,3400,3000,6300,300,*,UP,PDIF
-S 2100,3200,2100,6500,100,*,UP,PTRANS
-S 1800,3400,1800,6300,300,*,UP,PDIF
-S 3600,7300,3600,8000,300,*,UP,PDIF
-S 2700,7100,2700,8200,100,*,DOWN,PTRANS
-S 3100,7300,3100,8000,300,*,UP,PDIF
-S 2700,8700,2700,9800,100,*,UP,NTRANS
-S 3300,100,3300,1900,100,*,DOWN,NTRANS
-S 2100,100,2100,1900,100,*,UP,NTRANS
-S 2700,100,2700,1900,100,*,DOWN,NTRANS
-S 3900,100,3900,1900,100,*,DOWN,NTRANS
-S 2400,8900,2400,9600,300,*,UP,NDIF
-S 2400,300,2400,1700,300,*,UP,NDIF
-S 4200,300,4200,1700,300,*,UP,NDIF
-S 1800,300,1800,1700,300,*,UP,NDIF
-S 3000,8900,3000,9600,300,*,UP,NDIF
-S 3000,300,3000,1700,300,*,UP,NDIF
-S 3600,300,3600,1700,300,*,UP,NDIF
-S 2700,8500,3300,8500,300,*,RIGHT,POLY
-S 3300,1900,3300,3200,100,*,DOWN,POLY
-S 3900,1900,3900,3200,100,*,UP,POLY
-S 2700,1900,2700,3200,100,*,UP,POLY
-S 2100,1900,2100,3200,100,*,DOWN,POLY
-S 2700,8200,2700,8700,100,*,DOWN,POLY
-S 3300,8200,3300,8600,100,*,DOWN,POLY
-S 2400,1000,2400,4000,200,*,UP,ALU1
-S 3600,1000,3600,4000,200,*,UP,ALU1
-S 3000,500,3000,1500,200,*,UP,ALU1
-S 2400,7900,3600,7900,200,*,RIGHT,ALU1
-S 1800,500,1800,1500,200,*,UP,ALU1
-S 4200,2800,4200,6800,200,*,UP,ALU1
-S 4200,500,4200,1500,200,*,UP,ALU1
-S 4200,9000,4200,9700,200,*,UP,ALU1
-S 3000,9000,3000,9400,200,*,UP,ALU1
-S 1800,3500,1800,6800,200,*,UP,ALU1
-S 700,300,700,1500,200,*,DOWN,ALU1
-S 3000,2800,3000,7400,200,*,UP,ALU1
-S 1800,9000,1800,9700,200,*,DOWN,ALU1
-S 3300,6600,3900,6600,300,*,RIGHT,POLY
-S 3600,6600,3600,7900,200,*,UP,ALU1
-S 2400,7400,2400,9000,200,*,DOWN,ALU1
-S 2100,2200,3000,2200,300,*,RIGHT,POLY
-S 3300,2200,3900,2200,300,*,RIGHT,POLY
-S 2900,2200,3600,2200,200,*,RIGHT,ALU1
-S 3000,8500,3000,8500,100,en,LEFT,CALU1
-S 2500,1500,3600,1500,200,*,RIGHT,TALU2
-S 2500,4000,3500,4000,200,*,LEFT,TALU2
-S 2500,6000,3500,6000,200,*,RIGHT,TALU2
-V 3500,1500,CONT_VIA2,*
-V 1800,6800,CONT_BODY_N,*
-V 4200,6800,CONT_BODY_N,*
-V 3000,6800,CONT_BODY_N,*
-V 3600,7400,CONT_DIF_P,*
-V 3600,7900,CONT_DIF_P,*
-V 3600,6000,CONT_DIF_P,*
-V 2400,6000,CONT_DIF_P,*
-V 2400,4000,CONT_DIF_P,*
-V 2400,3500,CONT_DIF_P,*
-V 3600,3500,CONT_DIF_P,*
-V 3600,4000,CONT_DIF_P,*
-V 4200,6000,CONT_DIF_P,*
-V 4200,5500,CONT_DIF_P,*
-V 4200,5000,CONT_DIF_P,*
-V 4200,4500,CONT_DIF_P,*
-V 4200,3500,CONT_DIF_P,*
-V 4200,4000,CONT_DIF_P,*
-V 3000,5000,CONT_DIF_P,*
-V 3000,4000,CONT_DIF_P,*
-V 3000,5500,CONT_DIF_P,*
-V 3000,4500,CONT_DIF_P,*
-V 3000,3500,CONT_DIF_P,*
-V 1800,4000,CONT_DIF_P,*
-V 1800,4500,CONT_DIF_P,*
-V 1800,5000,CONT_DIF_P,*
-V 1800,5500,CONT_DIF_P,*
-V 1800,3500,CONT_DIF_P,*
-V 1800,6000,CONT_DIF_P,*
-V 4200,2900,CONT_BODY_N,*
-V 1800,2900,CONT_BODY_N,*
-V 3000,2900,CONT_BODY_N,*
-V 2400,7400,CONT_DIF_P,*
-V 3000,7400,CONT_DIF_P,*
-V 2400,7900,CONT_DIF_P,*
-V 3000,500,CONT_DIF_N,*
-V 2400,1000,CONT_DIF_N,*
-V 2400,1500,CONT_DIF_N,*
-V 2400,9000,CONT_DIF_N,*
-V 3000,1500,CONT_DIF_N,*
-V 4200,1000,CONT_DIF_N,*
-V 3000,1000,CONT_DIF_N,*
-V 1800,1000,CONT_DIF_N,*
-V 1800,1500,CONT_DIF_N,*
-V 1800,500,CONT_DIF_N,*
-V 3600,1500,CONT_DIF_N,*
-V 4200,1500,CONT_DIF_N,*
-V 4200,500,CONT_DIF_N,*
-V 3600,1000,CONT_DIF_N,*
-V 3000,9000,CONT_DIF_N,*
-V 3000,9500,CONT_DIF_N,*
-V 1800,9000,CONT_BODY_P,*
-V 4200,9000,CONT_BODY_P,*
-V 1800,9700,CONT_BODY_P,*
-V 4200,9700,CONT_BODY_P,*
-V 700,300,CONT_BODY_P,*
-V 700,1500,CONT_BODY_P,*
-V 700,900,CONT_BODY_P,*
-V 3000,8500,CONT_POLY,*
-V 2500,1500,CONT_VIA,*
-V 3500,4000,CONT_VIA,*
-V 3600,1500,CONT_VIA,*
-V 3500,6000,CONT_VIA,*
-V 2500,6000,CONT_VIA,*
-V 2500,4000,CONT_VIA,*
-V 2500,1500,CONT_VIA2,*
-V 3500,4000,CONT_VIA2,*
-V 2500,4000,CONT_VIA2,*
-V 2500,6000,CONT_VIA2,*
-V 3500,6000,CONT_VIA2,*
-V 3600,6600,CONT_POLY,*
-V 2900,2200,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/dp_sxlib/dp_ts_x4_buf.vbe b/alliance/share/cells/dp_sxlib/dp_ts_x4_buf.vbe
deleted file mode 100644
index bc108cba..00000000
--- a/alliance/share/cells/dp_sxlib/dp_ts_x4_buf.vbe
+++ /dev/null
@@ -1,21 +0,0 @@
-ENTITY dp_ts_x4_buf IS
-PORT (
-  en	 : in  BIT;
-  enx	 : out BIT;
-  nenx	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END dp_ts_x4_buf;
-
-ARCHITECTURE vbe OF dp_ts_x4_buf IS
-
-BEGIN
-  ASSERT (vdd and not vss)
-  REPORT "power supply is missing on dp_ts_x4_buf"
-  SEVERITY WARNING;
-
-  enx <= en;
-  nenx <= not en;
-
-END;
diff --git a/alliance/share/cells/dp_sxlib/dp_ts_x8.ap b/alliance/share/cells/dp_sxlib/dp_ts_x8.ap
deleted file mode 100644
index bd3be6d5..00000000
--- a/alliance/share/cells/dp_sxlib/dp_ts_x8.ap
+++ /dev/null
@@ -1,126 +0,0 @@
-V ALLIANCE : 6
-H dp_ts_x8,P,15/11/2000,100
-A 0,0,5500,5000
-R 4500,2000,ref_ref,enx
-R 3500,2000,ref_ref,nenx
-R 1000,1500,ref_ref,q_15
-R 1000,4000,ref_ref,q_40
-R 1000,3500,ref_ref,q_35
-R 500,1500,ref_ref,i_15
-R 500,3500,ref_ref,i_35
-R 500,3000,ref_ref,i_30
-R 500,1000,ref_ref,i_10
-R 1000,1000,ref_ref,q_10
-R 1000,3000,ref_ref,q_30
-R 1000,2500,ref_ref,q_25
-R 1000,2000,ref_ref,q_20
-R 500,4000,ref_ref,i_40
-R 500,2500,ref_ref,i_25
-R 500,2000,ref_ref,i_20
-S 700,1400,3000,1400,100,*,RIGHT,POLY
-S 700,2600,3000,2600,100,*,LEFT,POLY
-S 500,1000,500,4000,200,i,UP,CALU1
-S 1000,1000,1000,4000,200,q,UP,CALU1
-S 0,4700,5500,4700,600,vdd,LEFT,CALU1
-S 0,300,5500,300,600,vss,RIGHT,CALU1
-S 1000,2000,2200,2000,200,*,RIGHT,ALU1
-S 700,2600,700,4900,100,*,UP,PTRANS
-S 1300,2600,1300,4900,100,*,UP,PTRANS
-S 400,2800,400,4700,300,*,UP,PDIF
-S 1000,2800,1000,4700,300,*,UP,PDIF
-S 2500,2600,2500,4900,100,*,UP,PTRANS
-S 1600,2800,1600,4700,300,*,UP,PDIF
-S 1900,2600,1900,4900,100,*,UP,PTRANS
-S 2200,2800,2200,4700,300,*,UP,PDIF
-S 2800,2800,2800,4700,300,*,UP,PDIF
-S 1300,100,1300,1400,100,*,UP,NTRANS
-S 700,100,700,1400,100,*,UP,NTRANS
-S 2500,100,2500,1400,100,*,UP,NTRANS
-S 1900,100,1900,1400,100,*,UP,NTRANS
-S 1600,300,1600,1200,300,*,UP,NDIF
-S 400,300,400,1200,300,*,UP,NDIF
-S 1000,300,1000,1200,300,*,UP,NDIF
-S 2800,300,2800,1200,300,*,UP,NDIF
-S 2200,300,2200,1200,300,*,UP,NDIF
-S 1600,500,1600,1000,200,*,DOWN,ALU1
-S 1600,3000,1600,4500,200,*,DOWN,ALU1
-S 2200,1000,2200,4000,200,*,UP,ALU1
-S 0,3900,5500,3900,2400,*,LEFT,NWELL
-S 3700,3100,3700,4400,100,*,UP,PTRANS
-S 4600,3300,4600,4700,300,*,UP,PDIF
-S 5200,3300,5200,4200,300,*,UP,PDIF
-S 4900,3100,4900,4400,100,*,UP,PTRANS
-S 4000,3300,4000,4200,300,*,UP,PDIF
-S 4300,3100,4300,4400,100,*,UP,PTRANS
-S 3400,3300,3400,4200,300,*,UP,PDIF
-S 4300,600,4300,1400,100,*,UP,NTRANS
-S 3700,600,3700,1400,100,*,UP,NTRANS
-S 4900,600,4900,1400,100,*,UP,NTRANS
-S 3400,800,3400,1200,300,*,UP,NDIF
-S 4600,800,4600,1200,300,*,UP,NDIF
-S 4000,400,4000,1200,300,*,UP,NDIF
-S 5200,800,5200,1200,300,*,UP,NDIF
-S 500,2000,4900,2000,100,*,RIGHT,POLY
-S 4700,1500,4900,1500,300,*,RIGHT,POLY
-S 4300,3000,4500,3000,300,*,RIGHT,POLY
-S 3500,3000,3700,3000,300,*,RIGHT,POLY
-S 3500,1500,3700,1500,300,*,RIGHT,POLY
-S 4900,2000,4900,3100,100,*,UP,POLY
-S 4300,1400,4300,2000,100,*,DOWN,POLY
-S 2900,4000,5200,4000,100,*,RIGHT,ALU1
-S 2900,1000,2900,1500,100,*,DOWN,ALU1
-S 4000,1000,4000,3500,100,*,DOWN,ALU1
-S 5200,1000,5200,4000,100,*,DOWN,ALU1
-S 3500,1500,3500,3000,200,*,DOWN,ALU1
-S 2900,2500,2900,4000,100,*,DOWN,ALU1
-S 2900,1000,4600,1000,100,*,RIGHT,ALU1
-S 3400,3500,4000,3500,100,*,RIGHT,ALU1
-S 4500,1500,4700,1500,200,*,RIGHT,ALU1
-S 3500,2000,4500,2000,200,*,RIGHT,TALU2
-S 4500,2000,4500,2000,200,enx,LEFT,CALU3
-S 3500,2000,3500,2000,200,nenx,LEFT,CALU3
-S 4500,1500,4500,3000,200,*,DOWN,ALU1
-V 3400,4700,CONT_BODY_N,*
-V 3400,300,CONT_BODY_P,*
-V 2200,4000,CONT_DIF_P,*
-V 2200,3500,CONT_DIF_P,*
-V 400,4500,CONT_DIF_P,*
-V 1000,3500,CONT_DIF_P,*
-V 1000,4000,CONT_DIF_P,*
-V 1000,3000,CONT_DIF_P,*
-V 2200,3000,CONT_DIF_P,*
-V 1600,3000,CONT_DIF_P,*
-V 1600,4500,CONT_DIF_P,*
-V 2800,4500,CONT_DIF_P,*
-V 1600,3500,CONT_DIF_P,*
-V 1600,4000,CONT_DIF_P,*
-V 1600,1000,CONT_DIF_N,*
-V 2200,1000,CONT_DIF_N,*
-V 1600,500,CONT_DIF_N,*
-V 1000,1000,CONT_DIF_N,*
-V 400,500,CONT_DIF_N,*
-V 2800,500,CONT_DIF_N,*
-V 500,2000,CONT_POLY,*
-V 5200,4000,CONT_DIF_P,*
-V 4000,4700,CONT_BODY_N,*
-V 5200,4700,CONT_BODY_N,*
-V 3400,3500,CONT_DIF_P,*
-V 4000,4000,CONT_DIF_P,*
-V 4600,4500,CONT_DIF_P,*
-V 5200,1000,CONT_DIF_N,*
-V 3400,1000,CONT_DIF_N,*
-V 4600,1000,CONT_DIF_N,*
-V 4000,500,CONT_DIF_N,*
-V 4600,300,CONT_BODY_P,*
-V 5200,300,CONT_BODY_P,*
-V 2900,2500,CONT_POLY,*
-V 4500,3000,CONT_POLY,*
-V 4700,1500,CONT_POLY,*
-V 3500,3000,CONT_POLY,*
-V 3500,1500,CONT_POLY,*
-V 2900,1500,CONT_POLY,*
-V 4500,2000,CONT_VIA,*
-V 3500,2000,CONT_VIA,*
-V 4500,2000,CONT_VIA2,*
-V 3500,2000,CONT_VIA2,*
-EOF
diff --git a/alliance/share/cells/dp_sxlib/dp_ts_x8.vbe b/alliance/share/cells/dp_sxlib/dp_ts_x8.vbe
deleted file mode 100644
index 9f939f6a..00000000
--- a/alliance/share/cells/dp_sxlib/dp_ts_x8.vbe
+++ /dev/null
@@ -1,28 +0,0 @@
-ENTITY dp_ts_x8 IS
-PORT (
-  enx	 : in  BIT;
-  nenx	 : in  BIT;
-  i	 : in  BIT;
-  q	 : out MUX_BIT BUS;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END dp_ts_x8;
-
-ARCHITECTURE vbe OF dp_ts_x8 IS
-
-BEGIN
-  ASSERT (vdd and not vss)
-  REPORT "power supply is missing on dp_ts_x8"
-  SEVERITY WARNING;
-
-  ASSERT (enx xor  nenx)
-  REPORT "wrong control signals on dp_ts_x8"
-  SEVERITY WARNING;
-
-  label0 : BLOCK (enx = '1')
-  BEGIN
-    q <= GUARDED i;
-  END BLOCK label0;
-
-END;
diff --git a/alliance/share/cells/dp_sxlib/dp_ts_x8_buf.ap b/alliance/share/cells/dp_sxlib/dp_ts_x8_buf.ap
deleted file mode 100644
index aa84ba43..00000000
--- a/alliance/share/cells/dp_sxlib/dp_ts_x8_buf.ap
+++ /dev/null
@@ -1,142 +0,0 @@
-V ALLIANCE : 6
-H dp_ts_x8_buf,P,14/11/2000,10
-A -100,0,450,1000
-R 250,400,ref_ref,nenx
-R 350,400,ref_ref,enx
-S 250,600,350,600,20,*,RIGHT,TALU2
-S 250,400,350,400,20,*,RIGHT,TALU2
-S 250,150,350,150,20,*,RIGHT,TALU2
-S -100,970,450,970,60,vss,RIGHT,CALU1
-S -100,30,450,30,60,vss,RIGHT,CALU1
-S -100,500,450,500,460,*,RIGHT,NWELL
-S -100,470,450,470,60,vdd,RIGHT,CALU1
-S -100,530,450,530,60,vdd,RIGHT,CALU1
-S 330,220,390,220,30,*,RIGHT,POLY
-S 290,220,360,220,20,*,RIGHT,ALU1
-S 210,220,300,220,30,*,RIGHT,POLY
-S 360,660,360,790,20,*,UP,ALU1
-S 240,740,240,900,20,*,DOWN,ALU1
-S 330,660,390,660,30,*,RIGHT,POLY
-S 180,900,180,970,20,*,DOWN,ALU1
-S 300,280,300,740,20,*,UP,ALU1
-S 70,30,70,150,20,*,DOWN,ALU1
-S 180,350,180,680,20,*,UP,ALU1
-S 300,900,300,940,20,*,UP,ALU1
-S 420,900,420,970,20,*,UP,ALU1
-S 420,50,420,150,20,*,UP,ALU1
-S 420,280,420,680,20,*,UP,ALU1
-S 180,50,180,150,20,*,UP,ALU1
-S 240,790,360,790,20,*,RIGHT,ALU1
-S 300,50,300,150,20,*,UP,ALU1
-S 360,100,360,400,20,*,UP,ALU1
-S 240,100,240,400,20,*,UP,ALU1
-S 330,820,330,860,10,*,DOWN,POLY
-S 270,820,270,870,10,*,DOWN,POLY
-S 210,190,210,320,10,*,DOWN,POLY
-S 270,190,270,320,10,*,UP,POLY
-S 390,190,390,320,10,*,UP,POLY
-S 330,190,330,320,10,*,DOWN,POLY
-S 270,850,330,850,30,*,RIGHT,POLY
-S 360,30,360,170,30,*,UP,NDIF
-S 300,30,300,170,30,*,UP,NDIF
-S 300,890,300,960,30,*,UP,NDIF
-S 180,30,180,170,30,*,UP,NDIF
-S 420,30,420,170,30,*,UP,NDIF
-S 240,30,240,170,30,*,UP,NDIF
-S 240,890,240,960,30,*,UP,NDIF
-S 390,10,390,190,10,*,DOWN,NTRANS
-S 270,10,270,190,10,*,DOWN,NTRANS
-S 210,10,210,190,10,*,UP,NTRANS
-S 330,10,330,190,10,*,DOWN,NTRANS
-S 270,870,270,980,10,*,UP,NTRANS
-S 310,730,310,800,30,*,UP,PDIF
-S 270,710,270,820,10,*,DOWN,PTRANS
-S 360,730,360,800,30,*,UP,PDIF
-S 180,340,180,630,30,*,UP,PDIF
-S 210,320,210,650,10,*,UP,PTRANS
-S 300,340,300,630,30,*,UP,PDIF
-S 240,340,240,630,30,*,UP,PDIF
-S 270,320,270,650,10,*,UP,PTRANS
-S 420,340,420,630,30,*,DOWN,PDIF
-S 240,730,240,800,30,*,UP,PDIF
-S 390,320,390,650,10,*,DOWN,PTRANS
-S 360,340,360,630,30,*,UP,PDIF
-S 330,320,330,650,10,*,UP,PTRANS
-S 330,710,330,820,10,*,DOWN,PTRANS
-S 250,150,250,600,20,nenx,DOWN,CALU3
-S 350,150,350,600,20,enx,DOWN,CALU3
-S 300,850,300,850,10,en,LEFT,CALU1
-S 350,150,360,150,20,*,RIGHT,ALU1
-V 290,220,CONT_POLY,*
-V 360,660,CONT_POLY,*
-V 350,600,CONT_VIA2,*
-V 250,600,CONT_VIA2,*
-V 250,400,CONT_VIA2,*
-V 350,400,CONT_VIA2,*
-V 250,150,CONT_VIA2,*
-V 250,400,CONT_VIA,*
-V 250,600,CONT_VIA,*
-V 350,600,CONT_VIA,*
-V 350,400,CONT_VIA,*
-V 250,150,CONT_VIA,*
-V 300,850,CONT_POLY,*
-V 70,90,CONT_BODY_P,*
-V 70,150,CONT_BODY_P,*
-V 70,30,CONT_BODY_P,*
-V 420,970,CONT_BODY_P,*
-V 180,970,CONT_BODY_P,*
-V 420,900,CONT_BODY_P,*
-V 180,900,CONT_BODY_P,*
-V 300,950,CONT_DIF_N,*
-V 300,900,CONT_DIF_N,*
-V 360,100,CONT_DIF_N,*
-V 420,50,CONT_DIF_N,*
-V 420,150,CONT_DIF_N,*
-V 360,150,CONT_DIF_N,*
-V 180,50,CONT_DIF_N,*
-V 180,150,CONT_DIF_N,*
-V 180,100,CONT_DIF_N,*
-V 300,100,CONT_DIF_N,*
-V 420,100,CONT_DIF_N,*
-V 300,150,CONT_DIF_N,*
-V 240,900,CONT_DIF_N,*
-V 240,150,CONT_DIF_N,*
-V 240,100,CONT_DIF_N,*
-V 300,50,CONT_DIF_N,*
-V 240,790,CONT_DIF_P,*
-V 300,740,CONT_DIF_P,*
-V 240,740,CONT_DIF_P,*
-V 300,290,CONT_BODY_N,*
-V 180,290,CONT_BODY_N,*
-V 420,290,CONT_BODY_N,*
-V 180,600,CONT_DIF_P,*
-V 180,350,CONT_DIF_P,*
-V 180,550,CONT_DIF_P,*
-V 180,500,CONT_DIF_P,*
-V 180,450,CONT_DIF_P,*
-V 180,400,CONT_DIF_P,*
-V 300,350,CONT_DIF_P,*
-V 300,450,CONT_DIF_P,*
-V 300,550,CONT_DIF_P,*
-V 300,400,CONT_DIF_P,*
-V 300,500,CONT_DIF_P,*
-V 420,400,CONT_DIF_P,*
-V 420,350,CONT_DIF_P,*
-V 420,450,CONT_DIF_P,*
-V 420,500,CONT_DIF_P,*
-V 420,550,CONT_DIF_P,*
-V 420,600,CONT_DIF_P,*
-V 360,400,CONT_DIF_P,*
-V 360,350,CONT_DIF_P,*
-V 240,350,CONT_DIF_P,*
-V 240,400,CONT_DIF_P,*
-V 240,600,CONT_DIF_P,*
-V 360,600,CONT_DIF_P,*
-V 360,790,CONT_DIF_P,*
-V 360,740,CONT_DIF_P,*
-V 300,680,CONT_BODY_N,*
-V 420,680,CONT_BODY_N,*
-V 180,680,CONT_BODY_N,*
-V 350,150,CONT_VIA2,*
-V 350,150,CONT_VIA,*
-EOF
diff --git a/alliance/share/cells/dp_sxlib/dp_ts_x8_buf.vbe b/alliance/share/cells/dp_sxlib/dp_ts_x8_buf.vbe
deleted file mode 100644
index 66bbb142..00000000
--- a/alliance/share/cells/dp_sxlib/dp_ts_x8_buf.vbe
+++ /dev/null
@@ -1,21 +0,0 @@
-ENTITY dp_ts_x8_buf IS
-PORT (
-  en	 : in  BIT;
-  enx	 : out BIT;
-  nenx	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END dp_ts_x8_buf;
-
-ARCHITECTURE vbe OF dp_ts_x8_buf IS
-
-BEGIN
-  ASSERT (vdd and not vss)
-  REPORT "power supply is missing on dp_ts_x8_buf"
-  SEVERITY WARNING;
-
-  enx <= en;
-  nenx <= not en;
-
-END;
diff --git a/alliance/share/cells/padlib/CATAL b/alliance/share/cells/padlib/CATAL
deleted file mode 100644
index 34c210f8..00000000
--- a/alliance/share/cells/padlib/CATAL
+++ /dev/null
@@ -1,35 +0,0 @@
-padreal G
-padreal C
-pck_sp C
-pi_sp C
-piot_sp C
-piotw_sp C
-pot_sp C
-potw_sp C
-po_sp C
-pow_sp C
-pvdde_sp C
-pvddeck_sp C
-pvddi_sp C
-pvddick_sp C
-pvsse_sp C
-pvsseck_sp C
-pvssi_sp C
-pvssick_sp C
-palck_sp C
-pali_sp C
-paliot_sp C
-paliotw_sp C
-palo_sp C
-palot_sp C
-palotw_sp C
-palow_sp C
-palvdde_sp C
-palvddeck_sp C
-palvddi_sp C
-palvddick_sp C
-palvsse_sp C
-palvsseck_sp C
-palvssi_sp C
-palvssick_sp C
-corner_sp C
diff --git a/alliance/share/cells/padlib/corner_sp.ap b/alliance/share/cells/padlib/corner_sp.ap
deleted file mode 100644
index d71aabe0..00000000
--- a/alliance/share/cells/padlib/corner_sp.ap
+++ /dev/null
@@ -1,24 +0,0 @@
-V ALLIANCE : 6
-H corner_sp,P,13/10/2000,100
-A 0,0,50000,50000
-C 48700,0,1200,ck,0,SOUTH,ALU2
-C 45300,0,4000,vssi,0,SOUTH,ALU2
-C 40900,0,4000,vddi,0,SOUTH,ALU2
-C 19700,0,12000,vsse,0,SOUTH,ALU2
-C 32500,0,12000,vdde,0,SOUTH,ALU2
-C 50000,4700,4000,vssi,1,EAST,ALU2
-C 50000,9100,4000,vddi,1,EAST,ALU2
-C 50000,30300,12000,vsse,1,EAST,ALU2
-C 50000,17500,12000,vdde,1,EAST,ALU2
-C 50000,1300,1200,ck,1,EAST,ALU2
-S 19700,0,19700,36200,12000,*,UP,ALU2
-S 48200,1300,50000,1300,1200,*,RIGHT,ALU2
-S 48700,100,48700,1800,1200,*,UP,ALU2
-S 43400,4700,50000,4700,4000,*,LEFT,ALU2
-S 45300,0,45300,6600,4000,*,UP,ALU2
-S 39000,9100,50000,9100,4000,*,LEFT,ALU2
-S 40900,0,40900,11000,4000,*,UP,ALU2
-S 26600,17500,50000,17500,12000,*,LEFT,ALU2
-S 32500,0,32500,23400,12000,*,UP,ALU2
-S 13800,30300,50000,30300,12000,*,LEFT,ALU2
-EOF
diff --git a/alliance/share/cells/padlib/corner_sp.vbe b/alliance/share/cells/padlib/corner_sp.vbe
deleted file mode 100644
index bd9d7ca6..00000000
--- a/alliance/share/cells/padlib/corner_sp.vbe
+++ /dev/null
@@ -1,27 +0,0 @@
--- VHDL data flow description generated from `corner_sp`
---		date : Thu Feb 23 17:06:23 1995
-
-
--- Entity Declaration
-
-ENTITY corner_sp IS
-  PORT (
-  ck : in BIT;	-- ck
-  vdde : in BIT;	-- vdde
-  vddi : in BIT;	-- vddi
-  vsse : in BIT;	-- vsse
-  vssi : in BIT	-- vssi
-  );
-END corner_sp;
-
-
--- Architecture Declaration
-
-ARCHITECTURE behaviour_data_flow OF corner_sp IS
-
-BEGIN
-  ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1')
-    REPORT "power supply is missing on corner_sp"
-    SEVERITY WARNING;
-
-END;
diff --git a/alliance/share/cells/padlib/padreal.ap b/alliance/share/cells/padlib/padreal.ap
deleted file mode 100644
index d5822782..00000000
--- a/alliance/share/cells/padlib/padreal.ap
+++ /dev/null
@@ -1,7 +0,0 @@
-V ALLIANCE : 6
-H padreal,P,13/10/2000,100
-A 0,7600,17200,21300
-C 8600,7600,10000,in,0,SOUTH,ALU1
-S 8600,7700,8600,21200,10000,*,UP,ALU1
-B 8600,15200,12200,12200,CONT_VIA,*
-EOF
diff --git a/alliance/share/cells/padlib/padreal.cif b/alliance/share/cells/padlib/padreal.cif
deleted file mode 100644
index 8ce61cd4..00000000
--- a/alliance/share/cells/padlib/padreal.cif
+++ /dev/null
@@ -1,24 +0,0 @@
-(rds to CIF driver version 1.03
-technology /users/alc/distrib/dev/alliance-3.2/etc/prol10_7.rds
-Wed May 21 16:49:13 1997
-padreal
-distrib);
-
-DS1 5 2;
-9 padreal;
-(AB : 0.00, 0.00 150.50, 118.15 in micron);
-4A 0 0 6020 4726; 
-LCC;
-B4000 4000 3010 3320;
-LCM;
-B3500 1320 3010 660;
-B4400 4400 3010 3320;
-LCM2;
-B4400 4400 3010 3320;
-LCG;
-B4000 4000 3010 3320;
-DF;
-
-C1;
-(AB : 0.00, 0.00 150.50, 118.15 in micron); 
-E 
diff --git a/alliance/share/cells/padlib/padsymb.db b/alliance/share/cells/padlib/padsymb.db
deleted file mode 100644
index 7ef08ac8..00000000
--- a/alliance/share/cells/padlib/padsymb.db
+++ /dev/null
@@ -1,60 +0,0 @@
-#cell1 padsymb any library 31744 v7r5.6
-# 24-Nov-91 14:16 24-Nov-91 14:16 stacs * .
-v1(50,padsymb
-(33,CP
-[padreal,cp]
-[palck_sp,cp]
-[pali_sp,cp]
-[paliot_sp,cp]
-[paliotw_sp,cp]
-[palo_sp,cp]
-[palot_sp,cp]
-[palotw_sp,cp]
-[palow_sp,cp]
-[palvdde_sp,cp]
-[palvddeck_sp,cp]
-[palvddi_sp,cp]
-[palvddick_sp,cp]
-[palvsse_sp,cp]
-[palvsseck_sp,cp]
-[palvssi_sp,cp]
-[palvssick_sp,cp]
-[pck_sp,cp]
-[pi_sp,cp]
-[piot_sp,cp]
-[piotw_sp,cp]
-[po_sp,cp]
-[pot_sp,cp]
-[potw_sp,cp]
-[pow_sp,cp]
-[pvdde_sp,cp]
-[pvddeck_sp,cp]
-[pvddi_sp,cp]
-[pvddick_sp,cp]
-[pvsse_sp,cp]
-[pvsseck_sp,cp]
-[pvssi_sp,cp]
-[pvssick_sp,cp]
-)
-(16,HNS
-[pck_sp,hns]
-[pi_sp,hns]
-[piot_sp,hns]
-[piotw_sp,hns]
-[po_sp,hns]
-[pot_sp,hns]
-[potw_sp,hns]
-[pow_sp,hns]
-[pvdde_sp,hns]
-[pvddeck_sp,hns]
-[pvddi_sp,hns]
-[pvddick_sp,hns]
-[pvsse_sp,hns]
-[pvsseck_sp,hns]
-[pvssi_sp,hns]
-[pvssick_sp,hns]
-)
-(1,CIF
-[padreal,cif]
-)
-)
diff --git a/alliance/share/cells/padlib/palck_sp.ap b/alliance/share/cells/padlib/palck_sp.ap
deleted file mode 100644
index ac3f5a7c..00000000
--- a/alliance/share/cells/padlib/palck_sp.ap
+++ /dev/null
@@ -1,823 +0,0 @@
-V ALLIANCE : 6
-H palck_sp,P,13/10/2000,100
-A 300,100,17500,36400
-C 300,17600,12000,vdde,0,WEST,ALU2
-C 300,30400,12000,vsse,0,WEST,ALU2
-C 17500,30400,12000,vsse,1,EAST,ALU2
-C 17500,17600,12000,vdde,1,EAST,ALU2
-C 17500,9200,4000,vddi,1,EAST,ALU2
-C 17500,4800,4000,vssi,1,EAST,ALU2
-C 17500,1400,1200,ck,1,EAST,ALU2
-C 300,1400,1200,ck,0,WEST,ALU2
-C 300,9200,4000,vddi,0,WEST,ALU2
-C 300,4800,4000,vssi,0,WEST,ALU2
-S 15000,1000,15000,4900,200,*,UP,ALU1
-S 13800,1000,13800,4900,200,*,UP,ALU1
-S 12600,1000,12600,4900,200,*,UP,ALU1
-S 11300,6400,12000,6400,200,*,RIGHT,ALU1
-S 8400,500,15600,500,200,*,RIGHT,ALU1
-S 15600,500,15600,4000,200,*,UP,ALU1
-S 14400,500,14400,4000,200,*,UP,ALU1
-S 13200,500,13200,4000,200,*,UP,ALU1
-S 12000,500,12000,4000,200,*,UP,ALU1
-S 10800,500,10800,9200,200,*,UP,ALU1
-S 9600,500,9600,9200,200,*,UP,ALU1
-S 8400,500,8400,5500,200,*,UP,ALU1
-S 7800,4500,8400,4500,200,*,RIGHT,ALU1
-S 7800,6400,8400,6400,200,*,RIGHT,ALU1
-S 3700,5900,3700,12800,200,*,UP,ALU1
-S 1800,12800,11400,12800,200,*,RIGHT,ALU1
-S 2200,5900,2200,12800,1000,*,UP,ALU1
-S 4900,5900,4900,12800,200,*,UP,ALU1
-S 6100,5900,6100,12800,200,*,UP,ALU1
-S 6400,14400,8200,14400,200,*,RIGHT,ALU1
-S 6700,14400,6700,23400,800,*,UP,ALU1
-S 11400,7300,11400,12800,200,*,UP,ALU1
-S 7300,5900,7300,12800,200,*,UP,ALU1
-S 9000,5900,9000,12800,200,*,UP,ALU1
-S 10200,5900,10200,12800,200,*,UP,ALU1
-S 12000,4400,12000,13400,200,*,UP,ALU1
-S 8800,13400,12000,13400,200,*,RIGHT,ALU1
-S 8800,13400,8800,15100,200,*,UP,ALU1
-S 8200,14400,8200,23400,200,*,UP,ALU1
-S 9300,25100,10100,25100,200,*,RIGHT,ALU1
-S 9700,25100,9700,29600,1000,*,UP,ALU1
-S 300,30400,17500,30400,12000,log.vsse,RIGHT,ALU2
-S 8700,6400,11800,6400,300,*,RIGHT,POLY
-S 11400,6800,11400,12900,300,*,UP,NTIE
-S 1800,6000,11400,6000,300,*,RIGHT,NTIE
-S 13200,4500,13200,5400,200,*,DOWN,ALU1
-S 14400,4500,14400,5400,200,*,DOWN,ALU1
-S 12000,5400,14400,5400,200,*,RIGHT,ALU1
-S 1700,12800,11400,12800,300,*,RIGHT,NTIE
-S 1600,9400,11600,9400,7200,*,RIGHT,NWELL
-S 10200,6700,10200,9300,300,*,UP,PDIF
-S 16200,1000,16200,5000,200,*,UP,ALU1
-S 11400,1000,11400,5000,200,*,UP,ALU1
-S 10200,1000,10200,5000,200,*,UP,ALU1
-S 8700,4500,15300,4500,300,*,RIGHT,POLY
-S 1800,1100,16200,1100,300,*,RIGHT,PTIE
-S 1800,4900,16200,4900,300,*,RIGHT,PTIE
-S 12000,1600,12000,4200,200,*,UP,NDIF
-S 13800,1600,13800,4200,200,*,UP,NDIF
-S 15600,1600,15600,4200,300,*,UP,NDIF
-S 15600,1600,15600,4200,200,*,UP,NDIF
-S 16200,1000,16200,5000,300,*,UP,PTIE
-S 14700,1400,14700,4400,100,*,UP,NTRANS
-S 14100,1400,14100,4400,100,*,UP,NTRANS
-S 15000,1600,15000,4200,200,*,UP,NDIF
-S 14400,1600,14400,4200,200,*,UP,NDIF
-S 15300,1400,15300,4400,100,*,UP,NTRANS
-S 12900,1400,12900,4400,100,*,UP,NTRANS
-S 12600,1600,12600,4200,200,*,UP,NDIF
-S 13200,1600,13200,4200,200,*,UP,NDIF
-S 12300,1400,12300,4400,100,*,UP,NTRANS
-S 13500,1400,13500,4400,100,*,UP,NTRANS
-S 11100,1400,11100,4400,100,*,UP,NTRANS
-S 11700,1400,11700,4400,100,*,UP,NTRANS
-S 10500,1400,10500,4400,100,*,UP,NTRANS
-S 10200,1600,10200,4200,300,*,UP,NDIF
-S 11400,1600,11400,4200,200,*,UP,NDIF
-S 10800,1600,10800,4200,200,*,UP,NDIF
-S 10800,6700,10800,9300,300,*,UP,PDIF
-S 10200,6700,10200,9300,300,*,UP,PDIF
-S 10500,6500,10500,9500,100,*,UP,PTRANS
-S 9600,6700,9600,9300,300,*,UP,PDIF
-S 9900,6500,9900,9500,100,*,UP,PTRANS
-S 9300,6500,9300,9500,100,*,UP,PTRANS
-S 9900,1400,9900,4400,100,*,UP,NTRANS
-S 9300,1400,9300,4400,100,*,UP,NTRANS
-S 3100,1600,3100,4200,200,*,UP,NDIF
-S 8400,1600,8400,4200,300,*,UP,NDIF
-S 8700,1400,8700,4400,100,*,UP,NTRANS
-S 9000,1600,9000,4200,200,*,UP,NDIF
-S 9600,1600,9600,4200,200,*,UP,NDIF
-S 3700,1600,3700,4200,200,*,UP,NDIF
-S 5200,1400,5200,4400,100,*,UP,NTRANS
-S 4600,1400,4600,4400,100,*,UP,NTRANS
-S 2800,1400,2800,4400,100,*,UP,NTRANS
-S 6700,1600,6700,4200,200,*,UP,NDIF
-S 4000,1400,4000,4400,100,*,UP,NTRANS
-S 3400,1400,3400,4400,100,*,UP,NTRANS
-S 6100,1600,6100,4200,200,*,UP,NDIF
-S 5500,1600,5500,4200,200,*,UP,NDIF
-S 4900,1600,4900,4200,200,*,UP,NDIF
-S 4300,1600,4300,4200,200,*,UP,NDIF
-S 2500,1600,2500,4200,300,*,UP,NDIF
-S 7300,1600,7300,4200,400,*,UP,NDIF
-S 7000,1400,7000,4400,100,*,UP,NTRANS
-S 6400,1400,6400,4400,100,*,UP,NTRANS
-S 5800,1400,5800,4400,100,*,UP,NTRANS
-S 2500,6700,2500,12300,400,*,UP,PDIF
-S 8400,6700,8400,9300,400,*,UP,PDIF
-S 8700,6500,8700,9500,100,*,UP,PTRANS
-S 9000,6700,9000,9300,300,*,UP,PDIF
-S 7000,6500,7000,12500,100,*,UP,PTRANS
-S 3100,6700,3100,12300,200,*,UP,PDIF
-S 3700,6700,3700,12300,200,*,UP,PDIF
-S 4300,6700,4300,12300,200,*,UP,PDIF
-S 4900,6700,4900,12300,200,*,UP,PDIF
-S 5500,6700,5500,12300,200,*,UP,PDIF
-S 6100,6700,6100,12300,200,*,UP,PDIF
-S 6700,6700,6700,12300,200,*,UP,PDIF
-S 4600,6500,4600,12500,100,*,UP,PTRANS
-S 5200,6500,5200,12500,100,*,UP,PTRANS
-S 5800,6500,5800,12500,100,*,UP,PTRANS
-S 6400,6500,6400,12500,100,*,UP,PTRANS
-S 2800,6500,2800,12500,100,*,UP,PTRANS
-S 3400,6500,3400,12500,100,*,UP,PTRANS
-S 4000,6500,4000,12500,100,*,UP,PTRANS
-S 3700,6700,3700,12300,400,*,UP,PDIF
-S 4900,6700,4900,12300,400,*,UP,PDIF
-S 6100,6700,6100,12300,400,*,UP,PDIF
-S 7300,6700,7300,12300,400,*,UP,PDIF
-S 1800,5900,1800,12800,300,*,UP,NTIE
-S 1900,1200,1900,5000,300,*,UP,PTIE
-S 2800,4500,8400,4500,300,*,RIGHT,POLY
-S 2800,12500,7000,12500,100,*,RIGHT,POLY
-S 2800,1400,7000,1400,100,*,RIGHT,POLY
-S 8700,6300,8700,6500,100,*,UP,POLY
-S 2800,6400,8400,6400,300,*,RIGHT,POLY
-S 8400,5300,8400,9200,200,*,UP,ALU1
-S 9000,1000,9000,5000,200,*,UP,ALU1
-S 2200,1000,2200,5000,900,*,UP,ALU1
-S 7300,1000,7300,5000,200,*,UP,ALU1
-S 6100,1000,6100,5000,200,*,UP,ALU1
-S 4900,1000,4900,5000,200,*,UP,ALU1
-S 3700,1000,3700,5000,200,*,UP,ALU1
-S 3100,1000,3100,12300,200,*,UP,ALU1
-S 4300,1000,4300,12300,200,*,UP,ALU1
-S 5500,1000,5500,12300,200,*,UP,ALU1
-S 6700,1000,6700,12300,200,*,UP,ALU1
-S 7600,15000,7600,29900,200,*,UP,ALU1
-S 8800,15000,8800,29900,200,*,UP,ALU1
-S 8200,24500,8200,29600,200,*,UP,ALU1
-S 9400,25600,9400,29000,300,*,UP,NDIF
-S 8800,25600,8800,29000,300,*,UP,NDIF
-S 8200,25600,8200,29000,300,*,UP,NDIF
-S 7600,25600,7600,29000,300,*,UP,NDIF
-S 7300,25400,7300,29200,100,*,UP,NTRANS
-S 7900,25400,7900,29200,100,*,UP,NTRANS
-S 8500,25400,8500,29200,100,*,UP,NTRANS
-S 9100,25400,9100,29200,100,*,UP,NTRANS
-S 7100,29500,9500,29500,300,*,RIGHT,PTIE
-S 9400,14900,9400,22800,300,*,UP,PDIF
-S 8800,14900,8800,22800,200,*,UP,PDIF
-S 8200,14900,8200,22800,200,*,UP,PDIF
-S 7600,14900,7600,22800,200,*,UP,PDIF
-S 7300,14700,7300,23000,100,*,UP,PTRANS
-S 7900,14700,7900,23000,100,*,UP,PTRANS
-S 8500,14700,8500,23000,100,*,UP,PTRANS
-S 9100,14700,9100,23000,100,*,UP,PTRANS
-S 8400,14200,8400,23500,2800,*,UP,NWELL
-S 8800,24500,8800,24700,200,*,UP,POLY
-S 7100,25100,8500,25100,300,*,RIGHT,PTIE
-S 7300,25400,9100,25400,100,*,RIGHT,POLY
-S 8800,24600,8800,25400,200,*,UP,POLY
-S 8800,24600,9300,24600,300,*,RIGHT,POLY
-S 7100,23300,9500,23300,300,*,RIGHT,NTIE
-S 6700,14200,6700,23500,1000,*,UP,NWELL
-S 9900,14200,9900,23500,600,*,UP,NWELL
-S 7000,25600,7000,29000,300,*,UP,NDIF
-S 7000,14900,7000,22800,300,*,UP,PDIF
-S 6400,14400,6400,23400,300,*,UP,NTIE
-S 6400,23300,7000,23300,300,*,RIGHT,NTIE
-S 10000,27100,10000,29300,300,*,UP,PTIE
-S 9400,29500,10100,29500,300,*,RIGHT,PTIE
-S 6300,29500,7100,29500,300,*,RIGHT,PTIE
-S 6400,25000,6400,29600,300,*,UP,PTIE
-S 6300,25100,7100,25100,300,*,RIGHT,PTIE
-S 6700,25000,6700,29600,900,*,UP,ALU1
-S 7500,30400,9400,30400,900,*,RIGHT,ALU1
-S 9300,24600,9700,24600,200,*,RIGHT,ALU1
-S 10000,25000,10000,27300,300,*,UP,PTIE
-S 9100,25100,10000,25100,300,*,RIGHT,PTIE
-S 9800,14200,9800,23500,400,*,UP,NWELL
-S 6400,14400,8500,14400,300,*,RIGHT,NTIE
-S 7300,14700,9100,14700,100,*,RIGHT,POLY
-S 9500,23300,10000,23300,300,*,RIGHT,NTIE
-S 10000,14400,10000,23400,300,*,UP,NTIE
-S 9900,14200,9900,23500,600,*,UP,NWELL
-S 9700,14300,9700,23400,1000,*,UP,ALU1
-S 8800,13700,8800,14600,200,*,UP,POLY
-S 7600,13800,8300,13800,200,*,RIGHT,ALU1
-S 8200,13800,8800,13800,300,*,RIGHT,POLY
-S 9100,14400,10000,14400,300,*,RIGHT,NTIE
-S 8900,30900,8900,36400,1000,*,UP,ALU1
-S 300,1400,17500,1400,1200,log.ck,RIGHT,ALU2
-S 300,4800,17500,4800,4000,log.vssi,RIGHT,ALU2
-S 300,9200,17500,9200,4000,log.vddi,RIGHT,ALU2
-S 300,17600,17500,17600,12000,log.vdde,RIGHT,ALU2
-B 6700,27300,800,4600,CONT_VIA,*
-B 9700,18800,1000,9300,CONT_VIA,*
-B 6700,18900,800,9200,CONT_VIA,*
-B 2200,3900,1000,2200,CONT_VIA,*
-B 2200,9200,1000,4000,CONT_VIA,*
-B 14400,5400,200,200,CONT_TURN1,*
-B 8400,500,200,200,CONT_TURN1,*
-B 15600,500,200,200,CONT_TURN1,*
-B 8800,13400,200,200,CONT_TURN1,*
-B 12000,13400,200,200,CONT_TURN1,*
-B 10100,25100,200,200,CONT_TURN1,*
-B 9300,25100,200,200,CONT_TURN1,*
-V 11800,6400,CONT_POLY,*
-V 11400,6400,CONT_POLY,*
-V 14400,4500,CONT_POLY,*
-V 13200,4500,CONT_POLY,*
-V 12000,4500,CONT_POLY,*
-V 11400,11600,CONT_BODY_N,*
-V 11400,12400,CONT_BODY_N,*
-V 11400,12000,CONT_BODY_N,*
-V 11400,12800,CONT_BODY_N,*
-V 11400,10500,CONT_BODY_N,*
-V 11400,10000,CONT_BODY_N,*
-V 11400,8900,CONT_BODY_N,*
-V 11400,8400,CONT_BODY_N,*
-V 11400,7400,CONT_BODY_N,*
-V 11400,7900,CONT_VIA,*
-V 11400,11000,CONT_VIA,*
-V 11400,9400,CONT_VIA,*
-V 10200,7000,CONT_DIF_P,*
-V 10200,7800,CONT_DIF_P,*
-V 10200,7000,CONT_DIF_P,*
-V 10200,8200,CONT_DIF_P,*
-V 10200,9000,CONT_DIF_P,*
-V 10200,6000,CONT_BODY_N,*
-V 10200,12800,CONT_BODY_N,*
-V 10200,7400,CONT_VIA,*
-V 10200,8600,CONT_VIA,*
-V 10200,11000,CONT_VIA,*
-V 10200,9400,CONT_VIA,*
-V 10200,10200,CONT_VIA,*
-V 16200,2900,CONT_VIA,*
-V 16200,3700,CONT_VIA,*
-V 16200,4500,CONT_VIA,*
-V 15000,1100,CONT_BODY_P,*
-V 13800,1100,CONT_BODY_P,*
-V 12600,1100,CONT_BODY_P,*
-V 11400,1100,CONT_BODY_P,*
-V 10200,1100,CONT_BODY_P,*
-V 13800,4900,CONT_BODY_P,*
-V 8400,2400,CONT_DIF_N,*
-V 9600,2400,CONT_DIF_N,*
-V 10800,2400,CONT_DIF_N,*
-V 12000,2400,CONT_DIF_N,*
-V 13200,2400,CONT_DIF_N,*
-V 14400,2400,CONT_DIF_N,*
-V 15600,2400,CONT_DIF_N,*
-V 12600,4900,CONT_BODY_P,*
-V 11400,4900,CONT_BODY_P,*
-V 10200,4900,CONT_BODY_P,*
-V 10800,7000,CONT_DIF_P,*
-V 10800,8600,CONT_DIF_P,*
-V 10800,8100,CONT_DIF_P,*
-V 10800,7500,CONT_DIF_P,*
-V 10800,9100,CONT_DIF_P,*
-V 15000,4900,CONT_BODY_P,*
-V 10800,3900,CONT_DIF_N,*
-V 10800,2900,CONT_DIF_N,*
-V 10800,1900,CONT_DIF_N,*
-V 10800,3400,CONT_DIF_N,*
-V 12000,1900,CONT_DIF_N,*
-V 12000,2900,CONT_DIF_N,*
-V 12000,3900,CONT_DIF_N,*
-V 12000,3400,CONT_DIF_N,*
-V 13200,3400,CONT_DIF_N,*
-V 13200,3900,CONT_DIF_N,*
-V 13200,2900,CONT_DIF_N,*
-V 13200,1900,CONT_DIF_N,*
-V 15000,2500,CONT_DIF_N,*
-V 15000,2000,CONT_DIF_N,*
-V 15000,3500,CONT_DIF_N,*
-V 15000,4000,CONT_VIA,*
-V 15000,3000,CONT_VIA,*
-V 14400,1900,CONT_DIF_N,*
-V 14400,2900,CONT_DIF_N,*
-V 14400,3900,CONT_DIF_N,*
-V 14400,3400,CONT_DIF_N,*
-V 13800,3500,CONT_DIF_N,*
-V 13800,2000,CONT_DIF_N,*
-V 13800,2500,CONT_DIF_N,*
-V 13800,3000,CONT_VIA,*
-V 13800,4000,CONT_VIA,*
-V 12600,2500,CONT_DIF_N,*
-V 12600,3500,CONT_DIF_N,*
-V 12600,2000,CONT_DIF_N,*
-V 12600,3000,CONT_VIA,*
-V 12600,4000,CONT_VIA,*
-V 11400,2000,CONT_DIF_N,*
-V 11400,3500,CONT_DIF_N,*
-V 11400,2500,CONT_DIF_N,*
-V 11400,4000,CONT_VIA,*
-V 11400,3000,CONT_VIA,*
-V 10200,2500,CONT_DIF_N,*
-V 10200,3500,CONT_DIF_N,*
-V 10200,2000,CONT_DIF_N,*
-V 10200,3000,CONT_VIA,*
-V 10200,4000,CONT_VIA,*
-V 15600,1900,CONT_DIF_N,*
-V 15600,3900,CONT_DIF_N,*
-V 15600,3400,CONT_DIF_N,*
-V 15600,2900,CONT_DIF_N,*
-V 16200,2500,CONT_BODY_P,*
-V 16200,2100,CONT_BODY_P,*
-V 16200,4900,CONT_BODY_P,*
-V 16200,1700,CONT_BODY_P,*
-V 16200,1300,CONT_BODY_P,*
-V 16200,4100,CONT_BODY_P,*
-V 16200,3300,CONT_BODY_P,*
-V 9600,9100,CONT_DIF_P,*
-V 9600,7500,CONT_DIF_P,*
-V 9600,8100,CONT_DIF_P,*
-V 9600,8600,CONT_DIF_P,*
-V 9600,7000,CONT_DIF_P,*
-V 9600,2900,CONT_DIF_N,*
-V 9000,3500,CONT_DIF_N,*
-V 9000,2000,CONT_DIF_N,*
-V 8400,2900,CONT_DIF_N,*
-V 8400,3400,CONT_DIF_N,*
-V 8400,3900,CONT_DIF_N,*
-V 9600,3900,CONT_DIF_N,*
-V 9600,3400,CONT_DIF_N,*
-V 2500,1900,CONT_DIF_N,*
-V 2500,3900,CONT_DIF_N,*
-V 2500,3400,CONT_DIF_N,*
-V 2500,2400,CONT_DIF_N,*
-V 2500,2900,CONT_DIF_N,*
-V 9000,2500,CONT_DIF_N,*
-V 9600,1900,CONT_DIF_N,*
-V 8400,1900,CONT_DIF_N,*
-V 4900,3500,CONT_DIF_N,*
-V 3700,2000,CONT_DIF_N,*
-V 3700,3500,CONT_DIF_N,*
-V 3700,2500,CONT_DIF_N,*
-V 3100,2900,CONT_DIF_N,*
-V 3100,2400,CONT_DIF_N,*
-V 3100,3900,CONT_DIF_N,*
-V 3100,3400,CONT_DIF_N,*
-V 5500,3400,CONT_DIF_N,*
-V 5500,3900,CONT_DIF_N,*
-V 4300,2400,CONT_DIF_N,*
-V 4300,2900,CONT_DIF_N,*
-V 4300,3900,CONT_DIF_N,*
-V 4300,3400,CONT_DIF_N,*
-V 4900,2500,CONT_DIF_N,*
-V 4900,2000,CONT_DIF_N,*
-V 6700,2900,CONT_DIF_N,*
-V 6700,3900,CONT_DIF_N,*
-V 6700,3400,CONT_DIF_N,*
-V 6100,2500,CONT_DIF_N,*
-V 6100,2000,CONT_DIF_N,*
-V 6100,3500,CONT_DIF_N,*
-V 5500,2900,CONT_DIF_N,*
-V 5500,2400,CONT_DIF_N,*
-V 7300,3500,CONT_DIF_N,*
-V 7300,2500,CONT_DIF_N,*
-V 7300,2000,CONT_DIF_N,*
-V 6700,2400,CONT_DIF_N,*
-V 9000,7000,CONT_DIF_P,*
-V 9000,7800,CONT_DIF_P,*
-V 9000,7000,CONT_DIF_P,*
-V 6700,10600,CONT_DIF_P,*
-V 9000,9000,CONT_DIF_P,*
-V 9000,8200,CONT_DIF_P,*
-V 8400,8600,CONT_DIF_P,*
-V 8400,8100,CONT_DIF_P,*
-V 8400,7500,CONT_DIF_P,*
-V 8400,7000,CONT_DIF_P,*
-V 8400,9100,CONT_DIF_P,*
-V 6700,12200,CONT_DIF_P,*
-V 6700,7800,CONT_DIF_P,*
-V 6700,8200,CONT_DIF_P,*
-V 6700,8600,CONT_DIF_P,*
-V 6700,9000,CONT_DIF_P,*
-V 6700,9400,CONT_DIF_P,*
-V 6700,9800,CONT_DIF_P,*
-V 6700,10200,CONT_DIF_P,*
-V 5500,9400,CONT_DIF_P,*
-V 5500,9000,CONT_DIF_P,*
-V 5500,8600,CONT_DIF_P,*
-V 6700,7000,CONT_DIF_P,*
-V 6700,7400,CONT_DIF_P,*
-V 6700,11000,CONT_DIF_P,*
-V 6700,11400,CONT_DIF_P,*
-V 6700,11800,CONT_DIF_P,*
-V 5500,11800,CONT_DIF_P,*
-V 5500,11400,CONT_DIF_P,*
-V 5500,11000,CONT_DIF_P,*
-V 5500,7400,CONT_DIF_P,*
-V 5500,7000,CONT_DIF_P,*
-V 5500,10600,CONT_DIF_P,*
-V 5500,10200,CONT_DIF_P,*
-V 5500,9800,CONT_DIF_P,*
-V 4300,9800,CONT_DIF_P,*
-V 4300,10200,CONT_DIF_P,*
-V 4300,10600,CONT_DIF_P,*
-V 4300,7000,CONT_DIF_P,*
-V 4300,7400,CONT_DIF_P,*
-V 5500,8200,CONT_DIF_P,*
-V 5500,7800,CONT_DIF_P,*
-V 5500,12200,CONT_DIF_P,*
-V 4300,11400,CONT_DIF_P,*
-V 4300,11800,CONT_DIF_P,*
-V 4300,12200,CONT_DIF_P,*
-V 4300,7800,CONT_DIF_P,*
-V 4300,8200,CONT_DIF_P,*
-V 4300,8600,CONT_DIF_P,*
-V 4300,9000,CONT_DIF_P,*
-V 4300,9400,CONT_DIF_P,*
-V 3100,9400,CONT_DIF_P,*
-V 3100,9000,CONT_DIF_P,*
-V 3100,8600,CONT_DIF_P,*
-V 3100,8200,CONT_DIF_P,*
-V 3100,7800,CONT_DIF_P,*
-V 3100,7400,CONT_DIF_P,*
-V 3100,7000,CONT_DIF_P,*
-V 4300,11000,CONT_DIF_P,*
-V 2500,7200,CONT_DIF_P,*
-V 3100,12200,CONT_DIF_P,*
-V 3100,11800,CONT_DIF_P,*
-V 3100,11400,CONT_DIF_P,*
-V 3100,11000,CONT_DIF_P,*
-V 3100,10600,CONT_DIF_P,*
-V 3100,10200,CONT_DIF_P,*
-V 3100,9800,CONT_DIF_P,*
-V 2500,11200,CONT_DIF_P,*
-V 2500,10700,CONT_DIF_P,*
-V 2500,10200,CONT_DIF_P,*
-V 2500,9700,CONT_DIF_P,*
-V 2500,9200,CONT_DIF_P,*
-V 2500,8700,CONT_DIF_P,*
-V 2500,8200,CONT_DIF_P,*
-V 2500,7700,CONT_DIF_P,*
-V 2500,12200,CONT_DIF_P,*
-V 2500,11700,CONT_DIF_P,*
-V 7300,12200,CONT_DIF_P,*
-V 7300,7800,CONT_DIF_P,*
-V 7300,8200,CONT_DIF_P,*
-V 7300,9000,CONT_DIF_P,*
-V 7300,9400,CONT_DIF_P,*
-V 7300,10200,CONT_DIF_P,*
-V 7300,10600,CONT_DIF_P,*
-V 7300,11400,CONT_DIF_P,*
-V 7300,11800,CONT_DIF_P,*
-V 6100,10200,CONT_DIF_P,*
-V 6100,9400,CONT_DIF_P,*
-V 6100,9000,CONT_DIF_P,*
-V 6100,8200,CONT_DIF_P,*
-V 6100,7800,CONT_DIF_P,*
-V 6100,12200,CONT_DIF_P,*
-V 6100,11800,CONT_DIF_P,*
-V 7300,7000,CONT_DIF_P,*
-V 4900,9000,CONT_DIF_P,*
-V 4900,8200,CONT_DIF_P,*
-V 4900,7800,CONT_DIF_P,*
-V 4900,12200,CONT_DIF_P,*
-V 4900,11800,CONT_DIF_P,*
-V 6100,7000,CONT_DIF_P,*
-V 6100,11400,CONT_DIF_P,*
-V 6100,10600,CONT_DIF_P,*
-V 3700,7800,CONT_DIF_P,*
-V 3700,12200,CONT_DIF_P,*
-V 3700,11800,CONT_DIF_P,*
-V 4900,7000,CONT_DIF_P,*
-V 4900,11400,CONT_DIF_P,*
-V 4900,10600,CONT_DIF_P,*
-V 4900,10200,CONT_DIF_P,*
-V 4900,9400,CONT_DIF_P,*
-V 3700,7000,CONT_DIF_P,*
-V 3700,11400,CONT_DIF_P,*
-V 3700,10600,CONT_DIF_P,*
-V 3700,10200,CONT_DIF_P,*
-V 3700,9400,CONT_DIF_P,*
-V 3700,9000,CONT_DIF_P,*
-V 3700,8200,CONT_DIF_P,*
-V 9000,12800,CONT_BODY_N,*
-V 9000,6000,CONT_BODY_N,*
-V 9600,12800,CONT_BODY_N,*
-V 7300,6000,CONT_BODY_N,*
-V 1800,9700,CONT_BODY_N,*
-V 1800,9200,CONT_BODY_N,*
-V 1800,8700,CONT_BODY_N,*
-V 1800,8200,CONT_BODY_N,*
-V 1800,12200,CONT_BODY_N,*
-V 4900,6000,CONT_BODY_N,*
-V 3700,6000,CONT_BODY_N,*
-V 1800,7700,CONT_BODY_N,*
-V 1800,7200,CONT_BODY_N,*
-V 1800,11700,CONT_BODY_N,*
-V 1800,11200,CONT_BODY_N,*
-V 1800,10700,CONT_BODY_N,*
-V 1800,10200,CONT_BODY_N,*
-V 3700,12800,CONT_BODY_N,*
-V 4900,12800,CONT_BODY_N,*
-V 6100,12800,CONT_BODY_N,*
-V 7300,12800,CONT_BODY_N,*
-V 2300,6000,CONT_BODY_N,*
-V 1800,6200,CONT_BODY_N,*
-V 1800,6700,CONT_BODY_N,*
-V 6100,6000,CONT_BODY_N,*
-V 6700,12800,CONT_BODY_N,*
-V 5500,12800,CONT_BODY_N,*
-V 4300,12800,CONT_BODY_N,*
-V 3100,12800,CONT_BODY_N,*
-V 2500,12800,CONT_BODY_N,*
-V 1800,12800,CONT_BODY_N,*
-V 9000,1100,CONT_BODY_P,*
-V 9000,4900,CONT_BODY_P,*
-V 6100,4900,CONT_BODY_P,*
-V 4900,4900,CONT_BODY_P,*
-V 3700,4900,CONT_BODY_P,*
-V 7300,1100,CONT_BODY_P,*
-V 6100,1100,CONT_BODY_P,*
-V 4900,1100,CONT_BODY_P,*
-V 3700,1100,CONT_BODY_P,*
-V 2400,4900,CONT_BODY_P,*
-V 1900,4100,CONT_BODY_P,*
-V 1900,3700,CONT_BODY_P,*
-V 1900,4500,CONT_BODY_P,*
-V 1900,1300,CONT_BODY_P,*
-V 1900,1700,CONT_BODY_P,*
-V 1900,2900,CONT_BODY_P,*
-V 2400,1100,CONT_BODY_P,*
-V 7300,4900,CONT_BODY_P,*
-V 1900,4900,CONT_BODY_P,*
-V 1900,2100,CONT_BODY_P,*
-V 1900,2500,CONT_BODY_P,*
-V 1900,3300,CONT_BODY_P,*
-V 8300,6400,CONT_POLY,*
-V 7900,4500,CONT_POLY,*
-V 8300,4500,CONT_POLY,*
-V 7900,6400,CONT_POLY,*
-V 9000,11000,CONT_VIA,*
-V 9000,8600,CONT_VIA,*
-V 9000,7400,CONT_VIA,*
-V 9000,4000,CONT_VIA,*
-V 9000,3000,CONT_VIA,*
-V 9000,10200,CONT_VIA,*
-V 9000,9400,CONT_VIA,*
-V 7300,11000,CONT_VIA,*
-V 7300,7400,CONT_VIA,*
-V 7300,8600,CONT_VIA,*
-V 7300,9800,CONT_VIA,*
-V 6100,7400,CONT_VIA,*
-V 6100,9800,CONT_VIA,*
-V 6100,8600,CONT_VIA,*
-V 6100,11000,CONT_VIA,*
-V 4900,11000,CONT_VIA,*
-V 4900,7400,CONT_VIA,*
-V 4900,9800,CONT_VIA,*
-V 4900,8600,CONT_VIA,*
-V 3700,9800,CONT_VIA,*
-V 3700,8600,CONT_VIA,*
-V 3700,11000,CONT_VIA,*
-V 3700,7400,CONT_VIA,*
-V 3700,4000,CONT_VIA,*
-V 3700,3000,CONT_VIA,*
-V 4900,3000,CONT_VIA,*
-V 4900,4000,CONT_VIA,*
-V 6100,4000,CONT_VIA,*
-V 6100,3000,CONT_VIA,*
-V 7300,4000,CONT_VIA,*
-V 7300,3000,CONT_VIA,*
-V 6700,1100,CONT_VIA,*
-V 5500,1100,CONT_VIA,*
-V 4300,1100,CONT_VIA,*
-V 3100,1100,CONT_VIA,*
-V 3100,1800,CONT_VIA,*
-V 4300,1800,CONT_VIA,*
-V 5500,1800,CONT_VIA,*
-V 6700,1800,CONT_VIA,*
-V 9400,28500,CONT_DIF_N,*
-V 9400,26900,CONT_DIF_N,*
-V 9400,26500,CONT_DIF_N,*
-V 9400,28100,CONT_DIF_N,*
-V 9400,27700,CONT_DIF_N,*
-V 9400,26100,CONT_DIF_N,*
-V 9400,27300,CONT_VIA,*
-V 9400,25700,CONT_VIA,*
-V 9400,28900,CONT_VIA,*
-V 8200,25700,CONT_VIA,*
-V 8200,26100,CONT_DIF_N,*
-V 8200,27700,CONT_DIF_N,*
-V 8200,28100,CONT_DIF_N,*
-V 8200,27300,CONT_DIF_N,*
-V 8200,28900,CONT_DIF_N,*
-V 8200,26500,CONT_DIF_N,*
-V 8200,28500,CONT_VIA,*
-V 8200,26900,CONT_VIA,*
-V 9400,29500,CONT_BODY_P,*
-V 8200,29500,CONT_BODY_P,*
-V 7800,14400,CONT_BODY_N,*
-V 7600,25800,CONT_DIF_N,*
-V 7600,28200,CONT_DIF_N,*
-V 7600,28600,CONT_DIF_N,*
-V 7600,26200,CONT_DIF_N,*
-V 7600,26600,CONT_DIF_N,*
-V 7600,27000,CONT_DIF_N,*
-V 7600,27400,CONT_DIF_N,*
-V 7600,27800,CONT_DIF_N,*
-V 8800,26600,CONT_DIF_N,*
-V 8800,27000,CONT_DIF_N,*
-V 8800,26200,CONT_DIF_N,*
-V 8800,25800,CONT_DIF_N,*
-V 8800,28600,CONT_DIF_N,*
-V 8800,27400,CONT_DIF_N,*
-V 8800,27800,CONT_DIF_N,*
-V 8800,28200,CONT_DIF_N,*
-V 8200,15100,CONT_DIF_P,*
-V 7600,15500,CONT_DIF_P,*
-V 8200,15500,CONT_DIF_P,*
-V 7600,15900,CONT_DIF_P,*
-V 7600,15100,CONT_DIF_P,*
-V 8800,15100,CONT_DIF_P,*
-V 9400,15100,CONT_DIF_P,*
-V 8800,15500,CONT_DIF_P,*
-V 9400,15500,CONT_DIF_P,*
-V 8800,15900,CONT_DIF_P,*
-V 8200,16300,CONT_DIF_P,*
-V 7600,16300,CONT_DIF_P,*
-V 7600,20300,CONT_DIF_P,*
-V 7600,18700,CONT_DIF_P,*
-V 8200,18700,CONT_DIF_P,*
-V 7600,19100,CONT_DIF_P,*
-V 8200,19100,CONT_DIF_P,*
-V 7600,19500,CONT_DIF_P,*
-V 7600,19900,CONT_DIF_P,*
-V 8200,19900,CONT_DIF_P,*
-V 8200,20300,CONT_DIF_P,*
-V 7600,17100,CONT_DIF_P,*
-V 7600,16700,CONT_DIF_P,*
-V 8200,16700,CONT_DIF_P,*
-V 7600,18300,CONT_DIF_P,*
-V 7600,17900,CONT_DIF_P,*
-V 7600,17500,CONT_DIF_P,*
-V 8200,17500,CONT_DIF_P,*
-V 8200,17900,CONT_DIF_P,*
-V 8800,16300,CONT_DIF_P,*
-V 9400,16300,CONT_DIF_P,*
-V 9400,20300,CONT_DIF_P,*
-V 8800,19100,CONT_DIF_P,*
-V 8800,19500,CONT_DIF_P,*
-V 8800,19900,CONT_DIF_P,*
-V 9400,19900,CONT_DIF_P,*
-V 8800,20300,CONT_DIF_P,*
-V 8800,18300,CONT_DIF_P,*
-V 8800,17900,CONT_DIF_P,*
-V 8800,18700,CONT_DIF_P,*
-V 9400,18700,CONT_DIF_P,*
-V 9400,19100,CONT_DIF_P,*
-V 8800,17100,CONT_DIF_P,*
-V 8800,16700,CONT_DIF_P,*
-V 9400,16700,CONT_DIF_P,*
-V 9400,17900,CONT_DIF_P,*
-V 9400,17500,CONT_DIF_P,*
-V 8800,17500,CONT_DIF_P,*
-V 8200,15900,CONT_VIA,*
-V 8200,18300,CONT_VIA,*
-V 8200,19500,CONT_VIA,*
-V 8200,17100,CONT_VIA,*
-V 7600,20700,CONT_DIF_P,*
-V 8800,20700,CONT_DIF_P,*
-V 8200,20700,CONT_VIA,*
-V 7600,21100,CONT_DIF_P,*
-V 8800,21100,CONT_DIF_P,*
-V 8200,21100,CONT_DIF_P,*
-V 9400,21100,CONT_DIF_P,*
-V 8200,21500,CONT_DIF_P,*
-V 9400,21500,CONT_DIF_P,*
-V 8800,21500,CONT_DIF_P,*
-V 7600,21500,CONT_DIF_P,*
-V 7600,21900,CONT_DIF_P,*
-V 8800,21900,CONT_DIF_P,*
-V 8200,21900,CONT_VIA,*
-V 7600,22300,CONT_DIF_P,*
-V 8200,22300,CONT_DIF_P,*
-V 8800,22300,CONT_DIF_P,*
-V 9400,22300,CONT_DIF_P,*
-V 8200,25100,CONT_BODY_P,*
-V 9400,25100,CONT_BODY_P,*
-V 9300,24600,CONT_POLY,*
-V 8200,24600,CONT_VIA,*
-V 9400,23300,CONT_BODY_N,*
-V 8200,23300,CONT_BODY_N,*
-V 9400,22700,CONT_DIF_P,*
-V 8800,22700,CONT_DIF_P,*
-V 8200,22700,CONT_DIF_P,*
-V 7600,22700,CONT_DIF_P,*
-V 8200,14400,CONT_VIA,*
-V 7300,14400,CONT_BODY_N,*
-V 7000,26500,CONT_DIF_N,*
-V 7000,27700,CONT_DIF_N,*
-V 7000,28500,CONT_DIF_N,*
-V 7000,28100,CONT_DIF_N,*
-V 7000,26900,CONT_DIF_N,*
-V 7000,25700,CONT_DIF_N,*
-V 7000,27300,CONT_DIF_N,*
-V 7000,28900,CONT_DIF_N,*
-V 7000,26100,CONT_DIF_N,*
-V 7000,17100,CONT_DIF_P,*
-V 7000,20700,CONT_DIF_P,*
-V 7000,19500,CONT_DIF_P,*
-V 7000,19900,CONT_DIF_P,*
-V 7000,18700,CONT_DIF_P,*
-V 7000,18300,CONT_DIF_P,*
-V 7000,16700,CONT_DIF_P,*
-V 7000,17500,CONT_DIF_P,*
-V 7000,17900,CONT_DIF_P,*
-V 7000,20300,CONT_DIF_P,*
-V 7000,19100,CONT_DIF_P,*
-V 7000,15100,CONT_DIF_P,*
-V 7000,15500,CONT_DIF_P,*
-V 7000,15900,CONT_DIF_P,*
-V 7000,16300,CONT_DIF_P,*
-V 7000,21900,CONT_DIF_P,*
-V 7000,22300,CONT_DIF_P,*
-V 7000,21100,CONT_DIF_P,*
-V 7000,22700,CONT_DIF_P,*
-V 7000,21500,CONT_DIF_P,*
-V 6400,18000,CONT_BODY_N,*
-V 6400,18800,CONT_BODY_N,*
-V 6400,18400,CONT_BODY_N,*
-V 6400,17200,CONT_BODY_N,*
-V 6400,16400,CONT_BODY_N,*
-V 6400,15600,CONT_BODY_N,*
-V 6400,15200,CONT_BODY_N,*
-V 6400,14800,CONT_BODY_N,*
-V 6400,19600,CONT_BODY_N,*
-V 6400,20800,CONT_BODY_N,*
-V 6400,19200,CONT_BODY_N,*
-V 6400,16800,CONT_BODY_N,*
-V 6400,16000,CONT_BODY_N,*
-V 6900,14400,CONT_BODY_N,*
-V 6400,14400,CONT_BODY_N,*
-V 6400,17600,CONT_BODY_N,*
-V 6400,20400,CONT_BODY_N,*
-V 6400,20000,CONT_BODY_N,*
-V 6400,22400,CONT_BODY_N,*
-V 6400,22800,CONT_BODY_N,*
-V 6400,22000,CONT_BODY_N,*
-V 6400,23300,CONT_BODY_N,*
-V 6400,21200,CONT_BODY_N,*
-V 7000,23300,CONT_BODY_N,*
-V 6400,21600,CONT_BODY_N,*
-V 6400,26700,CONT_BODY_P,*
-V 6400,27900,CONT_BODY_P,*
-V 7000,29500,CONT_BODY_P,*
-V 7000,25100,CONT_BODY_P,*
-V 10000,29100,CONT_BODY_P,*
-V 6400,28300,CONT_BODY_P,*
-V 6400,25500,CONT_BODY_P,*
-V 6400,27100,CONT_BODY_P,*
-V 6400,25100,CONT_BODY_P,*
-V 6400,28700,CONT_BODY_P,*
-V 6400,26300,CONT_BODY_P,*
-V 10000,27900,CONT_BODY_P,*
-V 10000,27500,CONT_BODY_P,*
-V 6400,29100,CONT_BODY_P,*
-V 6400,25900,CONT_BODY_P,*
-V 6400,27500,CONT_BODY_P,*
-V 10000,28700,CONT_BODY_P,*
-V 6400,29500,CONT_BODY_P,*
-V 10000,29500,CONT_VIA,*
-V 10000,28300,CONT_VIA,*
-V 9700,24600,CONT_VIA,*
-V 10000,25100,CONT_VIA,*
-V 10000,27100,CONT_VIA,*
-V 10000,26700,CONT_BODY_P,*
-V 10000,26300,CONT_BODY_P,*
-V 10000,25900,CONT_VIA,*
-V 10000,25500,CONT_BODY_P,*
-V 9400,14400,CONT_BODY_N,*
-V 10000,22800,CONT_BODY_N,*
-V 10000,22000,CONT_BODY_N,*
-V 10000,23300,CONT_BODY_N,*
-V 10000,21200,CONT_BODY_N,*
-V 10000,21600,CONT_BODY_N,*
-V 10000,22400,CONT_BODY_N,*
-V 10000,15600,CONT_BODY_N,*
-V 10000,16800,CONT_BODY_N,*
-V 10000,17200,CONT_BODY_N,*
-V 10000,18400,CONT_BODY_N,*
-V 10000,18800,CONT_BODY_N,*
-V 10000,19200,CONT_BODY_N,*
-V 10000,16400,CONT_BODY_N,*
-V 10000,20800,CONT_BODY_N,*
-V 10000,20400,CONT_BODY_N,*
-V 10000,20000,CONT_BODY_N,*
-V 10000,19600,CONT_BODY_N,*
-V 10000,16000,CONT_BODY_N,*
-V 10000,14400,CONT_BODY_N,*
-V 10000,18000,CONT_BODY_N,*
-V 10000,14800,CONT_BODY_N,*
-V 10000,15200,CONT_BODY_N,*
-V 10000,17600,CONT_BODY_N,*
-V 9400,21900,CONT_DIF_P,*
-V 9400,20700,CONT_DIF_P,*
-V 9400,19500,CONT_DIF_P,*
-V 9400,18300,CONT_DIF_P,*
-V 9400,17100,CONT_DIF_P,*
-V 9400,15900,CONT_DIF_P,*
-V 7700,13800,CONT_VIA,*
-V 8200,13800,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/padlib/pali_sp.ap b/alliance/share/cells/padlib/pali_sp.ap
deleted file mode 100644
index 8acf28a9..00000000
--- a/alliance/share/cells/padlib/pali_sp.ap
+++ /dev/null
@@ -1,533 +0,0 @@
-V ALLIANCE : 6
-H pali_sp,P, 9/10/2000,100
-A 0,-700,17200,35600
-C 0,29600,12000,vsse,0,WEST,ALU2
-C 17200,29600,12000,vsse,1,EAST,ALU2
-C 0,8400,4000,vddi,0,WEST,ALU2
-C 0,4000,4000,vssi,0,WEST,ALU2
-C 17200,4000,4000,vssi,1,EAST,ALU2
-C 17200,8400,4000,vddi,1,EAST,ALU2
-C 0,16800,12000,vdde,0,WEST,ALU2
-C 17200,16800,12000,vdde,1,EAST,ALU2
-C 17200,600,1200,ck,1,EAST,ALU2
-C 0,600,1200,ck,0,WEST,ALU2
-C 8200,-700,200,t,1,SOUTH,ALU2
-C 8200,-700,200,t,0,SOUTH,ALU1
-S 8400,12550,12400,12550,300,*,RIGHT,ALU1
-S 12300,4600,12300,12600,300,*,UP,ALU1
-S 7300,200,7300,4200,900,*,UP,ALU1
-S 8800,200,8800,4200,200,*,UP,ALU1
-S 10500,200,10500,4200,200,*,UP,ALU1
-S 12000,200,12000,4200,800,*,UP,ALU1
-S 11700,5300,11700,12000,200,*,UP,ALU1
-S 10500,5200,10500,12000,200,*,UP,ALU1
-S 8800,5200,8800,12000,200,*,UP,ALU1
-S 6800,12000,11800,12000,200,*,RIGHT,ALU1
-S 9900,13600,9900,22600,700,*,UP,ALU1
-S 9100,13600,9100,22600,200,*,UP,ALU1
-S 9000,13600,10100,13600,200,*,RIGHT,ALU1
-S 7900,13800,7900,22600,200,*,UP,ALU1
-S 8500,23800,9200,23800,300,*,RIGHT,POLY
-S 9100,23800,9500,23800,200,*,RIGHT,ALU1
-S 9700,24300,9700,28800,200,*,UP,ALU1
-S 9100,24300,9100,28800,200,*,UP,ALU1
-S 6400,24200,6400,28800,800,*,UP,ALU1
-S 7900,23700,7900,28800,200,*,UP,ALU1
-S 0,29600,17200,29600,12000,vsse,RIGHT,ALU2
-S 8600,30100,8600,35600,1000,*,UP,ALU1
-S 8200,-700,8200,-400,300,*,UP,ALU2
-S 8500,12600,8500,13000,300,*,UP,ALU1
-S 7200,29600,9100,29600,900,*,RIGHT,ALU1
-S 100,600,17200,600,1200,ck,RIGHT,ALU2
-S 6400,13500,6400,22600,800,*,UP,ALU1
-S 6000,24300,6800,24300,300,*,RIGHT,PTIE
-S 6100,24200,6100,28800,300,*,UP,PTIE
-S 6000,28700,6800,28700,300,*,RIGHT,PTIE
-S 9100,28700,9800,28700,300,*,RIGHT,PTIE
-S 6100,22500,6700,22500,300,*,RIGHT,NTIE
-S 6100,13600,6700,13600,300,*,RIGHT,NTIE
-S 6100,13600,6100,22600,300,*,UP,NTIE
-S 6700,14100,6700,22000,300,*,UP,PDIF
-S 6700,24800,6700,28200,300,*,UP,NDIF
-S 9600,13400,9600,22700,600,*,UP,NWELL
-S 6400,13400,6400,22700,1000,*,UP,NWELL
-S 11100,3600,11100,5700,300,*,UP,ALU1
-S 11000,4700,12400,4700,300,*,RIGHT,ALU1
-S 9300,5600,10000,5600,300,*,RIGHT,ALU1
-S 9300,3700,10000,3700,300,*,RIGHT,ALU1
-S 9900,4500,9900,8400,300,*,UP,ALU1
-S 7200,5100,7200,12100,1000,*,UP,ALU1
-S 9800,-300,11200,-300,300,*,RIGHT,ALU1
-S 8200,-700,8200,11500,300,*,UP,ALU1
-S 9900,-400,9900,4700,300,*,UP,ALU1
-S 11100,-400,11100,3200,300,*,UP,ALU1
-S 7900,600,8500,600,100,*,RIGHT,POLY
-S 10200,5600,11200,5600,300,*,RIGHT,POLY
-S 10200,5500,10200,5700,100,*,UP,POLY
-S 10200,3700,11400,3700,300,*,RIGHT,POLY
-S 7900,5600,9900,5600,300,*,RIGHT,POLY
-S 7900,11700,8500,11700,100,*,RIGHT,POLY
-S 7000,4100,12400,4100,300,*,RIGHT,PTIE
-S 7000,400,7000,4200,300,*,UP,PTIE
-S 6900,300,12400,300,300,*,RIGHT,PTIE
-S 12300,200,12300,4200,300,*,UP,PTIE
-S 11700,5100,11700,12100,300,*,UP,NTIE
-S 6800,5200,11800,5200,300,*,RIGHT,NTIE
-S 6900,5100,6900,12000,300,*,UP,NTIE
-S 6800,12000,11800,12000,300,*,RIGHT,NTIE
-S 8800,5900,8800,11500,400,*,UP,PDIF
-S 8500,5700,8500,11700,100,*,UP,PTRANS
-S 7900,5700,7900,11700,100,*,UP,PTRANS
-S 10200,5700,10200,8700,100,*,UP,PTRANS
-S 9900,5900,9900,8500,400,*,UP,PDIF
-S 8200,5900,8200,11500,200,*,UP,PDIF
-S 10500,5900,10500,8500,300,*,UP,PDIF
-S 7600,5900,7600,11500,400,*,UP,PDIF
-S 7900,600,7900,3600,100,*,UP,NTRANS
-S 8500,600,8500,3600,100,*,UP,NTRANS
-S 8800,800,8800,3400,400,*,UP,NDIF
-S 7600,800,7600,3400,300,*,UP,NDIF
-S 8200,800,8200,3400,200,*,UP,NDIF
-S 11100,800,11100,3400,200,*,UP,NDIF
-S 10500,800,10500,3400,200,*,UP,NDIF
-S 11700,800,11700,3400,300,*,UP,NDIF
-S 11700,800,11700,3400,200,*,UP,NDIF
-S 10200,600,10200,3600,100,*,UP,NTRANS
-S 9900,800,9900,3400,300,*,UP,NDIF
-S 10800,600,10800,3600,100,*,UP,NTRANS
-S 11400,600,11400,3600,100,*,UP,NTRANS
-S 6700,8600,11900,8600,7200,*,RIGHT,NWELL
-S 7900,3700,9900,3700,300,*,RIGHT,POLY
-S 9700,24200,9700,28500,300,*,UP,PTIE
-S 9100,24300,9700,24300,300,*,LEFT,PTIE
-S 10000,13600,10000,22600,300,*,UP,NTIE
-S 9900,13400,9900,22700,600,*,UP,NWELL
-S 9500,13400,9500,22700,400,*,UP,NWELL
-S 9300,13600,10000,13600,300,*,RIGHT,NTIE
-S 9100,13100,9500,13100,200,*,RIGHT,ALU1
-S 9100,22500,10000,22500,300,*,RIGHT,NTIE
-S 8500,13000,8500,14300,300,*,DOWN,ALU1
-S 6800,13600,8000,13600,300,*,RIGHT,ALU1
-S 8500,13100,8500,13900,200,*,UP,POLY
-S 6800,22500,9200,22500,300,*,RIGHT,NTIE
-S 8500,23800,8500,24600,200,*,UP,POLY
-S 7000,24600,8800,24600,100,*,RIGHT,POLY
-S 8800,24300,9200,24300,300,*,RIGHT,PTIE
-S 6800,24300,8200,24300,300,*,RIGHT,PTIE
-S 8500,23700,8500,23900,200,*,DOWN,POLY
-S 7000,13900,8800,13900,100,*,RIGHT,POLY
-S 8800,13600,9200,13600,300,*,RIGHT,NTIE
-S 6800,13600,8200,13600,300,*,RIGHT,NTIE
-S 8100,13400,8100,22700,2800,*,UP,NWELL
-S 8800,13900,8800,22200,100,*,UP,PTRANS
-S 8200,13900,8200,22200,100,*,UP,PTRANS
-S 7600,13900,7600,22200,100,*,UP,PTRANS
-S 7000,13900,7000,22200,100,*,UP,PTRANS
-S 7300,14100,7300,22000,200,*,UP,PDIF
-S 7900,14100,7900,22000,200,*,UP,PDIF
-S 8500,14100,8500,22000,200,*,UP,PDIF
-S 9100,14100,9100,22000,300,*,UP,PDIF
-S 6800,28700,9200,28700,300,*,RIGHT,PTIE
-S 8800,24600,8800,28400,100,*,UP,NTRANS
-S 8200,24600,8200,28400,100,*,UP,NTRANS
-S 7600,24600,7600,28400,100,*,UP,NTRANS
-S 7000,24600,7000,28400,100,*,UP,NTRANS
-S 7300,24800,7300,28200,300,*,UP,NDIF
-S 7900,24800,7900,28200,300,*,UP,NDIF
-S 8500,24800,8500,28200,300,*,UP,NDIF
-S 9100,24800,9100,28200,300,*,UP,NDIF
-S 8500,14200,8500,29100,300,*,UP,ALU1
-S 7300,14200,7300,29100,300,*,UP,ALU1
-S 8500,13100,9100,13100,200,*,RIGHT,POLY
-S 0,4000,17200,4000,4000,vssi,RIGHT,ALU2
-S 0,8400,17200,8400,4000,vddi,RIGHT,ALU2
-S 0,16800,17200,16800,12000,vdde,RIGHT,ALU2
-V 10500,9500,CONT_VIA,*
-B 7200,8400,1000,4000,CONT_VIA,*
-B 12000,3100,700,2100,CONT_VIA,*
-B 7300,3100,800,2100,CONT_VIA,*
-B 9900,18050,600,9000,CONT_VIA,*
-V 9100,13600,CONT_BODY_N,*
-B 6400,26500,800,4600,CONT_VIA,*
-B 6400,18000,800,9100,CONT_VIA,*
-V 9100,23800,CONT_POLY,*
-V 9500,23800,CONT_VIA,*
-B 9400,26500,800,4600,CONT_VIA,*
-V 8200,-500,CONT_VIA,*
-V 6100,28700,CONT_BODY_P,*
-V 9700,27900,CONT_BODY_P,*
-V 6100,26700,CONT_BODY_P,*
-V 6100,25100,CONT_BODY_P,*
-V 6100,28300,CONT_BODY_P,*
-V 9700,26700,CONT_BODY_P,*
-V 9700,27100,CONT_BODY_P,*
-V 6100,25500,CONT_BODY_P,*
-V 6100,27900,CONT_BODY_P,*
-V 6100,24300,CONT_BODY_P,*
-V 6100,26300,CONT_BODY_P,*
-V 6100,24700,CONT_BODY_P,*
-V 6100,27500,CONT_BODY_P,*
-V 9700,28300,CONT_BODY_P,*
-V 6700,24300,CONT_BODY_P,*
-V 6700,28700,CONT_BODY_P,*
-V 6100,27100,CONT_BODY_P,*
-V 6100,25900,CONT_BODY_P,*
-V 6100,20800,CONT_BODY_N,*
-V 6700,22500,CONT_BODY_N,*
-V 6100,20400,CONT_BODY_N,*
-V 6100,22500,CONT_BODY_N,*
-V 6100,21200,CONT_BODY_N,*
-V 6100,22000,CONT_BODY_N,*
-V 6100,21600,CONT_BODY_N,*
-V 6100,19200,CONT_BODY_N,*
-V 6100,19600,CONT_BODY_N,*
-V 6100,16800,CONT_BODY_N,*
-V 6100,13600,CONT_BODY_N,*
-V 6600,13600,CONT_BODY_N,*
-V 6100,15200,CONT_BODY_N,*
-V 6100,16000,CONT_BODY_N,*
-V 6100,18400,CONT_BODY_N,*
-V 6100,20000,CONT_BODY_N,*
-V 6100,18800,CONT_BODY_N,*
-V 6100,14000,CONT_BODY_N,*
-V 6100,14400,CONT_BODY_N,*
-V 6100,14800,CONT_BODY_N,*
-V 6100,15600,CONT_BODY_N,*
-V 6100,16400,CONT_BODY_N,*
-V 6100,17600,CONT_BODY_N,*
-V 6100,18000,CONT_BODY_N,*
-V 6100,17200,CONT_BODY_N,*
-V 6700,20700,CONT_DIF_P,*
-V 6700,21900,CONT_DIF_P,*
-V 6700,20300,CONT_DIF_P,*
-V 6700,21500,CONT_DIF_P,*
-V 6700,21100,CONT_DIF_P,*
-V 6700,15500,CONT_DIF_P,*
-V 6700,15100,CONT_DIF_P,*
-V 6700,14700,CONT_DIF_P,*
-V 6700,14300,CONT_DIF_P,*
-V 6700,18300,CONT_DIF_P,*
-V 6700,19500,CONT_DIF_P,*
-V 6700,17100,CONT_DIF_P,*
-V 6700,16700,CONT_DIF_P,*
-V 6700,15900,CONT_DIF_P,*
-V 6700,17500,CONT_DIF_P,*
-V 6700,17900,CONT_DIF_P,*
-V 6700,19100,CONT_DIF_P,*
-V 6700,18700,CONT_DIF_P,*
-V 6700,19900,CONT_DIF_P,*
-V 6700,16300,CONT_DIF_P,*
-V 6700,25300,CONT_DIF_N,*
-V 6700,28100,CONT_DIF_N,*
-V 6700,26500,CONT_DIF_N,*
-V 6700,24900,CONT_DIF_N,*
-V 6700,26100,CONT_DIF_N,*
-V 6700,27300,CONT_DIF_N,*
-V 6700,27700,CONT_DIF_N,*
-V 6700,26900,CONT_DIF_N,*
-V 6700,25700,CONT_DIF_N,*
-V 10500,10200,CONT_VIA,*
-V 8800,2200,CONT_VIA,*
-V 8800,3200,CONT_VIA,*
-V 10500,7800,CONT_VIA,*
-V 11700,10200,CONT_VIA,*
-V 11700,8600,CONT_VIA,*
-V 11700,7100,CONT_VIA,*
-V 10500,2200,CONT_VIA,*
-V 10500,3200,CONT_VIA,*
-V 10500,6600,CONT_VIA,*
-V 8800,9000,CONT_VIA,*
-V 8800,7800,CONT_VIA,*
-V 8800,6600,CONT_VIA,*
-V 8800,10200,CONT_VIA,*
-V 10500,8700,CONT_VIA,*
-V 11100,5600,CONT_POLY,*
-V 9800,5600,CONT_POLY,*
-V 9400,5600,CONT_POLY,*
-V 9800,3700,CONT_POLY,*
-V 11100,3700,CONT_POLY,*
-V 9400,3700,CONT_POLY,*
-V 7000,3700,CONT_BODY_P,*
-V 7000,500,CONT_BODY_P,*
-V 7000,900,CONT_BODY_P,*
-V 7000,1700,CONT_BODY_P,*
-V 12300,2900,CONT_BODY_P,*
-V 7000,2100,CONT_BODY_P,*
-V 8800,4100,CONT_BODY_P,*
-V 12300,2500,CONT_BODY_P,*
-V 7000,4100,CONT_BODY_P,*
-V 7000,1300,CONT_BODY_P,*
-V 7500,4100,CONT_BODY_P,*
-V 12300,500,CONT_BODY_P,*
-V 11700,4100,CONT_BODY_P,*
-V 12300,3700,CONT_BODY_P,*
-V 7000,3300,CONT_BODY_P,*
-V 12300,3300,CONT_BODY_P,*
-V 7000,2500,CONT_BODY_P,*
-V 7000,2900,CONT_BODY_P,*
-V 10500,4100,CONT_BODY_P,*
-V 12300,900,CONT_BODY_P,*
-V 12300,2100,CONT_BODY_P,*
-V 12300,4100,CONT_BODY_P,*
-V 12300,1300,CONT_BODY_P,*
-V 12300,1700,CONT_BODY_P,*
-V 11700,300,CONT_BODY_P,*
-V 10500,300,CONT_BODY_P,*
-V 8800,300,CONT_BODY_P,*
-V 7500,300,CONT_BODY_P,*
-V 11700,9200,CONT_BODY_N,*
-V 11700,9700,CONT_BODY_N,*
-V 6900,6900,CONT_BODY_N,*
-V 6900,7900,CONT_BODY_N,*
-V 6900,6400,CONT_BODY_N,*
-V 6900,10900,CONT_BODY_N,*
-V 6900,7400,CONT_BODY_N,*
-V 11700,6100,CONT_BODY_N,*
-V 11700,5300,CONT_BODY_N,*
-V 8200,12000,CONT_BODY_N,*
-V 6900,11400,CONT_BODY_N,*
-V 6900,5900,CONT_BODY_N,*
-V 6900,5400,CONT_BODY_N,*
-V 6900,12000,CONT_BODY_N,*
-V 6900,10400,CONT_BODY_N,*
-V 8800,12000,CONT_BODY_N,*
-V 6900,9900,CONT_BODY_N,*
-V 6900,9400,CONT_BODY_N,*
-V 6900,8900,CONT_BODY_N,*
-V 6900,8400,CONT_BODY_N,*
-V 7400,5200,CONT_BODY_N,*
-V 7600,12000,CONT_BODY_N,*
-V 11700,6600,CONT_BODY_N,*
-V 11700,7600,CONT_BODY_N,*
-V 11700,8100,CONT_BODY_N,*
-V 11700,10900,CONT_BODY_N,*
-V 11700,11400,CONT_BODY_N,*
-V 8800,5200,CONT_BODY_N,*
-V 11100,12000,CONT_BODY_N,*
-V 11700,12000,CONT_BODY_N,*
-V 10500,5200,CONT_BODY_N,*
-V 10500,12000,CONT_BODY_N,*
-V 8200,7400,CONT_DIF_P,*
-V 8200,6600,CONT_DIF_P,*
-V 8200,6200,CONT_DIF_P,*
-V 7600,6900,CONT_DIF_P,*
-V 8200,8200,CONT_DIF_P,*
-V 7600,11400,CONT_DIF_P,*
-V 7600,6400,CONT_DIF_P,*
-V 7600,10900,CONT_DIF_P,*
-V 8200,7800,CONT_DIF_P,*
-V 8200,7000,CONT_DIF_P,*
-V 8200,11400,CONT_DIF_P,*
-V 8800,11400,CONT_DIF_P,*
-V 9900,6700,CONT_DIF_P,*
-V 8200,11000,CONT_DIF_P,*
-V 8200,10600,CONT_DIF_P,*
-V 8200,10200,CONT_DIF_P,*
-V 9900,7300,CONT_DIF_P,*
-V 9900,7800,CONT_DIF_P,*
-V 9900,6200,CONT_DIF_P,*
-V 9900,8300,CONT_DIF_P,*
-V 10500,6200,CONT_DIF_P,*
-V 10500,7000,CONT_DIF_P,*
-V 10500,6200,CONT_DIF_P,*
-V 10500,7400,CONT_DIF_P,*
-V 10500,8200,CONT_DIF_P,*
-V 8200,9800,CONT_DIF_P,*
-V 7600,9900,CONT_DIF_P,*
-V 7600,9400,CONT_DIF_P,*
-V 7600,8900,CONT_DIF_P,*
-V 8200,8600,CONT_DIF_P,*
-V 8200,9000,CONT_DIF_P,*
-V 8200,9400,CONT_DIF_P,*
-V 8800,6200,CONT_DIF_P,*
-V 7600,7900,CONT_DIF_P,*
-V 7600,7400,CONT_DIF_P,*
-V 7600,8400,CONT_DIF_P,*
-V 7600,10400,CONT_DIF_P,*
-V 8800,11000,CONT_DIF_P,*
-V 8800,10600,CONT_DIF_P,*
-V 8800,9800,CONT_DIF_P,*
-V 8800,9400,CONT_DIF_P,*
-V 8800,8600,CONT_DIF_P,*
-V 8800,8200,CONT_DIF_P,*
-V 8800,7400,CONT_DIF_P,*
-V 8800,7000,CONT_DIF_P,*
-V 8200,3100,CONT_DIF_N,*
-V 7600,2600,CONT_DIF_N,*
-V 11100,2600,CONT_DIF_N,*
-V 8200,2100,CONT_DIF_N,*
-V 9900,2100,CONT_DIF_N,*
-V 7600,1600,CONT_DIF_N,*
-V 7600,2100,CONT_DIF_N,*
-V 11700,2600,CONT_DIF_N,*
-V 11700,3100,CONT_DIF_N,*
-V 7600,1100,CONT_DIF_N,*
-V 9900,1100,CONT_DIF_N,*
-V 11700,2100,CONT_DIF_N,*
-V 11700,1600,CONT_DIF_N,*
-V 7600,3100,CONT_DIF_N,*
-V 11100,2100,CONT_DIF_N,*
-V 11700,1100,CONT_DIF_N,*
-V 10500,1700,CONT_DIF_N,*
-V 11100,1100,CONT_DIF_N,*
-V 8200,1600,CONT_DIF_N,*
-V 8800,1200,CONT_DIF_N,*
-V 8800,1700,CONT_DIF_N,*
-V 8800,2700,CONT_DIF_N,*
-V 10500,2700,CONT_DIF_N,*
-V 10500,1200,CONT_DIF_N,*
-V 9900,2600,CONT_DIF_N,*
-V 9900,3100,CONT_DIF_N,*
-V 11100,3100,CONT_DIF_N,*
-V 8200,2600,CONT_DIF_N,*
-V 9700,25900,CONT_BODY_P,*
-V 9700,24700,CONT_BODY_P,*
-V 9700,25500,CONT_BODY_P,*
-V 9500,13100,CONT_VIA,*
-V 10000,22500,CONT_BODY_N,*
-V 10000,20800,CONT_BODY_N,*
-V 10000,21600,CONT_BODY_N,*
-V 10000,22000,CONT_BODY_N,*
-V 10000,21200,CONT_BODY_N,*
-V 10000,19200,CONT_BODY_N,*
-V 10000,18800,CONT_BODY_N,*
-V 10000,16800,CONT_BODY_N,*
-V 10000,18400,CONT_BODY_N,*
-V 10000,15600,CONT_BODY_N,*
-V 10000,14800,CONT_BODY_N,*
-V 10000,16000,CONT_BODY_N,*
-V 10000,16400,CONT_BODY_N,*
-V 10000,17600,CONT_BODY_N,*
-V 10000,20000,CONT_BODY_N,*
-V 10000,19600,CONT_BODY_N,*
-V 10000,15200,CONT_BODY_N,*
-V 9600,13600,CONT_BODY_N,*
-V 10000,13600,CONT_BODY_N,*
-V 10000,17200,CONT_BODY_N,*
-V 10000,20400,CONT_BODY_N,*
-V 10000,18000,CONT_BODY_N,*
-V 10000,14000,CONT_BODY_N,*
-V 10000,14400,CONT_BODY_N,*
-V 7000,13600,CONT_BODY_N,*
-V 7900,13600,CONT_VIA,*
-V 7300,21900,CONT_DIF_P,*
-V 7900,21900,CONT_DIF_P,*
-V 8500,21900,CONT_DIF_P,*
-V 9100,21900,CONT_DIF_P,*
-V 7900,22500,CONT_BODY_N,*
-V 9100,22500,CONT_BODY_N,*
-V 7900,23800,CONT_VIA,*
-V 9100,24300,CONT_BODY_P,*
-V 7900,24300,CONT_BODY_P,*
-V 9100,21500,CONT_DIF_P,*
-V 8500,21500,CONT_DIF_P,*
-V 7900,21500,CONT_DIF_P,*
-V 7300,21500,CONT_DIF_P,*
-V 7900,21100,CONT_VIA,*
-V 9100,21100,CONT_VIA,*
-V 8500,21100,CONT_DIF_P,*
-V 7300,21100,CONT_DIF_P,*
-V 7300,20700,CONT_DIF_P,*
-V 8500,20700,CONT_DIF_P,*
-V 9100,20700,CONT_DIF_P,*
-V 7900,20700,CONT_DIF_P,*
-V 9100,20300,CONT_DIF_P,*
-V 7900,20300,CONT_DIF_P,*
-V 8500,20300,CONT_DIF_P,*
-V 7300,20300,CONT_DIF_P,*
-V 9100,19900,CONT_VIA,*
-V 7900,19900,CONT_VIA,*
-V 8500,19900,CONT_DIF_P,*
-V 7300,19900,CONT_DIF_P,*
-V 9100,16300,CONT_VIA,*
-V 9100,17500,CONT_VIA,*
-V 9100,18700,CONT_VIA,*
-V 7900,16300,CONT_VIA,*
-V 7900,18700,CONT_VIA,*
-V 7900,17500,CONT_VIA,*
-V 9100,15100,CONT_VIA,*
-V 7900,15100,CONT_VIA,*
-V 8500,16700,CONT_DIF_P,*
-V 9100,16700,CONT_DIF_P,*
-V 9100,17100,CONT_DIF_P,*
-V 9100,15900,CONT_DIF_P,*
-V 8500,15900,CONT_DIF_P,*
-V 8500,16300,CONT_DIF_P,*
-V 9100,18300,CONT_DIF_P,*
-V 9100,17900,CONT_DIF_P,*
-V 8500,17900,CONT_DIF_P,*
-V 8500,17100,CONT_DIF_P,*
-V 8500,17500,CONT_DIF_P,*
-V 8500,19500,CONT_DIF_P,*
-V 9100,19100,CONT_DIF_P,*
-V 8500,19100,CONT_DIF_P,*
-V 8500,18700,CONT_DIF_P,*
-V 8500,18300,CONT_DIF_P,*
-V 9100,19500,CONT_DIF_P,*
-V 9100,15500,CONT_DIF_P,*
-V 8500,15500,CONT_DIF_P,*
-V 7900,17100,CONT_DIF_P,*
-V 7900,16700,CONT_DIF_P,*
-V 7300,16700,CONT_DIF_P,*
-V 7300,17100,CONT_DIF_P,*
-V 7300,17500,CONT_DIF_P,*
-V 7900,15900,CONT_DIF_P,*
-V 7300,15900,CONT_DIF_P,*
-V 7300,16300,CONT_DIF_P,*
-V 7900,19500,CONT_DIF_P,*
-V 7900,19100,CONT_DIF_P,*
-V 7300,19100,CONT_DIF_P,*
-V 7300,18700,CONT_DIF_P,*
-V 7900,18300,CONT_DIF_P,*
-V 7300,18300,CONT_DIF_P,*
-V 7900,17900,CONT_DIF_P,*
-V 7300,17900,CONT_DIF_P,*
-V 7300,19500,CONT_DIF_P,*
-V 7300,15500,CONT_DIF_P,*
-V 7900,15500,CONT_DIF_P,*
-V 8500,15100,CONT_DIF_P,*
-V 9100,14700,CONT_DIF_P,*
-V 8500,14700,CONT_DIF_P,*
-V 9100,14300,CONT_DIF_P,*
-V 8500,14300,CONT_DIF_P,*
-V 7300,14300,CONT_DIF_P,*
-V 7300,15100,CONT_DIF_P,*
-V 7900,14700,CONT_DIF_P,*
-V 7300,14700,CONT_DIF_P,*
-V 7900,14300,CONT_DIF_P,*
-V 8500,27400,CONT_DIF_N,*
-V 8500,27000,CONT_DIF_N,*
-V 8500,26600,CONT_DIF_N,*
-V 8500,27800,CONT_DIF_N,*
-V 8500,25000,CONT_DIF_N,*
-V 8500,25400,CONT_DIF_N,*
-V 8500,26200,CONT_DIF_N,*
-V 8500,25800,CONT_DIF_N,*
-V 7300,27000,CONT_DIF_N,*
-V 7300,26600,CONT_DIF_N,*
-V 7300,26200,CONT_DIF_N,*
-V 7300,25800,CONT_DIF_N,*
-V 7300,25400,CONT_DIF_N,*
-V 7300,27800,CONT_DIF_N,*
-V 7300,27400,CONT_DIF_N,*
-V 7300,25000,CONT_DIF_N,*
-V 7500,13600,CONT_BODY_N,*
-V 7900,28700,CONT_BODY_P,*
-V 9100,28700,CONT_BODY_P,*
-V 7900,26100,CONT_VIA,*
-V 7900,27700,CONT_VIA,*
-V 7900,25700,CONT_DIF_N,*
-V 7900,28100,CONT_DIF_N,*
-V 7900,26500,CONT_DIF_N,*
-V 7900,27300,CONT_DIF_N,*
-V 7900,26900,CONT_DIF_N,*
-V 7900,25300,CONT_DIF_N,*
-V 7900,24900,CONT_VIA,*
-V 9100,25300,CONT_DIF_N,*
-V 9100,26900,CONT_DIF_N,*
-V 9100,27300,CONT_DIF_N,*
-V 9100,25700,CONT_DIF_N,*
-V 9100,26100,CONT_DIF_N,*
-V 9100,27700,CONT_DIF_N,*
-V 9100,13100,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/padlib/paliot_sp.ap b/alliance/share/cells/padlib/paliot_sp.ap
deleted file mode 100644
index b827f3a3..00000000
--- a/alliance/share/cells/padlib/paliot_sp.ap
+++ /dev/null
@@ -1,2062 +0,0 @@
-V ALLIANCE : 6
-H paliot_sp,P, 9/10/2000,100
-A 0,-700,17200,35600
-C 0,29600,12000,vsse,0,WEST,ALU2
-C 17200,29600,12000,vsse,1,EAST,ALU2
-C 17200,16800,12000,vdde,1,EAST,ALU2
-C 0,16800,12000,vdde,0,WEST,ALU2
-C 17200,8400,4000,vddi,1,EAST,ALU2
-C 17200,4000,4000,vssi,1,EAST,ALU2
-C 0,4000,4000,vssi,0,WEST,ALU2
-C 0,8400,4000,vddi,0,WEST,ALU2
-C 17200,600,1200,ck,1,EAST,ALU2
-C 0,600,1200,ck,0,WEST,ALU2
-C 3800,-700,200,t,1,SOUTH,ALU2
-C 4900,-700,200,i,1,SOUTH,ALU2
-C 15700,-700,200,b,1,SOUTH,ALU2
-C 15700,-700,200,b,0,SOUTH,ALU1
-C 3800,-700,200,t,0,SOUTH,ALU1
-C 4900,-700,200,i,0,SOUTH,ALU1
-S 15800,24300,16400,24300,200,*,RIGHT,ALU1
-S 15800,24300,15800,28800,200,*,UP,ALU1
-S 16200,24300,16200,29300,600,*,UP,ALU1
-S 2600,23900,2600,28800,200,*,UP,ALU1
-S 3800,24300,3800,28800,200,*,UP,ALU1
-S 5000,23800,5000,28800,200,*,UP,ALU1
-S 6200,24300,6200,28800,200,*,UP,ALU1
-S 8600,24300,8600,28800,200,*,UP,ALU1
-S 11000,24300,11000,28800,200,*,UP,ALU1
-S 13400,24300,13400,28800,200,*,UP,ALU1
-S 16400,1600,16900,1600,200,*,LEFT,ALU1
-S 3700,23200,16900,23200,200,*,RIGHT,ALU2
-S 6800,1600,16900,1600,200,*,RIGHT,ALU2
-S 3700,13600,5300,13600,200,*,RIGHT,ALU1
-S 3800,13600,3800,22600,200,*,UP,ALU1
-S 16900,1600,16900,23300,200,*,UP,ALU1
-S 800,-200,3200,-200,200,*,RIGHT,ALU1
-S 5400,-200,15100,-200,200,*,RIGHT,ALU1
-S 15200,-200,15200,4000,200,*,UP,ALU1
-S 800,5000,800,12000,200,*,DOWN,ALU1
-S 800,12000,2200,12000,200,*,RIGHT,ALU1
-S 1800,9200,2000,9200,100,*,RIGHT,ALU1
-S 800,10300,2100,10300,1000,*,LEFT,ALU1
-S 1100,8800,1100,9900,500,*,DOWN,ALU1
-S 3200,12000,6200,12000,200,*,RIGHT,ALU1
-S 800,-100,800,4100,200,*,UP,ALU1
-S 2000,-200,2000,3900,200,*,UP,ALU1
-S 3200,-200,3200,3900,200,*,UP,ALU1
-S 11000,-200,11000,3200,200,*,UP,ALU1
-S 9800,-200,9800,4100,200,*,UP,ALU1
-S 8600,-200,8600,4100,200,*,UP,ALU1
-S 7400,-200,7400,3200,200,*,UP,ALU1
-S 6200,-200,6200,4100,200,*,UP,ALU1
-S 6200,5200,6200,12000,200,*,UP,ALU1
-S 3200,5000,3200,12000,200,*,UP,ALU1
-S 4400,5000,4400,12000,200,*,UP,ALU1
-S 4400,-300,4400,4000,200,*,UP,ALU1
-S 15100,4500,15800,4500,200,*,LEFT,ALU1
-S 7700,5100,11700,5100,200,*,RIGHT,ALU1
-S 6200,4000,10400,4000,200,*,RIGHT,ALU1
-S 11000,5100,11000,12100,200,*,UP,ALU1
-S 16200,13500,16200,22600,600,*,UP,ALU1
-S 15800,13600,15800,22600,200,*,UP,ALU1
-S 14600,13600,14600,22600,200,*,UP,ALU1
-S 13400,13600,13400,22600,200,*,UP,ALU1
-S 12200,13600,12200,22600,200,*,UP,ALU1
-S 11000,13600,11000,22600,200,*,UP,ALU1
-S 9800,13600,9800,22600,200,*,UP,ALU1
-S 8600,13600,8600,22600,200,*,UP,ALU1
-S 7400,13600,7400,22600,200,*,UP,ALU1
-S 6200,13600,6200,22600,200,*,UP,ALU1
-S 5000,13600,5000,22600,200,*,UP,ALU1
-S 2600,13700,2600,22600,200,*,UP,ALU1
-S 2600,12600,3300,12600,200,*,RIGHT,ALU1
-S 2700,9000,2700,12600,200,*,UP,ALU1
-S 3200,12600,3200,13000,200,*,UP,ALU1
-S 14000,3900,14000,13100,200,*,UP,ALU1
-S 12800,5800,12800,13000,200,*,UP,ALU1
-S 11600,5800,11600,13100,200,*,UP,ALU1
-S 10400,5800,10400,13100,200,*,UP,ALU1
-S 9200,5800,9200,13100,200,*,UP,ALU1
-S 8000,5800,8000,13100,200,*,UP,ALU1
-S 6800,5800,6800,13100,200,*,UP,ALU1
-S 3700,13100,15300,13100,200,*,RIGHT,ALU1
-S 0,16800,17200,16800,12000,vdde,RIGHT,ALU2
-S 0,8400,17200,8400,4000,vddi,RIGHT,ALU2
-S 0,4000,17200,4000,4000,vssi,RIGHT,ALU2
-S 0,600,17200,600,1200,ck,RIGHT,ALU2
-S 3200,13100,3800,13100,200,*,RIGHT,POLY
-S 2000,14200,2000,29100,200,*,UP,ALU1
-S 3200,14200,3200,29100,200,*,UP,ALU1
-S 3800,24800,3800,28200,300,*,UP,NDIF
-S 3200,24800,3200,28200,300,*,UP,NDIF
-S 2600,24800,2600,28200,300,*,UP,NDIF
-S 2000,24800,2000,28200,300,*,UP,NDIF
-S 1700,24600,1700,28400,100,*,UP,NTRANS
-S 2300,24600,2300,28400,100,*,UP,NTRANS
-S 2900,24600,2900,28400,100,*,UP,NTRANS
-S 3500,24600,3500,28400,100,*,UP,NTRANS
-S 1500,28700,3900,28700,300,*,RIGHT,PTIE
-S 3800,14100,3800,22000,300,*,UP,PDIF
-S 3200,14100,3200,22000,200,*,UP,PDIF
-S 2600,14100,2600,22000,200,*,UP,PDIF
-S 2000,14100,2000,22000,200,*,UP,PDIF
-S 1700,13900,1700,22200,100,*,UP,PTRANS
-S 2300,13900,2300,22200,100,*,UP,PTRANS
-S 2900,13900,2900,22200,100,*,UP,PTRANS
-S 3500,13900,3500,22200,100,*,UP,PTRANS
-S 2800,13400,2800,22700,2800,*,UP,NWELL
-S 1500,13600,2900,13600,300,*,RIGHT,NTIE
-S 3500,13600,3900,13600,300,*,RIGHT,NTIE
-S 1700,13900,3500,13900,100,*,RIGHT,POLY
-S 3200,23700,3200,23900,200,*,DOWN,POLY
-S 1500,24300,2900,24300,300,*,RIGHT,PTIE
-S 3500,24300,3900,24300,300,*,RIGHT,PTIE
-S 1700,24600,3500,24600,100,*,RIGHT,POLY
-S 3200,23800,3200,24600,200,*,UP,POLY
-S 3200,23800,3700,23800,300,*,RIGHT,POLY
-S 1500,22500,3900,22500,300,*,RIGHT,NTIE
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-S 1500,13600,2700,13600,200,*,RIGHT,ALU1
-S 3200,13000,3200,14300,200,*,DOWN,ALU1
-S 3900,22500,6300,22500,300,*,RIGHT,NTIE
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-S 5600,23800,6100,23800,300,*,RIGHT,POLY
-S 5600,23800,5600,24600,200,*,UP,POLY
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-S 5900,24300,6300,24300,300,*,RIGHT,PTIE
-S 3900,24300,5300,24300,300,*,RIGHT,PTIE
-S 5600,23700,5600,23900,200,*,DOWN,POLY
-S 5900,13600,6300,13600,200,*,RIGHT,ALU1
-S 4100,13900,5900,13900,100,*,RIGHT,POLY
-S 5600,13300,5600,13900,200,*,UP,POLY
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-S 4400,14100,4400,22000,200,*,UP,PDIF
-S 5000,14100,5000,22000,200,*,UP,PDIF
-S 5600,14100,5600,22000,200,*,UP,PDIF
-S 6200,14100,6200,22000,300,*,UP,PDIF
-S 3900,28700,6300,28700,300,*,RIGHT,PTIE
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-S 5300,24600,5300,28400,100,*,UP,NTRANS
-S 4700,24600,4700,28400,100,*,UP,NTRANS
-S 4100,24600,4100,28400,100,*,UP,NTRANS
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-S 5000,24800,5000,28200,300,*,UP,NDIF
-S 5600,24800,5600,28200,300,*,UP,NDIF
-S 6200,24800,6200,28200,300,*,UP,NDIF
-S 5600,14200,5600,29100,200,*,UP,ALU1
-S 4400,14200,4400,29100,200,*,UP,ALU1
-S 6300,22500,8700,22500,300,*,RIGHT,NTIE
-S 8500,23200,8500,23800,200,*,UP,ALU1
-S 8000,23800,8500,23800,300,*,RIGHT,POLY
-S 8000,23800,8000,24600,200,*,UP,POLY
-S 6500,24600,8300,24600,100,*,RIGHT,POLY
-S 8300,24300,8700,24300,300,*,RIGHT,PTIE
-S 6300,24300,7700,24300,300,*,RIGHT,PTIE
-S 8000,23700,8000,23900,200,*,DOWN,POLY
-S 8300,13600,8700,13600,200,*,RIGHT,ALU1
-S 6300,13600,7700,13600,200,*,RIGHT,ALU1
-S 6500,13900,8300,13900,100,*,RIGHT,POLY
-S 8000,13300,8000,13900,200,*,UP,POLY
-S 8300,13600,8700,13600,300,*,RIGHT,NTIE
-S 6300,13600,7700,13600,300,*,RIGHT,NTIE
-S 7600,13400,7600,22700,2800,*,UP,NWELL
-S 8300,13900,8300,22200,100,*,UP,PTRANS
-S 7700,13900,7700,22200,100,*,UP,PTRANS
-S 7100,13900,7100,22200,100,*,UP,PTRANS
-S 6500,13900,6500,22200,100,*,UP,PTRANS
-S 6800,14100,6800,22000,200,*,UP,PDIF
-S 7400,14100,7400,22000,200,*,UP,PDIF
-S 8000,14100,8000,22000,200,*,UP,PDIF
-S 8600,14100,8600,22000,300,*,UP,PDIF
-S 6300,28700,8700,28700,300,*,RIGHT,PTIE
-S 8300,24600,8300,28400,100,*,UP,NTRANS
-S 7700,24600,7700,28400,100,*,UP,NTRANS
-S 7100,24600,7100,28400,100,*,UP,NTRANS
-S 6500,24600,6500,28400,100,*,UP,NTRANS
-S 6800,24800,6800,28200,300,*,UP,NDIF
-S 7400,24800,7400,28200,300,*,UP,NDIF
-S 8000,24800,8000,28200,300,*,UP,NDIF
-S 8600,24800,8600,28200,300,*,UP,NDIF
-S 7400,23700,7400,28800,200,*,UP,ALU1
-S 8000,14200,8000,29100,200,*,UP,ALU1
-S 6800,14200,6800,29100,200,*,UP,ALU1
-S 8700,22500,11100,22500,300,*,RIGHT,NTIE
-S 10900,23200,10900,23800,200,*,UP,ALU1
-S 10400,23800,10900,23800,300,*,RIGHT,POLY
-S 10400,23800,10400,24600,200,*,UP,POLY
-S 8900,24600,10700,24600,100,*,RIGHT,POLY
-S 10700,24300,11100,24300,300,*,RIGHT,PTIE
-S 8700,24300,10100,24300,300,*,RIGHT,PTIE
-S 10400,23700,10400,23900,200,*,DOWN,POLY
-S 10700,13600,11100,13600,200,*,RIGHT,ALU1
-S 8700,13600,10100,13600,200,*,RIGHT,ALU1
-S 8900,13900,10700,13900,100,*,RIGHT,POLY
-S 10400,13300,10400,13900,200,*,UP,POLY
-S 10700,13600,11100,13600,300,*,RIGHT,NTIE
-S 8700,13600,10100,13600,300,*,RIGHT,NTIE
-S 10000,13400,10000,22700,2800,*,UP,NWELL
-S 10700,13900,10700,22200,100,*,UP,PTRANS
-S 10100,13900,10100,22200,100,*,UP,PTRANS
-S 9500,13900,9500,22200,100,*,UP,PTRANS
-S 8900,13900,8900,22200,100,*,UP,PTRANS
-S 9200,14100,9200,22000,200,*,UP,PDIF
-S 9800,14100,9800,22000,200,*,UP,PDIF
-S 10400,14100,10400,22000,200,*,UP,PDIF
-S 11000,14100,11000,22000,300,*,UP,PDIF
-S 8700,28700,11100,28700,300,*,RIGHT,PTIE
-S 10700,24600,10700,28400,100,*,UP,NTRANS
-S 10100,24600,10100,28400,100,*,UP,NTRANS
-S 9500,24600,9500,28400,100,*,UP,NTRANS
-S 8900,24600,8900,28400,100,*,UP,NTRANS
-S 9200,24800,9200,28200,300,*,UP,NDIF
-S 9800,24800,9800,28200,300,*,UP,NDIF
-S 10400,24800,10400,28200,300,*,UP,NDIF
-S 11000,24800,11000,28200,300,*,UP,NDIF
-S 9800,23700,9800,28800,200,*,UP,ALU1
-S 10400,14200,10400,29100,200,*,UP,ALU1
-S 9200,14200,9200,29100,200,*,UP,ALU1
-S 11100,22500,13500,22500,300,*,RIGHT,NTIE
-S 13300,23200,13300,23800,200,*,UP,ALU1
-S 12800,23800,13300,23800,300,*,RIGHT,POLY
-S 12800,23800,12800,24600,200,*,UP,POLY
-S 11300,24600,13100,24600,100,*,RIGHT,POLY
-S 13100,24300,13500,24300,300,*,RIGHT,PTIE
-S 11100,24300,12500,24300,300,*,RIGHT,PTIE
-S 12800,23700,12800,23900,200,*,DOWN,POLY
-S 13100,13600,13500,13600,200,*,RIGHT,ALU1
-S 11100,13600,12500,13600,200,*,RIGHT,ALU1
-S 11300,13900,13100,13900,100,*,RIGHT,POLY
-S 12800,13300,12800,13900,200,*,UP,POLY
-S 13100,13600,13500,13600,300,*,RIGHT,NTIE
-S 11100,13600,12500,13600,300,*,RIGHT,NTIE
-S 12400,13400,12400,22700,2800,*,UP,NWELL
-S 13100,13900,13100,22200,100,*,UP,PTRANS
-S 12500,13900,12500,22200,100,*,UP,PTRANS
-S 11900,13900,11900,22200,100,*,UP,PTRANS
-S 11300,13900,11300,22200,100,*,UP,PTRANS
-S 11600,14100,11600,22000,200,*,UP,PDIF
-S 12200,14100,12200,22000,200,*,UP,PDIF
-S 12800,14100,12800,22000,200,*,UP,PDIF
-S 13400,14100,13400,22000,300,*,UP,PDIF
-S 11100,28700,13500,28700,300,*,RIGHT,PTIE
-S 13100,24600,13100,28400,100,*,UP,NTRANS
-S 12500,24600,12500,28400,100,*,UP,NTRANS
-S 11900,24600,11900,28400,100,*,UP,NTRANS
-S 11300,24600,11300,28400,100,*,UP,NTRANS
-S 11600,24800,11600,28200,300,*,UP,NDIF
-S 12200,24800,12200,28200,300,*,UP,NDIF
-S 12800,24800,12800,28200,300,*,UP,NDIF
-S 13400,24800,13400,28200,300,*,UP,NDIF
-S 12200,23700,12200,28800,200,*,UP,ALU1
-S 12800,14200,12800,29100,200,*,UP,ALU1
-S 11600,14200,11600,29100,200,*,UP,ALU1
-S 13500,22500,15900,22500,300,*,RIGHT,NTIE
-S 15700,23200,15700,23800,200,*,UP,ALU1
-S 15200,23800,15700,23800,300,*,RIGHT,POLY
-S 15200,23800,15200,24600,200,*,UP,POLY
-S 13700,24600,15500,24600,100,*,RIGHT,POLY
-S 15500,24300,15900,24300,300,*,RIGHT,PTIE
-S 13500,24300,14900,24300,300,*,RIGHT,PTIE
-S 15200,23700,15200,23900,200,*,DOWN,POLY
-S 15500,13600,15900,13600,200,*,RIGHT,ALU1
-S 13500,13600,14900,13600,200,*,RIGHT,ALU1
-S 13700,13900,15500,13900,100,*,RIGHT,POLY
-S 15200,13300,15200,13900,200,*,UP,POLY
-S 15500,13600,15900,13600,300,*,RIGHT,NTIE
-S 13500,13600,14900,13600,300,*,RIGHT,NTIE
-S 14800,13400,14800,22700,2800,*,UP,NWELL
-S 15500,13900,15500,22200,100,*,UP,PTRANS
-S 14900,13900,14900,22200,100,*,UP,PTRANS
-S 14300,13900,14300,22200,100,*,UP,PTRANS
-S 13700,13900,13700,22200,100,*,UP,PTRANS
-S 14000,14100,14000,22000,200,*,UP,PDIF
-S 14600,14100,14600,22000,200,*,UP,PDIF
-S 15200,14100,15200,22000,200,*,UP,PDIF
-S 15800,14100,15800,22000,300,*,UP,PDIF
-S 13500,28700,15900,28700,300,*,RIGHT,PTIE
-S 15500,24600,15500,28400,100,*,UP,NTRANS
-S 14900,24600,14900,28400,100,*,UP,NTRANS
-S 14300,24600,14300,28400,100,*,UP,NTRANS
-S 13700,24600,13700,28400,100,*,UP,NTRANS
-S 14000,24800,14000,28200,300,*,UP,NDIF
-S 14600,24800,14600,28200,300,*,UP,NDIF
-S 15200,24800,15200,28200,300,*,UP,NDIF
-S 15800,24800,15800,28200,300,*,UP,NDIF
-S 14600,23700,14600,28800,200,*,UP,ALU1
-S 15200,14200,15200,29100,200,*,UP,ALU1
-S 14000,14200,14000,29100,200,*,UP,ALU1
-S 3700,23100,3700,23800,200,*,UP,ALU1
-S 15800,28900,15800,29300,200,*,UP,ALU1
-S 8600,29200,8600,35600,13500,*,UP,ALU1
-S 700,28000,700,28800,100,*,UP,ALU1
-S 1100,24200,1100,29300,800,*,UP,ALU1
-S 2000,5700,2000,9300,200,*,DOWN,ALU1
-S 1800,9200,1800,9400,200,*,DOWN,ALU1
-S 15500,8100,15500,12100,2000,*,DOWN,ALU1
-S 15800,2800,15800,7500,200,*,UP,ALU1
-S 14600,2700,14600,7500,200,*,UP,ALU1
-S 15200,5000,15200,12100,200,*,UP,ALU1
-S 9700,4600,11100,4600,200,*,LEFT,ALU1
-S 11100,3900,11100,4600,200,*,UP,ALU1
-S 14000,600,14000,3300,200,*,UP,ALU1
-S 12800,600,12800,3300,200,*,UP,ALU1
-S 12200,700,12200,3900,200,*,UP,ALU1
-S 12200,4600,12200,11400,200,*,UP,ALU1
-S 11600,4600,13500,4600,200,*,RIGHT,ALU1
-S 13400,4600,13400,11400,200,*,UP,ALU1
-S 3700,13100,15300,13100,200,*,RIGHT,ALU1
-S 13400,700,13400,3900,200,*,UP,ALU1
-S 11600,600,11600,4600,200,*,UP,ALU1
-S 12200,3900,14000,3900,200,*,RIGHT,ALU1
-S 8600,5000,8600,12000,200,*,UP,ALU1
-S 6800,600,6800,3300,200,*,UP,ALU1
-S 1400,4500,3300,4500,200,*,RIGHT,ALU1
-S 6200,5100,7100,5100,200,*,RIGHT,ALU1
-S 2600,900,2600,8200,200,*,UP,ALU1
-S 1400,900,1400,4500,200,*,UP,ALU1
-S 5600,900,5600,11400,200,*,UP,ALU1
-S 5600,4600,7300,4600,200,*,RIGHT,ALU1
-S 9800,5700,9800,12000,200,*,UP,ALU1
-S 7400,5700,7400,12000,200,*,UP,ALU1
-S 10400,600,10400,3300,200,*,UP,ALU1
-S 9200,600,9200,3300,200,*,UP,ALU1
-S 8000,600,8000,3300,200,*,UP,ALU1
-S 5000,900,5000,11400,200,*,UP,ALU1
-S 14900,-100,14900,1900,800,*,DOWN,ALU1
-S 1400,11300,2700,11300,200,*,RIGHT,ALU1
-S 1100,13500,1100,22600,800,*,UP,ALU1
-S 700,5100,2100,5100,200,*,LEFT,ALU1
-S 1100,5000,1100,8700,900,*,UP,ALU1
-S 4900,-700,4900,300,200,*,UP,ALU1
-S 15700,-700,15700,2300,200,*,DOWN,ALU1
-S 3800,-700,3800,11400,200,*,UP,ALU1
-S 2900,3700,2900,5400,100,*,UP,POLY
-S 8900,5400,10700,5400,100,*,RIGHT,POLY
-S 8900,3700,10700,3700,100,*,RIGHT,POLY
-S 9800,4600,9800,5400,300,*,DOWN,POLY
-S 10800,4500,11300,4500,100,*,LEFT,POLY
-S 11300,4500,11300,5400,100,*,DOWN,POLY
-S 11300,5400,14900,5400,100,*,RIGHT,POLY
-S 10700,3700,10700,4500,100,*,DOWN,POLY
-S 7400,3700,7400,5400,200,*,UP,POLY
-S 3600,4500,4000,4500,300,*,RIGHT,POLY
-S 2900,8700,2900,9000,100,*,UP,POLY
-S 4700,3700,4700,5400,100,*,UP,POLY
-S 4100,3700,4100,5400,100,*,UP,POLY
-S 3500,3700,3500,5400,100,*,UP,POLY
-S 4700,200,4700,400,100,*,UP,POLY
-S 1700,3700,2900,3700,100,*,RIGHT,POLY
-S 11300,3600,11300,4100,100,*,DOWN,POLY
-S 11400,3800,11400,4100,100,*,DOWN,POLY
-S 11400,3700,14300,3700,100,*,RIGHT,POLY
-S 11400,3600,14300,3600,100,*,RIGHT,POLY
-S 5900,3700,5900,5400,100,*,UP,POLY
-S 5200,5300,5900,5300,300,*,RIGHT,POLY
-S 6500,3700,8300,3700,100,*,RIGHT,POLY
-S 6500,5400,8300,5400,100,*,RIGHT,POLY
-S 14300,3700,14300,3900,100,*,DOWN,POLY
-S 14200,4700,14200,5300,100,*,DOWN,POLY
-S 14300,4700,14300,5300,100,*,DOWN,POLY
-S 14200,4500,14900,4500,300,*,RIGHT,POLY
-S 14900,3700,14900,4300,100,*,UP,POLY
-S 10600,3800,10600,4500,100,*,DOWN,POLY
-S 10600,4600,11200,4600,100,*,LEFT,POLY
-S 11400,4500,11400,5300,100,*,DOWN,POLY
-S 11300,5500,14900,5500,100,*,RIGHT,POLY
-S 15500,3700,15500,5500,100,*,UP,POLY
-S 15500,2200,15500,2400,100,*,DOWN,POLY
-S 14200,3700,14200,3900,100,*,DOWN,POLY
-S 15900,24300,16500,24300,300,*,RIGHT,PTIE
-S 16000,28700,16500,28700,300,*,RIGHT,PTIE
-S 16400,24200,16400,28800,300,*,UP,PTIE
-S 700,24300,1500,24300,300,*,RIGHT,PTIE
-S 800,24200,800,28800,300,*,UP,PTIE
-S 700,28700,1500,28700,300,*,RIGHT,PTIE
-S 16400,1700,16400,4100,300,*,UP,PTIE
-S 7700,4000,10400,4000,300,*,RIGHT,PTIE
-S 11600,4000,14000,4000,300,*,RIGHT,PTIE
-S 6100,4000,7100,4000,300,*,RIGHT,PTIE
-S 15700,4000,16500,4000,300,*,LEFT,PTIE
-S 14600,0,14600,1900,300,*,DOWN,PTIE
-S 14900,0,14900,1900,300,*,DOWN,PTIE
-S 15200,1800,16500,1800,300,*,LEFT,PTIE
-S 700,4000,2700,4000,300,*,RIGHT,PTIE
-S 15200,-300,15200,1900,300,*,DOWN,PTIE
-S 700,-200,15300,-200,300,*,RIGHT,PTIE
-S 800,-300,800,4100,300,*,UP,PTIE
-S 16000,22500,16500,22500,300,*,RIGHT,NTIE
-S 800,22500,1400,22500,300,*,RIGHT,NTIE
-S 7700,5100,9500,5100,300,*,RIGHT,NTIE
-S 10100,5100,11000,5100,300,*,RIGHT,NTIE
-S 15700,5100,16500,5100,300,*,RIGHT,NTIE
-S 1400,5100,1400,6400,1100,*,DOWN,NTIE
-S 2000,9700,2000,12000,300,*,UP,NTIE
-S 2000,5000,2000,9100,300,*,UP,NTIE
-S 2200,8900,2200,9900,300,*,UP,NTIE
-S 15500,8100,15500,12000,2000,*,DOWN,NTIE
-S 16400,13600,16400,22600,300,*,UP,NTIE
-S 6100,5100,7100,5100,300,*,RIGHT,NTIE
-S 16400,5000,16400,12100,300,*,UP,NTIE
-S 14500,5100,15300,5100,300,*,RIGHT,NTIE
-S 11600,5100,14000,5100,300,*,RIGHT,NTIE
-S 16000,13600,16500,13600,300,*,RIGHT,NTIE
-S 800,13600,800,22600,300,*,UP,NTIE
-S 800,13600,1400,13600,300,*,RIGHT,NTIE
-S 700,5100,2700,5100,300,*,RIGHT,NTIE
-S 800,5000,800,12100,300,*,UP,NTIE
-S 700,12000,16500,12000,300,*,RIGHT,NTIE
-S 15500,5500,15500,7800,100,*,UP,PTRANS
-S 14900,5500,14900,7800,100,*,UP,PTRANS
-S 15200,5700,15200,7600,300,*,UP,PDIF
-S 15800,5700,15800,7600,300,*,UP,PDIF
-S 14600,5700,14600,7600,300,*,UP,PDIF
-S 3500,5400,3500,11700,100,*,UP,PTRANS
-S 3800,5600,3800,11500,300,*,UP,PDIF
-S 3200,5600,3200,11500,300,*,UP,PDIF
-S 2600,5600,2600,8500,300,*,UP,PDIF
-S 2900,5400,2900,8700,100,*,UP,PTRANS
-S 10700,5400,10700,11700,100,*,UP,PTRANS
-S 4700,5400,4700,11700,100,*,UP,PTRANS
-S 5000,5600,5000,11500,300,*,UP,PDIF
-S 4400,5600,4400,11500,300,*,UP,PDIF
-S 4100,5400,4100,11700,100,*,UP,PTRANS
-S 11000,5600,11000,11500,300,*,UP,PDIF
-S 9200,5600,9200,11500,300,*,UP,PDIF
-S 8900,5400,8900,11700,100,*,UP,PTRANS
-S 9500,5400,9500,11700,100,*,UP,PTRANS
-S 10100,5400,10100,11700,100,*,UP,PTRANS
-S 5900,5400,5900,11700,100,*,UP,PTRANS
-S 6200,5600,6200,11500,300,*,UP,PDIF
-S 6500,5400,6500,11700,100,*,UP,PTRANS
-S 7100,5400,7100,11700,100,*,UP,PTRANS
-S 9800,5600,9800,11500,300,*,UP,PDIF
-S 8300,5400,8300,11700,100,*,UP,PTRANS
-S 7400,5600,7400,11500,300,*,UP,PDIF
-S 8600,5600,8600,11500,300,*,UP,PDIF
-S 6800,5600,6800,11500,300,*,UP,PDIF
-S 10400,5600,10400,11500,300,*,UP,PDIF
-S 8000,5600,8000,11500,300,*,UP,PDIF
-S 5600,5600,5600,11500,300,*,UP,PDIF
-S 12500,5500,12500,11700,100,*,UP,PTRANS
-S 11600,5700,11600,11500,300,*,UP,PDIF
-S 11900,5500,11900,11700,100,*,UP,PTRANS
-S 1400,14100,1400,22000,300,*,UP,PDIF
-S 7700,5400,7700,11700,100,*,UP,PTRANS
-S 14000,5700,14000,11500,300,*,UP,PDIF
-S 13700,5500,13700,11700,100,*,UP,PTRANS
-S 13400,5700,13400,11500,300,*,UP,PDIF
-S 13100,5500,13100,11700,100,*,UP,PTRANS
-S 12800,5700,12800,11500,300,*,UP,PDIF
-S 12200,5700,12200,11500,300,*,UP,PDIF
-S 1400,24900,1400,28200,300,*,UP,NDIF
-S 2300,400,2300,3700,100,*,UP,NTRANS
-S 1700,400,1700,3700,100,*,UP,NTRANS
-S 2000,600,2000,3500,200,*,UP,NDIF
-S 2600,600,2600,3500,300,*,UP,NDIF
-S 1400,600,1400,3500,300,*,UP,NDIF
-S 11000,600,11000,3500,300,*,UP,NDIF
-S 4100,400,4100,3700,100,*,UP,NTRANS
-S 3500,400,3500,3700,100,*,UP,NTRANS
-S 3800,600,3800,3500,300,*,UP,NDIF
-S 3200,600,3200,3500,200,*,UP,NDIF
-S 2900,400,2900,3700,100,*,UP,NTRANS
-S 9500,400,9500,3700,100,*,UP,NTRANS
-S 10100,400,10100,3700,100,*,UP,NTRANS
-S 4400,600,4400,3500,200,*,UP,NDIF
-S 4700,400,4700,3700,100,*,UP,NTRANS
-S 5000,600,5000,3500,300,*,UP,NDIF
-S 10700,400,10700,3700,100,*,UP,NTRANS
-S 9800,600,9800,3500,200,*,UP,NDIF
-S 9200,600,9200,3500,300,*,UP,NDIF
-S 8900,400,8900,3700,100,*,UP,NTRANS
-S 10400,600,10400,3500,300,*,UP,NDIF
-S 8000,600,8000,3500,300,*,UP,NDIF
-S 5600,600,5600,3500,300,*,UP,NDIF
-S 5900,400,5900,3700,100,*,UP,NTRANS
-S 6200,600,6200,3500,200,*,UP,NDIF
-S 6500,400,6500,3700,100,*,UP,NTRANS
-S 7100,400,7100,3700,100,*,UP,NTRANS
-S 7700,400,7700,3700,100,*,UP,NTRANS
-S 8300,400,8300,3700,100,*,UP,NTRANS
-S 7400,600,7400,3500,200,*,UP,NDIF
-S 8600,600,8600,3500,200,*,UP,NDIF
-S 6800,600,6800,3500,300,*,UP,NDIF
-S 11600,600,11600,3400,300,*,UP,NDIF
-S 13700,400,13700,3600,100,*,UP,NTRANS
-S 13100,400,13100,3600,100,*,UP,NTRANS
-S 12500,400,12500,3600,100,*,UP,NTRANS
-S 11900,400,11900,3600,100,*,UP,NTRANS
-S 15500,2400,15500,3700,100,*,UP,NTRANS
-S 15800,2600,15800,3500,300,*,UP,NDIF
-S 14000,600,14000,3400,300,*,UP,NDIF
-S 13400,600,13400,3400,200,*,UP,NDIF
-S 12800,600,12800,3400,300,*,UP,NDIF
-S 12200,600,12200,3400,200,*,UP,NDIF
-S 15200,2600,15200,3500,300,*,DOWN,NDIF
-S 14600,2600,14600,3500,300,*,UP,NDIF
-S 14900,2400,14900,3700,100,*,UP,NTRANS
-S 16300,13400,16300,22700,600,*,UP,NWELL
-S 1000,13400,1000,22700,800,*,UP,NWELL
-S 600,8600,16600,8600,7200,*,RIGHT,NWELL
-S 600,5100,16600,5100,400,*,RIGHT,NWELL
-S 16200,23200,17000,23200,200,*,RIGHT,ALU1
-S 16400,5000,16400,12100,200,*,UP,ALU1
-S 16400,2300,16400,4100,200,*,UP,ALU1
-S 0,29600,17200,29600,12000,vsse,RIGHT,ALU2
-S 1100,9100,1700,9100,3900,*,RIGHT,PTRANS
-V 16400,1600,CONT_VIA,*
-B 15500,9200,1800,2100,CONT_VIA,*
-B 16100,18000,800,9100,CONT_VIA,*
-B 1000,18000,700,9100,CONT_VIA,*
-B 1100,26700,800,5200,CONT_VIA,*
-V 3700,13600,CONT_BODY_N,*
-V 3800,13100,CONT_POLY,*
-V 3800,27700,CONT_DIF_N,*
-V 3800,26100,CONT_DIF_N,*
-V 3800,25700,CONT_DIF_N,*
-V 3800,27300,CONT_DIF_N,*
-V 3800,26900,CONT_DIF_N,*
-V 3800,25300,CONT_DIF_N,*
-V 3800,26500,CONT_VIA,*
-V 3800,24900,CONT_VIA,*
-V 3800,28100,CONT_VIA,*
-V 2600,24900,CONT_VIA,*
-V 2600,25300,CONT_DIF_N,*
-V 2600,26900,CONT_DIF_N,*
-V 2600,27300,CONT_DIF_N,*
-V 2600,26500,CONT_DIF_N,*
-V 2600,28100,CONT_DIF_N,*
-V 2600,25700,CONT_DIF_N,*
-V 2600,27700,CONT_VIA,*
-V 2600,26100,CONT_VIA,*
-V 3800,28700,CONT_BODY_P,*
-V 2600,28700,CONT_BODY_P,*
-V 2200,13600,CONT_BODY_N,*
-V 2000,25000,CONT_DIF_N,*
-V 2000,27400,CONT_DIF_N,*
-V 2000,27800,CONT_DIF_N,*
-V 2000,25400,CONT_DIF_N,*
-V 2000,25800,CONT_DIF_N,*
-V 2000,26200,CONT_DIF_N,*
-V 2000,26600,CONT_DIF_N,*
-V 2000,27000,CONT_DIF_N,*
-V 3200,25800,CONT_DIF_N,*
-V 3200,26200,CONT_DIF_N,*
-V 3200,25400,CONT_DIF_N,*
-V 3200,25000,CONT_DIF_N,*
-V 3200,27800,CONT_DIF_N,*
-V 3200,26600,CONT_DIF_N,*
-V 3200,27000,CONT_DIF_N,*
-V 3200,27400,CONT_DIF_N,*
-V 2600,14300,CONT_DIF_P,*
-V 2000,14700,CONT_DIF_P,*
-V 2600,14700,CONT_DIF_P,*
-V 2000,15100,CONT_DIF_P,*
-V 2000,14300,CONT_DIF_P,*
-V 3200,14300,CONT_DIF_P,*
-V 3800,14300,CONT_DIF_P,*
-V 3200,14700,CONT_DIF_P,*
-V 3800,14700,CONT_DIF_P,*
-V 3200,15100,CONT_DIF_P,*
-V 2600,15500,CONT_DIF_P,*
-V 2000,15500,CONT_DIF_P,*
-V 2000,19500,CONT_DIF_P,*
-V 2000,17900,CONT_DIF_P,*
-V 2600,17900,CONT_DIF_P,*
-V 2000,18300,CONT_DIF_P,*
-V 2600,18300,CONT_DIF_P,*
-V 2000,18700,CONT_DIF_P,*
-V 2000,19100,CONT_DIF_P,*
-V 2600,19100,CONT_DIF_P,*
-V 2600,19500,CONT_DIF_P,*
-V 2000,16300,CONT_DIF_P,*
-V 2000,15900,CONT_DIF_P,*
-V 2600,15900,CONT_DIF_P,*
-V 2000,17500,CONT_DIF_P,*
-V 2000,17100,CONT_DIF_P,*
-V 2000,16700,CONT_DIF_P,*
-V 2600,16700,CONT_DIF_P,*
-V 2600,17100,CONT_DIF_P,*
-V 3200,15500,CONT_DIF_P,*
-V 3800,15500,CONT_DIF_P,*
-V 3800,19500,CONT_DIF_P,*
-V 3200,18300,CONT_DIF_P,*
-V 3200,18700,CONT_DIF_P,*
-V 3200,19100,CONT_DIF_P,*
-V 3800,19100,CONT_DIF_P,*
-V 3200,19500,CONT_DIF_P,*
-V 3200,17500,CONT_DIF_P,*
-V 3200,17100,CONT_DIF_P,*
-V 3200,17900,CONT_DIF_P,*
-V 3800,17900,CONT_DIF_P,*
-V 3800,18300,CONT_DIF_P,*
-V 3200,16300,CONT_DIF_P,*
-V 3200,15900,CONT_DIF_P,*
-V 3800,15900,CONT_DIF_P,*
-V 3800,17100,CONT_DIF_P,*
-V 3800,16700,CONT_DIF_P,*
-V 3200,16700,CONT_DIF_P,*
-V 2600,15100,CONT_VIA,*
-V 3800,15100,CONT_VIA,*
-V 2600,17500,CONT_VIA,*
-V 2600,18700,CONT_VIA,*
-V 2600,16300,CONT_VIA,*
-V 3800,18700,CONT_VIA,*
-V 3800,17500,CONT_VIA,*
-V 3800,16300,CONT_VIA,*
-V 2000,19900,CONT_DIF_P,*
-V 3200,19900,CONT_DIF_P,*
-V 2600,19900,CONT_VIA,*
-V 3800,19900,CONT_VIA,*
-V 2000,20300,CONT_DIF_P,*
-V 3200,20300,CONT_DIF_P,*
-V 2600,20300,CONT_DIF_P,*
-V 3800,20300,CONT_DIF_P,*
-V 2600,20700,CONT_DIF_P,*
-V 3800,20700,CONT_DIF_P,*
-V 3200,20700,CONT_DIF_P,*
-V 2000,20700,CONT_DIF_P,*
-V 2000,21100,CONT_DIF_P,*
-V 3200,21100,CONT_DIF_P,*
-V 3800,21100,CONT_VIA,*
-V 2600,21100,CONT_VIA,*
-V 2000,21500,CONT_DIF_P,*
-V 2600,21500,CONT_DIF_P,*
-V 3200,21500,CONT_DIF_P,*
-V 3800,21500,CONT_DIF_P,*
-V 2600,24300,CONT_BODY_P,*
-V 3800,24300,CONT_BODY_P,*
-V 3700,23800,CONT_POLY,*
-V 2600,23800,CONT_VIA,*
-V 3800,22500,CONT_BODY_N,*
-V 2600,22500,CONT_BODY_N,*
-V 3800,21900,CONT_DIF_P,*
-V 3200,21900,CONT_DIF_P,*
-V 2600,21900,CONT_DIF_P,*
-V 2000,21900,CONT_DIF_P,*
-V 2600,13600,CONT_VIA,*
-V 1700,13600,CONT_BODY_N,*
-V 4400,21900,CONT_DIF_P,*
-V 5000,21900,CONT_DIF_P,*
-V 5600,21900,CONT_DIF_P,*
-V 6200,21900,CONT_DIF_P,*
-V 5000,22500,CONT_BODY_N,*
-V 6200,22500,CONT_BODY_N,*
-V 6100,23200,CONT_VIA,*
-V 5000,23800,CONT_VIA,*
-V 6100,23800,CONT_POLY,*
-V 6200,24300,CONT_BODY_P,*
-V 5000,24300,CONT_BODY_P,*
-V 6200,21500,CONT_DIF_P,*
-V 5600,21500,CONT_DIF_P,*
-V 5000,21500,CONT_DIF_P,*
-V 4400,21500,CONT_DIF_P,*
-V 5000,21100,CONT_VIA,*
-V 6200,21100,CONT_VIA,*
-V 5600,21100,CONT_DIF_P,*
-V 4400,21100,CONT_DIF_P,*
-V 4400,20700,CONT_DIF_P,*
-V 5600,20700,CONT_DIF_P,*
-V 6200,20700,CONT_DIF_P,*
-V 5000,20700,CONT_DIF_P,*
-V 6200,20300,CONT_DIF_P,*
-V 5000,20300,CONT_DIF_P,*
-V 5600,20300,CONT_DIF_P,*
-V 4400,20300,CONT_DIF_P,*
-V 6200,19900,CONT_VIA,*
-V 5000,19900,CONT_VIA,*
-V 5600,19900,CONT_DIF_P,*
-V 4400,19900,CONT_DIF_P,*
-V 6200,16300,CONT_VIA,*
-V 6200,17500,CONT_VIA,*
-V 6200,18700,CONT_VIA,*
-V 5000,16300,CONT_VIA,*
-V 5000,18700,CONT_VIA,*
-V 5000,17500,CONT_VIA,*
-V 6200,15100,CONT_VIA,*
-V 5000,15100,CONT_VIA,*
-V 5600,16700,CONT_DIF_P,*
-V 6200,16700,CONT_DIF_P,*
-V 6200,17100,CONT_DIF_P,*
-V 6200,15900,CONT_DIF_P,*
-V 5600,15900,CONT_DIF_P,*
-V 5600,16300,CONT_DIF_P,*
-V 6200,18300,CONT_DIF_P,*
-V 6200,17900,CONT_DIF_P,*
-V 5600,17900,CONT_DIF_P,*
-V 5600,17100,CONT_DIF_P,*
-V 5600,17500,CONT_DIF_P,*
-V 5600,19500,CONT_DIF_P,*
-V 6200,19100,CONT_DIF_P,*
-V 5600,19100,CONT_DIF_P,*
-V 5600,18700,CONT_DIF_P,*
-V 5600,18300,CONT_DIF_P,*
-V 6200,19500,CONT_DIF_P,*
-V 6200,15500,CONT_DIF_P,*
-V 5600,15500,CONT_DIF_P,*
-V 5000,17100,CONT_DIF_P,*
-V 5000,16700,CONT_DIF_P,*
-V 4400,16700,CONT_DIF_P,*
-V 4400,17100,CONT_DIF_P,*
-V 4400,17500,CONT_DIF_P,*
-V 5000,15900,CONT_DIF_P,*
-V 4400,15900,CONT_DIF_P,*
-V 4400,16300,CONT_DIF_P,*
-V 5000,19500,CONT_DIF_P,*
-V 5000,19100,CONT_DIF_P,*
-V 4400,19100,CONT_DIF_P,*
-V 4400,18700,CONT_DIF_P,*
-V 5000,18300,CONT_DIF_P,*
-V 4400,18300,CONT_DIF_P,*
-V 5000,17900,CONT_DIF_P,*
-V 4400,17900,CONT_DIF_P,*
-V 4400,19500,CONT_DIF_P,*
-V 4400,15500,CONT_DIF_P,*
-V 5000,15500,CONT_DIF_P,*
-V 5600,15100,CONT_DIF_P,*
-V 6200,14700,CONT_DIF_P,*
-V 5600,14700,CONT_DIF_P,*
-V 6200,14300,CONT_DIF_P,*
-V 5600,14300,CONT_DIF_P,*
-V 4400,14300,CONT_DIF_P,*
-V 4400,15100,CONT_DIF_P,*
-V 5000,14700,CONT_DIF_P,*
-V 4400,14700,CONT_DIF_P,*
-V 5000,14300,CONT_DIF_P,*
-V 5600,27400,CONT_DIF_N,*
-V 5600,27000,CONT_DIF_N,*
-V 5600,26600,CONT_DIF_N,*
-V 5600,27800,CONT_DIF_N,*
-V 5600,25000,CONT_DIF_N,*
-V 5600,25400,CONT_DIF_N,*
-V 5600,26200,CONT_DIF_N,*
-V 5600,25800,CONT_DIF_N,*
-V 4400,27000,CONT_DIF_N,*
-V 4400,26600,CONT_DIF_N,*
-V 4400,26200,CONT_DIF_N,*
-V 4400,25800,CONT_DIF_N,*
-V 4400,25400,CONT_DIF_N,*
-V 4400,27800,CONT_DIF_N,*
-V 4400,27400,CONT_DIF_N,*
-V 4400,25000,CONT_DIF_N,*
-V 4900,13600,CONT_VIA,*
-V 5600,13100,CONT_POLY,*
-V 6000,13600,CONT_BODY_N,*
-V 4600,13600,CONT_BODY_N,*
-V 5200,13600,CONT_BODY_N,*
-V 4100,13600,CONT_BODY_N,*
-V 5000,28700,CONT_BODY_P,*
-V 6200,28700,CONT_BODY_P,*
-V 5000,26100,CONT_VIA,*
-V 5000,27700,CONT_VIA,*
-V 5000,25700,CONT_DIF_N,*
-V 5000,28100,CONT_DIF_N,*
-V 5000,26500,CONT_DIF_N,*
-V 5000,27300,CONT_DIF_N,*
-V 5000,26900,CONT_DIF_N,*
-V 5000,25300,CONT_DIF_N,*
-V 5000,24900,CONT_VIA,*
-V 6200,28100,CONT_VIA,*
-V 6200,24900,CONT_VIA,*
-V 6200,26500,CONT_VIA,*
-V 6200,25300,CONT_DIF_N,*
-V 6200,26900,CONT_DIF_N,*
-V 6200,27300,CONT_DIF_N,*
-V 6200,25700,CONT_DIF_N,*
-V 6200,26100,CONT_DIF_N,*
-V 6200,27700,CONT_DIF_N,*
-V 6800,21900,CONT_DIF_P,*
-V 7400,21900,CONT_DIF_P,*
-V 8000,21900,CONT_DIF_P,*
-V 8600,21900,CONT_DIF_P,*
-V 7400,22500,CONT_BODY_N,*
-V 8600,22500,CONT_BODY_N,*
-V 8500,23200,CONT_VIA,*
-V 7400,23800,CONT_VIA,*
-V 8500,23800,CONT_POLY,*
-V 8600,24300,CONT_BODY_P,*
-V 7400,24300,CONT_BODY_P,*
-V 8600,21500,CONT_DIF_P,*
-V 8000,21500,CONT_DIF_P,*
-V 7400,21500,CONT_DIF_P,*
-V 6800,21500,CONT_DIF_P,*
-V 7400,21100,CONT_VIA,*
-V 8600,21100,CONT_VIA,*
-V 8000,21100,CONT_DIF_P,*
-V 6800,21100,CONT_DIF_P,*
-V 6800,20700,CONT_DIF_P,*
-V 8000,20700,CONT_DIF_P,*
-V 8600,20700,CONT_DIF_P,*
-V 7400,20700,CONT_DIF_P,*
-V 8600,20300,CONT_DIF_P,*
-V 7400,20300,CONT_DIF_P,*
-V 8000,20300,CONT_DIF_P,*
-V 6800,20300,CONT_DIF_P,*
-V 8600,19900,CONT_VIA,*
-V 7400,19900,CONT_VIA,*
-V 8000,19900,CONT_DIF_P,*
-V 6800,19900,CONT_DIF_P,*
-V 8600,16300,CONT_VIA,*
-V 8600,17500,CONT_VIA,*
-V 8600,18700,CONT_VIA,*
-V 7400,16300,CONT_VIA,*
-V 7400,18700,CONT_VIA,*
-V 7400,17500,CONT_VIA,*
-V 8600,15100,CONT_VIA,*
-V 7400,15100,CONT_VIA,*
-V 8000,16700,CONT_DIF_P,*
-V 8600,16700,CONT_DIF_P,*
-V 8600,17100,CONT_DIF_P,*
-V 8600,15900,CONT_DIF_P,*
-V 8000,15900,CONT_DIF_P,*
-V 8000,16300,CONT_DIF_P,*
-V 8600,18300,CONT_DIF_P,*
-V 8600,17900,CONT_DIF_P,*
-V 8000,17900,CONT_DIF_P,*
-V 8000,17100,CONT_DIF_P,*
-V 8000,17500,CONT_DIF_P,*
-V 8000,19500,CONT_DIF_P,*
-V 8600,19100,CONT_DIF_P,*
-V 8000,19100,CONT_DIF_P,*
-V 8000,18700,CONT_DIF_P,*
-V 8000,18300,CONT_DIF_P,*
-V 8600,19500,CONT_DIF_P,*
-V 8600,15500,CONT_DIF_P,*
-V 8000,15500,CONT_DIF_P,*
-V 7400,17100,CONT_DIF_P,*
-V 7400,16700,CONT_DIF_P,*
-V 6800,16700,CONT_DIF_P,*
-V 6800,17100,CONT_DIF_P,*
-V 6800,17500,CONT_DIF_P,*
-V 7400,15900,CONT_DIF_P,*
-V 6800,15900,CONT_DIF_P,*
-V 6800,16300,CONT_DIF_P,*
-V 7400,19500,CONT_DIF_P,*
-V 7400,19100,CONT_DIF_P,*
-V 6800,19100,CONT_DIF_P,*
-V 6800,18700,CONT_DIF_P,*
-V 7400,18300,CONT_DIF_P,*
-V 6800,18300,CONT_DIF_P,*
-V 7400,17900,CONT_DIF_P,*
-V 6800,17900,CONT_DIF_P,*
-V 6800,19500,CONT_DIF_P,*
-V 6800,15500,CONT_DIF_P,*
-V 7400,15500,CONT_DIF_P,*
-V 8000,15100,CONT_DIF_P,*
-V 8600,14700,CONT_DIF_P,*
-V 8000,14700,CONT_DIF_P,*
-V 8600,14300,CONT_DIF_P,*
-V 8000,14300,CONT_DIF_P,*
-V 6800,14300,CONT_DIF_P,*
-V 6800,15100,CONT_DIF_P,*
-V 7400,14700,CONT_DIF_P,*
-V 6800,14700,CONT_DIF_P,*
-V 7400,14300,CONT_DIF_P,*
-V 8000,27400,CONT_DIF_N,*
-V 8000,27000,CONT_DIF_N,*
-V 8000,26600,CONT_DIF_N,*
-V 8000,27800,CONT_DIF_N,*
-V 8000,25000,CONT_DIF_N,*
-V 8000,25400,CONT_DIF_N,*
-V 8000,26200,CONT_DIF_N,*
-V 8000,25800,CONT_DIF_N,*
-V 6800,27000,CONT_DIF_N,*
-V 6800,26600,CONT_DIF_N,*
-V 6800,26200,CONT_DIF_N,*
-V 6800,25800,CONT_DIF_N,*
-V 6800,25400,CONT_DIF_N,*
-V 6800,27800,CONT_DIF_N,*
-V 6800,27400,CONT_DIF_N,*
-V 6800,25000,CONT_DIF_N,*
-V 7300,13600,CONT_VIA,*
-V 8000,13100,CONT_POLY,*
-V 8400,13600,CONT_BODY_N,*
-V 7000,13600,CONT_BODY_N,*
-V 7600,13600,CONT_BODY_N,*
-V 6500,13600,CONT_BODY_N,*
-V 7400,28700,CONT_BODY_P,*
-V 8600,28700,CONT_BODY_P,*
-V 7400,26100,CONT_VIA,*
-V 7400,27700,CONT_VIA,*
-V 7400,25700,CONT_DIF_N,*
-V 7400,28100,CONT_DIF_N,*
-V 7400,26500,CONT_DIF_N,*
-V 7400,27300,CONT_DIF_N,*
-V 7400,26900,CONT_DIF_N,*
-V 7400,25300,CONT_DIF_N,*
-V 7400,24900,CONT_VIA,*
-V 8600,28100,CONT_VIA,*
-V 8600,24900,CONT_VIA,*
-V 8600,26500,CONT_VIA,*
-V 8600,25300,CONT_DIF_N,*
-V 8600,26900,CONT_DIF_N,*
-V 8600,27300,CONT_DIF_N,*
-V 8600,25700,CONT_DIF_N,*
-V 8600,26100,CONT_DIF_N,*
-V 8600,27700,CONT_DIF_N,*
-V 9200,21900,CONT_DIF_P,*
-V 9800,21900,CONT_DIF_P,*
-V 10400,21900,CONT_DIF_P,*
-V 11000,21900,CONT_DIF_P,*
-V 9800,22500,CONT_BODY_N,*
-V 11000,22500,CONT_BODY_N,*
-V 10900,23200,CONT_VIA,*
-V 9800,23800,CONT_VIA,*
-V 10900,23800,CONT_POLY,*
-V 11000,24300,CONT_BODY_P,*
-V 9800,24300,CONT_BODY_P,*
-V 11000,21500,CONT_DIF_P,*
-V 10400,21500,CONT_DIF_P,*
-V 9800,21500,CONT_DIF_P,*
-V 9200,21500,CONT_DIF_P,*
-V 9800,21100,CONT_VIA,*
-V 11000,21100,CONT_VIA,*
-V 10400,21100,CONT_DIF_P,*
-V 9200,21100,CONT_DIF_P,*
-V 9200,20700,CONT_DIF_P,*
-V 10400,20700,CONT_DIF_P,*
-V 11000,20700,CONT_DIF_P,*
-V 9800,20700,CONT_DIF_P,*
-V 11000,20300,CONT_DIF_P,*
-V 9800,20300,CONT_DIF_P,*
-V 10400,20300,CONT_DIF_P,*
-V 9200,20300,CONT_DIF_P,*
-V 11000,19900,CONT_VIA,*
-V 9800,19900,CONT_VIA,*
-V 10400,19900,CONT_DIF_P,*
-V 9200,19900,CONT_DIF_P,*
-V 11000,16300,CONT_VIA,*
-V 11000,17500,CONT_VIA,*
-V 11000,18700,CONT_VIA,*
-V 9800,16300,CONT_VIA,*
-V 9800,18700,CONT_VIA,*
-V 9800,17500,CONT_VIA,*
-V 11000,15100,CONT_VIA,*
-V 9800,15100,CONT_VIA,*
-V 10400,16700,CONT_DIF_P,*
-V 11000,16700,CONT_DIF_P,*
-V 11000,17100,CONT_DIF_P,*
-V 11000,15900,CONT_DIF_P,*
-V 10400,15900,CONT_DIF_P,*
-V 10400,16300,CONT_DIF_P,*
-V 11000,18300,CONT_DIF_P,*
-V 11000,17900,CONT_DIF_P,*
-V 10400,17900,CONT_DIF_P,*
-V 10400,17100,CONT_DIF_P,*
-V 10400,17500,CONT_DIF_P,*
-V 10400,19500,CONT_DIF_P,*
-V 11000,19100,CONT_DIF_P,*
-V 10400,19100,CONT_DIF_P,*
-V 10400,18700,CONT_DIF_P,*
-V 10400,18300,CONT_DIF_P,*
-V 11000,19500,CONT_DIF_P,*
-V 11000,15500,CONT_DIF_P,*
-V 10400,15500,CONT_DIF_P,*
-V 9800,17100,CONT_DIF_P,*
-V 9800,16700,CONT_DIF_P,*
-V 9200,16700,CONT_DIF_P,*
-V 9200,17100,CONT_DIF_P,*
-V 9200,17500,CONT_DIF_P,*
-V 9800,15900,CONT_DIF_P,*
-V 9200,15900,CONT_DIF_P,*
-V 9200,16300,CONT_DIF_P,*
-V 9800,19500,CONT_DIF_P,*
-V 9800,19100,CONT_DIF_P,*
-V 9200,19100,CONT_DIF_P,*
-V 9200,18700,CONT_DIF_P,*
-V 9800,18300,CONT_DIF_P,*
-V 9200,18300,CONT_DIF_P,*
-V 9800,17900,CONT_DIF_P,*
-V 9200,17900,CONT_DIF_P,*
-V 9200,19500,CONT_DIF_P,*
-V 9200,15500,CONT_DIF_P,*
-V 9800,15500,CONT_DIF_P,*
-V 10400,15100,CONT_DIF_P,*
-V 11000,14700,CONT_DIF_P,*
-V 10400,14700,CONT_DIF_P,*
-V 11000,14300,CONT_DIF_P,*
-V 10400,14300,CONT_DIF_P,*
-V 9200,14300,CONT_DIF_P,*
-V 9200,15100,CONT_DIF_P,*
-V 9800,14700,CONT_DIF_P,*
-V 9200,14700,CONT_DIF_P,*
-V 9800,14300,CONT_DIF_P,*
-V 10400,27400,CONT_DIF_N,*
-V 10400,27000,CONT_DIF_N,*
-V 10400,26600,CONT_DIF_N,*
-V 10400,27800,CONT_DIF_N,*
-V 10400,25000,CONT_DIF_N,*
-V 10400,25400,CONT_DIF_N,*
-V 10400,26200,CONT_DIF_N,*
-V 10400,25800,CONT_DIF_N,*
-V 9200,27000,CONT_DIF_N,*
-V 9200,26600,CONT_DIF_N,*
-V 9200,26200,CONT_DIF_N,*
-V 9200,25800,CONT_DIF_N,*
-V 9200,25400,CONT_DIF_N,*
-V 9200,27800,CONT_DIF_N,*
-V 9200,27400,CONT_DIF_N,*
-V 9200,25000,CONT_DIF_N,*
-V 9700,13600,CONT_VIA,*
-V 10400,13100,CONT_POLY,*
-V 10800,13600,CONT_BODY_N,*
-V 9400,13600,CONT_BODY_N,*
-V 10000,13600,CONT_BODY_N,*
-V 8900,13600,CONT_BODY_N,*
-V 9800,28700,CONT_BODY_P,*
-V 11000,28700,CONT_BODY_P,*
-V 9800,26100,CONT_VIA,*
-V 9800,27700,CONT_VIA,*
-V 9800,25700,CONT_DIF_N,*
-V 9800,28100,CONT_DIF_N,*
-V 9800,26500,CONT_DIF_N,*
-V 9800,27300,CONT_DIF_N,*
-V 9800,26900,CONT_DIF_N,*
-V 9800,25300,CONT_DIF_N,*
-V 9800,24900,CONT_VIA,*
-V 11000,28100,CONT_VIA,*
-V 11000,24900,CONT_VIA,*
-V 11000,26500,CONT_VIA,*
-V 11000,25300,CONT_DIF_N,*
-V 11000,26900,CONT_DIF_N,*
-V 11000,27300,CONT_DIF_N,*
-V 11000,25700,CONT_DIF_N,*
-V 11000,26100,CONT_DIF_N,*
-V 11000,27700,CONT_DIF_N,*
-V 11600,21900,CONT_DIF_P,*
-V 12200,21900,CONT_DIF_P,*
-V 12800,21900,CONT_DIF_P,*
-V 13400,21900,CONT_DIF_P,*
-V 12200,22500,CONT_BODY_N,*
-V 13400,22500,CONT_BODY_N,*
-V 13300,23200,CONT_VIA,*
-V 12200,23800,CONT_VIA,*
-V 13300,23800,CONT_POLY,*
-V 13400,24300,CONT_BODY_P,*
-V 12200,24300,CONT_BODY_P,*
-V 13400,21500,CONT_DIF_P,*
-V 12800,21500,CONT_DIF_P,*
-V 12200,21500,CONT_DIF_P,*
-V 11600,21500,CONT_DIF_P,*
-V 12200,21100,CONT_VIA,*
-V 13400,21100,CONT_VIA,*
-V 12800,21100,CONT_DIF_P,*
-V 11600,21100,CONT_DIF_P,*
-V 11600,20700,CONT_DIF_P,*
-V 12800,20700,CONT_DIF_P,*
-V 13400,20700,CONT_DIF_P,*
-V 12200,20700,CONT_DIF_P,*
-V 13400,20300,CONT_DIF_P,*
-V 12200,20300,CONT_DIF_P,*
-V 12800,20300,CONT_DIF_P,*
-V 11600,20300,CONT_DIF_P,*
-V 13400,19900,CONT_VIA,*
-V 12200,19900,CONT_VIA,*
-V 12800,19900,CONT_DIF_P,*
-V 11600,19900,CONT_DIF_P,*
-V 13400,16300,CONT_VIA,*
-V 13400,17500,CONT_VIA,*
-V 13400,18700,CONT_VIA,*
-V 12200,16300,CONT_VIA,*
-V 12200,18700,CONT_VIA,*
-V 12200,17500,CONT_VIA,*
-V 13400,15100,CONT_VIA,*
-V 12200,15100,CONT_VIA,*
-V 12800,16700,CONT_DIF_P,*
-V 13400,16700,CONT_DIF_P,*
-V 13400,17100,CONT_DIF_P,*
-V 13400,15900,CONT_DIF_P,*
-V 12800,15900,CONT_DIF_P,*
-V 12800,16300,CONT_DIF_P,*
-V 13400,18300,CONT_DIF_P,*
-V 13400,17900,CONT_DIF_P,*
-V 12800,17900,CONT_DIF_P,*
-V 12800,17100,CONT_DIF_P,*
-V 12800,17500,CONT_DIF_P,*
-V 12800,19500,CONT_DIF_P,*
-V 13400,19100,CONT_DIF_P,*
-V 12800,19100,CONT_DIF_P,*
-V 12800,18700,CONT_DIF_P,*
-V 12800,18300,CONT_DIF_P,*
-V 13400,19500,CONT_DIF_P,*
-V 13400,15500,CONT_DIF_P,*
-V 12800,15500,CONT_DIF_P,*
-V 12200,17100,CONT_DIF_P,*
-V 12200,16700,CONT_DIF_P,*
-V 11600,16700,CONT_DIF_P,*
-V 11600,17100,CONT_DIF_P,*
-V 11600,17500,CONT_DIF_P,*
-V 12200,15900,CONT_DIF_P,*
-V 11600,15900,CONT_DIF_P,*
-V 11600,16300,CONT_DIF_P,*
-V 12200,19500,CONT_DIF_P,*
-V 12200,19100,CONT_DIF_P,*
-V 11600,19100,CONT_DIF_P,*
-V 11600,18700,CONT_DIF_P,*
-V 12200,18300,CONT_DIF_P,*
-V 11600,18300,CONT_DIF_P,*
-V 12200,17900,CONT_DIF_P,*
-V 11600,17900,CONT_DIF_P,*
-V 11600,19500,CONT_DIF_P,*
-V 11600,15500,CONT_DIF_P,*
-V 12200,15500,CONT_DIF_P,*
-V 12800,15100,CONT_DIF_P,*
-V 13400,14700,CONT_DIF_P,*
-V 12800,14700,CONT_DIF_P,*
-V 13400,14300,CONT_DIF_P,*
-V 12800,14300,CONT_DIF_P,*
-V 11600,14300,CONT_DIF_P,*
-V 11600,15100,CONT_DIF_P,*
-V 12200,14700,CONT_DIF_P,*
-V 11600,14700,CONT_DIF_P,*
-V 12200,14300,CONT_DIF_P,*
-V 12800,27400,CONT_DIF_N,*
-V 12800,27000,CONT_DIF_N,*
-V 12800,26600,CONT_DIF_N,*
-V 12800,27800,CONT_DIF_N,*
-V 12800,25000,CONT_DIF_N,*
-V 12800,25400,CONT_DIF_N,*
-V 12800,26200,CONT_DIF_N,*
-V 12800,25800,CONT_DIF_N,*
-V 11600,27000,CONT_DIF_N,*
-V 11600,26600,CONT_DIF_N,*
-V 11600,26200,CONT_DIF_N,*
-V 11600,25800,CONT_DIF_N,*
-V 11600,25400,CONT_DIF_N,*
-V 11600,27800,CONT_DIF_N,*
-V 11600,27400,CONT_DIF_N,*
-V 11600,25000,CONT_DIF_N,*
-V 12100,13600,CONT_VIA,*
-V 12800,13100,CONT_POLY,*
-V 13200,13600,CONT_BODY_N,*
-V 11800,13600,CONT_BODY_N,*
-V 12400,13600,CONT_BODY_N,*
-V 11300,13600,CONT_BODY_N,*
-V 12200,28700,CONT_BODY_P,*
-V 13400,28700,CONT_BODY_P,*
-V 12200,26100,CONT_VIA,*
-V 12200,27700,CONT_VIA,*
-V 12200,25700,CONT_DIF_N,*
-V 12200,28100,CONT_DIF_N,*
-V 12200,26500,CONT_DIF_N,*
-V 12200,27300,CONT_DIF_N,*
-V 12200,26900,CONT_DIF_N,*
-V 12200,25300,CONT_DIF_N,*
-V 12200,24900,CONT_VIA,*
-V 13400,28100,CONT_VIA,*
-V 13400,24900,CONT_VIA,*
-V 13400,26500,CONT_VIA,*
-V 13400,25300,CONT_DIF_N,*
-V 13400,26900,CONT_DIF_N,*
-V 13400,27300,CONT_DIF_N,*
-V 13400,25700,CONT_DIF_N,*
-V 13400,26100,CONT_DIF_N,*
-V 13400,27700,CONT_DIF_N,*
-V 14000,21900,CONT_DIF_P,*
-V 14600,21900,CONT_DIF_P,*
-V 15200,21900,CONT_DIF_P,*
-V 15800,21900,CONT_DIF_P,*
-V 14600,22500,CONT_BODY_N,*
-V 15800,22500,CONT_BODY_N,*
-V 15700,23200,CONT_VIA,*
-V 14600,23800,CONT_VIA,*
-V 15700,23800,CONT_POLY,*
-V 15800,24300,CONT_BODY_P,*
-V 14600,24300,CONT_BODY_P,*
-V 15800,21500,CONT_DIF_P,*
-V 15200,21500,CONT_DIF_P,*
-V 14600,21500,CONT_DIF_P,*
-V 14000,21500,CONT_DIF_P,*
-V 14600,21100,CONT_VIA,*
-V 15200,21100,CONT_DIF_P,*
-V 14000,21100,CONT_DIF_P,*
-V 14000,20700,CONT_DIF_P,*
-V 15200,20700,CONT_DIF_P,*
-V 15800,20700,CONT_DIF_P,*
-V 14600,20700,CONT_DIF_P,*
-V 15800,20300,CONT_DIF_P,*
-V 14600,20300,CONT_DIF_P,*
-V 15200,20300,CONT_DIF_P,*
-V 14000,20300,CONT_DIF_P,*
-V 14600,19900,CONT_VIA,*
-V 15200,19900,CONT_DIF_P,*
-V 14000,19900,CONT_DIF_P,*
-V 14600,16300,CONT_VIA,*
-V 14600,18700,CONT_VIA,*
-V 14600,17500,CONT_VIA,*
-V 14600,15100,CONT_VIA,*
-V 15200,16700,CONT_DIF_P,*
-V 15800,16700,CONT_DIF_P,*
-V 15800,17100,CONT_DIF_P,*
-V 15800,15900,CONT_DIF_P,*
-V 15200,15900,CONT_DIF_P,*
-V 15200,16300,CONT_DIF_P,*
-V 15800,18300,CONT_DIF_P,*
-V 15800,17900,CONT_DIF_P,*
-V 15200,17900,CONT_DIF_P,*
-V 15200,17100,CONT_DIF_P,*
-V 15200,17500,CONT_DIF_P,*
-V 15200,19500,CONT_DIF_P,*
-V 15800,19100,CONT_DIF_P,*
-V 15200,19100,CONT_DIF_P,*
-V 15200,18700,CONT_DIF_P,*
-V 15200,18300,CONT_DIF_P,*
-V 15800,19500,CONT_DIF_P,*
-V 15800,15500,CONT_DIF_P,*
-V 15200,15500,CONT_DIF_P,*
-V 14600,17100,CONT_DIF_P,*
-V 14600,16700,CONT_DIF_P,*
-V 14000,16700,CONT_DIF_P,*
-V 14000,17100,CONT_DIF_P,*
-V 14000,17500,CONT_DIF_P,*
-V 14600,15900,CONT_DIF_P,*
-V 14000,15900,CONT_DIF_P,*
-V 14000,16300,CONT_DIF_P,*
-V 14600,19500,CONT_DIF_P,*
-V 14600,19100,CONT_DIF_P,*
-V 14000,19100,CONT_DIF_P,*
-V 14000,18700,CONT_DIF_P,*
-V 14600,18300,CONT_DIF_P,*
-V 14000,18300,CONT_DIF_P,*
-V 14600,17900,CONT_DIF_P,*
-V 14000,17900,CONT_DIF_P,*
-V 14000,19500,CONT_DIF_P,*
-V 14000,15500,CONT_DIF_P,*
-V 14600,15500,CONT_DIF_P,*
-V 15200,15100,CONT_DIF_P,*
-V 15800,14700,CONT_DIF_P,*
-V 15200,14700,CONT_DIF_P,*
-V 15800,14300,CONT_DIF_P,*
-V 15200,14300,CONT_DIF_P,*
-V 14000,14300,CONT_DIF_P,*
-V 14000,15100,CONT_DIF_P,*
-V 14600,14700,CONT_DIF_P,*
-V 14000,14700,CONT_DIF_P,*
-V 14600,14300,CONT_DIF_P,*
-V 15200,27400,CONT_DIF_N,*
-V 15200,27000,CONT_DIF_N,*
-V 15200,26600,CONT_DIF_N,*
-V 15200,27800,CONT_DIF_N,*
-V 15200,25000,CONT_DIF_N,*
-V 15200,25400,CONT_DIF_N,*
-V 15200,26200,CONT_DIF_N,*
-V 15200,25800,CONT_DIF_N,*
-V 14000,27000,CONT_DIF_N,*
-V 14000,26600,CONT_DIF_N,*
-V 14000,26200,CONT_DIF_N,*
-V 14000,25800,CONT_DIF_N,*
-V 14000,25400,CONT_DIF_N,*
-V 14000,27800,CONT_DIF_N,*
-V 14000,27400,CONT_DIF_N,*
-V 14000,25000,CONT_DIF_N,*
-V 14500,13600,CONT_VIA,*
-V 15200,13100,CONT_POLY,*
-V 15600,13600,CONT_BODY_N,*
-V 14200,13600,CONT_BODY_N,*
-V 14800,13600,CONT_BODY_N,*
-V 13700,13600,CONT_BODY_N,*
-V 14600,28700,CONT_BODY_P,*
-V 15800,28700,CONT_BODY_P,*
-V 14600,26100,CONT_VIA,*
-V 14600,27700,CONT_VIA,*
-V 14600,25700,CONT_DIF_N,*
-V 14600,28100,CONT_DIF_N,*
-V 14600,26500,CONT_DIF_N,*
-V 14600,27300,CONT_DIF_N,*
-V 14600,26900,CONT_DIF_N,*
-V 14600,25300,CONT_DIF_N,*
-V 14600,24900,CONT_VIA,*
-V 15800,28100,CONT_VIA,*
-V 15800,24900,CONT_VIA,*
-V 15800,26500,CONT_VIA,*
-V 15800,25300,CONT_DIF_N,*
-V 15800,26900,CONT_DIF_N,*
-V 15800,27300,CONT_DIF_N,*
-V 15800,25700,CONT_DIF_N,*
-V 15800,26100,CONT_DIF_N,*
-V 15800,27700,CONT_DIF_N,*
-V 16400,29200,CONT_VIA,*
-V 15800,29200,CONT_VIA,*
-V 16400,25900,CONT_VIA,*
-V 16100,24300,CONT_VIA,*
-V 16400,27900,CONT_VIA,*
-V 3700,23200,CONT_VIA,*
-V 2000,5800,CONT_VIA,*
-V 16400,3600,CONT_VIA,*
-V 16400,2400,CONT_VIA,*
-V 15200,3500,CONT_VIA,*
-V 14000,1600,CONT_VIA,*
-V 12800,1600,CONT_VIA,*
-V 11600,1600,CONT_VIA,*
-V 16400,7500,CONT_VIA,*
-V 16400,6700,CONT_VIA,*
-V 2000,3200,CONT_VIA,*
-V 2000,2300,CONT_VIA,*
-V 3200,9000,CONT_VIA,*
-V 3200,7400,CONT_VIA,*
-V 3200,6600,CONT_VIA,*
-V 3200,2300,CONT_VIA,*
-V 3200,3500,CONT_VIA,*
-V 3200,10200,CONT_VIA,*
-V 6800,1600,CONT_VIA,*
-V 4400,2300,CONT_VIA,*
-V 4400,6600,CONT_VIA,*
-V 4400,7400,CONT_VIA,*
-V 4400,9000,CONT_VIA,*
-V 4400,10200,CONT_VIA,*
-V 4400,3500,CONT_VIA,*
-V 9800,6600,CONT_VIA,*
-V 9800,10200,CONT_VIA,*
-V 6200,9000,CONT_VIA,*
-V 8000,1600,CONT_VIA,*
-V 9800,9000,CONT_VIA,*
-V 9800,7400,CONT_VIA,*
-V 9800,2300,CONT_VIA,*
-V 11000,7400,CONT_VIA,*
-V 11000,9000,CONT_VIA,*
-V 11000,10200,CONT_VIA,*
-V 7400,6600,CONT_VIA,*
-V 11000,6600,CONT_VIA,*
-V 11000,2300,CONT_VIA,*
-V 7400,7400,CONT_VIA,*
-V 7400,2300,CONT_VIA,*
-V 6200,2300,CONT_VIA,*
-V 6200,3500,CONT_VIA,*
-V 6200,10200,CONT_VIA,*
-V 8600,3500,CONT_VIA,*
-V 6200,7400,CONT_VIA,*
-V 6200,6600,CONT_VIA,*
-V 8600,7400,CONT_VIA,*
-V 8600,9000,CONT_VIA,*
-V 8600,10200,CONT_VIA,*
-V 8600,6600,CONT_VIA,*
-V 8600,2300,CONT_VIA,*
-V 7400,10200,CONT_VIA,*
-V 7400,9000,CONT_VIA,*
-V 9200,1600,CONT_VIA,*
-V 10400,1600,CONT_VIA,*
-V 2000,9900,CONT_VIA,*
-V 800,9800,CONT_VIA,*
-V 800,6600,CONT_VIA,*
-V 800,2300,CONT_VIA,*
-V 800,3500,CONT_VIA,*
-V 15700,-700,CONT_VIA,*
-V 3800,-700,CONT_VIA,*
-V 4900,-700,CONT_VIA,*
-V 9800,4600,CONT_POLY,*
-V 15100,4500,CONT_POLY,*
-V 11100,4000,CONT_POLY,*
-V 1800,9400,CONT_POLY,*
-V 15700,2300,CONT_POLY,*
-V 14500,3800,CONT_POLY,*
-V 5100,5300,CONT_POLY,*
-V 2700,8900,CONT_POLY,*
-V 3300,4500,CONT_POLY,*
-V 4900,300,CONT_POLY,*
-V 7400,4600,CONT_POLY,*
-V 16400,28300,CONT_BODY_P,*
-V 16400,28700,CONT_BODY_P,*
-V 16400,24300,CONT_BODY_P,*
-V 16400,25500,CONT_BODY_P,*
-V 16400,25100,CONT_BODY_P,*
-V 16400,24700,CONT_BODY_P,*
-V 16400,26300,CONT_BODY_P,*
-V 16400,26700,CONT_BODY_P,*
-V 16400,27100,CONT_BODY_P,*
-V 16400,27500,CONT_BODY_P,*
-V 1200,28700,CONT_BODY_P,*
-V 1200,24300,CONT_BODY_P,*
-V 800,28300,CONT_BODY_P,*
-V 800,24300,CONT_BODY_P,*
-V 800,25500,CONT_BODY_P,*
-V 800,25100,CONT_BODY_P,*
-V 800,24700,CONT_BODY_P,*
-V 800,28700,CONT_BODY_P,*
-V 800,25900,CONT_BODY_P,*
-V 800,26300,CONT_BODY_P,*
-V 800,26700,CONT_BODY_P,*
-V 800,27100,CONT_BODY_P,*
-V 800,27500,CONT_BODY_P,*
-V 800,27900,CONT_BODY_P,*
-V 16400,2800,CONT_BODY_P,*
-V 16400,3200,CONT_BODY_P,*
-V 15200,4000,CONT_BODY_P,*
-V 16400,4000,CONT_BODY_P,*
-V 16400,4000,CONT_BODY_P,*
-V 2000,4000,CONT_BODY_P,*
-V 7800,4000,CONT_BODY_P,*
-V 9000,4000,CONT_BODY_P,*
-V 8200,4000,CONT_BODY_P,*
-V 7000,4000,CONT_BODY_P,*
-V 6600,4000,CONT_BODY_P,*
-V 4400,4000,CONT_BODY_P,*
-V 3200,4000,CONT_BODY_P,*
-V 15200,1800,CONT_BODY_P,*
-V 9400,4000,CONT_BODY_P,*
-V 9900,4000,CONT_BODY_P,*
-V 10300,4000,CONT_BODY_P,*
-V 6200,4000,CONT_BODY_P,*
-V 8600,4000,CONT_BODY_P,*
-V 14700,200,CONT_BODY_P,*
-V 15200,600,CONT_BODY_P,*
-V 14700,600,CONT_BODY_P,*
-V 15200,1000,CONT_BODY_P,*
-V 14700,1000,CONT_BODY_P,*
-V 15200,1400,CONT_BODY_P,*
-V 14700,1400,CONT_BODY_P,*
-V 14700,1800,CONT_BODY_P,*
-V 15200,200,CONT_BODY_P,*
-V 800,700,CONT_BODY_P,*
-V 800,1100,CONT_BODY_P,*
-V 800,1500,CONT_BODY_P,*
-V 800,1900,CONT_BODY_P,*
-V 800,2700,CONT_BODY_P,*
-V 800,3100,CONT_BODY_P,*
-V 800,4000,CONT_BODY_P,*
-V 800,300,CONT_BODY_P,*
-V 2800,-200,CONT_BODY_P,*
-V 2400,-200,CONT_BODY_P,*
-V 1600,-200,CONT_BODY_P,*
-V 15200,-200,CONT_BODY_P,*
-V 11600,-200,CONT_BODY_P,*
-V 5400,-200,CONT_BODY_P,*
-V 5800,-200,CONT_BODY_P,*
-V 6600,-200,CONT_BODY_P,*
-V 7000,-200,CONT_BODY_P,*
-V 7800,-200,CONT_BODY_P,*
-V 8200,-200,CONT_BODY_P,*
-V 9400,-200,CONT_BODY_P,*
-V 9000,-200,CONT_BODY_P,*
-V 10200,-200,CONT_BODY_P,*
-V 10600,-200,CONT_BODY_P,*
-V 14000,-200,CONT_BODY_P,*
-V 13600,-200,CONT_BODY_P,*
-V 14400,-200,CONT_BODY_P,*
-V 14800,-200,CONT_BODY_P,*
-V 12800,-200,CONT_BODY_P,*
-V 13200,-200,CONT_BODY_P,*
-V 1200,-200,CONT_BODY_P,*
-V 12400,-200,CONT_BODY_P,*
-V 12000,-200,CONT_BODY_P,*
-V 8600,-200,CONT_BODY_P,*
-V 11000,-200,CONT_BODY_P,*
-V 9800,-200,CONT_BODY_P,*
-V 4400,-200,CONT_BODY_P,*
-V 3200,-200,CONT_BODY_P,*
-V 2000,-200,CONT_BODY_P,*
-V 6200,-200,CONT_BODY_P,*
-V 7400,-200,CONT_BODY_P,*
-V 800,-200,CONT_BODY_P,*
-V 1400,22500,CONT_BODY_N,*
-V 16400,22000,CONT_BODY_N,*
-V 16400,22500,CONT_BODY_N,*
-V 16400,20400,CONT_BODY_N,*
-V 16400,20800,CONT_BODY_N,*
-V 16400,20000,CONT_BODY_N,*
-V 16400,21200,CONT_BODY_N,*
-V 16400,21600,CONT_BODY_N,*
-V 800,21200,CONT_BODY_N,*
-V 800,20800,CONT_BODY_N,*
-V 800,20400,CONT_BODY_N,*
-V 800,20000,CONT_BODY_N,*
-V 800,22500,CONT_BODY_N,*
-V 800,22000,CONT_BODY_N,*
-V 800,21600,CONT_BODY_N,*
-V 16400,10400,CONT_BODY_N,*
-V 16400,5100,CONT_BODY_N,*
-V 15200,5100,CONT_BODY_N,*
-V 11000,12000,CONT_BODY_N,*
-V 2100,12000,CONT_BODY_N,*
-V 16400,7100,CONT_BODY_N,*
-V 16400,11200,CONT_BODY_N,*
-V 16400,6300,CONT_BODY_N,*
-V 16400,5900,CONT_BODY_N,*
-V 16400,12000,CONT_BODY_N,*
-V 16400,9500,CONT_BODY_N,*
-V 16400,11600,CONT_BODY_N,*
-V 16400,7900,CONT_BODY_N,*
-V 8200,5100,CONT_BODY_N,*
-V 7800,5100,CONT_BODY_N,*
-V 10200,5100,CONT_BODY_N,*
-V 10600,5100,CONT_BODY_N,*
-V 16400,5500,CONT_BODY_N,*
-V 16400,9100,CONT_BODY_N,*
-V 16400,8300,CONT_BODY_N,*
-V 16400,10800,CONT_BODY_N,*
-V 4000,12000,CONT_BODY_N,*
-V 3600,12000,CONT_BODY_N,*
-V 8600,12000,CONT_BODY_N,*
-V 9800,12000,CONT_BODY_N,*
-V 5800,12000,CONT_BODY_N,*
-V 5300,12000,CONT_BODY_N,*
-V 4400,12000,CONT_BODY_N,*
-V 7000,5100,CONT_BODY_N,*
-V 6600,5100,CONT_BODY_N,*
-V 7400,12000,CONT_BODY_N,*
-V 11000,5100,CONT_BODY_N,*
-V 9400,5100,CONT_BODY_N,*
-V 9000,5100,CONT_BODY_N,*
-V 4400,5100,CONT_BODY_N,*
-V 4800,12000,CONT_BODY_N,*
-V 3200,5100,CONT_BODY_N,*
-V 6300,12000,CONT_BODY_N,*
-V 6200,5100,CONT_BODY_N,*
-V 8600,5100,CONT_BODY_N,*
-V 1200,12000,CONT_BODY_N,*
-V 1700,12000,CONT_BODY_N,*
-V 3200,12000,CONT_BODY_N,*
-V 16000,13600,CONT_BODY_N,*
-V 1300,13600,CONT_BODY_N,*
-V 16400,14400,CONT_BODY_N,*
-V 16400,14800,CONT_BODY_N,*
-V 16400,15200,CONT_BODY_N,*
-V 16400,13600,CONT_BODY_N,*
-V 16400,15600,CONT_BODY_N,*
-V 16400,17200,CONT_BODY_N,*
-V 16400,16800,CONT_BODY_N,*
-V 16400,16000,CONT_BODY_N,*
-V 16400,18400,CONT_BODY_N,*
-V 16400,18800,CONT_BODY_N,*
-V 16400,19200,CONT_BODY_N,*
-V 16400,19600,CONT_BODY_N,*
-V 16400,17600,CONT_BODY_N,*
-V 16400,18000,CONT_BODY_N,*
-V 16400,16400,CONT_BODY_N,*
-V 16400,14000,CONT_BODY_N,*
-V 2000,5100,CONT_BODY_N,*
-V 1400,5100,CONT_BODY_N,*
-V 1400,5500,CONT_BODY_N,*
-V 1400,5900,CONT_BODY_N,*
-V 1400,6300,CONT_BODY_N,*
-V 2000,10300,CONT_BODY_N,*
-V 2000,10700,CONT_BODY_N,*
-V 11700,5100,CONT_BODY_N,*
-V 16000,11600,CONT_BODY_N,*
-V 16000,10400,CONT_BODY_N,*
-V 16000,8300,CONT_BODY_N,*
-V 16000,10800,CONT_BODY_N,*
-V 16000,11200,CONT_BODY_N,*
-V 16000,12000,CONT_BODY_N,*
-V 16000,9500,CONT_BODY_N,*
-V 16000,9100,CONT_BODY_N,*
-V 15600,11200,CONT_BODY_N,*
-V 15600,10800,CONT_BODY_N,*
-V 15600,8300,CONT_BODY_N,*
-V 15600,10400,CONT_BODY_N,*
-V 15600,11600,CONT_BODY_N,*
-V 15600,9100,CONT_BODY_N,*
-V 15600,9500,CONT_BODY_N,*
-V 15600,12000,CONT_BODY_N,*
-V 15200,9100,CONT_BODY_N,*
-V 15200,11600,CONT_BODY_N,*
-V 15200,10400,CONT_BODY_N,*
-V 15200,8300,CONT_BODY_N,*
-V 15200,10800,CONT_BODY_N,*
-V 15200,11200,CONT_BODY_N,*
-V 15200,12000,CONT_BODY_N,*
-V 15200,9500,CONT_BODY_N,*
-V 14800,12000,CONT_BODY_N,*
-V 14800,11200,CONT_BODY_N,*
-V 14800,10800,CONT_BODY_N,*
-V 14800,8300,CONT_BODY_N,*
-V 14800,10400,CONT_BODY_N,*
-V 14800,11600,CONT_BODY_N,*
-V 14800,9100,CONT_BODY_N,*
-V 14800,9500,CONT_BODY_N,*
-V 800,10800,CONT_BODY_N,*
-V 800,10400,CONT_BODY_N,*
-V 800,5100,CONT_BODY_N,*
-V 800,7400,CONT_BODY_N,*
-V 800,7800,CONT_BODY_N,*
-V 800,8200,CONT_BODY_N,*
-V 800,8600,CONT_BODY_N,*
-V 800,9000,CONT_BODY_N,*
-V 800,12000,CONT_BODY_N,*
-V 800,11600,CONT_BODY_N,*
-V 800,11200,CONT_BODY_N,*
-V 800,19600,CONT_BODY_N,*
-V 800,19200,CONT_BODY_N,*
-V 800,18800,CONT_BODY_N,*
-V 800,9400,CONT_BODY_N,*
-V 800,5500,CONT_BODY_N,*
-V 800,5900,CONT_BODY_N,*
-V 800,6300,CONT_BODY_N,*
-V 800,7000,CONT_BODY_N,*
-V 800,13600,CONT_BODY_N,*
-V 800,16800,CONT_BODY_N,*
-V 800,17200,CONT_BODY_N,*
-V 800,16400,CONT_BODY_N,*
-V 800,16000,CONT_BODY_N,*
-V 800,18000,CONT_BODY_N,*
-V 800,17600,CONT_BODY_N,*
-V 800,18400,CONT_BODY_N,*
-V 800,15600,CONT_BODY_N,*
-V 800,15200,CONT_BODY_N,*
-V 800,14800,CONT_BODY_N,*
-V 800,14400,CONT_BODY_N,*
-V 800,14000,CONT_BODY_N,*
-V 1400,20300,CONT_DIF_P,*
-V 1400,20700,CONT_DIF_P,*
-V 1400,21100,CONT_DIF_P,*
-V 1400,21500,CONT_DIF_P,*
-V 1400,21900,CONT_DIF_P,*
-V 12200,6600,CONT_DIF_P,*
-V 13400,6600,CONT_DIF_P,*
-V 14000,5800,CONT_DIF_P,*
-V 1400,6900,CONT_DIF_P,*
-V 1400,11300,CONT_DIF_P,*
-V 15200,7500,CONT_DIF_P,*
-V 15800,7500,CONT_DIF_P,*
-V 14600,7500,CONT_DIF_P,*
-V 14000,8200,CONT_DIF_P,*
-V 13400,10200,CONT_DIF_P,*
-V 12200,10200,CONT_DIF_P,*
-V 12200,9000,CONT_DIF_P,*
-V 13400,9000,CONT_DIF_P,*
-V 12200,7400,CONT_DIF_P,*
-V 13400,7400,CONT_DIF_P,*
-V 14000,7400,CONT_DIF_P,*
-V 14000,6200,CONT_DIF_P,*
-V 14000,9400,CONT_DIF_P,*
-V 14000,9800,CONT_DIF_P,*
-V 14000,6600,CONT_DIF_P,*
-V 14000,7000,CONT_DIF_P,*
-V 14000,10600,CONT_DIF_P,*
-V 14000,11000,CONT_DIF_P,*
-V 12800,11000,CONT_DIF_P,*
-V 12800,7800,CONT_DIF_P,*
-V 12800,8200,CONT_DIF_P,*
-V 14000,10200,CONT_DIF_P,*
-V 14000,7800,CONT_DIF_P,*
-V 14000,9000,CONT_DIF_P,*
-V 14000,8600,CONT_DIF_P,*
-V 14000,11400,CONT_DIF_P,*
-V 12800,11400,CONT_DIF_P,*
-V 13400,7800,CONT_DIF_P,*
-V 13400,8200,CONT_DIF_P,*
-V 13400,11400,CONT_DIF_P,*
-V 12800,8600,CONT_DIF_P,*
-V 11600,10600,CONT_DIF_P,*
-V 12800,9400,CONT_DIF_P,*
-V 12800,9800,CONT_DIF_P,*
-V 12800,10600,CONT_DIF_P,*
-V 13400,6200,CONT_DIF_P,*
-V 13400,5800,CONT_DIF_P,*
-V 13400,7000,CONT_DIF_P,*
-V 12800,10200,CONT_DIF_P,*
-V 11600,9400,CONT_DIF_P,*
-V 12800,9000,CONT_DIF_P,*
-V 13400,10600,CONT_DIF_P,*
-V 13400,11000,CONT_DIF_P,*
-V 11600,8600,CONT_DIF_P,*
-V 11600,8200,CONT_DIF_P,*
-V 11600,5800,CONT_DIF_P,*
-V 11600,11000,CONT_DIF_P,*
-V 12200,11000,CONT_DIF_P,*
-V 13400,9800,CONT_DIF_P,*
-V 13400,9400,CONT_DIF_P,*
-V 13400,8600,CONT_DIF_P,*
-V 11600,10200,CONT_DIF_P,*
-V 11600,7000,CONT_DIF_P,*
-V 11600,6600,CONT_DIF_P,*
-V 11600,9800,CONT_DIF_P,*
-V 12200,9800,CONT_DIF_P,*
-V 11600,6200,CONT_DIF_P,*
-V 11600,7400,CONT_DIF_P,*
-V 11600,11400,CONT_DIF_P,*
-V 12200,6200,CONT_DIF_P,*
-V 12200,8600,CONT_DIF_P,*
-V 12200,11400,CONT_DIF_P,*
-V 12200,8200,CONT_DIF_P,*
-V 12200,7800,CONT_DIF_P,*
-V 12200,10600,CONT_DIF_P,*
-V 11600,9000,CONT_DIF_P,*
-V 11600,7800,CONT_DIF_P,*
-V 2600,6600,CONT_DIF_P,*
-V 2600,6200,CONT_DIF_P,*
-V 2600,7400,CONT_DIF_P,*
-V 2600,7000,CONT_DIF_P,*
-V 3200,9400,CONT_DIF_P,*
-V 12200,9400,CONT_DIF_P,*
-V 12200,7000,CONT_DIF_P,*
-V 12200,5800,CONT_DIF_P,*
-V 3200,8200,CONT_DIF_P,*
-V 3200,7800,CONT_DIF_P,*
-V 3200,11000,CONT_DIF_P,*
-V 3200,9800,CONT_DIF_P,*
-V 3800,5800,CONT_DIF_P,*
-V 2600,5800,CONT_DIF_P,*
-V 2600,8200,CONT_DIF_P,*
-V 2600,7800,CONT_DIF_P,*
-V 3800,9800,CONT_DIF_P,*
-V 3200,5800,CONT_DIF_P,*
-V 3200,7000,CONT_DIF_P,*
-V 3200,6200,CONT_DIF_P,*
-V 3800,8600,CONT_DIF_P,*
-V 3200,10600,CONT_DIF_P,*
-V 3200,8600,CONT_DIF_P,*
-V 3200,11400,CONT_DIF_P,*
-V 3800,10600,CONT_DIF_P,*
-V 3800,6600,CONT_DIF_P,*
-V 3800,11000,CONT_DIF_P,*
-V 3800,8200,CONT_DIF_P,*
-V 4400,7800,CONT_DIF_P,*
-V 3800,10200,CONT_DIF_P,*
-V 3800,7000,CONT_DIF_P,*
-V 3800,9400,CONT_DIF_P,*
-V 4400,8600,CONT_DIF_P,*
-V 4400,10600,CONT_DIF_P,*
-V 4400,9400,CONT_DIF_P,*
-V 3800,7800,CONT_DIF_P,*
-V 3800,9000,CONT_DIF_P,*
-V 3800,11400,CONT_DIF_P,*
-V 3800,7400,CONT_DIF_P,*
-V 3800,6200,CONT_DIF_P,*
-V 5000,9400,CONT_DIF_P,*
-V 4400,6200,CONT_DIF_P,*
-V 4400,7000,CONT_DIF_P,*
-V 4400,5800,CONT_DIF_P,*
-V 4400,9800,CONT_DIF_P,*
-V 4400,11000,CONT_DIF_P,*
-V 4400,8200,CONT_DIF_P,*
-V 4400,11400,CONT_DIF_P,*
-V 10400,11000,CONT_DIF_P,*
-V 5000,5800,CONT_DIF_P,*
-V 5000,8200,CONT_DIF_P,*
-V 5000,11000,CONT_DIF_P,*
-V 5000,6600,CONT_DIF_P,*
-V 5000,10600,CONT_DIF_P,*
-V 5000,9800,CONT_DIF_P,*
-V 5000,10200,CONT_DIF_P,*
-V 10400,8200,CONT_DIF_P,*
-V 5000,6200,CONT_DIF_P,*
-V 5000,7400,CONT_DIF_P,*
-V 5000,11400,CONT_DIF_P,*
-V 5000,8600,CONT_DIF_P,*
-V 5000,9000,CONT_DIF_P,*
-V 5000,7800,CONT_DIF_P,*
-V 5000,7000,CONT_DIF_P,*
-V 10400,9800,CONT_DIF_P,*
-V 10400,9400,CONT_DIF_P,*
-V 10400,6200,CONT_DIF_P,*
-V 10400,7400,CONT_DIF_P,*
-V 10400,11400,CONT_DIF_P,*
-V 10400,8600,CONT_DIF_P,*
-V 9200,8600,CONT_DIF_P,*
-V 10400,7000,CONT_DIF_P,*
-V 9200,5800,CONT_DIF_P,*
-V 9200,11000,CONT_DIF_P,*
-V 9200,10600,CONT_DIF_P,*
-V 10400,9000,CONT_DIF_P,*
-V 10400,7800,CONT_DIF_P,*
-V 10400,10200,CONT_DIF_P,*
-V 9200,10200,CONT_DIF_P,*
-V 10400,10600,CONT_DIF_P,*
-V 9200,6600,CONT_DIF_P,*
-V 9200,9800,CONT_DIF_P,*
-V 9200,9400,CONT_DIF_P,*
-V 9200,6200,CONT_DIF_P,*
-V 9200,7400,CONT_DIF_P,*
-V 9200,11400,CONT_DIF_P,*
-V 11000,5800,CONT_DIF_P,*
-V 10400,5800,CONT_DIF_P,*
-V 11000,9800,CONT_DIF_P,*
-V 11000,10600,CONT_DIF_P,*
-V 11000,11000,CONT_DIF_P,*
-V 11000,7800,CONT_DIF_P,*
-V 9200,9000,CONT_DIF_P,*
-V 9200,7800,CONT_DIF_P,*
-V 9800,7800,CONT_DIF_P,*
-V 10400,6600,CONT_DIF_P,*
-V 9800,10600,CONT_DIF_P,*
-V 11000,9400,CONT_DIF_P,*
-V 11000,8200,CONT_DIF_P,*
-V 11000,11400,CONT_DIF_P,*
-V 11000,8600,CONT_DIF_P,*
-V 11000,6200,CONT_DIF_P,*
-V 9800,9800,CONT_DIF_P,*
-V 9200,8200,CONT_DIF_P,*
-V 9800,7000,CONT_DIF_P,*
-V 9800,5800,CONT_DIF_P,*
-V 9800,6200,CONT_DIF_P,*
-V 9800,8600,CONT_DIF_P,*
-V 9800,11400,CONT_DIF_P,*
-V 9800,8200,CONT_DIF_P,*
-V 5600,6200,CONT_DIF_P,*
-V 9200,7000,CONT_DIF_P,*
-V 5600,11400,CONT_DIF_P,*
-V 5600,8600,CONT_DIF_P,*
-V 5600,8200,CONT_DIF_P,*
-V 5600,5800,CONT_DIF_P,*
-V 9800,11000,CONT_DIF_P,*
-V 9800,9400,CONT_DIF_P,*
-V 5600,9000,CONT_DIF_P,*
-V 11000,7000,CONT_DIF_P,*
-V 5600,7800,CONT_DIF_P,*
-V 5600,7000,CONT_DIF_P,*
-V 5600,6600,CONT_DIF_P,*
-V 5600,9800,CONT_DIF_P,*
-V 5600,9400,CONT_DIF_P,*
-V 5600,10600,CONT_DIF_P,*
-V 6200,8600,CONT_DIF_P,*
-V 5600,7400,CONT_DIF_P,*
-V 6200,8200,CONT_DIF_P,*
-V 6200,7800,CONT_DIF_P,*
-V 6200,11000,CONT_DIF_P,*
-V 6200,9800,CONT_DIF_P,*
-V 6200,9400,CONT_DIF_P,*
-V 5600,11000,CONT_DIF_P,*
-V 6200,7000,CONT_DIF_P,*
-V 5600,10200,CONT_DIF_P,*
-V 7400,9400,CONT_DIF_P,*
-V 7400,9800,CONT_DIF_P,*
-V 7400,7000,CONT_DIF_P,*
-V 7400,5800,CONT_DIF_P,*
-V 7400,6200,CONT_DIF_P,*
-V 6200,10600,CONT_DIF_P,*
-V 7400,11400,CONT_DIF_P,*
-V 6200,11400,CONT_DIF_P,*
-V 7400,7800,CONT_DIF_P,*
-V 7400,11000,CONT_DIF_P,*
-V 7400,10600,CONT_DIF_P,*
-V 8600,9400,CONT_DIF_P,*
-V 8600,8200,CONT_DIF_P,*
-V 6200,5800,CONT_DIF_P,*
-V 8600,8600,CONT_DIF_P,*
-V 6200,6200,CONT_DIF_P,*
-V 8600,5800,CONT_DIF_P,*
-V 8600,7000,CONT_DIF_P,*
-V 8600,9800,CONT_DIF_P,*
-V 8600,10600,CONT_DIF_P,*
-V 8600,11000,CONT_DIF_P,*
-V 7400,8600,CONT_DIF_P,*
-V 6800,9000,CONT_DIF_P,*
-V 7400,8200,CONT_DIF_P,*
-V 6800,10200,CONT_DIF_P,*
-V 6800,7000,CONT_DIF_P,*
-V 6800,6600,CONT_DIF_P,*
-V 6800,9800,CONT_DIF_P,*
-V 6800,9400,CONT_DIF_P,*
-V 8600,11400,CONT_DIF_P,*
-V 6800,7400,CONT_DIF_P,*
-V 8600,6200,CONT_DIF_P,*
-V 6800,8600,CONT_DIF_P,*
-V 6800,8200,CONT_DIF_P,*
-V 6800,5800,CONT_DIF_P,*
-V 6800,11000,CONT_DIF_P,*
-V 6800,10600,CONT_DIF_P,*
-V 8600,7800,CONT_DIF_P,*
-V 8000,7800,CONT_DIF_P,*
-V 6800,7800,CONT_DIF_P,*
-V 8000,7000,CONT_DIF_P,*
-V 8000,6600,CONT_DIF_P,*
-V 8000,9800,CONT_DIF_P,*
-V 8000,9400,CONT_DIF_P,*
-V 8000,6200,CONT_DIF_P,*
-V 6800,6200,CONT_DIF_P,*
-V 8000,7400,CONT_DIF_P,*
-V 6800,11400,CONT_DIF_P,*
-V 8000,11400,CONT_DIF_P,*
-V 8000,8600,CONT_DIF_P,*
-V 8000,8200,CONT_DIF_P,*
-V 8000,5800,CONT_DIF_P,*
-V 8000,11000,CONT_DIF_P,*
-V 8000,10600,CONT_DIF_P,*
-V 8000,9000,CONT_DIF_P,*
-V 8000,10200,CONT_DIF_P,*
-V 1400,14300,CONT_DIF_P,*
-V 1400,19900,CONT_DIF_P,*
-V 1400,19500,CONT_DIF_P,*
-V 1400,19100,CONT_DIF_P,*
-V 1400,18700,CONT_DIF_P,*
-V 1400,18300,CONT_DIF_P,*
-V 1400,17500,CONT_DIF_P,*
-V 1400,17900,CONT_DIF_P,*
-V 12800,5800,CONT_DIF_P,*
-V 1400,17100,CONT_DIF_P,*
-V 1400,16700,CONT_DIF_P,*
-V 1400,16300,CONT_DIF_P,*
-V 1400,15900,CONT_DIF_P,*
-V 1400,15500,CONT_DIF_P,*
-V 1400,15100,CONT_DIF_P,*
-V 1400,14700,CONT_DIF_P,*
-V 14600,5800,CONT_DIF_P,*
-V 15800,6600,CONT_DIF_P,*
-V 15800,5800,CONT_DIF_P,*
-V 15800,6200,CONT_DIF_P,*
-V 12800,6600,CONT_DIF_P,*
-V 12800,7000,CONT_DIF_P,*
-V 12800,6200,CONT_DIF_P,*
-V 12800,7400,CONT_DIF_P,*
-V 15800,7000,CONT_DIF_P,*
-V 15200,6200,CONT_DIF_P,*
-V 15200,5800,CONT_DIF_P,*
-V 15200,6600,CONT_DIF_P,*
-V 15200,7000,CONT_DIF_P,*
-V 14600,7000,CONT_DIF_P,*
-V 14600,6600,CONT_DIF_P,*
-V 14600,6200,CONT_DIF_P,*
-V 1400,27300,CONT_DIF_N,*
-V 1400,26100,CONT_DIF_N,*
-V 1400,24900,CONT_DIF_N,*
-V 1400,25300,CONT_DIF_N,*
-V 1400,25700,CONT_DIF_N,*
-V 1400,26500,CONT_DIF_N,*
-V 1400,26900,CONT_DIF_N,*
-V 1400,27700,CONT_DIF_N,*
-V 1400,28100,CONT_DIF_N,*
-V 13400,2300,CONT_DIF_N,*
-V 12200,2300,CONT_DIF_N,*
-V 14600,3300,CONT_DIF_N,*
-V 15200,2700,CONT_DIF_N,*
-V 15200,3100,CONT_DIF_N,*
-V 13400,1900,CONT_DIF_N,*
-V 13400,700,CONT_DIF_N,*
-V 13400,1100,CONT_DIF_N,*
-V 14000,2500,CONT_DIF_N,*
-V 13400,2800,CONT_DIF_N,*
-V 12800,700,CONT_DIF_N,*
-V 12800,2500,CONT_DIF_N,*
-V 12800,2100,CONT_DIF_N,*
-V 11600,2500,CONT_DIF_N,*
-V 11600,1200,CONT_DIF_N,*
-V 12200,2800,CONT_DIF_N,*
-V 13400,1500,CONT_DIF_N,*
-V 14000,2900,CONT_DIF_N,*
-V 12800,3300,CONT_DIF_N,*
-V 12800,2900,CONT_DIF_N,*
-V 13400,3300,CONT_DIF_N,*
-V 14000,3300,CONT_DIF_N,*
-V 12200,1100,CONT_DIF_N,*
-V 12200,700,CONT_DIF_N,*
-V 12200,1900,CONT_DIF_N,*
-V 12200,3300,CONT_DIF_N,*
-V 11600,2900,CONT_DIF_N,*
-V 11600,3300,CONT_DIF_N,*
-V 11600,2100,CONT_DIF_N,*
-V 1400,900,CONT_DIF_N,*
-V 1400,2500,CONT_DIF_N,*
-V 14000,700,CONT_DIF_N,*
-V 14000,1200,CONT_DIF_N,*
-V 12800,1200,CONT_DIF_N,*
-V 11600,700,CONT_DIF_N,*
-V 14000,2100,CONT_DIF_N,*
-V 12200,1500,CONT_DIF_N,*
-V 2000,1100,CONT_DIF_N,*
-V 2000,700,CONT_DIF_N,*
-V 2600,1300,CONT_DIF_N,*
-V 2600,900,CONT_DIF_N,*
-V 6800,700,CONT_DIF_N,*
-V 6800,1200,CONT_DIF_N,*
-V 2600,1700,CONT_DIF_N,*
-V 1400,1300,CONT_DIF_N,*
-V 3200,1900,CONT_DIF_N,*
-V 3200,2700,CONT_DIF_N,*
-V 3200,3100,CONT_DIF_N,*
-V 3200,700,CONT_DIF_N,*
-V 1400,2100,CONT_DIF_N,*
-V 1400,2900,CONT_DIF_N,*
-V 1400,3300,CONT_DIF_N,*
-V 1400,1700,CONT_DIF_N,*
-V 3800,900,CONT_DIF_N,*
-V 3800,1300,CONT_DIF_N,*
-V 3800,1700,CONT_DIF_N,*
-V 3800,3300,CONT_DIF_N,*
-V 2600,2500,CONT_DIF_N,*
-V 2600,2100,CONT_DIF_N,*
-V 2600,2900,CONT_DIF_N,*
-V 2600,3300,CONT_DIF_N,*
-V 4400,700,CONT_DIF_N,*
-V 4400,3100,CONT_DIF_N,*
-V 4400,2700,CONT_DIF_N,*
-V 4400,1900,CONT_DIF_N,*
-V 2000,2700,CONT_DIF_N,*
-V 2000,1900,CONT_DIF_N,*
-V 2000,1500,CONT_DIF_N,*
-V 3800,2500,CONT_DIF_N,*
-V 5000,1700,CONT_DIF_N,*
-V 4400,1500,CONT_DIF_N,*
-V 4400,1100,CONT_DIF_N,*
-V 3800,2100,CONT_DIF_N,*
-V 3800,2900,CONT_DIF_N,*
-V 3200,1100,CONT_DIF_N,*
-V 3200,1500,CONT_DIF_N,*
-V 8000,1200,CONT_DIF_N,*
-V 10400,2500,CONT_DIF_N,*
-V 10400,1200,CONT_DIF_N,*
-V 5000,1300,CONT_DIF_N,*
-V 5000,900,CONT_DIF_N,*
-V 5000,2500,CONT_DIF_N,*
-V 5000,2100,CONT_DIF_N,*
-V 5000,2900,CONT_DIF_N,*
-V 5000,3300,CONT_DIF_N,*
-V 9800,3300,CONT_DIF_N,*
-V 11000,1500,CONT_DIF_N,*
-V 9200,2900,CONT_DIF_N,*
-V 9200,3300,CONT_DIF_N,*
-V 9200,2100,CONT_DIF_N,*
-V 9800,2800,CONT_DIF_N,*
-V 10400,3300,CONT_DIF_N,*
-V 10400,2100,CONT_DIF_N,*
-V 9200,1200,CONT_DIF_N,*
-V 10400,2900,CONT_DIF_N,*
-V 9800,1100,CONT_DIF_N,*
-V 9800,700,CONT_DIF_N,*
-V 9800,1900,CONT_DIF_N,*
-V 11000,1900,CONT_DIF_N,*
-V 10400,700,CONT_DIF_N,*
-V 9200,700,CONT_DIF_N,*
-V 11000,700,CONT_DIF_N,*
-V 5600,2100,CONT_DIF_N,*
-V 5600,1700,CONT_DIF_N,*
-V 5600,1300,CONT_DIF_N,*
-V 5600,900,CONT_DIF_N,*
-V 5600,2900,CONT_DIF_N,*
-V 9200,2500,CONT_DIF_N,*
-V 8000,700,CONT_DIF_N,*
-V 9800,1500,CONT_DIF_N,*
-V 6200,1100,CONT_DIF_N,*
-V 6200,1500,CONT_DIF_N,*
-V 6200,1900,CONT_DIF_N,*
-V 6200,2700,CONT_DIF_N,*
-V 6200,3100,CONT_DIF_N,*
-V 11000,2700,CONT_DIF_N,*
-V 11000,3100,CONT_DIF_N,*
-V 5600,2500,CONT_DIF_N,*
-V 7400,1900,CONT_DIF_N,*
-V 8600,1900,CONT_DIF_N,*
-V 8600,2700,CONT_DIF_N,*
-V 8600,3100,CONT_DIF_N,*
-V 8600,700,CONT_DIF_N,*
-V 5600,3300,CONT_DIF_N,*
-V 11000,1100,CONT_DIF_N,*
-V 6200,700,CONT_DIF_N,*
-V 6800,3300,CONT_DIF_N,*
-V 6800,2100,CONT_DIF_N,*
-V 6800,2500,CONT_DIF_N,*
-V 8000,2900,CONT_DIF_N,*
-V 8000,3300,CONT_DIF_N,*
-V 7400,1500,CONT_DIF_N,*
-V 7400,1100,CONT_DIF_N,*
-V 8000,2100,CONT_DIF_N,*
-V 7400,700,CONT_DIF_N,*
-V 8000,2500,CONT_DIF_N,*
-V 7400,3300,CONT_DIF_N,*
-V 7400,2800,CONT_DIF_N,*
-V 6800,2900,CONT_DIF_N,*
-V 8600,1100,CONT_DIF_N,*
-V 8600,1500,CONT_DIF_N,*
-V 14600,2700,CONT_DIF_N,*
-V 15800,2800,CONT_DIF_N,*
-V 15800,3400,CONT_DIF_N,*
-V 16900,23200,CONT_VIA,*
-V 16300,23200,CONT_VIA,*
-V 16900,1600,CONT_VIA,*
-EOF
diff --git a/alliance/share/cells/padlib/paliotw_sp.ap b/alliance/share/cells/padlib/paliotw_sp.ap
deleted file mode 100644
index a34c76be..00000000
--- a/alliance/share/cells/padlib/paliotw_sp.ap
+++ /dev/null
@@ -1,1623 +0,0 @@
-V ALLIANCE : 4
-H paliotw_sp,P,26/ 0/100,100
-A 0,-700,17200,35600
-C 4900,-700,200,i,0,SOUTH,ALU1
-C 3800,-700,200,t,0,SOUTH,ALU1
-C 15700,-700,200,b,0,SOUTH,ALU1
-C 15700,-700,200,b,1,SOUTH,ALU2
-C 4900,-700,200,i,1,SOUTH,ALU2
-C 3800,-700,200,t,1,SOUTH,ALU2
-C 0,600,1200,ck,0,WEST,ALU2
-C 17200,600,1200,ck,1,EAST,ALU2
-C 0,8400,4000,vddi,0,WEST,ALU2
-C 0,4000,4000,vssi,0,WEST,ALU2
-C 17200,4000,4000,vssi,1,EAST,ALU2
-C 17200,8400,4000,vddi,1,EAST,ALU2
-C 0,16800,12000,vdde,0,WEST,ALU2
-C 17200,16800,12000,vdde,1,EAST,ALU2
-C 17200,29600,12000,vsse,1,EAST,ALU2
-C 0,29600,12000,vsse,0,WEST,ALU2
-S 1100,9100,1700,9100,3900,*,RIGHT,PTRANS
-S 0,29600,17200,29600,12000,vsse,RIGHT,ALU2
-S 6400,13000,14100,13000,200,*,RIGHT,ALU1
-S 6400,13100,14100,13100,200,*,RIGHT,ALU1
-S 2700,12600,6000,12600,300,*,RIGHT,ALU1
-S 5900,12500,5900,12900,300,*,UP,ALU1
-S 6400,23200,16900,23200,300,*,RIGHT,ALU2
-S 16200,23200,17000,23200,300,*,RIGHT,ALU1
-S 16400,1600,17000,1600,300,*,LEFT,ALU1
-S 16400,2300,16400,4100,200,*,UP,ALU1
-S 16900,1500,16900,23300,300,*,UP,ALU1
-S 16400,5000,16400,12100,200,*,UP,ALU1
-S 600,5100,16600,5100,400,*,RIGHT,NWELL
-S 600,8600,16600,8600,7200,*,RIGHT,NWELL
-S 14900,2400,14900,3700,100,*,UP,NTRANS
-S 14600,2600,14600,3500,300,*,UP,NDIF
-S 15200,2600,15200,3500,300,*,DOWN,NDIF
-S 12200,600,12200,3400,200,*,UP,NDIF
-S 12800,600,12800,3400,300,*,UP,NDIF
-S 13400,600,13400,3400,200,*,UP,NDIF
-S 14000,600,14000,3400,300,*,UP,NDIF
-S 15800,2600,15800,3500,300,*,UP,NDIF
-S 15500,2400,15500,3700,100,*,UP,NTRANS
-S 11900,400,11900,3600,100,*,UP,NTRANS
-S 12500,400,12500,3600,100,*,UP,NTRANS
-S 13100,400,13100,3600,100,*,UP,NTRANS
-S 13700,400,13700,3600,100,*,UP,NTRANS
-S 11600,600,11600,3400,300,*,UP,NDIF
-S 6800,600,6800,3500,300,*,UP,NDIF
-S 8600,600,8600,3500,200,*,UP,NDIF
-S 7400,600,7400,3500,200,*,UP,NDIF
-S 8300,400,8300,3700,100,*,UP,NTRANS
-S 7700,400,7700,3700,100,*,UP,NTRANS
-S 7100,400,7100,3700,100,*,UP,NTRANS
-S 6500,400,6500,3700,100,*,UP,NTRANS
-S 6200,600,6200,3500,200,*,UP,NDIF
-S 5900,400,5900,3700,100,*,UP,NTRANS
-S 5600,600,5600,3500,300,*,UP,NDIF
-S 8000,600,8000,3500,300,*,UP,NDIF
-S 10400,600,10400,3500,300,*,UP,NDIF
-S 8900,400,8900,3700,100,*,UP,NTRANS
-S 9200,600,9200,3500,300,*,UP,NDIF
-S 9800,600,9800,3500,200,*,UP,NDIF
-S 10700,400,10700,3700,100,*,UP,NTRANS
-S 5000,600,5000,3500,300,*,UP,NDIF
-S 4700,400,4700,3700,100,*,UP,NTRANS
-S 4400,600,4400,3500,200,*,UP,NDIF
-S 10100,400,10100,3700,100,*,UP,NTRANS
-S 9500,400,9500,3700,100,*,UP,NTRANS
-S 2900,400,2900,3700,100,*,UP,NTRANS
-S 3200,600,3200,3500,200,*,UP,NDIF
-S 3800,600,3800,3500,300,*,UP,NDIF
-S 3500,400,3500,3700,100,*,UP,NTRANS
-S 4100,400,4100,3700,100,*,UP,NTRANS
-S 11000,600,11000,3500,300,*,UP,NDIF
-S 1400,600,1400,3500,300,*,UP,NDIF
-S 2600,600,2600,3500,300,*,UP,NDIF
-S 2000,600,2000,3500,200,*,UP,NDIF
-S 1700,400,1700,3700,100,*,UP,NTRANS
-S 2300,400,2300,3700,100,*,UP,NTRANS
-S 12200,5700,12200,11500,300,*,UP,PDIF
-S 12800,5700,12800,11500,300,*,UP,PDIF
-S 13100,5500,13100,11700,100,*,UP,PTRANS
-S 13400,5700,13400,11500,300,*,UP,PDIF
-S 13700,5500,13700,11700,100,*,UP,PTRANS
-S 14000,5700,14000,11500,300,*,UP,PDIF
-S 8300,5400,8300,11700,100,*,UP,PTRANS
-S 7700,5400,7700,11700,100,*,UP,PTRANS
-S 11900,5500,11900,11700,100,*,UP,PTRANS
-S 11600,5700,11600,11500,300,*,UP,PDIF
-S 12500,5500,12500,11700,100,*,UP,PTRANS
-S 5900,5400,5900,11700,100,*,UP,PTRANS
-S 5600,5600,5600,11500,300,*,UP,PDIF
-S 8000,5600,8000,11500,300,*,UP,PDIF
-S 10400,5600,10400,11500,300,*,UP,PDIF
-S 6800,5600,6800,11500,300,*,UP,PDIF
-S 8600,5600,8600,11500,300,*,UP,PDIF
-S 7400,5600,7400,11500,300,*,UP,PDIF
-S 11000,5600,11000,11500,300,*,UP,PDIF
-S 9800,5600,9800,11500,300,*,UP,PDIF
-S 7100,5400,7100,11700,100,*,UP,PTRANS
-S 6500,5400,6500,11700,100,*,UP,PTRANS
-S 6200,5600,6200,11500,300,*,UP,PDIF
-S 10700,5400,10700,11700,100,*,UP,PTRANS
-S 10100,5400,10100,11700,100,*,UP,PTRANS
-S 9500,5400,9500,11700,100,*,UP,PTRANS
-S 8900,5400,8900,11700,100,*,UP,PTRANS
-S 9200,5600,9200,11500,300,*,UP,PDIF
-S 3500,5400,3500,11700,100,*,UP,PTRANS
-S 4100,5400,4100,11700,100,*,UP,PTRANS
-S 4400,5600,4400,11500,300,*,UP,PDIF
-S 5000,5600,5000,11500,300,*,UP,PDIF
-S 4700,5400,4700,11700,100,*,UP,PTRANS
-S 2900,5400,2900,8700,100,*,UP,PTRANS
-S 2600,5600,2600,8500,300,*,UP,PDIF
-S 3200,5600,3200,11500,300,*,UP,PDIF
-S 3800,5600,3800,11500,300,*,UP,PDIF
-S 14600,5700,14600,7600,300,*,UP,PDIF
-S 15800,5700,15800,7600,300,*,UP,PDIF
-S 15200,5700,15200,7600,300,*,UP,PDIF
-S 14900,5500,14900,7800,100,*,UP,PTRANS
-S 15500,5500,15500,7800,100,*,UP,PTRANS
-S 700,12000,16500,12000,300,*,RIGHT,NTIE
-S 800,5000,800,12100,300,*,UP,NTIE
-S 700,5100,2700,5100,300,*,RIGHT,NTIE
-S 11600,5100,14000,5100,300,*,RIGHT,NTIE
-S 14500,5100,15300,5100,300,*,RIGHT,NTIE
-S 1400,5100,1400,6400,1100,*,DOWN,NTIE
-S 15700,5100,16500,5100,300,*,RIGHT,NTIE
-S 10100,5100,11000,5100,300,*,RIGHT,NTIE
-S 7700,5100,9500,5100,300,*,RIGHT,NTIE
-S 16400,5000,16400,12100,300,*,UP,NTIE
-S 6100,5100,7100,5100,300,*,RIGHT,NTIE
-S 15500,8100,15500,12000,2000,*,DOWN,NTIE
-S 2200,8900,2200,9900,300,*,UP,NTIE
-S 2000,5000,2000,9100,300,*,UP,NTIE
-S 2000,9700,2000,12000,300,*,UP,NTIE
-S 800,-300,800,4100,300,*,UP,PTIE
-S 700,-200,15300,-200,300,*,RIGHT,PTIE
-S 15200,-300,15200,1900,300,*,DOWN,PTIE
-S 700,4000,2700,4000,300,*,RIGHT,PTIE
-S 15200,1800,16500,1800,300,*,LEFT,PTIE
-S 14900,0,14900,1900,300,*,DOWN,PTIE
-S 14600,0,14600,1900,300,*,DOWN,PTIE
-S 15700,4000,16500,4000,300,*,LEFT,PTIE
-S 6100,4000,7100,4000,300,*,RIGHT,PTIE
-S 11600,4000,14000,4000,300,*,RIGHT,PTIE
-S 7700,4000,10400,4000,300,*,RIGHT,PTIE
-S 16400,1700,16400,4100,300,*,UP,PTIE
-S 14200,3700,14200,3900,100,*,DOWN,POLY
-S 15500,2200,15500,2400,100,*,DOWN,POLY
-S 15500,3700,15500,5500,100,*,UP,POLY
-S 11300,5500,14900,5500,100,*,RIGHT,POLY
-S 11400,4500,11400,5300,100,*,DOWN,POLY
-S 10600,4600,11200,4600,100,*,LEFT,POLY
-S 10600,3800,10600,4500,100,*,DOWN,POLY
-S 14900,3700,14900,4300,100,*,UP,POLY
-S 14200,4500,14900,4500,300,*,RIGHT,POLY
-S 14300,4700,14300,5300,100,*,DOWN,POLY
-S 14200,4700,14200,5300,100,*,DOWN,POLY
-S 14300,3700,14300,3900,100,*,DOWN,POLY
-S 6500,5400,8300,5400,100,*,RIGHT,POLY
-S 6500,3700,8300,3700,100,*,RIGHT,POLY
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-S 11400,3700,14300,3700,100,*,RIGHT,POLY
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-S 700,12000,2300,12000,300,*,RIGHT,ALU1
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-S 11600,4600,13500,4600,200,*,RIGHT,ALU1
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-S 1200,8800,1200,9700,500,*,DOWN,ALU1
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-S 11900,13600,11900,22600,300,*,UP,NTIE
-S 11500,22500,12000,22500,300,*,RIGHT,NTIE
-S 11700,13500,11700,22600,600,*,UP,ALU1
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-S 11400,24300,12000,24300,300,*,RIGHT,PTIE
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-S 11700,24200,11700,29300,600,*,UP,ALU1
-S 3700,13400,3700,22700,800,*,UP,NWELL
-S 4100,24900,4100,28200,300,*,UP,NDIF
-S 4100,14100,4100,22000,300,*,UP,PDIF
-S 3500,13600,4100,13600,300,*,RIGHT,NTIE
-S 3500,13600,3500,22600,300,*,UP,NTIE
-S 3500,22500,4100,22500,300,*,RIGHT,NTIE
-S 3400,28700,4200,28700,300,*,RIGHT,PTIE
-S 3500,24200,3500,28800,300,*,UP,PTIE
-S 3400,24300,4200,24300,300,*,RIGHT,PTIE
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-S 6400,23100,6400,23800,200,*,UP,ALU1
-S 3800,24200,3800,29300,800,*,UP,ALU1
-S 3400,28000,3400,28800,100,*,UP,ALU1
-S 9500,14200,9500,29100,300,*,UP,ALU1
-S 10700,14200,10700,29100,300,*,UP,ALU1
-S 10100,23700,10100,28800,300,*,UP,ALU1
-S 11300,24200,11300,28800,300,*,UP,ALU1
-S 11300,24800,11300,28200,300,*,UP,NDIF
-S 10700,24800,10700,28200,300,*,UP,NDIF
-S 10100,24800,10100,28200,300,*,UP,NDIF
-S 9500,24800,9500,28200,300,*,UP,NDIF
-S 9200,24600,9200,28400,100,*,UP,NTRANS
-S 9800,24600,9800,28400,100,*,UP,NTRANS
-S 10400,24600,10400,28400,100,*,UP,NTRANS
-S 11000,24600,11000,28400,100,*,UP,NTRANS
-S 9000,28700,11400,28700,300,*,RIGHT,PTIE
-S 11300,14100,11300,22000,300,*,UP,PDIF
-S 10700,14100,10700,22000,200,*,UP,PDIF
-S 10100,14100,10100,22000,200,*,UP,PDIF
-S 9500,14100,9500,22000,200,*,UP,PDIF
-S 9200,13900,9200,22200,100,*,UP,PTRANS
-S 10100,13800,10100,22600,300,*,UP,ALU1
-S 9800,13900,9800,22200,100,*,UP,PTRANS
-S 10400,13900,10400,22200,100,*,UP,PTRANS
-S 11000,13900,11000,22200,100,*,UP,PTRANS
-S 10300,13400,10300,22700,2800,*,UP,NWELL
-S 11300,13800,11300,22600,300,*,UP,ALU1
-S 9000,13600,10400,13600,300,*,RIGHT,NTIE
-S 11000,13600,11400,13600,300,*,RIGHT,NTIE
-S 10700,13300,10700,13900,200,*,UP,POLY
-S 9200,13900,11000,13900,100,*,RIGHT,POLY
-S 9000,13600,10400,13600,300,*,RIGHT,ALU1
-S 11000,13600,11400,13600,300,*,RIGHT,ALU1
-S 10700,23700,10700,23900,200,*,DOWN,POLY
-S 9000,24300,10400,24300,300,*,RIGHT,PTIE
-S 11000,24300,11400,24300,300,*,RIGHT,PTIE
-S 9200,24600,11000,24600,100,*,RIGHT,POLY
-S 10700,23800,10700,24600,200,*,UP,POLY
-S 10700,23800,11200,23800,300,*,RIGHT,POLY
-S 11200,23200,11200,23800,200,*,UP,ALU1
-S 9000,22500,11400,22500,300,*,RIGHT,NTIE
-S 7100,14200,7100,29100,300,*,UP,ALU1
-S 8300,14200,8300,29100,300,*,UP,ALU1
-S 7700,23700,7700,28800,300,*,UP,ALU1
-S 8900,24200,8900,28800,300,*,UP,ALU1
-S 8900,24800,8900,28200,300,*,UP,NDIF
-S 8300,24800,8300,28200,300,*,UP,NDIF
-S 7700,24800,7700,28200,300,*,UP,NDIF
-S 7100,24800,7100,28200,300,*,UP,NDIF
-S 6800,24600,6800,28400,100,*,UP,NTRANS
-S 7400,24600,7400,28400,100,*,UP,NTRANS
-S 8000,24600,8000,28400,100,*,UP,NTRANS
-S 8600,24600,8600,28400,100,*,UP,NTRANS
-S 6600,28700,9000,28700,300,*,RIGHT,PTIE
-S 8900,14100,8900,22000,300,*,UP,PDIF
-S 8300,14100,8300,22000,200,*,UP,PDIF
-S 7700,14100,7700,22000,200,*,UP,PDIF
-S 7100,14100,7100,22000,200,*,UP,PDIF
-S 6800,13900,6800,22200,100,*,UP,PTRANS
-S 7700,13800,7700,22600,300,*,UP,ALU1
-S 7400,13900,7400,22200,100,*,UP,PTRANS
-S 8000,13900,8000,22200,100,*,UP,PTRANS
-S 8600,13900,8600,22200,100,*,UP,PTRANS
-S 7900,13400,7900,22700,2800,*,UP,NWELL
-S 8900,13800,8900,22600,300,*,UP,ALU1
-S 6600,13600,8000,13600,300,*,RIGHT,NTIE
-S 8600,13600,9000,13600,300,*,RIGHT,NTIE
-S 8300,13300,8300,13900,200,*,UP,POLY
-S 6800,13900,8600,13900,100,*,RIGHT,POLY
-S 6600,13600,8000,13600,300,*,RIGHT,ALU1
-S 8600,13600,9000,13600,300,*,RIGHT,ALU1
-S 8300,23700,8300,23900,200,*,DOWN,POLY
-S 6600,24300,8000,24300,300,*,RIGHT,PTIE
-S 8600,24300,9000,24300,300,*,RIGHT,PTIE
-S 6800,24600,8600,24600,100,*,RIGHT,POLY
-S 8300,23800,8300,24600,200,*,UP,POLY
-S 8300,23800,8800,23800,300,*,RIGHT,POLY
-S 8800,23200,8800,23800,200,*,UP,ALU1
-S 6600,22500,9000,22500,300,*,RIGHT,NTIE
-S 5900,13000,5900,14300,300,*,DOWN,ALU1
-S 6500,13500,6500,22600,300,*,UP,ALU1
-S 4200,13600,5400,13600,300,*,RIGHT,ALU1
-S 5900,13100,5900,13900,200,*,UP,POLY
-S 4200,22500,6600,22500,300,*,RIGHT,NTIE
-S 5900,23800,6400,23800,300,*,RIGHT,POLY
-S 5900,23800,5900,24600,200,*,UP,POLY
-S 4400,24600,6200,24600,100,*,RIGHT,POLY
-S 6200,24300,6600,24300,300,*,RIGHT,PTIE
-S 4200,24300,5600,24300,300,*,RIGHT,PTIE
-S 5900,23700,5900,23900,200,*,DOWN,POLY
-S 4400,13900,6200,13900,100,*,RIGHT,POLY
-S 6200,13600,6600,13600,300,*,RIGHT,NTIE
-S 4200,13600,5600,13600,300,*,RIGHT,NTIE
-S 5500,13400,5500,22700,2800,*,UP,NWELL
-S 6200,13900,6200,22200,100,*,UP,PTRANS
-S 5600,13900,5600,22200,100,*,UP,PTRANS
-S 5000,13900,5000,22200,100,*,UP,PTRANS
-S 5300,13800,5300,22600,300,*,UP,ALU1
-S 4400,13900,4400,22200,100,*,UP,PTRANS
-S 4700,14100,4700,22000,200,*,UP,PDIF
-S 5300,14100,5300,22000,200,*,UP,PDIF
-S 5900,14100,5900,22000,200,*,UP,PDIF
-S 6500,14100,6500,22000,300,*,UP,PDIF
-S 4200,28700,6600,28700,300,*,RIGHT,PTIE
-S 6200,24600,6200,28400,100,*,UP,NTRANS
-S 5600,24600,5600,28400,100,*,UP,NTRANS
-S 5000,24600,5000,28400,100,*,UP,NTRANS
-S 4400,24600,4400,28400,100,*,UP,NTRANS
-S 4700,24800,4700,28200,300,*,UP,NDIF
-S 5300,24800,5300,28200,300,*,UP,NDIF
-S 5900,24800,5900,28200,300,*,UP,NDIF
-S 6500,24800,6500,28200,300,*,UP,NDIF
-S 6500,24200,6500,28800,300,*,UP,ALU1
-S 5300,23700,5300,28800,300,*,UP,ALU1
-S 5900,14200,5900,29100,300,*,UP,ALU1
-S 4700,14200,4700,29100,300,*,UP,ALU1
-S 5900,13100,6500,13100,200,*,RIGHT,POLY
-S 6400,13500,6400,13700,200,*,DOWN,ALU1
-S 0,600,17200,600,1200,ck,RIGHT,ALU2
-S 0,4000,17200,4000,4000,vssi,RIGHT,ALU2
-S 0,8400,17200,8400,4000,vddi,RIGHT,ALU2
-S 0,16800,17200,16800,12000,vdde,RIGHT,ALU2
-V 16300,23200,CONT_VIA
-V 16900,23200,CONT_VIA
-V 16500,1600,CONT_VIA
-V 16900,1600,CONT_VIA
-V 15800,3400,CONT_DIF_N
-V 15800,2800,CONT_DIF_N
-V 14600,2700,CONT_DIF_N
-V 8600,1500,CONT_DIF_N
-V 8600,1100,CONT_DIF_N
-V 6800,2900,CONT_DIF_N
-V 7400,2800,CONT_DIF_N
-V 7400,3300,CONT_DIF_N
-V 8000,2500,CONT_DIF_N
-V 7400,700,CONT_DIF_N
-V 8000,2100,CONT_DIF_N
-V 7400,1100,CONT_DIF_N
-V 7400,1500,CONT_DIF_N
-V 8000,3300,CONT_DIF_N
-V 8000,2900,CONT_DIF_N
-V 6800,2500,CONT_DIF_N
-V 6800,2100,CONT_DIF_N
-V 6800,3300,CONT_DIF_N
-V 6200,700,CONT_DIF_N
-V 11000,1100,CONT_DIF_N
-V 5600,3300,CONT_DIF_N
-V 8600,700,CONT_DIF_N
-V 8600,3100,CONT_DIF_N
-V 8600,2700,CONT_DIF_N
-V 8600,1900,CONT_DIF_N
-V 7400,1900,CONT_DIF_N
-V 5600,2500,CONT_DIF_N
-V 11000,3100,CONT_DIF_N
-V 11000,2700,CONT_DIF_N
-V 6200,3100,CONT_DIF_N
-V 6200,2700,CONT_DIF_N
-V 6200,1900,CONT_DIF_N
-V 6200,1500,CONT_DIF_N
-V 6200,1100,CONT_DIF_N
-V 9800,1500,CONT_DIF_N
-V 8000,700,CONT_DIF_N
-V 9200,2500,CONT_DIF_N
-V 5600,2900,CONT_DIF_N
-V 5600,900,CONT_DIF_N
-V 5600,1300,CONT_DIF_N
-V 5600,1700,CONT_DIF_N
-V 5600,2100,CONT_DIF_N
-V 11000,700,CONT_DIF_N
-V 9200,700,CONT_DIF_N
-V 10400,700,CONT_DIF_N
-V 11000,1900,CONT_DIF_N
-V 9800,1900,CONT_DIF_N
-V 9800,700,CONT_DIF_N
-V 9800,1100,CONT_DIF_N
-V 10400,2900,CONT_DIF_N
-V 9200,1200,CONT_DIF_N
-V 10400,2100,CONT_DIF_N
-V 10400,3300,CONT_DIF_N
-V 9800,2800,CONT_DIF_N
-V 9200,2100,CONT_DIF_N
-V 9200,3300,CONT_DIF_N
-V 9200,2900,CONT_DIF_N
-V 11000,1500,CONT_DIF_N
-V 9800,3300,CONT_DIF_N
-V 5000,3300,CONT_DIF_N
-V 5000,2900,CONT_DIF_N
-V 5000,2100,CONT_DIF_N
-V 5000,2500,CONT_DIF_N
-V 5000,900,CONT_DIF_N
-V 5000,1300,CONT_DIF_N
-V 10400,1200,CONT_DIF_N
-V 10400,2500,CONT_DIF_N
-V 8000,1200,CONT_DIF_N
-V 3200,1500,CONT_DIF_N
-V 3200,1100,CONT_DIF_N
-V 3800,2900,CONT_DIF_N
-V 3800,2100,CONT_DIF_N
-V 4400,1100,CONT_DIF_N
-V 4400,1500,CONT_DIF_N
-V 5000,1700,CONT_DIF_N
-V 3800,2500,CONT_DIF_N
-V 2000,1500,CONT_DIF_N
-V 2000,1900,CONT_DIF_N
-V 2000,2700,CONT_DIF_N
-V 4400,1900,CONT_DIF_N
-V 4400,2700,CONT_DIF_N
-V 4400,3100,CONT_DIF_N
-V 4400,700,CONT_DIF_N
-V 2600,3300,CONT_DIF_N
-V 2600,2900,CONT_DIF_N
-V 2600,2100,CONT_DIF_N
-V 2600,2500,CONT_DIF_N
-V 3800,3300,CONT_DIF_N
-V 3800,1700,CONT_DIF_N
-V 3800,1300,CONT_DIF_N
-V 3800,900,CONT_DIF_N
-V 1400,1700,CONT_DIF_N
-V 1400,3300,CONT_DIF_N
-V 1400,2900,CONT_DIF_N
-V 1400,2100,CONT_DIF_N
-V 3200,700,CONT_DIF_N
-V 3200,3100,CONT_DIF_N
-V 3200,2700,CONT_DIF_N
-V 3200,1900,CONT_DIF_N
-V 1400,1300,CONT_DIF_N
-V 2600,1700,CONT_DIF_N
-V 6800,1200,CONT_DIF_N
-V 6800,700,CONT_DIF_N
-V 2600,900,CONT_DIF_N
-V 2600,1300,CONT_DIF_N
-V 2000,700,CONT_DIF_N
-V 2000,1100,CONT_DIF_N
-V 12200,1500,CONT_DIF_N
-V 14000,2100,CONT_DIF_N
-V 11600,700,CONT_DIF_N
-V 12800,1200,CONT_DIF_N
-V 14000,1200,CONT_DIF_N
-V 14000,700,CONT_DIF_N
-V 1400,2500,CONT_DIF_N
-V 1400,900,CONT_DIF_N
-V 11600,2100,CONT_DIF_N
-V 11600,3300,CONT_DIF_N
-V 11600,2900,CONT_DIF_N
-V 12200,3300,CONT_DIF_N
-V 12200,1900,CONT_DIF_N
-V 12200,700,CONT_DIF_N
-V 12200,1100,CONT_DIF_N
-V 14000,3300,CONT_DIF_N
-V 13400,3300,CONT_DIF_N
-V 12800,2900,CONT_DIF_N
-V 12800,3300,CONT_DIF_N
-V 14000,2900,CONT_DIF_N
-V 13400,1500,CONT_DIF_N
-V 12200,2800,CONT_DIF_N
-V 11600,1200,CONT_DIF_N
-V 11600,2500,CONT_DIF_N
-V 12800,2100,CONT_DIF_N
-V 12800,2500,CONT_DIF_N
-V 12800,700,CONT_DIF_N
-V 13400,2800,CONT_DIF_N
-V 14000,2500,CONT_DIF_N
-V 13400,1100,CONT_DIF_N
-V 13400,700,CONT_DIF_N
-V 13400,1900,CONT_DIF_N
-V 15200,3100,CONT_DIF_N
-V 15200,2700,CONT_DIF_N
-V 14600,3300,CONT_DIF_N
-V 12200,2300,CONT_DIF_N
-V 13400,2300,CONT_DIF_N
-V 14600,6200,CONT_DIF_P
-V 14600,6600,CONT_DIF_P
-V 14600,7000,CONT_DIF_P
-V 15200,7000,CONT_DIF_P
-V 15200,6600,CONT_DIF_P
-V 15200,5800,CONT_DIF_P
-V 15200,6200,CONT_DIF_P
-V 15800,7000,CONT_DIF_P
-V 12800,7400,CONT_DIF_P
-V 12800,6200,CONT_DIF_P
-V 12800,7000,CONT_DIF_P
-V 12800,6600,CONT_DIF_P
-V 15800,6200,CONT_DIF_P
-V 15800,5800,CONT_DIF_P
-V 15800,6600,CONT_DIF_P
-V 14600,5800,CONT_DIF_P
-V 8000,9000,CONT_DIF_P
-V 8000,10600,CONT_DIF_P
-V 8000,11000,CONT_DIF_P
-V 8000,5800,CONT_DIF_P
-V 8000,8200,CONT_DIF_P
-V 8000,8600,CONT_DIF_P
-V 8000,11400,CONT_DIF_P
-V 12800,5800,CONT_DIF_P
-V 8000,7400,CONT_DIF_P
-V 6800,6200,CONT_DIF_P
-V 8000,6200,CONT_DIF_P
-V 8000,9400,CONT_DIF_P
-V 8000,9800,CONT_DIF_P
-V 8000,6600,CONT_DIF_P
-V 8000,7000,CONT_DIF_P
-V 8000,10200,CONT_DIF_P
-V 8000,7800,CONT_DIF_P
-V 8600,7800,CONT_DIF_P
-V 6800,10600,CONT_DIF_P
-V 6800,11000,CONT_DIF_P
-V 6800,5800,CONT_DIF_P
-V 6800,8200,CONT_DIF_P
-V 6800,8600,CONT_DIF_P
-V 6800,11400,CONT_DIF_P
-V 6800,7400,CONT_DIF_P
-V 8600,11400,CONT_DIF_P
-V 6800,9400,CONT_DIF_P
-V 6800,9800,CONT_DIF_P
-V 6800,6600,CONT_DIF_P
-V 6800,7000,CONT_DIF_P
-V 6800,10200,CONT_DIF_P
-V 6800,7800,CONT_DIF_P
-V 6800,9000,CONT_DIF_P
-V 7400,8600,CONT_DIF_P
-V 8600,11000,CONT_DIF_P
-V 8600,10600,CONT_DIF_P
-V 8600,9800,CONT_DIF_P
-V 8600,7000,CONT_DIF_P
-V 8600,5800,CONT_DIF_P
-V 8600,6200,CONT_DIF_P
-V 8600,8600,CONT_DIF_P
-V 6200,5800,CONT_DIF_P
-V 8600,8200,CONT_DIF_P
-V 8600,9400,CONT_DIF_P
-V 7400,10600,CONT_DIF_P
-V 7400,11000,CONT_DIF_P
-V 7400,7800,CONT_DIF_P
-V 7400,8200,CONT_DIF_P
-V 7400,11400,CONT_DIF_P
-V 6200,10600,CONT_DIF_P
-V 7400,6200,CONT_DIF_P
-V 7400,5800,CONT_DIF_P
-V 7400,7000,CONT_DIF_P
-V 7400,9800,CONT_DIF_P
-V 7400,9400,CONT_DIF_P
-V 6200,6200,CONT_DIF_P
-V 6200,7000,CONT_DIF_P
-V 5600,11000,CONT_DIF_P
-V 6200,9400,CONT_DIF_P
-V 6200,9800,CONT_DIF_P
-V 6200,11000,CONT_DIF_P
-V 6200,7800,CONT_DIF_P
-V 6200,8200,CONT_DIF_P
-V 6200,11400,CONT_DIF_P
-V 6200,8600,CONT_DIF_P
-V 5600,10600,CONT_DIF_P
-V 5600,9400,CONT_DIF_P
-V 5600,9800,CONT_DIF_P
-V 5600,6600,CONT_DIF_P
-V 5600,7000,CONT_DIF_P
-V 5600,7800,CONT_DIF_P
-V 5600,10200,CONT_DIF_P
-V 5600,9000,CONT_DIF_P
-V 9800,9400,CONT_DIF_P
-V 9800,11000,CONT_DIF_P
-V 5600,5800,CONT_DIF_P
-V 5600,8200,CONT_DIF_P
-V 5600,8600,CONT_DIF_P
-V 5600,11400,CONT_DIF_P
-V 5600,7400,CONT_DIF_P
-V 5600,6200,CONT_DIF_P
-V 9800,8200,CONT_DIF_P
-V 9800,11400,CONT_DIF_P
-V 9800,8600,CONT_DIF_P
-V 9800,6200,CONT_DIF_P
-V 9800,5800,CONT_DIF_P
-V 9800,7000,CONT_DIF_P
-V 11000,7000,CONT_DIF_P
-V 9800,9800,CONT_DIF_P
-V 11000,6200,CONT_DIF_P
-V 11000,8600,CONT_DIF_P
-V 11000,11400,CONT_DIF_P
-V 11000,8200,CONT_DIF_P
-V 11000,9400,CONT_DIF_P
-V 9800,10600,CONT_DIF_P
-V 9200,7000,CONT_DIF_P
-V 9800,7800,CONT_DIF_P
-V 9200,7800,CONT_DIF_P
-V 9200,9000,CONT_DIF_P
-V 11000,7800,CONT_DIF_P
-V 11000,11000,CONT_DIF_P
-V 11000,10600,CONT_DIF_P
-V 11000,9800,CONT_DIF_P
-V 9200,8200,CONT_DIF_P
-V 11000,5800,CONT_DIF_P
-V 9200,11400,CONT_DIF_P
-V 9200,7400,CONT_DIF_P
-V 9200,6200,CONT_DIF_P
-V 9200,9400,CONT_DIF_P
-V 9200,9800,CONT_DIF_P
-V 9200,6600,CONT_DIF_P
-V 10400,6600,CONT_DIF_P
-V 9200,10200,CONT_DIF_P
-V 10400,10200,CONT_DIF_P
-V 10400,7800,CONT_DIF_P
-V 10400,9000,CONT_DIF_P
-V 9200,10600,CONT_DIF_P
-V 9200,11000,CONT_DIF_P
-V 9200,5800,CONT_DIF_P
-V 10400,5800,CONT_DIF_P
-V 9200,8600,CONT_DIF_P
-V 10400,8600,CONT_DIF_P
-V 10400,11400,CONT_DIF_P
-V 10400,7400,CONT_DIF_P
-V 10400,6200,CONT_DIF_P
-V 10400,9400,CONT_DIF_P
-V 10400,9800,CONT_DIF_P
-V 10400,10600,CONT_DIF_P
-V 5000,7800,CONT_DIF_P
-V 5000,9000,CONT_DIF_P
-V 5000,8600,CONT_DIF_P
-V 5000,11400,CONT_DIF_P
-V 5000,7400,CONT_DIF_P
-V 5000,6200,CONT_DIF_P
-V 10400,8200,CONT_DIF_P
-V 10400,7000,CONT_DIF_P
-V 5000,9800,CONT_DIF_P
-V 5000,10600,CONT_DIF_P
-V 5000,6600,CONT_DIF_P
-V 5000,11000,CONT_DIF_P
-V 5000,8200,CONT_DIF_P
-V 5000,5800,CONT_DIF_P
-V 10400,11000,CONT_DIF_P
-V 5000,7000,CONT_DIF_P
-V 4400,8200,CONT_DIF_P
-V 4400,11000,CONT_DIF_P
-V 4400,9800,CONT_DIF_P
-V 4400,5800,CONT_DIF_P
-V 4400,7000,CONT_DIF_P
-V 4400,6200,CONT_DIF_P
-V 5000,9400,CONT_DIF_P
-V 5000,10200,CONT_DIF_P
-V 3800,7400,CONT_DIF_P
-V 3800,11400,CONT_DIF_P
-V 3800,9000,CONT_DIF_P
-V 3800,7800,CONT_DIF_P
-V 4400,9400,CONT_DIF_P
-V 4400,10600,CONT_DIF_P
-V 4400,8600,CONT_DIF_P
-V 4400,11400,CONT_DIF_P
-V 3800,7000,CONT_DIF_P
-V 3800,10200,CONT_DIF_P
-V 4400,7800,CONT_DIF_P
-V 3800,8200,CONT_DIF_P
-V 3800,11000,CONT_DIF_P
-V 3800,6600,CONT_DIF_P
-V 3800,10600,CONT_DIF_P
-V 3800,6200,CONT_DIF_P
-V 3200,8600,CONT_DIF_P
-V 3200,10600,CONT_DIF_P
-V 3800,8600,CONT_DIF_P
-V 3200,6200,CONT_DIF_P
-V 3200,7000,CONT_DIF_P
-V 3200,5800,CONT_DIF_P
-V 3800,9800,CONT_DIF_P
-V 3800,9400,CONT_DIF_P
-V 2600,8200,CONT_DIF_P
-V 2600,5800,CONT_DIF_P
-V 3800,5800,CONT_DIF_P
-V 3200,9800,CONT_DIF_P
-V 3200,11000,CONT_DIF_P
-V 3200,7800,CONT_DIF_P
-V 3200,8200,CONT_DIF_P
-V 3200,11400,CONT_DIF_P
-V 12200,7000,CONT_DIF_P
-V 12200,9400,CONT_DIF_P
-V 3200,9400,CONT_DIF_P
-V 2600,7000,CONT_DIF_P
-V 2600,7400,CONT_DIF_P
-V 2600,6200,CONT_DIF_P
-V 2600,6600,CONT_DIF_P
-V 2600,7800,CONT_DIF_P
-V 11600,9000,CONT_DIF_P
-V 12200,10600,CONT_DIF_P
-V 12200,7800,CONT_DIF_P
-V 12200,8200,CONT_DIF_P
-V 12200,11400,CONT_DIF_P
-V 12200,8600,CONT_DIF_P
-V 12200,6200,CONT_DIF_P
-V 12200,5800,CONT_DIF_P
-V 11600,7400,CONT_DIF_P
-V 11600,6200,CONT_DIF_P
-V 12200,9800,CONT_DIF_P
-V 11600,9800,CONT_DIF_P
-V 11600,6600,CONT_DIF_P
-V 11600,7000,CONT_DIF_P
-V 11600,10200,CONT_DIF_P
-V 11600,7800,CONT_DIF_P
-V 13400,9400,CONT_DIF_P
-V 13400,9800,CONT_DIF_P
-V 12200,11000,CONT_DIF_P
-V 11600,11000,CONT_DIF_P
-V 11600,5800,CONT_DIF_P
-V 11600,8200,CONT_DIF_P
-V 11600,8600,CONT_DIF_P
-V 11600,11400,CONT_DIF_P
-V 13400,10600,CONT_DIF_P
-V 12800,9000,CONT_DIF_P
-V 11600,9400,CONT_DIF_P
-V 12800,10200,CONT_DIF_P
-V 13400,7000,CONT_DIF_P
-V 13400,5800,CONT_DIF_P
-V 13400,6200,CONT_DIF_P
-V 13400,8600,CONT_DIF_P
-V 12800,9800,CONT_DIF_P
-V 12800,9400,CONT_DIF_P
-V 11600,10600,CONT_DIF_P
-V 12800,8600,CONT_DIF_P
-V 13400,11400,CONT_DIF_P
-V 13400,8200,CONT_DIF_P
-V 13400,7800,CONT_DIF_P
-V 13400,11000,CONT_DIF_P
-V 14000,11400,CONT_DIF_P
-V 14000,8600,CONT_DIF_P
-V 14000,9000,CONT_DIF_P
-V 14000,7800,CONT_DIF_P
-V 14000,10200,CONT_DIF_P
-V 12800,8200,CONT_DIF_P
-V 12800,7800,CONT_DIF_P
-V 12800,10600,CONT_DIF_P
-V 14000,11000,CONT_DIF_P
-V 14000,10600,CONT_DIF_P
-V 14000,7000,CONT_DIF_P
-V 14000,6600,CONT_DIF_P
-V 14000,9800,CONT_DIF_P
-V 14000,9400,CONT_DIF_P
-V 14000,6200,CONT_DIF_P
-V 12800,11400,CONT_DIF_P
-V 13400,7400,CONT_DIF_P
-V 12200,7400,CONT_DIF_P
-V 13400,9000,CONT_DIF_P
-V 12200,9000,CONT_DIF_P
-V 12200,10200,CONT_DIF_P
-V 13400,10200,CONT_DIF_P
-V 14000,8200,CONT_DIF_P
-V 12800,11000,CONT_DIF_P
-V 15800,7500,CONT_DIF_P
-V 15200,7500,CONT_DIF_P
-V 1400,11300,CONT_DIF_P
-V 1400,6900,CONT_DIF_P
-V 14000,5800,CONT_DIF_P
-V 13400,6600,CONT_DIF_P
-V 12200,6600,CONT_DIF_P
-V 14000,7400,CONT_DIF_P
-V 14600,7500,CONT_DIF_P
-V 800,5900,CONT_BODY_N
-V 800,5500,CONT_BODY_N
-V 800,9400,CONT_BODY_N
-V 800,12000,CONT_BODY_N
-V 800,9000,CONT_BODY_N
-V 800,8600,CONT_BODY_N
-V 800,8200,CONT_BODY_N
-V 800,7800,CONT_BODY_N
-V 800,7400,CONT_BODY_N
-V 800,7000,CONT_BODY_N
-V 800,6300,CONT_BODY_N
-V 800,5100,CONT_BODY_N
-V 800,10400,CONT_BODY_N
-V 800,10800,CONT_BODY_N
-V 800,11200,CONT_BODY_N
-V 800,11600,CONT_BODY_N
-V 14800,9500,CONT_BODY_N
-V 14800,9100,CONT_BODY_N
-V 14800,11600,CONT_BODY_N
-V 14800,10400,CONT_BODY_N
-V 14800,8300,CONT_BODY_N
-V 14800,10800,CONT_BODY_N
-V 14800,11200,CONT_BODY_N
-V 14800,12000,CONT_BODY_N
-V 15200,9500,CONT_BODY_N
-V 15200,12000,CONT_BODY_N
-V 15200,11200,CONT_BODY_N
-V 15200,10800,CONT_BODY_N
-V 15200,8300,CONT_BODY_N
-V 15200,10400,CONT_BODY_N
-V 15200,11600,CONT_BODY_N
-V 15200,9100,CONT_BODY_N
-V 15600,12000,CONT_BODY_N
-V 15600,9500,CONT_BODY_N
-V 15600,9100,CONT_BODY_N
-V 15600,11600,CONT_BODY_N
-V 15600,10400,CONT_BODY_N
-V 15600,8300,CONT_BODY_N
-V 15600,10800,CONT_BODY_N
-V 15600,11200,CONT_BODY_N
-V 16000,9100,CONT_BODY_N
-V 16000,9500,CONT_BODY_N
-V 16000,12000,CONT_BODY_N
-V 16000,11200,CONT_BODY_N
-V 16000,10800,CONT_BODY_N
-V 16000,8300,CONT_BODY_N
-V 16000,10400,CONT_BODY_N
-V 16000,11600,CONT_BODY_N
-V 11700,5100,CONT_BODY_N
-V 2000,10700,CONT_BODY_N
-V 2000,10300,CONT_BODY_N
-V 1400,6300,CONT_BODY_N
-V 1400,5900,CONT_BODY_N
-V 1400,5500,CONT_BODY_N
-V 1400,5100,CONT_BODY_N
-V 2000,5100,CONT_BODY_N
-V 3200,12000,CONT_BODY_N
-V 1700,12000,CONT_BODY_N
-V 1200,12000,CONT_BODY_N
-V 6600,5100,CONT_BODY_N
-V 7000,5100,CONT_BODY_N
-V 8600,5100,CONT_BODY_N
-V 6200,5100,CONT_BODY_N
-V 6300,12000,CONT_BODY_N
-V 3200,5100,CONT_BODY_N
-V 3600,12000,CONT_BODY_N
-V 4000,12000,CONT_BODY_N
-V 4800,12000,CONT_BODY_N
-V 4400,5100,CONT_BODY_N
-V 9000,5100,CONT_BODY_N
-V 9400,5100,CONT_BODY_N
-V 11000,5100,CONT_BODY_N
-V 7400,12000,CONT_BODY_N
-V 7800,5100,CONT_BODY_N
-V 8200,5100,CONT_BODY_N
-V 4400,12000,CONT_BODY_N
-V 5300,12000,CONT_BODY_N
-V 5800,12000,CONT_BODY_N
-V 9800,12000,CONT_BODY_N
-V 8600,12000,CONT_BODY_N
-V 16400,11200,CONT_BODY_N
-V 16400,7100,CONT_BODY_N
-V 16400,10800,CONT_BODY_N
-V 16400,8300,CONT_BODY_N
-V 16400,9100,CONT_BODY_N
-V 16400,5500,CONT_BODY_N
-V 10600,5100,CONT_BODY_N
-V 10200,5100,CONT_BODY_N
-V 16400,5100,CONT_BODY_N
-V 16400,10400,CONT_BODY_N
-V 16400,7900,CONT_BODY_N
-V 16400,11600,CONT_BODY_N
-V 16400,9500,CONT_BODY_N
-V 16400,12000,CONT_BODY_N
-V 16400,5900,CONT_BODY_N
-V 16400,6300,CONT_BODY_N
-V 2100,12000,CONT_BODY_N
-V 11000,12000,CONT_BODY_N
-V 15200,5100,CONT_BODY_N
-V 800,-200,CONT_BODY_P
-V 7400,-200,CONT_BODY_P
-V 6200,-200,CONT_BODY_P
-V 2000,-200,CONT_BODY_P
-V 3200,-200,CONT_BODY_P
-V 4400,-200,CONT_BODY_P
-V 9800,-200,CONT_BODY_P
-V 11000,-200,CONT_BODY_P
-V 8600,-200,CONT_BODY_P
-V 12000,-200,CONT_BODY_P
-V 12400,-200,CONT_BODY_P
-V 1200,-200,CONT_BODY_P
-V 13200,-200,CONT_BODY_P
-V 12800,-200,CONT_BODY_P
-V 14800,-200,CONT_BODY_P
-V 14400,-200,CONT_BODY_P
-V 13600,-200,CONT_BODY_P
-V 14000,-200,CONT_BODY_P
-V 10600,-200,CONT_BODY_P
-V 10200,-200,CONT_BODY_P
-V 9000,-200,CONT_BODY_P
-V 9400,-200,CONT_BODY_P
-V 8200,-200,CONT_BODY_P
-V 7800,-200,CONT_BODY_P
-V 7000,-200,CONT_BODY_P
-V 6600,-200,CONT_BODY_P
-V 5800,-200,CONT_BODY_P
-V 5400,-200,CONT_BODY_P
-V 11600,-200,CONT_BODY_P
-V 15200,-200,CONT_BODY_P
-V 1600,-200,CONT_BODY_P
-V 2400,-200,CONT_BODY_P
-V 2800,-200,CONT_BODY_P
-V 800,300,CONT_BODY_P
-V 800,4000,CONT_BODY_P
-V 800,3100,CONT_BODY_P
-V 800,2700,CONT_BODY_P
-V 800,1900,CONT_BODY_P
-V 800,1500,CONT_BODY_P
-V 800,1100,CONT_BODY_P
-V 800,700,CONT_BODY_P
-V 15200,200,CONT_BODY_P
-V 14700,1800,CONT_BODY_P
-V 14700,1400,CONT_BODY_P
-V 15200,1400,CONT_BODY_P
-V 14700,1000,CONT_BODY_P
-V 15200,1000,CONT_BODY_P
-V 14700,600,CONT_BODY_P
-V 15200,600,CONT_BODY_P
-V 14700,200,CONT_BODY_P
-V 8600,4000,CONT_BODY_P
-V 6200,4000,CONT_BODY_P
-V 10300,4000,CONT_BODY_P
-V 9900,4000,CONT_BODY_P
-V 9400,4000,CONT_BODY_P
-V 15200,1800,CONT_BODY_P
-V 3200,4000,CONT_BODY_P
-V 4400,4000,CONT_BODY_P
-V 6600,4000,CONT_BODY_P
-V 7000,4000,CONT_BODY_P
-V 8200,4000,CONT_BODY_P
-V 9000,4000,CONT_BODY_P
-V 7800,4000,CONT_BODY_P
-V 2000,4000,CONT_BODY_P
-V 16400,4000,CONT_BODY_P
-V 16400,4000,CONT_BODY_P
-V 15200,4000,CONT_BODY_P
-V 16400,3200,CONT_BODY_P
-V 16400,2800,CONT_BODY_P
-V 7400,4600,CONT_POLY
-V 4900,300,CONT_POLY
-V 3300,4500,CONT_POLY
-V 2700,8900,CONT_POLY
-V 5100,5300,CONT_POLY
-V 14500,3800,CONT_POLY
-V 15700,2300,CONT_POLY
-V 1800,9400,CONT_POLY
-V 11100,4000,CONT_POLY
-V 15100,4500,CONT_POLY
-V 9800,4600,CONT_POLY
-V 4900,-700,CONT_VIA
-V 3800,-700,CONT_VIA
-V 15700,-700,CONT_VIA
-V 800,3500,CONT_VIA
-V 800,2300,CONT_VIA
-V 800,6600,CONT_VIA
-V 800,9800,CONT_VIA
-V 14800,8700,CONT_VIA
-V 14800,10000,CONT_VIA
-V 15200,10000,CONT_VIA
-V 15200,8700,CONT_VIA
-V 15600,8700,CONT_VIA
-V 15600,10000,CONT_VIA
-V 16000,10000,CONT_VIA
-V 16000,8700,CONT_VIA
-V 2000,9900,CONT_VIA
-V 6200,6600,CONT_VIA
-V 6200,7400,CONT_VIA
-V 8600,3500,CONT_VIA
-V 10400,1600,CONT_VIA
-V 9200,1600,CONT_VIA
-V 7400,9000,CONT_VIA
-V 7400,10200,CONT_VIA
-V 11000,2300,CONT_VIA
-V 11000,6600,CONT_VIA
-V 7400,6600,CONT_VIA
-V 8600,2300,CONT_VIA
-V 8600,6600,CONT_VIA
-V 8600,10200,CONT_VIA
-V 8600,9000,CONT_VIA
-V 8600,7400,CONT_VIA
-V 9800,9000,CONT_VIA
-V 8000,1600,CONT_VIA
-V 6200,9000,CONT_VIA
-V 6200,10200,CONT_VIA
-V 6200,3500,CONT_VIA
-V 6200,2300,CONT_VIA
-V 7400,2300,CONT_VIA
-V 7400,7400,CONT_VIA
-V 4400,7400,CONT_VIA
-V 4400,6600,CONT_VIA
-V 4400,2300,CONT_VIA
-V 11000,10200,CONT_VIA
-V 11000,9000,CONT_VIA
-V 11000,7400,CONT_VIA
-V 9800,2300,CONT_VIA
-V 9800,7400,CONT_VIA
-V 3200,7400,CONT_VIA
-V 3200,9000,CONT_VIA
-V 2000,2300,CONT_VIA
-V 9800,10200,CONT_VIA
-V 9800,6600,CONT_VIA
-V 4400,3500,CONT_VIA
-V 4400,10200,CONT_VIA
-V 4400,9000,CONT_VIA
-V 2000,3200,CONT_VIA
-V 6800,1600,CONT_VIA
-V 3200,10200,CONT_VIA
-V 3200,3500,CONT_VIA
-V 3200,2300,CONT_VIA
-V 3200,6600,CONT_VIA
-V 16400,7500,CONT_VIA
-V 16400,10000,CONT_VIA
-V 16400,6700,CONT_VIA
-V 16400,8700,CONT_VIA
-V 11600,1600,CONT_VIA
-V 12800,1600,CONT_VIA
-V 14000,1600,CONT_VIA
-V 15200,3500,CONT_VIA
-V 16400,2400,CONT_VIA
-V 16400,3600,CONT_VIA
-V 2000,5800,CONT_VIA
-V 11900,18800,CONT_BODY_N
-V 11900,18400,CONT_BODY_N
-V 11900,14400,CONT_BODY_N
-V 11900,14000,CONT_BODY_N
-V 11900,16400,CONT_BODY_N
-V 11900,18000,CONT_BODY_N
-V 11900,17600,CONT_BODY_N
-V 11900,20000,CONT_BODY_N
-V 11900,19600,CONT_BODY_N
-V 11900,19200,CONT_BODY_N
-V 11500,13600,CONT_BODY_N
-V 11900,16000,CONT_BODY_N
-V 11900,16800,CONT_BODY_N
-V 11900,17200,CONT_BODY_N
-V 11900,15600,CONT_BODY_N
-V 11900,13600,CONT_BODY_N
-V 11900,15200,CONT_BODY_N
-V 11900,14800,CONT_BODY_N
-V 11900,21600,CONT_BODY_N
-V 11900,21200,CONT_BODY_N
-V 11900,20800,CONT_BODY_N
-V 11900,20400,CONT_BODY_N
-V 11900,22500,CONT_BODY_N
-V 11900,22000,CONT_BODY_N
-V 11600,19100,CONT_VIA
-V 11600,14300,CONT_VIA
-V 11600,15900,CONT_VIA
-V 11600,15500,CONT_VIA
-V 11600,18300,CONT_VIA
-V 11600,17100,CONT_VIA
-V 11600,17900,CONT_VIA
-V 11600,19500,CONT_VIA
-V 11600,14700,CONT_VIA
-V 11600,16700,CONT_VIA
-V 11600,13900,CONT_VIA
-V 11600,21500,CONT_VIA
-V 11600,21900,CONT_VIA
-V 11600,20300,CONT_VIA
-V 11600,20700,CONT_VIA
-V 11600,22500,CONT_VIA
-V 11900,27500,CONT_BODY_P
-V 11900,27100,CONT_BODY_P
-V 11900,26700,CONT_BODY_P
-V 11900,26300,CONT_BODY_P
-V 11900,24700,CONT_BODY_P
-V 11900,25100,CONT_BODY_P
-V 11900,25500,CONT_BODY_P
-V 11900,24300,CONT_BODY_P
-V 11900,28700,CONT_BODY_P
-V 11900,28300,CONT_BODY_P
-V 11900,27900,CONT_VIA
-V 11600,24300,CONT_VIA
-V 11900,25900,CONT_VIA
-V 11300,29200,CONT_VIA
-V 11900,29200,CONT_VIA
-V 4100,28100,CONT_DIF_N
-V 4100,27700,CONT_DIF_N
-V 4100,26900,CONT_DIF_N
-V 4100,26500,CONT_DIF_N
-V 4100,25700,CONT_DIF_N
-V 4100,25300,CONT_DIF_N
-V 4100,24900,CONT_DIF_N
-V 4100,26100,CONT_DIF_N
-V 4100,27300,CONT_DIF_N
-V 4100,14700,CONT_DIF_P
-V 4100,15100,CONT_DIF_P
-V 4100,15500,CONT_DIF_P
-V 4100,15900,CONT_DIF_P
-V 4100,16300,CONT_DIF_P
-V 4100,16700,CONT_DIF_P
-V 4100,17100,CONT_DIF_P
-V 4100,17900,CONT_DIF_P
-V 4100,17500,CONT_DIF_P
-V 4100,18300,CONT_DIF_P
-V 4100,18700,CONT_DIF_P
-V 4100,19100,CONT_DIF_P
-V 4100,19500,CONT_DIF_P
-V 4100,19900,CONT_DIF_P
-V 4100,14300,CONT_DIF_P
-V 4100,21900,CONT_DIF_P
-V 4100,21500,CONT_DIF_P
-V 4100,21100,CONT_DIF_P
-V 4100,20700,CONT_DIF_P
-V 4100,20300,CONT_DIF_P
-V 3500,16800,CONT_BODY_N
-V 3500,13600,CONT_BODY_N
-V 4000,13600,CONT_BODY_N
-V 3500,14000,CONT_BODY_N
-V 3500,14400,CONT_BODY_N
-V 3500,14800,CONT_BODY_N
-V 3500,15200,CONT_BODY_N
-V 3500,15600,CONT_BODY_N
-V 3500,19600,CONT_BODY_N
-V 3500,18400,CONT_BODY_N
-V 3500,20000,CONT_BODY_N
-V 3500,17600,CONT_BODY_N
-V 3500,18000,CONT_BODY_N
-V 3500,16000,CONT_BODY_N
-V 3500,16400,CONT_BODY_N
-V 3500,17200,CONT_BODY_N
-V 3500,18800,CONT_BODY_N
-V 3500,19200,CONT_BODY_N
-V 3500,20400,CONT_BODY_N
-V 3500,20800,CONT_BODY_N
-V 3500,21200,CONT_BODY_N
-V 3500,21600,CONT_BODY_N
-V 3500,22000,CONT_BODY_N
-V 4100,22500,CONT_BODY_N
-V 3500,22500,CONT_BODY_N
-V 3500,27500,CONT_BODY_P
-V 3500,27100,CONT_BODY_P
-V 3500,26700,CONT_BODY_P
-V 3500,26300,CONT_BODY_P
-V 3500,25900,CONT_BODY_P
-V 3500,28700,CONT_BODY_P
-V 3500,24700,CONT_BODY_P
-V 3500,25100,CONT_BODY_P
-V 3500,25500,CONT_BODY_P
-V 3900,24300,CONT_BODY_P
-V 3500,24300,CONT_BODY_P
-V 3900,28700,CONT_BODY_P
-V 3500,28300,CONT_BODY_P
-V 3500,27900,CONT_BODY_P
-V 3800,16000,CONT_VIA
-V 3800,16400,CONT_VIA
-V 3800,14000,CONT_VIA
-V 3800,19600,CONT_VIA
-V 3800,19200,CONT_VIA
-V 3800,18000,CONT_VIA
-V 3800,15600,CONT_VIA
-V 3800,15200,CONT_VIA
-V 3800,14800,CONT_VIA
-V 3800,14400,CONT_VIA
-V 3800,16800,CONT_VIA
-V 3800,17600,CONT_VIA
-V 3800,17200,CONT_VIA
-V 3800,18800,CONT_VIA
-V 3800,18400,CONT_VIA
-V 3800,20000,CONT_VIA
-V 6400,23200,CONT_VIA
-V 3500,29200,CONT_VIA
-V 4000,29200,CONT_VIA
-V 3800,27100,CONT_VIA
-V 3800,26700,CONT_VIA
-V 3800,22000,CONT_VIA
-V 3800,21600,CONT_VIA
-V 3800,21200,CONT_VIA
-V 3800,22500,CONT_VIA
-V 3800,20800,CONT_VIA
-V 3800,20400,CONT_VIA
-V 3800,25900,CONT_VIA
-V 3800,24700,CONT_VIA
-V 3800,25100,CONT_VIA
-V 3800,25500,CONT_VIA
-V 3800,26300,CONT_VIA
-V 3800,28300,CONT_VIA
-V 3800,27900,CONT_VIA
-V 3800,27500,CONT_VIA
-V 11300,27700,CONT_DIF_N
-V 11300,26100,CONT_DIF_N
-V 11300,25700,CONT_DIF_N
-V 11300,27300,CONT_DIF_N
-V 11300,26900,CONT_DIF_N
-V 11300,25300,CONT_DIF_N
-V 11300,26500,CONT_VIA
-V 11300,24900,CONT_VIA
-V 11300,28100,CONT_VIA
-V 10100,24900,CONT_VIA
-V 10100,25300,CONT_DIF_N
-V 10100,26900,CONT_DIF_N
-V 10100,27300,CONT_DIF_N
-V 10100,26500,CONT_DIF_N
-V 10100,28100,CONT_DIF_N
-V 10100,25700,CONT_DIF_N
-V 10100,27700,CONT_VIA
-V 10100,26100,CONT_VIA
-V 11300,28700,CONT_BODY_P
-V 10100,28700,CONT_BODY_P
-V 9200,13600,CONT_BODY_N
-V 10300,13600,CONT_BODY_N
-V 9700,13600,CONT_BODY_N
-V 11100,13600,CONT_BODY_N
-V 10700,13100,CONT_POLY
-V 10000,13600,CONT_VIA
-V 9500,25000,CONT_DIF_N
-V 9500,27400,CONT_DIF_N
-V 9500,27800,CONT_DIF_N
-V 9500,25400,CONT_DIF_N
-V 9500,25800,CONT_DIF_N
-V 9500,26200,CONT_DIF_N
-V 9500,26600,CONT_DIF_N
-V 9500,27000,CONT_DIF_N
-V 10700,25800,CONT_DIF_N
-V 10700,26200,CONT_DIF_N
-V 10700,25400,CONT_DIF_N
-V 10700,25000,CONT_DIF_N
-V 10700,27800,CONT_DIF_N
-V 10700,26600,CONT_DIF_N
-V 10700,27000,CONT_DIF_N
-V 10700,27400,CONT_DIF_N
-V 10100,14300,CONT_DIF_P
-V 9500,14700,CONT_DIF_P
-V 10100,14700,CONT_DIF_P
-V 9500,15100,CONT_DIF_P
-V 9500,14300,CONT_DIF_P
-V 10700,14300,CONT_DIF_P
-V 11300,14300,CONT_DIF_P
-V 10700,14700,CONT_DIF_P
-V 11300,14700,CONT_DIF_P
-V 10700,15100,CONT_DIF_P
-V 10100,15500,CONT_DIF_P
-V 9500,15500,CONT_DIF_P
-V 9500,19500,CONT_DIF_P
-V 9500,17900,CONT_DIF_P
-V 10100,17900,CONT_DIF_P
-V 9500,18300,CONT_DIF_P
-V 10100,18300,CONT_DIF_P
-V 9500,18700,CONT_DIF_P
-V 9500,19100,CONT_DIF_P
-V 10100,19100,CONT_DIF_P
-V 10100,19500,CONT_DIF_P
-V 9500,16300,CONT_DIF_P
-V 9500,15900,CONT_DIF_P
-V 10100,15900,CONT_DIF_P
-V 9500,17500,CONT_DIF_P
-V 9500,17100,CONT_DIF_P
-V 9500,16700,CONT_DIF_P
-V 10100,16700,CONT_DIF_P
-V 10100,17100,CONT_DIF_P
-V 10700,15500,CONT_DIF_P
-V 11300,15500,CONT_DIF_P
-V 11300,19500,CONT_DIF_P
-V 10700,18300,CONT_DIF_P
-V 10700,18700,CONT_DIF_P
-V 10700,19100,CONT_DIF_P
-V 11300,19100,CONT_DIF_P
-V 10700,19500,CONT_DIF_P
-V 10700,17500,CONT_DIF_P
-V 10700,17100,CONT_DIF_P
-V 10700,17900,CONT_DIF_P
-V 11300,17900,CONT_DIF_P
-V 11300,18300,CONT_DIF_P
-V 10700,16300,CONT_DIF_P
-V 10700,15900,CONT_DIF_P
-V 11300,15900,CONT_DIF_P
-V 11300,17100,CONT_DIF_P
-V 11300,16700,CONT_DIF_P
-V 10700,16700,CONT_DIF_P
-V 10100,15100,CONT_VIA
-V 11300,15100,CONT_VIA
-V 10100,17500,CONT_VIA
-V 10100,18700,CONT_VIA
-V 10100,16300,CONT_VIA
-V 11300,18700,CONT_VIA
-V 11300,17500,CONT_VIA
-V 11300,16300,CONT_VIA
-V 9500,19900,CONT_DIF_P
-V 10700,19900,CONT_DIF_P
-V 10100,19900,CONT_VIA
-V 11300,19900,CONT_VIA
-V 9500,20300,CONT_DIF_P
-V 10700,20300,CONT_DIF_P
-V 10100,20300,CONT_DIF_P
-V 11300,20300,CONT_DIF_P
-V 10100,20700,CONT_DIF_P
-V 11300,20700,CONT_DIF_P
-V 10700,20700,CONT_DIF_P
-V 9500,20700,CONT_DIF_P
-V 9500,21100,CONT_DIF_P
-V 10700,21100,CONT_DIF_P
-V 11300,21100,CONT_VIA
-V 10100,21100,CONT_VIA
-V 9500,21500,CONT_DIF_P
-V 10100,21500,CONT_DIF_P
-V 10700,21500,CONT_DIF_P
-V 11300,21500,CONT_DIF_P
-V 10100,24300,CONT_BODY_P
-V 11300,24300,CONT_BODY_P
-V 11200,23800,CONT_POLY
-V 10100,23800,CONT_VIA
-V 11200,23200,CONT_VIA
-V 11300,22500,CONT_BODY_N
-V 10100,22500,CONT_BODY_N
-V 11300,21900,CONT_DIF_P
-V 10700,21900,CONT_DIF_P
-V 10100,21900,CONT_DIF_P
-V 9500,21900,CONT_DIF_P
-V 8900,27700,CONT_DIF_N
-V 8900,26100,CONT_DIF_N
-V 8900,25700,CONT_DIF_N
-V 8900,27300,CONT_DIF_N
-V 8900,26900,CONT_DIF_N
-V 8900,25300,CONT_DIF_N
-V 8900,26500,CONT_VIA
-V 8900,24900,CONT_VIA
-V 8900,28100,CONT_VIA
-V 7700,24900,CONT_VIA
-V 7700,25300,CONT_DIF_N
-V 7700,26900,CONT_DIF_N
-V 7700,27300,CONT_DIF_N
-V 7700,26500,CONT_DIF_N
-V 7700,28100,CONT_DIF_N
-V 7700,25700,CONT_DIF_N
-V 7700,27700,CONT_VIA
-V 7700,26100,CONT_VIA
-V 8900,28700,CONT_BODY_P
-V 7700,28700,CONT_BODY_P
-V 6800,13600,CONT_BODY_N
-V 7900,13600,CONT_BODY_N
-V 7300,13600,CONT_BODY_N
-V 8700,13600,CONT_BODY_N
-V 8300,13100,CONT_POLY
-V 7600,13600,CONT_VIA
-V 7100,25000,CONT_DIF_N
-V 7100,27400,CONT_DIF_N
-V 7100,27800,CONT_DIF_N
-V 7100,25400,CONT_DIF_N
-V 7100,25800,CONT_DIF_N
-V 7100,26200,CONT_DIF_N
-V 7100,26600,CONT_DIF_N
-V 7100,27000,CONT_DIF_N
-V 8300,25800,CONT_DIF_N
-V 8300,26200,CONT_DIF_N
-V 8300,25400,CONT_DIF_N
-V 8300,25000,CONT_DIF_N
-V 8300,27800,CONT_DIF_N
-V 8300,26600,CONT_DIF_N
-V 8300,27000,CONT_DIF_N
-V 8300,27400,CONT_DIF_N
-V 7700,14300,CONT_DIF_P
-V 7100,14700,CONT_DIF_P
-V 7700,14700,CONT_DIF_P
-V 7100,15100,CONT_DIF_P
-V 7100,14300,CONT_DIF_P
-V 8300,14300,CONT_DIF_P
-V 8900,14300,CONT_DIF_P
-V 8300,14700,CONT_DIF_P
-V 8900,14700,CONT_DIF_P
-V 8300,15100,CONT_DIF_P
-V 7700,15500,CONT_DIF_P
-V 7100,15500,CONT_DIF_P
-V 7100,19500,CONT_DIF_P
-V 7100,17900,CONT_DIF_P
-V 7700,17900,CONT_DIF_P
-V 7100,18300,CONT_DIF_P
-V 7700,18300,CONT_DIF_P
-V 7100,18700,CONT_DIF_P
-V 7100,19100,CONT_DIF_P
-V 7700,19100,CONT_DIF_P
-V 7700,19500,CONT_DIF_P
-V 7100,16300,CONT_DIF_P
-V 7100,15900,CONT_DIF_P
-V 7700,15900,CONT_DIF_P
-V 7100,17500,CONT_DIF_P
-V 7100,17100,CONT_DIF_P
-V 7100,16700,CONT_DIF_P
-V 7700,16700,CONT_DIF_P
-V 7700,17100,CONT_DIF_P
-V 8300,15500,CONT_DIF_P
-V 8900,15500,CONT_DIF_P
-V 8900,19500,CONT_DIF_P
-V 8300,18300,CONT_DIF_P
-V 8300,18700,CONT_DIF_P
-V 8300,19100,CONT_DIF_P
-V 8900,19100,CONT_DIF_P
-V 8300,19500,CONT_DIF_P
-V 8300,17500,CONT_DIF_P
-V 8300,17100,CONT_DIF_P
-V 8300,17900,CONT_DIF_P
-V 8900,17900,CONT_DIF_P
-V 8900,18300,CONT_DIF_P
-V 8300,16300,CONT_DIF_P
-V 8300,15900,CONT_DIF_P
-V 8900,15900,CONT_DIF_P
-V 8900,17100,CONT_DIF_P
-V 8900,16700,CONT_DIF_P
-V 8300,16700,CONT_DIF_P
-V 7700,15100,CONT_VIA
-V 8900,15100,CONT_VIA
-V 7700,17500,CONT_VIA
-V 7700,18700,CONT_VIA
-V 7700,16300,CONT_VIA
-V 8900,18700,CONT_VIA
-V 8900,17500,CONT_VIA
-V 8900,16300,CONT_VIA
-V 7100,19900,CONT_DIF_P
-V 8300,19900,CONT_DIF_P
-V 7700,19900,CONT_VIA
-V 8900,19900,CONT_VIA
-V 7100,20300,CONT_DIF_P
-V 8300,20300,CONT_DIF_P
-V 7700,20300,CONT_DIF_P
-V 8900,20300,CONT_DIF_P
-V 7700,20700,CONT_DIF_P
-V 8900,20700,CONT_DIF_P
-V 8300,20700,CONT_DIF_P
-V 7100,20700,CONT_DIF_P
-V 7100,21100,CONT_DIF_P
-V 8300,21100,CONT_DIF_P
-V 8900,21100,CONT_VIA
-V 7700,21100,CONT_VIA
-V 7100,21500,CONT_DIF_P
-V 7700,21500,CONT_DIF_P
-V 8300,21500,CONT_DIF_P
-V 8900,21500,CONT_DIF_P
-V 7700,24300,CONT_BODY_P
-V 8900,24300,CONT_BODY_P
-V 8800,23800,CONT_POLY
-V 7700,23800,CONT_VIA
-V 8800,23200,CONT_VIA
-V 8900,22500,CONT_BODY_N
-V 7700,22500,CONT_BODY_N
-V 8900,21900,CONT_DIF_P
-V 8300,21900,CONT_DIF_P
-V 7700,21900,CONT_DIF_P
-V 7100,21900,CONT_DIF_P
-V 4400,13600,CONT_BODY_N
-V 5300,13600,CONT_VIA
-V 4700,21900,CONT_DIF_P
-V 5300,21900,CONT_DIF_P
-V 5900,21900,CONT_DIF_P
-V 6500,21900,CONT_DIF_P
-V 5300,22500,CONT_BODY_N
-V 6500,22500,CONT_BODY_N
-V 5300,23800,CONT_VIA
-V 6400,23800,CONT_POLY
-V 6500,24300,CONT_BODY_P
-V 5300,24300,CONT_BODY_P
-V 6500,21500,CONT_DIF_P
-V 5900,21500,CONT_DIF_P
-V 5300,21500,CONT_DIF_P
-V 4700,21500,CONT_DIF_P
-V 5300,21100,CONT_VIA
-V 6500,21100,CONT_VIA
-V 5900,21100,CONT_DIF_P
-V 4700,21100,CONT_DIF_P
-V 4700,20700,CONT_DIF_P
-V 5900,20700,CONT_DIF_P
-V 6500,20700,CONT_DIF_P
-V 5300,20700,CONT_DIF_P
-V 6500,20300,CONT_DIF_P
-V 5300,20300,CONT_DIF_P
-V 5900,20300,CONT_DIF_P
-V 4700,20300,CONT_DIF_P
-V 6500,19900,CONT_VIA
-V 5300,19900,CONT_VIA
-V 5900,19900,CONT_DIF_P
-V 4700,19900,CONT_DIF_P
-V 6500,16300,CONT_VIA
-V 6500,17500,CONT_VIA
-V 6500,18700,CONT_VIA
-V 5300,16300,CONT_VIA
-V 5300,18700,CONT_VIA
-V 5300,17500,CONT_VIA
-V 6500,15100,CONT_VIA
-V 5300,15100,CONT_VIA
-V 5900,16700,CONT_DIF_P
-V 6500,16700,CONT_DIF_P
-V 6500,17100,CONT_DIF_P
-V 6500,15900,CONT_DIF_P
-V 5900,15900,CONT_DIF_P
-V 5900,16300,CONT_DIF_P
-V 6500,18300,CONT_DIF_P
-V 6500,17900,CONT_DIF_P
-V 5900,17900,CONT_DIF_P
-V 5900,17100,CONT_DIF_P
-V 5900,17500,CONT_DIF_P
-V 5900,19500,CONT_DIF_P
-V 6500,19100,CONT_DIF_P
-V 5900,19100,CONT_DIF_P
-V 5900,18700,CONT_DIF_P
-V 5900,18300,CONT_DIF_P
-V 6500,19500,CONT_DIF_P
-V 6500,15500,CONT_DIF_P
-V 5900,15500,CONT_DIF_P
-V 5300,17100,CONT_DIF_P
-V 5300,16700,CONT_DIF_P
-V 4700,16700,CONT_DIF_P
-V 4700,17100,CONT_DIF_P
-V 4700,17500,CONT_DIF_P
-V 5300,15900,CONT_DIF_P
-V 4700,15900,CONT_DIF_P
-V 4700,16300,CONT_DIF_P
-V 5300,19500,CONT_DIF_P
-V 5300,19100,CONT_DIF_P
-V 4700,19100,CONT_DIF_P
-V 4700,18700,CONT_DIF_P
-V 5300,18300,CONT_DIF_P
-V 4700,18300,CONT_DIF_P
-V 5300,17900,CONT_DIF_P
-V 4700,17900,CONT_DIF_P
-V 4700,19500,CONT_DIF_P
-V 4700,15500,CONT_DIF_P
-V 5300,15500,CONT_DIF_P
-V 5900,15100,CONT_DIF_P
-V 6500,14700,CONT_DIF_P
-V 5900,14700,CONT_DIF_P
-V 6500,14300,CONT_DIF_P
-V 5900,14300,CONT_DIF_P
-V 4700,14300,CONT_DIF_P
-V 4700,15100,CONT_DIF_P
-V 5300,14700,CONT_DIF_P
-V 4700,14700,CONT_DIF_P
-V 5300,14300,CONT_DIF_P
-V 5900,27400,CONT_DIF_N
-V 5900,27000,CONT_DIF_N
-V 5900,26600,CONT_DIF_N
-V 5900,27800,CONT_DIF_N
-V 5900,25000,CONT_DIF_N
-V 5900,25400,CONT_DIF_N
-V 5900,26200,CONT_DIF_N
-V 5900,25800,CONT_DIF_N
-V 4700,27000,CONT_DIF_N
-V 4700,26600,CONT_DIF_N
-V 4700,26200,CONT_DIF_N
-V 4700,25800,CONT_DIF_N
-V 4700,25400,CONT_DIF_N
-V 4700,27800,CONT_DIF_N
-V 4700,27400,CONT_DIF_N
-V 4700,25000,CONT_DIF_N
-V 4900,13600,CONT_BODY_N
-V 5300,28700,CONT_BODY_P
-V 6500,28700,CONT_BODY_P
-V 5300,26100,CONT_VIA
-V 5300,27700,CONT_VIA
-V 5300,25700,CONT_DIF_N
-V 5300,28100,CONT_DIF_N
-V 5300,26500,CONT_DIF_N
-V 5300,27300,CONT_DIF_N
-V 5300,26900,CONT_DIF_N
-V 5300,25300,CONT_DIF_N
-V 5300,24900,CONT_VIA
-V 6500,28100,CONT_VIA
-V 6500,24900,CONT_VIA
-V 6500,26500,CONT_VIA
-V 6500,25300,CONT_DIF_N
-V 6500,26900,CONT_DIF_N
-V 6500,27300,CONT_DIF_N
-V 6500,25700,CONT_DIF_N
-V 6500,26100,CONT_DIF_N
-V 6500,27700,CONT_DIF_N
-V 6500,13100,CONT_POLY
-V 6400,13600,CONT_BODY_N
-EOF
diff --git a/alliance/share/cells/padlib/palo_sp.ap b/alliance/share/cells/padlib/palo_sp.ap
deleted file mode 100644
index e80dbc87..00000000
--- a/alliance/share/cells/padlib/palo_sp.ap
+++ /dev/null
@@ -1,1512 +0,0 @@
-V ALLIANCE : 6
-H palo_sp,P,13/10/2000,100
-A 0,-700,17200,35600
-C 0,600,1200,ck,0,WEST,ALU2
-C 17200,600,1200,ck,1,EAST,ALU2
-C 0,8400,4000,vddi,0,WEST,ALU2
-C 0,4000,4000,vssi,0,WEST,ALU2
-C 17200,4000,4000,vssi,1,EAST,ALU2
-C 17200,8400,4000,vddi,1,EAST,ALU2
-C 0,16800,12000,vdde,0,WEST,ALU2
-C 17200,16800,12000,vdde,1,EAST,ALU2
-C 4700,-700,200,i,1,SOUTH,ALU2
-C 4700,-700,200,i,0,SOUTH,ALU1
-C 17200,29600,12000,vsse,1,EAST,ALU2
-C 0,29600,12000,vsse,0,WEST,ALU2
-S 15900,1600,16900,1600,200,*,LEFT,ALU1
-S 15800,24300,16400,24300,200,*,RIGHT,ALU1
-S 15800,24300,15800,28800,200,*,UP,ALU1
-S 16200,24300,16200,29300,600,*,UP,ALU1
-S 0,16800,17200,16800,12000,vdde,RIGHT,ALU2
-S 0,8400,17200,8400,4000,vddi,RIGHT,ALU2
-S 0,4000,17200,4000,4000,vssi,RIGHT,ALU2
-S 13500,22500,15900,22500,300,*,RIGHT,NTIE
-S 15700,23200,15700,23800,200,*,UP,ALU1
-S 15200,23800,15700,23800,300,*,RIGHT,POLY
-S 15200,23800,15200,24600,200,*,UP,POLY
-S 13700,24600,15500,24600,100,*,RIGHT,POLY
-S 15500,24300,15900,24300,300,*,RIGHT,PTIE
-S 13500,24300,14900,24300,300,*,RIGHT,PTIE
-S 15200,23700,15200,23900,200,*,DOWN,POLY
-S 13500,13600,14900,13600,200,*,RIGHT,ALU1
-S 13700,13900,15500,13900,100,*,RIGHT,POLY
-S 15200,13300,15200,13900,200,*,UP,POLY
-S 15500,13600,15900,13600,300,*,RIGHT,NTIE
-S 13500,13600,14900,13600,300,*,RIGHT,NTIE
-S 14800,13400,14800,22700,2800,*,UP,NWELL
-S 15500,13900,15500,22200,100,*,UP,PTRANS
-S 14900,13900,14900,22200,100,*,UP,PTRANS
-S 14300,13900,14300,22200,100,*,UP,PTRANS
-S 13700,13900,13700,22200,100,*,UP,PTRANS
-S 14000,14100,14000,22000,200,*,UP,PDIF
-S 14600,14100,14600,22000,200,*,UP,PDIF
-S 15200,14100,15200,22000,200,*,UP,PDIF
-S 15800,14100,15800,22000,300,*,UP,PDIF
-S 13500,28700,15900,28700,300,*,RIGHT,PTIE
-S 15500,24600,15500,28400,100,*,UP,NTRANS
-S 14900,24600,14900,28400,100,*,UP,NTRANS
-S 14300,24600,14300,28400,100,*,UP,NTRANS
-S 13700,24600,13700,28400,100,*,UP,NTRANS
-S 14000,24800,14000,28200,300,*,UP,NDIF
-S 14600,24800,14600,28200,300,*,UP,NDIF
-S 15200,24800,15200,28200,300,*,UP,NDIF
-S 15800,24800,15800,28200,300,*,UP,NDIF
-S 14600,23700,14600,28800,200,*,UP,ALU1
-S 15200,14200,15200,29100,200,*,UP,ALU1
-S 14000,14200,14000,29100,200,*,UP,ALU1
-S 11100,22500,13500,22500,300,*,RIGHT,NTIE
-S 13300,23200,13300,23800,200,*,UP,ALU1
-S 12800,23800,13300,23800,300,*,RIGHT,POLY
-S 12800,23800,12800,24600,200,*,UP,POLY
-S 11300,24600,13100,24600,100,*,RIGHT,POLY
-S 13100,24300,13500,24300,300,*,RIGHT,PTIE
-S 11100,24300,12500,24300,300,*,RIGHT,PTIE
-S 12800,23700,12800,23900,200,*,DOWN,POLY
-S 13100,13600,13500,13600,200,*,RIGHT,ALU1
-S 11100,13600,12500,13600,200,*,RIGHT,ALU1
-S 11300,13900,13100,13900,100,*,RIGHT,POLY
-S 12800,13300,12800,13900,200,*,UP,POLY
-S 13100,13600,13500,13600,300,*,RIGHT,NTIE
-S 11100,13600,12500,13600,300,*,RIGHT,NTIE
-S 12400,13400,12400,22700,2800,*,UP,NWELL
-S 13100,13900,13100,22200,100,*,UP,PTRANS
-S 12500,13900,12500,22200,100,*,UP,PTRANS
-S 11900,13900,11900,22200,100,*,UP,PTRANS
-S 11300,13900,11300,22200,100,*,UP,PTRANS
-S 11600,14100,11600,22000,200,*,UP,PDIF
-S 12200,14100,12200,22000,200,*,UP,PDIF
-S 12800,14100,12800,22000,200,*,UP,PDIF
-S 13400,14100,13400,22000,300,*,UP,PDIF
-S 11100,28700,13500,28700,300,*,RIGHT,PTIE
-S 13100,24600,13100,28400,100,*,UP,NTRANS
-S 12500,24600,12500,28400,100,*,UP,NTRANS
-S 11900,24600,11900,28400,100,*,UP,NTRANS
-S 11300,24600,11300,28400,100,*,UP,NTRANS
-S 11600,24800,11600,28200,300,*,UP,NDIF
-S 12200,24800,12200,28200,300,*,UP,NDIF
-S 12800,24800,12800,28200,300,*,UP,NDIF
-S 13400,24800,13400,28200,300,*,UP,NDIF
-S 12800,14200,12800,29100,200,*,UP,ALU1
-S 11600,14200,11600,29100,200,*,UP,ALU1
-S 8700,22500,11100,22500,300,*,RIGHT,NTIE
-S 10900,23200,10900,23800,200,*,UP,ALU1
-S 10400,23800,10900,23800,300,*,RIGHT,POLY
-S 10400,23800,10400,24600,200,*,UP,POLY
-S 8900,24600,10700,24600,100,*,RIGHT,POLY
-S 10700,24300,11100,24300,300,*,RIGHT,PTIE
-S 8700,24300,10100,24300,300,*,RIGHT,PTIE
-S 10400,23700,10400,23900,200,*,DOWN,POLY
-S 10700,13600,11100,13600,200,*,RIGHT,ALU1
-S 8700,13600,10100,13600,200,*,RIGHT,ALU1
-S 8900,13900,10700,13900,100,*,RIGHT,POLY
-S 10400,13300,10400,13900,200,*,UP,POLY
-S 10700,13600,11100,13600,300,*,RIGHT,NTIE
-S 8700,13600,10100,13600,300,*,RIGHT,NTIE
-S 10000,13400,10000,22700,2800,*,UP,NWELL
-S 10700,13900,10700,22200,100,*,UP,PTRANS
-S 10100,13900,10100,22200,100,*,UP,PTRANS
-S 9500,13900,9500,22200,100,*,UP,PTRANS
-S 8900,13900,8900,22200,100,*,UP,PTRANS
-S 9200,14100,9200,22000,200,*,UP,PDIF
-S 9800,14100,9800,22000,200,*,UP,PDIF
-S 10400,14100,10400,22000,200,*,UP,PDIF
-S 11000,14100,11000,22000,300,*,UP,PDIF
-S 8700,28700,11100,28700,300,*,RIGHT,PTIE
-S 10700,24600,10700,28400,100,*,UP,NTRANS
-S 10100,24600,10100,28400,100,*,UP,NTRANS
-S 9500,24600,9500,28400,100,*,UP,NTRANS
-S 8900,24600,8900,28400,100,*,UP,NTRANS
-S 9200,24800,9200,28200,300,*,UP,NDIF
-S 9800,24800,9800,28200,300,*,UP,NDIF
-S 10400,24800,10400,28200,300,*,UP,NDIF
-S 11000,24800,11000,28200,300,*,UP,NDIF
-S 10400,14200,10400,29100,200,*,UP,ALU1
-S 9200,14200,9200,29100,200,*,UP,ALU1
-S 6300,22500,8700,22500,300,*,RIGHT,NTIE
-S 8500,23200,8500,23800,200,*,UP,ALU1
-S 8000,23800,8500,23800,300,*,RIGHT,POLY
-S 8000,23800,8000,24600,200,*,UP,POLY
-S 6500,24600,8300,24600,100,*,RIGHT,POLY
-S 8300,24300,8700,24300,300,*,RIGHT,PTIE
-S 6300,24300,7700,24300,300,*,RIGHT,PTIE
-S 8000,23700,8000,23900,200,*,DOWN,POLY
-S 8300,13600,8700,13600,200,*,RIGHT,ALU1
-S 6300,13600,7700,13600,200,*,RIGHT,ALU1
-S 6500,13900,8300,13900,100,*,RIGHT,POLY
-S 8000,13300,8000,13900,200,*,UP,POLY
-S 8300,13600,8700,13600,300,*,RIGHT,NTIE
-S 6300,13600,7700,13600,300,*,RIGHT,NTIE
-S 7600,13400,7600,22700,2800,*,UP,NWELL
-S 8300,13900,8300,22200,100,*,UP,PTRANS
-S 7700,13900,7700,22200,100,*,UP,PTRANS
-S 7100,13900,7100,22200,100,*,UP,PTRANS
-S 6500,13900,6500,22200,100,*,UP,PTRANS
-S 6800,14100,6800,22000,200,*,UP,PDIF
-S 7400,14100,7400,22000,200,*,UP,PDIF
-S 8000,14100,8000,22000,200,*,UP,PDIF
-S 8600,14100,8600,22000,300,*,UP,PDIF
-S 6300,28700,8700,28700,300,*,RIGHT,PTIE
-S 8300,24600,8300,28400,100,*,UP,NTRANS
-S 7700,24600,7700,28400,100,*,UP,NTRANS
-S 7100,24600,7100,28400,100,*,UP,NTRANS
-S 6500,24600,6500,28400,100,*,UP,NTRANS
-S 6800,24800,6800,28200,300,*,UP,NDIF
-S 7400,24800,7400,28200,300,*,UP,NDIF
-S 8000,24800,8000,28200,300,*,UP,NDIF
-S 8600,24800,8600,28200,300,*,UP,NDIF
-S 8000,14200,8000,29100,200,*,UP,ALU1
-S 6800,14200,6800,29100,200,*,UP,ALU1
-S 3900,22500,6300,22500,300,*,RIGHT,NTIE
-S 6100,23200,6100,23800,200,*,UP,ALU1
-S 5600,23800,6100,23800,300,*,RIGHT,POLY
-S 5600,23800,5600,24600,200,*,UP,POLY
-S 4100,24600,5900,24600,100,*,RIGHT,POLY
-S 5900,24300,6300,24300,300,*,RIGHT,PTIE
-S 3900,24300,5300,24300,300,*,RIGHT,PTIE
-S 5600,23700,5600,23900,200,*,DOWN,POLY
-S 5900,13600,6300,13600,200,*,RIGHT,ALU1
-S 3900,13600,5300,13600,200,*,RIGHT,ALU1
-S 4100,13900,5900,13900,100,*,RIGHT,POLY
-S 5600,13300,5600,13900,200,*,UP,POLY
-S 5900,13600,6300,13600,300,*,RIGHT,NTIE
-S 3900,13600,5300,13600,300,*,RIGHT,NTIE
-S 5200,13400,5200,22700,2800,*,UP,NWELL
-S 5900,13900,5900,22200,100,*,UP,PTRANS
-S 5300,13900,5300,22200,100,*,UP,PTRANS
-S 4700,13900,4700,22200,100,*,UP,PTRANS
-S 4100,13900,4100,22200,100,*,UP,PTRANS
-S 4400,14100,4400,22000,200,*,UP,PDIF
-S 5000,14100,5000,22000,200,*,UP,PDIF
-S 5600,14100,5600,22000,200,*,UP,PDIF
-S 6200,14100,6200,22000,300,*,UP,PDIF
-S 3900,28700,6300,28700,300,*,RIGHT,PTIE
-S 5900,24600,5900,28400,100,*,UP,NTRANS
-S 5300,24600,5300,28400,100,*,UP,NTRANS
-S 4700,24600,4700,28400,100,*,UP,NTRANS
-S 4100,24600,4100,28400,100,*,UP,NTRANS
-S 4400,24800,4400,28200,300,*,UP,NDIF
-S 5000,24800,5000,28200,300,*,UP,NDIF
-S 5600,24800,5600,28200,300,*,UP,NDIF
-S 6200,24800,6200,28200,300,*,UP,NDIF
-S 5000,23700,5000,28800,200,*,UP,ALU1
-S 5600,14200,5600,29100,200,*,UP,ALU1
-S 4400,14200,4400,29100,200,*,UP,ALU1
-S 1500,22500,3900,22500,300,*,RIGHT,NTIE
-S 3700,23200,3700,23800,200,*,UP,ALU1
-S 3200,23800,3700,23800,300,*,RIGHT,POLY
-S 3200,23800,3200,24600,200,*,UP,POLY
-S 1700,24600,3500,24600,100,*,RIGHT,POLY
-S 3500,24300,3900,24300,300,*,RIGHT,PTIE
-S 1500,24300,2900,24300,300,*,RIGHT,PTIE
-S 3200,23700,3200,23900,200,*,DOWN,POLY
-S 3500,13600,3900,13600,200,*,RIGHT,ALU1
-S 1500,13600,2900,13600,200,*,RIGHT,ALU1
-S 1700,13900,3500,13900,100,*,RIGHT,POLY
-S 3200,13300,3200,13900,200,*,UP,POLY
-S 3500,13600,3900,13600,300,*,RIGHT,NTIE
-S 1500,13600,2900,13600,300,*,RIGHT,NTIE
-S 2800,13400,2800,22700,2800,*,UP,NWELL
-S 3500,13900,3500,22200,100,*,UP,PTRANS
-S 2900,13900,2900,22200,100,*,UP,PTRANS
-S 2300,13900,2300,22200,100,*,UP,PTRANS
-S 1700,13900,1700,22200,100,*,UP,PTRANS
-S 2000,14100,2000,22000,200,*,UP,PDIF
-S 2600,14100,2600,22000,200,*,UP,PDIF
-S 3200,14100,3200,22000,200,*,UP,PDIF
-S 3800,14100,3800,22000,300,*,UP,PDIF
-S 1500,28700,3900,28700,300,*,RIGHT,PTIE
-S 3500,24600,3500,28400,100,*,UP,NTRANS
-S 2900,24600,2900,28400,100,*,UP,NTRANS
-S 2300,24600,2300,28400,100,*,UP,NTRANS
-S 1700,24600,1700,28400,100,*,UP,NTRANS
-S 2000,24800,2000,28200,300,*,UP,NDIF
-S 2600,24800,2600,28200,300,*,UP,NDIF
-S 3200,24800,3200,28200,300,*,UP,NDIF
-S 3800,24800,3800,28200,300,*,UP,NDIF
-S 2600,23700,2600,28800,200,*,UP,ALU1
-S 3200,14200,3200,29100,200,*,UP,ALU1
-S 2000,14200,2000,29100,200,*,UP,ALU1
-S 3800,-300,3800,4100,700,*,UP,ALU1
-S 3500,4000,4300,4000,300,*,RIGHT,PTIE
-S 3800,5000,3800,12100,700,*,UP,ALU1
-S 3500,5100,4300,5100,300,*,RIGHT,NTIE
-S 3600,5000,3600,12100,300,*,UP,NTIE
-S 3600,-300,3600,4100,300,*,UP,PTIE
-S 4200,600,4200,3500,300,*,UP,NDIF
-S 100,600,17200,600,1200,ck,RIGHT,ALU2
-S 5400,4600,7100,4600,200,*,RIGHT,ALU1
-S 5400,900,5400,11400,200,*,UP,ALU1
-S 4800,900,4800,11400,200,*,UP,ALU1
-S 7800,600,7800,3300,200,*,UP,ALU1
-S 4200,5000,4200,12100,200,*,UP,ALU1
-S 4200,-300,4200,4100,200,*,UP,ALU1
-S 7200,3700,7200,5400,200,*,UP,POLY
-S 6300,5400,8100,5400,100,*,RIGHT,POLY
-S 6300,3700,8100,3700,100,*,RIGHT,POLY
-S 5000,5300,5700,5300,300,*,RIGHT,POLY
-S 5700,3700,5700,5400,100,*,UP,POLY
-S 4500,3700,4500,5400,100,*,UP,POLY
-S 5900,4000,6900,4000,300,*,RIGHT,PTIE
-S 5900,5100,6900,5100,300,*,RIGHT,NTIE
-S 6600,5600,6600,11500,300,*,UP,PDIF
-S 8400,5600,8400,11500,300,*,UP,PDIF
-S 7200,5600,7200,11500,300,*,UP,PDIF
-S 8100,5400,8100,11700,100,*,UP,PTRANS
-S 7500,5400,7500,11700,100,*,UP,PTRANS
-S 6300,5400,6300,11700,100,*,UP,PTRANS
-S 6000,5600,6000,11500,300,*,UP,PDIF
-S 5700,5400,5700,11700,100,*,UP,PTRANS
-S 5400,5600,5400,11500,300,*,UP,PDIF
-S 7800,5600,7800,11500,300,*,UP,PDIF
-S 6900,5400,6900,11700,100,*,UP,PTRANS
-S 4800,5600,4800,11500,300,*,UP,PDIF
-S 4500,5400,4500,11700,100,*,UP,PTRANS
-S 4200,5600,4200,11500,300,*,UP,PDIF
-S 7800,600,7800,3500,300,*,UP,NDIF
-S 6600,600,6600,3500,300,*,UP,NDIF
-S 8400,600,8400,3500,200,*,UP,NDIF
-S 7200,600,7200,3500,200,*,UP,NDIF
-S 8100,400,8100,3700,100,*,UP,NTRANS
-S 7500,400,7500,3700,100,*,UP,NTRANS
-S 6900,400,6900,3700,100,*,UP,NTRANS
-S 6300,400,6300,3700,100,*,UP,NTRANS
-S 6000,600,6000,3500,200,*,UP,NDIF
-S 5700,400,5700,3700,100,*,UP,NTRANS
-S 5400,600,5400,3500,300,*,UP,NDIF
-S 4800,600,4800,3500,300,*,UP,NDIF
-S 4500,400,4500,3700,100,*,UP,NTRANS
-S 4200,600,4200,3500,200,*,UP,NDIF
-S 4500,200,4500,400,100,*,UP,POLY
-S 4700,-700,4700,300,200,*,UP,ALU1
-S 6600,600,6600,3300,200,*,UP,ALU1
-S 6000,5100,6900,5100,200,*,RIGHT,ALU1
-S 8400,600,8400,3500,300,*,UP,NDIF
-S 9000,5000,9000,12100,300,*,UP,NTIE
-S 9000,-300,9000,4100,300,*,UP,PTIE
-S 3500,-200,9100,-200,300,*,RIGHT,PTIE
-S 7500,4000,9100,4000,300,*,RIGHT,PTIE
-S 7500,5100,9100,5100,300,*,RIGHT,NTIE
-S 3400,8600,9200,8600,7200,*,RIGHT,NWELL
-S 3400,5100,9200,5100,400,*,RIGHT,NWELL
-S 3500,12000,9000,12000,300,*,RIGHT,NTIE
-S 8600,30100,8600,35600,12600,*,UP,ALU1
-S 15800,28900,15800,29300,200,*,UP,ALU1
-S 1900,29600,15300,29600,900,*,RIGHT,ALU1
-S 1100,24200,1100,29300,800,*,UP,ALU1
-S 700,28000,700,28800,100,*,UP,ALU1
-S 1100,13500,1100,22600,800,*,UP,ALU1
-S 16400,24200,16400,28800,300,*,UP,PTIE
-S 16000,28700,16500,28700,300,*,RIGHT,PTIE
-S 15900,24300,16500,24300,300,*,RIGHT,PTIE
-S 700,28700,1500,28700,300,*,RIGHT,PTIE
-S 800,24200,800,28800,300,*,UP,PTIE
-S 700,24300,1500,24300,300,*,RIGHT,PTIE
-S 15900,22500,16500,22500,300,*,RIGHT,NTIE
-S 800,22500,1400,22500,300,*,RIGHT,NTIE
-S 15900,13600,16500,13600,300,*,RIGHT,NTIE
-S 16400,13500,16400,22600,300,*,UP,NTIE
-S 800,13600,1400,13600,300,*,RIGHT,NTIE
-S 800,13600,800,22600,300,*,UP,NTIE
-S 1400,14100,1400,22000,300,*,UP,PDIF
-S 1400,24900,1400,28200,300,*,UP,NDIF
-S 16300,13400,16300,22700,600,*,UP,NWELL
-S 1000,13400,1000,22700,800,*,UP,NWELL
-S 16900,1600,16900,23300,200,*,UP,ALU1
-S 0,29600,17200,29600,12000,vsse,RIGHT,ALU2
-S 16300,23200,16900,23200,200,*,RIGHT,ALU1
-S 7200,-200,7200,3200,200,*,UP,ALU1
-S 9000,-200,9000,4100,200,*,UP,ALU1
-S 8400,-200,8400,4100,200,*,UP,ALU1
-S 7200,5800,7200,12000,200,*,UP,ALU1
-S 8400,5100,8400,12000,200,*,UP,ALU1
-S 9000,5200,9000,12100,200,*,UP,ALU1
-S 7500,5100,9000,5100,200,*,RIGHT,ALU1
-S 3500,5100,4200,5100,200,*,RIGHT,ALU1
-S 6000,5100,6000,12000,200,*,UP,ALU1
-S 7400,13600,7400,22600,200,*,UP,ALU1
-S 6200,13700,6200,22600,200,*,UP,ALU1
-S 5000,13600,5000,22600,200,*,UP,ALU1
-S 3800,13600,3800,22600,200,*,UP,ALU1
-S 2600,13600,2600,22600,200,*,UP,ALU1
-S 8600,13600,8600,22600,200,*,UP,ALU1
-S 9800,13700,9800,22600,200,*,UP,ALU1
-S 11000,13600,11000,22600,200,*,UP,ALU1
-S 12200,13700,12200,22600,200,*,UP,ALU1
-S 13400,13600,13400,22600,200,*,UP,ALU1
-S 14600,13600,14600,22600,200,*,UP,ALU1
-S 16200,13600,16200,22600,600,*,UP,ALU1
-S 15800,13700,15800,22600,200,*,UP,ALU1
-S 15500,13600,16400,13600,200,*,RIGHT,ALU1
-S 3100,13100,16900,13100,200,*,RIGHT,ALU1
-S 7800,5800,7800,13100,200,*,UP,ALU1
-S 6600,5800,6600,13000,200,*,UP,ALU1
-S 3500,12000,6000,12000,200,*,RIGHT,ALU1
-S 13400,24300,13400,28800,200,*,UP,ALU1
-S 12200,23800,12200,28800,200,*,UP,ALU1
-S 11000,24300,11000,28800,200,*,UP,ALU1
-S 9800,23800,9800,28800,200,*,UP,ALU1
-S 8600,24300,8600,28800,200,*,UP,ALU1
-S 7400,23900,7400,28800,200,*,UP,ALU1
-S 6200,24300,6200,28800,200,*,UP,ALU1
-S 3800,24400,3800,28800,200,*,UP,ALU1
-S 6000,4000,9100,4000,200,*,RIGHT,ALU1
-S 6000,-200,6000,4000,200,*,UP,ALU1
-S 5200,-200,9000,-200,200,*,RIGHT,ALU1
-S 6600,1600,16900,1600,200,*,RIGHT,ALU2
-S 3700,23200,16900,23200,200,*,RIGHT,ALU2
-V 15900,1600,CONT_VIA,*
-V 16400,1600,CONT_VIA,*
-V 14000,21900,CONT_DIF_P,*
-V 14600,21900,CONT_DIF_P,*
-V 15200,21900,CONT_DIF_P,*
-V 15800,21900,CONT_DIF_P,*
-V 14600,22500,CONT_BODY_N,*
-V 15800,22500,CONT_BODY_N,*
-V 15700,23200,CONT_VIA,*
-V 14600,23800,CONT_VIA,*
-V 15700,23800,CONT_POLY,*
-V 15800,24300,CONT_BODY_P,*
-V 14600,24300,CONT_BODY_P,*
-V 15800,21500,CONT_DIF_P,*
-V 15200,21500,CONT_DIF_P,*
-V 14600,21500,CONT_DIF_P,*
-V 14000,21500,CONT_DIF_P,*
-V 14600,21100,CONT_VIA,*
-V 15200,21100,CONT_DIF_P,*
-V 14000,21100,CONT_DIF_P,*
-V 14000,20700,CONT_DIF_P,*
-V 15200,20700,CONT_DIF_P,*
-V 15800,20700,CONT_DIF_P,*
-V 14600,20700,CONT_DIF_P,*
-V 15800,20300,CONT_DIF_P,*
-V 14600,20300,CONT_DIF_P,*
-V 15200,20300,CONT_DIF_P,*
-V 14000,20300,CONT_DIF_P,*
-V 14600,19900,CONT_VIA,*
-V 15200,19900,CONT_DIF_P,*
-V 14000,19900,CONT_DIF_P,*
-V 14600,16300,CONT_VIA,*
-V 14600,18700,CONT_VIA,*
-V 14600,17500,CONT_VIA,*
-V 14600,15100,CONT_VIA,*
-V 15200,16700,CONT_DIF_P,*
-V 15800,16700,CONT_DIF_P,*
-V 15800,17100,CONT_DIF_P,*
-V 15800,15900,CONT_DIF_P,*
-V 15200,15900,CONT_DIF_P,*
-V 15200,16300,CONT_DIF_P,*
-V 15800,18300,CONT_DIF_P,*
-V 15800,17900,CONT_DIF_P,*
-V 15200,17900,CONT_DIF_P,*
-V 15200,17100,CONT_DIF_P,*
-V 15200,17500,CONT_DIF_P,*
-V 15200,19500,CONT_DIF_P,*
-V 15800,19100,CONT_DIF_P,*
-V 15200,19100,CONT_DIF_P,*
-V 15200,18700,CONT_DIF_P,*
-V 15200,18300,CONT_DIF_P,*
-V 15800,19500,CONT_DIF_P,*
-V 15800,15500,CONT_DIF_P,*
-V 15200,15500,CONT_DIF_P,*
-V 14600,17100,CONT_DIF_P,*
-V 14600,16700,CONT_DIF_P,*
-V 14000,16700,CONT_DIF_P,*
-V 14000,17100,CONT_DIF_P,*
-V 14000,17500,CONT_DIF_P,*
-V 14600,15900,CONT_DIF_P,*
-V 14000,15900,CONT_DIF_P,*
-V 14000,16300,CONT_DIF_P,*
-V 14600,19500,CONT_DIF_P,*
-V 14600,19100,CONT_DIF_P,*
-V 14000,19100,CONT_DIF_P,*
-V 14000,18700,CONT_DIF_P,*
-V 14600,18300,CONT_DIF_P,*
-V 14000,18300,CONT_DIF_P,*
-V 14600,17900,CONT_DIF_P,*
-V 14000,17900,CONT_DIF_P,*
-V 14000,19500,CONT_DIF_P,*
-V 14000,15500,CONT_DIF_P,*
-V 14600,15500,CONT_DIF_P,*
-V 15200,15100,CONT_DIF_P,*
-V 15800,14700,CONT_DIF_P,*
-V 15200,14700,CONT_DIF_P,*
-V 15800,14300,CONT_DIF_P,*
-V 15200,14300,CONT_DIF_P,*
-V 14000,14300,CONT_DIF_P,*
-V 14000,15100,CONT_DIF_P,*
-V 14600,14700,CONT_DIF_P,*
-V 14000,14700,CONT_DIF_P,*
-V 14600,14300,CONT_DIF_P,*
-V 15200,27400,CONT_DIF_N,*
-V 15200,27000,CONT_DIF_N,*
-V 15200,26600,CONT_DIF_N,*
-V 15200,27800,CONT_DIF_N,*
-V 15200,25000,CONT_DIF_N,*
-V 15200,25400,CONT_DIF_N,*
-V 15200,26200,CONT_DIF_N,*
-V 15200,25800,CONT_DIF_N,*
-V 14000,27000,CONT_DIF_N,*
-V 14000,26600,CONT_DIF_N,*
-V 14000,26200,CONT_DIF_N,*
-V 14000,25800,CONT_DIF_N,*
-V 14000,25400,CONT_DIF_N,*
-V 14000,27800,CONT_DIF_N,*
-V 14000,27400,CONT_DIF_N,*
-V 14000,25000,CONT_DIF_N,*
-V 14500,13600,CONT_VIA,*
-V 15200,13100,CONT_POLY,*
-V 15600,13600,CONT_BODY_N,*
-V 14200,13600,CONT_BODY_N,*
-V 14800,13600,CONT_BODY_N,*
-V 13700,13600,CONT_BODY_N,*
-V 14600,28700,CONT_BODY_P,*
-V 15800,28700,CONT_BODY_P,*
-V 14600,26100,CONT_VIA,*
-V 14600,27700,CONT_VIA,*
-V 14600,25700,CONT_DIF_N,*
-V 14600,28100,CONT_DIF_N,*
-V 14600,26500,CONT_DIF_N,*
-V 14600,27300,CONT_DIF_N,*
-V 14600,26900,CONT_DIF_N,*
-V 14600,25300,CONT_DIF_N,*
-V 14600,24900,CONT_VIA,*
-V 15800,28100,CONT_VIA,*
-V 15800,24900,CONT_VIA,*
-V 15800,26500,CONT_VIA,*
-V 15800,25300,CONT_DIF_N,*
-V 15800,26900,CONT_DIF_N,*
-V 15800,27300,CONT_DIF_N,*
-V 15800,25700,CONT_DIF_N,*
-V 15800,26100,CONT_DIF_N,*
-V 15800,27700,CONT_DIF_N,*
-V 11600,21900,CONT_DIF_P,*
-V 12200,21900,CONT_DIF_P,*
-V 12800,21900,CONT_DIF_P,*
-V 13400,21900,CONT_DIF_P,*
-V 12200,22500,CONT_BODY_N,*
-V 13400,22500,CONT_BODY_N,*
-V 13300,23200,CONT_VIA,*
-V 12200,23800,CONT_VIA,*
-V 13300,23800,CONT_POLY,*
-V 13400,24300,CONT_BODY_P,*
-V 12200,24300,CONT_BODY_P,*
-V 13400,21500,CONT_DIF_P,*
-V 12800,21500,CONT_DIF_P,*
-V 12200,21500,CONT_DIF_P,*
-V 11600,21500,CONT_DIF_P,*
-V 12200,21100,CONT_VIA,*
-V 13400,21100,CONT_VIA,*
-V 12800,21100,CONT_DIF_P,*
-V 11600,21100,CONT_DIF_P,*
-V 11600,20700,CONT_DIF_P,*
-V 12800,20700,CONT_DIF_P,*
-V 13400,20700,CONT_DIF_P,*
-V 12200,20700,CONT_DIF_P,*
-V 13400,20300,CONT_DIF_P,*
-V 12200,20300,CONT_DIF_P,*
-V 12800,20300,CONT_DIF_P,*
-V 11600,20300,CONT_DIF_P,*
-V 13400,19900,CONT_VIA,*
-V 12200,19900,CONT_VIA,*
-V 12800,19900,CONT_DIF_P,*
-V 11600,19900,CONT_DIF_P,*
-V 13400,16300,CONT_VIA,*
-V 13400,17500,CONT_VIA,*
-V 13400,18700,CONT_VIA,*
-V 12200,16300,CONT_VIA,*
-V 12200,18700,CONT_VIA,*
-V 12200,17500,CONT_VIA,*
-V 13400,15100,CONT_VIA,*
-V 12200,15100,CONT_VIA,*
-V 12800,16700,CONT_DIF_P,*
-V 13400,16700,CONT_DIF_P,*
-V 13400,17100,CONT_DIF_P,*
-V 13400,15900,CONT_DIF_P,*
-V 12800,15900,CONT_DIF_P,*
-V 12800,16300,CONT_DIF_P,*
-V 13400,18300,CONT_DIF_P,*
-V 13400,17900,CONT_DIF_P,*
-V 12800,17900,CONT_DIF_P,*
-V 12800,17100,CONT_DIF_P,*
-V 12800,17500,CONT_DIF_P,*
-V 12800,19500,CONT_DIF_P,*
-V 13400,19100,CONT_DIF_P,*
-V 12800,19100,CONT_DIF_P,*
-V 12800,18700,CONT_DIF_P,*
-V 12800,18300,CONT_DIF_P,*
-V 13400,19500,CONT_DIF_P,*
-V 13400,15500,CONT_DIF_P,*
-V 12800,15500,CONT_DIF_P,*
-V 12200,17100,CONT_DIF_P,*
-V 12200,16700,CONT_DIF_P,*
-V 11600,16700,CONT_DIF_P,*
-V 11600,17100,CONT_DIF_P,*
-V 11600,17500,CONT_DIF_P,*
-V 12200,15900,CONT_DIF_P,*
-V 11600,15900,CONT_DIF_P,*
-V 11600,16300,CONT_DIF_P,*
-V 12200,19500,CONT_DIF_P,*
-V 12200,19100,CONT_DIF_P,*
-V 11600,19100,CONT_DIF_P,*
-V 11600,18700,CONT_DIF_P,*
-V 12200,18300,CONT_DIF_P,*
-V 11600,18300,CONT_DIF_P,*
-V 12200,17900,CONT_DIF_P,*
-V 11600,17900,CONT_DIF_P,*
-V 11600,19500,CONT_DIF_P,*
-V 11600,15500,CONT_DIF_P,*
-V 12200,15500,CONT_DIF_P,*
-V 12800,15100,CONT_DIF_P,*
-V 13400,14700,CONT_DIF_P,*
-V 12800,14700,CONT_DIF_P,*
-V 13400,14300,CONT_DIF_P,*
-V 12800,14300,CONT_DIF_P,*
-V 11600,14300,CONT_DIF_P,*
-V 11600,15100,CONT_DIF_P,*
-V 12200,14700,CONT_DIF_P,*
-V 11600,14700,CONT_DIF_P,*
-V 12200,14300,CONT_DIF_P,*
-V 12800,27400,CONT_DIF_N,*
-V 12800,27000,CONT_DIF_N,*
-V 12800,26600,CONT_DIF_N,*
-V 12800,27800,CONT_DIF_N,*
-V 12800,25000,CONT_DIF_N,*
-V 12800,25400,CONT_DIF_N,*
-V 12800,26200,CONT_DIF_N,*
-V 12800,25800,CONT_DIF_N,*
-V 11600,27000,CONT_DIF_N,*
-V 11600,26600,CONT_DIF_N,*
-V 11600,26200,CONT_DIF_N,*
-V 11600,25800,CONT_DIF_N,*
-V 11600,25400,CONT_DIF_N,*
-V 11600,27800,CONT_DIF_N,*
-V 11600,27400,CONT_DIF_N,*
-V 11600,25000,CONT_DIF_N,*
-V 12100,13600,CONT_VIA,*
-V 12800,13100,CONT_POLY,*
-V 13200,13600,CONT_BODY_N,*
-V 11800,13600,CONT_BODY_N,*
-V 12400,13600,CONT_BODY_N,*
-V 11300,13600,CONT_BODY_N,*
-V 12200,28700,CONT_BODY_P,*
-V 13400,28700,CONT_BODY_P,*
-V 12200,26100,CONT_VIA,*
-V 12200,27700,CONT_VIA,*
-V 12200,25700,CONT_DIF_N,*
-V 12200,28100,CONT_DIF_N,*
-V 12200,26500,CONT_DIF_N,*
-V 12200,27300,CONT_DIF_N,*
-V 12200,26900,CONT_DIF_N,*
-V 12200,25300,CONT_DIF_N,*
-V 12200,24900,CONT_VIA,*
-V 13400,28100,CONT_VIA,*
-V 13400,24900,CONT_VIA,*
-V 13400,26500,CONT_VIA,*
-V 13400,25300,CONT_DIF_N,*
-V 13400,26900,CONT_DIF_N,*
-V 13400,27300,CONT_DIF_N,*
-V 13400,25700,CONT_DIF_N,*
-V 13400,26100,CONT_DIF_N,*
-V 13400,27700,CONT_DIF_N,*
-V 9200,21900,CONT_DIF_P,*
-V 9800,21900,CONT_DIF_P,*
-V 10400,21900,CONT_DIF_P,*
-V 11000,21900,CONT_DIF_P,*
-V 9800,22500,CONT_BODY_N,*
-V 11000,22500,CONT_BODY_N,*
-V 10900,23200,CONT_VIA,*
-V 9800,23800,CONT_VIA,*
-V 10900,23800,CONT_POLY,*
-V 11000,24300,CONT_BODY_P,*
-V 9800,24300,CONT_BODY_P,*
-V 11000,21500,CONT_DIF_P,*
-V 10400,21500,CONT_DIF_P,*
-V 9800,21500,CONT_DIF_P,*
-V 9200,21500,CONT_DIF_P,*
-V 9800,21100,CONT_VIA,*
-V 11000,21100,CONT_VIA,*
-V 10400,21100,CONT_DIF_P,*
-V 9200,21100,CONT_DIF_P,*
-V 9200,20700,CONT_DIF_P,*
-V 10400,20700,CONT_DIF_P,*
-V 11000,20700,CONT_DIF_P,*
-V 9800,20700,CONT_DIF_P,*
-V 11000,20300,CONT_DIF_P,*
-V 9800,20300,CONT_DIF_P,*
-V 10400,20300,CONT_DIF_P,*
-V 9200,20300,CONT_DIF_P,*
-V 11000,19900,CONT_VIA,*
-V 9800,19900,CONT_VIA,*
-V 10400,19900,CONT_DIF_P,*
-V 9200,19900,CONT_DIF_P,*
-V 11000,16300,CONT_VIA,*
-V 11000,17500,CONT_VIA,*
-V 11000,18700,CONT_VIA,*
-V 9800,16300,CONT_VIA,*
-V 9800,18700,CONT_VIA,*
-V 9800,17500,CONT_VIA,*
-V 11000,15100,CONT_VIA,*
-V 9800,15100,CONT_VIA,*
-V 10400,16700,CONT_DIF_P,*
-V 11000,16700,CONT_DIF_P,*
-V 11000,17100,CONT_DIF_P,*
-V 11000,15900,CONT_DIF_P,*
-V 10400,15900,CONT_DIF_P,*
-V 10400,16300,CONT_DIF_P,*
-V 11000,18300,CONT_DIF_P,*
-V 11000,17900,CONT_DIF_P,*
-V 10400,17900,CONT_DIF_P,*
-V 10400,17100,CONT_DIF_P,*
-V 10400,17500,CONT_DIF_P,*
-V 10400,19500,CONT_DIF_P,*
-V 11000,19100,CONT_DIF_P,*
-V 10400,19100,CONT_DIF_P,*
-V 10400,18700,CONT_DIF_P,*
-V 10400,18300,CONT_DIF_P,*
-V 11000,19500,CONT_DIF_P,*
-V 11000,15500,CONT_DIF_P,*
-V 10400,15500,CONT_DIF_P,*
-V 9800,17100,CONT_DIF_P,*
-V 9800,16700,CONT_DIF_P,*
-V 9200,16700,CONT_DIF_P,*
-V 9200,17100,CONT_DIF_P,*
-V 9200,17500,CONT_DIF_P,*
-V 9800,15900,CONT_DIF_P,*
-V 9200,15900,CONT_DIF_P,*
-V 9200,16300,CONT_DIF_P,*
-V 9800,19500,CONT_DIF_P,*
-V 9800,19100,CONT_DIF_P,*
-V 9200,19100,CONT_DIF_P,*
-V 9200,18700,CONT_DIF_P,*
-V 9800,18300,CONT_DIF_P,*
-V 9200,18300,CONT_DIF_P,*
-V 9800,17900,CONT_DIF_P,*
-V 9200,17900,CONT_DIF_P,*
-V 9200,19500,CONT_DIF_P,*
-V 9200,15500,CONT_DIF_P,*
-V 9800,15500,CONT_DIF_P,*
-V 10400,15100,CONT_DIF_P,*
-V 11000,14700,CONT_DIF_P,*
-V 10400,14700,CONT_DIF_P,*
-V 11000,14300,CONT_DIF_P,*
-V 10400,14300,CONT_DIF_P,*
-V 9200,14300,CONT_DIF_P,*
-V 9200,15100,CONT_DIF_P,*
-V 9800,14700,CONT_DIF_P,*
-V 9200,14700,CONT_DIF_P,*
-V 9800,14300,CONT_DIF_P,*
-V 10400,27400,CONT_DIF_N,*
-V 10400,27000,CONT_DIF_N,*
-V 10400,26600,CONT_DIF_N,*
-V 10400,27800,CONT_DIF_N,*
-V 10400,25000,CONT_DIF_N,*
-V 10400,25400,CONT_DIF_N,*
-V 10400,26200,CONT_DIF_N,*
-V 10400,25800,CONT_DIF_N,*
-V 9200,27000,CONT_DIF_N,*
-V 9200,26600,CONT_DIF_N,*
-V 9200,26200,CONT_DIF_N,*
-V 9200,25800,CONT_DIF_N,*
-V 9200,25400,CONT_DIF_N,*
-V 9200,27800,CONT_DIF_N,*
-V 9200,27400,CONT_DIF_N,*
-V 9200,25000,CONT_DIF_N,*
-V 9700,13600,CONT_VIA,*
-V 10400,13100,CONT_POLY,*
-V 10800,13600,CONT_BODY_N,*
-V 9400,13600,CONT_BODY_N,*
-V 10000,13600,CONT_BODY_N,*
-V 8900,13600,CONT_BODY_N,*
-V 9800,28700,CONT_BODY_P,*
-V 11000,28700,CONT_BODY_P,*
-V 9800,26100,CONT_VIA,*
-V 9800,27700,CONT_VIA,*
-V 9800,25700,CONT_DIF_N,*
-V 9800,28100,CONT_DIF_N,*
-V 9800,26500,CONT_DIF_N,*
-V 9800,27300,CONT_DIF_N,*
-V 9800,26900,CONT_DIF_N,*
-V 9800,25300,CONT_DIF_N,*
-V 9800,24900,CONT_VIA,*
-V 11000,28100,CONT_VIA,*
-V 11000,24900,CONT_VIA,*
-V 11000,26500,CONT_VIA,*
-V 11000,25300,CONT_DIF_N,*
-V 11000,26900,CONT_DIF_N,*
-V 11000,27300,CONT_DIF_N,*
-V 11000,25700,CONT_DIF_N,*
-V 11000,26100,CONT_DIF_N,*
-V 11000,27700,CONT_DIF_N,*
-V 6800,21900,CONT_DIF_P,*
-V 7400,21900,CONT_DIF_P,*
-V 8000,21900,CONT_DIF_P,*
-V 8600,21900,CONT_DIF_P,*
-V 7400,22500,CONT_BODY_N,*
-V 8600,22500,CONT_BODY_N,*
-V 8500,23200,CONT_VIA,*
-V 7400,23800,CONT_VIA,*
-V 8500,23800,CONT_POLY,*
-V 8600,24300,CONT_BODY_P,*
-V 7400,24300,CONT_BODY_P,*
-V 8600,21500,CONT_DIF_P,*
-V 8000,21500,CONT_DIF_P,*
-V 7400,21500,CONT_DIF_P,*
-V 6800,21500,CONT_DIF_P,*
-V 7400,21100,CONT_VIA,*
-V 8600,21100,CONT_VIA,*
-V 8000,21100,CONT_DIF_P,*
-V 6800,21100,CONT_DIF_P,*
-V 6800,20700,CONT_DIF_P,*
-V 8000,20700,CONT_DIF_P,*
-V 8600,20700,CONT_DIF_P,*
-V 7400,20700,CONT_DIF_P,*
-V 8600,20300,CONT_DIF_P,*
-V 7400,20300,CONT_DIF_P,*
-V 8000,20300,CONT_DIF_P,*
-V 6800,20300,CONT_DIF_P,*
-V 8600,19900,CONT_VIA,*
-V 7400,19900,CONT_VIA,*
-V 8000,19900,CONT_DIF_P,*
-V 6800,19900,CONT_DIF_P,*
-V 8600,16300,CONT_VIA,*
-V 8600,17500,CONT_VIA,*
-V 8600,18700,CONT_VIA,*
-V 7400,16300,CONT_VIA,*
-V 7400,18700,CONT_VIA,*
-V 7400,17500,CONT_VIA,*
-V 8600,15100,CONT_VIA,*
-V 7400,15100,CONT_VIA,*
-V 8000,16700,CONT_DIF_P,*
-V 8600,16700,CONT_DIF_P,*
-V 8600,17100,CONT_DIF_P,*
-V 8600,15900,CONT_DIF_P,*
-V 8000,15900,CONT_DIF_P,*
-V 8000,16300,CONT_DIF_P,*
-V 8600,18300,CONT_DIF_P,*
-V 8600,17900,CONT_DIF_P,*
-V 8000,17900,CONT_DIF_P,*
-V 8000,17100,CONT_DIF_P,*
-V 8000,17500,CONT_DIF_P,*
-V 8000,19500,CONT_DIF_P,*
-V 8600,19100,CONT_DIF_P,*
-V 8000,19100,CONT_DIF_P,*
-V 8000,18700,CONT_DIF_P,*
-V 8000,18300,CONT_DIF_P,*
-V 8600,19500,CONT_DIF_P,*
-V 8600,15500,CONT_DIF_P,*
-V 8000,15500,CONT_DIF_P,*
-V 7400,17100,CONT_DIF_P,*
-V 7400,16700,CONT_DIF_P,*
-V 6800,16700,CONT_DIF_P,*
-V 6800,17100,CONT_DIF_P,*
-V 6800,17500,CONT_DIF_P,*
-V 7400,15900,CONT_DIF_P,*
-V 6800,15900,CONT_DIF_P,*
-V 6800,16300,CONT_DIF_P,*
-V 7400,19500,CONT_DIF_P,*
-V 7400,19100,CONT_DIF_P,*
-V 6800,19100,CONT_DIF_P,*
-V 6800,18700,CONT_DIF_P,*
-V 7400,18300,CONT_DIF_P,*
-V 6800,18300,CONT_DIF_P,*
-V 7400,17900,CONT_DIF_P,*
-V 6800,17900,CONT_DIF_P,*
-V 6800,19500,CONT_DIF_P,*
-V 6800,15500,CONT_DIF_P,*
-V 7400,15500,CONT_DIF_P,*
-V 8000,15100,CONT_DIF_P,*
-V 8600,14700,CONT_DIF_P,*
-V 8000,14700,CONT_DIF_P,*
-V 8600,14300,CONT_DIF_P,*
-V 8000,14300,CONT_DIF_P,*
-V 6800,14300,CONT_DIF_P,*
-V 6800,15100,CONT_DIF_P,*
-V 7400,14700,CONT_DIF_P,*
-V 6800,14700,CONT_DIF_P,*
-V 7400,14300,CONT_DIF_P,*
-V 8000,27400,CONT_DIF_N,*
-V 8000,27000,CONT_DIF_N,*
-V 8000,26600,CONT_DIF_N,*
-V 8000,27800,CONT_DIF_N,*
-V 8000,25000,CONT_DIF_N,*
-V 8000,25400,CONT_DIF_N,*
-V 8000,26200,CONT_DIF_N,*
-V 8000,25800,CONT_DIF_N,*
-V 6800,27000,CONT_DIF_N,*
-V 6800,26600,CONT_DIF_N,*
-V 6800,26200,CONT_DIF_N,*
-V 6800,25800,CONT_DIF_N,*
-V 6800,25400,CONT_DIF_N,*
-V 6800,27800,CONT_DIF_N,*
-V 6800,27400,CONT_DIF_N,*
-V 6800,25000,CONT_DIF_N,*
-V 7300,13600,CONT_VIA,*
-V 8000,13100,CONT_POLY,*
-V 8400,13600,CONT_BODY_N,*
-V 7000,13600,CONT_BODY_N,*
-V 7600,13600,CONT_BODY_N,*
-V 6500,13600,CONT_BODY_N,*
-V 7400,28700,CONT_BODY_P,*
-V 8600,28700,CONT_BODY_P,*
-V 7400,26100,CONT_VIA,*
-V 7400,27700,CONT_VIA,*
-V 7400,25700,CONT_DIF_N,*
-V 7400,28100,CONT_DIF_N,*
-V 7400,26500,CONT_DIF_N,*
-V 7400,27300,CONT_DIF_N,*
-V 7400,26900,CONT_DIF_N,*
-V 7400,25300,CONT_DIF_N,*
-V 7400,24900,CONT_VIA,*
-V 8600,28100,CONT_VIA,*
-V 8600,24900,CONT_VIA,*
-V 8600,26500,CONT_VIA,*
-V 8600,25300,CONT_DIF_N,*
-V 8600,26900,CONT_DIF_N,*
-V 8600,27300,CONT_DIF_N,*
-V 8600,25700,CONT_DIF_N,*
-V 8600,26100,CONT_DIF_N,*
-V 8600,27700,CONT_DIF_N,*
-V 4400,21900,CONT_DIF_P,*
-V 5000,21900,CONT_DIF_P,*
-V 5600,21900,CONT_DIF_P,*
-V 6200,21900,CONT_DIF_P,*
-V 5000,22500,CONT_BODY_N,*
-V 6200,22500,CONT_BODY_N,*
-V 6100,23200,CONT_VIA,*
-V 5000,23800,CONT_VIA,*
-V 6100,23800,CONT_POLY,*
-V 6200,24300,CONT_BODY_P,*
-V 5000,24300,CONT_BODY_P,*
-V 6200,21500,CONT_DIF_P,*
-V 5600,21500,CONT_DIF_P,*
-V 5000,21500,CONT_DIF_P,*
-V 4400,21500,CONT_DIF_P,*
-V 5000,21100,CONT_VIA,*
-V 6200,21100,CONT_VIA,*
-V 5600,21100,CONT_DIF_P,*
-V 4400,21100,CONT_DIF_P,*
-V 4400,20700,CONT_DIF_P,*
-V 5600,20700,CONT_DIF_P,*
-V 6200,20700,CONT_DIF_P,*
-V 5000,20700,CONT_DIF_P,*
-V 6200,20300,CONT_DIF_P,*
-V 5000,20300,CONT_DIF_P,*
-V 5600,20300,CONT_DIF_P,*
-V 4400,20300,CONT_DIF_P,*
-V 6200,19900,CONT_VIA,*
-V 5000,19900,CONT_VIA,*
-V 5600,19900,CONT_DIF_P,*
-V 4400,19900,CONT_DIF_P,*
-V 6200,16300,CONT_VIA,*
-V 6200,17500,CONT_VIA,*
-V 6200,18700,CONT_VIA,*
-V 5000,16300,CONT_VIA,*
-V 5000,18700,CONT_VIA,*
-V 5000,17500,CONT_VIA,*
-V 6200,15100,CONT_VIA,*
-V 5000,15100,CONT_VIA,*
-V 5600,16700,CONT_DIF_P,*
-V 6200,16700,CONT_DIF_P,*
-V 6200,17100,CONT_DIF_P,*
-V 6200,15900,CONT_DIF_P,*
-V 5600,15900,CONT_DIF_P,*
-V 5600,16300,CONT_DIF_P,*
-V 6200,18300,CONT_DIF_P,*
-V 6200,17900,CONT_DIF_P,*
-V 5600,17900,CONT_DIF_P,*
-V 5600,17100,CONT_DIF_P,*
-V 5600,17500,CONT_DIF_P,*
-V 5600,19500,CONT_DIF_P,*
-V 6200,19100,CONT_DIF_P,*
-V 5600,19100,CONT_DIF_P,*
-V 5600,18700,CONT_DIF_P,*
-V 5600,18300,CONT_DIF_P,*
-V 6200,19500,CONT_DIF_P,*
-V 6200,15500,CONT_DIF_P,*
-V 5600,15500,CONT_DIF_P,*
-V 5000,17100,CONT_DIF_P,*
-V 5000,16700,CONT_DIF_P,*
-V 4400,16700,CONT_DIF_P,*
-V 4400,17100,CONT_DIF_P,*
-V 4400,17500,CONT_DIF_P,*
-V 5000,15900,CONT_DIF_P,*
-V 4400,15900,CONT_DIF_P,*
-V 4400,16300,CONT_DIF_P,*
-V 5000,19500,CONT_DIF_P,*
-V 5000,19100,CONT_DIF_P,*
-V 4400,19100,CONT_DIF_P,*
-V 4400,18700,CONT_DIF_P,*
-V 5000,18300,CONT_DIF_P,*
-V 4400,18300,CONT_DIF_P,*
-V 5000,17900,CONT_DIF_P,*
-V 4400,17900,CONT_DIF_P,*
-V 4400,19500,CONT_DIF_P,*
-V 4400,15500,CONT_DIF_P,*
-V 5000,15500,CONT_DIF_P,*
-V 5600,15100,CONT_DIF_P,*
-V 6200,14700,CONT_DIF_P,*
-V 5600,14700,CONT_DIF_P,*
-V 6200,14300,CONT_DIF_P,*
-V 5600,14300,CONT_DIF_P,*
-V 4400,14300,CONT_DIF_P,*
-V 4400,15100,CONT_DIF_P,*
-V 5000,14700,CONT_DIF_P,*
-V 4400,14700,CONT_DIF_P,*
-V 5000,14300,CONT_DIF_P,*
-V 5600,27400,CONT_DIF_N,*
-V 5600,27000,CONT_DIF_N,*
-V 5600,26600,CONT_DIF_N,*
-V 5600,27800,CONT_DIF_N,*
-V 5600,25000,CONT_DIF_N,*
-V 5600,25400,CONT_DIF_N,*
-V 5600,26200,CONT_DIF_N,*
-V 5600,25800,CONT_DIF_N,*
-V 4400,27000,CONT_DIF_N,*
-V 4400,26600,CONT_DIF_N,*
-V 4400,26200,CONT_DIF_N,*
-V 4400,25800,CONT_DIF_N,*
-V 4400,25400,CONT_DIF_N,*
-V 4400,27800,CONT_DIF_N,*
-V 4400,27400,CONT_DIF_N,*
-V 4400,25000,CONT_DIF_N,*
-V 4900,13600,CONT_VIA,*
-V 5600,13100,CONT_POLY,*
-V 6000,13600,CONT_BODY_N,*
-V 4600,13600,CONT_BODY_N,*
-V 5200,13600,CONT_BODY_N,*
-V 4100,13600,CONT_BODY_N,*
-V 5000,28700,CONT_BODY_P,*
-V 6200,28700,CONT_BODY_P,*
-V 5000,26100,CONT_VIA,*
-V 5000,27700,CONT_VIA,*
-V 5000,25700,CONT_DIF_N,*
-V 5000,28100,CONT_DIF_N,*
-V 5000,26500,CONT_DIF_N,*
-V 5000,27300,CONT_DIF_N,*
-V 5000,26900,CONT_DIF_N,*
-V 5000,25300,CONT_DIF_N,*
-V 5000,24900,CONT_VIA,*
-V 6200,28100,CONT_VIA,*
-V 6200,24900,CONT_VIA,*
-V 6200,26500,CONT_VIA,*
-V 6200,25300,CONT_DIF_N,*
-V 6200,26900,CONT_DIF_N,*
-V 6200,27300,CONT_DIF_N,*
-V 6200,25700,CONT_DIF_N,*
-V 6200,26100,CONT_DIF_N,*
-V 6200,27700,CONT_DIF_N,*
-V 2000,21900,CONT_DIF_P,*
-V 2600,21900,CONT_DIF_P,*
-V 3200,21900,CONT_DIF_P,*
-V 3800,21900,CONT_DIF_P,*
-V 2600,22500,CONT_BODY_N,*
-V 3800,22500,CONT_BODY_N,*
-V 3700,23200,CONT_VIA,*
-V 2600,23800,CONT_VIA,*
-V 3700,23800,CONT_POLY,*
-V 3800,24300,CONT_BODY_P,*
-V 2600,24300,CONT_BODY_P,*
-V 3800,21500,CONT_DIF_P,*
-V 3200,21500,CONT_DIF_P,*
-V 2600,21500,CONT_DIF_P,*
-V 2000,21500,CONT_DIF_P,*
-V 2600,21100,CONT_VIA,*
-V 3800,21100,CONT_VIA,*
-V 3200,21100,CONT_DIF_P,*
-V 2000,21100,CONT_DIF_P,*
-V 2000,20700,CONT_DIF_P,*
-V 3200,20700,CONT_DIF_P,*
-V 3800,20700,CONT_DIF_P,*
-V 2600,20700,CONT_DIF_P,*
-V 3800,20300,CONT_DIF_P,*
-V 2600,20300,CONT_DIF_P,*
-V 3200,20300,CONT_DIF_P,*
-V 2000,20300,CONT_DIF_P,*
-V 3800,19900,CONT_VIA,*
-V 2600,19900,CONT_VIA,*
-V 3200,19900,CONT_DIF_P,*
-V 2000,19900,CONT_DIF_P,*
-V 3800,16300,CONT_VIA,*
-V 3800,17500,CONT_VIA,*
-V 3800,18700,CONT_VIA,*
-V 2600,16300,CONT_VIA,*
-V 2600,18700,CONT_VIA,*
-V 2600,17500,CONT_VIA,*
-V 3800,15100,CONT_VIA,*
-V 2600,15100,CONT_VIA,*
-V 3200,16700,CONT_DIF_P,*
-V 3800,16700,CONT_DIF_P,*
-V 3800,17100,CONT_DIF_P,*
-V 3800,15900,CONT_DIF_P,*
-V 3200,15900,CONT_DIF_P,*
-V 3200,16300,CONT_DIF_P,*
-V 3800,18300,CONT_DIF_P,*
-V 3800,17900,CONT_DIF_P,*
-V 3200,17900,CONT_DIF_P,*
-V 3200,17100,CONT_DIF_P,*
-V 3200,17500,CONT_DIF_P,*
-V 3200,19500,CONT_DIF_P,*
-V 3800,19100,CONT_DIF_P,*
-V 3200,19100,CONT_DIF_P,*
-V 3200,18700,CONT_DIF_P,*
-V 3200,18300,CONT_DIF_P,*
-V 3800,19500,CONT_DIF_P,*
-V 3800,15500,CONT_DIF_P,*
-V 3200,15500,CONT_DIF_P,*
-V 2600,17100,CONT_DIF_P,*
-V 2600,16700,CONT_DIF_P,*
-V 2000,16700,CONT_DIF_P,*
-V 2000,17100,CONT_DIF_P,*
-V 2000,17500,CONT_DIF_P,*
-V 2600,15900,CONT_DIF_P,*
-V 2000,15900,CONT_DIF_P,*
-V 2000,16300,CONT_DIF_P,*
-V 2600,19500,CONT_DIF_P,*
-V 2600,19100,CONT_DIF_P,*
-V 2000,19100,CONT_DIF_P,*
-V 2000,18700,CONT_DIF_P,*
-V 2600,18300,CONT_DIF_P,*
-V 2000,18300,CONT_DIF_P,*
-V 2600,17900,CONT_DIF_P,*
-V 2000,17900,CONT_DIF_P,*
-V 2000,19500,CONT_DIF_P,*
-V 2000,15500,CONT_DIF_P,*
-V 2600,15500,CONT_DIF_P,*
-V 3200,15100,CONT_DIF_P,*
-V 3800,14700,CONT_DIF_P,*
-V 3200,14700,CONT_DIF_P,*
-V 3800,14300,CONT_DIF_P,*
-V 3200,14300,CONT_DIF_P,*
-V 2000,14300,CONT_DIF_P,*
-V 2000,15100,CONT_DIF_P,*
-V 2600,14700,CONT_DIF_P,*
-V 2000,14700,CONT_DIF_P,*
-V 2600,14300,CONT_DIF_P,*
-V 3200,27400,CONT_DIF_N,*
-V 3200,27000,CONT_DIF_N,*
-V 3200,26600,CONT_DIF_N,*
-V 3200,27800,CONT_DIF_N,*
-V 3200,25000,CONT_DIF_N,*
-V 3200,25400,CONT_DIF_N,*
-V 3200,26200,CONT_DIF_N,*
-V 3200,25800,CONT_DIF_N,*
-V 2000,27000,CONT_DIF_N,*
-V 2000,26600,CONT_DIF_N,*
-V 2000,26200,CONT_DIF_N,*
-V 2000,25800,CONT_DIF_N,*
-V 2000,25400,CONT_DIF_N,*
-V 2000,27800,CONT_DIF_N,*
-V 2000,27400,CONT_DIF_N,*
-V 2000,25000,CONT_DIF_N,*
-V 2500,13600,CONT_VIA,*
-V 3200,13100,CONT_POLY,*
-V 3600,13600,CONT_BODY_N,*
-V 2200,13600,CONT_BODY_N,*
-V 2800,13600,CONT_BODY_N,*
-V 1700,13600,CONT_BODY_N,*
-V 2600,28700,CONT_BODY_P,*
-V 3800,28700,CONT_BODY_P,*
-V 2600,26100,CONT_VIA,*
-V 2600,27700,CONT_VIA,*
-V 2600,25700,CONT_DIF_N,*
-V 2600,28100,CONT_DIF_N,*
-V 2600,26500,CONT_DIF_N,*
-V 2600,27300,CONT_DIF_N,*
-V 2600,26900,CONT_DIF_N,*
-V 2600,25300,CONT_DIF_N,*
-V 2600,24900,CONT_VIA,*
-V 3800,28100,CONT_VIA,*
-V 3800,24900,CONT_VIA,*
-V 3800,26500,CONT_VIA,*
-V 3800,25300,CONT_DIF_N,*
-V 3800,26900,CONT_DIF_N,*
-V 3800,27300,CONT_DIF_N,*
-V 3800,25700,CONT_DIF_N,*
-V 3800,26100,CONT_DIF_N,*
-V 3800,27700,CONT_DIF_N,*
-V 3600,9800,CONT_BODY_N,*
-V 3600,5100,CONT_BODY_N,*
-V 3600,10800,CONT_BODY_N,*
-V 3600,11200,CONT_BODY_N,*
-V 3600,11600,CONT_BODY_N,*
-V 3600,12000,CONT_BODY_N,*
-V 3600,9000,CONT_BODY_N,*
-V 3600,8200,CONT_BODY_N,*
-V 3600,7800,CONT_BODY_N,*
-V 3600,7400,CONT_BODY_N,*
-V 3600,7000,CONT_BODY_N,*
-V 3600,6300,CONT_BODY_N,*
-V 3600,5900,CONT_BODY_N,*
-V 3600,5500,CONT_BODY_N,*
-V 3600,10400,CONT_BODY_N,*
-V 3600,9400,CONT_BODY_N,*
-V 3600,8600,CONT_BODY_N,*
-V 3600,-200,CONT_BODY_P,*
-V 3600,4000,CONT_BODY_P,*
-V 3600,3100,CONT_BODY_P,*
-V 3600,2700,CONT_BODY_P,*
-V 3600,1900,CONT_BODY_P,*
-V 3600,1500,CONT_BODY_P,*
-V 3600,1100,CONT_BODY_P,*
-V 3600,700,CONT_BODY_P,*
-V 3600,300,CONT_BODY_P,*
-V 3600,3500,CONT_VIA,*
-V 3600,2300,CONT_VIA,*
-V 3600,6600,CONT_VIA,*
-V 8400,3500,CONT_VIA,*
-V 7200,9000,CONT_VIA,*
-V 7200,10200,CONT_VIA,*
-V 7200,6600,CONT_VIA,*
-V 8400,2300,CONT_VIA,*
-V 8400,6600,CONT_VIA,*
-V 8400,10200,CONT_VIA,*
-V 8400,9000,CONT_VIA,*
-V 8400,7400,CONT_VIA,*
-V 6000,6600,CONT_VIA,*
-V 6000,7400,CONT_VIA,*
-V 6000,9000,CONT_VIA,*
-V 6000,10200,CONT_VIA,*
-V 6000,3500,CONT_VIA,*
-V 6000,2300,CONT_VIA,*
-V 7200,2300,CONT_VIA,*
-V 7200,7400,CONT_VIA,*
-V 7800,1600,CONT_VIA,*
-V 4200,3500,CONT_VIA,*
-V 4200,10200,CONT_VIA,*
-V 4200,9000,CONT_VIA,*
-V 4200,7400,CONT_VIA,*
-V 4200,6600,CONT_VIA,*
-V 4200,2300,CONT_VIA,*
-V 4900,5300,CONT_POLY,*
-V 7200,4600,CONT_POLY,*
-V 8400,4000,CONT_BODY_P,*
-V 6000,4000,CONT_BODY_P,*
-V 7600,4000,CONT_BODY_P,*
-V 4200,4000,CONT_BODY_P,*
-V 7200,-200,CONT_BODY_P,*
-V 6000,-200,CONT_BODY_P,*
-V 4200,-200,CONT_BODY_P,*
-V 8400,-200,CONT_BODY_P,*
-V 7200,12000,CONT_BODY_N,*
-V 6400,5100,CONT_BODY_N,*
-V 6800,5100,CONT_BODY_N,*
-V 8400,5100,CONT_BODY_N,*
-V 6000,5100,CONT_BODY_N,*
-V 6100,12000,CONT_BODY_N,*
-V 4200,5100,CONT_BODY_N,*
-V 7800,9000,CONT_DIF_P,*
-V 7800,10600,CONT_DIF_P,*
-V 7800,11000,CONT_DIF_P,*
-V 7800,5800,CONT_DIF_P,*
-V 7800,8200,CONT_DIF_P,*
-V 7800,8600,CONT_DIF_P,*
-V 7800,11400,CONT_DIF_P,*
-V 7800,7400,CONT_DIF_P,*
-V 6600,6200,CONT_DIF_P,*
-V 7800,6200,CONT_DIF_P,*
-V 7800,9400,CONT_DIF_P,*
-V 7800,9800,CONT_DIF_P,*
-V 7800,6600,CONT_DIF_P,*
-V 7800,7000,CONT_DIF_P,*
-V 7800,10200,CONT_DIF_P,*
-V 7800,7800,CONT_DIF_P,*
-V 8400,7800,CONT_DIF_P,*
-V 6600,10600,CONT_DIF_P,*
-V 6600,11000,CONT_DIF_P,*
-V 6600,5800,CONT_DIF_P,*
-V 6600,8200,CONT_DIF_P,*
-V 6600,8600,CONT_DIF_P,*
-V 6600,11400,CONT_DIF_P,*
-V 6600,7400,CONT_DIF_P,*
-V 8400,11400,CONT_DIF_P,*
-V 6600,9400,CONT_DIF_P,*
-V 6600,9800,CONT_DIF_P,*
-V 6600,6600,CONT_DIF_P,*
-V 6600,7000,CONT_DIF_P,*
-V 6600,10200,CONT_DIF_P,*
-V 6600,7800,CONT_DIF_P,*
-V 6600,9000,CONT_DIF_P,*
-V 7200,8600,CONT_DIF_P,*
-V 8400,11000,CONT_DIF_P,*
-V 8400,10600,CONT_DIF_P,*
-V 8400,9800,CONT_DIF_P,*
-V 8400,7000,CONT_DIF_P,*
-V 8400,5800,CONT_DIF_P,*
-V 8400,6200,CONT_DIF_P,*
-V 8400,8600,CONT_DIF_P,*
-V 6000,5800,CONT_DIF_P,*
-V 8400,8200,CONT_DIF_P,*
-V 8400,9400,CONT_DIF_P,*
-V 7200,10600,CONT_DIF_P,*
-V 7200,11000,CONT_DIF_P,*
-V 7200,7800,CONT_DIF_P,*
-V 7200,8200,CONT_DIF_P,*
-V 7200,11400,CONT_DIF_P,*
-V 6000,10600,CONT_DIF_P,*
-V 7200,6200,CONT_DIF_P,*
-V 7200,5800,CONT_DIF_P,*
-V 7200,7000,CONT_DIF_P,*
-V 7200,9800,CONT_DIF_P,*
-V 7200,9400,CONT_DIF_P,*
-V 6000,6200,CONT_DIF_P,*
-V 6000,7000,CONT_DIF_P,*
-V 5400,11000,CONT_DIF_P,*
-V 6000,9400,CONT_DIF_P,*
-V 6000,9800,CONT_DIF_P,*
-V 6000,11000,CONT_DIF_P,*
-V 6000,7800,CONT_DIF_P,*
-V 6000,8200,CONT_DIF_P,*
-V 6000,11400,CONT_DIF_P,*
-V 6000,8600,CONT_DIF_P,*
-V 5400,10600,CONT_DIF_P,*
-V 5400,9400,CONT_DIF_P,*
-V 5400,9800,CONT_DIF_P,*
-V 5400,6600,CONT_DIF_P,*
-V 5400,7000,CONT_DIF_P,*
-V 5400,7800,CONT_DIF_P,*
-V 5400,10200,CONT_DIF_P,*
-V 5400,9000,CONT_DIF_P,*
-V 5400,5800,CONT_DIF_P,*
-V 5400,8200,CONT_DIF_P,*
-V 5400,8600,CONT_DIF_P,*
-V 5400,11400,CONT_DIF_P,*
-V 5400,7400,CONT_DIF_P,*
-V 5400,6200,CONT_DIF_P,*
-V 4800,7000,CONT_DIF_P,*
-V 4800,7800,CONT_DIF_P,*
-V 4800,9000,CONT_DIF_P,*
-V 4800,8600,CONT_DIF_P,*
-V 4800,11400,CONT_DIF_P,*
-V 4800,7400,CONT_DIF_P,*
-V 4800,6200,CONT_DIF_P,*
-V 4800,9800,CONT_DIF_P,*
-V 4800,10600,CONT_DIF_P,*
-V 4800,6600,CONT_DIF_P,*
-V 4800,11000,CONT_DIF_P,*
-V 4800,8200,CONT_DIF_P,*
-V 4800,5800,CONT_DIF_P,*
-V 4800,10200,CONT_DIF_P,*
-V 4800,9400,CONT_DIF_P,*
-V 4200,11000,CONT_DIF_P,*
-V 4200,9800,CONT_DIF_P,*
-V 4200,5800,CONT_DIF_P,*
-V 4200,7000,CONT_DIF_P,*
-V 4200,6200,CONT_DIF_P,*
-V 4200,9400,CONT_DIF_P,*
-V 4200,10600,CONT_DIF_P,*
-V 4200,8600,CONT_DIF_P,*
-V 4200,11400,CONT_DIF_P,*
-V 4200,8200,CONT_DIF_P,*
-V 4200,7800,CONT_DIF_P,*
-V 7800,2100,CONT_DIF_N,*
-V 6600,2900,CONT_DIF_N,*
-V 7200,2800,CONT_DIF_N,*
-V 7200,3300,CONT_DIF_N,*
-V 7800,2500,CONT_DIF_N,*
-V 7200,700,CONT_DIF_N,*
-V 7800,3300,CONT_DIF_N,*
-V 7800,2900,CONT_DIF_N,*
-V 6600,2500,CONT_DIF_N,*
-V 6600,2100,CONT_DIF_N,*
-V 6600,3300,CONT_DIF_N,*
-V 6000,700,CONT_DIF_N,*
-V 8400,1500,CONT_DIF_N,*
-V 8400,1100,CONT_DIF_N,*
-V 8400,700,CONT_DIF_N,*
-V 8400,3100,CONT_DIF_N,*
-V 8400,2700,CONT_DIF_N,*
-V 8400,1900,CONT_DIF_N,*
-V 7200,1900,CONT_DIF_N,*
-V 5400,2500,CONT_DIF_N,*
-V 7200,1100,CONT_DIF_N,*
-V 7200,1500,CONT_DIF_N,*
-V 6000,3100,CONT_DIF_N,*
-V 6000,2700,CONT_DIF_N,*
-V 6000,1900,CONT_DIF_N,*
-V 6000,1500,CONT_DIF_N,*
-V 6000,1100,CONT_DIF_N,*
-V 5400,3300,CONT_DIF_N,*
-V 5400,2900,CONT_DIF_N,*
-V 5400,900,CONT_DIF_N,*
-V 5400,1300,CONT_DIF_N,*
-V 5400,1700,CONT_DIF_N,*
-V 5400,2100,CONT_DIF_N,*
-V 7800,700,CONT_DIF_N,*
-V 4800,2100,CONT_DIF_N,*
-V 4800,2500,CONT_DIF_N,*
-V 4800,900,CONT_DIF_N,*
-V 4800,1300,CONT_DIF_N,*
-V 4800,1700,CONT_DIF_N,*
-V 4800,3300,CONT_DIF_N,*
-V 4800,2900,CONT_DIF_N,*
-V 4200,1100,CONT_DIF_N,*
-V 4200,1500,CONT_DIF_N,*
-V 4200,1900,CONT_DIF_N,*
-V 4200,2700,CONT_DIF_N,*
-V 4200,3100,CONT_DIF_N,*
-V 4200,700,CONT_DIF_N,*
-V 7800,1200,CONT_DIF_N,*
-V 4700,300,CONT_POLY,*
-V 4700,-700,CONT_VIA,*
-V 6600,1600,CONT_VIA,*
-V 6600,1200,CONT_DIF_N,*
-V 6600,700,CONT_DIF_N,*
-V 6400,4000,CONT_BODY_P,*
-V 6800,4000,CONT_BODY_P,*
-V 8000,4000,CONT_BODY_P,*
-V 8000,-200,CONT_BODY_P,*
-V 7600,-200,CONT_BODY_P,*
-V 6800,-200,CONT_BODY_P,*
-V 6400,-200,CONT_BODY_P,*
-V 5600,-200,CONT_BODY_P,*
-V 5200,-200,CONT_BODY_P,*
-V 4600,12000,CONT_BODY_N,*
-V 4200,12000,CONT_BODY_N,*
-V 5100,12000,CONT_BODY_N,*
-V 5600,12000,CONT_BODY_N,*
-V 8400,12000,CONT_BODY_N,*
-V 7600,5100,CONT_BODY_N,*
-V 8000,5100,CONT_BODY_N,*
-V 9000,10000,CONT_VIA,*
-V 9000,7500,CONT_VIA,*
-V 9000,8700,CONT_VIA,*
-V 9000,6700,CONT_VIA,*
-V 9000,5100,CONT_BODY_N,*
-V 9000,11200,CONT_BODY_N,*
-V 9000,6300,CONT_BODY_N,*
-V 9000,5900,CONT_BODY_N,*
-V 9000,12000,CONT_BODY_N,*
-V 9000,9500,CONT_BODY_N,*
-V 9000,10400,CONT_BODY_N,*
-V 9000,5500,CONT_BODY_N,*
-V 9000,9100,CONT_BODY_N,*
-V 9000,8300,CONT_BODY_N,*
-V 9000,10800,CONT_BODY_N,*
-V 9000,11600,CONT_BODY_N,*
-V 9000,7900,CONT_BODY_N,*
-V 9000,7100,CONT_BODY_N,*
-V 9000,3600,CONT_VIA,*
-V 9000,2400,CONT_VIA,*
-V 9000,3200,CONT_BODY_P,*
-V 9000,800,CONT_BODY_P,*
-V 9000,300,CONT_BODY_P,*
-V 9000,4000,CONT_BODY_P,*
-V 9000,1200,CONT_BODY_P,*
-V 9000,1600,CONT_BODY_P,*
-V 9000,2000,CONT_BODY_P,*
-V 9000,2800,CONT_BODY_P,*
-V 9000,-200,CONT_BODY_P,*
-V 16400,27900,CONT_VIA,*
-V 16100,24300,CONT_VIA,*
-V 16400,25900,CONT_VIA,*
-V 15800,29200,CONT_VIA,*
-V 16400,29200,CONT_VIA,*
-V 16400,23200,CONT_VIA,*
-V 16900,23200,CONT_VIA,*
-V 1200,28700,CONT_BODY_P,*
-V 16400,24700,CONT_BODY_P,*
-V 16400,25100,CONT_BODY_P,*
-V 16400,25500,CONT_BODY_P,*
-V 16400,24300,CONT_BODY_P,*
-V 1200,24300,CONT_BODY_P,*
-V 16400,28700,CONT_BODY_P,*
-V 16400,28300,CONT_BODY_P,*
-V 16400,27500,CONT_BODY_P,*
-V 16400,27100,CONT_BODY_P,*
-V 16400,26700,CONT_BODY_P,*
-V 16400,26300,CONT_BODY_P,*
-V 800,27100,CONT_BODY_P,*
-V 800,26700,CONT_BODY_P,*
-V 800,26300,CONT_BODY_P,*
-V 800,25900,CONT_BODY_P,*
-V 800,28700,CONT_BODY_P,*
-V 800,24700,CONT_BODY_P,*
-V 800,25100,CONT_BODY_P,*
-V 800,25500,CONT_BODY_P,*
-V 800,24300,CONT_BODY_P,*
-V 800,28300,CONT_BODY_P,*
-V 800,27900,CONT_BODY_P,*
-V 800,27500,CONT_BODY_P,*
-V 16400,22000,CONT_BODY_N,*
-V 16400,21600,CONT_BODY_N,*
-V 16400,21200,CONT_BODY_N,*
-V 16400,20800,CONT_BODY_N,*
-V 1400,22500,CONT_BODY_N,*
-V 16400,20400,CONT_BODY_N,*
-V 16400,22500,CONT_BODY_N,*
-V 16400,20000,CONT_BODY_N,*
-V 800,22500,CONT_BODY_N,*
-V 800,20000,CONT_BODY_N,*
-V 800,20400,CONT_BODY_N,*
-V 800,20800,CONT_BODY_N,*
-V 800,21200,CONT_BODY_N,*
-V 800,21600,CONT_BODY_N,*
-V 800,22000,CONT_BODY_N,*
-V 1300,13600,CONT_BODY_N,*
-V 16400,18400,CONT_BODY_N,*
-V 16400,18000,CONT_BODY_N,*
-V 16400,17600,CONT_BODY_N,*
-V 16400,19600,CONT_BODY_N,*
-V 16400,19200,CONT_BODY_N,*
-V 16400,18800,CONT_BODY_N,*
-V 16000,13600,CONT_BODY_N,*
-V 16400,13600,CONT_BODY_N,*
-V 16400,15600,CONT_BODY_N,*
-V 16400,15200,CONT_BODY_N,*
-V 16400,14800,CONT_BODY_N,*
-V 16400,14400,CONT_BODY_N,*
-V 16400,14000,CONT_BODY_N,*
-V 16400,16400,CONT_BODY_N,*
-V 16400,16000,CONT_BODY_N,*
-V 16400,16800,CONT_BODY_N,*
-V 16400,17200,CONT_BODY_N,*
-V 800,13600,CONT_BODY_N,*
-V 800,14000,CONT_BODY_N,*
-V 800,14400,CONT_BODY_N,*
-V 800,14800,CONT_BODY_N,*
-V 800,15200,CONT_BODY_N,*
-V 800,15600,CONT_BODY_N,*
-V 800,19600,CONT_BODY_N,*
-V 800,18400,CONT_BODY_N,*
-V 800,17600,CONT_BODY_N,*
-V 800,18000,CONT_BODY_N,*
-V 800,16000,CONT_BODY_N,*
-V 800,16400,CONT_BODY_N,*
-V 800,17200,CONT_BODY_N,*
-V 800,16800,CONT_BODY_N,*
-V 800,18800,CONT_BODY_N,*
-V 800,19200,CONT_BODY_N,*
-V 1400,21900,CONT_DIF_P,*
-V 1400,21500,CONT_DIF_P,*
-V 1400,21100,CONT_DIF_P,*
-V 1400,20700,CONT_DIF_P,*
-V 1400,20300,CONT_DIF_P,*
-V 1400,16300,CONT_DIF_P,*
-V 1400,16700,CONT_DIF_P,*
-V 1400,17100,CONT_DIF_P,*
-V 1400,19100,CONT_DIF_P,*
-V 1400,19500,CONT_DIF_P,*
-V 1400,19900,CONT_DIF_P,*
-V 1400,14300,CONT_DIF_P,*
-V 1400,14700,CONT_DIF_P,*
-V 1400,15100,CONT_DIF_P,*
-V 1400,15500,CONT_DIF_P,*
-V 1400,15900,CONT_DIF_P,*
-V 1400,17900,CONT_DIF_P,*
-V 1400,17500,CONT_DIF_P,*
-V 1400,18300,CONT_DIF_P,*
-V 1400,18700,CONT_DIF_P,*
-V 1400,25700,CONT_DIF_N,*
-V 1400,25300,CONT_DIF_N,*
-V 1400,24900,CONT_DIF_N,*
-V 1400,26100,CONT_DIF_N,*
-V 1400,27300,CONT_DIF_N,*
-V 1400,28100,CONT_DIF_N,*
-V 1400,27700,CONT_DIF_N,*
-V 1400,26900,CONT_DIF_N,*
-V 1400,26500,CONT_DIF_N,*
-V 16900,1600,CONT_VIA,*
-B 1100,26700,800,5100,CONT_VIA,*
-B 16100,18100,600,9000,CONT_VIA,*
-B 1100,18000,600,9100,CONT_VIA,*
-EOF
diff --git a/alliance/share/cells/padlib/palot_sp.ap b/alliance/share/cells/padlib/palot_sp.ap
deleted file mode 100644
index 21813c53..00000000
--- a/alliance/share/cells/padlib/palot_sp.ap
+++ /dev/null
@@ -1,1946 +0,0 @@
-V ALLIANCE : 6
-H palot_sp,P,13/10/2000,100
-A 0,-700,17200,35600
-C 17200,16800,12000,vdde,1,EAST,ALU2
-C 0,16800,12000,vdde,0,WEST,ALU2
-C 17200,8400,4000,vddi,1,EAST,ALU2
-C 17200,4000,4000,vssi,1,EAST,ALU2
-C 0,4000,4000,vssi,0,WEST,ALU2
-C 0,8400,4000,vddi,0,WEST,ALU2
-C 17200,600,1200,ck,1,EAST,ALU2
-C 0,600,1200,ck,0,WEST,ALU2
-C 4600,-700,200,i,1,SOUTH,ALU2
-C 4600,-700,200,i,0,SOUTH,ALU1
-C 15400,-700,200,b,1,SOUTH,ALU2
-C 15400,-700,200,b,0,SOUTH,ALU1
-C 17200,29600,12000,vsse,1,EAST,ALU2
-C 0,29600,12000,vsse,0,WEST,ALU2
-S 15700,23200,16900,23200,200,*,RIGHT,ALU1
-S 16900,1600,16900,23200,200,*,UP,ALU1
-S 3700,23200,16900,23200,200,*,RIGHT,ALU2
-S 6500,1600,16900,1600,200,*,RIGHT,ALU2
-S 16400,1600,16900,1600,200,*,LEFT,ALU1
-S 15800,24300,16400,24300,200,*,RIGHT,ALU1
-S 15800,24300,15800,28800,200,*,UP,ALU1
-S 16200,24300,16200,29300,600,*,UP,ALU1
-S 13400,24300,13400,28800,200,*,UP,ALU1
-S 11000,24300,11000,28800,200,*,UP,ALU1
-S 8600,24300,8600,28800,200,*,UP,ALU1
-S 6200,24300,6200,28800,200,*,UP,ALU1
-S 3800,24400,3800,28800,200,*,UP,ALU1
-S 14800,4500,15500,4500,200,*,LEFT,ALU1
-S 5100,-200,14900,-200,200,*,RIGHT,ALU1
-S 14900,-200,14900,4000,200,*,UP,ALU1
-S 7400,5100,11400,5100,200,*,RIGHT,ALU1
-S 3200,12000,6000,12000,200,*,RIGHT,ALU1
-S 2100,5100,4100,5100,200,*,LEFT,ALU1
-S 2100,5100,2100,12100,200,*,DOWN,ALU1
-S 2400,5100,2400,8700,800,*,UP,ALU1
-S 2400,8700,2400,9900,500,*,DOWN,ALU1
-S 2100,10300,3300,10300,1000,*,LEFT,ALU1
-S 3300,9900,3300,11900,200,*,DOWN,ALU1
-S 10700,-200,10700,3200,200,*,UP,ALU1
-S 9500,-200,9500,4000,200,*,UP,ALU1
-S 8300,-200,8300,4000,200,*,UP,ALU1
-S 7100,-200,7100,3200,200,*,UP,ALU1
-S 5900,-200,5900,4000,200,*,UP,ALU1
-S 5900,4000,10100,4000,200,*,RIGHT,ALU1
-S 4100,5100,4100,12000,200,*,UP,ALU1
-S 8300,5100,8300,12000,200,*,UP,ALU1
-S 5900,5100,5900,12000,200,*,UP,ALU1
-S 10700,5100,10700,12100,200,*,UP,ALU1
-S 11300,4600,13100,4600,200,*,RIGHT,ALU1
-S 14600,13600,14600,22600,200,*,UP,ALU1
-S 2600,12600,3300,12600,200,*,LEFT,ALU1
-S 2700,11300,2700,12600,200,*,UP,ALU1
-S 3200,12600,3200,13100,200,*,UP,ALU1
-S 3700,13600,5300,13600,200,*,RIGHT,ALU1
-S 3800,13700,3800,22600,200,*,UP,ALU1
-S 15500,13600,16400,13600,200,*,RIGHT,ALU1
-S 16200,13600,16200,22600,600,*,UP,ALU1
-S 15800,13700,15800,22600,200,*,UP,ALU1
-S 13400,13600,13400,22600,200,*,UP,ALU1
-S 12200,13600,12200,22600,200,*,UP,ALU1
-S 11000,13600,11000,22600,200,*,UP,ALU1
-S 9800,13600,9800,22600,200,*,UP,ALU1
-S 8600,13600,8600,22600,200,*,UP,ALU1
-S 7400,13600,7400,22600,200,*,UP,ALU1
-S 6200,13600,6200,22600,200,*,UP,ALU1
-S 5000,13600,5000,22600,200,*,UP,ALU1
-S 2600,13600,2600,22600,200,*,UP,ALU1
-S 0,29600,17200,29600,12000,vsse,RIGHT,ALU2
-S 0,16800,17200,16800,12000,vdde,RIGHT,ALU2
-S 0,8400,17200,8400,4000,vddi,RIGHT,ALU2
-S 0,4000,17200,4000,4000,vssi,RIGHT,ALU2
-S 0,600,17200,600,1200,ck,RIGHT,ALU2
-S 3200,13100,3800,13100,200,*,RIGHT,POLY
-S 2000,14200,2000,29100,200,*,UP,ALU1
-S 3200,14200,3200,29100,200,*,UP,ALU1
-S 2600,23700,2600,28800,200,*,UP,ALU1
-S 3800,24800,3800,28200,300,*,UP,NDIF
-S 3200,24800,3200,28200,300,*,UP,NDIF
-S 2600,24800,2600,28200,300,*,UP,NDIF
-S 2000,24800,2000,28200,300,*,UP,NDIF
-S 1700,24600,1700,28400,100,*,UP,NTRANS
-S 2300,24600,2300,28400,100,*,UP,NTRANS
-S 2900,24600,2900,28400,100,*,UP,NTRANS
-S 3500,24600,3500,28400,100,*,UP,NTRANS
-S 1500,28700,3900,28700,300,*,RIGHT,PTIE
-S 3800,14100,3800,22000,300,*,UP,PDIF
-S 3200,14100,3200,22000,200,*,UP,PDIF
-S 2600,14100,2600,22000,200,*,UP,PDIF
-S 2000,14100,2000,22000,200,*,UP,PDIF
-S 1700,13900,1700,22200,100,*,UP,PTRANS
-S 2300,13900,2300,22200,100,*,UP,PTRANS
-S 2900,13900,2900,22200,100,*,UP,PTRANS
-S 3500,13900,3500,22200,100,*,UP,PTRANS
-S 2800,13400,2800,22700,2800,*,UP,NWELL
-S 1500,13600,2900,13600,300,*,RIGHT,NTIE
-S 3500,13600,3900,13600,300,*,RIGHT,NTIE
-S 1700,13900,3500,13900,100,*,RIGHT,POLY
-S 3200,23700,3200,23900,200,*,DOWN,POLY
-S 1500,24300,2900,24300,300,*,RIGHT,PTIE
-S 3500,24300,3900,24300,300,*,RIGHT,PTIE
-S 1700,24600,3500,24600,100,*,RIGHT,POLY
-S 3200,23800,3200,24600,200,*,UP,POLY
-S 3200,23800,3700,23800,300,*,RIGHT,POLY
-S 1500,22500,3900,22500,300,*,RIGHT,NTIE
-S 3200,13100,3200,13900,200,*,UP,POLY
-S 1500,13600,2700,13600,200,*,RIGHT,ALU1
-S 3200,13000,3200,14300,200,*,DOWN,ALU1
-S 3900,22500,6300,22500,300,*,RIGHT,NTIE
-S 6100,23200,6100,23800,200,*,UP,ALU1
-S 5600,23800,6100,23800,300,*,RIGHT,POLY
-S 5600,23800,5600,24600,200,*,UP,POLY
-S 4100,24600,5900,24600,100,*,RIGHT,POLY
-S 5900,24300,6300,24300,300,*,RIGHT,PTIE
-S 3900,24300,5300,24300,300,*,RIGHT,PTIE
-S 5600,23700,5600,23900,200,*,DOWN,POLY
-S 5900,13600,6300,13600,200,*,RIGHT,ALU1
-S 4100,13900,5900,13900,100,*,RIGHT,POLY
-S 5600,13300,5600,13900,200,*,UP,POLY
-S 5900,13600,6300,13600,300,*,RIGHT,NTIE
-S 3900,13600,5300,13600,300,*,RIGHT,NTIE
-S 5200,13400,5200,22700,2800,*,UP,NWELL
-S 5900,13900,5900,22200,100,*,UP,PTRANS
-S 5300,13900,5300,22200,100,*,UP,PTRANS
-S 4700,13900,4700,22200,100,*,UP,PTRANS
-S 4100,13900,4100,22200,100,*,UP,PTRANS
-S 4400,14100,4400,22000,200,*,UP,PDIF
-S 5000,14100,5000,22000,200,*,UP,PDIF
-S 5600,14100,5600,22000,200,*,UP,PDIF
-S 6200,14100,6200,22000,300,*,UP,PDIF
-S 3900,28700,6300,28700,300,*,RIGHT,PTIE
-S 5900,24600,5900,28400,100,*,UP,NTRANS
-S 5300,24600,5300,28400,100,*,UP,NTRANS
-S 4700,24600,4700,28400,100,*,UP,NTRANS
-S 4100,24600,4100,28400,100,*,UP,NTRANS
-S 4400,24800,4400,28200,300,*,UP,NDIF
-S 5000,24800,5000,28200,300,*,UP,NDIF
-S 5600,24800,5600,28200,300,*,UP,NDIF
-S 6200,24800,6200,28200,300,*,UP,NDIF
-S 5000,23700,5000,28800,200,*,UP,ALU1
-S 5600,14200,5600,29100,200,*,UP,ALU1
-S 4400,14200,4400,29100,200,*,UP,ALU1
-S 6300,22500,8700,22500,300,*,RIGHT,NTIE
-S 8500,23200,8500,23800,200,*,UP,ALU1
-S 8000,23800,8500,23800,300,*,RIGHT,POLY
-S 8000,23800,8000,24600,200,*,UP,POLY
-S 6500,24600,8300,24600,100,*,RIGHT,POLY
-S 8300,24300,8700,24300,300,*,RIGHT,PTIE
-S 6300,24300,7700,24300,300,*,RIGHT,PTIE
-S 8000,23700,8000,23900,200,*,DOWN,POLY
-S 8300,13600,8700,13600,200,*,RIGHT,ALU1
-S 6300,13600,7700,13600,200,*,RIGHT,ALU1
-S 6500,13900,8300,13900,100,*,RIGHT,POLY
-S 8000,13300,8000,13900,200,*,UP,POLY
-S 8300,13600,8700,13600,300,*,RIGHT,NTIE
-S 6300,13600,7700,13600,300,*,RIGHT,NTIE
-S 7600,13400,7600,22700,2800,*,UP,NWELL
-S 8300,13900,8300,22200,100,*,UP,PTRANS
-S 7700,13900,7700,22200,100,*,UP,PTRANS
-S 7100,13900,7100,22200,100,*,UP,PTRANS
-S 6500,13900,6500,22200,100,*,UP,PTRANS
-S 6800,14100,6800,22000,200,*,UP,PDIF
-S 7400,14100,7400,22000,200,*,UP,PDIF
-S 8000,14100,8000,22000,200,*,UP,PDIF
-S 8600,14100,8600,22000,300,*,UP,PDIF
-S 6300,28700,8700,28700,300,*,RIGHT,PTIE
-S 8300,24600,8300,28400,100,*,UP,NTRANS
-S 7700,24600,7700,28400,100,*,UP,NTRANS
-S 7100,24600,7100,28400,100,*,UP,NTRANS
-S 6500,24600,6500,28400,100,*,UP,NTRANS
-S 6800,24800,6800,28200,300,*,UP,NDIF
-S 7400,24800,7400,28200,300,*,UP,NDIF
-S 8000,24800,8000,28200,300,*,UP,NDIF
-S 8600,24800,8600,28200,300,*,UP,NDIF
-S 7400,23700,7400,28800,200,*,UP,ALU1
-S 8000,14200,8000,29100,200,*,UP,ALU1
-S 6800,14200,6800,29100,200,*,UP,ALU1
-S 8700,22500,11100,22500,300,*,RIGHT,NTIE
-S 10900,23200,10900,23800,200,*,UP,ALU1
-S 10400,23800,10900,23800,300,*,RIGHT,POLY
-S 10400,23800,10400,24600,200,*,UP,POLY
-S 8900,24600,10700,24600,100,*,RIGHT,POLY
-S 10700,24300,11100,24300,300,*,RIGHT,PTIE
-S 8700,24300,10100,24300,300,*,RIGHT,PTIE
-S 10400,23700,10400,23900,200,*,DOWN,POLY
-S 10700,13600,11100,13600,200,*,RIGHT,ALU1
-S 8700,13600,10100,13600,200,*,RIGHT,ALU1
-S 8900,13900,10700,13900,100,*,RIGHT,POLY
-S 10400,13300,10400,13900,200,*,UP,POLY
-S 10700,13600,11100,13600,300,*,RIGHT,NTIE
-S 8700,13600,10100,13600,300,*,RIGHT,NTIE
-S 10000,13400,10000,22700,2800,*,UP,NWELL
-S 10700,13900,10700,22200,100,*,UP,PTRANS
-S 10100,13900,10100,22200,100,*,UP,PTRANS
-S 9500,13900,9500,22200,100,*,UP,PTRANS
-S 8900,13900,8900,22200,100,*,UP,PTRANS
-S 9200,14100,9200,22000,200,*,UP,PDIF
-S 9800,14100,9800,22000,200,*,UP,PDIF
-S 10400,14100,10400,22000,200,*,UP,PDIF
-S 11000,14100,11000,22000,300,*,UP,PDIF
-S 8700,28700,11100,28700,300,*,RIGHT,PTIE
-S 10700,24600,10700,28400,100,*,UP,NTRANS
-S 10100,24600,10100,28400,100,*,UP,NTRANS
-S 9500,24600,9500,28400,100,*,UP,NTRANS
-S 8900,24600,8900,28400,100,*,UP,NTRANS
-S 9200,24800,9200,28200,300,*,UP,NDIF
-S 9800,24800,9800,28200,300,*,UP,NDIF
-S 10400,24800,10400,28200,300,*,UP,NDIF
-S 11000,24800,11000,28200,300,*,UP,NDIF
-S 9800,23700,9800,28800,200,*,UP,ALU1
-S 10400,14200,10400,29100,200,*,UP,ALU1
-S 9200,14200,9200,29100,200,*,UP,ALU1
-S 11100,22500,13500,22500,300,*,RIGHT,NTIE
-S 13300,23200,13300,23800,200,*,UP,ALU1
-S 12800,23800,13300,23800,300,*,RIGHT,POLY
-S 12800,23800,12800,24600,200,*,UP,POLY
-S 11300,24600,13100,24600,100,*,RIGHT,POLY
-S 13100,24300,13500,24300,300,*,RIGHT,PTIE
-S 11100,24300,12500,24300,300,*,RIGHT,PTIE
-S 12800,23700,12800,23900,200,*,DOWN,POLY
-S 13100,13600,13500,13600,200,*,RIGHT,ALU1
-S 11100,13600,12500,13600,200,*,RIGHT,ALU1
-S 11300,13900,13100,13900,100,*,RIGHT,POLY
-S 12800,13300,12800,13900,200,*,UP,POLY
-S 13100,13600,13500,13600,300,*,RIGHT,NTIE
-S 11100,13600,12500,13600,300,*,RIGHT,NTIE
-S 12400,13400,12400,22700,2800,*,UP,NWELL
-S 13100,13900,13100,22200,100,*,UP,PTRANS
-S 12500,13900,12500,22200,100,*,UP,PTRANS
-S 11900,13900,11900,22200,100,*,UP,PTRANS
-S 11300,13900,11300,22200,100,*,UP,PTRANS
-S 11600,14100,11600,22000,200,*,UP,PDIF
-S 12200,14100,12200,22000,200,*,UP,PDIF
-S 12800,14100,12800,22000,200,*,UP,PDIF
-S 13400,14100,13400,22000,300,*,UP,PDIF
-S 11100,28700,13500,28700,300,*,RIGHT,PTIE
-S 13100,24600,13100,28400,100,*,UP,NTRANS
-S 12500,24600,12500,28400,100,*,UP,NTRANS
-S 11900,24600,11900,28400,100,*,UP,NTRANS
-S 11300,24600,11300,28400,100,*,UP,NTRANS
-S 11600,24800,11600,28200,300,*,UP,NDIF
-S 12200,24800,12200,28200,300,*,UP,NDIF
-S 12800,24800,12800,28200,300,*,UP,NDIF
-S 13400,24800,13400,28200,300,*,UP,NDIF
-S 12200,23700,12200,28800,200,*,UP,ALU1
-S 12800,14200,12800,29100,200,*,UP,ALU1
-S 11600,14200,11600,29100,200,*,UP,ALU1
-S 13500,22500,15900,22500,300,*,RIGHT,NTIE
-S 15700,23200,15700,23800,200,*,UP,ALU1
-S 15200,23800,15700,23800,300,*,RIGHT,POLY
-S 15200,23800,15200,24600,200,*,UP,POLY
-S 13700,24600,15500,24600,100,*,RIGHT,POLY
-S 15500,24300,15900,24300,300,*,RIGHT,PTIE
-S 13500,24300,14900,24300,300,*,RIGHT,PTIE
-S 15200,23700,15200,23900,200,*,DOWN,POLY
-S 13500,13600,14900,13600,200,*,RIGHT,ALU1
-S 13700,13900,15500,13900,100,*,RIGHT,POLY
-S 15200,13300,15200,13900,200,*,UP,POLY
-S 15500,13600,15900,13600,300,*,RIGHT,NTIE
-S 13500,13600,14900,13600,300,*,RIGHT,NTIE
-S 14800,13400,14800,22700,2800,*,UP,NWELL
-S 15500,13900,15500,22200,100,*,UP,PTRANS
-S 14900,13900,14900,22200,100,*,UP,PTRANS
-S 14300,13900,14300,22200,100,*,UP,PTRANS
-S 13700,13900,13700,22200,100,*,UP,PTRANS
-S 14000,14100,14000,22000,200,*,UP,PDIF
-S 14600,14100,14600,22000,200,*,UP,PDIF
-S 15200,14100,15200,22000,200,*,UP,PDIF
-S 15800,14100,15800,22000,300,*,UP,PDIF
-S 13500,28700,15900,28700,300,*,RIGHT,PTIE
-S 15500,24600,15500,28400,100,*,UP,NTRANS
-S 14900,24600,14900,28400,100,*,UP,NTRANS
-S 14300,24600,14300,28400,100,*,UP,NTRANS
-S 13700,24600,13700,28400,100,*,UP,NTRANS
-S 14000,24800,14000,28200,300,*,UP,NDIF
-S 14600,24800,14600,28200,300,*,UP,NDIF
-S 15200,24800,15200,28200,300,*,UP,NDIF
-S 15800,24800,15800,28200,300,*,UP,NDIF
-S 14600,23700,14600,28800,200,*,UP,ALU1
-S 15200,14200,15200,29100,200,*,UP,ALU1
-S 14000,14200,14000,29100,200,*,UP,ALU1
-S 11000,5500,14600,5500,100,*,RIGHT,POLY
-S 15200,3700,15200,5500,100,*,UP,POLY
-S 14600,-100,14600,1900,800,*,DOWN,ALU1
-S 14300,0,14300,1900,300,*,DOWN,PTIE
-S 14600,0,14600,1900,300,*,DOWN,PTIE
-S 14900,-300,14900,1900,300,*,DOWN,PTIE
-S 14900,1800,16200,1800,300,*,LEFT,PTIE
-S 16100,1700,16100,4100,300,*,UP,PTIE
-S 14900,2600,14900,3500,300,*,DOWN,NDIF
-S 15400,-700,15400,2300,200,*,DOWN,ALU1
-S 14300,2600,14300,3500,300,*,UP,NDIF
-S 14600,2400,14600,3700,100,*,UP,NTRANS
-S 15200,2400,15200,3700,100,*,UP,NTRANS
-S 15500,2600,15500,3500,300,*,UP,NDIF
-S 15200,2200,15200,2400,100,*,DOWN,POLY
-S 12500,5800,12500,12900,200,*,UP,ALU1
-S 13900,3700,13900,3900,100,*,DOWN,POLY
-S 14000,3700,14000,3900,100,*,DOWN,POLY
-S 13900,4700,13900,5300,100,*,DOWN,POLY
-S 14000,4700,14000,5300,100,*,DOWN,POLY
-S 13900,4500,14600,4500,300,*,RIGHT,POLY
-S 14600,3700,14600,4300,100,*,UP,POLY
-S 14200,5100,15000,5100,300,*,RIGHT,NTIE
-S 11300,5100,13700,5100,300,*,RIGHT,NTIE
-S 7400,4000,10100,4000,300,*,RIGHT,PTIE
-S 10300,3800,10300,4500,100,*,DOWN,POLY
-S 10300,4600,10900,4600,100,*,LEFT,POLY
-S 11100,4500,11100,5300,100,*,DOWN,POLY
-S 11000,3600,11000,4100,100,*,DOWN,POLY
-S 11100,3800,11100,4100,100,*,DOWN,POLY
-S 11100,3700,14000,3700,100,*,RIGHT,POLY
-S 11100,3600,14000,3600,100,*,RIGHT,POLY
-S 11300,4000,13700,4000,300,*,RIGHT,PTIE
-S 13700,5700,13700,11500,300,*,UP,PDIF
-S 13400,5500,13400,11700,100,*,UP,PTRANS
-S 13100,5700,13100,11500,300,*,UP,PDIF
-S 12800,5500,12800,11700,100,*,UP,PTRANS
-S 12500,5700,12500,11500,300,*,UP,PDIF
-S 11900,5700,11900,11500,300,*,UP,PDIF
-S 12200,5500,12200,11700,100,*,UP,PTRANS
-S 11300,5700,11300,11500,300,*,UP,PDIF
-S 11600,5500,11600,11700,100,*,UP,PTRANS
-S 13700,600,13700,3400,300,*,UP,NDIF
-S 13100,600,13100,3400,200,*,UP,NDIF
-S 12500,600,12500,3400,300,*,UP,NDIF
-S 11900,600,11900,3400,200,*,UP,NDIF
-S 11300,600,11300,3400,300,*,UP,NDIF
-S 13400,400,13400,3600,100,*,UP,NTRANS
-S 12800,400,12800,3600,100,*,UP,NTRANS
-S 12200,400,12200,3600,100,*,UP,NTRANS
-S 11600,400,11600,3600,100,*,UP,NTRANS
-S 16100,2300,16100,4100,200,*,UP,ALU1
-S 4700,900,4700,11400,200,*,UP,ALU1
-S 5300,900,5300,11400,200,*,UP,ALU1
-S 5300,4600,7000,4600,200,*,RIGHT,ALU1
-S 9500,5700,9500,12000,200,*,UP,ALU1
-S 7100,5700,7100,12000,200,*,UP,ALU1
-S 10100,600,10100,3300,200,*,UP,ALU1
-S 8900,600,8900,3300,200,*,UP,ALU1
-S 7700,600,7700,3300,200,*,UP,ALU1
-S 6500,5800,6500,12900,200,*,UP,ALU1
-S 7700,5800,7700,12900,200,*,UP,ALU1
-S 8900,5800,8900,12900,200,*,UP,ALU1
-S 10100,5800,10100,12900,200,*,UP,ALU1
-S 6500,600,6500,3300,200,*,UP,ALU1
-S 5900,5100,6800,5100,200,*,RIGHT,ALU1
-S 4600,-700,4600,300,200,*,UP,ALU1
-S 5600,3700,5600,5400,100,*,UP,POLY
-S 4900,5300,5600,5300,300,*,RIGHT,POLY
-S 6200,3700,8000,3700,100,*,RIGHT,POLY
-S 6200,5400,8000,5400,100,*,RIGHT,POLY
-S 7100,3700,7100,5400,200,*,UP,POLY
-S 4400,3700,4400,5400,100,*,UP,POLY
-S 4400,200,4400,400,100,*,UP,POLY
-S 5800,4000,6800,4000,300,*,RIGHT,PTIE
-S 5800,5100,6800,5100,300,*,RIGHT,NTIE
-S 7400,5400,7400,11700,100,*,UP,PTRANS
-S 8000,5400,8000,11700,100,*,UP,PTRANS
-S 7100,5600,7100,11500,300,*,UP,PDIF
-S 8300,5600,8300,11500,300,*,UP,PDIF
-S 6500,5600,6500,11500,300,*,UP,PDIF
-S 10100,5600,10100,11500,300,*,UP,PDIF
-S 7700,5600,7700,11500,300,*,UP,PDIF
-S 5300,5600,5300,11500,300,*,UP,PDIF
-S 5600,5400,5600,11700,100,*,UP,PTRANS
-S 5900,5600,5900,11500,300,*,UP,PDIF
-S 6200,5400,6200,11700,100,*,UP,PTRANS
-S 6800,5400,6800,11700,100,*,UP,PTRANS
-S 9500,5600,9500,11500,300,*,UP,PDIF
-S 10700,5600,10700,11500,300,*,UP,PDIF
-S 8900,5600,8900,11500,300,*,UP,PDIF
-S 8600,5400,8600,11700,100,*,UP,PTRANS
-S 9200,5400,9200,11700,100,*,UP,PTRANS
-S 9800,5400,9800,11700,100,*,UP,PTRANS
-S 10400,5400,10400,11700,100,*,UP,PTRANS
-S 4400,5400,4400,11700,100,*,UP,PTRANS
-S 4700,5600,4700,11500,300,*,UP,PDIF
-S 4100,5600,4100,11500,300,*,UP,PDIF
-S 7400,400,7400,3700,100,*,UP,NTRANS
-S 8000,400,8000,3700,100,*,UP,NTRANS
-S 7100,600,7100,3500,200,*,UP,NDIF
-S 8300,600,8300,3500,200,*,UP,NDIF
-S 6500,600,6500,3500,300,*,UP,NDIF
-S 7700,600,7700,3500,300,*,UP,NDIF
-S 5300,600,5300,3500,300,*,UP,NDIF
-S 5600,400,5600,3700,100,*,UP,NTRANS
-S 5900,600,5900,3500,200,*,UP,NDIF
-S 6200,400,6200,3700,100,*,UP,NTRANS
-S 6800,400,6800,3700,100,*,UP,NTRANS
-S 10400,400,10400,3700,100,*,UP,NTRANS
-S 9500,600,9500,3500,200,*,UP,NDIF
-S 8900,600,8900,3500,300,*,UP,NDIF
-S 8600,400,8600,3700,100,*,UP,NTRANS
-S 10100,600,10100,3500,300,*,UP,NDIF
-S 9200,400,9200,3700,100,*,UP,NTRANS
-S 9800,400,9800,3700,100,*,UP,NTRANS
-S 4100,600,4100,3500,200,*,UP,NDIF
-S 4400,400,4400,3700,100,*,UP,NTRANS
-S 4700,600,4700,3500,300,*,UP,NDIF
-S 16100,5000,16100,12100,200,*,UP,ALU1
-S 16100,5000,16100,12100,300,*,UP,NTIE
-S 13100,700,13100,3900,200,*,UP,ALU1
-S 11300,600,11300,4600,200,*,UP,ALU1
-S 11900,3900,13700,3900,200,*,RIGHT,ALU1
-S 13700,600,13700,3300,200,*,UP,ALU1
-S 12500,600,12500,3300,200,*,UP,ALU1
-S 11900,700,11900,3900,200,*,UP,ALU1
-S 13700,3900,13700,12900,200,*,UP,ALU1
-S 11300,5800,11300,12900,200,*,UP,ALU1
-S 11900,4600,11900,11400,200,*,UP,ALU1
-S 13100,4600,13100,11400,200,*,UP,ALU1
-S 8600,5400,10400,5400,100,*,RIGHT,POLY
-S 8600,3700,10400,3700,100,*,RIGHT,POLY
-S 9500,4600,9500,5400,300,*,DOWN,POLY
-S 10500,4500,11000,4500,100,*,LEFT,POLY
-S 11000,4500,11000,5400,100,*,DOWN,POLY
-S 7400,5100,9200,5100,300,*,RIGHT,NTIE
-S 9800,5100,10700,5100,300,*,RIGHT,NTIE
-S 10700,600,10700,3500,300,*,UP,NDIF
-S 14900,5000,14900,12100,200,*,UP,ALU1
-S 11000,5400,14600,5400,100,*,RIGHT,POLY
-S 15400,4000,16200,4000,300,*,LEFT,PTIE
-S 15400,5100,16200,5100,300,*,RIGHT,NTIE
-S 9400,4600,10800,4600,200,*,LEFT,ALU1
-S 10400,3700,10400,4500,100,*,DOWN,POLY
-S 10800,3900,10800,4600,200,*,UP,ALU1
-S 15200,8100,15200,12100,2000,*,DOWN,ALU1
-S 15200,8100,15200,12000,2000,*,DOWN,NTIE
-S 15200,5500,15200,7800,100,*,UP,PTRANS
-S 14600,5500,14600,7800,100,*,UP,PTRANS
-S 14900,5700,14900,7600,300,*,UP,PDIF
-S 15500,5700,15500,7600,300,*,UP,PDIF
-S 14300,5700,14300,7600,300,*,UP,PDIF
-S 15500,2800,15500,7500,200,*,UP,ALU1
-S 14300,2700,14300,7500,200,*,UP,ALU1
-S 3300,5700,3300,9300,200,*,DOWN,ALU1
-S 3100,9200,3100,9400,200,*,DOWN,ALU1
-S 2700,5100,2700,6400,1100,*,DOWN,NTIE
-S 3300,9700,3300,12000,300,*,UP,NTIE
-S 3300,5000,3300,9100,300,*,UP,NTIE
-S 3500,8900,3500,9900,300,*,UP,NTIE
-S 2000,5100,4000,5100,300,*,RIGHT,NTIE
-S 2100,5000,2100,12100,300,*,UP,NTIE
-S 2000,12000,16200,12000,300,*,RIGHT,NTIE
-S 4100,600,4100,3500,300,*,UP,NDIF
-S 3500,-300,3500,4100,300,*,UP,PTIE
-S 3400,4000,4200,4000,300,*,RIGHT,PTIE
-S 3400,-200,15000,-200,300,*,RIGHT,PTIE
-S 3800,-300,3800,4100,800,*,UP,ALU1
-S 1900,5100,16300,5100,400,*,RIGHT,NWELL
-S 1900,8600,16300,8600,7200,*,RIGHT,NWELL
-S 8600,30100,8600,35600,12600,*,UP,ALU1
-S 3700,23100,3700,23800,200,*,UP,ALU1
-S 1900,29600,15300,29600,900,*,RIGHT,ALU1
-S 15800,28900,15800,29300,200,*,UP,ALU1
-S 700,28000,700,28800,100,*,UP,ALU1
-S 1100,24200,1100,29300,800,*,UP,ALU1
-S 3700,13000,15300,13000,200,*,RIGHT,ALU1
-S 3700,13100,15300,13100,200,*,RIGHT,ALU1
-S 1100,13500,1100,22600,800,*,UP,ALU1
-S 15900,24300,16500,24300,300,*,RIGHT,PTIE
-S 16000,28700,16500,28700,300,*,RIGHT,PTIE
-S 16400,24200,16400,28800,300,*,UP,PTIE
-S 700,24300,1500,24300,300,*,RIGHT,PTIE
-S 800,24200,800,28800,300,*,UP,PTIE
-S 700,28700,1500,28700,300,*,RIGHT,PTIE
-S 16000,22500,16500,22500,300,*,RIGHT,NTIE
-S 800,22500,1400,22500,300,*,RIGHT,NTIE
-S 16400,13600,16400,22600,300,*,UP,NTIE
-S 16000,13600,16500,13600,300,*,RIGHT,NTIE
-S 800,13600,800,22600,300,*,UP,NTIE
-S 800,13600,1400,13600,300,*,RIGHT,NTIE
-S 1400,14100,1400,22000,300,*,UP,PDIF
-S 1400,24900,1400,28200,300,*,UP,NDIF
-S 16300,13400,16300,22700,600,*,UP,NWELL
-S 1000,13400,1000,22700,800,*,UP,NWELL
-S 2400,9100,3000,9100,3900,*,RIGHT,PTRANS
-V 16400,1600,CONT_VIA,*
-B 1100,18100,800,9000,CONT_VIA,*
-B 15200,9200,2000,2200,CONT_VIA,*
-B 16100,18100,800,9000,CONT_VIA,*
-B 1100,26700,800,5100,CONT_VIA,*
-B 10800,4600,200,200,CONT_TURN1,*
-B 11300,4600,200,200,CONT_TURN1,*
-B 13100,4600,200,200,CONT_TURN1,*
-B 11900,3900,200,200,CONT_TURN1,*
-B 13700,3900,200,200,CONT_TURN1,*
-V 3700,13600,CONT_BODY_N,*
-V 3800,13100,CONT_POLY,*
-V 3800,27700,CONT_DIF_N,*
-V 3800,26100,CONT_DIF_N,*
-V 3800,25700,CONT_DIF_N,*
-V 3800,27300,CONT_DIF_N,*
-V 3800,26900,CONT_DIF_N,*
-V 3800,25300,CONT_DIF_N,*
-V 3800,26500,CONT_VIA,*
-V 3800,24900,CONT_VIA,*
-V 3800,28100,CONT_VIA,*
-V 2600,24900,CONT_VIA,*
-V 2600,25300,CONT_DIF_N,*
-V 2600,26900,CONT_DIF_N,*
-V 2600,27300,CONT_DIF_N,*
-V 2600,26500,CONT_DIF_N,*
-V 2600,28100,CONT_DIF_N,*
-V 2600,25700,CONT_DIF_N,*
-V 2600,27700,CONT_VIA,*
-V 2600,26100,CONT_VIA,*
-V 3800,28700,CONT_BODY_P,*
-V 2600,28700,CONT_BODY_P,*
-V 2200,13600,CONT_BODY_N,*
-V 2000,25000,CONT_DIF_N,*
-V 2000,27400,CONT_DIF_N,*
-V 2000,27800,CONT_DIF_N,*
-V 2000,25400,CONT_DIF_N,*
-V 2000,25800,CONT_DIF_N,*
-V 2000,26200,CONT_DIF_N,*
-V 2000,26600,CONT_DIF_N,*
-V 2000,27000,CONT_DIF_N,*
-V 3200,25800,CONT_DIF_N,*
-V 3200,26200,CONT_DIF_N,*
-V 3200,25400,CONT_DIF_N,*
-V 3200,25000,CONT_DIF_N,*
-V 3200,27800,CONT_DIF_N,*
-V 3200,26600,CONT_DIF_N,*
-V 3200,27000,CONT_DIF_N,*
-V 3200,27400,CONT_DIF_N,*
-V 2600,14300,CONT_DIF_P,*
-V 2000,14700,CONT_DIF_P,*
-V 2600,14700,CONT_DIF_P,*
-V 2000,15100,CONT_DIF_P,*
-V 2000,14300,CONT_DIF_P,*
-V 3200,14300,CONT_DIF_P,*
-V 3800,14300,CONT_DIF_P,*
-V 3200,14700,CONT_DIF_P,*
-V 3800,14700,CONT_DIF_P,*
-V 3200,15100,CONT_DIF_P,*
-V 2600,15500,CONT_DIF_P,*
-V 2000,15500,CONT_DIF_P,*
-V 2000,19500,CONT_DIF_P,*
-V 2000,17900,CONT_DIF_P,*
-V 2600,17900,CONT_DIF_P,*
-V 2000,18300,CONT_DIF_P,*
-V 2600,18300,CONT_DIF_P,*
-V 2000,18700,CONT_DIF_P,*
-V 2000,19100,CONT_DIF_P,*
-V 2600,19100,CONT_DIF_P,*
-V 2600,19500,CONT_DIF_P,*
-V 2000,16300,CONT_DIF_P,*
-V 2000,15900,CONT_DIF_P,*
-V 2600,15900,CONT_DIF_P,*
-V 2000,17500,CONT_DIF_P,*
-V 2000,17100,CONT_DIF_P,*
-V 2000,16700,CONT_DIF_P,*
-V 2600,16700,CONT_DIF_P,*
-V 2600,17100,CONT_DIF_P,*
-V 3200,15500,CONT_DIF_P,*
-V 3800,15500,CONT_DIF_P,*
-V 3800,19500,CONT_DIF_P,*
-V 3200,18300,CONT_DIF_P,*
-V 3200,18700,CONT_DIF_P,*
-V 3200,19100,CONT_DIF_P,*
-V 3800,19100,CONT_DIF_P,*
-V 3200,19500,CONT_DIF_P,*
-V 3200,17500,CONT_DIF_P,*
-V 3200,17100,CONT_DIF_P,*
-V 3200,17900,CONT_DIF_P,*
-V 3800,17900,CONT_DIF_P,*
-V 3800,18300,CONT_DIF_P,*
-V 3200,16300,CONT_DIF_P,*
-V 3200,15900,CONT_DIF_P,*
-V 3800,15900,CONT_DIF_P,*
-V 3800,17100,CONT_DIF_P,*
-V 3800,16700,CONT_DIF_P,*
-V 3200,16700,CONT_DIF_P,*
-V 2600,15100,CONT_VIA,*
-V 3800,15100,CONT_VIA,*
-V 2600,17500,CONT_VIA,*
-V 2600,18700,CONT_VIA,*
-V 2600,16300,CONT_VIA,*
-V 3800,18700,CONT_VIA,*
-V 3800,17500,CONT_VIA,*
-V 3800,16300,CONT_VIA,*
-V 2000,19900,CONT_DIF_P,*
-V 3200,19900,CONT_DIF_P,*
-V 2600,19900,CONT_VIA,*
-V 3800,19900,CONT_VIA,*
-V 2000,20300,CONT_DIF_P,*
-V 3200,20300,CONT_DIF_P,*
-V 2600,20300,CONT_DIF_P,*
-V 3800,20300,CONT_DIF_P,*
-V 2600,20700,CONT_DIF_P,*
-V 3800,20700,CONT_DIF_P,*
-V 3200,20700,CONT_DIF_P,*
-V 2000,20700,CONT_DIF_P,*
-V 2000,21100,CONT_DIF_P,*
-V 3200,21100,CONT_DIF_P,*
-V 3800,21100,CONT_VIA,*
-V 2600,21100,CONT_VIA,*
-V 2000,21500,CONT_DIF_P,*
-V 2600,21500,CONT_DIF_P,*
-V 3200,21500,CONT_DIF_P,*
-V 3800,21500,CONT_DIF_P,*
-V 2600,24300,CONT_BODY_P,*
-V 3800,24300,CONT_BODY_P,*
-V 3700,23800,CONT_POLY,*
-V 2600,23800,CONT_VIA,*
-V 3800,22500,CONT_BODY_N,*
-V 2600,22500,CONT_BODY_N,*
-V 3800,21900,CONT_DIF_P,*
-V 3200,21900,CONT_DIF_P,*
-V 2600,21900,CONT_DIF_P,*
-V 2000,21900,CONT_DIF_P,*
-V 2600,13600,CONT_VIA,*
-V 1700,13600,CONT_BODY_N,*
-V 4400,21900,CONT_DIF_P,*
-V 5000,21900,CONT_DIF_P,*
-V 5600,21900,CONT_DIF_P,*
-V 6200,21900,CONT_DIF_P,*
-V 5000,22500,CONT_BODY_N,*
-V 6200,22500,CONT_BODY_N,*
-V 6100,23200,CONT_VIA,*
-V 5000,23800,CONT_VIA,*
-V 6100,23800,CONT_POLY,*
-V 6200,24300,CONT_BODY_P,*
-V 5000,24300,CONT_BODY_P,*
-V 6200,21500,CONT_DIF_P,*
-V 5600,21500,CONT_DIF_P,*
-V 5000,21500,CONT_DIF_P,*
-V 4400,21500,CONT_DIF_P,*
-V 5000,21100,CONT_VIA,*
-V 6200,21100,CONT_VIA,*
-V 5600,21100,CONT_DIF_P,*
-V 4400,21100,CONT_DIF_P,*
-V 4400,20700,CONT_DIF_P,*
-V 5600,20700,CONT_DIF_P,*
-V 6200,20700,CONT_DIF_P,*
-V 5000,20700,CONT_DIF_P,*
-V 6200,20300,CONT_DIF_P,*
-V 5000,20300,CONT_DIF_P,*
-V 5600,20300,CONT_DIF_P,*
-V 4400,20300,CONT_DIF_P,*
-V 6200,19900,CONT_VIA,*
-V 5000,19900,CONT_VIA,*
-V 5600,19900,CONT_DIF_P,*
-V 4400,19900,CONT_DIF_P,*
-V 6200,16300,CONT_VIA,*
-V 6200,17500,CONT_VIA,*
-V 6200,18700,CONT_VIA,*
-V 5000,16300,CONT_VIA,*
-V 5000,18700,CONT_VIA,*
-V 5000,17500,CONT_VIA,*
-V 6200,15100,CONT_VIA,*
-V 5000,15100,CONT_VIA,*
-V 5600,16700,CONT_DIF_P,*
-V 6200,16700,CONT_DIF_P,*
-V 6200,17100,CONT_DIF_P,*
-V 6200,15900,CONT_DIF_P,*
-V 5600,15900,CONT_DIF_P,*
-V 5600,16300,CONT_DIF_P,*
-V 6200,18300,CONT_DIF_P,*
-V 6200,17900,CONT_DIF_P,*
-V 5600,17900,CONT_DIF_P,*
-V 5600,17100,CONT_DIF_P,*
-V 5600,17500,CONT_DIF_P,*
-V 5600,19500,CONT_DIF_P,*
-V 6200,19100,CONT_DIF_P,*
-V 5600,19100,CONT_DIF_P,*
-V 5600,18700,CONT_DIF_P,*
-V 5600,18300,CONT_DIF_P,*
-V 6200,19500,CONT_DIF_P,*
-V 6200,15500,CONT_DIF_P,*
-V 5600,15500,CONT_DIF_P,*
-V 5000,17100,CONT_DIF_P,*
-V 5000,16700,CONT_DIF_P,*
-V 4400,16700,CONT_DIF_P,*
-V 4400,17100,CONT_DIF_P,*
-V 4400,17500,CONT_DIF_P,*
-V 5000,15900,CONT_DIF_P,*
-V 4400,15900,CONT_DIF_P,*
-V 4400,16300,CONT_DIF_P,*
-V 5000,19500,CONT_DIF_P,*
-V 5000,19100,CONT_DIF_P,*
-V 4400,19100,CONT_DIF_P,*
-V 4400,18700,CONT_DIF_P,*
-V 5000,18300,CONT_DIF_P,*
-V 4400,18300,CONT_DIF_P,*
-V 5000,17900,CONT_DIF_P,*
-V 4400,17900,CONT_DIF_P,*
-V 4400,19500,CONT_DIF_P,*
-V 4400,15500,CONT_DIF_P,*
-V 5000,15500,CONT_DIF_P,*
-V 5600,15100,CONT_DIF_P,*
-V 6200,14700,CONT_DIF_P,*
-V 5600,14700,CONT_DIF_P,*
-V 6200,14300,CONT_DIF_P,*
-V 5600,14300,CONT_DIF_P,*
-V 4400,14300,CONT_DIF_P,*
-V 4400,15100,CONT_DIF_P,*
-V 5000,14700,CONT_DIF_P,*
-V 4400,14700,CONT_DIF_P,*
-V 5000,14300,CONT_DIF_P,*
-V 5600,27400,CONT_DIF_N,*
-V 5600,27000,CONT_DIF_N,*
-V 5600,26600,CONT_DIF_N,*
-V 5600,27800,CONT_DIF_N,*
-V 5600,25000,CONT_DIF_N,*
-V 5600,25400,CONT_DIF_N,*
-V 5600,26200,CONT_DIF_N,*
-V 5600,25800,CONT_DIF_N,*
-V 4400,27000,CONT_DIF_N,*
-V 4400,26600,CONT_DIF_N,*
-V 4400,26200,CONT_DIF_N,*
-V 4400,25800,CONT_DIF_N,*
-V 4400,25400,CONT_DIF_N,*
-V 4400,27800,CONT_DIF_N,*
-V 4400,27400,CONT_DIF_N,*
-V 4400,25000,CONT_DIF_N,*
-V 4900,13600,CONT_VIA,*
-V 5600,13100,CONT_POLY,*
-V 6000,13600,CONT_BODY_N,*
-V 4600,13600,CONT_BODY_N,*
-V 5200,13600,CONT_BODY_N,*
-V 4100,13600,CONT_BODY_N,*
-V 5000,28700,CONT_BODY_P,*
-V 6200,28700,CONT_BODY_P,*
-V 5000,26100,CONT_VIA,*
-V 5000,27700,CONT_VIA,*
-V 5000,25700,CONT_DIF_N,*
-V 5000,28100,CONT_DIF_N,*
-V 5000,26500,CONT_DIF_N,*
-V 5000,27300,CONT_DIF_N,*
-V 5000,26900,CONT_DIF_N,*
-V 5000,25300,CONT_DIF_N,*
-V 5000,24900,CONT_VIA,*
-V 6200,28100,CONT_VIA,*
-V 6200,24900,CONT_VIA,*
-V 6200,26500,CONT_VIA,*
-V 6200,25300,CONT_DIF_N,*
-V 6200,26900,CONT_DIF_N,*
-V 6200,27300,CONT_DIF_N,*
-V 6200,25700,CONT_DIF_N,*
-V 6200,26100,CONT_DIF_N,*
-V 6200,27700,CONT_DIF_N,*
-V 6800,21900,CONT_DIF_P,*
-V 7400,21900,CONT_DIF_P,*
-V 8000,21900,CONT_DIF_P,*
-V 8600,21900,CONT_DIF_P,*
-V 7400,22500,CONT_BODY_N,*
-V 8600,22500,CONT_BODY_N,*
-V 8500,23200,CONT_VIA,*
-V 7400,23800,CONT_VIA,*
-V 8500,23800,CONT_POLY,*
-V 8600,24300,CONT_BODY_P,*
-V 7400,24300,CONT_BODY_P,*
-V 8600,21500,CONT_DIF_P,*
-V 8000,21500,CONT_DIF_P,*
-V 7400,21500,CONT_DIF_P,*
-V 6800,21500,CONT_DIF_P,*
-V 7400,21100,CONT_VIA,*
-V 8600,21100,CONT_VIA,*
-V 8000,21100,CONT_DIF_P,*
-V 6800,21100,CONT_DIF_P,*
-V 6800,20700,CONT_DIF_P,*
-V 8000,20700,CONT_DIF_P,*
-V 8600,20700,CONT_DIF_P,*
-V 7400,20700,CONT_DIF_P,*
-V 8600,20300,CONT_DIF_P,*
-V 7400,20300,CONT_DIF_P,*
-V 8000,20300,CONT_DIF_P,*
-V 6800,20300,CONT_DIF_P,*
-V 8600,19900,CONT_VIA,*
-V 7400,19900,CONT_VIA,*
-V 8000,19900,CONT_DIF_P,*
-V 6800,19900,CONT_DIF_P,*
-V 8600,16300,CONT_VIA,*
-V 8600,17500,CONT_VIA,*
-V 8600,18700,CONT_VIA,*
-V 7400,16300,CONT_VIA,*
-V 7400,18700,CONT_VIA,*
-V 7400,17500,CONT_VIA,*
-V 8600,15100,CONT_VIA,*
-V 7400,15100,CONT_VIA,*
-V 8000,16700,CONT_DIF_P,*
-V 8600,16700,CONT_DIF_P,*
-V 8600,17100,CONT_DIF_P,*
-V 8600,15900,CONT_DIF_P,*
-V 8000,15900,CONT_DIF_P,*
-V 8000,16300,CONT_DIF_P,*
-V 8600,18300,CONT_DIF_P,*
-V 8600,17900,CONT_DIF_P,*
-V 8000,17900,CONT_DIF_P,*
-V 8000,17100,CONT_DIF_P,*
-V 8000,17500,CONT_DIF_P,*
-V 8000,19500,CONT_DIF_P,*
-V 8600,19100,CONT_DIF_P,*
-V 8000,19100,CONT_DIF_P,*
-V 8000,18700,CONT_DIF_P,*
-V 8000,18300,CONT_DIF_P,*
-V 8600,19500,CONT_DIF_P,*
-V 8600,15500,CONT_DIF_P,*
-V 8000,15500,CONT_DIF_P,*
-V 7400,17100,CONT_DIF_P,*
-V 7400,16700,CONT_DIF_P,*
-V 6800,16700,CONT_DIF_P,*
-V 6800,17100,CONT_DIF_P,*
-V 6800,17500,CONT_DIF_P,*
-V 7400,15900,CONT_DIF_P,*
-V 6800,15900,CONT_DIF_P,*
-V 6800,16300,CONT_DIF_P,*
-V 7400,19500,CONT_DIF_P,*
-V 7400,19100,CONT_DIF_P,*
-V 6800,19100,CONT_DIF_P,*
-V 6800,18700,CONT_DIF_P,*
-V 7400,18300,CONT_DIF_P,*
-V 6800,18300,CONT_DIF_P,*
-V 7400,17900,CONT_DIF_P,*
-V 6800,17900,CONT_DIF_P,*
-V 6800,19500,CONT_DIF_P,*
-V 6800,15500,CONT_DIF_P,*
-V 7400,15500,CONT_DIF_P,*
-V 8000,15100,CONT_DIF_P,*
-V 8600,14700,CONT_DIF_P,*
-V 8000,14700,CONT_DIF_P,*
-V 8600,14300,CONT_DIF_P,*
-V 8000,14300,CONT_DIF_P,*
-V 6800,14300,CONT_DIF_P,*
-V 6800,15100,CONT_DIF_P,*
-V 7400,14700,CONT_DIF_P,*
-V 6800,14700,CONT_DIF_P,*
-V 7400,14300,CONT_DIF_P,*
-V 8000,27400,CONT_DIF_N,*
-V 8000,27000,CONT_DIF_N,*
-V 8000,26600,CONT_DIF_N,*
-V 8000,27800,CONT_DIF_N,*
-V 8000,25000,CONT_DIF_N,*
-V 8000,25400,CONT_DIF_N,*
-V 8000,26200,CONT_DIF_N,*
-V 8000,25800,CONT_DIF_N,*
-V 6800,27000,CONT_DIF_N,*
-V 6800,26600,CONT_DIF_N,*
-V 6800,26200,CONT_DIF_N,*
-V 6800,25800,CONT_DIF_N,*
-V 6800,25400,CONT_DIF_N,*
-V 6800,27800,CONT_DIF_N,*
-V 6800,27400,CONT_DIF_N,*
-V 6800,25000,CONT_DIF_N,*
-V 7300,13600,CONT_VIA,*
-V 8000,13100,CONT_POLY,*
-V 8400,13600,CONT_BODY_N,*
-V 7000,13600,CONT_BODY_N,*
-V 7600,13600,CONT_BODY_N,*
-V 6500,13600,CONT_BODY_N,*
-V 7400,28700,CONT_BODY_P,*
-V 8600,28700,CONT_BODY_P,*
-V 7400,26100,CONT_VIA,*
-V 7400,27700,CONT_VIA,*
-V 7400,25700,CONT_DIF_N,*
-V 7400,28100,CONT_DIF_N,*
-V 7400,26500,CONT_DIF_N,*
-V 7400,27300,CONT_DIF_N,*
-V 7400,26900,CONT_DIF_N,*
-V 7400,25300,CONT_DIF_N,*
-V 7400,24900,CONT_VIA,*
-V 8600,28100,CONT_VIA,*
-V 8600,24900,CONT_VIA,*
-V 8600,26500,CONT_VIA,*
-V 8600,25300,CONT_DIF_N,*
-V 8600,26900,CONT_DIF_N,*
-V 8600,27300,CONT_DIF_N,*
-V 8600,25700,CONT_DIF_N,*
-V 8600,26100,CONT_DIF_N,*
-V 8600,27700,CONT_DIF_N,*
-V 9200,21900,CONT_DIF_P,*
-V 9800,21900,CONT_DIF_P,*
-V 10400,21900,CONT_DIF_P,*
-V 11000,21900,CONT_DIF_P,*
-V 9800,22500,CONT_BODY_N,*
-V 11000,22500,CONT_BODY_N,*
-V 10900,23200,CONT_VIA,*
-V 9800,23800,CONT_VIA,*
-V 10900,23800,CONT_POLY,*
-V 11000,24300,CONT_BODY_P,*
-V 9800,24300,CONT_BODY_P,*
-V 11000,21500,CONT_DIF_P,*
-V 10400,21500,CONT_DIF_P,*
-V 9800,21500,CONT_DIF_P,*
-V 9200,21500,CONT_DIF_P,*
-V 9800,21100,CONT_VIA,*
-V 11000,21100,CONT_VIA,*
-V 10400,21100,CONT_DIF_P,*
-V 9200,21100,CONT_DIF_P,*
-V 9200,20700,CONT_DIF_P,*
-V 10400,20700,CONT_DIF_P,*
-V 11000,20700,CONT_DIF_P,*
-V 9800,20700,CONT_DIF_P,*
-V 11000,20300,CONT_DIF_P,*
-V 9800,20300,CONT_DIF_P,*
-V 10400,20300,CONT_DIF_P,*
-V 9200,20300,CONT_DIF_P,*
-V 11000,19900,CONT_VIA,*
-V 9800,19900,CONT_VIA,*
-V 10400,19900,CONT_DIF_P,*
-V 9200,19900,CONT_DIF_P,*
-V 11000,16300,CONT_VIA,*
-V 11000,17500,CONT_VIA,*
-V 11000,18700,CONT_VIA,*
-V 9800,16300,CONT_VIA,*
-V 9800,18700,CONT_VIA,*
-V 9800,17500,CONT_VIA,*
-V 11000,15100,CONT_VIA,*
-V 9800,15100,CONT_VIA,*
-V 10400,16700,CONT_DIF_P,*
-V 11000,16700,CONT_DIF_P,*
-V 11000,17100,CONT_DIF_P,*
-V 11000,15900,CONT_DIF_P,*
-V 10400,15900,CONT_DIF_P,*
-V 10400,16300,CONT_DIF_P,*
-V 11000,18300,CONT_DIF_P,*
-V 11000,17900,CONT_DIF_P,*
-V 10400,17900,CONT_DIF_P,*
-V 10400,17100,CONT_DIF_P,*
-V 10400,17500,CONT_DIF_P,*
-V 10400,19500,CONT_DIF_P,*
-V 11000,19100,CONT_DIF_P,*
-V 10400,19100,CONT_DIF_P,*
-V 10400,18700,CONT_DIF_P,*
-V 10400,18300,CONT_DIF_P,*
-V 11000,19500,CONT_DIF_P,*
-V 11000,15500,CONT_DIF_P,*
-V 10400,15500,CONT_DIF_P,*
-V 9800,17100,CONT_DIF_P,*
-V 9800,16700,CONT_DIF_P,*
-V 9200,16700,CONT_DIF_P,*
-V 9200,17100,CONT_DIF_P,*
-V 9200,17500,CONT_DIF_P,*
-V 9800,15900,CONT_DIF_P,*
-V 9200,15900,CONT_DIF_P,*
-V 9200,16300,CONT_DIF_P,*
-V 9800,19500,CONT_DIF_P,*
-V 9800,19100,CONT_DIF_P,*
-V 9200,19100,CONT_DIF_P,*
-V 9200,18700,CONT_DIF_P,*
-V 9800,18300,CONT_DIF_P,*
-V 9200,18300,CONT_DIF_P,*
-V 9800,17900,CONT_DIF_P,*
-V 9200,17900,CONT_DIF_P,*
-V 9200,19500,CONT_DIF_P,*
-V 9200,15500,CONT_DIF_P,*
-V 9800,15500,CONT_DIF_P,*
-V 10400,15100,CONT_DIF_P,*
-V 11000,14700,CONT_DIF_P,*
-V 10400,14700,CONT_DIF_P,*
-V 11000,14300,CONT_DIF_P,*
-V 10400,14300,CONT_DIF_P,*
-V 9200,14300,CONT_DIF_P,*
-V 9200,15100,CONT_DIF_P,*
-V 9800,14700,CONT_DIF_P,*
-V 9200,14700,CONT_DIF_P,*
-V 9800,14300,CONT_DIF_P,*
-V 10400,27400,CONT_DIF_N,*
-V 10400,27000,CONT_DIF_N,*
-V 10400,26600,CONT_DIF_N,*
-V 10400,27800,CONT_DIF_N,*
-V 10400,25000,CONT_DIF_N,*
-V 10400,25400,CONT_DIF_N,*
-V 10400,26200,CONT_DIF_N,*
-V 10400,25800,CONT_DIF_N,*
-V 9200,27000,CONT_DIF_N,*
-V 9200,26600,CONT_DIF_N,*
-V 9200,26200,CONT_DIF_N,*
-V 9200,25800,CONT_DIF_N,*
-V 9200,25400,CONT_DIF_N,*
-V 9200,27800,CONT_DIF_N,*
-V 9200,27400,CONT_DIF_N,*
-V 9200,25000,CONT_DIF_N,*
-V 9700,13600,CONT_VIA,*
-V 10400,13100,CONT_POLY,*
-V 10800,13600,CONT_BODY_N,*
-V 9400,13600,CONT_BODY_N,*
-V 10000,13600,CONT_BODY_N,*
-V 8900,13600,CONT_BODY_N,*
-V 9800,28700,CONT_BODY_P,*
-V 11000,28700,CONT_BODY_P,*
-V 9800,26100,CONT_VIA,*
-V 9800,27700,CONT_VIA,*
-V 9800,25700,CONT_DIF_N,*
-V 9800,28100,CONT_DIF_N,*
-V 9800,26500,CONT_DIF_N,*
-V 9800,27300,CONT_DIF_N,*
-V 9800,26900,CONT_DIF_N,*
-V 9800,25300,CONT_DIF_N,*
-V 9800,24900,CONT_VIA,*
-V 11000,28100,CONT_VIA,*
-V 11000,24900,CONT_VIA,*
-V 11000,26500,CONT_VIA,*
-V 11000,25300,CONT_DIF_N,*
-V 11000,26900,CONT_DIF_N,*
-V 11000,27300,CONT_DIF_N,*
-V 11000,25700,CONT_DIF_N,*
-V 11000,26100,CONT_DIF_N,*
-V 11000,27700,CONT_DIF_N,*
-V 11600,21900,CONT_DIF_P,*
-V 12200,21900,CONT_DIF_P,*
-V 12800,21900,CONT_DIF_P,*
-V 13400,21900,CONT_DIF_P,*
-V 12200,22500,CONT_BODY_N,*
-V 13400,22500,CONT_BODY_N,*
-V 13300,23200,CONT_VIA,*
-V 12200,23800,CONT_VIA,*
-V 13300,23800,CONT_POLY,*
-V 13400,24300,CONT_BODY_P,*
-V 12200,24300,CONT_BODY_P,*
-V 13400,21500,CONT_DIF_P,*
-V 12800,21500,CONT_DIF_P,*
-V 12200,21500,CONT_DIF_P,*
-V 11600,21500,CONT_DIF_P,*
-V 12200,21100,CONT_VIA,*
-V 13400,21100,CONT_VIA,*
-V 12800,21100,CONT_DIF_P,*
-V 11600,21100,CONT_DIF_P,*
-V 11600,20700,CONT_DIF_P,*
-V 12800,20700,CONT_DIF_P,*
-V 13400,20700,CONT_DIF_P,*
-V 12200,20700,CONT_DIF_P,*
-V 13400,20300,CONT_DIF_P,*
-V 12200,20300,CONT_DIF_P,*
-V 12800,20300,CONT_DIF_P,*
-V 11600,20300,CONT_DIF_P,*
-V 13400,19900,CONT_VIA,*
-V 12200,19900,CONT_VIA,*
-V 12800,19900,CONT_DIF_P,*
-V 11600,19900,CONT_DIF_P,*
-V 13400,16300,CONT_VIA,*
-V 13400,17500,CONT_VIA,*
-V 13400,18700,CONT_VIA,*
-V 12200,16300,CONT_VIA,*
-V 12200,18700,CONT_VIA,*
-V 12200,17500,CONT_VIA,*
-V 13400,15100,CONT_VIA,*
-V 12200,15100,CONT_VIA,*
-V 12800,16700,CONT_DIF_P,*
-V 13400,16700,CONT_DIF_P,*
-V 13400,17100,CONT_DIF_P,*
-V 13400,15900,CONT_DIF_P,*
-V 12800,15900,CONT_DIF_P,*
-V 12800,16300,CONT_DIF_P,*
-V 13400,18300,CONT_DIF_P,*
-V 13400,17900,CONT_DIF_P,*
-V 12800,17900,CONT_DIF_P,*
-V 12800,17100,CONT_DIF_P,*
-V 12800,17500,CONT_DIF_P,*
-V 12800,19500,CONT_DIF_P,*
-V 13400,19100,CONT_DIF_P,*
-V 12800,19100,CONT_DIF_P,*
-V 12800,18700,CONT_DIF_P,*
-V 12800,18300,CONT_DIF_P,*
-V 13400,19500,CONT_DIF_P,*
-V 13400,15500,CONT_DIF_P,*
-V 12800,15500,CONT_DIF_P,*
-V 12200,17100,CONT_DIF_P,*
-V 12200,16700,CONT_DIF_P,*
-V 11600,16700,CONT_DIF_P,*
-V 11600,17100,CONT_DIF_P,*
-V 11600,17500,CONT_DIF_P,*
-V 12200,15900,CONT_DIF_P,*
-V 11600,15900,CONT_DIF_P,*
-V 11600,16300,CONT_DIF_P,*
-V 12200,19500,CONT_DIF_P,*
-V 12200,19100,CONT_DIF_P,*
-V 11600,19100,CONT_DIF_P,*
-V 11600,18700,CONT_DIF_P,*
-V 12200,18300,CONT_DIF_P,*
-V 11600,18300,CONT_DIF_P,*
-V 12200,17900,CONT_DIF_P,*
-V 11600,17900,CONT_DIF_P,*
-V 11600,19500,CONT_DIF_P,*
-V 11600,15500,CONT_DIF_P,*
-V 12200,15500,CONT_DIF_P,*
-V 12800,15100,CONT_DIF_P,*
-V 13400,14700,CONT_DIF_P,*
-V 12800,14700,CONT_DIF_P,*
-V 13400,14300,CONT_DIF_P,*
-V 12800,14300,CONT_DIF_P,*
-V 11600,14300,CONT_DIF_P,*
-V 11600,15100,CONT_DIF_P,*
-V 12200,14700,CONT_DIF_P,*
-V 11600,14700,CONT_DIF_P,*
-V 12200,14300,CONT_DIF_P,*
-V 12800,27400,CONT_DIF_N,*
-V 12800,27000,CONT_DIF_N,*
-V 12800,26600,CONT_DIF_N,*
-V 12800,27800,CONT_DIF_N,*
-V 12800,25000,CONT_DIF_N,*
-V 12800,25400,CONT_DIF_N,*
-V 12800,26200,CONT_DIF_N,*
-V 12800,25800,CONT_DIF_N,*
-V 11600,27000,CONT_DIF_N,*
-V 11600,26600,CONT_DIF_N,*
-V 11600,26200,CONT_DIF_N,*
-V 11600,25800,CONT_DIF_N,*
-V 11600,25400,CONT_DIF_N,*
-V 11600,27800,CONT_DIF_N,*
-V 11600,27400,CONT_DIF_N,*
-V 11600,25000,CONT_DIF_N,*
-V 12100,13600,CONT_VIA,*
-V 12800,13100,CONT_POLY,*
-V 13200,13600,CONT_BODY_N,*
-V 11800,13600,CONT_BODY_N,*
-V 12400,13600,CONT_BODY_N,*
-V 11300,13600,CONT_BODY_N,*
-V 12200,28700,CONT_BODY_P,*
-V 13400,28700,CONT_BODY_P,*
-V 12200,26100,CONT_VIA,*
-V 12200,27700,CONT_VIA,*
-V 12200,25700,CONT_DIF_N,*
-V 12200,28100,CONT_DIF_N,*
-V 12200,26500,CONT_DIF_N,*
-V 12200,27300,CONT_DIF_N,*
-V 12200,26900,CONT_DIF_N,*
-V 12200,25300,CONT_DIF_N,*
-V 12200,24900,CONT_VIA,*
-V 13400,28100,CONT_VIA,*
-V 13400,24900,CONT_VIA,*
-V 13400,26500,CONT_VIA,*
-V 13400,25300,CONT_DIF_N,*
-V 13400,26900,CONT_DIF_N,*
-V 13400,27300,CONT_DIF_N,*
-V 13400,25700,CONT_DIF_N,*
-V 13400,26100,CONT_DIF_N,*
-V 13400,27700,CONT_DIF_N,*
-V 14000,21900,CONT_DIF_P,*
-V 14600,21900,CONT_DIF_P,*
-V 15200,21900,CONT_DIF_P,*
-V 15800,21900,CONT_DIF_P,*
-V 14600,22500,CONT_BODY_N,*
-V 15800,22500,CONT_BODY_N,*
-V 15700,23200,CONT_VIA,*
-V 14600,23800,CONT_VIA,*
-V 15700,23800,CONT_POLY,*
-V 15800,24300,CONT_BODY_P,*
-V 14600,24300,CONT_BODY_P,*
-V 15800,21500,CONT_DIF_P,*
-V 15200,21500,CONT_DIF_P,*
-V 14600,21500,CONT_DIF_P,*
-V 14000,21500,CONT_DIF_P,*
-V 14600,21100,CONT_VIA,*
-V 15200,21100,CONT_DIF_P,*
-V 14000,21100,CONT_DIF_P,*
-V 14000,20700,CONT_DIF_P,*
-V 15200,20700,CONT_DIF_P,*
-V 15800,20700,CONT_DIF_P,*
-V 14600,20700,CONT_DIF_P,*
-V 15800,20300,CONT_DIF_P,*
-V 14600,20300,CONT_DIF_P,*
-V 15200,20300,CONT_DIF_P,*
-V 14000,20300,CONT_DIF_P,*
-V 14600,19900,CONT_VIA,*
-V 15200,19900,CONT_DIF_P,*
-V 14000,19900,CONT_DIF_P,*
-V 14600,16300,CONT_VIA,*
-V 14600,18700,CONT_VIA,*
-V 14600,17500,CONT_VIA,*
-V 14600,15100,CONT_VIA,*
-V 15200,16700,CONT_DIF_P,*
-V 15800,16700,CONT_DIF_P,*
-V 15800,17100,CONT_DIF_P,*
-V 15800,15900,CONT_DIF_P,*
-V 15200,15900,CONT_DIF_P,*
-V 15200,16300,CONT_DIF_P,*
-V 15800,18300,CONT_DIF_P,*
-V 15800,17900,CONT_DIF_P,*
-V 15200,17900,CONT_DIF_P,*
-V 15200,17100,CONT_DIF_P,*
-V 15200,17500,CONT_DIF_P,*
-V 15200,19500,CONT_DIF_P,*
-V 15800,19100,CONT_DIF_P,*
-V 15200,19100,CONT_DIF_P,*
-V 15200,18700,CONT_DIF_P,*
-V 15200,18300,CONT_DIF_P,*
-V 15800,19500,CONT_DIF_P,*
-V 15800,15500,CONT_DIF_P,*
-V 15200,15500,CONT_DIF_P,*
-V 14600,17100,CONT_DIF_P,*
-V 14600,16700,CONT_DIF_P,*
-V 14000,16700,CONT_DIF_P,*
-V 14000,17100,CONT_DIF_P,*
-V 14000,17500,CONT_DIF_P,*
-V 14600,15900,CONT_DIF_P,*
-V 14000,15900,CONT_DIF_P,*
-V 14000,16300,CONT_DIF_P,*
-V 14600,19500,CONT_DIF_P,*
-V 14600,19100,CONT_DIF_P,*
-V 14000,19100,CONT_DIF_P,*
-V 14000,18700,CONT_DIF_P,*
-V 14600,18300,CONT_DIF_P,*
-V 14000,18300,CONT_DIF_P,*
-V 14600,17900,CONT_DIF_P,*
-V 14000,17900,CONT_DIF_P,*
-V 14000,19500,CONT_DIF_P,*
-V 14000,15500,CONT_DIF_P,*
-V 14600,15500,CONT_DIF_P,*
-V 15200,15100,CONT_DIF_P,*
-V 15800,14700,CONT_DIF_P,*
-V 15200,14700,CONT_DIF_P,*
-V 15800,14300,CONT_DIF_P,*
-V 15200,14300,CONT_DIF_P,*
-V 14000,14300,CONT_DIF_P,*
-V 14000,15100,CONT_DIF_P,*
-V 14600,14700,CONT_DIF_P,*
-V 14000,14700,CONT_DIF_P,*
-V 14600,14300,CONT_DIF_P,*
-V 15200,27400,CONT_DIF_N,*
-V 15200,27000,CONT_DIF_N,*
-V 15200,26600,CONT_DIF_N,*
-V 15200,27800,CONT_DIF_N,*
-V 15200,25000,CONT_DIF_N,*
-V 15200,25400,CONT_DIF_N,*
-V 15200,26200,CONT_DIF_N,*
-V 15200,25800,CONT_DIF_N,*
-V 14000,27000,CONT_DIF_N,*
-V 14000,26600,CONT_DIF_N,*
-V 14000,26200,CONT_DIF_N,*
-V 14000,25800,CONT_DIF_N,*
-V 14000,25400,CONT_DIF_N,*
-V 14000,27800,CONT_DIF_N,*
-V 14000,27400,CONT_DIF_N,*
-V 14000,25000,CONT_DIF_N,*
-V 14500,13600,CONT_VIA,*
-V 15200,13100,CONT_POLY,*
-V 15600,13600,CONT_BODY_N,*
-V 14200,13600,CONT_BODY_N,*
-V 14800,13600,CONT_BODY_N,*
-V 13700,13600,CONT_BODY_N,*
-V 14600,28700,CONT_BODY_P,*
-V 15800,28700,CONT_BODY_P,*
-V 14600,26100,CONT_VIA,*
-V 14600,27700,CONT_VIA,*
-V 14600,25700,CONT_DIF_N,*
-V 14600,28100,CONT_DIF_N,*
-V 14600,26500,CONT_DIF_N,*
-V 14600,27300,CONT_DIF_N,*
-V 14600,26900,CONT_DIF_N,*
-V 14600,25300,CONT_DIF_N,*
-V 14600,24900,CONT_VIA,*
-V 15800,28100,CONT_VIA,*
-V 15800,24900,CONT_VIA,*
-V 15800,26500,CONT_VIA,*
-V 15800,25300,CONT_DIF_N,*
-V 15800,26900,CONT_DIF_N,*
-V 15800,27300,CONT_DIF_N,*
-V 15800,25700,CONT_DIF_N,*
-V 15800,26100,CONT_DIF_N,*
-V 15800,27700,CONT_DIF_N,*
-V 15500,7000,CONT_DIF_P,*
-V 14900,6200,CONT_DIF_P,*
-V 14900,5800,CONT_DIF_P,*
-V 14900,6600,CONT_DIF_P,*
-V 14900,7000,CONT_DIF_P,*
-V 14300,7000,CONT_DIF_P,*
-V 14300,6600,CONT_DIF_P,*
-V 14300,6200,CONT_DIF_P,*
-V 14300,5800,CONT_DIF_P,*
-V 15500,6600,CONT_DIF_P,*
-V 15500,5800,CONT_DIF_P,*
-V 15500,6200,CONT_DIF_P,*
-V 14500,12000,CONT_BODY_N,*
-V 14500,11200,CONT_BODY_N,*
-V 14500,10800,CONT_BODY_N,*
-V 14500,8300,CONT_BODY_N,*
-V 14500,10400,CONT_BODY_N,*
-V 14500,11600,CONT_BODY_N,*
-V 14500,9100,CONT_BODY_N,*
-V 14500,9500,CONT_BODY_N,*
-V 14900,9100,CONT_BODY_N,*
-V 14900,11600,CONT_BODY_N,*
-V 14900,10400,CONT_BODY_N,*
-V 14900,8300,CONT_BODY_N,*
-V 14900,10800,CONT_BODY_N,*
-V 14900,11200,CONT_BODY_N,*
-V 14900,12000,CONT_BODY_N,*
-V 14900,9500,CONT_BODY_N,*
-V 15300,11200,CONT_BODY_N,*
-V 15300,10800,CONT_BODY_N,*
-V 15300,8300,CONT_BODY_N,*
-V 15300,10400,CONT_BODY_N,*
-V 15300,11600,CONT_BODY_N,*
-V 15300,9100,CONT_BODY_N,*
-V 15300,9500,CONT_BODY_N,*
-V 15300,12000,CONT_BODY_N,*
-V 15700,11600,CONT_BODY_N,*
-V 15700,10400,CONT_BODY_N,*
-V 15700,8300,CONT_BODY_N,*
-V 15700,10800,CONT_BODY_N,*
-V 15700,11200,CONT_BODY_N,*
-V 15700,12000,CONT_BODY_N,*
-V 15700,9500,CONT_BODY_N,*
-V 15700,9100,CONT_BODY_N,*
-V 14900,200,CONT_BODY_P,*
-V 14400,200,CONT_BODY_P,*
-V 14900,600,CONT_BODY_P,*
-V 14400,600,CONT_BODY_P,*
-V 14900,1000,CONT_BODY_P,*
-V 14400,1000,CONT_BODY_P,*
-V 14900,1400,CONT_BODY_P,*
-V 14400,1400,CONT_BODY_P,*
-V 14400,1800,CONT_BODY_P,*
-V 14900,1800,CONT_BODY_P,*
-V 14300,2700,CONT_DIF_N,*
-V 15500,2800,CONT_DIF_N,*
-V 15500,3400,CONT_DIF_N,*
-V 15400,2300,CONT_POLY,*
-V 12500,6600,CONT_DIF_P,*
-V 12500,7000,CONT_DIF_P,*
-V 12500,6200,CONT_DIF_P,*
-V 12500,7400,CONT_DIF_P,*
-V 12500,5800,CONT_DIF_P,*
-V 11400,5100,CONT_BODY_N,*
-V 14200,3800,CONT_POLY,*
-V 9100,4000,CONT_BODY_P,*
-V 9600,4000,CONT_BODY_P,*
-V 10000,4000,CONT_BODY_P,*
-V 7100,10200,CONT_VIA,*
-V 7100,9000,CONT_VIA,*
-V 8900,1600,CONT_VIA,*
-V 10100,1600,CONT_VIA,*
-V 8300,3500,CONT_VIA,*
-V 5900,7400,CONT_VIA,*
-V 5900,6600,CONT_VIA,*
-V 8300,7400,CONT_VIA,*
-V 8300,9000,CONT_VIA,*
-V 8300,10200,CONT_VIA,*
-V 8300,6600,CONT_VIA,*
-V 8300,2300,CONT_VIA,*
-V 7100,6600,CONT_VIA,*
-V 10700,6600,CONT_VIA,*
-V 10700,2300,CONT_VIA,*
-V 7100,7400,CONT_VIA,*
-V 7100,2300,CONT_VIA,*
-V 5900,2300,CONT_VIA,*
-V 5900,3500,CONT_VIA,*
-V 5900,10200,CONT_VIA,*
-V 5900,9000,CONT_VIA,*
-V 7700,1600,CONT_VIA,*
-V 9500,9000,CONT_VIA,*
-V 9500,7400,CONT_VIA,*
-V 9500,2300,CONT_VIA,*
-V 10700,7400,CONT_VIA,*
-V 10700,9000,CONT_VIA,*
-V 10700,10200,CONT_VIA,*
-V 4100,2300,CONT_VIA,*
-V 4100,6600,CONT_VIA,*
-V 4100,7400,CONT_VIA,*
-V 4100,9000,CONT_VIA,*
-V 4100,10200,CONT_VIA,*
-V 4100,3500,CONT_VIA,*
-V 9500,6600,CONT_VIA,*
-V 9500,10200,CONT_VIA,*
-V 6500,1600,CONT_VIA,*
-V 4600,-700,CONT_VIA,*
-V 4800,5300,CONT_POLY,*
-V 4600,300,CONT_POLY,*
-V 7100,4600,CONT_POLY,*
-V 5900,4000,CONT_BODY_P,*
-V 8300,4000,CONT_BODY_P,*
-V 4100,4000,CONT_BODY_P,*
-V 7500,4000,CONT_BODY_P,*
-V 8700,4000,CONT_BODY_P,*
-V 7900,4000,CONT_BODY_P,*
-V 6700,4000,CONT_BODY_P,*
-V 6300,4000,CONT_BODY_P,*
-V 5900,-200,CONT_BODY_P,*
-V 7100,-200,CONT_BODY_P,*
-V 12100,-200,CONT_BODY_P,*
-V 11700,-200,CONT_BODY_P,*
-V 8300,-200,CONT_BODY_P,*
-V 10700,-200,CONT_BODY_P,*
-V 9500,-200,CONT_BODY_P,*
-V 4100,-200,CONT_BODY_P,*
-V 9900,-200,CONT_BODY_P,*
-V 10300,-200,CONT_BODY_P,*
-V 13700,-200,CONT_BODY_P,*
-V 13300,-200,CONT_BODY_P,*
-V 14100,-200,CONT_BODY_P,*
-V 14500,-200,CONT_BODY_P,*
-V 12500,-200,CONT_BODY_P,*
-V 12900,-200,CONT_BODY_P,*
-V 5100,-200,CONT_BODY_P,*
-V 5500,-200,CONT_BODY_P,*
-V 6300,-200,CONT_BODY_P,*
-V 6700,-200,CONT_BODY_P,*
-V 7500,-200,CONT_BODY_P,*
-V 7900,-200,CONT_BODY_P,*
-V 9100,-200,CONT_BODY_P,*
-V 8700,-200,CONT_BODY_P,*
-V 6000,12000,CONT_BODY_N,*
-V 5900,5100,CONT_BODY_N,*
-V 8300,5100,CONT_BODY_N,*
-V 6700,5100,CONT_BODY_N,*
-V 6300,5100,CONT_BODY_N,*
-V 7100,12000,CONT_BODY_N,*
-V 10700,5100,CONT_BODY_N,*
-V 9100,5100,CONT_BODY_N,*
-V 8700,5100,CONT_BODY_N,*
-V 4100,5100,CONT_BODY_N,*
-V 4500,12000,CONT_BODY_N,*
-V 3700,12000,CONT_BODY_N,*
-V 8300,12000,CONT_BODY_N,*
-V 9500,12000,CONT_BODY_N,*
-V 5500,12000,CONT_BODY_N,*
-V 5000,12000,CONT_BODY_N,*
-V 4100,12000,CONT_BODY_N,*
-V 7900,5100,CONT_BODY_N,*
-V 7500,5100,CONT_BODY_N,*
-V 9900,5100,CONT_BODY_N,*
-V 10300,5100,CONT_BODY_N,*
-V 7700,11400,CONT_DIF_P,*
-V 7700,8600,CONT_DIF_P,*
-V 7700,8200,CONT_DIF_P,*
-V 7700,5800,CONT_DIF_P,*
-V 7700,11000,CONT_DIF_P,*
-V 7700,10600,CONT_DIF_P,*
-V 7700,9000,CONT_DIF_P,*
-V 7700,10200,CONT_DIF_P,*
-V 7700,7000,CONT_DIF_P,*
-V 7700,6600,CONT_DIF_P,*
-V 7700,9800,CONT_DIF_P,*
-V 7700,9400,CONT_DIF_P,*
-V 7700,6200,CONT_DIF_P,*
-V 6500,6200,CONT_DIF_P,*
-V 7700,7400,CONT_DIF_P,*
-V 6500,11400,CONT_DIF_P,*
-V 6500,8600,CONT_DIF_P,*
-V 6500,8200,CONT_DIF_P,*
-V 6500,5800,CONT_DIF_P,*
-V 6500,11000,CONT_DIF_P,*
-V 6500,10600,CONT_DIF_P,*
-V 8300,7800,CONT_DIF_P,*
-V 7700,7800,CONT_DIF_P,*
-V 6500,7800,CONT_DIF_P,*
-V 6500,10200,CONT_DIF_P,*
-V 6500,7000,CONT_DIF_P,*
-V 6500,6600,CONT_DIF_P,*
-V 6500,9800,CONT_DIF_P,*
-V 6500,9400,CONT_DIF_P,*
-V 8300,11400,CONT_DIF_P,*
-V 6500,7400,CONT_DIF_P,*
-V 8300,6200,CONT_DIF_P,*
-V 8300,5800,CONT_DIF_P,*
-V 8300,7000,CONT_DIF_P,*
-V 8300,9800,CONT_DIF_P,*
-V 8300,10600,CONT_DIF_P,*
-V 8300,11000,CONT_DIF_P,*
-V 7100,8600,CONT_DIF_P,*
-V 6500,9000,CONT_DIF_P,*
-V 7100,8200,CONT_DIF_P,*
-V 7100,7800,CONT_DIF_P,*
-V 7100,11000,CONT_DIF_P,*
-V 7100,10600,CONT_DIF_P,*
-V 8300,9400,CONT_DIF_P,*
-V 8300,8200,CONT_DIF_P,*
-V 5900,5800,CONT_DIF_P,*
-V 8300,8600,CONT_DIF_P,*
-V 5900,6200,CONT_DIF_P,*
-V 7100,9400,CONT_DIF_P,*
-V 7100,9800,CONT_DIF_P,*
-V 7100,7000,CONT_DIF_P,*
-V 7100,5800,CONT_DIF_P,*
-V 7100,6200,CONT_DIF_P,*
-V 5900,10600,CONT_DIF_P,*
-V 7100,11400,CONT_DIF_P,*
-V 5900,11400,CONT_DIF_P,*
-V 5900,8200,CONT_DIF_P,*
-V 5900,7800,CONT_DIF_P,*
-V 5900,11000,CONT_DIF_P,*
-V 5900,9800,CONT_DIF_P,*
-V 5900,9400,CONT_DIF_P,*
-V 5300,11000,CONT_DIF_P,*
-V 5900,7000,CONT_DIF_P,*
-V 5300,10200,CONT_DIF_P,*
-V 5300,7800,CONT_DIF_P,*
-V 5300,7000,CONT_DIF_P,*
-V 5300,6600,CONT_DIF_P,*
-V 5300,9800,CONT_DIF_P,*
-V 5300,9400,CONT_DIF_P,*
-V 5300,10600,CONT_DIF_P,*
-V 5900,8600,CONT_DIF_P,*
-V 5300,7400,CONT_DIF_P,*
-V 5300,11400,CONT_DIF_P,*
-V 5300,8600,CONT_DIF_P,*
-V 5300,8200,CONT_DIF_P,*
-V 5300,5800,CONT_DIF_P,*
-V 9500,11000,CONT_DIF_P,*
-V 9500,9400,CONT_DIF_P,*
-V 5300,9000,CONT_DIF_P,*
-V 10700,7000,CONT_DIF_P,*
-V 9500,7000,CONT_DIF_P,*
-V 9500,5800,CONT_DIF_P,*
-V 9500,6200,CONT_DIF_P,*
-V 9500,8600,CONT_DIF_P,*
-V 9500,11400,CONT_DIF_P,*
-V 9500,8200,CONT_DIF_P,*
-V 5300,6200,CONT_DIF_P,*
-V 8900,7000,CONT_DIF_P,*
-V 9500,10600,CONT_DIF_P,*
-V 10700,9400,CONT_DIF_P,*
-V 10700,8200,CONT_DIF_P,*
-V 10700,11400,CONT_DIF_P,*
-V 10700,8600,CONT_DIF_P,*
-V 10700,6200,CONT_DIF_P,*
-V 9500,9800,CONT_DIF_P,*
-V 8900,8200,CONT_DIF_P,*
-V 10700,9800,CONT_DIF_P,*
-V 10700,10600,CONT_DIF_P,*
-V 10700,11000,CONT_DIF_P,*
-V 10700,7800,CONT_DIF_P,*
-V 8900,9000,CONT_DIF_P,*
-V 8900,7800,CONT_DIF_P,*
-V 9500,7800,CONT_DIF_P,*
-V 10100,6600,CONT_DIF_P,*
-V 8900,6600,CONT_DIF_P,*
-V 8900,9800,CONT_DIF_P,*
-V 8900,9400,CONT_DIF_P,*
-V 8900,6200,CONT_DIF_P,*
-V 8900,7400,CONT_DIF_P,*
-V 8900,11400,CONT_DIF_P,*
-V 10700,5800,CONT_DIF_P,*
-V 10100,5800,CONT_DIF_P,*
-V 8900,5800,CONT_DIF_P,*
-V 8900,11000,CONT_DIF_P,*
-V 8900,10600,CONT_DIF_P,*
-V 10100,9000,CONT_DIF_P,*
-V 10100,7800,CONT_DIF_P,*
-V 10100,10200,CONT_DIF_P,*
-V 8900,10200,CONT_DIF_P,*
-V 10100,10600,CONT_DIF_P,*
-V 10100,9800,CONT_DIF_P,*
-V 10100,9400,CONT_DIF_P,*
-V 10100,6200,CONT_DIF_P,*
-V 10100,7400,CONT_DIF_P,*
-V 10100,11400,CONT_DIF_P,*
-V 10100,8600,CONT_DIF_P,*
-V 8900,8600,CONT_DIF_P,*
-V 10100,7000,CONT_DIF_P,*
-V 10100,8200,CONT_DIF_P,*
-V 4700,6200,CONT_DIF_P,*
-V 4700,7400,CONT_DIF_P,*
-V 4700,11400,CONT_DIF_P,*
-V 4700,8600,CONT_DIF_P,*
-V 4700,9000,CONT_DIF_P,*
-V 4700,7800,CONT_DIF_P,*
-V 4700,7000,CONT_DIF_P,*
-V 10100,11000,CONT_DIF_P,*
-V 4700,5800,CONT_DIF_P,*
-V 4700,8200,CONT_DIF_P,*
-V 4700,11000,CONT_DIF_P,*
-V 4700,6600,CONT_DIF_P,*
-V 4700,10600,CONT_DIF_P,*
-V 4700,9800,CONT_DIF_P,*
-V 4700,10200,CONT_DIF_P,*
-V 4700,9400,CONT_DIF_P,*
-V 4100,6200,CONT_DIF_P,*
-V 4100,7000,CONT_DIF_P,*
-V 4100,5800,CONT_DIF_P,*
-V 4100,9800,CONT_DIF_P,*
-V 4100,11000,CONT_DIF_P,*
-V 4100,8200,CONT_DIF_P,*
-V 4100,11400,CONT_DIF_P,*
-V 4100,8600,CONT_DIF_P,*
-V 4100,10600,CONT_DIF_P,*
-V 4100,9400,CONT_DIF_P,*
-V 4100,7800,CONT_DIF_P,*
-V 7700,2100,CONT_DIF_N,*
-V 7100,700,CONT_DIF_N,*
-V 7700,2500,CONT_DIF_N,*
-V 7100,3300,CONT_DIF_N,*
-V 7100,2800,CONT_DIF_N,*
-V 6500,2900,CONT_DIF_N,*
-V 8300,1100,CONT_DIF_N,*
-V 8300,1500,CONT_DIF_N,*
-V 5900,700,CONT_DIF_N,*
-V 6500,3300,CONT_DIF_N,*
-V 6500,2100,CONT_DIF_N,*
-V 6500,2500,CONT_DIF_N,*
-V 7700,2900,CONT_DIF_N,*
-V 7700,3300,CONT_DIF_N,*
-V 7100,1500,CONT_DIF_N,*
-V 7100,1100,CONT_DIF_N,*
-V 5300,2500,CONT_DIF_N,*
-V 7100,1900,CONT_DIF_N,*
-V 8300,1900,CONT_DIF_N,*
-V 8300,2700,CONT_DIF_N,*
-V 8300,3100,CONT_DIF_N,*
-V 8300,700,CONT_DIF_N,*
-V 5300,3300,CONT_DIF_N,*
-V 10700,1100,CONT_DIF_N,*
-V 9500,1500,CONT_DIF_N,*
-V 5900,1100,CONT_DIF_N,*
-V 5900,1500,CONT_DIF_N,*
-V 5900,1900,CONT_DIF_N,*
-V 5900,2700,CONT_DIF_N,*
-V 5900,3100,CONT_DIF_N,*
-V 10700,2700,CONT_DIF_N,*
-V 10700,3100,CONT_DIF_N,*
-V 10700,700,CONT_DIF_N,*
-V 5300,2100,CONT_DIF_N,*
-V 5300,1700,CONT_DIF_N,*
-V 5300,1300,CONT_DIF_N,*
-V 5300,900,CONT_DIF_N,*
-V 5300,2900,CONT_DIF_N,*
-V 8900,2500,CONT_DIF_N,*
-V 7700,700,CONT_DIF_N,*
-V 8900,1200,CONT_DIF_N,*
-V 10100,2900,CONT_DIF_N,*
-V 9500,1100,CONT_DIF_N,*
-V 9500,700,CONT_DIF_N,*
-V 9500,1900,CONT_DIF_N,*
-V 10700,1900,CONT_DIF_N,*
-V 10100,700,CONT_DIF_N,*
-V 8900,700,CONT_DIF_N,*
-V 9500,3300,CONT_DIF_N,*
-V 10700,1500,CONT_DIF_N,*
-V 8900,2900,CONT_DIF_N,*
-V 8900,3300,CONT_DIF_N,*
-V 8900,2100,CONT_DIF_N,*
-V 9500,2800,CONT_DIF_N,*
-V 10100,3300,CONT_DIF_N,*
-V 10100,2100,CONT_DIF_N,*
-V 10100,2500,CONT_DIF_N,*
-V 10100,1200,CONT_DIF_N,*
-V 4700,1300,CONT_DIF_N,*
-V 4700,900,CONT_DIF_N,*
-V 4700,2500,CONT_DIF_N,*
-V 4700,2100,CONT_DIF_N,*
-V 4700,2900,CONT_DIF_N,*
-V 4700,3300,CONT_DIF_N,*
-V 4700,1700,CONT_DIF_N,*
-V 4100,1500,CONT_DIF_N,*
-V 4100,1100,CONT_DIF_N,*
-V 7700,1200,CONT_DIF_N,*
-V 4100,700,CONT_DIF_N,*
-V 4100,3100,CONT_DIF_N,*
-V 4100,2700,CONT_DIF_N,*
-V 4100,1900,CONT_DIF_N,*
-V 6500,700,CONT_DIF_N,*
-V 6500,1200,CONT_DIF_N,*
-V 16100,7500,CONT_VIA,*
-V 16100,6700,CONT_VIA,*
-V 16100,5500,CONT_BODY_N,*
-V 16100,9100,CONT_BODY_N,*
-V 16100,8300,CONT_BODY_N,*
-V 16100,10800,CONT_BODY_N,*
-V 16100,7100,CONT_BODY_N,*
-V 16100,11200,CONT_BODY_N,*
-V 16100,6300,CONT_BODY_N,*
-V 16100,5900,CONT_BODY_N,*
-V 16100,12000,CONT_BODY_N,*
-V 16100,9500,CONT_BODY_N,*
-V 16100,11600,CONT_BODY_N,*
-V 16100,7900,CONT_BODY_N,*
-V 16100,10400,CONT_BODY_N,*
-V 16100,5100,CONT_BODY_N,*
-V 13700,1600,CONT_VIA,*
-V 12500,1600,CONT_VIA,*
-V 11300,1600,CONT_VIA,*
-V 11900,9400,CONT_DIF_P,*
-V 11900,7000,CONT_DIF_P,*
-V 11900,5800,CONT_DIF_P,*
-V 11900,6200,CONT_DIF_P,*
-V 11900,8600,CONT_DIF_P,*
-V 11900,11400,CONT_DIF_P,*
-V 11900,8200,CONT_DIF_P,*
-V 11900,7800,CONT_DIF_P,*
-V 11900,10600,CONT_DIF_P,*
-V 11300,9000,CONT_DIF_P,*
-V 11300,7800,CONT_DIF_P,*
-V 11300,10200,CONT_DIF_P,*
-V 11300,7000,CONT_DIF_P,*
-V 11300,6600,CONT_DIF_P,*
-V 11300,9800,CONT_DIF_P,*
-V 11900,9800,CONT_DIF_P,*
-V 11300,6200,CONT_DIF_P,*
-V 11300,7400,CONT_DIF_P,*
-V 11300,11400,CONT_DIF_P,*
-V 11300,8600,CONT_DIF_P,*
-V 11300,8200,CONT_DIF_P,*
-V 11300,5800,CONT_DIF_P,*
-V 11300,11000,CONT_DIF_P,*
-V 11900,11000,CONT_DIF_P,*
-V 13100,9800,CONT_DIF_P,*
-V 13100,9400,CONT_DIF_P,*
-V 13100,8600,CONT_DIF_P,*
-V 13100,6200,CONT_DIF_P,*
-V 13100,5800,CONT_DIF_P,*
-V 13100,7000,CONT_DIF_P,*
-V 12500,10200,CONT_DIF_P,*
-V 11300,9400,CONT_DIF_P,*
-V 12500,9000,CONT_DIF_P,*
-V 13100,10600,CONT_DIF_P,*
-V 13100,11000,CONT_DIF_P,*
-V 13100,7800,CONT_DIF_P,*
-V 13100,8200,CONT_DIF_P,*
-V 13100,11400,CONT_DIF_P,*
-V 12500,8600,CONT_DIF_P,*
-V 11300,10600,CONT_DIF_P,*
-V 12500,9400,CONT_DIF_P,*
-V 12500,9800,CONT_DIF_P,*
-V 12500,10600,CONT_DIF_P,*
-V 12500,7800,CONT_DIF_P,*
-V 12500,8200,CONT_DIF_P,*
-V 13700,10200,CONT_DIF_P,*
-V 13700,7800,CONT_DIF_P,*
-V 13700,9000,CONT_DIF_P,*
-V 13700,8600,CONT_DIF_P,*
-V 13700,11400,CONT_DIF_P,*
-V 12500,11400,CONT_DIF_P,*
-V 13700,6200,CONT_DIF_P,*
-V 13700,9400,CONT_DIF_P,*
-V 13700,9800,CONT_DIF_P,*
-V 13700,6600,CONT_DIF_P,*
-V 13700,7000,CONT_DIF_P,*
-V 13700,10600,CONT_DIF_P,*
-V 13700,11000,CONT_DIF_P,*
-V 12500,11000,CONT_DIF_P,*
-V 13700,8200,CONT_DIF_P,*
-V 13100,10200,CONT_DIF_P,*
-V 11900,10200,CONT_DIF_P,*
-V 11900,9000,CONT_DIF_P,*
-V 13100,9000,CONT_DIF_P,*
-V 11900,7400,CONT_DIF_P,*
-V 13100,7400,CONT_DIF_P,*
-V 13700,7400,CONT_DIF_P,*
-V 11900,6600,CONT_DIF_P,*
-V 13100,6600,CONT_DIF_P,*
-V 13700,5800,CONT_DIF_P,*
-V 13700,700,CONT_DIF_N,*
-V 13700,1200,CONT_DIF_N,*
-V 12500,1200,CONT_DIF_N,*
-V 11300,700,CONT_DIF_N,*
-V 13700,2100,CONT_DIF_N,*
-V 11900,1500,CONT_DIF_N,*
-V 13700,3300,CONT_DIF_N,*
-V 11900,1100,CONT_DIF_N,*
-V 11900,700,CONT_DIF_N,*
-V 11900,1900,CONT_DIF_N,*
-V 11900,3300,CONT_DIF_N,*
-V 11300,2900,CONT_DIF_N,*
-V 11300,3300,CONT_DIF_N,*
-V 11300,2100,CONT_DIF_N,*
-V 11300,2500,CONT_DIF_N,*
-V 11300,1200,CONT_DIF_N,*
-V 11900,2800,CONT_DIF_N,*
-V 13100,1500,CONT_DIF_N,*
-V 13700,2900,CONT_DIF_N,*
-V 12500,3300,CONT_DIF_N,*
-V 12500,2900,CONT_DIF_N,*
-V 13100,3300,CONT_DIF_N,*
-V 13100,1900,CONT_DIF_N,*
-V 13100,700,CONT_DIF_N,*
-V 13100,1100,CONT_DIF_N,*
-V 13700,2500,CONT_DIF_N,*
-V 13100,2800,CONT_DIF_N,*
-V 12500,700,CONT_DIF_N,*
-V 12500,2500,CONT_DIF_N,*
-V 12500,2100,CONT_DIF_N,*
-V 13100,2300,CONT_DIF_N,*
-V 11900,2300,CONT_DIF_N,*
-V 9500,4600,CONT_POLY,*
-V 14900,3500,CONT_VIA,*
-V 14900,-200,CONT_BODY_P,*
-V 14900,5100,CONT_BODY_N,*
-V 14300,3300,CONT_DIF_N,*
-V 14900,2700,CONT_DIF_N,*
-V 14900,3100,CONT_DIF_N,*
-V 16100,4000,CONT_BODY_P,*
-V 16100,4000,CONT_BODY_P,*
-V 16100,2800,CONT_BODY_P,*
-V 16100,3200,CONT_BODY_P,*
-V 16100,3600,CONT_VIA,*
-V 16100,2400,CONT_VIA,*
-V 14800,4500,CONT_POLY,*
-V 10700,12000,CONT_BODY_N,*
-V 15400,-700,CONT_VIA,*
-V 11300,-200,CONT_BODY_P,*
-V 10800,4000,CONT_POLY,*
-V 14900,4000,CONT_BODY_P,*
-V 14900,7500,CONT_DIF_P,*
-V 15500,7500,CONT_DIF_P,*
-V 14300,7500,CONT_DIF_P,*
-V 3300,5800,CONT_VIA,*
-V 2100,9800,CONT_VIA,*
-V 2100,6600,CONT_VIA,*
-V 3300,9900,CONT_VIA,*
-V 3100,9400,CONT_POLY,*
-V 2100,5100,CONT_BODY_N,*
-V 2100,11600,CONT_BODY_N,*
-V 2100,11200,CONT_BODY_N,*
-V 2100,10800,CONT_BODY_N,*
-V 2100,10400,CONT_BODY_N,*
-V 2100,7000,CONT_BODY_N,*
-V 2100,7400,CONT_BODY_N,*
-V 2100,7800,CONT_BODY_N,*
-V 2100,8200,CONT_BODY_N,*
-V 2100,8600,CONT_BODY_N,*
-V 2100,9000,CONT_BODY_N,*
-V 2100,12000,CONT_BODY_N,*
-V 2100,9400,CONT_BODY_N,*
-V 2100,5500,CONT_BODY_N,*
-V 2100,5900,CONT_BODY_N,*
-V 2100,6300,CONT_BODY_N,*
-V 2700,5500,CONT_BODY_N,*
-V 2700,5900,CONT_BODY_N,*
-V 2700,6300,CONT_BODY_N,*
-V 3300,10300,CONT_BODY_N,*
-V 3300,10700,CONT_BODY_N,*
-V 3300,5100,CONT_BODY_N,*
-V 2700,5100,CONT_BODY_N,*
-V 2700,6900,CONT_DIF_P,*
-V 2700,11300,CONT_DIF_P,*
-V 3300,12000,CONT_BODY_N,*
-V 3300,11300,CONT_BODY_N,*
-V 3500,2300,CONT_VIA,*
-V 3500,3500,CONT_VIA,*
-V 3500,4000,CONT_BODY_P,*
-V 3500,300,CONT_BODY_P,*
-V 3500,700,CONT_BODY_P,*
-V 3500,1100,CONT_BODY_P,*
-V 3500,1500,CONT_BODY_P,*
-V 3500,1900,CONT_BODY_P,*
-V 3500,2700,CONT_BODY_P,*
-V 3500,3100,CONT_BODY_P,*
-V 3500,-200,CONT_BODY_P,*
-V 16400,29200,CONT_VIA,*
-V 15800,29200,CONT_VIA,*
-V 16400,25900,CONT_VIA,*
-V 16100,24300,CONT_VIA,*
-V 16400,27900,CONT_VIA,*
-V 3700,23200,CONT_VIA,*
-V 16400,28300,CONT_BODY_P,*
-V 16400,28700,CONT_BODY_P,*
-V 16400,24300,CONT_BODY_P,*
-V 16400,25500,CONT_BODY_P,*
-V 16400,25100,CONT_BODY_P,*
-V 16400,24700,CONT_BODY_P,*
-V 16400,26300,CONT_BODY_P,*
-V 16400,26700,CONT_BODY_P,*
-V 16400,27100,CONT_BODY_P,*
-V 16400,27500,CONT_BODY_P,*
-V 1200,28700,CONT_BODY_P,*
-V 1200,24300,CONT_BODY_P,*
-V 800,28300,CONT_BODY_P,*
-V 800,24300,CONT_BODY_P,*
-V 800,25500,CONT_BODY_P,*
-V 800,25100,CONT_BODY_P,*
-V 800,24700,CONT_BODY_P,*
-V 800,28700,CONT_BODY_P,*
-V 800,25900,CONT_BODY_P,*
-V 800,26300,CONT_BODY_P,*
-V 800,26700,CONT_BODY_P,*
-V 800,27100,CONT_BODY_P,*
-V 800,27500,CONT_BODY_P,*
-V 800,27900,CONT_BODY_P,*
-V 1400,22500,CONT_BODY_N,*
-V 16400,22000,CONT_BODY_N,*
-V 16400,22500,CONT_BODY_N,*
-V 16400,20400,CONT_BODY_N,*
-V 16400,20800,CONT_BODY_N,*
-V 16400,20000,CONT_BODY_N,*
-V 16400,21200,CONT_BODY_N,*
-V 16400,21600,CONT_BODY_N,*
-V 800,21200,CONT_BODY_N,*
-V 800,20800,CONT_BODY_N,*
-V 800,20400,CONT_BODY_N,*
-V 800,20000,CONT_BODY_N,*
-V 800,22500,CONT_BODY_N,*
-V 800,22000,CONT_BODY_N,*
-V 800,21600,CONT_BODY_N,*
-V 1300,13600,CONT_BODY_N,*
-V 16400,13600,CONT_BODY_N,*
-V 16400,15600,CONT_BODY_N,*
-V 16400,17200,CONT_BODY_N,*
-V 16400,16800,CONT_BODY_N,*
-V 16400,16000,CONT_BODY_N,*
-V 16000,13600,CONT_BODY_N,*
-V 16400,19600,CONT_BODY_N,*
-V 16400,17600,CONT_BODY_N,*
-V 16400,18000,CONT_BODY_N,*
-V 16400,16400,CONT_BODY_N,*
-V 16400,14000,CONT_BODY_N,*
-V 16400,14400,CONT_BODY_N,*
-V 16400,14800,CONT_BODY_N,*
-V 16400,15200,CONT_BODY_N,*
-V 16400,18400,CONT_BODY_N,*
-V 16400,18800,CONT_BODY_N,*
-V 16400,19200,CONT_BODY_N,*
-V 800,18000,CONT_BODY_N,*
-V 800,17600,CONT_BODY_N,*
-V 800,18400,CONT_BODY_N,*
-V 800,19600,CONT_BODY_N,*
-V 800,19200,CONT_BODY_N,*
-V 800,18800,CONT_BODY_N,*
-V 800,14800,CONT_BODY_N,*
-V 800,14400,CONT_BODY_N,*
-V 800,14000,CONT_BODY_N,*
-V 800,13600,CONT_BODY_N,*
-V 800,16800,CONT_BODY_N,*
-V 800,17200,CONT_BODY_N,*
-V 800,16400,CONT_BODY_N,*
-V 800,16000,CONT_BODY_N,*
-V 800,15600,CONT_BODY_N,*
-V 800,15200,CONT_BODY_N,*
-V 1400,20300,CONT_DIF_P,*
-V 1400,20700,CONT_DIF_P,*
-V 1400,21100,CONT_DIF_P,*
-V 1400,21500,CONT_DIF_P,*
-V 1400,21900,CONT_DIF_P,*
-V 1400,17500,CONT_DIF_P,*
-V 1400,17900,CONT_DIF_P,*
-V 1400,15100,CONT_DIF_P,*
-V 1400,14700,CONT_DIF_P,*
-V 1400,14300,CONT_DIF_P,*
-V 1400,19900,CONT_DIF_P,*
-V 1400,19500,CONT_DIF_P,*
-V 1400,19100,CONT_DIF_P,*
-V 1400,18700,CONT_DIF_P,*
-V 1400,18300,CONT_DIF_P,*
-V 1400,17100,CONT_DIF_P,*
-V 1400,16700,CONT_DIF_P,*
-V 1400,16300,CONT_DIF_P,*
-V 1400,15900,CONT_DIF_P,*
-V 1400,15500,CONT_DIF_P,*
-V 1400,27300,CONT_DIF_N,*
-V 1400,26100,CONT_DIF_N,*
-V 1400,24900,CONT_DIF_N,*
-V 1400,25300,CONT_DIF_N,*
-V 1400,25700,CONT_DIF_N,*
-V 1400,26500,CONT_DIF_N,*
-V 1400,26900,CONT_DIF_N,*
-V 1400,27700,CONT_DIF_N,*
-V 1400,28100,CONT_DIF_N,*
-V 16900,23200,CONT_VIA,*
-V 16300,23200,CONT_VIA,*
-V 16900,1600,CONT_VIA,*
-EOF
diff --git a/alliance/share/cells/padlib/palotw_sp.ap b/alliance/share/cells/padlib/palotw_sp.ap
deleted file mode 100644
index fa8d41c8..00000000
--- a/alliance/share/cells/padlib/palotw_sp.ap
+++ /dev/null
@@ -1,1502 +0,0 @@
-V ALLIANCE : 4
-H palotw_sp,P,26/ 0/100,100
-A 0,-700,17200,35600
-C 0,29600,12000,vsse,0,WEST,ALU2
-C 17200,29600,12000,vsse,1,EAST,ALU2
-C 17200,16800,12000,vdde,1,EAST,ALU2
-C 0,16800,12000,vdde,0,WEST,ALU2
-C 17200,8400,4000,vddi,1,EAST,ALU2
-C 17200,4000,4000,vssi,1,EAST,ALU2
-C 0,4000,4000,vssi,0,WEST,ALU2
-C 0,8400,4000,vddi,0,WEST,ALU2
-C 17200,600,1200,ck,1,EAST,ALU2
-C 0,600,1200,ck,0,WEST,ALU2
-C 4600,-700,200,i,1,SOUTH,ALU2
-C 4600,-700,200,i,0,SOUTH,ALU1
-C 15400,-700,200,b,1,SOUTH,ALU2
-C 15400,-700,200,b,0,SOUTH,ALU1
-S 2400,9100,3000,9100,3900,*,RIGHT,PTRANS
-S 0,29600,17200,29600,12000,vsse,RIGHT,ALU2
-S 1900,5100,16300,5100,400,*,RIGHT,NWELL
-S 1900,8600,16300,8600,7200,*,RIGHT,NWELL
-S 7700,30100,7700,35600,6200,*,UP,ALU1
-S 11000,5500,14600,5500,100,*,RIGHT,POLY
-S 15200,3700,15200,5500,100,*,UP,POLY
-S 14600,-100,14600,1900,800,*,DOWN,ALU1
-S 14300,0,14300,1900,300,*,DOWN,PTIE
-S 14600,0,14600,1900,300,*,DOWN,PTIE
-S 14900,-300,14900,1900,300,*,DOWN,PTIE
-S 14900,1800,16200,1800,300,*,LEFT,PTIE
-S 16100,1700,16100,4100,300,*,UP,PTIE
-S 14900,2600,14900,3500,300,*,DOWN,NDIF
-S 15400,-700,15400,2300,200,*,DOWN,ALU1
-S 14300,2600,14300,3500,300,*,UP,NDIF
-S 14600,2400,14600,3700,100,*,UP,NTRANS
-S 15200,2400,15200,3700,100,*,UP,NTRANS
-S 15500,2600,15500,3500,300,*,UP,NDIF
-S 15200,2200,15200,2400,100,*,DOWN,POLY
-S 12500,5800,12500,12900,200,*,UP,ALU1
-S 7400,5100,11500,5100,300,*,RIGHT,ALU1
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-S 13900,3700,13900,3900,100,*,DOWN,POLY
-S 14000,3700,14000,3900,100,*,DOWN,POLY
-S 13900,4700,13900,5300,100,*,DOWN,POLY
-S 14000,4700,14000,5300,100,*,DOWN,POLY
-S 13900,4500,14600,4500,300,*,RIGHT,POLY
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-S 11300,5100,13700,5100,300,*,RIGHT,NTIE
-S 7400,4000,10100,4000,300,*,RIGHT,PTIE
-S 5700,4000,10100,4000,300,*,RIGHT,ALU1
-S 10300,3800,10300,4500,100,*,DOWN,POLY
-S 10300,4600,10900,4600,100,*,LEFT,POLY
-S 11100,4500,11100,5300,100,*,DOWN,POLY
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-S 11100,3800,11100,4100,100,*,DOWN,POLY
-S 11100,3700,14000,3700,100,*,RIGHT,POLY
-S 11100,3600,14000,3600,100,*,RIGHT,POLY
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-S 11300,5700,11300,11500,300,*,UP,PDIF
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-S 4100,5000,4100,12100,200,*,UP,ALU1
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-S 8900,5800,8900,12900,200,*,UP,ALU1
-S 10100,5800,10100,12900,200,*,UP,ALU1
-S 8300,5000,8300,12000,200,*,UP,ALU1
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-S 5900,5100,6800,5100,300,*,RIGHT,ALU1
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-S 3400,-200,15000,-200,300,*,RIGHT,PTIE
-S 3400,4000,4200,4000,300,*,RIGHT,PTIE
-S 5900,13000,5900,14300,300,*,DOWN,ALU1
-S 6500,13500,6500,22600,300,*,UP,ALU1
-S 4200,13600,5400,13600,300,*,RIGHT,ALU1
-S 5900,13100,5900,13900,200,*,UP,POLY
-S 4200,22500,6600,22500,300,*,RIGHT,NTIE
-S 5900,23800,6400,23800,300,*,RIGHT,POLY
-S 5900,23800,5900,24600,200,*,UP,POLY
-S 4400,24600,6200,24600,100,*,RIGHT,POLY
-S 6200,24300,6600,24300,300,*,RIGHT,PTIE
-S 4200,24300,5600,24300,300,*,RIGHT,PTIE
-S 5900,23700,5900,23900,200,*,DOWN,POLY
-S 4400,13900,6200,13900,100,*,RIGHT,POLY
-S 6200,13600,6600,13600,300,*,RIGHT,NTIE
-S 4200,13600,5600,13600,300,*,RIGHT,NTIE
-S 5500,13400,5500,22700,2800,*,UP,NWELL
-S 6200,13900,6200,22200,100,*,UP,PTRANS
-S 5600,13900,5600,22200,100,*,UP,PTRANS
-S 5000,13900,5000,22200,100,*,UP,PTRANS
-S 5300,13800,5300,22600,300,*,UP,ALU1
-S 4400,13900,4400,22200,100,*,UP,PTRANS
-S 4700,14100,4700,22000,200,*,UP,PDIF
-S 5300,14100,5300,22000,200,*,UP,PDIF
-S 5900,14100,5900,22000,200,*,UP,PDIF
-S 6500,14100,6500,22000,300,*,UP,PDIF
-S 4200,28700,6600,28700,300,*,RIGHT,PTIE
-S 6200,24600,6200,28400,100,*,UP,NTRANS
-S 5600,24600,5600,28400,100,*,UP,NTRANS
-S 5000,24600,5000,28400,100,*,UP,NTRANS
-S 4400,24600,4400,28400,100,*,UP,NTRANS
-S 4700,24800,4700,28200,300,*,UP,NDIF
-S 5300,24800,5300,28200,300,*,UP,NDIF
-S 5900,24800,5900,28200,300,*,UP,NDIF
-S 6500,24800,6500,28200,300,*,UP,NDIF
-S 6500,24200,6500,28800,300,*,UP,ALU1
-S 5300,23700,5300,28800,300,*,UP,ALU1
-S 5900,14200,5900,29100,300,*,UP,ALU1
-S 4700,14200,4700,29100,300,*,UP,ALU1
-S 5900,13100,6500,13100,200,*,RIGHT,POLY
-S 6400,13500,6400,13700,200,*,DOWN,ALU1
-S 7100,14200,7100,29100,300,*,UP,ALU1
-S 8300,14200,8300,29100,300,*,UP,ALU1
-S 7700,23700,7700,28800,300,*,UP,ALU1
-S 8900,24200,8900,28800,300,*,UP,ALU1
-S 8900,24800,8900,28200,300,*,UP,NDIF
-S 8300,24800,8300,28200,300,*,UP,NDIF
-S 7700,24800,7700,28200,300,*,UP,NDIF
-S 7100,24800,7100,28200,300,*,UP,NDIF
-S 6800,24600,6800,28400,100,*,UP,NTRANS
-S 7400,24600,7400,28400,100,*,UP,NTRANS
-S 8000,24600,8000,28400,100,*,UP,NTRANS
-S 8600,24600,8600,28400,100,*,UP,NTRANS
-S 6600,28700,9000,28700,300,*,RIGHT,PTIE
-S 8900,14100,8900,22000,300,*,UP,PDIF
-S 8300,14100,8300,22000,200,*,UP,PDIF
-S 7700,14100,7700,22000,200,*,UP,PDIF
-S 7100,14100,7100,22000,200,*,UP,PDIF
-S 6800,13900,6800,22200,100,*,UP,PTRANS
-S 7700,13800,7700,22600,300,*,UP,ALU1
-S 7400,13900,7400,22200,100,*,UP,PTRANS
-S 8000,13900,8000,22200,100,*,UP,PTRANS
-S 8600,13900,8600,22200,100,*,UP,PTRANS
-S 7900,13400,7900,22700,2800,*,UP,NWELL
-S 8900,13800,8900,22600,300,*,UP,ALU1
-S 6600,13600,8000,13600,300,*,RIGHT,NTIE
-S 8600,13600,9000,13600,300,*,RIGHT,NTIE
-S 8300,13300,8300,13900,200,*,UP,POLY
-S 6800,13900,8600,13900,100,*,RIGHT,POLY
-S 6600,13600,8000,13600,300,*,RIGHT,ALU1
-S 8600,13600,9000,13600,300,*,RIGHT,ALU1
-S 8300,23700,8300,23900,200,*,DOWN,POLY
-S 6600,24300,8000,24300,300,*,RIGHT,PTIE
-S 8600,24300,9000,24300,300,*,RIGHT,PTIE
-S 6800,24600,8600,24600,100,*,RIGHT,POLY
-S 8300,23800,8300,24600,200,*,UP,POLY
-S 8300,23800,8800,23800,300,*,RIGHT,POLY
-S 8800,23200,8800,23800,200,*,UP,ALU1
-S 6600,22500,9000,22500,300,*,RIGHT,NTIE
-S 9500,14200,9500,29100,300,*,UP,ALU1
-S 10700,14200,10700,29100,300,*,UP,ALU1
-S 10100,23700,10100,28800,300,*,UP,ALU1
-S 11300,24200,11300,28800,300,*,UP,ALU1
-S 11300,24800,11300,28200,300,*,UP,NDIF
-S 10700,24800,10700,28200,300,*,UP,NDIF
-S 10100,24800,10100,28200,300,*,UP,NDIF
-S 9500,24800,9500,28200,300,*,UP,NDIF
-S 9200,24600,9200,28400,100,*,UP,NTRANS
-S 9800,24600,9800,28400,100,*,UP,NTRANS
-S 10400,24600,10400,28400,100,*,UP,NTRANS
-S 11000,24600,11000,28400,100,*,UP,NTRANS
-S 9000,28700,11400,28700,300,*,RIGHT,PTIE
-S 11300,14100,11300,22000,300,*,UP,PDIF
-S 10700,14100,10700,22000,200,*,UP,PDIF
-S 10100,14100,10100,22000,200,*,UP,PDIF
-S 9500,14100,9500,22000,200,*,UP,PDIF
-S 9200,13900,9200,22200,100,*,UP,PTRANS
-S 10100,13800,10100,22600,300,*,UP,ALU1
-S 9800,13900,9800,22200,100,*,UP,PTRANS
-S 10400,13900,10400,22200,100,*,UP,PTRANS
-S 11000,13900,11000,22200,100,*,UP,PTRANS
-S 10300,13400,10300,22700,2800,*,UP,NWELL
-S 11300,13800,11300,22600,300,*,UP,ALU1
-S 9000,13600,10400,13600,300,*,RIGHT,NTIE
-S 11000,13600,11400,13600,300,*,RIGHT,NTIE
-S 10700,13300,10700,13900,200,*,UP,POLY
-S 9200,13900,11000,13900,100,*,RIGHT,POLY
-S 9000,13600,10400,13600,300,*,RIGHT,ALU1
-S 11000,13600,11400,13600,300,*,RIGHT,ALU1
-S 10700,23700,10700,23900,200,*,DOWN,POLY
-S 9000,24300,10400,24300,300,*,RIGHT,PTIE
-S 11000,24300,11400,24300,300,*,RIGHT,PTIE
-S 9200,24600,11000,24600,100,*,RIGHT,POLY
-S 10700,23800,10700,24600,200,*,UP,POLY
-S 10700,23800,11200,23800,300,*,RIGHT,POLY
-S 11200,23200,11200,23800,200,*,UP,ALU1
-S 9000,22500,11400,22500,300,*,RIGHT,NTIE
-S 0,4000,17200,4000,4000,vssi,RIGHT,ALU2
-S 0,8400,17200,8400,4000,vddi,RIGHT,ALU2
-S 0,16800,17200,16800,12000,vdde,RIGHT,ALU2
-V 15500,7000,CONT_DIF_P
-V 14900,6200,CONT_DIF_P
-V 14900,5800,CONT_DIF_P
-V 14900,6600,CONT_DIF_P
-V 14900,7000,CONT_DIF_P
-V 14300,7000,CONT_DIF_P
-V 14300,6600,CONT_DIF_P
-V 14300,6200,CONT_DIF_P
-V 14300,5800,CONT_DIF_P
-V 15500,6600,CONT_DIF_P
-V 15500,5800,CONT_DIF_P
-V 15500,6200,CONT_DIF_P
-V 14500,12000,CONT_BODY_N
-V 14500,11200,CONT_BODY_N
-V 14500,10800,CONT_BODY_N
-V 14500,8300,CONT_BODY_N
-V 14500,10400,CONT_BODY_N
-V 14500,11600,CONT_BODY_N
-V 14500,9100,CONT_BODY_N
-V 14500,9500,CONT_BODY_N
-V 14500,10000,CONT_VIA
-V 14500,8700,CONT_VIA
-V 14900,9100,CONT_BODY_N
-V 14900,11600,CONT_BODY_N
-V 14900,10400,CONT_BODY_N
-V 14900,8300,CONT_BODY_N
-V 14900,10800,CONT_BODY_N
-V 14900,11200,CONT_BODY_N
-V 14900,12000,CONT_BODY_N
-V 14900,9500,CONT_BODY_N
-V 14900,8700,CONT_VIA
-V 14900,10000,CONT_VIA
-V 15300,11200,CONT_BODY_N
-V 15300,10800,CONT_BODY_N
-V 15300,8300,CONT_BODY_N
-V 15300,10400,CONT_BODY_N
-V 15300,11600,CONT_BODY_N
-V 15300,9100,CONT_BODY_N
-V 15300,9500,CONT_BODY_N
-V 15300,12000,CONT_BODY_N
-V 15300,10000,CONT_VIA
-V 15300,8700,CONT_VIA
-V 15700,11600,CONT_BODY_N
-V 15700,10400,CONT_BODY_N
-V 15700,8300,CONT_BODY_N
-V 15700,10800,CONT_BODY_N
-V 15700,11200,CONT_BODY_N
-V 15700,12000,CONT_BODY_N
-V 15700,9500,CONT_BODY_N
-V 15700,9100,CONT_BODY_N
-V 15700,8700,CONT_VIA
-V 15700,10000,CONT_VIA
-V 14900,200,CONT_BODY_P
-V 14400,200,CONT_BODY_P
-V 14900,600,CONT_BODY_P
-V 14400,600,CONT_BODY_P
-V 14900,1000,CONT_BODY_P
-V 14400,1000,CONT_BODY_P
-V 14900,1400,CONT_BODY_P
-V 14400,1400,CONT_BODY_P
-V 14400,1800,CONT_BODY_P
-V 14900,1800,CONT_BODY_P
-V 14300,2700,CONT_DIF_N
-V 15500,2800,CONT_DIF_N
-V 15500,3400,CONT_DIF_N
-V 15400,2300,CONT_POLY
-V 12500,6600,CONT_DIF_P
-V 12500,7000,CONT_DIF_P
-V 12500,6200,CONT_DIF_P
-V 12500,7400,CONT_DIF_P
-V 12500,5800,CONT_DIF_P
-V 11400,5100,CONT_BODY_N
-V 14200,3800,CONT_POLY
-V 9100,4000,CONT_BODY_P
-V 9600,4000,CONT_BODY_P
-V 10000,4000,CONT_BODY_P
-V 16300,1600,CONT_VIA
-V 16100,23200,CONT_VIA
-V 16700,23200,CONT_VIA
-V 7100,10200,CONT_VIA
-V 7100,9000,CONT_VIA
-V 8900,1600,CONT_VIA
-V 10100,1600,CONT_VIA
-V 8300,3500,CONT_VIA
-V 5900,7400,CONT_VIA
-V 5900,6600,CONT_VIA
-V 8300,7400,CONT_VIA
-V 8300,9000,CONT_VIA
-V 8300,10200,CONT_VIA
-V 8300,6600,CONT_VIA
-V 8300,2300,CONT_VIA
-V 7100,6600,CONT_VIA
-V 10700,6600,CONT_VIA
-V 10700,2300,CONT_VIA
-V 7100,7400,CONT_VIA
-V 7100,2300,CONT_VIA
-V 5900,2300,CONT_VIA
-V 5900,3500,CONT_VIA
-V 5900,10200,CONT_VIA
-V 5900,9000,CONT_VIA
-V 7700,1600,CONT_VIA
-V 9500,9000,CONT_VIA
-V 9500,7400,CONT_VIA
-V 9500,2300,CONT_VIA
-V 10700,7400,CONT_VIA
-V 10700,9000,CONT_VIA
-V 10700,10200,CONT_VIA
-V 4100,2300,CONT_VIA
-V 4100,6600,CONT_VIA
-V 4100,7400,CONT_VIA
-V 4100,9000,CONT_VIA
-V 4100,10200,CONT_VIA
-V 4100,3500,CONT_VIA
-V 9500,6600,CONT_VIA
-V 9500,10200,CONT_VIA
-V 6500,1600,CONT_VIA
-V 4600,-700,CONT_VIA
-V 4800,5300,CONT_POLY
-V 4600,300,CONT_POLY
-V 7100,4600,CONT_POLY
-V 5900,4000,CONT_BODY_P
-V 8300,4000,CONT_BODY_P
-V 4100,4000,CONT_BODY_P
-V 7500,4000,CONT_BODY_P
-V 8700,4000,CONT_BODY_P
-V 7900,4000,CONT_BODY_P
-V 6700,4000,CONT_BODY_P
-V 6300,4000,CONT_BODY_P
-V 5900,-200,CONT_BODY_P
-V 7100,-200,CONT_BODY_P
-V 12100,-200,CONT_BODY_P
-V 11700,-200,CONT_BODY_P
-V 8300,-200,CONT_BODY_P
-V 10700,-200,CONT_BODY_P
-V 9500,-200,CONT_BODY_P
-V 4100,-200,CONT_BODY_P
-V 9900,-200,CONT_BODY_P
-V 10300,-200,CONT_BODY_P
-V 13700,-200,CONT_BODY_P
-V 13300,-200,CONT_BODY_P
-V 14100,-200,CONT_BODY_P
-V 14500,-200,CONT_BODY_P
-V 12500,-200,CONT_BODY_P
-V 12900,-200,CONT_BODY_P
-V 5100,-200,CONT_BODY_P
-V 5500,-200,CONT_BODY_P
-V 6300,-200,CONT_BODY_P
-V 6700,-200,CONT_BODY_P
-V 7500,-200,CONT_BODY_P
-V 7900,-200,CONT_BODY_P
-V 9100,-200,CONT_BODY_P
-V 8700,-200,CONT_BODY_P
-V 6000,12000,CONT_BODY_N
-V 5900,5100,CONT_BODY_N
-V 8300,5100,CONT_BODY_N
-V 6700,5100,CONT_BODY_N
-V 6300,5100,CONT_BODY_N
-V 7100,12000,CONT_BODY_N
-V 10700,5100,CONT_BODY_N
-V 9100,5100,CONT_BODY_N
-V 8700,5100,CONT_BODY_N
-V 4100,5100,CONT_BODY_N
-V 4500,12000,CONT_BODY_N
-V 8300,12000,CONT_BODY_N
-V 9500,12000,CONT_BODY_N
-V 5500,12000,CONT_BODY_N
-V 5000,12000,CONT_BODY_N
-V 4100,12000,CONT_BODY_N
-V 7900,5100,CONT_BODY_N
-V 7500,5100,CONT_BODY_N
-V 9900,5100,CONT_BODY_N
-V 10300,5100,CONT_BODY_N
-V 7700,11400,CONT_DIF_P
-V 7700,8600,CONT_DIF_P
-V 7700,8200,CONT_DIF_P
-V 7700,5800,CONT_DIF_P
-V 7700,11000,CONT_DIF_P
-V 7700,10600,CONT_DIF_P
-V 7700,9000,CONT_DIF_P
-V 7700,10200,CONT_DIF_P
-V 7700,7000,CONT_DIF_P
-V 7700,6600,CONT_DIF_P
-V 7700,9800,CONT_DIF_P
-V 7700,9400,CONT_DIF_P
-V 7700,6200,CONT_DIF_P
-V 6500,6200,CONT_DIF_P
-V 7700,7400,CONT_DIF_P
-V 6500,11400,CONT_DIF_P
-V 6500,8600,CONT_DIF_P
-V 6500,8200,CONT_DIF_P
-V 6500,5800,CONT_DIF_P
-V 6500,11000,CONT_DIF_P
-V 6500,10600,CONT_DIF_P
-V 8300,7800,CONT_DIF_P
-V 7700,7800,CONT_DIF_P
-V 6500,7800,CONT_DIF_P
-V 6500,10200,CONT_DIF_P
-V 6500,7000,CONT_DIF_P
-V 6500,6600,CONT_DIF_P
-V 6500,9800,CONT_DIF_P
-V 6500,9400,CONT_DIF_P
-V 8300,11400,CONT_DIF_P
-V 6500,7400,CONT_DIF_P
-V 8300,6200,CONT_DIF_P
-V 8300,5800,CONT_DIF_P
-V 8300,7000,CONT_DIF_P
-V 8300,9800,CONT_DIF_P
-V 8300,10600,CONT_DIF_P
-V 8300,11000,CONT_DIF_P
-V 7100,8600,CONT_DIF_P
-V 6500,9000,CONT_DIF_P
-V 7100,8200,CONT_DIF_P
-V 7100,7800,CONT_DIF_P
-V 7100,11000,CONT_DIF_P
-V 7100,10600,CONT_DIF_P
-V 8300,9400,CONT_DIF_P
-V 8300,8200,CONT_DIF_P
-V 5900,5800,CONT_DIF_P
-V 8300,8600,CONT_DIF_P
-V 5900,6200,CONT_DIF_P
-V 7100,9400,CONT_DIF_P
-V 7100,9800,CONT_DIF_P
-V 7100,7000,CONT_DIF_P
-V 7100,5800,CONT_DIF_P
-V 7100,6200,CONT_DIF_P
-V 5900,10600,CONT_DIF_P
-V 7100,11400,CONT_DIF_P
-V 5900,11400,CONT_DIF_P
-V 5900,8200,CONT_DIF_P
-V 5900,7800,CONT_DIF_P
-V 5900,11000,CONT_DIF_P
-V 5900,9800,CONT_DIF_P
-V 5900,9400,CONT_DIF_P
-V 5300,11000,CONT_DIF_P
-V 5900,7000,CONT_DIF_P
-V 5300,10200,CONT_DIF_P
-V 5300,7800,CONT_DIF_P
-V 5300,7000,CONT_DIF_P
-V 5300,6600,CONT_DIF_P
-V 5300,9800,CONT_DIF_P
-V 5300,9400,CONT_DIF_P
-V 5300,10600,CONT_DIF_P
-V 5900,8600,CONT_DIF_P
-V 5300,7400,CONT_DIF_P
-V 5300,11400,CONT_DIF_P
-V 5300,8600,CONT_DIF_P
-V 5300,8200,CONT_DIF_P
-V 5300,5800,CONT_DIF_P
-V 9500,11000,CONT_DIF_P
-V 9500,9400,CONT_DIF_P
-V 5300,9000,CONT_DIF_P
-V 10700,7000,CONT_DIF_P
-V 9500,7000,CONT_DIF_P
-V 9500,5800,CONT_DIF_P
-V 9500,6200,CONT_DIF_P
-V 9500,8600,CONT_DIF_P
-V 9500,11400,CONT_DIF_P
-V 9500,8200,CONT_DIF_P
-V 5300,6200,CONT_DIF_P
-V 8900,7000,CONT_DIF_P
-V 9500,10600,CONT_DIF_P
-V 10700,9400,CONT_DIF_P
-V 10700,8200,CONT_DIF_P
-V 10700,11400,CONT_DIF_P
-V 10700,8600,CONT_DIF_P
-V 10700,6200,CONT_DIF_P
-V 9500,9800,CONT_DIF_P
-V 8900,8200,CONT_DIF_P
-V 10700,9800,CONT_DIF_P
-V 10700,10600,CONT_DIF_P
-V 10700,11000,CONT_DIF_P
-V 10700,7800,CONT_DIF_P
-V 8900,9000,CONT_DIF_P
-V 8900,7800,CONT_DIF_P
-V 9500,7800,CONT_DIF_P
-V 10100,6600,CONT_DIF_P
-V 8900,6600,CONT_DIF_P
-V 8900,9800,CONT_DIF_P
-V 8900,9400,CONT_DIF_P
-V 8900,6200,CONT_DIF_P
-V 8900,7400,CONT_DIF_P
-V 8900,11400,CONT_DIF_P
-V 10700,5800,CONT_DIF_P
-V 10100,5800,CONT_DIF_P
-V 8900,5800,CONT_DIF_P
-V 8900,11000,CONT_DIF_P
-V 8900,10600,CONT_DIF_P
-V 10100,9000,CONT_DIF_P
-V 10100,7800,CONT_DIF_P
-V 10100,10200,CONT_DIF_P
-V 8900,10200,CONT_DIF_P
-V 10100,10600,CONT_DIF_P
-V 10100,9800,CONT_DIF_P
-V 10100,9400,CONT_DIF_P
-V 10100,6200,CONT_DIF_P
-V 10100,7400,CONT_DIF_P
-V 10100,11400,CONT_DIF_P
-V 10100,8600,CONT_DIF_P
-V 8900,8600,CONT_DIF_P
-V 10100,7000,CONT_DIF_P
-V 10100,8200,CONT_DIF_P
-V 4700,6200,CONT_DIF_P
-V 4700,7400,CONT_DIF_P
-V 4700,11400,CONT_DIF_P
-V 4700,8600,CONT_DIF_P
-V 4700,9000,CONT_DIF_P
-V 4700,7800,CONT_DIF_P
-V 4700,7000,CONT_DIF_P
-V 10100,11000,CONT_DIF_P
-V 4700,5800,CONT_DIF_P
-V 4700,8200,CONT_DIF_P
-V 4700,11000,CONT_DIF_P
-V 4700,6600,CONT_DIF_P
-V 4700,10600,CONT_DIF_P
-V 4700,9800,CONT_DIF_P
-V 4700,10200,CONT_DIF_P
-V 4700,9400,CONT_DIF_P
-V 4100,6200,CONT_DIF_P
-V 4100,7000,CONT_DIF_P
-V 4100,5800,CONT_DIF_P
-V 4100,9800,CONT_DIF_P
-V 4100,11000,CONT_DIF_P
-V 4100,8200,CONT_DIF_P
-V 4100,11400,CONT_DIF_P
-V 4100,8600,CONT_DIF_P
-V 4100,10600,CONT_DIF_P
-V 4100,9400,CONT_DIF_P
-V 4100,7800,CONT_DIF_P
-V 7700,2100,CONT_DIF_N
-V 7100,700,CONT_DIF_N
-V 7700,2500,CONT_DIF_N
-V 7100,3300,CONT_DIF_N
-V 7100,2800,CONT_DIF_N
-V 6500,2900,CONT_DIF_N
-V 8300,1100,CONT_DIF_N
-V 8300,1500,CONT_DIF_N
-V 5900,700,CONT_DIF_N
-V 6500,3300,CONT_DIF_N
-V 6500,2100,CONT_DIF_N
-V 6500,2500,CONT_DIF_N
-V 7700,2900,CONT_DIF_N
-V 7700,3300,CONT_DIF_N
-V 7100,1500,CONT_DIF_N
-V 7100,1100,CONT_DIF_N
-V 5300,2500,CONT_DIF_N
-V 7100,1900,CONT_DIF_N
-V 8300,1900,CONT_DIF_N
-V 8300,2700,CONT_DIF_N
-V 8300,3100,CONT_DIF_N
-V 8300,700,CONT_DIF_N
-V 5300,3300,CONT_DIF_N
-V 10700,1100,CONT_DIF_N
-V 9500,1500,CONT_DIF_N
-V 5900,1100,CONT_DIF_N
-V 5900,1500,CONT_DIF_N
-V 5900,1900,CONT_DIF_N
-V 5900,2700,CONT_DIF_N
-V 5900,3100,CONT_DIF_N
-V 10700,2700,CONT_DIF_N
-V 10700,3100,CONT_DIF_N
-V 10700,700,CONT_DIF_N
-V 5300,2100,CONT_DIF_N
-V 5300,1700,CONT_DIF_N
-V 5300,1300,CONT_DIF_N
-V 5300,900,CONT_DIF_N
-V 5300,2900,CONT_DIF_N
-V 8900,2500,CONT_DIF_N
-V 7700,700,CONT_DIF_N
-V 8900,1200,CONT_DIF_N
-V 10100,2900,CONT_DIF_N
-V 9500,1100,CONT_DIF_N
-V 9500,700,CONT_DIF_N
-V 9500,1900,CONT_DIF_N
-V 10700,1900,CONT_DIF_N
-V 10100,700,CONT_DIF_N
-V 8900,700,CONT_DIF_N
-V 9500,3300,CONT_DIF_N
-V 10700,1500,CONT_DIF_N
-V 8900,2900,CONT_DIF_N
-V 8900,3300,CONT_DIF_N
-V 8900,2100,CONT_DIF_N
-V 9500,2800,CONT_DIF_N
-V 10100,3300,CONT_DIF_N
-V 10100,2100,CONT_DIF_N
-V 10100,2500,CONT_DIF_N
-V 10100,1200,CONT_DIF_N
-V 4700,1300,CONT_DIF_N
-V 4700,900,CONT_DIF_N
-V 4700,2500,CONT_DIF_N
-V 4700,2100,CONT_DIF_N
-V 4700,2900,CONT_DIF_N
-V 4700,3300,CONT_DIF_N
-V 4700,1700,CONT_DIF_N
-V 4100,1500,CONT_DIF_N
-V 4100,1100,CONT_DIF_N
-V 7700,1200,CONT_DIF_N
-V 4100,700,CONT_DIF_N
-V 4100,3100,CONT_DIF_N
-V 4100,2700,CONT_DIF_N
-V 4100,1900,CONT_DIF_N
-V 6500,700,CONT_DIF_N
-V 6500,1200,CONT_DIF_N
-V 16100,7500,CONT_VIA
-V 16100,8700,CONT_VIA
-V 16100,6700,CONT_VIA
-V 16100,10000,CONT_VIA
-V 16100,5500,CONT_BODY_N
-V 16100,9100,CONT_BODY_N
-V 16100,8300,CONT_BODY_N
-V 16100,10800,CONT_BODY_N
-V 16100,7100,CONT_BODY_N
-V 16100,11200,CONT_BODY_N
-V 16100,6300,CONT_BODY_N
-V 16100,5900,CONT_BODY_N
-V 16100,12000,CONT_BODY_N
-V 16100,9500,CONT_BODY_N
-V 16100,11600,CONT_BODY_N
-V 16100,7900,CONT_BODY_N
-V 16100,10400,CONT_BODY_N
-V 16100,5100,CONT_BODY_N
-V 13700,1600,CONT_VIA
-V 12500,1600,CONT_VIA
-V 11300,1600,CONT_VIA
-V 11900,9400,CONT_DIF_P
-V 11900,7000,CONT_DIF_P
-V 11900,5800,CONT_DIF_P
-V 11900,6200,CONT_DIF_P
-V 11900,8600,CONT_DIF_P
-V 11900,11400,CONT_DIF_P
-V 11900,8200,CONT_DIF_P
-V 11900,7800,CONT_DIF_P
-V 11900,10600,CONT_DIF_P
-V 11300,9000,CONT_DIF_P
-V 11300,7800,CONT_DIF_P
-V 11300,10200,CONT_DIF_P
-V 11300,7000,CONT_DIF_P
-V 11300,6600,CONT_DIF_P
-V 11300,9800,CONT_DIF_P
-V 11900,9800,CONT_DIF_P
-V 11300,6200,CONT_DIF_P
-V 11300,7400,CONT_DIF_P
-V 11300,11400,CONT_DIF_P
-V 11300,8600,CONT_DIF_P
-V 11300,8200,CONT_DIF_P
-V 11300,5800,CONT_DIF_P
-V 11300,11000,CONT_DIF_P
-V 11900,11000,CONT_DIF_P
-V 13100,9800,CONT_DIF_P
-V 13100,9400,CONT_DIF_P
-V 13100,8600,CONT_DIF_P
-V 13100,6200,CONT_DIF_P
-V 13100,5800,CONT_DIF_P
-V 13100,7000,CONT_DIF_P
-V 12500,10200,CONT_DIF_P
-V 11300,9400,CONT_DIF_P
-V 12500,9000,CONT_DIF_P
-V 13100,10600,CONT_DIF_P
-V 13100,11000,CONT_DIF_P
-V 13100,7800,CONT_DIF_P
-V 13100,8200,CONT_DIF_P
-V 13100,11400,CONT_DIF_P
-V 12500,8600,CONT_DIF_P
-V 11300,10600,CONT_DIF_P
-V 12500,9400,CONT_DIF_P
-V 12500,9800,CONT_DIF_P
-V 12500,10600,CONT_DIF_P
-V 12500,7800,CONT_DIF_P
-V 12500,8200,CONT_DIF_P
-V 13700,10200,CONT_DIF_P
-V 13700,7800,CONT_DIF_P
-V 13700,9000,CONT_DIF_P
-V 13700,8600,CONT_DIF_P
-V 13700,11400,CONT_DIF_P
-V 12500,11400,CONT_DIF_P
-V 13700,6200,CONT_DIF_P
-V 13700,9400,CONT_DIF_P
-V 13700,9800,CONT_DIF_P
-V 13700,6600,CONT_DIF_P
-V 13700,7000,CONT_DIF_P
-V 13700,10600,CONT_DIF_P
-V 13700,11000,CONT_DIF_P
-V 12500,11000,CONT_DIF_P
-V 13700,8200,CONT_DIF_P
-V 13100,10200,CONT_DIF_P
-V 11900,10200,CONT_DIF_P
-V 11900,9000,CONT_DIF_P
-V 13100,9000,CONT_DIF_P
-V 11900,7400,CONT_DIF_P
-V 13100,7400,CONT_DIF_P
-V 13700,7400,CONT_DIF_P
-V 11900,6600,CONT_DIF_P
-V 13100,6600,CONT_DIF_P
-V 13700,5800,CONT_DIF_P
-V 13700,700,CONT_DIF_N
-V 13700,1200,CONT_DIF_N
-V 12500,1200,CONT_DIF_N
-V 11300,700,CONT_DIF_N
-V 13700,2100,CONT_DIF_N
-V 11900,1500,CONT_DIF_N
-V 13700,3300,CONT_DIF_N
-V 11900,1100,CONT_DIF_N
-V 11900,700,CONT_DIF_N
-V 11900,1900,CONT_DIF_N
-V 11900,3300,CONT_DIF_N
-V 11300,2900,CONT_DIF_N
-V 11300,3300,CONT_DIF_N
-V 11300,2100,CONT_DIF_N
-V 11300,2500,CONT_DIF_N
-V 11300,1200,CONT_DIF_N
-V 11900,2800,CONT_DIF_N
-V 13100,1500,CONT_DIF_N
-V 13700,2900,CONT_DIF_N
-V 12500,3300,CONT_DIF_N
-V 12500,2900,CONT_DIF_N
-V 13100,3300,CONT_DIF_N
-V 13100,1900,CONT_DIF_N
-V 13100,700,CONT_DIF_N
-V 13100,1100,CONT_DIF_N
-V 13700,2500,CONT_DIF_N
-V 13100,2800,CONT_DIF_N
-V 12500,700,CONT_DIF_N
-V 12500,2500,CONT_DIF_N
-V 12500,2100,CONT_DIF_N
-V 13100,2300,CONT_DIF_N
-V 11900,2300,CONT_DIF_N
-V 16700,1600,CONT_VIA
-V 9500,4600,CONT_POLY
-V 14900,3500,CONT_VIA
-V 14900,-200,CONT_BODY_P
-V 14900,5100,CONT_BODY_N
-V 14300,3300,CONT_DIF_N
-V 14900,2700,CONT_DIF_N
-V 14900,3100,CONT_DIF_N
-V 16100,4000,CONT_BODY_P
-V 16100,4000,CONT_BODY_P
-V 16100,2800,CONT_BODY_P
-V 16100,3200,CONT_BODY_P
-V 16100,3600,CONT_VIA
-V 16100,2400,CONT_VIA
-V 14800,4500,CONT_POLY
-V 10700,12000,CONT_BODY_N
-V 15400,-700,CONT_VIA
-V 11300,-200,CONT_BODY_P
-V 10800,4000,CONT_POLY
-V 14900,4000,CONT_BODY_P
-V 14900,7500,CONT_DIF_P
-V 15500,7500,CONT_DIF_P
-V 14300,7500,CONT_DIF_P
-V 3800,27500,CONT_VIA
-V 3800,27900,CONT_VIA
-V 3800,28300,CONT_VIA
-V 3800,26300,CONT_VIA
-V 3800,25500,CONT_VIA
-V 3800,25100,CONT_VIA
-V 3800,24700,CONT_VIA
-V 3800,25900,CONT_VIA
-V 3800,20400,CONT_VIA
-V 3800,20800,CONT_VIA
-V 3800,22500,CONT_VIA
-V 3800,21200,CONT_VIA
-V 3800,21600,CONT_VIA
-V 3800,22000,CONT_VIA
-V 3800,26700,CONT_VIA
-V 3800,27100,CONT_VIA
-V 4000,29200,CONT_VIA
-V 3500,29200,CONT_VIA
-V 6400,23200,CONT_VIA
-V 3800,20000,CONT_VIA
-V 3800,18400,CONT_VIA
-V 3800,18800,CONT_VIA
-V 3800,17200,CONT_VIA
-V 3800,17600,CONT_VIA
-V 3800,16800,CONT_VIA
-V 3800,14400,CONT_VIA
-V 3800,14800,CONT_VIA
-V 3800,15200,CONT_VIA
-V 3800,15600,CONT_VIA
-V 3800,18000,CONT_VIA
-V 3800,19200,CONT_VIA
-V 3800,19600,CONT_VIA
-V 3800,14000,CONT_VIA
-V 3800,16400,CONT_VIA
-V 3800,16000,CONT_VIA
-V 3500,27900,CONT_BODY_P
-V 3500,28300,CONT_BODY_P
-V 3900,28700,CONT_BODY_P
-V 3500,24300,CONT_BODY_P
-V 3900,24300,CONT_BODY_P
-V 3500,25500,CONT_BODY_P
-V 3500,25100,CONT_BODY_P
-V 3500,24700,CONT_BODY_P
-V 3500,28700,CONT_BODY_P
-V 3500,25900,CONT_BODY_P
-V 3500,26300,CONT_BODY_P
-V 3500,26700,CONT_BODY_P
-V 3500,27100,CONT_BODY_P
-V 3500,27500,CONT_BODY_P
-V 3500,22500,CONT_BODY_N
-V 4100,22500,CONT_BODY_N
-V 3500,22000,CONT_BODY_N
-V 3500,21600,CONT_BODY_N
-V 3500,21200,CONT_BODY_N
-V 3500,20800,CONT_BODY_N
-V 3500,20400,CONT_BODY_N
-V 3500,19200,CONT_BODY_N
-V 3500,18800,CONT_BODY_N
-V 3500,17200,CONT_BODY_N
-V 3500,16400,CONT_BODY_N
-V 3500,16000,CONT_BODY_N
-V 3500,18000,CONT_BODY_N
-V 3500,17600,CONT_BODY_N
-V 3500,20000,CONT_BODY_N
-V 3500,18400,CONT_BODY_N
-V 3500,19600,CONT_BODY_N
-V 3500,15600,CONT_BODY_N
-V 3500,15200,CONT_BODY_N
-V 3500,14800,CONT_BODY_N
-V 3500,14400,CONT_BODY_N
-V 3500,14000,CONT_BODY_N
-V 4000,13600,CONT_BODY_N
-V 3500,13600,CONT_BODY_N
-V 3500,16800,CONT_BODY_N
-V 4100,20300,CONT_DIF_P
-V 4100,20700,CONT_DIF_P
-V 4100,21100,CONT_DIF_P
-V 4100,21500,CONT_DIF_P
-V 4100,21900,CONT_DIF_P
-V 4100,14300,CONT_DIF_P
-V 4100,19900,CONT_DIF_P
-V 4100,19500,CONT_DIF_P
-V 4100,19100,CONT_DIF_P
-V 4100,18700,CONT_DIF_P
-V 4100,18300,CONT_DIF_P
-V 4100,17500,CONT_DIF_P
-V 4100,17900,CONT_DIF_P
-V 4100,17100,CONT_DIF_P
-V 4100,16700,CONT_DIF_P
-V 4100,16300,CONT_DIF_P
-V 4100,15900,CONT_DIF_P
-V 4100,15500,CONT_DIF_P
-V 4100,15100,CONT_DIF_P
-V 4100,14700,CONT_DIF_P
-V 4100,27300,CONT_DIF_N
-V 4100,26100,CONT_DIF_N
-V 4100,24900,CONT_DIF_N
-V 4100,25300,CONT_DIF_N
-V 4100,25700,CONT_DIF_N
-V 4100,26500,CONT_DIF_N
-V 4100,26900,CONT_DIF_N
-V 4100,27700,CONT_DIF_N
-V 4100,28100,CONT_DIF_N
-V 11900,29200,CONT_VIA
-V 11300,29200,CONT_VIA
-V 11900,25900,CONT_VIA
-V 11600,24300,CONT_VIA
-V 11900,27900,CONT_VIA
-V 11900,28300,CONT_BODY_P
-V 11900,28700,CONT_BODY_P
-V 11900,24300,CONT_BODY_P
-V 11900,25500,CONT_BODY_P
-V 11900,25100,CONT_BODY_P
-V 11900,24700,CONT_BODY_P
-V 11900,26300,CONT_BODY_P
-V 11900,26700,CONT_BODY_P
-V 11900,27100,CONT_BODY_P
-V 11900,27500,CONT_BODY_P
-V 11600,22500,CONT_VIA
-V 11600,20700,CONT_VIA
-V 11600,20300,CONT_VIA
-V 11600,21900,CONT_VIA
-V 11600,21500,CONT_VIA
-V 11600,13900,CONT_VIA
-V 11600,16700,CONT_VIA
-V 11600,14700,CONT_VIA
-V 11600,19500,CONT_VIA
-V 11600,17900,CONT_VIA
-V 11600,17100,CONT_VIA
-V 11600,18300,CONT_VIA
-V 11600,15500,CONT_VIA
-V 11600,15900,CONT_VIA
-V 11600,14300,CONT_VIA
-V 11600,19100,CONT_VIA
-V 11900,22000,CONT_BODY_N
-V 11900,22500,CONT_BODY_N
-V 11900,20400,CONT_BODY_N
-V 11900,20800,CONT_BODY_N
-V 11900,21200,CONT_BODY_N
-V 11900,21600,CONT_BODY_N
-V 11900,14800,CONT_BODY_N
-V 11900,15200,CONT_BODY_N
-V 11900,13600,CONT_BODY_N
-V 11900,15600,CONT_BODY_N
-V 11900,17200,CONT_BODY_N
-V 11900,16800,CONT_BODY_N
-V 11900,16000,CONT_BODY_N
-V 11500,13600,CONT_BODY_N
-V 11900,19200,CONT_BODY_N
-V 11900,19600,CONT_BODY_N
-V 11900,20000,CONT_BODY_N
-V 11900,17600,CONT_BODY_N
-V 11900,18000,CONT_BODY_N
-V 11900,16400,CONT_BODY_N
-V 11900,14000,CONT_BODY_N
-V 11900,14400,CONT_BODY_N
-V 11900,18400,CONT_BODY_N
-V 11900,18800,CONT_BODY_N
-V 3300,5800,CONT_VIA
-V 3300,9900,CONT_VIA
-V 2100,9800,CONT_VIA
-V 2100,6600,CONT_VIA
-V 3100,9400,CONT_POLY
-V 3300,5100,CONT_BODY_N
-V 2700,5100,CONT_BODY_N
-V 2700,5500,CONT_BODY_N
-V 2700,5900,CONT_BODY_N
-V 2700,6300,CONT_BODY_N
-V 3300,10300,CONT_BODY_N
-V 3300,10700,CONT_BODY_N
-V 2100,11600,CONT_BODY_N
-V 2100,11200,CONT_BODY_N
-V 2100,10800,CONT_BODY_N
-V 2100,10400,CONT_BODY_N
-V 2100,5100,CONT_BODY_N
-V 2100,6300,CONT_BODY_N
-V 2100,7000,CONT_BODY_N
-V 2100,7400,CONT_BODY_N
-V 2100,7800,CONT_BODY_N
-V 2100,8200,CONT_BODY_N
-V 2100,8600,CONT_BODY_N
-V 2100,9000,CONT_BODY_N
-V 2100,12000,CONT_BODY_N
-V 2100,9400,CONT_BODY_N
-V 2100,5500,CONT_BODY_N
-V 2100,5900,CONT_BODY_N
-V 2700,6900,CONT_DIF_P
-V 2700,11300,CONT_DIF_P
-V 3600,12000,CONT_BODY_N
-V 3300,11500,CONT_BODY_N
-V 3500,2300,CONT_VIA
-V 3500,3500,CONT_VIA
-V 3500,700,CONT_BODY_P
-V 3500,1100,CONT_BODY_P
-V 3500,1500,CONT_BODY_P
-V 3500,1900,CONT_BODY_P
-V 3500,2700,CONT_BODY_P
-V 3500,3100,CONT_BODY_P
-V 3500,4000,CONT_BODY_P
-V 3500,300,CONT_BODY_P
-V 3500,-200,CONT_BODY_P
-V 4400,13600,CONT_BODY_N
-V 5300,13600,CONT_VIA
-V 4700,21900,CONT_DIF_P
-V 5300,21900,CONT_DIF_P
-V 5900,21900,CONT_DIF_P
-V 6500,21900,CONT_DIF_P
-V 5300,22500,CONT_BODY_N
-V 6500,22500,CONT_BODY_N
-V 5300,23800,CONT_VIA
-V 6400,23800,CONT_POLY
-V 6500,24300,CONT_BODY_P
-V 5300,24300,CONT_BODY_P
-V 6500,21500,CONT_DIF_P
-V 5900,21500,CONT_DIF_P
-V 5300,21500,CONT_DIF_P
-V 4700,21500,CONT_DIF_P
-V 5300,21100,CONT_VIA
-V 6500,21100,CONT_VIA
-V 5900,21100,CONT_DIF_P
-V 4700,21100,CONT_DIF_P
-V 4700,20700,CONT_DIF_P
-V 5900,20700,CONT_DIF_P
-V 6500,20700,CONT_DIF_P
-V 5300,20700,CONT_DIF_P
-V 6500,20300,CONT_DIF_P
-V 5300,20300,CONT_DIF_P
-V 5900,20300,CONT_DIF_P
-V 4700,20300,CONT_DIF_P
-V 6500,19900,CONT_VIA
-V 5300,19900,CONT_VIA
-V 5900,19900,CONT_DIF_P
-V 4700,19900,CONT_DIF_P
-V 6500,16300,CONT_VIA
-V 6500,17500,CONT_VIA
-V 6500,18700,CONT_VIA
-V 5300,16300,CONT_VIA
-V 5300,18700,CONT_VIA
-V 5300,17500,CONT_VIA
-V 6500,15100,CONT_VIA
-V 5300,15100,CONT_VIA
-V 5900,16700,CONT_DIF_P
-V 6500,16700,CONT_DIF_P
-V 6500,17100,CONT_DIF_P
-V 6500,15900,CONT_DIF_P
-V 5900,15900,CONT_DIF_P
-V 5900,16300,CONT_DIF_P
-V 6500,18300,CONT_DIF_P
-V 6500,17900,CONT_DIF_P
-V 5900,17900,CONT_DIF_P
-V 5900,17100,CONT_DIF_P
-V 5900,17500,CONT_DIF_P
-V 5900,19500,CONT_DIF_P
-V 6500,19100,CONT_DIF_P
-V 5900,19100,CONT_DIF_P
-V 5900,18700,CONT_DIF_P
-V 5900,18300,CONT_DIF_P
-V 6500,19500,CONT_DIF_P
-V 6500,15500,CONT_DIF_P
-V 5900,15500,CONT_DIF_P
-V 5300,17100,CONT_DIF_P
-V 5300,16700,CONT_DIF_P
-V 4700,16700,CONT_DIF_P
-V 4700,17100,CONT_DIF_P
-V 4700,17500,CONT_DIF_P
-V 5300,15900,CONT_DIF_P
-V 4700,15900,CONT_DIF_P
-V 4700,16300,CONT_DIF_P
-V 5300,19500,CONT_DIF_P
-V 5300,19100,CONT_DIF_P
-V 4700,19100,CONT_DIF_P
-V 4700,18700,CONT_DIF_P
-V 5300,18300,CONT_DIF_P
-V 4700,18300,CONT_DIF_P
-V 5300,17900,CONT_DIF_P
-V 4700,17900,CONT_DIF_P
-V 4700,19500,CONT_DIF_P
-V 4700,15500,CONT_DIF_P
-V 5300,15500,CONT_DIF_P
-V 5900,15100,CONT_DIF_P
-V 6500,14700,CONT_DIF_P
-V 5900,14700,CONT_DIF_P
-V 6500,14300,CONT_DIF_P
-V 5900,14300,CONT_DIF_P
-V 4700,14300,CONT_DIF_P
-V 4700,15100,CONT_DIF_P
-V 5300,14700,CONT_DIF_P
-V 4700,14700,CONT_DIF_P
-V 5300,14300,CONT_DIF_P
-V 5900,27400,CONT_DIF_N
-V 5900,27000,CONT_DIF_N
-V 5900,26600,CONT_DIF_N
-V 5900,27800,CONT_DIF_N
-V 5900,25000,CONT_DIF_N
-V 5900,25400,CONT_DIF_N
-V 5900,26200,CONT_DIF_N
-V 5900,25800,CONT_DIF_N
-V 4700,27000,CONT_DIF_N
-V 4700,26600,CONT_DIF_N
-V 4700,26200,CONT_DIF_N
-V 4700,25800,CONT_DIF_N
-V 4700,25400,CONT_DIF_N
-V 4700,27800,CONT_DIF_N
-V 4700,27400,CONT_DIF_N
-V 4700,25000,CONT_DIF_N
-V 4900,13600,CONT_BODY_N
-V 5300,28700,CONT_BODY_P
-V 6500,28700,CONT_BODY_P
-V 5300,26100,CONT_VIA
-V 5300,27700,CONT_VIA
-V 5300,25700,CONT_DIF_N
-V 5300,28100,CONT_DIF_N
-V 5300,26500,CONT_DIF_N
-V 5300,27300,CONT_DIF_N
-V 5300,26900,CONT_DIF_N
-V 5300,25300,CONT_DIF_N
-V 5300,24900,CONT_VIA
-V 6500,28100,CONT_VIA
-V 6500,24900,CONT_VIA
-V 6500,26500,CONT_VIA
-V 6500,25300,CONT_DIF_N
-V 6500,26900,CONT_DIF_N
-V 6500,27300,CONT_DIF_N
-V 6500,25700,CONT_DIF_N
-V 6500,26100,CONT_DIF_N
-V 6500,27700,CONT_DIF_N
-V 6500,13100,CONT_POLY
-V 6400,13600,CONT_BODY_N
-V 8900,27700,CONT_DIF_N
-V 8900,26100,CONT_DIF_N
-V 8900,25700,CONT_DIF_N
-V 8900,27300,CONT_DIF_N
-V 8900,26900,CONT_DIF_N
-V 8900,25300,CONT_DIF_N
-V 8900,26500,CONT_VIA
-V 8900,24900,CONT_VIA
-V 8900,28100,CONT_VIA
-V 7700,24900,CONT_VIA
-V 7700,25300,CONT_DIF_N
-V 7700,26900,CONT_DIF_N
-V 7700,27300,CONT_DIF_N
-V 7700,26500,CONT_DIF_N
-V 7700,28100,CONT_DIF_N
-V 7700,25700,CONT_DIF_N
-V 7700,27700,CONT_VIA
-V 7700,26100,CONT_VIA
-V 8900,28700,CONT_BODY_P
-V 7700,28700,CONT_BODY_P
-V 6800,13600,CONT_BODY_N
-V 7900,13600,CONT_BODY_N
-V 7300,13600,CONT_BODY_N
-V 8700,13600,CONT_BODY_N
-V 8300,13100,CONT_POLY
-V 7600,13600,CONT_VIA
-V 7100,25000,CONT_DIF_N
-V 7100,27400,CONT_DIF_N
-V 7100,27800,CONT_DIF_N
-V 7100,25400,CONT_DIF_N
-V 7100,25800,CONT_DIF_N
-V 7100,26200,CONT_DIF_N
-V 7100,26600,CONT_DIF_N
-V 7100,27000,CONT_DIF_N
-V 8300,25800,CONT_DIF_N
-V 8300,26200,CONT_DIF_N
-V 8300,25400,CONT_DIF_N
-V 8300,25000,CONT_DIF_N
-V 8300,27800,CONT_DIF_N
-V 8300,26600,CONT_DIF_N
-V 8300,27000,CONT_DIF_N
-V 8300,27400,CONT_DIF_N
-V 7700,14300,CONT_DIF_P
-V 7100,14700,CONT_DIF_P
-V 7700,14700,CONT_DIF_P
-V 7100,15100,CONT_DIF_P
-V 7100,14300,CONT_DIF_P
-V 8300,14300,CONT_DIF_P
-V 8900,14300,CONT_DIF_P
-V 8300,14700,CONT_DIF_P
-V 8900,14700,CONT_DIF_P
-V 8300,15100,CONT_DIF_P
-V 7700,15500,CONT_DIF_P
-V 7100,15500,CONT_DIF_P
-V 7100,19500,CONT_DIF_P
-V 7100,17900,CONT_DIF_P
-V 7700,17900,CONT_DIF_P
-V 7100,18300,CONT_DIF_P
-V 7700,18300,CONT_DIF_P
-V 7100,18700,CONT_DIF_P
-V 7100,19100,CONT_DIF_P
-V 7700,19100,CONT_DIF_P
-V 7700,19500,CONT_DIF_P
-V 7100,16300,CONT_DIF_P
-V 7100,15900,CONT_DIF_P
-V 7700,15900,CONT_DIF_P
-V 7100,17500,CONT_DIF_P
-V 7100,17100,CONT_DIF_P
-V 7100,16700,CONT_DIF_P
-V 7700,16700,CONT_DIF_P
-V 7700,17100,CONT_DIF_P
-V 8300,15500,CONT_DIF_P
-V 8900,15500,CONT_DIF_P
-V 8900,19500,CONT_DIF_P
-V 8300,18300,CONT_DIF_P
-V 8300,18700,CONT_DIF_P
-V 8300,19100,CONT_DIF_P
-V 8900,19100,CONT_DIF_P
-V 8300,19500,CONT_DIF_P
-V 8300,17500,CONT_DIF_P
-V 8300,17100,CONT_DIF_P
-V 8300,17900,CONT_DIF_P
-V 8900,17900,CONT_DIF_P
-V 8900,18300,CONT_DIF_P
-V 8300,16300,CONT_DIF_P
-V 8300,15900,CONT_DIF_P
-V 8900,15900,CONT_DIF_P
-V 8900,17100,CONT_DIF_P
-V 8900,16700,CONT_DIF_P
-V 8300,16700,CONT_DIF_P
-V 7700,15100,CONT_VIA
-V 8900,15100,CONT_VIA
-V 7700,17500,CONT_VIA
-V 7700,18700,CONT_VIA
-V 7700,16300,CONT_VIA
-V 8900,18700,CONT_VIA
-V 8900,17500,CONT_VIA
-V 8900,16300,CONT_VIA
-V 7100,19900,CONT_DIF_P
-V 8300,19900,CONT_DIF_P
-V 7700,19900,CONT_VIA
-V 8900,19900,CONT_VIA
-V 7100,20300,CONT_DIF_P
-V 8300,20300,CONT_DIF_P
-V 7700,20300,CONT_DIF_P
-V 8900,20300,CONT_DIF_P
-V 7700,20700,CONT_DIF_P
-V 8900,20700,CONT_DIF_P
-V 8300,20700,CONT_DIF_P
-V 7100,20700,CONT_DIF_P
-V 7100,21100,CONT_DIF_P
-V 8300,21100,CONT_DIF_P
-V 8900,21100,CONT_VIA
-V 7700,21100,CONT_VIA
-V 7100,21500,CONT_DIF_P
-V 7700,21500,CONT_DIF_P
-V 8300,21500,CONT_DIF_P
-V 8900,21500,CONT_DIF_P
-V 7700,24300,CONT_BODY_P
-V 8900,24300,CONT_BODY_P
-V 8800,23800,CONT_POLY
-V 7700,23800,CONT_VIA
-V 8800,23200,CONT_VIA
-V 8900,22500,CONT_BODY_N
-V 7700,22500,CONT_BODY_N
-V 8900,21900,CONT_DIF_P
-V 8300,21900,CONT_DIF_P
-V 7700,21900,CONT_DIF_P
-V 7100,21900,CONT_DIF_P
-V 11300,27700,CONT_DIF_N
-V 11300,26100,CONT_DIF_N
-V 11300,25700,CONT_DIF_N
-V 11300,27300,CONT_DIF_N
-V 11300,26900,CONT_DIF_N
-V 11300,25300,CONT_DIF_N
-V 11300,26500,CONT_VIA
-V 11300,24900,CONT_VIA
-V 11300,28100,CONT_VIA
-V 10100,24900,CONT_VIA
-V 10100,25300,CONT_DIF_N
-V 10100,26900,CONT_DIF_N
-V 10100,27300,CONT_DIF_N
-V 10100,26500,CONT_DIF_N
-V 10100,28100,CONT_DIF_N
-V 10100,25700,CONT_DIF_N
-V 10100,27700,CONT_VIA
-V 10100,26100,CONT_VIA
-V 11300,28700,CONT_BODY_P
-V 10100,28700,CONT_BODY_P
-V 9200,13600,CONT_BODY_N
-V 10300,13600,CONT_BODY_N
-V 9700,13600,CONT_BODY_N
-V 11100,13600,CONT_BODY_N
-V 10700,13100,CONT_POLY
-V 10000,13600,CONT_VIA
-V 9500,25000,CONT_DIF_N
-V 9500,27400,CONT_DIF_N
-V 9500,27800,CONT_DIF_N
-V 9500,25400,CONT_DIF_N
-V 9500,25800,CONT_DIF_N
-V 9500,26200,CONT_DIF_N
-V 9500,26600,CONT_DIF_N
-V 9500,27000,CONT_DIF_N
-V 10700,25800,CONT_DIF_N
-V 10700,26200,CONT_DIF_N
-V 10700,25400,CONT_DIF_N
-V 10700,25000,CONT_DIF_N
-V 10700,27800,CONT_DIF_N
-V 10700,26600,CONT_DIF_N
-V 10700,27000,CONT_DIF_N
-V 10700,27400,CONT_DIF_N
-V 10100,14300,CONT_DIF_P
-V 9500,14700,CONT_DIF_P
-V 10100,14700,CONT_DIF_P
-V 9500,15100,CONT_DIF_P
-V 9500,14300,CONT_DIF_P
-V 10700,14300,CONT_DIF_P
-V 11300,14300,CONT_DIF_P
-V 10700,14700,CONT_DIF_P
-V 11300,14700,CONT_DIF_P
-V 10700,15100,CONT_DIF_P
-V 10100,15500,CONT_DIF_P
-V 9500,15500,CONT_DIF_P
-V 9500,19500,CONT_DIF_P
-V 9500,17900,CONT_DIF_P
-V 10100,17900,CONT_DIF_P
-V 9500,18300,CONT_DIF_P
-V 10100,18300,CONT_DIF_P
-V 9500,18700,CONT_DIF_P
-V 9500,19100,CONT_DIF_P
-V 10100,19100,CONT_DIF_P
-V 10100,19500,CONT_DIF_P
-V 9500,16300,CONT_DIF_P
-V 9500,15900,CONT_DIF_P
-V 10100,15900,CONT_DIF_P
-V 9500,17500,CONT_DIF_P
-V 9500,17100,CONT_DIF_P
-V 9500,16700,CONT_DIF_P
-V 10100,16700,CONT_DIF_P
-V 10100,17100,CONT_DIF_P
-V 10700,15500,CONT_DIF_P
-V 11300,15500,CONT_DIF_P
-V 11300,19500,CONT_DIF_P
-V 10700,18300,CONT_DIF_P
-V 10700,18700,CONT_DIF_P
-V 10700,19100,CONT_DIF_P
-V 11300,19100,CONT_DIF_P
-V 10700,19500,CONT_DIF_P
-V 10700,17500,CONT_DIF_P
-V 10700,17100,CONT_DIF_P
-V 10700,17900,CONT_DIF_P
-V 11300,17900,CONT_DIF_P
-V 11300,18300,CONT_DIF_P
-V 10700,16300,CONT_DIF_P
-V 10700,15900,CONT_DIF_P
-V 11300,15900,CONT_DIF_P
-V 11300,17100,CONT_DIF_P
-V 11300,16700,CONT_DIF_P
-V 10700,16700,CONT_DIF_P
-V 10100,15100,CONT_VIA
-V 11300,15100,CONT_VIA
-V 10100,17500,CONT_VIA
-V 10100,18700,CONT_VIA
-V 10100,16300,CONT_VIA
-V 11300,18700,CONT_VIA
-V 11300,17500,CONT_VIA
-V 11300,16300,CONT_VIA
-V 9500,19900,CONT_DIF_P
-V 10700,19900,CONT_DIF_P
-V 10100,19900,CONT_VIA
-V 11300,19900,CONT_VIA
-V 9500,20300,CONT_DIF_P
-V 10700,20300,CONT_DIF_P
-V 10100,20300,CONT_DIF_P
-V 11300,20300,CONT_DIF_P
-V 10100,20700,CONT_DIF_P
-V 11300,20700,CONT_DIF_P
-V 10700,20700,CONT_DIF_P
-V 9500,20700,CONT_DIF_P
-V 9500,21100,CONT_DIF_P
-V 10700,21100,CONT_DIF_P
-V 11300,21100,CONT_VIA
-V 10100,21100,CONT_VIA
-V 9500,21500,CONT_DIF_P
-V 10100,21500,CONT_DIF_P
-V 10700,21500,CONT_DIF_P
-V 11300,21500,CONT_DIF_P
-V 10100,24300,CONT_BODY_P
-V 11300,24300,CONT_BODY_P
-V 11200,23800,CONT_POLY
-V 10100,23800,CONT_VIA
-V 11200,23200,CONT_VIA
-V 11300,22500,CONT_BODY_N
-V 10100,22500,CONT_BODY_N
-V 11300,21900,CONT_DIF_P
-V 10700,21900,CONT_DIF_P
-V 10100,21900,CONT_DIF_P
-V 9500,21900,CONT_DIF_P
-EOF
diff --git a/alliance/share/cells/padlib/palow_sp.ap b/alliance/share/cells/padlib/palow_sp.ap
deleted file mode 100644
index 01f349c9..00000000
--- a/alliance/share/cells/padlib/palow_sp.ap
+++ /dev/null
@@ -1,1064 +0,0 @@
-V ALLIANCE : 3
-H palow_sp,P,11/ 9/95
-A 0,-7,172,356
-C 0,6,12,ck,0,WEST,ALU2
-C 172,6,12,ck,1,EAST,ALU2
-C 0,84,40,vddi,0,WEST,ALU2
-C 0,40,40,vssi,0,WEST,ALU2
-C 172,40,40,vssi,1,EAST,ALU2
-C 172,84,40,vddi,1,EAST,ALU2
-C 0,168,120,vdde,0,WEST,ALU2
-C 172,168,120,vdde,1,EAST,ALU2
-C 75,-7,2,i,1,SOUTH,ALU2
-C 75,-7,2,i,0,SOUTH,ALU1
-C 172,296,120,vsse,1,EAST,ALU2
-C 0,296,120,vsse,0,WEST,ALU2
-S 0,6,172,6,12,ck,RIGHT,ALU2
-S 0,40,172,40,40,vssi,RIGHT,ALU2
-S 0,84,172,84,40,vddi,RIGHT,ALU2
-S 0,168,172,168,120,vdde,RIGHT,ALU2
-S 0,296,172,296,120,vsse,RIGHT,ALU2
-S 126,225,132,225,3,*,RIGHT,NTIE
-S 126,136,132,136,3,*,RIGHT,NTIE
-S 134,16,144,16,3,*,RIGHT,ALU1
-S 125,289,125,293,3,*,UP,ALU1
-S 129,242,129,293,6,*,UP,ALU1
-S 129,135,129,226,6,*,UP,ALU1
-S 131,242,131,288,3,*,UP,PTIE
-S 127,287,132,287,3,*,RIGHT,PTIE
-S 126,243,132,243,3,*,RIGHT,PTIE
-S 131,135,131,226,3,*,UP,NTIE
-S 130,134,130,227,6,*,UP,NWELL
-S 50,242,50,293,8,*,UP,ALU1
-S 46,280,46,288,1,*,UP,ALU1
-S 50,135,50,226,8,*,UP,ALU1
-S 46,287,54,287,3,*,RIGHT,PTIE
-S 47,242,47,288,3,*,UP,PTIE
-S 46,243,54,243,3,*,RIGHT,PTIE
-S 47,225,53,225,3,*,RIGHT,NTIE
-S 47,136,53,136,3,*,RIGHT,NTIE
-S 47,136,47,226,3,*,UP,NTIE
-S 53,141,53,220,3,*,UP,PDIF
-S 53,249,53,282,3,*,UP,NDIF
-S 49,134,49,227,8,*,UP,NWELL
-S 143,16,143,233,3,*,UP,ALU1
-S 137,232,144,232,3,*,RIGHT,ALU1
-S 76,232,143,232,3,*,RIGHT,ALU2
-S 112,50,112,120,2,*,UP,ALU1
-S 88,51,97,51,3,*,RIGHT,ALU1
-S 118,50,118,121,3,*,UP,ALU1
-S 86,40,119,40,3,*,RIGHT,ALU1
-S 103,51,119,51,3,*,RIGHT,ALU1
-S 70,50,70,121,2,*,UP,ALU1
-S 106,58,106,129,2,*,UP,ALU1
-S 94,58,94,129,2,*,UP,ALU1
-S 94,6,94,33,2,*,UP,ALU1
-S 63,120,90,120,3,*,RIGHT,ALU1
-S 100,57,100,120,2,*,UP,ALU1
-S 82,46,99,46,2,*,RIGHT,ALU1
-S 88,50,88,121,2,*,UP,ALU1
-S 82,9,82,114,2,*,UP,ALU1
-S 76,9,76,114,2,*,UP,ALU1
-S 106,6,106,33,2,*,UP,ALU1
-S 66,50,66,121,7,*,UP,ALU1
-S 63,51,71,51,3,*,RIGHT,ALU1
-S 66,-3,66,41,7,*,UP,ALU1
-S 100,-3,100,32,2,*,UP,ALU1
-S 88,-3,88,41,2,*,UP,ALU1
-S 70,-3,70,41,2,*,UP,ALU1
-S 75,-7,75,3,2,*,UP,ALU1
-S 112,-3,112,41,2,*,UP,ALU1
-S 118,-3,118,41,3,*,UP,ALU1
-S 79,-2,119,-2,3,*,RIGHT,ALU1
-S 100,37,100,54,2,*,UP,POLY
-S 91,54,109,54,1,*,RIGHT,POLY
-S 91,37,109,37,1,*,RIGHT,POLY
-S 78,53,85,53,3,*,RIGHT,POLY
-S 85,37,85,54,1,*,UP,POLY
-S 73,37,73,54,1,*,UP,POLY
-S 73,2,73,4,1,*,UP,POLY
-S 63,40,71,40,3,*,RIGHT,PTIE
-S 87,40,97,40,3,*,RIGHT,PTIE
-S 103,40,119,40,3,*,RIGHT,PTIE
-S 64,-3,64,41,3,*,UP,PTIE
-S 118,-3,118,41,3,*,UP,PTIE
-S 63,-2,119,-2,3,*,RIGHT,PTIE
-S 63,51,71,51,3,*,RIGHT,NTIE
-S 64,50,64,121,3,*,UP,NTIE
-S 87,51,97,51,3,*,RIGHT,NTIE
-S 118,50,118,121,3,*,UP,NTIE
-S 103,51,119,51,3,*,RIGHT,NTIE
-S 63,120,118,120,3,*,RIGHT,NTIE
-S 82,56,82,115,3,*,UP,PDIF
-S 106,56,106,115,3,*,UP,PDIF
-S 97,54,97,117,1,*,UP,PTRANS
-S 76,56,76,115,3,*,UP,PDIF
-S 73,54,73,117,1,*,UP,PTRANS
-S 70,56,70,115,3,*,UP,PDIF
-S 103,54,103,117,1,*,UP,PTRANS
-S 91,54,91,117,1,*,UP,PTRANS
-S 88,56,88,115,3,*,UP,PDIF
-S 85,54,85,117,1,*,UP,PTRANS
-S 94,56,94,115,3,*,UP,PDIF
-S 112,56,112,115,3,*,UP,PDIF
-S 100,56,100,115,3,*,UP,PDIF
-S 109,54,109,117,1,*,UP,PTRANS
-S 85,4,85,37,1,*,UP,NTRANS
-S 82,6,82,35,3,*,UP,NDIF
-S 76,6,76,35,3,*,UP,NDIF
-S 73,4,73,37,1,*,UP,NTRANS
-S 70,6,70,35,2,*,UP,NDIF
-S 112,6,112,35,3,*,UP,NDIF
-S 103,4,103,37,1,*,UP,NTRANS
-S 97,4,97,37,1,*,UP,NTRANS
-S 91,4,91,37,1,*,UP,NTRANS
-S 88,6,88,35,2,*,UP,NDIF
-S 70,6,70,35,3,*,UP,NDIF
-S 106,6,106,35,3,*,UP,NDIF
-S 94,6,94,35,3,*,UP,NDIF
-S 112,6,112,35,2,*,UP,NDIF
-S 100,6,100,35,2,*,UP,NDIF
-S 109,4,109,37,1,*,UP,NTRANS
-S 62,86,120,86,72,*,RIGHT,NWELL
-S 62,51,120,51,4,*,RIGHT,NWELL
-S 66,16,143,16,3,*,RIGHT,ALU2
-S 70,130,144,130,2,*,RIGHT,ALU1
-S 70,131,144,131,2,*,RIGHT,ALU1
-S 58,296,120,296,9,*,RIGHT,ALU1
-S 59,142,59,291,3,*,UP,ALU1
-S 71,142,71,291,3,*,UP,ALU1
-S 65,237,65,288,3,*,UP,ALU1
-S 77,242,77,288,3,*,UP,ALU1
-S 77,248,77,282,3,*,UP,NDIF
-S 71,248,71,282,3,*,UP,NDIF
-S 65,248,65,282,3,*,UP,NDIF
-S 59,248,59,282,3,*,UP,NDIF
-S 56,246,56,284,1,*,UP,NTRANS
-S 62,246,62,284,1,*,UP,NTRANS
-S 68,246,68,284,1,*,UP,NTRANS
-S 74,246,74,284,1,*,UP,NTRANS
-S 54,287,78,287,3,*,RIGHT,PTIE
-S 77,141,77,220,3,*,UP,PDIF
-S 71,141,71,220,2,*,UP,PDIF
-S 65,141,65,220,2,*,UP,PDIF
-S 59,141,59,220,2,*,UP,PDIF
-S 56,139,56,222,1,*,UP,PTRANS
-S 65,138,65,226,3,*,UP,ALU1
-S 62,139,62,222,1,*,UP,PTRANS
-S 68,139,68,222,1,*,UP,PTRANS
-S 74,139,74,222,1,*,UP,PTRANS
-S 67,134,67,227,28,*,UP,NWELL
-S 77,138,77,226,3,*,UP,ALU1
-S 54,136,68,136,3,*,RIGHT,NTIE
-S 74,136,78,136,3,*,RIGHT,NTIE
-S 71,133,71,139,2,*,UP,POLY
-S 56,139,74,139,1,*,RIGHT,POLY
-S 54,136,68,136,3,*,RIGHT,ALU1
-S 74,136,78,136,3,*,RIGHT,ALU1
-S 71,237,71,239,2,*,UP,POLY
-S 54,243,68,243,3,*,RIGHT,PTIE
-S 74,243,78,243,3,*,RIGHT,PTIE
-S 56,246,74,246,1,*,RIGHT,POLY
-S 71,238,71,246,2,*,UP,POLY
-S 71,238,76,238,3,*,RIGHT,POLY
-S 76,232,76,238,2,*,UP,ALU1
-S 54,225,78,225,3,*,RIGHT,NTIE
-S 107,142,107,291,3,*,UP,ALU1
-S 119,142,119,291,3,*,UP,ALU1
-S 113,237,113,288,3,*,UP,ALU1
-S 125,242,125,288,3,*,UP,ALU1
-S 125,248,125,282,3,*,UP,NDIF
-S 119,248,119,282,3,*,UP,NDIF
-S 113,248,113,282,3,*,UP,NDIF
-S 107,248,107,282,3,*,UP,NDIF
-S 104,246,104,284,1,*,UP,NTRANS
-S 110,246,110,284,1,*,UP,NTRANS
-S 116,246,116,284,1,*,UP,NTRANS
-S 122,246,122,284,1,*,UP,NTRANS
-S 102,287,126,287,3,*,RIGHT,PTIE
-S 125,141,125,220,3,*,UP,PDIF
-S 119,141,119,220,2,*,UP,PDIF
-S 113,141,113,220,2,*,UP,PDIF
-S 107,141,107,220,2,*,UP,PDIF
-S 104,139,104,222,1,*,UP,PTRANS
-S 113,138,113,226,3,*,UP,ALU1
-S 110,139,110,222,1,*,UP,PTRANS
-S 116,139,116,222,1,*,UP,PTRANS
-S 122,139,122,222,1,*,UP,PTRANS
-S 115,134,115,227,28,*,UP,NWELL
-S 125,138,125,226,3,*,UP,ALU1
-S 102,136,116,136,3,*,RIGHT,NTIE
-S 122,136,126,136,3,*,RIGHT,NTIE
-S 119,133,119,139,2,*,UP,POLY
-S 104,139,122,139,1,*,RIGHT,POLY
-S 102,136,116,136,3,*,RIGHT,ALU1
-S 122,136,126,136,3,*,RIGHT,ALU1
-S 119,237,119,239,2,*,UP,POLY
-S 102,243,116,243,3,*,RIGHT,PTIE
-S 122,243,126,243,3,*,RIGHT,PTIE
-S 104,246,122,246,1,*,RIGHT,POLY
-S 119,238,119,246,2,*,UP,POLY
-S 119,238,124,238,3,*,RIGHT,POLY
-S 124,232,124,238,2,*,UP,ALU1
-S 102,225,126,225,3,*,RIGHT,NTIE
-S 83,142,83,291,3,*,UP,ALU1
-S 95,142,95,291,3,*,UP,ALU1
-S 89,237,89,288,3,*,UP,ALU1
-S 101,242,101,288,3,*,UP,ALU1
-S 101,248,101,282,3,*,UP,NDIF
-S 95,248,95,282,3,*,UP,NDIF
-S 89,248,89,282,3,*,UP,NDIF
-S 83,248,83,282,3,*,UP,NDIF
-S 80,246,80,284,1,*,UP,NTRANS
-S 86,246,86,284,1,*,UP,NTRANS
-S 92,246,92,284,1,*,UP,NTRANS
-S 98,246,98,284,1,*,UP,NTRANS
-S 78,287,102,287,3,*,RIGHT,PTIE
-S 101,141,101,220,3,*,UP,PDIF
-S 95,141,95,220,2,*,UP,PDIF
-S 89,141,89,220,2,*,UP,PDIF
-S 83,141,83,220,2,*,UP,PDIF
-S 80,139,80,222,1,*,UP,PTRANS
-S 89,138,89,226,3,*,UP,ALU1
-S 86,139,86,222,1,*,UP,PTRANS
-S 92,139,92,222,1,*,UP,PTRANS
-S 98,139,98,222,1,*,UP,PTRANS
-S 91,134,91,227,28,*,UP,NWELL
-S 101,138,101,226,3,*,UP,ALU1
-S 78,136,92,136,3,*,RIGHT,NTIE
-S 98,136,102,136,3,*,RIGHT,NTIE
-S 95,133,95,139,2,*,UP,POLY
-S 80,139,98,139,1,*,RIGHT,POLY
-S 78,136,92,136,3,*,RIGHT,ALU1
-S 98,136,102,136,3,*,RIGHT,ALU1
-S 95,237,95,239,2,*,UP,POLY
-S 78,243,92,243,3,*,RIGHT,PTIE
-S 98,243,102,243,3,*,RIGHT,PTIE
-S 80,246,98,246,1,*,RIGHT,POLY
-S 95,238,95,246,2,*,UP,POLY
-S 95,238,100,238,3,*,RIGHT,POLY
-S 100,232,100,238,2,*,UP,ALU1
-S 78,225,102,225,3,*,RIGHT,NTIE
-S 89,301,89,356,62,*,UP,ALU1
-V 135,16,CONT_VIA
-V 139,16,CONT_VIA
-V 125,292,CONT_VIA
-V 131,292,CONT_VIA
-V 128,225,CONT_VIA
-V 131,279,CONT_VIA
-V 128,243,CONT_VIA
-V 131,259,CONT_VIA
-V 128,219,CONT_VIA
-V 128,203,CONT_VIA
-V 128,207,CONT_VIA
-V 128,215,CONT_VIA
-V 128,195,CONT_VIA
-V 128,191,CONT_VIA
-V 128,147,CONT_VIA
-V 128,167,CONT_VIA
-V 128,139,CONT_VIA
-V 128,143,CONT_VIA
-V 128,159,CONT_VIA
-V 128,155,CONT_VIA
-V 128,183,CONT_VIA
-V 128,171,CONT_VIA
-V 128,179,CONT_VIA
-V 131,247,CONT_BODY_P
-V 131,251,CONT_BODY_P
-V 131,255,CONT_BODY_P
-V 131,243,CONT_BODY_P
-V 131,287,CONT_BODY_P
-V 131,283,CONT_BODY_P
-V 131,275,CONT_BODY_P
-V 131,271,CONT_BODY_P
-V 131,267,CONT_BODY_P
-V 131,263,CONT_BODY_P
-V 131,216,CONT_BODY_N
-V 131,212,CONT_BODY_N
-V 131,208,CONT_BODY_N
-V 131,204,CONT_BODY_N
-V 131,225,CONT_BODY_N
-V 131,200,CONT_BODY_N
-V 131,220,CONT_BODY_N
-V 131,184,CONT_BODY_N
-V 131,180,CONT_BODY_N
-V 131,176,CONT_BODY_N
-V 131,196,CONT_BODY_N
-V 131,192,CONT_BODY_N
-V 131,188,CONT_BODY_N
-V 127,136,CONT_BODY_N
-V 131,136,CONT_BODY_N
-V 131,156,CONT_BODY_N
-V 131,152,CONT_BODY_N
-V 131,148,CONT_BODY_N
-V 131,144,CONT_BODY_N
-V 131,140,CONT_BODY_N
-V 131,164,CONT_BODY_N
-V 131,160,CONT_BODY_N
-V 131,168,CONT_BODY_N
-V 131,172,CONT_BODY_N
-V 50,208,CONT_VIA
-V 50,204,CONT_VIA
-V 50,200,CONT_VIA
-V 52,292,CONT_VIA
-V 50,279,CONT_VIA
-V 50,275,CONT_VIA
-V 50,271,CONT_VIA
-V 50,267,CONT_VIA
-V 50,220,CONT_VIA
-V 50,216,CONT_VIA
-V 50,212,CONT_VIA
-V 50,225,CONT_VIA
-V 50,259,CONT_VIA
-V 50,247,CONT_VIA
-V 50,251,CONT_VIA
-V 50,255,CONT_VIA
-V 50,263,CONT_VIA
-V 50,283,CONT_VIA
-V 47,292,CONT_VIA
-V 50,156,CONT_VIA
-V 50,152,CONT_VIA
-V 50,148,CONT_VIA
-V 50,144,CONT_VIA
-V 50,168,CONT_VIA
-V 50,160,CONT_VIA
-V 50,164,CONT_VIA
-V 50,140,CONT_VIA
-V 50,176,CONT_VIA
-V 50,172,CONT_VIA
-V 50,188,CONT_VIA
-V 50,184,CONT_VIA
-V 50,196,CONT_VIA
-V 50,192,CONT_VIA
-V 50,180,CONT_VIA
-V 51,287,CONT_BODY_P
-V 51,243,CONT_BODY_P
-V 47,271,CONT_BODY_P
-V 47,267,CONT_BODY_P
-V 47,263,CONT_BODY_P
-V 47,259,CONT_BODY_P
-V 47,287,CONT_BODY_P
-V 47,247,CONT_BODY_P
-V 47,251,CONT_BODY_P
-V 47,255,CONT_BODY_P
-V 47,243,CONT_BODY_P
-V 47,283,CONT_BODY_P
-V 47,279,CONT_BODY_P
-V 47,275,CONT_BODY_P
-V 53,225,CONT_BODY_N
-V 47,225,CONT_BODY_N
-V 47,200,CONT_BODY_N
-V 47,204,CONT_BODY_N
-V 47,208,CONT_BODY_N
-V 47,212,CONT_BODY_N
-V 47,216,CONT_BODY_N
-V 47,220,CONT_BODY_N
-V 52,136,CONT_BODY_N
-V 47,168,CONT_BODY_N
-V 47,136,CONT_BODY_N
-V 47,140,CONT_BODY_N
-V 47,144,CONT_BODY_N
-V 47,148,CONT_BODY_N
-V 47,152,CONT_BODY_N
-V 47,156,CONT_BODY_N
-V 47,192,CONT_BODY_N
-V 47,196,CONT_BODY_N
-V 47,184,CONT_BODY_N
-V 47,176,CONT_BODY_N
-V 47,180,CONT_BODY_N
-V 47,160,CONT_BODY_N
-V 47,164,CONT_BODY_N
-V 47,172,CONT_BODY_N
-V 47,188,CONT_BODY_N
-V 53,219,CONT_DIF_P
-V 53,215,CONT_DIF_P
-V 53,211,CONT_DIF_P
-V 53,207,CONT_DIF_P
-V 53,203,CONT_DIF_P
-V 53,199,CONT_DIF_P
-V 53,163,CONT_DIF_P
-V 53,167,CONT_DIF_P
-V 53,171,CONT_DIF_P
-V 53,187,CONT_DIF_P
-V 53,191,CONT_DIF_P
-V 53,195,CONT_DIF_P
-V 53,143,CONT_DIF_P
-V 53,147,CONT_DIF_P
-V 53,151,CONT_DIF_P
-V 53,155,CONT_DIF_P
-V 53,159,CONT_DIF_P
-V 53,179,CONT_DIF_P
-V 53,175,CONT_DIF_P
-V 53,183,CONT_DIF_P
-V 53,257,CONT_DIF_N
-V 53,253,CONT_DIF_N
-V 53,249,CONT_DIF_N
-V 53,261,CONT_DIF_N
-V 53,273,CONT_DIF_N
-V 53,281,CONT_DIF_N
-V 53,277,CONT_DIF_N
-V 53,269,CONT_DIF_N
-V 53,265,CONT_DIF_N
-V 138,232,CONT_VIA
-V 143,232,CONT_VIA
-V 118,36,CONT_VIA
-V 118,24,CONT_VIA
-V 118,100,CONT_VIA
-V 118,75,CONT_VIA
-V 118,87,CONT_VIA
-V 118,67,CONT_VIA
-V 94,16,CONT_VIA
-V 106,16,CONT_VIA
-V 70,35,CONT_VIA
-V 70,102,CONT_VIA
-V 70,90,CONT_VIA
-V 70,74,CONT_VIA
-V 70,66,CONT_VIA
-V 70,23,CONT_VIA
-V 88,66,CONT_VIA
-V 88,74,CONT_VIA
-V 88,90,CONT_VIA
-V 88,102,CONT_VIA
-V 88,35,CONT_VIA
-V 88,23,CONT_VIA
-V 100,23,CONT_VIA
-V 100,74,CONT_VIA
-V 100,90,CONT_VIA
-V 100,102,CONT_VIA
-V 100,66,CONT_VIA
-V 112,23,CONT_VIA
-V 112,66,CONT_VIA
-V 112,102,CONT_VIA
-V 112,90,CONT_VIA
-V 112,74,CONT_VIA
-V 112,35,CONT_VIA
-V 64,66,CONT_VIA
-V 64,35,CONT_VIA
-V 64,23,CONT_VIA
-V 75,-7,CONT_VIA
-V 75,3,CONT_POLY
-V 77,53,CONT_POLY
-V 100,46,CONT_POLY
-V 118,28,CONT_BODY_P
-V 118,32,CONT_BODY_P
-V 118,8,CONT_BODY_P
-V 118,3,CONT_BODY_P
-V 118,40,CONT_BODY_P
-V 118,12,CONT_BODY_P
-V 118,16,CONT_BODY_P
-V 118,20,CONT_BODY_P
-V 92,40,CONT_BODY_P
-V 96,40,CONT_BODY_P
-V 108,40,CONT_BODY_P
-V 112,40,CONT_BODY_P
-V 88,40,CONT_BODY_P
-V 104,40,CONT_BODY_P
-V 70,40,CONT_BODY_P
-V 64,40,CONT_BODY_P
-V 64,31,CONT_BODY_P
-V 64,27,CONT_BODY_P
-V 64,19,CONT_BODY_P
-V 64,15,CONT_BODY_P
-V 64,11,CONT_BODY_P
-V 64,7,CONT_BODY_P
-V 64,3,CONT_BODY_P
-V 96,-2,CONT_BODY_P
-V 92,-2,CONT_BODY_P
-V 84,-2,CONT_BODY_P
-V 80,-2,CONT_BODY_P
-V 118,-2,CONT_BODY_P
-V 64,-2,CONT_BODY_P
-V 100,-2,CONT_BODY_P
-V 88,-2,CONT_BODY_P
-V 70,-2,CONT_BODY_P
-V 112,-2,CONT_BODY_P
-V 108,-2,CONT_BODY_P
-V 104,-2,CONT_BODY_P
-V 118,91,CONT_BODY_N
-V 118,83,CONT_BODY_N
-V 118,108,CONT_BODY_N
-V 118,116,CONT_BODY_N
-V 118,79,CONT_BODY_N
-V 118,71,CONT_BODY_N
-V 118,51,CONT_BODY_N
-V 118,112,CONT_BODY_N
-V 118,63,CONT_BODY_N
-V 118,59,CONT_BODY_N
-V 118,120,CONT_BODY_N
-V 118,95,CONT_BODY_N
-V 118,104,CONT_BODY_N
-V 118,55,CONT_BODY_N
-V 70,51,CONT_BODY_N
-V 74,120,CONT_BODY_N
-V 70,120,CONT_BODY_N
-V 79,120,CONT_BODY_N
-V 84,120,CONT_BODY_N
-V 112,120,CONT_BODY_N
-V 104,51,CONT_BODY_N
-V 108,51,CONT_BODY_N
-V 100,120,CONT_BODY_N
-V 92,51,CONT_BODY_N
-V 96,51,CONT_BODY_N
-V 112,51,CONT_BODY_N
-V 88,51,CONT_BODY_N
-V 89,120,CONT_BODY_N
-V 64,86,CONT_BODY_N
-V 64,78,CONT_BODY_N
-V 64,74,CONT_BODY_N
-V 64,70,CONT_BODY_N
-V 64,63,CONT_BODY_N
-V 64,59,CONT_BODY_N
-V 64,55,CONT_BODY_N
-V 64,104,CONT_BODY_N
-V 64,94,CONT_BODY_N
-V 64,98,CONT_BODY_N
-V 64,51,CONT_BODY_N
-V 64,108,CONT_BODY_N
-V 64,112,CONT_BODY_N
-V 64,116,CONT_BODY_N
-V 64,120,CONT_BODY_N
-V 64,90,CONT_BODY_N
-V 64,82,CONT_BODY_N
-V 70,114,CONT_DIF_P
-V 70,82,CONT_DIF_P
-V 70,78,CONT_DIF_P
-V 70,110,CONT_DIF_P
-V 70,98,CONT_DIF_P
-V 70,58,CONT_DIF_P
-V 70,70,CONT_DIF_P
-V 70,62,CONT_DIF_P
-V 70,94,CONT_DIF_P
-V 70,106,CONT_DIF_P
-V 70,86,CONT_DIF_P
-V 76,98,CONT_DIF_P
-V 76,106,CONT_DIF_P
-V 76,66,CONT_DIF_P
-V 76,110,CONT_DIF_P
-V 76,82,CONT_DIF_P
-V 76,58,CONT_DIF_P
-V 76,102,CONT_DIF_P
-V 76,94,CONT_DIF_P
-V 82,62,CONT_DIF_P
-V 76,70,CONT_DIF_P
-V 76,78,CONT_DIF_P
-V 76,90,CONT_DIF_P
-V 76,86,CONT_DIF_P
-V 76,114,CONT_DIF_P
-V 76,74,CONT_DIF_P
-V 76,62,CONT_DIF_P
-V 82,78,CONT_DIF_P
-V 82,102,CONT_DIF_P
-V 82,90,CONT_DIF_P
-V 82,58,CONT_DIF_P
-V 82,82,CONT_DIF_P
-V 82,86,CONT_DIF_P
-V 82,114,CONT_DIF_P
-V 82,74,CONT_DIF_P
-V 88,82,CONT_DIF_P
-V 88,114,CONT_DIF_P
-V 88,86,CONT_DIF_P
-V 82,106,CONT_DIF_P
-V 82,94,CONT_DIF_P
-V 82,98,CONT_DIF_P
-V 82,66,CONT_DIF_P
-V 82,70,CONT_DIF_P
-V 100,94,CONT_DIF_P
-V 88,62,CONT_DIF_P
-V 88,70,CONT_DIF_P
-V 82,110,CONT_DIF_P
-V 88,94,CONT_DIF_P
-V 88,98,CONT_DIF_P
-V 88,110,CONT_DIF_P
-V 88,78,CONT_DIF_P
-V 100,78,CONT_DIF_P
-V 100,82,CONT_DIF_P
-V 100,114,CONT_DIF_P
-V 88,106,CONT_DIF_P
-V 100,62,CONT_DIF_P
-V 100,58,CONT_DIF_P
-V 100,70,CONT_DIF_P
-V 100,98,CONT_DIF_P
-V 112,58,CONT_DIF_P
-V 112,62,CONT_DIF_P
-V 112,86,CONT_DIF_P
-V 88,58,CONT_DIF_P
-V 112,82,CONT_DIF_P
-V 112,94,CONT_DIF_P
-V 100,106,CONT_DIF_P
-V 100,110,CONT_DIF_P
-V 94,102,CONT_DIF_P
-V 94,78,CONT_DIF_P
-V 94,90,CONT_DIF_P
-V 100,86,CONT_DIF_P
-V 112,110,CONT_DIF_P
-V 112,106,CONT_DIF_P
-V 112,98,CONT_DIF_P
-V 112,70,CONT_DIF_P
-V 94,86,CONT_DIF_P
-V 94,114,CONT_DIF_P
-V 94,74,CONT_DIF_P
-V 112,114,CONT_DIF_P
-V 94,94,CONT_DIF_P
-V 94,98,CONT_DIF_P
-V 94,66,CONT_DIF_P
-V 94,70,CONT_DIF_P
-V 106,70,CONT_DIF_P
-V 106,102,CONT_DIF_P
-V 106,78,CONT_DIF_P
-V 112,78,CONT_DIF_P
-V 94,106,CONT_DIF_P
-V 94,110,CONT_DIF_P
-V 94,58,CONT_DIF_P
-V 94,82,CONT_DIF_P
-V 106,86,CONT_DIF_P
-V 106,114,CONT_DIF_P
-V 106,74,CONT_DIF_P
-V 94,62,CONT_DIF_P
-V 106,62,CONT_DIF_P
-V 106,94,CONT_DIF_P
-V 106,98,CONT_DIF_P
-V 106,66,CONT_DIF_P
-V 106,90,CONT_DIF_P
-V 106,106,CONT_DIF_P
-V 106,110,CONT_DIF_P
-V 106,58,CONT_DIF_P
-V 106,82,CONT_DIF_P
-V 94,12,CONT_DIF_N
-V 94,7,CONT_DIF_N
-V 76,29,CONT_DIF_N
-V 70,11,CONT_DIF_N
-V 70,15,CONT_DIF_N
-V 70,19,CONT_DIF_N
-V 70,27,CONT_DIF_N
-V 70,31,CONT_DIF_N
-V 70,7,CONT_DIF_N
-V 106,12,CONT_DIF_N
-V 82,21,CONT_DIF_N
-V 106,7,CONT_DIF_N
-V 76,21,CONT_DIF_N
-V 76,25,CONT_DIF_N
-V 76,9,CONT_DIF_N
-V 76,13,CONT_DIF_N
-V 76,17,CONT_DIF_N
-V 76,33,CONT_DIF_N
-V 88,19,CONT_DIF_N
-V 88,15,CONT_DIF_N
-V 88,11,CONT_DIF_N
-V 82,33,CONT_DIF_N
-V 82,29,CONT_DIF_N
-V 82,9,CONT_DIF_N
-V 82,13,CONT_DIF_N
-V 82,17,CONT_DIF_N
-V 112,27,CONT_DIF_N
-V 112,19,CONT_DIF_N
-V 100,19,CONT_DIF_N
-V 82,25,CONT_DIF_N
-V 100,11,CONT_DIF_N
-V 100,15,CONT_DIF_N
-V 88,31,CONT_DIF_N
-V 88,27,CONT_DIF_N
-V 94,25,CONT_DIF_N
-V 94,21,CONT_DIF_N
-V 94,33,CONT_DIF_N
-V 88,7,CONT_DIF_N
-V 112,15,CONT_DIF_N
-V 112,11,CONT_DIF_N
-V 112,7,CONT_DIF_N
-V 112,31,CONT_DIF_N
-V 106,21,CONT_DIF_N
-V 94,29,CONT_DIF_N
-V 100,28,CONT_DIF_N
-V 100,33,CONT_DIF_N
-V 106,25,CONT_DIF_N
-V 100,7,CONT_DIF_N
-V 106,33,CONT_DIF_N
-V 106,29,CONT_DIF_N
-V 143,16,CONT_VIA
-V 77,277,CONT_DIF_N
-V 77,261,CONT_DIF_N
-V 77,257,CONT_DIF_N
-V 77,273,CONT_DIF_N
-V 77,269,CONT_DIF_N
-V 77,253,CONT_DIF_N
-V 77,265,CONT_VIA
-V 77,249,CONT_VIA
-V 77,281,CONT_VIA
-V 65,249,CONT_VIA
-V 65,253,CONT_DIF_N
-V 65,269,CONT_DIF_N
-V 65,273,CONT_DIF_N
-V 65,265,CONT_DIF_N
-V 65,281,CONT_DIF_N
-V 65,257,CONT_DIF_N
-V 65,277,CONT_VIA
-V 65,261,CONT_VIA
-V 77,287,CONT_BODY_P
-V 65,287,CONT_BODY_P
-V 56,136,CONT_BODY_N
-V 67,136,CONT_BODY_N
-V 61,136,CONT_BODY_N
-V 75,136,CONT_BODY_N
-V 71,131,CONT_POLY
-V 64,136,CONT_VIA
-V 59,250,CONT_DIF_N
-V 59,274,CONT_DIF_N
-V 59,278,CONT_DIF_N
-V 59,254,CONT_DIF_N
-V 59,258,CONT_DIF_N
-V 59,262,CONT_DIF_N
-V 59,266,CONT_DIF_N
-V 59,270,CONT_DIF_N
-V 71,258,CONT_DIF_N
-V 71,262,CONT_DIF_N
-V 71,254,CONT_DIF_N
-V 71,250,CONT_DIF_N
-V 71,278,CONT_DIF_N
-V 71,266,CONT_DIF_N
-V 71,270,CONT_DIF_N
-V 71,274,CONT_DIF_N
-V 65,143,CONT_DIF_P
-V 59,147,CONT_DIF_P
-V 65,147,CONT_DIF_P
-V 59,151,CONT_DIF_P
-V 59,143,CONT_DIF_P
-V 71,143,CONT_DIF_P
-V 77,143,CONT_DIF_P
-V 71,147,CONT_DIF_P
-V 77,147,CONT_DIF_P
-V 71,151,CONT_DIF_P
-V 65,155,CONT_DIF_P
-V 59,155,CONT_DIF_P
-V 59,195,CONT_DIF_P
-V 59,179,CONT_DIF_P
-V 65,179,CONT_DIF_P
-V 59,183,CONT_DIF_P
-V 65,183,CONT_DIF_P
-V 59,187,CONT_DIF_P
-V 59,191,CONT_DIF_P
-V 65,191,CONT_DIF_P
-V 65,195,CONT_DIF_P
-V 59,163,CONT_DIF_P
-V 59,159,CONT_DIF_P
-V 65,159,CONT_DIF_P
-V 59,175,CONT_DIF_P
-V 59,171,CONT_DIF_P
-V 59,167,CONT_DIF_P
-V 65,167,CONT_DIF_P
-V 65,171,CONT_DIF_P
-V 71,155,CONT_DIF_P
-V 77,155,CONT_DIF_P
-V 77,195,CONT_DIF_P
-V 71,183,CONT_DIF_P
-V 71,187,CONT_DIF_P
-V 71,191,CONT_DIF_P
-V 77,191,CONT_DIF_P
-V 71,195,CONT_DIF_P
-V 71,175,CONT_DIF_P
-V 71,171,CONT_DIF_P
-V 71,179,CONT_DIF_P
-V 77,179,CONT_DIF_P
-V 77,183,CONT_DIF_P
-V 71,163,CONT_DIF_P
-V 71,159,CONT_DIF_P
-V 77,159,CONT_DIF_P
-V 77,171,CONT_DIF_P
-V 77,167,CONT_DIF_P
-V 71,167,CONT_DIF_P
-V 65,151,CONT_VIA
-V 77,151,CONT_VIA
-V 65,175,CONT_VIA
-V 65,187,CONT_VIA
-V 65,163,CONT_VIA
-V 77,187,CONT_VIA
-V 77,175,CONT_VIA
-V 77,163,CONT_VIA
-V 59,199,CONT_DIF_P
-V 71,199,CONT_DIF_P
-V 65,199,CONT_VIA
-V 77,199,CONT_VIA
-V 59,203,CONT_DIF_P
-V 71,203,CONT_DIF_P
-V 65,203,CONT_DIF_P
-V 77,203,CONT_DIF_P
-V 65,207,CONT_DIF_P
-V 77,207,CONT_DIF_P
-V 71,207,CONT_DIF_P
-V 59,207,CONT_DIF_P
-V 59,211,CONT_DIF_P
-V 71,211,CONT_DIF_P
-V 77,211,CONT_VIA
-V 65,211,CONT_VIA
-V 59,215,CONT_DIF_P
-V 65,215,CONT_DIF_P
-V 71,215,CONT_DIF_P
-V 77,215,CONT_DIF_P
-V 65,243,CONT_BODY_P
-V 77,243,CONT_BODY_P
-V 76,238,CONT_POLY
-V 65,238,CONT_VIA
-V 76,232,CONT_VIA
-V 77,225,CONT_BODY_N
-V 65,225,CONT_BODY_N
-V 77,219,CONT_DIF_P
-V 71,219,CONT_DIF_P
-V 65,219,CONT_DIF_P
-V 59,219,CONT_DIF_P
-V 125,277,CONT_DIF_N
-V 125,261,CONT_DIF_N
-V 125,257,CONT_DIF_N
-V 125,273,CONT_DIF_N
-V 125,269,CONT_DIF_N
-V 125,253,CONT_DIF_N
-V 125,265,CONT_VIA
-V 125,249,CONT_VIA
-V 125,281,CONT_VIA
-V 113,249,CONT_VIA
-V 113,253,CONT_DIF_N
-V 113,269,CONT_DIF_N
-V 113,273,CONT_DIF_N
-V 113,265,CONT_DIF_N
-V 113,281,CONT_DIF_N
-V 113,257,CONT_DIF_N
-V 113,277,CONT_VIA
-V 113,261,CONT_VIA
-V 125,287,CONT_BODY_P
-V 113,287,CONT_BODY_P
-V 104,136,CONT_BODY_N
-V 115,136,CONT_BODY_N
-V 109,136,CONT_BODY_N
-V 123,136,CONT_BODY_N
-V 119,131,CONT_POLY
-V 112,136,CONT_VIA
-V 107,250,CONT_DIF_N
-V 107,274,CONT_DIF_N
-V 107,278,CONT_DIF_N
-V 107,254,CONT_DIF_N
-V 107,258,CONT_DIF_N
-V 107,262,CONT_DIF_N
-V 107,266,CONT_DIF_N
-V 107,270,CONT_DIF_N
-V 119,258,CONT_DIF_N
-V 119,262,CONT_DIF_N
-V 119,254,CONT_DIF_N
-V 119,250,CONT_DIF_N
-V 119,278,CONT_DIF_N
-V 119,266,CONT_DIF_N
-V 119,270,CONT_DIF_N
-V 119,274,CONT_DIF_N
-V 113,143,CONT_DIF_P
-V 107,147,CONT_DIF_P
-V 113,147,CONT_DIF_P
-V 107,151,CONT_DIF_P
-V 107,143,CONT_DIF_P
-V 119,143,CONT_DIF_P
-V 125,143,CONT_DIF_P
-V 119,147,CONT_DIF_P
-V 125,147,CONT_DIF_P
-V 119,151,CONT_DIF_P
-V 113,155,CONT_DIF_P
-V 107,155,CONT_DIF_P
-V 107,195,CONT_DIF_P
-V 107,179,CONT_DIF_P
-V 113,179,CONT_DIF_P
-V 107,183,CONT_DIF_P
-V 113,183,CONT_DIF_P
-V 107,187,CONT_DIF_P
-V 107,191,CONT_DIF_P
-V 113,191,CONT_DIF_P
-V 113,195,CONT_DIF_P
-V 107,163,CONT_DIF_P
-V 107,159,CONT_DIF_P
-V 113,159,CONT_DIF_P
-V 107,175,CONT_DIF_P
-V 107,171,CONT_DIF_P
-V 107,167,CONT_DIF_P
-V 113,167,CONT_DIF_P
-V 113,171,CONT_DIF_P
-V 119,155,CONT_DIF_P
-V 125,155,CONT_DIF_P
-V 125,195,CONT_DIF_P
-V 119,183,CONT_DIF_P
-V 119,187,CONT_DIF_P
-V 119,191,CONT_DIF_P
-V 125,191,CONT_DIF_P
-V 119,195,CONT_DIF_P
-V 119,175,CONT_DIF_P
-V 119,171,CONT_DIF_P
-V 119,179,CONT_DIF_P
-V 125,179,CONT_DIF_P
-V 125,183,CONT_DIF_P
-V 119,163,CONT_DIF_P
-V 119,159,CONT_DIF_P
-V 125,159,CONT_DIF_P
-V 125,171,CONT_DIF_P
-V 125,167,CONT_DIF_P
-V 119,167,CONT_DIF_P
-V 113,151,CONT_VIA
-V 125,151,CONT_VIA
-V 113,175,CONT_VIA
-V 113,187,CONT_VIA
-V 113,163,CONT_VIA
-V 125,187,CONT_VIA
-V 125,175,CONT_VIA
-V 125,163,CONT_VIA
-V 107,199,CONT_DIF_P
-V 119,199,CONT_DIF_P
-V 113,199,CONT_VIA
-V 125,199,CONT_VIA
-V 107,203,CONT_DIF_P
-V 119,203,CONT_DIF_P
-V 113,203,CONT_DIF_P
-V 125,203,CONT_DIF_P
-V 113,207,CONT_DIF_P
-V 125,207,CONT_DIF_P
-V 119,207,CONT_DIF_P
-V 107,207,CONT_DIF_P
-V 107,211,CONT_DIF_P
-V 119,211,CONT_DIF_P
-V 125,211,CONT_VIA
-V 113,211,CONT_VIA
-V 107,215,CONT_DIF_P
-V 113,215,CONT_DIF_P
-V 119,215,CONT_DIF_P
-V 125,215,CONT_DIF_P
-V 113,243,CONT_BODY_P
-V 125,243,CONT_BODY_P
-V 124,238,CONT_POLY
-V 113,238,CONT_VIA
-V 124,232,CONT_VIA
-V 125,225,CONT_BODY_N
-V 113,225,CONT_BODY_N
-V 125,219,CONT_DIF_P
-V 119,219,CONT_DIF_P
-V 113,219,CONT_DIF_P
-V 107,219,CONT_DIF_P
-V 101,277,CONT_DIF_N
-V 101,261,CONT_DIF_N
-V 101,257,CONT_DIF_N
-V 101,273,CONT_DIF_N
-V 101,269,CONT_DIF_N
-V 101,253,CONT_DIF_N
-V 101,265,CONT_VIA
-V 101,249,CONT_VIA
-V 101,281,CONT_VIA
-V 89,249,CONT_VIA
-V 89,253,CONT_DIF_N
-V 89,269,CONT_DIF_N
-V 89,273,CONT_DIF_N
-V 89,265,CONT_DIF_N
-V 89,281,CONT_DIF_N
-V 89,257,CONT_DIF_N
-V 89,277,CONT_VIA
-V 89,261,CONT_VIA
-V 101,287,CONT_BODY_P
-V 89,287,CONT_BODY_P
-V 80,136,CONT_BODY_N
-V 91,136,CONT_BODY_N
-V 85,136,CONT_BODY_N
-V 99,136,CONT_BODY_N
-V 95,131,CONT_POLY
-V 88,136,CONT_VIA
-V 83,250,CONT_DIF_N
-V 83,274,CONT_DIF_N
-V 83,278,CONT_DIF_N
-V 83,254,CONT_DIF_N
-V 83,258,CONT_DIF_N
-V 83,262,CONT_DIF_N
-V 83,266,CONT_DIF_N
-V 83,270,CONT_DIF_N
-V 95,258,CONT_DIF_N
-V 95,262,CONT_DIF_N
-V 95,254,CONT_DIF_N
-V 95,250,CONT_DIF_N
-V 95,278,CONT_DIF_N
-V 95,266,CONT_DIF_N
-V 95,270,CONT_DIF_N
-V 95,274,CONT_DIF_N
-V 89,143,CONT_DIF_P
-V 83,147,CONT_DIF_P
-V 89,147,CONT_DIF_P
-V 83,151,CONT_DIF_P
-V 83,143,CONT_DIF_P
-V 95,143,CONT_DIF_P
-V 101,143,CONT_DIF_P
-V 95,147,CONT_DIF_P
-V 101,147,CONT_DIF_P
-V 95,151,CONT_DIF_P
-V 89,155,CONT_DIF_P
-V 83,155,CONT_DIF_P
-V 83,195,CONT_DIF_P
-V 83,179,CONT_DIF_P
-V 89,179,CONT_DIF_P
-V 83,183,CONT_DIF_P
-V 89,183,CONT_DIF_P
-V 83,187,CONT_DIF_P
-V 83,191,CONT_DIF_P
-V 89,191,CONT_DIF_P
-V 89,195,CONT_DIF_P
-V 83,163,CONT_DIF_P
-V 83,159,CONT_DIF_P
-V 89,159,CONT_DIF_P
-V 83,175,CONT_DIF_P
-V 83,171,CONT_DIF_P
-V 83,167,CONT_DIF_P
-V 89,167,CONT_DIF_P
-V 89,171,CONT_DIF_P
-V 95,155,CONT_DIF_P
-V 101,155,CONT_DIF_P
-V 101,195,CONT_DIF_P
-V 95,183,CONT_DIF_P
-V 95,187,CONT_DIF_P
-V 95,191,CONT_DIF_P
-V 101,191,CONT_DIF_P
-V 95,195,CONT_DIF_P
-V 95,175,CONT_DIF_P
-V 95,171,CONT_DIF_P
-V 95,179,CONT_DIF_P
-V 101,179,CONT_DIF_P
-V 101,183,CONT_DIF_P
-V 95,163,CONT_DIF_P
-V 95,159,CONT_DIF_P
-V 101,159,CONT_DIF_P
-V 101,171,CONT_DIF_P
-V 101,167,CONT_DIF_P
-V 95,167,CONT_DIF_P
-V 89,151,CONT_VIA
-V 101,151,CONT_VIA
-V 89,175,CONT_VIA
-V 89,187,CONT_VIA
-V 89,163,CONT_VIA
-V 101,187,CONT_VIA
-V 101,175,CONT_VIA
-V 101,163,CONT_VIA
-V 83,199,CONT_DIF_P
-V 95,199,CONT_DIF_P
-V 89,199,CONT_VIA
-V 101,199,CONT_VIA
-V 83,203,CONT_DIF_P
-V 95,203,CONT_DIF_P
-V 89,203,CONT_DIF_P
-V 101,203,CONT_DIF_P
-V 89,207,CONT_DIF_P
-V 101,207,CONT_DIF_P
-V 95,207,CONT_DIF_P
-V 83,207,CONT_DIF_P
-V 83,211,CONT_DIF_P
-V 95,211,CONT_DIF_P
-V 101,211,CONT_VIA
-V 89,211,CONT_VIA
-V 83,215,CONT_DIF_P
-V 89,215,CONT_DIF_P
-V 95,215,CONT_DIF_P
-V 101,215,CONT_DIF_P
-V 89,243,CONT_BODY_P
-V 101,243,CONT_BODY_P
-V 100,238,CONT_POLY
-V 89,238,CONT_VIA
-V 100,232,CONT_VIA
-V 101,225,CONT_BODY_N
-V 89,225,CONT_BODY_N
-V 101,219,CONT_DIF_P
-V 95,219,CONT_DIF_P
-V 89,219,CONT_DIF_P
-V 83,219,CONT_DIF_P
-EOF
diff --git a/alliance/share/cells/padlib/palvdde_sp.ap b/alliance/share/cells/padlib/palvdde_sp.ap
deleted file mode 100644
index f1e2af8c..00000000
--- a/alliance/share/cells/padlib/palvdde_sp.ap
+++ /dev/null
@@ -1,140 +0,0 @@
-V ALLIANCE : 3
-H palvdde_sp,P,11/ 9/95
-A 0,-7,172,356
-C 172,168,120,vdde,1,EAST,ALU2
-C 0,168,120,vdde,0,WEST,ALU2
-C 172,84,40,vddi,1,EAST,ALU2
-C 0,84,40,vddi,0,WEST,ALU2
-C 172,40,40,vssi,1,EAST,ALU2
-C 0,40,40,vssi,0,WEST,ALU2
-C 172,6,12,ck,1,EAST,ALU2
-C 0,6,12,ck,0,WEST,ALU2
-C 172,296,120,vsse,1,EAST,ALU2
-C 0,296,120,vsse,0,WEST,ALU2
-S 0,40,172,40,40,vssi,RIGHT,ALU2
-S 0,84,172,84,40,vddi,RIGHT,ALU2
-S 0,168,172,168,120,vdde,RIGHT,ALU2
-S 0,6,172,6,12,ck,RIGHT,ALU2
-S 0,296,172,296,120,vsse,RIGHT,ALU2
-S 86,108,86,356,100,*,UP,ALU1
-V 42,110,CONT_VIA
-V 62,110,CONT_VIA
-V 82,110,CONT_VIA
-V 102,110,CONT_VIA
-V 122,110,CONT_VIA
-V 132,115,CONT_VIA
-V 132,125,CONT_VIA
-V 132,145,CONT_VIA
-V 132,175,CONT_VIA
-V 132,185,CONT_VIA
-V 132,195,CONT_VIA
-V 122,150,CONT_VIA
-V 122,180,CONT_VIA
-V 122,190,CONT_VIA
-V 122,120,CONT_VIA
-V 132,135,CONT_VIA
-V 112,155,CONT_VIA
-V 112,145,CONT_VIA
-V 132,155,CONT_VIA
-V 132,165,CONT_VIA
-V 112,125,CONT_VIA
-V 112,115,CONT_VIA
-V 122,130,CONT_VIA
-V 122,140,CONT_VIA
-V 92,115,CONT_VIA
-V 112,135,CONT_VIA
-V 122,160,CONT_VIA
-V 122,170,CONT_VIA
-V 112,195,CONT_VIA
-V 112,185,CONT_VIA
-V 112,175,CONT_VIA
-V 112,165,CONT_VIA
-V 92,195,CONT_VIA
-V 92,185,CONT_VIA
-V 92,175,CONT_VIA
-V 102,180,CONT_VIA
-V 102,190,CONT_VIA
-V 102,120,CONT_VIA
-V 92,125,CONT_VIA
-V 82,190,CONT_VIA
-V 82,180,CONT_VIA
-V 102,130,CONT_VIA
-V 102,140,CONT_VIA
-V 102,150,CONT_VIA
-V 102,160,CONT_VIA
-V 102,170,CONT_VIA
-V 82,130,CONT_VIA
-V 72,115,CONT_VIA
-V 72,125,CONT_VIA
-V 92,165,CONT_VIA
-V 92,155,CONT_VIA
-V 92,145,CONT_VIA
-V 92,135,CONT_VIA
-V 82,120,CONT_VIA
-V 72,165,CONT_VIA
-V 72,175,CONT_VIA
-V 72,185,CONT_VIA
-V 72,195,CONT_VIA
-V 82,170,CONT_VIA
-V 82,160,CONT_VIA
-V 82,150,CONT_VIA
-V 82,140,CONT_VIA
-V 52,125,CONT_VIA
-V 62,120,CONT_VIA
-V 62,190,CONT_VIA
-V 62,180,CONT_VIA
-V 72,135,CONT_VIA
-V 72,145,CONT_VIA
-V 72,155,CONT_VIA
-V 52,185,CONT_VIA
-V 52,195,CONT_VIA
-V 62,170,CONT_VIA
-V 62,160,CONT_VIA
-V 62,150,CONT_VIA
-V 62,140,CONT_VIA
-V 62,130,CONT_VIA
-V 52,115,CONT_VIA
-V 42,190,CONT_VIA
-V 42,120,CONT_VIA
-V 52,135,CONT_VIA
-V 52,145,CONT_VIA
-V 52,155,CONT_VIA
-V 52,165,CONT_VIA
-V 52,175,CONT_VIA
-V 42,130,CONT_VIA
-V 42,140,CONT_VIA
-V 42,150,CONT_VIA
-V 42,160,CONT_VIA
-V 42,170,CONT_VIA
-V 42,180,CONT_VIA
-V 122,200,CONT_VIA
-V 132,205,CONT_VIA
-V 132,215,CONT_VIA
-V 132,225,CONT_VIA
-V 112,225,CONT_VIA
-V 112,215,CONT_VIA
-V 92,205,CONT_VIA
-V 82,200,CONT_VIA
-V 102,200,CONT_VIA
-V 112,205,CONT_VIA
-V 122,210,CONT_VIA
-V 122,220,CONT_VIA
-V 102,220,CONT_VIA
-V 82,220,CONT_VIA
-V 82,210,CONT_VIA
-V 72,205,CONT_VIA
-V 72,215,CONT_VIA
-V 72,225,CONT_VIA
-V 92,225,CONT_VIA
-V 92,215,CONT_VIA
-V 62,220,CONT_VIA
-V 62,210,CONT_VIA
-V 52,205,CONT_VIA
-V 52,215,CONT_VIA
-V 52,225,CONT_VIA
-V 62,200,CONT_VIA
-V 102,210,CONT_VIA
-V 42,200,CONT_VIA
-V 42,210,CONT_VIA
-V 42,220,CONT_VIA
-EOF
diff --git a/alliance/share/cells/padlib/palvddeck_sp.ap b/alliance/share/cells/padlib/palvddeck_sp.ap
deleted file mode 100644
index 354c10e5..00000000
--- a/alliance/share/cells/padlib/palvddeck_sp.ap
+++ /dev/null
@@ -1,290 +0,0 @@
-V ALLIANCE : 6
-H palvddeck_sp,P,13/10/2000,100
-A 0,-700,17200,35600
-C 0,29600,12000,vsse,0,WEST,ALU2
-C 17200,29600,12000,vsse,1,EAST,ALU2
-C 0,600,1200,ck,0,WEST,ALU2
-C 17200,600,1200,ck,1,EAST,ALU2
-C 0,4000,4000,vssi,0,WEST,ALU2
-C 17200,4000,4000,vssi,1,EAST,ALU2
-C 0,8400,4000,vddi,0,WEST,ALU2
-C 17200,8400,4000,vddi,1,EAST,ALU2
-C 0,16800,12000,vdde,0,WEST,ALU2
-C 17200,16800,12000,vdde,1,EAST,ALU2
-C 6700,-700,200,cko,1,SOUTH,ALU2
-C 6700,-700,200,cko,0,SOUTH,ALU1
-C 7900,-700,200,cko,3,SOUTH,ALU2
-C 7900,-700,200,cko,2,SOUTH,ALU1
-C 9100,-700,200,cko,5,SOUTH,ALU2
-C 9100,-700,200,cko,4,SOUTH,ALU1
-S 8600,10900,8600,35600,10000,*,UP,ALU1
-S 8500,2100,8500,4900,200,*,UP,ALU1
-S 7300,2200,7300,4500,200,*,UP,ALU1
-S 4300,2100,6100,2100,300,*,RIGHT,ALU1
-S 4300,2000,4300,5100,200,*,UP,ALU1
-S 6100,10400,9700,10400,200,*,RIGHT,ALU1
-S 6700,6600,9100,6600,200,*,RIGHT,ALU1
-S 6200,6100,7200,6100,200,*,RIGHT,ALU1
-S 6200,6100,6200,6900,200,*,UP,ALU1
-S 4300,6100,4300,10400,300,*,UP,ALU1
-S 6200,5000,8500,5000,200,*,RIGHT,ALU1
-S 3800,100,3800,5600,200,*,UP,ALU1
-S 3800,5600,5200,5600,200,*,RIGHT,ALU1
-S 6200,4400,6200,5000,200,*,UP,ALU1
-S 9700,6000,9700,10400,200,*,UP,ALU1
-S 4200,6100,5000,6100,200,*,RIGHT,ALU1
-S 0,29600,17200,29600,12000,vsse,RIGHT,ALU2
-S 5700,4900,5700,6200,200,*,UP,ALU1
-S 5500,2800,5500,5100,200,*,UP,ALU1
-S 4100,8500,9900,8500,5200,*,RIGHT,NWELL
-S 5800,5600,7600,5600,200,*,RIGHT,ALU1
-S 6100,6800,6100,10400,200,*,UP,ALU1
-S 7300,7100,7300,10400,200,*,UP,ALU1
-S 8500,7100,8500,10400,200,*,UP,ALU1
-S 6000,10400,9800,10400,300,*,RIGHT,NTIE
-S 6100,10300,6100,11100,300,*,UP,NTIE
-S 9700,6100,9700,10500,300,*,UP,NTIE
-S 7900,6700,7900,9600,200,*,UP,ALU1
-S 6700,6700,6700,9600,200,*,UP,ALU1
-S 9100,6600,9100,9900,300,*,UP,PDIF
-S 8500,6600,8500,9900,200,*,UP,PDIF
-S 7900,6600,7900,9900,200,*,UP,PDIF
-S 7300,6600,7300,9900,200,*,UP,PDIF
-S 6100,6600,6100,9900,300,*,UP,PDIF
-S 6700,6600,6700,9900,200,*,UP,PDIF
-S 6400,6400,6400,10100,100,*,UP,PTRANS
-S 7000,6400,7000,10100,100,*,UP,PTRANS
-S 7600,6400,7600,10100,100,*,UP,PTRANS
-S 8200,6400,8200,10100,100,*,UP,PTRANS
-S 8800,6400,8800,10100,100,*,UP,PTRANS
-S 4200,6100,5000,6100,300,*,RIGHT,NTIE
-S 4300,6000,4300,11000,300,*,UP,NTIE
-S 4900,6600,4900,10400,300,*,UP,PDIF
-S 4900,6800,4900,10400,200,*,UP,ALU1
-S 6100,2000,6100,4500,200,*,UP,ALU1
-S 9700,2000,9700,5100,300,*,UP,PTIE
-S 9700,2000,9700,5100,300,*,UP,ALU1
-S 4200,5000,5000,5000,300,*,RIGHT,PTIE
-S 4200,2100,9800,2100,300,*,RIGHT,PTIE
-S 9700,2000,9700,5100,300,*,UP,PTIE
-S 4300,2000,4300,5100,300,*,UP,PTIE
-S 8500,2600,8500,4500,200,*,UP,NDIF
-S 7300,2600,7300,4400,200,*,UP,NDIF
-S 4900,2600,4900,4400,300,*,UP,NDIF
-S 6100,2600,6100,4400,300,*,UP,NDIF
-S 7900,2600,7900,4400,300,*,UP,NDIF
-S 5500,2600,5500,4500,300,*,UP,NDIF
-S 9100,2600,9100,4500,300,*,UP,NDIF
-S 5500,6600,5500,10500,300,*,UP,PDIF
-S 6700,2600,6700,4500,200,*,UP,NDIF
-S 4900,2000,4900,5100,200,*,UP,ALU1
-S 7600,2400,7600,4700,100,*,UP,NTRANS
-S 8200,2400,8200,4700,100,*,UP,NTRANS
-S 8800,2400,8800,4700,100,*,UP,NTRANS
-S 5200,2400,5200,4700,100,*,UP,NTRANS
-S 6400,2400,6400,4700,100,*,UP,NTRANS
-S 7000,2400,7000,4700,100,*,UP,NTRANS
-S 5200,6400,5200,10700,100,*,UP,PTRANS
-S 5400,6100,7200,6100,300,*,RIGHT,NTIE
-S 8000,6100,9800,6100,300,*,RIGHT,NTIE
-S 8000,5000,9800,5000,300,*,RIGHT,PTIE
-S 5400,5000,7200,5000,300,*,RIGHT,PTIE
-S 6400,6400,8800,6400,100,*,RIGHT,POLY
-S 5200,4700,5200,6400,100,*,UP,POLY
-S 6400,4700,8800,4700,100,*,RIGHT,POLY
-S 7600,4700,7600,6400,500,*,UP,POLY
-S 5500,6100,5500,10400,200,*,UP,ALU1
-S 0,600,17200,600,1200,ck,RIGHT,ALU2
-S 6700,-700,6700,4400,200,*,UP,ALU1
-S 7900,-700,7900,4400,200,*,UP,ALU1
-S 9100,-700,9100,9600,200,*,UP,ALU1
-S 6700,1600,9100,1600,200,*,RIGHT,ALU1
-S 0,16800,17200,16800,12000,vdde,RIGHT,ALU2
-S 0,4000,17200,4000,4000,vssi,RIGHT,ALU2
-S 0,8400,17200,8400,4000,vddi,RIGHT,ALU2
-B 8600,16800,10000,12000,CONT_VIA,*
-B 3800,5600,200,200,CONT_TURN1,*
-V 4300,10300,CONT_BODY_N,*
-V 4300,9700,CONT_VIA,*
-V 4300,9300,CONT_BODY_N,*
-V 4300,8900,CONT_BODY_N,*
-V 4300,8500,CONT_VIA,*
-V 4300,8100,CONT_BODY_N,*
-V 4300,7700,CONT_BODY_N,*
-V 5200,5600,CONT_POLY,*
-V 4300,7300,CONT_BODY_N,*
-V 4300,6900,CONT_VIA,*
-V 4300,6500,CONT_BODY_N,*
-V 4300,6100,CONT_BODY_N,*
-V 4900,6100,CONT_BODY_N,*
-V 6700,6100,CONT_BODY_N,*
-V 6200,6100,CONT_BODY_N,*
-V 7100,6100,CONT_BODY_N,*
-V 7600,5600,CONT_POLY,*
-V 9700,9600,CONT_VIA,*
-V 9700,7000,CONT_VIA,*
-V 9700,6500,CONT_BODY_N,*
-V 9700,6100,CONT_BODY_N,*
-V 9700,7600,CONT_BODY_N,*
-V 9700,8000,CONT_BODY_N,*
-V 9700,8400,CONT_BODY_N,*
-V 9700,8800,CONT_BODY_N,*
-V 9700,9200,CONT_BODY_N,*
-V 9700,10000,CONT_BODY_N,*
-V 9700,10400,CONT_BODY_N,*
-V 9300,10400,CONT_BODY_N,*
-V 8900,10400,CONT_BODY_N,*
-V 8500,10400,CONT_BODY_N,*
-V 8100,10400,CONT_BODY_N,*
-V 7700,10400,CONT_BODY_N,*
-V 7300,10400,CONT_BODY_N,*
-V 6900,10400,CONT_BODY_N,*
-V 6500,10400,CONT_BODY_N,*
-V 6100,10400,CONT_BODY_N,*
-V 8500,7100,CONT_DIF_P,*
-V 8500,9600,CONT_DIF_P,*
-V 8500,9200,CONT_DIF_P,*
-V 8500,8800,CONT_DIF_P,*
-V 8500,8000,CONT_DIF_P,*
-V 8500,7600,CONT_DIF_P,*
-V 8500,10000,CONT_VIA,*
-V 8500,8400,CONT_VIA,*
-V 7300,7100,CONT_DIF_P,*
-V 7300,7600,CONT_DIF_P,*
-V 7300,8000,CONT_DIF_P,*
-V 7300,8800,CONT_DIF_P,*
-V 7300,9200,CONT_DIF_P,*
-V 7300,9600,CONT_DIF_P,*
-V 7300,8400,CONT_VIA,*
-V 7300,10000,CONT_VIA,*
-V 4900,6800,CONT_DIF_P,*
-V 4900,10400,CONT_DIF_P,*
-V 4900,9600,CONT_DIF_P,*
-V 4900,9200,CONT_DIF_P,*
-V 4900,8800,CONT_DIF_P,*
-V 4900,8000,CONT_DIF_P,*
-V 4900,7600,CONT_DIF_P,*
-V 4900,7200,CONT_VIA,*
-V 4900,10000,CONT_VIA,*
-V 4900,8400,CONT_VIA,*
-V 6100,7200,CONT_VIA,*
-V 6100,8400,CONT_VIA,*
-V 6100,10000,CONT_VIA,*
-V 6100,6800,CONT_DIF_P,*
-V 6100,7600,CONT_DIF_P,*
-V 6100,8000,CONT_DIF_P,*
-V 6100,8800,CONT_DIF_P,*
-V 6100,9200,CONT_DIF_P,*
-V 6100,9600,CONT_DIF_P,*
-V 6200,5000,CONT_BODY_P,*
-V 6600,5000,CONT_VIA,*
-V 8100,5000,CONT_BODY_P,*
-V 7100,5000,CONT_BODY_P,*
-V 9700,2500,CONT_BODY_P,*
-V 9700,3300,CONT_BODY_P,*
-V 9700,3700,CONT_BODY_P,*
-V 9700,4100,CONT_BODY_P,*
-V 9700,5000,CONT_BODY_P,*
-V 9700,2100,CONT_BODY_P,*
-V 9700,4500,CONT_VIA,*
-V 9700,2900,CONT_VIA,*
-V 4300,5000,CONT_BODY_P,*
-V 4300,4500,CONT_VIA,*
-V 4300,4100,CONT_BODY_P,*
-V 4300,3700,CONT_BODY_P,*
-V 4300,3300,CONT_BODY_P,*
-V 4300,2900,CONT_VIA,*
-V 4300,2500,CONT_BODY_P,*
-V 4300,2100,CONT_BODY_P,*
-V 5300,2100,CONT_BODY_P,*
-V 5700,2100,CONT_BODY_P,*
-V 4900,5000,CONT_BODY_P,*
-V 8500,5000,CONT_BODY_P,*
-V 4900,2100,CONT_BODY_P,*
-V 6100,2100,CONT_BODY_P,*
-V 7300,2100,CONT_BODY_P,*
-V 8500,2100,CONT_BODY_P,*
-V 8500,2400,CONT_VIA,*
-V 7300,2400,CONT_VIA,*
-V 6100,2400,CONT_VIA,*
-V 4900,2400,CONT_VIA,*
-V 8500,2800,CONT_DIF_N,*
-V 7300,2800,CONT_DIF_N,*
-V 6100,2800,CONT_DIF_N,*
-V 4900,2800,CONT_DIF_N,*
-V 4900,3200,CONT_DIF_N,*
-V 6100,3200,CONT_DIF_N,*
-V 7300,3200,CONT_DIF_N,*
-V 8500,3200,CONT_DIF_N,*
-V 8500,3600,CONT_DIF_N,*
-V 7300,3600,CONT_DIF_N,*
-V 6100,3600,CONT_DIF_N,*
-V 4900,3600,CONT_DIF_N,*
-V 4900,4400,CONT_DIF_N,*
-V 4900,4000,CONT_VIA,*
-V 8500,4000,CONT_VIA,*
-V 7300,4000,CONT_VIA,*
-V 6100,4000,CONT_VIA,*
-V 8500,4400,CONT_DIF_N,*
-V 6100,4400,CONT_DIF_N,*
-V 7300,4400,CONT_DIF_N,*
-V 9100,3600,CONT_DIF_N,*
-V 9100,4000,CONT_DIF_N,*
-V 9100,4400,CONT_DIF_N,*
-V 9100,2800,CONT_DIF_N,*
-V 7900,3600,CONT_DIF_N,*
-V 7900,3200,CONT_DIF_N,*
-V 7900,4400,CONT_DIF_N,*
-V 7900,4000,CONT_DIF_N,*
-V 6700,4000,CONT_DIF_N,*
-V 6700,4400,CONT_DIF_N,*
-V 6700,2800,CONT_DIF_N,*
-V 6700,3200,CONT_DIF_N,*
-V 6700,3600,CONT_DIF_N,*
-V 9100,3200,CONT_DIF_N,*
-V 7900,2800,CONT_DIF_N,*
-V 5500,4000,CONT_DIF_N,*
-V 5500,4400,CONT_DIF_N,*
-V 5500,2800,CONT_DIF_N,*
-V 5500,3200,CONT_DIF_N,*
-V 5500,3600,CONT_DIF_N,*
-V 9100,9200,CONT_DIF_P,*
-V 9100,9600,CONT_DIF_P,*
-V 9100,6800,CONT_DIF_P,*
-V 9100,7200,CONT_DIF_P,*
-V 9100,7600,CONT_DIF_P,*
-V 9100,8000,CONT_DIF_P,*
-V 7900,8800,CONT_DIF_P,*
-V 7900,8400,CONT_DIF_P,*
-V 9100,8400,CONT_DIF_P,*
-V 9100,8800,CONT_DIF_P,*
-V 7900,7200,CONT_DIF_P,*
-V 7900,6800,CONT_DIF_P,*
-V 7900,9600,CONT_DIF_P,*
-V 7900,9200,CONT_DIF_P,*
-V 6700,6800,CONT_DIF_P,*
-V 6700,7200,CONT_DIF_P,*
-V 6700,7600,CONT_DIF_P,*
-V 6700,8000,CONT_DIF_P,*
-V 6700,8400,CONT_DIF_P,*
-V 6700,8800,CONT_DIF_P,*
-V 7900,8000,CONT_DIF_P,*
-V 7900,7600,CONT_DIF_P,*
-V 6700,9200,CONT_DIF_P,*
-V 6700,9600,CONT_DIF_P,*
-V 5500,10000,CONT_DIF_P,*
-V 5500,10400,CONT_DIF_P,*
-V 5500,6800,CONT_DIF_P,*
-V 5500,7200,CONT_DIF_P,*
-V 5500,7600,CONT_DIF_P,*
-V 5500,8000,CONT_DIF_P,*
-V 5500,8400,CONT_DIF_P,*
-V 5500,8800,CONT_DIF_P,*
-V 5500,9200,CONT_DIF_P,*
-V 5500,9600,CONT_DIF_P,*
-V 3800,200,CONT_VIA,*
-V 3800,1000,CONT_VIA,*
-V 6700,-700,CONT_VIA,*
-V 7900,-700,CONT_VIA,*
-V 9100,-700,CONT_VIA,*
-EOF
diff --git a/alliance/share/cells/padlib/palvddi_sp.ap b/alliance/share/cells/padlib/palvddi_sp.ap
deleted file mode 100644
index c488a147..00000000
--- a/alliance/share/cells/padlib/palvddi_sp.ap
+++ /dev/null
@@ -1,44 +0,0 @@
-V ALLIANCE : 6
-H palvddi_sp,P,13/10/2000,100
-A 0,-700,17200,35600
-C 8600,-700,10000,vddi,0,SOUTH,ALU1
-C 8600,-700,10000,vddi,2,SOUTH,ALU2
-C 17200,16800,12000,vdde,1,EAST,ALU2
-C 0,16800,12000,vdde,0,WEST,ALU2
-C 17200,8400,4000,vddi,4,EAST,ALU2
-C 0,8400,4000,vddi,3,WEST,ALU2
-C 17200,4000,4000,vssi,1,EAST,ALU2
-C 0,4000,4000,vssi,0,WEST,ALU2
-C 17200,600,1200,ck,1,EAST,ALU2
-C 0,600,1200,ck,0,WEST,ALU2
-C 17200,29600,12000,vsse,1,EAST,ALU2
-C 0,29600,12000,vsse,0,WEST,ALU2
-S 0,4000,17200,4000,4000,vssi,RIGHT,ALU2
-S 0,16800,17200,16800,12000,vdde,RIGHT,ALU2
-S 0,8400,17100,8400,4000,vddi,RIGHT,ALU2
-S 0,600,17200,600,1200,ck,RIGHT,ALU2
-S 0,29600,17200,29600,12000,vsse,RIGHT,ALU2
-S 8600,-700,8600,35600,10000,*,UP,ALU1
-V 5700,-400,CONT_VIA,*
-V 5200,-400,CONT_VIA,*
-V 4700,-400,CONT_VIA,*
-V 4200,-400,CONT_VIA,*
-V 3700,-400,CONT_VIA,*
-V 9700,-400,CONT_VIA,*
-V 10200,-400,CONT_VIA,*
-V 7700,-400,CONT_VIA,*
-V 8200,-400,CONT_VIA,*
-V 8700,-400,CONT_VIA,*
-V 9200,-400,CONT_VIA,*
-V 6700,-400,CONT_VIA,*
-V 7200,-400,CONT_VIA,*
-V 6200,-400,CONT_VIA,*
-V 10700,-400,CONT_VIA,*
-V 11200,-400,CONT_VIA,*
-V 11700,-400,CONT_VIA,*
-V 12200,-400,CONT_VIA,*
-V 13200,-400,CONT_VIA,*
-V 12700,-400,CONT_VIA,*
-B 8600,-500,10000,400,CONT_TURN2,*
-B 8600,8400,10000,4000,CONT_VIA,*
-EOF
diff --git a/alliance/share/cells/padlib/palvddick_sp.ap b/alliance/share/cells/padlib/palvddick_sp.ap
deleted file mode 100644
index dba9f897..00000000
--- a/alliance/share/cells/padlib/palvddick_sp.ap
+++ /dev/null
@@ -1,411 +0,0 @@
-V ALLIANCE : 6
-H palvddick_sp,P,13/10/2000,100
-A 0,-700,17200,35600
-C 8600,-700,10000,vddi,0,SOUTH,ALU1
-C 17200,600,1200,ck,1,EAST,ALU2
-C 17200,4000,4000,vssi,1,EAST,ALU2
-C 17200,8400,4000,vddi,4,EAST,ALU2
-C 0,600,1200,ck,0,WEST,ALU2
-C 0,4000,4000,vssi,0,WEST,ALU2
-C 0,8400,4000,vddi,3,WEST,ALU2
-C 0,16800,12000,vdde,0,WEST,ALU2
-C 17200,16800,12000,vdde,1,EAST,ALU2
-C 8600,-700,10000,vddi,1,SOUTH,ALU2
-C 15500,-700,200,cko,3,SOUTH,ALU2
-C 15500,-700,200,cko,2,SOUTH,ALU1
-C 1700,-700,200,cko,1,SOUTH,ALU2
-C 1700,-700,200,cko,0,SOUTH,ALU1
-C 17200,29600,12000,vsse,1,EAST,ALU2
-C 0,29600,12000,vsse,0,WEST,ALU2
-S 0,8400,17200,8400,4000,vddi,RIGHT,ALU2
-S 0,4000,17200,4000,4000,vssi,RIGHT,ALU2
-S 0,16800,17200,16800,12000,vdde,RIGHT,ALU2
-S 15500,-700,15500,1500,200,*,UP,ALU1
-S 0,600,17200,600,1200,ck,RIGHT,ALU2
-S 1700,-700,1700,1600,200,*,DOWN,ALU1
-S 0,29600,17200,29600,12000,vsse,RIGHT,ALU2
-S 8600,-700,8600,35600,10000,*,UP,ALU1
-S 15200,5200,15800,5200,100,*,RIGHT,POLY
-S 14900,7100,15500,7100,100,*,RIGHT,POLY
-S 13600,5700,14100,5700,300,*,RIGHT,PTIE
-S 14300,5200,14300,7100,100,*,DOWN,POLY
-S 14300,5200,14600,5200,100,*,RIGHT,POLY
-S 14200,2100,16800,2100,300,*,LEFT,PTIE
-S 14300,2100,14300,3400,300,*,UP,PTIE
-S 13300,6800,14100,6800,300,*,RIGHT,NTIE
-S 14400,300,14400,3800,200,*,DOWN,ALU1
-S 13600,3300,14300,3300,300,*,LEFT,PTIE
-S 14300,4400,14300,6300,200,*,DOWN,ALU1
-S 14600,3700,14600,3900,100,*,DOWN,POLY
-S 13200,12700,16600,12700,400,*,RIGHT,NWELL
-S 13200,9700,16600,9700,6200,*,RIGHT,NWELL
-S 14300,7100,14300,9400,100,*,UP,PTRANS
-S 14900,7100,14900,12400,100,*,UP,PTRANS
-S 15500,7100,15500,12400,100,*,UP,PTRANS
-S 13400,6700,13400,9800,300,*,UP,NTIE
-S 13300,9700,14100,9700,300,*,RIGHT,NTIE
-S 15200,7300,15200,12200,200,*,DOWN,PDIF
-S 15800,7300,15800,12200,300,*,DOWN,PDIF
-S 14600,7300,14600,12200,300,*,DOWN,PDIF
-S 14000,7300,14000,9200,300,*,DOWN,PDIF
-S 14000,9600,14000,12800,300,*,UP,NTIE
-S 14000,12700,16500,12700,300,*,RIGHT,NTIE
-S 16400,6700,16400,12800,300,*,UP,NTIE
-S 14000,6300,14000,9100,200,*,DOWN,ALU1
-S 15200,6300,15200,11900,200,*,DOWN,ALU1
-S 16700,2100,16700,5800,300,*,DOWN,PTIE
-S 15800,2400,15800,5200,100,*,DOWN,NTRANS
-S 14600,3900,14600,5200,100,*,DOWN,NTRANS
-S 15200,2400,15200,5200,100,*,DOWN,NTRANS
-S 16100,2600,16100,5000,300,*,DOWN,NDIF
-S 14300,4100,14300,5000,300,*,DOWN,NDIF
-S 14900,2600,14900,5000,300,*,DOWN,NDIF
-S 15500,2600,15500,5000,300,*,DOWN,NDIF
-S 13700,3400,13700,5800,300,*,UP,PTIE
-S 14900,2100,14900,5800,200,*,DOWN,ALU1
-S 15500,1500,15500,6300,200,*,DOWN,ALU1
-S 15400,5200,15400,7100,200,*,UP,POLY
-S 14700,6300,15300,6300,300,*,LEFT,POLY
-S 15700,5700,16700,5700,300,*,RIGHT,PTIE
-S 14500,5700,15100,5700,300,*,RIGHT,PTIE
-S 15700,6800,16400,6800,300,*,RIGHT,NTIE
-S 14500,6800,15100,6800,300,*,RIGHT,NTIE
-S 1400,5200,2000,5200,100,*,RIGHT,POLY
-S 1700,7100,2300,7100,100,*,RIGHT,POLY
-S 3100,5700,3600,5700,300,*,RIGHT,PTIE
-S 2900,5200,2900,7100,100,*,UP,POLY
-S 2600,5200,2900,5200,100,*,RIGHT,POLY
-S 400,2100,3000,2100,300,*,LEFT,PTIE
-S 2900,2100,2900,3400,300,*,DOWN,PTIE
-S 3100,6800,3900,6800,300,*,RIGHT,NTIE
-S 2800,300,2800,3800,200,*,UP,ALU1
-S 2900,3300,3600,3300,300,*,LEFT,PTIE
-S 2900,4400,2900,6300,200,*,UP,ALU1
-S 2600,3700,2600,3900,100,*,UP,POLY
-S 600,12700,4000,12700,400,*,RIGHT,NWELL
-S 600,9700,4000,9700,6200,*,RIGHT,NWELL
-S 2900,7100,2900,9400,100,*,DOWN,PTRANS
-S 2300,7100,2300,12400,100,*,DOWN,PTRANS
-S 1700,7100,1700,12400,100,*,DOWN,PTRANS
-S 3800,6700,3800,9800,300,*,DOWN,NTIE
-S 3100,9700,3900,9700,300,*,RIGHT,NTIE
-S 2000,7300,2000,12200,200,*,UP,PDIF
-S 1400,7300,1400,12200,300,*,UP,PDIF
-S 2600,7300,2600,12200,300,*,UP,PDIF
-S 3200,7300,3200,9200,300,*,UP,PDIF
-S 3200,9600,3200,12800,300,*,DOWN,NTIE
-S 700,12700,3200,12700,300,*,RIGHT,NTIE
-S 800,6700,800,12800,300,*,DOWN,NTIE
-S 3200,6300,3200,9100,200,*,UP,ALU1
-S 2000,6300,2000,11900,200,*,UP,ALU1
-S 500,2100,500,5800,300,*,UP,PTIE
-S 1400,2400,1400,5200,100,*,UP,NTRANS
-S 2600,3900,2600,5200,100,*,UP,NTRANS
-S 2000,2400,2000,5200,100,*,UP,NTRANS
-S 1100,2600,1100,5000,300,*,UP,NDIF
-S 2900,4100,2900,5000,300,*,UP,NDIF
-S 2300,2600,2300,5000,300,*,UP,NDIF
-S 1700,2600,1700,5000,300,*,UP,NDIF
-S 3500,3400,3500,5800,300,*,DOWN,PTIE
-S 2300,2100,2300,5800,200,*,UP,ALU1
-S 1700,1500,1700,6300,200,*,UP,ALU1
-S 1800,5200,1800,7100,200,*,DOWN,POLY
-S 1900,6300,2500,6300,300,*,LEFT,POLY
-S 500,5700,1500,5700,300,*,RIGHT,PTIE
-S 2100,5700,2700,5700,300,*,RIGHT,PTIE
-S 800,6800,1500,6800,300,*,RIGHT,NTIE
-S 2100,6800,2700,6800,300,*,RIGHT,NTIE
-S 1700,1600,15700,1600,200,*,RIGHT,ALU2
-S 3200,9600,3200,12800,200,*,UP,ALU1
-S 14000,9600,14000,12800,200,*,DOWN,ALU1
-S 14000,12600,16500,12600,500,*,LEFT,ALU1
-S 700,12600,3200,12600,500,*,LEFT,ALU1
-S 2500,6300,3200,6300,200,*,RIGHT,ALU1
-S 14000,6300,14700,6300,200,*,RIGHT,ALU1
-S 15200,6300,15500,6300,200,*,RIGHT,ALU1
-S 1700,6300,2000,6300,200,*,RIGHT,ALU1
-S 2600,6800,2600,12800,200,*,UP,ALU1
-S 800,2100,800,5800,900,*,UP,ALU1
-S 400,2100,1200,2100,200,*,LEFT,ALU1
-S 14600,6800,14600,12800,200,*,DOWN,ALU1
-S 15800,6800,15800,12800,200,*,DOWN,ALU1
-S 16200,6800,16200,12800,700,*,UP,ALU1
-S 15800,6800,16500,6800,200,*,LEFT,ALU1
-S 1000,6800,1000,12800,700,*,DOWN,ALU1
-S 1400,6800,1400,12800,200,*,UP,ALU1
-S 700,6800,1400,6800,200,*,LEFT,ALU1
-S 16400,2100,16400,5800,900,*,DOWN,ALU1
-S 16000,2100,16800,2100,200,*,RIGHT,ALU1
-S 1500,1600,2100,1600,200,*,LEFT,ALU1
-S 15100,1600,15700,1600,200,*,LEFT,ALU1
-V 5700,-400,CONT_VIA,*
-V 5200,-400,CONT_VIA,*
-V 4700,-400,CONT_VIA,*
-V 4200,-400,CONT_VIA,*
-V 3700,-400,CONT_VIA,*
-V 9700,-400,CONT_VIA,*
-V 10200,-400,CONT_VIA,*
-V 7700,-400,CONT_VIA,*
-V 8200,-400,CONT_VIA,*
-V 8700,-400,CONT_VIA,*
-V 9200,-400,CONT_VIA,*
-V 6700,-400,CONT_VIA,*
-V 7200,-400,CONT_VIA,*
-V 6200,-400,CONT_VIA,*
-V 10700,-400,CONT_VIA,*
-V 11200,-400,CONT_VIA,*
-V 11700,-400,CONT_VIA,*
-V 12200,-400,CONT_VIA,*
-V 13200,-400,CONT_VIA,*
-V 12700,-400,CONT_VIA,*
-B 8600,-500,10000,400,CONT_TURN2,*
-V 1500,1600,CONT_VIA,*
-V 15700,1600,CONT_VIA,*
-V 15500,-700,CONT_VIA,*
-V 1700,-700,CONT_VIA,*
-V 16400,9900,CONT_VIA,*
-V 16400,10300,CONT_BODY_N,*
-V 14700,6300,CONT_POLY,*
-V 16700,5700,CONT_BODY_P,*
-V 16700,5300,CONT_VIA,*
-V 16700,4900,CONT_BODY_P,*
-V 16700,4500,CONT_BODY_P,*
-V 16700,4100,CONT_BODY_P,*
-V 16700,3700,CONT_VIA,*
-V 16700,3300,CONT_BODY_P,*
-V 16700,2900,CONT_BODY_P,*
-V 16700,2500,CONT_BODY_P,*
-V 16700,2100,CONT_BODY_P,*
-V 14900,2100,CONT_BODY_P,*
-V 16100,2100,CONT_BODY_P,*
-V 14900,2500,CONT_VIA,*
-V 16100,2500,CONT_VIA,*
-V 16100,5300,CONT_VIA,*
-V 14900,5300,CONT_VIA,*
-V 14900,5700,CONT_BODY_P,*
-V 16100,5700,CONT_BODY_P,*
-V 16400,9100,CONT_BODY_N,*
-V 16400,9500,CONT_BODY_N,*
-V 14000,12300,CONT_BODY_N,*
-V 14000,11900,CONT_BODY_N,*
-V 14000,11500,CONT_BODY_N,*
-V 14000,11100,CONT_BODY_N,*
-V 14000,10700,CONT_BODY_N,*
-V 16400,10700,CONT_BODY_N,*
-V 16400,11100,CONT_BODY_N,*
-V 16400,11500,CONT_BODY_N,*
-V 16400,11900,CONT_BODY_N,*
-V 16400,12300,CONT_BODY_N,*
-V 16400,12700,CONT_BODY_N,*
-V 16000,12700,CONT_BODY_N,*
-V 15600,12700,CONT_BODY_N,*
-V 15200,12700,CONT_BODY_N,*
-V 14800,12700,CONT_BODY_N,*
-V 14400,12700,CONT_BODY_N,*
-V 14000,12700,CONT_BODY_N,*
-V 14000,9700,CONT_BODY_N,*
-V 16400,8300,CONT_BODY_N,*
-V 16400,7900,CONT_BODY_N,*
-V 16400,7500,CONT_BODY_N,*
-V 16400,7100,CONT_VIA,*
-V 16400,8700,CONT_VIA,*
-V 14300,4400,CONT_DIF_N,*
-V 14400,3800,CONT_POLY,*
-V 16400,6800,CONT_BODY_N,*
-V 14000,8300,CONT_DIF_P,*
-V 14000,8700,CONT_DIF_P,*
-V 14000,9100,CONT_DIF_P,*
-V 14000,7500,CONT_DIF_P,*
-V 14000,7900,CONT_DIF_P,*
-V 14600,7100,CONT_VIA,*
-V 14600,8700,CONT_VIA,*
-V 14600,6800,CONT_BODY_N,*
-V 14600,7900,CONT_DIF_P,*
-V 14600,8300,CONT_DIF_P,*
-V 14600,9100,CONT_DIF_P,*
-V 14600,9500,CONT_DIF_P,*
-V 14600,9900,CONT_DIF_P,*
-V 14600,7500,CONT_DIF_P,*
-V 15200,11900,CONT_DIF_P,*
-V 15200,7500,CONT_DIF_P,*
-V 15200,11500,CONT_DIF_P,*
-V 15200,9500,CONT_DIF_P,*
-V 15200,9100,CONT_DIF_P,*
-V 15200,8700,CONT_DIF_P,*
-V 15200,8300,CONT_DIF_P,*
-V 15200,7900,CONT_DIF_P,*
-V 15200,11100,CONT_DIF_P,*
-V 15200,10700,CONT_DIF_P,*
-V 15200,10300,CONT_DIF_P,*
-V 15200,9900,CONT_DIF_P,*
-V 15800,8700,CONT_VIA,*
-V 15800,7100,CONT_VIA,*
-V 15800,6800,CONT_BODY_N,*
-V 15800,7500,CONT_DIF_P,*
-V 15800,7900,CONT_DIF_P,*
-V 15800,8300,CONT_DIF_P,*
-V 15800,9100,CONT_DIF_P,*
-V 15800,9500,CONT_DIF_P,*
-V 15800,9900,CONT_DIF_P,*
-V 16100,2900,CONT_DIF_N,*
-V 16100,3300,CONT_DIF_N,*
-V 16100,3700,CONT_DIF_N,*
-V 16100,4100,CONT_DIF_N,*
-V 16100,4500,CONT_DIF_N,*
-V 16100,4900,CONT_DIF_N,*
-V 14900,3200,CONT_DIF_N,*
-V 14900,2800,CONT_DIF_N,*
-V 15500,4800,CONT_DIF_N,*
-V 15500,4400,CONT_DIF_N,*
-V 15500,4000,CONT_DIF_N,*
-V 15500,3600,CONT_DIF_N,*
-V 15500,3200,CONT_DIF_N,*
-V 15500,2800,CONT_DIF_N,*
-V 14300,4900,CONT_DIF_N,*
-V 14900,4800,CONT_DIF_N,*
-V 14900,4400,CONT_DIF_N,*
-V 14900,4000,CONT_DIF_N,*
-V 14900,3600,CONT_DIF_N,*
-V 14400,200,CONT_VIA,*
-V 14400,1000,CONT_VIA,*
-V 14000,10200,CONT_VIA,*
-V 14600,10200,CONT_VIA,*
-V 15800,10200,CONT_VIA,*
-V 14600,11700,CONT_DIF_P,*
-V 14600,10500,CONT_DIF_P,*
-V 14600,10900,CONT_DIF_P,*
-V 14600,11300,CONT_DIF_P,*
-V 15800,10500,CONT_DIF_P,*
-V 15800,10900,CONT_DIF_P,*
-V 15800,11300,CONT_DIF_P,*
-V 15800,11700,CONT_DIF_P,*
-V 15800,12100,CONT_DIF_P,*
-V 14600,12100,CONT_DIF_P,*
-V 800,9900,CONT_VIA,*
-V 800,10300,CONT_BODY_N,*
-V 2500,6300,CONT_POLY,*
-V 500,5700,CONT_BODY_P,*
-V 500,5300,CONT_VIA,*
-V 500,4900,CONT_BODY_P,*
-V 500,4500,CONT_BODY_P,*
-V 500,4100,CONT_BODY_P,*
-V 500,3700,CONT_VIA,*
-V 500,3300,CONT_BODY_P,*
-V 500,2900,CONT_BODY_P,*
-V 500,2500,CONT_BODY_P,*
-V 500,2100,CONT_BODY_P,*
-V 2300,2100,CONT_BODY_P,*
-V 1100,2100,CONT_BODY_P,*
-V 2300,2500,CONT_VIA,*
-V 1100,2500,CONT_VIA,*
-V 1100,5300,CONT_VIA,*
-V 2300,5300,CONT_VIA,*
-V 2300,5700,CONT_BODY_P,*
-V 1100,5700,CONT_BODY_P,*
-V 800,9100,CONT_BODY_N,*
-V 800,9500,CONT_BODY_N,*
-V 3200,12300,CONT_BODY_N,*
-V 3200,11900,CONT_BODY_N,*
-V 3200,11500,CONT_BODY_N,*
-V 3200,11100,CONT_BODY_N,*
-V 3200,10700,CONT_BODY_N,*
-V 800,10700,CONT_BODY_N,*
-V 800,11100,CONT_BODY_N,*
-V 800,11500,CONT_BODY_N,*
-V 800,11900,CONT_BODY_N,*
-V 800,12300,CONT_BODY_N,*
-V 800,12700,CONT_BODY_N,*
-V 1200,12700,CONT_BODY_N,*
-V 1600,12700,CONT_BODY_N,*
-V 2000,12700,CONT_BODY_N,*
-V 2400,12700,CONT_BODY_N,*
-V 2800,12700,CONT_BODY_N,*
-V 3200,12700,CONT_BODY_N,*
-V 3200,9700,CONT_BODY_N,*
-V 800,8300,CONT_BODY_N,*
-V 800,7900,CONT_BODY_N,*
-V 800,7500,CONT_BODY_N,*
-V 800,7100,CONT_VIA,*
-V 800,8700,CONT_VIA,*
-V 2900,4400,CONT_DIF_N,*
-V 2800,3800,CONT_POLY,*
-V 800,6800,CONT_BODY_N,*
-V 3200,8300,CONT_DIF_P,*
-V 3200,8700,CONT_DIF_P,*
-V 3200,9100,CONT_DIF_P,*
-V 3200,7500,CONT_DIF_P,*
-V 3200,7900,CONT_DIF_P,*
-V 2600,7100,CONT_VIA,*
-V 2600,8700,CONT_VIA,*
-V 2600,6800,CONT_BODY_N,*
-V 2600,7900,CONT_DIF_P,*
-V 2600,8300,CONT_DIF_P,*
-V 2600,9100,CONT_DIF_P,*
-V 2600,9500,CONT_DIF_P,*
-V 2600,9900,CONT_DIF_P,*
-V 2600,7500,CONT_DIF_P,*
-V 2000,11900,CONT_DIF_P,*
-V 2000,7500,CONT_DIF_P,*
-V 2000,11500,CONT_DIF_P,*
-V 2000,9500,CONT_DIF_P,*
-V 2000,9100,CONT_DIF_P,*
-V 2000,8700,CONT_DIF_P,*
-V 2000,8300,CONT_DIF_P,*
-V 2000,7900,CONT_DIF_P,*
-V 2000,11100,CONT_DIF_P,*
-V 2000,10700,CONT_DIF_P,*
-V 2000,10300,CONT_DIF_P,*
-V 2000,9900,CONT_DIF_P,*
-V 1400,8700,CONT_VIA,*
-V 1400,7100,CONT_VIA,*
-V 1400,6800,CONT_BODY_N,*
-V 1400,7500,CONT_DIF_P,*
-V 1400,7900,CONT_DIF_P,*
-V 1400,8300,CONT_DIF_P,*
-V 1400,9100,CONT_DIF_P,*
-V 1400,9500,CONT_DIF_P,*
-V 1400,9900,CONT_DIF_P,*
-V 1100,2900,CONT_DIF_N,*
-V 1100,3300,CONT_DIF_N,*
-V 1100,3700,CONT_DIF_N,*
-V 1100,4100,CONT_DIF_N,*
-V 1100,4500,CONT_DIF_N,*
-V 1100,4900,CONT_DIF_N,*
-V 2300,3200,CONT_DIF_N,*
-V 2300,2800,CONT_DIF_N,*
-V 1700,4800,CONT_DIF_N,*
-V 1700,4400,CONT_DIF_N,*
-V 1700,4000,CONT_DIF_N,*
-V 1700,3600,CONT_DIF_N,*
-V 1700,3200,CONT_DIF_N,*
-V 1700,2800,CONT_DIF_N,*
-V 2900,4900,CONT_DIF_N,*
-V 2300,4800,CONT_DIF_N,*
-V 2300,4400,CONT_DIF_N,*
-V 2300,4000,CONT_DIF_N,*
-V 2300,3600,CONT_DIF_N,*
-V 2800,200,CONT_VIA,*
-V 2800,1000,CONT_VIA,*
-V 3200,10200,CONT_VIA,*
-V 2600,10200,CONT_VIA,*
-V 1400,10200,CONT_VIA,*
-V 2600,11700,CONT_DIF_P,*
-V 2600,10500,CONT_DIF_P,*
-V 2600,10900,CONT_DIF_P,*
-V 2600,11300,CONT_DIF_P,*
-V 1400,10500,CONT_DIF_P,*
-V 1400,10900,CONT_DIF_P,*
-V 1400,11300,CONT_DIF_P,*
-V 1400,11700,CONT_DIF_P,*
-V 1400,12100,CONT_DIF_P,*
-V 2600,12100,CONT_DIF_P,*
-B 8600,8400,10000,4000,CONT_VIA,*
-B 3200,6300,200,200,CONT_TURN1,*
-B 2000,6300,200,200,CONT_TURN1,*
-B 1700,6300,200,200,CONT_TURN1,*
-B 15500,6300,200,200,CONT_TURN1,*
-B 15200,6300,200,200,CONT_TURN1,*
-B 14000,6300,200,200,CONT_TURN1,*
-V 2100,1600,CONT_VIA,*
-V 15100,1600,CONT_VIA,*
-EOF
diff --git a/alliance/share/cells/padlib/palvsse_sp.ap b/alliance/share/cells/padlib/palvsse_sp.ap
deleted file mode 100644
index dbf5496e..00000000
--- a/alliance/share/cells/padlib/palvsse_sp.ap
+++ /dev/null
@@ -1,21 +0,0 @@
-V ALLIANCE : 6
-H palvsse_sp,P,13/10/2000,100
-A 0,-700,17200,35600
-C 0,29600,12000,vsse,0,WEST,ALU2
-C 17200,29600,12000,vsse,1,EAST,ALU2
-C 0,600,1200,ck,0,WEST,ALU2
-C 17200,600,1200,ck,1,EAST,ALU2
-C 0,4000,4000,vssi,0,WEST,ALU2
-C 17200,4000,4000,vssi,1,EAST,ALU2
-C 0,8400,4000,vddi,0,WEST,ALU2
-C 17200,8400,4000,vddi,1,EAST,ALU2
-C 0,16800,12000,vdde,0,WEST,ALU2
-C 17200,16800,12000,vdde,1,EAST,ALU2
-S 8600,23600,8600,35600,10000,*,UP,ALU1
-S 0,29600,17200,29600,12000,vsse,RIGHT,ALU2
-S 0,600,17200,600,1200,ck,RIGHT,ALU2
-S 0,16800,17200,16800,12000,vdde,RIGHT,ALU2
-S 0,8400,17200,8400,4000,vddi,RIGHT,ALU2
-S 0,4000,17200,4000,4000,vssi,RIGHT,ALU2
-B 8600,29600,10000,12000,CONT_VIA,*
-EOF
diff --git a/alliance/share/cells/padlib/palvsseck_sp.ap b/alliance/share/cells/padlib/palvsseck_sp.ap
deleted file mode 100644
index 2b805b4f..00000000
--- a/alliance/share/cells/padlib/palvsseck_sp.ap
+++ /dev/null
@@ -1,290 +0,0 @@
-V ALLIANCE : 6
-H palvsseck_sp,P,13/10/2000,100
-A 0,-700,17200,35600
-C 9100,-700,200,cko,4,SOUTH,ALU1
-C 9100,-700,200,cko,5,SOUTH,ALU2
-C 7900,-700,200,cko,2,SOUTH,ALU1
-C 7900,-700,200,cko,3,SOUTH,ALU2
-C 6700,-700,200,cko,0,SOUTH,ALU1
-C 6700,-700,200,cko,1,SOUTH,ALU2
-C 17200,16800,12000,vdde,1,EAST,ALU2
-C 0,16800,12000,vdde,0,WEST,ALU2
-C 17200,8400,4000,vddi,1,EAST,ALU2
-C 0,8400,4000,vddi,0,WEST,ALU2
-C 17200,4000,4000,vssi,1,EAST,ALU2
-C 0,4000,4000,vssi,0,WEST,ALU2
-C 17200,600,1200,ck,1,EAST,ALU2
-C 0,600,1200,ck,0,WEST,ALU2
-C 17200,29600,12000,vsse,1,EAST,ALU2
-C 0,29600,12000,vsse,0,WEST,ALU2
-S 8600,23700,8600,35600,10000,*,UP,ALU1
-S 0,8400,17200,8400,4000,vddi,RIGHT,ALU2
-S 0,4000,17200,4000,4000,vssi,RIGHT,ALU2
-S 0,16800,17200,16800,12000,vdde,RIGHT,ALU2
-S 6700,1600,9100,1600,200,*,RIGHT,ALU1
-S 9100,-700,9100,9600,200,*,UP,ALU1
-S 7900,-700,7900,4400,200,*,UP,ALU1
-S 6700,-700,6700,4400,200,*,UP,ALU1
-S 0,600,17200,600,1200,ck,RIGHT,ALU2
-S 5500,6100,5500,10400,200,*,UP,ALU1
-S 7600,4700,7600,6400,500,*,UP,POLY
-S 6400,4700,8800,4700,100,*,RIGHT,POLY
-S 5200,4700,5200,6400,100,*,UP,POLY
-S 6400,6400,8800,6400,100,*,RIGHT,POLY
-S 5400,5000,7200,5000,300,*,RIGHT,PTIE
-S 8000,5000,9800,5000,300,*,RIGHT,PTIE
-S 8000,6100,9800,6100,300,*,RIGHT,NTIE
-S 5400,6100,7200,6100,300,*,RIGHT,NTIE
-S 5200,6400,5200,10700,100,*,UP,PTRANS
-S 7000,2400,7000,4700,100,*,UP,NTRANS
-S 6400,2400,6400,4700,100,*,UP,NTRANS
-S 5200,2400,5200,4700,100,*,UP,NTRANS
-S 8800,2400,8800,4700,100,*,UP,NTRANS
-S 8200,2400,8200,4700,100,*,UP,NTRANS
-S 7600,2400,7600,4700,100,*,UP,NTRANS
-S 4900,2000,4900,5100,200,*,UP,ALU1
-S 6700,2600,6700,4500,200,*,UP,NDIF
-S 5500,6600,5500,10500,300,*,UP,PDIF
-S 9100,2600,9100,4500,300,*,UP,NDIF
-S 5500,2600,5500,4500,300,*,UP,NDIF
-S 7900,2600,7900,4400,300,*,UP,NDIF
-S 6100,2600,6100,4400,300,*,UP,NDIF
-S 4900,2600,4900,4400,300,*,UP,NDIF
-S 7300,2600,7300,4400,200,*,UP,NDIF
-S 8500,2600,8500,4500,200,*,UP,NDIF
-S 4300,2000,4300,5100,300,*,UP,PTIE
-S 9700,2000,9700,5100,300,*,UP,PTIE
-S 4200,2100,9800,2100,300,*,RIGHT,PTIE
-S 4200,5000,5000,5000,300,*,RIGHT,PTIE
-S 9700,2000,9700,5100,300,*,UP,ALU1
-S 9700,2000,9700,5100,300,*,UP,PTIE
-S 6100,2000,6100,4500,200,*,UP,ALU1
-S 4900,6800,4900,10400,200,*,UP,ALU1
-S 4900,6600,4900,10400,300,*,UP,PDIF
-S 4300,6000,4300,11000,300,*,UP,NTIE
-S 4200,6100,5000,6100,300,*,RIGHT,NTIE
-S 8800,6400,8800,10100,100,*,UP,PTRANS
-S 8200,6400,8200,10100,100,*,UP,PTRANS
-S 7600,6400,7600,10100,100,*,UP,PTRANS
-S 7000,6400,7000,10100,100,*,UP,PTRANS
-S 6400,6400,6400,10100,100,*,UP,PTRANS
-S 6700,6600,6700,9900,200,*,UP,PDIF
-S 6100,6600,6100,9900,300,*,UP,PDIF
-S 7300,6600,7300,9900,200,*,UP,PDIF
-S 7900,6600,7900,9900,200,*,UP,PDIF
-S 8500,6600,8500,9900,200,*,UP,PDIF
-S 9100,6600,9100,9900,300,*,UP,PDIF
-S 6700,6700,6700,9600,200,*,UP,ALU1
-S 7900,6700,7900,9600,200,*,UP,ALU1
-S 9700,6100,9700,10500,300,*,UP,NTIE
-S 6100,10300,6100,11100,300,*,UP,NTIE
-S 6000,10400,9800,10400,300,*,RIGHT,NTIE
-S 8500,7100,8500,10400,200,*,UP,ALU1
-S 7300,7100,7300,10400,200,*,UP,ALU1
-S 6100,6800,6100,10400,200,*,UP,ALU1
-S 5800,5600,7600,5600,200,*,RIGHT,ALU1
-S 4100,8500,9900,8500,5200,*,RIGHT,NWELL
-S 5500,2800,5500,5100,200,*,UP,ALU1
-S 5700,4900,5700,6200,200,*,UP,ALU1
-S 0,29600,17200,29600,12000,vsse,RIGHT,ALU2
-S 4200,6100,5000,6100,200,*,RIGHT,ALU1
-S 9700,6000,9700,10400,200,*,UP,ALU1
-S 6200,4400,6200,5000,200,*,UP,ALU1
-S 3800,5600,5200,5600,200,*,RIGHT,ALU1
-S 3800,100,3800,5600,200,*,UP,ALU1
-S 6200,5000,8500,5000,200,*,RIGHT,ALU1
-S 4300,6100,4300,10400,300,*,UP,ALU1
-S 6200,6100,6200,6900,200,*,UP,ALU1
-S 6200,6100,7200,6100,200,*,RIGHT,ALU1
-S 6700,6600,9100,6600,200,*,RIGHT,ALU1
-S 6100,10400,9700,10400,200,*,RIGHT,ALU1
-S 4300,2000,4300,5100,200,*,UP,ALU1
-S 4300,2100,6100,2100,300,*,RIGHT,ALU1
-S 7300,2200,7300,4500,200,*,UP,ALU1
-S 8500,2100,8500,4900,200,*,UP,ALU1
-B 8600,29600,10000,12000,CONT_VIA,*
-V 9100,-700,CONT_VIA,*
-V 7900,-700,CONT_VIA,*
-V 6700,-700,CONT_VIA,*
-V 3800,1000,CONT_VIA,*
-V 3800,200,CONT_VIA,*
-V 5500,9600,CONT_DIF_P,*
-V 5500,9200,CONT_DIF_P,*
-V 5500,8800,CONT_DIF_P,*
-V 5500,8400,CONT_DIF_P,*
-V 5500,8000,CONT_DIF_P,*
-V 5500,7600,CONT_DIF_P,*
-V 5500,7200,CONT_DIF_P,*
-V 5500,6800,CONT_DIF_P,*
-V 5500,10400,CONT_DIF_P,*
-V 5500,10000,CONT_DIF_P,*
-V 6700,9600,CONT_DIF_P,*
-V 6700,9200,CONT_DIF_P,*
-V 7900,7600,CONT_DIF_P,*
-V 7900,8000,CONT_DIF_P,*
-V 6700,8800,CONT_DIF_P,*
-V 6700,8400,CONT_DIF_P,*
-V 6700,8000,CONT_DIF_P,*
-V 6700,7600,CONT_DIF_P,*
-V 6700,7200,CONT_DIF_P,*
-V 6700,6800,CONT_DIF_P,*
-V 7900,9200,CONT_DIF_P,*
-V 7900,9600,CONT_DIF_P,*
-V 7900,6800,CONT_DIF_P,*
-V 7900,7200,CONT_DIF_P,*
-V 9100,8800,CONT_DIF_P,*
-V 9100,8400,CONT_DIF_P,*
-V 7900,8400,CONT_DIF_P,*
-V 7900,8800,CONT_DIF_P,*
-V 9100,8000,CONT_DIF_P,*
-V 9100,7600,CONT_DIF_P,*
-V 9100,7200,CONT_DIF_P,*
-V 9100,6800,CONT_DIF_P,*
-V 9100,9600,CONT_DIF_P,*
-V 9100,9200,CONT_DIF_P,*
-V 5500,3600,CONT_DIF_N,*
-V 5500,3200,CONT_DIF_N,*
-V 5500,2800,CONT_DIF_N,*
-V 5500,4400,CONT_DIF_N,*
-V 5500,4000,CONT_DIF_N,*
-V 7900,2800,CONT_DIF_N,*
-V 9100,3200,CONT_DIF_N,*
-V 6700,3600,CONT_DIF_N,*
-V 6700,3200,CONT_DIF_N,*
-V 6700,2800,CONT_DIF_N,*
-V 6700,4400,CONT_DIF_N,*
-V 6700,4000,CONT_DIF_N,*
-V 7900,4000,CONT_DIF_N,*
-V 7900,4400,CONT_DIF_N,*
-V 7900,3200,CONT_DIF_N,*
-V 7900,3600,CONT_DIF_N,*
-V 9100,2800,CONT_DIF_N,*
-V 9100,4400,CONT_DIF_N,*
-V 9100,4000,CONT_DIF_N,*
-V 9100,3600,CONT_DIF_N,*
-V 7300,4400,CONT_DIF_N,*
-V 6100,4400,CONT_DIF_N,*
-V 8500,4400,CONT_DIF_N,*
-V 6100,4000,CONT_VIA,*
-V 7300,4000,CONT_VIA,*
-V 8500,4000,CONT_VIA,*
-V 4900,4000,CONT_VIA,*
-V 4900,4400,CONT_DIF_N,*
-V 4900,3600,CONT_DIF_N,*
-V 6100,3600,CONT_DIF_N,*
-V 7300,3600,CONT_DIF_N,*
-V 8500,3600,CONT_DIF_N,*
-V 8500,3200,CONT_DIF_N,*
-V 7300,3200,CONT_DIF_N,*
-V 6100,3200,CONT_DIF_N,*
-V 4900,3200,CONT_DIF_N,*
-V 4900,2800,CONT_DIF_N,*
-V 6100,2800,CONT_DIF_N,*
-V 7300,2800,CONT_DIF_N,*
-V 8500,2800,CONT_DIF_N,*
-V 4900,2400,CONT_VIA,*
-V 6100,2400,CONT_VIA,*
-V 7300,2400,CONT_VIA,*
-V 8500,2400,CONT_VIA,*
-V 8500,2100,CONT_BODY_P,*
-V 7300,2100,CONT_BODY_P,*
-V 6100,2100,CONT_BODY_P,*
-V 4900,2100,CONT_BODY_P,*
-V 8500,5000,CONT_BODY_P,*
-V 4900,5000,CONT_BODY_P,*
-V 5700,2100,CONT_BODY_P,*
-V 5300,2100,CONT_BODY_P,*
-V 4300,2100,CONT_BODY_P,*
-V 4300,2500,CONT_BODY_P,*
-V 4300,2900,CONT_VIA,*
-V 4300,3300,CONT_BODY_P,*
-V 4300,3700,CONT_BODY_P,*
-V 4300,4100,CONT_BODY_P,*
-V 4300,4500,CONT_VIA,*
-V 4300,5000,CONT_BODY_P,*
-V 9700,2900,CONT_VIA,*
-V 9700,4500,CONT_VIA,*
-V 9700,2100,CONT_BODY_P,*
-V 9700,5000,CONT_BODY_P,*
-V 9700,4100,CONT_BODY_P,*
-V 9700,3700,CONT_BODY_P,*
-V 9700,3300,CONT_BODY_P,*
-V 9700,2500,CONT_BODY_P,*
-V 7100,5000,CONT_BODY_P,*
-V 8100,5000,CONT_BODY_P,*
-V 6600,5000,CONT_VIA,*
-V 6200,5000,CONT_BODY_P,*
-V 6100,9600,CONT_DIF_P,*
-V 6100,9200,CONT_DIF_P,*
-V 6100,8800,CONT_DIF_P,*
-V 6100,8000,CONT_DIF_P,*
-V 6100,7600,CONT_DIF_P,*
-V 6100,6800,CONT_DIF_P,*
-V 6100,10000,CONT_VIA,*
-V 6100,8400,CONT_VIA,*
-V 6100,7200,CONT_VIA,*
-V 4900,8400,CONT_VIA,*
-V 4900,10000,CONT_VIA,*
-V 4900,7200,CONT_VIA,*
-V 4900,7600,CONT_DIF_P,*
-V 4900,8000,CONT_DIF_P,*
-V 4900,8800,CONT_DIF_P,*
-V 4900,9200,CONT_DIF_P,*
-V 4900,9600,CONT_DIF_P,*
-V 4900,10400,CONT_DIF_P,*
-V 4900,6800,CONT_DIF_P,*
-V 7300,10000,CONT_VIA,*
-V 7300,8400,CONT_VIA,*
-V 7300,9600,CONT_DIF_P,*
-V 7300,9200,CONT_DIF_P,*
-V 7300,8800,CONT_DIF_P,*
-V 7300,8000,CONT_DIF_P,*
-V 7300,7600,CONT_DIF_P,*
-V 7300,7100,CONT_DIF_P,*
-V 8500,8400,CONT_VIA,*
-V 8500,10000,CONT_VIA,*
-V 8500,7600,CONT_DIF_P,*
-V 8500,8000,CONT_DIF_P,*
-V 8500,8800,CONT_DIF_P,*
-V 8500,9200,CONT_DIF_P,*
-V 8500,9600,CONT_DIF_P,*
-V 8500,7100,CONT_DIF_P,*
-V 6100,10400,CONT_BODY_N,*
-V 6500,10400,CONT_BODY_N,*
-V 6900,10400,CONT_BODY_N,*
-V 7300,10400,CONT_BODY_N,*
-V 7700,10400,CONT_BODY_N,*
-V 8100,10400,CONT_BODY_N,*
-V 8500,10400,CONT_BODY_N,*
-V 8900,10400,CONT_BODY_N,*
-V 9300,10400,CONT_BODY_N,*
-V 9700,10400,CONT_BODY_N,*
-V 9700,10000,CONT_BODY_N,*
-V 9700,9200,CONT_BODY_N,*
-V 9700,8800,CONT_BODY_N,*
-V 9700,8400,CONT_BODY_N,*
-V 9700,8000,CONT_BODY_N,*
-V 9700,7600,CONT_BODY_N,*
-V 9700,6100,CONT_BODY_N,*
-V 9700,6500,CONT_BODY_N,*
-V 9700,7000,CONT_VIA,*
-V 9700,9600,CONT_VIA,*
-V 7600,5600,CONT_POLY,*
-V 7100,6100,CONT_BODY_N,*
-V 6200,6100,CONT_BODY_N,*
-V 6700,6100,CONT_BODY_N,*
-V 4900,6100,CONT_BODY_N,*
-V 4300,6100,CONT_BODY_N,*
-V 4300,6500,CONT_BODY_N,*
-V 4300,6900,CONT_VIA,*
-V 4300,7300,CONT_BODY_N,*
-V 5200,5600,CONT_POLY,*
-V 4300,7700,CONT_BODY_N,*
-V 4300,8100,CONT_BODY_N,*
-V 4300,8500,CONT_VIA,*
-V 4300,8900,CONT_BODY_N,*
-V 4300,9300,CONT_BODY_N,*
-V 4300,9700,CONT_VIA,*
-V 4300,10300,CONT_BODY_N,*
-B 3800,5600,200,200,CONT_TURN1,*
-EOF
diff --git a/alliance/share/cells/padlib/palvssi_sp.ap b/alliance/share/cells/padlib/palvssi_sp.ap
deleted file mode 100644
index 8cb75bab..00000000
--- a/alliance/share/cells/padlib/palvssi_sp.ap
+++ /dev/null
@@ -1,44 +0,0 @@
-V ALLIANCE : 6
-H palvssi_sp,P,13/10/2000,100
-A 0,0,17200,36300
-C 8600,0,10000,vssi,2,SOUTH,ALU1
-C 17200,17500,12000,vdde,3,EAST,ALU2
-C 0,17500,12000,vdde,2,WEST,ALU2
-C 17200,9100,4000,vddi,3,EAST,ALU2
-C 0,9100,4000,vddi,2,WEST,ALU2
-C 17200,4700,4000,vssi,9,EAST,ALU2
-C 0,4700,4000,vssi,8,WEST,ALU2
-C 17200,1300,1200,ck,3,EAST,ALU2
-C 0,1300,1200,ck,2,WEST,ALU2
-C 17200,30300,12000,vsse,3,EAST,ALU2
-C 0,30300,12000,vsse,2,WEST,ALU2
-C 8600,0,10000,vssi,3,SOUTH,ALU2
-S 8600,0,8600,36300,10000,*,UP,ALU1
-S 0,4700,17200,4700,4000,vssi,RIGHT,ALU2
-S 0,9100,17200,9100,4000,vddi,RIGHT,ALU2
-S 0,17500,17200,17500,12000,vdde,RIGHT,ALU2
-S 0,1300,17200,1300,1200,ck,RIGHT,ALU2
-S 0,30300,17200,30300,12000,vsse,RIGHT,ALU2
-B 8600,200,10000,400,CONT_TURN2,*
-V 10700,300,CONT_VIA,*
-V 11200,300,CONT_VIA,*
-V 11700,300,CONT_VIA,*
-V 12200,300,CONT_VIA,*
-V 13200,300,CONT_VIA,*
-V 12700,300,CONT_VIA,*
-V 9700,300,CONT_VIA,*
-V 10200,300,CONT_VIA,*
-V 7700,300,CONT_VIA,*
-V 8200,300,CONT_VIA,*
-V 8700,300,CONT_VIA,*
-V 9200,300,CONT_VIA,*
-V 6700,300,CONT_VIA,*
-V 7200,300,CONT_VIA,*
-V 6200,300,CONT_VIA,*
-V 5700,300,CONT_VIA,*
-V 5200,300,CONT_VIA,*
-V 4700,300,CONT_VIA,*
-V 4200,300,CONT_VIA,*
-V 3700,300,CONT_VIA,*
-B 8600,4700,10000,4000,CONT_VIA,*
-EOF
diff --git a/alliance/share/cells/padlib/palvssick_sp.ap b/alliance/share/cells/padlib/palvssick_sp.ap
deleted file mode 100644
index 0b4aee73..00000000
--- a/alliance/share/cells/padlib/palvssick_sp.ap
+++ /dev/null
@@ -1,411 +0,0 @@
-V ALLIANCE : 6
-H palvssick_sp,P,13/10/2000,100
-A 0,0,17200,36300
-C 8600,0,10000,vssi,2,SOUTH,ALU1
-C 8600,0,10000,vssi,4,SOUTH,ALU2
-C 17200,1300,1200,ck,3,EAST,ALU2
-C 17200,4700,4000,vssi,8,EAST,ALU2
-C 17200,9100,4000,vddi,3,EAST,ALU2
-C 0,1300,1200,ck,2,WEST,ALU2
-C 0,4700,4000,vssi,7,WEST,ALU2
-C 0,9100,4000,vddi,2,WEST,ALU2
-C 0,17500,12000,vdde,2,WEST,ALU2
-C 17200,17500,12000,vdde,3,EAST,ALU2
-C 15500,0,200,cko,7,SOUTH,ALU2
-C 15500,0,200,cko,6,SOUTH,ALU1
-C 1700,0,200,cko,5,SOUTH,ALU2
-C 1700,0,200,cko,4,SOUTH,ALU1
-C 17200,30300,12000,vsse,3,EAST,ALU2
-C 0,30300,12000,vsse,2,WEST,ALU2
-S 800,7500,1500,7500,300,*,RIGHT,NTIE
-S 2100,7500,2700,7500,300,*,RIGHT,NTIE
-S 3100,10400,3900,10400,300,*,RIGHT,NTIE
-S 2000,8000,2000,12900,200,*,UP,PDIF
-S 1400,8000,1400,12900,300,*,UP,PDIF
-S 2600,8000,2600,12900,300,*,UP,PDIF
-S 3200,8000,3200,9900,300,*,UP,PDIF
-S 3200,10300,3200,13500,300,*,DOWN,NTIE
-S 700,13400,3200,13400,300,*,RIGHT,NTIE
-S 800,7400,800,13500,300,*,DOWN,NTIE
-S 14500,7500,15100,7500,300,*,RIGHT,NTIE
-S 3100,7500,3900,7500,300,*,RIGHT,NTIE
-S 600,13400,4000,13400,400,*,RIGHT,NWELL
-S 600,10400,4000,10400,6200,*,RIGHT,NWELL
-S 2900,7800,2900,10100,100,*,DOWN,PTRANS
-S 2300,7800,2300,13100,100,*,DOWN,PTRANS
-S 1700,7800,1700,13100,100,*,DOWN,PTRANS
-S 3800,7400,3800,10500,300,*,DOWN,NTIE
-S 15200,8000,15200,12900,200,*,DOWN,PDIF
-S 15800,8000,15800,12900,300,*,DOWN,PDIF
-S 14600,8000,14600,12900,300,*,DOWN,PDIF
-S 14000,8000,14000,9900,300,*,DOWN,PDIF
-S 14000,10300,14000,13500,300,*,UP,NTIE
-S 14000,13400,16500,13400,300,*,RIGHT,NTIE
-S 16400,7400,16400,13500,300,*,UP,NTIE
-S 15700,7500,16400,7500,300,*,RIGHT,NTIE
-S 13300,7500,14100,7500,300,*,RIGHT,NTIE
-S 13200,13400,16600,13400,400,*,RIGHT,NWELL
-S 13200,10400,16600,10400,6200,*,RIGHT,NWELL
-S 14300,7800,14300,10100,100,*,UP,PTRANS
-S 14900,7800,14900,13100,100,*,UP,PTRANS
-S 15500,7800,15500,13100,100,*,UP,PTRANS
-S 13400,7400,13400,10500,300,*,UP,NTIE
-S 13300,10400,14100,10400,300,*,RIGHT,NTIE
-S 15800,3100,15800,5900,100,*,DOWN,NTRANS
-S 14600,4600,14600,5900,100,*,DOWN,NTRANS
-S 15200,3100,15200,5900,100,*,DOWN,NTRANS
-S 1400,3100,1400,5900,100,*,UP,NTRANS
-S 2600,4600,2600,5900,100,*,UP,NTRANS
-S 2000,3100,2000,5900,100,*,UP,NTRANS
-S 1100,3300,1100,5700,300,*,UP,NDIF
-S 2900,4800,2900,5700,300,*,UP,NDIF
-S 2300,3300,2300,5700,300,*,UP,NDIF
-S 1700,3300,1700,5700,300,*,UP,NDIF
-S 14900,3300,14900,5700,300,*,DOWN,NDIF
-S 15500,3300,15500,5700,300,*,DOWN,NDIF
-S 16100,3300,16100,5700,300,*,DOWN,NDIF
-S 14300,4800,14300,5700,300,*,DOWN,NDIF
-S 400,2800,3000,2800,300,*,LEFT,PTIE
-S 500,2800,500,6500,300,*,UP,PTIE
-S 500,6400,1500,6400,300,*,RIGHT,PTIE
-S 3100,6400,3600,6400,300,*,RIGHT,PTIE
-S 2900,2800,2900,4100,300,*,DOWN,PTIE
-S 2900,4000,3600,4000,300,*,LEFT,PTIE
-S 3500,4100,3500,6500,300,*,DOWN,PTIE
-S 2100,6400,2700,6400,300,*,RIGHT,PTIE
-S 13600,6400,14100,6400,300,*,RIGHT,PTIE
-S 14200,2800,16800,2800,300,*,LEFT,PTIE
-S 14300,2800,14300,4100,300,*,UP,PTIE
-S 13600,4000,14300,4000,300,*,LEFT,PTIE
-S 16700,2800,16700,6500,300,*,DOWN,PTIE
-S 13700,4100,13700,6500,300,*,UP,PTIE
-S 15700,6400,16700,6400,300,*,RIGHT,PTIE
-S 14500,6400,15100,6400,300,*,RIGHT,PTIE
-S 1800,5900,1800,7800,200,*,DOWN,POLY
-S 1900,7000,2500,7000,300,*,LEFT,POLY
-S 2600,5900,2900,5900,100,*,RIGHT,POLY
-S 2600,4400,2600,4600,100,*,UP,POLY
-S 15400,5900,15400,7800,200,*,UP,POLY
-S 14700,7000,15300,7000,300,*,LEFT,POLY
-S 1400,5900,2000,5900,100,*,RIGHT,POLY
-S 1700,7800,2300,7800,100,*,RIGHT,POLY
-S 2900,5900,2900,7800,100,*,UP,POLY
-S 15200,5900,15800,5900,100,*,RIGHT,POLY
-S 14900,7800,15500,7800,100,*,RIGHT,POLY
-S 14300,5900,14300,7800,100,*,DOWN,POLY
-S 14300,5900,14600,5900,100,*,RIGHT,POLY
-S 14600,4400,14600,4600,100,*,DOWN,POLY
-S 15500,0,15500,2200,200,*,UP,ALU1
-S 1700,0,1700,2300,200,*,DOWN,ALU1
-S 8600,0,8600,36300,10000,*,UP,ALU1
-S 800,2800,800,6500,900,*,UP,ALU1
-S 400,2800,1200,2800,200,*,LEFT,ALU1
-S 700,7500,1400,7500,200,*,LEFT,ALU1
-S 16400,2800,16400,6500,900,*,DOWN,ALU1
-S 16000,2800,16800,2800,200,*,RIGHT,ALU1
-S 1500,2300,2100,2300,200,*,LEFT,ALU1
-S 15100,2300,15700,2300,200,*,LEFT,ALU1
-S 14600,7500,14600,13500,200,*,DOWN,ALU1
-S 15800,7500,15800,13500,200,*,DOWN,ALU1
-S 16200,7500,16200,13500,700,*,UP,ALU1
-S 15800,7500,16500,7500,200,*,LEFT,ALU1
-S 1000,7500,1000,13500,700,*,DOWN,ALU1
-S 1400,7500,1400,13500,200,*,UP,ALU1
-S 14000,10300,14000,13500,200,*,DOWN,ALU1
-S 14000,13300,16500,13300,500,*,LEFT,ALU1
-S 700,13300,3200,13300,500,*,LEFT,ALU1
-S 2500,7000,3200,7000,200,*,RIGHT,ALU1
-S 14000,7000,14700,7000,200,*,RIGHT,ALU1
-S 15200,7000,15500,7000,200,*,RIGHT,ALU1
-S 1700,7000,2000,7000,200,*,RIGHT,ALU1
-S 2600,7500,2600,13500,200,*,UP,ALU1
-S 15500,2200,15500,7000,200,*,DOWN,ALU1
-S 2800,1000,2800,4500,200,*,UP,ALU1
-S 2900,5100,2900,7000,200,*,UP,ALU1
-S 3200,7000,3200,9800,200,*,UP,ALU1
-S 2000,7000,2000,12600,200,*,UP,ALU1
-S 2300,2800,2300,6500,200,*,UP,ALU1
-S 1700,2200,1700,7000,200,*,UP,ALU1
-S 3200,10300,3200,13500,200,*,UP,ALU1
-S 14400,1000,14400,4500,200,*,DOWN,ALU1
-S 14300,5100,14300,7000,200,*,DOWN,ALU1
-S 14000,7000,14000,9800,200,*,DOWN,ALU1
-S 15200,7000,15200,12600,200,*,DOWN,ALU1
-S 14900,2800,14900,6500,200,*,DOWN,ALU1
-S 0,9100,17200,9100,4000,vddi,RIGHT,ALU2
-S 0,4700,17200,4700,4000,vssi,RIGHT,ALU2
-S 0,17500,17200,17500,12000,vdde,RIGHT,ALU2
-S 0,1300,17200,1300,1200,ck,RIGHT,ALU2
-S 1700,2300,15700,2300,200,*,RIGHT,ALU2
-S 0,30300,17200,30300,12000,vsse,RIGHT,ALU2
-V 4000,300,CONT_VIA,*
-V 4500,300,CONT_VIA,*
-V 8500,300,CONT_VIA,*
-V 8000,300,CONT_VIA,*
-V 7500,300,CONT_VIA,*
-V 7000,300,CONT_VIA,*
-V 6500,300,CONT_VIA,*
-V 6000,300,CONT_VIA,*
-V 5500,300,CONT_VIA,*
-V 5000,300,CONT_VIA,*
-V 9000,300,CONT_VIA,*
-V 9500,300,CONT_VIA,*
-V 10000,300,CONT_VIA,*
-V 10500,300,CONT_VIA,*
-V 11000,300,CONT_VIA,*
-V 11500,300,CONT_VIA,*
-V 12000,300,CONT_VIA,*
-V 12500,300,CONT_VIA,*
-V 13000,300,CONT_VIA,*
-V 13500,300,CONT_VIA,*
-B 8600,200,10000,400,CONT_TURN2,*
-V 1400,11200,CONT_DIF_P,*
-V 1400,11600,CONT_DIF_P,*
-V 1400,12000,CONT_DIF_P,*
-V 1400,12400,CONT_DIF_P,*
-V 1400,12800,CONT_DIF_P,*
-V 2600,12800,CONT_DIF_P,*
-V 1400,9000,CONT_DIF_P,*
-V 1400,9800,CONT_DIF_P,*
-V 1400,10200,CONT_DIF_P,*
-V 1400,10600,CONT_DIF_P,*
-V 2600,12400,CONT_DIF_P,*
-V 2600,11200,CONT_DIF_P,*
-V 2600,11600,CONT_DIF_P,*
-V 2600,12000,CONT_DIF_P,*
-V 2000,8600,CONT_DIF_P,*
-V 2000,11800,CONT_DIF_P,*
-V 2000,11400,CONT_DIF_P,*
-V 2000,11000,CONT_DIF_P,*
-V 2000,10600,CONT_DIF_P,*
-V 1400,7500,CONT_BODY_N,*
-V 1400,8200,CONT_DIF_P,*
-V 1400,8600,CONT_DIF_P,*
-V 2600,8200,CONT_DIF_P,*
-V 2000,12600,CONT_DIF_P,*
-V 2000,8200,CONT_DIF_P,*
-V 2000,12200,CONT_DIF_P,*
-V 2000,10200,CONT_DIF_P,*
-V 2000,9800,CONT_DIF_P,*
-V 2000,9400,CONT_DIF_P,*
-V 2000,9000,CONT_DIF_P,*
-V 3200,8200,CONT_DIF_P,*
-V 3200,8600,CONT_DIF_P,*
-V 2600,7500,CONT_BODY_N,*
-V 2600,8600,CONT_DIF_P,*
-V 2600,9000,CONT_DIF_P,*
-V 2600,9800,CONT_DIF_P,*
-V 2600,10200,CONT_DIF_P,*
-V 2600,10600,CONT_DIF_P,*
-V 3200,10400,CONT_BODY_N,*
-V 800,9000,CONT_BODY_N,*
-V 800,8600,CONT_BODY_N,*
-V 800,8200,CONT_BODY_N,*
-V 800,7500,CONT_BODY_N,*
-V 3200,9000,CONT_DIF_P,*
-V 3200,9400,CONT_DIF_P,*
-V 3200,9800,CONT_DIF_P,*
-V 800,13000,CONT_BODY_N,*
-V 800,13400,CONT_BODY_N,*
-V 1200,13400,CONT_BODY_N,*
-V 1600,13400,CONT_BODY_N,*
-V 2000,13400,CONT_BODY_N,*
-V 2400,13400,CONT_BODY_N,*
-V 2800,13400,CONT_BODY_N,*
-V 3200,13400,CONT_BODY_N,*
-V 3200,12600,CONT_BODY_N,*
-V 3200,12200,CONT_BODY_N,*
-V 3200,11800,CONT_BODY_N,*
-V 3200,11400,CONT_BODY_N,*
-V 800,11400,CONT_BODY_N,*
-V 800,11800,CONT_BODY_N,*
-V 800,12200,CONT_BODY_N,*
-V 800,12600,CONT_BODY_N,*
-V 15800,12000,CONT_DIF_P,*
-V 15800,12400,CONT_DIF_P,*
-V 15800,12800,CONT_DIF_P,*
-V 14600,12800,CONT_DIF_P,*
-V 800,11000,CONT_BODY_N,*
-V 800,9800,CONT_BODY_N,*
-V 800,10200,CONT_BODY_N,*
-V 3200,13000,CONT_BODY_N,*
-V 15800,10200,CONT_DIF_P,*
-V 15800,10600,CONT_DIF_P,*
-V 14600,12400,CONT_DIF_P,*
-V 14600,11200,CONT_DIF_P,*
-V 14600,11600,CONT_DIF_P,*
-V 14600,12000,CONT_DIF_P,*
-V 15800,11200,CONT_DIF_P,*
-V 15800,11600,CONT_DIF_P,*
-V 15200,11400,CONT_DIF_P,*
-V 15200,11000,CONT_DIF_P,*
-V 15200,10600,CONT_DIF_P,*
-V 15800,7500,CONT_BODY_N,*
-V 15800,8200,CONT_DIF_P,*
-V 15800,8600,CONT_DIF_P,*
-V 15800,9000,CONT_DIF_P,*
-V 15800,9800,CONT_DIF_P,*
-V 15200,8200,CONT_DIF_P,*
-V 15200,12200,CONT_DIF_P,*
-V 15200,10200,CONT_DIF_P,*
-V 15200,9800,CONT_DIF_P,*
-V 15200,9400,CONT_DIF_P,*
-V 15200,9000,CONT_DIF_P,*
-V 15200,8600,CONT_DIF_P,*
-V 15200,11800,CONT_DIF_P,*
-V 14600,7500,CONT_BODY_N,*
-V 14600,8600,CONT_DIF_P,*
-V 14600,9000,CONT_DIF_P,*
-V 14600,9800,CONT_DIF_P,*
-V 14600,10200,CONT_DIF_P,*
-V 14600,10600,CONT_DIF_P,*
-V 14600,8200,CONT_DIF_P,*
-V 15200,12600,CONT_DIF_P,*
-V 16400,8600,CONT_BODY_N,*
-V 16400,8200,CONT_BODY_N,*
-V 16400,7500,CONT_BODY_N,*
-V 14000,9000,CONT_DIF_P,*
-V 14000,9400,CONT_DIF_P,*
-V 14000,9800,CONT_DIF_P,*
-V 14000,8200,CONT_DIF_P,*
-V 14000,8600,CONT_DIF_P,*
-V 16000,13400,CONT_BODY_N,*
-V 15600,13400,CONT_BODY_N,*
-V 15200,13400,CONT_BODY_N,*
-V 14800,13400,CONT_BODY_N,*
-V 14400,13400,CONT_BODY_N,*
-V 14000,13400,CONT_BODY_N,*
-V 14000,10400,CONT_BODY_N,*
-V 16400,9000,CONT_BODY_N,*
-V 14000,11800,CONT_BODY_N,*
-V 14000,11400,CONT_BODY_N,*
-V 16400,11400,CONT_BODY_N,*
-V 16400,11800,CONT_BODY_N,*
-V 16400,12200,CONT_BODY_N,*
-V 16400,12600,CONT_BODY_N,*
-V 16400,13000,CONT_BODY_N,*
-V 16400,13400,CONT_BODY_N,*
-V 16400,11000,CONT_BODY_N,*
-V 16400,9800,CONT_BODY_N,*
-V 16400,10200,CONT_BODY_N,*
-V 14000,13000,CONT_BODY_N,*
-V 14000,12600,CONT_BODY_N,*
-V 14000,12200,CONT_BODY_N,*
-V 2300,5500,CONT_DIF_N,*
-V 2300,5100,CONT_DIF_N,*
-V 2300,4700,CONT_DIF_N,*
-V 2300,4300,CONT_DIF_N,*
-V 2300,3500,CONT_DIF_N,*
-V 1700,5500,CONT_DIF_N,*
-V 1700,5100,CONT_DIF_N,*
-V 1700,4700,CONT_DIF_N,*
-V 1700,4300,CONT_DIF_N,*
-V 1700,3900,CONT_DIF_N,*
-V 1700,3500,CONT_DIF_N,*
-V 2900,5600,CONT_DIF_N,*
-V 2900,5100,CONT_DIF_N,*
-V 1100,3600,CONT_DIF_N,*
-V 1100,4000,CONT_DIF_N,*
-V 1100,4400,CONT_DIF_N,*
-V 1100,4800,CONT_DIF_N,*
-V 1100,5200,CONT_DIF_N,*
-V 1100,5600,CONT_DIF_N,*
-V 2300,3900,CONT_DIF_N,*
-V 15500,4300,CONT_DIF_N,*
-V 15500,3900,CONT_DIF_N,*
-V 15500,3500,CONT_DIF_N,*
-V 14300,5600,CONT_DIF_N,*
-V 14900,5500,CONT_DIF_N,*
-V 14900,5100,CONT_DIF_N,*
-V 14900,4700,CONT_DIF_N,*
-V 14900,4300,CONT_DIF_N,*
-V 16100,4800,CONT_DIF_N,*
-V 16100,5200,CONT_DIF_N,*
-V 16100,5600,CONT_DIF_N,*
-V 14900,3900,CONT_DIF_N,*
-V 14900,3500,CONT_DIF_N,*
-V 15500,5500,CONT_DIF_N,*
-V 15500,5100,CONT_DIF_N,*
-V 15500,4700,CONT_DIF_N,*
-V 14300,5100,CONT_DIF_N,*
-V 16100,3600,CONT_DIF_N,*
-V 16100,4000,CONT_DIF_N,*
-V 16100,4400,CONT_DIF_N,*
-V 500,3600,CONT_BODY_P,*
-V 500,3200,CONT_BODY_P,*
-V 500,2800,CONT_BODY_P,*
-V 500,6400,CONT_BODY_P,*
-V 500,5600,CONT_BODY_P,*
-V 500,5200,CONT_BODY_P,*
-V 500,4800,CONT_BODY_P,*
-V 500,4000,CONT_BODY_P,*
-V 2300,2800,CONT_BODY_P,*
-V 1100,2800,CONT_BODY_P,*
-V 2300,6400,CONT_BODY_P,*
-V 1100,6400,CONT_BODY_P,*
-V 14900,2800,CONT_BODY_P,*
-V 16100,2800,CONT_BODY_P,*
-V 14900,6400,CONT_BODY_P,*
-V 16100,6400,CONT_BODY_P,*
-V 16700,6400,CONT_BODY_P,*
-V 16700,5600,CONT_BODY_P,*
-V 16700,5200,CONT_BODY_P,*
-V 16700,4800,CONT_BODY_P,*
-V 16700,4000,CONT_BODY_P,*
-V 16700,3600,CONT_BODY_P,*
-V 16700,3200,CONT_BODY_P,*
-V 16700,2800,CONT_BODY_P,*
-V 14700,7000,CONT_POLY,*
-V 14400,4500,CONT_POLY,*
-V 2500,7000,CONT_POLY,*
-V 2800,4500,CONT_POLY,*
-V 15500,0,CONT_VIA,*
-V 1700,0,CONT_VIA,*
-V 500,6000,CONT_VIA,*
-V 500,4400,CONT_VIA,*
-B 15200,7000,200,200,CONT_TURN1,*
-B 14000,7000,200,200,CONT_TURN1,*
-V 2100,2300,CONT_VIA,*
-V 15100,2300,CONT_VIA,*
-B 3200,7000,200,200,CONT_TURN1,*
-B 2000,7000,200,200,CONT_TURN1,*
-B 1700,7000,200,200,CONT_TURN1,*
-B 15500,7000,200,200,CONT_TURN1,*
-V 2600,10900,CONT_VIA,*
-V 1400,10900,CONT_VIA,*
-V 2800,900,CONT_VIA,*
-V 2800,1700,CONT_VIA,*
-V 3200,10900,CONT_VIA,*
-V 1400,9400,CONT_VIA,*
-V 1400,7800,CONT_VIA,*
-V 2600,7800,CONT_VIA,*
-V 2600,9400,CONT_VIA,*
-V 800,7800,CONT_VIA,*
-V 800,9400,CONT_VIA,*
-V 2300,6000,CONT_VIA,*
-V 2300,3200,CONT_VIA,*
-V 1100,3200,CONT_VIA,*
-V 1100,6000,CONT_VIA,*
-V 800,10600,CONT_VIA,*
-V 14400,1700,CONT_VIA,*
-V 14000,10900,CONT_VIA,*
-V 14600,10900,CONT_VIA,*
-V 15800,10900,CONT_VIA,*
-V 14400,900,CONT_VIA,*
-V 15800,9400,CONT_VIA,*
-V 15800,7800,CONT_VIA,*
-V 14600,7800,CONT_VIA,*
-V 14600,9400,CONT_VIA,*
-V 16400,7800,CONT_VIA,*
-V 16400,9400,CONT_VIA,*
-V 16100,3200,CONT_VIA,*
-V 16100,6000,CONT_VIA,*
-V 14900,6000,CONT_VIA,*
-V 16700,4400,CONT_VIA,*
-V 14900,3200,CONT_VIA,*
-V 16400,10600,CONT_VIA,*
-V 16700,6000,CONT_VIA,*
-B 8600,4700,10000,4000,CONT_VIA,*
-V 1500,2300,CONT_VIA,*
-V 15700,2300,CONT_VIA,*
-EOF
diff --git a/alliance/share/cells/padlib/pck_sp.al b/alliance/share/cells/padlib/pck_sp.al
deleted file mode 100644
index f2988375..00000000
--- a/alliance/share/cells/padlib/pck_sp.al
+++ /dev/null
@@ -1,56 +0,0 @@
-V ALLIANCE : 4
-H pck_sp,L,23/ 2/95
-C pad,UNKNOWN,EXTERNAL,2
-C ck,UNKNOWN,EXTERNAL,1
-C vdde,UNKNOWN,EXTERNAL,3
-C vddi,UNKNOWN,EXTERNAL,4
-C vsse,UNKNOWN,EXTERNAL,5
-C vssi,UNKNOWN,EXTERNAL,6
-T N,1,27,6,2,7,0,0,0,0,147,29
-T N,1,27,7,2,6,0,0,0,0,141,29
-T N,1,27,7,2,6,0,0,0,0,153,29
-T N,1,27,7,2,6,0,0,0,0,129,29
-T N,1,27,6,2,7,0,0,0,0,123,29
-T N,1,27,6,2,7,0,0,0,0,135,29
-T N,1,27,6,2,7,0,0,0,0,111,29
-T N,1,27,7,2,6,0,0,0,0,117,29
-T N,1,27,7,2,6,0,0,0,0,105,29
-T N,1,27,6,2,7,0,0,0,0,99,29
-T N,1,27,7,2,6,0,0,0,0,93,29
-T N,1,27,6,2,7,0,0,0,0,87,29
-T N,1,27,1,7,6,0,0,0,0,52,29
-T N,1,27,6,7,1,0,0,0,0,46,29
-T N,1,27,1,7,6,0,0,0,0,28,29
-T N,1,27,1,7,6,0,0,0,0,40,29
-T N,1,27,6,7,1,0,0,0,0,34,29
-T N,1,27,6,7,1,0,0,0,0,70,29
-T N,1,27,1,7,6,0,0,0,0,64,29
-T N,1,27,6,7,1,0,0,0,0,58,29
-T N,1,35,2,5,5,0,0,0,0,73,273
-T N,1,35,5,5,2,0,0,0,0,79,273
-T N,1,35,2,5,5,0,0,0,0,85,273
-T N,1,35,5,5,2,0,0,0,0,91,273
-T P,1,27,7,2,4,0,0,0,0,105,80
-T P,1,27,4,2,7,0,0,0,0,99,80
-T P,1,27,7,2,4,0,0,0,0,93,80
-T P,1,27,4,2,7,0,0,0,0,87,80
-T P,1,57,4,7,1,0,0,0,0,70,95
-T P,1,57,4,7,1,0,0,0,0,46,95
-T P,1,57,1,7,4,0,0,0,0,52,95
-T P,1,57,4,7,1,0,0,0,0,58,95
-T P,1,57,1,7,4,0,0,0,0,64,95
-T P,1,57,1,7,4,0,0,0,0,28,95
-T P,1,57,4,7,1,0,0,0,0,34,95
-T P,1,57,1,7,4,0,0,0,0,40,95
-T P,1,80,2,3,3,0,0,0,0,73,188.5
-T P,1,80,3,3,2,0,0,0,0,79,188.5
-T P,1,80,2,3,3,0,0,0,0,85,188.5
-T P,1,80,3,3,2,0,0,0,0,91,188.5
-S 7,INTERNAL,0,mbk_sig3
-S 6,EXTERNAL,0,vssi
-S 5,EXTERNAL,0,vsse
-S 4,EXTERNAL,0,vddi
-S 3,EXTERNAL,0,vdde
-S 2,EXTERNAL,0,pad
-S 1,EXTERNAL,0,ck
-EOF
diff --git a/alliance/share/cells/padlib/pck_sp.ap b/alliance/share/cells/padlib/pck_sp.ap
deleted file mode 100644
index a98320d6..00000000
--- a/alliance/share/cells/padlib/pck_sp.ap
+++ /dev/null
@@ -1,17 +0,0 @@
-V ALLIANCE : 3
-H pck_sp,P,30/ 0/95
-A 3,1,175,501
-C 3,48,40,vssi,0,WEST,ALU2
-C 3,92,40,vddi,0,WEST,ALU2
-C 3,14,12,ck,0,WEST,ALU2
-C 175,14,12,ck,1,EAST,ALU2
-C 175,48,40,vssi,1,EAST,ALU2
-C 175,92,40,vddi,1,EAST,ALU2
-C 175,176,120,vdde,1,EAST,ALU2
-C 175,304,120,vsse,1,EAST,ALU2
-C 3,304,120,vsse,0,WEST,ALU2
-C 3,176,120,vdde,0,WEST,ALU2
-C 91,501,1,pad,0,NORTH,ALU1
-I 3,1,palck_sp,log,NOSYM
-I 3,364,padreal,pad,NOSYM
-EOF
diff --git a/alliance/share/cells/padlib/pck_sp.vbe b/alliance/share/cells/padlib/pck_sp.vbe
deleted file mode 100644
index f989fea0..00000000
--- a/alliance/share/cells/padlib/pck_sp.vbe
+++ /dev/null
@@ -1,38 +0,0 @@
--- VHDL data flow description generated from `pck_sp`
---		date : Thu Feb 23 17:05:59 1995
-
-
--- Entity Declaration
-
-ENTITY pck_sp IS
-  GENERIC (
-    CONSTANT area : NATURAL := 86000;	-- area
-    CONSTANT cin_pad : NATURAL := 1326;	-- cin_pad
-    CONSTANT tpll_pad : NATURAL := 1443;	-- tpll_pad
-    CONSTANT rdown_pad : NATURAL := 58;	-- rdown_pad
-    CONSTANT tphh_pad : NATURAL := 228;	-- tphh_pad
-    CONSTANT rup_pad : NATURAL := 68	-- rup_pad
-  );
-  PORT (
-  pad : in BIT;	-- pad
-  ck : out BIT;	-- ck
-  vdde : in BIT;	-- vdde
-  vddi : in BIT;	-- vddi
-  vsse : in BIT;	-- vsse
-  vssi : in BIT	-- vssi
-  );
-END pck_sp;
-
-
--- Architecture Declaration
-
-ARCHITECTURE behaviour_data_flow OF pck_sp IS
-
-BEGIN
-  ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1')
-    REPORT "power supply is missing on pck_sp"
-    SEVERITY WARNING;
-
-
-ck <= pad;
-END;
diff --git a/alliance/share/cells/padlib/pi_sp.al b/alliance/share/cells/padlib/pi_sp.al
deleted file mode 100644
index fff951fc..00000000
--- a/alliance/share/cells/padlib/pi_sp.al
+++ /dev/null
@@ -1,34 +0,0 @@
-V ALLIANCE : 4
-H pi_sp,L,23/ 2/95
-C pad,UNKNOWN,EXTERNAL,2
-C t,UNKNOWN,EXTERNAL,3
-C ck,UNKNOWN,EXTERNAL,1
-C vdde,UNKNOWN,EXTERNAL,4
-C vddi,UNKNOWN,EXTERNAL,5
-C vsse,UNKNOWN,EXTERNAL,6
-C vssi,UNKNOWN,EXTERNAL,7
-T N,1,27,3,8,7,0,0,0,0,88,29
-T N,1,27,7,8,3,0,0,0,0,94,29
-T N,1,27,7,2,8,0,0,0,0,111,29
-T N,1,27,8,2,7,0,0,0,0,117,29
-T N,1,27,7,2,8,0,0,0,0,123,29
-T N,1,35,6,6,2,0,0,0,0,97,273
-T N,1,35,2,6,6,0,0,0,0,91,273
-T N,1,35,6,6,2,0,0,0,0,85,273
-T N,1,35,2,6,6,0,0,0,0,79,273
-T P,1,57,5,8,3,0,0,0,0,94,95
-T P,1,57,3,8,5,0,0,0,0,88,95
-T P,1,27,5,2,8,0,0,0,0,111,80
-T P,1,80,4,4,2,0,0,0,0,97,188.5
-T P,1,80,2,4,4,0,0,0,0,91,188.5
-T P,1,80,4,4,2,0,0,0,0,85,188.5
-T P,1,80,2,4,4,0,0,0,0,79,188.5
-S 8,INTERNAL,0,mbk_sig4
-S 7,EXTERNAL,0,vssi
-S 6,EXTERNAL,0,vsse
-S 5,EXTERNAL,0,vddi
-S 4,EXTERNAL,0,vdde
-S 3,EXTERNAL,0,t
-S 2,EXTERNAL,0,pad
-S 1,EXTERNAL,0,ck
-EOF
diff --git a/alliance/share/cells/padlib/pi_sp.ap b/alliance/share/cells/padlib/pi_sp.ap
deleted file mode 100644
index 5ed67aa0..00000000
--- a/alliance/share/cells/padlib/pi_sp.ap
+++ /dev/null
@@ -1,19 +0,0 @@
-V ALLIANCE : 3
-H pi_sp,P,30/ 0/95
-A 9,1,181,501
-C 91,1,2,t,1,SOUTH,ALU2
-C 91,1,2,t,0,SOUTH,ALU1
-C 9,14,12,ck,0,WEST,ALU2
-C 181,14,12,ck,1,EAST,ALU2
-C 181,48,40,vssi,1,EAST,ALU2
-C 181,92,40,vddi,1,EAST,ALU2
-C 181,176,120,vdde,1,EAST,ALU2
-C 9,304,120,vsse,0,WEST,ALU2
-C 181,304,120,vsse,1,EAST,ALU2
-C 9,176,120,vdde,0,WEST,ALU2
-C 9,92,40,vddi,0,WEST,ALU2
-C 9,48,40,vssi,0,WEST,ALU2
-C 97,501,1,pad,0,NORTH,ALU1
-I 9,364,padreal,pad,NOSYM
-I 9,1,pali_sp,log,NOSYM
-EOF
diff --git a/alliance/share/cells/padlib/pi_sp.vbe b/alliance/share/cells/padlib/pi_sp.vbe
deleted file mode 100644
index 9791020d..00000000
--- a/alliance/share/cells/padlib/pi_sp.vbe
+++ /dev/null
@@ -1,39 +0,0 @@
--- VHDL data flow description generated from `pi_sp`
---		date : Thu Feb 23 17:06:23 1995
-
-
--- Entity Declaration
-
-ENTITY pi_sp IS
-  GENERIC (
-    CONSTANT area : NATURAL := 86000;	-- area
-    CONSTANT cin_pad : NATURAL := 654;	-- cin_pad
-    CONSTANT tpll_pad : NATURAL := 1487;	-- tpll_pad
-    CONSTANT rdown_pad : NATURAL := 234;	-- rdown_pad
-    CONSTANT tphh_pad : NATURAL := 233;	-- tphh_pad
-    CONSTANT rup_pad : NATURAL := 273	-- rup_pad
-  );
-  PORT (
-  pad : in BIT;	-- pad
-  t : out BIT;	-- t
-  ck : in BIT;	-- ck
-  vdde : in BIT;	-- vdde
-  vddi : in BIT;	-- vddi
-  vsse : in BIT;	-- vsse
-  vssi : in BIT	-- vssi
-  );
-END pi_sp;
-
-
--- Architecture Declaration
-
-ARCHITECTURE behaviour_data_flow OF pi_sp IS
-
-BEGIN
-  ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1')
-    REPORT "power supply is missing on pi_sp"
-    SEVERITY WARNING;
-
-
-t <= pad;
-END;
diff --git a/alliance/share/cells/padlib/piot_sp.al b/alliance/share/cells/padlib/piot_sp.al
deleted file mode 100644
index b530e02c..00000000
--- a/alliance/share/cells/padlib/piot_sp.al
+++ /dev/null
@@ -1,118 +0,0 @@
-V ALLIANCE : 4
-H piot_sp,L,23/ 2/95
-C i,UNKNOWN,EXTERNAL,3
-C b,UNKNOWN,EXTERNAL,1
-C t,UNKNOWN,EXTERNAL,5
-C pad,UNKNOWN,EXTERNAL,4
-C ck,UNKNOWN,EXTERNAL,2
-C vdde,UNKNOWN,EXTERNAL,6
-C vddi,UNKNOWN,EXTERNAL,7
-C vsse,UNKNOWN,EXTERNAL,8
-C vssi,UNKNOWN,EXTERNAL,9
-T N,1,10,9,17,16,0,0,0,0,149,30.5
-T N,1,10,17,1,9,0,0,0,0,155,30.5
-T N,1,29,14,16,15,0,0,0,0,119,20
-T N,1,29,15,16,14,0,0,0,0,125,20
-T N,1,29,14,16,15,0,0,0,0,131,20
-T N,1,29,15,16,14,0,0,0,0,137,20
-T N,1,30,9,13,15,0,0,0,0,83,20.5
-T N,1,30,15,13,9,0,0,0,0,77,20.5
-T N,1,30,9,13,15,0,0,0,0,71,20.5
-T N,1,30,15,13,9,0,0,0,0,65,20.5
-T N,1,30,9,12,13,0,0,0,0,59,20.5
-T N,1,30,15,17,9,0,0,0,0,89,20.5
-T N,1,30,9,17,15,0,0,0,0,107,20.5
-T N,1,30,12,3,9,0,0,0,0,47,20.5
-T N,1,30,15,17,9,0,0,0,0,101,20.5
-T N,1,30,9,17,15,0,0,0,0,95,20.5
-T N,1,30,9,4,11,0,0,0,0,29,20.5
-T N,1,30,5,11,9,0,0,0,0,35,20.5
-T N,1,30,9,11,5,0,0,0,0,41,20.5
-T N,1,30,9,4,11,0,0,0,0,17,20.5
-T N,1,30,11,4,9,0,0,0,0,23,20.5
-T N,1,35,4,15,8,0,0,0,0,137,265
-T N,1,35,8,15,4,0,0,0,0,143,265
-T N,1,35,4,15,8,0,0,0,0,149,265
-T N,1,35,8,15,4,0,0,0,0,155,265
-T N,1,35,4,15,8,0,0,0,0,113,265
-T N,1,35,8,15,4,0,0,0,0,119,265
-T N,1,35,4,15,8,0,0,0,0,125,265
-T N,1,35,8,15,4,0,0,0,0,131,265
-T N,1,35,4,15,8,0,0,0,0,89,265
-T N,1,35,8,15,4,0,0,0,0,95,265
-T N,1,35,4,15,8,0,0,0,0,101,265
-T N,1,35,8,15,4,0,0,0,0,107,265
-T N,1,35,4,15,8,0,0,0,0,65,265
-T N,1,35,8,15,4,0,0,0,0,71,265
-T N,1,35,4,15,8,0,0,0,0,77,265
-T N,1,35,8,15,4,0,0,0,0,83,265
-T N,1,35,4,15,8,0,0,0,0,41,265
-T N,1,35,8,15,4,0,0,0,0,47,265
-T N,1,35,4,15,8,0,0,0,0,53,265
-T N,1,35,8,15,4,0,0,0,0,59,265
-T N,1,35,8,15,4,0,0,0,0,35,265
-T N,1,35,4,15,8,0,0,0,0,29,265
-T N,1,35,8,15,4,0,0,0,0,23,265
-T N,1,35,4,15,8,0,0,0,0,17,265
-T P,1,59,15,17,14,0,0,0,0,131,86
-T P,1,59,14,17,15,0,0,0,0,137,86
-T P,1,60,14,13,7,0,0,0,0,77,85.5
-T P,1,59,15,17,14,0,0,0,0,119,86
-T P,1,59,14,17,15,0,0,0,0,125,86
-T P,1,60,7,13,14,0,0,0,0,83,85.5
-T P,1,60,7,13,14,0,0,0,0,71,85.5
-T P,1,60,14,13,7,0,0,0,0,65,85.5
-T P,1,60,7,12,13,0,0,0,0,59,85.5
-T P,1,60,14,16,7,0,0,0,0,101,85.5
-T P,1,60,7,16,14,0,0,0,0,95,85.5
-T P,1,60,14,16,7,0,0,0,0,89,85.5
-T P,1,60,7,11,5,0,0,0,0,41,85.5
-T P,1,60,12,3,7,0,0,0,0,47,85.5
-T P,1,60,7,16,14,0,0,0,0,107,85.5
-T P,40,3,7,9,4,0,0,0,0,14,91
-T P,1,30,7,4,11,0,0,0,0,29,70.5
-T P,1,60,5,11,7,0,0,0,0,35,85.5
-T P,1,20,7,17,16,0,0,0,0,149,66.5
-T P,1,20,17,1,7,0,0,0,0,155,66.5
-T P,1,80,4,14,6,0,0,0,0,137,180.5
-T P,1,80,6,14,4,0,0,0,0,143,180.5
-T P,1,80,4,14,6,0,0,0,0,149,180.5
-T P,1,80,6,14,4,0,0,0,0,155,180.5
-T P,1,80,4,14,6,0,0,0,0,113,180.5
-T P,1,80,6,14,4,0,0,0,0,119,180.5
-T P,1,80,4,14,6,0,0,0,0,125,180.5
-T P,1,80,6,14,4,0,0,0,0,131,180.5
-T P,1,80,4,14,6,0,0,0,0,89,180.5
-T P,1,80,6,14,4,0,0,0,0,95,180.5
-T P,1,80,4,14,6,0,0,0,0,101,180.5
-T P,1,80,6,14,4,0,0,0,0,107,180.5
-T P,1,80,4,14,6,0,0,0,0,65,180.5
-T P,1,80,6,14,4,0,0,0,0,71,180.5
-T P,1,80,4,14,6,0,0,0,0,77,180.5
-T P,1,80,6,14,4,0,0,0,0,83,180.5
-T P,1,80,4,14,6,0,0,0,0,41,180.5
-T P,1,80,6,14,4,0,0,0,0,47,180.5
-T P,1,80,4,14,6,0,0,0,0,53,180.5
-T P,1,80,6,14,4,0,0,0,0,59,180.5
-T P,1,80,6,14,4,0,0,0,0,35,180.5
-T P,1,80,4,14,6,0,0,0,0,29,180.5
-T P,1,80,6,14,4,0,0,0,0,23,180.5
-T P,1,80,4,14,6,0,0,0,0,17,180.5
-S 17,INTERNAL,0,mbk_sig10
-S 16,INTERNAL,0,mbk_sig12
-S 15,INTERNAL,0,mbk_sig9
-S 14,INTERNAL,0,mbk_sig11
-S 13,INTERNAL,0,mbk_sig6
-S 12,INTERNAL,0,mbk_sig7
-S 11,INTERNAL,0,mbk_sig2
-S 10,INTERNAL,0,mbk_sig15
-S 9,EXTERNAL,0,vssi
-S 8,EXTERNAL,0,vsse
-S 7,EXTERNAL,0,vddi
-S 6,EXTERNAL,0,vdde
-S 5,EXTERNAL,0,t
-S 4,EXTERNAL,0,pad
-S 3,EXTERNAL,0,i
-S 2,EXTERNAL,0,ck
-S 1,EXTERNAL,0,b
-EOF
diff --git a/alliance/share/cells/padlib/piot_sp.ap b/alliance/share/cells/padlib/piot_sp.ap
deleted file mode 100644
index 9e1d31ee..00000000
--- a/alliance/share/cells/padlib/piot_sp.ap
+++ /dev/null
@@ -1,23 +0,0 @@
-V ALLIANCE : 3
-H piot_sp,P,23/ 1/95
-A 0,-7,172,493
-C 157,-7,2,b,2,SOUTH,ALU1
-C 157,-7,2,b,3,SOUTH,ALU2
-C 49,-7,2,i,2,SOUTH,ALU1
-C 38,-7,2,t,2,SOUTH,ALU1
-C 49,-7,2,i,3,SOUTH,ALU2
-C 38,-7,2,t,3,SOUTH,ALU2
-C 88,493,1,pad,0,NORTH,ALU1
-C 0,296,120,vsse,0,WEST,ALU2
-C 172,296,120,vsse,1,EAST,ALU2
-C 172,6,12,ck,1,EAST,ALU2
-C 172,40,40,vssi,1,EAST,ALU2
-C 172,84,40,vddi,1,EAST,ALU2
-C 172,168,120,vdde,1,EAST,ALU2
-C 0,6,12,ck,0,WEST,ALU2
-C 0,40,40,vssi,0,WEST,ALU2
-C 0,84,40,vddi,0,WEST,ALU2
-C 0,168,120,vdde,0,WEST,ALU2
-I 0,356,padreal,pad,NOSYM
-I 0,-7,paliot_sp,logic,NOSYM
-EOF
diff --git a/alliance/share/cells/padlib/piot_sp.vbe b/alliance/share/cells/padlib/piot_sp.vbe
deleted file mode 100644
index 645ca029..00000000
--- a/alliance/share/cells/padlib/piot_sp.vbe
+++ /dev/null
@@ -1,54 +0,0 @@
--- VHDL data flow description generated from `piot_sp`
---		date : Thu Feb 23 17:07:10 1995
-
-
--- Entity Declaration
-
-ENTITY piot_sp IS
-  GENERIC (
-    CONSTANT area : NATURAL := 86000;	-- area
-    CONSTANT rup : NATURAL := 402;	-- rup
-    CONSTANT rdown : NATURAL := 0	-- rdown
-  );
-  PORT (
-  i : in BIT;	-- i
-  b : in BIT;	-- b
-  t : out BIT;	-- t
-  pad : inout MUX_BIT BUS;	-- pad
-  ck : in BIT;	-- ck
-  vdde : in BIT;	-- vdde
-  vddi : in BIT;	-- vddi
-  vsse : in BIT;	-- vsse
-  vssi : in BIT	-- vssi
-  );
-END piot_sp;
-
-
--- Architecture Declaration
-
-ARCHITECTURE behaviour_data_flow OF piot_sp IS
-  SIGNAL b1 : BIT;		-- b1
-  SIGNAL b2 : BIT;		-- b2
-  SIGNAL b3 : BIT;		-- b3
-  SIGNAL b4 : BIT;		-- b4
-  SIGNAL b5 : BIT;		-- b5
-  SIGNAL b6 : BIT;		-- b6
-
-BEGIN
-  ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1')
-    REPORT "power supply is missing on piot_sp"
-    SEVERITY WARNING;
-
-  b6 <= b5;
-  b5 <= b4;
-  b4 <= b3;
-  b3 <= b2;
-  b2 <= b1;
-  b1 <= b;
-	label0 : BLOCK (b6 = '1')
-	BEGIN
-	pad <= GUARDED i;
-	END BLOCK label0;
-
-t <= pad;
-END;
diff --git a/alliance/share/cells/padlib/piotw_sp.al b/alliance/share/cells/padlib/piotw_sp.al
deleted file mode 100644
index 0e62cb08..00000000
--- a/alliance/share/cells/padlib/piotw_sp.al
+++ /dev/null
@@ -1,94 +0,0 @@
-V ALLIANCE : 4
-H piotw_sp,L,23/ 2/95
-C i,UNKNOWN,EXTERNAL,3
-C b,UNKNOWN,EXTERNAL,1
-C t,UNKNOWN,EXTERNAL,5
-C pad,UNKNOWN,EXTERNAL,4
-C ck,UNKNOWN,EXTERNAL,2
-C vdde,UNKNOWN,EXTERNAL,6
-C vddi,UNKNOWN,EXTERNAL,7
-C vsse,UNKNOWN,EXTERNAL,8
-C vssi,UNKNOWN,EXTERNAL,9
-T N,1,10,9,17,16,0,0,0,0,149,30.5
-T N,1,10,17,1,9,0,0,0,0,155,30.5
-T N,1,29,14,16,15,0,0,0,0,119,20
-T N,1,29,15,16,14,0,0,0,0,125,20
-T N,1,29,14,16,15,0,0,0,0,131,20
-T N,1,29,15,16,14,0,0,0,0,137,20
-T N,1,30,9,13,15,0,0,0,0,83,20.5
-T N,1,30,15,13,9,0,0,0,0,77,20.5
-T N,1,30,9,13,15,0,0,0,0,71,20.5
-T N,1,30,15,13,9,0,0,0,0,65,20.5
-T N,1,30,9,12,13,0,0,0,0,59,20.5
-T N,1,30,15,17,9,0,0,0,0,89,20.5
-T N,1,30,9,17,15,0,0,0,0,107,20.5
-T N,1,30,12,3,9,0,0,0,0,47,20.5
-T N,1,30,15,17,9,0,0,0,0,101,20.5
-T N,1,30,9,17,15,0,0,0,0,95,20.5
-T N,1,30,9,4,11,0,0,0,0,29,20.5
-T N,1,30,5,11,9,0,0,0,0,35,20.5
-T N,1,30,9,11,5,0,0,0,0,41,20.5
-T N,1,30,9,4,11,0,0,0,0,17,20.5
-T N,1,30,11,4,9,0,0,0,0,23,20.5
-T N,1,35,4,15,8,0,0,0,0,92,265
-T N,1,35,8,15,4,0,0,0,0,98,265
-T N,1,35,4,15,8,0,0,0,0,104,265
-T N,1,35,8,15,4,0,0,0,0,110,265
-T N,1,35,4,15,8,0,0,0,0,68,265
-T N,1,35,8,15,4,0,0,0,0,74,265
-T N,1,35,4,15,8,0,0,0,0,80,265
-T N,1,35,8,15,4,0,0,0,0,86,265
-T N,1,35,8,15,4,0,0,0,0,62,265
-T N,1,35,4,15,8,0,0,0,0,56,265
-T N,1,35,8,15,4,0,0,0,0,50,265
-T N,1,35,4,15,8,0,0,0,0,44,265
-T P,1,59,15,17,14,0,0,0,0,131,86
-T P,1,59,14,17,15,0,0,0,0,137,86
-T P,1,60,7,13,14,0,0,0,0,83,85.5
-T P,1,60,14,13,7,0,0,0,0,77,85.5
-T P,1,59,15,17,14,0,0,0,0,119,86
-T P,1,59,14,17,15,0,0,0,0,125,86
-T P,1,60,7,12,13,0,0,0,0,59,85.5
-T P,1,60,7,13,14,0,0,0,0,71,85.5
-T P,1,60,14,13,7,0,0,0,0,65,85.5
-T P,1,60,7,16,14,0,0,0,0,107,85.5
-T P,1,60,14,16,7,0,0,0,0,101,85.5
-T P,1,60,7,16,14,0,0,0,0,95,85.5
-T P,1,60,14,16,7,0,0,0,0,89,85.5
-T P,1,60,5,11,7,0,0,0,0,35,85.5
-T P,1,60,7,11,5,0,0,0,0,41,85.5
-T P,1,60,12,3,7,0,0,0,0,47,85.5
-T P,40,3,7,9,4,0,0,0,0,14,91
-T P,1,30,7,4,11,0,0,0,0,29,70.5
-T P,1,20,7,17,16,0,0,0,0,149,66.5
-T P,1,20,17,1,7,0,0,0,0,155,66.5
-T P,1,80,4,14,6,0,0,0,0,92,180.5
-T P,1,80,6,14,4,0,0,0,0,98,180.5
-T P,1,80,4,14,6,0,0,0,0,104,180.5
-T P,1,80,6,14,4,0,0,0,0,110,180.5
-T P,1,80,4,14,6,0,0,0,0,68,180.5
-T P,1,80,6,14,4,0,0,0,0,74,180.5
-T P,1,80,4,14,6,0,0,0,0,80,180.5
-T P,1,80,6,14,4,0,0,0,0,86,180.5
-T P,1,80,6,14,4,0,0,0,0,62,180.5
-T P,1,80,4,14,6,0,0,0,0,56,180.5
-T P,1,80,6,14,4,0,0,0,0,50,180.5
-T P,1,80,4,14,6,0,0,0,0,44,180.5
-S 17,INTERNAL,0,mbk_sig10
-S 16,INTERNAL,0,mbk_sig12
-S 15,INTERNAL,0,mbk_sig9
-S 14,INTERNAL,0,mbk_sig11
-S 13,INTERNAL,0,mbk_sig6
-S 12,INTERNAL,0,mbk_sig7
-S 11,INTERNAL,0,mbk_sig2
-S 10,INTERNAL,0,mbk_sig15
-S 9,EXTERNAL,0,vssi
-S 8,EXTERNAL,0,vsse
-S 7,EXTERNAL,0,vddi
-S 6,EXTERNAL,0,vdde
-S 5,EXTERNAL,0,t
-S 4,EXTERNAL,0,pad
-S 3,EXTERNAL,0,i
-S 2,EXTERNAL,0,ck
-S 1,EXTERNAL,0,b
-EOF
diff --git a/alliance/share/cells/padlib/piotw_sp.ap b/alliance/share/cells/padlib/piotw_sp.ap
deleted file mode 100644
index 6ae120d9..00000000
--- a/alliance/share/cells/padlib/piotw_sp.ap
+++ /dev/null
@@ -1,23 +0,0 @@
-V ALLIANCE : 3
-H piotw_sp,P,23/ 1/95
-A 0,-7,172,493
-C 157,-7,2,b,2,SOUTH,ALU1
-C 157,-7,2,b,3,SOUTH,ALU2
-C 49,-7,2,i,2,SOUTH,ALU1
-C 49,-7,2,i,3,SOUTH,ALU2
-C 38,-7,2,t,2,SOUTH,ALU1
-C 38,-7,2,t,3,SOUTH,ALU2
-C 88,493,1,pad,0,NORTH,ALU1
-C 172,296,120,vsse,1,EAST,ALU2
-C 0,296,120,vsse,0,WEST,ALU2
-C 0,168,120,vdde,0,WEST,ALU2
-C 0,84,40,vddi,0,WEST,ALU2
-C 0,40,40,vssi,0,WEST,ALU2
-C 0,6,12,ck,0,WEST,ALU2
-C 172,168,120,vdde,1,EAST,ALU2
-C 172,84,40,vddi,1,EAST,ALU2
-C 172,40,40,vssi,1,EAST,ALU2
-C 172,6,12,ck,1,EAST,ALU2
-I 0,356,padreal,pad,NOSYM
-I 0,-7,paliotw_sp,logic,NOSYM
-EOF
diff --git a/alliance/share/cells/padlib/piotw_sp.vbe b/alliance/share/cells/padlib/piotw_sp.vbe
deleted file mode 100644
index 4dcd59df..00000000
--- a/alliance/share/cells/padlib/piotw_sp.vbe
+++ /dev/null
@@ -1,54 +0,0 @@
--- VHDL data flow description generated from `piotw_sp`
---		date : Thu Feb 23 17:07:47 1995
-
-
--- Entity Declaration
-
-ENTITY piotw_sp IS
-  GENERIC (
-    CONSTANT area : NATURAL := 86000;	-- area
-    CONSTANT rup : NATURAL := 402;	-- rup
-    CONSTANT rdown : NATURAL := 0	-- rdown
-  );
-  PORT (
-  i : in BIT;	-- i
-  b : in BIT;	-- b
-  t : out BIT;	-- t
-  pad : inout MUX_BIT BUS;	-- pad
-  ck : in BIT;	-- ck
-  vdde : in BIT;	-- vdde
-  vddi : in BIT;	-- vddi
-  vsse : in BIT;	-- vsse
-  vssi : in BIT	-- vssi
-  );
-END piotw_sp;
-
-
--- Architecture Declaration
-
-ARCHITECTURE behaviour_data_flow OF piotw_sp IS
-  SIGNAL b1 : BIT;		-- b1
-  SIGNAL b2 : BIT;		-- b2
-  SIGNAL b3 : BIT;		-- b3
-  SIGNAL b4 : BIT;		-- b4
-  SIGNAL b5 : BIT;		-- b5
-  SIGNAL b6 : BIT;		-- b6
-
-BEGIN
-  ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1')
-    REPORT "power supply is missing on piotw_sp"
-    SEVERITY WARNING;
-
-  b6 <= b5;
-  b5 <= b4;
-  b4 <= b3;
-  b3 <= b2;
-  b2 <= b1;
-  b1 <= b;
-	label0 : BLOCK (b6 = '1')
-	BEGIN
-	pad <= GUARDED i;
-	END BLOCK label0;
-
-t <= pad;
-END;
diff --git a/alliance/share/cells/padlib/po_sp.al b/alliance/share/cells/padlib/po_sp.al
deleted file mode 100644
index dc58d26d..00000000
--- a/alliance/share/cells/padlib/po_sp.al
+++ /dev/null
@@ -1,80 +0,0 @@
-V ALLIANCE : 4
-H po_sp,L,23/ 2/95
-C i,UNKNOWN,EXTERNAL,2
-C pad,UNKNOWN,EXTERNAL,3
-C ck,UNKNOWN,EXTERNAL,1
-C vdde,UNKNOWN,EXTERNAL,4
-C vddi,UNKNOWN,EXTERNAL,5
-C vsse,UNKNOWN,EXTERNAL,6
-C vssi,UNKNOWN,EXTERNAL,7
-T N,1,30,10,2,7,0,0,0,0,45,20.5
-T N,1,30,7,10,9,0,0,0,0,57,20.5
-T N,1,30,8,9,7,0,0,0,0,63,20.5
-T N,1,30,7,9,8,0,0,0,0,69,20.5
-T N,1,30,8,9,7,0,0,0,0,75,20.5
-T N,1,30,7,9,8,0,0,0,0,81,20.5
-T N,1,35,3,8,6,0,0,0,0,17,265
-T N,1,35,6,8,3,0,0,0,0,23,265
-T N,1,35,3,8,6,0,0,0,0,29,265
-T N,1,35,6,8,3,0,0,0,0,35,265
-T N,1,35,3,8,6,0,0,0,0,41,265
-T N,1,35,6,8,3,0,0,0,0,47,265
-T N,1,35,3,8,6,0,0,0,0,53,265
-T N,1,35,6,8,3,0,0,0,0,59,265
-T N,1,35,3,8,6,0,0,0,0,65,265
-T N,1,35,6,8,3,0,0,0,0,71,265
-T N,1,35,3,8,6,0,0,0,0,77,265
-T N,1,35,6,8,3,0,0,0,0,83,265
-T N,1,35,3,8,6,0,0,0,0,89,265
-T N,1,35,6,8,3,0,0,0,0,95,265
-T N,1,35,3,8,6,0,0,0,0,101,265
-T N,1,35,6,8,3,0,0,0,0,107,265
-T N,1,35,3,8,6,0,0,0,0,113,265
-T N,1,35,6,8,3,0,0,0,0,119,265
-T N,1,35,3,8,6,0,0,0,0,125,265
-T N,1,35,6,8,3,0,0,0,0,131,265
-T N,1,35,3,8,6,0,0,0,0,137,265
-T N,1,35,6,8,3,0,0,0,0,143,265
-T N,1,35,3,8,6,0,0,0,0,149,265
-T N,1,35,6,8,3,0,0,0,0,155,265
-T P,1,60,10,2,5,0,0,0,0,45,85.5
-T P,1,60,5,9,8,0,0,0,0,69,85.5
-T P,1,60,5,10,9,0,0,0,0,57,85.5
-T P,1,60,8,9,5,0,0,0,0,63,85.5
-T P,1,60,8,9,5,0,0,0,0,75,85.5
-T P,1,60,5,9,8,0,0,0,0,81,85.5
-T P,1,80,3,8,4,0,0,0,0,17,180.5
-T P,1,80,4,8,3,0,0,0,0,23,180.5
-T P,1,80,3,8,4,0,0,0,0,29,180.5
-T P,1,80,4,8,3,0,0,0,0,35,180.5
-T P,1,80,3,8,4,0,0,0,0,41,180.5
-T P,1,80,4,8,3,0,0,0,0,47,180.5
-T P,1,80,3,8,4,0,0,0,0,53,180.5
-T P,1,80,4,8,3,0,0,0,0,59,180.5
-T P,1,80,3,8,4,0,0,0,0,65,180.5
-T P,1,80,4,8,3,0,0,0,0,71,180.5
-T P,1,80,3,8,4,0,0,0,0,77,180.5
-T P,1,80,4,8,3,0,0,0,0,83,180.5
-T P,1,80,3,8,4,0,0,0,0,89,180.5
-T P,1,80,4,8,3,0,0,0,0,95,180.5
-T P,1,80,3,8,4,0,0,0,0,101,180.5
-T P,1,80,4,8,3,0,0,0,0,107,180.5
-T P,1,80,3,8,4,0,0,0,0,113,180.5
-T P,1,80,4,8,3,0,0,0,0,119,180.5
-T P,1,80,3,8,4,0,0,0,0,125,180.5
-T P,1,80,4,8,3,0,0,0,0,131,180.5
-T P,1,80,3,8,4,0,0,0,0,137,180.5
-T P,1,80,4,8,3,0,0,0,0,143,180.5
-T P,1,80,3,8,4,0,0,0,0,149,180.5
-T P,1,80,4,8,3,0,0,0,0,155,180.5
-S 10,INTERNAL,0,mbk_sig3
-S 9,INTERNAL,0,mbk_sig4
-S 8,INTERNAL,0,mbk_sig6
-S 7,EXTERNAL,0,vssi
-S 6,EXTERNAL,0,vsse
-S 5,EXTERNAL,0,vddi
-S 4,EXTERNAL,0,vdde
-S 3,EXTERNAL,0,pad
-S 2,EXTERNAL,0,i
-S 1,EXTERNAL,0,ck
-EOF
diff --git a/alliance/share/cells/padlib/po_sp.ap b/alliance/share/cells/padlib/po_sp.ap
deleted file mode 100644
index d6f6cc34..00000000
--- a/alliance/share/cells/padlib/po_sp.ap
+++ /dev/null
@@ -1,19 +0,0 @@
-V ALLIANCE : 3
-H po_sp,P,30/ 0/95
-A 0,-7,172,493
-C 172,6,12,ck,1,EAST,ALU2
-C 172,40,40,vssi,1,EAST,ALU2
-C 172,84,40,vddi,1,EAST,ALU2
-C 172,168,120,vdde,1,EAST,ALU2
-C 0,168,120,vdde,0,WEST,ALU2
-C 0,84,40,vddi,0,WEST,ALU2
-C 0,6,12,ck,0,WEST,ALU2
-C 0,40,40,vssi,0,WEST,ALU2
-C 47,-7,2,i,1,SOUTH,ALU2
-C 47,-7,2,i,0,SOUTH,ALU1
-C 88,493,1,pad,0,NORTH,ALU1
-C 172,296,120,vsse,1,EAST,ALU2
-C 0,296,120,vsse,0,WEST,ALU2
-I 0,-7,palo_sp,logic,NOSYM
-I 0,356,padreal,pad,NOSYM
-EOF
diff --git a/alliance/share/cells/padlib/po_sp.vbe b/alliance/share/cells/padlib/po_sp.vbe
deleted file mode 100644
index b646800d..00000000
--- a/alliance/share/cells/padlib/po_sp.vbe
+++ /dev/null
@@ -1,39 +0,0 @@
--- VHDL data flow description generated from `po_sp`
---		date : Thu Feb 23 17:08:20 1995
-
-
--- Entity Declaration
-
-ENTITY po_sp IS
-  GENERIC (
-    CONSTANT area : NATURAL := 86000;	-- area
-    CONSTANT cin_i : NATURAL := 191;	-- cin_i
-    CONSTANT tpll_i : NATURAL := 2176;	-- tpll_i
-    CONSTANT rdown_i : NATURAL := 15;	-- rdown_i
-    CONSTANT tphh_i : NATURAL := 2032;	-- tphh_i
-    CONSTANT rup_i : NATURAL := 16	-- rup_i
-  );
-  PORT (
-  i : in BIT;	-- i
-  pad : out BIT;	-- pad
-  ck : in BIT;	-- ck
-  vdde : in BIT;	-- vdde
-  vddi : in BIT;	-- vddi
-  vsse : in BIT;	-- vsse
-  vssi : in BIT	-- vssi
-  );
-END po_sp;
-
-
--- Architecture Declaration
-
-ARCHITECTURE behaviour_data_flow OF po_sp IS
-
-BEGIN
-  ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1')
-    REPORT "power supply is missing on po_sp"
-    SEVERITY WARNING;
-
-
-pad <= i;
-END;
diff --git a/alliance/share/cells/padlib/pot_sp.al b/alliance/share/cells/padlib/pot_sp.al
deleted file mode 100644
index 814c64f8..00000000
--- a/alliance/share/cells/padlib/pot_sp.al
+++ /dev/null
@@ -1,107 +0,0 @@
-V ALLIANCE : 4
-H pot_sp,L,23/ 2/95
-C i,UNKNOWN,EXTERNAL,3
-C b,UNKNOWN,EXTERNAL,1
-C pad,UNKNOWN,EXTERNAL,4
-C ck,UNKNOWN,EXTERNAL,2
-C vdde,UNKNOWN,EXTERNAL,5
-C vddi,UNKNOWN,EXTERNAL,6
-C vsse,UNKNOWN,EXTERNAL,7
-C vssi,UNKNOWN,EXTERNAL,8
-T N,1,30,15,3,8,0,0,0,0,44,20.5
-T N,1,30,13,14,8,0,0,0,0,98,20.5
-T N,1,30,8,14,13,0,0,0,0,92,20.5
-T N,1,30,13,14,8,0,0,0,0,86,20.5
-T N,1,30,8,14,13,0,0,0,0,104,20.5
-T N,1,30,8,12,13,0,0,0,0,68,20.5
-T N,1,30,13,12,8,0,0,0,0,62,20.5
-T N,1,30,8,15,12,0,0,0,0,56,20.5
-T N,1,30,8,12,13,0,0,0,0,80,20.5
-T N,1,30,13,12,8,0,0,0,0,74,20.5
-T N,1,29,10,11,13,0,0,0,0,116,20
-T N,1,29,13,11,10,0,0,0,0,122,20
-T N,1,29,10,11,13,0,0,0,0,128,20
-T N,1,29,13,11,10,0,0,0,0,134,20
-T N,1,10,14,1,8,0,0,0,0,152,30.5
-T N,1,10,8,14,11,0,0,0,0,146,30.5
-T N,1,35,4,13,7,0,0,0,0,137,265
-T N,1,35,7,13,4,0,0,0,0,143,265
-T N,1,35,4,13,7,0,0,0,0,149,265
-T N,1,35,7,13,4,0,0,0,0,155,265
-T N,1,35,4,13,7,0,0,0,0,113,265
-T N,1,35,7,13,4,0,0,0,0,119,265
-T N,1,35,4,13,7,0,0,0,0,125,265
-T N,1,35,7,13,4,0,0,0,0,131,265
-T N,1,35,4,13,7,0,0,0,0,89,265
-T N,1,35,7,13,4,0,0,0,0,95,265
-T N,1,35,4,13,7,0,0,0,0,101,265
-T N,1,35,7,13,4,0,0,0,0,107,265
-T N,1,35,4,13,7,0,0,0,0,65,265
-T N,1,35,7,13,4,0,0,0,0,71,265
-T N,1,35,4,13,7,0,0,0,0,77,265
-T N,1,35,7,13,4,0,0,0,0,83,265
-T N,1,35,4,13,7,0,0,0,0,41,265
-T N,1,35,7,13,4,0,0,0,0,47,265
-T N,1,35,4,13,7,0,0,0,0,53,265
-T N,1,35,7,13,4,0,0,0,0,59,265
-T N,1,35,7,13,4,0,0,0,0,35,265
-T N,1,35,4,13,7,0,0,0,0,29,265
-T N,1,35,7,13,4,0,0,0,0,23,265
-T N,1,35,4,13,7,0,0,0,0,17,265
-T P,40,3,6,8,4,0,0,0,0,27,91
-T P,1,20,6,14,11,0,0,0,0,146,66.5
-T P,1,20,14,1,6,0,0,0,0,152,66.5
-T P,1,60,15,3,6,0,0,0,0,44,85.5
-T P,1,60,6,11,10,0,0,0,0,104,85.5
-T P,1,60,10,11,6,0,0,0,0,98,85.5
-T P,1,60,6,11,10,0,0,0,0,92,85.5
-T P,1,60,10,11,6,0,0,0,0,86,85.5
-T P,1,60,6,12,10,0,0,0,0,68,85.5
-T P,1,60,10,12,6,0,0,0,0,62,85.5
-T P,1,60,6,15,12,0,0,0,0,56,85.5
-T P,1,60,6,12,10,0,0,0,0,80,85.5
-T P,1,60,10,12,6,0,0,0,0,74,85.5
-T P,1,59,13,14,10,0,0,0,0,116,86
-T P,1,59,10,14,13,0,0,0,0,122,86
-T P,1,59,13,14,10,0,0,0,0,128,86
-T P,1,59,10,14,13,0,0,0,0,134,86
-T P,1,80,4,10,5,0,0,0,0,137,180.5
-T P,1,80,5,10,4,0,0,0,0,143,180.5
-T P,1,80,4,10,5,0,0,0,0,149,180.5
-T P,1,80,5,10,4,0,0,0,0,155,180.5
-T P,1,80,4,10,5,0,0,0,0,113,180.5
-T P,1,80,5,10,4,0,0,0,0,119,180.5
-T P,1,80,4,10,5,0,0,0,0,125,180.5
-T P,1,80,5,10,4,0,0,0,0,131,180.5
-T P,1,80,4,10,5,0,0,0,0,89,180.5
-T P,1,80,5,10,4,0,0,0,0,95,180.5
-T P,1,80,4,10,5,0,0,0,0,101,180.5
-T P,1,80,5,10,4,0,0,0,0,107,180.5
-T P,1,80,4,10,5,0,0,0,0,65,180.5
-T P,1,80,5,10,4,0,0,0,0,71,180.5
-T P,1,80,4,10,5,0,0,0,0,77,180.5
-T P,1,80,5,10,4,0,0,0,0,83,180.5
-T P,1,80,4,10,5,0,0,0,0,41,180.5
-T P,1,80,5,10,4,0,0,0,0,47,180.5
-T P,1,80,4,10,5,0,0,0,0,53,180.5
-T P,1,80,5,10,4,0,0,0,0,59,180.5
-T P,1,80,5,10,4,0,0,0,0,35,180.5
-T P,1,80,4,10,5,0,0,0,0,29,180.5
-T P,1,80,5,10,4,0,0,0,0,23,180.5
-T P,1,80,4,10,5,0,0,0,0,17,180.5
-S 15,INTERNAL,0,mbk_sig4
-S 14,INTERNAL,0,mbk_sig7
-S 13,INTERNAL,0,mbk_sig6
-S 12,INTERNAL,0,mbk_sig3
-S 11,INTERNAL,0,mbk_sig9
-S 10,INTERNAL,0,mbk_sig8
-S 9,INTERNAL,0,mbk_sig12
-S 8,EXTERNAL,0,vssi
-S 7,EXTERNAL,0,vsse
-S 6,EXTERNAL,0,vddi
-S 5,EXTERNAL,0,vdde
-S 4,EXTERNAL,0,pad
-S 3,EXTERNAL,0,i
-S 2,EXTERNAL,0,ck
-S 1,EXTERNAL,0,b
-EOF
diff --git a/alliance/share/cells/padlib/pot_sp.ap b/alliance/share/cells/padlib/pot_sp.ap
deleted file mode 100644
index f43040f1..00000000
--- a/alliance/share/cells/padlib/pot_sp.ap
+++ /dev/null
@@ -1,21 +0,0 @@
-V ALLIANCE : 3
-H pot_sp,P,30/ 0/95
-A 0,-7,172,493
-C 154,-7,2,b,0,SOUTH,ALU1
-C 154,-7,2,b,1,SOUTH,ALU2
-C 46,-7,2,i,0,SOUTH,ALU1
-C 46,-7,2,i,1,SOUTH,ALU2
-C 0,168,120,vdde,0,WEST,ALU2
-C 0,84,40,vddi,0,WEST,ALU2
-C 0,40,40,vssi,0,WEST,ALU2
-C 0,6,12,ck,0,WEST,ALU2
-C 172,168,120,vdde,1,EAST,ALU2
-C 172,84,40,vddi,1,EAST,ALU2
-C 172,40,40,vssi,1,EAST,ALU2
-C 172,6,12,ck,1,EAST,ALU2
-C 172,296,120,vsse,1,EAST,ALU2
-C 0,296,120,vsse,0,WEST,ALU2
-C 88,493,1,pad,0,NORTH,ALU1
-I 0,-7,palot_sp,logic,NOSYM
-I 0,356,padreal,pad,NOSYM
-EOF
diff --git a/alliance/share/cells/padlib/pot_sp.vbe b/alliance/share/cells/padlib/pot_sp.vbe
deleted file mode 100644
index 578b57bc..00000000
--- a/alliance/share/cells/padlib/pot_sp.vbe
+++ /dev/null
@@ -1,51 +0,0 @@
--- VHDL data flow description generated from `pot_sp`
---		date : Thu Feb 23 17:09:25 1995
-
-
--- Entity Declaration
-
-ENTITY pot_sp IS
-  GENERIC (
-    CONSTANT area : NATURAL := 86000;	-- area
-    CONSTANT rup : NATURAL := 684404;	-- rup
-    CONSTANT rdown : NATURAL := 24	-- rdown
-  );
-  PORT (
-  i : in BIT;	-- i
-  b : in BIT;	-- b
-  pad : out MUX_BIT BUS;	-- pad
-  ck : in BIT;	-- ck
-  vdde : in BIT;	-- vdde
-  vddi : in BIT;	-- vddi
-  vsse : in BIT;	-- vsse
-  vssi : in BIT	-- vssi
-  );
-END pot_sp;
-
-
--- Architecture Declaration
-
-ARCHITECTURE behaviour_data_flow OF pot_sp IS
-  SIGNAL b1 : BIT;		-- b1
-  SIGNAL b2 : BIT;		-- b2
-  SIGNAL b3 : BIT;		-- b3
-  SIGNAL b4 : BIT;		-- b4
-  SIGNAL b5 : BIT;		-- b5
-  SIGNAL b6 : BIT;		-- b6
-
-BEGIN
-  ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1')
-    REPORT "power supply is missing on pot_sp"
-    SEVERITY WARNING;
-
-  b6 <= b5;
-  b5 <= b4;
-  b4 <= b3;
-  b3 <= b2;
-  b2 <= b1;
-  b1 <= b;
-	label0 : BLOCK (b6 = '1')
-	BEGIN
-	pad <= GUARDED i;
-	END BLOCK label0;
-END;
diff --git a/alliance/share/cells/padlib/potw_sp.al b/alliance/share/cells/padlib/potw_sp.al
deleted file mode 100644
index 4eb9a3ee..00000000
--- a/alliance/share/cells/padlib/potw_sp.al
+++ /dev/null
@@ -1,83 +0,0 @@
-V ALLIANCE : 4
-H potw_sp,L,23/ 2/95
-C i,UNKNOWN,EXTERNAL,3
-C b,UNKNOWN,EXTERNAL,1
-C pad,UNKNOWN,EXTERNAL,4
-C ck,UNKNOWN,EXTERNAL,2
-C vdde,UNKNOWN,EXTERNAL,5
-C vddi,UNKNOWN,EXTERNAL,6
-C vsse,UNKNOWN,EXTERNAL,7
-C vssi,UNKNOWN,EXTERNAL,8
-T N,1,10,8,15,14,0,0,0,0,146,30.5
-T N,1,10,15,1,8,0,0,0,0,152,30.5
-T N,1,29,12,14,13,0,0,0,0,134,20
-T N,1,29,13,14,12,0,0,0,0,128,20
-T N,1,29,12,14,13,0,0,0,0,122,20
-T N,1,29,13,14,12,0,0,0,0,116,20
-T N,1,30,12,11,8,0,0,0,0,74,20.5
-T N,1,30,8,11,12,0,0,0,0,80,20.5
-T N,1,30,8,10,11,0,0,0,0,56,20.5
-T N,1,30,12,11,8,0,0,0,0,62,20.5
-T N,1,30,8,11,12,0,0,0,0,68,20.5
-T N,1,30,8,15,12,0,0,0,0,104,20.5
-T N,1,30,12,15,8,0,0,0,0,86,20.5
-T N,1,30,8,15,12,0,0,0,0,92,20.5
-T N,1,30,12,15,8,0,0,0,0,98,20.5
-T N,1,30,10,3,8,0,0,0,0,44,20.5
-T N,1,35,7,12,4,0,0,0,0,62,265
-T N,1,35,4,12,7,0,0,0,0,56,265
-T N,1,35,7,12,4,0,0,0,0,50,265
-T N,1,35,4,12,7,0,0,0,0,44,265
-T N,1,35,4,12,7,0,0,0,0,68,265
-T N,1,35,7,12,4,0,0,0,0,74,265
-T N,1,35,4,12,7,0,0,0,0,80,265
-T N,1,35,7,12,4,0,0,0,0,86,265
-T N,1,35,4,12,7,0,0,0,0,92,265
-T N,1,35,7,12,4,0,0,0,0,98,265
-T N,1,35,4,12,7,0,0,0,0,104,265
-T N,1,35,7,12,4,0,0,0,0,110,265
-T P,1,59,13,15,12,0,0,0,0,134,86
-T P,1,59,12,15,13,0,0,0,0,128,86
-T P,1,59,13,15,12,0,0,0,0,122,86
-T P,1,59,12,15,13,0,0,0,0,116,86
-T P,1,60,13,11,6,0,0,0,0,74,85.5
-T P,1,60,6,11,13,0,0,0,0,80,85.5
-T P,1,60,6,10,11,0,0,0,0,56,85.5
-T P,1,60,13,11,6,0,0,0,0,62,85.5
-T P,1,60,6,11,13,0,0,0,0,68,85.5
-T P,1,60,13,14,6,0,0,0,0,86,85.5
-T P,1,60,6,14,13,0,0,0,0,92,85.5
-T P,1,60,13,14,6,0,0,0,0,98,85.5
-T P,1,60,6,14,13,0,0,0,0,104,85.5
-T P,1,60,10,3,6,0,0,0,0,44,85.5
-T P,1,20,15,1,6,0,0,0,0,152,66.5
-T P,1,20,6,15,14,0,0,0,0,146,66.5
-T P,40,3,6,8,4,0,0,0,0,27,91
-T P,1,80,5,13,4,0,0,0,0,62,180.5
-T P,1,80,4,13,5,0,0,0,0,56,180.5
-T P,1,80,5,13,4,0,0,0,0,50,180.5
-T P,1,80,4,13,5,0,0,0,0,44,180.5
-T P,1,80,4,13,5,0,0,0,0,68,180.5
-T P,1,80,5,13,4,0,0,0,0,74,180.5
-T P,1,80,4,13,5,0,0,0,0,80,180.5
-T P,1,80,5,13,4,0,0,0,0,86,180.5
-T P,1,80,4,13,5,0,0,0,0,92,180.5
-T P,1,80,5,13,4,0,0,0,0,98,180.5
-T P,1,80,4,13,5,0,0,0,0,104,180.5
-T P,1,80,5,13,4,0,0,0,0,110,180.5
-S 15,INTERNAL,0,mbk_sig7
-S 14,INTERNAL,0,mbk_sig9
-S 13,INTERNAL,0,mbk_sig8
-S 12,INTERNAL,0,mbk_sig6
-S 11,INTERNAL,0,mbk_sig4
-S 10,INTERNAL,0,mbk_sig3
-S 9,INTERNAL,0,mbk_sig12
-S 8,EXTERNAL,0,vssi
-S 7,EXTERNAL,0,vsse
-S 6,EXTERNAL,0,vddi
-S 5,EXTERNAL,0,vdde
-S 4,EXTERNAL,0,pad
-S 3,EXTERNAL,0,i
-S 2,EXTERNAL,0,ck
-S 1,EXTERNAL,0,b
-EOF
diff --git a/alliance/share/cells/padlib/potw_sp.ap b/alliance/share/cells/padlib/potw_sp.ap
deleted file mode 100644
index 82e16248..00000000
--- a/alliance/share/cells/padlib/potw_sp.ap
+++ /dev/null
@@ -1,21 +0,0 @@
-V ALLIANCE : 3
-H potw_sp,P,30/ 0/95
-A 0,-7,172,493
-C 154,-7,2,b,0,SOUTH,ALU1
-C 154,-7,2,b,1,SOUTH,ALU2
-C 46,-7,2,i,1,SOUTH,ALU2
-C 46,-7,2,i,0,SOUTH,ALU1
-C 172,6,12,ck,1,EAST,ALU2
-C 172,40,40,vssi,1,EAST,ALU2
-C 172,84,40,vddi,1,EAST,ALU2
-C 172,168,120,vdde,1,EAST,ALU2
-C 0,6,12,ck,0,WEST,ALU2
-C 0,40,40,vssi,0,WEST,ALU2
-C 0,84,40,vddi,0,WEST,ALU2
-C 0,168,120,vdde,0,WEST,ALU2
-C 0,296,120,vsse,0,WEST,ALU2
-C 172,296,120,vsse,1,EAST,ALU2
-C 88,493,1,pad,0,NORTH,ALU1
-I 0,-7,palotw_sp,logic,NOSYM
-I 0,356,padreal,pad,NOSYM
-EOF
diff --git a/alliance/share/cells/padlib/potw_sp.vbe b/alliance/share/cells/padlib/potw_sp.vbe
deleted file mode 100644
index bd7513d3..00000000
--- a/alliance/share/cells/padlib/potw_sp.vbe
+++ /dev/null
@@ -1,51 +0,0 @@
--- VHDL data flow description generated from `potw_sp`
---		date : Thu Feb 23 17:09:58 1995
-
-
--- Entity Declaration
-
-ENTITY potw_sp IS
-  GENERIC (
-    CONSTANT area : NATURAL := 86000;	-- area
-    CONSTANT rup : NATURAL := 684404;	-- rup
-    CONSTANT rdown : NATURAL := 49	-- rdown
-  );
-  PORT (
-  i : in BIT;	-- i
-  b : in BIT;	-- b
-  pad : out MUX_BIT BUS;	-- pad
-  ck : in BIT;	-- ck
-  vdde : in BIT;	-- vdde
-  vddi : in BIT;	-- vddi
-  vsse : in BIT;	-- vsse
-  vssi : in BIT	-- vssi
-  );
-END potw_sp;
-
-
--- Architecture Declaration
-
-ARCHITECTURE behaviour_data_flow OF potw_sp IS
-  SIGNAL b1 : BIT;		-- b1
-  SIGNAL b2 : BIT;		-- b2
-  SIGNAL b3 : BIT;		-- b3
-  SIGNAL b4 : BIT;		-- b4
-  SIGNAL b5 : BIT;		-- b5
-  SIGNAL b6 : BIT;		-- b6
-
-BEGIN
-  ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1')
-    REPORT "power supply is missing on potw_sp"
-    SEVERITY WARNING;
-
-  b6 <= b5;
-  b5 <= b4;
-  b4 <= b3;
-  b3 <= b2;
-  b2 <= b1;
-  b1 <= b;
-	label0 : BLOCK (b6 = '1')
-	BEGIN
-	pad <= GUARDED i;
-	END BLOCK label0;
-END;
diff --git a/alliance/share/cells/padlib/pow_sp.al b/alliance/share/cells/padlib/pow_sp.al
deleted file mode 100644
index 50f28c09..00000000
--- a/alliance/share/cells/padlib/pow_sp.al
+++ /dev/null
@@ -1,56 +0,0 @@
-V ALLIANCE : 4
-H pow_sp,L,23/ 2/95
-C i,UNKNOWN,EXTERNAL,2
-C pad,UNKNOWN,EXTERNAL,3
-C ck,UNKNOWN,EXTERNAL,1
-C vdde,UNKNOWN,EXTERNAL,4
-C vddi,UNKNOWN,EXTERNAL,5
-C vsse,UNKNOWN,EXTERNAL,6
-C vssi,UNKNOWN,EXTERNAL,7
-T N,1,30,7,10,9,0,0,0,0,85,20.5
-T N,1,30,10,2,7,0,0,0,0,73,20.5
-T N,1,30,8,9,7,0,0,0,0,103,20.5
-T N,1,30,7,9,8,0,0,0,0,97,20.5
-T N,1,30,8,9,7,0,0,0,0,91,20.5
-T N,1,30,7,9,8,0,0,0,0,109,20.5
-T N,1,35,3,8,6,0,0,0,0,56,265
-T N,1,35,6,8,3,0,0,0,0,62,265
-T N,1,35,3,8,6,0,0,0,0,68,265
-T N,1,35,6,8,3,0,0,0,0,74,265
-T N,1,35,3,8,6,0,0,0,0,104,265
-T N,1,35,6,8,3,0,0,0,0,110,265
-T N,1,35,3,8,6,0,0,0,0,116,265
-T N,1,35,6,8,3,0,0,0,0,122,265
-T N,1,35,3,8,6,0,0,0,0,80,265
-T N,1,35,6,8,3,0,0,0,0,86,265
-T N,1,35,3,8,6,0,0,0,0,92,265
-T N,1,35,6,8,3,0,0,0,0,98,265
-T P,1,60,5,9,8,0,0,0,0,97,85.5
-T P,1,60,10,2,5,0,0,0,0,73,85.5
-T P,1,60,8,9,5,0,0,0,0,103,85.5
-T P,1,60,8,9,5,0,0,0,0,91,85.5
-T P,1,60,5,10,9,0,0,0,0,85,85.5
-T P,1,60,5,9,8,0,0,0,0,109,85.5
-T P,1,80,3,8,4,0,0,0,0,56,180.5
-T P,1,80,4,8,3,0,0,0,0,62,180.5
-T P,1,80,3,8,4,0,0,0,0,68,180.5
-T P,1,80,4,8,3,0,0,0,0,74,180.5
-T P,1,80,3,8,4,0,0,0,0,104,180.5
-T P,1,80,4,8,3,0,0,0,0,110,180.5
-T P,1,80,3,8,4,0,0,0,0,116,180.5
-T P,1,80,4,8,3,0,0,0,0,122,180.5
-T P,1,80,3,8,4,0,0,0,0,80,180.5
-T P,1,80,4,8,3,0,0,0,0,86,180.5
-T P,1,80,3,8,4,0,0,0,0,92,180.5
-T P,1,80,4,8,3,0,0,0,0,98,180.5
-S 10,INTERNAL,0,mbk_sig5
-S 9,INTERNAL,0,mbk_sig4
-S 8,INTERNAL,0,mbk_sig3
-S 7,EXTERNAL,0,vssi
-S 6,EXTERNAL,0,vsse
-S 5,EXTERNAL,0,vddi
-S 4,EXTERNAL,0,vdde
-S 3,EXTERNAL,0,pad
-S 2,EXTERNAL,0,i
-S 1,EXTERNAL,0,ck
-EOF
diff --git a/alliance/share/cells/padlib/pow_sp.ap b/alliance/share/cells/padlib/pow_sp.ap
deleted file mode 100644
index e9c8e663..00000000
--- a/alliance/share/cells/padlib/pow_sp.ap
+++ /dev/null
@@ -1,19 +0,0 @@
-V ALLIANCE : 3
-H pow_sp,P,30/ 0/95
-A 0,-7,172,493
-C 75,-7,2,i,0,SOUTH,ALU1
-C 75,-7,2,i,1,SOUTH,ALU2
-C 172,6,12,ck,1,EAST,ALU2
-C 172,40,40,vssi,1,EAST,ALU2
-C 172,84,40,vddi,1,EAST,ALU2
-C 172,168,120,vdde,1,EAST,ALU2
-C 0,168,120,vdde,0,WEST,ALU2
-C 0,84,40,vddi,0,WEST,ALU2
-C 0,6,12,ck,0,WEST,ALU2
-C 0,40,40,vssi,0,WEST,ALU2
-C 0,296,120,vsse,0,WEST,ALU2
-C 172,296,120,vsse,1,EAST,ALU2
-C 88,493,1,pad,0,NORTH,ALU1
-I 0,-7,palow_sp,logic,NOSYM
-I 0,356,padreal,pad,NOSYM
-EOF
diff --git a/alliance/share/cells/padlib/pow_sp.vbe b/alliance/share/cells/padlib/pow_sp.vbe
deleted file mode 100644
index ffbb6455..00000000
--- a/alliance/share/cells/padlib/pow_sp.vbe
+++ /dev/null
@@ -1,39 +0,0 @@
--- VHDL data flow description generated from `pow_sp`
---		date : Thu Feb 23 17:08:48 1995
-
-
--- Entity Declaration
-
-ENTITY pow_sp IS
-  GENERIC (
-    CONSTANT area : NATURAL := 86000;	-- area
-    CONSTANT cin_i : NATURAL := 191;	-- cin_i
-    CONSTANT tpll_i : NATURAL := 1777;	-- tpll_i
-    CONSTANT rdown_i : NATURAL := 30;	-- rdown_i
-    CONSTANT tphh_i : NATURAL := 1608;	-- tphh_i
-    CONSTANT rup_i : NATURAL := 32	-- rup_i
-  );
-  PORT (
-  i : in BIT;	-- i
-  pad : out BIT;	-- pad
-  ck : in BIT;	-- ck
-  vdde : in BIT;	-- vdde
-  vddi : in BIT;	-- vddi
-  vsse : in BIT;	-- vsse
-  vssi : in BIT	-- vssi
-  );
-END pow_sp;
-
-
--- Architecture Declaration
-
-ARCHITECTURE behaviour_data_flow OF pow_sp IS
-
-BEGIN
-  ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1')
-    REPORT "power supply is missing on pow_sp"
-    SEVERITY WARNING;
-
-
-pad <= i;
-END;
diff --git a/alliance/share/cells/padlib/pvdde_sp.al b/alliance/share/cells/padlib/pvdde_sp.al
deleted file mode 100644
index 6d26778e..00000000
--- a/alliance/share/cells/padlib/pvdde_sp.al
+++ /dev/null
@@ -1,13 +0,0 @@
-V ALLIANCE : 4
-H pvdde_sp,L,23/ 2/95
-C ck,UNKNOWN,EXTERNAL,1
-C vdde,UNKNOWN,EXTERNAL,2
-C vddi,UNKNOWN,EXTERNAL,3
-C vsse,UNKNOWN,EXTERNAL,4
-C vssi,UNKNOWN,EXTERNAL,5
-S 5,EXTERNAL,0,vssi
-S 4,EXTERNAL,0,vsse
-S 3,EXTERNAL,0,vddi
-S 2,EXTERNAL,0,vdde
-S 1,EXTERNAL,0,ck
-EOF
diff --git a/alliance/share/cells/padlib/pvdde_sp.ap b/alliance/share/cells/padlib/pvdde_sp.ap
deleted file mode 100644
index 7cc3206d..00000000
--- a/alliance/share/cells/padlib/pvdde_sp.ap
+++ /dev/null
@@ -1,17 +0,0 @@
-V ALLIANCE : 3
-H pvdde_sp,P,30/ 0/95
-A 0,0,172,500
-C 172,13,12,ck,1,EAST,ALU2
-C 172,47,40,vssi,1,EAST,ALU2
-C 172,91,40,vddi,1,EAST,ALU2
-C 172,175,120,vdde,1,EAST,ALU2
-C 0,175,120,vdde,0,WEST,ALU2
-C 0,91,40,vddi,0,WEST,ALU2
-C 0,47,40,vssi,0,WEST,ALU2
-C 0,13,12,ck,0,WEST,ALU2
-C 0,303,120,vsse,0,WEST,ALU2
-C 172,303,120,vsse,1,EAST,ALU2
-C 88,500,1,vdde,2,NORTH,ALU1
-I 0,0,palvdde_sp,logic,NOSYM
-I 0,363,padreal,pad,NOSYM
-EOF
diff --git a/alliance/share/cells/padlib/pvdde_sp.vbe b/alliance/share/cells/padlib/pvdde_sp.vbe
deleted file mode 100644
index 7dbb223c..00000000
--- a/alliance/share/cells/padlib/pvdde_sp.vbe
+++ /dev/null
@@ -1,30 +0,0 @@
--- VHDL data flow description generated from `pvdde_sp`
---		date : Thu Feb 23 17:10:19 1995
-
-
--- Entity Declaration
-
-ENTITY pvdde_sp IS
-  GENERIC (
-    CONSTANT area : NATURAL := 86000	-- area
-  );
-  PORT (
-  ck : in BIT;	-- ck
-  vdde : in BIT;	-- vdde
-  vddi : in BIT;	-- vddi
-  vsse : in BIT;	-- vsse
-  vssi : in BIT	-- vssi
-  );
-END pvdde_sp;
-
-
--- Architecture Declaration
-
-ARCHITECTURE behaviour_data_flow OF pvdde_sp IS
-
-BEGIN
-  ASSERT ((((not (vssi) and not (vsse)) and vddi) and vdde) = '1')
-    REPORT "power supply is missing on pvdde_sp"
-    SEVERITY WARNING;
-
-END;
diff --git a/alliance/share/cells/padlib/pvddeck_sp.al b/alliance/share/cells/padlib/pvddeck_sp.al
deleted file mode 100644
index 416456a2..00000000
--- a/alliance/share/cells/padlib/pvddeck_sp.al
+++ /dev/null
@@ -1,28 +0,0 @@
-V ALLIANCE : 4
-H pvddeck_sp,L,23/ 2/95
-C cko,UNKNOWN,EXTERNAL,2
-C ck,UNKNOWN,EXTERNAL,1
-C vdde,UNKNOWN,EXTERNAL,3
-C vddi,UNKNOWN,EXTERNAL,4
-C vsse,UNKNOWN,EXTERNAL,5
-C vssi,UNKNOWN,EXTERNAL,6
-T N,1,20,6,7,2,0,0,0,0,70,42.5
-T N,1,20,2,7,6,0,0,0,0,64,42.5
-T N,1,20,7,1,6,0,0,0,0,52,42.5
-T N,1,20,2,7,6,0,0,0,0,88,42.5
-T N,1,20,6,7,2,0,0,0,0,82,42.5
-T N,1,20,2,7,6,0,0,0,0,76,42.5
-T P,1,40,7,1,4,0,0,0,0,52,92.5
-T P,1,34,2,7,4,0,0,0,0,88,89.5
-T P,1,34,4,7,2,0,0,0,0,82,89.5
-T P,1,34,2,7,4,0,0,0,0,76,89.5
-T P,1,34,4,7,2,0,0,0,0,70,89.5
-T P,1,34,2,7,4,0,0,0,0,64,89.5
-S 7,INTERNAL,0,mbk_sig4
-S 6,EXTERNAL,0,vssi
-S 5,EXTERNAL,0,vsse
-S 4,EXTERNAL,0,vddi
-S 3,EXTERNAL,0,vdde
-S 2,EXTERNAL,0,cko
-S 1,EXTERNAL,0,ck
-EOF
diff --git a/alliance/share/cells/padlib/pvddeck_sp.ap b/alliance/share/cells/padlib/pvddeck_sp.ap
deleted file mode 100644
index e7e0d2d7..00000000
--- a/alliance/share/cells/padlib/pvddeck_sp.ap
+++ /dev/null
@@ -1,23 +0,0 @@
-V ALLIANCE : 3
-H pvddeck_sp,P,30/ 0/95
-A 0,0,172,500
-C 172,13,12,ck,1,EAST,ALU2
-C 172,47,40,vssi,1,EAST,ALU2
-C 172,91,40,vddi,1,EAST,ALU2
-C 172,175,120,vdde,1,EAST,ALU2
-C 0,175,120,vdde,0,WEST,ALU2
-C 0,91,40,vddi,0,WEST,ALU2
-C 0,47,40,vssi,0,WEST,ALU2
-C 0,13,12,ck,0,WEST,ALU2
-C 67,0,2,cko,1,SOUTH,ALU2
-C 67,0,2,cko,0,SOUTH,ALU1
-C 79,0,2,cko,3,SOUTH,ALU2
-C 79,0,2,cko,2,SOUTH,ALU1
-C 91,0,2,cko,5,SOUTH,ALU2
-C 91,0,2,cko,4,SOUTH,ALU1
-C 172,303,120,vsse,1,EAST,ALU2
-C 0,303,120,vsse,0,WEST,ALU2
-C 88,500,1,vdde,2,NORTH,ALU1
-I 0,0,palvddeck_sp,logic,NOSYM
-I 0,363,padreal,pad,NOSYM
-EOF
diff --git a/alliance/share/cells/padlib/pvddeck_sp.vbe b/alliance/share/cells/padlib/pvddeck_sp.vbe
deleted file mode 100644
index 6f0f899f..00000000
--- a/alliance/share/cells/padlib/pvddeck_sp.vbe
+++ /dev/null
@@ -1,40 +0,0 @@
--- VHDL data flow description generated from `pvddeck_sp`
---		date : Thu Feb 23 17:11:45 1995
-
-
--- Entity Declaration
-
-ENTITY pvddeck_sp IS
-  GENERIC (
-    CONSTANT area : NATURAL := 86000;	-- area
-    CONSTANT cin_ck : NATURAL := 127;	-- cin_ck
-    CONSTANT tpll_ck : NATURAL := 1055;	-- tpll_ck
-    CONSTANT rdown_ck : NATURAL := 126;	-- rdown_ck
-    CONSTANT tphh_ck : NATURAL := 963;	-- tphh_ck
-    CONSTANT rup_ck : NATURAL := 183	-- rup_ck
-  );
-  PORT (
-  cko : out WOR_BIT BUS;	-- cko
-  ck : in BIT;	-- ck
-  vdde : in BIT;	-- vdde
-  vddi : in BIT;	-- vddi
-  vsse : in BIT;	-- vsse
-  vssi : in BIT	-- vssi
-  );
-END pvddeck_sp;
-
-
--- Architecture Declaration
-
-ARCHITECTURE behaviour_data_flow OF pvddeck_sp IS
-
-BEGIN
-  ASSERT ((((not (vssi) and not (vsse)) and vddi) and vdde) = '1')
-    REPORT "power supply is missing on pvddeck_sp"
-    SEVERITY WARNING;
-
-	label0 : BLOCK ('1' = '1')
-	BEGIN
-	cko <= GUARDED ck;
-	END BLOCK label0;
-END;
diff --git a/alliance/share/cells/padlib/pvddi_sp.al b/alliance/share/cells/padlib/pvddi_sp.al
deleted file mode 100644
index 11982763..00000000
--- a/alliance/share/cells/padlib/pvddi_sp.al
+++ /dev/null
@@ -1,13 +0,0 @@
-V ALLIANCE : 4
-H pvddi_sp,L,23/ 2/95
-C ck,UNKNOWN,EXTERNAL,1
-C vdde,UNKNOWN,EXTERNAL,2
-C vddi,UNKNOWN,EXTERNAL,3
-C vsse,UNKNOWN,EXTERNAL,4
-C vssi,UNKNOWN,EXTERNAL,5
-S 5,EXTERNAL,0,vssi
-S 4,EXTERNAL,0,vsse
-S 3,EXTERNAL,0,vddi
-S 2,EXTERNAL,0,vdde
-S 1,EXTERNAL,0,ck
-EOF
diff --git a/alliance/share/cells/padlib/pvddi_sp.ap b/alliance/share/cells/padlib/pvddi_sp.ap
deleted file mode 100644
index 7d1cdd1e..00000000
--- a/alliance/share/cells/padlib/pvddi_sp.ap
+++ /dev/null
@@ -1,19 +0,0 @@
-V ALLIANCE : 3
-H pvddi_sp,P,30/ 0/95
-A 0,0,172,500
-C 86,0,100,vddi,0,SOUTH,ALU1
-C 86,0,100,vddi,1,SOUTH,ALU2
-C 0,47,40,vssi,0,WEST,ALU2
-C 0,175,120,vdde,0,WEST,ALU2
-C 0,91,40,vddi,2,WEST,ALU2
-C 0,13,12,ck,0,WEST,ALU2
-C 172,175,120,vdde,1,EAST,ALU2
-C 172,91,40,vddi,3,EAST,ALU2
-C 172,47,40,vssi,1,EAST,ALU2
-C 172,13,12,ck,1,EAST,ALU2
-C 0,303,120,vsse,0,WEST,ALU2
-C 172,303,120,vsse,1,EAST,ALU2
-C 88,500,1,vddi,4,NORTH,ALU1
-I 0,0,palvddi_sp,logic,NOSYM
-I 0,363,padreal,pad,NOSYM
-EOF
diff --git a/alliance/share/cells/padlib/pvddi_sp.vbe b/alliance/share/cells/padlib/pvddi_sp.vbe
deleted file mode 100644
index 94cec5b4..00000000
--- a/alliance/share/cells/padlib/pvddi_sp.vbe
+++ /dev/null
@@ -1,30 +0,0 @@
--- VHDL data flow description generated from `pvddi_sp`
---		date : Thu Feb 23 17:11:01 1995
-
-
--- Entity Declaration
-
-ENTITY pvddi_sp IS
-  GENERIC (
-    CONSTANT area : NATURAL := 86000	-- area
-  );
-  PORT (
-  ck : in BIT;	-- ck
-  vdde : in BIT;	-- vdde
-  vddi : in BIT;	-- vddi
-  vsse : in BIT;	-- vsse
-  vssi : in BIT	-- vssi
-  );
-END pvddi_sp;
-
-
--- Architecture Declaration
-
-ARCHITECTURE behaviour_data_flow OF pvddi_sp IS
-
-BEGIN
-  ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1')
-    REPORT "power supply is missing on pvddi_sp"
-    SEVERITY WARNING;
-
-END;
diff --git a/alliance/share/cells/padlib/pvddick_sp.al b/alliance/share/cells/padlib/pvddick_sp.al
deleted file mode 100644
index e8205034..00000000
--- a/alliance/share/cells/padlib/pvddick_sp.al
+++ /dev/null
@@ -1,29 +0,0 @@
-V ALLIANCE : 4
-H pvddick_sp,L,23/ 2/95
-C cko,UNKNOWN,EXTERNAL,2
-C ck,UNKNOWN,EXTERNAL,1
-C vdde,UNKNOWN,EXTERNAL,3
-C vddi,UNKNOWN,EXTERNAL,4
-C vsse,UNKNOWN,EXTERNAL,5
-C vssi,UNKNOWN,EXTERNAL,6
-T N,1,25,2,8,6,0,0,0,0,158,45
-T N,1,10,8,1,6,0,0,0,0,146,52.5
-T N,1,25,6,8,2,0,0,0,0,152,45
-T N,1,25,2,7,6,0,0,0,0,14,45
-T N,1,10,7,1,6,0,0,0,0,26,52.5
-T N,1,25,6,7,2,0,0,0,0,20,45
-T P,1,20,4,1,8,0,0,0,0,143,89.5
-T P,1,50,2,8,4,0,0,0,0,149,104.5
-T P,1,50,4,8,2,0,0,0,0,155,104.5
-T P,1,20,4,1,7,0,0,0,0,29,89.5
-T P,1,50,2,7,4,0,0,0,0,23,104.5
-T P,1,50,4,7,2,0,0,0,0,17,104.5
-S 8,INTERNAL,0,mbk_sig6
-S 7,INTERNAL,0,mbk_sig5
-S 6,EXTERNAL,0,vssi
-S 5,EXTERNAL,0,vsse
-S 4,EXTERNAL,0,vddi
-S 3,EXTERNAL,0,vdde
-S 2,EXTERNAL,0,cko
-S 1,EXTERNAL,0,ck
-EOF
diff --git a/alliance/share/cells/padlib/pvddick_sp.ap b/alliance/share/cells/padlib/pvddick_sp.ap
deleted file mode 100644
index f5178836..00000000
--- a/alliance/share/cells/padlib/pvddick_sp.ap
+++ /dev/null
@@ -1,23 +0,0 @@
-V ALLIANCE : 3
-H pvddick_sp,P,30/ 0/95
-A 0,0,172,500
-C 86,0,100,vddi,1,SOUTH,ALU2
-C 86,0,100,vddi,0,SOUTH,ALU1
-C 17,0,2,cko,0,SOUTH,ALU1
-C 17,0,2,cko,1,SOUTH,ALU2
-C 172,13,12,ck,1,EAST,ALU2
-C 172,47,40,vssi,1,EAST,ALU2
-C 172,91,40,vddi,3,EAST,ALU2
-C 172,175,120,vdde,1,EAST,ALU2
-C 0,175,120,vdde,0,WEST,ALU2
-C 0,91,40,vddi,2,WEST,ALU2
-C 0,47,40,vssi,0,WEST,ALU2
-C 0,13,12,ck,0,WEST,ALU2
-C 155,0,1,cko,2,SOUTH,ALU1
-C 155,0,2,cko,2,SOUTH,ALU2
-C 172,303,120,vsse,1,EAST,ALU2
-C 0,303,120,vsse,0,WEST,ALU2
-C 88,500,1,vddi,4,NORTH,ALU1
-I 0,0,palvddick_sp,logic,NOSYM
-I 0,363,padreal,pad,NOSYM
-EOF
diff --git a/alliance/share/cells/padlib/pvddick_sp.vbe b/alliance/share/cells/padlib/pvddick_sp.vbe
deleted file mode 100644
index 37c44073..00000000
--- a/alliance/share/cells/padlib/pvddick_sp.vbe
+++ /dev/null
@@ -1,40 +0,0 @@
--- VHDL data flow description generated from `pvddick_sp`
---		date : Thu Feb 23 17:12:35 1995
-
-
--- Entity Declaration
-
-ENTITY pvddick_sp IS
-  GENERIC (
-    CONSTANT area : NATURAL := 86000;	-- area
-    CONSTANT cin_ck : NATURAL := 127;	-- cin_ck
-    CONSTANT tpll_ck : NATURAL := 1235;	-- tpll_ck
-    CONSTANT rdown_ck : NATURAL := 253;	-- rdown_ck
-    CONSTANT tphh_ck : NATURAL := 1109;	-- tphh_ck
-    CONSTANT rup_ck : NATURAL := 311	-- rup_ck
-  );
-  PORT (
-  cko : out WOR_BIT BUS;	-- cko
-  ck : in BIT;	-- ck
-  vdde : in BIT;	-- vdde
-  vddi : in BIT;	-- vddi
-  vsse : in BIT;	-- vsse
-  vssi : in BIT	-- vssi
-  );
-END pvddick_sp;
-
-
--- Architecture Declaration
-
-ARCHITECTURE behaviour_data_flow OF pvddick_sp IS
-
-BEGIN
-  ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1')
-    REPORT "power supply is missing on pvddick_sp"
-    SEVERITY WARNING;
-
-	label0 : BLOCK ('1' = '1')
-	BEGIN
-	cko <= GUARDED ck;
-	END BLOCK label0;
-END;
diff --git a/alliance/share/cells/padlib/pvsse_sp.al b/alliance/share/cells/padlib/pvsse_sp.al
deleted file mode 100644
index 9d497fd4..00000000
--- a/alliance/share/cells/padlib/pvsse_sp.al
+++ /dev/null
@@ -1,13 +0,0 @@
-V ALLIANCE : 4
-H pvsse_sp,L,23/ 2/95
-C ck,UNKNOWN,EXTERNAL,1
-C vdde,UNKNOWN,EXTERNAL,2
-C vddi,UNKNOWN,EXTERNAL,3
-C vsse,UNKNOWN,EXTERNAL,4
-C vssi,UNKNOWN,EXTERNAL,5
-S 5,EXTERNAL,0,vssi
-S 4,EXTERNAL,0,vsse
-S 3,EXTERNAL,0,vddi
-S 2,EXTERNAL,0,vdde
-S 1,EXTERNAL,0,ck
-EOF
diff --git a/alliance/share/cells/padlib/pvsse_sp.ap b/alliance/share/cells/padlib/pvsse_sp.ap
deleted file mode 100644
index 817bfe1e..00000000
--- a/alliance/share/cells/padlib/pvsse_sp.ap
+++ /dev/null
@@ -1,17 +0,0 @@
-V ALLIANCE : 3
-H pvsse_sp,P,30/ 0/95
-A 0,0,172,500
-C 172,13,12,ck,1,EAST,ALU2
-C 172,47,40,vssi,1,EAST,ALU2
-C 172,91,40,vddi,1,EAST,ALU2
-C 172,175,120,vdde,1,EAST,ALU2
-C 0,175,120,vdde,0,WEST,ALU2
-C 0,91,40,vddi,0,WEST,ALU2
-C 0,47,40,vssi,0,WEST,ALU2
-C 0,13,12,ck,0,WEST,ALU2
-C 0,303,120,vsse,0,WEST,ALU2
-C 172,303,120,vsse,1,EAST,ALU2
-C 88,500,1,vsse,2,NORTH,ALU1
-I 0,0,palvsse_sp,logic,NOSYM
-I 0,363,padreal,pad,NOSYM
-EOF
diff --git a/alliance/share/cells/padlib/pvsse_sp.vbe b/alliance/share/cells/padlib/pvsse_sp.vbe
deleted file mode 100644
index fd9208ee..00000000
--- a/alliance/share/cells/padlib/pvsse_sp.vbe
+++ /dev/null
@@ -1,30 +0,0 @@
--- VHDL data flow description generated from `pvsse_sp`
---		date : Thu Feb 23 17:10:40 1995
-
-
--- Entity Declaration
-
-ENTITY pvsse_sp IS
-  GENERIC (
-    CONSTANT area : NATURAL := 86000	-- area
-  );
-  PORT (
-  ck : in BIT;	-- ck
-  vdde : in BIT;	-- vdde
-  vddi : in BIT;	-- vddi
-  vsse : in BIT;	-- vsse
-  vssi : in BIT	-- vssi
-  );
-END pvsse_sp;
-
-
--- Architecture Declaration
-
-ARCHITECTURE behaviour_data_flow OF pvsse_sp IS
-
-BEGIN
-  ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1')
-    REPORT "power supply is missing on pvsse_sp"
-    SEVERITY WARNING;
-
-END;
diff --git a/alliance/share/cells/padlib/pvsseck_sp.al b/alliance/share/cells/padlib/pvsseck_sp.al
deleted file mode 100644
index e3289211..00000000
--- a/alliance/share/cells/padlib/pvsseck_sp.al
+++ /dev/null
@@ -1,28 +0,0 @@
-V ALLIANCE : 4
-H pvsseck_sp,L,23/ 2/95
-C cko,UNKNOWN,EXTERNAL,2
-C ck,UNKNOWN,EXTERNAL,1
-C vdde,UNKNOWN,EXTERNAL,3
-C vddi,UNKNOWN,EXTERNAL,4
-C vsse,UNKNOWN,EXTERNAL,5
-C vssi,UNKNOWN,EXTERNAL,6
-T N,1,20,6,7,2,0,0,0,0,70,42.5
-T N,1,20,2,7,6,0,0,0,0,64,42.5
-T N,1,20,7,1,6,0,0,0,0,52,42.5
-T N,1,20,2,7,6,0,0,0,0,88,42.5
-T N,1,20,6,7,2,0,0,0,0,82,42.5
-T N,1,20,2,7,6,0,0,0,0,76,42.5
-T P,1,40,7,1,4,0,0,0,0,52,92.5
-T P,1,34,2,7,4,0,0,0,0,88,89.5
-T P,1,34,4,7,2,0,0,0,0,82,89.5
-T P,1,34,2,7,4,0,0,0,0,76,89.5
-T P,1,34,4,7,2,0,0,0,0,70,89.5
-T P,1,34,2,7,4,0,0,0,0,64,89.5
-S 7,INTERNAL,0,mbk_sig4
-S 6,EXTERNAL,0,vssi
-S 5,EXTERNAL,0,vsse
-S 4,EXTERNAL,0,vddi
-S 3,EXTERNAL,0,vdde
-S 2,EXTERNAL,0,cko
-S 1,EXTERNAL,0,ck
-EOF
diff --git a/alliance/share/cells/padlib/pvsseck_sp.ap b/alliance/share/cells/padlib/pvsseck_sp.ap
deleted file mode 100644
index 83240817..00000000
--- a/alliance/share/cells/padlib/pvsseck_sp.ap
+++ /dev/null
@@ -1,23 +0,0 @@
-V ALLIANCE : 3
-H pvsseck_sp,P,30/ 0/95
-A 0,0,172,500
-C 172,13,12,ck,1,EAST,ALU2
-C 172,47,40,vssi,1,EAST,ALU2
-C 172,91,40,vddi,1,EAST,ALU2
-C 172,175,120,vdde,1,EAST,ALU2
-C 0,175,120,vdde,0,WEST,ALU2
-C 0,91,40,vddi,0,WEST,ALU2
-C 0,47,40,vssi,0,WEST,ALU2
-C 0,13,12,ck,0,WEST,ALU2
-C 67,0,2,cko,1,SOUTH,ALU2
-C 67,0,2,cko,0,SOUTH,ALU1
-C 79,0,2,cko,3,SOUTH,ALU2
-C 79,0,2,cko,2,SOUTH,ALU1
-C 91,0,2,cko,5,SOUTH,ALU2
-C 91,0,2,cko,4,SOUTH,ALU1
-C 0,303,120,vsse,0,WEST,ALU2
-C 172,303,120,vsse,1,EAST,ALU2
-C 88,500,1,vsse,2,NORTH,ALU1
-I 0,0,palvsseck_sp,logic,NOSYM
-I 0,363,padreal,pad,NOSYM
-EOF
diff --git a/alliance/share/cells/padlib/pvsseck_sp.vbe b/alliance/share/cells/padlib/pvsseck_sp.vbe
deleted file mode 100644
index 444ac41e..00000000
--- a/alliance/share/cells/padlib/pvsseck_sp.vbe
+++ /dev/null
@@ -1,40 +0,0 @@
--- VHDL data flow description generated from `pvsseck_sp`
---		date : Thu Feb 23 17:12:08 1995
-
-
--- Entity Declaration
-
-ENTITY pvsseck_sp IS
-  GENERIC (
-    CONSTANT area : NATURAL := 86000;	-- area
-    CONSTANT cin_ck : NATURAL := 127;	-- cin_ck
-    CONSTANT tpll_ck : NATURAL := 1055;	-- tpll_ck
-    CONSTANT rdown_ck : NATURAL := 126;	-- rdown_ck
-    CONSTANT tphh_ck : NATURAL := 963;	-- tphh_ck
-    CONSTANT rup_ck : NATURAL := 183	-- rup_ck
-  );
-  PORT (
-  cko : out WOR_BIT BUS;	-- cko
-  ck : in BIT;	-- ck
-  vdde : in BIT;	-- vdde
-  vddi : in BIT;	-- vddi
-  vsse : in BIT;	-- vsse
-  vssi : in BIT	-- vssi
-  );
-END pvsseck_sp;
-
-
--- Architecture Declaration
-
-ARCHITECTURE behaviour_data_flow OF pvsseck_sp IS
-
-BEGIN
-  ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1')
-    REPORT "power supply is missing on pvsseck_sp"
-    SEVERITY WARNING;
-
-	label0 : BLOCK ('1' = '1')
-	BEGIN
-	cko <= GUARDED ck;
-	END BLOCK label0;
-END;
diff --git a/alliance/share/cells/padlib/pvssi_sp.al b/alliance/share/cells/padlib/pvssi_sp.al
deleted file mode 100644
index 466d2100..00000000
--- a/alliance/share/cells/padlib/pvssi_sp.al
+++ /dev/null
@@ -1,13 +0,0 @@
-V ALLIANCE : 4
-H pvssi_sp,L,23/ 2/95
-C ck,UNKNOWN,EXTERNAL,1
-C vdde,UNKNOWN,EXTERNAL,2
-C vddi,UNKNOWN,EXTERNAL,3
-C vsse,UNKNOWN,EXTERNAL,4
-C vssi,UNKNOWN,EXTERNAL,5
-S 5,EXTERNAL,0,vssi
-S 4,EXTERNAL,0,vsse
-S 3,EXTERNAL,0,vddi
-S 2,EXTERNAL,0,vdde
-S 1,EXTERNAL,0,ck
-EOF
diff --git a/alliance/share/cells/padlib/pvssi_sp.ap b/alliance/share/cells/padlib/pvssi_sp.ap
deleted file mode 100644
index a823dbff..00000000
--- a/alliance/share/cells/padlib/pvssi_sp.ap
+++ /dev/null
@@ -1,19 +0,0 @@
-V ALLIANCE : 3
-H pvssi_sp,P,30/ 0/95
-A 0,0,172,500
-C 86,0,100,vssi,1,SOUTH,ALU2
-C 86,0,100,vssi,0,SOUTH,ALU1
-C 0,13,12,ck,0,WEST,ALU2
-C 0,47,40,vssi,2,WEST,ALU2
-C 0,91,40,vddi,0,WEST,ALU2
-C 0,175,120,vdde,0,WEST,ALU2
-C 172,175,120,vdde,1,EAST,ALU2
-C 172,91,40,vddi,1,EAST,ALU2
-C 172,47,40,vssi,3,EAST,ALU2
-C 172,13,12,ck,1,EAST,ALU2
-C 0,303,120,vsse,0,WEST,ALU2
-C 172,303,120,vsse,1,EAST,ALU2
-C 88,500,1,vssi,4,NORTH,ALU1
-I 0,0,palvssi_sp,logic,NOSYM
-I 0,363,padreal,pad,NOSYM
-EOF
diff --git a/alliance/share/cells/padlib/pvssi_sp.vbe b/alliance/share/cells/padlib/pvssi_sp.vbe
deleted file mode 100644
index 6f817126..00000000
--- a/alliance/share/cells/padlib/pvssi_sp.vbe
+++ /dev/null
@@ -1,30 +0,0 @@
--- VHDL data flow description generated from `pvssi_sp`
---		date : Thu Feb 23 17:11:22 1995
-
-
--- Entity Declaration
-
-ENTITY pvssi_sp IS
-  GENERIC (
-    CONSTANT area : NATURAL := 86000	-- area
-  );
-  PORT (
-  ck : in BIT;	-- ck
-  vdde : in BIT;	-- vdde
-  vddi : in BIT;	-- vddi
-  vsse : in BIT;	-- vsse
-  vssi : in BIT	-- vssi
-  );
-END pvssi_sp;
-
-
--- Architecture Declaration
-
-ARCHITECTURE behaviour_data_flow OF pvssi_sp IS
-
-BEGIN
-  ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1')
-    REPORT "power supply is missing on pvssi_sp"
-    SEVERITY WARNING;
-
-END;
diff --git a/alliance/share/cells/padlib/pvssick_sp.al b/alliance/share/cells/padlib/pvssick_sp.al
deleted file mode 100644
index 878902e0..00000000
--- a/alliance/share/cells/padlib/pvssick_sp.al
+++ /dev/null
@@ -1,29 +0,0 @@
-V ALLIANCE : 4
-H pvssick_sp,L,23/ 2/95
-C cko,UNKNOWN,EXTERNAL,2
-C ck,UNKNOWN,EXTERNAL,1
-C vdde,UNKNOWN,EXTERNAL,3
-C vddi,UNKNOWN,EXTERNAL,4
-C vsse,UNKNOWN,EXTERNAL,5
-C vssi,UNKNOWN,EXTERNAL,6
-T N,1,25,2,8,6,0,0,0,0,158,45
-T N,1,10,8,1,6,0,0,0,0,146,52.5
-T N,1,25,6,8,2,0,0,0,0,152,45
-T N,1,25,2,7,6,0,0,0,0,14,45
-T N,1,10,7,1,6,0,0,0,0,26,52.5
-T N,1,25,6,7,2,0,0,0,0,20,45
-T P,1,20,4,1,8,0,0,0,0,143,89.5
-T P,1,50,2,8,4,0,0,0,0,149,104.5
-T P,1,50,4,8,2,0,0,0,0,155,104.5
-T P,1,20,4,1,7,0,0,0,0,29,89.5
-T P,1,50,2,7,4,0,0,0,0,23,104.5
-T P,1,50,4,7,2,0,0,0,0,17,104.5
-S 8,INTERNAL,0,mbk_sig5
-S 7,INTERNAL,0,mbk_sig4
-S 6,EXTERNAL,0,vssi
-S 5,EXTERNAL,0,vsse
-S 4,EXTERNAL,0,vddi
-S 3,EXTERNAL,0,vdde
-S 2,EXTERNAL,0,cko
-S 1,EXTERNAL,0,ck
-EOF
diff --git a/alliance/share/cells/padlib/pvssick_sp.ap b/alliance/share/cells/padlib/pvssick_sp.ap
deleted file mode 100644
index 77ea531d..00000000
--- a/alliance/share/cells/padlib/pvssick_sp.ap
+++ /dev/null
@@ -1,23 +0,0 @@
-V ALLIANCE : 3
-H pvssick_sp,P,30/ 0/95
-A 0,0,172,500
-C 86,0,100,vssi,1,SOUTH,ALU2
-C 86,0,100,vssi,0,SOUTH,ALU1
-C 17,0,2,cko,0,SOUTH,ALU1
-C 17,0,2,cko,1,SOUTH,ALU2
-C 172,91,40,vddi,1,EAST,ALU2
-C 172,47,40,vssi,3,EAST,ALU2
-C 172,13,12,ck,1,EAST,ALU2
-C 172,175,120,vdde,1,EAST,ALU2
-C 0,175,120,vdde,0,WEST,ALU2
-C 0,91,40,vddi,0,WEST,ALU2
-C 0,47,40,vssi,2,WEST,ALU2
-C 0,13,12,ck,0,WEST,ALU2
-C 155,0,2,cko,2,SOUTH,ALU1
-C 155,0,2,cko,3,SOUTH,ALU2
-C 172,303,120,vsse,1,EAST,ALU2
-C 0,303,120,vsse,0,WEST,ALU2
-C 88,500,1,vssi,4,NORTH,ALU1
-I 0,0,palvssick_sp,logic,NOSYM
-I 0,363,padreal,pad,NOSYM
-EOF
diff --git a/alliance/share/cells/padlib/pvssick_sp.vbe b/alliance/share/cells/padlib/pvssick_sp.vbe
deleted file mode 100644
index e780f4e6..00000000
--- a/alliance/share/cells/padlib/pvssick_sp.vbe
+++ /dev/null
@@ -1,40 +0,0 @@
--- VHDL data flow description generated from `pvssick_sp`
---		date : Thu Feb 23 17:13:01 1995
-
-
--- Entity Declaration
-
-ENTITY pvssick_sp IS
-  GENERIC (
-    CONSTANT area : NATURAL := 86000;	-- area
-    CONSTANT cin_ck : NATURAL := 127;	-- cin_ck
-    CONSTANT tpll_ck : NATURAL := 1235;	-- tpll_ck
-    CONSTANT rdown_ck : NATURAL := 253;	-- rdown_ck
-    CONSTANT tphh_ck : NATURAL := 1109;	-- tphh_ck
-    CONSTANT rup_ck : NATURAL := 311	-- rup_ck
-  );
-  PORT (
-  cko : out WOR_BIT BUS;	-- cko
-  ck : in BIT;	-- ck
-  vdde : in BIT;	-- vdde
-  vddi : in BIT;	-- vddi
-  vsse : in BIT;	-- vsse
-  vssi : in BIT	-- vssi
-  );
-END pvssick_sp;
-
-
--- Architecture Declaration
-
-ARCHITECTURE behaviour_data_flow OF pvssick_sp IS
-
-BEGIN
-  ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1')
-    REPORT "power supply is missing on pvssick_sp"
-    SEVERITY WARNING;
-
-	label0 : BLOCK ('1' = '1')
-	BEGIN
-	cko <= GUARDED ck;
-	END BLOCK label0;
-END;
diff --git a/alliance/share/cells/rflib/CATAL b/alliance/share/cells/rflib/CATAL
deleted file mode 100644
index a06325c8..00000000
--- a/alliance/share/cells/rflib/CATAL
+++ /dev/null
@@ -1,32 +0,0 @@
-rf_dec_bufad0  C
-rf_dec_bufad1  C
-rf_dec_bufad1r  C
-rf_dec_bufad2  C
-rf_dec_bufad2r  C
-rf_dec_nand2  C
-rf_dec_nand3  C
-rf_dec_nand4  C
-rf_dec_nao3  C
-rf_dec_nbuf  C
-rf_dec_nor3  C
-rf_fifo_buf  C
-rf_fifo_clock  C
-rf_fifo_empty  C
-rf_fifo_full  C
-rf_fifo_inc  C
-rf_fifo_nop  C
-rf_fifo_ok  C
-rf_fifo_orand4  C
-rf_fifo_orand5  C
-rf_fifo_ptreset  C
-rf_fifo_ptset  C
-rf_inmux_buf_2  C
-rf_inmux_buf_4  C
-rf_inmux_mem  C
-rf_mid_buf_2  C
-rf_mid_buf_4  C
-rf_mid_mem  C
-rf_mid_mem_r0  C
-rf_out_buf_2  C
-rf_out_buf_4  C
-rf_out_mem  C
diff --git a/alliance/share/cells/rflib/rf_dec_bufad0.ap b/alliance/share/cells/rflib/rf_dec_bufad0.ap
deleted file mode 100644
index 2af0ad41..00000000
--- a/alliance/share/cells/rflib/rf_dec_bufad0.ap
+++ /dev/null
@@ -1,78 +0,0 @@
-V ALLIANCE : 6
-H rf_dec_bufad0,P,15/ 3/2001,10
-A 0,0,450,500
-S 0,390,450,390,240,*,LEFT,NWELL
-S 0,470,450,470,60,vdd,RIGHT,CALU1
-S 0,30,450,30,60,vss,RIGHT,CALU1
-S 320,300,320,450,20,*,UP,ALU1
-S 320,50,320,100,20,*,DOWN,ALU1
-S 150,150,210,150,20,*,RIGHT,ALU1
-S 200,300,200,450,20,*,DOWN,ALU1
-S 200,50,200,100,20,*,UP,ALU1
-S 390,300,390,470,20,*,UP,ALU1
-S 390,30,390,150,20,*,DOWN,ALU1
-S 260,100,260,400,20,*,DOWN,ALU1
-S 110,140,110,260,10,*,UP,POLY
-S 170,140,170,260,10,*,UP,POLY
-S 230,140,230,260,10,*,UP,POLY
-S 290,140,290,260,10,*,UP,POLY
-S 210,150,290,150,30,*,RIGHT,POLY
-S 390,20,390,160,30,*,DOWN,PTIE
-S 200,30,200,120,30,*,UP,NDIF
-S 260,30,260,120,30,*,UP,NDIF
-S 80,30,80,120,30,*,UP,NDIF
-S 140,30,140,120,30,*,UP,NDIF
-S 320,30,320,120,30,*,UP,NDIF
-S 230,10,230,140,10,*,DOWN,NTRANS
-S 290,10,290,140,10,*,DOWN,NTRANS
-S 110,10,110,140,10,*,DOWN,NTRANS
-S 170,10,170,140,10,*,DOWN,NTRANS
-S 80,280,80,470,30,*,DOWN,PDIF
-S 230,260,230,490,10,*,UP,PTRANS
-S 260,280,260,470,30,*,DOWN,PDIF
-S 170,260,170,490,10,*,UP,PTRANS
-S 110,260,110,490,10,*,UP,PTRANS
-S 140,280,140,470,30,*,DOWN,PDIF
-S 290,260,290,490,10,*,UP,PTRANS
-S 320,280,320,470,30,*,DOWN,PDIF
-S 390,290,390,480,30,*,UP,NTIE
-S 200,280,200,470,30,*,DOWN,PDIF
-S 50,200,170,200,30,*,RIGHT,POLY
-S 140,100,140,400,20,*,DOWN,ALU1
-S 50,100,50,400,10,i,UP,CALU1
-S 150,250,150,250,20,nq,LEFT,CALU2
-S 250,300,250,300,20,q,LEFT,CALU2
-V 150,250,CONT_VIA,*
-V 250,300,CONT_VIA,*
-V 210,150,CONT_POLY,*
-V 390,150,CONT_BODY_P,*
-V 390,30,CONT_BODY_P,*
-V 390,100,CONT_BODY_P,*
-V 320,100,CONT_DIF_N,*
-V 320,50,CONT_DIF_N,*
-V 200,100,CONT_DIF_N,*
-V 200,50,CONT_DIF_N,*
-V 80,50,CONT_DIF_N,*
-V 260,100,CONT_DIF_N,*
-V 140,100,CONT_DIF_N,*
-V 320,350,CONT_DIF_P,*
-V 320,450,CONT_DIF_P,*
-V 200,300,CONT_DIF_P,*
-V 200,350,CONT_DIF_P,*
-V 200,400,CONT_DIF_P,*
-V 140,400,CONT_DIF_P,*
-V 140,300,CONT_DIF_P,*
-V 140,350,CONT_DIF_P,*
-V 260,300,CONT_DIF_P,*
-V 260,350,CONT_DIF_P,*
-V 260,400,CONT_DIF_P,*
-V 320,400,CONT_DIF_P,*
-V 320,300,CONT_DIF_P,*
-V 390,350,CONT_BODY_N,*
-V 390,400,CONT_BODY_N,*
-V 390,470,CONT_BODY_N,*
-V 200,450,CONT_DIF_P,*
-V 80,450,CONT_DIF_P,*
-V 390,300,CONT_BODY_N,*
-V 50,200,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/rflib/rf_dec_bufad0.vbe b/alliance/share/cells/rflib/rf_dec_bufad0.vbe
deleted file mode 100644
index 03c3741f..00000000
--- a/alliance/share/cells/rflib/rf_dec_bufad0.vbe
+++ /dev/null
@@ -1,21 +0,0 @@
-ENTITY rf_dec_bufad0 IS
-PORT (
-  i      : in  BIT;
-  nq  	 : inout BIT;
-  q  	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END rf_dec_bufad0;
-
-ARCHITECTURE VBE OF rf_dec_bufad0 IS
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on rf_dec_bufad0"
-  SEVERITY WARNING;
-
-  nq <= not i;
-  q  <= not nq;
-
-END;
diff --git a/alliance/share/cells/rflib/rf_dec_bufad1.ap b/alliance/share/cells/rflib/rf_dec_bufad1.ap
deleted file mode 100644
index 052e0c81..00000000
--- a/alliance/share/cells/rflib/rf_dec_bufad1.ap
+++ /dev/null
@@ -1,90 +0,0 @@
-V ALLIANCE : 6
-H rf_dec_bufad1,P,15/ 3/2001,10
-A 0,0,500,500
-S 0,30,500,30,60,vss,RIGHT,CALU1
-S 0,470,500,470,60,vdd,RIGHT,CALU1
-S 0,390,500,390,240,*,LEFT,NWELL
-S 430,50,430,100,20,*,DOWN,ALU1
-S 430,300,430,450,20,*,UP,ALU1
-S 370,100,370,400,20,*,DOWN,ALU1
-S 190,300,190,450,20,*,UP,ALU1
-S 190,50,190,100,20,*,DOWN,ALU1
-S 310,50,310,100,20,*,UP,ALU1
-S 310,300,310,450,20,*,DOWN,ALU1
-S 320,150,400,150,30,*,RIGHT,POLY
-S 400,140,400,260,10,*,UP,POLY
-S 340,140,340,260,10,*,UP,POLY
-S 280,140,280,260,10,*,UP,POLY
-S 220,140,220,260,10,*,UP,POLY
-S 430,30,430,120,30,*,UP,NDIF
-S 250,30,250,120,30,*,UP,NDIF
-S 190,30,190,120,30,*,UP,NDIF
-S 370,30,370,120,30,*,UP,NDIF
-S 310,30,310,120,30,*,UP,NDIF
-S 280,10,280,140,10,*,DOWN,NTRANS
-S 220,10,220,140,10,*,DOWN,NTRANS
-S 400,10,400,140,10,*,DOWN,NTRANS
-S 340,10,340,140,10,*,DOWN,NTRANS
-S 250,280,250,470,30,*,DOWN,PDIF
-S 220,260,220,490,10,*,UP,PTRANS
-S 280,260,280,490,10,*,UP,PTRANS
-S 370,280,370,470,30,*,DOWN,PDIF
-S 340,260,340,490,10,*,UP,PTRANS
-S 190,280,190,470,30,*,DOWN,PDIF
-S 310,280,310,470,30,*,DOWN,PDIF
-S 430,280,430,470,30,*,DOWN,PDIF
-S 400,260,400,490,10,*,UP,PTRANS
-S 100,300,100,470,20,*,UP,ALU1
-S 100,30,100,150,20,*,DOWN,ALU1
-S 100,20,100,160,30,*,DOWN,PTIE
-S 100,290,100,480,30,*,UP,NTIE
-S 300,200,300,200,20,q,LEFT,CALU3
-S 250,200,250,200,20,nq,LEFT,CALU3
-S 200,200,200,200,20,i,LEFT,CALU3
-S 200,200,300,200,20,*,RIGHT,TALU2
-S 250,100,250,400,20,*,DOWN,ALU1
-S 250,150,320,150,20,*,RIGHT,ALU1
-S 300,200,370,200,20,*,RIGHT,ALU1
-S 200,200,280,200,30,*,RIGHT,POLY
-V 320,150,CONT_POLY,*
-V 190,100,CONT_DIF_N,*
-V 190,50,CONT_DIF_N,*
-V 310,50,CONT_DIF_N,*
-V 310,100,CONT_DIF_N,*
-V 430,50,CONT_DIF_N,*
-V 430,100,CONT_DIF_N,*
-V 250,100,CONT_DIF_N,*
-V 370,100,CONT_DIF_N,*
-V 310,450,CONT_DIF_P,*
-V 370,300,CONT_DIF_P,*
-V 250,350,CONT_DIF_P,*
-V 250,300,CONT_DIF_P,*
-V 250,400,CONT_DIF_P,*
-V 190,450,CONT_DIF_P,*
-V 190,300,CONT_DIF_P,*
-V 190,350,CONT_DIF_P,*
-V 190,400,CONT_DIF_P,*
-V 310,350,CONT_DIF_P,*
-V 310,300,CONT_DIF_P,*
-V 430,450,CONT_DIF_P,*
-V 430,350,CONT_DIF_P,*
-V 430,300,CONT_DIF_P,*
-V 430,400,CONT_DIF_P,*
-V 370,400,CONT_DIF_P,*
-V 370,350,CONT_DIF_P,*
-V 310,400,CONT_DIF_P,*
-V 100,150,CONT_BODY_P,*
-V 100,30,CONT_BODY_P,*
-V 100,100,CONT_BODY_P,*
-V 100,300,CONT_BODY_N,*
-V 100,350,CONT_BODY_N,*
-V 100,400,CONT_BODY_N,*
-V 100,470,CONT_BODY_N,*
-V 200,200,CONT_VIA2,*
-V 250,200,CONT_VIA2,*
-V 300,200,CONT_VIA2,*
-V 200,200,CONT_VIA,*
-V 250,200,CONT_VIA,*
-V 300,200,CONT_VIA,*
-V 200,200,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/rflib/rf_dec_bufad1.vbe b/alliance/share/cells/rflib/rf_dec_bufad1.vbe
deleted file mode 100644
index af255e8d..00000000
--- a/alliance/share/cells/rflib/rf_dec_bufad1.vbe
+++ /dev/null
@@ -1,21 +0,0 @@
-ENTITY rf_dec_bufad1 IS
-PORT (
-  i      : in    BIT;
-  nq  	 : inout BIT;
-  q  	 : out   BIT;
-  vdd	 : in    BIT;
-  vss	 : in    BIT
-);
-END rf_dec_bufad1;
-
-ARCHITECTURE VBE OF rf_dec_bufad1 IS
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on rf_dec_bufad1"
-  SEVERITY WARNING;
-
-  nq <= not i;
-  q  <= not nq;
-
-END;
diff --git a/alliance/share/cells/rflib/rf_dec_bufad2.ap b/alliance/share/cells/rflib/rf_dec_bufad2.ap
deleted file mode 100644
index 75204720..00000000
--- a/alliance/share/cells/rflib/rf_dec_bufad2.ap
+++ /dev/null
@@ -1,135 +0,0 @@
-V ALLIANCE : 6
-H rf_dec_bufad2,P,15/ 3/2001,10
-A 0,0,500,500
-S 200,200,450,200,20,*,LEFT,TALU2
-S 90,200,200,200,20,*,RIGHT,ALU1
-S 180,200,250,200,30,*,RIGHT,POLY
-S 140,150,300,150,20,*,LEFT,ALU1
-S 140,250,300,250,20,*,RIGHT,ALU1
-S 60,150,140,150,30,*,RIGHT,POLY
-S 60,250,140,250,30,*,RIGHT,POLY
-S 90,100,90,400,20,*,DOWN,ALU1
-S 250,200,250,200,20,i0,LEFT,CALU3
-S 210,250,210,400,20,*,UP,ALU1
-S 210,100,210,150,20,*,DOWN,ALU1
-S 300,150,300,250,20,*,DOWN,ALU1
-S 350,150,400,150,20,*,RIGHT,ALU1
-S 350,250,400,250,20,*,RIGHT,ALU1
-S 330,100,350,100,20,*,RIGHT,ALU1
-S 330,300,350,300,20,*,RIGHT,ALU1
-S 330,350,350,350,20,*,RIGHT,ALU1
-S 330,400,350,400,20,*,RIGHT,ALU1
-S 350,100,350,400,20,*,UP,ALU1
-S 300,200,400,200,30,*,RIGHT,POLY
-S 400,250,480,250,30,*,RIGHT,POLY
-S 400,200,400,200,20,i1,LEFT,CALU3
-S 330,280,330,470,30,*,DOWN,PDIF
-S 510,280,510,470,30,*,DOWN,PDIF
-S 420,260,420,490,10,*,UP,PTRANS
-S 390,280,390,470,30,*,DOWN,PDIF
-S 480,260,480,490,10,*,UP,PTRANS
-S 450,280,450,470,30,*,DOWN,PDIF
-S 300,260,300,490,10,*,UP,PTRANS
-S 270,280,270,470,30,*,DOWN,PDIF
-S 360,260,360,490,10,*,UP,PTRANS
-S 480,10,480,140,10,*,DOWN,NTRANS
-S 420,10,420,140,10,*,DOWN,NTRANS
-S 360,10,360,140,10,*,DOWN,NTRANS
-S 300,10,300,140,10,*,DOWN,NTRANS
-S 330,30,330,120,30,*,UP,NDIF
-S 270,30,270,120,30,*,UP,NDIF
-S 510,30,510,120,30,*,UP,NDIF
-S 450,30,450,120,30,*,UP,NDIF
-S 390,30,390,120,30,*,UP,NDIF
-S 400,150,480,150,30,*,RIGHT,POLY
-S 360,140,360,260,10,*,UP,POLY
-S 300,140,300,260,10,*,UP,POLY
-S 510,300,510,450,20,*,UP,ALU1
-S 510,50,510,100,20,*,DOWN,ALU1
-S 450,100,450,400,20,*,DOWN,ALU1
-S 270,50,270,100,20,*,DOWN,ALU1
-S 270,300,270,450,20,*,UP,ALU1
-S 0,390,500,390,240,*,LEFT,NWELL
-S 240,140,240,260,10,*,UP,POLY
-S 180,140,180,260,10,*,UP,POLY
-S 240,260,240,490,10,*,UP,PTRANS
-S 90,30,90,120,30,*,UP,NDIF
-S 30,30,30,120,30,*,UP,NDIF
-S 210,30,210,120,30,*,UP,NDIF
-S 150,30,150,120,30,*,UP,NDIF
-S 120,10,120,140,10,*,DOWN,NTRANS
-S 60,10,60,140,10,*,DOWN,NTRANS
-S 240,10,240,140,10,*,DOWN,NTRANS
-S 180,10,180,140,10,*,DOWN,NTRANS
-S 90,280,90,470,30,*,DOWN,PDIF
-S 60,260,60,490,10,*,UP,PTRANS
-S 120,260,120,490,10,*,UP,PTRANS
-S 210,280,210,470,30,*,DOWN,PDIF
-S 180,260,180,490,10,*,UP,PTRANS
-S 30,300,30,450,20,*,UP,ALU1
-S 30,50,30,100,20,*,DOWN,ALU1
-S 30,280,30,470,30,*,DOWN,PDIF
-S 150,280,150,470,30,*,DOWN,PDIF
-S 0,30,500,30,60,vss,RIGHT,CALU1
-S 0,470,500,470,60,vdd,RIGHT,CALU1
-S 200,200,200,200,20,q0,LEFT,CALU3
-S 300,200,300,200,20,nq0,LEFT,CALU3
-S 350,200,350,200,20,nq1,LEFT,CALU3
-S 450,200,450,200,20,q1,LEFT,CALU3
-V 140,150,CONT_POLY,*
-V 140,250,CONT_POLY,*
-V 200,200,CONT_VIA2,*
-V 300,200,CONT_VIA2,*
-V 250,200,CONT_VIA2,*
-V 250,200,CONT_POLY,*
-V 400,200,CONT_POLY,*
-V 400,250,CONT_POLY,*
-V 300,200,CONT_VIA,*
-V 250,200,CONT_VIA,*
-V 200,200,CONT_VIA,*
-V 400,200,CONT_VIA,*
-V 450,200,CONT_VIA,*
-V 350,200,CONT_VIA,*
-V 400,200,CONT_VIA2,*
-V 450,200,CONT_VIA2,*
-V 350,200,CONT_VIA2,*
-V 270,450,CONT_DIF_P,*
-V 510,300,CONT_DIF_P,*
-V 510,350,CONT_DIF_P,*
-V 270,350,CONT_DIF_P,*
-V 270,300,CONT_DIF_P,*
-V 330,400,CONT_DIF_P,*
-V 330,350,CONT_DIF_P,*
-V 330,300,CONT_DIF_P,*
-V 270,400,CONT_DIF_P,*
-V 450,400,CONT_DIF_P,*
-V 450,350,CONT_DIF_P,*
-V 450,300,CONT_DIF_P,*
-V 390,450,CONT_DIF_P,*
-V 510,450,CONT_DIF_P,*
-V 510,400,CONT_DIF_P,*
-V 450,100,CONT_DIF_N,*
-V 390,50,CONT_DIF_N,*
-V 510,100,CONT_DIF_N,*
-V 510,50,CONT_DIF_N,*
-V 330,100,CONT_DIF_N,*
-V 270,50,CONT_DIF_N,*
-V 270,100,CONT_DIF_N,*
-V 400,150,CONT_POLY,*
-V 90,100,CONT_DIF_N,*
-V 210,100,CONT_DIF_N,*
-V 210,400,CONT_DIF_P,*
-V 210,350,CONT_DIF_P,*
-V 210,300,CONT_DIF_P,*
-V 90,350,CONT_DIF_P,*
-V 90,300,CONT_DIF_P,*
-V 90,400,CONT_DIF_P,*
-V 30,450,CONT_DIF_P,*
-V 30,100,CONT_DIF_N,*
-V 30,50,CONT_DIF_N,*
-V 30,300,CONT_DIF_P,*
-V 30,350,CONT_DIF_P,*
-V 30,400,CONT_DIF_P,*
-V 150,450,CONT_DIF_P,*
-V 150,50,CONT_DIF_N,*
-EOF
diff --git a/alliance/share/cells/rflib/rf_dec_bufad2.vbe b/alliance/share/cells/rflib/rf_dec_bufad2.vbe
deleted file mode 100644
index 10b7cb27..00000000
--- a/alliance/share/cells/rflib/rf_dec_bufad2.vbe
+++ /dev/null
@@ -1,26 +0,0 @@
-ENTITY rf_dec_bufad2 IS
-PORT (
-  i0     : in  BIT;
-  i1     : in  BIT;
-  nq0  	 : inout BIT;
-  q0   	 : out BIT;
-  nq1  	 : inout BIT;
-  q1   	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END rf_dec_bufad2;
-
-ARCHITECTURE VBE OF rf_dec_bufad2 IS
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on rf_dec_bufad2"
-  SEVERITY WARNING;
-
-  nq0 <= not i0;
-  q0  <= not nq0;
-  nq1 <= not i1;
-  q1  <= not nq1;
-
-END;
diff --git a/alliance/share/cells/rflib/rf_dec_nand2.ap b/alliance/share/cells/rflib/rf_dec_nand2.ap
deleted file mode 100644
index 01b30116..00000000
--- a/alliance/share/cells/rflib/rf_dec_nand2.ap
+++ /dev/null
@@ -1,69 +0,0 @@
-V ALLIANCE : 6
-H rf_dec_nand2,P,21/ 8/2000,10
-A 0,0,500,500
-S 260,190,260,310,10,*,UP,POLY
-S 240,140,240,210,10,*,UP,POLY
-S 300,200,350,200,20,*,RIGHT,ALU1
-S 200,200,350,200,20,*,RIGHT,TALU2
-S 250,200,250,200,20,i1,LEFT,CALU3
-S 200,200,200,200,20,i0,LEFT,CALU3
-S 350,200,350,200,20,nq,LEFT,CALU3
-S 270,100,300,100,20,*,RIGHT,ALU1
-S 230,350,300,350,20,*,LEFT,ALU1
-S 300,100,300,350,20,*,UP,ALU1
-S 200,140,200,310,10,*,DOWN,POLY
-S 170,330,170,460,30,*,DOWN,PDIF
-S 290,330,290,460,30,*,DOWN,PDIF
-S 260,310,260,440,10,*,UP,PTRANS
-S 200,310,200,440,10,*,UP,PTRANS
-S 230,330,230,420,30,*,DOWN,PDIF
-S 290,400,290,450,20,*,DOWN,ALU1
-S 170,400,170,450,20,*,DOWN,ALU1
-S 240,10,240,140,10,*,DOWN,NTRANS
-S 200,10,200,140,10,*,DOWN,NTRANS
-S 270,30,270,120,30,*,DOWN,NDIF
-S 170,30,170,120,30,*,DOWN,NDIF
-S 170,50,170,100,20,*,DOWN,ALU1
-S 0,390,500,390,240,*,RIGHT,NWELL
-S 0,30,500,30,60,vss,RIGHT,CALU1
-S 0,470,500,470,60,vdd,RIGHT,CALU1
-S 70,300,70,470,20,*,UP,ALU1
-S 70,30,70,150,20,*,DOWN,ALU1
-S 70,20,70,160,30,*,DOWN,PTIE
-S 70,290,70,480,30,*,UP,NTIE
-S 430,30,430,150,20,*,DOWN,ALU1
-S 430,300,430,470,20,*,UP,ALU1
-S 430,20,430,160,30,*,DOWN,PTIE
-S 430,290,430,480,30,*,UP,NTIE
-V 200,200,CONT_POLY,*
-V 250,200,CONT_POLY,*
-V 350,200,CONT_VIA,*
-V 200,200,CONT_VIA,*
-V 250,200,CONT_VIA,*
-V 250,200,CONT_VIA2,*
-V 200,200,CONT_VIA2,*
-V 350,200,CONT_VIA2,*
-V 270,100,CONT_DIF_N,*
-V 170,450,CONT_DIF_P,*
-V 170,400,CONT_DIF_P,*
-V 290,400,CONT_DIF_P,*
-V 230,350,CONT_DIF_P,*
-V 230,470,CONT_BODY_N,*
-V 290,450,CONT_DIF_P,*
-V 170,50,CONT_DIF_N,*
-V 170,100,CONT_DIF_N,*
-V 70,30,CONT_BODY_P,*
-V 70,100,CONT_BODY_P,*
-V 70,150,CONT_BODY_P,*
-V 70,300,CONT_BODY_N,*
-V 70,400,CONT_BODY_N,*
-V 70,470,CONT_BODY_N,*
-V 70,350,CONT_BODY_N,*
-V 430,150,CONT_BODY_P,*
-V 430,100,CONT_BODY_P,*
-V 430,30,CONT_BODY_P,*
-V 430,400,CONT_BODY_N,*
-V 430,300,CONT_BODY_N,*
-V 430,350,CONT_BODY_N,*
-V 430,470,CONT_BODY_N,*
-EOF
diff --git a/alliance/share/cells/rflib/rf_dec_nand2.vbe b/alliance/share/cells/rflib/rf_dec_nand2.vbe
deleted file mode 100644
index 7c0132d8..00000000
--- a/alliance/share/cells/rflib/rf_dec_nand2.vbe
+++ /dev/null
@@ -1,20 +0,0 @@
-ENTITY rf_dec_nand2 IS
-PORT (
-  i0     : in  BIT;
-  i1     : in  BIT;
-  nq   	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END rf_dec_nand2;
-
-ARCHITECTURE VBE OF rf_dec_nand2 IS
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on rf_dec_nand2"
-  SEVERITY WARNING;
-
-  nq <= not(i0 and i1);
-
-END;
diff --git a/alliance/share/cells/rflib/rf_dec_nand3.ap b/alliance/share/cells/rflib/rf_dec_nand3.ap
deleted file mode 100644
index 0d495560..00000000
--- a/alliance/share/cells/rflib/rf_dec_nand3.ap
+++ /dev/null
@@ -1,84 +0,0 @@
-V ALLIANCE : 6
-H rf_dec_nand3,P,22/ 8/2000,10
-A 0,0,500,500
-S 350,200,350,200,20,i0,LEFT,CALU3
-S 170,50,170,100,20,*,DOWN,ALU1
-S 170,30,170,120,30,*,DOWN,NDIF
-S 0,30,500,30,60,vss,RIGHT,CALU1
-S 0,470,500,470,60,vdd,RIGHT,CALU1
-S 0,390,500,390,240,*,RIGHT,NWELL
-S 70,300,70,470,20,*,UP,ALU1
-S 70,30,70,150,20,*,DOWN,ALU1
-S 70,20,70,160,30,*,DOWN,PTIE
-S 70,290,70,480,30,*,UP,NTIE
-S 190,350,350,350,20,*,LEFT,ALU1
-S 350,100,350,350,20,*,UP,ALU1
-S 250,400,250,450,20,*,DOWN,ALU1
-S 370,400,370,450,20,*,DOWN,ALU1
-S 200,140,200,310,10,*,UP,POLY
-S 200,310,220,310,10,*,RIGHT,POLY
-S 310,30,310,120,30,*,DOWN,NDIF
-S 200,10,200,140,10,*,DOWN,NTRANS
-S 240,10,240,140,10,*,DOWN,NTRANS
-S 280,10,280,140,10,*,DOWN,NTRANS
-S 190,330,190,420,30,*,DOWN,PDIF
-S 220,310,220,440,10,*,UP,PTRANS
-S 280,310,280,440,10,*,UP,PTRANS
-S 340,310,340,440,10,*,UP,PTRANS
-S 370,330,370,460,30,*,DOWN,PDIF
-S 250,330,250,460,30,*,DOWN,PDIF
-S 310,330,310,420,30,*,DOWN,PDIF
-S 430,30,430,150,20,*,DOWN,ALU1
-S 430,300,430,470,20,*,UP,ALU1
-S 430,20,430,160,30,*,DOWN,PTIE
-S 430,290,430,480,30,*,UP,NTIE
-S 260,310,280,310,10,*,RIGHT,POLY
-S 310,310,340,310,10,*,RIGHT,POLY
-S 310,100,350,100,20,*,RIGHT,ALU1
-S 200,200,200,200,20,i1,LEFT,CALU3
-S 250,200,250,200,20,i2,LEFT,CALU3
-S 400,200,400,200,20,nq,LEFT,CALU3
-S 200,200,400,200,20,*,RIGHT,TALU2
-S 300,200,350,200,20,*,RIGHT,ALU2
-S 350,200,400,200,20,*,RIGHT,ALU1
-S 240,140,240,210,10,*,UP,POLY
-S 260,190,260,310,10,*,UP,POLY
-S 310,140,310,310,10,*,DOWN,POLY
-S 280,140,310,140,10,*,RIGHT,POLY
-V 170,100,CONT_DIF_N,*
-V 170,50,CONT_DIF_N,*
-V 70,30,CONT_BODY_P,*
-V 70,100,CONT_BODY_P,*
-V 70,150,CONT_BODY_P,*
-V 70,300,CONT_BODY_N,*
-V 70,400,CONT_BODY_N,*
-V 70,470,CONT_BODY_N,*
-V 70,350,CONT_BODY_N,*
-V 370,450,CONT_DIF_P,*
-V 310,470,CONT_BODY_N,*
-V 190,470,CONT_BODY_N,*
-V 190,350,CONT_DIF_P,*
-V 310,350,CONT_DIF_P,*
-V 370,400,CONT_DIF_P,*
-V 250,400,CONT_DIF_P,*
-V 250,450,CONT_DIF_P,*
-V 430,150,CONT_BODY_P,*
-V 430,100,CONT_BODY_P,*
-V 430,30,CONT_BODY_P,*
-V 430,400,CONT_BODY_N,*
-V 430,300,CONT_BODY_N,*
-V 430,350,CONT_BODY_N,*
-V 430,470,CONT_BODY_N,*
-V 310,100,CONT_DIF_N,*
-V 250,200,CONT_VIA2,*
-V 400,200,CONT_VIA2,*
-V 350,200,CONT_VIA2,*
-V 200,200,CONT_VIA2,*
-V 400,200,CONT_VIA,*
-V 250,200,CONT_VIA,*
-V 200,200,CONT_VIA,*
-V 300,200,CONT_VIA,*
-V 300,200,CONT_POLY,*
-V 250,200,CONT_POLY,*
-V 200,200,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/rflib/rf_dec_nand3.vbe b/alliance/share/cells/rflib/rf_dec_nand3.vbe
deleted file mode 100644
index c1eec05c..00000000
--- a/alliance/share/cells/rflib/rf_dec_nand3.vbe
+++ /dev/null
@@ -1,21 +0,0 @@
-ENTITY rf_dec_nand3 IS
-PORT (
-  i0     : in  BIT;
-  i1     : in  BIT;
-  i2     : in  BIT;
-  nq   	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END rf_dec_nand3;
-
-ARCHITECTURE VBE OF rf_dec_nand3 IS
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on rf_dec_nand3"
-  SEVERITY WARNING;
-
-  nq <= not(i0 and i1 and i2);
-
-END;
diff --git a/alliance/share/cells/rflib/rf_dec_nand4.ap b/alliance/share/cells/rflib/rf_dec_nand4.ap
deleted file mode 100644
index ce1a4f57..00000000
--- a/alliance/share/cells/rflib/rf_dec_nand4.ap
+++ /dev/null
@@ -1,96 +0,0 @@
-V ALLIANCE : 6
-H rf_dec_nand4,P,21/ 8/2000,10
-A 0,0,500,500
-S 280,140,310,140,10,*,RIGHT,POLY
-S 310,140,310,310,10,*,DOWN,POLY
-S 240,140,240,210,10,*,UP,POLY
-S 260,190,260,310,10,*,UP,POLY
-S 350,200,400,200,20,*,RIGHT,ALU1
-S 300,200,350,200,20,*,RIGHT,ALU2
-S 150,200,400,200,20,*,RIGHT,TALU2
-S 250,200,250,200,20,i2,LEFT,CALU3
-S 200,200,200,200,20,i1,LEFT,CALU3
-S 150,200,150,200,20,i0,LEFT,CALU3
-S 350,200,350,200,20,i3,LEFT,CALU3
-S 400,200,400,200,20,nq,LEFT,CALU3
-S 430,290,430,480,30,*,UP,NTIE
-S 430,20,430,160,30,*,DOWN,PTIE
-S 430,300,430,470,20,*,UP,ALU1
-S 430,30,430,150,20,*,DOWN,ALU1
-S 310,330,310,420,30,*,DOWN,PDIF
-S 130,330,130,460,30,*,DOWN,PDIF
-S 250,330,250,460,30,*,DOWN,PDIF
-S 370,330,370,460,30,*,DOWN,PDIF
-S 160,310,160,440,10,*,UP,PTRANS
-S 340,310,340,440,10,*,UP,PTRANS
-S 280,310,280,440,10,*,UP,PTRANS
-S 220,310,220,440,10,*,UP,PTRANS
-S 190,330,190,420,30,*,DOWN,PDIF
-S 280,10,280,140,10,*,DOWN,NTRANS
-S 240,10,240,140,10,*,DOWN,NTRANS
-S 200,10,200,140,10,*,DOWN,NTRANS
-S 160,10,160,140,10,*,DOWN,NTRANS
-S 130,30,130,120,30,*,DOWN,NDIF
-S 310,30,310,120,30,*,DOWN,NDIF
-S 160,140,160,310,10,*,DOWN,POLY
-S 200,310,220,310,10,*,RIGHT,POLY
-S 200,140,200,310,10,*,UP,POLY
-S 130,50,130,100,20,*,DOWN,ALU1
-S 370,400,370,450,20,*,DOWN,ALU1
-S 250,400,250,450,20,*,DOWN,ALU1
-S 350,100,350,350,20,*,UP,ALU1
-S 190,350,350,350,20,*,LEFT,ALU1
-S 130,350,130,450,20,*,DOWN,ALU1
-S 70,290,70,480,30,*,UP,NTIE
-S 70,20,70,160,30,*,DOWN,PTIE
-S 70,30,70,150,20,*,DOWN,ALU1
-S 70,300,70,470,20,*,UP,ALU1
-S 0,390,500,390,240,*,RIGHT,NWELL
-S 0,470,500,470,60,vdd,RIGHT,CALU1
-S 0,30,500,30,60,vss,RIGHT,CALU1
-S 260,310,280,310,10,*,RIGHT,POLY
-S 310,310,340,310,10,*,RIGHT,POLY
-S 310,100,350,100,20,*,RIGHT,ALU1
-V 200,200,CONT_POLY,*
-V 150,200,CONT_POLY,*
-V 250,200,CONT_POLY,*
-V 300,200,CONT_POLY,*
-V 400,200,CONT_VIA,*
-V 250,200,CONT_VIA,*
-V 300,200,CONT_VIA,*
-V 150,200,CONT_VIA,*
-V 200,200,CONT_VIA,*
-V 350,200,CONT_VIA2,*
-V 400,200,CONT_VIA2,*
-V 250,200,CONT_VIA2,*
-V 150,200,CONT_VIA2,*
-V 200,200,CONT_VIA2,*
-V 430,470,CONT_BODY_N,*
-V 430,350,CONT_BODY_N,*
-V 430,300,CONT_BODY_N,*
-V 430,400,CONT_BODY_N,*
-V 430,30,CONT_BODY_P,*
-V 430,100,CONT_BODY_P,*
-V 430,150,CONT_BODY_P,*
-V 250,450,CONT_DIF_P,*
-V 250,400,CONT_DIF_P,*
-V 370,400,CONT_DIF_P,*
-V 310,350,CONT_DIF_P,*
-V 190,350,CONT_DIF_P,*
-V 130,350,CONT_DIF_P,*
-V 130,400,CONT_DIF_P,*
-V 190,470,CONT_BODY_N,*
-V 310,470,CONT_BODY_N,*
-V 130,450,CONT_DIF_P,*
-V 370,450,CONT_DIF_P,*
-V 130,100,CONT_DIF_N,*
-V 130,50,CONT_DIF_N,*
-V 70,350,CONT_BODY_N,*
-V 70,470,CONT_BODY_N,*
-V 70,400,CONT_BODY_N,*
-V 70,300,CONT_BODY_N,*
-V 70,150,CONT_BODY_P,*
-V 70,100,CONT_BODY_P,*
-V 70,30,CONT_BODY_P,*
-V 310,100,CONT_DIF_N,*
-EOF
diff --git a/alliance/share/cells/rflib/rf_dec_nand4.vbe b/alliance/share/cells/rflib/rf_dec_nand4.vbe
deleted file mode 100644
index b8fb199a..00000000
--- a/alliance/share/cells/rflib/rf_dec_nand4.vbe
+++ /dev/null
@@ -1,22 +0,0 @@
-ENTITY rf_dec_nand4 IS
-PORT (
-  i0     : in  BIT;
-  i1     : in  BIT;
-  i2     : in  BIT;
-  i3     : in  BIT;
-  nq   	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END rf_dec_nand4;
-
-ARCHITECTURE VBE OF rf_dec_nand4 IS
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on rf_dec_nand4"
-  SEVERITY WARNING;
-
-  nq <= not(i0 and i1 and i2 and i3);
-
-END;
diff --git a/alliance/share/cells/rflib/rf_dec_nao3.ap b/alliance/share/cells/rflib/rf_dec_nao3.ap
deleted file mode 100644
index d11fca4c..00000000
--- a/alliance/share/cells/rflib/rf_dec_nao3.ap
+++ /dev/null
@@ -1,62 +0,0 @@
-V ALLIANCE : 6
-H rf_dec_nao3,P, 7/11/2000,10
-A 0,0,250,500
-S 200,350,200,350,20,i2,LEFT,CALU2
-S 200,200,200,350,20,*,DOWN,ALU1
-S 210,400,210,450,20,*,DOWN,ALU1
-S 100,400,100,400,20,i0,LEFT,CALU2
-S 100,200,120,200,30,*,RIGHT,POLY
-S 120,260,120,490,10,*,UP,PTRANS
-S 100,250,100,400,20,*,UP,ALU1
-S 50,200,100,200,20,*,RIGHT,ALU2
-S 0,470,250,470,60,vdd,RIGHT,CALU1
-S 0,30,250,30,60,vss,RIGHT,CALU1
-S 0,390,250,390,240,*,RIGHT,NWELL
-S 180,260,180,490,10,*,UP,PTRANS
-S 210,280,210,470,30,*,DOWN,PDIF
-S 30,100,150,100,20,*,LEFT,ALU1
-S 150,150,150,400,20,*,DOWN,ALU1
-S 90,150,150,150,20,*,LEFT,ALU1
-S 60,60,60,190,10,*,DOWN,NTRANS
-S 120,60,120,190,10,*,DOWN,NTRANS
-S 150,80,150,170,30,*,UP,NDIF
-S 30,80,30,170,30,*,UP,NDIF
-S 90,80,90,170,30,*,UP,NDIF
-S 180,200,210,200,30,*,RIGHT,POLY
-S 180,60,180,190,10,*,DOWN,NTRANS
-S 210,40,210,170,30,*,UP,NDIF
-S 150,280,150,470,20,*,DOWN,PDIF
-S 180,190,180,260,10,*,DOWN,POLY
-S 120,190,120,260,10,*,DOWN,POLY
-S 60,190,60,260,10,*,DOWN,POLY
-S 70,250,100,250,20,*,RIGHT,ALU1
-S 60,260,60,490,10,*,UP,PTRANS
-S 30,280,30,470,30,*,DOWN,PDIF
-S 90,280,90,470,20,*,DOWN,PDIF
-S 30,300,30,450,20,*,DOWN,ALU1
-S 220,40,220,170,30,*,UP,NDIF
-S 50,200,50,200,20,i1,LEFT,CALU2
-S 100,150,100,150,20,nq,LEFT,CALU2
-V 200,350,CONT_VIA,*
-V 30,300,CONT_DIF_P,*
-V 30,350,CONT_DIF_P,*
-V 30,400,CONT_DIF_P,*
-V 210,400,CONT_DIF_P,*
-V 100,400,CONT_VIA,*
-V 210,450,CONT_DIF_P,*
-V 150,100,CONT_DIF_N,*
-V 30,100,CONT_DIF_N,*
-V 30,30,CONT_BODY_P,*
-V 150,30,CONT_BODY_P,*
-V 210,50,CONT_DIF_N,*
-V 100,200,CONT_VIA,*
-V 100,200,CONT_POLY,*
-V 90,150,CONT_DIF_N,*
-V 200,200,CONT_POLY,*
-V 100,150,CONT_VIA,*
-V 150,400,CONT_DIF_P,*
-V 150,350,CONT_DIF_P,*
-V 150,300,CONT_DIF_P,*
-V 70,250,CONT_POLY,*
-V 30,450,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/rflib/rf_dec_nao3.vbe b/alliance/share/cells/rflib/rf_dec_nao3.vbe
deleted file mode 100644
index 6f76808b..00000000
--- a/alliance/share/cells/rflib/rf_dec_nao3.vbe
+++ /dev/null
@@ -1,21 +0,0 @@
-ENTITY rf_dec_nao3 IS
-PORT (
-  i0     : in  BIT;
-  i1     : in  BIT;
-  i2     : in  BIT;
-  nq   	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END rf_dec_nao3;
-
-ARCHITECTURE VBE OF rf_dec_nao3 IS
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on rf_dec_nao3"
-  SEVERITY WARNING;
-
-  nq <= not(i2 and (i1 or i0));
-
-END;
diff --git a/alliance/share/cells/rflib/rf_dec_nbuf.ap b/alliance/share/cells/rflib/rf_dec_nbuf.ap
deleted file mode 100644
index 972ec4ca..00000000
--- a/alliance/share/cells/rflib/rf_dec_nbuf.ap
+++ /dev/null
@@ -1,79 +0,0 @@
-V ALLIANCE : 6
-H rf_dec_nbuf,P,15/ 3/2001,10
-A 0,0,550,500
-S 90,100,90,400,20,*,DOWN,ALU1
-S 100,250,210,250,20,*,RIGHT,ALU1
-S 0,390,550,390,240,*,LEFT,NWELL
-S 0,470,550,470,60,vdd,RIGHT,CALU1
-S 0,30,550,30,60,vss,RIGHT,CALU1
-S 340,20,340,160,30,*,DOWN,PTIE
-S 340,290,340,480,30,*,UP,NTIE
-S 340,300,340,470,20,*,UP,ALU1
-S 340,30,340,150,20,*,DOWN,ALU1
-S 150,280,150,470,30,*,DOWN,PDIF
-S 30,280,30,470,30,*,DOWN,PDIF
-S 30,50,30,100,20,*,DOWN,ALU1
-S 30,300,30,450,20,*,UP,ALU1
-S 180,260,180,490,10,*,UP,PTRANS
-S 210,280,210,470,30,*,DOWN,PDIF
-S 120,260,120,490,10,*,UP,PTRANS
-S 60,260,60,490,10,*,UP,PTRANS
-S 90,280,90,470,30,*,DOWN,PDIF
-S 180,10,180,140,10,*,DOWN,NTRANS
-S 240,10,240,140,10,*,DOWN,NTRANS
-S 60,10,60,140,10,*,DOWN,NTRANS
-S 120,10,120,140,10,*,DOWN,NTRANS
-S 150,30,150,120,30,*,UP,NDIF
-S 210,30,210,120,30,*,UP,NDIF
-S 30,30,30,120,30,*,UP,NDIF
-S 90,30,90,120,30,*,UP,NDIF
-S 240,260,240,490,10,*,UP,PTRANS
-S 60,140,60,260,10,*,UP,POLY
-S 120,140,120,260,10,*,UP,POLY
-S 180,140,180,260,10,*,UP,POLY
-S 240,140,240,260,10,*,UP,POLY
-S 210,100,210,400,20,*,DOWN,ALU1
-S 270,300,270,450,20,*,UP,ALU1
-S 270,50,270,100,20,*,DOWN,ALU1
-S 270,30,270,120,30,*,UP,NDIF
-S 270,280,270,470,30,*,DOWN,PDIF
-S 150,300,150,450,20,*,DOWN,ALU1
-S 500,100,500,400,10,i,UP,CALU1
-S 60,200,500,200,30,*,RIGHT,POLY
-S 100,100,200,100,20,nq,RIGHT,CALU2
-V 340,150,CONT_BODY_P,*
-V 340,30,CONT_BODY_P,*
-V 340,100,CONT_BODY_P,*
-V 340,300,CONT_BODY_N,*
-V 340,350,CONT_BODY_N,*
-V 340,400,CONT_BODY_N,*
-V 340,470,CONT_BODY_N,*
-V 150,50,CONT_DIF_N,*
-V 150,450,CONT_DIF_P,*
-V 30,400,CONT_DIF_P,*
-V 30,350,CONT_DIF_P,*
-V 30,300,CONT_DIF_P,*
-V 30,50,CONT_DIF_N,*
-V 30,100,CONT_DIF_N,*
-V 30,450,CONT_DIF_P,*
-V 90,400,CONT_DIF_P,*
-V 90,300,CONT_DIF_P,*
-V 90,350,CONT_DIF_P,*
-V 210,300,CONT_DIF_P,*
-V 210,350,CONT_DIF_P,*
-V 210,400,CONT_DIF_P,*
-V 210,100,CONT_DIF_N,*
-V 90,100,CONT_DIF_N,*
-V 270,100,CONT_DIF_N,*
-V 270,50,CONT_DIF_N,*
-V 270,400,CONT_DIF_P,*
-V 270,300,CONT_DIF_P,*
-V 270,350,CONT_DIF_P,*
-V 270,450,CONT_DIF_P,*
-V 150,300,CONT_DIF_P,*
-V 150,350,CONT_DIF_P,*
-V 150,400,CONT_DIF_P,*
-V 500,200,CONT_POLY,*
-V 200,100,CONT_VIA,*
-V 100,100,CONT_VIA,*
-EOF
diff --git a/alliance/share/cells/rflib/rf_dec_nbuf.vbe b/alliance/share/cells/rflib/rf_dec_nbuf.vbe
deleted file mode 100644
index 336421b0..00000000
--- a/alliance/share/cells/rflib/rf_dec_nbuf.vbe
+++ /dev/null
@@ -1,19 +0,0 @@
-ENTITY rf_dec_nbuf IS
-PORT (
-  i      : in  BIT;
-  nq   	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END rf_dec_nbuf;
-
-ARCHITECTURE VBE OF rf_dec_nbuf IS
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on rf_dec_nbuf"
-  SEVERITY WARNING;
-
-  nq <= not i;
-
-END;
diff --git a/alliance/share/cells/rflib/rf_dec_nor3.ap b/alliance/share/cells/rflib/rf_dec_nor3.ap
deleted file mode 100644
index e15c13d4..00000000
--- a/alliance/share/cells/rflib/rf_dec_nor3.ap
+++ /dev/null
@@ -1,61 +0,0 @@
-V ALLIANCE : 6
-H rf_dec_nor3,P,22/ 8/2000,10
-A 0,0,250,500
-S 50,200,50,200,20,i1,LEFT,CALU2
-S 50,200,100,200,20,*,RIGHT,ALU2
-S 100,150,100,150,20,nq,LEFT,CALU2
-S 220,40,220,120,30,*,UP,NDIF
-S 200,100,200,100,20,i2,LEFT,CALU2
-S 200,100,200,150,20,*,UP,ALU1
-S 150,100,150,150,20,*,DOWN,ALU1
-S 50,150,150,150,20,*,RIGHT,ALU1
-S 180,150,210,150,30,*,RIGHT,POLY
-S 100,250,100,400,20,*,UP,ALU1
-S 0,470,250,470,60,vdd,RIGHT,CALU1
-S 0,30,250,30,60,vss,RIGHT,CALU1
-S 210,300,210,450,20,*,DOWN,ALU1
-S 50,100,50,400,20,*,DOWN,ALU1
-S 0,390,250,390,240,*,RIGHT,NWELL
-S 60,140,60,240,10,*,DOWN,POLY
-S 60,240,110,240,10,*,LEFT,POLY
-S 180,260,180,490,10,*,UP,PTRANS
-S 50,280,50,420,30,*,DOWN,PDIF
-S 100,260,100,490,10,*,UP,PTRANS
-S 70,280,70,420,30,*,DOWN,PDIF
-S 140,260,140,490,10,*,UP,PTRANS
-S 120,60,120,140,10,*,DOWN,NTRANS
-S 180,60,180,140,10,*,DOWN,NTRANS
-S 60,60,60,140,10,*,DOWN,NTRANS
-S 210,280,210,470,30,*,DOWN,PDIF
-S 90,40,90,120,30,*,UP,NDIF
-S 30,80,30,120,30,*,UP,NDIF
-S 210,40,210,120,30,*,UP,NDIF
-S 150,80,150,120,30,*,UP,NDIF
-S 30,100,150,100,20,*,LEFT,ALU1
-S 120,140,120,210,10,*,DOWN,POLY
-S 140,190,140,260,10,*,DOWN,POLY
-S 100,200,140,200,30,*,RIGHT,POLY
-S 180,140,180,260,10,*,UP,POLY
-S 100,400,100,400,20,i0,LEFT,CALU2
-V 200,100,CONT_VIA,*
-V 100,150,CONT_VIA,*
-V 200,150,CONT_POLY,*
-V 210,300,CONT_DIF_P,*
-V 210,350,CONT_DIF_P,*
-V 210,400,CONT_DIF_P,*
-V 50,300,CONT_DIF_P,*
-V 50,350,CONT_DIF_P,*
-V 50,400,CONT_DIF_P,*
-V 100,400,CONT_VIA,*
-V 100,250,CONT_POLY,*
-V 30,470,CONT_BODY_N,*
-V 210,450,CONT_DIF_P,*
-V 150,100,CONT_DIF_N,*
-V 30,100,CONT_DIF_N,*
-V 90,50,CONT_DIF_N,*
-V 30,30,CONT_BODY_P,*
-V 150,30,CONT_BODY_P,*
-V 210,50,CONT_DIF_N,*
-V 100,200,CONT_VIA,*
-V 100,200,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/rflib/rf_dec_nor3.vbe b/alliance/share/cells/rflib/rf_dec_nor3.vbe
deleted file mode 100644
index a13eb4b1..00000000
--- a/alliance/share/cells/rflib/rf_dec_nor3.vbe
+++ /dev/null
@@ -1,21 +0,0 @@
-ENTITY rf_dec_nor3 IS
-PORT (
-  i0     : in  BIT;
-  i1     : in  BIT;
-  i2     : in  BIT;
-  nq   	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END rf_dec_nor3;
-
-ARCHITECTURE VBE OF rf_dec_nor3 IS
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on rf_dec_nor3"
-  SEVERITY WARNING;
-
-  nq <= not(i0 or i1 or i2);
-
-END;
diff --git a/alliance/share/cells/rflib/rf_fifo_buf.ap b/alliance/share/cells/rflib/rf_fifo_buf.ap
deleted file mode 100644
index 9907c6ef..00000000
--- a/alliance/share/cells/rflib/rf_fifo_buf.ap
+++ /dev/null
@@ -1,211 +0,0 @@
-V ALLIANCE : 6
-H rf_fifo_buf,P,14/ 6/2001,10
-A 0,0,500,1000
-R 400,800,ref_ref,reset
-S 0,530,500,530,60,vdd,RIGHT,CALU1
-S 0,470,500,470,60,vdd,RIGHT,CALU1
-S 0,610,540,610,240,*,RIGHT,NWELL
-S 0,390,540,390,240,*,RIGHT,NWELL
-S 50,100,50,400,20,xcks,DOWN,CALU1
-S 350,100,350,400,20,xckm,DOWN,CALU1
-S 250,600,250,900,20,nw,DOWN,CALU1
-S 280,750,300,750,30,*,RIGHT,POLY
-S 300,750,300,750,20,w,LEFT,CALU2
-S 50,600,50,900,20,nr,DOWN,CALU1
-S 80,850,100,850,30,*,RIGHT,POLY
-S 100,850,100,850,20,r,LEFT,CALU2
-S 110,880,110,970,30,*,DOWN,NDIF
-S 110,900,110,950,20,*,DOWN,ALU1
-S 80,740,80,860,10,*,DOWN,POLY
-S 80,860,80,990,10,*,DOWN,NTRANS
-S 50,880,50,970,30,*,UP,NDIF
-S 400,400,430,400,20,*,RIGHT,ALU1
-S 400,350,440,350,20,*,RIGHT,ALU1
-S 400,300,440,300,20,*,RIGHT,ALU1
-S 400,150,440,150,20,*,RIGHT,ALU1
-S 400,100,440,100,20,*,RIGHT,ALU1
-S 400,100,400,400,20,xreset,DOWN,CALU1
-S 450,250,470,250,30,*,RIGHT,POLY
-S 470,190,470,260,10,*,DOWN,POLY
-S 280,740,280,810,10,*,DOWN,POLY
-S 140,390,200,390,10,*,RIGHT,POLY
-S 200,110,260,110,10,*,RIGHT,POLY
-S 200,100,200,100,20,ckm,LEFT,CALU2
-S 200,400,200,400,20,cks,LEFT,CALU2
-S 300,200,320,200,30,*,RIGHT,POLY
-S 80,200,100,200,30,*,RIGHT,POLY
-S 230,200,300,200,20,*,RIGHT,ALU1
-S 320,190,320,260,10,*,DOWN,POLY
-S 260,190,260,260,10,*,DOWN,POLY
-S 230,150,230,350,20,*,DOWN,ALU1
-S 260,110,260,190,10,*,DOWN,NTRANS
-S 230,130,230,170,30,*,UP,NDIF
-S 230,280,230,370,30,*,DOWN,PDIF
-S 260,260,260,390,10,*,UP,PTRANS
-S 290,280,290,470,30,*,UP,PDIF
-S 320,260,320,490,10,*,UP,PTRANS
-S 350,280,350,470,30,*,DOWN,PDIF
-S 320,60,320,190,10,*,DOWN,NTRANS
-S 290,40,290,170,30,*,UP,NDIF
-S 350,80,350,170,30,*,UP,NDIF
-S 290,300,290,450,20,*,DOWN,ALU1
-S 290,50,290,150,20,*,DOWN,ALU1
-S 140,190,140,260,10,*,DOWN,POLY
-S 170,150,170,350,20,*,DOWN,ALU1
-S 140,110,140,190,10,*,DOWN,NTRANS
-S 170,130,170,170,30,*,UP,NDIF
-S 80,190,80,260,10,*,DOWN,POLY
-S 100,200,170,200,20,*,RIGHT,ALU1
-S 170,280,170,370,30,*,DOWN,PDIF
-S 140,260,140,390,10,*,UP,PTRANS
-S 110,40,110,170,30,*,UP,NDIF
-S 110,50,110,150,20,*,DOWN,ALU1
-S 500,50,500,150,20,*,DOWN,ALU1
-S 500,40,500,170,30,*,UP,NDIF
-S 80,60,80,190,10,*,DOWN,NTRANS
-S 470,60,470,190,10,*,DOWN,NTRANS
-S 50,80,50,170,30,*,UP,NDIF
-S 440,80,440,170,30,*,UP,NDIF
-S 80,260,80,490,10,*,UP,PTRANS
-S 50,280,50,470,30,*,DOWN,PDIF
-S 110,280,110,470,30,*,UP,PDIF
-S 470,260,470,490,10,*,UP,PTRANS
-S 500,280,500,470,30,*,UP,PDIF
-S 440,280,440,470,30,*,DOWN,PDIF
-S 110,300,110,450,20,*,DOWN,ALU1
-S 500,300,500,450,20,*,DOWN,ALU1
-S 280,510,280,740,10,*,UP,PTRANS
-S 250,530,250,720,30,*,DOWN,PDIF
-S 310,530,310,720,30,*,UP,PDIF
-S 280,810,280,940,10,*,DOWN,NTRANS
-S 310,830,310,960,30,*,DOWN,NDIF
-S 250,830,250,920,30,*,UP,NDIF
-S 310,850,310,950,20,*,DOWN,ALU1
-S 310,550,310,700,20,*,DOWN,ALU1
-S 50,530,50,720,30,*,DOWN,PDIF
-S 80,510,80,740,10,*,UP,PTRANS
-S 110,530,110,720,30,*,UP,PDIF
-S 110,550,110,700,20,*,DOWN,ALU1
-S 500,550,500,700,20,*,DOWN,ALU1
-S 440,530,440,720,30,*,DOWN,PDIF
-S 500,530,500,720,30,*,UP,PDIF
-S 470,510,470,740,10,*,UP,PTRANS
-S 0,30,500,30,60,vss,RIGHT,CALU1
-S 0,970,500,970,60,vss,RIGHT,CALU1
-S 470,740,470,860,10,*,DOWN,POLY
-S 400,800,400,800,20,reset,LEFT,CALU2
-S 400,800,470,800,30,*,RIGHT,POLY
-S 440,830,440,920,30,*,UP,NDIF
-S 470,810,470,940,10,*,DOWN,NTRANS
-S 500,830,500,960,30,*,DOWN,NDIF
-S 500,850,500,950,20,*,DOWN,ALU1
-S 450,600,450,900,20,*,DOWN,ALU1
-S 450,250,500,250,20,*,RIGHT,TALU2
-S 450,250,450,600,20,nreset,DOWN,CALU3
-S 450,600,500,600,20,*,RIGHT,TALU2
-V 250,970,CONT_BODY_P,*
-V 370,970,CONT_BODY_P,*
-V 300,750,CONT_VIA,*
-V 300,750,CONT_POLY,*
-V 100,850,CONT_VIA,*
-V 100,850,CONT_POLY,*
-V 110,950,CONT_DIF_N,*
-V 110,900,CONT_DIF_N,*
-V 50,900,CONT_DIF_N,*
-V 450,600,CONT_VIA,*
-V 450,600,CONT_VIA2,*
-V 450,250,CONT_POLY,*
-V 450,250,CONT_VIA,*
-V 450,250,CONT_VIA2,*
-V 440,30,CONT_BODY_P,*
-V 350,30,CONT_BODY_P,*
-V 230,30,CONT_BODY_P,*
-V 170,30,CONT_BODY_P,*
-V 30,30,CONT_BODY_P,*
-V 230,470,CONT_BODY_N,*
-V 170,470,CONT_BODY_N,*
-V 200,100,CONT_VIA,*
-V 200,100,CONT_POLY,*
-V 200,400,CONT_VIA,*
-V 200,400,CONT_POLY,*
-V 300,200,CONT_POLY,*
-V 230,150,CONT_DIF_N,*
-V 230,350,CONT_DIF_P,*
-V 290,450,CONT_DIF_P,*
-V 290,400,CONT_DIF_P,*
-V 290,350,CONT_DIF_P,*
-V 350,400,CONT_DIF_P,*
-V 230,300,CONT_DIF_P,*
-V 350,350,CONT_DIF_P,*
-V 290,300,CONT_DIF_P,*
-V 290,50,CONT_DIF_N,*
-V 290,100,CONT_DIF_N,*
-V 290,150,CONT_DIF_N,*
-V 350,150,CONT_DIF_N,*
-V 350,100,CONT_DIF_N,*
-V 290,50,CONT_DIF_N,*
-V 170,150,CONT_DIF_N,*
-V 100,200,CONT_POLY,*
-V 170,300,CONT_DIF_P,*
-V 110,50,CONT_DIF_N,*
-V 110,50,CONT_DIF_N,*
-V 110,150,CONT_DIF_N,*
-V 110,100,CONT_DIF_N,*
-V 50,150,CONT_DIF_N,*
-V 50,100,CONT_DIF_N,*
-V 440,150,CONT_DIF_N,*
-V 440,100,CONT_DIF_N,*
-V 500,150,CONT_DIF_N,*
-V 110,400,CONT_DIF_P,*
-V 110,450,CONT_DIF_P,*
-V 50,350,CONT_DIF_P,*
-V 50,400,CONT_DIF_P,*
-V 110,300,CONT_DIF_P,*
-V 170,350,CONT_DIF_P,*
-V 110,350,CONT_DIF_P,*
-V 500,450,CONT_DIF_P,*
-V 500,400,CONT_DIF_P,*
-V 500,350,CONT_DIF_P,*
-V 500,300,CONT_DIF_P,*
-V 440,300,CONT_DIF_P,*
-V 440,350,CONT_DIF_P,*
-V 440,400,CONT_DIF_P,*
-V 310,600,CONT_DIF_P,*
-V 310,650,CONT_DIF_P,*
-V 310,700,CONT_DIF_P,*
-V 250,600,CONT_DIF_P,*
-V 250,650,CONT_DIF_P,*
-V 250,700,CONT_DIF_P,*
-V 310,550,CONT_DIF_P,*
-V 250,900,CONT_DIF_N,*
-V 250,850,CONT_DIF_N,*
-V 310,900,CONT_DIF_N,*
-V 310,950,CONT_DIF_N,*
-V 310,850,CONT_DIF_N,*
-V 50,700,CONT_DIF_P,*
-V 50,650,CONT_DIF_P,*
-V 50,600,CONT_DIF_P,*
-V 110,700,CONT_DIF_P,*
-V 110,650,CONT_DIF_P,*
-V 110,600,CONT_DIF_P,*
-V 110,550,CONT_DIF_P,*
-V 110,950,CONT_DIF_N,*
-V 500,550,CONT_DIF_P,*
-V 500,600,CONT_DIF_P,*
-V 500,650,CONT_DIF_P,*
-V 500,700,CONT_DIF_P,*
-V 440,600,CONT_DIF_P,*
-V 500,50,CONT_DIF_N,*
-V 500,100,CONT_DIF_N,*
-V 400,800,CONT_VIA,*
-V 400,800,CONT_POLY,*
-V 440,650,CONT_DIF_P,*
-V 440,700,CONT_DIF_P,*
-V 500,850,CONT_DIF_N,*
-V 500,900,CONT_DIF_N,*
-V 440,850,CONT_DIF_N,*
-V 440,900,CONT_DIF_N,*
-V 500,950,CONT_DIF_N,*
-V 440,970,CONT_BODY_P,*
-V 180,970,CONT_BODY_P,*
-EOF
diff --git a/alliance/share/cells/rflib/rf_fifo_buf.vbe b/alliance/share/cells/rflib/rf_fifo_buf.vbe
deleted file mode 100644
index 2d64fed8..00000000
--- a/alliance/share/cells/rflib/rf_fifo_buf.vbe
+++ /dev/null
@@ -1,33 +0,0 @@
-ENTITY rf_fifo_buf IS
-PORT (
-  cks    : in  BIT;
-  ckm    : in  BIT;
-  r      : in  BIT;
-  w      : in  BIT;
-  reset  : in  BIT;
-  xcks 	 : out BIT;
-  xckm 	 : out BIT;
-  nr   	 : out BIT;
-  nw   	 : out BIT;
-  xreset : out BIT;
-  nreset : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END rf_fifo_buf;
-
-ARCHITECTURE VBE OF rf_fifo_buf IS
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on rf_fifo_clock"
-  SEVERITY WARNING;
-
-  xcks <= cks;
-  xckm <= ckm;
-  nr   <= not r;
-  nw   <= not w;
-  xreset <= reset;
-  nreset <= not reset;
-
-END;
diff --git a/alliance/share/cells/rflib/rf_fifo_clock.ap b/alliance/share/cells/rflib/rf_fifo_clock.ap
deleted file mode 100644
index 6eb26e6e..00000000
--- a/alliance/share/cells/rflib/rf_fifo_clock.ap
+++ /dev/null
@@ -1,254 +0,0 @@
-V ALLIANCE : 6
-H rf_fifo_clock,P,14/ 6/2001,10
-A 0,0,500,1000
-R 250,700,ref_ref,ck_25
-S 0,530,500,530,60,vdd,RIGHT,CALU1
-S 0,470,500,470,60,vdd,RIGHT,CALU1
-S 100,400,450,400,20,*,RIGHT,TALU2
-S 300,200,400,200,20,*,RIGHT,TALU2
-S 400,200,400,600,20,*,DOWN,TALU3
-S 350,250,350,600,20,*,DOWN,TALU3
-S 450,400,450,800,20,*,DOWN,TALU3
-S 100,850,350,850,20,*,RIGHT,TALU2
-S 300,800,450,800,20,*,RIGHT,TALU2
-S 350,850,410,850,30,*,RIGHT,POLY
-S 300,400,300,800,20,cks,UP,CALU3
-S 350,600,400,600,20,*,RIGHT,TALU2
-S 200,700,500,700,20,ck,RIGHT,CALU2
-S 40,550,40,600,20,*,UP,ALU1
-S 50,650,50,800,20,wok,UP,CALU1
-S 400,850,440,850,20,*,RIGHT,ALU1
-S 70,510,70,690,10,*,UP,PTRANS
-S 40,530,40,670,30,*,DOWN,PDIF
-S 290,690,290,860,10,*,UP,POLY
-S 450,400,450,800,20,*,DOWN,ALU3
-S 450,800,470,800,30,*,RIGHT,POLY
-S 200,700,230,700,30,*,RIGHT,POLY
-S 230,690,230,860,10,*,DOWN,POLY
-S 400,600,400,850,20,*,UP,ALU1
-S 320,600,350,600,20,*,RIGHT,ALU1
-S 320,600,320,750,20,*,DOWN,ALU1
-S 380,650,400,650,20,*,RIGHT,ALU1
-S 410,690,410,860,10,*,DOWN,POLY
-S 470,690,470,860,10,*,UP,POLY
-S 500,550,500,650,20,*,UP,ALU1
-S 180,530,180,670,70,*,UP,PDIF
-S 180,550,180,650,20,*,UP,ALU1
-S 500,530,500,670,30,*,UP,PDIF
-S 320,530,320,670,30,*,UP,PDIF
-S 260,530,260,670,30,*,UP,PDIF
-S 290,510,290,690,10,*,UP,PTRANS
-S 380,530,380,670,30,*,UP,PDIF
-S 410,510,410,690,10,*,UP,PTRANS
-S 440,530,440,670,30,*,UP,PDIF
-S 230,510,230,690,10,*,UP,PTRANS
-S 470,510,470,690,10,*,UP,PTRANS
-S 230,860,230,930,10,*,DOWN,NTRANS
-S 290,860,290,930,10,*,DOWN,NTRANS
-S 260,880,260,910,30,*,DOWN,NDIF
-S 470,860,470,930,10,*,DOWN,NTRANS
-S 410,860,410,930,10,*,DOWN,NTRANS
-S 440,880,440,910,30,*,DOWN,NDIF
-S 0,30,500,30,60,vss,RIGHT,CALU1
-S 0,970,500,970,60,vss,RIGHT,CALU1
-S 280,190,280,260,10,*,DOWN,POLY
-S 370,80,370,120,30,*,UP,NDIF
-S 250,80,250,170,30,*,UP,NDIF
-S 310,40,310,170,30,*,UP,NDIF
-S 280,60,280,190,10,*,DOWN,NTRANS
-S 340,60,340,140,10,*,DOWN,NTRANS
-S 310,280,310,470,30,*,UP,PDIF
-S 280,260,280,490,10,*,UP,PTRANS
-S 250,280,250,470,30,*,UP,PDIF
-S 500,330,500,470,30,*,UP,PDIF
-S 500,40,500,120,30,*,UP,NDIF
-S 310,300,310,450,20,*,DOWN,ALU1
-S 500,350,500,450,20,*,DOWN,ALU1
-S 500,50,500,100,20,*,DOWN,ALU1
-S 310,50,310,150,20,*,DOWN,ALU1
-S 90,300,90,450,20,*,DOWN,ALU1
-S 90,50,90,150,20,*,DOWN,ALU1
-S 120,190,120,260,10,*,DOWN,POLY
-S 90,40,90,170,30,*,UP,NDIF
-S 150,80,150,170,30,*,UP,NDIF
-S 30,80,30,120,30,*,UP,NDIF
-S 60,60,60,140,10,*,DOWN,NTRANS
-S 120,60,120,190,10,*,DOWN,NTRANS
-S 120,260,120,490,10,*,UP,PTRANS
-S 150,280,150,470,30,*,UP,PDIF
-S 90,280,90,470,30,*,UP,PDIF
-S 500,880,500,960,30,*,DOWN,NDIF
-S 380,880,380,920,30,*,DOWN,NDIF
-S 380,880,380,960,30,*,DOWN,NDIF
-S 320,880,320,960,30,*,DOWN,NDIF
-S 320,900,320,950,20,*,DOWN,ALU1
-S 500,900,500,950,20,*,DOWN,ALU1
-S 340,260,340,390,10,*,UP,PTRANS
-S 370,280,370,370,30,*,UP,PDIF
-S 340,140,340,260,10,*,DOWN,POLY
-S 370,100,370,350,20,*,DOWN,ALU1
-S 150,100,150,400,20,*,UP,ALU1
-S 250,100,250,400,20,*,UP,ALU1
-S 440,850,440,900,20,*,DOWN,ALU1
-S 190,750,320,750,20,*,RIGHT,ALU1
-S 70,690,70,810,10,*,DOWN,POLY
-S 130,690,130,810,10,*,DOWN,POLY
-S 130,510,130,690,10,*,UP,PTRANS
-S 100,830,100,970,30,*,DOWN,NDIF
-S 40,830,40,970,30,*,DOWN,NDIF
-S 70,810,70,990,10,*,DOWN,NTRANS
-S 130,810,130,990,10,*,DOWN,NTRANS
-S 100,530,100,670,30,*,UP,PDIF
-S 40,850,100,850,20,*,RIGHT,ALU1
-S 40,900,100,900,20,*,RIGHT,ALU1
-S 180,850,180,950,20,*,DOWN,ALU1
-S 180,880,180,920,30,*,DOWN,NDIF
-S 180,830,180,970,70,*,UP,NDIF
-S 30,200,100,200,20,*,RIGHT,ALU1
-S 60,250,80,250,30,*,RIGHT,POLY
-S 100,200,120,200,30,*,LEFT,POLY
-S 80,250,100,250,20,*,RIGHT,ALU1
-S 100,250,350,250,20,*,RIGHT,ALU2
-S 350,250,350,600,20,*,DOWN,ALU3
-S 300,250,370,250,20,*,RIGHT,ALU1
-S 280,250,300,250,30,*,RIGHT,POLY
-S 320,200,340,200,30,*,RIGHT,POLY
-S 300,200,400,200,20,*,RIGHT,ALU2
-S 300,200,320,200,20,*,RIGHT,ALU1
-S 400,200,400,600,20,*,DOWN,ALU3
-S 250,400,300,400,20,*,RIGHT,ALU2
-S 60,260,60,390,10,*,UP,PTRANS
-S 30,280,30,370,30,*,UP,PDIF
-S 60,140,60,260,10,*,UP,POLY
-S 30,100,30,350,20,*,DOWN,ALU1
-S 130,750,190,750,30,*,RIGHT,POLY
-S 240,750,240,900,20,*,DOWN,ALU1
-S 240,900,260,900,20,*,RIGHT,ALU1
-S 100,600,100,900,20,ckok,UP,CALU1
-S 430,100,430,400,20,*,DOWN,ALU1
-S 460,140,460,310,10,*,DOWN,POLY
-S 460,310,460,440,10,*,UP,PTRANS
-S 430,80,430,120,30,*,UP,NDIF
-S 460,60,460,140,10,*,DOWN,NTRANS
-S 430,330,430,420,30,*,UP,PDIF
-S 430,400,450,400,20,*,RIGHT,ALU1
-S 480,250,500,250,20,*,RIGHT,ALU1
-S 460,250,490,250,30,*,LEFT,POLY
-S 500,250,500,700,20,ck,DOWN,CALU3
-S 100,250,500,250,20,*,RIGHT,TALU2
-S 0,610,540,610,240,*,RIGHT,NWELL
-S 0,390,540,390,240,*,RIGHT,NWELL
-S 200,400,200,850,20,ckm,UP,CALU3
-S 150,400,200,400,20,*,RIGHT,ALU2
-S 200,850,350,850,20,*,LEFT,ALU2
-V 300,800,CONT_POLY,*
-V 300,800,CONT_VIA,*
-V 300,800,CONT_VIA2,*
-V 350,850,CONT_POLY,*
-V 350,850,CONT_VIA,*
-V 100,650,CONT_DIF_P,*
-V 100,600,CONT_DIF_P,*
-V 40,550,CONT_DIF_P,*
-V 40,600,CONT_DIF_P,*
-V 250,30,CONT_BODY_P,*
-V 150,30,CONT_BODY_P,*
-V 450,800,CONT_POLY,*
-V 450,800,CONT_VIA,*
-V 450,800,CONT_VIA2,*
-V 500,700,CONT_VIA2,*
-V 200,700,CONT_VIA,*
-V 200,700,CONT_POLY,*
-V 350,600,CONT_VIA,*
-V 350,600,CONT_VIA2,*
-V 400,600,CONT_VIA,*
-V 400,600,CONT_VIA2,*
-V 320,600,CONT_DIF_P,*
-V 380,650,CONT_DIF_P,*
-V 320,650,CONT_DIF_P,*
-V 180,600,CONT_DIF_P,*
-V 180,650,CONT_DIF_P,*
-V 180,550,CONT_DIF_P,*
-V 440,30,CONT_BODY_P,*
-V 500,50,CONT_DIF_N,*
-V 500,50,CONT_DIF_N,*
-V 500,450,CONT_DIF_P,*
-V 500,100,CONT_DIF_N,*
-V 370,30,CONT_BODY_P,*
-V 370,100,CONT_DIF_N,*
-V 310,50,CONT_DIF_N,*
-V 310,150,CONT_DIF_N,*
-V 310,100,CONT_DIF_N,*
-V 250,100,CONT_DIF_N,*
-V 250,150,CONT_DIF_N,*
-V 310,300,CONT_DIF_P,*
-V 310,350,CONT_DIF_P,*
-V 310,400,CONT_DIF_P,*
-V 310,450,CONT_DIF_P,*
-V 250,400,CONT_DIF_P,*
-V 250,350,CONT_DIF_P,*
-V 250,300,CONT_DIF_P,*
-V 500,350,CONT_DIF_P,*
-V 500,400,CONT_DIF_P,*
-V 30,30,CONT_BODY_P,*
-V 90,100,CONT_DIF_N,*
-V 90,50,CONT_DIF_N,*
-V 90,150,CONT_DIF_N,*
-V 150,100,CONT_DIF_N,*
-V 150,150,CONT_DIF_N,*
-V 30,100,CONT_DIF_N,*
-V 90,450,CONT_DIF_P,*
-V 90,300,CONT_DIF_P,*
-V 90,350,CONT_DIF_P,*
-V 150,350,CONT_DIF_P,*
-V 150,300,CONT_DIF_P,*
-V 150,400,CONT_DIF_P,*
-V 90,400,CONT_DIF_P,*
-V 500,550,CONT_DIF_P,*
-V 500,600,CONT_DIF_P,*
-V 500,650,CONT_DIF_P,*
-V 500,950,CONT_DIF_N,*
-V 500,900,CONT_DIF_N,*
-V 440,900,CONT_DIF_N,*
-V 380,900,CONT_DIF_N,*
-V 380,950,CONT_DIF_N,*
-V 440,970,CONT_BODY_P,*
-V 260,970,CONT_BODY_P,*
-V 260,900,CONT_DIF_N,*
-V 320,900,CONT_DIF_N,*
-V 320,950,CONT_DIF_N,*
-V 370,350,CONT_DIF_P,*
-V 370,300,CONT_DIF_P,*
-V 380,480,CONT_BODY_N,*
-V 440,480,CONT_BODY_N,*
-V 190,750,CONT_POLY,*
-V 40,900,CONT_DIF_N,*
-V 40,850,CONT_DIF_N,*
-V 30,480,CONT_BODY_N,*
-V 50,750,CONT_POLY,*
-V 180,900,CONT_DIF_N,*
-V 180,950,CONT_DIF_N,*
-V 180,850,CONT_DIF_N,*
-V 100,200,CONT_POLY,*
-V 80,250,CONT_POLY,*
-V 100,250,CONT_VIA,*
-V 350,250,CONT_VIA2,*
-V 300,250,CONT_POLY,*
-V 320,200,CONT_POLY,*
-V 400,200,CONT_VIA2,*
-V 300,200,CONT_VIA,*
-V 250,400,CONT_VIA,*
-V 300,400,CONT_VIA2,*
-V 150,400,CONT_VIA,*
-V 30,300,CONT_DIF_P,*
-V 30,350,CONT_DIF_P,*
-V 430,100,CONT_DIF_N,*
-V 430,400,CONT_DIF_P,*
-V 430,350,CONT_DIF_P,*
-V 450,400,CONT_VIA2,*
-V 450,400,CONT_VIA,*
-V 500,250,CONT_VIA2,*
-V 500,250,CONT_VIA,*
-V 480,250,CONT_POLY,*
-V 200,400,CONT_VIA2,*
-V 200,850,CONT_VIA2,*
-EOF
diff --git a/alliance/share/cells/rflib/rf_fifo_clock.vbe b/alliance/share/cells/rflib/rf_fifo_clock.vbe
deleted file mode 100644
index 27c0acf0..00000000
--- a/alliance/share/cells/rflib/rf_fifo_clock.vbe
+++ /dev/null
@@ -1,39 +0,0 @@
-ENTITY rf_fifo_clock IS
-PORT (
-  ck     : in  BIT;
-  wok    : in  BIT;
-  cks 	 : inout BIT;
-  ckm 	 : inout BIT;
-  ckok   : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END rf_fifo_clock;
-
-ARCHITECTURE VBE OF rf_fifo_clock IS
-
-  SIGNAL nck    : BIT;
-  SIGNAL sck    : BIT;
-  SIGNAL mck    : BIT;
-  SIGNAL nsck   : BIT;
-  SIGNAL nmck   : BIT;
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on rf_fifo_clock"
-  SEVERITY WARNING;
-
-  nck  <= not ck;
-  sck  <= nck nor ckm;
-  mck  <=  ck nor cks;
-  nmck <=  not mck;
-  nsck <=  not sck;
-  cks  <=  not nsck;
-  ckm  <=  not nmck;
-  ckok <= mck nand wok;
-
---      cks <= not(ck);
---	ckm <= ck;
---	ckok <= ckm nand wok;
-
-END;
diff --git a/alliance/share/cells/rflib/rf_fifo_empty.ap b/alliance/share/cells/rflib/rf_fifo_empty.ap
deleted file mode 100644
index d2908ef6..00000000
--- a/alliance/share/cells/rflib/rf_fifo_empty.ap
+++ /dev/null
@@ -1,94 +0,0 @@
-V ALLIANCE : 6
-H rf_fifo_empty,P,11/ 6/2000,10
-A 0,0,500,500
-S 450,150,450,400,20,empty,DOWN,CALU1
-S 100,300,100,300,20,emptynext,LEFT,CALU2
-S 90,300,120,300,30,*,RIGHT,POLY
-S 100,150,100,200,10,*,DOWN,ALU1
-S 40,200,40,400,10,*,DOWN,ALU1
-S 40,200,100,200,10,*,RIGHT,ALU1
-S 150,100,150,150,10,*,DOWN,ALU1
-S 100,150,150,150,10,*,RIGHT,ALU1
-S 40,400,90,400,10,*,LEFT,ALU1
-S 200,100,220,100,20,*,RIGHT,ALU1
-S 330,150,330,350,10,z,DOWN,ALU1
-S 220,110,300,110,10,*,RIGHT,POLY
-S 210,130,210,170,30,*,DOWN,NDIF
-S 120,140,120,360,10,*,DOWN,POLY
-S 60,140,60,360,10,*,DOWN,POLY
-S 90,380,90,470,30,*,DOWN,PDIF
-S 120,360,120,490,10,*,DOWN,PTRANS
-S 60,360,60,490,10,*,DOWN,PTRANS
-S 30,380,30,470,30,*,DOWN,PDIF
-S 150,380,150,470,30,*,DOWN,PDIF
-S 150,30,150,170,30,*,DOWN,NDIF
-S 180,110,180,190,10,*,UP,NTRANS
-S 150,200,180,200,30,*,RIGHT,POLY
-S 0,30,500,30,60,vss,RIGHT,CALU1
-S 0,470,500,470,60,vdd,RIGHT,CALU1
-S 360,190,360,310,10,*,DOWN,POLY
-S 390,30,390,170,30,*,DOWN,NDIF
-S 390,330,390,470,30,*,DOWN,PDIF
-S 180,400,230,400,50,*,RIGHT,PTRANS
-S 250,400,300,400,50,*,RIGHT,PTRANS
-S 210,300,360,300,10,*,RIGHT,POLY
-S 420,190,420,310,10,*,DOWN,POLY
-S 420,310,420,490,10,*,DOWN,PTRANS
-S 420,10,420,190,10,*,UP,NTRANS
-S 450,30,450,170,30,*,DOWN,NDIF
-S 450,330,450,470,30,*,DOWN,PDIF
-S 210,150,210,350,10,y,DOWN,ALU1
-S 400,100,400,200,10,*,DOWN,ALU1
-S 270,100,400,100,10,*,LEFT,ALU1
-S 270,100,270,350,10,t,DOWN,ALU1
-S 180,250,180,420,10,*,DOWN,POLY
-S 180,250,320,250,10,*,RIGHT,POLY
-S 0,390,500,390,240,*,RIGHT,NWELL
-S 360,310,360,390,10,*,DOWN,PTRANS
-S 330,330,330,370,30,*,DOWN,PDIF
-S 310,400,450,400,10,*,RIGHT,ALU1
-S 360,110,360,190,10,*,UP,NTRANS
-S 30,30,30,120,30,*,DOWN,NDIF
-S 90,30,90,120,30,*,DOWN,NDIF
-S 120,10,120,140,10,*,UP,NTRANS
-S 60,10,60,140,10,*,UP,NTRANS
-S 270,130,270,170,30,*,DOWN,NDIF
-S 330,130,330,170,30,*,DOWN,NDIF
-S 300,110,300,190,10,*,UP,NTRANS
-S 50,150,50,150,20,nreset,LEFT,CALU2
-S 150,200,150,200,20,ckm,LEFT,CALU2
-S 200,100,200,100,20,cks,LEFT,CALU2
-V 330,30,CONT_BODY_P,*
-V 210,30,CONT_BODY_P,*
-V 90,400,CONT_DIF_P,*
-V 150,150,CONT_DIF_N,*
-V 220,100,CONT_POLY,*
-V 200,100,CONT_VIA,*
-V 210,150,CONT_DIF_N,*
-V 50,150,CONT_POLY,*
-V 50,150,CONT_VIA,*
-V 150,200,CONT_VIA,*
-V 150,100,CONT_DIF_N,*
-V 30,50,CONT_DIF_N,*
-V 30,450,CONT_DIF_P,*
-V 150,450,CONT_DIF_P,*
-V 210,350,CONT_DIF_P,*
-V 210,450,CONT_DIF_P,*
-V 100,300,CONT_POLY,*
-V 100,300,CONT_VIA,*
-V 160,200,CONT_POLY,*
-V 390,50,CONT_DIF_N,*
-V 330,150,CONT_DIF_N,*
-V 390,450,CONT_DIF_P,*
-V 330,350,CONT_DIF_P,*
-V 270,450,CONT_DIF_P,*
-V 270,350,CONT_DIF_P,*
-V 450,350,CONT_DIF_P,*
-V 450,150,CONT_DIF_N,*
-V 400,200,CONT_POLY,*
-V 270,150,CONT_DIF_N,*
-V 320,250,CONT_POLY,*
-V 220,300,CONT_POLY,*
-V 310,400,CONT_POLY,*
-V 330,470,CONT_BODY_N,*
-EOF
diff --git a/alliance/share/cells/rflib/rf_fifo_empty.vbe b/alliance/share/cells/rflib/rf_fifo_empty.vbe
deleted file mode 100644
index f0cea2dd..00000000
--- a/alliance/share/cells/rflib/rf_fifo_empty.vbe
+++ /dev/null
@@ -1,34 +0,0 @@
-ENTITY rf_fifo_empty IS
-PORT (
-  ckm 	         : in  BIT;
-  nreset         : in  BIT;
-  emptynext 	 : in  BIT;
-  cks            : in  BIT;
-  empty          : out BIT;
-  vdd	         : in  BIT;
-  vss	         : in  BIT
-);
-END rf_fifo_empty;
-
-ARCHITECTURE VBE OF rf_fifo_empty IS
-  SIGNAL latchm	 : REG_BIT REGISTER;
-  SIGNAL latchs	 : REG_BIT REGISTER;
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on rf_fifo_empty"
-  SEVERITY WARNING;
-
-  label0 : BLOCK (ckm = '1')
-  BEGIN
-    latchm <= GUARDED (emptynext nand nreset);
-  END BLOCK label0;
-
-  label1 : BLOCK (cks = '1')
-  BEGIN
-    latchs <= GUARDED (not latchm);
-  END BLOCK label1;
-
-  empty <= (not latchs);
-
-END;
diff --git a/alliance/share/cells/rflib/rf_fifo_full.ap b/alliance/share/cells/rflib/rf_fifo_full.ap
deleted file mode 100644
index 64cf857a..00000000
--- a/alliance/share/cells/rflib/rf_fifo_full.ap
+++ /dev/null
@@ -1,95 +0,0 @@
-V ALLIANCE : 6
-H rf_fifo_full,P, 6/ 7/2000,100
-A 0,0,5000,5000
-S 900,1000,1000,1000,200,*,RIGHT,ALU1
-S 4500,1500,4500,4000,200,full,DOWN,CALU1
-S 3900,2000,4200,2000,300,*,RIGHT,POLY
-S 3300,1500,3300,3500,100,z,DOWN,ALU1
-S 1200,900,1200,2600,100,*,UP,POLY
-S 600,900,600,2600,100,*,DOWN,POLY
-S 900,2800,900,4700,300,*,DOWN,PDIF
-S 1200,2600,1200,4900,100,*,DOWN,PTRANS
-S 600,2600,600,4900,100,*,DOWN,PTRANS
-S 300,2800,300,4700,300,*,DOWN,PDIF
-S 1500,2800,1500,4700,300,*,DOWN,PDIF
-S 1000,2500,1200,2500,300,*,RIGHT,POLY
-S 300,2000,300,3000,100,*,DOWN,ALU1
-S 1600,2000,1800,2000,300,*,RIGHT,POLY
-S 2200,1100,3000,1100,100,*,RIGHT,POLY
-S 2100,1300,2100,1700,300,*,DOWN,NDIF
-S 1500,1300,1500,1700,300,*,DOWN,NDIF
-S 1800,1100,1800,1900,100,*,UP,NTRANS
-S 1500,300,1500,700,300,*,DOWN,NDIF
-S 900,300,900,1100,300,*,DOWN,NDIF
-S 1200,100,1200,900,100,*,UP,NTRANS
-S 600,100,600,900,100,*,UP,NTRANS
-S 300,300,300,700,300,*,DOWN,NDIF
-S 0,300,5000,300,600,vss,RIGHT,CALU1
-S 0,4700,5000,4700,600,vdd,RIGHT,CALU1
-S 3600,1900,3600,3100,100,*,DOWN,POLY
-S 3900,300,3900,1700,300,*,DOWN,NDIF
-S 3900,3300,3900,4700,300,*,DOWN,PDIF
-S 1800,4000,2300,4000,500,*,RIGHT,PTRANS
-S 2500,4000,3000,4000,500,*,RIGHT,PTRANS
-S 2100,3000,3600,3000,100,*,RIGHT,POLY
-S 4200,1900,4200,3100,100,*,DOWN,POLY
-S 4200,3100,4200,4900,100,*,DOWN,PTRANS
-S 4200,100,4200,1900,100,*,UP,NTRANS
-S 4500,300,4500,1700,300,*,DOWN,NDIF
-S 4500,3300,4500,4700,300,*,DOWN,PDIF
-S 2100,1500,2100,3500,100,y,DOWN,ALU1
-S 4000,1000,4000,2000,100,*,DOWN,ALU1
-S 2700,1000,4000,1000,100,*,LEFT,ALU1
-S 2700,1000,2700,3500,100,t,DOWN,ALU1
-S 1800,2500,1800,4200,100,*,DOWN,POLY
-S 1800,2500,3200,2500,100,*,RIGHT,POLY
-S 0,3900,5000,3900,2400,*,RIGHT,NWELL
-S 3600,3100,3600,3900,100,*,DOWN,PTRANS
-S 3300,3300,3300,3700,300,*,DOWN,PDIF
-S 3100,4000,4500,4000,100,*,RIGHT,ALU1
-S 3600,1100,3600,1900,100,*,UP,NTRANS
-S 2700,1300,2700,1700,300,*,DOWN,NDIF
-S 3300,1300,3300,1700,300,*,DOWN,NDIF
-S 3000,1100,3000,1900,100,*,UP,NTRANS
-S 2000,1000,2200,1000,200,*,RIGHT,ALU1
-S 500,1500,500,1500,200,reset,LEFT,CALU2
-S 1500,2000,1500,2000,200,ckm,LEFT,CALU2
-S 2000,1000,2000,1000,200,cks,LEFT,CALU2
-S 1000,2500,1000,2500,200,fullnext,LEFT,CALU2
-S 1000,1000,1000,2000,100,*,DOWN,ALU1
-S 300,2000,1000,2000,100,*,RIGHT,ALU1
-S 1000,1500,1500,1500,100,*,RIGHT,ALU1
-V 1000,2500,CONT_POLY,*
-V 1000,2500,CONT_VIA,*
-V 300,3000,CONT_DIF_P,*
-V 3300,300,CONT_BODY_P,*
-V 2100,300,CONT_BODY_P,*
-V 1600,2000,CONT_POLY,*
-V 1500,2000,CONT_VIA,*
-V 2200,1000,CONT_POLY,*
-V 500,1500,CONT_POLY,*
-V 500,1500,CONT_VIA,*
-V 2100,1500,CONT_DIF_N,*
-V 1500,1500,CONT_DIF_N,*
-V 1500,500,CONT_DIF_N,*
-V 900,1000,CONT_DIF_N,*
-V 300,500,CONT_DIF_N,*
-V 1500,4500,CONT_DIF_P,*
-V 2100,3500,CONT_DIF_P,*
-V 2100,4500,CONT_DIF_P,*
-V 3900,500,CONT_DIF_N,*
-V 3300,1500,CONT_DIF_N,*
-V 3900,4500,CONT_DIF_P,*
-V 3300,3500,CONT_DIF_P,*
-V 2700,4500,CONT_DIF_P,*
-V 2700,3500,CONT_DIF_P,*
-V 4500,3500,CONT_DIF_P,*
-V 4500,1500,CONT_DIF_N,*
-V 4000,2000,CONT_POLY,*
-V 2700,1500,CONT_DIF_N,*
-V 3200,2500,CONT_POLY,*
-V 2200,3000,CONT_POLY,*
-V 3100,4000,CONT_POLY,*
-V 3300,4700,CONT_BODY_N,*
-V 2000,1000,CONT_VIA,*
-EOF
diff --git a/alliance/share/cells/rflib/rf_fifo_full.vbe b/alliance/share/cells/rflib/rf_fifo_full.vbe
deleted file mode 100644
index 69a6c28c..00000000
--- a/alliance/share/cells/rflib/rf_fifo_full.vbe
+++ /dev/null
@@ -1,34 +0,0 @@
-ENTITY rf_fifo_full IS
-PORT (
-  ckm 	         : in  BIT;
-  reset          : in  BIT;
-  fullnext 	 : in  BIT;
-  cks            : in  BIT;
-  full           : out BIT;
-  vdd	         : in  BIT;
-  vss	         : in  BIT
-);
-END rf_fifo_full;
-
-ARCHITECTURE VBE OF rf_fifo_full IS
-  SIGNAL latchm	 : REG_BIT REGISTER;
-  SIGNAL latchs	 : REG_BIT REGISTER;
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on rf_fifo_full"
-  SEVERITY WARNING;
-
-  label0 : BLOCK (ckm = '1')
-  BEGIN
-    latchm <= GUARDED (fullnext nor reset);
-  END BLOCK label0;
-
-  label1 : BLOCK (cks = '1')
-  BEGIN
-    latchs <= GUARDED (not latchm);
-  END BLOCK label1;
-
-  full <= (not latchs);
-
-END;
diff --git a/alliance/share/cells/rflib/rf_fifo_inc.ap b/alliance/share/cells/rflib/rf_fifo_inc.ap
deleted file mode 100644
index aa9bda96..00000000
--- a/alliance/share/cells/rflib/rf_fifo_inc.ap
+++ /dev/null
@@ -1,97 +0,0 @@
-V ALLIANCE : 6
-H rf_fifo_inc,P, 6/ 7/2000,100
-A 0,0,5000,5000
-S 1100,2500,1100,3000,200,*,DOWN,ALU1
-S 1100,3000,3000,3000,200,*,RIGHT,ALU1
-S 2600,1000,2600,3000,200,*,DOWN,ALU1
-S 3000,4000,3600,4000,100,*,RIGHT,ALU1
-S 3500,4000,3800,4000,300,*,RIGHT,POLY
-S 3400,1900,4100,1900,100,*,RIGHT,ALU1
-S 3500,300,3500,700,300,*,DOWN,NDIF
-S 4100,300,4100,1100,300,*,DOWN,NDIF
-S 4100,1000,4100,4000,100,*,UP,ALU1
-S 500,1000,500,4000,200,*,UP,ALU1
-S 500,4000,500,4000,200,inc,LEFT,CALU2
-S 0,2800,0,4700,300,*,DOWN,PDIF
-S 3000,2800,3000,3700,300,*,DOWN,PDIF
-S 2400,2800,2400,3700,300,*,DOWN,PDIF
-S 3800,4100,3800,4900,100,*,UP,PTRANS
-S 3500,4300,3500,4700,300,*,UP,PDIF
-S 0,3900,5000,3900,2400,*,RIGHT,NWELL
-S 300,2600,300,4900,100,*,DOWN,PTRANS
-S 1200,2800,1200,4700,300,*,DOWN,PDIF
-S 600,2800,600,4700,300,*,DOWN,PDIF
-S 900,2600,900,4900,100,*,DOWN,PTRANS
-S 1500,2600,1500,3900,100,*,UP,PTRANS
-S 1800,2800,1800,3700,300,*,DOWN,PDIF
-S 2700,2600,2700,3900,100,*,UP,PTRANS
-S 2100,2600,2100,3900,100,*,UP,PTRANS
-S 900,600,900,1900,100,*,UP,NTRANS
-S 300,600,300,1900,100,*,UP,NTRANS
-S 1500,600,1500,1900,100,*,UP,NTRANS
-S 3800,100,3800,900,100,*,UP,NTRANS
-S 1900,600,1900,1900,100,*,UP,NTRANS
-S 2300,600,2300,1900,100,*,UP,NTRANS
-S 2600,800,2600,1700,300,*,DOWN,NDIF
-S 0,300,0,1700,300,*,DOWN,NDIF
-S 600,800,600,1700,300,*,DOWN,NDIF
-S 1200,800,1200,1700,300,*,DOWN,NDIF
-S 3800,900,3800,4100,100,*,DOWN,POLY
-S 1900,1900,1900,2600,100,*,DOWN,POLY
-S 2300,1900,3400,1900,100,*,RIGHT,POLY
-S 1500,1900,1500,2600,100,*,DOWN,POLY
-S 2700,1900,2700,2600,100,*,DOWN,POLY
-S 900,1900,900,2600,100,*,DOWN,POLY
-S 300,1900,300,2600,100,*,DOWN,POLY
-S 0,300,5000,300,600,vss,RIGHT,CALU1
-S 0,3000,0,4500,200,*,UP,ALU1
-S 0,500,0,1500,200,*,UP,ALU1
-S 1200,500,1200,1500,200,*,DOWN,ALU1
-S 0,4700,5000,4700,600,vdd,RIGHT,CALU1
-S 2400,3500,2400,4700,200,*,UP,ALU1
-S 1200,3500,1200,4500,200,*,DOWN,ALU1
-S 300,2500,1000,2500,300,*,RIGHT,POLY
-S 1500,2000,1500,2000,200,ckm,LEFT,CALU2
-S 2000,2500,2000,2500,200,nreset,LEFT,CALU2
-S 4100,3900,4100,4700,300,*,UP,PDIF
-S 3000,4000,3000,4000,200,nval,LEFT,CALU2
-V 3600,4000,CONT_POLY,*
-V 3500,500,CONT_DIF_N,*
-V 4100,1000,CONT_DIF_N,*
-V 3000,4000,CONT_VIA,*
-V 0,4000,CONT_DIF_P,*
-V 0,3500,CONT_DIF_P,*
-V 0,4500,CONT_DIF_P,*
-V 0,3000,CONT_DIF_P,*
-V 1200,4000,CONT_DIF_P,*
-V 1200,4500,CONT_DIF_P,*
-V 3000,3000,CONT_DIF_P,*
-V 1800,3000,CONT_DIF_P,*
-V 2400,3500,CONT_DIF_P,*
-V 3500,4500,CONT_DIF_P,*
-V 2400,4700,CONT_BODY_N,*
-V 1800,4700,CONT_BODY_N,*
-V 600,4000,CONT_DIF_P,*
-V 600,3500,CONT_DIF_P,*
-V 600,3000,CONT_DIF_P,*
-V 1200,3500,CONT_DIF_P,*
-V 1200,1500,CONT_DIF_N,*
-V 2600,1500,CONT_DIF_N,*
-V 2600,1000,CONT_DIF_N,*
-V 0,1000,CONT_DIF_N,*
-V 0,1500,CONT_DIF_N,*
-V 0,500,CONT_DIF_N,*
-V 600,1000,CONT_DIF_N,*
-V 600,1500,CONT_DIF_N,*
-V 1200,1000,CONT_DIF_N,*
-V 2400,300,CONT_BODY_P,*
-V 1800,300,CONT_BODY_P,*
-V 2000,2500,CONT_POLY,*
-V 3400,1900,CONT_POLY,*
-V 500,4000,CONT_VIA,*
-V 2000,2500,CONT_VIA,*
-V 1000,2500,CONT_POLY,*
-V 1500,2000,CONT_VIA,*
-V 1500,2000,CONT_POLY,*
-V 4100,4000,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/rflib/rf_fifo_inc.vbe b/alliance/share/cells/rflib/rf_fifo_inc.vbe
deleted file mode 100644
index ee01d1c5..00000000
--- a/alliance/share/cells/rflib/rf_fifo_inc.vbe
+++ /dev/null
@@ -1,21 +0,0 @@
-ENTITY rf_fifo_inc IS
-PORT (
-  ckm    : in  BIT;
-  nreset : in  BIT;
-  nval	 : in  BIT;
-  inc    : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END rf_fifo_inc;
-
-ARCHITECTURE VBE OF rf_fifo_inc IS
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on rf_fifo_inc"
-  SEVERITY WARNING;
-
-  inc <= (not nval) and nreset and ckm;
-
-END;
diff --git a/alliance/share/cells/rflib/rf_fifo_nop.ap b/alliance/share/cells/rflib/rf_fifo_nop.ap
deleted file mode 100644
index eac030ca..00000000
--- a/alliance/share/cells/rflib/rf_fifo_nop.ap
+++ /dev/null
@@ -1,107 +0,0 @@
-V ALLIANCE : 6
-H rf_fifo_nop,P, 6/ 7/2000,100
-A 0,0,5000,5000
-S 1100,2500,1100,3000,200,*,DOWN,ALU1
-S 1100,3000,3000,3000,200,*,RIGHT,ALU1
-S 2600,1000,2600,3000,200,*,DOWN,ALU1
-S 3000,4000,3000,4000,200,nval,LEFT,CALU2
-S 4000,3000,4000,3000,200,rwok,LEFT,CALU2
-S 4500,1500,4500,1500,200,rw,LEFT,CALU2
-S 3000,4000,4100,4000,100,*,RIGHT,ALU1
-S 3500,1000,3500,4000,100,*,UP,ALU1
-S 4100,3900,4100,4700,300,*,UP,PDIF
-S 2000,2500,2000,2500,200,nreset,LEFT,CALU2
-S 1500,2000,1500,2000,200,ckm,LEFT,CALU2
-S 300,2500,1000,2500,300,*,RIGHT,POLY
-S 1200,3500,1200,4500,200,*,DOWN,ALU1
-S 3800,3000,4100,3000,300,*,RIGHT,POLY
-S 500,4000,500,4000,200,nop,LEFT,CALU2
-S 2400,3500,2400,4700,200,*,UP,ALU1
-S 0,4700,5000,4700,600,vdd,RIGHT,CALU1
-S 1200,500,1200,1500,200,*,DOWN,ALU1
-S 0,500,0,1500,200,*,UP,ALU1
-S 0,3000,0,4500,200,*,UP,ALU1
-S 0,300,5000,300,600,vss,RIGHT,CALU1
-S 300,1900,300,2600,100,*,DOWN,POLY
-S 900,1900,900,2600,100,*,DOWN,POLY
-S 2700,1900,2700,2600,100,*,DOWN,POLY
-S 1500,1900,1500,2600,100,*,DOWN,POLY
-S 2300,1900,3400,1900,100,*,RIGHT,POLY
-S 1900,1900,1900,2600,100,*,DOWN,POLY
-S 4400,900,4400,4100,100,*,UP,POLY
-S 3800,900,3800,4100,100,*,DOWN,POLY
-S 1200,800,1200,1700,300,*,DOWN,NDIF
-S 600,800,600,1700,300,*,DOWN,NDIF
-S 4700,300,4700,700,300,*,DOWN,NDIF
-S 4100,300,4100,700,300,*,DOWN,NDIF
-S 0,300,0,1700,300,*,DOWN,NDIF
-S 3500,300,3500,1100,300,*,DOWN,NDIF
-S 2600,800,2600,1700,300,*,DOWN,NDIF
-S 2300,600,2300,1900,100,*,UP,NTRANS
-S 1900,600,1900,1900,100,*,UP,NTRANS
-S 3800,100,3800,900,100,*,UP,NTRANS
-S 4400,100,4400,900,100,*,UP,NTRANS
-S 1500,600,1500,1900,100,*,UP,NTRANS
-S 300,600,300,1900,100,*,UP,NTRANS
-S 900,600,900,1900,100,*,UP,NTRANS
-S 2100,2600,2100,3900,100,*,UP,PTRANS
-S 2700,2600,2700,3900,100,*,UP,PTRANS
-S 1800,2800,1800,3700,300,*,DOWN,PDIF
-S 1500,2600,1500,3900,100,*,UP,PTRANS
-S 900,2600,900,4900,100,*,DOWN,PTRANS
-S 600,2800,600,4700,300,*,DOWN,PDIF
-S 1200,2800,1200,4700,300,*,DOWN,PDIF
-S 300,2600,300,4900,100,*,DOWN,PTRANS
-S 0,3900,5000,3900,2400,*,RIGHT,NWELL
-S 4700,4300,4700,4700,300,*,UP,PDIF
-S 3500,4300,3500,4700,300,*,UP,PDIF
-S 3800,4100,3800,4900,100,*,UP,PTRANS
-S 4400,4100,4400,4900,100,*,UP,PTRANS
-S 2400,2800,2400,3700,300,*,DOWN,PDIF
-S 3000,2800,3000,3700,300,*,DOWN,PDIF
-S 0,2800,0,4700,300,*,DOWN,PDIF
-S 500,1000,500,4000,200,*,UP,ALU1
-V 3000,4000,CONT_VIA,*
-V 4100,4000,CONT_DIF_P,*
-V 1500,2000,CONT_POLY,*
-V 1500,2000,CONT_VIA,*
-V 1000,2500,CONT_POLY,*
-V 4500,1500,CONT_POLY,*
-V 4500,1500,CONT_VIA,*
-V 4000,3000,CONT_VIA,*
-V 4000,3000,CONT_POLY,*
-V 2000,2500,CONT_VIA,*
-V 500,4000,CONT_VIA,*
-V 3400,1900,CONT_POLY,*
-V 2000,2500,CONT_POLY,*
-V 1800,300,CONT_BODY_P,*
-V 2400,300,CONT_BODY_P,*
-V 1200,1000,CONT_DIF_N,*
-V 600,1500,CONT_DIF_N,*
-V 600,1000,CONT_DIF_N,*
-V 0,500,CONT_DIF_N,*
-V 0,1500,CONT_DIF_N,*
-V 0,1000,CONT_DIF_N,*
-V 4700,500,CONT_DIF_N,*
-V 3500,1000,CONT_DIF_N,*
-V 2600,1000,CONT_DIF_N,*
-V 2600,1500,CONT_DIF_N,*
-V 1200,1500,CONT_DIF_N,*
-V 1200,3500,CONT_DIF_P,*
-V 600,3000,CONT_DIF_P,*
-V 600,3500,CONT_DIF_P,*
-V 600,4000,CONT_DIF_P,*
-V 1800,4700,CONT_BODY_N,*
-V 2400,4700,CONT_BODY_N,*
-V 4700,4500,CONT_DIF_P,*
-V 3500,4500,CONT_DIF_P,*
-V 2400,3500,CONT_DIF_P,*
-V 1800,3000,CONT_DIF_P,*
-V 3000,3000,CONT_DIF_P,*
-V 1200,4500,CONT_DIF_P,*
-V 1200,4000,CONT_DIF_P,*
-V 0,3000,CONT_DIF_P,*
-V 0,4500,CONT_DIF_P,*
-V 0,3500,CONT_DIF_P,*
-V 0,4000,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/rflib/rf_fifo_nop.vbe b/alliance/share/cells/rflib/rf_fifo_nop.vbe
deleted file mode 100644
index b032c3a1..00000000
--- a/alliance/share/cells/rflib/rf_fifo_nop.vbe
+++ /dev/null
@@ -1,24 +0,0 @@
-ENTITY rf_fifo_nop IS
-PORT (
-  ckm    : in  BIT;
-  nreset : in  BIT;
-  rw     : in  BIT;
-  rwok   : in  BIT;
-  nval	 : inout BIT;
-  nop    : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END rf_fifo_nop;
-
-ARCHITECTURE VBE OF rf_fifo_nop IS
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on rf_fifo_nop"
-  SEVERITY WARNING;
-
-  nval <= rw nand rwok;
-  nop <= nval and nreset and ckm;
-
-END;
diff --git a/alliance/share/cells/rflib/rf_fifo_ok.ap b/alliance/share/cells/rflib/rf_fifo_ok.ap
deleted file mode 100644
index e36b9f07..00000000
--- a/alliance/share/cells/rflib/rf_fifo_ok.ap
+++ /dev/null
@@ -1,100 +0,0 @@
-V ALLIANCE : 6
-H rf_fifo_ok,P,11/ 6/2000,10
-A 0,0,500,500
-S 250,150,250,300,10,*,UP,ALU1
-S 250,150,330,150,10,*,RIGHT,ALU1
-S 270,300,270,400,10,*,DOWN,ALU1
-S 450,350,450,350,20,ripple,LEFT,CALU2
-S 330,400,450,400,10,*,RIGHT,ALU1
-S 270,100,450,100,10,*,RIGHT,ALU1
-S 200,150,200,150,20,nrw,LEFT,CALU2
-S 350,250,350,250,20,rw,LEFT,CALU2
-S 50,200,300,200,20,prev,RIGHT,CALU2
-S 100,100,100,400,20,ok,DOWN,CALU1
-S 210,350,210,450,20,*,UP,ALU1
-S 150,50,150,100,20,*,DOWN,ALU1
-S 30,50,30,100,20,*,DOWN,ALU1
-S 150,350,150,450,20,*,UP,ALU1
-S 30,300,30,450,20,*,DOWN,ALU1
-S 40,200,120,200,30,*,RIGHT,POLY
-S 150,300,270,300,10,*,RIGHT,ALU1
-S 450,250,450,350,10,*,DOWN,ALU1
-S 420,250,460,250,30,*,RIGHT,POLY
-S 210,290,210,470,30,*,DOWN,PDIF
-S 240,140,240,270,10,*,UP,POLY
-S 240,270,240,490,10,*,UP,PTRANS
-S 210,30,210,120,30,*,UP,NDIF
-S 240,10,240,140,10,*,DOWN,NTRANS
-S 270,290,270,470,30,*,DOWN,PDIF
-S 300,140,300,270,10,*,UP,POLY
-S 300,270,300,490,10,*,UP,PTRANS
-S 270,30,270,120,30,*,UP,NDIF
-S 300,10,300,140,10,*,DOWN,NTRANS
-S 330,290,330,470,30,*,DOWN,PDIF
-S 360,140,360,270,10,*,UP,POLY
-S 360,270,360,490,10,*,UP,PTRANS
-S 330,30,330,120,30,*,UP,NDIF
-S 360,10,360,140,10,*,DOWN,NTRANS
-S 390,290,390,470,30,*,DOWN,PDIF
-S 420,140,420,270,10,*,UP,POLY
-S 420,270,420,490,10,*,UP,PTRANS
-S 390,30,390,120,30,*,UP,NDIF
-S 420,10,420,140,10,*,DOWN,NTRANS
-S 450,290,450,470,30,*,DOWN,PDIF
-S 450,30,450,120,30,*,UP,NDIF
-S 0,390,500,390,240,,RIGHT,NWELL
-S 0,30,500,30,60,vss,RIGHT,CALU1
-S 0,470,500,470,60,vdd,RIGHT,CALU1
-S 330,100,330,150,30,,UP,NDIF
-S 60,140,60,270,10,*,UP,POLY
-S 120,140,120,270,10,*,UP,POLY
-S 30,30,30,120,30,*,UP,NDIF
-S 90,30,90,120,30,*,UP,NDIF
-S 150,30,150,120,30,*,UP,NDIF
-S 60,10,60,140,10,*,DOWN,NTRANS
-S 120,10,120,140,10,*,DOWN,NTRANS
-S 90,290,90,470,30,*,DOWN,PDIF
-S 120,270,120,490,10,*,UP,PTRANS
-S 150,290,150,470,30,*,DOWN,PDIF
-S 30,290,30,470,30,*,DOWN,PDIF
-S 60,270,60,490,10,*,UP,PTRANS
-S 190,150,240,150,30,*,RIGHT,POLY
-S 150,300,150,300,20,nextval,LEFT,CALU2
-V 150,100,CONT_DIF_N,*
-V 30,100,CONT_DIF_N,*
-V 30,300,CONT_DIF_P,*
-V 30,350,CONT_DIF_P,*
-V 30,400,CONT_DIF_P,*
-V 150,350,CONT_DIF_P,*
-V 150,400,CONT_DIF_P,*
-V 210,350,CONT_DIF_P,*
-V 210,400,CONT_DIF_P,*
-V 90,350,CONT_DIF_P,*
-V 90,300,CONT_DIF_P,*
-V 50,200,CONT_POLY,*
-V 50,200,CONT_VIA,*
-V 150,300,CONT_VIA,*
-V 450,250,CONT_POLY,*
-V 450,350,CONT_VIA,*
-V 210,450,CONT_DIF_P,*
-V 210,50,CONT_DIF_N,*
-V 270,400,CONT_DIF_P,*
-V 330,400,CONT_DIF_P,*
-V 390,450,CONT_DIF_P,*
-V 450,400,CONT_DIF_P,*
-V 330,150,CONT_DIF_N,*
-V 450,100,CONT_DIF_N,*
-V 270,100,CONT_DIF_N,*
-V 90,100,CONT_DIF_N,*
-V 30,50,CONT_DIF_N,*
-V 30,450,CONT_DIF_P,*
-V 90,400,CONT_DIF_P,*
-V 150,450,CONT_DIF_P,*
-V 150,50,CONT_DIF_N,*
-V 350,250,CONT_POLY,*
-V 300,200,CONT_POLY,*
-V 300,200,CONT_VIA,*
-V 350,250,CONT_VIA,*
-V 200,150,CONT_VIA,*
-V 200,150,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/rflib/rf_fifo_ok.vbe b/alliance/share/cells/rflib/rf_fifo_ok.vbe
deleted file mode 100644
index 5537c904..00000000
--- a/alliance/share/cells/rflib/rf_fifo_ok.vbe
+++ /dev/null
@@ -1,24 +0,0 @@
-ENTITY rf_fifo_ok IS
-PORT (
-  rw      : in  BIT;
-  ripple  : in  BIT;
-  nrw 	  : in  BIT;
-  prev    : in  BIT;
-  nextval : out BIT;
-  ok      : out BIT;
-  vdd	  : in  BIT;
-  vss	  : in  BIT
-);
-END rf_fifo_ok;
-
-ARCHITECTURE VBE OF rf_fifo_ok IS
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on rf_fifo_ok"
-  SEVERITY WARNING;
-
-  ok <= (not prev);
-  nextval <= not(((rw and ripple) or prev) and nrw);
-
-END;
diff --git a/alliance/share/cells/rflib/rf_fifo_orand4.ap b/alliance/share/cells/rflib/rf_fifo_orand4.ap
deleted file mode 100644
index dfe080d6..00000000
--- a/alliance/share/cells/rflib/rf_fifo_orand4.ap
+++ /dev/null
@@ -1,79 +0,0 @@
-V ALLIANCE : 6
-H rf_fifo_orand4,P,11/ 6/2000,10
-A 0,0,500,500
-S 150,100,290,100,10,*,RIGHT,ALU1
-S 150,350,230,350,10,*,RIGHT,ALU1
-S 150,100,150,350,10,*,DOWN,ALU1
-S 250,150,250,300,10,b1,DOWN,CALU1
-S 200,150,200,300,10,a1,DOWN,CALU1
-S 380,270,380,490,10,*,UP,PTRANS
-S 410,290,410,470,30,*,DOWN,PDIF
-S 290,290,290,470,30,*,DOWN,PDIF
-S 320,270,320,490,10,*,UP,PTRANS
-S 350,290,350,470,30,*,DOWN,PDIF
-S 290,290,290,470,30,*,DOWN,PDIF
-S 260,270,260,490,10,*,UP,PTRANS
-S 230,290,230,470,30,*,DOWN,PDIF
-S 200,270,200,490,10,*,UP,PTRANS
-S 170,290,170,470,30,*,DOWN,PDIF
-S 260,10,260,140,10,*,DOWN,NTRANS
-S 200,10,200,140,10,*,DOWN,NTRANS
-S 320,10,320,140,10,*,DOWN,NTRANS
-S 380,10,380,140,10,*,DOWN,NTRANS
-S 290,30,290,120,30,*,UP,NDIF
-S 350,30,350,120,30,*,UP,NDIF
-S 410,30,410,120,30,*,UP,NDIF
-S 290,30,290,120,30,*,UP,NDIF
-S 230,30,230,120,30,*,UP,NDIF
-S 170,30,170,120,30,*,UP,NDIF
-S 320,250,340,250,30,,LEFT,POLY
-S 320,140,320,270,10,*,UP,POLY
-S 380,140,380,270,10,*,UP,POLY
-S 380,250,400,250,30,,RIGHT,POLY
-S 260,140,260,270,10,*,UP,POLY
-S 200,140,200,270,10,*,UP,POLY
-S 400,100,400,350,10,b0,DOWN,CALU1
-S 350,100,350,350,10,a0,DOWN,CALU1
-S 290,400,410,400,10,aux11,RIGHT,ALU1
-S 170,400,290,400,10,aux12,RIGHT,ALU1
-S 100,100,100,400,10,rippleout,UP,CALU1
-S 0,470,500,470,60,vdd,RIGHT,CALU1
-S 40,30,40,100,20,*,DOWN,ALU1
-S 40,300,40,470,20,*,DOWN,ALU1
-S 0,30,500,30,60,vss,RIGHT,CALU1
-S 70,160,70,270,10,*,DOWN,POLY
-S 70,200,150,200,30,*,RIGHT,POLY
-S 100,80,100,140,30,*,DOWN,NDIF
-S 40,80,40,140,30,*,DOWN,NDIF
-S 70,60,70,160,10,*,UP,NTRANS
-S 0,390,500,390,240,,RIGHT,NWELL
-S 100,290,100,420,30,*,UP,PDIF
-S 40,290,40,420,30,*,UP,PDIF
-S 70,270,70,440,10,*,DOWN,PTRANS
-V 150,200,CONT_POLY,*
-V 200,250,CONT_POLY,*
-V 340,250,CONT_POLY,*
-V 410,400,CONT_DIF_P,*
-V 290,400,CONT_DIF_P,*
-V 230,350,CONT_DIF_P,*
-V 350,450,CONT_DIF_P,*
-V 290,400,CONT_DIF_P,*
-V 170,400,CONT_DIF_P,*
-V 410,50,CONT_DIF_N,*
-V 290,100,CONT_DIF_N,*
-V 170,50,CONT_DIF_N,*
-V 400,250,CONT_POLY,*
-V 260,250,CONT_POLY,*
-V 40,30,CONT_BODY_P,*
-V 100,30,CONT_BODY_P,*
-V 100,100,CONT_DIF_N,*
-V 40,100,CONT_DIF_N,*
-V 40,350,CONT_DIF_P,*
-V 40,470,CONT_BODY_N,*
-V 100,470,CONT_BODY_N,*
-V 40,300,CONT_DIF_P,*
-V 40,400,CONT_DIF_P,*
-V 100,300,CONT_DIF_P,*
-V 100,350,CONT_DIF_P,*
-V 100,400,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/rflib/rf_fifo_orand4.vbe b/alliance/share/cells/rflib/rf_fifo_orand4.vbe
deleted file mode 100644
index fae9974d..00000000
--- a/alliance/share/cells/rflib/rf_fifo_orand4.vbe
+++ /dev/null
@@ -1,22 +0,0 @@
-ENTITY rf_fifo_orand4 IS
-PORT (
-  a0        : in  BIT;
-  b0        : in  BIT;
-  a1        : in  BIT;
-  b1        : in  BIT;
-  rippleout : out BIT;
-  vdd	    : in  BIT;
-  vss       : in  BIT
-);
-END rf_fifo_orand4;
-
-ARCHITECTURE VBE OF rf_fifo_orand4 IS
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on rf_fifo_orand4"
-  SEVERITY WARNING;
-
-  rippleout <= (a0 and b0) or (a1 and b1);
-
-END;
diff --git a/alliance/share/cells/rflib/rf_fifo_orand5.ap b/alliance/share/cells/rflib/rf_fifo_orand5.ap
deleted file mode 100644
index e49afec6..00000000
--- a/alliance/share/cells/rflib/rf_fifo_orand5.ap
+++ /dev/null
@@ -1,86 +0,0 @@
-V ALLIANCE : 6
-H rf_fifo_orand5,P,11/ 6/2000,10
-A 0,0,500,500
-S 100,100,100,400,10,rippleout,UP,CALU1
-S 250,150,250,300,10,b1,DOWN,CALU1
-S 200,150,200,300,10,a1,DOWN,CALU1
-S 450,150,450,300,10,b0,DOWN,CALU1
-S 350,150,350,300,10,a0,DOWN,CALU1
-S 300,150,300,300,10,ripplein,DOWN,CALU1
-S 280,100,460,100,10,sor,RIGHT,ALU1
-S 0,470,500,470,60,vdd,RIGHT,CALU1
-S 40,30,40,100,20,*,DOWN,ALU1
-S 40,300,40,470,20,*,DOWN,ALU1
-S 150,100,460,100,10,sor,RIGHT,ALU1
-S 150,100,150,350,10,*,DOWN,ALU1
-S 150,350,400,350,10,sor,RIGHT,ALU1
-S 160,400,280,400,10,aux12,RIGHT,ALU1
-S 340,400,460,400,10,aux11,RIGHT,ALU1
-S 0,30,500,30,60,vss,RIGHT,CALU1
-S 310,140,310,270,10,*,UP,POLY
-S 250,140,250,270,10,*,UP,POLY
-S 190,140,190,270,10,*,UP,POLY
-S 350,250,370,250,30,,LEFT,POLY
-S 430,140,430,270,10,*,UP,POLY
-S 370,140,370,270,10,*,UP,POLY
-S 70,160,70,270,10,*,DOWN,POLY
-S 70,200,150,200,30,*,RIGHT,POLY
-S 430,250,450,250,30,,RIGHT,POLY
-S 280,30,280,120,30,*,UP,NDIF
-S 220,30,220,120,30,*,UP,NDIF
-S 160,30,160,120,30,*,UP,NDIF
-S 460,30,460,120,30,*,UP,NDIF
-S 400,30,400,120,30,*,UP,NDIF
-S 340,30,340,120,30,*,UP,NDIF
-S 100,80,100,140,30,*,DOWN,NDIF
-S 40,80,40,140,30,*,DOWN,NDIF
-S 70,60,70,160,10,*,UP,NTRANS
-S 430,10,430,140,10,*,DOWN,NTRANS
-S 370,10,370,140,10,*,DOWN,NTRANS
-S 310,10,310,140,10,*,DOWN,NTRANS
-S 250,10,250,140,10,*,DOWN,NTRANS
-S 190,10,190,140,10,*,DOWN,NTRANS
-S 340,290,340,470,30,*,DOWN,PDIF
-S 310,270,310,490,10,*,UP,PTRANS
-S 280,290,280,470,30,*,DOWN,PDIF
-S 250,270,250,490,10,*,UP,PTRANS
-S 220,290,220,470,30,*,DOWN,PDIF
-S 190,270,190,490,10,*,UP,PTRANS
-S 160,290,160,470,30,*,DOWN,PDIF
-S 0,390,500,390,240,,RIGHT,NWELL
-S 100,290,100,420,30,*,UP,PDIF
-S 40,290,40,420,30,*,UP,PDIF
-S 70,270,70,440,10,*,DOWN,PTRANS
-S 460,290,460,470,30,*,DOWN,PDIF
-S 430,270,430,490,10,*,UP,PTRANS
-S 400,290,400,470,30,*,DOWN,PDIF
-S 370,270,370,490,10,*,UP,PTRANS
-V 300,250,CONT_POLY,*
-V 250,250,CONT_POLY,*
-V 200,250,CONT_POLY,*
-V 150,200,CONT_POLY,*
-V 450,250,CONT_POLY,*
-V 350,250,CONT_POLY,*
-V 40,30,CONT_BODY_P,*
-V 100,30,CONT_BODY_P,*
-V 460,100,CONT_DIF_N,*
-V 340,50,CONT_DIF_N,*
-V 280,100,CONT_DIF_N,*
-V 160,50,CONT_DIF_N,*
-V 100,100,CONT_DIF_N,*
-V 40,100,CONT_DIF_N,*
-V 40,350,CONT_DIF_P,*
-V 280,400,CONT_DIF_P,*
-V 160,400,CONT_DIF_P,*
-V 460,400,CONT_DIF_P,*
-V 40,470,CONT_BODY_N,*
-V 100,470,CONT_BODY_N,*
-V 220,450,CONT_DIF_P,*
-V 40,300,CONT_DIF_P,*
-V 40,400,CONT_DIF_P,*
-V 100,300,CONT_DIF_P,*
-V 100,350,CONT_DIF_P,*
-V 100,400,CONT_DIF_P,*
-V 400,350,CONT_DIF_P,*
-V 340,400,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/rflib/rf_fifo_orand5.vbe b/alliance/share/cells/rflib/rf_fifo_orand5.vbe
deleted file mode 100644
index 6307f9c8..00000000
--- a/alliance/share/cells/rflib/rf_fifo_orand5.vbe
+++ /dev/null
@@ -1,23 +0,0 @@
-ENTITY rf_fifo_orand5 IS
-PORT (
-  a0        : in  BIT;
-  b0        : in  BIT;
-  a1        : in  BIT;
-  b1        : in  BIT;
-  ripplein  : in  BIT;
-  rippleout : out BIT;
-  vdd	    : in  BIT;
-  vss       : in  BIT
-);
-END rf_fifo_orand5;
-
-ARCHITECTURE VBE OF rf_fifo_orand5 IS
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on rf_fifo_orand5"
-  SEVERITY WARNING;
-
-  rippleout <= ripplein or (a0 and b0) or (a1 and b1);
-
-END;
diff --git a/alliance/share/cells/rflib/rf_fifo_ptreset.ap b/alliance/share/cells/rflib/rf_fifo_ptreset.ap
deleted file mode 100644
index 0ed7fd35..00000000
--- a/alliance/share/cells/rflib/rf_fifo_ptreset.ap
+++ /dev/null
@@ -1,119 +0,0 @@
-V ALLIANCE : 6
-H rf_fifo_ptreset,P,11/ 6/2000,10
-A 0,0,500,500
-S 100,200,400,200,20,*,RIGHT,TALU2
-S 150,200,150,200,20,cks,LEFT,CALU3
-S 350,200,350,200,20,nop,LEFT,CALU3
-S 250,200,250,200,20,reset,LEFT,CALU3
-S 300,200,300,200,20,inc,LEFT,CALU3
-S 100,200,150,200,20,*,LEFT,ALU2
-S 350,200,400,200,20,*,RIGHT,ALU2
-S 0,390,500,390,240,*,RIGHT,NWELL
-S 0,50,0,150,20,*,DOWN,ALU1
-S 500,50,500,150,20,*,UP,ALU1
-S 440,100,450,100,20,*,RIGHT,ALU1
-S 440,400,450,400,20,*,RIGHT,ALU1
-S 50,100,60,100,20,*,RIGHT,ALU1
-S 50,400,60,400,20,*,RIGHT,ALU1
-S 210,190,250,190,10,*,RIGHT,POLY
-S 450,100,450,400,20,pt,DOWN,ALU1
-S 300,100,300,100,20,ptm1,LEFT,CALU2
-S 30,250,350,250,10,*,LEFT,POLY
-S 150,300,470,300,10,*,RIGHT,POLY
-S 370,100,370,150,20,*,DOWN,ALU1
-S 350,150,350,350,20,x,UP,ALU1
-S 120,100,150,100,20,*,RIGHT,ALU1
-S 150,100,150,350,20,z,UP,ALU1
-S 50,100,50,400,20,y,DOWN,ALU1
-S 240,150,360,150,20,*,LEFT,ALU1
-S 240,100,240,150,20,*,UP,ALU1
-S 0,350,0,450,20,*,DOWN,ALU1
-S 500,350,500,450,20,*,UP,ALU1
-S 290,190,330,190,10,*,RIGHT,POLY
-S 470,190,470,310,10,*,DOWN,POLY
-S 30,190,30,310,10,*,DOWN,POLY
-S 30,310,30,490,10,*,DOWN,PTRANS
-S 0,330,0,470,30,*,DOWN,PDIF
-S 60,330,60,470,30,*,DOWN,PDIF
-S 30,10,30,190,10,*,UP,NTRANS
-S 0,30,0,170,30,*,DOWN,NDIF
-S 60,30,60,170,30,*,DOWN,NDIF
-S 500,330,500,470,30,*,DOWN,PDIF
-S 500,30,500,170,30,*,DOWN,NDIF
-S 440,330,440,470,30,*,DOWN,PDIF
-S 440,30,440,170,30,*,DOWN,NDIF
-S 470,310,470,490,10,*,DOWN,PTRANS
-S 470,10,470,190,10,*,UP,NTRANS
-S 0,470,500,470,60,vdd,RIGHT,CALU1
-S 0,30,500,30,60,vss,RIGHT,CALU1
-S 330,400,380,400,50,*,RIGHT,PTRANS
-S 120,400,170,400,50,*,RIGHT,PTRANS
-S 50,350,400,350,20,*,LEFT,ALU2
-S 180,400,440,400,20,*,RIGHT,ALU1
-S 180,380,180,420,30,*,DOWN,POLY
-S 390,380,390,420,30,*,DOWN,POLY
-S 400,350,400,420,30,*,UP,POLY
-S 330,60,330,190,10,*,UP,NTRANS
-S 300,80,300,170,30,*,DOWN,NDIF
-S 410,60,410,190,10,*,UP,NTRANS
-S 370,80,370,170,50,*,DOWN,NDIF
-S 210,60,210,190,10,*,UP,NTRANS
-S 180,40,180,170,30,*,DOWN,NDIF
-S 240,80,240,170,30,*,DOWN,NDIF
-S 90,60,90,190,10,*,UP,NTRANS
-S 120,80,120,170,30,*,DOWN,NDIF
-S 400,100,450,100,20,pt,LEFT,CALU2
-S 50,350,400,350,20,*,RIGHT,TALU2
-V 150,200,CONT_VIA2,*
-V 350,200,CONT_VIA2,*
-V 300,200,CONT_VIA2,*
-V 250,200,CONT_VIA2,*
-V 250,200,CONT_POLY,*
-V 250,200,CONT_VIA,*
-V 300,200,CONT_VIA,*
-V 400,200,CONT_VIA,*
-V 290,470,CONT_BODY_N,*
-V 210,470,CONT_BODY_N,*
-V 450,100,CONT_VIA,*
-V 370,100,CONT_DIF_N,*
-V 370,150,CONT_DIF_N,*
-V 150,300,CONT_POLY,*
-V 350,350,CONT_DIF_P,*
-V 150,350,CONT_DIF_P,*
-V 100,200,CONT_VIA,*
-V 240,100,CONT_DIF_N,*
-V 240,150,CONT_DIF_N,*
-V 0,350,CONT_DIF_P,*
-V 0,400,CONT_DIF_P,*
-V 500,400,CONT_DIF_P,*
-V 500,350,CONT_DIF_P,*
-V 0,100,CONT_DIF_N,*
-V 0,150,CONT_DIF_N,*
-V 500,100,CONT_DIF_N,*
-V 500,150,CONT_DIF_N,*
-V 300,100,CONT_VIA,*
-V 400,200,CONT_POLY,*
-V 350,250,CONT_POLY,*
-V 300,100,CONT_DIF_N,*
-V 300,200,CONT_POLY,*
-V 180,50,CONT_DIF_N,*
-V 100,200,CONT_POLY,*
-V 0,450,CONT_DIF_P,*
-V 500,450,CONT_DIF_P,*
-V 0,50,CONT_DIF_N,*
-V 500,50,CONT_DIF_N,*
-V 120,100,CONT_DIF_N,*
-V 60,400,CONT_DIF_P,*
-V 60,100,CONT_DIF_N,*
-V 440,400,CONT_DIF_P,*
-V 440,100,CONT_DIF_N,*
-V 350,450,CONT_DIF_P,*
-V 150,450,CONT_DIF_P,*
-V 180,400,CONT_POLY,*
-V 400,350,CONT_POLY,*
-V 50,350,CONT_VIA,*
-V 400,350,CONT_VIA,*
-V 300,30,CONT_BODY_P,*
-V 370,30,CONT_BODY_P,*
-V 120,30,CONT_BODY_P,*
-EOF
diff --git a/alliance/share/cells/rflib/rf_fifo_ptreset.vbe b/alliance/share/cells/rflib/rf_fifo_ptreset.vbe
deleted file mode 100644
index 392a043d..00000000
--- a/alliance/share/cells/rflib/rf_fifo_ptreset.vbe
+++ /dev/null
@@ -1,45 +0,0 @@
-ENTITY rf_fifo_ptreset IS
-PORT (
-  nop 	 : in  BIT;
-  inc 	 : in  BIT;
-  cks    : in  BIT;
-  reset  : in  BIT;
-  ptm1   : in  BIT;
-  pt     : inout BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END rf_fifo_ptreset;
-
-ARCHITECTURE VBE OF rf_fifo_ptreset IS
-  SIGNAL latchm	 : REG_BIT REGISTER;
-  SIGNAL latchs	 : REG_BIT REGISTER;
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on rf_fifo_ptreset"
-  SEVERITY WARNING;
-
-  label0 : BLOCK (inc = '1')
-  BEGIN
-    latchm <= GUARDED ptm1;
-  END BLOCK label0;
-
-  label1 : BLOCK (reset = '1')
-  BEGIN
-    latchm <= GUARDED '0';
-  END BLOCK label1;
-
-  label2 : BLOCK (nop = '1')
-  BEGIN
-    latchm <= GUARDED pt;
-  END BLOCK label2;
-
-  label3 : BLOCK (cks = '1')
-  BEGIN
-    latchs <= GUARDED (not latchm);
-  END BLOCK label3;
-
-  pt <= (not latchs);
-
-END;
diff --git a/alliance/share/cells/rflib/rf_fifo_ptset.ap b/alliance/share/cells/rflib/rf_fifo_ptset.ap
deleted file mode 100644
index 2bcc24cf..00000000
--- a/alliance/share/cells/rflib/rf_fifo_ptset.ap
+++ /dev/null
@@ -1,115 +0,0 @@
-V ALLIANCE : 6
-H rf_fifo_ptset,P,11/ 6/2000,10
-A 0,0,500,500
-S 50,350,400,350,20,*,RIGHT,TALU2
-S 100,200,400,200,20,*,RIGHT,TALU2
-S 350,200,350,200,20,nop,LEFT,CALU3
-S 450,100,450,400,20,*,DOWN,ALU1
-S 400,100,450,100,20,pt,LEFT,CALU2
-S 120,80,120,170,30,*,DOWN,NDIF
-S 90,60,90,190,10,*,UP,NTRANS
-S 300,80,300,170,30,*,DOWN,NDIF
-S 370,80,370,170,50,*,DOWN,NDIF
-S 410,60,410,190,10,*,UP,NTRANS
-S 330,60,330,190,10,*,UP,NTRANS
-S 180,400,440,400,20,*,RIGHT,ALU1
-S 200,150,200,300,20,*,DOWN,ALU1
-S 280,350,350,350,20,*,RIGHT,ALU1
-S 200,150,350,150,20,*,RIGHT,ALU1
-S 350,100,350,350,20,x,UP,ALU1
-S 350,100,370,100,20,*,RIGHT,ALU1
-S 180,380,180,420,30,*,DOWN,POLY
-S 390,340,390,420,30,*,UP,POLY
-S 50,400,60,400,20,*,RIGHT,ALU1
-S 50,100,60,100,20,*,RIGHT,ALU1
-S 440,100,450,100,20,*,RIGHT,ALU1
-S 440,400,450,400,20,*,RIGHT,ALU1
-S 50,350,400,350,20,*,RIGHT,ALU2
-S 330,400,380,400,50,*,RIGHT,PTRANS
-S 120,400,170,400,50,*,RIGHT,PTRANS
-S 30,300,200,300,10,*,RIGHT,POLY
-S 150,250,470,250,10,*,RIGHT,POLY
-S 220,330,220,470,30,*,DOWN,PDIF
-S 280,330,280,470,30,*,DOWN,PDIF
-S 250,310,250,490,10,*,DOWN,PTRANS
-S 0,30,500,30,60,vss,RIGHT,CALU1
-S 0,470,500,470,60,vdd,RIGHT,CALU1
-S 470,10,470,190,10,*,UP,NTRANS
-S 470,310,470,490,10,*,DOWN,PTRANS
-S 440,30,440,170,30,*,DOWN,NDIF
-S 440,330,440,470,30,*,DOWN,PDIF
-S 500,30,500,170,30,*,DOWN,NDIF
-S 500,330,500,470,30,*,DOWN,PDIF
-S 60,30,60,170,30,*,DOWN,NDIF
-S 0,30,0,170,30,*,DOWN,NDIF
-S 30,10,30,190,10,*,UP,NTRANS
-S 60,330,60,470,30,*,DOWN,PDIF
-S 0,330,0,470,30,*,DOWN,PDIF
-S 30,310,30,490,10,*,DOWN,PTRANS
-S 30,190,30,310,10,*,DOWN,POLY
-S 470,190,470,310,10,*,DOWN,POLY
-S 290,190,330,190,10,*,RIGHT,POLY
-S 500,350,500,450,20,*,UP,ALU1
-S 0,350,0,450,20,*,DOWN,ALU1
-S 50,100,50,400,20,y,DOWN,ALU1
-S 150,100,150,350,20,z,UP,ALU1
-S 120,100,150,100,20,*,RIGHT,ALU1
-S 300,100,300,100,20,ptm1,LEFT,CALU2
-S 250,200,250,300,20,*,DOWN,ALU1
-S 500,50,500,150,20,*,UP,ALU1
-S 0,50,0,150,20,*,DOWN,ALU1
-S 0,390,500,390,240,*,RIGHT,NWELL
-S 250,200,250,200,20,nreset,LEFT,CALU3
-S 150,200,150,200,20,cks,LEFT,CALU3
-S 350,200,400,200,20,*,RIGHT,ALU2
-S 100,200,150,200,20,*,LEFT,ALU2
-S 300,200,300,200,20,inc,LEFT,CALU3
-V 370,30,CONT_BODY_P,*
-V 300,30,CONT_BODY_P,*
-V 120,30,CONT_BODY_P,*
-V 400,350,CONT_POLY,*
-V 400,350,CONT_VIA,*
-V 50,350,CONT_VIA,*
-V 350,450,CONT_DIF_P,*
-V 150,450,CONT_DIF_P,*
-V 180,400,CONT_POLY,*
-V 200,300,CONT_POLY,*
-V 250,300,CONT_POLY,*
-V 150,250,CONT_POLY,*
-V 280,350,CONT_DIF_P,*
-V 220,450,CONT_DIF_P,*
-V 440,100,CONT_DIF_N,*
-V 440,400,CONT_DIF_P,*
-V 60,100,CONT_DIF_N,*
-V 60,400,CONT_DIF_P,*
-V 120,100,CONT_DIF_N,*
-V 500,50,CONT_DIF_N,*
-V 0,50,CONT_DIF_N,*
-V 500,450,CONT_DIF_P,*
-V 0,450,CONT_DIF_P,*
-V 100,200,CONT_POLY,*
-V 300,200,CONT_POLY,*
-V 300,100,CONT_DIF_N,*
-V 400,200,CONT_POLY,*
-V 300,100,CONT_VIA,*
-V 500,150,CONT_DIF_N,*
-V 500,100,CONT_DIF_N,*
-V 0,150,CONT_DIF_N,*
-V 0,100,CONT_DIF_N,*
-V 500,350,CONT_DIF_P,*
-V 500,400,CONT_DIF_P,*
-V 0,400,CONT_DIF_P,*
-V 0,350,CONT_DIF_P,*
-V 100,200,CONT_VIA,*
-V 150,350,CONT_DIF_P,*
-V 350,350,CONT_DIF_P,*
-V 370,100,CONT_DIF_N,*
-V 450,100,CONT_VIA,*
-V 250,200,CONT_VIA,*
-V 300,200,CONT_VIA,*
-V 400,200,CONT_VIA,*
-V 150,200,CONT_VIA2,*
-V 250,200,CONT_VIA2,*
-V 300,200,CONT_VIA2,*
-V 350,200,CONT_VIA2,*
-EOF
diff --git a/alliance/share/cells/rflib/rf_fifo_ptset.vbe b/alliance/share/cells/rflib/rf_fifo_ptset.vbe
deleted file mode 100644
index ac804b83..00000000
--- a/alliance/share/cells/rflib/rf_fifo_ptset.vbe
+++ /dev/null
@@ -1,45 +0,0 @@
-ENTITY rf_fifo_ptset IS
-PORT (
-  nop 	 : in  BIT;
-  inc 	 : in  BIT;
-  cks    : in  BIT;
-  nreset : in  BIT;
-  ptm1   : in  BIT;
-  pt     : inout BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END rf_fifo_ptset;
-
-ARCHITECTURE VBE OF rf_fifo_ptset IS
-  SIGNAL latchm	 : REG_BIT REGISTER;
-  SIGNAL latchs	 : REG_BIT REGISTER;
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on rf_fifo_ptset"
-  SEVERITY WARNING;
-
-  label0 : BLOCK (inc = '1')
-  BEGIN
-    latchm <= GUARDED ptm1;
-  END BLOCK label0;
-
-  label1 : BLOCK (nreset = '0')
-  BEGIN
-    latchm <= GUARDED '1';
-  END BLOCK label1;
-
-  label2 : BLOCK (nop = '1')
-  BEGIN
-    latchm <= GUARDED pt;
-  END BLOCK label2;
-
-  label3 : BLOCK (cks = '1')
-  BEGIN
-    latchs <= GUARDED (not latchm);
-  END BLOCK label3;
-
-  pt <= (not latchs);
-
-END;
diff --git a/alliance/share/cells/rflib/rf_inmux_buf_2.ap b/alliance/share/cells/rflib/rf_inmux_buf_2.ap
deleted file mode 100644
index 109b056c..00000000
--- a/alliance/share/cells/rflib/rf_inmux_buf_2.ap
+++ /dev/null
@@ -1,206 +0,0 @@
-V ALLIANCE : 6
-H rf_inmux_buf_2,P,13/ 3/2001,10
-A 0,0,450,1000
-S 270,400,390,400,20,*,RIGHT,ALU2
-S 250,150,250,150,20,sel1,LEFT,CALU3
-S 350,400,350,400,20,sel0,LEFT,CALU3
-S 30,540,30,720,30,*,DOWN,PDIF
-S 90,540,90,720,30,*,DOWN,PDIF
-S 60,520,60,740,10,*,UP,PTRANS
-S 300,750,470,750,120,*,LEFT,NWELL
-S 60,800,150,800,10,*,RIGHT,POLY
-S 210,550,210,650,20,*,DOWN,ALU1
-S 60,740,60,870,10,*,DOWN,POLY
-S 150,650,210,650,20,*,RIGHT,ALU1
-S 90,600,150,600,20,*,RIGHT,ALU1
-S 90,600,90,900,20,*,DOWN,ALU1
-S 120,600,180,600,30,*,RIGHT,POLY
-S 180,490,180,600,10,*,UP,POLY
-S 120,490,120,600,10,*,UP,POLY
-S 60,490,180,490,10,*,RIGHT,POLY
-S 90,890,90,970,30,*,UP,NDIF
-S 30,890,30,970,30,*,UP,NDIF
-S 30,840,30,950,20,*,UP,ALU1
-S 60,870,60,990,10,*,DOWN,NTRANS
-S 30,550,30,700,20,*,DOWN,ALU1
-S 450,350,450,450,20,*,DOWN,ALU1
-S 450,550,450,700,20,*,DOWN,ALU1
-S 180,130,180,260,10,*,UP,POLY
-S 120,130,120,260,10,*,DOWN,POLY
-S 60,130,60,260,10,*,DOWN,POLY
-S 120,10,120,130,10,*,UP,NTRANS
-S 180,10,180,130,10,*,UP,NTRANS
-S 300,10,300,130,10,*,UP,NTRANS
-S 360,10,360,130,10,*,UP,NTRANS
-S 420,10,420,130,10,*,UP,NTRANS
-S 0,610,470,610,240,*,RIGHT,NWELL
-S 0,390,470,390,240,*,RIGHT,NWELL
-S 450,890,450,970,30,*,UP,NDIF
-S 450,530,450,720,30,*,DOWN,PDIF
-S 210,280,210,470,30,*,DOWN,PDIF
-S 390,280,390,470,30,*,DOWN,PDIF
-S 270,280,270,470,30,*,DOWN,PDIF
-S 360,260,360,490,10,*,UP,PTRANS
-S 300,260,300,490,10,*,UP,PTRANS
-S 330,280,330,470,30,*,DOWN,PDIF
-S 60,10,60,130,10,*,UP,NTRANS
-S 330,30,330,110,30,*,DOWN,NDIF
-S 390,30,390,110,30,*,DOWN,NDIF
-S 450,30,450,110,30,*,DOWN,NDIF
-S 270,30,270,110,30,*,DOWN,NDIF
-S 210,30,210,110,30,*,DOWN,NDIF
-S 150,30,150,110,30,*,DOWN,NDIF
-S 90,30,90,110,30,*,DOWN,NDIF
-S 30,30,30,110,30,*,DOWN,NDIF
-S 180,260,180,490,10,*,UP,PTRANS
-S 120,260,120,490,10,*,UP,PTRANS
-S 60,260,60,490,10,*,UP,PTRANS
-S 150,280,150,470,30,*,DOWN,PDIF
-S 90,280,90,470,30,*,DOWN,PDIF
-S 30,280,30,470,30,*,DOWN,PDIF
-S 30,300,30,450,20,*,DOWN,ALU1
-S 90,100,90,400,20,*,DOWN,ALU1
-S 210,100,210,400,20,*,DOWN,ALU1
-S 270,100,270,400,20,*,DOWN,ALU1
-S 390,100,390,400,20,*,DOWN,ALU1
-S 300,130,300,260,10,*,DOWN,POLY
-S 360,130,360,260,10,*,DOWN,POLY
-S 330,550,330,790,20,*,UP,ALU1
-S 270,600,270,900,20,*,DOWN,ALU1
-S 360,740,360,870,10,*,UP,POLY
-S 300,740,300,870,10,*,UP,POLY
-S 240,740,240,870,10,*,UP,POLY
-S 420,740,420,870,10,*,UP,POLY
-S 210,530,210,720,30,*,DOWN,PDIF
-S 420,510,420,740,10,*,UP,PTRANS
-S 390,530,390,720,30,*,DOWN,PDIF
-S 240,510,240,740,10,*,UP,PTRANS
-S 270,530,270,720,30,*,DOWN,PDIF
-S 360,510,360,740,10,*,UP,PTRANS
-S 300,510,300,740,10,*,UP,PTRANS
-S 330,530,330,720,30,*,DOWN,PDIF
-S 420,870,420,990,10,*,DOWN,NTRANS
-S 330,890,330,970,30,*,UP,NDIF
-S 210,890,210,970,30,*,UP,NDIF
-S 390,890,390,970,30,*,UP,NDIF
-S 240,870,240,990,10,*,DOWN,NTRANS
-S 270,890,270,970,30,*,UP,NDIF
-S 360,870,360,990,10,*,DOWN,NTRANS
-S 300,870,300,990,10,*,DOWN,NTRANS
-S 190,750,420,750,30,*,LEFT,POLY
-S 450,330,450,470,30,*,DOWN,PDIF
-S 420,310,420,490,10,*,UP,PTRANS
-S 420,130,420,310,10,*,DOWN,POLY
-S 330,300,330,450,20,*,DOWN,ALU1
-S 150,300,150,450,20,*,DOWN,ALU1
-S 210,240,420,240,30,*,LEFT,POLY
-S 60,240,180,240,30,*,LEFT,POLY
-S 150,50,150,160,20,*,DOWN,ALU1
-S 330,50,330,160,20,*,DOWN,ALU1
-S 30,50,30,160,20,*,DOWN,ALU1
-S 450,50,450,100,20,*,DOWN,ALU1
-S 0,970,450,970,60,vss,RIGHT,CALU1
-S 0,30,450,30,60,vss,RIGHT,CALU1
-S 0,470,450,470,60,vdd,LEFT,CALU1
-S 0,530,450,530,60,vdd,LEFT,CALU1
-S 150,700,150,900,20,sel,UP,CALU1
-S 450,900,450,950,20,vdd,DOWN,ALU1
-S 200,700,200,900,20,ck,UP,CALU1
-S 390,600,390,900,20,*,DOWN,ALU1
-S 350,900,350,900,20,nck,LEFT,CALU2
-S 270,900,390,900,20,vdd,RIGHT,ALU1
-S 90,150,250,150,20,*,RIGHT,ALU2
-S 50,150,250,150,20,*,RIGHT,TALU2
-S 250,400,400,400,20,*,RIGHT,TALU2
-V 250,150,CONT_VIA2,*
-V 350,400,CONT_VIA2,*
-V 150,800,CONT_POLY,*
-V 150,650,CONT_BODY_N,*
-V 150,600,CONT_POLY,*
-V 150,540,CONT_BODY_N,*
-V 90,900,CONT_DIF_N,*
-V 30,900,CONT_DIF_N,*
-V 30,950,CONT_DIF_N,*
-V 30,840,CONT_BODY_P,*
-V 90,650,CONT_DIF_P,*
-V 90,600,CONT_DIF_P,*
-V 90,700,CONT_DIF_P,*
-V 30,600,CONT_DIF_P,*
-V 30,650,CONT_DIF_P,*
-V 30,700,CONT_DIF_P,*
-V 30,550,CONT_DIF_P,*
-V 450,700,CONT_DIF_P,*
-V 150,100,CONT_DIF_N,*
-V 330,100,CONT_DIF_N,*
-V 390,400,CONT_VIA,*
-V 270,400,CONT_VIA,*
-V 450,950,CONT_DIF_N,*
-V 450,900,CONT_DIF_N,*
-V 450,650,CONT_DIF_P,*
-V 450,600,CONT_DIF_P,*
-V 450,550,CONT_DIF_P,*
-V 270,350,CONT_DIF_P,*
-V 330,450,CONT_DIF_P,*
-V 330,400,CONT_DIF_P,*
-V 330,300,CONT_DIF_P,*
-V 330,350,CONT_DIF_P,*
-V 390,400,CONT_DIF_P,*
-V 390,350,CONT_DIF_P,*
-V 270,400,CONT_DIF_P,*
-V 30,50,CONT_DIF_N,*
-V 150,50,CONT_DIF_N,*
-V 330,50,CONT_DIF_N,*
-V 450,50,CONT_DIF_N,*
-V 30,300,CONT_DIF_P,*
-V 30,400,CONT_DIF_P,*
-V 30,350,CONT_DIF_P,*
-V 30,450,CONT_DIF_P,*
-V 150,450,CONT_DIF_P,*
-V 150,350,CONT_DIF_P,*
-V 150,400,CONT_DIF_P,*
-V 150,300,CONT_DIF_P,*
-V 450,400,CONT_DIF_P,*
-V 450,350,CONT_DIF_P,*
-V 390,300,CONT_DIF_P,*
-V 270,300,CONT_DIF_P,*
-V 90,100,CONT_DIF_N,*
-V 210,100,CONT_DIF_N,*
-V 270,100,CONT_DIF_N,*
-V 390,100,CONT_DIF_N,*
-V 210,350,CONT_DIF_P,*
-V 210,400,CONT_DIF_P,*
-V 210,300,CONT_DIF_P,*
-V 90,400,CONT_DIF_P,*
-V 90,350,CONT_DIF_P,*
-V 90,300,CONT_DIF_P,*
-V 330,790,CONT_BODY_N,*
-V 210,550,CONT_DIF_P,*
-V 270,600,CONT_DIF_P,*
-V 330,700,CONT_DIF_P,*
-V 330,650,CONT_DIF_P,*
-V 330,550,CONT_DIF_P,*
-V 330,600,CONT_DIF_P,*
-V 390,700,CONT_DIF_P,*
-V 390,650,CONT_DIF_P,*
-V 390,600,CONT_DIF_P,*
-V 270,700,CONT_DIF_P,*
-V 270,650,CONT_DIF_P,*
-V 210,600,CONT_DIF_P,*
-V 210,650,CONT_DIF_P,*
-V 390,900,CONT_DIF_N,*
-V 210,950,CONT_DIF_N,*
-V 270,900,CONT_DIF_N,*
-V 330,950,CONT_DIF_N,*
-V 200,750,CONT_POLY,*
-V 450,450,CONT_DIF_P,*
-V 330,160,CONT_BODY_P,*
-V 220,240,CONT_POLY,*
-V 210,150,CONT_VIA,*
-V 150,160,CONT_BODY_P,*
-V 30,160,CONT_BODY_P,*
-V 30,100,CONT_DIF_N,*
-V 450,100,CONT_DIF_N,*
-V 150,950,CONT_BODY_P,*
-V 350,900,CONT_VIA,*
-V 90,150,CONT_VIA,*
-EOF
diff --git a/alliance/share/cells/rflib/rf_inmux_buf_2.vbe b/alliance/share/cells/rflib/rf_inmux_buf_2.vbe
deleted file mode 100644
index 29ceb42c..00000000
--- a/alliance/share/cells/rflib/rf_inmux_buf_2.vbe
+++ /dev/null
@@ -1,24 +0,0 @@
-ENTITY rf_inmux_buf_2 IS
-PORT (
-  ck     : in  BIT;
-  sel    : in  BIT;
-  nck 	 : out BIT;
-  sel0	 : out BIT;
-  sel1	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END rf_inmux_buf_2;
-
-ARCHITECTURE VBE OF rf_inmux_buf_2 IS
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on rf_inmux_buf_2"
-  SEVERITY WARNING;
-
-  nck <= not ck;
-  sel1 <= sel;
-  sel0 <= not sel;
-
-END;
diff --git a/alliance/share/cells/rflib/rf_inmux_buf_4.ap b/alliance/share/cells/rflib/rf_inmux_buf_4.ap
deleted file mode 100644
index 64935b6d..00000000
--- a/alliance/share/cells/rflib/rf_inmux_buf_4.ap
+++ /dev/null
@@ -1,359 +0,0 @@
-V ALLIANCE : 6
-H rf_inmux_buf_4,P,10/11/2000,10
-A 0,0,450,2000
-S 50,2000,150,2000,20,*,RIGHT,TALU2
-S 50,0,150,0,20,*,RIGHT,TALU2
-S 50,1000,150,1000,20,*,RIGHT,TALU2
-S 60,800,150,800,30,*,RIGHT,POLY
-S 0,1390,470,1390,240,*,LEFT,NWELL
-S 90,890,90,1110,30,*,UP,NDIF
-S 30,1280,30,1460,30,*,DOWN,PDIF
-S 90,1280,90,1460,30,*,DOWN,PDIF
-S 60,1260,60,1480,10,*,UP,PTRANS
-S 30,1030,30,1110,30,*,UP,NDIF
-S 60,1010,60,1130,10,*,DOWN,NTRANS
-S 120,1400,180,1400,30,*,LEFT,POLY
-S 180,1400,180,1510,10,*,UP,POLY
-S 120,1400,120,1510,10,*,UP,POLY
-S 60,1130,60,1260,10,*,DOWN,POLY
-S 30,1300,30,1450,20,*,DOWN,ALU1
-S 90,1400,150,1400,20,*,LEFT,ALU1
-S 90,1100,90,1400,20,*,DOWN,ALU1
-S 30,1050,30,1160,20,*,UP,ALU1
-S 450,1530,450,1670,30,*,DOWN,PDIF
-S 420,1510,420,1690,10,*,UP,PTRANS
-S 180,1510,180,1740,10,*,UP,PTRANS
-S 120,1510,120,1740,10,*,UP,PTRANS
-S 60,1510,60,1740,10,*,UP,PTRANS
-S 150,1530,150,1720,30,*,DOWN,PDIF
-S 90,1530,90,1720,30,*,DOWN,PDIF
-S 30,1530,30,1720,30,*,DOWN,PDIF
-S 0,1610,470,1610,240,*,LEFT,NWELL
-S 210,1530,210,1720,30,*,DOWN,PDIF
-S 390,1530,390,1720,30,*,DOWN,PDIF
-S 270,1530,270,1720,30,*,DOWN,PDIF
-S 360,1510,360,1740,10,*,UP,PTRANS
-S 300,1510,300,1740,10,*,UP,PTRANS
-S 330,1530,330,1720,30,*,DOWN,PDIF
-S 210,1890,210,1970,30,*,DOWN,NDIF
-S 150,1890,150,1970,30,*,DOWN,NDIF
-S 90,1890,90,1970,30,*,DOWN,NDIF
-S 30,1890,30,1970,30,*,DOWN,NDIF
-S 420,1870,420,1990,10,*,UP,NTRANS
-S 60,1870,60,1990,10,*,UP,NTRANS
-S 330,1890,330,1970,30,*,DOWN,NDIF
-S 390,1890,390,1970,30,*,DOWN,NDIF
-S 450,1890,450,1970,30,*,DOWN,NDIF
-S 270,1890,270,1970,30,*,DOWN,NDIF
-S 120,1870,120,1990,10,*,UP,NTRANS
-S 180,1870,180,1990,10,*,UP,NTRANS
-S 300,1870,300,1990,10,*,UP,NTRANS
-S 360,1870,360,1990,10,*,UP,NTRANS
-S 420,1690,420,1870,10,*,DOWN,POLY
-S 210,1760,420,1760,30,*,RIGHT,POLY
-S 60,1760,180,1760,30,*,RIGHT,POLY
-S 300,1740,300,1870,10,*,DOWN,POLY
-S 360,1740,360,1870,10,*,DOWN,POLY
-S 60,1510,180,1510,10,*,LEFT,POLY
-S 180,1740,180,1870,10,*,UP,POLY
-S 120,1740,120,1870,10,*,DOWN,POLY
-S 60,1740,60,1870,10,*,DOWN,POLY
-S 330,1550,330,1700,20,*,DOWN,ALU1
-S 150,1550,150,1700,20,*,DOWN,ALU1
-S 150,1840,150,1950,20,*,DOWN,ALU1
-S 330,1840,330,1950,20,*,DOWN,ALU1
-S 30,1840,30,1950,20,*,DOWN,ALU1
-S 450,1900,450,1950,20,*,DOWN,ALU1
-S 90,1600,90,1900,20,*,DOWN,ALU1
-S 210,1600,210,1900,20,*,DOWN,ALU1
-S 270,1600,270,1900,20,*,DOWN,ALU1
-S 390,1600,390,1900,20,*,DOWN,ALU1
-S 450,1550,450,1650,20,*,DOWN,ALU1
-S 30,1550,30,1700,20,*,DOWN,ALU1
-S 270,1600,390,1600,20,*,LEFT,ALU2
-S 90,1850,250,1850,20,*,LEFT,ALU2
-S 450,50,450,100,20,*,DOWN,ALU1
-S 30,50,30,160,20,*,DOWN,ALU1
-S 90,150,250,150,20,*,RIGHT,ALU2
-S 330,50,330,160,20,*,DOWN,ALU1
-S 150,50,150,160,20,*,DOWN,ALU1
-S 60,240,180,240,30,*,LEFT,POLY
-S 210,240,420,240,30,*,LEFT,POLY
-S 150,300,150,450,20,*,DOWN,ALU1
-S 330,300,330,450,20,*,DOWN,ALU1
-S 420,130,420,310,10,*,DOWN,POLY
-S 420,310,420,490,10,*,UP,PTRANS
-S 450,330,450,470,30,*,DOWN,PDIF
-S 190,750,420,750,30,*,LEFT,POLY
-S 300,870,300,990,10,*,DOWN,NTRANS
-S 360,870,360,990,10,*,DOWN,NTRANS
-S 270,890,270,970,30,*,UP,NDIF
-S 240,870,240,990,10,*,DOWN,NTRANS
-S 390,890,390,970,30,*,UP,NDIF
-S 210,890,210,970,30,*,UP,NDIF
-S 330,890,330,970,30,*,UP,NDIF
-S 420,870,420,990,10,*,DOWN,NTRANS
-S 330,530,330,720,30,*,DOWN,PDIF
-S 300,510,300,740,10,*,UP,PTRANS
-S 360,510,360,740,10,*,UP,PTRANS
-S 270,530,270,720,30,*,DOWN,PDIF
-S 240,510,240,740,10,*,UP,PTRANS
-S 390,530,390,720,30,*,DOWN,PDIF
-S 420,510,420,740,10,*,UP,PTRANS
-S 210,530,210,720,30,*,DOWN,PDIF
-S 420,740,420,870,10,*,UP,POLY
-S 240,740,240,870,10,*,UP,POLY
-S 300,740,300,870,10,*,UP,POLY
-S 360,740,360,870,10,*,UP,POLY
-S 390,600,390,900,20,*,DOWN,ALU1
-S 270,600,270,900,20,*,DOWN,ALU1
-S 330,550,330,790,20,*,UP,ALU1
-S 360,130,360,260,10,*,DOWN,POLY
-S 300,130,300,260,10,*,DOWN,POLY
-S 390,100,390,400,20,*,DOWN,ALU1
-S 270,100,270,400,20,*,DOWN,ALU1
-S 210,100,210,400,20,*,DOWN,ALU1
-S 90,100,90,400,20,*,DOWN,ALU1
-S 30,300,30,450,20,*,DOWN,ALU1
-S 30,280,30,470,30,*,DOWN,PDIF
-S 90,280,90,470,30,*,DOWN,PDIF
-S 150,280,150,470,30,*,DOWN,PDIF
-S 60,260,60,490,10,*,UP,PTRANS
-S 120,260,120,490,10,*,UP,PTRANS
-S 180,260,180,490,10,*,UP,PTRANS
-S 30,30,30,110,30,*,DOWN,NDIF
-S 90,30,90,110,30,*,DOWN,NDIF
-S 150,30,150,110,30,*,DOWN,NDIF
-S 210,30,210,110,30,*,DOWN,NDIF
-S 270,30,270,110,30,*,DOWN,NDIF
-S 450,30,450,110,30,*,DOWN,NDIF
-S 390,30,390,110,30,*,DOWN,NDIF
-S 330,30,330,110,30,*,DOWN,NDIF
-S 60,10,60,130,10,*,UP,NTRANS
-S 330,280,330,470,30,*,DOWN,PDIF
-S 300,260,300,490,10,*,UP,PTRANS
-S 360,260,360,490,10,*,UP,PTRANS
-S 270,280,270,470,30,*,DOWN,PDIF
-S 390,280,390,470,30,*,DOWN,PDIF
-S 210,280,210,470,30,*,DOWN,PDIF
-S 450,530,450,720,30,*,DOWN,PDIF
-S 450,890,450,970,30,*,UP,NDIF
-S 0,390,470,390,240,*,RIGHT,NWELL
-S 0,610,470,610,240,*,RIGHT,NWELL
-S 420,10,420,130,10,*,UP,NTRANS
-S 360,10,360,130,10,*,UP,NTRANS
-S 300,10,300,130,10,*,UP,NTRANS
-S 180,10,180,130,10,*,UP,NTRANS
-S 120,10,120,130,10,*,UP,NTRANS
-S 60,130,60,260,10,*,DOWN,POLY
-S 120,130,120,260,10,*,DOWN,POLY
-S 180,130,180,260,10,*,UP,POLY
-S 270,400,390,400,20,*,RIGHT,ALU2
-S 450,550,450,700,20,*,DOWN,ALU1
-S 450,350,450,450,20,*,DOWN,ALU1
-S 30,550,30,700,20,*,DOWN,ALU1
-S 60,870,60,990,10,*,DOWN,NTRANS
-S 30,840,30,950,20,*,UP,ALU1
-S 30,890,30,970,30,*,UP,NDIF
-S 60,490,180,490,10,*,RIGHT,POLY
-S 120,490,120,600,10,*,UP,POLY
-S 180,490,180,600,10,*,UP,POLY
-S 120,600,180,600,30,*,RIGHT,POLY
-S 90,600,90,900,20,*,DOWN,ALU1
-S 90,600,150,600,20,*,RIGHT,ALU1
-S 150,650,210,650,20,*,RIGHT,ALU1
-S 60,740,60,870,10,*,DOWN,POLY
-S 210,550,210,650,20,*,DOWN,ALU1
-S 300,750,470,750,120,*,LEFT,NWELL
-S 60,520,60,740,10,*,UP,PTRANS
-S 90,540,90,720,30,*,DOWN,PDIF
-S 30,540,30,720,30,*,DOWN,PDIF
-S 0,1470,450,1470,60,vdd,RIGHT,CALU1
-S 0,1530,450,1530,60,vdd,RIGHT,CALU1
-S 0,470,450,470,60,vdd,RIGHT,CALU1
-S 0,530,450,530,60,vdd,RIGHT,CALU1
-S 0,970,450,970,60,vss,RIGHT,CALU1
-S 0,1030,450,1030,60,vss,RIGHT,CALU1
-S 0,1970,450,1970,60,vss,LEFT,CALU1
-S 0,30,450,30,60,vss,RIGHT,CALU1
-S 250,150,250,1850,20,sel1,DOWN,CALU3
-S 350,400,350,1600,20,sel0,UP,CALU3
-S 90,1850,250,1850,20,*,RIGHT,TALU2
-S 270,1600,390,1600,20,*,RIGHT,TALU2
-S 90,150,250,150,20,*,RIGHT,TALU2
-S 270,400,390,400,20,*,RIGHT,TALU2
-S 90,240,210,240,20,*,RIGHT,ALU1
-S 270,240,390,240,20,*,RIGHT,ALU1
-S 150,700,150,900,20,sel,UP,CALU1
-S 200,700,200,900,20,ck,UP,CALU1
-S 330,900,330,950,20,*,UP,ALU1
-S 450,900,450,950,20,*,DOWN,ALU1
-S 270,900,390,900,20,nck,RIGHT,CALU2
-S 100,0,100,2000,120,vss,UP,CALU3
-V 380,1040,CONT_BODY_P,*
-V 380,1460,CONT_BODY_N,*
-V 300,1040,CONT_BODY_P,*
-V 200,1040,CONT_BODY_P,*
-V 300,1460,CONT_BODY_N,*
-V 210,1460,CONT_BODY_N,*
-V 30,1450,CONT_DIF_P,*
-V 150,1460,CONT_BODY_N,*
-V 90,1350,CONT_DIF_P,*
-V 90,1400,CONT_DIF_P,*
-V 90,1300,CONT_DIF_P,*
-V 30,1400,CONT_DIF_P,*
-V 30,1350,CONT_DIF_P,*
-V 30,1300,CONT_DIF_P,*
-V 90,1100,CONT_DIF_N,*
-V 30,1100,CONT_DIF_N,*
-V 30,1050,CONT_DIF_N,*
-V 30,1160,CONT_BODY_P,*
-V 150,1400,CONT_POLY,*
-V 450,1550,CONT_DIF_P,*
-V 270,1700,CONT_DIF_P,*
-V 210,1650,CONT_DIF_P,*
-V 210,1600,CONT_DIF_P,*
-V 210,1700,CONT_DIF_P,*
-V 90,1600,CONT_DIF_P,*
-V 90,1650,CONT_DIF_P,*
-V 90,1700,CONT_DIF_P,*
-V 30,1550,CONT_DIF_P,*
-V 150,1550,CONT_DIF_P,*
-V 150,1650,CONT_DIF_P,*
-V 150,1600,CONT_DIF_P,*
-V 150,1700,CONT_DIF_P,*
-V 450,1600,CONT_DIF_P,*
-V 450,1650,CONT_DIF_P,*
-V 390,1700,CONT_DIF_P,*
-V 330,1700,CONT_DIF_P,*
-V 330,1650,CONT_DIF_P,*
-V 390,1600,CONT_DIF_P,*
-V 390,1650,CONT_DIF_P,*
-V 270,1600,CONT_DIF_P,*
-V 30,1700,CONT_DIF_P,*
-V 30,1600,CONT_DIF_P,*
-V 30,1650,CONT_DIF_P,*
-V 270,1650,CONT_DIF_P,*
-V 330,1550,CONT_DIF_P,*
-V 330,1600,CONT_DIF_P,*
-V 30,1900,CONT_DIF_N,*
-V 450,1900,CONT_DIF_N,*
-V 150,1950,CONT_DIF_N,*
-V 330,1950,CONT_DIF_N,*
-V 450,1950,CONT_DIF_N,*
-V 90,1900,CONT_DIF_N,*
-V 210,1900,CONT_DIF_N,*
-V 270,1900,CONT_DIF_N,*
-V 390,1900,CONT_DIF_N,*
-V 150,1900,CONT_DIF_N,*
-V 330,1900,CONT_DIF_N,*
-V 30,1950,CONT_DIF_N,*
-V 150,1840,CONT_BODY_P,*
-V 30,1840,CONT_BODY_P,*
-V 330,1840,CONT_BODY_P,*
-V 220,1760,CONT_POLY,*
-V 210,1850,CONT_VIA,*
-V 390,1600,CONT_VIA,*
-V 270,1600,CONT_VIA,*
-V 90,1850,CONT_VIA,*
-V 250,1850,CONT_VIA2,*
-V 350,1600,CONT_VIA2,*
-V 450,100,CONT_DIF_N,*
-V 30,100,CONT_DIF_N,*
-V 30,160,CONT_BODY_P,*
-V 90,150,CONT_VIA,*
-V 150,160,CONT_BODY_P,*
-V 210,150,CONT_VIA,*
-V 220,240,CONT_POLY,*
-V 330,160,CONT_BODY_P,*
-V 450,450,CONT_DIF_P,*
-V 200,750,CONT_POLY,*
-V 330,950,CONT_DIF_N,*
-V 270,900,CONT_DIF_N,*
-V 210,950,CONT_DIF_N,*
-V 390,900,CONT_DIF_N,*
-V 210,650,CONT_DIF_P,*
-V 210,600,CONT_DIF_P,*
-V 270,650,CONT_DIF_P,*
-V 270,700,CONT_DIF_P,*
-V 390,600,CONT_DIF_P,*
-V 390,650,CONT_DIF_P,*
-V 390,700,CONT_DIF_P,*
-V 330,600,CONT_DIF_P,*
-V 330,550,CONT_DIF_P,*
-V 330,650,CONT_DIF_P,*
-V 330,700,CONT_DIF_P,*
-V 270,600,CONT_DIF_P,*
-V 210,550,CONT_DIF_P,*
-V 330,790,CONT_BODY_N,*
-V 390,900,CONT_VIA,*
-V 270,900,CONT_VIA,*
-V 90,300,CONT_DIF_P,*
-V 90,350,CONT_DIF_P,*
-V 90,400,CONT_DIF_P,*
-V 210,300,CONT_DIF_P,*
-V 210,400,CONT_DIF_P,*
-V 210,350,CONT_DIF_P,*
-V 390,100,CONT_DIF_N,*
-V 270,100,CONT_DIF_N,*
-V 210,100,CONT_DIF_N,*
-V 90,100,CONT_DIF_N,*
-V 270,300,CONT_DIF_P,*
-V 390,300,CONT_DIF_P,*
-V 450,350,CONT_DIF_P,*
-V 450,400,CONT_DIF_P,*
-V 150,300,CONT_DIF_P,*
-V 150,400,CONT_DIF_P,*
-V 150,350,CONT_DIF_P,*
-V 150,450,CONT_DIF_P,*
-V 30,450,CONT_DIF_P,*
-V 30,350,CONT_DIF_P,*
-V 30,400,CONT_DIF_P,*
-V 30,300,CONT_DIF_P,*
-V 450,50,CONT_DIF_N,*
-V 330,50,CONT_DIF_N,*
-V 150,50,CONT_DIF_N,*
-V 30,50,CONT_DIF_N,*
-V 270,400,CONT_DIF_P,*
-V 390,350,CONT_DIF_P,*
-V 390,400,CONT_DIF_P,*
-V 330,350,CONT_DIF_P,*
-V 330,300,CONT_DIF_P,*
-V 330,400,CONT_DIF_P,*
-V 330,450,CONT_DIF_P,*
-V 270,350,CONT_DIF_P,*
-V 450,550,CONT_DIF_P,*
-V 450,600,CONT_DIF_P,*
-V 450,650,CONT_DIF_P,*
-V 450,900,CONT_DIF_N,*
-V 450,950,CONT_DIF_N,*
-V 270,400,CONT_VIA,*
-V 390,400,CONT_VIA,*
-V 350,400,CONT_VIA2,*
-V 330,100,CONT_DIF_N,*
-V 150,100,CONT_DIF_N,*
-V 450,700,CONT_DIF_P,*
-V 250,150,CONT_VIA2,*
-V 30,550,CONT_DIF_P,*
-V 30,700,CONT_DIF_P,*
-V 30,650,CONT_DIF_P,*
-V 30,600,CONT_DIF_P,*
-V 90,700,CONT_DIF_P,*
-V 90,600,CONT_DIF_P,*
-V 90,650,CONT_DIF_P,*
-V 30,840,CONT_BODY_P,*
-V 30,950,CONT_DIF_N,*
-V 30,900,CONT_DIF_N,*
-V 90,900,CONT_DIF_N,*
-V 150,540,CONT_BODY_N,*
-V 150,600,CONT_POLY,*
-V 150,650,CONT_BODY_N,*
-V 150,800,CONT_POLY,*
-V 330,900,CONT_DIF_N,*
-B 100,1000,120,20,CONT_VIA2,*
-B 100,1000,120,20,CONT_VIA,*
-B 100,0,120,20,CONT_VIA,*
-B 100,0,120,20,CONT_VIA2,*
-B 100,2000,120,20,CONT_VIA2,*
-B 100,2000,120,20,CONT_VIA,*
-EOF
diff --git a/alliance/share/cells/rflib/rf_inmux_buf_4.vbe b/alliance/share/cells/rflib/rf_inmux_buf_4.vbe
deleted file mode 100644
index e0512ca7..00000000
--- a/alliance/share/cells/rflib/rf_inmux_buf_4.vbe
+++ /dev/null
@@ -1,24 +0,0 @@
-ENTITY rf_inmux_buf_4 IS
-PORT (
-  ck     : in  BIT;
-  sel    : in  BIT;
-  nck 	 : out BIT;
-  sel0	 : out BIT;
-  sel1	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END rf_inmux_buf_4;
-
-ARCHITECTURE VBE OF rf_inmux_buf_4 IS
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on rf_inmux_buf_4"
-  SEVERITY WARNING;
-
-  nck <= not ck;
-  sel1 <= sel;
-  sel0 <= not sel;
-
-END;
diff --git a/alliance/share/cells/rflib/rf_inmux_mem.ap b/alliance/share/cells/rflib/rf_inmux_mem.ap
deleted file mode 100644
index a86f56c4..00000000
--- a/alliance/share/cells/rflib/rf_inmux_mem.ap
+++ /dev/null
@@ -1,108 +0,0 @@
-V ALLIANCE : 6
-H rf_inmux_mem,P,14/ 6/2001,10
-A 0,0,450,500
-R 400,400,ref_ref,datain1_40
-R 400,350,ref_ref,datain1_35
-R 400,300,ref_ref,datain1_30
-R 400,250,ref_ref,datain1_25
-R 400,200,ref_ref,datain1_20
-R 400,150,ref_ref,datain1_15
-R 200,400,ref_ref,datain0_40
-R 200,350,ref_ref,datain0_35
-R 200,300,ref_ref,datain0_30
-R 200,250,ref_ref,datain0_25
-R 200,200,ref_ref,datain0_20
-R 200,150,ref_ref,datain0_15
-S 90,100,90,400,20,*,UP,ALU1
-S 0,470,450,470,60,vdd,RIGHT,CALU1
-S 0,30,450,30,60,vss,RIGHT,CALU1
-S 260,200,340,200,10,*,RIGHT,POLY
-S 340,200,340,340,10,*,DOWN,POLY
-S 0,430,450,430,160,*,LEFT,NWELL
-S 0,390,360,390,240,*,RIGHT,NWELL
-S 60,250,300,250,10,*,RIGHT,POLY
-S 380,340,410,340,10,*,RIGHT,POLY
-S 250,100,250,300,10,*,DOWN,ALU1
-S 260,290,260,340,10,*,UP,POLY
-S 190,340,220,340,10,*,RIGHT,POLY
-S 170,360,170,470,70,*,DOWN,PDIF
-S 410,360,410,460,30,*,UP,PDIF
-S 300,360,300,450,50,*,UP,PDIF
-S 260,340,260,470,10,*,UP,PTRANS
-S 220,340,220,470,10,*,UP,PTRANS
-S 340,340,340,470,10,*,UP,PTRANS
-S 380,340,380,470,10,*,UP,PTRANS
-S 90,280,90,470,30,*,DOWN,PDIF
-S 150,280,150,330,30,*,UP,PDIF
-S 30,280,30,470,30,*,DOWN,PDIF
-S 120,260,120,490,10,*,UP,PTRANS
-S 60,260,60,490,10,*,UP,PTRANS
-S 120,140,120,260,10,*,UP,POLY
-S 60,140,60,260,10,*,UP,POLY
-S 250,100,340,100,10,*,RIGHT,ALU1
-S 290,30,290,160,30,*,UP,NDIF
-S 300,30,300,70,50,*,UP,NDIF
-S 380,90,380,140,10,*,UP,POLY
-S 380,140,400,140,10,*,LEFT,POLY
-S 300,30,300,160,30,*,UP,NDIF
-S 220,90,220,140,10,*,UP,POLY
-S 260,90,260,200,10,*,UP,POLY
-S 220,10,220,90,10,*,DOWN,NTRANS
-S 260,10,260,90,10,*,DOWN,NTRANS
-S 410,30,410,70,30,*,DOWN,NDIF
-S 150,50,150,170,20,*,UP,ALU1
-S 340,10,340,90,10,*,DOWN,NTRANS
-S 380,10,380,90,10,*,DOWN,NTRANS
-S 190,140,220,140,10,*,RIGHT,POLY
-S 150,300,150,450,20,*,DOWN,ALU1
-S 170,30,170,120,70,*,UP,NDIF
-S 120,10,120,140,10,*,DOWN,NTRANS
-S 90,30,90,120,30,*,UP,NDIF
-S 300,150,300,400,10,*,UP,ALU1
-S 60,10,60,140,10,*,DOWN,NTRANS
-S 30,30,30,120,30,*,UP,NDIF
-S 30,300,30,450,20,*,DOWN,ALU1
-S 30,50,30,170,20,*,UP,ALU1
-S 250,300,250,300,20,sel1,LEFT,CALU3
-S 350,300,350,300,20,sel0,LEFT,CALU3
-S 250,300,350,300,20,vdd,RIGHT,TALU2
-S 200,150,200,400,20,datain0,UP,CALU1
-S 400,150,400,400,20,datain1,UP,CALU1
-S 100,100,100,100,20,dinx,LEFT,CALU2
-V 250,300,CONT_VIA2,*
-V 350,300,CONT_VIA2,*
-V 350,300,CONT_POLY,*
-V 350,300,CONT_VIA,*
-V 250,300,CONT_VIA,*
-V 300,250,CONT_POLY,*
-V 400,330,CONT_POLY,*
-V 200,330,CONT_POLY,*
-V 250,300,CONT_POLY,*
-V 300,500,CONT_BODY_N,*
-V 340,100,CONT_POLY,*
-V 150,170,CONT_BODY_P,*
-V 150,300,CONT_DIF_P,*
-V 150,100,CONT_DIF_N,*
-V 150,450,CONT_DIF_P,*
-V 150,50,CONT_DIF_N,*
-V 90,100,CONT_DIF_N,*
-V 90,300,CONT_DIF_P,*
-V 90,400,CONT_DIF_P,*
-V 90,350,CONT_DIF_P,*
-V 150,400,CONT_DIF_P,*
-V 150,350,CONT_DIF_P,*
-V 300,400,CONT_DIF_P,*
-V 300,150,CONT_DIF_N,*
-V 400,150,CONT_POLY,*
-V 410,450,CONT_DIF_P,*
-V 410,50,CONT_DIF_N,*
-V 200,150,CONT_POLY,*
-V 30,350,CONT_DIF_P,*
-V 30,300,CONT_DIF_P,*
-V 30,450,CONT_DIF_P,*
-V 30,400,CONT_DIF_P,*
-V 30,170,CONT_BODY_P,*
-V 30,50,CONT_DIF_N,*
-V 30,100,CONT_DIF_N,*
-V 100,100,CONT_VIA,*
-EOF
diff --git a/alliance/share/cells/rflib/rf_inmux_mem.vbe b/alliance/share/cells/rflib/rf_inmux_mem.vbe
deleted file mode 100644
index b0869fa9..00000000
--- a/alliance/share/cells/rflib/rf_inmux_mem.vbe
+++ /dev/null
@@ -1,22 +0,0 @@
-ENTITY rf_inmux_mem IS
-PORT (
-  datain0   : in  BIT;
-  datain1   : in  BIT;
-  sel0      : in  BIT;
-  sel1      : in  BIT;
-  dinx      : out BIT;
-  vdd	    : in  BIT;
-  vss	    : in  BIT
-);
-END rf_inmux_mem;
-
-ARCHITECTURE VBE OF rf_inmux_mem IS
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on sff1_x4"
-  SEVERITY WARNING;
-
-  dinx <= (sel0 and datain0) or (sel1 and datain1);
-
-END;
diff --git a/alliance/share/cells/rflib/rf_mid_buf_2.ap b/alliance/share/cells/rflib/rf_mid_buf_2.ap
deleted file mode 100644
index 93b7afe2..00000000
--- a/alliance/share/cells/rflib/rf_mid_buf_2.ap
+++ /dev/null
@@ -1,162 +0,0 @@
-V ALLIANCE : 6
-H rf_mid_buf_2,P,14/11/2000,10
-A 0,0,250,1000
-S 50,600,200,600,20,*,RIGHT,TALU2
-S 50,400,200,400,20,*,RIGHT,TALU2
-S 50,150,200,150,20,*,RIGHT,TALU2
-S 0,900,0,950,20,*,UP,ALU1
-S 160,890,160,970,30,*,DOWN,NDIF
-S 140,850,180,850,30,*,RIGHT,POLY
-S 180,840,180,870,10,*,UP,POLY
-S 160,820,160,860,10,*,UP,POLY
-S 150,900,200,900,20,*,LEFT,ALU1
-S 180,870,180,990,10,*,UP,NTRANS
-S 30,640,30,670,10,*,UP,POLY
-S 90,640,90,670,10,*,UP,POLY
-S 160,640,160,670,10,*,UP,POLY
-S 220,640,220,670,10,*,UP,POLY
-S 250,330,250,620,30,*,DOWN,PDIF
-S 120,330,120,620,30,*,UP,PDIF
-S 160,310,160,640,10,*,UP,PTRANS
-S 30,310,30,640,10,*,UP,PTRANS
-S 0,330,0,620,30,*,UP,PDIF
-S 90,310,90,640,10,*,UP,PTRANS
-S 130,330,130,620,30,*,UP,PDIF
-S 190,330,190,620,30,*,UP,PDIF
-S 220,310,220,640,10,*,DOWN,PTRANS
-S 60,330,60,620,30,*,UP,PDIF
-S 60,100,60,400,20,*,UP,ALU1
-S 190,100,190,400,20,*,UP,ALU1
-S 250,280,250,790,20,*,UP,ALU1
-S 250,30,250,180,30,*,UP,NDIF
-S 90,10,90,200,10,*,DOWN,NTRANS
-S 130,30,130,180,30,*,UP,NDIF
-S 120,30,120,180,30,*,UP,NDIF
-S 160,10,160,200,10,*,DOWN,NTRANS
-S 190,30,190,180,30,*,UP,NDIF
-S 220,10,220,200,10,*,DOWN,NTRANS
-S 30,10,30,200,10,*,UP,NTRANS
-S 60,30,60,180,30,*,UP,NDIF
-S 0,30,0,180,30,*,UP,NDIF
-S 250,850,250,900,20,*,UP,ALU1
-S 250,720,250,800,30,*,UP,PDIF
-S 160,700,160,820,10,*,DOWN,PTRANS
-S 190,720,190,800,20,*,UP,PDIF
-S 220,700,220,820,10,*,UP,PTRANS
-S 130,720,130,800,30,*,UP,PDIF
-S 250,890,250,970,30,*,UP,NDIF
-S -20,650,270,650,320,*,LEFT,NWELL
-S -20,390,270,390,260,*,LEFT,NWELL
-S 220,200,220,310,10,*,UP,POLY
-S 160,200,160,310,10,*,UP,POLY
-S 90,200,90,310,10,*,UP,POLY
-S 30,200,30,310,10,*,UP,POLY
-S 0,890,0,970,30,*,UP,NDIF
-S 30,700,30,820,10,*,DOWN,PTRANS
-S 90,700,90,820,10,*,DOWN,PTRANS
-S 60,720,60,800,30,*,UP,PDIF
-S 0,720,0,800,30,*,UP,PDIF
-S 0,280,0,790,20,*,UP,ALU1
-S 160,660,220,660,30,*,RIGHT,POLY
-S 30,660,90,660,30,*,RIGHT,POLY
-S 220,870,220,990,10,*,UP,NTRANS
-S 220,850,260,850,30,*,RIGHT,POLY
-S 220,820,220,870,10,*,DOWN,POLY
-S 30,870,30,990,10,*,UP,NTRANS
-S 160,210,220,210,10,*,RIGHT,POLY
-S 30,210,90,210,10,*,RIGHT,POLY
-S 200,660,200,900,20,*,DOWN,ALU1
-S 50,660,50,900,20,*,UP,ALU1
-S 120,280,120,740,20,*,UP,ALU1
-S 100,800,100,850,20,*,UP,ALU1
-S 30,820,30,870,10,*,DOWN,POLY
-S 30,850,100,850,30,*,RIGHT,POLY
-S 90,820,90,860,10,*,DOWN,POLY
-S 120,50,120,150,20,*,UP,ALU1
-S 250,50,250,150,20,*,UP,ALU1
-S 0,50,0,150,20,*,UP,ALU1
-S 0,30,250,30,60,vss,RIGHT,CALU1
-S 0,970,250,970,60,vss,RIGHT,CALU1
-S 0,530,250,530,60,vdd,RIGHT,CALU1
-S 0,470,250,470,60,vdd,RIGHT,CALU1
-S 250,900,250,900,20,nck,LEFT,CALU2
-S 100,800,100,800,20,selr,LEFT,CALU2
-S 150,850,150,850,20,selw,LEFT,CALU2
-S 200,150,200,600,20,write,UP,CALU3
-S 50,150,50,600,20,read,UP,CALU3
-V 0,900,CONT_DIF_N,*
-V 100,970,CONT_BODY_P,*
-V 150,900,CONT_DIF_N,*
-V 250,670,CONT_BODY_N,*
-V 50,150,CONT_VIA,*
-V 50,150,CONT_VIA2,*
-V 50,400,CONT_VIA,*
-V 50,400,CONT_VIA2,*
-V 50,600,CONT_VIA,*
-V 50,600,CONT_VIA2,*
-V 120,740,CONT_DIF_P,*
-V 0,280,CONT_BODY_N,*
-V 250,280,CONT_BODY_N,*
-V 120,500,CONT_DIF_P,*
-V 120,450,CONT_DIF_P,*
-V 120,550,CONT_DIF_P,*
-V 120,400,CONT_DIF_P,*
-V 120,100,CONT_DIF_N,*
-V 250,850,CONT_POLY,*
-V 250,950,CONT_DIF_N,*
-V 250,600,CONT_DIF_P,*
-V 190,600,CONT_DIF_P,*
-V 60,600,CONT_DIF_P,*
-V 0,600,CONT_DIF_P,*
-V 250,550,CONT_DIF_P,*
-V 250,500,CONT_DIF_P,*
-V 0,550,CONT_DIF_P,*
-V 0,500,CONT_DIF_P,*
-V 250,450,CONT_DIF_P,*
-V 0,450,CONT_DIF_P,*
-V 250,150,CONT_DIF_N,*
-V 190,150,CONT_DIF_N,*
-V 250,100,CONT_DIF_N,*
-V 190,100,CONT_DIF_N,*
-V 250,350,CONT_DIF_P,*
-V 190,350,CONT_DIF_P,*
-V 250,400,CONT_DIF_P,*
-V 190,400,CONT_DIF_P,*
-V 0,100,CONT_DIF_N,*
-V 60,100,CONT_DIF_N,*
-V 60,150,CONT_DIF_N,*
-V 0,150,CONT_DIF_N,*
-V 0,400,CONT_DIF_P,*
-V 60,400,CONT_DIF_P,*
-V 60,350,CONT_DIF_P,*
-V 0,350,CONT_DIF_P,*
-V 120,280,CONT_BODY_N,*
-V 0,950,CONT_DIF_N,*
-V 250,900,CONT_VIA,*
-V 190,740,CONT_DIF_P,*
-V 0,740,CONT_DIF_P,*
-V 60,740,CONT_DIF_P,*
-V 250,740,CONT_DIF_P,*
-V 60,900,CONT_DIF_N,*
-V 150,850,CONT_VIA,*
-V 150,850,CONT_POLY,*
-V 200,660,CONT_POLY,*
-V 100,850,CONT_POLY,*
-V 0,790,CONT_DIF_P,*
-V 190,790,CONT_DIF_P,*
-V 250,790,CONT_DIF_P,*
-V 50,660,CONT_POLY,*
-V 100,800,CONT_VIA,*
-V 120,670,CONT_BODY_N,*
-V 200,600,CONT_VIA2,*
-V 200,600,CONT_VIA,*
-V 200,400,CONT_VIA2,*
-V 200,400,CONT_VIA,*
-V 200,150,CONT_VIA2,*
-V 200,150,CONT_VIA,*
-V 120,150,CONT_DIF_N,*
-V 120,350,CONT_DIF_P,*
-V 250,50,CONT_DIF_N,*
-V 120,50,CONT_DIF_N,*
-V 0,50,CONT_DIF_N,*
-EOF
diff --git a/alliance/share/cells/rflib/rf_mid_buf_2.vbe b/alliance/share/cells/rflib/rf_mid_buf_2.vbe
deleted file mode 100644
index 3545d57e..00000000
--- a/alliance/share/cells/rflib/rf_mid_buf_2.vbe
+++ /dev/null
@@ -1,23 +0,0 @@
-ENTITY rf_mid_buf_2 IS
-PORT (
-  selr   : in  BIT;
-  selw   : in  BIT;
-  nck    : in  BIT;
-  read	 : out BIT;
-  write  : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END rf_mid_buf_2;
-
-ARCHITECTURE VBE OF rf_mid_buf_2 IS
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on rf_mid_buf_2"
-  SEVERITY WARNING;
-
-  read <= selr;
-  write <= selw and nck;
-
-END;
diff --git a/alliance/share/cells/rflib/rf_mid_buf_4.ap b/alliance/share/cells/rflib/rf_mid_buf_4.ap
deleted file mode 100644
index 81942b9e..00000000
--- a/alliance/share/cells/rflib/rf_mid_buf_4.ap
+++ /dev/null
@@ -1,306 +0,0 @@
-V ALLIANCE : 6
-H rf_mid_buf_4,P,14/ 9/2000,10
-A 0,0,250,2000
-S 50,1400,50,1850,20,read,UP,CALU3
-S 200,150,200,600,20,write,UP,CALU3
-S 60,900,130,900,20,*,LEFT,ALU1
-S 90,820,90,870,10,*,DOWN,POLY
-S 160,820,160,870,10,*,UP,POLY
-S 90,850,160,850,30,*,RIGHT,POLY
-S 120,890,120,970,30,*,DOWN,NDIF
-S 90,870,90,990,10,*,DOWN,NTRANS
-S 160,870,160,990,10,*,DOWN,NTRANS
-S 130,890,130,970,30,*,DOWN,NDIF
-S 220,640,220,670,10,*,DOWN,POLY
-S 160,640,160,670,10,*,DOWN,POLY
-S 90,640,90,670,10,*,DOWN,POLY
-S 30,640,30,670,10,*,DOWN,POLY
-S 0,330,0,620,30,*,UP,PDIF
-S 130,330,130,620,30,*,DOWN,PDIF
-S 90,310,90,640,10,*,DOWN,PTRANS
-S 220,310,220,640,10,*,DOWN,PTRANS
-S 250,330,250,620,30,*,DOWN,PDIF
-S 160,310,160,640,10,*,DOWN,PTRANS
-S 120,330,120,620,30,*,DOWN,PDIF
-S 60,330,60,620,30,*,DOWN,PDIF
-S 30,310,30,640,10,*,UP,PTRANS
-S 190,330,190,620,30,*,DOWN,PDIF
-S 130,40,130,100,20,*,DOWN,ALU1
-S 250,40,250,150,20,*,DOWN,ALU1
-S 0,40,0,150,20,*,DOWN,ALU1
-S 190,100,190,400,20,*,DOWN,ALU1
-S 60,100,60,400,20,*,DOWN,ALU1
-S 190,660,190,740,20,*,DOWN,ALU1
-S 130,740,130,790,20,*,UP,ALU1
-S 0,280,0,790,20,*,DOWN,ALU1
-S 60,660,60,900,20,*,UP,ALU1
-S 60,660,190,660,20,*,RIGHT,ALU1
-S 30,660,220,660,30,*,RIGHT,POLY
-S 60,600,190,600,20,*,RIGHT,ALU1
-S 130,280,130,550,20,*,DOWN,ALU1
-S 0,30,0,180,30,*,DOWN,NDIF
-S 160,10,160,200,10,*,UP,NTRANS
-S 120,30,120,180,30,*,DOWN,NDIF
-S 130,30,130,180,30,*,DOWN,NDIF
-S 90,10,90,200,10,*,UP,NTRANS
-S 60,30,60,180,30,*,DOWN,NDIF
-S 30,10,30,200,10,*,UP,NTRANS
-S 220,10,220,200,10,*,DOWN,NTRANS
-S 190,30,190,180,30,*,DOWN,NDIF
-S 250,30,250,180,30,*,DOWN,NDIF
-S 0,850,0,900,20,*,DOWN,ALU1
-S 0,720,0,800,30,*,DOWN,PDIF
-S 90,700,90,820,10,*,UP,PTRANS
-S 60,720,60,800,20,*,DOWN,PDIF
-S 30,700,30,820,10,*,DOWN,PTRANS
-S 120,720,120,800,30,*,DOWN,PDIF
-S 0,890,0,970,30,*,DOWN,NDIF
-S 60,150,190,150,20,*,RIGHT,ALU1
-S -20,650,270,650,320,*,LEFT,NWELL
-S -20,390,270,390,260,*,LEFT,NWELL
-S 30,200,30,310,10,*,DOWN,POLY
-S 90,200,90,310,10,*,DOWN,POLY
-S 160,200,160,310,10,*,DOWN,POLY
-S 220,200,220,310,10,*,DOWN,POLY
-S 30,210,220,210,10,*,RIGHT,POLY
-S 250,890,250,970,30,*,DOWN,NDIF
-S 220,700,220,820,10,*,UP,PTRANS
-S 160,700,160,820,10,*,UP,PTRANS
-S 190,720,190,800,30,*,DOWN,PDIF
-S 250,720,250,800,30,*,DOWN,PDIF
-S 250,850,250,900,20,*,UP,ALU1
-S 250,280,250,790,20,*,DOWN,ALU1
-S 130,790,250,790,20,*,LEFT,ALU1
-S 220,870,220,990,10,*,DOWN,NTRANS
-S 190,890,190,970,30,*,DOWN,NDIF
-S 30,870,30,990,10,*,DOWN,NTRANS
-S 60,890,60,970,30,*,DOWN,NDIF
-S -10,850,30,850,30,*,RIGHT,POLY
-S 30,820,30,870,10,*,UP,POLY
-S 220,820,220,870,10,*,UP,POLY
-S 220,850,260,850,30,*,RIGHT,POLY
-S 130,1900,130,1960,20,*,DOWN,ALU1
-S 250,1850,250,1960,20,*,DOWN,ALU1
-S 0,1850,0,1960,20,*,DOWN,ALU1
-S 190,1600,190,1900,20,*,DOWN,ALU1
-S 60,1600,60,1900,20,*,DOWN,ALU1
-S 0,1210,0,1720,20,*,DOWN,ALU1
-S 30,1340,220,1340,30,*,LEFT,POLY
-S 60,1400,190,1400,20,*,LEFT,ALU1
-S 130,1450,130,1720,20,*,DOWN,ALU1
-S 0,1820,0,1970,30,*,DOWN,NDIF
-S 160,1800,160,1990,10,*,UP,NTRANS
-S 120,1820,120,1970,30,*,DOWN,NDIF
-S 130,1820,130,1970,30,*,DOWN,NDIF
-S 90,1800,90,1990,10,*,UP,NTRANS
-S 60,1820,60,1970,30,*,DOWN,NDIF
-S 30,1800,30,1990,10,*,UP,NTRANS
-S 220,1800,220,1990,10,*,DOWN,NTRANS
-S 190,1820,190,1970,30,*,DOWN,NDIF
-S 250,1820,250,1970,30,*,DOWN,NDIF
-S 30,1130,30,1180,10,*,DOWN,POLY
-S 0,1200,0,1280,30,*,DOWN,PDIF
-S 90,1180,90,1300,10,*,UP,PTRANS
-S 60,1200,60,1280,20,*,DOWN,PDIF
-S 30,1180,30,1300,10,*,DOWN,PTRANS
-S 120,1200,120,1280,30,*,DOWN,PDIF
-S 60,1850,190,1850,20,*,LEFT,ALU1
-S -20,1350,270,1350,320,*,RIGHT,NWELL
-S -20,1610,270,1610,260,*,RIGHT,NWELL
-S 30,1690,30,1800,10,*,DOWN,POLY
-S 90,1690,90,1800,10,*,DOWN,POLY
-S 160,1690,160,1800,10,*,DOWN,POLY
-S 220,1690,220,1800,10,*,DOWN,POLY
-S 30,1790,220,1790,10,*,LEFT,POLY
-S 250,1210,250,1720,20,*,DOWN,ALU1
-S 90,1130,90,1180,10,*,DOWN,POLY
-S 160,1130,160,1180,10,*,DOWN,POLY
-S 220,1130,220,1180,10,*,DOWN,POLY
-S 30,1060,30,1130,10,*,DOWN,NTRANS
-S 60,1080,60,1110,30,*,DOWN,NDIF
-S 90,1060,90,1130,10,*,DOWN,NTRANS
-S 220,1060,220,1130,10,*,DOWN,NTRANS
-S 160,1060,160,1130,10,*,DOWN,NTRANS
-S 190,1080,190,1110,30,*,DOWN,NDIF
-S 250,1040,250,1110,30,*,DOWN,NDIF
-S 0,1040,0,1110,30,*,DOWN,NDIF
-S 120,1040,120,1110,30,*,DOWN,NDIF
-S 130,1040,130,1110,30,*,DOWN,NDIF
-S 30,1150,220,1150,30,*,LEFT,POLY
-S 250,1200,250,1280,30,*,DOWN,PDIF
-S 220,1180,220,1300,10,*,UP,PTRANS
-S 190,1200,190,1280,20,*,DOWN,PDIF
-S 160,1180,160,1300,10,*,DOWN,PTRANS
-S 130,1200,130,1280,30,*,DOWN,PDIF
-S 190,1100,190,1210,20,*,UP,ALU1
-S 130,1260,250,1260,20,*,LEFT,ALU1
-S 250,1050,250,1100,20,*,UP,ALU1
-S 0,1050,0,1100,20,*,DOWN,ALU1
-S 130,1380,130,1670,30,*,DOWN,PDIF
-S 120,1380,120,1670,30,*,DOWN,PDIF
-S 60,1380,60,1670,30,*,DOWN,PDIF
-S 30,1360,30,1690,10,*,UP,PTRANS
-S 190,1380,190,1670,30,*,DOWN,PDIF
-S 220,1360,220,1690,10,*,DOWN,PTRANS
-S 90,1360,90,1690,10,*,DOWN,PTRANS
-S 250,1380,250,1670,30,*,DOWN,PDIF
-S 160,1360,160,1690,10,*,DOWN,PTRANS
-S 0,1380,0,1670,30,*,UP,PDIF
-S 220,1330,220,1360,10,*,UP,POLY
-S 160,1330,160,1360,10,*,UP,POLY
-S 90,1330,90,1360,10,*,UP,POLY
-S 30,1330,30,1360,10,*,UP,POLY
-S 50,1340,190,1340,20,*,LEFT,ALU1
-S 60,1210,60,1340,20,*,UP,ALU1
-S 60,1100,190,1100,20,*,LEFT,ALU1
-S 60,1210,190,1210,20,*,LEFT,ALU1
-S 0,1850,250,1850,20,*,RIGHT,TALU2
-S 0,1600,250,1600,20,*,RIGHT,TALU2
-S 0,1400,250,1400,20,*,RIGHT,TALU2
-S 0,600,250,600,20,*,RIGHT,TALU2
-S 0,400,250,400,20,*,RIGHT,TALU2
-S 0,150,250,150,20,*,RIGHT,TALU2
-S 0,900,250,900,20,nck,RIGHT,CALU2
-S 150,850,150,850,20,selw,LEFT,CALU2
-S 100,1150,100,1150,20,selr,LEFT,CALU2
-S 0,1970,250,1970,60,vss,LEFT,CALU1
-S 0,1470,250,1470,60,vdd,LEFT,CALU1
-S 0,1530,250,1530,60,vdd,LEFT,CALU1
-S 0,970,250,970,60,vss,RIGHT,CALU1
-S 0,1030,250,1030,60,vss,RIGHT,CALU1
-S 0,470,250,470,60,vdd,RIGHT,CALU1
-S 0,530,250,530,60,vdd,RIGHT,CALU1
-S 0,30,250,30,60,vss,RIGHT,CALU1
-V 130,900,CONT_DIF_N,*
-V 250,670,CONT_BODY_N,*
-V 200,150,CONT_VIA,*
-V 200,150,CONT_VIA2,*
-V 200,400,CONT_VIA,*
-V 200,400,CONT_VIA2,*
-V 200,600,CONT_VIA,*
-V 200,600,CONT_VIA2,*
-V 130,660,CONT_POLY,*
-V 60,790,CONT_DIF_P,*
-V 130,740,CONT_DIF_P,*
-V 0,790,CONT_DIF_P,*
-V 190,660,CONT_POLY,*
-V 60,660,CONT_POLY,*
-V 250,280,CONT_BODY_N,*
-V 0,280,CONT_BODY_N,*
-V 130,500,CONT_DIF_P,*
-V 130,450,CONT_DIF_P,*
-V 130,550,CONT_DIF_P,*
-V 130,400,CONT_DIF_P,*
-V 150,850,CONT_POLY,*
-V 130,40,CONT_DIF_N,*
-V 130,100,CONT_DIF_N,*
-V 0,850,CONT_POLY,*
-V 0,950,CONT_DIF_N,*
-V 0,600,CONT_DIF_P,*
-V 60,600,CONT_DIF_P,*
-V 190,600,CONT_DIF_P,*
-V 250,600,CONT_DIF_P,*
-V 0,550,CONT_DIF_P,*
-V 0,500,CONT_DIF_P,*
-V 250,550,CONT_DIF_P,*
-V 250,500,CONT_DIF_P,*
-V 0,450,CONT_DIF_P,*
-V 250,450,CONT_DIF_P,*
-V 0,150,CONT_DIF_N,*
-V 60,150,CONT_DIF_N,*
-V 0,40,CONT_DIF_N,*
-V 0,100,CONT_DIF_N,*
-V 60,100,CONT_DIF_N,*
-V 0,350,CONT_DIF_P,*
-V 60,350,CONT_DIF_P,*
-V 0,400,CONT_DIF_P,*
-V 60,400,CONT_DIF_P,*
-V 250,100,CONT_DIF_N,*
-V 190,100,CONT_DIF_N,*
-V 250,40,CONT_DIF_N,*
-V 190,150,CONT_DIF_N,*
-V 250,150,CONT_DIF_N,*
-V 250,400,CONT_DIF_P,*
-V 190,400,CONT_DIF_P,*
-V 190,350,CONT_DIF_P,*
-V 250,350,CONT_DIF_P,*
-V 130,280,CONT_BODY_N,*
-V 250,950,CONT_DIF_N,*
-V 250,850,CONT_POLY,*
-V 250,900,CONT_VIA,*
-V 150,850,CONT_VIA,*
-V 0,900,CONT_VIA,*
-V 130,790,CONT_DIF_P,*
-V 250,790,CONT_DIF_P,*
-V 60,740,CONT_DIF_P,*
-V 250,740,CONT_DIF_P,*
-V 190,740,CONT_DIF_P,*
-V 0,740,CONT_DIF_P,*
-V 60,1850,CONT_VIA2,*
-V 50,1600,CONT_VIA2,*
-V 50,1400,CONT_VIA2,*
-V 60,1850,CONT_VIA,*
-V 50,1600,CONT_VIA,*
-V 50,1400,CONT_VIA,*
-V 130,1340,CONT_POLY,*
-V 60,1210,CONT_DIF_P,*
-V 0,1210,CONT_DIF_P,*
-V 190,1340,CONT_POLY,*
-V 60,1340,CONT_POLY,*
-V 250,1720,CONT_BODY_N,*
-V 0,1720,CONT_BODY_N,*
-V 130,1500,CONT_DIF_P,*
-V 130,1550,CONT_DIF_P,*
-V 130,1450,CONT_DIF_P,*
-V 130,1600,CONT_DIF_P,*
-V 130,1960,CONT_DIF_N,*
-V 130,1900,CONT_DIF_N,*
-V 0,1050,CONT_DIF_N,*
-V 0,1400,CONT_DIF_P,*
-V 60,1400,CONT_DIF_P,*
-V 190,1400,CONT_DIF_P,*
-V 250,1400,CONT_DIF_P,*
-V 0,1450,CONT_DIF_P,*
-V 0,1500,CONT_DIF_P,*
-V 250,1450,CONT_DIF_P,*
-V 250,1500,CONT_DIF_P,*
-V 0,1550,CONT_DIF_P,*
-V 250,1550,CONT_DIF_P,*
-V 0,1850,CONT_DIF_N,*
-V 60,1850,CONT_DIF_N,*
-V 0,1960,CONT_DIF_N,*
-V 0,1900,CONT_DIF_N,*
-V 60,1900,CONT_DIF_N,*
-V 0,1650,CONT_DIF_P,*
-V 60,1650,CONT_DIF_P,*
-V 0,1600,CONT_DIF_P,*
-V 60,1600,CONT_DIF_P,*
-V 250,1900,CONT_DIF_N,*
-V 190,1900,CONT_DIF_N,*
-V 250,1960,CONT_DIF_N,*
-V 190,1850,CONT_DIF_N,*
-V 250,1850,CONT_DIF_N,*
-V 250,1600,CONT_DIF_P,*
-V 190,1600,CONT_DIF_P,*
-V 190,1650,CONT_DIF_P,*
-V 250,1650,CONT_DIF_P,*
-V 130,1720,CONT_BODY_N,*
-V 60,1260,CONT_DIF_P,*
-V 0,1260,CONT_DIF_P,*
-V 100,1150,CONT_VIA,*
-V 100,1150,CONT_POLY,*
-V 60,1100,CONT_DIF_N,*
-V 120,1050,CONT_DIF_N,*
-V 250,1050,CONT_DIF_N,*
-V 190,1030,CONT_BODY_P,*
-V 60,1030,CONT_BODY_P,*
-V 190,1210,CONT_DIF_P,*
-V 130,1260,CONT_DIF_P,*
-V 190,1100,CONT_DIF_N,*
-V 250,1210,CONT_DIF_P,*
-V 250,1260,CONT_DIF_P,*
-V 250,1100,CONT_DIF_N,*
-V 0,1100,CONT_DIF_N,*
-V 250,1330,CONT_BODY_N,*
-V 0,1330,CONT_BODY_N,*
-EOF
diff --git a/alliance/share/cells/rflib/rf_mid_buf_4.vbe b/alliance/share/cells/rflib/rf_mid_buf_4.vbe
deleted file mode 100644
index 18cc9b4d..00000000
--- a/alliance/share/cells/rflib/rf_mid_buf_4.vbe
+++ /dev/null
@@ -1,23 +0,0 @@
-ENTITY rf_mid_buf_4 IS
-PORT (
-  selr   : in  BIT;
-  selw   : in  BIT;
-  nck    : in  BIT;
-  read	 : out BIT;
-  write  : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END rf_mid_buf_4;
-
-ARCHITECTURE VBE OF rf_mid_buf_4 IS
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on rf_mid_buf_4"
-  SEVERITY WARNING;
-
-  read <= selr;
-  write <= selw and nck;
-
-END;
diff --git a/alliance/share/cells/rflib/rf_mid_mem.ap b/alliance/share/cells/rflib/rf_mid_mem.ap
deleted file mode 100644
index 0e7ed189..00000000
--- a/alliance/share/cells/rflib/rf_mid_mem.ap
+++ /dev/null
@@ -1,87 +0,0 @@
-V ALLIANCE : 6
-H rf_mid_mem,P,13/11/2000,10
-A 0,0,250,500
-S 200,150,250,150,20,*,RIGHT,TALU2
-S 50,300,50,300,20,read,LEFT,CALU3
-S 200,150,200,150,20,write,LEFT,CALU3
-S 190,150,220,150,30,*,RIGHT,POLY
-S 220,50,220,140,10,*,UP,NTRANS
-S 250,70,250,120,30,*,DOWN,NDIF
-S 200,200,200,400,10,latch,DOWN,ALU1
-S 150,200,200,200,10,latch,LEFT,ALU1
-S 130,160,130,180,40,*,DOWN,NDIF
-S 160,220,160,270,100,*,DOWN,NDIF
-S 220,200,220,290,10,*,UP,NTRANS
-S 0,230,50,230,20,*,RIGHT,ALU1
-S 100,250,150,250,10,*,RIGHT,ALU1
-S 30,280,100,280,10,*,RIGHT,ALU1
-S 100,250,100,280,10,*,DOWN,ALU1
-S 30,220,30,270,80,*,DOWN,NDIF
-S 90,290,90,340,10,*,DOWN,POLY
-S 90,200,90,290,10,*,UP,NTRANS
-S 150,100,150,200,10,latch,UP,ALU1
-S 60,330,90,330,30,*,RIGHT,POLY
-S 50,200,90,200,10,*,RIGHT,POLY
-S 30,280,30,400,10,*,DOWN,ALU1
-S 0,30,0,230,20,*,UP,ALU1
-S 110,100,150,100,20,*,RIGHT,ALU1
-S 90,70,100,70,10,*,LEFT,POLY
-S 100,70,100,110,10,*,DOWN,POLY
-S 0,160,0,270,30,*,UP,NDIF
-S 30,70,90,70,10,*,RIGHT,NTRANS
-S 150,290,220,290,10,*,RIGHT,POLY
-S 120,360,200,360,10,*,RIGHT,POLY
-S 0,430,250,430,160,*,RIGHT,NWELL
-S 250,220,250,270,30,*,UP,NDIF
-S 60,100,60,140,20,*,DOWN,ALU1
-S 60,480,160,480,10,*,RIGHT,POLY
-S 160,470,160,480,10,*,DOWN,POLY
-S 100,450,140,450,30,*,RIGHT,PDIF
-S 170,420,170,470,30,*,UP,PTRANS
-S 200,420,220,420,70,*,RIGHT,PDIF
-S 80,330,80,390,10,*,DOWN,ALU1
-S 80,390,150,390,10,*,RIGHT,ALU1
-S 120,360,120,420,10,*,DOWN,PTRANS
-S 30,360,30,460,30,*,UP,PDIF
-S 90,360,90,460,30,*,UP,PDIF
-S 60,340,60,480,10,*,UP,PTRANS
-S 20,160,20,180,20,*,DOWN,NDIF
-S 70,150,70,200,50,*,UP,NTRANS
-S 50,300,150,300,20,*,RIGHT,ALU2
-S 150,80,150,180,30,*,DOWN,NDIF
-S 160,80,160,180,30,*,DOWN,NDIF
-S 180,80,180,120,50,*,DOWN,NDIF
-S 190,70,190,120,30,*,UP,NDIF
-S 0,30,250,30,60,vss,RIGHT,CALU1
-S 0,470,250,470,60,vdd,RIGHT,CALU1
-S 250,100,250,100,20,dinx,LEFT,CALU2
-S 50,300,150,300,20,ck,RIGHT,TALU2
-S 250,250,250,250,20,rbus,LEFT,CALU2
-V 200,150,CONT_VIA,*
-V 200,150,CONT_VIA2,*
-V 200,150,CONT_POLY,*
-V 200,500,CONT_BODY_N,*
-V 250,250,CONT_DIF_N,*
-V 50,230,CONT_DIF_N,*
-V 150,250,CONT_DIF_N,*
-V 80,330,CONT_POLY,*
-V 0,230,CONT_DIF_N,*
-V 150,100,CONT_DIF_N,*
-V 60,40,CONT_DIF_N,*
-V 110,100,CONT_POLY,*
-V 150,300,CONT_POLY,*
-V 200,350,CONT_POLY,*
-V 60,100,CONT_DIF_N,*
-V 60,140,CONT_POLY,*
-V 250,100,CONT_DIF_N,*
-V 210,400,CONT_DIF_P,*
-V 150,390,CONT_DIF_P,*
-V 90,450,CONT_DIF_P,*
-V 30,400,CONT_DIF_P,*
-V 0,170,CONT_DIF_N,*
-V 150,300,CONT_VIA,*
-V 50,300,CONT_VIA2,*
-V 250,100,CONT_VIA,*
-V 250,250,CONT_VIA,*
-V 120,30,CONT_BODY_P,*
-EOF
diff --git a/alliance/share/cells/rflib/rf_mid_mem.vbe b/alliance/share/cells/rflib/rf_mid_mem.vbe
deleted file mode 100644
index abe96394..00000000
--- a/alliance/share/cells/rflib/rf_mid_mem.vbe
+++ /dev/null
@@ -1,30 +0,0 @@
-ENTITY rf_mid_mem IS
-PORT (
-  dinx	 : in  BIT;
-  write  : in  BIT;
-  read   : in  BIT;
-  rbus   : out MUX_BIT BUS;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END rf_mid_mem;
-
-ARCHITECTURE VBE OF rf_mid_mem IS
-  SIGNAL latch	 : REG_BIT REGISTER;
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on rf_mid_mem"
-  SEVERITY WARNING;
-
-  label0 : BLOCK (write = '1')
-  BEGIN
-    latch <= GUARDED dinx;
-  END BLOCK label0;
-
-  label1 : BLOCK (read = '1')
-  BEGIN
-    rbus <= GUARDED latch;
-  END BLOCK label1;
-
-END;
diff --git a/alliance/share/cells/rflib/rf_mid_mem_r0.ap b/alliance/share/cells/rflib/rf_mid_mem_r0.ap
deleted file mode 100644
index c2e99907..00000000
--- a/alliance/share/cells/rflib/rf_mid_mem_r0.ap
+++ /dev/null
@@ -1,30 +0,0 @@
-V ALLIANCE : 6
-H rf_mid_mem_r0,P,13/11/2000,10
-A 0,0,250,500
-S 200,150,250,150,20,*,RIGHT,TALU2
-S 250,250,250,250,20,rbus,LEFT,CALU2
-S 50,300,150,300,20,ck,RIGHT,TALU2
-S 250,100,250,100,20,dinx,LEFT,CALU2
-S 0,470,250,470,60,vdd,RIGHT,CALU1
-S 0,30,250,30,60,vss,RIGHT,CALU1
-S 50,300,150,300,20,*,RIGHT,ALU2
-S 250,220,250,270,30,*,UP,NDIF
-S 0,430,250,430,160,*,RIGHT,NWELL
-S 150,290,220,290,10,*,RIGHT,POLY
-S 0,160,0,270,30,*,UP,NDIF
-S 0,30,0,230,20,*,UP,ALU1
-S 220,200,220,290,10,*,UP,NTRANS
-S 200,150,200,150,20,write,LEFT,CALU3
-S 50,300,50,300,20,read,LEFT,CALU3
-S 190,220,190,270,30,*,UP,NDIF
-S 0,230,190,230,20,*,RIGHT,ALU1
-V 250,250,CONT_VIA,*
-V 50,300,CONT_VIA2,*
-V 150,300,CONT_VIA,*
-V 0,170,CONT_DIF_N,*
-V 150,300,CONT_POLY,*
-V 0,230,CONT_DIF_N,*
-V 250,250,CONT_DIF_N,*
-V 200,500,CONT_BODY_N,*
-V 190,230,CONT_DIF_N,*
-EOF
diff --git a/alliance/share/cells/rflib/rf_mid_mem_r0.vbe b/alliance/share/cells/rflib/rf_mid_mem_r0.vbe
deleted file mode 100644
index 71c03d0e..00000000
--- a/alliance/share/cells/rflib/rf_mid_mem_r0.vbe
+++ /dev/null
@@ -1,25 +0,0 @@
-ENTITY rf_mid_mem_r0 IS
-PORT (
-  dinx	 : in  BIT;
-  write  : in  BIT;
-  read   : in  BIT;
-  rbus   : out MUX_BIT BUS;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END rf_mid_mem_r0;
-
-ARCHITECTURE VBE OF rf_mid_mem_r0 IS
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on rf_mid_mem_r0"
-  SEVERITY WARNING;
-
-  label1 : BLOCK (read = '1')
-  BEGIN
-    rbus <= GUARDED '0';
-  END BLOCK label1;
-
-
-END;
diff --git a/alliance/share/cells/rflib/rf_out_buf_2.ap b/alliance/share/cells/rflib/rf_out_buf_2.ap
deleted file mode 100644
index aeadedee..00000000
--- a/alliance/share/cells/rflib/rf_out_buf_2.ap
+++ /dev/null
@@ -1,79 +0,0 @@
-V ALLIANCE : 6
-H rf_out_buf_2,P,13/ 3/2001,10
-A 0,0,550,1000
-S 290,30,290,150,20,*,DOWN,ALU1
-S 150,650,150,900,20,*,DOWN,ALU1
-S 150,900,150,900,20,nck,LEFT,CALU2
-S 0,970,550,970,60,vss,RIGHT,CALU1
-S 0,30,550,30,60,vss,RIGHT,CALU1
-S 0,530,550,530,60,vdd,RIGHT,CALU1
-S 0,470,550,470,60,vdd,RIGHT,CALU1
-S -20,390,430,390,260,*,LEFT,NWELL
-S -20,650,430,650,320,*,LEFT,NWELL
-S 0,390,550,390,240,*,LEFT,NWELL
-S 0,610,550,610,240,*,LEFT,NWELL
-S 210,280,210,670,20,*,UP,ALU1
-S 90,280,90,670,20,*,UP,ALU1
-S 150,100,150,400,20,*,UP,ALU1
-S 90,40,90,150,20,*,UP,ALU1
-S 210,40,210,150,20,*,UP,ALU1
-S 120,210,180,210,30,*,RIGHT,POLY
-S 120,650,180,650,30,*,RIGHT,POLY
-S 180,200,180,310,10,*,UP,POLY
-S 120,200,120,310,10,*,UP,POLY
-S 210,30,210,180,30,*,UP,NDIF
-S 150,30,150,180,30,*,UP,NDIF
-S 90,30,90,180,30,*,UP,NDIF
-S 180,10,180,200,10,*,DOWN,NTRANS
-S 120,10,120,200,10,*,UP,NTRANS
-S 120,310,120,640,10,*,UP,PTRANS
-S 150,330,150,620,30,*,UP,PDIF
-S 180,310,180,640,10,*,UP,PTRANS
-S 90,330,90,620,30,*,UP,PDIF
-S 210,330,210,620,30,*,UP,PDIF
-S 150,150,150,600,20,xcks,UP,CALU3
-S 100,150,200,150,20,*,RIGHT,TALU2
-S 100,400,200,400,20,*,RIGHT,TALU2
-S 100,600,200,600,20,*,RIGHT,TALU2
-V 290,30,CONT_BODY_P,*
-V 290,150,CONT_BODY_P,*
-V 290,90,CONT_BODY_P,*
-V 150,900,CONT_VIA,*
-V 220,970,CONT_BODY_P,*
-V 280,970,CONT_BODY_P,*
-V 90,100,CONT_DIF_N,*
-V 210,150,CONT_DIF_N,*
-V 210,40,CONT_DIF_N,*
-V 210,100,CONT_DIF_N,*
-V 150,150,CONT_DIF_N,*
-V 150,100,CONT_DIF_N,*
-V 90,150,CONT_DIF_N,*
-V 90,40,CONT_DIF_N,*
-V 90,350,CONT_DIF_P,*
-V 90,400,CONT_DIF_P,*
-V 90,450,CONT_DIF_P,*
-V 90,500,CONT_DIF_P,*
-V 90,550,CONT_DIF_P,*
-V 90,600,CONT_DIF_P,*
-V 90,670,CONT_BODY_N,*
-V 210,670,CONT_BODY_N,*
-V 210,280,CONT_BODY_N,*
-V 210,350,CONT_DIF_P,*
-V 210,450,CONT_DIF_P,*
-V 90,280,CONT_BODY_N,*
-V 150,600,CONT_DIF_P,*
-V 150,400,CONT_DIF_P,*
-V 150,350,CONT_DIF_P,*
-V 210,550,CONT_DIF_P,*
-V 210,400,CONT_DIF_P,*
-V 210,600,CONT_DIF_P,*
-V 150,600,CONT_VIA2,*
-V 150,600,CONT_VIA,*
-V 150,400,CONT_VIA2,*
-V 150,400,CONT_VIA,*
-V 150,150,CONT_VIA2,*
-V 150,150,CONT_VIA,*
-V 290,470,CONT_BODY_N,*
-V 290,530,CONT_BODY_N,*
-V 150,650,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/rflib/rf_out_buf_2.vbe b/alliance/share/cells/rflib/rf_out_buf_2.vbe
deleted file mode 100644
index 6262aed7..00000000
--- a/alliance/share/cells/rflib/rf_out_buf_2.vbe
+++ /dev/null
@@ -1,19 +0,0 @@
-ENTITY rf_out_buf_2 IS
-PORT (
-  nck    : in  BIT;
-  xcks	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END rf_out_buf_2;
-
-ARCHITECTURE VBE OF rf_out_buf_2 IS
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on rf_out_buf_2"
-  SEVERITY WARNING;
-
-  xcks <= not nck;
-
-END;
diff --git a/alliance/share/cells/rflib/rf_out_buf_4.ap b/alliance/share/cells/rflib/rf_out_buf_4.ap
deleted file mode 100644
index 6287401e..00000000
--- a/alliance/share/cells/rflib/rf_out_buf_4.ap
+++ /dev/null
@@ -1,156 +0,0 @@
-V ALLIANCE : 6
-H rf_out_buf_4,P,14/11/2000,10
-A 0,0,550,2000
-S 100,1850,200,1850,20,*,RIGHT,TALU2
-S 100,1600,200,1600,20,*,RIGHT,TALU2
-S 100,1400,200,1400,20,*,RIGHT,TALU2
-S 100,600,200,600,20,*,RIGHT,TALU2
-S 100,400,200,400,20,*,RIGHT,TALU2
-S 100,150,200,150,20,*,RIGHT,TALU2
-S 450,0,450,2000,120,vdd,UP,CALU3
-S 0,30,550,30,60,vss,RIGHT,CALU1
-S 0,530,550,530,60,vdd,RIGHT,CALU1
-S 0,470,550,470,60,vdd,RIGHT,CALU1
-S 0,1530,550,1530,60,vdd,LEFT,CALU1
-S 0,1470,550,1470,60,vdd,LEFT,CALU1
-S 0,1970,550,1970,60,vss,LEFT,CALU1
-S 0,1030,550,1030,60,vss,LEFT,CALU1
-S 0,970,550,970,60,vss,LEFT,CALU1
-S 0,1390,550,1390,240,*,RIGHT,NWELL
-S 0,1610,550,1610,240,*,RIGHT,NWELL
-S -20,1350,430,1350,320,*,RIGHT,NWELL
-S -20,1610,430,1610,260,*,RIGHT,NWELL
-S 0,610,550,610,240,*,LEFT,NWELL
-S 0,390,550,390,240,*,LEFT,NWELL
-S -20,650,430,650,320,*,LEFT,NWELL
-S -20,390,430,390,260,*,LEFT,NWELL
-S 150,150,150,1850,20,xcks,DOWN,CALU3
-S 150,900,150,900,20,nck,LEFT,CALU2
-S 150,1600,150,1900,20,*,UP,ALU1
-S 90,1850,90,1960,20,*,UP,ALU1
-S 210,1330,210,1720,20,*,UP,ALU1
-S 90,1330,90,1720,20,*,UP,ALU1
-S 210,1850,210,1960,20,*,UP,ALU1
-S 120,1690,120,1800,10,*,UP,POLY
-S 120,1790,180,1790,10,*,LEFT,POLY
-S 180,1690,180,1800,10,*,UP,POLY
-S 150,1820,150,1970,30,*,UP,NDIF
-S 90,1820,90,1970,30,*,UP,NDIF
-S 210,1820,210,1970,30,*,UP,NDIF
-S 120,1800,120,1990,10,*,UP,NTRANS
-S 180,1800,180,1990,10,*,DOWN,NTRANS
-S 150,1380,150,1670,30,*,UP,PDIF
-S 120,1360,120,1690,10,*,UP,PTRANS
-S 90,1380,90,1670,30,*,UP,PDIF
-S 180,1360,180,1690,10,*,UP,PTRANS
-S 210,1380,210,1670,30,*,UP,PDIF
-S 280,1850,280,1970,20,*,DOWN,ALU1
-S 120,640,120,1360,10,*,UP,POLY
-S 180,640,180,1360,10,*,UP,POLY
-S 120,900,180,900,30,*,RIGHT,POLY
-S 90,40,90,150,20,*,UP,ALU1
-S 150,100,150,400,20,*,UP,ALU1
-S 210,280,210,670,20,*,UP,ALU1
-S 90,280,90,670,20,*,UP,ALU1
-S 180,200,180,310,10,*,UP,POLY
-S 120,200,120,310,10,*,UP,POLY
-S 120,210,180,210,10,*,RIGHT,POLY
-S 90,30,90,180,30,*,UP,NDIF
-S 150,30,150,180,30,*,UP,NDIF
-S 120,10,120,200,10,*,UP,NTRANS
-S 180,10,180,200,10,*,DOWN,NTRANS
-S 90,330,90,620,30,*,UP,PDIF
-S 180,310,180,640,10,*,UP,PTRANS
-S 150,330,150,620,30,*,UP,PDIF
-S 120,310,120,640,10,*,UP,PTRANS
-S 210,330,210,620,30,*,UP,PDIF
-S 270,30,270,150,20,*,DOWN,ALU1
-S 210,40,210,150,20,*,UP,ALU1
-S 210,30,210,180,30,*,UP,NDIF
-S 400,500,500,500,20,*,RIGHT,TALU2
-S 400,1500,500,1500,20,*,RIGHT,TALU2
-B 450,1500,120,20,CONT_VIA,*
-B 450,1500,120,20,CONT_VIA2,*
-B 450,500,120,20,CONT_VIA2,*
-B 450,500,120,20,CONT_VIA,*
-V 460,1030,CONT_BODY_P,*
-V 460,970,CONT_BODY_P,*
-V 150,900,CONT_VIA,*
-V 150,900,CONT_POLY,*
-V 90,1900,CONT_DIF_N,*
-V 90,1960,CONT_DIF_N,*
-V 90,1850,CONT_DIF_N,*
-V 150,1900,CONT_DIF_N,*
-V 150,1850,CONT_DIF_N,*
-V 210,1960,CONT_DIF_N,*
-V 210,1900,CONT_DIF_N,*
-V 210,1850,CONT_DIF_N,*
-V 150,1600,CONT_DIF_P,*
-V 150,1400,CONT_DIF_P,*
-V 90,1720,CONT_BODY_N,*
-V 90,1400,CONT_DIF_P,*
-V 90,1450,CONT_DIF_P,*
-V 90,1500,CONT_DIF_P,*
-V 90,1550,CONT_DIF_P,*
-V 90,1600,CONT_DIF_P,*
-V 90,1650,CONT_DIF_P,*
-V 150,1650,CONT_DIF_P,*
-V 90,1330,CONT_BODY_N,*
-V 210,1330,CONT_BODY_N,*
-V 210,1650,CONT_DIF_P,*
-V 210,1600,CONT_DIF_P,*
-V 210,1550,CONT_DIF_P,*
-V 210,1500,CONT_DIF_P,*
-V 210,1450,CONT_DIF_P,*
-V 210,1400,CONT_DIF_P,*
-V 210,1720,CONT_BODY_N,*
-V 280,1970,CONT_BODY_P,*
-V 280,1850,CONT_BODY_P,*
-V 280,1910,CONT_BODY_P,*
-V 270,1530,CONT_BODY_N,*
-V 270,1470,CONT_BODY_N,*
-V 150,1850,CONT_VIA2,*
-V 150,1850,CONT_VIA,*
-V 150,1600,CONT_VIA2,*
-V 150,1600,CONT_VIA,*
-V 150,1400,CONT_VIA2,*
-V 150,1400,CONT_VIA,*
-V 90,100,CONT_DIF_N,*
-V 90,40,CONT_DIF_N,*
-V 90,150,CONT_DIF_N,*
-V 150,100,CONT_DIF_N,*
-V 150,150,CONT_DIF_N,*
-V 150,350,CONT_DIF_P,*
-V 150,400,CONT_DIF_P,*
-V 150,600,CONT_DIF_P,*
-V 90,280,CONT_BODY_N,*
-V 90,600,CONT_DIF_P,*
-V 90,550,CONT_DIF_P,*
-V 90,500,CONT_DIF_P,*
-V 90,450,CONT_DIF_P,*
-V 90,400,CONT_DIF_P,*
-V 90,350,CONT_DIF_P,*
-V 90,670,CONT_BODY_N,*
-V 210,280,CONT_BODY_N,*
-V 210,670,CONT_BODY_N,*
-V 210,350,CONT_DIF_P,*
-V 210,400,CONT_DIF_P,*
-V 210,450,CONT_DIF_P,*
-V 210,500,CONT_DIF_P,*
-V 210,550,CONT_DIF_P,*
-V 210,600,CONT_DIF_P,*
-V 270,530,CONT_BODY_N,*
-V 270,470,CONT_BODY_N,*
-V 270,90,CONT_BODY_P,*
-V 270,150,CONT_BODY_P,*
-V 270,30,CONT_BODY_P,*
-V 210,150,CONT_DIF_N,*
-V 210,40,CONT_DIF_N,*
-V 210,100,CONT_DIF_N,*
-V 150,600,CONT_VIA2,*
-V 150,600,CONT_VIA,*
-V 150,400,CONT_VIA2,*
-V 150,400,CONT_VIA,*
-V 150,150,CONT_VIA2,*
-V 150,150,CONT_VIA,*
-EOF
diff --git a/alliance/share/cells/rflib/rf_out_buf_4.vbe b/alliance/share/cells/rflib/rf_out_buf_4.vbe
deleted file mode 100644
index 868f2527..00000000
--- a/alliance/share/cells/rflib/rf_out_buf_4.vbe
+++ /dev/null
@@ -1,19 +0,0 @@
-ENTITY rf_out_buf_4 IS
-PORT (
-  nck    : in  BIT;
-  xcks	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END rf_out_buf_4;
-
-ARCHITECTURE VBE OF rf_out_buf_4 IS
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on rf_out_buf_4"
-  SEVERITY WARNING;
-
-  xcks <= not nck;
-
-END;
diff --git a/alliance/share/cells/rflib/rf_out_mem.ap b/alliance/share/cells/rflib/rf_out_mem.ap
deleted file mode 100644
index 31fb0579..00000000
--- a/alliance/share/cells/rflib/rf_out_mem.ap
+++ /dev/null
@@ -1,140 +0,0 @@
-V ALLIANCE : 6
-H rf_out_mem,P,14/ 6/2001,10
-A 0,0,550,500
-R 450,400,ref_ref,dataout_40
-R 450,350,ref_ref,dataout_35
-R 450,300,ref_ref,dataout_30
-R 450,250,ref_ref,dataout_25
-R 450,200,ref_ref,dataout_20
-R 450,150,ref_ref,dataout_15
-R 450,100,ref_ref,dataout_10
-S 150,250,250,250,20,*,RIGHT,TALU2
-S 150,310,150,470,30,*,UP,PDIF
-S 210,310,210,420,30,*,UP,PDIF
-S 180,290,180,440,10,*,UP,PTRANS
-S 180,210,180,290,10,*,DOWN,POLY
-S 450,100,450,400,20,dataout,DOWN,CALU1
-S 0,470,550,470,60,vdd,LEFT,CALU1
-S 0,30,550,30,60,vss,RIGHT,CALU1
-S 390,300,390,450,20,*,DOWN,ALU1
-S 390,50,390,150,20,*,UP,ALU1
-S 510,300,510,450,20,*,UP,ALU1
-S 510,50,510,150,20,*,UP,ALU1
-S 420,190,420,260,10,*,DOWN,POLY
-S 480,190,480,260,10,*,DOWN,POLY
-S 510,280,510,470,30,*,UP,PDIF
-S 10,410,60,410,30,*,RIGHT,PTRANS
-S 450,280,450,470,30,*,UP,PDIF
-S 420,260,420,490,10,*,UP,PTRANS
-S 90,380,90,470,30,*,UP,PDIF
-S 390,280,390,470,30,*,UP,PDIF
-S 120,360,120,490,10,*,UP,PTRANS
-S 480,260,480,490,10,*,UP,PTRANS
-S 480,60,480,190,10,*,UP,NTRANS
-S 510,40,510,170,30,*,UP,NDIF
-S 420,60,420,190,10,*,UP,NTRANS
-S 450,80,450,170,30,*,UP,NDIF
-S 0,430,550,430,160,*,RIGHT,NWELL
-S 60,340,60,420,10,*,DOWN,POLY
-S 60,350,90,350,30,*,RIGHT,POLY
-S 330,250,400,250,10,*,RIGHT,ALU1
-S 390,250,480,250,30,*,RIGHT,POLY
-S 110,390,550,390,240,*,LEFT,NWELL
-S 360,290,360,390,10,*,UP,PTRANS
-S 330,310,330,370,30,*,UP,PDIF
-S 270,230,360,230,10,*,RIGHT,POLY
-S 360,210,360,290,10,*,DOWN,POLY
-S 360,110,360,210,10,*,UP,NTRANS
-S 330,130,330,190,30,*,UP,NDIF
-S 390,40,390,190,30,*,UP,NDIF
-S 300,400,330,400,30,*,RIGHT,POLY
-S 250,400,300,400,30,*,RIGHT,PTRANS
-S 50,250,50,250,20,rbus,LEFT,CALU2
-S 30,300,50,300,20,*,LEFT,ALU1
-S 30,300,30,370,20,*,UP,ALU1
-S 250,80,300,80,40,*,RIGHT,NTRANS
-S 240,120,240,210,10,*,UP,NTRANS
-S 270,120,270,190,30,*,UP,NDIF
-S 210,150,210,190,30,*,UP,NDIF
-S 180,120,180,210,10,*,UP,NTRANS
-S 330,100,330,400,10,*,DOWN,ALU1
-S 150,250,230,250,20,*,RIGHT,ALU2
-S 240,210,240,250,10,*,DOWN,POLY
-S 150,30,150,190,30,*,UP,NDIF
-S 300,80,330,80,40,*,RIGHT,POLY
-S 150,250,150,250,20,xcks,LEFT,CALU3
-S 150,400,150,450,20,*,UP,ALU1
-S 150,50,150,100,20,*,DOWN,ALU1
-S 210,350,210,400,10,*,UP,ALU1
-S 150,350,210,350,10,*,LEFT,ALU1
-S 150,150,150,350,10,*,UP,ALU1
-S 150,150,210,150,10,*,RIGHT,ALU1
-S 100,260,180,260,10,*,RIGHT,POLY
-S 50,200,50,300,20,*,UP,ALU1
-S 50,210,120,210,10,*,RIGHT,POLY
-S 120,80,120,210,10,*,UP,NTRANS
-S 90,100,90,190,30,*,UP,NDIF
-S 50,310,120,310,10,*,RIGHT,POLY
-S 120,310,120,360,10,*,DOWN,POLY
-S 80,350,100,350,20,*,RIGHT,ALU1
-S 100,150,100,350,10,*,UP,ALU1
-S 90,350,90,400,10,*,DOWN,ALU1
-S 270,150,280,150,20,*,RIGHT,ALU1
-S 280,150,280,350,10,*,DOWN,ALU1
-S 270,350,280,350,10,*,LEFT,ALU1
-S 270,350,270,360,10,*,UP,ALU1
-V 270,440,CONT_DIF_P,*
-V 330,30,CONT_BODY_P,*
-V 450,30,CONT_BODY_P,*
-V 210,470,CONT_BODY_N,*
-V 390,300,CONT_DIF_P,*
-V 510,350,CONT_DIF_P,*
-V 210,400,CONT_DIF_P,*
-V 510,400,CONT_DIF_P,*
-V 390,350,CONT_DIF_P,*
-V 390,400,CONT_DIF_P,*
-V 30,370,CONT_DIF_P,*
-V 510,300,CONT_DIF_P,*
-V 150,450,CONT_DIF_P,*
-V 390,450,CONT_DIF_P,*
-V 510,450,CONT_DIF_P,*
-V 450,400,CONT_DIF_P,*
-V 30,450,CONT_DIF_P,*
-V 90,400,CONT_DIF_P,*
-V 210,350,CONT_DIF_P,*
-V 330,350,CONT_DIF_P,*
-V 450,300,CONT_DIF_P,*
-V 450,350,CONT_DIF_P,*
-V 150,400,CONT_DIF_P,*
-V 390,150,CONT_DIF_N,*
-V 510,150,CONT_DIF_N,*
-V 330,150,CONT_DIF_N,*
-V 510,50,CONT_DIF_N,*
-V 390,100,CONT_DIF_N,*
-V 450,100,CONT_DIF_N,*
-V 450,150,CONT_DIF_N,*
-V 390,50,CONT_DIF_N,*
-V 510,100,CONT_DIF_N,*
-V 80,350,CONT_POLY,*
-V 330,470,CONT_BODY_N,*
-V 400,250,CONT_POLY,*
-V 270,360,CONT_DIF_P,*
-V 320,400,CONT_POLY,*
-V 50,250,CONT_VIA,*
-V 50,300,CONT_POLY,*
-V 270,30,CONT_DIF_N,*
-V 270,150,CONT_DIF_N,*
-V 280,230,CONT_POLY,*
-V 210,150,CONT_DIF_N,*
-V 320,100,CONT_POLY,*
-V 150,250,CONT_VIA2,*
-V 230,250,CONT_POLY,*
-V 230,250,CONT_VIA,*
-V 210,30,CONT_BODY_P,*
-V 150,100,CONT_DIF_N,*
-V 150,50,CONT_DIF_N,*
-V 50,200,CONT_POLY,*
-V 90,150,CONT_DIF_N,*
-V 90,30,CONT_BODY_P,*
-V 100,260,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/rflib/rf_out_mem.vbe b/alliance/share/cells/rflib/rf_out_mem.vbe
deleted file mode 100644
index 86cd1067..00000000
--- a/alliance/share/cells/rflib/rf_out_mem.vbe
+++ /dev/null
@@ -1,26 +0,0 @@
-ENTITY rf_out_mem IS
-PORT (
-  rbus    : in  BIT;
-  xcks     : in  BIT;
-  dataout : out BIT;
-  vdd     : in  BIT;
-  vss     : in  BIT
-);
-END rf_out_mem;
-
-ARCHITECTURE VBE OF rf_out_mem IS
-  SIGNAL latch	 : REG_BIT REGISTER;
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on rf_out_mem"
-  SEVERITY WARNING;
-
-  label0 : BLOCK (xcks = '1')
-  BEGIN
-    latch <= GUARDED rbus;
-  END BLOCK label0;
-
-  dataout <= latch;
-
-END;
diff --git a/alliance/share/cells/rflib/rflib.lef b/alliance/share/cells/rflib/rflib.lef
deleted file mode 100644
index a2bd4347..00000000
--- a/alliance/share/cells/rflib/rflib.lef
+++ /dev/null
@@ -1,2508 +0,0 @@
-
-MACRO rf_dec_bufad0
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      45.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION INOUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-        END
-    END nq
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-        END
-    END q
-    PIN i
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 39.00 6.00 41.00 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END i
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 42.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 42.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 43.50 41.00 ;
-    END
-END rf_dec_bufad0
-
-
-MACRO rf_dec_bufad1
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      50.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION INOUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-        END
-    END nq
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-        END
-    END q
-    PIN i
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-        END
-    END i
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 47.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 47.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 48.50 41.00 ;
-        LAYER L_ALU2 ;
-        RECT 19.00 19.00 31.00 21.00 ;
-    END
-END rf_dec_bufad1
-
-
-MACRO rf_dec_bufad2
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      50.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq0
-        DIRECTION INOUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-        END
-    END nq0
-    PIN nq1
-        DIRECTION INOUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-        END
-    END nq1
-    PIN q0
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-        END
-    END q0
-    PIN q1
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 44.00 19.00 46.00 21.00 ;
-        END
-    END q1
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-        END
-    END i1
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 47.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 47.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 48.50 41.00 ;
-        LAYER L_ALU2 ;
-        RECT 19.00 19.00 46.00 21.00 ;
-    END
-END rf_dec_bufad2
-
-
-MACRO rf_dec_nand2
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      50.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-        END
-    END nq
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-        END
-    END i1
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-        END
-    END i0
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 47.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 47.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 48.50 41.00 ;
-        LAYER L_ALU2 ;
-        RECT 19.00 19.00 36.00 21.00 ;
-    END
-END rf_dec_nand2
-
-
-MACRO rf_dec_nand3
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      50.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-        END
-    END nq
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-        END
-    END i1
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-        END
-    END i2
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 47.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 47.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 48.50 41.00 ;
-        LAYER L_ALU2 ;
-        RECT 29.00 19.00 36.00 21.00 ;
-        RECT 19.00 19.00 41.00 21.00 ;
-    END
-END rf_dec_nand3
-
-
-MACRO rf_dec_nand4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      50.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-        END
-    END nq
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-        END
-    END i2
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-        END
-    END i1
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-        END
-    END i0
-    PIN i3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-        END
-    END i3
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 47.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 47.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 48.50 41.00 ;
-        LAYER L_ALU2 ;
-        RECT 14.00 19.00 41.00 21.00 ;
-        RECT 29.00 19.00 36.00 21.00 ;
-    END
-END rf_dec_nand4
-
-
-MACRO rf_dec_nao3
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      25.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END nq
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-        END
-    END i2
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-        END
-    END i1
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 22.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 22.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 23.50 41.00 ;
-        LAYER L_ALU2 ;
-        RECT 4.00 19.00 11.00 21.00 ;
-    END
-END rf_dec_nao3
-
-
-MACRO rf_dec_nbuf
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      55.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 19.00 9.00 21.00 11.00 ;
-            RECT 14.00 9.00 16.00 11.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END nq
-    PIN i
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 49.00 39.00 51.00 41.00 ;
-            RECT 49.00 34.00 51.00 36.00 ;
-            RECT 49.00 29.00 51.00 31.00 ;
-            RECT 49.00 24.00 51.00 26.00 ;
-            RECT 49.00 19.00 51.00 21.00 ;
-            RECT 49.00 14.00 51.00 16.00 ;
-            RECT 49.00 9.00 51.00 11.00 ;
-        END
-    END i
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 52.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 52.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 53.50 41.00 ;
-    END
-END rf_dec_nbuf
-
-
-MACRO rf_dec_nor3
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      25.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END nq
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-        END
-    END i1
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 19.00 9.00 21.00 11.00 ;
-        END
-    END i2
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-        END
-    END i0
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 22.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 22.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 23.50 41.00 ;
-        LAYER L_ALU2 ;
-        RECT 4.00 19.00 11.00 21.00 ;
-    END
-END rf_dec_nor3
-
-
-MACRO rf_fifo_buf
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      50.00 BY 100.00 ;
-    SYMMETRY  Y ;
-    SITE      core ;
-    PIN xcks
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 39.00 6.00 41.00 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END xcks
-    PIN xckm
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 34.00 39.00 36.00 41.00 ;
-            RECT 34.00 34.00 36.00 36.00 ;
-            RECT 34.00 29.00 36.00 31.00 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-            RECT 34.00 14.00 36.00 16.00 ;
-            RECT 34.00 9.00 36.00 11.00 ;
-        END
-    END xckm
-    PIN nw
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 89.00 26.00 91.00 ;
-            RECT 24.00 84.00 26.00 86.00 ;
-            RECT 24.00 79.00 26.00 81.00 ;
-            RECT 24.00 74.00 26.00 76.00 ;
-            RECT 24.00 69.00 26.00 71.00 ;
-            RECT 24.00 64.00 26.00 66.00 ;
-            RECT 24.00 59.00 26.00 61.00 ;
-        END
-    END nw
-    PIN nr
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 89.00 6.00 91.00 ;
-            RECT 4.00 84.00 6.00 86.00 ;
-            RECT 4.00 79.00 6.00 81.00 ;
-            RECT 4.00 74.00 6.00 76.00 ;
-            RECT 4.00 69.00 6.00 71.00 ;
-            RECT 4.00 64.00 6.00 66.00 ;
-            RECT 4.00 59.00 6.00 61.00 ;
-        END
-    END nr
-    PIN xreset
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 39.00 39.00 41.00 41.00 ;
-            RECT 39.00 34.00 41.00 36.00 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-            RECT 39.00 24.00 41.00 26.00 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-            RECT 39.00 14.00 41.00 16.00 ;
-            RECT 39.00 9.00 41.00 11.00 ;
-        END
-    END xreset
-    PIN nreset
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 44.00 59.00 46.00 61.00 ;
-            RECT 44.00 54.00 46.00 56.00 ;
-            RECT 44.00 49.00 46.00 51.00 ;
-            RECT 44.00 44.00 46.00 46.00 ;
-            RECT 44.00 39.00 46.00 41.00 ;
-            RECT 44.00 34.00 46.00 36.00 ;
-            RECT 44.00 29.00 46.00 31.00 ;
-            RECT 44.00 24.00 46.00 26.00 ;
-        END
-    END nreset
-    PIN w
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 29.00 74.00 31.00 76.00 ;
-        END
-    END w
-    PIN r
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 9.00 84.00 11.00 86.00 ;
-        END
-    END r
-    PIN ckm
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 19.00 9.00 21.00 11.00 ;
-        END
-    END ckm
-    PIN cks
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 19.00 39.00 21.00 41.00 ;
-        END
-    END cks
-    PIN reset
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 39.00 79.00 41.00 81.00 ;
-        END
-    END reset
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 47.00 47.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 53.00 47.00 53.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 47.00 3.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 97.00 47.00 97.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 48.50 41.00 ;
-        RECT 1.50 59.00 48.50 91.00 ;
-        LAYER L_ALU2 ;
-        RECT 44.00 59.00 51.00 61.00 ;
-        RECT 44.00 24.00 51.00 26.00 ;
-    END
-END rf_fifo_buf
-
-
-MACRO rf_fifo_clock
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      50.00 BY 100.00 ;
-    SYMMETRY  Y ;
-    SITE      core ;
-    PIN cks
-        DIRECTION INOUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 29.00 79.00 31.00 81.00 ;
-            RECT 29.00 74.00 31.00 76.00 ;
-            RECT 29.00 69.00 31.00 71.00 ;
-            RECT 29.00 64.00 31.00 66.00 ;
-            RECT 29.00 59.00 31.00 61.00 ;
-            RECT 29.00 54.00 31.00 56.00 ;
-            RECT 29.00 49.00 31.00 51.00 ;
-            RECT 29.00 44.00 31.00 46.00 ;
-            RECT 29.00 39.00 31.00 41.00 ;
-        END
-    END cks
-    PIN ckm
-        DIRECTION INOUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 19.00 84.00 21.00 86.00 ;
-            RECT 19.00 79.00 21.00 81.00 ;
-            RECT 19.00 74.00 21.00 76.00 ;
-            RECT 19.00 69.00 21.00 71.00 ;
-            RECT 19.00 64.00 21.00 66.00 ;
-            RECT 19.00 59.00 21.00 61.00 ;
-            RECT 19.00 54.00 21.00 56.00 ;
-            RECT 19.00 49.00 21.00 51.00 ;
-            RECT 19.00 44.00 21.00 46.00 ;
-            RECT 19.00 39.00 21.00 41.00 ;
-        END
-    END ckm
-    PIN ckok
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 89.00 11.00 91.00 ;
-            RECT 9.00 84.00 11.00 86.00 ;
-            RECT 9.00 79.00 11.00 81.00 ;
-            RECT 9.00 74.00 11.00 76.00 ;
-            RECT 9.00 69.00 11.00 71.00 ;
-            RECT 9.00 64.00 11.00 66.00 ;
-            RECT 9.00 59.00 11.00 61.00 ;
-        END
-    END ckok
-    PIN wok
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 79.00 6.00 81.00 ;
-            RECT 4.00 74.00 6.00 76.00 ;
-            RECT 4.00 69.00 6.00 71.00 ;
-            RECT 4.00 64.00 6.00 66.00 ;
-        END
-    END wok
-    PIN ck
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 49.00 69.00 51.00 71.00 ;
-            RECT 49.00 64.00 51.00 66.00 ;
-            RECT 49.00 59.00 51.00 61.00 ;
-            RECT 49.00 54.00 51.00 56.00 ;
-            RECT 49.00 49.00 51.00 51.00 ;
-            RECT 49.00 44.00 51.00 46.00 ;
-            RECT 49.00 39.00 51.00 41.00 ;
-            RECT 49.00 34.00 51.00 36.00 ;
-            RECT 49.00 29.00 51.00 31.00 ;
-            RECT 49.00 24.00 51.00 26.00 ;
-            LAYER L_ALU2 ;
-            RECT 49.00 69.00 51.00 71.00 ;
-            RECT 44.00 69.00 46.00 71.00 ;
-            RECT 39.00 69.00 41.00 71.00 ;
-            RECT 34.00 69.00 36.00 71.00 ;
-            RECT 29.00 69.00 31.00 71.00 ;
-            RECT 24.00 69.00 26.00 71.00 ;
-            RECT 19.00 69.00 21.00 71.00 ;
-        END
-    END ck
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 47.00 47.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 53.00 47.00 53.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 47.00 3.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 97.00 47.00 97.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 48.50 41.00 ;
-        RECT 1.50 59.00 48.50 91.00 ;
-        LAYER L_ALU2 ;
-        RECT 19.00 84.00 36.00 86.00 ;
-        RECT 14.00 39.00 21.00 41.00 ;
-        RECT 9.00 24.00 51.00 26.00 ;
-        RECT 24.00 39.00 31.00 41.00 ;
-        RECT 29.00 19.00 41.00 21.00 ;
-        RECT 9.00 24.00 36.00 26.00 ;
-        RECT 34.00 59.00 41.00 61.00 ;
-        RECT 29.00 79.00 46.00 81.00 ;
-        RECT 9.00 84.00 36.00 86.00 ;
-        RECT 29.00 19.00 41.00 21.00 ;
-        RECT 9.00 39.00 46.00 41.00 ;
-        LAYER L_ALU3 ;
-        RECT 39.00 19.00 41.00 61.00 ;
-        RECT 34.00 24.00 36.00 61.00 ;
-        RECT 44.00 39.00 46.00 81.00 ;
-        RECT 44.00 39.00 46.00 81.00 ;
-        RECT 34.00 24.00 36.00 61.00 ;
-        RECT 39.00 19.00 41.00 61.00 ;
-    END
-END rf_fifo_clock
-
-
-MACRO rf_fifo_empty
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      50.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN empty
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 44.00 39.00 46.00 41.00 ;
-            RECT 44.00 34.00 46.00 36.00 ;
-            RECT 44.00 29.00 46.00 31.00 ;
-            RECT 44.00 24.00 46.00 26.00 ;
-            RECT 44.00 19.00 46.00 21.00 ;
-            RECT 44.00 14.00 46.00 16.00 ;
-        END
-    END empty
-    PIN emptynext
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-        END
-    END emptynext
-    PIN nreset
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-        END
-    END nreset
-    PIN ckm
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-        END
-    END ckm
-    PIN cks
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 19.00 9.00 21.00 11.00 ;
-        END
-    END cks
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 47.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 47.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 48.50 41.00 ;
-    END
-END rf_fifo_empty
-
-
-MACRO rf_fifo_full
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      50.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN full
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 44.00 39.00 46.00 41.00 ;
-            RECT 44.00 34.00 46.00 36.00 ;
-            RECT 44.00 29.00 46.00 31.00 ;
-            RECT 44.00 24.00 46.00 26.00 ;
-            RECT 44.00 19.00 46.00 21.00 ;
-            RECT 44.00 14.00 46.00 16.00 ;
-        END
-    END full
-    PIN reset
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-        END
-    END reset
-    PIN ckm
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-        END
-    END ckm
-    PIN cks
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 19.00 9.00 21.00 11.00 ;
-        END
-    END cks
-    PIN fullnext
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-        END
-    END fullnext
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 47.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 47.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 48.50 41.00 ;
-    END
-END rf_fifo_full
-
-
-MACRO rf_fifo_inc
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      50.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN inc
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 4.00 39.00 6.00 41.00 ;
-        END
-    END inc
-    PIN ckm
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-        END
-    END ckm
-    PIN nreset
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-        END
-    END nreset
-    PIN nval
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 29.00 39.00 31.00 41.00 ;
-        END
-    END nval
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 47.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 47.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 48.50 41.00 ;
-    END
-END rf_fifo_inc
-
-
-MACRO rf_fifo_nop
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      50.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nval
-        DIRECTION INOUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 29.00 39.00 31.00 41.00 ;
-        END
-    END nval
-    PIN nop
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 4.00 39.00 6.00 41.00 ;
-        END
-    END nop
-    PIN rwok
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-        END
-    END rwok
-    PIN rw
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 44.00 14.00 46.00 16.00 ;
-        END
-    END rw
-    PIN nreset
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-        END
-    END nreset
-    PIN ckm
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-        END
-    END ckm
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 47.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 47.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 48.50 41.00 ;
-    END
-END rf_fifo_nop
-
-
-MACRO rf_fifo_ok
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      50.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN ok
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END ok
-    PIN nextval
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-        END
-    END nextval
-    PIN ripple
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 44.00 34.00 46.00 36.00 ;
-        END
-    END ripple
-    PIN nrw
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-        END
-    END nrw
-    PIN rw
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-        END
-    END rw
-    PIN prev
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-        END
-    END prev
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 47.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 47.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 48.50 41.00 ;
-    END
-END rf_fifo_ok
-
-
-MACRO rf_fifo_orand4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      50.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN rippleout
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END rippleout
-    PIN b1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-        END
-    END b1
-    PIN a1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-        END
-    END a1
-    PIN b0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 39.00 34.00 41.00 36.00 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-            RECT 39.00 24.00 41.00 26.00 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-            RECT 39.00 14.00 41.00 16.00 ;
-            RECT 39.00 9.00 41.00 11.00 ;
-        END
-    END b0
-    PIN a0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 34.00 34.00 36.00 36.00 ;
-            RECT 34.00 29.00 36.00 31.00 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-            RECT 34.00 14.00 36.00 16.00 ;
-            RECT 34.00 9.00 36.00 11.00 ;
-        END
-    END a0
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 47.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 47.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 48.50 41.00 ;
-    END
-END rf_fifo_orand4
-
-
-MACRO rf_fifo_orand5
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      50.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN rippleout
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END rippleout
-    PIN b1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-        END
-    END b1
-    PIN a1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-        END
-    END a1
-    PIN b0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 44.00 29.00 46.00 31.00 ;
-            RECT 44.00 24.00 46.00 26.00 ;
-            RECT 44.00 19.00 46.00 21.00 ;
-            RECT 44.00 14.00 46.00 16.00 ;
-        END
-    END b0
-    PIN a0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 34.00 29.00 36.00 31.00 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-            RECT 34.00 14.00 36.00 16.00 ;
-        END
-    END a0
-    PIN ripplein
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 29.00 31.00 31.00 ;
-            RECT 29.00 24.00 31.00 26.00 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-            RECT 29.00 14.00 31.00 16.00 ;
-        END
-    END ripplein
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 47.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 47.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 48.50 41.00 ;
-    END
-END rf_fifo_orand5
-
-
-MACRO rf_fifo_ptreset
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      50.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN pt
-        DIRECTION INOUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 44.00 9.00 46.00 11.00 ;
-            RECT 39.00 9.00 41.00 11.00 ;
-        END
-    END pt
-    PIN cks
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-        END
-    END cks
-    PIN nop
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-        END
-    END nop
-    PIN reset
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-        END
-    END reset
-    PIN inc
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-        END
-    END inc
-    PIN ptm1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 29.00 9.00 31.00 11.00 ;
-        END
-    END ptm1
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 47.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 47.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 48.50 41.00 ;
-        LAYER L_ALU2 ;
-        RECT 4.00 34.00 41.00 36.00 ;
-        RECT 4.00 34.00 41.00 36.00 ;
-        RECT 34.00 19.00 41.00 21.00 ;
-        RECT 9.00 19.00 16.00 21.00 ;
-        RECT 9.00 19.00 41.00 21.00 ;
-    END
-END rf_fifo_ptreset
-
-
-MACRO rf_fifo_ptset
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      50.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN pt
-        DIRECTION INOUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 44.00 9.00 46.00 11.00 ;
-            RECT 39.00 9.00 41.00 11.00 ;
-        END
-    END pt
-    PIN nop
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-        END
-    END nop
-    PIN ptm1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 29.00 9.00 31.00 11.00 ;
-        END
-    END ptm1
-    PIN nreset
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-        END
-    END nreset
-    PIN cks
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-        END
-    END cks
-    PIN inc
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-        END
-    END inc
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 47.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 47.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 48.50 41.00 ;
-        LAYER L_ALU2 ;
-        RECT 9.00 19.00 16.00 21.00 ;
-        RECT 34.00 19.00 41.00 21.00 ;
-        RECT 4.00 34.00 41.00 36.00 ;
-        RECT 9.00 19.00 41.00 21.00 ;
-        RECT 4.00 34.00 41.00 36.00 ;
-    END
-END rf_fifo_ptset
-
-
-MACRO rf_inmux_buf_2
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      45.00 BY 100.00 ;
-    SYMMETRY  Y ;
-    SITE      core ;
-    PIN sel1
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-        END
-    END sel1
-    PIN sel0
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 34.00 39.00 36.00 41.00 ;
-        END
-    END sel0
-    PIN nck
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 34.00 89.00 36.00 91.00 ;
-        END
-    END nck
-    PIN sel
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 89.00 16.00 91.00 ;
-            RECT 14.00 84.00 16.00 86.00 ;
-            RECT 14.00 79.00 16.00 81.00 ;
-            RECT 14.00 74.00 16.00 76.00 ;
-            RECT 14.00 69.00 16.00 71.00 ;
-        END
-    END sel
-    PIN ck
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 89.00 21.00 91.00 ;
-            RECT 19.00 84.00 21.00 86.00 ;
-            RECT 19.00 79.00 21.00 81.00 ;
-            RECT 19.00 74.00 21.00 76.00 ;
-            RECT 19.00 69.00 21.00 71.00 ;
-        END
-    END ck
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 42.00 47.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 53.00 42.00 53.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 42.00 3.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 97.00 42.00 97.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 43.50 41.00 ;
-        RECT 1.50 59.00 43.50 91.00 ;
-        LAYER L_ALU2 ;
-        RECT 24.00 39.00 41.00 41.00 ;
-        RECT 4.00 14.00 26.00 16.00 ;
-        RECT 8.00 14.00 26.00 16.00 ;
-        RECT 26.00 39.00 40.00 41.00 ;
-    END
-END rf_inmux_buf_2
-
-
-MACRO rf_inmux_buf_4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      45.00 BY 200.00 ;
-    SYMMETRY  Y ;
-    SITE      core ;
-    PIN sel1
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 24.00 184.00 26.00 186.00 ;
-            RECT 24.00 179.00 26.00 181.00 ;
-            RECT 24.00 174.00 26.00 176.00 ;
-            RECT 24.00 169.00 26.00 171.00 ;
-            RECT 24.00 164.00 26.00 166.00 ;
-            RECT 24.00 159.00 26.00 161.00 ;
-            RECT 24.00 154.00 26.00 156.00 ;
-            RECT 24.00 149.00 26.00 151.00 ;
-            RECT 24.00 144.00 26.00 146.00 ;
-            RECT 24.00 139.00 26.00 141.00 ;
-            RECT 24.00 134.00 26.00 136.00 ;
-            RECT 24.00 129.00 26.00 131.00 ;
-            RECT 24.00 124.00 26.00 126.00 ;
-            RECT 24.00 119.00 26.00 121.00 ;
-            RECT 24.00 114.00 26.00 116.00 ;
-            RECT 24.00 109.00 26.00 111.00 ;
-            RECT 24.00 104.00 26.00 106.00 ;
-            RECT 24.00 99.00 26.00 101.00 ;
-            RECT 24.00 94.00 26.00 96.00 ;
-            RECT 24.00 89.00 26.00 91.00 ;
-            RECT 24.00 84.00 26.00 86.00 ;
-            RECT 24.00 79.00 26.00 81.00 ;
-            RECT 24.00 74.00 26.00 76.00 ;
-            RECT 24.00 69.00 26.00 71.00 ;
-            RECT 24.00 64.00 26.00 66.00 ;
-            RECT 24.00 59.00 26.00 61.00 ;
-            RECT 24.00 54.00 26.00 56.00 ;
-            RECT 24.00 49.00 26.00 51.00 ;
-            RECT 24.00 44.00 26.00 46.00 ;
-            RECT 24.00 39.00 26.00 41.00 ;
-            RECT 24.00 34.00 26.00 36.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-        END
-    END sel1
-    PIN sel0
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 34.00 159.00 36.00 161.00 ;
-            RECT 34.00 154.00 36.00 156.00 ;
-            RECT 34.00 149.00 36.00 151.00 ;
-            RECT 34.00 144.00 36.00 146.00 ;
-            RECT 34.00 139.00 36.00 141.00 ;
-            RECT 34.00 134.00 36.00 136.00 ;
-            RECT 34.00 129.00 36.00 131.00 ;
-            RECT 34.00 124.00 36.00 126.00 ;
-            RECT 34.00 119.00 36.00 121.00 ;
-            RECT 34.00 114.00 36.00 116.00 ;
-            RECT 34.00 109.00 36.00 111.00 ;
-            RECT 34.00 104.00 36.00 106.00 ;
-            RECT 34.00 99.00 36.00 101.00 ;
-            RECT 34.00 94.00 36.00 96.00 ;
-            RECT 34.00 89.00 36.00 91.00 ;
-            RECT 34.00 84.00 36.00 86.00 ;
-            RECT 34.00 79.00 36.00 81.00 ;
-            RECT 34.00 74.00 36.00 76.00 ;
-            RECT 34.00 69.00 36.00 71.00 ;
-            RECT 34.00 64.00 36.00 66.00 ;
-            RECT 34.00 59.00 36.00 61.00 ;
-            RECT 34.00 54.00 36.00 56.00 ;
-            RECT 34.00 49.00 36.00 51.00 ;
-            RECT 34.00 44.00 36.00 46.00 ;
-            RECT 34.00 39.00 36.00 41.00 ;
-        END
-    END sel0
-    PIN nck
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 34.00 89.00 36.00 91.00 ;
-            RECT 29.00 89.00 31.00 91.00 ;
-        END
-    END nck
-    PIN sel
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 89.00 16.00 91.00 ;
-            RECT 14.00 84.00 16.00 86.00 ;
-            RECT 14.00 79.00 16.00 81.00 ;
-            RECT 14.00 74.00 16.00 76.00 ;
-            RECT 14.00 69.00 16.00 71.00 ;
-        END
-    END sel
-    PIN ck
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 89.00 21.00 91.00 ;
-            RECT 19.00 84.00 21.00 86.00 ;
-            RECT 19.00 79.00 21.00 81.00 ;
-            RECT 19.00 74.00 21.00 76.00 ;
-            RECT 19.00 69.00 21.00 71.00 ;
-        END
-    END ck
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 42.00 47.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 53.00 42.00 53.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 147.00 42.00 147.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 153.00 42.00 153.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 42.00 3.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 97.00 42.00 97.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 103.00 42.00 103.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 197.00 42.00 197.00 ;
-            LAYER L_ALU3 ;
-            WIDTH 12.00 ;
-            PATH 10.00 6.00 10.00 194.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 43.50 41.00 ;
-        RECT 1.50 59.00 43.50 91.00 ;
-        RECT 1.50 109.00 43.50 141.00 ;
-        RECT 1.50 159.00 43.50 191.00 ;
-        LAYER L_ALU2 ;
-        RECT 26.00 39.00 40.00 41.00 ;
-        RECT 8.00 14.00 26.00 16.00 ;
-        RECT 26.00 159.00 40.00 161.00 ;
-        RECT 8.00 184.00 26.00 186.00 ;
-        RECT 26.00 39.00 40.00 41.00 ;
-        RECT 8.00 14.00 26.00 16.00 ;
-        RECT 8.00 184.00 26.00 186.00 ;
-        RECT 26.00 159.00 40.00 161.00 ;
-        RECT 4.00 99.00 16.00 101.00 ;
-        RECT 4.00 -1.00 16.00 1.00 ;
-        RECT 4.00 199.00 16.00 201.00 ;
-    END
-END rf_inmux_buf_4
-
-
-MACRO rf_inmux_mem
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      45.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN dinx
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END dinx
-    PIN sel1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-        END
-    END sel1
-    PIN sel0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 34.00 29.00 36.00 31.00 ;
-        END
-    END sel0
-    PIN datain0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 39.00 21.00 41.00 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-        END
-    END datain0
-    PIN datain1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 39.00 39.00 41.00 41.00 ;
-            RECT 39.00 34.00 41.00 36.00 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-            RECT 39.00 24.00 41.00 26.00 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-            RECT 39.00 14.00 41.00 16.00 ;
-        END
-    END datain1
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 42.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 42.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 43.50 41.00 ;
-        LAYER L_ALU2 ;
-        RECT 24.00 29.00 36.00 31.00 ;
-    END
-END rf_inmux_mem
-
-
-MACRO rf_mid_buf_2
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      25.00 BY 100.00 ;
-    SYMMETRY  Y ;
-    SITE      core ;
-    PIN write
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 19.00 59.00 21.00 61.00 ;
-            RECT 19.00 54.00 21.00 56.00 ;
-            RECT 19.00 49.00 21.00 51.00 ;
-            RECT 19.00 44.00 21.00 46.00 ;
-            RECT 19.00 39.00 21.00 41.00 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-        END
-    END write
-    PIN read
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 4.00 59.00 6.00 61.00 ;
-            RECT 4.00 54.00 6.00 56.00 ;
-            RECT 4.00 49.00 6.00 51.00 ;
-            RECT 4.00 44.00 6.00 46.00 ;
-            RECT 4.00 39.00 6.00 41.00 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-        END
-    END read
-    PIN nck
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 24.00 89.00 26.00 91.00 ;
-        END
-    END nck
-    PIN selr
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 9.00 79.00 11.00 81.00 ;
-        END
-    END selr
-    PIN selw
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 14.00 84.00 16.00 86.00 ;
-        END
-    END selw
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 22.00 47.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 53.00 22.00 53.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 22.00 3.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 97.00 22.00 97.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 23.50 41.00 ;
-        RECT 1.50 59.00 23.50 91.00 ;
-        LAYER L_ALU2 ;
-        RECT 4.00 14.00 21.00 16.00 ;
-        RECT 4.00 39.00 21.00 41.00 ;
-        RECT 4.00 59.00 21.00 61.00 ;
-    END
-END rf_mid_buf_2
-
-
-MACRO rf_mid_buf_4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      25.00 BY 200.00 ;
-    SYMMETRY  Y ;
-    SITE      core ;
-    PIN read
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 4.00 184.00 6.00 186.00 ;
-            RECT 4.00 179.00 6.00 181.00 ;
-            RECT 4.00 174.00 6.00 176.00 ;
-            RECT 4.00 169.00 6.00 171.00 ;
-            RECT 4.00 164.00 6.00 166.00 ;
-            RECT 4.00 159.00 6.00 161.00 ;
-            RECT 4.00 154.00 6.00 156.00 ;
-            RECT 4.00 149.00 6.00 151.00 ;
-            RECT 4.00 144.00 6.00 146.00 ;
-            RECT 4.00 139.00 6.00 141.00 ;
-        END
-    END read
-    PIN write
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 19.00 59.00 21.00 61.00 ;
-            RECT 19.00 54.00 21.00 56.00 ;
-            RECT 19.00 49.00 21.00 51.00 ;
-            RECT 19.00 44.00 21.00 46.00 ;
-            RECT 19.00 39.00 21.00 41.00 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-        END
-    END write
-    PIN nck
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 24.00 89.00 26.00 91.00 ;
-            RECT 19.00 89.00 21.00 91.00 ;
-            RECT 14.00 89.00 16.00 91.00 ;
-            RECT 9.00 89.00 11.00 91.00 ;
-            RECT 4.00 89.00 6.00 91.00 ;
-            RECT -1.00 89.00 1.00 91.00 ;
-        END
-    END nck
-    PIN selw
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 14.00 84.00 16.00 86.00 ;
-        END
-    END selw
-    PIN selr
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 9.00 114.00 11.00 116.00 ;
-        END
-    END selr
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 22.00 47.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 53.00 22.00 53.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 147.00 22.00 147.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 153.00 22.00 153.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 22.00 3.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 97.00 22.00 97.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 103.00 22.00 103.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 197.00 22.00 197.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 23.50 41.00 ;
-        RECT 1.50 59.00 23.50 91.00 ;
-        RECT 1.50 109.00 23.50 141.00 ;
-        RECT 1.50 159.00 23.50 191.00 ;
-        LAYER L_ALU2 ;
-        RECT -1.00 14.00 26.00 16.00 ;
-        RECT -1.00 39.00 26.00 41.00 ;
-        RECT -1.00 59.00 26.00 61.00 ;
-        RECT -1.00 139.00 26.00 141.00 ;
-        RECT -1.00 159.00 26.00 161.00 ;
-        RECT -1.00 184.00 26.00 186.00 ;
-    END
-END rf_mid_buf_4
-
-
-MACRO rf_mid_mem
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      25.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN rbus
-        DIRECTION OUTPUT TRISTATE ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-        END
-    END rbus
-    PIN read
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-        END
-    END read
-    PIN write
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-        END
-    END write
-    PIN dinx
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 24.00 9.00 26.00 11.00 ;
-        END
-    END dinx
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 22.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 22.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 23.50 41.00 ;
-        LAYER L_ALU2 ;
-        RECT 4.00 29.00 16.00 31.00 ;
-        RECT 4.00 29.00 16.00 31.00 ;
-        RECT 19.00 14.00 26.00 16.00 ;
-    END
-END rf_mid_mem
-
-
-MACRO rf_mid_mem_r0
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      25.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN rbus
-        DIRECTION OUTPUT TRISTATE ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-        END
-    END rbus
-    PIN dinx
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 24.00 9.00 26.00 11.00 ;
-        END
-    END dinx
-    PIN write
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-        END
-    END write
-    PIN read
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-        END
-    END read
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 22.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 22.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 23.50 41.00 ;
-        LAYER L_ALU2 ;
-        RECT 4.00 29.00 16.00 31.00 ;
-        RECT 4.00 29.00 16.00 31.00 ;
-        RECT 19.00 14.00 26.00 16.00 ;
-    END
-END rf_mid_mem_r0
-
-
-MACRO rf_out_buf_2
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      55.00 BY 100.00 ;
-    SYMMETRY  Y ;
-    SITE      core ;
-    PIN xcks
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 14.00 59.00 16.00 61.00 ;
-            RECT 14.00 54.00 16.00 56.00 ;
-            RECT 14.00 49.00 16.00 51.00 ;
-            RECT 14.00 44.00 16.00 46.00 ;
-            RECT 14.00 39.00 16.00 41.00 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-        END
-    END xcks
-    PIN nck
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 14.00 89.00 16.00 91.00 ;
-        END
-    END nck
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 52.00 47.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 53.00 52.00 53.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 52.00 3.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 97.00 52.00 97.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 53.50 41.00 ;
-        RECT 1.50 59.00 53.50 91.00 ;
-        LAYER L_ALU2 ;
-        RECT 9.00 59.00 21.00 61.00 ;
-        RECT 9.00 39.00 21.00 41.00 ;
-        RECT 9.00 14.00 21.00 16.00 ;
-    END
-END rf_out_buf_2
-
-
-MACRO rf_out_buf_4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      55.00 BY 200.00 ;
-    SYMMETRY  Y ;
-    SITE      core ;
-    PIN xcks
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 14.00 184.00 16.00 186.00 ;
-            RECT 14.00 179.00 16.00 181.00 ;
-            RECT 14.00 174.00 16.00 176.00 ;
-            RECT 14.00 169.00 16.00 171.00 ;
-            RECT 14.00 164.00 16.00 166.00 ;
-            RECT 14.00 159.00 16.00 161.00 ;
-            RECT 14.00 154.00 16.00 156.00 ;
-            RECT 14.00 149.00 16.00 151.00 ;
-            RECT 14.00 144.00 16.00 146.00 ;
-            RECT 14.00 139.00 16.00 141.00 ;
-            RECT 14.00 134.00 16.00 136.00 ;
-            RECT 14.00 129.00 16.00 131.00 ;
-            RECT 14.00 124.00 16.00 126.00 ;
-            RECT 14.00 119.00 16.00 121.00 ;
-            RECT 14.00 114.00 16.00 116.00 ;
-            RECT 14.00 109.00 16.00 111.00 ;
-            RECT 14.00 104.00 16.00 106.00 ;
-            RECT 14.00 99.00 16.00 101.00 ;
-            RECT 14.00 94.00 16.00 96.00 ;
-            RECT 14.00 89.00 16.00 91.00 ;
-            RECT 14.00 84.00 16.00 86.00 ;
-            RECT 14.00 79.00 16.00 81.00 ;
-            RECT 14.00 74.00 16.00 76.00 ;
-            RECT 14.00 69.00 16.00 71.00 ;
-            RECT 14.00 64.00 16.00 66.00 ;
-            RECT 14.00 59.00 16.00 61.00 ;
-            RECT 14.00 54.00 16.00 56.00 ;
-            RECT 14.00 49.00 16.00 51.00 ;
-            RECT 14.00 44.00 16.00 46.00 ;
-            RECT 14.00 39.00 16.00 41.00 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-        END
-    END xcks
-    PIN nck
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 14.00 89.00 16.00 91.00 ;
-        END
-    END nck
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 52.00 47.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 53.00 52.00 53.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 147.00 52.00 147.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 153.00 52.00 153.00 ;
-            LAYER L_ALU3 ;
-            WIDTH 12.00 ;
-            PATH 45.00 6.00 45.00 194.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 52.00 3.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 97.00 52.00 97.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 103.00 52.00 103.00 ;
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 197.00 52.00 197.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 53.50 41.00 ;
-        RECT 1.50 59.00 53.50 91.00 ;
-        RECT 1.50 109.00 53.50 141.00 ;
-        RECT 1.50 159.00 53.50 191.00 ;
-        LAYER L_ALU2 ;
-        RECT 39.00 149.00 51.00 151.00 ;
-        RECT 39.00 49.00 51.00 51.00 ;
-        RECT 9.00 14.00 21.00 16.00 ;
-        RECT 9.00 39.00 21.00 41.00 ;
-        RECT 9.00 59.00 21.00 61.00 ;
-        RECT 9.00 139.00 21.00 141.00 ;
-        RECT 9.00 159.00 21.00 161.00 ;
-        RECT 9.00 184.00 21.00 186.00 ;
-    END
-END rf_out_buf_4
-
-
-MACRO rf_out_mem
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      55.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN dataout
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 44.00 39.00 46.00 41.00 ;
-            RECT 44.00 34.00 46.00 36.00 ;
-            RECT 44.00 29.00 46.00 31.00 ;
-            RECT 44.00 24.00 46.00 26.00 ;
-            RECT 44.00 19.00 46.00 21.00 ;
-            RECT 44.00 14.00 46.00 16.00 ;
-            RECT 44.00 9.00 46.00 11.00 ;
-        END
-    END dataout
-    PIN rbus
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU2 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-        END
-    END rbus
-    PIN xcks
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU3 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-        END
-    END xcks
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 52.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 52.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 53.50 41.00 ;
-        LAYER L_ALU2 ;
-        RECT 14.00 24.00 24.00 26.00 ;
-        RECT 14.00 24.00 26.00 26.00 ;
-    END
-END rf_out_mem
-
-
-END LIBRARY
diff --git a/alliance/share/cells/sxlib/000000002.dat b/alliance/share/cells/sxlib/000000002.dat
deleted file mode 100644
index 8f5f6414..00000000
Binary files a/alliance/share/cells/sxlib/000000002.dat and /dev/null differ
diff --git a/alliance/share/cells/sxlib/000000003.dat b/alliance/share/cells/sxlib/000000003.dat
deleted file mode 100644
index 2cc0a6b6..00000000
Binary files a/alliance/share/cells/sxlib/000000003.dat and /dev/null differ
diff --git a/alliance/share/cells/sxlib/000000004.dat b/alliance/share/cells/sxlib/000000004.dat
deleted file mode 100644
index bb0180ee..00000000
Binary files a/alliance/share/cells/sxlib/000000004.dat and /dev/null differ
diff --git a/alliance/share/cells/sxlib/000000005.dat b/alliance/share/cells/sxlib/000000005.dat
deleted file mode 100644
index b9c01ea0..00000000
Binary files a/alliance/share/cells/sxlib/000000005.dat and /dev/null differ
diff --git a/alliance/share/cells/sxlib/000000006.dat b/alliance/share/cells/sxlib/000000006.dat
deleted file mode 100644
index 04eea4f5..00000000
Binary files a/alliance/share/cells/sxlib/000000006.dat and /dev/null differ
diff --git a/alliance/share/cells/sxlib/000000007.dat b/alliance/share/cells/sxlib/000000007.dat
deleted file mode 100644
index cd8150e9..00000000
Binary files a/alliance/share/cells/sxlib/000000007.dat and /dev/null differ
diff --git a/alliance/share/cells/sxlib/000000008.dat b/alliance/share/cells/sxlib/000000008.dat
deleted file mode 100644
index 2bf65cac..00000000
Binary files a/alliance/share/cells/sxlib/000000008.dat and /dev/null differ
diff --git a/alliance/share/cells/sxlib/000000009.dat b/alliance/share/cells/sxlib/000000009.dat
deleted file mode 100644
index 639b813b..00000000
Binary files a/alliance/share/cells/sxlib/000000009.dat and /dev/null differ
diff --git a/alliance/share/cells/sxlib/000000010.dat b/alliance/share/cells/sxlib/000000010.dat
deleted file mode 100644
index 8ea6907b..00000000
Binary files a/alliance/share/cells/sxlib/000000010.dat and /dev/null differ
diff --git a/alliance/share/cells/sxlib/000000011.dat b/alliance/share/cells/sxlib/000000011.dat
deleted file mode 100644
index e23d8aa5..00000000
Binary files a/alliance/share/cells/sxlib/000000011.dat and /dev/null differ
diff --git a/alliance/share/cells/sxlib/000000012.dat b/alliance/share/cells/sxlib/000000012.dat
deleted file mode 100644
index 68fee161..00000000
Binary files a/alliance/share/cells/sxlib/000000012.dat and /dev/null differ
diff --git a/alliance/share/cells/sxlib/000000013.dat b/alliance/share/cells/sxlib/000000013.dat
deleted file mode 100644
index 3647fbf3..00000000
Binary files a/alliance/share/cells/sxlib/000000013.dat and /dev/null differ
diff --git a/alliance/share/cells/sxlib/000000014.dat b/alliance/share/cells/sxlib/000000014.dat
deleted file mode 100644
index 5074e607..00000000
Binary files a/alliance/share/cells/sxlib/000000014.dat and /dev/null differ
diff --git a/alliance/share/cells/sxlib/000000015.dat b/alliance/share/cells/sxlib/000000015.dat
deleted file mode 100644
index f0f207eb..00000000
Binary files a/alliance/share/cells/sxlib/000000015.dat and /dev/null differ
diff --git a/alliance/share/cells/sxlib/000000016.dat b/alliance/share/cells/sxlib/000000016.dat
deleted file mode 100644
index 027c98ea..00000000
Binary files a/alliance/share/cells/sxlib/000000016.dat and /dev/null differ
diff --git a/alliance/share/cells/sxlib/000000017.dat b/alliance/share/cells/sxlib/000000017.dat
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-3 NOA2AO222_X1 57
-3 NOA2AO222_X4 58
-3 NOA3AO322_X1 59
-3 NOA3AO322_X4 60
-3 NTS_X1 61
-3 NTS_X2 62
-3 NXR2_X1 63
-3 NXR2_X4 64
-3 O2_X2 65
-3 O2_X4 66
-3 O3_X2 67
-3 O3_X4 68
-3 O4_X2 69
-3 O4_X4 70
-3 OA22_X2 71
-3 OA22_X4 72
-3 OA2A22_X2 73
-3 OA2A22_X4 74
-3 OA2A2A23_X2 75
-3 OA2A2A23_X4 76
-3 OA2A2A2A24_X2 77
-3 OA2A2A2A24_X4 78
-3 OA2AO222_X2 79
-3 OA2AO222_X4 80
-3 OA3AO322_X2 81
-3 OA3AO322_X4 82
-3 ON12_X1 83
-3 ON12_X4 84
-3 ONE_X0 85
-3 ROWEND_X0 86
-3 SFF1_X4 87
-3 SFF2_X4 88
-3 SFF3_X4 89
-3 TIE_X0 90
-3 TS_X4 91
-3 TS_X8 92
-3 XR2_X1 93
-3 XR2_X4 94
-3 ZERO_X0 95
diff --git a/alliance/share/cells/sxlib/Makefile b/alliance/share/cells/sxlib/Makefile
deleted file mode 100644
index 4cc01da1..00000000
--- a/alliance/share/cells/sxlib/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-sxlib.log : sxlib.db sxlib.sdb
-	liban -arch FTGS sxlib.db > sxlib.log
diff --git a/alliance/share/cells/sxlib/a2_x2.al b/alliance/share/cells/sxlib/a2_x2.al
deleted file mode 100644
index 56135369..00000000
--- a/alliance/share/cells/sxlib/a2_x2.al
+++ /dev/null
@@ -1,28 +0,0 @@
-V ALLIANCE : 6
-H a2_x2,L,30/10/99
-C i0,IN,EXTERNAL,7
-C i1,IN,EXTERNAL,6
-C q,OUT,EXTERNAL,1
-C vdd,IN,EXTERNAL,5
-C vss,IN,EXTERNAL,4
-T P,0.35,5.9,1,2,5,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00006
-T P,0.35,2.9,5,6,2,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00005
-T P,0.35,2.9,2,7,5,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00004
-T N,0.35,2.9,2,7,3,0,0.75,0.75,7.3,7.3,1.8,3.75,tr_00003
-T N,0.35,2.9,4,2,1,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00002
-T N,0.35,2.9,3,6,4,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00001
-S 7,EXTERNAL,i0
-Q 0.00214738
-S 6,EXTERNAL,i1
-Q 0.00400776
-S 5,EXTERNAL,vdd
-Q 0.00374949
-S 4,EXTERNAL,vss
-Q 0.00298567
-S 3,INTERNAL
-Q 0
-S 2,INTERNAL
-Q 0.00463918
-S 1,EXTERNAL,q
-Q 0.00258522
-EOF
diff --git a/alliance/share/cells/sxlib/a2_x2.ap b/alliance/share/cells/sxlib/a2_x2.ap
deleted file mode 100644
index fa59a07f..00000000
--- a/alliance/share/cells/sxlib/a2_x2.ap
+++ /dev/null
@@ -1,73 +0,0 @@
-V ALLIANCE : 6
-H a2_x2,P,30/ 8/2000,100
-A 0,0,2500,5000
-R 2000,2000,ref_ref,q_20
-R 2000,1500,ref_ref,q_15
-R 2000,1000,ref_ref,q_10
-R 2000,4000,ref_ref,q_40
-R 2000,3500,ref_ref,q_35
-R 2000,3000,ref_ref,q_30
-R 2000,2500,ref_ref,q_25
-R 500,3500,ref_ref,i0_35
-R 500,3000,ref_ref,i0_30
-R 500,2500,ref_ref,i0_25
-R 500,2000,ref_ref,i0_20
-R 500,1500,ref_ref,i0_15
-R 1500,1000,ref_ref,i1_10
-R 1500,1500,ref_ref,i1_15
-R 1500,2000,ref_ref,i1_20
-R 1500,2500,ref_ref,i1_25
-R 1500,3000,ref_ref,i1_30
-R 1500,3500,ref_ref,i1_35
-R 1500,4000,ref_ref,i1_40
-S 2000,1000,2000,4000,200,*,DOWN,ALU1
-S 300,4000,300,4500,200,*,UP,ALU1
-S 300,1000,950,1000,100,*,RIGHT,ALU1
-S 950,1000,950,4000,100,*,DOWN,ALU1
-S 0,3900,2500,3900,2400,*,RIGHT,NWELL
-S 500,1500,500,3500,100,*,DOWN,ALU1
-S 900,3300,900,4200,300,*,DOWN,PDIF
-S 600,3100,600,4400,100,*,UP,PTRANS
-S 300,3300,300,4600,300,*,DOWN,PDIF
-S 1200,3100,1200,4400,100,*,UP,PTRANS
-S 1200,2400,1200,3100,100,*,DOWN,POLY
-S 1200,100,1200,1400,100,*,DOWN,NTRANS
-S 1500,300,1500,1200,300,*,UP,NDIF
-S 2100,300,2100,1200,300,*,UP,NDIF
-S 1800,100,1800,1400,100,*,DOWN,NTRANS
-S 2100,2800,2100,4700,300,*,DOWN,PDIF
-S 1500,2800,1500,4700,300,*,DOWN,PDIF
-S 1800,2600,1800,4900,100,*,UP,PTRANS
-S 1500,1000,1500,4000,100,*,DOWN,ALU1
-S 1800,1400,1800,2600,100,*,UP,POLY
-S 1200,2500,1500,2500,300,*,RIGHT,POLY
-S 1200,1500,1500,1500,300,*,RIGHT,POLY
-S 0,300,2500,300,600,vss,RIGHT,ALU1
-S 0,4700,2500,4700,600,vdd,RIGHT,ALU1
-S 0,300,2500,300,600,vss,RIGHT,CALU1
-S 0,4700,2500,4700,600,vdd,RIGHT,CALU1
-S 1000,2000,1800,2000,100,*,RIGHT,POLY
-S 600,600,600,1900,100,*,DOWN,NTRANS
-S 300,800,300,1700,300,*,UP,NDIF
-S 900,300,900,1700,300,*,UP,NDIF
-S 2000,1000,2000,4000,200,q,DOWN,CALU1
-S 500,1500,500,3500,200,i0,DOWN,CALU1
-S 1500,1000,1500,4000,200,i1,DOWN,CALU1
-V 300,4000,CONT_DIF_P,*
-V 500,3000,CONT_POLY,*
-V 1500,500,CONT_DIF_N,*
-V 300,1000,CONT_DIF_N,*
-V 1400,1500,CONT_POLY,*
-V 2100,1000,CONT_DIF_N,*
-V 900,4700,CONT_BODY_N,*
-V 2100,3000,CONT_DIF_P,*
-V 2100,3500,CONT_DIF_P,*
-V 2100,4000,CONT_DIF_P,*
-V 1500,4500,CONT_DIF_P,*
-V 900,4000,CONT_DIF_P,*
-V 300,4500,CONT_DIF_P,*
-V 1000,2000,CONT_POLY,*
-V 1400,2500,CONT_POLY,*
-V 500,2000,CONT_POLY,*
-V 300,300,CONT_BODY_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/a2_x2.sym b/alliance/share/cells/sxlib/a2_x2.sym
deleted file mode 100644
index 4ef52f4a..00000000
Binary files a/alliance/share/cells/sxlib/a2_x2.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/a2_x2.vbe b/alliance/share/cells/sxlib/a2_x2.vbe
deleted file mode 100644
index 8e6db7cd..00000000
--- a/alliance/share/cells/sxlib/a2_x2.vbe
+++ /dev/null
@@ -1,32 +0,0 @@
-ENTITY a2_x2 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 1250;
-  CONSTANT cin_i0	 : NATURAL := 9;
-  CONSTANT cin_i1	 : NATURAL := 11;
-  CONSTANT rdown_i0_q	 : NATURAL := 1620;
-  CONSTANT rdown_i1_q	 : NATURAL := 1620;
-  CONSTANT rup_i0_q	 : NATURAL := 1790;
-  CONSTANT rup_i1_q	 : NATURAL := 1790;
-  CONSTANT tphh_i1_q	 : NATURAL := 203;
-  CONSTANT tphh_i0_q	 : NATURAL := 261;
-  CONSTANT tpll_i0_q	 : NATURAL := 388;
-  CONSTANT tpll_i1_q	 : NATURAL := 434;
-  CONSTANT transistors	 : NATURAL := 6
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END a2_x2;
-
-ARCHITECTURE behaviour_data_flow OF a2_x2 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on a2_x2"
-  SEVERITY WARNING;
-  q <= (i0 and i1) after 1000 ps;
-END;
diff --git a/alliance/share/cells/sxlib/a2_x2.vhd b/alliance/share/cells/sxlib/a2_x2.vhd
deleted file mode 100644
index 9c04bc77..00000000
--- a/alliance/share/cells/sxlib/a2_x2.vhd
+++ /dev/null
@@ -1,20 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY a2_x2 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END a2_x2;
-
-ARCHITECTURE RTL OF a2_x2 IS
-BEGIN
-  q <= (i0 AND i1);
-END RTL;
diff --git a/alliance/share/cells/sxlib/a2_x4.al b/alliance/share/cells/sxlib/a2_x4.al
deleted file mode 100644
index 70f58873..00000000
--- a/alliance/share/cells/sxlib/a2_x4.al
+++ /dev/null
@@ -1,30 +0,0 @@
-V ALLIANCE : 6
-H a2_x4,L,30/10/99
-C i0,IN,EXTERNAL,7
-C i1,IN,EXTERNAL,6
-C q,OUT,EXTERNAL,2
-C vdd,IN,EXTERNAL,5
-C vss,IN,EXTERNAL,1
-T P,0.35,5.9,2,4,5,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00008
-T P,0.35,5.9,5,4,2,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00007
-T P,0.35,2.9,5,6,4,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00006
-T P,0.35,2.9,4,7,5,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00005
-T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00004
-T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00003
-T N,0.35,2.9,3,6,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002
-T N,0.35,2.9,4,7,3,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00001
-S 7,EXTERNAL,i0
-Q 0.00214738
-S 6,EXTERNAL,i1
-Q 0.00400776
-S 5,EXTERNAL,vdd
-Q 0.00579486
-S 4,INTERNAL
-Q 0.00596944
-S 3,INTERNAL
-Q 0
-S 2,EXTERNAL,q
-Q 0.00258522
-S 1,EXTERNAL,vss
-Q 0.00450225
-EOF
diff --git a/alliance/share/cells/sxlib/a2_x4.ap b/alliance/share/cells/sxlib/a2_x4.ap
deleted file mode 100644
index 80b16acc..00000000
--- a/alliance/share/cells/sxlib/a2_x4.ap
+++ /dev/null
@@ -1,84 +0,0 @@
-V ALLIANCE : 6
-H a2_x4,P,30/ 8/2000,100
-A 0,0,3000,5000
-R 2000,2000,ref_ref,q_20
-R 2000,1500,ref_ref,q_15
-R 2000,1000,ref_ref,q_10
-R 2000,4000,ref_ref,q_40
-R 2000,3500,ref_ref,q_35
-R 2000,3000,ref_ref,q_30
-R 2000,2500,ref_ref,q_25
-R 500,3500,ref_ref,i0_35
-R 500,3000,ref_ref,i0_30
-R 500,2500,ref_ref,i0_25
-R 500,2000,ref_ref,i0_20
-R 500,1500,ref_ref,i0_15
-R 1500,1000,ref_ref,i1_10
-R 1500,1500,ref_ref,i1_15
-R 1500,2000,ref_ref,i1_20
-R 1500,2500,ref_ref,i1_25
-R 1500,3000,ref_ref,i1_30
-R 1500,3500,ref_ref,i1_35
-R 1500,4000,ref_ref,i1_40
-S 2000,1000,2000,4000,200,*,DOWN,ALU1
-S 500,1500,500,3500,100,*,DOWN,ALU1
-S 900,3300,900,4200,300,*,DOWN,PDIF
-S 600,3100,600,4400,100,*,UP,PTRANS
-S 300,3300,300,4600,300,*,DOWN,PDIF
-S 1200,3100,1200,4400,100,*,UP,PTRANS
-S 1200,2400,1200,3100,100,*,DOWN,POLY
-S 600,100,600,1400,100,*,DOWN,NTRANS
-S 1200,100,1200,1400,100,*,DOWN,NTRANS
-S 900,300,900,1200,300,*,UP,NDIF
-S 300,300,300,1200,300,*,UP,NDIF
-S 2700,500,2700,1700,200,*,DOWN,ALU1
-S 2700,300,2700,1200,300,*,UP,NDIF
-S 2400,100,2400,1400,100,*,DOWN,NTRANS
-S 0,300,3000,300,600,vss,RIGHT,CALU1
-S 1500,300,1500,1200,300,*,UP,NDIF
-S 2100,300,2100,1200,300,*,UP,NDIF
-S 1800,100,1800,1400,100,*,DOWN,NTRANS
-S 0,4700,3000,4700,600,vdd,RIGHT,CALU1
-S 2100,2800,2100,4700,300,*,DOWN,PDIF
-S 1500,2800,1500,4700,300,*,DOWN,PDIF
-S 2700,2800,2700,4700,300,*,DOWN,PDIF
-S 2400,2600,2400,4900,100,*,UP,PTRANS
-S 1800,2600,1800,4900,100,*,UP,PTRANS
-S 1500,1000,1500,4000,100,*,DOWN,ALU1
-S 1000,2000,2400,2000,100,*,RIGHT,POLY
-S 1800,1400,1800,2600,100,*,UP,POLY
-S 2400,1400,2400,2600,100,*,DOWN,POLY
-S 1200,2500,1500,2500,300,*,RIGHT,POLY
-S 1200,1500,1500,1500,300,*,RIGHT,POLY
-S 2700,3000,2700,4500,200,*,DOWN,ALU1
-S 0,3900,3000,3900,2400,*,RIGHT,NWELL
-S 950,1000,950,4000,100,*,DOWN,ALU1
-S 300,1000,950,1000,100,*,RIGHT,ALU1
-S 300,4000,300,4500,200,*,UP,ALU1
-S 2000,1000,2000,4000,200,q,DOWN,CALU1
-S 500,1500,500,3500,200,i0,DOWN,CALU1
-S 1500,1000,1500,4000,200,i1,DOWN,CALU1
-V 500,3000,CONT_POLY,*
-V 2700,1700,CONT_BODY_P,*
-V 2700,500,CONT_DIF_N,*
-V 2700,1000,CONT_DIF_N,*
-V 1500,500,CONT_DIF_N,*
-V 300,1000,CONT_DIF_N,*
-V 1400,1500,CONT_POLY,*
-V 500,1500,CONT_POLY,*
-V 2100,1000,CONT_DIF_N,*
-V 900,4700,CONT_BODY_N,*
-V 2100,3000,CONT_DIF_P,*
-V 2100,3500,CONT_DIF_P,*
-V 2100,4000,CONT_DIF_P,*
-V 2700,3500,CONT_DIF_P,*
-V 2700,3000,CONT_DIF_P,*
-V 1500,4500,CONT_DIF_P,*
-V 2700,4500,CONT_DIF_P,*
-V 2700,4000,CONT_DIF_P,*
-V 900,4000,CONT_DIF_P,*
-V 300,4500,CONT_DIF_P,*
-V 1000,2000,CONT_POLY,*
-V 1400,2500,CONT_POLY,*
-V 300,4000,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/a2_x4.sym b/alliance/share/cells/sxlib/a2_x4.sym
deleted file mode 100644
index db1efc87..00000000
Binary files a/alliance/share/cells/sxlib/a2_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/a2_x4.vbe b/alliance/share/cells/sxlib/a2_x4.vbe
deleted file mode 100644
index f6955d6e..00000000
--- a/alliance/share/cells/sxlib/a2_x4.vbe
+++ /dev/null
@@ -1,32 +0,0 @@
-ENTITY a2_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 1500;
-  CONSTANT cin_i0	 : NATURAL := 9;
-  CONSTANT cin_i1	 : NATURAL := 11;
-  CONSTANT rdown_i0_q	 : NATURAL := 810;
-  CONSTANT rdown_i1_q	 : NATURAL := 810;
-  CONSTANT rup_i0_q	 : NATURAL := 890;
-  CONSTANT rup_i1_q	 : NATURAL := 890;
-  CONSTANT tphh_i1_q	 : NATURAL := 269;
-  CONSTANT tphh_i0_q	 : NATURAL := 338;
-  CONSTANT tpll_i0_q	 : NATURAL := 476;
-  CONSTANT tpll_i1_q	 : NATURAL := 518;
-  CONSTANT transistors	 : NATURAL := 8
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END a2_x4;
-
-ARCHITECTURE behaviour_data_flow OF a2_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on a2_x4"
-  SEVERITY WARNING;
-  q <= (i0 and i1) after 1100 ps;
-END;
diff --git a/alliance/share/cells/sxlib/a2_x4.vhd b/alliance/share/cells/sxlib/a2_x4.vhd
deleted file mode 100644
index 577cea82..00000000
--- a/alliance/share/cells/sxlib/a2_x4.vhd
+++ /dev/null
@@ -1,20 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY a2_x4 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END a2_x4;
-
-ARCHITECTURE RTL OF a2_x4 IS
-BEGIN
-  q <= (i0 AND i1);
-END RTL;
diff --git a/alliance/share/cells/sxlib/a3_x2.al b/alliance/share/cells/sxlib/a3_x2.al
deleted file mode 100644
index 87820e7b..00000000
--- a/alliance/share/cells/sxlib/a3_x2.al
+++ /dev/null
@@ -1,35 +0,0 @@
-V ALLIANCE : 6
-H a3_x2,L,30/10/99
-C i0,IN,EXTERNAL,9
-C i1,IN,EXTERNAL,8
-C i2,IN,EXTERNAL,7
-C q,OUT,EXTERNAL,5
-C vdd,IN,EXTERNAL,6
-C vss,IN,EXTERNAL,4
-T P,0.35,2.9,3,8,6,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00008
-T P,0.35,2.9,6,9,3,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00007
-T P,0.35,5.9,5,3,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00006
-T P,0.35,2.9,6,7,3,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00005
-T N,0.35,2.9,3,9,1,0,0.75,0.75,7.3,7.3,1.8,3.75,tr_00004
-T N,0.35,2.9,1,8,2,0,0.75,0.75,7.3,7.3,3,3.75,tr_00003
-T N,0.35,2.9,2,7,4,0,0.75,0.75,7.3,7.3,4.2,3.75,tr_00002
-T N,0.35,2.9,4,3,5,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00001
-S 9,EXTERNAL,i0
-Q 0.00260759
-S 8,EXTERNAL,i1
-Q 0.00282737
-S 7,EXTERNAL,i2
-Q 0.00304715
-S 6,EXTERNAL,vdd
-Q 0.00350341
-S 5,EXTERNAL,q
-Q 0.00364281
-S 4,EXTERNAL,vss
-Q 0.00332715
-S 3,INTERNAL
-Q 0.00629467
-S 2,INTERNAL
-Q 0
-S 1,INTERNAL
-Q 0
-EOF
diff --git a/alliance/share/cells/sxlib/a3_x2.ap b/alliance/share/cells/sxlib/a3_x2.ap
deleted file mode 100644
index f29b2379..00000000
--- a/alliance/share/cells/sxlib/a3_x2.ap
+++ /dev/null
@@ -1,90 +0,0 @@
-V ALLIANCE : 6
-H a3_x2,P, 6/ 9/2000,100
-A 0,0,3000,5000
-R 1500,2500,ref_ref,i2_25
-R 1500,2000,ref_ref,i2_20
-R 1500,1500,ref_ref,i2_15
-R 500,1500,ref_ref,i0_15
-R 1000,1500,ref_ref,i1_15
-R 500,3500,ref_ref,i0_35
-R 500,3000,ref_ref,i0_30
-R 500,2500,ref_ref,i0_25
-R 500,2000,ref_ref,i0_20
-R 1000,3500,ref_ref,i1_35
-R 1000,3000,ref_ref,i1_30
-R 1000,2500,ref_ref,i1_25
-R 1000,2000,ref_ref,i1_20
-R 1500,3000,ref_ref,i2_30
-R 1500,3500,ref_ref,i2_35
-R 2500,2000,ref_ref,q_20
-R 2500,2500,ref_ref,q_25
-R 2500,3000,ref_ref,q_30
-R 2500,3500,ref_ref,q_35
-R 2500,4000,ref_ref,q_40
-R 2500,1500,ref_ref,q_15
-R 2500,1000,ref_ref,q_10
-S 1900,2000,2400,2000,300,*,RIGHT,POLY
-S 300,300,1100,300,300,*,RIGHT,PTIE
-S 2500,3000,2700,3000,200,*,LEFT,ALU1
-S 2500,3500,2700,3500,200,*,LEFT,ALU1
-S 1800,2600,1800,3100,100,*,UP,POLY
-S 1400,1900,1400,2600,100,*,UP,POLY
-S 1400,2600,1800,2600,100,*,RIGHT,POLY
-S 1500,1500,1500,3500,100,*,DOWN,ALU1
-S 2000,1000,2000,4000,100,*,UP,ALU1
-S 300,1000,2000,1000,100,*,RIGHT,ALU1
-S 300,800,300,1700,300,*,UP,NDIF
-S 600,600,600,1900,100,*,DOWN,NTRANS
-S 1000,600,1000,1900,100,*,DOWN,NTRANS
-S 1400,600,1400,1900,100,*,DOWN,NTRANS
-S 1000,1900,1000,3100,100,*,UP,POLY
-S 600,1900,600,3100,100,*,UP,POLY
-S 1000,3100,1200,3100,100,*,LEFT,POLY
-S 900,3300,900,4600,300,*,DOWN,PDIF
-S 1200,3100,1200,4400,100,*,UP,PTRANS
-S 300,3300,300,4200,300,*,DOWN,PDIF
-S 600,3100,600,4400,100,*,UP,PTRANS
-S 500,1500,500,3500,100,*,DOWN,ALU1
-S 1000,1500,1000,3500,100,*,DOWN,ALU1
-S 300,4000,2000,4000,100,*,RIGHT,ALU1
-S 2100,2800,2100,4700,300,*,UP,PDIF
-S 0,4700,3000,4700,600,vdd,RIGHT,CALU1
-S 0,300,3000,300,600,vss,RIGHT,CALU1
-S 2400,1400,2400,2600,100,*,UP,POLY
-S 2700,2800,2700,4700,300,*,DOWN,PDIF
-S 2400,2600,2400,4900,100,*,UP,PTRANS
-S 2400,100,2400,1400,100,*,DOWN,NTRANS
-S 2700,300,2700,1200,300,*,UP,NDIF
-S 1800,3100,1800,4400,100,*,UP,PTRANS
-S 1500,3300,1500,4200,300,*,DOWN,PDIF
-S 0,3900,3000,3900,2400,*,RIGHT,NWELL
-S 2500,950,2500,4050,200,*,DOWN,ALU1
-S 2450,4000,2700,4000,200,*,LEFT,ALU1
-S 2450,1000,2700,1000,200,*,LEFT,ALU1
-S 1500,1500,1500,3500,200,i2,DOWN,CALU1
-S 500,1500,500,3500,200,i0,DOWN,CALU1
-S 1000,1500,1000,3500,200,i1,DOWN,CALU1
-S 2500,1000,2500,4000,200,q,DOWN,CALU1
-S 2000,300,2000,1200,400,*,UP,NDIF
-S 1700,300,1700,1700,300,*,UP,NDIF
-V 1500,4700,CONT_BODY_N,*
-V 1100,300,CONT_BODY_P,*
-V 700,300,CONT_BODY_P,*
-V 300,300,CONT_BODY_P,*
-V 2000,2000,CONT_POLY,*
-V 1500,2500,CONT_POLY,*
-V 300,1000,CONT_DIF_N,*
-V 500,2000,CONT_POLY,*
-V 900,4500,CONT_DIF_P,*
-V 1000,2500,CONT_POLY,*
-V 300,4000,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 300,4700,CONT_BODY_N,*
-V 2700,3000,CONT_DIF_P,*
-V 2700,4000,CONT_DIF_P,*
-V 2700,3500,CONT_DIF_P,*
-V 2700,1000,CONT_DIF_N,*
-V 2100,4500,CONT_DIF_P,*
-V 2100,500,CONT_DIF_N,*
-V 1700,500,CONT_DIF_N,*
-EOF
diff --git a/alliance/share/cells/sxlib/a3_x2.sym b/alliance/share/cells/sxlib/a3_x2.sym
deleted file mode 100644
index 64f0ad54..00000000
Binary files a/alliance/share/cells/sxlib/a3_x2.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/a3_x2.vbe b/alliance/share/cells/sxlib/a3_x2.vbe
deleted file mode 100644
index 7a7b521b..00000000
--- a/alliance/share/cells/sxlib/a3_x2.vbe
+++ /dev/null
@@ -1,38 +0,0 @@
-ENTITY a3_x2 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 1500;
-  CONSTANT cin_i0	 : NATURAL := 10;
-  CONSTANT cin_i1	 : NATURAL := 10;
-  CONSTANT cin_i2	 : NATURAL := 10;
-  CONSTANT rdown_i0_q	 : NATURAL := 1620;
-  CONSTANT rdown_i1_q	 : NATURAL := 1620;
-  CONSTANT rdown_i2_q	 : NATURAL := 1620;
-  CONSTANT rup_i0_q	 : NATURAL := 1790;
-  CONSTANT rup_i1_q	 : NATURAL := 1790;
-  CONSTANT rup_i2_q	 : NATURAL := 1790;
-  CONSTANT tphh_i2_q	 : NATURAL := 290;
-  CONSTANT tphh_i1_q	 : NATURAL := 353;
-  CONSTANT tphh_i0_q	 : NATURAL := 395;
-  CONSTANT tpll_i0_q	 : NATURAL := 435;
-  CONSTANT tpll_i1_q	 : NATURAL := 479;
-  CONSTANT tpll_i2_q	 : NATURAL := 521;
-  CONSTANT transistors	 : NATURAL := 8
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END a3_x2;
-
-ARCHITECTURE behaviour_data_flow OF a3_x2 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on a3_x2"
-  SEVERITY WARNING;
-  q <= ((i0 and i1) and i2) after 1100 ps;
-END;
diff --git a/alliance/share/cells/sxlib/a3_x2.vhd b/alliance/share/cells/sxlib/a3_x2.vhd
deleted file mode 100644
index 08ae6662..00000000
--- a/alliance/share/cells/sxlib/a3_x2.vhd
+++ /dev/null
@@ -1,21 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY a3_x2 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END a3_x2;
-
-ARCHITECTURE RTL OF a3_x2 IS
-BEGIN
-  q <= ((i0 AND i1) AND i2);
-END RTL;
diff --git a/alliance/share/cells/sxlib/a3_x4.al b/alliance/share/cells/sxlib/a3_x4.al
deleted file mode 100644
index a0b7376e..00000000
--- a/alliance/share/cells/sxlib/a3_x4.al
+++ /dev/null
@@ -1,37 +0,0 @@
-V ALLIANCE : 6
-H a3_x4,L,30/10/99
-C i0,IN,EXTERNAL,9
-C i1,IN,EXTERNAL,8
-C i2,IN,EXTERNAL,7
-C q,OUT,EXTERNAL,3
-C vdd,IN,EXTERNAL,6
-C vss,IN,EXTERNAL,2
-T P,0.35,5.9,6,4,3,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00010
-T P,0.35,5.9,3,4,6,0,0.75,0.75,13.3,13.3,6.9,11.25,tr_00009
-T P,0.35,2.9,6,7,4,0,0.75,0.75,7.3,7.3,5.4,10.65,tr_00008
-T P,0.35,2.9,4,8,6,0,0.75,0.75,7.3,7.3,3.6,10.65,tr_00007
-T P,0.35,2.9,6,9,4,0,0.75,0.75,7.3,7.3,1.8,10.65,tr_00006
-T N,0.35,2.9,4,9,5,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00005
-T N,0.35,2.9,3,4,2,0,0.75,0.75,7.3,7.3,8.7,2.25,tr_00004
-T N,0.35,2.9,2,4,3,0,0.75,0.75,7.3,7.3,6.9,2.25,tr_00003
-T N,0.35,2.9,5,8,1,0,0.75,0.75,7.3,7.3,3,2.25,tr_00002
-T N,0.35,2.9,1,7,2,0,0.75,0.75,7.3,7.3,4.2,2.25,tr_00001
-S 9,EXTERNAL,i0
-Q 0.0028158
-S 8,EXTERNAL,i1
-Q 0.00331294
-S 7,EXTERNAL,i2
-Q 0.00325537
-S 6,EXTERNAL,vdd
-Q 0.00554878
-S 5,INTERNAL
-Q 0
-S 4,INTERNAL
-Q 0.00773401
-S 3,EXTERNAL,q
-Q 0.00264397
-S 2,EXTERNAL,vss
-Q 0.00484372
-S 1,INTERNAL
-Q 0
-EOF
diff --git a/alliance/share/cells/sxlib/a3_x4.ap b/alliance/share/cells/sxlib/a3_x4.ap
deleted file mode 100644
index 2f1c1791..00000000
--- a/alliance/share/cells/sxlib/a3_x4.ap
+++ /dev/null
@@ -1,96 +0,0 @@
-V ALLIANCE : 6
-H a3_x4,P,30/ 8/2000,100
-A 0,0,3500,5000
-R 2500,1500,ref_ref,q_15
-R 500,3500,ref_ref,i0_35
-R 500,3000,ref_ref,i0_30
-R 500,2500,ref_ref,i0_25
-R 500,2000,ref_ref,i0_20
-R 500,1500,ref_ref,i0_15
-R 1000,3500,ref_ref,i1_35
-R 1000,3000,ref_ref,i1_30
-R 1000,2500,ref_ref,i1_25
-R 1000,2000,ref_ref,i1_20
-R 1000,1500,ref_ref,i1_15
-R 1500,1500,ref_ref,i2_15
-R 1500,2000,ref_ref,i2_20
-R 1500,2500,ref_ref,i2_25
-R 1500,3000,ref_ref,i2_30
-R 1500,3500,ref_ref,i2_35
-R 2500,4000,ref_ref,q_40
-R 2500,3500,ref_ref,q_35
-R 2500,3000,ref_ref,q_30
-R 2500,2500,ref_ref,q_25
-R 2500,2000,ref_ref,q_20
-R 2500,1000,ref_ref,q_10
-S 2000,4500,2000,4700,300,*,UP,PDIF
-S 0,300,3500,300,600,vss,RIGHT,CALU1
-S 600,100,600,1400,100,*,DOWN,NTRANS
-S 300,300,300,1200,300,*,UP,NDIF
-S 3200,300,3200,1200,300,*,UP,NDIF
-S 2900,100,2900,1400,100,*,DOWN,NTRANS
-S 2600,300,2600,1200,300,*,UP,NDIF
-S 2300,100,2300,1400,100,*,DOWN,NTRANS
-S 0,4700,3500,4700,600,vdd,RIGHT,CALU1
-S 3200,2800,3200,4700,300,*,DOWN,PDIF
-S 2900,2600,2900,4900,100,*,UP,PTRANS
-S 2600,2800,2600,4700,300,*,DOWN,PDIF
-S 2300,2600,2300,4900,100,*,UP,PTRANS
-S 2900,1400,2900,2600,100,*,UP,POLY
-S 2300,1400,2300,2600,100,*,UP,POLY
-S 500,1500,500,3500,100,*,DOWN,ALU1
-S 1000,1500,1000,3500,100,*,DOWN,ALU1
-S 1500,1500,1500,3500,100,*,DOWN,ALU1
-S 1800,2900,1800,4200,100,*,UP,PTRANS
-S 300,1000,2000,1000,100,*,RIGHT,ALU1
-S 2000,1000,2000,4000,100,*,UP,ALU1
-S 300,4000,2000,4000,100,*,RIGHT,ALU1
-S 1000,2500,1200,2500,300,*,RIGHT,POLY
-S 1000,100,1000,1400,100,*,DOWN,NTRANS
-S 1400,100,1400,1400,100,*,DOWN,NTRANS
-S 1000,1400,1000,2600,100,*,UP,POLY
-S 1400,1400,1400,2100,100,*,UP,POLY
-S 1600,2900,1800,2900,100,*,RIGHT,POLY
-S 1600,1900,1600,2900,100,*,DOWN,POLY
-S 1900,2000,2900,2000,300,*,RIGHT,POLY
-S 2100,2800,2100,4700,300,*,UP,PDIF
-S 300,3100,300,4000,300,*,DOWN,PDIF
-S 1200,2900,1200,4200,100,*,UP,PTRANS
-S 600,2900,600,4200,100,*,UP,PTRANS
-S 1500,3100,1500,4000,300,*,DOWN,PDIF
-S 900,3100,900,4600,300,*,DOWN,PDIF
-S 1900,300,1900,1200,300,*,UP,NDIF
-S 1700,300,1700,1200,300,*,UP,NDIF
-S 3200,3000,3200,4500,200,*,DOWN,ALU1
-S 3200,500,3200,1700,200,*,DOWN,ALU1
-S 1200,2400,1200,2900,100,*,DOWN,POLY
-S 600,1400,600,2900,100,*,UP,POLY
-S 0,3900,3500,3900,2400,*,RIGHT,NWELL
-S 2500,950,2500,4050,200,*,DOWN,ALU1
-S 2500,1000,2500,4000,200,q,DOWN,CALU1
-S 500,1500,500,3500,200,i0,DOWN,CALU1
-S 1000,1500,1000,3500,200,i1,DOWN,CALU1
-S 1500,1500,1500,3500,200,i2,DOWN,CALU1
-V 2000,4600,CONT_DIF_P,*
-V 300,1000,CONT_DIF_N,*
-V 500,1500,CONT_POLY,*
-V 3200,500,CONT_DIF_N,*
-V 3200,1000,CONT_DIF_N,*
-V 2000,500,CONT_DIF_N,*
-V 2600,1000,CONT_DIF_N,*
-V 2600,3000,CONT_DIF_P,*
-V 2600,4000,CONT_DIF_P,*
-V 3200,4000,CONT_DIF_P,*
-V 3200,3000,CONT_DIF_P,*
-V 3200,3500,CONT_DIF_P,*
-V 3200,4500,CONT_DIF_P,*
-V 2600,3500,CONT_DIF_P,*
-V 3200,1700,CONT_BODY_P,*
-V 900,4500,CONT_DIF_P,*
-V 1000,2500,CONT_POLY,*
-V 1500,2000,CONT_POLY,*
-V 2000,2000,CONT_POLY,*
-V 300,4000,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 300,4700,CONT_BODY_N,*
-EOF
diff --git a/alliance/share/cells/sxlib/a3_x4.sym b/alliance/share/cells/sxlib/a3_x4.sym
deleted file mode 100644
index 3f536421..00000000
Binary files a/alliance/share/cells/sxlib/a3_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/a3_x4.vbe b/alliance/share/cells/sxlib/a3_x4.vbe
deleted file mode 100644
index 556b6b0f..00000000
--- a/alliance/share/cells/sxlib/a3_x4.vbe
+++ /dev/null
@@ -1,38 +0,0 @@
-ENTITY a3_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 1750;
-  CONSTANT cin_i0	 : NATURAL := 10;
-  CONSTANT cin_i1	 : NATURAL := 11;
-  CONSTANT cin_i2	 : NATURAL := 11;
-  CONSTANT rdown_i0_q	 : NATURAL := 810;
-  CONSTANT rdown_i1_q	 : NATURAL := 810;
-  CONSTANT rdown_i2_q	 : NATURAL := 810;
-  CONSTANT rup_i0_q	 : NATURAL := 890;
-  CONSTANT rup_i1_q	 : NATURAL := 890;
-  CONSTANT rup_i2_q	 : NATURAL := 890;
-  CONSTANT tphh_i2_q	 : NATURAL := 356;
-  CONSTANT tphh_i1_q	 : NATURAL := 428;
-  CONSTANT tphh_i0_q	 : NATURAL := 478;
-  CONSTANT tpll_i0_q	 : NATURAL := 514;
-  CONSTANT tpll_i1_q	 : NATURAL := 554;
-  CONSTANT tpll_i2_q	 : NATURAL := 592;
-  CONSTANT transistors	 : NATURAL := 10
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END a3_x4;
-
-ARCHITECTURE behaviour_data_flow OF a3_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on a3_x4"
-  SEVERITY WARNING;
-  q <= ((i0 and i1) and i2) after 1200 ps;
-END;
diff --git a/alliance/share/cells/sxlib/a3_x4.vhd b/alliance/share/cells/sxlib/a3_x4.vhd
deleted file mode 100644
index 751f7ee5..00000000
--- a/alliance/share/cells/sxlib/a3_x4.vhd
+++ /dev/null
@@ -1,21 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY a3_x4 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END a3_x4;
-
-ARCHITECTURE RTL OF a3_x4 IS
-BEGIN
-  q <= ((i0 AND i1) AND i2);
-END RTL;
diff --git a/alliance/share/cells/sxlib/a4_x2.al b/alliance/share/cells/sxlib/a4_x2.al
deleted file mode 100644
index bd8536a8..00000000
--- a/alliance/share/cells/sxlib/a4_x2.al
+++ /dev/null
@@ -1,42 +0,0 @@
-V ALLIANCE : 6
-H a4_x2,L,30/10/99
-C i0,IN,EXTERNAL,10
-C i1,IN,EXTERNAL,9
-C i2,IN,EXTERNAL,8
-C i3,IN,EXTERNAL,7
-C q,OUT,EXTERNAL,11
-C vdd,IN,EXTERNAL,6
-C vss,IN,EXTERNAL,2
-T P,0.35,5.9,11,1,6,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00010
-T P,0.35,2.9,1,10,6,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00009
-T P,0.35,2.9,6,9,1,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00008
-T P,0.35,2.9,1,8,6,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00007
-T P,0.35,2.9,6,7,1,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00006
-T N,0.35,2.9,4,8,5,0,0.75,0.75,7.3,7.3,4.2,3.75,tr_00005
-T N,0.35,2.9,2,10,3,0,0.75,0.75,7.3,7.3,1.8,3.75,tr_00004
-T N,0.35,2.9,5,7,1,0,0.75,0.75,7.3,7.3,5.4,3.75,tr_00003
-T N,0.35,2.9,3,9,4,0,0.75,0.75,7.3,7.3,3,3.75,tr_00002
-T N,0.35,2.9,2,1,11,0,0.75,0.75,7.3,7.3,8.7,2.25,tr_00001
-S 11,EXTERNAL,q
-Q 0.00364281
-S 10,EXTERNAL,i0
-Q 0.00288944
-S 9,EXTERNAL,i1
-Q 0.00310922
-S 8,EXTERNAL,i2
-Q 0.00332901
-S 7,EXTERNAL,i3
-Q 0.00318596
-S 6,EXTERNAL,vdd
-Q 0.0046087
-S 5,INTERNAL
-Q 0
-S 4,INTERNAL
-Q 0
-S 3,INTERNAL
-Q 0
-S 2,EXTERNAL,vss
-Q 0.00402115
-S 1,INTERNAL
-Q 0.00564944
-EOF
diff --git a/alliance/share/cells/sxlib/a4_x2.ap b/alliance/share/cells/sxlib/a4_x2.ap
deleted file mode 100644
index cecffc5a..00000000
--- a/alliance/share/cells/sxlib/a4_x2.ap
+++ /dev/null
@@ -1,107 +0,0 @@
-V ALLIANCE : 6
-H a4_x2,P,30/ 8/2000,100
-A 0,0,3500,5000
-R 500,1500,ref_ref,i0_15
-R 500,2000,ref_ref,i0_20
-R 500,2500,ref_ref,i0_25
-R 500,3000,ref_ref,i0_30
-R 500,3500,ref_ref,i0_35
-R 1500,2500,ref_ref,i2_25
-R 1000,3000,ref_ref,i1_30
-R 2000,1500,ref_ref,i3_15
-R 2000,2000,ref_ref,i3_20
-R 2000,2500,ref_ref,i3_25
-R 2000,3000,ref_ref,i3_30
-R 2000,3500,ref_ref,i3_35
-R 1500,3500,ref_ref,i2_35
-R 1500,3000,ref_ref,i2_30
-R 1000,3500,ref_ref,i1_35
-R 1500,2000,ref_ref,i2_20
-R 1500,1500,ref_ref,i2_15
-R 1000,1500,ref_ref,i1_15
-R 1000,2000,ref_ref,i1_20
-R 1000,2500,ref_ref,i1_25
-R 3000,4000,ref_ref,q_40
-R 3000,3500,ref_ref,q_35
-R 3000,3000,ref_ref,q_30
-R 3000,2500,ref_ref,q_25
-R 3000,2000,ref_ref,q_20
-R 3000,1500,ref_ref,q_15
-R 3000,1000,ref_ref,q_10
-R 500,1000,ref_ref,i0_10
-R 1000,1000,ref_ref,i1_10
-R 1500,1000,ref_ref,i2_10
-S 300,4000,300,4500,200,*,UP,ALU1
-S 2950,4000,3200,4000,200,*,RIGHT,ALU1
-S 2950,1000,3200,1000,200,*,LEFT,ALU1
-S 3000,950,3000,4050,200,*,DOWN,ALU1
-S 900,4000,2550,4000,100,*,RIGHT,ALU1
-S 2100,1000,2550,1000,100,*,RIGHT,ALU1
-S 2550,1000,2550,4000,100,*,DOWN,ALU1
-S 0,3900,3500,3900,2400,*,RIGHT,NWELL
-S 900,3300,900,4200,300,*,DOWN,PDIF
-S 2400,3100,2400,4400,100,*,UP,PTRANS
-S 1800,3100,1800,4400,100,*,UP,PTRANS
-S 1500,3300,1500,4600,300,*,DOWN,PDIF
-S 2700,2800,2700,4700,300,*,DOWN,PDIF
-S 2100,3300,2100,4200,300,*,DOWN,PDIF
-S 1200,3100,1200,4400,100,*,UP,PTRANS
-S 600,3100,600,4400,100,*,UP,PTRANS
-S 300,3300,300,4600,300,*,DOWN,PDIF
-S 2000,1500,2000,3500,100,*,DOWN,ALU1
-S 1000,3100,1200,3100,100,*,RIGHT,POLY
-S 1600,3100,1800,3100,100,*,RIGHT,POLY
-S 2100,3100,2400,3100,100,*,LEFT,POLY
-S 2900,2600,2900,4900,100,*,UP,PTRANS
-S 3200,2800,3200,4700,300,*,DOWN,PDIF
-S 2900,1400,2900,2600,100,*,UP,POLY
-S 2900,100,2900,1400,100,*,DOWN,NTRANS
-S 2700,300,2700,1200,300,*,DOWN,NDIF
-S 0,4700,3500,4700,600,vdd,RIGHT,CALU1
-S 2400,2500,2900,2500,300,*,RIGHT,POLY
-S 3200,300,3200,1200,300,*,UP,NDIF
-S 0,300,3500,300,600,vss,RIGHT,CALU1
-S 1800,1900,2100,1900,100,*,RIGHT,POLY
-S 1600,2400,1600,3100,100,*,UP,POLY
-S 2100,1900,2100,3100,100,*,DOWN,POLY
-S 1400,1900,1400,2600,100,*,UP,POLY
-S 1000,1900,1000,3100,100,*,UP,POLY
-S 600,1900,600,3100,100,*,DOWN,POLY
-S 1000,600,1000,1900,100,*,DOWN,NTRANS
-S 1800,600,1800,1900,100,*,DOWN,NTRANS
-S 600,600,600,1900,100,*,DOWN,NTRANS
-S 1400,600,1400,1900,100,*,DOWN,NTRANS
-S 300,400,300,1700,300,*,UP,NDIF
-S 2000,800,2000,1700,300,*,UP,NDIF
-S 500,1000,500,3500,100,*,DOWN,ALU1
-S 1000,1000,1000,3500,100,*,DOWN,ALU1
-S 1500,1000,1500,3500,100,*,DOWN,ALU1
-S 3000,3500,3200,3500,200,*,RIGHT,ALU1
-S 3000,3000,3200,3000,200,*,RIGHT,ALU1
-S 500,1000,500,3500,200,i0,DOWN,CALU1
-S 1500,1000,1500,3500,200,i2,DOWN,CALU1
-S 1000,1000,1000,3500,200,i1,DOWN,CALU1
-S 2000,1500,2000,3500,200,i3,DOWN,CALU1
-S 3000,1000,3000,4000,200,q,DOWN,CALU1
-V 300,4000,CONT_DIF_P,*
-V 900,4700,CONT_BODY_N,*
-V 900,4000,CONT_DIF_P,*
-V 2100,4000,CONT_DIF_P,*
-V 1500,4500,CONT_DIF_P,*
-V 300,4500,CONT_DIF_P,*
-V 300,500,CONT_DIF_N,*
-V 1000,2500,CONT_POLY,*
-V 2600,4700,CONT_DIF_P,*
-V 2500,2500,CONT_POLY,*
-V 3200,4000,CONT_DIF_P,*
-V 3200,3500,CONT_DIF_P,*
-V 3200,3000,CONT_DIF_P,*
-V 3200,1000,CONT_DIF_N,*
-V 2100,1000,CONT_DIF_N,*
-V 2600,400,CONT_DIF_N,*
-V 2000,2000,CONT_POLY,*
-V 500,2500,CONT_POLY,*
-V 1500,2500,CONT_POLY,*
-V 1000,300,CONT_BODY_P,*
-V 1800,300,CONT_BODY_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/a4_x2.sym b/alliance/share/cells/sxlib/a4_x2.sym
deleted file mode 100644
index 716d5421..00000000
Binary files a/alliance/share/cells/sxlib/a4_x2.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/a4_x2.vbe b/alliance/share/cells/sxlib/a4_x2.vbe
deleted file mode 100644
index 3a635396..00000000
--- a/alliance/share/cells/sxlib/a4_x2.vbe
+++ /dev/null
@@ -1,44 +0,0 @@
-ENTITY a4_x2 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 1750;
-  CONSTANT cin_i0	 : NATURAL := 10;
-  CONSTANT cin_i1	 : NATURAL := 10;
-  CONSTANT cin_i2	 : NATURAL := 11;
-  CONSTANT cin_i3	 : NATURAL := 10;
-  CONSTANT rdown_i0_q	 : NATURAL := 1620;
-  CONSTANT rdown_i1_q	 : NATURAL := 1620;
-  CONSTANT rdown_i2_q	 : NATURAL := 1620;
-  CONSTANT rdown_i3_q	 : NATURAL := 1620;
-  CONSTANT rup_i0_q	 : NATURAL := 1790;
-  CONSTANT rup_i1_q	 : NATURAL := 1790;
-  CONSTANT rup_i2_q	 : NATURAL := 1790;
-  CONSTANT rup_i3_q	 : NATURAL := 1790;
-  CONSTANT tphh_i0_q	 : NATURAL := 374;
-  CONSTANT tphh_i1_q	 : NATURAL := 441;
-  CONSTANT tpll_i3_q	 : NATURAL := 455;
-  CONSTANT tphh_i2_q	 : NATURAL := 482;
-  CONSTANT tpll_i2_q	 : NATURAL := 498;
-  CONSTANT tphh_i3_q	 : NATURAL := 506;
-  CONSTANT tpll_i1_q	 : NATURAL := 539;
-  CONSTANT tpll_i0_q	 : NATURAL := 578;
-  CONSTANT transistors	 : NATURAL := 10
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  i3	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END a4_x2;
-
-ARCHITECTURE behaviour_data_flow OF a4_x2 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on a4_x2"
-  SEVERITY WARNING;
-  q <= (((i0 and i1) and i2) and i3) after 1200 ps;
-END;
diff --git a/alliance/share/cells/sxlib/a4_x2.vhd b/alliance/share/cells/sxlib/a4_x2.vhd
deleted file mode 100644
index 5819d66a..00000000
--- a/alliance/share/cells/sxlib/a4_x2.vhd
+++ /dev/null
@@ -1,22 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY a4_x2 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  i3	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END a4_x2;
-
-ARCHITECTURE RTL OF a4_x2 IS
-BEGIN
-  q <= (((i0 AND i1) AND i2) AND i3);
-END RTL;
diff --git a/alliance/share/cells/sxlib/a4_x4.al b/alliance/share/cells/sxlib/a4_x4.al
deleted file mode 100644
index 7ce75993..00000000
--- a/alliance/share/cells/sxlib/a4_x4.al
+++ /dev/null
@@ -1,45 +0,0 @@
-V ALLIANCE : 6
-H a4_x4,L,30/10/99
-C i0,IN,EXTERNAL,10
-C i1,IN,EXTERNAL,9
-C i2,IN,EXTERNAL,8
-C i3,IN,EXTERNAL,7
-C q,OUT,EXTERNAL,11
-C vdd,IN,EXTERNAL,6
-C vss,IN,EXTERNAL,5
-T P,0.35,5.9,11,3,6,0,0.75,0.75,13.3,13.3,10.2,11.25,tr_00013
-T P,0.35,5.9,11,3,6,0,0.75,0.75,13.3,13.3,8.4,11.25,tr_00012
-T P,0.35,2.9,6,7,3,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00011
-T P,0.35,2.9,3,8,6,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00010
-T P,0.35,2.9,6,9,3,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00009
-T P,0.35,2.9,3,10,6,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00008
-T N,0.35,2.9,11,3,5,0,0.75,0.75,7.3,7.3,10.2,2.25,tr_00007
-T N,0.35,2.9,11,3,5,0,0.75,0.75,7.3,7.3,10.2,2.25,tr_00006
-T N,0.35,2.9,5,3,11,0,0.75,0.75,7.3,7.3,8.4,2.25,tr_00005
-T N,0.35,2.9,1,9,4,0,0.75,0.75,7.3,7.3,3,3.75,tr_00004
-T N,0.35,2.9,2,7,3,0,0.75,0.75,7.3,7.3,5.4,3.75,tr_00003
-T N,0.35,2.9,5,10,1,0,0.75,0.75,7.3,7.3,1.8,3.75,tr_00002
-T N,0.35,2.9,4,8,2,0,0.75,0.75,7.3,7.3,4.2,3.75,tr_00001
-S 11,EXTERNAL,q
-Q 0.00264397
-S 10,EXTERNAL,i0
-Q 0.00288944
-S 9,EXTERNAL,i1
-Q 0.00310922
-S 8,EXTERNAL,i2
-Q 0.00332901
-S 7,EXTERNAL,i3
-Q 0.00318597
-S 6,EXTERNAL,vdd
-Q 0.00665407
-S 5,EXTERNAL,vss
-Q 0.00571399
-S 4,INTERNAL
-Q 0
-S 3,INTERNAL
-Q 0.0070012
-S 2,INTERNAL
-Q 0
-S 1,INTERNAL
-Q 0
-EOF
diff --git a/alliance/share/cells/sxlib/a4_x4.ap b/alliance/share/cells/sxlib/a4_x4.ap
deleted file mode 100644
index 08860dfc..00000000
--- a/alliance/share/cells/sxlib/a4_x4.ap
+++ /dev/null
@@ -1,116 +0,0 @@
-V ALLIANCE : 6
-H a4_x4,P,30/ 8/2000,100
-A 0,0,4000,5000
-R 1500,1000,ref_ref,i2_10
-R 1000,1000,ref_ref,i1_10
-R 500,1000,ref_ref,i0_10
-R 3000,1000,ref_ref,q_10
-R 3000,1500,ref_ref,q_15
-R 3000,2000,ref_ref,q_20
-R 3000,2500,ref_ref,q_25
-R 3000,3000,ref_ref,q_30
-R 3000,3500,ref_ref,q_35
-R 3000,4000,ref_ref,q_40
-R 1000,2500,ref_ref,i1_25
-R 1000,2000,ref_ref,i1_20
-R 1000,1500,ref_ref,i1_15
-R 1500,1500,ref_ref,i2_15
-R 1500,2000,ref_ref,i2_20
-R 1000,3500,ref_ref,i1_35
-R 1500,3000,ref_ref,i2_30
-R 1500,3500,ref_ref,i2_35
-R 2000,3500,ref_ref,i3_35
-R 2000,3000,ref_ref,i3_30
-R 2000,2500,ref_ref,i3_25
-R 2000,2000,ref_ref,i3_20
-R 2000,1500,ref_ref,i3_15
-R 1000,3000,ref_ref,i1_30
-R 1500,2500,ref_ref,i2_25
-R 500,3500,ref_ref,i0_35
-R 500,3000,ref_ref,i0_30
-R 500,2500,ref_ref,i0_25
-R 500,2000,ref_ref,i0_20
-R 500,1500,ref_ref,i0_15
-S 3000,1000,3000,4000,200,q,DOWN,CALU1
-S 2000,1500,2000,3500,200,i3,DOWN,CALU1
-S 1000,1000,1000,3500,200,i1,DOWN,CALU1
-S 1500,1000,1500,3500,200,i2,DOWN,CALU1
-S 500,1000,500,3500,200,i0,DOWN,CALU1
-S 300,4000,300,4500,200,*,UP,ALU1
-S 3000,950,3000,4050,200,*,DOWN,ALU1
-S 0,4700,4000,4700,600,vdd,RIGHT,CALU1
-S 2000,900,2000,1700,300,*,UP,NDIF
-S 2550,1000,2550,4000,100,*,DOWN,ALU1
-S 900,4000,2550,4000,100,*,RIGHT,ALU1
-S 2100,1000,2550,1000,100,*,RIGHT,ALU1
-S 0,3900,4000,3900,2400,*,RIGHT,NWELL
-S 1500,1000,1500,3500,100,*,DOWN,ALU1
-S 1000,1000,1000,3500,100,*,DOWN,ALU1
-S 500,1000,500,3500,100,*,DOWN,ALU1
-S 300,400,300,1700,300,*,UP,NDIF
-S 1400,600,1400,1900,100,*,DOWN,NTRANS
-S 600,600,600,1900,100,*,DOWN,NTRANS
-S 1800,600,1800,1900,100,*,DOWN,NTRANS
-S 1000,600,1000,1900,100,*,DOWN,NTRANS
-S 600,1900,600,3100,100,*,DOWN,POLY
-S 1000,1900,1000,3100,100,*,UP,POLY
-S 1400,1900,1400,2600,100,*,UP,POLY
-S 2100,1900,2100,3100,100,*,DOWN,POLY
-S 1600,2400,1600,3100,100,*,UP,POLY
-S 1800,1900,2100,1900,100,*,RIGHT,POLY
-S 3200,300,3200,1200,300,*,UP,NDIF
-S 3200,2800,3200,4700,300,*,DOWN,PDIF
-S 1000,3100,1200,3100,100,*,RIGHT,POLY
-S 2000,1500,2000,3500,100,*,DOWN,ALU1
-S 300,3300,300,4600,300,*,DOWN,PDIF
-S 600,3100,600,4400,100,*,UP,PTRANS
-S 1200,3100,1200,4400,100,*,UP,PTRANS
-S 2100,3300,2100,4200,300,*,DOWN,PDIF
-S 900,3300,900,4200,300,*,DOWN,PDIF
-S 0,300,4000,300,600,vss,RIGHT,CALU1
-S 2800,100,2800,1400,100,*,DOWN,NTRANS
-S 2800,1400,2800,2600,100,*,UP,POLY
-S 3400,100,3400,1400,100,*,DOWN,NTRANS
-S 2800,2600,2800,4900,100,*,UP,PTRANS
-S 3400,2600,3400,4900,100,*,DOWN,PTRANS
-S 3700,2800,3700,4700,300,*,UP,PDIF
-S 3700,300,3700,1200,300,*,DOWN,NDIF
-S 3700,3000,3700,4500,200,*,UP,ALU1
-S 3400,1400,3400,2600,100,*,DOWN,POLY
-S 2400,2500,3400,2500,300,*,RIGHT,POLY
-S 3700,500,3700,1700,200,*,DOWN,ALU1
-S 1450,3300,1450,4600,200,*,DOWN,PDIF
-S 1700,3100,1700,4400,100,*,UP,PTRANS
-S 2300,3100,2300,4400,100,*,UP,PTRANS
-S 2100,3100,2300,3100,100,*,LEFT,POLY
-S 1600,3100,1700,3100,100,*,RIGHT,POLY
-S 2550,2800,2550,4700,200,*,DOWN,PDIF
-V 300,4000,CONT_DIF_P,*
-V 1800,300,CONT_BODY_P,*
-V 1000,300,CONT_BODY_P,*
-V 1500,2500,CONT_POLY,*
-V 500,2500,CONT_POLY,*
-V 2000,2000,CONT_POLY,*
-V 2100,1000,CONT_DIF_N,*
-V 2500,2500,CONT_POLY,*
-V 1000,2500,CONT_POLY,*
-V 300,500,CONT_DIF_N,*
-V 300,4500,CONT_DIF_P,*
-V 900,4000,CONT_DIF_P,*
-V 900,4700,CONT_BODY_N,*
-V 2500,400,CONT_DIF_N,*
-V 3100,1000,CONT_DIF_N,*
-V 3100,4000,CONT_DIF_P,*
-V 3100,3000,CONT_DIF_P,*
-V 3100,3500,CONT_DIF_P,*
-V 2500,4700,CONT_DIF_P,*
-V 3700,1000,CONT_DIF_N,*
-V 3700,500,CONT_DIF_N,*
-V 3700,4500,CONT_DIF_P,*
-V 3700,4000,CONT_DIF_P,*
-V 3700,3500,CONT_DIF_P,*
-V 3700,3000,CONT_DIF_P,*
-V 3700,1700,CONT_BODY_P,*
-V 1500,4700,CONT_DIF_P,*
-V 2000,4000,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/a4_x4.sym b/alliance/share/cells/sxlib/a4_x4.sym
deleted file mode 100644
index d6f59e2b..00000000
Binary files a/alliance/share/cells/sxlib/a4_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/a4_x4.vbe b/alliance/share/cells/sxlib/a4_x4.vbe
deleted file mode 100644
index 4f96afa4..00000000
--- a/alliance/share/cells/sxlib/a4_x4.vbe
+++ /dev/null
@@ -1,44 +0,0 @@
-ENTITY a4_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 2000;
-  CONSTANT cin_i0	 : NATURAL := 10;
-  CONSTANT cin_i1	 : NATURAL := 10;
-  CONSTANT cin_i2	 : NATURAL := 11;
-  CONSTANT cin_i3	 : NATURAL := 10;
-  CONSTANT rdown_i0_q	 : NATURAL := 540;
-  CONSTANT rdown_i1_q	 : NATURAL := 540;
-  CONSTANT rdown_i2_q	 : NATURAL := 540;
-  CONSTANT rdown_i3_q	 : NATURAL := 540;
-  CONSTANT rup_i0_q	 : NATURAL := 890;
-  CONSTANT rup_i1_q	 : NATURAL := 890;
-  CONSTANT rup_i2_q	 : NATURAL := 890;
-  CONSTANT rup_i3_q	 : NATURAL := 890;
-  CONSTANT tphh_i0_q	 : NATURAL := 505;
-  CONSTANT tpll_i3_q	 : NATURAL := 538;
-  CONSTANT tpll_i2_q	 : NATURAL := 576;
-  CONSTANT tphh_i1_q	 : NATURAL := 578;
-  CONSTANT tpll_i1_q	 : NATURAL := 614;
-  CONSTANT tphh_i2_q	 : NATURAL := 627;
-  CONSTANT tpll_i0_q	 : NATURAL := 650;
-  CONSTANT tphh_i3_q	 : NATURAL := 661;
-  CONSTANT transistors	 : NATURAL := 13
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  i3	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END a4_x4;
-
-ARCHITECTURE behaviour_data_flow OF a4_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on a4_x4"
-  SEVERITY WARNING;
-  q <= (((i0 and i1) and i2) and i3) after 1300 ps;
-END;
diff --git a/alliance/share/cells/sxlib/a4_x4.vhd b/alliance/share/cells/sxlib/a4_x4.vhd
deleted file mode 100644
index 93ffcf82..00000000
--- a/alliance/share/cells/sxlib/a4_x4.vhd
+++ /dev/null
@@ -1,22 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY a4_x4 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  i3	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END a4_x4;
-
-ARCHITECTURE RTL OF a4_x4 IS
-BEGIN
-  q <= (((i0 AND i1) AND i2) AND i3);
-END RTL;
diff --git a/alliance/share/cells/sxlib/an12_x1.al b/alliance/share/cells/sxlib/an12_x1.al
deleted file mode 100644
index fd469213..00000000
--- a/alliance/share/cells/sxlib/an12_x1.al
+++ /dev/null
@@ -1,28 +0,0 @@
-V ALLIANCE : 6
-H an12_x1,L,30/10/99
-C i0,IN,EXTERNAL,7
-C i1,IN,EXTERNAL,6
-C q,OUT,EXTERNAL,1
-C vdd,IN,EXTERNAL,5
-C vss,IN,EXTERNAL,2
-T P,0.35,5.9,4,7,1,0,0.75,0.75,13.3,13.3,2.7,11.25,tr_00006
-T P,0.35,5.9,5,3,4,0,0.75,0.75,13.3,13.3,3.9,11.25,tr_00005
-T P,0.35,2.9,3,6,5,0,0.75,0.75,7.3,7.3,5.7,9.75,tr_00004
-T N,0.35,1.4,2,7,1,0,0.75,0.75,4.3,4.3,2.1,3,tr_00003
-T N,0.35,1.4,1,3,2,0,0.75,0.75,4.3,4.3,3.9,3,tr_00002
-T N,0.35,1.4,2,6,3,0,0.75,0.75,4.3,4.3,5.7,3,tr_00001
-S 7,EXTERNAL,i0
-Q 0.00319019
-S 6,EXTERNAL,i1
-Q 0.00362068
-S 5,EXTERNAL,vdd
-Q 0.00298567
-S 4,INTERNAL
-Q 0
-S 3,INTERNAL
-Q 0.00417012
-S 2,EXTERNAL,vss
-Q 0.00351447
-S 1,EXTERNAL,q
-Q 0.00384845
-EOF
diff --git a/alliance/share/cells/sxlib/an12_x1.ap b/alliance/share/cells/sxlib/an12_x1.ap
deleted file mode 100644
index c77449fb..00000000
--- a/alliance/share/cells/sxlib/an12_x1.ap
+++ /dev/null
@@ -1,84 +0,0 @@
-V ALLIANCE : 6
-H an12_x1,P, 6/ 9/2000,100
-A 0,0,2500,5000
-R 1500,1000,ref_ref,i1_10
-R 500,1000,ref_ref,q_10
-R 1000,4000,ref_ref,i0_40
-R 1000,3500,ref_ref,i0_35
-R 1000,3000,ref_ref,i0_30
-R 1000,2500,ref_ref,i0_25
-R 500,4000,ref_ref,q_40
-R 500,3500,ref_ref,q_35
-R 1500,2500,ref_ref,i1_25
-R 1500,3000,ref_ref,i1_30
-R 1500,3500,ref_ref,i1_35
-R 1500,4000,ref_ref,i1_40
-R 500,3000,ref_ref,q_30
-R 500,2500,ref_ref,q_25
-R 500,1500,ref_ref,q_15
-R 1000,2000,ref_ref,i0_20
-R 1000,1500,ref_ref,i0_15
-R 1500,1500,ref_ref,i1_15
-R 1500,2000,ref_ref,i1_20
-S 700,2000,900,2000,300,*,LEFT,POLY
-S 1700,1500,1900,1500,300,*,RIGHT,POLY
-S 1700,2500,1900,2500,300,*,RIGHT,POLY
-S 500,1000,500,1550,200,*,DOWN,ALU1
-S 250,2500,400,2500,200,*,LEFT,ALU1
-S 250,1500,500,1500,200,*,RIGHT,ALU1
-S 300,1450,300,2550,200,*,DOWN,ALU1
-S 900,2000,900,2600,100,*,UP,POLY
-S 700,2000,900,2000,100,*,RIGHT,POLY
-S 700,1400,700,2000,100,*,UP,POLY
-S 1900,2400,1900,2600,100,*,UP,POLY
-S 1900,1400,1900,1600,100,*,UP,POLY
-S 1500,1500,1700,1500,200,*,LEFT,ALU1
-S 1500,2500,1700,2500,200,*,LEFT,ALU1
-S 2200,1000,2200,3500,100,*,UP,ALU1
-S 1300,2000,2200,2000,100,*,RIGHT,POLY
-S 2200,2800,2200,3700,300,*,UP,PDIF
-S 2200,800,2200,1200,300,*,DOWN,NDIF
-S 1300,2050,1300,2600,100,*,DOWN,POLY
-S 400,2800,400,4200,300,*,DOWN,PDIF
-S 1900,2600,1900,3900,100,*,UP,PTRANS
-S 600,2800,600,4200,300,*,DOWN,PDIF
-S 1300,2600,1300,4900,100,*,UP,PTRANS
-S 1600,2800,1600,4700,300,*,UP,PDIF
-S 900,2600,900,4900,100,*,UP,PTRANS
-S 1900,600,1900,1400,100,*,DOWN,NTRANS
-S 1300,600,1300,1400,100,*,DOWN,NTRANS
-S 1600,400,1600,1200,300,*,UP,NDIF
-S 400,400,400,1200,300,*,UP,NDIF
-S 700,600,700,1400,100,*,DOWN,NTRANS
-S 1000,800,1000,1200,300,*,UP,NDIF
-S 1300,1400,1300,2000,100,*,UP,POLY
-S 450,1000,1000,1000,200,*,LEFT,ALU1
-S 1500,1000,1500,4000,100,*,UP,ALU1
-S 1000,1500,1000,4000,100,*,UP,ALU1
-S 0,3900,2500,3900,2400,*,RIGHT,NWELL
-S 0,300,2500,300,600,vss,RIGHT,CALU1
-S 0,4700,2500,4700,600,vdd,RIGHT,CALU1
-S 1500,1000,1500,4000,200,i1,DOWN,CALU1
-S 1000,1500,1000,4000,200,i0,DOWN,CALU1
-S 500,2500,500,4000,200,q,DOWN,CALU1
-S 500,1000,500,1500,200,q,DOWN,CALU1
-S 500,2450,500,4000,200,*,DOWN,ALU1
-V 900,2000,CONT_POLY,*
-V 1000,300,CONT_BODY_P,*
-V 2200,300,CONT_BODY_P,*
-V 1700,1500,CONT_POLY,*
-V 1700,2500,CONT_POLY,*
-V 2200,2000,CONT_POLY,*
-V 2200,1000,CONT_DIF_N,*
-V 2200,3500,CONT_DIF_P,*
-V 2200,4700,CONT_BODY_N,*
-V 400,4000,CONT_DIF_P,*
-V 400,3500,CONT_DIF_P,*
-V 400,3000,CONT_DIF_P,*
-V 1600,4500,CONT_DIF_P,*
-V 2200,3000,CONT_DIF_P,*
-V 1600,500,CONT_DIF_N,*
-V 1600,500,CONT_DIF_N,*
-V 400,500,CONT_DIF_N,*
-V 1000,1000,CONT_DIF_N,*
-EOF
diff --git a/alliance/share/cells/sxlib/an12_x1.sym b/alliance/share/cells/sxlib/an12_x1.sym
deleted file mode 100644
index eafa148f..00000000
Binary files a/alliance/share/cells/sxlib/an12_x1.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/an12_x1.vbe b/alliance/share/cells/sxlib/an12_x1.vbe
deleted file mode 100644
index 10267b44..00000000
--- a/alliance/share/cells/sxlib/an12_x1.vbe
+++ /dev/null
@@ -1,32 +0,0 @@
-ENTITY an12_x1 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 1250;
-  CONSTANT cin_i0	 : NATURAL := 12;
-  CONSTANT cin_i1	 : NATURAL := 9;
-  CONSTANT rdown_i0_q	 : NATURAL := 3640;
-  CONSTANT rdown_i1_q	 : NATURAL := 3640;
-  CONSTANT rup_i0_q	 : NATURAL := 3210;
-  CONSTANT rup_i1_q	 : NATURAL := 3210;
-  CONSTANT tplh_i0_q	 : NATURAL := 168;
-  CONSTANT tphl_i0_q	 : NATURAL := 200;
-  CONSTANT tphh_i1_q	 : NATURAL := 285;
-  CONSTANT tpll_i1_q	 : NATURAL := 405;
-  CONSTANT transistors	 : NATURAL := 6
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END an12_x1;
-
-ARCHITECTURE behaviour_data_flow OF an12_x1 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on an12_x1"
-  SEVERITY WARNING;
-  q <= (not (i0) and i1) after 1000 ps;
-END;
diff --git a/alliance/share/cells/sxlib/an12_x1.vhd b/alliance/share/cells/sxlib/an12_x1.vhd
deleted file mode 100644
index 6779ed37..00000000
--- a/alliance/share/cells/sxlib/an12_x1.vhd
+++ /dev/null
@@ -1,20 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY an12_x1 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END an12_x1;
-
-ARCHITECTURE RTL OF an12_x1 IS
-BEGIN
-  q <= (NOT(i0) AND i1);
-END RTL;
diff --git a/alliance/share/cells/sxlib/an12_x4.al b/alliance/share/cells/sxlib/an12_x4.al
deleted file mode 100644
index 95b23dae..00000000
--- a/alliance/share/cells/sxlib/an12_x4.al
+++ /dev/null
@@ -1,34 +0,0 @@
-V ALLIANCE : 6
-H an12_x4,L,30/10/99
-C i0,IN,EXTERNAL,6
-C i1,IN,EXTERNAL,7
-C q,OUT,EXTERNAL,8
-C vdd,IN,EXTERNAL,5
-C vss,IN,EXTERNAL,3
-T P,0.35,2.9,5,6,4,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00010
-T P,0.35,2.9,1,4,5,0,0.75,0.75,7.3,7.3,4.8,11.25,tr_00009
-T P,0.35,5.9,8,1,5,0,0.75,0.75,13.3,13.3,8.4,11.25,tr_00008
-T P,0.35,5.9,5,1,8,0,0.75,0.75,13.3,13.3,10.2,11.25,tr_00007
-T P,0.35,2.9,5,7,1,0,0.75,0.75,7.3,7.3,6.6,11.25,tr_00006
-T N,0.35,1.4,3,6,4,0,0.75,0.75,4.3,4.3,1.8,2.1,tr_00005
-T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00004
-T N,0.35,2.9,2,7,3,0,0.75,0.75,7.3,7.3,6.6,2.25,tr_00003
-T N,0.35,2.9,3,1,8,0,0.75,0.75,7.3,7.3,8.4,2.25,tr_00002
-T N,0.35,2.9,8,1,3,0,0.75,0.75,7.3,7.3,10.2,2.25,tr_00001
-S 8,EXTERNAL,q
-Q 0.00258522
-S 7,EXTERNAL,i1
-Q 0.00400776
-S 6,EXTERNAL,i0
-Q 0.00372902
-S 5,EXTERNAL,vdd
-Q 0.00606652
-S 4,INTERNAL
-Q 0.00525013
-S 3,EXTERNAL,vss
-Q 0.00536146
-S 2,INTERNAL
-Q 0
-S 1,INTERNAL
-Q 0.00603296
-EOF
diff --git a/alliance/share/cells/sxlib/an12_x4.ap b/alliance/share/cells/sxlib/an12_x4.ap
deleted file mode 100644
index eaf81a9e..00000000
--- a/alliance/share/cells/sxlib/an12_x4.ap
+++ /dev/null
@@ -1,103 +0,0 @@
-V ALLIANCE : 6
-H an12_x4,P,30/ 8/2000,100
-A 0,0,4000,5000
-R 2500,1500,ref_ref,i1_15
-R 2500,2000,ref_ref,i1_20
-R 2500,2500,ref_ref,i1_25
-R 2500,3000,ref_ref,i1_30
-R 2500,3500,ref_ref,i1_35
-R 2500,4000,ref_ref,i1_40
-R 3000,4000,ref_ref,q_40
-R 3000,3500,ref_ref,q_35
-R 3000,3000,ref_ref,q_30
-R 3000,2500,ref_ref,q_25
-R 3000,2000,ref_ref,q_20
-R 3000,1500,ref_ref,q_15
-R 3000,1000,ref_ref,q_10
-R 2500,1000,ref_ref,i1_10
-R 1000,1500,ref_ref,i0_15
-R 1000,3000,ref_ref,i0_30
-R 1000,3500,ref_ref,i0_35
-R 1000,2000,ref_ref,i0_20
-R 1000,2500,ref_ref,i0_25
-R 1000,1000,ref_ref,i0_10
-R 1000,4000,ref_ref,i0_40
-S 3000,1000,3000,4000,200,*,DOWN,ALU1
-S 3700,3000,3700,4500,200,*,DOWN,ALU1
-S 0,4700,4000,4700,600,vdd,RIGHT,CALU1
-S 3700,500,3700,1700,200,*,DOWN,ALU1
-S 2500,1000,2500,4000,100,*,DOWN,ALU1
-S 1950,1000,1950,4000,100,*,DOWN,ALU1
-S 0,300,4000,300,600,vss,RIGHT,CALU1
-S 2000,2000,3400,2000,100,*,RIGHT,POLY
-S 2800,1400,2800,2600,100,*,UP,POLY
-S 3400,1400,3400,2600,100,*,DOWN,POLY
-S 2200,2500,2500,2500,300,*,RIGHT,POLY
-S 2200,1500,2500,1500,300,*,RIGHT,POLY
-S 2200,2400,2200,3100,100,*,DOWN,POLY
-S 3700,300,3700,1200,300,*,UP,NDIF
-S 3400,100,3400,1400,100,*,DOWN,NTRANS
-S 2500,300,2500,1200,300,*,UP,NDIF
-S 3100,300,3100,1200,300,*,UP,NDIF
-S 2800,100,2800,1400,100,*,DOWN,NTRANS
-S 2200,100,2200,1400,100,*,DOWN,NTRANS
-S 2200,3100,2200,4400,100,*,UP,PTRANS
-S 3100,2800,3100,4700,300,*,DOWN,PDIF
-S 2500,2800,2500,4700,300,*,DOWN,PDIF
-S 3700,2800,3700,4700,300,*,DOWN,PDIF
-S 3400,2600,3400,4900,100,*,UP,PTRANS
-S 2800,2600,2800,4900,100,*,UP,PTRANS
-S 1900,3300,1900,4200,300,*,DOWN,PDIF
-S 0,3900,4000,3900,2400,*,RIGHT,NWELL
-S 1600,3100,1600,4400,100,*,UP,PTRANS
-S 1800,100,1800,1400,100,*,DOWN,NTRANS
-S 1500,1000,1950,1000,100,*,RIGHT,ALU1
-S 1500,300,1500,1200,300,*,UP,NDIF
-S 900,500,900,900,300,*,UP,NDIF
-S 600,300,600,1100,100,*,UP,NTRANS
-S 300,500,300,900,300,*,UP,NDIF
-S 600,3100,600,4400,100,*,UP,PTRANS
-S 300,3300,300,4200,300,*,DOWN,PDIF
-S 1000,1000,1000,4000,100,*,DOWN,ALU1
-S 1100,3300,1100,4600,700,*,DOWN,PDIF
-S 300,1000,300,4000,100,*,DOWN,ALU1
-S 300,2500,1600,2500,100,*,RIGHT,POLY
-S 1600,1400,1600,3100,100,*,DOWN,POLY
-S 1600,1400,1800,1400,100,*,RIGHT,POLY
-S 600,3100,1000,3100,100,*,RIGHT,POLY
-S 1000,3000,1000,3100,100,*,DOWN,POLY
-S 600,1100,1000,1100,100,*,RIGHT,POLY
-S 1000,1100,1000,1200,100,*,UP,POLY
-S 2500,1000,2500,4000,200,i1,DOWN,CALU1
-S 3000,1000,3000,4000,200,q,DOWN,CALU1
-S 1000,1000,1000,4000,200,i0,DOWN,CALU1
-V 1900,3500,CONT_DIF_P,*
-V 2000,2000,CONT_POLY,*
-V 2400,2500,CONT_POLY,*
-V 2400,1500,CONT_POLY,*
-V 3700,1700,CONT_BODY_P,*
-V 2500,500,CONT_DIF_N,*
-V 3100,1000,CONT_DIF_N,*
-V 3700,500,CONT_DIF_N,*
-V 3700,1000,CONT_DIF_N,*
-V 2500,4500,CONT_DIF_P,*
-V 3700,4500,CONT_DIF_P,*
-V 3700,4000,CONT_DIF_P,*
-V 1900,4000,CONT_DIF_P,*
-V 1900,4700,CONT_BODY_N,*
-V 3100,3000,CONT_DIF_P,*
-V 3100,3500,CONT_DIF_P,*
-V 3100,4000,CONT_DIF_P,*
-V 3700,3500,CONT_DIF_P,*
-V 3700,3000,CONT_DIF_P,*
-V 1300,4500,CONT_DIF_P,*
-V 1500,1000,CONT_DIF_N,*
-V 900,500,CONT_DIF_N,*
-V 300,1000,CONT_DIF_N,*
-V 300,3500,CONT_DIF_P,*
-V 300,4000,CONT_DIF_P,*
-V 1000,3000,CONT_POLY,*
-V 900,4500,CONT_DIF_P,*
-V 300,2500,CONT_POLY,*
-V 1000,1200,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/sxlib/an12_x4.sym b/alliance/share/cells/sxlib/an12_x4.sym
deleted file mode 100644
index 4b6274ce..00000000
Binary files a/alliance/share/cells/sxlib/an12_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/an12_x4.vbe b/alliance/share/cells/sxlib/an12_x4.vbe
deleted file mode 100644
index 0d030a6c..00000000
--- a/alliance/share/cells/sxlib/an12_x4.vbe
+++ /dev/null
@@ -1,32 +0,0 @@
-ENTITY an12_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 2000;
-  CONSTANT cin_i0	 : NATURAL := 9;
-  CONSTANT cin_i1	 : NATURAL := 11;
-  CONSTANT rdown_i0_q	 : NATURAL := 810;
-  CONSTANT rdown_i1_q	 : NATURAL := 810;
-  CONSTANT rup_i0_q	 : NATURAL := 890;
-  CONSTANT rup_i1_q	 : NATURAL := 890;
-  CONSTANT tphh_i1_q	 : NATURAL := 269;
-  CONSTANT tphl_i0_q	 : NATURAL := 461;
-  CONSTANT tplh_i0_q	 : NATURAL := 471;
-  CONSTANT tpll_i1_q	 : NATURAL := 518;
-  CONSTANT transistors	 : NATURAL := 10
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END an12_x4;
-
-ARCHITECTURE behaviour_data_flow OF an12_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on an12_x4"
-  SEVERITY WARNING;
-  q <= (not (i0) and i1) after 1100 ps;
-END;
diff --git a/alliance/share/cells/sxlib/an12_x4.vhd b/alliance/share/cells/sxlib/an12_x4.vhd
deleted file mode 100644
index cc1252a1..00000000
--- a/alliance/share/cells/sxlib/an12_x4.vhd
+++ /dev/null
@@ -1,20 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY an12_x4 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END an12_x4;
-
-ARCHITECTURE RTL OF an12_x4 IS
-BEGIN
-  q <= (NOT(i0) AND i1);
-END RTL;
diff --git a/alliance/share/cells/sxlib/ao22_x2.al b/alliance/share/cells/sxlib/ao22_x2.al
deleted file mode 100644
index 7a3497ad..00000000
--- a/alliance/share/cells/sxlib/ao22_x2.al
+++ /dev/null
@@ -1,35 +0,0 @@
-V ALLIANCE : 6
-H ao22_x2,L,30/10/99
-C i0,IN,EXTERNAL,8
-C i1,IN,EXTERNAL,6
-C i2,IN,EXTERNAL,7
-C q,OUT,EXTERNAL,4
-C vdd,IN,EXTERNAL,5
-C vss,IN,EXTERNAL,1
-T P,0.35,2.9,9,6,2,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00008
-T P,0.35,2.9,5,8,9,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00007
-T P,0.35,2.9,2,7,5,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00006
-T P,0.35,5.9,5,2,4,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00005
-T N,0.35,2.9,4,2,1,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00004
-T N,0.35,1.4,1,7,3,0,0.75,0.75,4.3,4.3,5.4,3,tr_00003
-T N,0.35,1.4,3,6,2,0,0.75,0.75,4.3,4.3,3.6,3,tr_00002
-T N,0.35,1.4,2,8,3,0,0.75,0.75,4.3,4.3,1.8,3,tr_00001
-S 9,INTERNAL
-Q 0
-S 8,EXTERNAL,i0
-Q 0.00295462
-S 7,EXTERNAL,i2
-Q 0.00371745
-S 6,EXTERNAL,i1
-Q 0.00344928
-S 5,EXTERNAL,vdd
-Q 0.00367968
-S 4,EXTERNAL,q
-Q 0.00358405
-S 3,INTERNAL
-Q 0.00114171
-S 2,INTERNAL
-Q 0.00464422
-S 1,EXTERNAL,vss
-Q 0.00367968
-EOF
diff --git a/alliance/share/cells/sxlib/ao22_x2.ap b/alliance/share/cells/sxlib/ao22_x2.ap
deleted file mode 100644
index 9b7b6482..00000000
--- a/alliance/share/cells/sxlib/ao22_x2.ap
+++ /dev/null
@@ -1,97 +0,0 @@
-V ALLIANCE : 6
-H ao22_x2,P,30/ 8/2000,100
-A 0,0,3000,5000
-R 1000,3000,ref_ref,i1_30
-R 1000,3500,ref_ref,i1_35
-R 1000,4000,ref_ref,i1_40
-R 500,4000,ref_ref,i0_40
-R 500,3500,ref_ref,i0_35
-R 500,3000,ref_ref,i0_30
-R 500,2500,ref_ref,i0_25
-R 500,2000,ref_ref,i0_20
-R 2000,1500,ref_ref,i2_15
-R 2000,2000,ref_ref,i2_20
-R 2000,2500,ref_ref,i2_25
-R 2000,3000,ref_ref,i2_30
-R 2000,3500,ref_ref,i2_35
-R 2000,4000,ref_ref,i2_40
-R 1000,2000,ref_ref,i1_20
-R 1000,2500,ref_ref,i1_25
-R 2500,4000,ref_ref,q_40
-R 2500,3500,ref_ref,q_35
-R 2500,3000,ref_ref,q_30
-R 2500,2500,ref_ref,q_25
-R 2500,2000,ref_ref,q_20
-R 2500,1500,ref_ref,q_15
-R 2500,1000,ref_ref,q_10
-R 2000,1000,ref_ref,i2_10
-S 500,2000,500,4000,200,i0,DOWN,CALU1
-S 1000,2000,1000,4000,200,i1,DOWN,CALU1
-S 2500,1000,2500,4000,200,q,DOWN,CALU1
-S 2000,1000,2000,4000,200,i2,DOWN,CALU1
-S 2100,2800,2100,4700,300,*,UP,PDIF
-S 2700,2800,2700,4700,300,*,UP,PDIF
-S 1200,3100,1200,4400,100,*,DOWN,PTRANS
-S 600,3100,600,4400,100,*,DOWN,PTRANS
-S 1800,3100,1800,4400,100,*,DOWN,PTRANS
-S 300,3300,300,4600,300,*,UP,PDIF
-S 900,3300,900,4200,300,*,UP,PDIF
-S 1500,3300,1500,4200,300,*,UP,PDIF
-S 2400,2600,2400,4900,100,*,DOWN,PTRANS
-S 0,3900,3000,3900,2400,*,RIGHT,NWELL
-S 900,800,900,1600,300,*,DOWN,NDIF
-S 2400,100,2400,1400,100,*,UP,NTRANS
-S 2100,300,2100,1200,300,*,DOWN,NDIF
-S 2700,300,2700,1200,300,*,DOWN,NDIF
-S 1800,600,1800,1400,100,*,UP,NTRANS
-S 300,800,300,1200,300,*,DOWN,NDIF
-S 1500,800,1500,1200,300,*,DOWN,NDIF
-S 1200,600,1200,1400,100,*,UP,NTRANS
-S 600,600,600,1400,100,*,UP,NTRANS
-S 1400,2100,2400,2100,100,*,RIGHT,POLY
-S 1000,1800,1000,2100,300,*,UP,POLY
-S 1800,2600,2100,2600,100,*,LEFT,POLY
-S 1800,2600,1800,3100,100,*,DOWN,POLY
-S 900,3100,1200,3100,100,*,RIGHT,POLY
-S 1800,1400,2100,1400,100,*,RIGHT,POLY
-S 900,1800,1200,1800,100,*,RIGHT,POLY
-S 1200,1400,1200,1800,100,*,DOWN,POLY
-S 600,1400,600,3100,100,*,UP,POLY
-S 2400,1400,2400,2600,100,*,UP,POLY
-S 0,300,3000,300,600,vss,RIGHT,CALU1
-S 2500,3500,2700,3500,200,*,RIGHT,ALU1
-S 2500,4000,2700,4000,200,*,RIGHT,ALU1
-S 2500,1000,2700,1000,200,*,RIGHT,ALU1
-S 500,2000,500,4000,100,*,UP,ALU1
-S 1000,2000,1000,4000,100,*,UP,ALU1
-S 300,1000,1500,1000,100,*,RIGHT,ALU1
-S 1500,1500,1500,4000,100,*,DOWN,ALU1
-S 900,1500,1500,1500,100,*,RIGHT,ALU1
-S 2000,1000,2000,4000,100,*,UP,ALU1
-S 0,4700,3000,4700,600,vdd,RIGHT,CALU1
-S 2500,3000,2700,3000,200,*,RIGHT,ALU1
-S 2500,950,2500,4050,200,*,DOWN,ALU1
-V 2700,4000,CONT_DIF_P,*
-V 2700,3500,CONT_DIF_P,*
-V 2700,3000,CONT_DIF_P,*
-V 300,4500,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 1500,3500,CONT_DIF_P,*
-V 900,4700,CONT_BODY_N,*
-V 2100,4500,CONT_DIF_P,*
-V 1500,4700,CONT_BODY_N,*
-V 900,1500,CONT_DIF_N,*
-V 2700,1000,CONT_DIF_N,*
-V 300,1000,CONT_DIF_N,*
-V 1500,1000,CONT_DIF_N,*
-V 2100,500,CONT_DIF_N,*
-V 1500,300,CONT_BODY_P,*
-V 300,300,CONT_BODY_P,*
-V 900,300,CONT_BODY_P,*
-V 500,2000,CONT_POLY,*
-V 1000,2000,CONT_POLY,*
-V 2000,1500,CONT_POLY,*
-V 2000,2500,CONT_POLY,*
-V 1500,2200,CONT_POLY,*
-V 1000,3000,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/sxlib/ao22_x2.sym b/alliance/share/cells/sxlib/ao22_x2.sym
deleted file mode 100644
index ce180b7b..00000000
Binary files a/alliance/share/cells/sxlib/ao22_x2.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/ao22_x2.vbe b/alliance/share/cells/sxlib/ao22_x2.vbe
deleted file mode 100644
index 7cfca61f..00000000
--- a/alliance/share/cells/sxlib/ao22_x2.vbe
+++ /dev/null
@@ -1,38 +0,0 @@
-ENTITY ao22_x2 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 1500;
-  CONSTANT cin_i0	 : NATURAL := 8;
-  CONSTANT cin_i1	 : NATURAL := 8;
-  CONSTANT cin_i2	 : NATURAL := 9;
-  CONSTANT rdown_i0_q	 : NATURAL := 1620;
-  CONSTANT rdown_i1_q	 : NATURAL := 1620;
-  CONSTANT rdown_i2_q	 : NATURAL := 1620;
-  CONSTANT rup_i0_q	 : NATURAL := 1790;
-  CONSTANT rup_i1_q	 : NATURAL := 1790;
-  CONSTANT rup_i2_q	 : NATURAL := 1790;
-  CONSTANT tphh_i2_q	 : NATURAL := 420;
-  CONSTANT tpll_i2_q	 : NATURAL := 425;
-  CONSTANT tpll_i0_q	 : NATURAL := 447;
-  CONSTANT tphh_i1_q	 : NATURAL := 493;
-  CONSTANT tpll_i1_q	 : NATURAL := 526;
-  CONSTANT tphh_i0_q	 : NATURAL := 558;
-  CONSTANT transistors	 : NATURAL := 8
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END ao22_x2;
-
-ARCHITECTURE behaviour_data_flow OF ao22_x2 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on ao22_x2"
-  SEVERITY WARNING;
-  q <= ((i0 or i1) and i2) after 1200 ps;
-END;
diff --git a/alliance/share/cells/sxlib/ao22_x2.vhd b/alliance/share/cells/sxlib/ao22_x2.vhd
deleted file mode 100644
index e0a0dd3e..00000000
--- a/alliance/share/cells/sxlib/ao22_x2.vhd
+++ /dev/null
@@ -1,21 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY ao22_x2 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END ao22_x2;
-
-ARCHITECTURE RTL OF ao22_x2 IS
-BEGIN
-  q <= ((i0 OR i1) AND i2);
-END RTL;
diff --git a/alliance/share/cells/sxlib/ao22_x4.al b/alliance/share/cells/sxlib/ao22_x4.al
deleted file mode 100644
index 97b82f3d..00000000
--- a/alliance/share/cells/sxlib/ao22_x4.al
+++ /dev/null
@@ -1,37 +0,0 @@
-V ALLIANCE : 6
-H ao22_x4,L,30/10/99
-C i0,IN,EXTERNAL,8
-C i1,IN,EXTERNAL,7
-C i2,IN,EXTERNAL,6
-C q,OUT,EXTERNAL,4
-C vdd,IN,EXTERNAL,5
-C vss,IN,EXTERNAL,2
-T P,0.35,2.9,3,6,5,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00010
-T P,0.35,2.9,5,8,9,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00009
-T P,0.35,2.9,9,7,3,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00008
-T P,0.35,5.9,5,3,4,0,0.75,0.75,13.3,13.3,8.1,11.25,tr_00007
-T P,0.35,5.9,4,3,5,0,0.75,0.75,13.3,13.3,9.9,11.25,tr_00006
-T N,0.35,1.4,3,8,1,0,0.75,0.75,4.3,4.3,1.8,3,tr_00005
-T N,0.35,1.4,1,7,3,0,0.75,0.75,4.3,4.3,3.6,3,tr_00004
-T N,0.35,1.4,2,6,1,0,0.75,0.75,4.3,4.3,5.4,3,tr_00003
-T N,0.35,2.9,2,3,4,0,0.75,0.75,7.3,7.3,9.9,2.25,tr_00002
-T N,0.35,2.9,4,3,2,0,0.75,0.75,7.3,7.3,8.1,2.25,tr_00001
-S 9,INTERNAL
-Q 0
-S 8,EXTERNAL,i0
-Q 0.00295461
-S 7,EXTERNAL,i1
-Q 0.00344928
-S 6,EXTERNAL,i2
-Q 0.00371745
-S 5,EXTERNAL,vdd
-Q 0.00606652
-S 4,EXTERNAL,q
-Q 0.00258522
-S 3,INTERNAL
-Q 0.00618269
-S 2,EXTERNAL,vss
-Q 0.00512644
-S 1,INTERNAL
-Q 0.00114171
-EOF
diff --git a/alliance/share/cells/sxlib/ao22_x4.ap b/alliance/share/cells/sxlib/ao22_x4.ap
deleted file mode 100644
index d4d655f2..00000000
--- a/alliance/share/cells/sxlib/ao22_x4.ap
+++ /dev/null
@@ -1,108 +0,0 @@
-V ALLIANCE : 6
-H ao22_x4,P,30/ 8/2000,100
-A 0,0,4000,5000
-R 2000,1000,ref_ref,i2_10
-R 3000,1500,ref_ref,q_15
-R 3000,2000,ref_ref,q_20
-R 3000,2500,ref_ref,q_25
-R 3000,3000,ref_ref,q_30
-R 3000,3500,ref_ref,q_35
-R 3000,4000,ref_ref,q_40
-R 3000,1000,ref_ref,q_10
-R 1000,2500,ref_ref,i1_25
-R 1000,2000,ref_ref,i1_20
-R 2000,4000,ref_ref,i2_40
-R 2000,3500,ref_ref,i2_35
-R 2000,3000,ref_ref,i2_30
-R 2000,2500,ref_ref,i2_25
-R 2000,2000,ref_ref,i2_20
-R 2000,1500,ref_ref,i2_15
-R 500,2000,ref_ref,i0_20
-R 500,2500,ref_ref,i0_25
-R 500,3000,ref_ref,i0_30
-R 500,3500,ref_ref,i0_35
-R 500,4000,ref_ref,i0_40
-R 1000,4000,ref_ref,i1_40
-R 1000,3500,ref_ref,i1_35
-R 1000,3000,ref_ref,i1_30
-S 3000,1000,3000,4000,200,q,DOWN,CALU1
-S 2000,1000,2000,4000,200,i2,DOWN,CALU1
-S 500,2000,500,4000,200,i0,DOWN,CALU1
-S 1000,2000,1000,4000,200,i1,DOWN,CALU1
-S 2000,1000,2000,4000,100,*,UP,ALU1
-S 900,1500,1500,1500,100,*,RIGHT,ALU1
-S 1500,1500,1500,4000,100,*,DOWN,ALU1
-S 300,1000,1500,1000,100,*,RIGHT,ALU1
-S 1000,2000,1000,4000,100,*,UP,ALU1
-S 500,2000,500,4000,100,*,UP,ALU1
-S 3600,500,3600,1000,200,*,DOWN,ALU1
-S 3600,3000,3600,4500,200,*,UP,ALU1
-S 3000,1000,3000,4000,200,*,DOWN,ALU1
-S 0,300,4000,300,600,vss,RIGHT,CALU1
-S 0,4700,4000,4700,600,vdd,RIGHT,CALU1
-S 600,1400,600,3100,100,*,UP,POLY
-S 1200,1400,1200,1800,100,*,DOWN,POLY
-S 900,1800,1200,1800,100,*,RIGHT,POLY
-S 1800,1400,2100,1400,100,*,RIGHT,POLY
-S 900,3100,1200,3100,100,*,RIGHT,POLY
-S 1800,2600,1800,3100,100,*,DOWN,POLY
-S 1800,2600,2100,2600,100,*,LEFT,POLY
-S 2700,1400,2700,2600,100,*,UP,POLY
-S 1400,2100,3300,2100,100,*,RIGHT,POLY
-S 1000,1800,1000,2100,300,*,UP,POLY
-S 3300,1400,3300,2600,100,*,UP,POLY
-S 600,600,600,1400,100,*,UP,NTRANS
-S 1200,600,1200,1400,100,*,UP,NTRANS
-S 1500,800,1500,1200,300,*,DOWN,NDIF
-S 300,800,300,1200,300,*,DOWN,NDIF
-S 1800,600,1800,1400,100,*,UP,NTRANS
-S 2100,300,2100,1200,300,*,DOWN,NDIF
-S 3300,100,3300,1400,100,*,UP,NTRANS
-S 900,800,900,1600,300,*,DOWN,NDIF
-S 2700,100,2700,1400,100,*,UP,NTRANS
-S 3000,300,3000,1200,300,*,DOWN,NDIF
-S 3600,300,3600,1200,300,*,DOWN,NDIF
-S 2400,300,2400,1200,300,*,DOWN,NDIF
-S 2400,2800,2400,4700,300,*,UP,PDIF
-S 1500,3300,1500,4200,300,*,UP,PDIF
-S 900,3300,900,4200,300,*,UP,PDIF
-S 300,3300,300,4600,300,*,UP,PDIF
-S 1800,3100,1800,4400,100,*,DOWN,PTRANS
-S 600,3100,600,4400,100,*,DOWN,PTRANS
-S 1200,3100,1200,4400,100,*,DOWN,PTRANS
-S 2100,2800,2100,4700,300,*,UP,PDIF
-S 2700,2600,2700,4900,100,*,DOWN,PTRANS
-S 3000,2800,3000,4700,300,*,UP,PDIF
-S 3300,2600,3300,4900,100,*,DOWN,PTRANS
-S 3600,2800,3600,4700,300,*,UP,PDIF
-S 0,3900,4000,3900,2400,*,RIGHT,NWELL
-V 1000,3000,CONT_POLY,*
-V 1500,2200,CONT_POLY,*
-V 2000,2500,CONT_POLY,*
-V 2000,1500,CONT_POLY,*
-V 1000,2000,CONT_POLY,*
-V 500,2000,CONT_POLY,*
-V 900,300,CONT_BODY_P,*
-V 300,300,CONT_BODY_P,*
-V 1500,300,CONT_BODY_P,*
-V 3600,1000,CONT_DIF_N,*
-V 1500,1000,CONT_DIF_N,*
-V 300,1000,CONT_DIF_N,*
-V 3000,1000,CONT_DIF_N,*
-V 2300,500,CONT_DIF_N,*
-V 3600,500,CONT_DIF_N,*
-V 900,1500,CONT_DIF_N,*
-V 3600,3000,CONT_DIF_P,*
-V 1500,4700,CONT_BODY_N,*
-V 3000,4000,CONT_DIF_P,*
-V 900,4700,CONT_BODY_N,*
-V 1500,3500,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 300,4500,CONT_DIF_P,*
-V 3600,4500,CONT_DIF_P,*
-V 2300,4500,CONT_DIF_P,*
-V 3600,4000,CONT_DIF_P,*
-V 3600,3500,CONT_DIF_P,*
-V 3000,3000,CONT_DIF_P,*
-V 3000,3500,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/ao22_x4.sym b/alliance/share/cells/sxlib/ao22_x4.sym
deleted file mode 100644
index a74c5237..00000000
Binary files a/alliance/share/cells/sxlib/ao22_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/ao22_x4.vbe b/alliance/share/cells/sxlib/ao22_x4.vbe
deleted file mode 100644
index 2995c9cc..00000000
--- a/alliance/share/cells/sxlib/ao22_x4.vbe
+++ /dev/null
@@ -1,38 +0,0 @@
-ENTITY ao22_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 2000;
-  CONSTANT cin_i0	 : NATURAL := 8;
-  CONSTANT cin_i1	 : NATURAL := 8;
-  CONSTANT cin_i2	 : NATURAL := 9;
-  CONSTANT rdown_i0_q	 : NATURAL := 810;
-  CONSTANT rdown_i1_q	 : NATURAL := 810;
-  CONSTANT rdown_i2_q	 : NATURAL := 810;
-  CONSTANT rup_i0_q	 : NATURAL := 890;
-  CONSTANT rup_i1_q	 : NATURAL := 890;
-  CONSTANT rup_i2_q	 : NATURAL := 890;
-  CONSTANT tpll_i2_q	 : NATURAL := 505;
-  CONSTANT tphh_i2_q	 : NATURAL := 526;
-  CONSTANT tpll_i0_q	 : NATURAL := 552;
-  CONSTANT tphh_i1_q	 : NATURAL := 615;
-  CONSTANT tpll_i1_q	 : NATURAL := 647;
-  CONSTANT tphh_i0_q	 : NATURAL := 674;
-  CONSTANT transistors	 : NATURAL := 10
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END ao22_x4;
-
-ARCHITECTURE behaviour_data_flow OF ao22_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on ao22_x4"
-  SEVERITY WARNING;
-  q <= ((i0 or i1) and i2) after 1300 ps;
-END;
diff --git a/alliance/share/cells/sxlib/ao22_x4.vhd b/alliance/share/cells/sxlib/ao22_x4.vhd
deleted file mode 100644
index 9edee9dd..00000000
--- a/alliance/share/cells/sxlib/ao22_x4.vhd
+++ /dev/null
@@ -1,21 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY ao22_x4 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END ao22_x4;
-
-ARCHITECTURE RTL OF ao22_x4 IS
-BEGIN
-  q <= ((i0 OR i1) AND i2);
-END RTL;
diff --git a/alliance/share/cells/sxlib/ao2o22_x2.al b/alliance/share/cells/sxlib/ao2o22_x2.al
deleted file mode 100644
index c9435003..00000000
--- a/alliance/share/cells/sxlib/ao2o22_x2.al
+++ /dev/null
@@ -1,42 +0,0 @@
-V ALLIANCE : 6
-H ao2o22_x2,L,30/10/99
-C i0,IN,EXTERNAL,6
-C i1,IN,EXTERNAL,4
-C i2,IN,EXTERNAL,5
-C i3,IN,EXTERNAL,7
-C q,OUT,EXTERNAL,8
-C vdd,IN,EXTERNAL,9
-C vss,IN,EXTERNAL,1
-T P,0.35,2.9,10,6,9,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00010
-T P,0.35,2.9,11,5,3,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00009
-T P,0.35,2.9,9,7,11,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00008
-T P,0.35,2.9,3,4,10,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00007
-T P,0.35,5.9,8,3,9,0,0.75,0.75,13.3,13.3,11.1,11.25,tr_00006
-T N,0.35,1.4,2,5,1,0,0.75,0.75,4.3,4.3,5.4,3,tr_00005
-T N,0.35,1.4,1,7,2,0,0.75,0.75,4.3,4.3,7.2,3,tr_00004
-T N,0.35,1.4,2,6,3,0,0.75,0.75,4.3,4.3,1.8,3,tr_00003
-T N,0.35,1.4,3,4,2,0,0.75,0.75,4.3,4.3,3.6,3,tr_00002
-T N,0.35,2.9,1,3,8,0,0.75,0.75,7.3,7.3,11.1,2.25,tr_00001
-S 11,INTERNAL
-Q 0
-S 10,INTERNAL
-Q 0
-S 9,EXTERNAL,vdd
-Q 0.00505663
-S 8,EXTERNAL,q
-Q 0.00258522
-S 7,EXTERNAL,i3
-Q 0.00295462
-S 6,EXTERNAL,i0
-Q 0.00295462
-S 5,EXTERNAL,i2
-Q 0.00323197
-S 4,EXTERNAL,i1
-Q 0.00323197
-S 3,INTERNAL
-Q 0.00640584
-S 2,INTERNAL
-Q 0.00199441
-S 1,EXTERNAL,vss
-Q 0.00564418
-EOF
diff --git a/alliance/share/cells/sxlib/ao2o22_x2.ap b/alliance/share/cells/sxlib/ao2o22_x2.ap
deleted file mode 100644
index 6d49c1c9..00000000
--- a/alliance/share/cells/sxlib/ao2o22_x2.ap
+++ /dev/null
@@ -1,111 +0,0 @@
-V ALLIANCE : 6
-H ao2o22_x2,P, 6/ 9/2000,100
-A 0,0,4500,5000
-R 4000,1000,ref_ref,q_10
-R 4000,1500,ref_ref,q_15
-R 4000,2500,ref_ref,q_25
-R 4000,3500,ref_ref,q_35
-R 4000,3000,ref_ref,q_30
-R 4000,2000,ref_ref,q_20
-R 4000,4000,ref_ref,q_40
-R 2500,3500,ref_ref,i3_35
-R 2000,3500,ref_ref,i2_35
-R 1000,3500,ref_ref,i1_35
-R 1000,4000,ref_ref,i1_40
-R 500,4000,ref_ref,i0_40
-R 500,3500,ref_ref,i0_35
-R 2500,1500,ref_ref,i3_15
-R 2500,2000,ref_ref,i3_20
-R 2500,2500,ref_ref,i3_25
-R 2500,3000,ref_ref,i3_30
-R 2000,3000,ref_ref,i2_30
-R 2000,2500,ref_ref,i2_25
-R 2000,2000,ref_ref,i2_20
-R 2000,1500,ref_ref,i2_15
-R 1000,2000,ref_ref,i1_20
-R 1000,2500,ref_ref,i1_25
-R 1000,3000,ref_ref,i1_30
-R 500,3000,ref_ref,i0_30
-R 500,2500,ref_ref,i0_25
-R 500,2000,ref_ref,i0_20
-S 3500,2000,3700,2000,300,*,RIGHT,POLY
-S 0,300,4500,300,600,vss,RIGHT,CALU1
-S 0,3900,4500,3900,2400,*,RIGHT,NWELL
-S 0,4700,4500,4700,600,vdd,RIGHT,CALU1
-S 3000,2000,3500,2000,100,*,RIGHT,ALU1
-S 3000,2000,3000,4000,100,*,DOWN,ALU1
-S 1600,4000,3000,4000,100,*,LEFT,ALU1
-S 3700,2600,3700,4900,100,*,UP,PTRANS
-S 4000,2800,4000,4700,300,*,DOWN,PDIF
-S 3400,2800,3400,4700,300,*,DOWN,PDIF
-S 3400,300,3400,1200,300,*,UP,NDIF
-S 4000,300,4000,1200,300,*,UP,NDIF
-S 3700,100,3700,1400,100,*,DOWN,NTRANS
-S 3700,1400,3700,2600,100,*,DOWN,POLY
-S 4000,1000,4000,4000,200,*,UP,ALU1
-S 3400,500,3400,1000,200,*,DOWN,ALU1
-S 300,800,300,1200,300,*,UP,NDIF
-S 2500,1500,2500,3500,100,*,DOWN,ALU1
-S 2000,1500,2000,3500,100,*,DOWN,ALU1
-S 900,1500,1500,1500,100,*,RIGHT,ALU1
-S 500,2000,500,4000,100,*,UP,ALU1
-S 1000,2000,1000,4000,100,*,DOWN,ALU1
-S 900,800,900,1600,300,*,UP,NDIF
-S 300,1000,2700,1000,100,*,RIGHT,ALU1
-S 1500,1500,1500,4000,100,*,UP,ALU1
-S 2700,800,2700,1200,300,*,UP,NDIF
-S 2100,400,2100,1200,300,*,UP,NDIF
-S 2100,3300,2100,4200,300,*,DOWN,PDIF
-S 300,3300,300,4600,300,*,DOWN,PDIF
-S 2700,3300,2700,4600,300,*,DOWN,PDIF
-S 600,1400,600,3100,100,*,DOWN,POLY
-S 1200,1400,1200,3100,100,*,DOWN,POLY
-S 1800,1400,1800,3100,100,*,DOWN,POLY
-S 2400,1400,2400,3100,100,*,DOWN,POLY
-S 1200,600,1200,1400,100,*,DOWN,NTRANS
-S 600,600,600,1400,100,*,DOWN,NTRANS
-S 2400,600,2400,1400,100,*,DOWN,NTRANS
-S 1800,600,1800,1400,100,*,DOWN,NTRANS
-S 1500,800,1500,1200,300,*,UP,NDIF
-S 1200,3100,1200,4400,100,*,UP,PTRANS
-S 2400,3100,2400,4400,100,*,UP,PTRANS
-S 1800,3100,1800,4400,100,*,UP,PTRANS
-S 1500,3300,1500,4200,300,*,DOWN,PDIF
-S 600,3100,600,4400,100,*,UP,PTRANS
-S 900,3300,900,4200,300,*,DOWN,PDIF
-S 1000,2000,1200,2000,300,*,RIGHT,POLY
-S 1800,2000,2000,2000,300,*,RIGHT,POLY
-S 4000,1000,4000,4000,200,q,DOWN,CALU1
-S 2500,1500,2500,3500,200,i3,DOWN,CALU1
-S 2000,1500,2000,3500,200,i2,DOWN,CALU1
-S 1000,2000,1000,4000,200,i1,DOWN,CALU1
-S 500,2000,500,4000,200,i0,DOWN,CALU1
-V 4000,4000,CONT_DIF_P,*
-V 4000,3500,CONT_DIF_P,*
-V 4000,3000,CONT_DIF_P,*
-V 3400,4500,CONT_DIF_P,*
-V 4000,1000,CONT_DIF_N,*
-V 3400,1000,CONT_DIF_N,*
-V 3400,500,CONT_DIF_N,*
-V 3500,2000,CONT_POLY,*
-V 300,300,CONT_BODY_P,*
-V 900,300,CONT_BODY_P,*
-V 2700,300,CONT_BODY_P,*
-V 900,4700,CONT_BODY_N,*
-V 2100,4700,CONT_BODY_N,*
-V 900,1500,CONT_DIF_N,*
-V 1500,3500,CONT_DIF_P,*
-V 300,1000,CONT_DIF_N,*
-V 1500,1000,CONT_DIF_N,*
-V 2700,1000,CONT_DIF_N,*
-V 2100,500,CONT_DIF_N,*
-V 1500,4000,CONT_DIF_P,*
-V 300,4500,CONT_DIF_P,*
-V 2700,4500,CONT_DIF_P,*
-V 1500,4700,CONT_BODY_N,*
-V 1500,300,CONT_BODY_P,*
-V 500,2000,CONT_POLY,*
-V 2500,2000,CONT_POLY,*
-V 1000,2000,CONT_POLY,*
-V 2000,2000,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/sxlib/ao2o22_x2.sym b/alliance/share/cells/sxlib/ao2o22_x2.sym
deleted file mode 100644
index e11d7a60..00000000
Binary files a/alliance/share/cells/sxlib/ao2o22_x2.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/ao2o22_x2.vbe b/alliance/share/cells/sxlib/ao2o22_x2.vbe
deleted file mode 100644
index c503d1b9..00000000
--- a/alliance/share/cells/sxlib/ao2o22_x2.vbe
+++ /dev/null
@@ -1,44 +0,0 @@
-ENTITY ao2o22_x2 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 2250;
-  CONSTANT cin_i0	 : NATURAL := 8;
-  CONSTANT cin_i1	 : NATURAL := 8;
-  CONSTANT cin_i2	 : NATURAL := 8;
-  CONSTANT cin_i3	 : NATURAL := 8;
-  CONSTANT rdown_i0_q	 : NATURAL := 1620;
-  CONSTANT rdown_i1_q	 : NATURAL := 1620;
-  CONSTANT rdown_i2_q	 : NATURAL := 1620;
-  CONSTANT rdown_i3_q	 : NATURAL := 1620;
-  CONSTANT rup_i0_q	 : NATURAL := 1790;
-  CONSTANT rup_i1_q	 : NATURAL := 1790;
-  CONSTANT rup_i2_q	 : NATURAL := 1790;
-  CONSTANT rup_i3_q	 : NATURAL := 1790;
-  CONSTANT tphh_i2_q	 : NATURAL := 432;
-  CONSTANT tpll_i0_q	 : NATURAL := 451;
-  CONSTANT tphh_i3_q	 : NATURAL := 488;
-  CONSTANT tphh_i1_q	 : NATURAL := 508;
-  CONSTANT tpll_i3_q	 : NATURAL := 526;
-  CONSTANT tpll_i1_q	 : NATURAL := 542;
-  CONSTANT tphh_i0_q	 : NATURAL := 572;
-  CONSTANT tpll_i2_q	 : NATURAL := 627;
-  CONSTANT transistors	 : NATURAL := 10
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  i3	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END ao2o22_x2;
-
-ARCHITECTURE behaviour_data_flow OF ao2o22_x2 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on ao2o22_x2"
-  SEVERITY WARNING;
-  q <= ((i0 or i1) and (i2 or i3)) after 1200 ps;
-END;
diff --git a/alliance/share/cells/sxlib/ao2o22_x2.vhd b/alliance/share/cells/sxlib/ao2o22_x2.vhd
deleted file mode 100644
index 1e6a58e7..00000000
--- a/alliance/share/cells/sxlib/ao2o22_x2.vhd
+++ /dev/null
@@ -1,22 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY ao2o22_x2 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  i3	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END ao2o22_x2;
-
-ARCHITECTURE RTL OF ao2o22_x2 IS
-BEGIN
-  q <= ((i0 OR i1) AND (i2 OR i3));
-END RTL;
diff --git a/alliance/share/cells/sxlib/ao2o22_x4.al b/alliance/share/cells/sxlib/ao2o22_x4.al
deleted file mode 100644
index b54bd5fc..00000000
--- a/alliance/share/cells/sxlib/ao2o22_x4.al
+++ /dev/null
@@ -1,44 +0,0 @@
-V ALLIANCE : 6
-H ao2o22_x4,L,30/10/99
-C i0,IN,EXTERNAL,5
-C i1,IN,EXTERNAL,4
-C i2,IN,EXTERNAL,6
-C i3,IN,EXTERNAL,7
-C q,OUT,EXTERNAL,8
-C vdd,IN,EXTERNAL,9
-C vss,IN,EXTERNAL,3
-T P,0.35,5.9,8,1,9,0,0.75,0.75,13.3,13.3,11.1,11.25,tr_00012
-T P,0.35,5.9,9,1,8,0,0.75,0.75,13.3,13.3,12.9,11.25,tr_00011
-T P,0.35,2.9,1,4,11,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00010
-T P,0.35,2.9,9,7,10,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00009
-T P,0.35,2.9,10,6,1,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00008
-T P,0.35,2.9,11,5,9,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00007
-T N,0.35,2.9,8,1,3,0,0.75,0.75,7.3,7.3,12.9,2.25,tr_00006
-T N,0.35,2.9,3,1,8,0,0.75,0.75,7.3,7.3,11.1,2.25,tr_00005
-T N,0.35,1.4,1,4,2,0,0.75,0.75,4.3,4.3,3.6,3,tr_00004
-T N,0.35,1.4,2,5,1,0,0.75,0.75,4.3,4.3,1.8,3,tr_00003
-T N,0.35,1.4,3,7,2,0,0.75,0.75,4.3,4.3,7.2,3,tr_00002
-T N,0.35,1.4,2,6,3,0,0.75,0.75,4.3,4.3,5.4,3,tr_00001
-S 11,INTERNAL
-Q 0
-S 10,INTERNAL
-Q 0
-S 9,EXTERNAL,vdd
-Q 0.007102
-S 8,EXTERNAL,q
-Q 0.00258522
-S 7,EXTERNAL,i3
-Q 0.00295462
-S 6,EXTERNAL,i2
-Q 0.00323197
-S 5,EXTERNAL,i0
-Q 0.00295461
-S 4,EXTERNAL,i1
-Q 0.00323197
-S 3,EXTERNAL,vss
-Q 0.00674947
-S 2,INTERNAL
-Q 0.00199441
-S 1,INTERNAL
-Q 0.00812254
-EOF
diff --git a/alliance/share/cells/sxlib/ao2o22_x4.ap b/alliance/share/cells/sxlib/ao2o22_x4.ap
deleted file mode 100644
index 072ba9f6..00000000
--- a/alliance/share/cells/sxlib/ao2o22_x4.ap
+++ /dev/null
@@ -1,124 +0,0 @@
-V ALLIANCE : 6
-H ao2o22_x4,P,30/ 8/2000,100
-A 0,0,5000,5000
-R 4000,1000,ref_ref,q_10
-R 4000,1500,ref_ref,q_15
-R 4000,2500,ref_ref,q_25
-R 4000,3500,ref_ref,q_35
-R 4000,3000,ref_ref,q_30
-R 4000,2000,ref_ref,q_20
-R 4000,4000,ref_ref,q_40
-R 2500,3500,ref_ref,i3_35
-R 2000,3500,ref_ref,i2_35
-R 1000,3500,ref_ref,i1_35
-R 1000,4000,ref_ref,i1_40
-R 500,4000,ref_ref,i0_40
-R 500,3500,ref_ref,i0_35
-R 2500,1500,ref_ref,i3_15
-R 2500,2000,ref_ref,i3_20
-R 2500,2500,ref_ref,i3_25
-R 2500,3000,ref_ref,i3_30
-R 2000,3000,ref_ref,i2_30
-R 2000,2500,ref_ref,i2_25
-R 2000,2000,ref_ref,i2_20
-R 2000,1500,ref_ref,i2_15
-R 1000,2000,ref_ref,i1_20
-R 1000,2500,ref_ref,i1_25
-R 1000,3000,ref_ref,i1_30
-R 500,3000,ref_ref,i0_30
-R 500,2500,ref_ref,i0_25
-R 500,2000,ref_ref,i0_20
-S 4000,1000,4000,4000,200,q,DOWN,CALU1
-S 2500,1500,2500,3500,200,i3,DOWN,CALU1
-S 2000,1500,2000,3500,200,i2,DOWN,CALU1
-S 1000,2000,1000,4000,200,i1,DOWN,CALU1
-S 500,2000,500,4000,200,i0,DOWN,CALU1
-S 0,300,5000,300,600,vss,RIGHT,CALU1
-S 0,3900,5000,3900,2400,*,RIGHT,NWELL
-S 0,4700,5000,4700,600,vdd,RIGHT,CALU1
-S 3000,2000,3500,2000,100,*,RIGHT,ALU1
-S 3000,2000,3000,4000,100,*,DOWN,ALU1
-S 1600,4000,3000,4000,100,*,LEFT,ALU1
-S 3700,2600,3700,4900,100,*,UP,PTRANS
-S 4300,2600,4300,4900,100,*,UP,PTRANS
-S 4000,2800,4000,4700,300,*,DOWN,PDIF
-S 3400,2800,3400,4700,300,*,DOWN,PDIF
-S 4600,2800,4600,4700,300,*,DOWN,PDIF
-S 4300,100,4300,1400,100,*,DOWN,NTRANS
-S 3400,300,3400,1200,300,*,UP,NDIF
-S 4000,300,4000,1200,300,*,UP,NDIF
-S 4600,300,4600,1200,300,*,UP,NDIF
-S 3700,100,3700,1400,100,*,DOWN,NTRANS
-S 3500,2000,4300,2000,300,*,RIGHT,POLY
-S 4300,1400,4300,2600,100,*,DOWN,POLY
-S 3700,1400,3700,2600,100,*,DOWN,POLY
-S 4000,1000,4000,4000,200,*,UP,ALU1
-S 3400,500,3400,1000,200,*,DOWN,ALU1
-S 4600,500,4600,1000,200,*,DOWN,ALU1
-S 4600,3000,4600,4500,200,*,DOWN,ALU1
-S 300,800,300,1200,300,*,UP,NDIF
-S 2500,1500,2500,3500,100,*,DOWN,ALU1
-S 2000,1500,2000,3500,100,*,DOWN,ALU1
-S 900,1500,1500,1500,100,*,RIGHT,ALU1
-S 500,2000,500,4000,100,*,UP,ALU1
-S 1000,2000,1000,4000,100,*,DOWN,ALU1
-S 900,800,900,1600,300,*,UP,NDIF
-S 300,1000,2700,1000,100,*,RIGHT,ALU1
-S 1500,1500,1500,4000,100,*,UP,ALU1
-S 2700,800,2700,1200,300,*,UP,NDIF
-S 2100,400,2100,1200,300,*,UP,NDIF
-S 2100,3300,2100,4200,300,*,DOWN,PDIF
-S 300,3300,300,4600,300,*,DOWN,PDIF
-S 2700,3300,2700,4600,300,*,DOWN,PDIF
-S 600,1400,600,3100,100,*,DOWN,POLY
-S 1200,1400,1200,3100,100,*,DOWN,POLY
-S 1800,1400,1800,3100,100,*,DOWN,POLY
-S 2400,1400,2400,3100,100,*,DOWN,POLY
-S 1200,600,1200,1400,100,*,DOWN,NTRANS
-S 600,600,600,1400,100,*,DOWN,NTRANS
-S 2400,600,2400,1400,100,*,DOWN,NTRANS
-S 1800,600,1800,1400,100,*,DOWN,NTRANS
-S 1500,800,1500,1200,300,*,UP,NDIF
-S 1200,3100,1200,4400,100,*,UP,PTRANS
-S 2400,3100,2400,4400,100,*,UP,PTRANS
-S 1800,3100,1800,4400,100,*,UP,PTRANS
-S 1500,3300,1500,4200,300,*,DOWN,PDIF
-S 600,3100,600,4400,100,*,UP,PTRANS
-S 900,3300,900,4200,300,*,DOWN,PDIF
-S 1000,2000,1200,2000,300,*,RIGHT,POLY
-S 1800,2000,2000,2000,300,*,RIGHT,POLY
-V 4000,4000,CONT_DIF_P,*
-V 4000,3500,CONT_DIF_P,*
-V 4000,3000,CONT_DIF_P,*
-V 4600,3000,CONT_DIF_P,*
-V 4600,3500,CONT_DIF_P,*
-V 4600,4000,CONT_DIF_P,*
-V 4600,4500,CONT_DIF_P,*
-V 3400,4500,CONT_DIF_P,*
-V 4600,500,CONT_DIF_N,*
-V 4000,1000,CONT_DIF_N,*
-V 4600,1000,CONT_DIF_N,*
-V 3400,1000,CONT_DIF_N,*
-V 3400,500,CONT_DIF_N,*
-V 3500,2000,CONT_POLY,*
-V 300,300,CONT_BODY_P,*
-V 900,300,CONT_BODY_P,*
-V 2700,300,CONT_BODY_P,*
-V 900,4700,CONT_BODY_N,*
-V 2100,4700,CONT_BODY_N,*
-V 900,1500,CONT_DIF_N,*
-V 1500,3500,CONT_DIF_P,*
-V 300,1000,CONT_DIF_N,*
-V 1500,1000,CONT_DIF_N,*
-V 2700,1000,CONT_DIF_N,*
-V 2100,500,CONT_DIF_N,*
-V 1500,4000,CONT_DIF_P,*
-V 300,4500,CONT_DIF_P,*
-V 2700,4500,CONT_DIF_P,*
-V 1500,4700,CONT_BODY_N,*
-V 1500,300,CONT_BODY_P,*
-V 500,2000,CONT_POLY,*
-V 2500,2000,CONT_POLY,*
-V 1000,2000,CONT_POLY,*
-V 2000,2000,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/sxlib/ao2o22_x4.sym b/alliance/share/cells/sxlib/ao2o22_x4.sym
deleted file mode 100644
index b81d17b3..00000000
Binary files a/alliance/share/cells/sxlib/ao2o22_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/ao2o22_x4.vbe b/alliance/share/cells/sxlib/ao2o22_x4.vbe
deleted file mode 100644
index 61a5bff6..00000000
--- a/alliance/share/cells/sxlib/ao2o22_x4.vbe
+++ /dev/null
@@ -1,44 +0,0 @@
-ENTITY ao2o22_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 2500;
-  CONSTANT cin_i0	 : NATURAL := 8;
-  CONSTANT cin_i1	 : NATURAL := 8;
-  CONSTANT cin_i2	 : NATURAL := 8;
-  CONSTANT cin_i3	 : NATURAL := 8;
-  CONSTANT rdown_i0_q	 : NATURAL := 810;
-  CONSTANT rdown_i1_q	 : NATURAL := 810;
-  CONSTANT rdown_i2_q	 : NATURAL := 810;
-  CONSTANT rdown_i3_q	 : NATURAL := 810;
-  CONSTANT rup_i0_q	 : NATURAL := 890;
-  CONSTANT rup_i1_q	 : NATURAL := 890;
-  CONSTANT rup_i2_q	 : NATURAL := 890;
-  CONSTANT rup_i3_q	 : NATURAL := 890;
-  CONSTANT tphh_i2_q	 : NATURAL := 554;
-  CONSTANT tpll_i0_q	 : NATURAL := 569;
-  CONSTANT tphh_i3_q	 : NATURAL := 606;
-  CONSTANT tphh_i1_q	 : NATURAL := 637;
-  CONSTANT tpll_i3_q	 : NATURAL := 639;
-  CONSTANT tpll_i1_q	 : NATURAL := 666;
-  CONSTANT tphh_i0_q	 : NATURAL := 696;
-  CONSTANT tpll_i2_q	 : NATURAL := 744;
-  CONSTANT transistors	 : NATURAL := 12
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  i3	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END ao2o22_x4;
-
-ARCHITECTURE behaviour_data_flow OF ao2o22_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on ao2o22_x4"
-  SEVERITY WARNING;
-  q <= ((i0 or i1) and (i2 or i3)) after 1300 ps;
-END;
diff --git a/alliance/share/cells/sxlib/ao2o22_x4.vhd b/alliance/share/cells/sxlib/ao2o22_x4.vhd
deleted file mode 100644
index e056132e..00000000
--- a/alliance/share/cells/sxlib/ao2o22_x4.vhd
+++ /dev/null
@@ -1,22 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY ao2o22_x4 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  i3	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END ao2o22_x4;
-
-ARCHITECTURE RTL OF ao2o22_x4 IS
-BEGIN
-  q <= ((i0 OR i1) AND (i2 OR i3));
-END RTL;
diff --git a/alliance/share/cells/sxlib/buf_x2.al b/alliance/share/cells/sxlib/buf_x2.al
deleted file mode 100644
index 1fcb2f7a..00000000
--- a/alliance/share/cells/sxlib/buf_x2.al
+++ /dev/null
@@ -1,21 +0,0 @@
-V ALLIANCE : 6
-H buf_x2,L,30/10/99
-C i,IN,EXTERNAL,5
-C q,OUT,EXTERNAL,2
-C vdd,IN,EXTERNAL,4
-C vss,IN,EXTERNAL,1
-T P,0.35,5.9,2,3,4,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00004
-T P,0.35,1.7,4,5,3,0,0.75,0.75,4.9,4.9,1.8,9.15,tr_00003
-T N,0.35,2.9,1,3,2,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002
-T N,0.35,0.8,3,5,1,0,0.75,0.75,3.1,3.1,1.8,3.3,tr_00001
-S 5,EXTERNAL,i
-Q 0.00373582
-S 4,EXTERNAL,vdd
-Q 0.00323175
-S 3,INTERNAL
-Q 0.00370178
-S 2,EXTERNAL,q
-Q 0.00258522
-S 1,EXTERNAL,vss
-Q 0.0026442
-EOF
diff --git a/alliance/share/cells/sxlib/buf_x2.ap b/alliance/share/cells/sxlib/buf_x2.ap
deleted file mode 100644
index 6fb7cab2..00000000
--- a/alliance/share/cells/sxlib/buf_x2.ap
+++ /dev/null
@@ -1,58 +0,0 @@
-V ALLIANCE : 6
-H buf_x2,P,30/ 8/2000,100
-A 0,0,2000,5000
-R 1000,1000,ref_ref,i_10
-R 1000,1500,ref_ref,i_15
-R 1500,1000,ref_ref,q_10
-R 1500,2500,ref_ref,q_25
-R 1500,1500,ref_ref,q_15
-R 1500,4000,ref_ref,q_40
-R 1500,3500,ref_ref,q_35
-R 1500,3000,ref_ref,q_30
-R 1500,2000,ref_ref,q_20
-R 1000,4000,ref_ref,i_40
-R 1000,3500,ref_ref,i_35
-R 1000,3000,ref_ref,i_30
-R 1000,2500,ref_ref,i_25
-R 1000,2000,ref_ref,i_20
-S 1500,1000,1500,4000,200,q,DOWN,CALU1
-S 1000,1000,1000,4000,200,i,DOWN,CALU1
-S 1000,1000,1000,4000,100,*,DOWN,ALU1
-S 800,1500,1000,1500,200,*,RIGHT,ALU1
-S 600,1500,800,1500,300,*,RIGHT,POLY
-S 300,4200,300,4700,200,*,DOWN,ALU1
-S 600,2500,800,2500,300,*,RIGHT,POLY
-S 1200,1400,1200,2600,100,*,DOWN,POLY
-S 300,4200,300,4700,300,*,DOWN,NTIE
-S 900,2800,900,4700,300,*,DOWN,PDIF
-S 1500,2800,1500,4700,300,*,DOWN,PDIF
-S 1200,2600,1200,4900,100,*,UP,PTRANS
-S 1200,100,1200,1400,100,*,DOWN,NTRANS
-S 900,300,900,1200,300,*,UP,NDIF
-S 1500,300,1500,1200,300,*,UP,NDIF
-S 800,2500,1000,2500,200,*,RIGHT,ALU1
-S 1500,1000,1500,4000,200,*,UP,ALU1
-S 0,4700,2000,4700,600,vdd,RIGHT,CALU1
-S 0,3900,2000,3900,2400,*,RIGHT,NWELL
-S 0,300,2000,300,600,vss,RIGHT,CALU1
-S 600,800,600,1400,100,*,DOWN,NTRANS
-S 600,2600,600,3500,100,*,UP,PTRANS
-S 300,2800,300,3300,300,*,DOWN,PDIF
-S 300,1000,300,1200,300,*,UP,NDIF
-S 300,1100,300,3000,100,*,DOWN,ALU1
-S 300,2000,1200,2000,200,*,RIGHT,POLY
-V 1500,4000,CONT_DIF_P,*
-V 1500,3500,CONT_DIF_P,*
-V 1500,3000,CONT_DIF_P,*
-V 800,1500,CONT_POLY,*
-V 300,2000,CONT_POLY,*
-V 800,2500,CONT_POLY,*
-V 300,300,CONT_BODY_P,*
-V 300,4200,CONT_BODY_N,*
-V 300,4700,CONT_BODY_N,*
-V 300,3000,CONT_DIF_P,*
-V 900,4500,CONT_DIF_P,*
-V 900,500,CONT_DIF_N,*
-V 1500,1000,CONT_DIF_N,*
-V 300,1100,CONT_DIF_N,*
-EOF
diff --git a/alliance/share/cells/sxlib/buf_x2.sym b/alliance/share/cells/sxlib/buf_x2.sym
deleted file mode 100644
index 9fb82c89..00000000
Binary files a/alliance/share/cells/sxlib/buf_x2.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/buf_x2.vbe b/alliance/share/cells/sxlib/buf_x2.vbe
deleted file mode 100644
index e2e4c344..00000000
--- a/alliance/share/cells/sxlib/buf_x2.vbe
+++ /dev/null
@@ -1,26 +0,0 @@
-ENTITY buf_x2 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 1000;
-  CONSTANT cin_i	 : NATURAL := 6;
-  CONSTANT rdown_i_q	 : NATURAL := 1620;
-  CONSTANT rup_i_q	 : NATURAL := 1790;
-  CONSTANT tpll_i_q	 : NATURAL := 391;
-  CONSTANT tphh_i_q	 : NATURAL := 409;
-  CONSTANT transistors	 : NATURAL := 4
-);
-PORT (
-  i	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END buf_x2;
-
-ARCHITECTURE behaviour_data_flow OF buf_x2 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on buf_x2"
-  SEVERITY WARNING;
-  q <= i after 1000 ps;
-END;
diff --git a/alliance/share/cells/sxlib/buf_x2.vhd b/alliance/share/cells/sxlib/buf_x2.vhd
deleted file mode 100644
index e5c84422..00000000
--- a/alliance/share/cells/sxlib/buf_x2.vhd
+++ /dev/null
@@ -1,19 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY buf_x2 IS
-PORT(
-  i	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END buf_x2;
-
-ARCHITECTURE RTL OF buf_x2 IS
-BEGIN
-  q <= i;
-END RTL;
diff --git a/alliance/share/cells/sxlib/buf_x4.al b/alliance/share/cells/sxlib/buf_x4.al
deleted file mode 100644
index f72dee40..00000000
--- a/alliance/share/cells/sxlib/buf_x4.al
+++ /dev/null
@@ -1,23 +0,0 @@
-V ALLIANCE : 6
-H buf_x4,L,30/10/99
-C i,IN,EXTERNAL,5
-C q,OUT,EXTERNAL,2
-C vdd,IN,EXTERNAL,4
-C vss,IN,EXTERNAL,1
-T P,0.35,5.9,2,3,4,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00006
-T P,0.35,5.9,4,3,2,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00005
-T P,0.35,2.9,4,5,3,0,0.75,0.75,7.3,7.3,1.8,9.75,tr_00004
-T N,0.35,2.9,2,3,1,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00003
-T N,0.35,2.9,1,3,2,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002
-T N,0.35,1.4,3,5,1,0,0.75,0.75,4.3,4.3,1.8,3,tr_00001
-S 5,EXTERNAL,i
-Q 0.00373582
-S 4,EXTERNAL,vdd
-Q 0.00527712
-S 3,INTERNAL
-Q 0.00574803
-S 2,EXTERNAL,q
-Q 0.00258522
-S 1,EXTERNAL,vss
-Q 0.00374949
-EOF
diff --git a/alliance/share/cells/sxlib/buf_x4.ap b/alliance/share/cells/sxlib/buf_x4.ap
deleted file mode 100644
index 9dbc6a6e..00000000
--- a/alliance/share/cells/sxlib/buf_x4.ap
+++ /dev/null
@@ -1,72 +0,0 @@
-V ALLIANCE : 6
-H buf_x4,P,30/ 8/2000,100
-A 0,0,2500,5000
-R 1000,2000,ref_ref,i_20
-R 1000,2500,ref_ref,i_25
-R 1000,3000,ref_ref,i_30
-R 1000,3500,ref_ref,i_35
-R 1000,4000,ref_ref,i_40
-R 1500,2000,ref_ref,q_20
-R 1500,3000,ref_ref,q_30
-R 1500,3500,ref_ref,q_35
-R 1500,4000,ref_ref,q_40
-R 1500,1500,ref_ref,q_15
-R 1500,2500,ref_ref,q_25
-R 1500,1000,ref_ref,q_10
-R 1000,1500,ref_ref,i_15
-R 1000,1000,ref_ref,i_10
-S 1500,1000,1500,4000,200,q,DOWN,CALU1
-S 1000,1000,1000,4000,200,i,DOWN,CALU1
-S 1500,1000,1500,4000,200,*,UP,ALU1
-S 0,3900,2500,3900,2400,*,RIGHT,NWELL
-S 800,2500,1000,2500,200,*,RIGHT,ALU1
-S 2100,300,2100,1200,300,*,UP,NDIF
-S 1500,300,1500,1200,300,*,UP,NDIF
-S 1800,100,1800,1400,100,*,DOWN,NTRANS
-S 900,300,900,1200,300,*,UP,NDIF
-S 1200,100,1200,1400,100,*,DOWN,NTRANS
-S 600,600,600,1400,100,*,DOWN,NTRANS
-S 300,800,300,1200,300,*,UP,NDIF
-S 300,2800,300,3700,300,*,DOWN,PDIF
-S 1200,2600,1200,4900,100,*,UP,PTRANS
-S 1800,2600,1800,4900,100,*,UP,PTRANS
-S 1500,2800,1500,4700,300,*,DOWN,PDIF
-S 900,2800,900,4700,300,*,DOWN,PDIF
-S 600,2600,600,3900,100,*,UP,PTRANS
-S 2100,2800,2100,4700,300,*,DOWN,PDIF
-S 300,4200,300,4700,300,*,DOWN,NTIE
-S 1800,1400,1800,2600,100,*,DOWN,POLY
-S 1200,1400,1200,2600,100,*,DOWN,POLY
-S 600,2500,800,2500,300,*,RIGHT,POLY
-S 300,4200,300,4700,200,*,DOWN,ALU1
-S 0,4700,2500,4700,600,vdd,RIGHT,CALU1
-S 2100,3000,2100,4500,200,*,DOWN,ALU1
-S 0,300,2500,300,600,vss,RIGHT,CALU1
-S 2100,500,2100,1000,200,*,DOWN,ALU1
-S 300,2000,1800,2000,300,*,RIGHT,POLY
-S 600,1500,800,1500,300,*,RIGHT,POLY
-S 800,1500,1000,1500,200,*,RIGHT,ALU1
-S 1000,1000,1000,4000,100,*,DOWN,ALU1
-S 300,1000,300,3500,100,*,DOWN,ALU1
-V 2100,1000,CONT_DIF_N,*
-V 1500,1000,CONT_DIF_N,*
-V 300,1000,CONT_DIF_N,*
-V 900,500,CONT_DIF_N,*
-V 2100,500,CONT_DIF_N,*
-V 2100,4000,CONT_DIF_P,*
-V 2100,4500,CONT_DIF_P,*
-V 900,4500,CONT_DIF_P,*
-V 300,3000,CONT_DIF_P,*
-V 2100,3500,CONT_DIF_P,*
-V 2100,3000,CONT_DIF_P,*
-V 300,4700,CONT_BODY_N,*
-V 300,4200,CONT_BODY_N,*
-V 300,300,CONT_BODY_P,*
-V 800,2500,CONT_POLY,*
-V 300,2000,CONT_POLY,*
-V 800,1500,CONT_POLY,*
-V 1500,3000,CONT_DIF_P,*
-V 1500,3500,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 300,3500,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/buf_x4.sym b/alliance/share/cells/sxlib/buf_x4.sym
deleted file mode 100644
index d4472e27..00000000
Binary files a/alliance/share/cells/sxlib/buf_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/buf_x4.vbe b/alliance/share/cells/sxlib/buf_x4.vbe
deleted file mode 100644
index 0b7726ef..00000000
--- a/alliance/share/cells/sxlib/buf_x4.vbe
+++ /dev/null
@@ -1,26 +0,0 @@
-ENTITY buf_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 1250;
-  CONSTANT cin_i	 : NATURAL := 9;
-  CONSTANT rdown_i_q	 : NATURAL := 810;
-  CONSTANT rup_i_q	 : NATURAL := 890;
-  CONSTANT tphh_i_q	 : NATURAL := 379;
-  CONSTANT tpll_i_q	 : NATURAL := 409;
-  CONSTANT transistors	 : NATURAL := 6
-);
-PORT (
-  i	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END buf_x4;
-
-ARCHITECTURE behaviour_data_flow OF buf_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on buf_x4"
-  SEVERITY WARNING;
-  q <= i after 1000 ps;
-END;
diff --git a/alliance/share/cells/sxlib/buf_x4.vhd b/alliance/share/cells/sxlib/buf_x4.vhd
deleted file mode 100644
index 208df74a..00000000
--- a/alliance/share/cells/sxlib/buf_x4.vhd
+++ /dev/null
@@ -1,19 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY buf_x4 IS
-PORT(
-  i	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END buf_x4;
-
-ARCHITECTURE RTL OF buf_x4 IS
-BEGIN
-  q <= i;
-END RTL;
diff --git a/alliance/share/cells/sxlib/buf_x8.al b/alliance/share/cells/sxlib/buf_x8.al
deleted file mode 100644
index 55ee04cf..00000000
--- a/alliance/share/cells/sxlib/buf_x8.al
+++ /dev/null
@@ -1,27 +0,0 @@
-V ALLIANCE : 6
-H buf_x8,L,30/10/99
-C i,IN,EXTERNAL,5
-C q,OUT,EXTERNAL,1
-C vdd,IN,EXTERNAL,4
-C vss,IN,EXTERNAL,2
-T P,0.35,5.9,1,3,4,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00010
-T P,0.35,5.9,4,3,1,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00009
-T P,0.35,5.9,1,3,4,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00008
-T P,0.35,5.9,4,3,1,0,0.75,0.75,13.3,13.3,9,11.25,tr_00007
-T P,0.35,5.9,4,5,3,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00006
-T N,0.35,2.9,1,3,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00005
-T N,0.35,2.9,2,3,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00004
-T N,0.35,2.9,2,3,1,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00003
-T N,0.35,2.9,1,3,2,0,0.75,0.75,7.3,7.3,9,2.25,tr_00002
-T N,0.35,2.9,3,5,2,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00001
-S 5,EXTERNAL,i
-Q 0.00373582
-S 4,EXTERNAL,vdd
-Q 0.00782917
-S 3,INTERNAL
-Q 0.00908482
-S 2,EXTERNAL,vss
-Q 0.00647781
-S 1,EXTERNAL,q
-Q 0.00599301
-EOF
diff --git a/alliance/share/cells/sxlib/buf_x8.ap b/alliance/share/cells/sxlib/buf_x8.ap
deleted file mode 100644
index 4e80fba3..00000000
--- a/alliance/share/cells/sxlib/buf_x8.ap
+++ /dev/null
@@ -1,99 +0,0 @@
-V ALLIANCE : 6
-H buf_x8,P,30/ 8/2000,100
-A 0,0,4000,5000
-R 1000,2000,ref_ref,i_20
-R 1000,2500,ref_ref,i_25
-R 1000,3000,ref_ref,i_30
-R 1000,3500,ref_ref,i_35
-R 1000,4000,ref_ref,i_40
-R 1000,1500,ref_ref,i_15
-R 1000,1000,ref_ref,i_10
-R 1500,1500,ref_ref,q_15
-R 1500,2500,ref_ref,q_25
-R 1500,1000,ref_ref,q_10
-R 1500,4000,ref_ref,q_40
-R 1500,3500,ref_ref,q_35
-R 1500,3000,ref_ref,q_30
-R 1500,2000,ref_ref,q_20
-S 1000,1000,1000,4000,200,i,DOWN,CALU1
-S 1500,1000,1500,4000,200,q,DOWN,CALU1
-S 1500,1000,1500,4000,200,*,UP,ALU1
-S 2700,1000,2700,4000,200,*,UP,ALU1
-S 1500,2000,2700,2000,200,*,RIGHT,ALU1
-S 0,3900,4000,3900,2400,*,RIGHT,NWELL
-S 800,2500,1000,2500,200,*,RIGHT,ALU1
-S 2100,300,2100,1200,300,*,UP,NDIF
-S 1500,300,1500,1200,300,*,UP,NDIF
-S 1800,100,1800,1400,100,*,DOWN,NTRANS
-S 900,300,900,1200,300,*,UP,NDIF
-S 1200,100,1200,1400,100,*,DOWN,NTRANS
-S 1200,2600,1200,4900,100,*,UP,PTRANS
-S 1800,2600,1800,4900,100,*,UP,PTRANS
-S 1500,2800,1500,4700,300,*,DOWN,PDIF
-S 900,2800,900,4700,300,*,DOWN,PDIF
-S 1800,1400,1800,2600,100,*,DOWN,POLY
-S 1200,1400,1200,2600,100,*,DOWN,POLY
-S 2100,3000,2100,4500,200,*,DOWN,ALU1
-S 2100,500,2100,1000,200,*,DOWN,ALU1
-S 2400,2600,2400,4900,100,*,UP,PTRANS
-S 2400,1400,2400,2600,100,*,DOWN,POLY
-S 2400,100,2400,1400,100,*,DOWN,NTRANS
-S 2700,300,2700,1200,300,*,UP,NDIF
-S 3300,300,3300,1200,300,*,UP,NDIF
-S 2700,2800,2700,4700,300,*,DOWN,PDIF
-S 2100,2800,2100,4700,300,*,DOWN,PDIF
-S 3000,100,3000,1400,100,*,DOWN,NTRANS
-S 3000,2600,3000,4900,100,*,UP,PTRANS
-S 0,300,4000,300,600,vss,RIGHT,CALU1
-S 0,4700,4000,4700,600,vdd,RIGHT,CALU1
-S 3000,1400,3000,2600,100,*,DOWN,POLY
-S 3300,4000,3300,4700,300,*,DOWN,PDIF
-S 3700,2900,3700,3400,300,*,DOWN,NTIE
-S 600,100,600,1400,100,*,DOWN,NTRANS
-S 600,2600,600,4900,100,*,UP,PTRANS
-S 300,2800,300,4700,300,*,DOWN,PDIF
-S 300,300,300,1200,300,*,UP,NDIF
-S 3200,1700,3800,1700,300,*,RIGHT,PTIE
-S 300,1000,300,4000,100,*,DOWN,ALU1
-S 300,2000,3000,2000,300,*,RIGHT,POLY
-S 600,2500,800,2500,300,*,RIGHT,POLY
-S 600,1500,800,1500,300,*,RIGHT,POLY
-S 800,1500,1000,1500,200,*,RIGHT,ALU1
-S 1000,1000,1000,4000,100,*,DOWN,ALU1
-S 3300,500,3300,1700,200,*,UP,ALU1
-S 3300,1700,3700,1700,200,*,RIGHT,ALU1
-S 3700,2900,3700,3400,200,*,DOWN,ALU1
-S 3250,3400,3700,3400,200,*,RIGHT,ALU1
-S 3300,3350,3300,4500,200,*,DOWN,ALU1
-V 2100,1000,CONT_DIF_N,*
-V 300,1000,CONT_DIF_N,*
-V 900,500,CONT_DIF_N,*
-V 2100,500,CONT_DIF_N,*
-V 2100,4000,CONT_DIF_P,*
-V 2100,4500,CONT_DIF_P,*
-V 900,4500,CONT_DIF_P,*
-V 300,3000,CONT_DIF_P,*
-V 2100,3500,CONT_DIF_P,*
-V 2100,3000,CONT_DIF_P,*
-V 800,2500,CONT_POLY,*
-V 3300,500,CONT_DIF_N,*
-V 3300,1000,CONT_DIF_N,*
-V 3300,4000,CONT_DIF_P,*
-V 3300,4500,CONT_DIF_P,*
-V 3700,2900,CONT_BODY_N,*
-V 3700,3400,CONT_BODY_N,*
-V 3300,1700,CONT_BODY_P,*
-V 3700,1700,CONT_BODY_P,*
-V 300,3500,CONT_DIF_P,*
-V 300,4000,CONT_DIF_P,*
-V 300,2000,CONT_POLY,*
-V 800,1500,CONT_POLY,*
-V 1500,1000,CONT_DIF_N,*
-V 2700,3000,CONT_DIF_P,*
-V 2700,4000,CONT_DIF_P,*
-V 2700,3500,CONT_DIF_P,*
-V 2700,1000,CONT_DIF_N,*
-V 1500,3000,CONT_DIF_P,*
-V 1500,3500,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/buf_x8.sym b/alliance/share/cells/sxlib/buf_x8.sym
deleted file mode 100644
index 21c53cae..00000000
Binary files a/alliance/share/cells/sxlib/buf_x8.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/buf_x8.vbe b/alliance/share/cells/sxlib/buf_x8.vbe
deleted file mode 100644
index 3b2ecc3b..00000000
--- a/alliance/share/cells/sxlib/buf_x8.vbe
+++ /dev/null
@@ -1,26 +0,0 @@
-ENTITY buf_x8 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 2000;
-  CONSTANT cin_i	 : NATURAL := 15;
-  CONSTANT rdown_i_q	 : NATURAL := 400;
-  CONSTANT rup_i_q	 : NATURAL := 450;
-  CONSTANT tphh_i_q	 : NATURAL := 343;
-  CONSTANT tpll_i_q	 : NATURAL := 396;
-  CONSTANT transistors	 : NATURAL := 10
-);
-PORT (
-  i	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END buf_x8;
-
-ARCHITECTURE behaviour_data_flow OF buf_x8 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on buf_x8"
-  SEVERITY WARNING;
-  q <= i after 1000 ps;
-END;
diff --git a/alliance/share/cells/sxlib/buf_x8.vhd b/alliance/share/cells/sxlib/buf_x8.vhd
deleted file mode 100644
index cf5f0e48..00000000
--- a/alliance/share/cells/sxlib/buf_x8.vhd
+++ /dev/null
@@ -1,19 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY buf_x8 IS
-PORT(
-  i	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END buf_x8;
-
-ARCHITECTURE RTL OF buf_x8 IS
-BEGIN
-  q <= i;
-END RTL;
diff --git a/alliance/share/cells/sxlib/fulladder_x2.al b/alliance/share/cells/sxlib/fulladder_x2.al
deleted file mode 100644
index 10a81b4e..00000000
--- a/alliance/share/cells/sxlib/fulladder_x2.al
+++ /dev/null
@@ -1,100 +0,0 @@
-V ALLIANCE : 6
-H fulladder_x2,L,30/10/99
-C a1,UNKNOWN,EXTERNAL,9
-C a2,UNKNOWN,EXTERNAL,10
-C a3,UNKNOWN,EXTERNAL,16
-C a4,UNKNOWN,EXTERNAL,21
-C b1,UNKNOWN,EXTERNAL,7
-C b2,UNKNOWN,EXTERNAL,6
-C b3,UNKNOWN,EXTERNAL,23
-C b4,UNKNOWN,EXTERNAL,24
-C cin1,IN,EXTERNAL,8
-C cin2,IN,EXTERNAL,22
-C cin3,IN,EXTERNAL,20
-C cout,OUT,EXTERNAL,11
-C sout,OUT,EXTERNAL,12
-C vdd,IN,EXTERNAL,14
-C vss,IN,EXTERNAL,1
-T P,0.35,2,27,24,25,0,0.75,0.75,5.5,5.5,28.2,10.8,tr_00028
-T P,0.35,2,25,21,26,0,0.75,0.75,5.5,5.5,26.7,10.8,tr_00027
-T P,0.35,2,26,20,15,0,0.75,0.75,5.5,5.5,25.2,10.8,tr_00026
-T P,0.35,2.6,15,2,27,0,0.75,0.75,6.7,6.7,23.4,11.1,tr_00025
-T P,0.35,2,27,22,14,0,0.75,0.75,5.5,5.5,21.6,11.4,tr_00024
-T P,0.35,2,14,23,27,0,0.75,0.75,5.5,5.5,20.1,11.4,tr_00023
-T P,0.35,2,27,16,14,0,0.75,0.75,5.5,5.5,18.3,11.4,tr_00022
-T P,0.35,2.6,14,9,13,0,0.75,0.75,6.7,6.7,1.8,11.1,tr_00021
-T P,0.35,3.8,13,6,5,0,0.75,0.75,9.1,9.1,8.7,10.5,tr_00020
-T P,0.35,3.8,5,10,2,0,0.75,0.75,9.1,9.1,7.2,10.5,tr_00019
-T P,0.35,2.6,2,8,13,0,0.75,0.75,6.7,6.7,5.4,11.1,tr_00018
-T P,0.35,2.6,13,7,14,0,0.75,0.75,6.7,6.7,3.6,11.1,tr_00017
-T P,0.35,5.9,14,2,11,0,0.75,0.75,13.3,13.3,12.3,11.25,tr_00016
-T P,0.35,5.9,12,15,14,0,0.75,0.75,13.3,13.3,14.1,11.25,tr_00015
-T N,0.35,1.4,17,2,15,0,0.75,0.75,4.3,4.3,23.1,3.3,tr_00014
-T N,0.35,1.1,1,24,17,0,0.75,0.75,3.7,3.7,28.2,3.15,tr_00013
-T N,0.35,1.1,1,20,17,0,0.75,0.75,3.7,3.7,24.9,3.15,tr_00012
-T N,0.35,1.1,17,21,1,0,0.75,0.75,3.7,3.7,26.4,3.15,tr_00011
-T N,0.35,1.1,18,23,19,0,0.75,0.75,3.7,3.7,19.8,3.15,tr_00010
-T N,0.35,1.1,19,16,1,0,0.75,0.75,3.7,3.7,18.3,3.15,tr_00009
-T N,0.35,1.1,15,22,18,0,0.75,0.75,3.7,3.7,21.3,3.15,tr_00008
-T N,0.35,1.7,2,7,3,0,0.75,0.75,4.9,4.9,3.3,3.45,tr_00007
-T N,0.35,1.4,3,9,1,0,0.75,0.75,4.3,4.3,1.8,3.3,tr_00006
-T N,0.35,1.1,4,8,2,0,0.75,0.75,3.7,3.7,5.1,3.15,tr_00005
-T N,0.35,1.1,1,10,4,0,0.75,0.75,3.7,3.7,6.9,3.15,tr_00004
-T N,0.35,1.1,4,6,1,0,0.75,0.75,3.7,3.7,8.7,3.15,tr_00003
-T N,0.35,2.9,11,2,1,0,0.75,0.75,7.3,7.3,12.3,2.25,tr_00002
-T N,0.35,2.9,1,15,12,0,0.75,0.75,7.3,7.3,14.1,2.25,tr_00001
-S 27,INTERNAL
-Q 0.00250174
-S 26,INTERNAL
-Q 0
-S 25,INTERNAL
-Q 0
-S 24,EXTERNAL,b4
-Q 0.00295462
-S 23,EXTERNAL,b3
-Q 0.00296195
-S 22,EXTERNAL,cin2
-Q 0.00296195
-S 21,EXTERNAL,a4
-Q 0.00310499
-S 20,EXTERNAL,cin3
-Q 0.00283471
-S 19,INTERNAL
-Q 0
-S 18,INTERNAL
-Q 0
-S 17,INTERNAL
-Q 0.00108534
-S 16,EXTERNAL,a3
-Q 0.00281157
-S 15,INTERNAL
-Q 0.00630209
-S 14,EXTERNAL,vdd
-Q 0.0105755
-S 13,INTERNAL
-Q 0.00227626
-S 12,EXTERNAL,sout
-Q 0.00211518
-S 11,EXTERNAL,cout
-Q 0.00276149
-S 10,EXTERNAL,a2
-Q 0.00262649
-S 9,EXTERNAL,a1
-Q 0.00316706
-S 8,EXTERNAL,cin1
-Q 0.00311233
-S 7,EXTERNAL,b1
-Q 0.00311656
-S 6,EXTERNAL,b2
-Q 0.00239514
-S 5,INTERNAL
-Q 0
-S 4,INTERNAL
-Q 0.00114171
-S 3,INTERNAL
-Q 0
-S 2,INTERNAL
-Q 0.0112381
-S 1,EXTERNAL,vss
-Q 0.0111043
-EOF
diff --git a/alliance/share/cells/sxlib/fulladder_x2.ap b/alliance/share/cells/sxlib/fulladder_x2.ap
deleted file mode 100644
index 95608e04..00000000
--- a/alliance/share/cells/sxlib/fulladder_x2.ap
+++ /dev/null
@@ -1,275 +0,0 @@
-V ALLIANCE : 6
-H fulladder_x2,P, 6/ 9/2000,100
-A 0,0,10000,5000
-R 9500,3500,ref_ref,b4_35
-R 9000,3500,ref_ref,a4_35
-R 1000,3500,ref_ref,b1_35
-R 500,3500,ref_ref,a1_35
-R 500,1000,ref_ref,a1_10
-R 9500,3000,ref_ref,b4_30
-R 9500,2500,ref_ref,b4_25
-R 9500,2000,ref_ref,b4_20
-R 9500,1500,ref_ref,b4_15
-R 9000,3000,ref_ref,a4_30
-R 9000,2500,ref_ref,a4_25
-R 9000,2000,ref_ref,a4_20
-R 9000,1500,ref_ref,a4_15
-R 8500,3000,ref_ref,cin3_30
-R 8500,2500,ref_ref,cin3_25
-R 8500,2000,ref_ref,cin3_20
-R 8500,1500,ref_ref,cin3_15
-R 7000,3000,ref_ref,cin2_30
-R 7000,2500,ref_ref,cin2_25
-R 7000,2000,ref_ref,cin2_20
-R 7000,1500,ref_ref,cin2_15
-R 6500,3000,ref_ref,b3_30
-R 6500,2500,ref_ref,b3_25
-R 6500,2000,ref_ref,b3_20
-R 6500,1500,ref_ref,b3_15
-R 6000,3000,ref_ref,a3_30
-R 6000,2500,ref_ref,a3_25
-R 6000,2000,ref_ref,a3_20
-R 6000,1500,ref_ref,a3_15
-R 5000,3500,ref_ref,sout_35
-R 5000,3000,ref_ref,sout_30
-R 5000,2500,ref_ref,sout_25
-R 5000,2000,ref_ref,sout_20
-R 5000,1500,ref_ref,sout_15
-R 5000,1000,ref_ref,sout_10
-R 4000,1000,ref_ref,cout_10
-R 3500,3000,ref_ref,cout_30
-R 3500,2500,ref_ref,cout_25
-R 3500,2000,ref_ref,cout_20
-R 3500,1500,ref_ref,cout_15
-R 3000,3000,ref_ref,b2_30
-R 3000,2500,ref_ref,b2_25
-R 3000,2000,ref_ref,b2_20
-R 3000,1500,ref_ref,b2_15
-R 2500,3000,ref_ref,a2_30
-R 2500,2500,ref_ref,a2_25
-R 2500,2000,ref_ref,a2_20
-R 2500,1500,ref_ref,a2_15
-R 2000,3000,ref_ref,cin1_30
-R 2000,2500,ref_ref,cin1_25
-R 2000,2000,ref_ref,cin1_20
-R 2000,1500,ref_ref,cin1_15
-R 1000,3000,ref_ref,b1_30
-R 1000,2500,ref_ref,b1_25
-R 1000,2000,ref_ref,b1_20
-R 1000,1500,ref_ref,b1_15
-R 500,3000,ref_ref,a1_30
-R 500,2500,ref_ref,a1_25
-R 500,2000,ref_ref,a1_20
-R 500,1500,ref_ref,a1_15
-S 9100,900,9100,1200,300,*,UP,NDIF
-S 8000,900,8000,1200,300,*,UP,NDIF
-S 6400,3500,6400,4100,300,*,UP,PDIF
-S 300,3300,300,4100,300,*,UP,PDIF
-S 1500,3300,1500,4100,300,*,UP,PDIF
-S 6950,3600,6950,4650,200,*,UP,PDIF
-S 8550,450,8550,1200,200,*,UP,NDIF
-S 500,1000,500,3500,100,*,DOWN,ALU1
-S 1000,1500,1000,3500,100,*,UP,ALU1
-S 9000,1500,9000,3500,100,*,UP,ALU1
-S 9500,1500,9500,3500,100,*,DOWN,ALU1
-S 900,400,2000,400,300,*,RIGHT,PTIE
-S 300,500,300,1300,300,*,UP,NDIF
-S 7400,900,7400,1200,300,*,UP,NDIF
-S 7700,700,7700,1500,100,*,UP,NTRANS
-S 7700,1500,7700,3100,100,*,UP,POLY
-S 0,3900,10000,3900,2400,*,RIGHT,NWELL
-S 1600,4700,3200,4700,300,*,RIGHT,NTIE
-S 7600,4700,9200,4700,300,*,RIGHT,NTIE
-S 6400,400,7900,400,300,*,RIGHT,PTIE
-S 8400,2500,8400,3100,100,*,DOWN,POLY
-S 6100,1400,6100,3300,100,*,UP,POLY
-S 6600,1400,6600,3300,100,*,UP,POLY
-S 7100,1400,7100,3300,100,*,UP,POLY
-S 8900,1400,8900,3100,100,*,UP,POLY
-S 9400,1400,9400,3100,100,*,DOWN,POLY
-S 6600,3300,6700,3300,100,*,RIGHT,POLY
-S 7100,3300,7200,3300,100,*,RIGHT,POLY
-S 7700,3100,7800,3100,100,*,RIGHT,POLY
-S 9700,3300,9700,4000,300,*,UP,PDIF
-S 7500,3300,7500,4100,300,*,UP,PDIF
-S 8100,3300,8100,4100,200,*,UP,PDIF
-S 8700,3300,8700,3900,200,*,UP,PDIF
-S 9400,3100,9400,4100,100,*,UP,PTRANS
-S 8900,3100,8900,4100,100,*,UP,PTRANS
-S 8400,3100,8400,4100,100,*,UP,PTRANS
-S 7800,3100,7800,4300,100,*,UP,PTRANS
-S 5700,3500,5700,4600,400,*,UP,PDIF
-S 7200,3300,7200,4300,100,*,UP,PTRANS
-S 6700,3300,6700,4300,100,*,UP,PTRANS
-S 6100,3300,6100,4300,100,*,UP,PTRANS
-S 8300,1400,8300,2400,100,*,UP,POLY
-S 5800,500,5800,1200,300,*,UP,NDIF
-S 9700,1000,9700,1200,300,*,UP,NDIF
-S 9400,700,9400,1400,100,*,UP,NTRANS
-S 8300,700,8300,1400,100,*,UP,NTRANS
-S 8800,700,8800,1400,100,*,UP,NTRANS
-S 6600,700,6600,1400,100,*,UP,NTRANS
-S 6100,700,6100,1400,100,*,UP,NTRANS
-S 7100,700,7100,1400,100,*,UP,NTRANS
-S 8800,1400,8900,1400,100,*,RIGHT,POLY
-S 1100,700,1100,1600,100,*,UP,NTRANS
-S 600,1500,600,3100,100,*,UP,POLY
-S 1000,2000,1200,2000,100,*,LEFT,POLY
-S 1700,2500,2000,2500,100,*,RIGHT,POLY
-S 1700,1400,1700,2500,100,*,UP,POLY
-S 1800,2400,1800,3100,100,*,UP,POLY
-S 1100,1600,1100,2000,100,*,UP,POLY
-S 1200,2000,1200,3100,100,*,UP,POLY
-S 2100,2900,2100,4100,200,*,UP,PDIF
-S 2900,1400,2900,2700,100,*,UP,POLY
-S 2400,1900,2400,2700,100,*,UP,POLY
-S 900,3300,900,4450,300,*,UP,PDIF
-S 600,3100,600,4300,100,*,UP,PTRANS
-S 3200,2900,3200,4100,300,*,UP,PDIF
-S 2700,2900,2700,4100,200,*,UP,PDIF
-S 2900,2700,2900,4300,100,*,UP,PTRANS
-S 2400,2700,2400,4300,100,*,UP,PTRANS
-S 1800,3100,1800,4300,100,*,UP,PTRANS
-S 1200,3100,1200,4300,100,*,UP,PTRANS
-S 2300,1400,2300,1900,100,*,UP,POLY
-S 3200,900,3200,1200,300,*,UP,NDIF
-S 2600,500,2600,1200,300,*,UP,NDIF
-S 2000,900,2000,1200,300,*,UP,NDIF
-S 1400,900,1400,1400,300,*,UP,NDIF
-S 600,700,600,1500,100,*,UP,NTRANS
-S 1700,700,1700,1400,100,*,UP,NTRANS
-S 2300,700,2300,1400,100,*,UP,NTRANS
-S 2900,700,2900,1400,100,*,UP,NTRANS
-S 0,300,10000,300,600,vss,RIGHT,CALU1
-S 0,4700,10000,4700,600,vdd,RIGHT,CALU1
-S 8000,1500,8000,3550,100,*,UP,ALU1
-S 7500,950,7500,1500,100,*,UP,ALU1
-S 9200,400,9600,400,300,*,RIGHT,PTIE
-S 8300,2400,8400,2400,100,*,RIGHT,POLY
-S 9700,300,9700,1000,200,*,DOWN,ALU1
-S 7500,2000,7500,3500,100,*,UP,ALU1
-S 8000,1000,9100,1000,100,*,RIGHT,ALU1
-S 6400,4000,9700,4000,100,*,RIGHT,ALU1
-S 2000,1000,3200,1000,100,*,RIGHT,ALU1
-S 300,4000,3200,4000,100,*,RIGHT,ALU1
-S 2300,1900,2400,1900,100,*,RIGHT,POLY
-S 1500,1000,1500,3500,100,*,UP,ALU1
-S 2000,1500,2000,3000,100,*,DOWN,ALU1
-S 2500,1500,2500,3000,100,*,UP,ALU1
-S 3000,1500,3000,3000,100,*,UP,ALU1
-S 7500,1500,8000,1500,100,*,RIGHT,ALU1
-S 3800,300,3800,1200,300,*,UP,NDIF
-S 4400,300,4400,1200,300,*,UP,NDIF
-S 4100,100,4100,1400,100,*,DOWN,NTRANS
-S 4700,100,4700,1400,100,*,DOWN,NTRANS
-S 5000,300,5000,1200,300,*,UP,NDIF
-S 3800,2800,3800,4700,300,*,DOWN,PDIF
-S 4400,2800,4400,4700,300,*,DOWN,PDIF
-S 4100,2600,4100,4900,100,*,UP,PTRANS
-S 4700,2600,4700,4900,100,*,UP,PTRANS
-S 5000,2800,5000,4700,300,*,DOWN,PDIF
-S 5500,1000,7400,1000,100,*,RIGHT,ALU1
-S 4100,1400,4100,2600,100,*,UP,POLY
-S 4700,1400,4700,2600,100,*,UP,POLY
-S 4700,2000,5500,2000,100,*,LEFT,POLY
-S 3450,3000,3800,3000,200,*,LEFT,ALU1
-S 3500,1450,3500,3050,200,*,DOWN,ALU1
-S 3800,1000,4000,1000,200,*,LEFT,ALU1
-S 6000,1500,6000,3000,100,*,DOWN,ALU1
-S 6500,1500,6500,3000,100,*,DOWN,ALU1
-S 7000,1500,7000,3000,100,*,UP,ALU1
-S 8500,1500,8500,3000,100,*,UP,ALU1
-S 5500,1000,5500,2000,100,*,DOWN,ALU1
-S 4300,2500,4400,2500,100,*,RIGHT,ALU1
-S 4400,2500,4400,4000,100,*,UP,ALU1
-S 4400,4000,5600,4000,100,*,RIGHT,ALU1
-S 5600,3500,5600,4000,100,*,DOWN,ALU1
-S 5600,3500,7500,3500,100,*,RIGHT,ALU1
-S 1500,3500,4400,3500,100,*,LEFT,ALU1
-S 5000,1000,5000,3500,200,*,UP,ALU1
-S 9500,1500,9500,3500,200,b4,DOWN,CALU1
-S 9000,1500,9000,3500,200,a4,DOWN,CALU1
-S 1000,1500,1000,3500,200,b1,DOWN,CALU1
-S 500,1000,500,3500,200,a1,DOWN,CALU1
-S 8500,1500,8500,3000,200,cin3,DOWN,CALU1
-S 7000,1500,7000,3000,200,cin2,DOWN,CALU1
-S 6500,1500,6500,3000,200,b3,DOWN,CALU1
-S 6000,1500,6000,3000,200,a3,DOWN,CALU1
-S 5000,1000,5000,3500,200,sout,DOWN,CALU1
-S 3000,1500,3000,3000,200,b2,DOWN,CALU1
-S 2500,1500,2500,3000,200,a2,DOWN,CALU1
-S 2000,1500,2000,3000,200,cin1,DOWN,CALU1
-S 3500,1500,3500,3000,200,cout,DOWN,CALU1
-S 4000,1000,4000,1500,200,cout,DOWN,CALU1
-S 4000,1000,4000,1550,200,*,DOWN,ALU1
-S 3450,1500,4050,1500,200,*,RIGHT,ALU1
-S 1000,2000,1200,2000,300,*,RIGHT,POLY
-S 1700,2500,2000,2500,300,*,LEFT,POLY
-S 4100,2500,4300,2500,300,*,LEFT,POLY
-S 7500,2000,7700,2000,300,*,RIGHT,POLY
-V 6950,4600,CONT_DIF_P,*
-V 8550,400,CONT_DIF_N,*
-V 1500,400,CONT_BODY_P,*
-V 1000,400,CONT_BODY_P,*
-V 300,500,CONT_DIF_N,*
-V 1600,4700,CONT_BODY_N,*
-V 2000,4700,CONT_BODY_N,*
-V 2400,4700,CONT_BODY_N,*
-V 2800,4700,CONT_BODY_N,*
-V 3200,4700,CONT_BODY_N,*
-V 9200,4700,CONT_BODY_N,*
-V 8800,4700,CONT_BODY_N,*
-V 8400,4700,CONT_BODY_N,*
-V 8000,4700,CONT_BODY_N,*
-V 7600,4700,CONT_BODY_N,*
-V 3200,400,CONT_BODY_P,*
-V 7400,400,CONT_BODY_P,*
-V 6900,400,CONT_BODY_P,*
-V 6400,400,CONT_BODY_P,*
-V 3000,2500,CONT_POLY,*
-V 7500,4000,CONT_DIF_P,*
-V 6350,4700,CONT_BODY_N,*
-V 6400,4000,CONT_DIF_P,*
-V 9700,4000,CONT_DIF_P,*
-V 8100,3500,CONT_DIF_P,*
-V 5800,500,CONT_DIF_N,*
-V 9700,1000,CONT_DIF_N,*
-V 9100,1000,CONT_DIF_N,*
-V 8000,1000,CONT_DIF_N,*
-V 7400,1000,CONT_DIF_N,*
-V 7950,400,CONT_BODY_P,*
-V 9600,400,CONT_BODY_P,*
-V 9200,400,CONT_BODY_P,*
-V 8500,2500,CONT_POLY,*
-V 6000,2000,CONT_POLY,*
-V 6500,2000,CONT_POLY,*
-V 7000,2000,CONT_POLY,*
-V 7500,2000,CONT_POLY,*
-V 9500,2000,CONT_POLY,*
-V 9000,2500,CONT_POLY,*
-V 2100,3500,CONT_DIF_P,*
-V 2600,500,CONT_DIF_N,*
-V 3200,1000,CONT_DIF_N,*
-V 2000,1000,CONT_DIF_N,*
-V 900,4500,CONT_DIF_P,*
-V 300,4700,CONT_BODY_N,*
-V 1500,4000,CONT_DIF_P,*
-V 300,4000,CONT_DIF_P,*
-V 3200,4000,CONT_DIF_P,*
-V 500,2000,CONT_POLY,*
-V 1000,2000,CONT_POLY,*
-V 2500,2000,CONT_POLY,*
-V 2000,400,CONT_BODY_P,*
-V 2000,2500,CONT_POLY,*
-V 1400,1000,CONT_DIF_N,*
-V 3800,1000,CONT_DIF_N,*
-V 5000,1000,CONT_DIF_N,*
-V 4400,500,CONT_DIF_N,*
-V 4400,4500,CONT_DIF_P,*
-V 3800,3000,CONT_DIF_P,*
-V 5000,3000,CONT_DIF_P,*
-V 5500,2000,CONT_POLY,*
-V 4300,2500,CONT_POLY,*
-V 5000,3500,CONT_DIF_P,*
-V 5700,4500,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/fulladder_x2.vbe b/alliance/share/cells/sxlib/fulladder_x2.vbe
deleted file mode 100644
index 1df49a55..00000000
--- a/alliance/share/cells/sxlib/fulladder_x2.vbe
+++ /dev/null
@@ -1,121 +0,0 @@
-ENTITY fulladder_x2 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 5000;
-  CONSTANT cin_a1	 : NATURAL := 8;
-  CONSTANT cin_a2	 : NATURAL := 8;
-  CONSTANT cin_a3	 : NATURAL := 6;
-  CONSTANT cin_a4	 : NATURAL := 6;
-  CONSTANT cin_b1	 : NATURAL := 8;
-  CONSTANT cin_b2	 : NATURAL := 8;
-  CONSTANT cin_b3	 : NATURAL := 6;
-  CONSTANT cin_b4	 : NATURAL := 6;
-  CONSTANT cin_cin1	 : NATURAL := 7;
-  CONSTANT cin_cin2	 : NATURAL := 6;
-  CONSTANT cin_cin3	 : NATURAL := 6;
-  CONSTANT rdown_a1_cout	 : NATURAL := 1620;
-  CONSTANT rdown_a1_sout	 : NATURAL := 1620;
-  CONSTANT rdown_a2_cout	 : NATURAL := 1620;
-  CONSTANT rdown_a2_sout	 : NATURAL := 1620;
-  CONSTANT rdown_a3_sout	 : NATURAL := 1620;
-  CONSTANT rdown_a4_sout	 : NATURAL := 1620;
-  CONSTANT rdown_b1_cout	 : NATURAL := 1620;
-  CONSTANT rdown_b1_sout	 : NATURAL := 1620;
-  CONSTANT rdown_b2_cout	 : NATURAL := 1620;
-  CONSTANT rdown_b2_sout	 : NATURAL := 1620;
-  CONSTANT rdown_b3_sout	 : NATURAL := 1620;
-  CONSTANT rdown_b4_sout	 : NATURAL := 1620;
-  CONSTANT rdown_cin1_cout	 : NATURAL := 1620;
-  CONSTANT rdown_cin1_sout	 : NATURAL := 1620;
-  CONSTANT rdown_cin2_sout	 : NATURAL := 1620;
-  CONSTANT rdown_cin3_sout	 : NATURAL := 1620;
-  CONSTANT rup_a1_cout	 : NATURAL := 1790;
-  CONSTANT rup_a1_sout	 : NATURAL := 1790;
-  CONSTANT rup_a2_cout	 : NATURAL := 1790;
-  CONSTANT rup_a2_sout	 : NATURAL := 1790;
-  CONSTANT rup_a3_sout	 : NATURAL := 1790;
-  CONSTANT rup_a4_sout	 : NATURAL := 1790;
-  CONSTANT rup_b1_cout	 : NATURAL := 1790;
-  CONSTANT rup_b1_sout	 : NATURAL := 1790;
-  CONSTANT rup_b2_cout	 : NATURAL := 1790;
-  CONSTANT rup_b2_sout	 : NATURAL := 1790;
-  CONSTANT rup_b3_sout	 : NATURAL := 1790;
-  CONSTANT rup_b4_sout	 : NATURAL := 1790;
-  CONSTANT rup_cin1_cout	 : NATURAL := 1790;
-  CONSTANT rup_cin1_sout	 : NATURAL := 1790;
-  CONSTANT rup_cin2_sout	 : NATURAL := 1790;
-  CONSTANT rup_cin3_sout	 : NATURAL := 1790;
-  CONSTANT tphh_cin3_sout	 : NATURAL := 489;
-  CONSTANT tphh_a4_sout	 : NATURAL := 536;
-  CONSTANT tphh_b4_sout	 : NATURAL := 581;
-  CONSTANT tphh_a2_cout	 : NATURAL := 658;
-  CONSTANT tpll_cin1_cout	 : NATURAL := 694;
-  CONSTANT tphh_a1_cout	 : NATURAL := 699;
-  CONSTANT tpll_b1_cout	 : NATURAL := 709;
-  CONSTANT tpll_a1_cout	 : NATURAL := 736;
-  CONSTANT tphh_cin1_cout	 : NATURAL := 742;
-  CONSTANT tpll_b2_cout	 : NATURAL := 748;
-  CONSTANT tphh_b2_cout	 : NATURAL := 751;
-  CONSTANT tphh_b1_cout	 : NATURAL := 777;
-  CONSTANT tpll_a2_cout	 : NATURAL := 782;
-  CONSTANT tpll_cin2_sout	 : NATURAL := 893;
-  CONSTANT tphh_a3_sout	 : NATURAL := 902;
-  CONSTANT tpll_b3_sout	 : NATURAL := 951;
-  CONSTANT tpll_a3_sout	 : NATURAL := 1008;
-  CONSTANT tphh_b3_sout	 : NATURAL := 1014;
-  CONSTANT tpll_b4_sout	 : NATURAL := 1071;
-  CONSTANT tpll_a4_sout	 : NATURAL := 1114;
-  CONSTANT tphh_cin2_sout	 : NATURAL := 1116;
-  CONSTANT tphl_a2_sout	 : NATURAL := 1128;
-  CONSTANT tpll_cin3_sout	 : NATURAL := 1149;
-  CONSTANT tplh_cin1_sout	 : NATURAL := 1163;
-  CONSTANT tphl_a1_sout	 : NATURAL := 1169;
-  CONSTANT tplh_b1_sout	 : NATURAL := 1178;
-  CONSTANT tplh_a1_sout	 : NATURAL := 1205;
-  CONSTANT tphl_cin1_sout	 : NATURAL := 1212;
-  CONSTANT tplh_b2_sout	 : NATURAL := 1217;
-  CONSTANT tphl_b2_sout	 : NATURAL := 1221;
-  CONSTANT tphl_b1_sout	 : NATURAL := 1247;
-  CONSTANT tplh_a2_sout	 : NATURAL := 1251;
-  CONSTANT transistors	 : NATURAL := 28
-);
-PORT (
-  a1	 : in  BIT;
-  a2	 : in  BIT;
-  a3	 : in  BIT;
-  a4	 : in  BIT;
-  b1	 : in  BIT;
-  b2	 : in  BIT;
-  b3	 : in  BIT;
-  b4	 : in  BIT;
-  cin1	 : in  BIT;
-  cin2	 : in  BIT;
-  cin3	 : in  BIT;
-  cout	 : out BIT;
-  sout	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END fulladder_x2;
-
-ARCHITECTURE behaviour_data_flow OF fulladder_x2 IS
-  SIGNAL ncout	 : BIT;
-
-BEGIN
-  ASSERT ((((cin1 and cin2) and cin3) or not (((cin1 or cin2) or cin3))) = '1')
-  REPORT "cin1, cin2, cin3 must be connected together on fulladder_x2"
-  SEVERITY WARNING;
-  ASSERT (((((b1 and b2) and b3) and b4) or not ((((b1 or b2) or b3) or
-  b4))) = '1')
-  REPORT "b1, b2, b3, b4 must be connected together on fulladder_x2"
-  SEVERITY WARNING;
-  ASSERT (((((a1 and a2) and a3) and a4) or not ((((a1 or a2) or a3) or
-  a4))) = '1')
-  REPORT "a1, a2, a3, a4 must be connected together on fulladder_x2"
-  SEVERITY WARNING;
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on fulladder_x2"
-  SEVERITY WARNING;
-  ncout <= not (((a1 and b1) or ((a2 or b2) and cin1)));
-  sout <= (((a3 and b3) and cin2) or (((a4 or b4) or cin3) and ncout)) after 1900 ps;
-  cout <= not (ncout) after 1400 ps;
-END;
diff --git a/alliance/share/cells/sxlib/fulladder_x2.vhd b/alliance/share/cells/sxlib/fulladder_x2.vhd
deleted file mode 100644
index d9d8f757..00000000
--- a/alliance/share/cells/sxlib/fulladder_x2.vhd
+++ /dev/null
@@ -1,34 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY fulladder_x2 IS
-PORT(
-  a1	: IN STD_LOGIC;
-  a2	: IN STD_LOGIC;
-  a3	: IN STD_LOGIC;
-  a4	: IN STD_LOGIC;
-  b1	: IN STD_LOGIC;
-  b2	: IN STD_LOGIC;
-  b3	: IN STD_LOGIC;
-  b4	: IN STD_LOGIC;
-  cin1	: IN STD_LOGIC;
-  cin2	: IN STD_LOGIC;
-  cin3	: IN STD_LOGIC;
-  cout	: OUT STD_LOGIC;
-  sout	: OUT STD_LOGIC
-);
-END fulladder_x2;
-
-ARCHITECTURE RTL OF fulladder_x2 IS
-  SIGNAL ncout	: STD_LOGIC;
-
-BEGIN
-  cout <= NOT(ncout);
-  sout <= (((a3 AND b3) AND cin2) OR (((a4 OR b4) OR cin3) AND ncout));
-  ncout <= NOT(((a1 AND b1) OR ((a2 OR b2) AND cin1)));
-END RTL;
diff --git a/alliance/share/cells/sxlib/fulladder_x4.al b/alliance/share/cells/sxlib/fulladder_x4.al
deleted file mode 100644
index 777242de..00000000
--- a/alliance/share/cells/sxlib/fulladder_x4.al
+++ /dev/null
@@ -1,104 +0,0 @@
-V ALLIANCE : 6
-H fulladder_x4,L,30/10/99
-C a1,UNKNOWN,EXTERNAL,10
-C a2,UNKNOWN,EXTERNAL,9
-C a3,UNKNOWN,EXTERNAL,20
-C a4,UNKNOWN,EXTERNAL,24
-C b1,UNKNOWN,EXTERNAL,7
-C b2,UNKNOWN,EXTERNAL,8
-C b3,UNKNOWN,EXTERNAL,21
-C b4,UNKNOWN,EXTERNAL,23
-C cin1,IN,EXTERNAL,6
-C cin2,IN,EXTERNAL,22
-C cin3,IN,EXTERNAL,19
-C cout,OUT,EXTERNAL,11
-C sout,OUT,EXTERNAL,12
-C vdd,IN,EXTERNAL,13
-C vss,IN,EXTERNAL,1
-T P,0.35,5.9,11,3,13,0,0.75,0.75,13.3,13.3,12.3,11.25,tr_00032
-T P,0.35,2.6,14,7,13,0,0.75,0.75,6.7,6.7,3.6,11.1,tr_00031
-T P,0.35,2.6,3,6,14,0,0.75,0.75,6.7,6.7,5.4,11.1,tr_00030
-T P,0.35,3.8,5,9,3,0,0.75,0.75,9.1,9.1,7.2,10.5,tr_00029
-T P,0.35,3.8,14,8,5,0,0.75,0.75,9.1,9.1,8.7,10.5,tr_00028
-T P,0.35,2.6,13,10,14,0,0.75,0.75,6.7,6.7,1.8,11.1,tr_00027
-T P,0.35,5.9,13,3,11,0,0.75,0.75,13.3,13.3,14.1,11.25,tr_00026
-T P,0.35,5.9,13,15,12,0,0.75,0.75,13.3,13.3,17.7,11.25,tr_00025
-T P,0.35,5.9,12,15,13,0,0.75,0.75,13.3,13.3,15.9,11.25,tr_00024
-T P,0.35,2,13,21,25,0,0.75,0.75,5.5,5.5,21.6,11.4,tr_00023
-T P,0.35,2,25,22,13,0,0.75,0.75,5.5,5.5,23.1,11.4,tr_00022
-T P,0.35,2,25,23,27,0,0.75,0.75,5.5,5.5,29.7,10.8,tr_00021
-T P,0.35,2,27,24,26,0,0.75,0.75,5.5,5.5,28.2,10.8,tr_00020
-T P,0.35,2,25,20,13,0,0.75,0.75,5.5,5.5,19.8,11.4,tr_00019
-T P,0.35,2.6,15,3,25,0,0.75,0.75,6.7,6.7,24.9,11.1,tr_00018
-T P,0.35,2,26,19,15,0,0.75,0.75,5.5,5.5,26.7,10.8,tr_00017
-T N,0.35,2.9,1,3,11,0,0.75,0.75,7.3,7.3,12.3,2.25,tr_00016
-T N,0.35,1.1,2,8,1,0,0.75,0.75,3.7,3.7,8.7,3.15,tr_00015
-T N,0.35,1.1,1,9,2,0,0.75,0.75,3.7,3.7,6.9,3.15,tr_00014
-T N,0.35,1.1,2,6,3,0,0.75,0.75,3.7,3.7,5.1,3.15,tr_00013
-T N,0.35,1.4,4,10,1,0,0.75,0.75,4.3,4.3,1.8,3.3,tr_00012
-T N,0.35,1.7,3,7,4,0,0.75,0.75,4.9,4.9,3.3,3.45,tr_00011
-T N,0.35,2.9,11,3,1,0,0.75,0.75,7.3,7.3,14.1,2.25,tr_00010
-T N,0.35,2.9,12,15,1,0,0.75,0.75,7.3,7.3,17.7,2.25,tr_00009
-T N,0.35,2.9,1,15,12,0,0.75,0.75,7.3,7.3,15.9,2.25,tr_00008
-T N,0.35,1.4,16,3,15,0,0.75,0.75,4.3,4.3,24.6,3.3,tr_00007
-T N,0.35,1.1,1,23,16,0,0.75,0.75,3.7,3.7,29.7,3.15,tr_00006
-T N,0.35,1.1,15,22,17,0,0.75,0.75,3.7,3.7,22.8,3.15,tr_00005
-T N,0.35,1.1,17,21,18,0,0.75,0.75,3.7,3.7,21.3,3.15,tr_00004
-T N,0.35,1.1,16,24,1,0,0.75,0.75,3.7,3.7,27.9,3.15,tr_00003
-T N,0.35,1.1,1,19,16,0,0.75,0.75,3.7,3.7,26.4,3.15,tr_00002
-T N,0.35,1.1,18,20,1,0,0.75,0.75,3.7,3.7,19.8,3.15,tr_00001
-S 27,INTERNAL
-Q 0
-S 26,INTERNAL
-Q 0
-S 25,INTERNAL
-Q 0.00250174
-S 24,EXTERNAL,a4
-Q 0.00310499
-S 23,EXTERNAL,b4
-Q 0.00295462
-S 22,EXTERNAL,cin2
-Q 0.00296195
-S 21,EXTERNAL,b3
-Q 0.00296195
-S 20,EXTERNAL,a3
-Q 0.00252972
-S 19,EXTERNAL,cin3
-Q 0.00283471
-S 18,INTERNAL
-Q 0
-S 17,INTERNAL
-Q 0
-S 16,INTERNAL
-Q 0.00108534
-S 15,INTERNAL
-Q 0.00752047
-S 14,INTERNAL
-Q 0.00227626
-S 13,EXTERNAL,vdd
-Q 0.010917
-S 12,EXTERNAL,sout
-Q 0.00217394
-S 11,EXTERNAL,cout
-Q 0.00217394
-S 10,EXTERNAL,a1
-Q 0.00316706
-S 9,EXTERNAL,a2
-Q 0.00262649
-S 8,EXTERNAL,b2
-Q 0.00239514
-S 7,EXTERNAL,b1
-Q 0.00311656
-S 6,EXTERNAL,cin1
-Q 0.00311233
-S 5,INTERNAL
-Q 0
-S 4,INTERNAL
-Q 0
-S 3,INTERNAL
-Q 0.0135185
-S 2,INTERNAL
-Q 0.00114171
-S 1,EXTERNAL,vss
-Q 0.0122096
-EOF
diff --git a/alliance/share/cells/sxlib/fulladder_x4.ap b/alliance/share/cells/sxlib/fulladder_x4.ap
deleted file mode 100644
index a896b73d..00000000
--- a/alliance/share/cells/sxlib/fulladder_x4.ap
+++ /dev/null
@@ -1,286 +0,0 @@
-V ALLIANCE : 6
-H fulladder_x4,P, 6/ 9/2000,100
-A 0,0,10500,5000
-R 4500,3500,ref_ref,cout_35
-R 4500,1000,ref_ref,cout_10
-R 4500,3000,ref_ref,cout_30
-R 4500,2500,ref_ref,cout_25
-R 4500,2000,ref_ref,cout_20
-R 4500,1500,ref_ref,cout_15
-R 7000,2000,ref_ref,b3_20
-R 10000,1500,ref_ref,b4_15
-R 6500,3000,ref_ref,a3_30
-R 6500,2500,ref_ref,a3_25
-R 6500,2000,ref_ref,a3_20
-R 9000,1500,ref_ref,cin3_15
-R 7000,1500,ref_ref,b3_15
-R 9000,2000,ref_ref,cin3_20
-R 10000,3500,ref_ref,b4_35
-R 7500,3000,ref_ref,cin2_30
-R 7500,2500,ref_ref,cin2_25
-R 7500,2000,ref_ref,cin2_20
-R 7500,1500,ref_ref,cin2_15
-R 7000,3000,ref_ref,b3_30
-R 7000,2500,ref_ref,b3_25
-R 10000,2500,ref_ref,b4_25
-R 10000,2000,ref_ref,b4_20
-R 9500,3000,ref_ref,a4_30
-R 9500,2500,ref_ref,a4_25
-R 9500,2000,ref_ref,a4_20
-R 9500,1500,ref_ref,a4_15
-R 9000,3000,ref_ref,cin3_30
-R 9000,2500,ref_ref,cin3_25
-R 9500,3500,ref_ref,a4_35
-R 10000,3000,ref_ref,b4_30
-R 5500,2000,ref_ref,sout_20
-R 5500,2500,ref_ref,sout_25
-R 5500,3000,ref_ref,sout_30
-R 5500,3500,ref_ref,sout_35
-R 5500,1000,ref_ref,sout_10
-R 5500,1500,ref_ref,sout_15
-R 1000,3500,ref_ref,b1_35
-R 500,3500,ref_ref,a1_35
-R 500,1000,ref_ref,a1_10
-R 3000,3000,ref_ref,b2_30
-R 3000,2500,ref_ref,b2_25
-R 3000,2000,ref_ref,b2_20
-R 3000,1500,ref_ref,b2_15
-R 2500,3000,ref_ref,a2_30
-R 2500,2500,ref_ref,a2_25
-R 2500,2000,ref_ref,a2_20
-R 2500,1500,ref_ref,a2_15
-R 2000,3000,ref_ref,cin1_30
-R 2000,2500,ref_ref,cin1_25
-R 2000,2000,ref_ref,cin1_20
-R 2000,1500,ref_ref,cin1_15
-R 1000,3000,ref_ref,b1_30
-R 1000,2500,ref_ref,b1_25
-R 1000,2000,ref_ref,b1_20
-R 1000,1500,ref_ref,b1_15
-R 500,3000,ref_ref,a1_30
-R 500,2500,ref_ref,a1_25
-R 500,2000,ref_ref,a1_20
-R 500,1500,ref_ref,a1_15
-S 9600,900,9600,1200,300,*,UP,NDIF
-S 8500,900,8500,1200,300,*,UP,NDIF
-S 6900,3500,6900,4100,300,*,UP,PDIF
-S 1500,3300,1500,4100,300,*,UP,PDIF
-S 4500,1000,4500,3500,200,cout,DOWN,CALU1
-S 6500,2000,6500,3000,200,a3,DOWN,CALU1
-S 7500,1500,7500,3000,200,cin2,DOWN,CALU1
-S 7000,1500,7000,3000,200,b3,DOWN,CALU1
-S 9000,1500,9000,3000,200,cin3,DOWN,CALU1
-S 9500,1500,9500,3500,200,a4,DOWN,CALU1
-S 10000,1500,10000,3500,200,b4,DOWN,CALU1
-S 5500,1000,5500,3500,200,sout,DOWN,CALU1
-S 3000,1500,3000,3000,200,b2,DOWN,CALU1
-S 2500,1500,2500,3000,200,a2,DOWN,CALU1
-S 2000,1500,2000,3000,200,cin1,DOWN,CALU1
-S 1000,1500,1000,3500,200,b1,DOWN,CALU1
-S 500,1000,500,3500,200,a1,DOWN,CALU1
-S 5300,2000,6000,2000,300,*,LEFT,POLY
-S 3900,2000,4700,2000,300,*,RIGHT,POLY
-S 0,4700,10500,4700,600,vdd,RIGHT,CALU1
-S 0,3900,10500,3900,2400,*,RIGHT,NWELL
-S 0,300,10500,300,600,vss,RIGHT,CALU1
-S 3800,500,3800,1000,200,*,UP,ALU1
-S 3800,4000,6100,4000,100,*,RIGHT,ALU1
-S 4500,950,4500,3550,200,*,UP,ALU1
-S 3800,2000,3900,2000,100,*,RIGHT,ALU1
-S 3800,2000,3800,4000,100,*,UP,ALU1
-S 1500,3500,3800,3500,100,*,LEFT,ALU1
-S 5500,950,5500,3550,200,*,UP,ALU1
-S 6500,1000,6500,1500,100,*,DOWN,ALU1
-S 6000,1500,6500,1500,100,*,RIGHT,ALU1
-S 6500,1000,7900,1000,100,*,RIGHT,ALU1
-S 6000,1500,6000,2000,100,*,DOWN,ALU1
-S 6500,2000,6500,3000,100,*,DOWN,ALU1
-S 6300,3500,6300,4700,300,*,UP,PDIF
-S 6300,300,6300,1200,300,*,UP,NDIF
-S 8900,3100,8900,4100,100,*,UP,PTRANS
-S 8300,3100,8300,4300,100,*,UP,PTRANS
-S 8100,4700,9700,4700,300,*,RIGHT,NTIE
-S 10200,3300,10200,4000,300,*,UP,PDIF
-S 8000,3300,8000,4100,300,*,UP,PDIF
-S 8600,3300,8600,4100,200,*,UP,PDIF
-S 6600,3300,6600,4300,100,*,UP,PTRANS
-S 9400,3100,9400,4100,100,*,UP,PTRANS
-S 9200,3300,9200,3900,200,*,UP,PDIF
-S 9900,3100,9900,4100,100,*,UP,PTRANS
-S 7700,3300,7700,4300,100,*,UP,PTRANS
-S 7200,3300,7200,4300,100,*,UP,PTRANS
-S 6600,700,6600,1400,100,*,UP,NTRANS
-S 8800,700,8800,1400,100,*,UP,NTRANS
-S 9300,700,9300,1400,100,*,UP,NTRANS
-S 7100,700,7100,1400,100,*,UP,NTRANS
-S 10200,1000,10200,1200,300,*,UP,NDIF
-S 7600,700,7600,1400,100,*,UP,NTRANS
-S 9900,700,9900,1400,100,*,UP,NTRANS
-S 7900,900,7900,1200,300,*,UP,NDIF
-S 8200,700,8200,1500,100,*,UP,NTRANS
-S 6900,400,8400,400,300,*,RIGHT,PTIE
-S 9700,400,10100,400,300,*,RIGHT,PTIE
-S 8800,2400,8900,2400,100,*,RIGHT,POLY
-S 9300,1400,9400,1400,100,*,RIGHT,POLY
-S 7600,3300,7700,3300,100,*,RIGHT,POLY
-S 8200,3100,8300,3100,100,*,RIGHT,POLY
-S 8200,1500,8200,3100,100,*,UP,POLY
-S 8900,2500,8900,3100,100,*,DOWN,POLY
-S 6600,1400,6600,3300,100,*,UP,POLY
-S 7100,1400,7100,3300,100,*,UP,POLY
-S 7600,1400,7600,3300,100,*,UP,POLY
-S 9400,1400,9400,3100,100,*,UP,POLY
-S 9900,1400,9900,3100,100,*,DOWN,POLY
-S 8800,1400,8800,2400,100,*,UP,POLY
-S 7100,3300,7200,3300,100,*,RIGHT,POLY
-S 7000,1500,7000,3000,100,*,DOWN,ALU1
-S 7500,1500,7500,3000,100,*,UP,ALU1
-S 9000,1500,9000,3000,100,*,UP,ALU1
-S 8000,2000,8000,3500,100,*,UP,ALU1
-S 8500,1000,9600,1000,100,*,RIGHT,ALU1
-S 6900,4000,10200,4000,100,*,RIGHT,ALU1
-S 9500,1500,9500,3500,100,*,UP,ALU1
-S 10000,1500,10000,3500,100,*,DOWN,ALU1
-S 6100,3500,6100,4000,100,*,DOWN,ALU1
-S 6100,3500,8000,3500,100,*,RIGHT,ALU1
-S 8500,1500,8500,3550,100,*,UP,ALU1
-S 8000,950,8000,1500,100,*,UP,ALU1
-S 8000,1500,8500,1500,100,*,RIGHT,ALU1
-S 10200,300,10200,1000,200,*,DOWN,ALU1
-S 6200,2800,6200,4700,300,*,DOWN,PDIF
-S 5300,2600,5300,4900,100,*,UP,PTRANS
-S 5600,2800,5600,4700,300,*,DOWN,PDIF
-S 5900,2600,5900,4900,100,*,UP,PTRANS
-S 6200,300,6200,1200,300,*,UP,NDIF
-S 5300,100,5300,1400,100,*,DOWN,NTRANS
-S 5600,300,5600,1200,300,*,UP,NDIF
-S 5900,100,5900,1400,100,*,DOWN,NTRANS
-S 5300,1400,5300,2600,100,*,UP,POLY
-S 5900,1400,5900,2600,100,*,UP,POLY
-S 5000,2800,5000,4700,300,*,DOWN,PDIF
-S 5000,300,5000,1200,300,*,UP,NDIF
-S 4700,100,4700,1400,100,*,DOWN,NTRANS
-S 4700,2600,4700,4900,100,*,UP,PTRANS
-S 4700,1400,4700,2600,100,*,UP,POLY
-S 500,1000,500,3500,100,*,DOWN,ALU1
-S 1000,1500,1000,3500,100,*,UP,ALU1
-S 900,400,2000,400,300,*,RIGHT,PTIE
-S 300,500,300,1300,300,*,UP,NDIF
-S 1600,4700,3200,4700,300,*,RIGHT,NTIE
-S 1100,700,1100,1600,100,*,UP,NTRANS
-S 600,1500,600,3100,100,*,UP,POLY
-S 1000,2000,1200,2000,100,*,LEFT,POLY
-S 1700,2500,2000,2500,100,*,RIGHT,POLY
-S 1700,1400,1700,2500,100,*,UP,POLY
-S 1800,2400,1800,3100,100,*,UP,POLY
-S 1100,1600,1100,2000,100,*,UP,POLY
-S 1200,2000,1200,3100,100,*,UP,POLY
-S 2100,2900,2100,4100,200,*,UP,PDIF
-S 2900,1400,2900,2700,100,*,UP,POLY
-S 2400,1900,2400,2700,100,*,UP,POLY
-S 300,3300,300,4050,300,*,UP,PDIF
-S 900,3300,900,4450,300,*,UP,PDIF
-S 600,3100,600,4300,100,*,UP,PTRANS
-S 3200,2900,3200,4100,300,*,UP,PDIF
-S 2700,2900,2700,4100,200,*,UP,PDIF
-S 2900,2700,2900,4300,100,*,UP,PTRANS
-S 2400,2700,2400,4300,100,*,UP,PTRANS
-S 1800,3100,1800,4300,100,*,UP,PTRANS
-S 1200,3100,1200,4300,100,*,UP,PTRANS
-S 2300,1400,2300,1900,100,*,UP,POLY
-S 3200,900,3200,1200,300,*,UP,NDIF
-S 2600,500,2600,1200,300,*,UP,NDIF
-S 2000,900,2000,1200,300,*,UP,NDIF
-S 1400,900,1400,1400,300,*,UP,NDIF
-S 600,700,600,1500,100,*,UP,NTRANS
-S 1700,700,1700,1400,100,*,UP,NTRANS
-S 2300,700,2300,1400,100,*,UP,NTRANS
-S 2900,700,2900,1400,100,*,UP,NTRANS
-S 2000,1000,3200,1000,100,*,RIGHT,ALU1
-S 300,4000,3200,4000,100,*,RIGHT,ALU1
-S 2300,1900,2400,1900,100,*,RIGHT,POLY
-S 1500,1000,1500,3500,100,*,UP,ALU1
-S 2000,1500,2000,3000,100,*,DOWN,ALU1
-S 2500,1500,2500,3000,100,*,UP,ALU1
-S 3000,1500,3000,3000,100,*,UP,ALU1
-S 3800,300,3800,1200,300,*,UP,NDIF
-S 4400,300,4400,1200,300,*,UP,NDIF
-S 4100,100,4100,1400,100,*,DOWN,NTRANS
-S 3800,2800,3800,4700,300,*,DOWN,PDIF
-S 4400,2800,4400,4700,300,*,DOWN,PDIF
-S 4100,2600,4100,4900,100,*,UP,PTRANS
-S 4100,1400,4100,2600,100,*,UP,POLY
-S 7450,3600,7450,4650,200,*,UP,PDIF
-S 9050,400,9050,1200,200,*,UP,NDIF
-S 1000,2000,1200,2000,300,*,RIGHT,POLY
-S 1700,2500,2000,2500,300,*,LEFT,POLY
-S 8000,2000,8200,2000,300,*,RIGHT,POLY
-V 3800,1000,CONT_DIF_N,*
-V 4400,3500,CONT_DIF_P,*
-V 4400,3000,CONT_DIF_P,*
-V 4400,1000,CONT_DIF_N,*
-V 3900,2000,CONT_POLY,*
-V 10200,4000,CONT_DIF_P,*
-V 8600,3500,CONT_DIF_P,*
-V 9300,4700,CONT_BODY_N,*
-V 8900,4700,CONT_BODY_N,*
-V 8500,4700,CONT_BODY_N,*
-V 8100,4700,CONT_BODY_N,*
-V 8000,4000,CONT_DIF_P,*
-V 6900,4000,CONT_DIF_P,*
-V 9700,4700,CONT_BODY_N,*
-V 7900,1000,CONT_DIF_N,*
-V 10200,1000,CONT_DIF_N,*
-V 9600,1000,CONT_DIF_N,*
-V 8500,1000,CONT_DIF_N,*
-V 6900,400,CONT_BODY_P,*
-V 8450,400,CONT_BODY_P,*
-V 10100,400,CONT_BODY_P,*
-V 9700,400,CONT_BODY_P,*
-V 7900,400,CONT_BODY_P,*
-V 7400,400,CONT_BODY_P,*
-V 10000,2000,CONT_POLY,*
-V 9500,2500,CONT_POLY,*
-V 9000,2500,CONT_POLY,*
-V 6500,2000,CONT_POLY,*
-V 7000,2000,CONT_POLY,*
-V 7500,2000,CONT_POLY,*
-V 8000,2000,CONT_POLY,*
-V 6000,2000,CONT_POLY,*
-V 5600,3000,CONT_DIF_P,*
-V 5600,3500,CONT_DIF_P,*
-V 5600,1000,CONT_DIF_N,*
-V 6200,500,CONT_DIF_N,*
-V 5000,500,CONT_DIF_N,*
-V 3800,500,CONT_DIF_N,*
-V 6200,4500,CONT_DIF_P,*
-V 5000,4500,CONT_DIF_P,*
-V 3800,4500,CONT_DIF_P,*
-V 1500,400,CONT_BODY_P,*
-V 1000,400,CONT_BODY_P,*
-V 300,500,CONT_DIF_N,*
-V 1600,4700,CONT_BODY_N,*
-V 2000,4700,CONT_BODY_N,*
-V 2400,4700,CONT_BODY_N,*
-V 2800,4700,CONT_BODY_N,*
-V 3200,4700,CONT_BODY_N,*
-V 3200,400,CONT_BODY_P,*
-V 3000,2500,CONT_POLY,*
-V 2100,3500,CONT_DIF_P,*
-V 2600,500,CONT_DIF_N,*
-V 3200,1000,CONT_DIF_N,*
-V 2000,1000,CONT_DIF_N,*
-V 900,4500,CONT_DIF_P,*
-V 300,4700,CONT_BODY_N,*
-V 1500,4000,CONT_DIF_P,*
-V 300,4000,CONT_DIF_P,*
-V 3200,4000,CONT_DIF_P,*
-V 500,2000,CONT_POLY,*
-V 1000,2000,CONT_POLY,*
-V 2500,2000,CONT_POLY,*
-V 2000,400,CONT_BODY_P,*
-V 2000,2500,CONT_POLY,*
-V 1400,1000,CONT_DIF_N,*
-V 7450,4600,CONT_DIF_P,*
-V 9050,400,CONT_DIF_N,*
-EOF
diff --git a/alliance/share/cells/sxlib/fulladder_x4.vbe b/alliance/share/cells/sxlib/fulladder_x4.vbe
deleted file mode 100644
index 8c5b5658..00000000
--- a/alliance/share/cells/sxlib/fulladder_x4.vbe
+++ /dev/null
@@ -1,121 +0,0 @@
-ENTITY fulladder_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 5250;
-  CONSTANT cin_a1	 : NATURAL := 8;
-  CONSTANT cin_a2	 : NATURAL := 8;
-  CONSTANT cin_a3	 : NATURAL := 6;
-  CONSTANT cin_a4	 : NATURAL := 6;
-  CONSTANT cin_b1	 : NATURAL := 8;
-  CONSTANT cin_b2	 : NATURAL := 8;
-  CONSTANT cin_b3	 : NATURAL := 6;
-  CONSTANT cin_b4	 : NATURAL := 6;
-  CONSTANT cin_cin1	 : NATURAL := 7;
-  CONSTANT cin_cin2	 : NATURAL := 6;
-  CONSTANT cin_cin3	 : NATURAL := 6;
-  CONSTANT rdown_a1_cout	 : NATURAL := 810;
-  CONSTANT rdown_a1_sout	 : NATURAL := 810;
-  CONSTANT rdown_a2_cout	 : NATURAL := 810;
-  CONSTANT rdown_a2_sout	 : NATURAL := 810;
-  CONSTANT rdown_a3_sout	 : NATURAL := 810;
-  CONSTANT rdown_a4_sout	 : NATURAL := 810;
-  CONSTANT rdown_b1_cout	 : NATURAL := 810;
-  CONSTANT rdown_b1_sout	 : NATURAL := 810;
-  CONSTANT rdown_b2_cout	 : NATURAL := 810;
-  CONSTANT rdown_b2_sout	 : NATURAL := 810;
-  CONSTANT rdown_b3_sout	 : NATURAL := 810;
-  CONSTANT rdown_b4_sout	 : NATURAL := 810;
-  CONSTANT rdown_cin1_cout	 : NATURAL := 810;
-  CONSTANT rdown_cin1_sout	 : NATURAL := 810;
-  CONSTANT rdown_cin2_sout	 : NATURAL := 810;
-  CONSTANT rdown_cin3_sout	 : NATURAL := 810;
-  CONSTANT rup_a1_cout	 : NATURAL := 890;
-  CONSTANT rup_a1_sout	 : NATURAL := 890;
-  CONSTANT rup_a2_cout	 : NATURAL := 890;
-  CONSTANT rup_a2_sout	 : NATURAL := 890;
-  CONSTANT rup_a3_sout	 : NATURAL := 890;
-  CONSTANT rup_a4_sout	 : NATURAL := 890;
-  CONSTANT rup_b1_cout	 : NATURAL := 890;
-  CONSTANT rup_b1_sout	 : NATURAL := 890;
-  CONSTANT rup_b2_cout	 : NATURAL := 890;
-  CONSTANT rup_b2_sout	 : NATURAL := 890;
-  CONSTANT rup_b3_sout	 : NATURAL := 890;
-  CONSTANT rup_b4_sout	 : NATURAL := 890;
-  CONSTANT rup_cin1_cout	 : NATURAL := 890;
-  CONSTANT rup_cin1_sout	 : NATURAL := 890;
-  CONSTANT rup_cin2_sout	 : NATURAL := 890;
-  CONSTANT rup_cin3_sout	 : NATURAL := 890;
-  CONSTANT tphh_cin3_sout	 : NATURAL := 630;
-  CONSTANT tphh_a4_sout	 : NATURAL := 673;
-  CONSTANT tphh_b4_sout	 : NATURAL := 715;
-  CONSTANT tphh_a1_cout	 : NATURAL := 800;
-  CONSTANT tphh_a2_cout	 : NATURAL := 801;
-  CONSTANT tpll_cin1_cout	 : NATURAL := 830;
-  CONSTANT tpll_b1_cout	 : NATURAL := 839;
-  CONSTANT tpll_a1_cout	 : NATURAL := 866;
-  CONSTANT tpll_b2_cout	 : NATURAL := 883;
-  CONSTANT tphh_b1_cout	 : NATURAL := 884;
-  CONSTANT tphh_b2_cout	 : NATURAL := 892;
-  CONSTANT tphh_cin1_cout	 : NATURAL := 899;
-  CONSTANT tpll_a2_cout	 : NATURAL := 924;
-  CONSTANT tphh_a3_sout	 : NATURAL := 1086;
-  CONSTANT tpll_cin2_sout	 : NATURAL := 1150;
-  CONSTANT tphh_b3_sout	 : NATURAL := 1202;
-  CONSTANT tpll_b3_sout	 : NATURAL := 1208;
-  CONSTANT tpll_a3_sout	 : NATURAL := 1265;
-  CONSTANT tphh_cin2_sout	 : NATURAL := 1308;
-  CONSTANT tpll_b4_sout	 : NATURAL := 1329;
-  CONSTANT tpll_a4_sout	 : NATURAL := 1377;
-  CONSTANT tpll_cin3_sout	 : NATURAL := 1417;
-  CONSTANT tphl_a1_sout	 : NATURAL := 1471;
-  CONSTANT tphl_a2_sout	 : NATURAL := 1472;
-  CONSTANT tplh_cin1_sout	 : NATURAL := 1492;
-  CONSTANT tplh_b1_sout	 : NATURAL := 1501;
-  CONSTANT tplh_a1_sout	 : NATURAL := 1528;
-  CONSTANT tplh_b2_sout	 : NATURAL := 1545;
-  CONSTANT tphl_b1_sout	 : NATURAL := 1555;
-  CONSTANT tphl_b2_sout	 : NATURAL := 1563;
-  CONSTANT tphl_cin1_sout	 : NATURAL := 1570;
-  CONSTANT tplh_a2_sout	 : NATURAL := 1586;
-  CONSTANT transistors	 : NATURAL := 32
-);
-PORT (
-  a1	 : in  BIT;
-  a2	 : in  BIT;
-  a3	 : in  BIT;
-  a4	 : in  BIT;
-  b1	 : in  BIT;
-  b2	 : in  BIT;
-  b3	 : in  BIT;
-  b4	 : in  BIT;
-  cin1	 : in  BIT;
-  cin2	 : in  BIT;
-  cin3	 : in  BIT;
-  cout	 : out BIT;
-  sout	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END fulladder_x4;
-
-ARCHITECTURE behaviour_data_flow OF fulladder_x4 IS
-  SIGNAL ncout	 : BIT;
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on fulladder_x4"
-  SEVERITY WARNING;
-  ASSERT (((((a1 and a2) and a3) and a4) or not ((((a1 or a2) or a3) or
-  a4))) = '1')
-  REPORT "a1, a2, a3, a4 must be connected together on fulladder_x4"
-  SEVERITY WARNING;
-  ASSERT (((((b1 and b2) and b3) and b4) or not ((((b1 or b2) or b3) or
-  b4))) = '1')
-  REPORT "b1, b2, b3, b4 must be connected together on fulladder_x4"
-  SEVERITY WARNING;
-  ASSERT ((((cin1 and cin2) and cin3) or not (((cin1 or cin2) or cin3))) = '1')
-  REPORT "cin1, cin2, cin3 must be connected together on fulladder_x4"
-  SEVERITY WARNING;
-  ncout <= not (((a1 and b1) or ((a2 or b2) and cin1)));
-  sout <= (((a3 and b3) and cin2) or (((a4 or b4) or cin3) and ncout)) after 2200 ps;
-  cout <= not (ncout) after 1500 ps;
-END;
diff --git a/alliance/share/cells/sxlib/fulladder_x4.vhd b/alliance/share/cells/sxlib/fulladder_x4.vhd
deleted file mode 100644
index 73aa48a2..00000000
--- a/alliance/share/cells/sxlib/fulladder_x4.vhd
+++ /dev/null
@@ -1,34 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY fulladder_x4 IS
-PORT(
-  a1	: IN STD_LOGIC;
-  a2	: IN STD_LOGIC;
-  a3	: IN STD_LOGIC;
-  a4	: IN STD_LOGIC;
-  b1	: IN STD_LOGIC;
-  b2	: IN STD_LOGIC;
-  b3	: IN STD_LOGIC;
-  b4	: IN STD_LOGIC;
-  cin1	: IN STD_LOGIC;
-  cin2	: IN STD_LOGIC;
-  cin3	: IN STD_LOGIC;
-  cout	: OUT STD_LOGIC;
-  sout	: OUT STD_LOGIC
-);
-END fulladder_x4;
-
-ARCHITECTURE RTL OF fulladder_x4 IS
-  SIGNAL ncout	: STD_LOGIC;
-
-BEGIN
-  cout <= NOT(ncout);
-  sout <= (((a3 AND b3) AND cin2) OR (((a4 OR b4) OR cin3) AND ncout));
-  ncout <= NOT(((a1 AND b1) OR ((a2 OR b2) AND cin1)));
-END RTL;
diff --git a/alliance/share/cells/sxlib/halfadder_x2.al b/alliance/share/cells/sxlib/halfadder_x2.al
deleted file mode 100644
index fab1b263..00000000
--- a/alliance/share/cells/sxlib/halfadder_x2.al
+++ /dev/null
@@ -1,57 +0,0 @@
-V ALLIANCE : 6
-H halfadder_x2,L,30/10/99
-C a,UNKNOWN,EXTERNAL,7
-C b,UNKNOWN,EXTERNAL,8
-C cout,OUT,EXTERNAL,4
-C sout,OUT,EXTERNAL,14
-C vdd,IN,EXTERNAL,6
-C vss,IN,EXTERNAL,3
-T P,0.35,2.6,6,7,1,0,0.75,0.75,6.7,6.7,3.9,11.1,tr_00020
-T P,0.35,5.9,14,9,6,0,0.75,0.75,13.3,13.3,21.9,11.25,tr_00019
-T P,0.35,5.9,4,1,6,0,0.75,0.75,13.3,13.3,2.1,11.25,tr_00018
-T P,0.35,3.2,12,8,6,0,0.75,0.75,7.9,7.9,11.1,9.9,tr_00017
-T P,0.35,3.2,6,13,12,0,0.75,0.75,7.9,7.9,16.5,9.9,tr_00016
-T P,0.35,3.2,12,5,9,0,0.75,0.75,7.9,7.9,14.7,9.9,tr_00015
-T P,0.35,3.2,9,7,12,0,0.75,0.75,7.9,7.9,12.9,9.9,tr_00014
-T P,0.35,2.6,1,8,6,0,0.75,0.75,6.7,6.7,5.7,11.1,tr_00013
-T P,0.35,2.3,6,8,5,0,0.75,0.75,6.1,6.1,9.3,9.45,tr_00012
-T P,0.35,3.2,13,7,6,0,0.75,0.75,7.9,7.9,18.3,9.9,tr_00011
-T N,0.35,2.9,3,9,14,0,0.75,0.75,7.3,7.3,21.9,2.25,tr_00010
-T N,0.35,2.9,3,1,4,0,0.75,0.75,7.3,7.3,2.1,2.25,tr_00009
-T N,0.35,1.4,3,8,11,0,0.75,0.75,4.3,4.3,11.1,3,tr_00008
-T N,0.35,2,1,8,2,0,0.75,0.75,5.5,5.5,5.7,3.3,tr_00007
-T N,0.35,1.4,2,7,3,0,0.75,0.75,4.3,4.3,3.9,3,tr_00006
-T N,0.35,1.7,9,5,10,0,0.75,0.75,4.9,4.9,14.7,3.15,tr_00005
-T N,0.35,1.4,10,7,3,0,0.75,0.75,4.3,4.3,16.5,3,tr_00004
-T N,0.35,1.1,3,7,13,0,0.75,0.75,3.7,3.7,18.3,3.15,tr_00003
-T N,0.35,1.7,11,13,9,0,0.75,0.75,4.9,4.9,12.9,3.15,tr_00002
-T N,0.35,1.1,5,8,3,0,0.75,0.75,3.7,3.7,9.3,3.15,tr_00001
-S 14,EXTERNAL,sout
-Q 0.00258522
-S 13,INTERNAL
-Q 0.00530432
-S 12,INTERNAL
-Q 0.00171257
-S 11,INTERNAL
-Q 0
-S 10,INTERNAL
-Q 0
-S 9,INTERNAL
-Q 0.0062563
-S 8,EXTERNAL,b
-Q 0.0069823
-S 7,EXTERNAL,a
-Q 0.0115667
-S 6,EXTERNAL,vdd
-Q 0.00938587
-S 5,INTERNAL
-Q 0.00442919
-S 4,EXTERNAL,cout
-Q 0.00258522
-S 3,EXTERNAL,vss
-Q 0.00832828
-S 2,INTERNAL
-Q 0
-S 1,INTERNAL
-Q 0.00435733
-EOF
diff --git a/alliance/share/cells/sxlib/halfadder_x2.ap b/alliance/share/cells/sxlib/halfadder_x2.ap
deleted file mode 100644
index 76802044..00000000
--- a/alliance/share/cells/sxlib/halfadder_x2.ap
+++ /dev/null
@@ -1,185 +0,0 @@
-V ALLIANCE : 6
-H halfadder_x2,P,30/ 8/2000,100
-A 0,0,8000,5000
-R 7500,2500,ref_ref,sout_25
-R 7500,2000,ref_ref,sout_20
-R 7500,1500,ref_ref,sout_15
-R 3500,1500,ref_ref,b_15
-R 3500,2000,ref_ref,b_20
-R 3500,2500,ref_ref,b_25
-R 3500,3000,ref_ref,b_30
-R 7500,4000,ref_ref,sout_40
-R 7500,1000,ref_ref,sout_10
-R 7500,3000,ref_ref,sout_30
-R 7500,3500,ref_ref,sout_35
-R 1000,3500,ref_ref,a_35
-R 1000,4000,ref_ref,a_40
-R 1000,1000,ref_ref,a_10
-R 1000,1500,ref_ref,a_15
-R 1000,2500,ref_ref,a_25
-R 1000,2000,ref_ref,a_20
-R 3500,3500,ref_ref,b_35
-R 3500,1000,ref_ref,b_10
-R 500,4000,ref_ref,cout_40
-R 500,1000,ref_ref,cout_10
-R 500,3000,ref_ref,cout_30
-R 500,3500,ref_ref,cout_35
-R 500,2500,ref_ref,cout_25
-R 500,2000,ref_ref,cout_20
-R 500,1500,ref_ref,cout_15
-R 1000,3000,ref_ref,a_30
-S 7500,1000,7500,4000,200,*,DOWN,ALU1
-S 500,1000,500,4000,200,*,DOWN,ALU1
-S 5200,2800,5200,3800,300,*,DOWN,PDIF
-S 3400,2800,3400,4500,300,*,DOWN,PDIF
-S 5800,2800,5800,4500,300,*,DOWN,PDIF
-S 2800,2800,2800,3500,300,*,UP,PDIF
-S 6400,2800,6400,3800,300,*,DOWN,PDIF
-S 6100,2600,6100,4000,100,*,UP,PTRANS
-S 3100,2600,3100,3700,100,*,UP,PTRANS
-S 0,3900,8000,3900,2400,*,LEFT,NWELL
-S 1900,3100,1900,4300,100,*,DOWN,PTRANS
-S 1600,3300,1600,4100,300,*,UP,PDIF
-S 4300,2600,4300,4000,100,*,UP,PTRANS
-S 4900,2600,4900,4000,100,*,UP,PTRANS
-S 5500,2600,5500,4000,100,*,UP,PTRANS
-S 3700,2600,3700,4000,100,*,UP,PTRANS
-S 4000,2800,4000,3800,300,*,DOWN,PDIF
-S 4600,2800,4600,3800,300,*,DOWN,PDIF
-S 700,2600,700,4900,100,*,DOWN,PTRANS
-S 2200,3300,2200,4600,300,*,UP,PDIF
-S 400,2800,400,4700,300,*,UP,PDIF
-S 1000,2800,1000,4700,300,*,UP,PDIF
-S 7000,3400,7000,4700,300,*,DOWN,PDIF
-S 7600,2800,7600,4700,300,*,DOWN,PDIF
-S 7300,2600,7300,4900,100,*,UP,PTRANS
-S 1300,3100,1300,4300,100,*,DOWN,PTRANS
-S 3100,700,3100,1400,100,*,DOWN,NTRANS
-S 4300,600,4300,1500,100,*,DOWN,NTRANS
-S 4600,800,4600,1300,300,*,UP,NDIF
-S 4000,800,4000,1300,300,*,UP,NDIF
-S 5200,800,5200,1300,300,*,UP,NDIF
-S 6100,700,6100,1400,100,*,DOWN,NTRANS
-S 6400,900,6400,1600,300,*,UP,NDIF
-S 5500,600,5500,1400,100,*,DOWN,NTRANS
-S 2800,1000,2800,1200,300,*,UP,NDIF
-S 3400,400,3400,1200,300,*,UP,NDIF
-S 5800,400,5800,1200,300,*,UP,NDIF
-S 4900,600,4900,1500,100,*,DOWN,NTRANS
-S 1300,600,1300,1400,100,*,UP,NTRANS
-S 1900,600,1900,1600,100,*,UP,NTRANS
-S 2200,800,2200,1400,300,*,DOWN,NDIF
-S 1600,800,1600,1400,300,*,DOWN,NDIF
-S 3700,600,3700,1400,100,*,DOWN,NTRANS
-S 1000,300,1000,1200,300,*,DOWN,NDIF
-S 400,300,400,1200,300,*,DOWN,NDIF
-S 700,100,700,1400,100,*,UP,NTRANS
-S 7000,300,7000,1000,300,*,UP,NDIF
-S 7600,300,7600,1200,300,*,UP,NDIF
-S 7300,100,7300,1400,100,*,DOWN,NTRANS
-S 4900,1500,4900,2600,100,*,DOWN,POLY
-S 7000,2000,7300,2000,300,*,RIGHT,POLY
-S 4300,1500,4600,1500,100,*,RIGHT,POLY
-S 7300,1400,7300,2600,100,*,DOWN,POLY
-S 1900,2000,2000,2000,100,*,RIGHT,POLY
-S 1900,1600,1900,2000,100,*,UP,POLY
-S 1000,2500,1300,2500,300,*,RIGHT,POLY
-S 3100,2600,3700,2600,100,*,RIGHT,POLY
-S 3100,1400,3700,1400,100,*,RIGHT,POLY
-S 2800,2000,4900,2000,100,*,RIGHT,POLY
-S 5500,1400,6100,1400,100,*,RIGHT,POLY
-S 5500,2000,5500,2600,100,*,DOWN,POLY
-S 5500,2000,6500,2000,100,*,RIGHT,POLY
-S 4300,2600,4600,2600,100,*,RIGHT,POLY
-S 1000,1500,1300,1500,300,*,RIGHT,POLY
-S 700,2000,1500,2000,100,*,RIGHT,POLY
-S 1300,2400,1300,3100,100,*,UP,POLY
-S 700,1400,700,2600,100,*,DOWN,POLY
-S 0,300,8000,300,600,vss,RIGHT,CALU1
-S 5000,1600,5000,2000,100,*,DOWN,ALU1
-S 0,4700,8000,4700,600,vdd,RIGHT,CALU1
-S 7000,1000,7000,2000,100,*,DOWN,ALU1
-S 7000,3500,7000,4500,200,*,DOWN,ALU1
-S 6000,1500,6000,4000,100,*,DOWN,ALU1
-S 6500,1500,6500,2900,100,*,DOWN,ALU1
-S 2100,3500,3500,3500,100,*,RIGHT,ALU1
-S 2100,3000,2100,3500,100,*,DOWN,ALU1
-S 2000,3000,2100,3000,100,*,LEFT,ALU1
-S 4500,1600,5000,1600,100,*,RIGHT,ALU1
-S 5200,3000,5200,3500,100,*,DOWN,ALU1
-S 2800,1000,2800,3000,100,*,DOWN,ALU1
-S 4000,3000,4600,3000,100,*,LEFT,ALU1
-S 4000,1000,4000,3000,100,*,UP,ALU1
-S 5000,2000,5500,2000,100,*,RIGHT,ALU1
-S 4500,2500,6000,2500,100,*,RIGHT,ALU1
-S 4000,1000,7000,1000,100,*,RIGHT,ALU1
-S 2000,2000,2000,3000,100,*,UP,ALU1
-S 1550,1000,1550,3500,100,*,UP,ALU1
-S 1000,4000,6000,4000,100,*,RIGHT,ALU1
-S 1550,1000,2200,1000,100,*,RIGHT,ALU1
-S 1000,1000,1000,4000,100,*,UP,ALU1
-S 3500,1000,3500,3500,100,*,UP,ALU1
-S 4000,3500,5200,3500,100,*,RIGHT,ALU1
-S 7500,1000,7500,4000,200,sout,DOWN,CALU1
-S 3500,1000,3500,3500,200,b,DOWN,CALU1
-S 1000,1000,1000,4000,200,a,DOWN,CALU1
-S 500,1000,500,4000,200,cout,DOWN,CALU1
-V 4000,4700,CONT_BODY_N,*
-V 5200,4700,CONT_BODY_N,*
-V 7000,3500,CONT_DIF_P,*
-V 2800,3000,CONT_DIF_P,*
-V 6500,2900,CONT_DIF_P,*
-V 7600,3000,CONT_DIF_P,*
-V 7600,3500,CONT_DIF_P,*
-V 7600,4000,CONT_DIF_P,*
-V 7000,4500,CONT_DIF_P,*
-V 4600,4700,CONT_BODY_N,*
-V 4600,3000,CONT_DIF_P,*
-V 3400,4500,CONT_DIF_P,*
-V 5800,4500,CONT_DIF_P,*
-V 2800,4700,CONT_BODY_N,*
-V 6400,4700,CONT_BODY_N,*
-V 4000,3500,CONT_DIF_P,*
-V 5200,3500,CONT_DIF_P,*
-V 7000,4000,CONT_DIF_P,*
-V 400,3500,CONT_DIF_P,*
-V 400,3000,CONT_DIF_P,*
-V 2200,4500,CONT_DIF_P,*
-V 1600,3500,CONT_DIF_P,*
-V 400,4000,CONT_DIF_P,*
-V 1600,4700,CONT_BODY_N,*
-V 1000,4500,CONT_DIF_P,*
-V 5200,3000,CONT_DIF_P,*
-V 7600,1000,CONT_DIF_N,*
-V 7000,500,CONT_DIF_N,*
-V 4600,1100,CONT_DIF_N,*
-V 1000,500,CONT_DIF_N,*
-V 2200,1000,CONT_DIF_N,*
-V 400,1000,CONT_DIF_N,*
-V 2800,1000,CONT_DIF_N,*
-V 3400,500,CONT_DIF_N,*
-V 5800,500,CONT_DIF_N,*
-V 6500,1500,CONT_DIF_N,*
-V 2200,300,CONT_BODY_P,*
-V 2800,300,CONT_BODY_P,*
-V 6400,300,CONT_BODY_P,*
-V 4600,300,CONT_BODY_P,*
-V 5200,300,CONT_BODY_P,*
-V 4000,300,CONT_BODY_P,*
-V 1600,300,CONT_BODY_P,*
-V 7000,2000,CONT_POLY,*
-V 5500,2000,CONT_POLY,*
-V 6500,2000,CONT_POLY,*
-V 6000,2500,CONT_POLY,*
-V 4500,1600,CONT_POLY,*
-V 1500,2000,CONT_POLY,*
-V 1100,2500,CONT_POLY,*
-V 2000,2000,CONT_POLY,*
-V 6000,1500,CONT_POLY,*
-V 4500,2500,CONT_POLY,*
-V 3500,2500,CONT_POLY,*
-V 3500,1500,CONT_POLY,*
-V 2800,2000,CONT_POLY,*
-V 2000,3000,CONT_POLY,*
-V 1100,1500,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/sxlib/halfadder_x2.vbe b/alliance/share/cells/sxlib/halfadder_x2.vbe
deleted file mode 100644
index 13966fa6..00000000
--- a/alliance/share/cells/sxlib/halfadder_x2.vbe
+++ /dev/null
@@ -1,50 +0,0 @@
-ENTITY halfadder_x2 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 4000;
-  CONSTANT cin_a	 : NATURAL := 27;
-  CONSTANT cin_b	 : NATURAL := 22;
-  CONSTANT rdown_a_cout	 : NATURAL := 1620;
-  CONSTANT rdown_a_sout	 : NATURAL := 1620;
-  CONSTANT rdown_a_sout	 : NATURAL := 1620;
-  CONSTANT rdown_b_cout	 : NATURAL := 1620;
-  CONSTANT rdown_b_sout	 : NATURAL := 1620;
-  CONSTANT rdown_b_sout	 : NATURAL := 1620;
-  CONSTANT rup_a_cout	 : NATURAL := 1790;
-  CONSTANT rup_a_sout	 : NATURAL := 1790;
-  CONSTANT rup_a_sout	 : NATURAL := 1790;
-  CONSTANT rup_b_cout	 : NATURAL := 1790;
-  CONSTANT rup_b_sout	 : NATURAL := 1790;
-  CONSTANT rup_b_sout	 : NATURAL := 1790;
-  CONSTANT tphh_a_cout	 : NATURAL := 361;
-  CONSTANT tpll_b_cout	 : NATURAL := 383;
-  CONSTANT tphh_b_cout	 : NATURAL := 386;
-  CONSTANT tpll_a_cout	 : NATURAL := 398;
-  CONSTANT tphh_a_sout	 : NATURAL := 421;
-  CONSTANT tpll_b_sout	 : NATURAL := 497;
-  CONSTANT tphl_b_sout	 : NATURAL := 531;
-  CONSTANT tplh_b_sout	 : NATURAL := 556;
-  CONSTANT tphh_b_sout	 : NATURAL := 558;
-  CONSTANT tpll_a_sout	 : NATURAL := 562;
-  CONSTANT tphl_a_sout	 : NATURAL := 575;
-  CONSTANT tplh_a_sout	 : NATURAL := 607;
-  CONSTANT transistors	 : NATURAL := 20
-);
-PORT (
-  a	 : in  BIT;
-  b	 : in  BIT;
-  cout	 : out BIT;
-  sout	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END halfadder_x2;
-
-ARCHITECTURE behaviour_data_flow OF halfadder_x2 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on halfadder_x2"
-  SEVERITY WARNING;
-  sout <= (a xor b) after 1200 ps;
-  cout <= (a and b) after 1000 ps;
-END;
diff --git a/alliance/share/cells/sxlib/halfadder_x2.vhd b/alliance/share/cells/sxlib/halfadder_x2.vhd
deleted file mode 100644
index 9ca38530..00000000
--- a/alliance/share/cells/sxlib/halfadder_x2.vhd
+++ /dev/null
@@ -1,22 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY halfadder_x2 IS
-PORT(
-  a	: IN STD_LOGIC;
-  b	: IN STD_LOGIC;
-  cout	: OUT STD_LOGIC;
-  sout	: OUT STD_LOGIC
-);
-END halfadder_x2;
-
-ARCHITECTURE RTL OF halfadder_x2 IS
-BEGIN
-  cout <= (a AND b);
-  sout <= (a XOR b);
-END RTL;
diff --git a/alliance/share/cells/sxlib/halfadder_x4.al b/alliance/share/cells/sxlib/halfadder_x4.al
deleted file mode 100644
index 4d1b8f27..00000000
--- a/alliance/share/cells/sxlib/halfadder_x4.al
+++ /dev/null
@@ -1,61 +0,0 @@
-V ALLIANCE : 6
-H halfadder_x4,L,30/10/99
-C a,UNKNOWN,EXTERNAL,6
-C b,UNKNOWN,EXTERNAL,7
-C cout,OUT,EXTERNAL,1
-C sout,OUT,EXTERNAL,14
-C vdd,IN,EXTERNAL,5
-C vss,IN,EXTERNAL,2
-T P,0.35,5.9,1,4,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00024
-T P,0.35,5.9,1,4,5,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00023
-T P,0.35,5.9,5,9,14,0,0.75,0.75,13.3,13.3,25.2,11.25,tr_00022
-T P,0.35,5.9,14,9,5,0,0.75,0.75,13.3,13.3,23.4,11.25,tr_00021
-T P,0.35,2.6,5,6,4,0,0.75,0.75,6.7,6.7,5.4,11.1,tr_00020
-T P,0.35,2.6,4,7,5,0,0.75,0.75,6.7,6.7,7.2,11.1,tr_00019
-T P,0.35,3.2,9,6,12,0,0.75,0.75,7.9,7.9,14.4,9.9,tr_00018
-T P,0.35,3.2,12,11,9,0,0.75,0.75,7.9,7.9,16.2,9.9,tr_00017
-T P,0.35,3.2,5,13,12,0,0.75,0.75,7.9,7.9,18,9.9,tr_00016
-T P,0.35,3.2,12,7,5,0,0.75,0.75,7.9,7.9,12.6,9.9,tr_00015
-T P,0.35,3.2,13,6,5,0,0.75,0.75,7.9,7.9,19.8,9.9,tr_00014
-T P,0.35,2.3,5,7,11,0,0.75,0.75,6.1,6.1,10.8,9.45,tr_00013
-T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00012
-T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00011
-T N,0.35,2.9,14,9,2,0,0.75,0.75,7.3,7.3,25.2,2.25,tr_00010
-T N,0.35,2.9,2,9,14,0,0.75,0.75,7.3,7.3,23.4,2.25,tr_00009
-T N,0.35,1.4,3,6,2,0,0.75,0.75,4.3,4.3,5.4,3,tr_00008
-T N,0.35,2,4,7,3,0,0.75,0.75,5.5,5.5,7.2,3.3,tr_00007
-T N,0.35,1.4,2,7,8,0,0.75,0.75,4.3,4.3,12.6,3,tr_00006
-T N,0.35,1.4,10,6,2,0,0.75,0.75,4.3,4.3,18,3,tr_00005
-T N,0.35,1.7,9,11,10,0,0.75,0.75,4.9,4.9,16.2,3.15,tr_00004
-T N,0.35,1.7,8,13,9,0,0.75,0.75,4.9,4.9,14.4,3.15,tr_00003
-T N,0.35,1.1,2,6,13,0,0.75,0.75,3.7,3.7,19.8,3.15,tr_00002
-T N,0.35,1.1,11,7,2,0,0.75,0.75,3.7,3.7,10.8,3.15,tr_00001
-S 14,EXTERNAL,sout
-Q 0.00258522
-S 13,INTERNAL
-Q 0.00530431
-S 12,INTERNAL
-Q 0.00171257
-S 11,INTERNAL
-Q 0.00442919
-S 10,INTERNAL
-Q 0
-S 9,INTERNAL
-Q 0.00752047
-S 8,INTERNAL
-Q 0
-S 7,EXTERNAL,b
-Q 0.0069823
-S 6,EXTERNAL,a
-Q 0.0115667
-S 5,EXTERNAL,vdd
-Q 0.0134766
-S 4,INTERNAL
-Q 0.00589885
-S 3,INTERNAL
-Q 0
-S 2,EXTERNAL,vss
-Q 0.011949
-S 1,EXTERNAL,cout
-Q 0.00258522
-EOF
diff --git a/alliance/share/cells/sxlib/halfadder_x4.ap b/alliance/share/cells/sxlib/halfadder_x4.ap
deleted file mode 100644
index 8a9ab130..00000000
--- a/alliance/share/cells/sxlib/halfadder_x4.ap
+++ /dev/null
@@ -1,216 +0,0 @@
-V ALLIANCE : 6
-H halfadder_x4,P, 6/ 9/2000,100
-A 0,0,9000,5000
-R 1000,4000,ref_ref,cout_40
-R 1000,1000,ref_ref,cout_10
-R 1000,3000,ref_ref,cout_30
-R 1000,3500,ref_ref,cout_35
-R 1000,2500,ref_ref,cout_25
-R 1000,2000,ref_ref,cout_20
-R 1000,1500,ref_ref,cout_15
-R 1500,3000,ref_ref,a_30
-R 1500,3500,ref_ref,a_35
-R 1500,4000,ref_ref,a_40
-R 1500,1000,ref_ref,a_10
-R 1500,1500,ref_ref,a_15
-R 1500,2500,ref_ref,a_25
-R 1500,2000,ref_ref,a_20
-R 4000,3500,ref_ref,b_35
-R 4000,1000,ref_ref,b_10
-R 4000,1500,ref_ref,b_15
-R 4000,2000,ref_ref,b_20
-R 4000,2500,ref_ref,b_25
-R 4000,3000,ref_ref,b_30
-R 8000,4000,ref_ref,sout_40
-R 8000,1000,ref_ref,sout_10
-R 8000,3000,ref_ref,sout_30
-R 8000,3500,ref_ref,sout_35
-R 8000,2500,ref_ref,sout_25
-R 8000,2000,ref_ref,sout_20
-R 8000,1500,ref_ref,sout_15
-S 7500,2000,8400,2000,300,*,RIGHT,POLY
-S 1000,1000,1000,4000,200,cout,DOWN,CALU1
-S 1500,1000,1500,4000,200,a,DOWN,CALU1
-S 4000,1000,4000,3500,200,b,DOWN,CALU1
-S 8000,1000,8000,4000,200,sout,DOWN,CALU1
-S 600,2600,600,4900,100,*,UP,PTRANS
-S 300,2800,300,4700,300,*,DOWN,PDIF
-S 1200,2600,1200,4900,100,*,DOWN,PTRANS
-S 2700,3300,2700,4600,300,*,UP,PDIF
-S 900,2800,900,4700,300,*,UP,PDIF
-S 1500,2800,1500,4700,300,*,UP,PDIF
-S 8400,2600,8400,4900,100,*,UP,PTRANS
-S 8700,2800,8700,4700,300,*,DOWN,PDIF
-S 7500,3400,7500,4700,300,*,DOWN,PDIF
-S 8100,2800,8100,4700,300,*,DOWN,PDIF
-S 7800,2600,7800,4900,100,*,UP,PTRANS
-S 300,300,300,1200,300,*,UP,NDIF
-S 600,100,600,1400,100,*,DOWN,NTRANS
-S 1500,300,1500,1200,300,*,DOWN,NDIF
-S 900,300,900,1200,300,*,DOWN,NDIF
-S 1200,100,1200,1400,100,*,UP,NTRANS
-S 7500,300,7500,1000,300,*,UP,NDIF
-S 8700,300,8700,1200,300,*,UP,NDIF
-S 8100,300,8100,1200,300,*,UP,NDIF
-S 8400,100,8400,1400,100,*,DOWN,NTRANS
-S 7800,100,7800,1400,100,*,DOWN,NTRANS
-S 600,1400,600,2600,100,*,DOWN,POLY
-S 1500,1500,1800,1500,300,*,RIGHT,POLY
-S 1200,2000,2000,2000,100,*,RIGHT,POLY
-S 1800,2400,1800,3100,100,*,UP,POLY
-S 1200,1400,1200,2600,100,*,DOWN,POLY
-S 1500,2500,1800,2500,300,*,RIGHT,POLY
-S 3600,2600,4200,2600,100,*,RIGHT,POLY
-S 3600,1400,4200,1400,100,*,RIGHT,POLY
-S 3300,2000,5400,2000,100,*,RIGHT,POLY
-S 6000,1400,6600,1400,100,*,RIGHT,POLY
-S 6000,2000,6000,2600,100,*,DOWN,POLY
-S 6000,2000,7000,2000,100,*,RIGHT,POLY
-S 4800,2600,5100,2600,100,*,RIGHT,POLY
-S 7800,1400,7800,2600,100,*,DOWN,POLY
-S 8400,1400,8400,2600,100,*,DOWN,POLY
-S 0,300,9000,300,600,vss,RIGHT,CALU1
-S 300,3000,300,4500,200,*,DOWN,ALU1
-S 300,500,300,1000,200,*,DOWN,ALU1
-S 300,1000,300,1700,200,*,UP,ALU1
-S 0,4700,9000,4700,600,vdd,RIGHT,CALU1
-S 2500,2000,2500,3000,100,*,UP,ALU1
-S 2050,1000,2050,3500,100,*,UP,ALU1
-S 1500,4000,6500,4000,100,*,RIGHT,ALU1
-S 2050,1000,2700,1000,100,*,RIGHT,ALU1
-S 1500,1000,1500,4000,100,*,UP,ALU1
-S 4000,1000,4000,3500,100,*,UP,ALU1
-S 4500,3500,5700,3500,100,*,RIGHT,ALU1
-S 5700,3000,5700,3500,100,*,DOWN,ALU1
-S 3300,1000,3300,3000,100,*,DOWN,ALU1
-S 4500,3000,5100,3000,100,*,LEFT,ALU1
-S 4500,1000,4500,3000,100,*,UP,ALU1
-S 8700,1000,8700,1700,200,*,UP,ALU1
-S 5500,2000,6000,2000,100,*,RIGHT,ALU1
-S 5000,2500,6500,2500,100,*,RIGHT,ALU1
-S 4500,1000,7500,1000,100,*,RIGHT,ALU1
-S 7500,1000,7500,2000,100,*,DOWN,ALU1
-S 8700,500,8700,1000,200,*,DOWN,ALU1
-S 8700,3000,8700,4500,200,*,DOWN,ALU1
-S 7500,3500,7500,4500,200,*,DOWN,ALU1
-S 6500,1500,6500,4000,100,*,DOWN,ALU1
-S 7000,1500,7000,2900,100,*,DOWN,ALU1
-S 2600,3500,4000,3500,100,*,RIGHT,ALU1
-S 2600,3000,2600,3500,100,*,DOWN,ALU1
-S 2500,3000,2600,3000,100,*,LEFT,ALU1
-S 600,2000,1200,2000,300,*,LEFT,POLY
-S 2400,2000,2500,2000,100,*,RIGHT,POLY
-S 1800,600,1800,1400,100,*,UP,NTRANS
-S 1800,3100,1800,4300,100,*,DOWN,PTRANS
-S 2400,3100,2400,4300,100,*,DOWN,PTRANS
-S 2100,3300,2100,4100,300,*,UP,PDIF
-S 2400,1600,2400,2000,100,*,UP,POLY
-S 2400,600,2400,1600,100,*,UP,NTRANS
-S 2700,800,2700,1400,300,*,DOWN,NDIF
-S 2100,800,2100,1400,300,*,DOWN,NDIF
-S 4200,600,4200,1400,100,*,DOWN,NTRANS
-S 6000,600,6000,1400,100,*,DOWN,NTRANS
-S 4800,2600,4800,4000,100,*,UP,PTRANS
-S 5400,2600,5400,4000,100,*,UP,PTRANS
-S 6000,2600,6000,4000,100,*,UP,PTRANS
-S 4200,2600,4200,4000,100,*,UP,PTRANS
-S 3300,1000,3300,1200,300,*,UP,NDIF
-S 3900,400,3900,1200,300,*,UP,NDIF
-S 6300,400,6300,1200,300,*,UP,NDIF
-S 5000,1600,5500,1600,100,*,RIGHT,ALU1
-S 4800,1500,5100,1500,100,*,RIGHT,POLY
-S 5400,600,5400,1500,100,*,DOWN,NTRANS
-S 4800,600,4800,1500,100,*,DOWN,NTRANS
-S 5100,800,5100,1300,300,*,UP,NDIF
-S 4500,800,4500,1300,300,*,UP,NDIF
-S 5700,800,5700,1300,300,*,UP,NDIF
-S 5500,1600,5500,2000,100,*,DOWN,ALU1
-S 4500,2800,4500,3800,300,*,DOWN,PDIF
-S 5100,2800,5100,3800,300,*,DOWN,PDIF
-S 5700,2800,5700,3800,300,*,DOWN,PDIF
-S 3900,2800,3900,4500,300,*,DOWN,PDIF
-S 6300,2800,6300,4500,300,*,DOWN,PDIF
-S 0,3900,9000,3900,2400,*,LEFT,NWELL
-S 5400,1500,5400,2600,100,*,DOWN,POLY
-S 6600,700,6600,1400,100,*,DOWN,NTRANS
-S 6900,900,6900,1600,300,*,UP,NDIF
-S 3300,2800,3300,3500,300,*,UP,PDIF
-S 6900,2800,6900,3800,300,*,DOWN,PDIF
-S 6600,2600,6600,4000,100,*,UP,PTRANS
-S 3600,700,3600,1400,100,*,DOWN,NTRANS
-S 3600,2600,3600,3700,100,*,UP,PTRANS
-S 1000,1000,1000,4000,200,*,DOWN,ALU1
-S 8000,1000,8000,4000,200,*,DOWN,ALU1
-V 300,4500,CONT_DIF_P,*
-V 300,4000,CONT_DIF_P,*
-V 300,3500,CONT_DIF_P,*
-V 300,3000,CONT_DIF_P,*
-V 900,3500,CONT_DIF_P,*
-V 900,3000,CONT_DIF_P,*
-V 2700,4500,CONT_DIF_P,*
-V 2100,3500,CONT_DIF_P,*
-V 900,4000,CONT_DIF_P,*
-V 2100,4700,CONT_BODY_N,*
-V 1500,4500,CONT_DIF_P,*
-V 5700,3000,CONT_DIF_P,*
-V 5100,3000,CONT_DIF_P,*
-V 3900,4500,CONT_DIF_P,*
-V 6300,4500,CONT_DIF_P,*
-V 3300,4700,CONT_BODY_N,*
-V 6900,4700,CONT_BODY_N,*
-V 4500,3500,CONT_DIF_P,*
-V 5700,3500,CONT_DIF_P,*
-V 7500,4000,CONT_DIF_P,*
-V 7500,3500,CONT_DIF_P,*
-V 8700,3000,CONT_DIF_P,*
-V 8700,3500,CONT_DIF_P,*
-V 8700,4000,CONT_DIF_P,*
-V 8700,4500,CONT_DIF_P,*
-V 3300,3000,CONT_DIF_P,*
-V 7000,2900,CONT_DIF_P,*
-V 8100,3000,CONT_DIF_P,*
-V 8100,3500,CONT_DIF_P,*
-V 8100,4000,CONT_DIF_P,*
-V 7500,4500,CONT_DIF_P,*
-V 300,500,CONT_DIF_N,*
-V 300,1000,CONT_DIF_N,*
-V 1500,500,CONT_DIF_N,*
-V 2700,1000,CONT_DIF_N,*
-V 900,1000,CONT_DIF_N,*
-V 3300,1000,CONT_DIF_N,*
-V 3900,500,CONT_DIF_N,*
-V 6300,500,CONT_DIF_N,*
-V 7000,1500,CONT_DIF_N,*
-V 8100,1000,CONT_DIF_N,*
-V 8700,1000,CONT_DIF_N,*
-V 8700,500,CONT_DIF_N,*
-V 7500,500,CONT_DIF_N,*
-V 2700,300,CONT_BODY_P,*
-V 300,1700,CONT_BODY_P,*
-V 3300,300,CONT_BODY_P,*
-V 6900,300,CONT_BODY_P,*
-V 8700,1700,CONT_BODY_P,*
-V 2500,3000,CONT_POLY,*
-V 1600,1500,CONT_POLY,*
-V 2000,2000,CONT_POLY,*
-V 1600,2500,CONT_POLY,*
-V 2500,2000,CONT_POLY,*
-V 6500,1500,CONT_POLY,*
-V 5000,2500,CONT_POLY,*
-V 4000,2500,CONT_POLY,*
-V 4000,1500,CONT_POLY,*
-V 3300,2000,CONT_POLY,*
-V 7500,2000,CONT_POLY,*
-V 6000,2000,CONT_POLY,*
-V 7000,2000,CONT_POLY,*
-V 6500,2500,CONT_POLY,*
-V 5000,1600,CONT_POLY,*
-V 5100,1100,CONT_DIF_N,*
-V 5100,300,CONT_BODY_P,*
-V 5700,300,CONT_BODY_P,*
-V 4500,300,CONT_BODY_P,*
-V 2100,300,CONT_BODY_P,*
-V 5100,4700,CONT_BODY_N,*
-V 4500,4700,CONT_BODY_N,*
-V 5700,4700,CONT_BODY_N,*
-EOF
diff --git a/alliance/share/cells/sxlib/halfadder_x4.vbe b/alliance/share/cells/sxlib/halfadder_x4.vbe
deleted file mode 100644
index bbb062f9..00000000
--- a/alliance/share/cells/sxlib/halfadder_x4.vbe
+++ /dev/null
@@ -1,50 +0,0 @@
-ENTITY halfadder_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 4500;
-  CONSTANT cin_a	 : NATURAL := 27;
-  CONSTANT cin_b	 : NATURAL := 22;
-  CONSTANT rdown_a_cout	 : NATURAL := 810;
-  CONSTANT rdown_a_sout	 : NATURAL := 810;
-  CONSTANT rdown_a_sout	 : NATURAL := 810;
-  CONSTANT rdown_b_cout	 : NATURAL := 810;
-  CONSTANT rdown_b_sout	 : NATURAL := 810;
-  CONSTANT rdown_b_sout	 : NATURAL := 810;
-  CONSTANT rup_a_cout	 : NATURAL := 890;
-  CONSTANT rup_a_sout	 : NATURAL := 890;
-  CONSTANT rup_a_sout	 : NATURAL := 890;
-  CONSTANT rup_b_cout	 : NATURAL := 890;
-  CONSTANT rup_b_sout	 : NATURAL := 890;
-  CONSTANT rup_b_sout	 : NATURAL := 890;
-  CONSTANT tphh_a_cout	 : NATURAL := 467;
-  CONSTANT tpll_b_cout	 : NATURAL := 480;
-  CONSTANT tpll_a_cout	 : NATURAL := 494;
-  CONSTANT tphh_b_cout	 : NATURAL := 500;
-  CONSTANT tphh_a_sout	 : NATURAL := 527;
-  CONSTANT tpll_b_sout	 : NATURAL := 594;
-  CONSTANT tphl_b_sout	 : NATURAL := 607;
-  CONSTANT tplh_b_sout	 : NATURAL := 642;
-  CONSTANT tphh_b_sout	 : NATURAL := 655;
-  CONSTANT tphl_a_sout	 : NATURAL := 656;
-  CONSTANT tpll_a_sout	 : NATURAL := 665;
-  CONSTANT tplh_a_sout	 : NATURAL := 692;
-  CONSTANT transistors	 : NATURAL := 24
-);
-PORT (
-  a	 : in  BIT;
-  b	 : in  BIT;
-  cout	 : out BIT;
-  sout	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END halfadder_x4;
-
-ARCHITECTURE behaviour_data_flow OF halfadder_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on halfadder_x4"
-  SEVERITY WARNING;
-  sout <= (a xor b) after 1300 ps;
-  cout <= (a and b) after 1100 ps;
-END;
diff --git a/alliance/share/cells/sxlib/halfadder_x4.vhd b/alliance/share/cells/sxlib/halfadder_x4.vhd
deleted file mode 100644
index f253a47b..00000000
--- a/alliance/share/cells/sxlib/halfadder_x4.vhd
+++ /dev/null
@@ -1,22 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY halfadder_x4 IS
-PORT(
-  a	: IN STD_LOGIC;
-  b	: IN STD_LOGIC;
-  cout	: OUT STD_LOGIC;
-  sout	: OUT STD_LOGIC
-);
-END halfadder_x4;
-
-ARCHITECTURE RTL OF halfadder_x4 IS
-BEGIN
-  cout <= (a AND b);
-  sout <= (a XOR b);
-END RTL;
diff --git a/alliance/share/cells/sxlib/inv_x1.al b/alliance/share/cells/sxlib/inv_x1.al
deleted file mode 100644
index 5ae39942..00000000
--- a/alliance/share/cells/sxlib/inv_x1.al
+++ /dev/null
@@ -1,17 +0,0 @@
-V ALLIANCE : 6
-H inv_x1,L,30/10/99
-C i,IN,EXTERNAL,4
-C nq,OUT,EXTERNAL,2
-C vdd,IN,EXTERNAL,3
-C vss,IN,EXTERNAL,1
-T P,0.35,2.9,2,4,3,0,0.75,0.75,7.3,7.3,2.1,9.75,tr_00002
-T N,0.35,1.4,1,4,2,0,0.75,0.75,4.3,4.3,2.1,3,tr_00001
-S 4,EXTERNAL,i
-Q 0.00353623
-S 3,EXTERNAL,vdd
-Q 0.00230273
-S 2,EXTERNAL,nq
-Q 0.00240895
-S 1,EXTERNAL,vss
-Q 0.00230273
-EOF
diff --git a/alliance/share/cells/sxlib/inv_x1.ap b/alliance/share/cells/sxlib/inv_x1.ap
deleted file mode 100644
index 2c3572d7..00000000
--- a/alliance/share/cells/sxlib/inv_x1.ap
+++ /dev/null
@@ -1,41 +0,0 @@
-V ALLIANCE : 6
-H inv_x1,P,30/ 8/2000,100
-A 0,0,1500,5000
-R 1000,4000,ref_ref,nq_40
-R 1000,3500,ref_ref,nq_35
-R 1000,3000,ref_ref,nq_30
-R 1000,2500,ref_ref,nq_25
-R 1000,2000,ref_ref,nq_20
-R 1000,1500,ref_ref,nq_15
-R 1000,1000,ref_ref,nq_10
-R 500,1000,ref_ref,i_10
-R 500,1500,ref_ref,i_15
-R 500,2000,ref_ref,i_20
-R 500,2500,ref_ref,i_25
-R 500,3000,ref_ref,i_30
-R 500,3500,ref_ref,i_35
-R 500,4000,ref_ref,i_40
-S 1000,1000,1000,4000,200,*,DOWN,ALU1
-S 1000,2800,1000,3700,300,*,DOWN,PDIF
-S 700,2600,700,3900,100,*,UP,PTRANS
-S 1000,800,1000,1200,300,*,UP,NDIF
-S 700,600,700,1400,100,*,DOWN,NTRANS
-S 0,300,1500,300,600,vss,RIGHT,CALU1
-S 0,4700,1500,4700,600,vdd,RIGHT,CALU1
-S 400,2000,700,2000,300,*,RIGHT,POLY
-S 700,1400,700,2600,100,*,UP,POLY
-S 500,1000,500,4000,100,*,DOWN,ALU1
-S 0,3900,1500,3900,2400,*,RIGHT,NWELL
-S 350,400,350,1200,400,*,UP,NDIF
-S 350,2800,350,4600,400,*,DOWN,PDIF
-S 1000,1000,1000,4000,200,nq,DOWN,CALU1
-S 500,1000,500,4000,200,i,DOWN,CALU1
-V 1000,3000,CONT_DIF_P,*
-V 400,4500,CONT_DIF_P,*
-V 1000,3500,CONT_DIF_P,*
-V 400,500,CONT_DIF_N,*
-V 1000,1000,CONT_DIF_N,*
-V 500,2000,CONT_POLY,*
-V 1000,4700,CONT_BODY_N,*
-V 1000,300,CONT_BODY_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/inv_x1.sym b/alliance/share/cells/sxlib/inv_x1.sym
deleted file mode 100644
index dc735e9d..00000000
Binary files a/alliance/share/cells/sxlib/inv_x1.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/inv_x1.vbe b/alliance/share/cells/sxlib/inv_x1.vbe
deleted file mode 100644
index 67e85e02..00000000
--- a/alliance/share/cells/sxlib/inv_x1.vbe
+++ /dev/null
@@ -1,26 +0,0 @@
-ENTITY inv_x1 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 750;
-  CONSTANT cin_i	 : NATURAL := 8;
-  CONSTANT rdown_i_nq	 : NATURAL := 3640;
-  CONSTANT rup_i_nq	 : NATURAL := 3720;
-  CONSTANT tphl_i_nq	 : NATURAL := 101;
-  CONSTANT tplh_i_nq	 : NATURAL := 139;
-  CONSTANT transistors	 : NATURAL := 2
-);
-PORT (
-  i	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END inv_x1;
-
-ARCHITECTURE behaviour_data_flow OF inv_x1 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on inv_x1"
-  SEVERITY WARNING;
-  nq <= not (i) after 700 ps;
-END;
diff --git a/alliance/share/cells/sxlib/inv_x1.vhd b/alliance/share/cells/sxlib/inv_x1.vhd
deleted file mode 100644
index 92c2d59a..00000000
--- a/alliance/share/cells/sxlib/inv_x1.vhd
+++ /dev/null
@@ -1,19 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY inv_x1 IS
-PORT(
-  i	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END inv_x1;
-
-ARCHITECTURE RTL OF inv_x1 IS
-BEGIN
-  nq <= NOT(i);
-END RTL;
diff --git a/alliance/share/cells/sxlib/inv_x2.al b/alliance/share/cells/sxlib/inv_x2.al
deleted file mode 100644
index c02fcb01..00000000
--- a/alliance/share/cells/sxlib/inv_x2.al
+++ /dev/null
@@ -1,17 +0,0 @@
-V ALLIANCE : 6
-H inv_x2,L,30/10/99
-C i,IN,EXTERNAL,4
-C nq,OUT,EXTERNAL,1
-C vdd,IN,EXTERNAL,3
-C vss,IN,EXTERNAL,2
-T P,0.35,4.4,1,4,3,0,0.75,0.75,10.3,10.3,2.1,10.5,tr_00002
-T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,2.1,3.75,tr_00001
-S 4,EXTERNAL,i
-Q 0.0031892
-S 3,EXTERNAL,vdd
-Q 0.00230273
-S 2,EXTERNAL,vss
-Q 0.00230273
-S 1,EXTERNAL,nq
-Q 0.00276148
-EOF
diff --git a/alliance/share/cells/sxlib/inv_x2.ap b/alliance/share/cells/sxlib/inv_x2.ap
deleted file mode 100644
index 4cd20dba..00000000
--- a/alliance/share/cells/sxlib/inv_x2.ap
+++ /dev/null
@@ -1,43 +0,0 @@
-V ALLIANCE : 6
-H inv_x2,P,30/ 8/2000,100
-A 0,0,1500,5000
-R 500,4000,ref_ref,i_40
-R 500,3500,ref_ref,i_35
-R 500,3000,ref_ref,i_30
-R 500,2500,ref_ref,i_25
-R 500,2000,ref_ref,i_20
-R 500,1500,ref_ref,i_15
-R 500,1000,ref_ref,i_10
-R 1000,1000,ref_ref,nq_10
-R 1000,1500,ref_ref,nq_15
-R 1000,2000,ref_ref,nq_20
-R 1000,2500,ref_ref,nq_25
-R 1000,3000,ref_ref,nq_30
-R 1000,3500,ref_ref,nq_35
-R 1000,4000,ref_ref,nq_40
-S 0,300,1500,300,600,vss,RIGHT,CALU1
-S 1000,1000,1000,4000,200,*,DOWN,ALU1
-S 500,1000,500,4000,100,*,DOWN,ALU1
-S 400,2000,700,2000,300,*,RIGHT,POLY
-S 700,2600,700,4400,100,*,UP,PTRANS
-S 1000,2800,1000,4200,300,*,DOWN,PDIF
-S 700,1900,700,2600,100,*,UP,POLY
-S 700,600,700,1900,100,*,DOWN,NTRANS
-S 1000,800,1000,1700,300,*,UP,NDIF
-S 0,4700,1500,4700,600,vdd,RIGHT,CALU1
-S 0,3900,1500,3900,2400,*,RIGHT,NWELL
-S 350,400,350,1700,400,*,UP,NDIF
-S 350,2800,350,4600,400,*,DOWN,PDIF
-S 500,1000,500,4000,200,i,DOWN,CALU1
-S 1000,1000,1000,4000,200,nq,DOWN,CALU1
-V 500,2000,CONT_POLY,*
-V 1000,1000,CONT_DIF_N,*
-V 400,500,CONT_DIF_N,*
-V 1000,3500,CONT_DIF_P,*
-V 400,4500,CONT_DIF_P,*
-V 1000,4000,CONT_DIF_P,*
-V 1000,3000,CONT_DIF_P,*
-V 1000,1500,CONT_DIF_N,*
-V 1000,4700,CONT_BODY_N,*
-V 1000,300,CONT_BODY_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/inv_x2.sym b/alliance/share/cells/sxlib/inv_x2.sym
deleted file mode 100644
index 93f40e69..00000000
Binary files a/alliance/share/cells/sxlib/inv_x2.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/inv_x2.vbe b/alliance/share/cells/sxlib/inv_x2.vbe
deleted file mode 100644
index 9df0116d..00000000
--- a/alliance/share/cells/sxlib/inv_x2.vbe
+++ /dev/null
@@ -1,26 +0,0 @@
-ENTITY inv_x2 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 750;
-  CONSTANT cin_i	 : NATURAL := 12;
-  CONSTANT rdown_i_nq	 : NATURAL := 1620;
-  CONSTANT rup_i_nq	 : NATURAL := 2420;
-  CONSTANT tphl_i_nq	 : NATURAL := 69;
-  CONSTANT tplh_i_nq	 : NATURAL := 163;
-  CONSTANT transistors	 : NATURAL := 2
-);
-PORT (
-  i	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END inv_x2;
-
-ARCHITECTURE behaviour_data_flow OF inv_x2 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on inv_x2"
-  SEVERITY WARNING;
-  nq <= not (i) after 800 ps;
-END;
diff --git a/alliance/share/cells/sxlib/inv_x2.vhd b/alliance/share/cells/sxlib/inv_x2.vhd
deleted file mode 100644
index d4b14dd6..00000000
--- a/alliance/share/cells/sxlib/inv_x2.vhd
+++ /dev/null
@@ -1,19 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY inv_x2 IS
-PORT(
-  i	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END inv_x2;
-
-ARCHITECTURE RTL OF inv_x2 IS
-BEGIN
-  nq <= NOT(i);
-END RTL;
diff --git a/alliance/share/cells/sxlib/inv_x4.al b/alliance/share/cells/sxlib/inv_x4.al
deleted file mode 100644
index bb87114c..00000000
--- a/alliance/share/cells/sxlib/inv_x4.al
+++ /dev/null
@@ -1,19 +0,0 @@
-V ALLIANCE : 6
-H inv_x4,L,30/10/99
-C i,IN,EXTERNAL,4
-C nq,OUT,EXTERNAL,1
-C vdd,IN,EXTERNAL,3
-C vss,IN,EXTERNAL,2
-T P,0.35,4.1,3,4,1,0,0.75,0.75,9.7,9.7,3.9,12.15,tr_00004
-T P,0.35,5.9,1,4,3,0,0.75,0.75,13.3,13.3,2.1,11.25,tr_00003
-T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,2.1,2.25,tr_00002
-T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,3.9,2.25,tr_00001
-S 4,EXTERNAL,i
-Q 0.00530442
-S 3,EXTERNAL,vdd
-Q 0.00423058
-S 2,EXTERNAL,vss
-Q 0.0038193
-S 1,EXTERNAL,nq
-Q 0.00258522
-EOF
diff --git a/alliance/share/cells/sxlib/inv_x4.ap b/alliance/share/cells/sxlib/inv_x4.ap
deleted file mode 100644
index a9cd56af..00000000
--- a/alliance/share/cells/sxlib/inv_x4.ap
+++ /dev/null
@@ -1,54 +0,0 @@
-V ALLIANCE : 6
-H inv_x4,P,30/ 8/2000,100
-A 0,0,2000,5000
-R 1000,1000,ref_ref,nq_10
-R 1000,1500,ref_ref,nq_15
-R 1000,2000,ref_ref,nq_20
-R 1000,2500,ref_ref,nq_25
-R 1000,3000,ref_ref,nq_30
-R 1000,3500,ref_ref,nq_35
-R 1000,4000,ref_ref,nq_40
-R 500,4000,ref_ref,i_40
-R 500,3500,ref_ref,i_35
-R 500,3000,ref_ref,i_30
-R 500,2500,ref_ref,i_25
-R 500,2000,ref_ref,i_20
-R 500,1500,ref_ref,i_15
-R 500,1000,ref_ref,i_10
-S 1000,1000,1000,4000,200,nq,DOWN,CALU1
-S 500,1000,500,4000,200,i,DOWN,CALU1
-S 0,300,2000,300,600,vss,RIGHT,CALU1
-S 0,3900,2000,3900,2400,*,LEFT,NWELL
-S 0,4700,2000,4700,600,vdd,RIGHT,CALU1
-S 1600,2900,1600,4500,200,*,DOWN,ALU1
-S 1600,500,1600,1700,200,*,DOWN,ALU1
-S 1600,3400,1600,4700,300,*,DOWN,PDIF
-S 1300,1400,1300,3200,100,*,UP,POLY
-S 1300,3200,1300,4900,100,*,UP,PTRANS
-S 400,300,400,1200,300,*,UP,NDIF
-S 1000,300,1000,1200,300,*,UP,NDIF
-S 700,100,700,1400,100,*,DOWN,NTRANS
-S 1300,100,1300,1400,100,*,DOWN,NTRANS
-S 1600,300,1600,1200,300,*,UP,NDIF
-S 500,1500,1300,1500,300,*,RIGHT,POLY
-S 400,2800,400,4700,300,*,DOWN,PDIF
-S 1000,2800,1000,4700,300,*,DOWN,PDIF
-S 700,2600,700,4900,100,*,UP,PTRANS
-S 700,1400,700,2600,100,*,UP,POLY
-S 500,1000,500,4000,100,*,DOWN,ALU1
-S 1000,1000,1000,4000,200,*,DOWN,ALU1
-V 1600,2900,CONT_BODY_N,*
-V 1600,1700,CONT_BODY_P,*
-V 400,500,CONT_DIF_N,*
-V 1000,1000,CONT_DIF_N,*
-V 1600,500,CONT_DIF_N,*
-V 1600,1000,CONT_DIF_N,*
-V 500,1500,CONT_POLY,*
-V 1600,4000,CONT_DIF_P,*
-V 1000,3500,CONT_DIF_P,*
-V 1000,3000,CONT_DIF_P,*
-V 1600,3500,CONT_DIF_P,*
-V 1600,4500,CONT_DIF_P,*
-V 1000,4000,CONT_DIF_P,*
-V 400,4500,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/inv_x4.sym b/alliance/share/cells/sxlib/inv_x4.sym
deleted file mode 100644
index 2a1da33c..00000000
Binary files a/alliance/share/cells/sxlib/inv_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/inv_x4.vbe b/alliance/share/cells/sxlib/inv_x4.vbe
deleted file mode 100644
index 3091ae3f..00000000
--- a/alliance/share/cells/sxlib/inv_x4.vbe
+++ /dev/null
@@ -1,26 +0,0 @@
-ENTITY inv_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 1000;
-  CONSTANT cin_i	 : NATURAL := 26;
-  CONSTANT rdown_i_nq	 : NATURAL := 810;
-  CONSTANT rup_i_nq	 : NATURAL := 1060;
-  CONSTANT tphl_i_nq	 : NATURAL := 71;
-  CONSTANT tplh_i_nq	 : NATURAL := 143;
-  CONSTANT transistors	 : NATURAL := 4
-);
-PORT (
-  i	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END inv_x4;
-
-ARCHITECTURE behaviour_data_flow OF inv_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on inv_x4"
-  SEVERITY WARNING;
-  nq <= not (i) after 700 ps;
-END;
diff --git a/alliance/share/cells/sxlib/inv_x4.vhd b/alliance/share/cells/sxlib/inv_x4.vhd
deleted file mode 100644
index 2263c327..00000000
--- a/alliance/share/cells/sxlib/inv_x4.vhd
+++ /dev/null
@@ -1,19 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY inv_x4 IS
-PORT(
-  i	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END inv_x4;
-
-ARCHITECTURE RTL OF inv_x4 IS
-BEGIN
-  nq <= NOT(i);
-END RTL;
diff --git a/alliance/share/cells/sxlib/inv_x8.al b/alliance/share/cells/sxlib/inv_x8.al
deleted file mode 100644
index f3b8f6ac..00000000
--- a/alliance/share/cells/sxlib/inv_x8.al
+++ /dev/null
@@ -1,23 +0,0 @@
-V ALLIANCE : 6
-H inv_x8,L,30/10/99
-C i,IN,EXTERNAL,4
-C nq,OUT,EXTERNAL,2
-C vdd,IN,EXTERNAL,3
-C vss,IN,EXTERNAL,1
-T P,0.35,5.9,2,4,3,0,0.75,0.75,13.3,13.3,2.1,11.25,tr_00008
-T P,0.35,5.9,3,4,2,0,0.75,0.75,13.3,13.3,3.9,11.25,tr_00007
-T P,0.35,5.9,3,4,2,0,0.75,0.75,13.3,13.3,7.5,11.25,tr_00006
-T P,0.35,5.9,2,4,3,0,0.75,0.75,13.3,13.3,5.7,11.25,tr_00005
-T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,3.9,2.25,tr_00004
-T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,2.1,2.25,tr_00003
-T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,7.5,2.25,tr_00002
-T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,5.7,2.25,tr_00001
-S 4,EXTERNAL,i
-Q 0.00785425
-S 3,EXTERNAL,vdd
-Q 0.0074877
-S 2,EXTERNAL,nq
-Q 0.00599301
-S 1,EXTERNAL,vss
-Q 0.00613633
-EOF
diff --git a/alliance/share/cells/sxlib/inv_x8.ap b/alliance/share/cells/sxlib/inv_x8.ap
deleted file mode 100644
index e2f85ee0..00000000
--- a/alliance/share/cells/sxlib/inv_x8.ap
+++ /dev/null
@@ -1,84 +0,0 @@
-V ALLIANCE : 6
-H inv_x8,P,30/ 8/2000,100
-A 0,0,3500,5000
-R 500,4000,ref_ref,i_40
-R 500,3500,ref_ref,i_35
-R 500,3000,ref_ref,i_30
-R 500,2500,ref_ref,i_25
-R 500,2000,ref_ref,i_20
-R 500,1500,ref_ref,i_15
-R 500,1000,ref_ref,i_10
-R 1000,4000,ref_ref,nq_40
-R 1000,3500,ref_ref,nq_35
-R 1000,3000,ref_ref,nq_30
-R 1000,2500,ref_ref,nq_25
-R 1000,2000,ref_ref,nq_20
-R 1000,1500,ref_ref,nq_15
-R 1000,1000,ref_ref,nq_10
-S 500,1000,500,4000,200,i,DOWN,CALU1
-S 1000,1000,1000,4000,200,nq,DOWN,CALU1
-S 0,3900,3500,3900,2400,*,LEFT,NWELL
-S 2800,300,2800,1200,300,*,UP,NDIF
-S 0,300,3500,300,600,vss,RIGHT,CALU1
-S 0,4700,3500,4700,600,vdd,RIGHT,CALU1
-S 2500,1400,2500,2600,100,*,UP,POLY
-S 1900,1400,1900,2600,100,*,UP,POLY
-S 1300,1400,1300,2600,100,*,UP,POLY
-S 700,1400,700,2600,100,*,UP,POLY
-S 400,2800,400,4700,300,*,DOWN,PDIF
-S 1000,2800,1000,4700,300,*,DOWN,PDIF
-S 700,2600,700,4900,100,*,UP,PTRANS
-S 1600,2800,1600,4700,300,*,DOWN,PDIF
-S 1300,2600,1300,4900,100,*,UP,PTRANS
-S 2500,2600,2500,4900,100,*,UP,PTRANS
-S 2200,2800,2200,4700,300,*,DOWN,PDIF
-S 1900,2600,1900,4900,100,*,UP,PTRANS
-S 1300,100,1300,1400,100,*,DOWN,NTRANS
-S 1600,300,1600,1200,300,*,UP,NDIF
-S 700,100,700,1400,100,*,DOWN,NTRANS
-S 1000,300,1000,1200,300,*,UP,NDIF
-S 400,300,400,1200,300,*,UP,NDIF
-S 2200,300,2200,1200,300,*,UP,NDIF
-S 2500,100,2500,1400,100,*,DOWN,NTRANS
-S 1900,100,1900,1400,100,*,DOWN,NTRANS
-S 500,1000,500,4000,100,*,DOWN,ALU1
-S 1600,500,1600,1000,200,*,DOWN,ALU1
-S 1600,3000,1600,4500,200,*,UP,ALU1
-S 400,1500,2500,1500,300,*,RIGHT,POLY
-S 2700,1700,3300,1700,300,*,RIGHT,PTIE
-S 2800,3900,2800,4700,300,*,DOWN,PDIF
-S 3200,2800,3200,3500,300,*,UP,NTIE
-S 2200,1000,2200,4000,200,*,DOWN,ALU1
-S 1000,2000,2200,2000,200,*,LEFT,ALU1
-S 1000,1000,1000,4000,200,*,DOWN,ALU1
-S 2800,1700,3200,1700,200,*,LEFT,ALU1
-S 2800,500,2800,1700,200,*,DOWN,ALU1
-S 3200,2900,3200,3400,200,*,UP,ALU1
-S 2750,3400,3200,3400,200,*,LEFT,ALU1
-S 2800,3350,2800,4500,200,*,UP,ALU1
-V 2800,500,CONT_DIF_N,*
-V 1000,3500,CONT_DIF_P,*
-V 1000,3000,CONT_DIF_P,*
-V 400,4500,CONT_DIF_P,*
-V 1600,4000,CONT_DIF_P,*
-V 1600,4500,CONT_DIF_P,*
-V 1600,3500,CONT_DIF_P,*
-V 1600,3000,CONT_DIF_P,*
-V 1000,4000,CONT_DIF_P,*
-V 2200,4000,CONT_DIF_P,*
-V 2200,3500,CONT_DIF_P,*
-V 2200,3000,CONT_DIF_P,*
-V 1000,1000,CONT_DIF_N,*
-V 400,500,CONT_DIF_N,*
-V 2200,1000,CONT_DIF_N,*
-V 2800,1000,CONT_DIF_N,*
-V 1600,500,CONT_DIF_N,*
-V 1600,1000,CONT_DIF_N,*
-V 500,1500,CONT_POLY,*
-V 2800,1700,CONT_BODY_P,*
-V 3200,1700,CONT_BODY_P,*
-V 3200,2900,CONT_BODY_N,*
-V 2800,4500,CONT_DIF_P,*
-V 2800,4000,CONT_DIF_P,*
-V 3200,3400,CONT_BODY_N,*
-EOF
diff --git a/alliance/share/cells/sxlib/inv_x8.sym b/alliance/share/cells/sxlib/inv_x8.sym
deleted file mode 100644
index c0564bf1..00000000
Binary files a/alliance/share/cells/sxlib/inv_x8.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/inv_x8.vbe b/alliance/share/cells/sxlib/inv_x8.vbe
deleted file mode 100644
index 4e6fa063..00000000
--- a/alliance/share/cells/sxlib/inv_x8.vbe
+++ /dev/null
@@ -1,26 +0,0 @@
-ENTITY inv_x8 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 1750;
-  CONSTANT cin_i	 : NATURAL := 54;
-  CONSTANT rdown_i_nq	 : NATURAL := 400;
-  CONSTANT rup_i_nq	 : NATURAL := 450;
-  CONSTANT tphl_i_nq	 : NATURAL := 86;
-  CONSTANT tplh_i_nq	 : NATURAL := 133;
-  CONSTANT transistors	 : NATURAL := 8
-);
-PORT (
-  i	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END inv_x8;
-
-ARCHITECTURE behaviour_data_flow OF inv_x8 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on inv_x8"
-  SEVERITY WARNING;
-  nq <= not (i) after 700 ps;
-END;
diff --git a/alliance/share/cells/sxlib/inv_x8.vhd b/alliance/share/cells/sxlib/inv_x8.vhd
deleted file mode 100644
index 9d32ed3c..00000000
--- a/alliance/share/cells/sxlib/inv_x8.vhd
+++ /dev/null
@@ -1,19 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY inv_x8 IS
-PORT(
-  i	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END inv_x8;
-
-ARCHITECTURE RTL OF inv_x8 IS
-BEGIN
-  nq <= NOT(i);
-END RTL;
diff --git a/alliance/share/cells/sxlib/mx2_x2.al b/alliance/share/cells/sxlib/mx2_x2.al
deleted file mode 100644
index 719679f7..00000000
--- a/alliance/share/cells/sxlib/mx2_x2.al
+++ /dev/null
@@ -1,45 +0,0 @@
-V ALLIANCE : 6
-H mx2_x2,L,30/10/99
-C cmd,IN,EXTERNAL,6
-C i0,IN,EXTERNAL,7
-C i1,IN,EXTERNAL,8
-C q,OUT,EXTERNAL,9
-C vdd,IN,EXTERNAL,10
-C vss,IN,EXTERNAL,1
-T P,0.35,2.9,10,7,11,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00012
-T P,0.35,2.9,2,3,12,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00011
-T P,0.35,2.9,11,6,2,0,0.75,0.75,7.3,7.3,4.8,11.25,tr_00010
-T P,0.35,2.9,3,6,10,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00009
-T P,0.35,2.9,12,8,10,0,0.75,0.75,7.3,7.3,8.4,11.25,tr_00008
-T P,0.35,5.9,10,2,9,0,0.75,0.75,13.3,13.3,11.4,11.25,tr_00007
-T N,0.35,2.9,9,2,1,0,0.75,0.75,7.3,7.3,11.4,2.25,tr_00006
-T N,0.35,1.4,4,7,1,0,0.75,0.75,4.3,4.3,3.6,1.5,tr_00005
-T N,0.35,1.4,2,3,4,0,0.75,0.75,4.3,4.3,4.8,1.5,tr_00004
-T N,0.35,1.4,1,6,3,0,0.75,0.75,4.3,4.3,1.8,1.5,tr_00003
-T N,0.35,1.4,5,6,2,0,0.75,0.75,4.3,4.3,7.2,1.5,tr_00002
-T N,0.35,1.4,1,8,5,0,0.75,0.75,4.3,4.3,8.4,1.5,tr_00001
-S 12,INTERNAL
-Q 0
-S 11,INTERNAL
-Q 0
-S 10,EXTERNAL,vdd
-Q 0.00658426
-S 9,EXTERNAL,q
-Q 0.00264397
-S 8,EXTERNAL,i1
-Q 0.00371745
-S 7,EXTERNAL,i0
-Q 0.00336619
-S 6,EXTERNAL,cmd
-Q 0.00660261
-S 5,INTERNAL
-Q 0
-S 4,INTERNAL
-Q 0
-S 3,INTERNAL
-Q 0.00595297
-S 2,INTERNAL
-Q 0.0047485
-S 1,EXTERNAL,vss
-Q 0.00552667
-EOF
diff --git a/alliance/share/cells/sxlib/mx2_x2.ap b/alliance/share/cells/sxlib/mx2_x2.ap
deleted file mode 100644
index 82901f4c..00000000
--- a/alliance/share/cells/sxlib/mx2_x2.ap
+++ /dev/null
@@ -1,117 +0,0 @@
-V ALLIANCE : 6
-H mx2_x2,P,30/ 8/2000,100
-A 0,0,4500,5000
-R 3000,4000,ref_ref,i1_40
-R 3000,3500,ref_ref,i1_35
-R 3000,3000,ref_ref,i1_30
-R 3000,2500,ref_ref,i1_25
-R 3000,2000,ref_ref,i1_20
-R 3000,1500,ref_ref,i1_15
-R 3000,1000,ref_ref,i1_10
-R 1000,4000,ref_ref,i0_40
-R 1000,3500,ref_ref,i0_35
-R 1000,3000,ref_ref,i0_30
-R 1000,2500,ref_ref,i0_25
-R 1000,2000,ref_ref,i0_20
-R 1000,1500,ref_ref,i0_15
-R 4000,1000,ref_ref,q_10
-R 4000,3000,ref_ref,q_30
-R 4000,2000,ref_ref,q_20
-R 4000,1500,ref_ref,q_15
-R 4000,4000,ref_ref,q_40
-R 4000,3500,ref_ref,q_35
-R 4000,2500,ref_ref,q_25
-R 1500,4000,ref_ref,cmd_40
-R 1500,3500,ref_ref,cmd_35
-R 1500,3000,ref_ref,cmd_30
-R 1500,2500,ref_ref,cmd_25
-R 1500,2000,ref_ref,cmd_20
-R 1500,1500,ref_ref,cmd_15
-S 3000,1000,3000,4000,200,i1,DOWN,CALU1
-S 1000,1500,1000,4000,200,i0,DOWN,CALU1
-S 4000,1000,4000,4000,200,q,DOWN,CALU1
-S 1500,1500,1500,4000,200,cmd,DOWN,CALU1
-S 4000,950,4000,4050,200,*,DOWN,ALU1
-S 600,2000,2400,2000,100,*,RIGHT,POLY
-S 300,1000,2500,1000,100,*,RIGHT,ALU1
-S 1000,1500,1000,4000,100,*,DOWN,ALU1
-S 0,4700,4500,4700,600,vdd,RIGHT,CALU1
-S 0,300,4500,300,600,vss,RIGHT,CALU1
-S 300,3300,300,4200,300,*,DOWN,PDIF
-S 300,1000,300,4000,100,*,DOWN,ALU1
-S 1600,2000,1600,3100,100,*,UP,POLY
-S 1200,3100,1200,4400,100,*,DOWN,PTRANS
-S 2400,3100,2400,4400,100,*,DOWN,PTRANS
-S 1600,3100,1600,4400,100,*,DOWN,PTRANS
-S 900,3300,900,4600,300,*,DOWN,PDIF
-S 600,3100,600,4400,100,*,DOWN,PTRANS
-S 2000,3300,2000,4200,500,*,DOWN,PDIF
-S 2000,1500,2000,4000,100,*,DOWN,ALU1
-S 4100,300,4100,1200,300,*,DOWN,NDIF
-S 3800,100,3800,1400,100,*,UP,NTRANS
-S 2800,3100,2800,4400,100,*,DOWN,PTRANS
-S 3300,300,3300,1200,700,*,DOWN,NDIF
-S 3300,3300,3300,4700,700,*,UP,PDIF
-S 3500,3000,3500,4500,200,*,UP,ALU1
-S 2000,2300,3800,2300,100,*,RIGHT,POLY
-S 2500,1000,2500,2700,100,*,UP,ALU1
-S 2400,2800,2400,3100,100,*,UP,POLY
-S 2800,3100,3100,3100,100,*,RIGHT,POLY
-S 900,3100,1200,3100,100,*,RIGHT,POLY
-S 2800,1400,3100,1400,100,*,RIGHT,POLY
-S 0,3900,4500,3900,2400,*,RIGHT,NWELL
-S 1200,100,1200,900,100,*,UP,NTRANS
-S 1600,100,1600,900,100,*,UP,NTRANS
-S 3500,500,3500,1700,200,*,DOWN,ALU1
-S 600,100,600,900,100,*,UP,NTRANS
-S 900,300,900,700,300,*,UP,NDIF
-S 300,300,300,1200,300,*,UP,NDIF
-S 600,900,600,3100,100,*,DOWN,POLY
-S 2400,100,2400,900,100,*,UP,NTRANS
-S 2800,100,2800,900,100,*,UP,NTRANS
-S 2400,900,2400,2000,100,*,DOWN,POLY
-S 2800,900,2800,1400,100,*,DOWN,POLY
-S 2000,300,2000,1600,300,*,DOWN,NDIF
-S 1000,1400,1200,1400,100,*,LEFT,POLY
-S 1200,900,1200,1400,100,*,DOWN,POLY
-S 1500,1500,1500,4000,100,*,UP,ALU1
-S 2000,300,2000,700,500,*,DOWN,NDIF
-S 1500,4700,2500,4700,300,*,RIGHT,NTIE
-S 2100,300,2100,1600,300,*,DOWN,NDIF
-S 3000,1000,3000,4000,100,*,DOWN,ALU1
-S 3800,1400,3800,2600,100,*,DOWN,POLY
-S 3800,2600,3800,4900,100,*,DOWN,PTRANS
-S 4100,2800,4100,4700,300,*,UP,PDIF
-S 3500,2800,3500,3300,300,*,DOWN,PDIF
-V 3000,1500,CONT_POLY,*
-V 300,4700,CONT_BODY_N,*
-V 900,500,CONT_DIF_N,*
-V 300,1000,CONT_DIF_N,*
-V 900,4500,CONT_DIF_P,*
-V 1000,1500,CONT_POLY,*
-V 300,4000,CONT_DIF_P,*
-V 300,3500,CONT_DIF_P,*
-V 1000,3000,CONT_POLY,*
-V 3000,3000,CONT_POLY,*
-V 2000,1500,CONT_DIF_N,*
-V 2000,3500,CONT_DIF_P,*
-V 2000,4700,CONT_BODY_N,*
-V 2000,4000,CONT_DIF_P,*
-V 3500,3500,CONT_DIF_P,*
-V 3500,4000,CONT_DIF_P,*
-V 4100,3500,CONT_DIF_P,*
-V 4100,4000,CONT_DIF_P,*
-V 4100,3000,CONT_DIF_P,*
-V 4100,1000,CONT_DIF_N,*
-V 3500,500,CONT_DIF_N,*
-V 3500,4500,CONT_DIF_P,*
-V 3500,1000,CONT_DIF_N,*
-V 3500,3000,CONT_DIF_P,*
-V 2500,2700,CONT_POLY,*
-V 2000,2400,CONT_POLY,*
-V 3500,1700,CONT_BODY_P,*
-V 1500,2000,CONT_POLY,*
-V 1600,1000,CONT_POLY,*
-V 1500,4700,CONT_BODY_N,*
-V 2500,4700,CONT_BODY_N,*
-EOF
diff --git a/alliance/share/cells/sxlib/mx2_x2.sym b/alliance/share/cells/sxlib/mx2_x2.sym
deleted file mode 100644
index 572a87c6..00000000
Binary files a/alliance/share/cells/sxlib/mx2_x2.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/mx2_x2.vbe b/alliance/share/cells/sxlib/mx2_x2.vbe
deleted file mode 100644
index 7e478744..00000000
--- a/alliance/share/cells/sxlib/mx2_x2.vbe
+++ /dev/null
@@ -1,42 +0,0 @@
-ENTITY mx2_x2 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 2250;
-  CONSTANT cin_cmd	 : NATURAL := 17;
-  CONSTANT cin_i0	 : NATURAL := 8;
-  CONSTANT cin_i1	 : NATURAL := 9;
-  CONSTANT rdown_cmd_q	 : NATURAL := 1620;
-  CONSTANT rdown_cmd_q	 : NATURAL := 1620;
-  CONSTANT rdown_i0_q	 : NATURAL := 1620;
-  CONSTANT rdown_i1_q	 : NATURAL := 1620;
-  CONSTANT rup_cmd_q	 : NATURAL := 1790;
-  CONSTANT rup_cmd_q	 : NATURAL := 1790;
-  CONSTANT rup_i0_q	 : NATURAL := 1790;
-  CONSTANT rup_i1_q	 : NATURAL := 1790;
-  CONSTANT tphh_i0_q	 : NATURAL := 451;
-  CONSTANT tphh_i1_q	 : NATURAL := 451;
-  CONSTANT tpll_i0_q	 : NATURAL := 469;
-  CONSTANT tpll_i1_q	 : NATURAL := 469;
-  CONSTANT tphh_cmd_q	 : NATURAL := 484;
-  CONSTANT tphl_cmd_q	 : NATURAL := 485;
-  CONSTANT tpll_cmd_q	 : NATURAL := 522;
-  CONSTANT tplh_cmd_q	 : NATURAL := 534;
-  CONSTANT transistors	 : NATURAL := 12
-);
-PORT (
-  cmd	 : in  BIT;
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END mx2_x2;
-
-ARCHITECTURE behaviour_data_flow OF mx2_x2 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on mx2_x2"
-  SEVERITY WARNING;
-  q <= ((i1 and cmd) or (not (cmd) and i0)) after 1100 ps;
-END;
diff --git a/alliance/share/cells/sxlib/mx2_x2.vhd b/alliance/share/cells/sxlib/mx2_x2.vhd
deleted file mode 100644
index c115df14..00000000
--- a/alliance/share/cells/sxlib/mx2_x2.vhd
+++ /dev/null
@@ -1,21 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY mx2_x2 IS
-PORT(
-  cmd	: IN STD_LOGIC;
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END mx2_x2;
-
-ARCHITECTURE RTL OF mx2_x2 IS
-BEGIN
-  q <= ((i1 AND cmd) OR (NOT(cmd) AND i0));
-END RTL;
diff --git a/alliance/share/cells/sxlib/mx2_x4.al b/alliance/share/cells/sxlib/mx2_x4.al
deleted file mode 100644
index be51afcd..00000000
--- a/alliance/share/cells/sxlib/mx2_x4.al
+++ /dev/null
@@ -1,47 +0,0 @@
-V ALLIANCE : 6
-H mx2_x4,L,30/10/99
-C cmd,IN,EXTERNAL,6
-C i0,IN,EXTERNAL,8
-C i1,IN,EXTERNAL,7
-C q,OUT,EXTERNAL,9
-C vdd,IN,EXTERNAL,10
-C vss,IN,EXTERNAL,3
-T P,0.35,2.9,11,7,10,0,0.75,0.75,7.3,7.3,8.4,11.25,tr_00014
-T P,0.35,2.9,2,6,10,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00013
-T P,0.35,2.9,12,6,1,0,0.75,0.75,7.3,7.3,4.8,11.25,tr_00012
-T P,0.35,2.9,1,2,11,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00011
-T P,0.35,2.9,10,8,12,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00010
-T P,0.35,5.9,9,1,10,0,0.75,0.75,13.3,13.3,13.2,11.25,tr_00009
-T P,0.35,5.9,10,1,9,0,0.75,0.75,13.3,13.3,11.4,11.25,tr_00008
-T N,0.35,1.4,3,7,4,0,0.75,0.75,4.3,4.3,8.4,1.5,tr_00007
-T N,0.35,1.4,4,6,1,0,0.75,0.75,4.3,4.3,7.2,1.5,tr_00006
-T N,0.35,1.4,3,6,2,0,0.75,0.75,4.3,4.3,1.8,1.5,tr_00005
-T N,0.35,1.4,1,2,5,0,0.75,0.75,4.3,4.3,4.8,1.5,tr_00004
-T N,0.35,1.4,5,8,3,0,0.75,0.75,4.3,4.3,3.6,1.5,tr_00003
-T N,0.35,2.9,9,1,3,0,0.75,0.75,7.3,7.3,11.4,2.25,tr_00002
-T N,0.35,2.9,3,1,9,0,0.75,0.75,7.3,7.3,13.2,2.25,tr_00001
-S 12,INTERNAL
-Q 0
-S 11,INTERNAL
-Q 0
-S 10,EXTERNAL,vdd
-Q 0.00862963
-S 9,EXTERNAL,q
-Q 0.00264397
-S 8,EXTERNAL,i0
-Q 0.00336619
-S 7,EXTERNAL,i1
-Q 0.00371745
-S 6,EXTERNAL,cmd
-Q 0.00660261
-S 5,INTERNAL
-Q 0
-S 4,INTERNAL
-Q 0
-S 3,EXTERNAL,vss
-Q 0.00721951
-S 2,INTERNAL
-Q 0.00595297
-S 1,INTERNAL
-Q 0.00607876
-EOF
diff --git a/alliance/share/cells/sxlib/mx2_x4.ap b/alliance/share/cells/sxlib/mx2_x4.ap
deleted file mode 100644
index fabbde0d..00000000
--- a/alliance/share/cells/sxlib/mx2_x4.ap
+++ /dev/null
@@ -1,132 +0,0 @@
-V ALLIANCE : 6
-H mx2_x4,P,30/ 8/2000,100
-A 0,0,5000,5000
-R 1500,1500,ref_ref,cmd_15
-R 1500,2000,ref_ref,cmd_20
-R 1500,2500,ref_ref,cmd_25
-R 1500,3000,ref_ref,cmd_30
-R 1500,3500,ref_ref,cmd_35
-R 1500,4000,ref_ref,cmd_40
-R 4000,2500,ref_ref,q_25
-R 4000,3500,ref_ref,q_35
-R 4000,4000,ref_ref,q_40
-R 4000,1500,ref_ref,q_15
-R 4000,2000,ref_ref,q_20
-R 4000,3000,ref_ref,q_30
-R 4000,1000,ref_ref,q_10
-R 1000,1500,ref_ref,i0_15
-R 1000,2000,ref_ref,i0_20
-R 1000,2500,ref_ref,i0_25
-R 1000,3000,ref_ref,i0_30
-R 1000,3500,ref_ref,i0_35
-R 1000,4000,ref_ref,i0_40
-R 3000,1000,ref_ref,i1_10
-R 3000,1500,ref_ref,i1_15
-R 3000,2000,ref_ref,i1_20
-R 3000,2500,ref_ref,i1_25
-R 3000,3000,ref_ref,i1_30
-R 3000,3500,ref_ref,i1_35
-R 3000,4000,ref_ref,i1_40
-S 1500,1500,1500,4000,200,cmd,DOWN,CALU1
-S 4000,1000,4000,4000,200,q,DOWN,CALU1
-S 1000,1500,1000,4000,200,i0,DOWN,CALU1
-S 3000,1000,3000,4000,200,i1,DOWN,CALU1
-S 4000,950,4000,4050,200,*,DOWN,ALU1
-S 3000,1000,3000,4000,100,*,DOWN,ALU1
-S 2100,300,2100,1600,300,*,DOWN,NDIF
-S 1500,4700,2500,4700,300,*,RIGHT,NTIE
-S 2000,300,2000,700,500,*,DOWN,NDIF
-S 1500,1500,1500,4000,100,*,UP,ALU1
-S 1200,900,1200,1400,100,*,DOWN,POLY
-S 1000,1400,1200,1400,100,*,LEFT,POLY
-S 2000,300,2000,1600,300,*,DOWN,NDIF
-S 2800,900,2800,1400,100,*,DOWN,POLY
-S 2400,900,2400,2000,100,*,DOWN,POLY
-S 2800,100,2800,900,100,*,UP,NTRANS
-S 2400,100,2400,900,100,*,UP,NTRANS
-S 600,900,600,3100,100,*,DOWN,POLY
-S 300,300,300,1200,300,*,UP,NDIF
-S 900,300,900,700,300,*,UP,NDIF
-S 600,100,600,900,100,*,UP,NTRANS
-S 3500,500,3500,1700,200,*,DOWN,ALU1
-S 1600,100,1600,900,100,*,UP,NTRANS
-S 1200,100,1200,900,100,*,UP,NTRANS
-S 2800,1400,3100,1400,100,*,RIGHT,POLY
-S 900,3100,1200,3100,100,*,RIGHT,POLY
-S 2800,3100,3100,3100,100,*,RIGHT,POLY
-S 2400,2800,2400,3100,100,*,UP,POLY
-S 2500,1000,2500,2700,100,*,UP,ALU1
-S 3500,3000,3500,4500,200,*,UP,ALU1
-S 3300,3300,3300,4700,700,*,UP,PDIF
-S 3300,300,3300,1200,700,*,DOWN,NDIF
-S 2800,3100,2800,4400,100,*,DOWN,PTRANS
-S 3800,100,3800,1400,100,*,UP,NTRANS
-S 4100,300,4100,1200,300,*,DOWN,NDIF
-S 2000,1500,2000,4000,100,*,DOWN,ALU1
-S 2000,3300,2000,4200,500,*,DOWN,PDIF
-S 600,3100,600,4400,100,*,DOWN,PTRANS
-S 900,3300,900,4600,300,*,DOWN,PDIF
-S 1600,3100,1600,4400,100,*,DOWN,PTRANS
-S 2400,3100,2400,4400,100,*,DOWN,PTRANS
-S 1200,3100,1200,4400,100,*,DOWN,PTRANS
-S 1600,2000,1600,3100,100,*,UP,POLY
-S 300,1000,300,4000,100,*,DOWN,ALU1
-S 300,3300,300,4200,300,*,DOWN,PDIF
-S 1000,1500,1000,4000,100,*,DOWN,ALU1
-S 300,1000,2500,1000,100,*,RIGHT,ALU1
-S 600,2000,2400,2000,100,*,RIGHT,POLY
-S 4400,100,4400,1400,100,*,UP,NTRANS
-S 4700,300,4700,1200,300,*,DOWN,NDIF
-S 2000,2300,4400,2300,100,*,RIGHT,POLY
-S 0,3900,5000,3900,2400,*,RIGHT,NWELL
-S 0,300,5000,300,600,vss,RIGHT,CALU1
-S 0,4700,5000,4700,600,vdd,RIGHT,CALU1
-S 4700,3000,4700,4500,200,*,UP,ALU1
-S 4700,500,4700,1700,200,*,DOWN,ALU1
-S 4400,2600,4400,4900,100,*,DOWN,PTRANS
-S 4700,2800,4700,4700,300,*,UP,PDIF
-S 4700,2800,4700,3300,300,*,DOWN,PDIF
-S 3500,2800,3500,3300,300,*,DOWN,PDIF
-S 4100,2800,4100,4700,300,*,UP,PDIF
-S 3800,2600,3800,4900,100,*,DOWN,PTRANS
-S 3800,1400,3800,2600,100,*,DOWN,POLY
-S 4400,1400,4400,2600,100,*,DOWN,POLY
-V 2500,4700,CONT_BODY_N,*
-V 1500,4700,CONT_BODY_N,*
-V 1600,1000,CONT_POLY,*
-V 1500,2000,CONT_POLY,*
-V 3500,1700,CONT_BODY_P,*
-V 2000,2400,CONT_POLY,*
-V 2500,2700,CONT_POLY,*
-V 3500,3000,CONT_DIF_P,*
-V 3500,1000,CONT_DIF_N,*
-V 3500,4500,CONT_DIF_P,*
-V 3500,500,CONT_DIF_N,*
-V 4100,1000,CONT_DIF_N,*
-V 4100,3000,CONT_DIF_P,*
-V 4100,4000,CONT_DIF_P,*
-V 4100,3500,CONT_DIF_P,*
-V 3500,4000,CONT_DIF_P,*
-V 3500,3500,CONT_DIF_P,*
-V 2000,4000,CONT_DIF_P,*
-V 2000,4700,CONT_BODY_N,*
-V 2000,3500,CONT_DIF_P,*
-V 2000,1500,CONT_DIF_N,*
-V 3000,3000,CONT_POLY,*
-V 1000,3000,CONT_POLY,*
-V 300,3500,CONT_DIF_P,*
-V 300,4000,CONT_DIF_P,*
-V 1000,1500,CONT_POLY,*
-V 900,4500,CONT_DIF_P,*
-V 300,1000,CONT_DIF_N,*
-V 900,500,CONT_DIF_N,*
-V 300,4700,CONT_BODY_N,*
-V 3000,1500,CONT_POLY,*
-V 4700,3500,CONT_DIF_P,*
-V 4700,3000,CONT_DIF_P,*
-V 4700,4500,CONT_DIF_P,*
-V 4700,4000,CONT_DIF_P,*
-V 4700,1700,CONT_BODY_P,*
-V 4700,500,CONT_DIF_N,*
-V 4700,1000,CONT_DIF_N,*
-EOF
diff --git a/alliance/share/cells/sxlib/mx2_x4.sym b/alliance/share/cells/sxlib/mx2_x4.sym
deleted file mode 100644
index 8224e178..00000000
Binary files a/alliance/share/cells/sxlib/mx2_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/mx2_x4.vbe b/alliance/share/cells/sxlib/mx2_x4.vbe
deleted file mode 100644
index a27f7c19..00000000
--- a/alliance/share/cells/sxlib/mx2_x4.vbe
+++ /dev/null
@@ -1,42 +0,0 @@
-ENTITY mx2_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 2500;
-  CONSTANT cin_cmd	 : NATURAL := 17;
-  CONSTANT cin_i0	 : NATURAL := 8;
-  CONSTANT cin_i1	 : NATURAL := 9;
-  CONSTANT rdown_cmd_q	 : NATURAL := 810;
-  CONSTANT rdown_cmd_q	 : NATURAL := 810;
-  CONSTANT rdown_i0_q	 : NATURAL := 810;
-  CONSTANT rdown_i1_q	 : NATURAL := 810;
-  CONSTANT rup_cmd_q	 : NATURAL := 890;
-  CONSTANT rup_cmd_q	 : NATURAL := 890;
-  CONSTANT rup_i0_q	 : NATURAL := 890;
-  CONSTANT rup_i1_q	 : NATURAL := 890;
-  CONSTANT tphh_i0_q	 : NATURAL := 564;
-  CONSTANT tphh_i1_q	 : NATURAL := 564;
-  CONSTANT tphl_cmd_q	 : NATURAL := 574;
-  CONSTANT tpll_i0_q	 : NATURAL := 576;
-  CONSTANT tpll_i1_q	 : NATURAL := 576;
-  CONSTANT tphh_cmd_q	 : NATURAL := 615;
-  CONSTANT tplh_cmd_q	 : NATURAL := 631;
-  CONSTANT tpll_cmd_q	 : NATURAL := 647;
-  CONSTANT transistors	 : NATURAL := 14
-);
-PORT (
-  cmd	 : in  BIT;
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END mx2_x4;
-
-ARCHITECTURE behaviour_data_flow OF mx2_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on mx2_x4"
-  SEVERITY WARNING;
-  q <= ((i1 and cmd) or (not (cmd) and i0)) after 1200 ps;
-END;
diff --git a/alliance/share/cells/sxlib/mx2_x4.vhd b/alliance/share/cells/sxlib/mx2_x4.vhd
deleted file mode 100644
index 2da047b5..00000000
--- a/alliance/share/cells/sxlib/mx2_x4.vhd
+++ /dev/null
@@ -1,21 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY mx2_x4 IS
-PORT(
-  cmd	: IN STD_LOGIC;
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END mx2_x4;
-
-ARCHITECTURE RTL OF mx2_x4 IS
-BEGIN
-  q <= ((i1 AND cmd) OR (NOT(cmd) AND i0));
-END RTL;
diff --git a/alliance/share/cells/sxlib/mx3_x2.al b/alliance/share/cells/sxlib/mx3_x2.al
deleted file mode 100644
index 6b49a823..00000000
--- a/alliance/share/cells/sxlib/mx3_x2.al
+++ /dev/null
@@ -1,69 +0,0 @@
-V ALLIANCE : 6
-H mx3_x2,L,30/10/99
-C cmd0,IN,EXTERNAL,15
-C cmd1,IN,EXTERNAL,9
-C i0,IN,EXTERNAL,14
-C i1,IN,EXTERNAL,8
-C i2,IN,EXTERNAL,10
-C q,OUT,EXTERNAL,12
-C vdd,IN,EXTERNAL,7
-C vss,IN,EXTERNAL,3
-T P,0.35,2.9,16,6,1,0,0.75,0.75,7.3,7.3,7.8,12.75,tr_00020
-T P,0.35,2.9,7,13,18,0,0.75,0.75,7.3,7.3,10.8,12.75,tr_00019
-T P,0.35,2.9,19,15,7,0,0.75,0.75,7.3,7.3,12.6,12.75,tr_00018
-T P,0.35,2.9,1,14,19,0,0.75,0.75,7.3,7.3,13.8,12.75,tr_00017
-T P,0.35,2.9,18,8,16,0,0.75,0.75,7.3,7.3,9,12.75,tr_00016
-T P,0.35,2.9,17,10,18,0,0.75,0.75,7.3,7.3,4.2,12.75,tr_00015
-T P,0.35,2.9,1,9,17,0,0.75,0.75,7.3,7.3,6,12.75,tr_00014
-T P,0.35,5.9,12,1,7,0,0.75,0.75,13.3,13.3,17.4,11.25,tr_00013
-T P,0.35,2,6,9,7,0,0.75,0.75,5.5,5.5,2.4,9.3,tr_00012
-T P,0.35,2,7,15,13,0,0.75,0.75,5.5,5.5,15.6,9.3,tr_00011
-T N,0.35,1.7,4,8,2,0,0.75,0.75,4.9,4.9,9,2.55,tr_00010
-T N,0.35,1.7,2,9,1,0,0.75,0.75,4.9,4.9,7.8,2.55,tr_00009
-T N,0.35,1.7,1,6,5,0,0.75,0.75,4.9,4.9,6,2.55,tr_00008
-T N,0.35,1.7,5,10,4,0,0.75,0.75,4.9,4.9,4.2,2.55,tr_00007
-T N,0.35,1.7,3,15,4,0,0.75,0.75,4.9,4.9,10.8,1.95,tr_00006
-T N,0.35,1.7,11,13,3,0,0.75,0.75,4.9,4.9,12.6,1.95,tr_00005
-T N,0.35,1.7,1,14,11,0,0.75,0.75,4.9,4.9,13.8,1.95,tr_00004
-T N,0.35,1.1,3,9,6,0,0.75,0.75,3.7,3.7,2.4,5.25,tr_00003
-T N,0.35,1.1,13,15,3,0,0.75,0.75,3.7,3.7,15.6,4.95,tr_00002
-T N,0.35,2.9,3,1,12,0,0.75,0.75,7.3,7.3,17.4,3.75,tr_00001
-S 19,INTERNAL
-Q 0
-S 18,INTERNAL
-Q 0.00170541
-S 17,INTERNAL
-Q 0
-S 16,INTERNAL
-Q 0
-S 15,EXTERNAL,cmd0
-Q 0.00553121
-S 14,EXTERNAL,i0
-Q 0.00386191
-S 13,INTERNAL
-Q 0.0057783
-S 12,EXTERNAL,q
-Q 0.00361343
-S 11,INTERNAL
-Q 0
-S 10,EXTERNAL,i2
-Q 0.0021309
-S 9,EXTERNAL,cmd1
-Q 0.00604152
-S 8,EXTERNAL,i1
-Q 0.0025589
-S 7,EXTERNAL,vdd
-Q 0.00654004
-S 6,INTERNAL
-Q 0.00547335
-S 5,INTERNAL
-Q 0
-S 4,INTERNAL
-Q 0.00170541
-S 3,EXTERNAL,vss
-Q 0.00671631
-S 2,INTERNAL
-Q 0
-S 1,INTERNAL
-Q 0.00814817
-EOF
diff --git a/alliance/share/cells/sxlib/mx3_x2.ap b/alliance/share/cells/sxlib/mx3_x2.ap
deleted file mode 100644
index 79da05fd..00000000
--- a/alliance/share/cells/sxlib/mx3_x2.ap
+++ /dev/null
@@ -1,182 +0,0 @@
-V ALLIANCE : 6
-H mx3_x2,P, 6/ 9/2000,100
-A 0,0,6500,5000
-R 6000,4000,ref_ref,q_40
-R 6000,3500,ref_ref,q_35
-R 6000,3000,ref_ref,q_30
-R 6000,2500,ref_ref,q_25
-R 6000,1500,ref_ref,q_15
-R 6000,1000,ref_ref,q_10
-R 4500,2500,ref_ref,i0_25
-R 4000,3000,ref_ref,i0_30
-R 4000,2000,ref_ref,i0_20
-R 3500,3000,ref_ref,cmd0_30
-R 3500,2500,ref_ref,cmd0_25
-R 3500,2000,ref_ref,cmd0_20
-R 2500,2500,ref_ref,i1_25
-R 1500,2500,ref_ref,i2_25
-R 500,3500,ref_ref,cmd1_35
-R 500,3000,ref_ref,cmd1_30
-R 500,2500,ref_ref,cmd1_25
-R 500,2000,ref_ref,cmd1_20
-R 500,1500,ref_ref,cmd1_15
-S 1800,1500,2000,1500,300,*,RIGHT,POLY
-S 4400,3000,4600,3000,300,*,LEFT,POLY
-S 4400,2000,4600,2000,300,*,RIGHT,POLY
-S 1800,3500,2000,3500,300,*,RIGHT,POLY
-S 4000,2000,4000,2000,200,i0,LEFT,CALU1
-S 4500,2500,4500,2500,200,i0,LEFT,CALU1
-S 4000,3000,4000,3000,200,i0,LEFT,CALU1
-S 6000,1000,6000,1500,200,q,DOWN,CALU1
-S 6000,2500,6000,4000,200,q,DOWN,CALU1
-S 6000,950,6000,1550,200,*,DOWN,ALU1
-S 6000,2450,6000,4000,200,*,DOWN,ALU1
-S 3500,2000,3500,3000,200,cmd0,DOWN,CALU1
-S 2500,2500,2500,2500,200,i1,LEFT,CALU1
-S 1500,2500,1500,2500,200,i2,LEFT,CALU1
-S 500,1500,500,3500,200,cmd1,DOWN,CALU1
-S 4900,400,4900,1000,300,*,UP,NDIF
-S 5500,2000,5700,2000,200,*,LEFT,ALU1
-S 6050,1500,6250,1500,200,*,LEFT,ALU1
-S 6200,1450,6200,2550,200,*,DOWN,ALU1
-S 6050,2500,6250,2500,200,*,RIGHT,ALU1
-S 5500,500,5500,1700,300,*,DOWN,NDIF
-S 6100,800,6100,1700,300,*,UP,NDIF
-S 5800,600,5800,1900,100,*,DOWN,NTRANS
-S 4900,1500,4900,1700,300,*,DOWN,NDIF
-S 4900,1000,5500,1000,100,*,RIGHT,ALU1
-S 2300,3500,5500,3500,100,*,RIGHT,ALU1
-S 5500,1000,5500,3500,100,*,DOWN,ALU1
-S 1100,1600,1100,1900,300,*,UP,NDIF
-S 800,1400,800,2100,100,*,DOWN,NTRANS
-S 3500,3600,3600,3600,100,*,RIGHT,POLY
-S 3500,1500,3500,3600,100,*,UP,POLY
-S 4900,3500,4900,4000,100,*,DOWN,ALU1
-S 1100,600,1100,1000,300,*,DOWN,NDIF
-S 1700,600,1700,1100,200,*,DOWN,NDIF
-S 2300,600,2300,1600,300,*,UP,NDIF
-S 3300,400,3300,1100,300,*,DOWN,NDIF
-S 4600,200,4600,1100,100,*,UP,NTRANS
-S 4200,200,4200,1100,100,*,UP,NTRANS
-S 3600,200,3600,1100,100,*,UP,NTRANS
-S 1400,400,1400,1300,100,*,UP,NTRANS
-S 2000,400,2000,1300,100,*,UP,NTRANS
-S 2600,400,2600,1300,100,*,UP,NTRANS
-S 3000,400,3000,1300,100,*,UP,NTRANS
-S 1100,2800,1100,3400,300,*,UP,PDIF
-S 5200,2600,5200,3600,100,*,UP,PTRANS
-S 800,2600,800,3600,100,*,UP,PTRANS
-S 4600,1100,4600,2000,100,*,DOWN,POLY
-S 3900,400,3900,900,200,*,DOWN,NDIF
-S 4200,1100,4200,1500,100,*,UP,POLY
-S 3000,1300,3000,3600,100,*,DOWN,POLY
-S 2600,1300,2600,2000,100,*,UP,POLY
-S 2000,1300,2000,1500,100,*,DOWN,POLY
-S 1400,1300,1400,3600,100,*,DOWN,POLY
-S 4900,2800,4900,3400,300,*,UP,PDIF
-S 3500,2500,3900,2500,200,*,RIGHT,ALU1
-S 6100,2800,6100,4700,300,*,UP,PDIF
-S 5800,2000,5800,2600,100,*,DOWN,POLY
-S 0,4700,6500,4700,600,vdd,RIGHT,CALU1
-S 0,300,6500,300,600,vss,RIGHT,CALU1
-S 0,3900,6500,3900,2400,*,RIGHT,NWELL
-S 4900,3000,5000,3000,100,*,RIGHT,ALU1
-S 4400,2000,4400,3000,100,*,UP,ALU1
-S 5500,2800,5500,4600,300,*,DOWN,PDIF
-S 5800,2600,5800,4900,100,*,UP,PTRANS
-S 4000,3300,4000,3600,100,*,UP,POLY
-S 4000,3600,4200,3600,100,*,LEFT,POLY
-S 4000,2500,5200,2500,100,*,RIGHT,POLY
-S 3800,1100,3800,1900,100,*,DOWN,POLY
-S 3800,1900,4000,1900,100,*,LEFT,POLY
-S 4000,1900,4000,3300,100,*,DOWN,POLY
-S 4500,2000,4600,2000,100,*,RIGHT,POLY
-S 4600,3000,4600,3600,100,*,UP,POLY
-S 4400,3000,4600,3000,100,*,RIGHT,POLY
-S 3000,2000,3000,3500,100,*,UP,ALU1
-S 2800,2000,3000,2000,100,*,RIGHT,ALU1
-S 1800,3000,2500,3000,100,*,LEFT,ALU1
-S 2500,2500,3000,2500,100,*,RIGHT,POLY
-S 2000,2000,2600,2000,100,*,RIGHT,POLY
-S 2000,2000,2000,3600,100,*,DOWN,POLY
-S 500,2800,500,4000,300,*,UP,PDIF
-S 2000,3600,2000,4900,100,*,UP,PTRANS
-S 2300,3500,2300,4700,300,*,UP,PDIF
-S 1700,3800,1700,4700,200,*,DOWN,PDIF
-S 1400,3600,1400,4900,100,*,UP,PTRANS
-S 1100,3800,1100,4700,300,*,UP,PDIF
-S 3000,3600,3000,4900,100,*,UP,PTRANS
-S 3300,3800,3300,4700,200,*,UP,PDIF
-S 4600,3600,4600,4900,100,*,UP,PTRANS
-S 4900,3800,4900,4700,300,*,UP,PDIF
-S 4200,3600,4200,4900,100,*,UP,PTRANS
-S 3600,3600,3600,4900,100,*,UP,PTRANS
-S 3900,3800,3900,4700,200,*,UP,PDIF
-S 2600,3600,2600,4900,100,*,UP,PTRANS
-S 500,1000,500,1900,300,*,DOWN,NDIF
-S 500,2500,800,2500,300,*,RIGHT,POLY
-S 800,2100,800,2600,100,*,DOWN,POLY
-S 1800,1500,2000,1500,100,*,RIGHT,POLY
-S 3600,1100,3800,1100,100,*,RIGHT,POLY
-S 3300,1500,3400,1500,100,*,LEFT,POLY
-S 2600,3000,2600,3600,100,*,UP,POLY
-S 500,400,500,1000,200,*,DOWN,ALU1
-S 1100,1000,3300,1000,100,*,RIGHT,ALU1
-S 500,3500,1800,3500,100,*,LEFT,ALU1
-S 500,4000,500,4600,200,*,UP,ALU1
-S 2000,2000,2000,3000,100,*,UP,ALU1
-S 1000,1800,1000,3000,100,*,UP,ALU1
-S 500,1500,500,3500,100,*,DOWN,ALU1
-S 1800,1500,1800,2000,100,*,UP,ALU1
-S 1800,2000,1900,2000,100,*,RIGHT,ALU1
-S 1000,3000,1800,3000,100,*,LEFT,ALU1
-S 1100,4000,3300,4000,100,*,RIGHT,ALU1
-S 2300,1500,2800,1500,100,*,RIGHT,ALU1
-S 2800,1500,2800,2000,100,*,UP,ALU1
-S 4000,3000,4400,3000,200,*,RIGHT,ALU1
-S 4000,2000,4400,2000,200,*,RIGHT,ALU1
-S 3500,2000,3500,3000,100,*,DOWN,ALU1
-S 5200,1900,5200,2600,100,*,DOWN,POLY
-S 5200,1300,5200,1900,100,*,DOWN,NTRANS
-S 3400,1500,5000,1500,100,*,RIGHT,ALU1
-S 5000,1500,5000,3000,100,*,DOWN,ALU1
-V 6100,300,CONT_BODY_P,*
-V 5700,2000,CONT_POLY,*
-V 3900,2500,CONT_POLY,*
-V 6100,1000,CONT_DIF_N,*
-V 6100,1500,CONT_DIF_N,*
-V 6100,3000,CONT_DIF_P,*
-V 6100,4000,CONT_DIF_P,*
-V 6100,3500,CONT_DIF_P,*
-V 5500,500,CONT_DIF_N,*
-V 5500,4600,CONT_DIF_P,*
-V 4400,2000,CONT_POLY,*
-V 4400,3000,CONT_POLY,*
-V 2500,3000,CONT_POLY,*
-V 4900,3000,CONT_DIF_P,*
-V 1100,3000,CONT_DIF_P,*
-V 500,4600,CONT_BODY_N,*
-V 500,4000,CONT_DIF_P,*
-V 4900,4000,CONT_DIF_P,*
-V 1100,4000,CONT_DIF_P,*
-V 2300,3500,CONT_DIF_P,*
-V 3900,4500,CONT_DIF_P,*
-V 3300,4000,CONT_DIF_P,*
-V 3900,500,CONT_DIF_N,*
-V 500,1000,CONT_DIF_N,*
-V 1100,1000,CONT_DIF_N,*
-V 4900,1000,CONT_DIF_N,*
-V 3300,1000,CONT_DIF_N,*
-V 1100,1800,CONT_DIF_N,*
-V 1100,1800,CONT_DIF_N,*
-V 2300,1500,CONT_DIF_N,*
-V 500,400,CONT_BODY_P,*
-V 1500,2500,CONT_POLY,*
-V 2500,2500,CONT_POLY,*
-V 500,2500,CONT_POLY,*
-V 1800,1500,CONT_POLY,*
-V 3400,1500,CONT_POLY,*
-V 4200,1500,CONT_POLY,*
-V 1800,3500,CONT_POLY,*
-V 4900,1600,CONT_DIF_N,*
-EOF
diff --git a/alliance/share/cells/sxlib/mx3_x2.vbe b/alliance/share/cells/sxlib/mx3_x2.vbe
deleted file mode 100644
index 5d534511..00000000
--- a/alliance/share/cells/sxlib/mx3_x2.vbe
+++ /dev/null
@@ -1,59 +0,0 @@
-ENTITY mx3_x2 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 3250;
-  CONSTANT cin_cmd0	 : NATURAL := 15;
-  CONSTANT cin_cmd1	 : NATURAL := 15;
-  CONSTANT cin_i0	 : NATURAL := 9;
-  CONSTANT cin_i1	 : NATURAL := 8;
-  CONSTANT cin_i2	 : NATURAL := 8;
-  CONSTANT rdown_cmd0_q	 : NATURAL := 1620;
-  CONSTANT rdown_cmd0_q	 : NATURAL := 1620;
-  CONSTANT rdown_cmd1_q	 : NATURAL := 1620;
-  CONSTANT rdown_cmd1_q	 : NATURAL := 1620;
-  CONSTANT rdown_i0_q	 : NATURAL := 1620;
-  CONSTANT rdown_i1_q	 : NATURAL := 1620;
-  CONSTANT rdown_i2_q	 : NATURAL := 1620;
-  CONSTANT rup_cmd0_q	 : NATURAL := 1790;
-  CONSTANT rup_cmd0_q	 : NATURAL := 1790;
-  CONSTANT rup_cmd1_q	 : NATURAL := 1790;
-  CONSTANT rup_cmd1_q	 : NATURAL := 1790;
-  CONSTANT rup_i0_q	 : NATURAL := 1790;
-  CONSTANT rup_i1_q	 : NATURAL := 1790;
-  CONSTANT rup_i2_q	 : NATURAL := 1790;
-  CONSTANT tphh_i0_q	 : NATURAL := 538;
-  CONSTANT tphh_cmd0_q	 : NATURAL := 573;
-  CONSTANT tphh_i1_q	 : NATURAL := 654;
-  CONSTANT tphh_i2_q	 : NATURAL := 654;
-  CONSTANT tpll_i0_q	 : NATURAL := 658;
-  CONSTANT tphh_cmd1_q	 : NATURAL := 664;
-  CONSTANT tpll_cmd0_q	 : NATURAL := 680;
-  CONSTANT tplh_cmd1_q	 : NATURAL := 738;
-  CONSTANT tphl_cmd1_q	 : NATURAL := 739;
-  CONSTANT tplh_cmd0_q	 : NATURAL := 768;
-  CONSTANT tphl_cmd0_q	 : NATURAL := 792;
-  CONSTANT tpll_i1_q	 : NATURAL := 808;
-  CONSTANT tpll_i2_q	 : NATURAL := 808;
-  CONSTANT tpll_cmd1_q	 : NATURAL := 817;
-  CONSTANT transistors	 : NATURAL := 20
-);
-PORT (
-  cmd0	 : in  BIT;
-  cmd1	 : in  BIT;
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END mx3_x2;
-
-ARCHITECTURE behaviour_data_flow OF mx3_x2 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on mx3_x2"
-  SEVERITY WARNING;
-  q <= ((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not (cmd1)
-  and i2)))) after 1400 ps;
-END;
diff --git a/alliance/share/cells/sxlib/mx3_x2.vhd b/alliance/share/cells/sxlib/mx3_x2.vhd
deleted file mode 100644
index 9fc27c51..00000000
--- a/alliance/share/cells/sxlib/mx3_x2.vhd
+++ /dev/null
@@ -1,23 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY mx3_x2 IS
-PORT(
-  cmd0	: IN STD_LOGIC;
-  cmd1	: IN STD_LOGIC;
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END mx3_x2;
-
-ARCHITECTURE RTL OF mx3_x2 IS
-BEGIN
-  q <= ((NOT(cmd0) AND i0) OR (cmd0 AND ((cmd1 AND i1) OR (NOT(cmd1) AND i2))));
-END RTL;
diff --git a/alliance/share/cells/sxlib/mx3_x4.al b/alliance/share/cells/sxlib/mx3_x4.al
deleted file mode 100644
index a852eb31..00000000
--- a/alliance/share/cells/sxlib/mx3_x4.al
+++ /dev/null
@@ -1,71 +0,0 @@
-V ALLIANCE : 6
-H mx3_x4,L,30/10/99
-C cmd0,IN,EXTERNAL,14
-C cmd1,IN,EXTERNAL,9
-C i0,IN,EXTERNAL,15
-C i1,IN,EXTERNAL,8
-C i2,IN,EXTERNAL,10
-C q,OUT,EXTERNAL,11
-C vdd,IN,EXTERNAL,7
-C vss,IN,EXTERNAL,3
-T P,0.35,5.9,7,2,11,0,0.75,0.75,13.3,13.3,18.9,11.25,tr_00022
-T P,0.35,2.9,18,6,2,0,0.75,0.75,7.3,7.3,7.5,12.75,tr_00021
-T P,0.35,2.9,7,13,17,0,0.75,0.75,7.3,7.3,10.5,12.75,tr_00020
-T P,0.35,2.9,19,14,7,0,0.75,0.75,7.3,7.3,12.3,12.75,tr_00019
-T P,0.35,2.9,2,15,19,0,0.75,0.75,7.3,7.3,13.5,12.75,tr_00018
-T P,0.35,2.9,17,8,18,0,0.75,0.75,7.3,7.3,8.7,12.75,tr_00017
-T P,0.35,2.9,16,10,17,0,0.75,0.75,7.3,7.3,3.9,12.75,tr_00016
-T P,0.35,2.9,2,9,16,0,0.75,0.75,7.3,7.3,5.7,12.75,tr_00015
-T P,0.35,5.9,11,2,7,0,0.75,0.75,13.3,13.3,17.1,11.25,tr_00014
-T P,0.35,2,6,9,7,0,0.75,0.75,5.5,5.5,2.1,9.3,tr_00013
-T P,0.35,2,7,14,13,0,0.75,0.75,5.5,5.5,15.3,9.3,tr_00012
-T N,0.35,2.9,11,2,3,0,0.75,0.75,7.3,7.3,18.9,3.75,tr_00011
-T N,0.35,1.7,1,9,2,0,0.75,0.75,4.9,4.9,7.5,2.55,tr_00010
-T N,0.35,1.7,2,6,5,0,0.75,0.75,4.9,4.9,5.7,2.55,tr_00009
-T N,0.35,1.7,12,13,3,0,0.75,0.75,4.9,4.9,12.3,1.95,tr_00008
-T N,0.35,1.7,2,15,12,0,0.75,0.75,4.9,4.9,13.5,1.95,tr_00007
-T N,0.35,1.7,4,8,1,0,0.75,0.75,4.9,4.9,8.7,2.55,tr_00006
-T N,0.35,2.9,3,2,11,0,0.75,0.75,7.3,7.3,17.1,3.75,tr_00005
-T N,0.35,1.7,5,10,4,0,0.75,0.75,4.9,4.9,3.9,2.55,tr_00004
-T N,0.35,1.7,3,14,4,0,0.75,0.75,4.9,4.9,10.5,1.95,tr_00003
-T N,0.35,1.1,13,14,3,0,0.75,0.75,3.7,3.7,15.3,4.95,tr_00002
-T N,0.35,1.1,3,9,6,0,0.75,0.75,3.7,3.7,2.1,5.25,tr_00001
-S 19,INTERNAL
-Q 0
-S 18,INTERNAL
-Q 0
-S 17,INTERNAL
-Q 0.00170541
-S 16,INTERNAL
-Q 0
-S 15,EXTERNAL,i0
-Q 0.00397942
-S 14,EXTERNAL,cmd0
-Q 0.00547246
-S 13,INTERNAL
-Q 0.00589104
-S 12,INTERNAL
-Q 0
-S 11,EXTERNAL,q
-Q 0.00396596
-S 10,EXTERNAL,i2
-Q 0.0021309
-S 9,EXTERNAL,cmd1
-Q 0.00604152
-S 8,EXTERNAL,i1
-Q 0.0025589
-S 7,EXTERNAL,vdd
-Q 0.00864417
-S 6,INTERNAL
-Q 0.00586794
-S 5,INTERNAL
-Q 0
-S 4,INTERNAL
-Q 0.00170541
-S 3,EXTERNAL,vss
-Q 0.00823288
-S 2,INTERNAL
-Q 0.00946154
-S 1,INTERNAL
-Q 0
-EOF
diff --git a/alliance/share/cells/sxlib/mx3_x4.ap b/alliance/share/cells/sxlib/mx3_x4.ap
deleted file mode 100644
index 728f68b5..00000000
--- a/alliance/share/cells/sxlib/mx3_x4.ap
+++ /dev/null
@@ -1,203 +0,0 @@
-V ALLIANCE : 6
-H mx3_x4,P, 6/ 9/2000,100
-A 0,0,7000,5000
-R 6500,2000,ref_ref,q_20
-R 500,1500,ref_ref,cmd1_15
-R 500,2000,ref_ref,cmd1_20
-R 500,2500,ref_ref,cmd1_25
-R 500,3000,ref_ref,cmd1_30
-R 500,3500,ref_ref,cmd1_35
-R 1500,2500,ref_ref,i2_25
-R 2500,2500,ref_ref,i1_25
-R 3500,2000,ref_ref,cmd0_20
-R 3500,2500,ref_ref,cmd0_25
-R 3500,3000,ref_ref,cmd0_30
-R 4000,2000,ref_ref,i0_20
-R 4000,3000,ref_ref,i0_30
-R 4500,2500,ref_ref,i0_25
-R 6000,1000,ref_ref,q_10
-R 6000,1500,ref_ref,q_15
-R 6000,2500,ref_ref,q_25
-R 6000,3000,ref_ref,q_30
-R 6000,3500,ref_ref,q_35
-R 6000,4000,ref_ref,q_40
-S 4300,3000,4500,3000,300,*,RIGHT,POLY
-S 4300,2000,4500,2000,300,*,RIGHT,POLY
-S 1700,1500,1900,1500,300,*,RIGHT,POLY
-S 1700,3500,1900,3500,300,*,RIGHT,POLY
-S 1300,2500,1500,2500,300,*,LEFT,POLY
-S 500,3500,1700,3500,100,*,LEFT,ALU1
-S 500,1500,500,3500,100,*,DOWN,ALU1
-S 6500,2000,6500,2000,200,q,LEFT,CALU1
-S 6000,1000,6000,1500,200,q,DOWN,CALU1
-S 6000,2500,6000,4000,200,q,DOWN,CALU1
-S 4000,2000,4000,2000,200,i0,LEFT,CALU1
-S 4000,3000,4000,3000,200,i0,LEFT,CALU1
-S 4500,2500,4500,2500,200,i0,LEFT,CALU1
-S 500,1500,500,3500,200,cmd1,DOWN,CALU1
-S 1500,2500,1500,2500,200,i2,LEFT,CALU1
-S 2500,2500,2500,2500,200,i1,LEFT,CALU1
-S 3500,2000,3500,3000,200,cmd0,DOWN,CALU1
-S 4800,400,4800,1000,300,*,UP,NDIF
-S 0,4700,7000,4700,600,vdd,RIGHT,CALU1
-S 0,3900,7000,3900,2400,*,RIGHT,NWELL
-S 0,300,7000,300,600,vss,RIGHT,CALU1
-S 5950,1500,6150,1500,200,*,LEFT,ALU1
-S 6100,1450,6100,2550,200,*,DOWN,ALU1
-S 5950,2500,6150,2500,200,*,RIGHT,ALU1
-S 6000,2450,6000,4000,200,*,DOWN,ALU1
-S 400,4000,400,4600,200,*,UP,ALU1
-S 4800,3500,4800,4000,100,*,DOWN,ALU1
-S 4300,2000,4300,3000,100,*,UP,ALU1
-S 1000,4000,3200,4000,100,*,RIGHT,ALU1
-S 2200,1500,2700,1500,100,*,RIGHT,ALU1
-S 1700,3000,2400,3000,100,*,LEFT,ALU1
-S 6600,3000,6600,4600,200,*,UP,ALU1
-S 1700,1500,1700,2000,100,*,UP,ALU1
-S 2700,1500,2700,2000,100,*,UP,ALU1
-S 6000,950,6000,1550,200,*,DOWN,ALU1
-S 400,400,400,1000,200,*,DOWN,ALU1
-S 1000,1000,3200,1000,100,*,RIGHT,ALU1
-S 6600,300,6600,1500,200,*,DOWN,ALU1
-S 1900,1300,1900,1500,100,*,DOWN,POLY
-S 1300,1300,1300,3600,100,*,DOWN,POLY
-S 3900,3300,3900,3600,100,*,UP,POLY
-S 3900,3600,4100,3600,100,*,LEFT,POLY
-S 4500,1100,4500,2000,100,*,DOWN,POLY
-S 3400,3600,3500,3600,100,*,RIGHT,POLY
-S 3400,1500,3400,3600,100,*,UP,POLY
-S 3900,1900,3900,3300,100,*,DOWN,POLY
-S 4400,2000,4500,2000,100,*,RIGHT,POLY
-S 4500,3000,4500,3600,100,*,UP,POLY
-S 4300,3000,4500,3000,100,*,RIGHT,POLY
-S 2400,2500,2900,2500,100,*,RIGHT,POLY
-S 4100,1100,4100,1500,100,*,UP,POLY
-S 2900,1300,2900,3600,100,*,DOWN,POLY
-S 2500,1300,2500,2000,100,*,UP,POLY
-S 3500,1100,3700,1100,100,*,RIGHT,POLY
-S 3200,1500,3300,1500,100,*,LEFT,POLY
-S 2500,3000,2500,3600,100,*,UP,POLY
-S 1900,2000,2500,2000,100,*,RIGHT,POLY
-S 1900,2000,1900,3600,100,*,DOWN,POLY
-S 3900,2500,5100,2500,100,*,RIGHT,POLY
-S 3700,1100,3700,1900,100,*,DOWN,POLY
-S 3700,1900,3900,1900,100,*,LEFT,POLY
-S 5600,2000,6300,2000,100,*,RIGHT,POLY
-S 400,2500,700,2500,300,*,RIGHT,POLY
-S 700,2100,700,2600,100,*,DOWN,POLY
-S 1700,1500,1900,1500,100,*,RIGHT,POLY
-S 6300,1900,6300,2600,100,*,DOWN,POLY
-S 5700,1900,5700,2600,100,*,DOWN,POLY
-S 1000,1600,1000,1900,300,*,UP,NDIF
-S 700,1400,700,2100,100,*,DOWN,NTRANS
-S 1000,600,1000,1000,300,*,DOWN,NDIF
-S 1600,600,1600,1100,200,*,DOWN,NDIF
-S 2200,600,2200,1600,300,*,UP,NDIF
-S 3200,400,3200,1100,300,*,DOWN,NDIF
-S 3500,200,3500,1100,100,*,UP,NTRANS
-S 1300,400,1300,1300,100,*,UP,NTRANS
-S 5400,500,5400,1700,300,*,DOWN,NDIF
-S 6000,800,6000,1700,300,*,UP,NDIF
-S 5700,600,5700,1900,100,*,DOWN,NTRANS
-S 2900,400,2900,1300,100,*,UP,NTRANS
-S 3800,400,3800,900,200,*,DOWN,NDIF
-S 4500,200,4500,1100,100,*,UP,NTRANS
-S 4100,200,4100,1100,100,*,UP,NTRANS
-S 1900,400,1900,1300,100,*,UP,NTRANS
-S 2500,400,2500,1300,100,*,UP,NTRANS
-S 6300,600,6300,1900,100,*,DOWN,NTRANS
-S 6600,800,6600,1700,300,*,DOWN,NDIF
-S 400,1000,400,1900,300,*,DOWN,NDIF
-S 1000,2800,1000,3400,300,*,UP,PDIF
-S 5100,2600,5100,3600,100,*,UP,PTRANS
-S 700,2600,700,3600,100,*,UP,PTRANS
-S 4800,2800,4800,3400,300,*,UP,PDIF
-S 6000,2800,6000,4700,300,*,UP,PDIF
-S 5400,2800,5400,4600,300,*,DOWN,PDIF
-S 5700,2600,5700,4900,100,*,UP,PTRANS
-S 1900,3600,1900,4900,100,*,UP,PTRANS
-S 2200,3500,2200,4700,300,*,UP,PDIF
-S 1600,3800,1600,4700,200,*,DOWN,PDIF
-S 1300,3600,1300,4900,100,*,UP,PTRANS
-S 1000,3800,1000,4700,300,*,UP,PDIF
-S 2900,3600,2900,4900,100,*,UP,PTRANS
-S 3200,3800,3200,4700,200,*,UP,PDIF
-S 4500,3600,4500,4900,100,*,UP,PTRANS
-S 4800,3800,4800,4700,300,*,UP,PDIF
-S 4100,3600,4100,4900,100,*,UP,PTRANS
-S 3500,3600,3500,4900,100,*,UP,PTRANS
-S 3800,3800,3800,4700,200,*,UP,PDIF
-S 2500,3600,2500,4900,100,*,UP,PTRANS
-S 6300,2600,6300,4900,100,*,UP,PTRANS
-S 6600,2800,6600,4700,300,*,UP,PDIF
-S 400,2800,400,4000,300,*,UP,PDIF
-S 1000,1800,1000,3000,100,*,UP,ALU1
-S 1000,3000,1700,3000,100,*,LEFT,ALU1
-S 3500,2000,3500,3000,100,*,DOWN,ALU1
-S 4000,3000,4300,3000,200,*,RIGHT,ALU1
-S 4000,2000,4300,2000,200,*,RIGHT,ALU1
-S 4300,2500,4500,2500,200,*,LEFT,ALU1
-S 5500,1000,5500,3500,100,*,DOWN,ALU1
-S 5500,2000,5600,2000,200,*,LEFT,ALU1
-S 4800,1000,5500,1000,100,*,RIGHT,ALU1
-S 2200,3500,5500,3500,100,*,RIGHT,ALU1
-S 6100,2000,6500,2000,200,*,RIGHT,ALU1
-S 4800,2950,5000,2950,100,*,RIGHT,ALU1
-S 3500,2500,3800,2500,200,*,RIGHT,ALU1
-S 3000,2000,3000,3500,100,*,UP,ALU1
-S 2700,2000,3000,2000,100,*,RIGHT,ALU1
-S 2000,2000,2000,3000,100,*,UP,ALU1
-S 1700,2000,2000,2000,100,*,RIGHT,ALU1
-S 2000,2950,2400,2950,100,*,RIGHT,ALU1
-S 5100,1300,5100,1900,100,*,DOWN,NTRANS
-S 5100,1900,5100,2600,100,*,DOWN,POLY
-S 5000,1700,5000,2950,100,*,DOWN,ALU1
-S 3300,1500,4800,1500,100,*,RIGHT,ALU1
-S 4800,1700,5000,1700,100,*,LEFT,ALU1
-S 4800,1500,4800,1700,100,*,DOWN,ALU1
-V 5600,2000,CONT_POLY,*
-V 3800,2500,CONT_POLY,*
-V 4300,2000,CONT_POLY,*
-V 4300,3000,CONT_POLY,*
-V 1700,1500,CONT_POLY,*
-V 3300,1500,CONT_POLY,*
-V 4100,1500,CONT_POLY,*
-V 1700,3500,CONT_POLY,*
-V 2400,3000,CONT_POLY,*
-V 400,2500,CONT_POLY,*
-V 6000,300,CONT_BODY_P,*
-V 400,400,CONT_BODY_P,*
-V 6600,1500,CONT_DIF_N,*
-V 6000,1500,CONT_DIF_N,*
-V 1000,1800,CONT_DIF_N,*
-V 1000,1800,CONT_DIF_N,*
-V 2200,1500,CONT_DIF_N,*
-V 6000,1000,CONT_DIF_N,*
-V 5400,500,CONT_DIF_N,*
-V 3800,500,CONT_DIF_N,*
-V 1000,1000,CONT_DIF_N,*
-V 4800,1000,CONT_DIF_N,*
-V 3200,1000,CONT_DIF_N,*
-V 6600,1000,CONT_DIF_N,*
-V 400,1000,CONT_DIF_N,*
-V 1000,3000,CONT_DIF_P,*
-V 6600,3000,CONT_DIF_P,*
-V 6600,3500,CONT_DIF_P,*
-V 6600,4000,CONT_DIF_P,*
-V 6000,3000,CONT_DIF_P,*
-V 6000,4000,CONT_DIF_P,*
-V 6000,3500,CONT_DIF_P,*
-V 5400,4600,CONT_DIF_P,*
-V 4800,3000,CONT_DIF_P,*
-V 6600,4600,CONT_DIF_P,*
-V 4800,4000,CONT_DIF_P,*
-V 1000,4000,CONT_DIF_P,*
-V 2200,3500,CONT_DIF_P,*
-V 3800,4500,CONT_DIF_P,*
-V 3200,4000,CONT_DIF_P,*
-V 400,4600,CONT_BODY_N,*
-V 400,4000,CONT_DIF_P,*
-V 1500,2500,CONT_POLY,*
-V 2500,2500,CONT_POLY,*
-V 4800,1600,CONT_DIF_N,*
-EOF
diff --git a/alliance/share/cells/sxlib/mx3_x4.vbe b/alliance/share/cells/sxlib/mx3_x4.vbe
deleted file mode 100644
index d69143bd..00000000
--- a/alliance/share/cells/sxlib/mx3_x4.vbe
+++ /dev/null
@@ -1,59 +0,0 @@
-ENTITY mx3_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 3500;
-  CONSTANT cin_cmd0	 : NATURAL := 15;
-  CONSTANT cin_cmd1	 : NATURAL := 15;
-  CONSTANT cin_i0	 : NATURAL := 9;
-  CONSTANT cin_i1	 : NATURAL := 8;
-  CONSTANT cin_i2	 : NATURAL := 8;
-  CONSTANT rdown_cmd0_q	 : NATURAL := 810;
-  CONSTANT rdown_cmd0_q	 : NATURAL := 810;
-  CONSTANT rdown_cmd1_q	 : NATURAL := 810;
-  CONSTANT rdown_cmd1_q	 : NATURAL := 810;
-  CONSTANT rdown_i0_q	 : NATURAL := 810;
-  CONSTANT rdown_i1_q	 : NATURAL := 810;
-  CONSTANT rdown_i2_q	 : NATURAL := 810;
-  CONSTANT rup_cmd0_q	 : NATURAL := 890;
-  CONSTANT rup_cmd0_q	 : NATURAL := 890;
-  CONSTANT rup_cmd1_q	 : NATURAL := 890;
-  CONSTANT rup_cmd1_q	 : NATURAL := 890;
-  CONSTANT rup_i0_q	 : NATURAL := 890;
-  CONSTANT rup_i1_q	 : NATURAL := 890;
-  CONSTANT rup_i2_q	 : NATURAL := 890;
-  CONSTANT tphh_i0_q	 : NATURAL := 640;
-  CONSTANT tphh_cmd0_q	 : NATURAL := 683;
-  CONSTANT tphh_i1_q	 : NATURAL := 770;
-  CONSTANT tphh_i2_q	 : NATURAL := 770;
-  CONSTANT tpll_i0_q	 : NATURAL := 774;
-  CONSTANT tpll_cmd0_q	 : NATURAL := 779;
-  CONSTANT tphh_cmd1_q	 : NATURAL := 792;
-  CONSTANT tplh_cmd0_q	 : NATURAL := 844;
-  CONSTANT tplh_cmd1_q	 : NATURAL := 846;
-  CONSTANT tphl_cmd1_q	 : NATURAL := 872;
-  CONSTANT tphl_cmd0_q	 : NATURAL := 922;
-  CONSTANT tpll_i1_q	 : NATURAL := 948;
-  CONSTANT tpll_i2_q	 : NATURAL := 948;
-  CONSTANT tpll_cmd1_q	 : NATURAL := 967;
-  CONSTANT transistors	 : NATURAL := 22
-);
-PORT (
-  cmd0	 : in  BIT;
-  cmd1	 : in  BIT;
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END mx3_x4;
-
-ARCHITECTURE behaviour_data_flow OF mx3_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on mx3_x4"
-  SEVERITY WARNING;
-  q <= ((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not (cmd1)
-  and i2)))) after 1600 ps;
-END;
diff --git a/alliance/share/cells/sxlib/mx3_x4.vhd b/alliance/share/cells/sxlib/mx3_x4.vhd
deleted file mode 100644
index 281c341e..00000000
--- a/alliance/share/cells/sxlib/mx3_x4.vhd
+++ /dev/null
@@ -1,23 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY mx3_x4 IS
-PORT(
-  cmd0	: IN STD_LOGIC;
-  cmd1	: IN STD_LOGIC;
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END mx3_x4;
-
-ARCHITECTURE RTL OF mx3_x4 IS
-BEGIN
-  q <= ((NOT(cmd0) AND i0) OR (cmd0 AND ((cmd1 AND i1) OR (NOT(cmd1) AND i2))));
-END RTL;
diff --git a/alliance/share/cells/sxlib/na2_x1.al b/alliance/share/cells/sxlib/na2_x1.al
deleted file mode 100644
index e9556bd6..00000000
--- a/alliance/share/cells/sxlib/na2_x1.al
+++ /dev/null
@@ -1,24 +0,0 @@
-V ALLIANCE : 6
-H na2_x1,L,30/10/99
-C i0,IN,EXTERNAL,5
-C i1,IN,EXTERNAL,4
-C nq,OUT,EXTERNAL,1
-C vdd,IN,EXTERNAL,6
-C vss,IN,EXTERNAL,2
-T P,0.35,2.9,1,5,6,0,0.75,0.75,7.3,7.3,2.1,11.25,tr_00004
-T P,0.35,2.9,6,4,1,0,0.75,0.75,7.3,7.3,3.9,11.25,tr_00003
-T N,0.35,2.9,2,5,3,0,0.75,0.75,7.3,7.3,2.1,3.75,tr_00002
-T N,0.35,2.9,3,4,1,0,0.75,0.75,7.3,7.3,3.3,3.75,tr_00001
-S 6,EXTERNAL,vdd
-Q 0.00282047
-S 5,EXTERNAL,i0
-Q 0.00353623
-S 4,EXTERNAL,i1
-Q 0.00368237
-S 3,INTERNAL
-Q 0
-S 2,EXTERNAL,vss
-Q 0.0026442
-S 1,EXTERNAL,nq
-Q 0.00279086
-EOF
diff --git a/alliance/share/cells/sxlib/na2_x1.ap b/alliance/share/cells/sxlib/na2_x1.ap
deleted file mode 100644
index f900eaf4..00000000
--- a/alliance/share/cells/sxlib/na2_x1.ap
+++ /dev/null
@@ -1,58 +0,0 @@
-V ALLIANCE : 6
-H na2_x1,P,30/ 8/2000,100
-A 0,0,2000,5000
-R 1000,1000,ref_ref,nq_10
-R 1000,1500,ref_ref,nq_15
-R 1000,2000,ref_ref,nq_20
-R 1000,2500,ref_ref,nq_25
-R 1000,3000,ref_ref,nq_30
-R 1000,3500,ref_ref,nq_35
-R 1000,4000,ref_ref,nq_40
-R 1500,4000,ref_ref,i1_40
-R 1500,3500,ref_ref,i1_35
-R 1500,3000,ref_ref,i1_30
-R 1500,2500,ref_ref,i1_25
-R 1500,2000,ref_ref,i1_20
-R 1500,1500,ref_ref,i1_15
-R 500,1000,ref_ref,i0_10
-R 500,1500,ref_ref,i0_15
-R 500,2000,ref_ref,i0_20
-R 500,2500,ref_ref,i0_25
-R 500,3000,ref_ref,i0_30
-R 500,3500,ref_ref,i0_35
-R 500,4000,ref_ref,i0_40
-S 1000,1000,1000,4000,200,nq,DOWN,CALU1
-S 1500,1500,1500,4000,200,i1,DOWN,CALU1
-S 500,1000,500,4000,200,i0,DOWN,CALU1
-S 0,3900,2000,3900,2400,*,RIGHT,NWELL
-S 400,3000,700,3000,300,*,RIGHT,POLY
-S 1500,1500,1500,4000,100,*,DOWN,ALU1
-S 1600,3300,1600,4600,300,*,DOWN,PDIF
-S 400,3300,400,4600,300,*,DOWN,PDIF
-S 700,3100,700,4400,100,*,UP,PTRANS
-S 1000,3300,1000,4200,300,*,DOWN,PDIF
-S 1300,3100,1300,4400,100,*,UP,PTRANS
-S 500,1000,500,4000,100,*,DOWN,ALU1
-S 0,4700,2000,4700,600,vdd,RIGHT,CALU1
-S 0,300,2000,300,600,vss,RIGHT,CALU1
-S 1300,2000,1600,2000,300,*,RIGHT,POLY
-S 1300,1900,1300,3100,100,*,DOWN,POLY
-S 700,600,700,1900,100,*,DOWN,NTRANS
-S 1100,600,1100,1900,100,*,DOWN,NTRANS
-S 700,1900,700,3100,100,*,UP,POLY
-S 1100,1900,1600,1900,100,*,RIGHT,POLY
-S 1000,1000,1400,1000,200,*,RIGHT,ALU1
-S 1400,800,1400,1700,300,*,UP,NDIF
-S 400,400,400,1700,300,*,UP,NDIF
-S 1000,950,1000,4000,200,*,UP,ALU1
-V 500,3000,CONT_POLY,*
-V 1600,4500,CONT_DIF_P,*
-V 400,4500,CONT_DIF_P,*
-V 1000,4000,CONT_DIF_P,*
-V 1000,3500,CONT_DIF_P,*
-V 1000,4700,CONT_BODY_N,*
-V 1500,2000,CONT_POLY,*
-V 400,500,CONT_DIF_N,*
-V 1400,1000,CONT_DIF_N,*
-V 1250,300,CONT_BODY_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/na2_x1.sym b/alliance/share/cells/sxlib/na2_x1.sym
deleted file mode 100644
index 0ef443c8..00000000
Binary files a/alliance/share/cells/sxlib/na2_x1.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/na2_x1.vbe b/alliance/share/cells/sxlib/na2_x1.vbe
deleted file mode 100644
index 486b6aaf..00000000
--- a/alliance/share/cells/sxlib/na2_x1.vbe
+++ /dev/null
@@ -1,32 +0,0 @@
-ENTITY na2_x1 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 1000;
-  CONSTANT cin_i0	 : NATURAL := 11;
-  CONSTANT cin_i1	 : NATURAL := 11;
-  CONSTANT rdown_i0_nq	 : NATURAL := 2850;
-  CONSTANT rdown_i1_nq	 : NATURAL := 2850;
-  CONSTANT rup_i0_nq	 : NATURAL := 3720;
-  CONSTANT rup_i1_nq	 : NATURAL := 3720;
-  CONSTANT tphl_i0_nq	 : NATURAL := 59;
-  CONSTANT tphl_i1_nq	 : NATURAL := 111;
-  CONSTANT tplh_i1_nq	 : NATURAL := 234;
-  CONSTANT tplh_i0_nq	 : NATURAL := 288;
-  CONSTANT transistors	 : NATURAL := 4
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END na2_x1;
-
-ARCHITECTURE behaviour_data_flow OF na2_x1 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on na2_x1"
-  SEVERITY WARNING;
-  nq <= not ((i0 and i1)) after 900 ps;
-END;
diff --git a/alliance/share/cells/sxlib/na2_x1.vhd b/alliance/share/cells/sxlib/na2_x1.vhd
deleted file mode 100644
index 23b74f77..00000000
--- a/alliance/share/cells/sxlib/na2_x1.vhd
+++ /dev/null
@@ -1,20 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY na2_x1 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END na2_x1;
-
-ARCHITECTURE RTL OF na2_x1 IS
-BEGIN
-  nq <= NOT((i0 AND i1));
-END RTL;
diff --git a/alliance/share/cells/sxlib/na2_x4.al b/alliance/share/cells/sxlib/na2_x4.al
deleted file mode 100644
index 49769d58..00000000
--- a/alliance/share/cells/sxlib/na2_x4.al
+++ /dev/null
@@ -1,34 +0,0 @@
-V ALLIANCE : 6
-H na2_x4,L,30/10/99
-C i0,IN,EXTERNAL,8
-C i1,IN,EXTERNAL,7
-C nq,OUT,EXTERNAL,2
-C vdd,IN,EXTERNAL,5
-C vss,IN,EXTERNAL,1
-T P,0.35,2.9,6,3,5,0,0.75,0.75,7.3,7.3,8.7,9.75,tr_00010
-T P,0.35,5.9,2,6,5,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00009
-T P,0.35,5.9,5,6,2,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00008
-T P,0.35,2.9,3,8,5,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00007
-T P,0.35,2.9,5,7,3,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00006
-T N,0.35,2.9,1,6,2,0,0.75,0.75,7.3,7.3,5.1,2.25,tr_00005
-T N,0.35,2.9,2,6,1,0,0.75,0.75,7.3,7.3,6.9,2.25,tr_00004
-T N,0.35,1.4,1,3,6,0,0.75,0.75,4.3,4.3,8.7,3,tr_00003
-T N,0.35,2.9,4,7,1,0,0.75,0.75,7.3,7.3,3.3,3.75,tr_00002
-T N,0.35,2.9,3,8,4,0,0.75,0.75,7.3,7.3,1.8,3.75,tr_00001
-S 8,EXTERNAL,i0
-Q 0.00260759
-S 7,EXTERNAL,i1
-Q 0.00297253
-S 6,INTERNAL
-Q 0.0060306
-S 5,EXTERNAL,vdd
-Q 0.0046087
-S 4,INTERNAL
-Q 0
-S 3,INTERNAL
-Q 0.00560951
-S 2,EXTERNAL,nq
-Q 0.00214456
-S 1,EXTERNAL,vss
-Q 0.00419742
-EOF
diff --git a/alliance/share/cells/sxlib/na2_x4.ap b/alliance/share/cells/sxlib/na2_x4.ap
deleted file mode 100644
index 3d02b215..00000000
--- a/alliance/share/cells/sxlib/na2_x4.ap
+++ /dev/null
@@ -1,91 +0,0 @@
-V ALLIANCE : 6
-H na2_x4,P,30/ 8/2000,100
-A 0,0,3500,5000
-R 2000,1000,ref_ref,nq_10
-R 2000,1500,ref_ref,nq_15
-R 2000,2000,ref_ref,nq_20
-R 2000,2500,ref_ref,nq_25
-R 2000,3000,ref_ref,nq_30
-R 2000,3500,ref_ref,nq_35
-R 500,1500,ref_ref,i0_15
-R 500,2000,ref_ref,i0_20
-R 500,2500,ref_ref,i0_25
-R 500,3000,ref_ref,i0_30
-R 500,3500,ref_ref,i0_35
-R 1000,3500,ref_ref,i1_35
-R 1000,3000,ref_ref,i1_30
-R 1000,2500,ref_ref,i1_25
-R 1000,2000,ref_ref,i1_20
-R 1000,1500,ref_ref,i1_15
-S 2000,1000,2000,3500,200,nq,DOWN,CALU1
-S 500,1500,500,3500,200,i0,DOWN,CALU1
-S 1000,1500,1000,3500,200,i1,DOWN,CALU1
-S 0,3900,3500,3900,2400,*,RIGHT,NWELL
-S 300,300,900,300,300,*,LEFT,PTIE
-S 1700,100,1700,1400,100,*,DOWN,NTRANS
-S 2000,300,2000,1200,300,*,UP,NDIF
-S 2300,100,2300,1400,100,*,DOWN,NTRANS
-S 2600,300,2600,1200,300,*,UP,NDIF
-S 0,300,3500,300,600,vss,RIGHT,CALU1
-S 2900,600,2900,1400,100,*,DOWN,NTRANS
-S 3200,800,3200,1200,300,*,DOWN,NDIF
-S 0,4700,3500,4700,600,vdd,RIGHT,CALU1
-S 2600,2800,2600,4700,300,*,DOWN,PDIF
-S 2900,2600,2900,3900,100,*,UP,PTRANS
-S 3200,2800,3200,3700,300,*,UP,PDIF
-S 2900,1400,2900,2600,100,*,DOWN,POLY
-S 300,1000,1500,1000,100,*,RIGHT,ALU1
-S 1000,1500,1000,3500,100,*,UP,ALU1
-S 500,1500,500,3500,100,*,UP,ALU1
-S 900,4000,3000,4000,100,*,RIGHT,ALU1
-S 3200,1000,3200,3500,100,*,DOWN,ALU1
-S 2100,2800,2100,4700,300,*,DOWN,PDIF
-S 1800,2600,1800,4900,100,*,UP,PTRANS
-S 2400,2600,2400,4900,100,*,UP,PTRANS
-S 1500,2800,1500,4700,300,*,DOWN,PDIF
-S 850,3700,850,4200,200,*,DOWN,PDIF
-S 600,3100,600,4400,100,*,UP,PTRANS
-S 900,3300,900,4200,300,*,DOWN,PDIF
-S 1200,3100,1200,4400,100,*,UP,PTRANS
-S 300,3300,300,4600,300,*,DOWN,PDIF
-S 1500,1000,1500,4000,100,*,UP,ALU1
-S 2700,4300,2700,4700,300,*,UP,PDIF
-S 1200,1900,1200,3100,100,*,UP,POLY
-S 900,2000,1200,2000,300,*,RIGHT,POLY
-S 2500,2000,3200,2000,100,*,LEFT,ALU1
-S 1700,2000,2600,2000,300,*,RIGHT,POLY
-S 1700,1400,1700,2100,100,*,UP,POLY
-S 2300,1400,2300,1900,100,*,DOWN,POLY
-S 1800,1900,1800,2600,100,*,DOWN,POLY
-S 2400,1900,2400,2600,100,*,DOWN,POLY
-S 1100,600,1100,1900,100,*,DOWN,NTRANS
-S 300,800,300,1700,300,*,UP,NDIF
-S 900,800,900,1700,300,*,UP,NDIF
-S 600,600,600,1900,100,*,DOWN,NTRANS
-S 600,1900,600,3100,100,*,DOWN,POLY
-S 1400,300,1400,1700,300,*,UP,NDIF
-S 2000,1000,2000,3550,200,*,DOWN,ALU1
-S 300,4000,300,4500,200,*,UP,ALU1
-V 3200,300,CONT_BODY_P,*
-V 300,300,CONT_BODY_P,*
-V 300,1000,CONT_DIF_N,*
-V 1400,500,CONT_DIF_N,*
-V 2600,500,CONT_DIF_N,*
-V 2000,1000,CONT_DIF_N,*
-V 3200,1000,CONT_DIF_N,*
-V 800,300,CONT_BODY_P,*
-V 3200,3000,CONT_DIF_P,*
-V 3200,3500,CONT_DIF_P,*
-V 3000,4000,CONT_POLY,*
-V 1000,2000,CONT_POLY,*
-V 500,2000,CONT_POLY,*
-V 2700,4500,CONT_DIF_P,*
-V 2100,3000,CONT_DIF_P,*
-V 2100,3500,CONT_DIF_P,*
-V 300,4500,CONT_DIF_P,*
-V 900,4000,CONT_DIF_P,*
-V 900,4700,CONT_BODY_N,*
-V 2500,2000,CONT_POLY,*
-V 1500,4500,CONT_DIF_P,*
-V 300,4000,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/na2_x4.sym b/alliance/share/cells/sxlib/na2_x4.sym
deleted file mode 100644
index be1b6080..00000000
Binary files a/alliance/share/cells/sxlib/na2_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/na2_x4.vbe b/alliance/share/cells/sxlib/na2_x4.vbe
deleted file mode 100644
index c73eca05..00000000
--- a/alliance/share/cells/sxlib/na2_x4.vbe
+++ /dev/null
@@ -1,32 +0,0 @@
-ENTITY na2_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 1750;
-  CONSTANT cin_i0	 : NATURAL := 10;
-  CONSTANT cin_i1	 : NATURAL := 10;
-  CONSTANT rdown_i0_nq	 : NATURAL := 810;
-  CONSTANT rdown_i1_nq	 : NATURAL := 810;
-  CONSTANT rup_i0_nq	 : NATURAL := 890;
-  CONSTANT rup_i1_nq	 : NATURAL := 890;
-  CONSTANT tphl_i1_nq	 : NATURAL := 353;
-  CONSTANT tphl_i0_nq	 : NATURAL := 412;
-  CONSTANT tplh_i0_nq	 : NATURAL := 552;
-  CONSTANT tplh_i1_nq	 : NATURAL := 601;
-  CONSTANT transistors	 : NATURAL := 10
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END na2_x4;
-
-ARCHITECTURE behaviour_data_flow OF na2_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on na2_x4"
-  SEVERITY WARNING;
-  nq <= not ((i0 and i1)) after 1200 ps;
-END;
diff --git a/alliance/share/cells/sxlib/na2_x4.vhd b/alliance/share/cells/sxlib/na2_x4.vhd
deleted file mode 100644
index ef555cb4..00000000
--- a/alliance/share/cells/sxlib/na2_x4.vhd
+++ /dev/null
@@ -1,20 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY na2_x4 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END na2_x4;
-
-ARCHITECTURE RTL OF na2_x4 IS
-BEGIN
-  nq <= NOT((i0 AND i1));
-END RTL;
diff --git a/alliance/share/cells/sxlib/na3_x1.al b/alliance/share/cells/sxlib/na3_x1.al
deleted file mode 100644
index e2da070a..00000000
--- a/alliance/share/cells/sxlib/na3_x1.al
+++ /dev/null
@@ -1,31 +0,0 @@
-V ALLIANCE : 6
-H na3_x1,L,30/10/99
-C i0,IN,EXTERNAL,7
-C i1,IN,EXTERNAL,5
-C i2,IN,EXTERNAL,6
-C nq,OUT,EXTERNAL,2
-C vdd,IN,EXTERNAL,8
-C vss,IN,EXTERNAL,3
-T P,0.35,2.9,2,7,8,0,0.75,0.75,7.3,7.3,2.1,11.25,tr_00006
-T P,0.35,2.9,2,6,8,0,0.75,0.75,7.3,7.3,5.7,11.25,tr_00005
-T P,0.35,2.9,8,5,2,0,0.75,0.75,7.3,7.3,3.9,11.25,tr_00004
-T N,0.35,2.9,1,6,2,0,0.75,0.75,7.3,7.3,4.2,2.25,tr_00003
-T N,0.35,2.9,4,5,1,0,0.75,0.75,7.3,7.3,3,2.25,tr_00002
-T N,0.35,2.9,3,7,4,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00001
-S 8,EXTERNAL,vdd
-Q 0.0033382
-S 7,EXTERNAL,i0
-Q 0.00388325
-S 6,EXTERNAL,i2
-Q 0.00352565
-S 5,EXTERNAL,i1
-Q 0.00390877
-S 4,INTERNAL
-Q 0
-S 3,EXTERNAL,vss
-Q 0.00298567
-S 2,EXTERNAL,nq
-Q 0.00346654
-S 1,INTERNAL
-Q 0
-EOF
diff --git a/alliance/share/cells/sxlib/na3_x1.ap b/alliance/share/cells/sxlib/na3_x1.ap
deleted file mode 100644
index ffa9d262..00000000
--- a/alliance/share/cells/sxlib/na3_x1.ap
+++ /dev/null
@@ -1,77 +0,0 @@
-V ALLIANCE : 6
-H na3_x1,P,30/ 8/2000,100
-A 0,0,2500,5000
-R 1500,1000,ref_ref,i2_10
-R 1500,1500,ref_ref,i2_15
-R 1500,2000,ref_ref,i2_20
-R 1500,2500,ref_ref,i2_25
-R 1500,3000,ref_ref,i2_30
-R 1500,3500,ref_ref,i2_35
-R 1000,1000,ref_ref,i1_10
-R 1000,1500,ref_ref,i1_15
-R 1000,2000,ref_ref,i1_20
-R 1000,2500,ref_ref,i1_25
-R 1000,3000,ref_ref,i1_30
-R 1000,3500,ref_ref,i1_35
-R 500,1000,ref_ref,i0_10
-R 500,1500,ref_ref,i0_15
-R 500,2000,ref_ref,i0_20
-R 500,2500,ref_ref,i0_25
-R 500,3000,ref_ref,i0_30
-R 500,3500,ref_ref,i0_35
-R 500,4000,ref_ref,i0_40
-R 2000,1000,ref_ref,nq_10
-R 2000,1500,ref_ref,nq_15
-R 2000,2000,ref_ref,nq_20
-R 2000,3000,ref_ref,nq_30
-R 2000,2500,ref_ref,nq_25
-R 2000,3500,ref_ref,nq_35
-R 2000,4000,ref_ref,nq_40
-S 1500,1000,1500,3500,200,i2,DOWN,CALU1
-S 1000,1000,1000,3500,200,i1,DOWN,CALU1
-S 500,1000,500,4000,200,i0,DOWN,CALU1
-S 2000,1000,2000,4000,200,nq,DOWN,CALU1
-S 2000,4000,2200,4000,200,*,RIGHT,ALU1
-S 1000,1400,1000,2100,100,*,UP,POLY
-S 1300,1900,1300,3100,100,*,DOWN,POLY
-S 900,2000,1300,2000,300,*,RIGHT,POLY
-S 400,3000,700,3000,300,*,RIGHT,POLY
-S 600,1400,600,3100,100,*,DOWN,POLY
-S 1400,1600,1900,1600,100,*,LEFT,POLY
-S 1900,1600,1900,3100,100,*,DOWN,POLY
-S 700,3100,700,4400,100,*,UP,PTRANS
-S 1900,3100,1900,4400,100,*,UP,PTRANS
-S 1600,3300,1600,4600,300,*,DOWN,PDIF
-S 400,3300,400,4600,300,*,DOWN,PDIF
-S 1300,3100,1300,4400,100,*,UP,PTRANS
-S 1000,3300,1000,4200,300,*,DOWN,PDIF
-S 2200,3300,2200,4200,300,*,DOWN,PDIF
-S 1900,800,1900,1200,500,*,UP,NDIF
-S 1600,300,1600,1200,200,*,UP,NDIF
-S 1400,100,1400,1400,100,*,DOWN,NTRANS
-S 1000,100,1000,1400,100,*,DOWN,NTRANS
-S 1500,1000,1500,3500,100,*,DOWN,ALU1
-S 1000,1000,1000,3500,100,*,UP,ALU1
-S 500,1000,500,4000,100,*,DOWN,ALU1
-S 0,4700,2500,4700,600,vdd,RIGHT,CALU1
-S 0,300,2500,300,600,vss,RIGHT,CALU1
-S 800,300,800,1200,300,*,UP,NDIF
-S 600,100,600,1400,100,*,DOWN,NTRANS
-S 300,300,300,1200,300,*,DOWN,NDIF
-S 1700,900,1700,1200,300,*,DOWN,NDIF
-S 0,3900,2500,3900,2400,*,RIGHT,NWELL
-S 2000,1000,2000,4000,200,*,UP,ALU1
-S 1000,4000,2200,4000,200,*,RIGHT,ALU1
-V 1000,2000,CONT_POLY,*
-V 500,3000,CONT_POLY,*
-V 2200,4700,CONT_BODY_N,*
-V 1000,4000,CONT_DIF_P,*
-V 400,4500,CONT_DIF_P,*
-V 1600,4500,CONT_DIF_P,*
-V 2200,4000,CONT_DIF_P,*
-V 1000,4700,CONT_BODY_N,*
-V 2000,1000,CONT_DIF_N,*
-V 1500,1500,CONT_POLY,*
-V 2200,300,CONT_BODY_P,*
-V 300,500,CONT_DIF_N,*
-EOF
diff --git a/alliance/share/cells/sxlib/na3_x1.sym b/alliance/share/cells/sxlib/na3_x1.sym
deleted file mode 100644
index f2d1f56c..00000000
Binary files a/alliance/share/cells/sxlib/na3_x1.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/na3_x1.vbe b/alliance/share/cells/sxlib/na3_x1.vbe
deleted file mode 100644
index d51e1207..00000000
--- a/alliance/share/cells/sxlib/na3_x1.vbe
+++ /dev/null
@@ -1,38 +0,0 @@
-ENTITY na3_x1 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 1250;
-  CONSTANT cin_i0	 : NATURAL := 11;
-  CONSTANT cin_i1	 : NATURAL := 11;
-  CONSTANT cin_i2	 : NATURAL := 11;
-  CONSTANT rdown_i0_nq	 : NATURAL := 4120;
-  CONSTANT rdown_i1_nq	 : NATURAL := 4120;
-  CONSTANT rdown_i2_nq	 : NATURAL := 4120;
-  CONSTANT rup_i0_nq	 : NATURAL := 3720;
-  CONSTANT rup_i1_nq	 : NATURAL := 3720;
-  CONSTANT rup_i2_nq	 : NATURAL := 3720;
-  CONSTANT tphl_i0_nq	 : NATURAL := 119;
-  CONSTANT tphl_i1_nq	 : NATURAL := 171;
-  CONSTANT tphl_i2_nq	 : NATURAL := 193;
-  CONSTANT tplh_i2_nq	 : NATURAL := 265;
-  CONSTANT tplh_i1_nq	 : NATURAL := 316;
-  CONSTANT tplh_i0_nq	 : NATURAL := 363;
-  CONSTANT transistors	 : NATURAL := 6
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END na3_x1;
-
-ARCHITECTURE behaviour_data_flow OF na3_x1 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on na3_x1"
-  SEVERITY WARNING;
-  nq <= not (((i0 and i1) and i2)) after 1000 ps;
-END;
diff --git a/alliance/share/cells/sxlib/na3_x1.vhd b/alliance/share/cells/sxlib/na3_x1.vhd
deleted file mode 100644
index 278daf09..00000000
--- a/alliance/share/cells/sxlib/na3_x1.vhd
+++ /dev/null
@@ -1,21 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY na3_x1 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END na3_x1;
-
-ARCHITECTURE RTL OF na3_x1 IS
-BEGIN
-  nq <= NOT(((i0 AND i1) AND i2));
-END RTL;
diff --git a/alliance/share/cells/sxlib/na3_x4.al b/alliance/share/cells/sxlib/na3_x4.al
deleted file mode 100644
index caa069a8..00000000
--- a/alliance/share/cells/sxlib/na3_x4.al
+++ /dev/null
@@ -1,41 +0,0 @@
-V ALLIANCE : 6
-H na3_x4,L,30/10/99
-C i0,IN,EXTERNAL,8
-C i1,IN,EXTERNAL,9
-C i2,IN,EXTERNAL,10
-C nq,OUT,EXTERNAL,5
-C vdd,IN,EXTERNAL,6
-C vss,IN,EXTERNAL,4
-T P,0.35,2.9,6,9,3,0,0.75,0.75,7.3,7.3,5.4,10.95,tr_00012
-T P,0.35,2.9,3,10,6,0,0.75,0.75,7.3,7.3,3.6,10.95,tr_00011
-T P,0.35,2.9,6,8,3,0,0.75,0.75,7.3,7.3,1.8,10.95,tr_00010
-T P,0.35,5.9,6,7,5,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00009
-T P,0.35,2.9,7,3,6,0,0.75,0.75,7.3,7.3,10.2,9.75,tr_00008
-T P,0.35,5.9,5,7,6,0,0.75,0.75,13.3,13.3,6.9,11.25,tr_00007
-T N,0.35,2.9,2,9,4,0,0.75,0.75,7.3,7.3,4.5,3.75,tr_00006
-T N,0.35,2.9,3,8,1,0,0.75,0.75,7.3,7.3,2.1,3.75,tr_00005
-T N,0.35,2.9,1,10,2,0,0.75,0.75,7.3,7.3,3.3,3.75,tr_00004
-T N,0.35,2.9,4,7,5,0,0.75,0.75,7.3,7.3,6.6,2.25,tr_00003
-T N,0.35,2.9,5,7,4,0,0.75,0.75,7.3,7.3,8.4,2.25,tr_00002
-T N,0.35,1.4,4,3,7,0,0.75,0.75,4.3,4.3,10.2,3,tr_00001
-S 10,EXTERNAL,i2
-Q 0.00312291
-S 9,EXTERNAL,i1
-Q 0.00275797
-S 8,EXTERNAL,i0
-Q 0.00290312
-S 7,INTERNAL
-Q 0.0060306
-S 6,EXTERNAL,vdd
-Q 0.00436263
-S 5,EXTERNAL,nq
-Q 0.00214456
-S 4,EXTERNAL,vss
-Q 0.00436263
-S 3,INTERNAL
-Q 0.00663132
-S 2,INTERNAL
-Q 0
-S 1,INTERNAL
-Q 0
-EOF
diff --git a/alliance/share/cells/sxlib/na3_x4.ap b/alliance/share/cells/sxlib/na3_x4.ap
deleted file mode 100644
index 4022c49c..00000000
--- a/alliance/share/cells/sxlib/na3_x4.ap
+++ /dev/null
@@ -1,101 +0,0 @@
-V ALLIANCE : 6
-H na3_x4,P,30/ 8/2000,100
-A 0,0,4000,5000
-R 1500,3000,ref_ref,i1_30
-R 1500,3500,ref_ref,i1_35
-R 500,3000,ref_ref,i0_30
-R 500,3500,ref_ref,i0_35
-R 500,1500,ref_ref,i0_15
-R 500,2000,ref_ref,i0_20
-R 500,2500,ref_ref,i0_25
-R 1500,2500,ref_ref,i1_25
-R 1500,2000,ref_ref,i1_20
-R 1500,1500,ref_ref,i1_15
-R 2500,1000,ref_ref,nq_10
-R 2500,1500,ref_ref,nq_15
-R 2500,2000,ref_ref,nq_20
-R 2500,2500,ref_ref,nq_25
-R 2500,3000,ref_ref,nq_30
-R 2500,3500,ref_ref,nq_35
-R 1000,3500,ref_ref,i2_35
-R 1000,3000,ref_ref,i2_30
-R 1000,2500,ref_ref,i2_25
-R 1000,2000,ref_ref,i2_20
-R 1000,1500,ref_ref,i2_15
-S 500,1500,500,3500,200,i0,DOWN,CALU1
-S 1500,1500,1500,3500,200,i1,DOWN,CALU1
-S 2500,1000,2500,3500,200,nq,DOWN,CALU1
-S 1000,1500,1000,3500,200,i2,DOWN,CALU1
-S 0,3900,4000,3900,2400,*,RIGHT,NWELL
-S 1100,1900,1100,2600,100,*,UP,POLY
-S 900,2500,1200,2500,300,*,RIGHT,POLY
-S 600,1900,600,3000,100,*,DOWN,POLY
-S 1200,2400,1200,3000,100,*,DOWN,POLY
-S 1800,2100,1800,3000,100,*,DOWN,POLY
-S 900,3200,900,4600,300,*,DOWN,PDIF
-S 300,3200,300,4100,300,*,DOWN,PDIF
-S 1800,3000,1800,4300,100,*,UP,PTRANS
-S 1500,3200,1500,4100,300,*,DOWN,PDIF
-S 1200,3000,1200,4300,100,*,UP,PTRANS
-S 600,3000,600,4300,100,*,UP,PTRANS
-S 2100,2800,2100,4700,300,*,DOWN,PDIF
-S 1400,2100,1800,2100,100,*,RIGHT,POLY
-S 500,1500,500,3500,100,*,UP,ALU1
-S 400,2000,700,2000,300,*,RIGHT,POLY
-S 300,4000,3500,4000,100,*,RIGHT,ALU1
-S 400,1000,2000,1000,100,*,RIGHT,ALU1
-S 400,800,400,1700,300,*,UP,NDIF
-S 1800,300,1800,1700,300,*,UP,NDIF
-S 1500,600,1500,1900,100,*,DOWN,NTRANS
-S 700,600,700,1900,100,*,DOWN,NTRANS
-S 0,300,4000,300,600,vss,RIGHT,CALU1
-S 0,4700,4000,4700,600,vdd,RIGHT,CALU1
-S 3700,800,3700,1200,300,*,DOWN,NDIF
-S 1100,600,1100,1900,100,*,DOWN,NTRANS
-S 1900,300,1900,1700,300,*,UP,NDIF
-S 2200,100,2200,1400,100,*,DOWN,NTRANS
-S 2500,300,2500,1200,300,*,UP,NDIF
-S 2800,100,2800,1400,100,*,DOWN,NTRANS
-S 3100,300,3100,1200,300,*,UP,NDIF
-S 3400,600,3400,1400,100,*,DOWN,NTRANS
-S 2900,2600,2900,4900,100,*,UP,PTRANS
-S 3100,2800,3100,4700,300,*,DOWN,PDIF
-S 3400,2600,3400,3900,100,*,UP,PTRANS
-S 3700,2800,3700,3700,300,*,UP,PDIF
-S 2600,2800,2600,4700,300,*,DOWN,PDIF
-S 2300,2600,2300,4900,100,*,UP,PTRANS
-S 3400,1400,3400,2600,100,*,DOWN,POLY
-S 2200,2000,3100,2000,300,*,RIGHT,POLY
-S 2200,1400,2200,2100,100,*,UP,POLY
-S 2800,1400,2800,1900,100,*,DOWN,POLY
-S 2300,1900,2300,2600,100,*,DOWN,POLY
-S 2900,1900,2900,2600,100,*,DOWN,POLY
-S 2000,1000,2000,4000,100,*,UP,ALU1
-S 3000,2000,3700,2000,100,*,LEFT,ALU1
-S 1500,1500,1500,3500,100,*,UP,ALU1
-S 1000,1500,1000,3500,100,*,UP,ALU1
-S 3700,1000,3700,3500,100,*,DOWN,ALU1
-S 2500,1000,2500,3550,200,*,DOWN,ALU1
-V 300,300,CONT_BODY_P,*
-V 900,4500,CONT_DIF_P,*
-V 3200,4600,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 300,4700,CONT_BODY_N,*
-V 300,4000,CONT_DIF_P,*
-V 500,2000,CONT_POLY,*
-V 400,1000,CONT_DIF_N,*
-V 1900,500,CONT_DIF_N,*
-V 3100,500,CONT_DIF_N,*
-V 2500,1000,CONT_DIF_N,*
-V 3700,1000,CONT_DIF_N,*
-V 3700,3000,CONT_DIF_P,*
-V 3700,3500,CONT_DIF_P,*
-V 2600,3000,CONT_DIF_P,*
-V 2600,3500,CONT_DIF_P,*
-V 3700,300,CONT_BODY_P,*
-V 3500,4000,CONT_POLY,*
-V 1500,2000,CONT_POLY,*
-V 3000,2000,CONT_POLY,*
-V 1000,2500,CONT_POLY,*
-V 2000,4600,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/na3_x4.sym b/alliance/share/cells/sxlib/na3_x4.sym
deleted file mode 100644
index 95146908..00000000
Binary files a/alliance/share/cells/sxlib/na3_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/na3_x4.vbe b/alliance/share/cells/sxlib/na3_x4.vbe
deleted file mode 100644
index 160a97f6..00000000
--- a/alliance/share/cells/sxlib/na3_x4.vbe
+++ /dev/null
@@ -1,38 +0,0 @@
-ENTITY na3_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 2000;
-  CONSTANT cin_i0	 : NATURAL := 10;
-  CONSTANT cin_i1	 : NATURAL := 10;
-  CONSTANT cin_i2	 : NATURAL := 10;
-  CONSTANT rdown_i0_nq	 : NATURAL := 810;
-  CONSTANT rdown_i1_nq	 : NATURAL := 810;
-  CONSTANT rdown_i2_nq	 : NATURAL := 810;
-  CONSTANT rup_i0_nq	 : NATURAL := 890;
-  CONSTANT rup_i1_nq	 : NATURAL := 890;
-  CONSTANT rup_i2_nq	 : NATURAL := 890;
-  CONSTANT tphl_i1_nq	 : NATURAL := 460;
-  CONSTANT tphl_i2_nq	 : NATURAL := 519;
-  CONSTANT tphl_i0_nq	 : NATURAL := 556;
-  CONSTANT tplh_i0_nq	 : NATURAL := 601;
-  CONSTANT tplh_i2_nq	 : NATURAL := 647;
-  CONSTANT tplh_i1_nq	 : NATURAL := 691;
-  CONSTANT transistors	 : NATURAL := 12
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END na3_x4;
-
-ARCHITECTURE behaviour_data_flow OF na3_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on na3_x4"
-  SEVERITY WARNING;
-  nq <= not (((i0 and i1) and i2)) after 1300 ps;
-END;
diff --git a/alliance/share/cells/sxlib/na3_x4.vhd b/alliance/share/cells/sxlib/na3_x4.vhd
deleted file mode 100644
index ccf28ce7..00000000
--- a/alliance/share/cells/sxlib/na3_x4.vhd
+++ /dev/null
@@ -1,21 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY na3_x4 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END na3_x4;
-
-ARCHITECTURE RTL OF na3_x4 IS
-BEGIN
-  nq <= NOT(((i0 AND i1) AND i2));
-END RTL;
diff --git a/alliance/share/cells/sxlib/na4_x1.al b/alliance/share/cells/sxlib/na4_x1.al
deleted file mode 100644
index 3287ed3c..00000000
--- a/alliance/share/cells/sxlib/na4_x1.al
+++ /dev/null
@@ -1,38 +0,0 @@
-V ALLIANCE : 6
-H na4_x1,L,30/10/99
-C i0,IN,EXTERNAL,8
-C i1,IN,EXTERNAL,7
-C i2,IN,EXTERNAL,6
-C i3,IN,EXTERNAL,9
-C nq,OUT,EXTERNAL,4
-C vdd,IN,EXTERNAL,10
-C vss,IN,EXTERNAL,3
-T P,0.35,2.9,10,7,4,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00008
-T P,0.35,2.9,4,6,10,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00007
-T P,0.35,2.9,10,9,4,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00006
-T P,0.35,2.9,4,8,10,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00005
-T N,0.35,2.9,3,8,1,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00004
-T N,0.35,2.9,1,7,2,0,0.75,0.75,7.3,7.3,3,2.25,tr_00003
-T N,0.35,2.9,2,6,5,0,0.75,0.75,7.3,7.3,4.2,2.25,tr_00002
-T N,0.35,2.9,5,9,4,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00001
-S 10,EXTERNAL,vdd
-Q 0.00444349
-S 9,EXTERNAL,i3
-Q 0.00381484
-S 8,EXTERNAL,i0
-Q 0.00323647
-S 7,EXTERNAL,i1
-Q 0.00345625
-S 6,EXTERNAL,i2
-Q 0.00367603
-S 5,INTERNAL
-Q 0
-S 4,EXTERNAL,nq
-Q 0.0035253
-S 3,EXTERNAL,vss
-Q 0.00332715
-S 2,INTERNAL
-Q 0
-S 1,INTERNAL
-Q 0
-EOF
diff --git a/alliance/share/cells/sxlib/na4_x1.ap b/alliance/share/cells/sxlib/na4_x1.ap
deleted file mode 100644
index 9207c5af..00000000
--- a/alliance/share/cells/sxlib/na4_x1.ap
+++ /dev/null
@@ -1,90 +0,0 @@
-V ALLIANCE : 6
-H na4_x1,P,30/ 8/2000,100
-A 0,0,3000,5000
-R 2500,4000,ref_ref,nq_40
-R 2500,1000,ref_ref,nq_10
-R 2500,1500,ref_ref,nq_15
-R 2500,2000,ref_ref,nq_20
-R 2500,2500,ref_ref,nq_25
-R 2500,3000,ref_ref,nq_30
-R 2500,3500,ref_ref,nq_35
-R 2000,3500,ref_ref,i3_35
-R 2000,3000,ref_ref,i3_30
-R 2000,2500,ref_ref,i3_25
-R 2000,2000,ref_ref,i3_20
-R 2000,1500,ref_ref,i3_15
-R 2000,1000,ref_ref,i3_10
-R 1500,1000,ref_ref,i2_10
-R 1500,1500,ref_ref,i2_15
-R 1500,2000,ref_ref,i2_20
-R 1500,2500,ref_ref,i2_25
-R 1500,3000,ref_ref,i2_30
-R 1500,3500,ref_ref,i2_35
-R 1000,3500,ref_ref,i1_35
-R 1000,3000,ref_ref,i1_30
-R 1000,2500,ref_ref,i1_25
-R 1000,2000,ref_ref,i1_20
-R 1000,1500,ref_ref,i1_15
-R 1000,1000,ref_ref,i1_10
-R 500,1000,ref_ref,i0_10
-R 500,3500,ref_ref,i0_35
-R 500,3000,ref_ref,i0_30
-R 500,2500,ref_ref,i0_25
-R 500,2000,ref_ref,i0_20
-R 500,1500,ref_ref,i0_15
-S 300,4000,300,4500,200,*,UP,ALU1
-S 900,4000,2550,4000,200,*,LEFT,ALU1
-S 2500,1000,2500,4050,200,*,UP,ALU1
-S 600,1400,600,3100,100,*,DOWN,POLY
-S 2400,1900,2400,3100,100,*,UP,POLY
-S 1800,1900,2400,1900,100,*,RIGHT,POLY
-S 1800,1400,1800,1900,100,*,UP,POLY
-S 1800,2600,1800,3100,100,*,UP,POLY
-S 1400,2600,1800,2600,100,*,RIGHT,POLY
-S 1400,1400,1400,2600,100,*,UP,POLY
-S 1000,3100,1200,3100,100,*,RIGHT,POLY
-S 1000,1400,1000,3100,100,*,UP,POLY
-S 2300,800,2300,1200,700,*,UP,NDIF
-S 2000,1000,2000,3500,100,*,DOWN,ALU1
-S 1500,1000,1500,3500,100,*,DOWN,ALU1
-S 1000,1000,1000,3500,100,*,DOWN,ALU1
-S 500,1000,500,3500,100,*,DOWN,ALU1
-S 2100,300,2100,1200,300,*,DOWN,NDIF
-S 1800,100,1800,1400,100,*,DOWN,NTRANS
-S 1400,100,1400,1400,100,*,DOWN,NTRANS
-S 1000,100,1000,1400,100,*,DOWN,NTRANS
-S 300,3300,300,4600,300,*,DOWN,PDIF
-S 1500,3300,1500,4600,300,*,DOWN,PDIF
-S 2700,3300,2700,4600,300,*,DOWN,PDIF
-S 600,3100,600,4400,100,*,UP,PTRANS
-S 2400,3100,2400,4400,100,*,UP,PTRANS
-S 1800,3100,1800,4400,100,*,UP,PTRANS
-S 1200,3100,1200,4400,100,*,UP,PTRANS
-S 900,3300,900,4200,300,*,DOWN,PDIF
-S 2100,3300,2100,4200,300,*,DOWN,PDIF
-S 0,4700,3000,4700,600,vdd,RIGHT,CALU1
-S 0,300,3000,300,600,vss,RIGHT,CALU1
-S 600,100,600,1400,100,*,DOWN,NTRANS
-S 300,300,300,1200,300,*,DOWN,NDIF
-S 0,3900,3000,3900,2400,*,RIGHT,NWELL
-S 2500,1000,2500,4000,200,nq,DOWN,CALU1
-S 2000,1000,2000,3500,200,i3,DOWN,CALU1
-S 1500,1000,1500,3500,200,i2,DOWN,CALU1
-S 1000,1000,1000,3500,200,i1,DOWN,CALU1
-S 500,1000,500,3500,200,i0,DOWN,CALU1
-V 300,4000,CONT_DIF_P,*
-V 500,1500,CONT_POLY,*
-V 2000,2000,CONT_POLY,*
-V 1500,2500,CONT_POLY,*
-V 1000,2000,CONT_POLY,*
-V 900,4700,CONT_BODY_N,*
-V 2100,4700,CONT_BODY_N,*
-V 2500,1000,CONT_DIF_N,*
-V 2100,4000,CONT_DIF_P,*
-V 900,4000,CONT_DIF_P,*
-V 300,4500,CONT_DIF_P,*
-V 2700,4500,CONT_DIF_P,*
-V 1500,4500,CONT_DIF_P,*
-V 2700,300,CONT_BODY_P,*
-V 300,500,CONT_DIF_N,*
-EOF
diff --git a/alliance/share/cells/sxlib/na4_x1.sym b/alliance/share/cells/sxlib/na4_x1.sym
deleted file mode 100644
index 17cafb1e..00000000
Binary files a/alliance/share/cells/sxlib/na4_x1.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/na4_x1.vbe b/alliance/share/cells/sxlib/na4_x1.vbe
deleted file mode 100644
index 07f51ce0..00000000
--- a/alliance/share/cells/sxlib/na4_x1.vbe
+++ /dev/null
@@ -1,44 +0,0 @@
-ENTITY na4_x1 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 1500;
-  CONSTANT cin_i0	 : NATURAL := 10;
-  CONSTANT cin_i1	 : NATURAL := 11;
-  CONSTANT cin_i2	 : NATURAL := 11;
-  CONSTANT cin_i3	 : NATURAL := 11;
-  CONSTANT rdown_i0_nq	 : NATURAL := 5400;
-  CONSTANT rdown_i1_nq	 : NATURAL := 5400;
-  CONSTANT rdown_i2_nq	 : NATURAL := 5400;
-  CONSTANT rdown_i3_nq	 : NATURAL := 5400;
-  CONSTANT rup_i0_nq	 : NATURAL := 3720;
-  CONSTANT rup_i1_nq	 : NATURAL := 3720;
-  CONSTANT rup_i2_nq	 : NATURAL := 3720;
-  CONSTANT rup_i3_nq	 : NATURAL := 3720;
-  CONSTANT tphl_i0_nq	 : NATURAL := 179;
-  CONSTANT tphl_i1_nq	 : NATURAL := 237;
-  CONSTANT tphl_i2_nq	 : NATURAL := 269;
-  CONSTANT tphl_i3_nq	 : NATURAL := 282;
-  CONSTANT tplh_i3_nq	 : NATURAL := 302;
-  CONSTANT tplh_i2_nq	 : NATURAL := 350;
-  CONSTANT tplh_i1_nq	 : NATURAL := 395;
-  CONSTANT tplh_i0_nq	 : NATURAL := 438;
-  CONSTANT transistors	 : NATURAL := 8
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  i3	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END na4_x1;
-
-ARCHITECTURE behaviour_data_flow OF na4_x1 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on na4_x1"
-  SEVERITY WARNING;
-  nq <= not ((((i0 and i1) and i2) and i3)) after 1000 ps;
-END;
diff --git a/alliance/share/cells/sxlib/na4_x1.vhd b/alliance/share/cells/sxlib/na4_x1.vhd
deleted file mode 100644
index cedcb1c0..00000000
--- a/alliance/share/cells/sxlib/na4_x1.vhd
+++ /dev/null
@@ -1,22 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY na4_x1 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  i3	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END na4_x1;
-
-ARCHITECTURE RTL OF na4_x1 IS
-BEGIN
-  nq <= NOT((((i0 AND i1) AND i2) AND i3));
-END RTL;
diff --git a/alliance/share/cells/sxlib/na4_x4.al b/alliance/share/cells/sxlib/na4_x4.al
deleted file mode 100644
index 111fa2f3..00000000
--- a/alliance/share/cells/sxlib/na4_x4.al
+++ /dev/null
@@ -1,48 +0,0 @@
-V ALLIANCE : 6
-H na4_x4,L,30/10/99
-C i0,IN,EXTERNAL,6
-C i1,IN,EXTERNAL,8
-C i2,IN,EXTERNAL,11
-C i3,IN,EXTERNAL,12
-C nq,OUT,EXTERNAL,2
-C vdd,IN,EXTERNAL,5
-C vss,IN,EXTERNAL,3
-T P,0.35,2.9,5,12,7,0,0.75,0.75,7.3,7.3,13.2,11.25,tr_00014
-T P,0.35,2.9,7,11,5,0,0.75,0.75,7.3,7.3,11.4,11.25,tr_00013
-T P,0.35,2.9,5,8,7,0,0.75,0.75,7.3,7.3,9.6,11.25,tr_00012
-T P,0.35,2.9,7,6,5,0,0.75,0.75,7.3,7.3,7.8,11.25,tr_00011
-T P,0.35,5.9,2,4,5,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00010
-T P,0.35,5.9,5,4,2,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00009
-T P,0.35,2.9,5,7,4,0,0.75,0.75,7.3,7.3,1.8,9.75,tr_00008
-T N,0.35,2.9,9,11,10,0,0.75,0.75,7.3,7.3,10.2,2.25,tr_00007
-T N,0.35,2.9,1,8,9,0,0.75,0.75,7.3,7.3,9,2.25,tr_00006
-T N,0.35,2.9,3,6,1,0,0.75,0.75,7.3,7.3,7.8,2.25,tr_00005
-T N,0.35,2.9,10,12,7,0,0.75,0.75,7.3,7.3,11.4,2.25,tr_00004
-T N,0.35,2.9,2,4,3,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00003
-T N,0.35,2.9,3,4,2,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002
-T N,0.35,1.4,4,7,3,0,0.75,0.75,4.3,4.3,1.8,3,tr_00001
-S 12,EXTERNAL,i3
-Q 0.00381484
-S 11,EXTERNAL,i2
-Q 0.00367603
-S 10,INTERNAL
-Q 0
-S 9,INTERNAL
-Q 0
-S 8,EXTERNAL,i1
-Q 0.00345625
-S 7,INTERNAL
-Q 0.00793105
-S 6,EXTERNAL,i0
-Q 0.00323647
-S 5,EXTERNAL,vdd
-Q 0.00557437
-S 4,INTERNAL
-Q 0.00589179
-S 3,EXTERNAL,vss
-Q 0.00504558
-S 2,EXTERNAL,nq
-Q 0.00211518
-S 1,INTERNAL
-Q 0
-EOF
diff --git a/alliance/share/cells/sxlib/na4_x4.ap b/alliance/share/cells/sxlib/na4_x4.ap
deleted file mode 100644
index 8f6b0f1f..00000000
--- a/alliance/share/cells/sxlib/na4_x4.ap
+++ /dev/null
@@ -1,126 +0,0 @@
-V ALLIANCE : 6
-H na4_x4,P,30/ 8/2000,100
-A 0,0,5000,5000
-R 1500,1000,ref_ref,nq_10
-R 1500,3500,ref_ref,nq_35
-R 1500,3000,ref_ref,nq_30
-R 1500,2500,ref_ref,nq_25
-R 1500,2000,ref_ref,nq_20
-R 1500,1500,ref_ref,nq_15
-R 3500,1500,ref_ref,i2_15
-R 3500,1000,ref_ref,i2_10
-R 4000,1000,ref_ref,i3_10
-R 4000,1500,ref_ref,i3_15
-R 4000,2000,ref_ref,i3_20
-R 4000,2500,ref_ref,i3_25
-R 4000,3000,ref_ref,i3_30
-R 4000,3500,ref_ref,i3_35
-R 3000,2000,ref_ref,i1_20
-R 3000,2500,ref_ref,i1_25
-R 3000,3000,ref_ref,i1_30
-R 3000,3500,ref_ref,i1_35
-R 3500,3500,ref_ref,i2_35
-R 3500,3000,ref_ref,i2_30
-R 3500,2500,ref_ref,i2_25
-R 3500,2000,ref_ref,i2_20
-R 2500,1500,ref_ref,i0_15
-R 2500,2000,ref_ref,i0_20
-R 2500,2500,ref_ref,i0_25
-R 2500,3000,ref_ref,i0_30
-R 2500,3500,ref_ref,i0_35
-R 2500,1000,ref_ref,i0_10
-R 3000,1000,ref_ref,i1_10
-R 3000,1500,ref_ref,i1_15
-S 300,3000,300,3500,100,*,DOWN,ALU1
-S 4550,1000,4550,4000,100,*,UP,ALU1
-S 4400,1900,4400,3100,100,*,UP,POLY
-S 0,300,5000,300,600,vss,RIGHT,CALU1
-S 2300,3300,2300,4700,300,*,DOWN,PDIF
-S 0,4700,5000,4700,600,vdd,RIGHT,CALU1
-S 600,1500,800,1500,300,*,RIGHT,POLY
-S 300,1000,300,3000,100,*,DOWN,ALU1
-S 600,2500,800,2500,300,*,RIGHT,POLY
-S 1200,1400,1200,2600,100,*,DOWN,POLY
-S 1800,1400,1800,2600,100,*,DOWN,POLY
-S 2100,2800,2100,4700,300,*,DOWN,PDIF
-S 600,2600,600,3900,100,*,UP,PTRANS
-S 900,2800,900,4700,300,*,DOWN,PDIF
-S 1500,2800,1500,4700,300,*,DOWN,PDIF
-S 1800,2600,1800,4900,100,*,UP,PTRANS
-S 1200,2600,1200,4900,100,*,UP,PTRANS
-S 300,2800,300,3700,300,*,DOWN,PDIF
-S 300,800,300,1200,300,*,UP,NDIF
-S 600,600,600,1400,100,*,DOWN,NTRANS
-S 1200,100,1200,1400,100,*,DOWN,NTRANS
-S 900,300,900,1200,300,*,UP,NDIF
-S 1800,100,1800,1400,100,*,DOWN,NTRANS
-S 1500,300,1500,1200,300,*,UP,NDIF
-S 2100,300,2100,1200,300,*,UP,NDIF
-S 3800,100,3800,1400,100,*,DOWN,NTRANS
-S 4100,300,4100,1200,300,*,DOWN,NDIF
-S 4300,800,4300,1200,700,*,UP,NDIF
-S 2300,300,2300,1200,300,*,DOWN,NDIF
-S 2600,100,2600,1400,100,*,DOWN,NTRANS
-S 3000,100,3000,1400,100,*,DOWN,NTRANS
-S 3400,100,3400,1400,100,*,DOWN,NTRANS
-S 2600,3100,2600,4400,100,*,UP,PTRANS
-S 4700,3300,4700,4600,300,*,DOWN,PDIF
-S 3500,3300,3500,4600,300,*,DOWN,PDIF
-S 4100,3300,4100,4200,300,*,DOWN,PDIF
-S 2900,3300,2900,4200,300,*,DOWN,PDIF
-S 3200,3100,3200,4400,100,*,UP,PTRANS
-S 3800,3100,3800,4400,100,*,UP,PTRANS
-S 4400,3100,4400,4400,100,*,UP,PTRANS
-S 2600,1400,2600,3100,100,*,DOWN,POLY
-S 3000,1400,3000,3100,100,*,UP,POLY
-S 3000,3100,3200,3100,100,*,RIGHT,POLY
-S 3400,1400,3400,2600,100,*,UP,POLY
-S 3400,2600,3800,2600,100,*,RIGHT,POLY
-S 3800,2600,3800,3100,100,*,UP,POLY
-S 3800,1400,3800,1900,100,*,UP,POLY
-S 3800,1900,4400,1900,100,*,RIGHT,POLY
-S 2500,1000,2500,3500,100,*,DOWN,ALU1
-S 3000,1000,3000,3500,100,*,DOWN,ALU1
-S 3500,1000,3500,3500,100,*,DOWN,ALU1
-S 4000,1000,4000,3500,100,*,DOWN,ALU1
-S 0,3900,5000,3900,2400,*,RIGHT,NWELL
-S 1500,1000,1500,3500,200,*,UP,ALU1
-S 1050,1500,1050,4000,100,*,DOWN,ALU1
-S 800,2500,1050,2500,200,*,RIGHT,ALU1
-S 800,1500,1050,1500,200,*,RIGHT,ALU1
-S 600,2000,1800,2000,300,*,RIGHT,POLY
-S 300,2000,600,2000,200,*,LEFT,ALU1
-S 1050,4000,4550,4000,100,*,LEFT,ALU1
-S 1500,1000,1500,3500,200,nq,DOWN,CALU1
-S 3500,1000,3500,3500,200,i2,DOWN,CALU1
-S 4000,1000,4000,3500,200,i3,DOWN,CALU1
-S 3000,1000,3000,3500,200,i1,DOWN,CALU1
-S 2500,1000,2500,3500,200,i0,DOWN,CALU1
-V 300,3500,CONT_DIF_P,*
-V 1500,3000,CONT_DIF_P,*
-V 1500,3500,CONT_DIF_P,*
-V 2200,500,CONT_DIF_N,*
-V 2200,4500,CONT_DIF_P,*
-V 800,1500,CONT_POLY,*
-V 800,2500,CONT_POLY,*
-V 300,300,CONT_BODY_P,*
-V 300,4700,CONT_BODY_N,*
-V 300,3000,CONT_DIF_P,*
-V 900,4500,CONT_DIF_P,*
-V 900,500,CONT_DIF_N,*
-V 300,1000,CONT_DIF_N,*
-V 1500,1000,CONT_DIF_N,*
-V 4500,1000,CONT_DIF_N,*
-V 2900,4000,CONT_DIF_P,*
-V 4100,4000,CONT_DIF_P,*
-V 3500,4500,CONT_DIF_P,*
-V 4700,4500,CONT_DIF_P,*
-V 4100,4700,CONT_BODY_N,*
-V 2900,4700,CONT_BODY_N,*
-V 4700,300,CONT_BODY_P,*
-V 3000,2000,CONT_POLY,*
-V 3500,2500,CONT_POLY,*
-V 4000,2000,CONT_POLY,*
-V 2500,1500,CONT_POLY,*
-V 600,2000,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/sxlib/na4_x4.sym b/alliance/share/cells/sxlib/na4_x4.sym
deleted file mode 100644
index 9b5c878b..00000000
Binary files a/alliance/share/cells/sxlib/na4_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/na4_x4.vbe b/alliance/share/cells/sxlib/na4_x4.vbe
deleted file mode 100644
index a67d1890..00000000
--- a/alliance/share/cells/sxlib/na4_x4.vbe
+++ /dev/null
@@ -1,44 +0,0 @@
-ENTITY na4_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 2500;
-  CONSTANT cin_i0	 : NATURAL := 10;
-  CONSTANT cin_i1	 : NATURAL := 11;
-  CONSTANT cin_i2	 : NATURAL := 11;
-  CONSTANT cin_i3	 : NATURAL := 11;
-  CONSTANT rdown_i0_nq	 : NATURAL := 810;
-  CONSTANT rdown_i1_nq	 : NATURAL := 810;
-  CONSTANT rdown_i2_nq	 : NATURAL := 810;
-  CONSTANT rdown_i3_nq	 : NATURAL := 810;
-  CONSTANT rup_i0_nq	 : NATURAL := 890;
-  CONSTANT rup_i1_nq	 : NATURAL := 890;
-  CONSTANT rup_i2_nq	 : NATURAL := 890;
-  CONSTANT rup_i3_nq	 : NATURAL := 890;
-  CONSTANT tphl_i0_nq	 : NATURAL := 578;
-  CONSTANT tphl_i1_nq	 : NATURAL := 643;
-  CONSTANT tplh_i3_nq	 : NATURAL := 644;
-  CONSTANT tphl_i2_nq	 : NATURAL := 681;
-  CONSTANT tplh_i2_nq	 : NATURAL := 689;
-  CONSTANT tphl_i3_nq	 : NATURAL := 703;
-  CONSTANT tplh_i1_nq	 : NATURAL := 731;
-  CONSTANT tplh_i0_nq	 : NATURAL := 771;
-  CONSTANT transistors	 : NATURAL := 14
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  i3	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END na4_x4;
-
-ARCHITECTURE behaviour_data_flow OF na4_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on na4_x4"
-  SEVERITY WARNING;
-  nq <= not ((((i0 and i1) and i2) and i3)) after 1400 ps;
-END;
diff --git a/alliance/share/cells/sxlib/na4_x4.vhd b/alliance/share/cells/sxlib/na4_x4.vhd
deleted file mode 100644
index 5593da22..00000000
--- a/alliance/share/cells/sxlib/na4_x4.vhd
+++ /dev/null
@@ -1,22 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY na4_x4 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  i3	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END na4_x4;
-
-ARCHITECTURE RTL OF na4_x4 IS
-BEGIN
-  nq <= NOT((((i0 AND i1) AND i2) AND i3));
-END RTL;
diff --git a/alliance/share/cells/sxlib/nao22_x1.al b/alliance/share/cells/sxlib/nao22_x1.al
deleted file mode 100644
index 22bbb6dc..00000000
--- a/alliance/share/cells/sxlib/nao22_x1.al
+++ /dev/null
@@ -1,31 +0,0 @@
-V ALLIANCE : 6
-H nao22_x1,L,30/10/99
-C i0,IN,EXTERNAL,6
-C i1,IN,EXTERNAL,7
-C i2,IN,EXTERNAL,8
-C nq,OUT,EXTERNAL,1
-C vdd,IN,EXTERNAL,4
-C vss,IN,EXTERNAL,3
-T P,0.35,5.9,4,8,1,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00006
-T P,0.35,5.9,5,6,4,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00005
-T P,0.35,5.9,1,7,5,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00004
-T N,0.35,2.9,2,6,1,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00003
-T N,0.35,2.9,1,7,2,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002
-T N,0.35,2.9,2,8,3,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00001
-S 8,EXTERNAL,i2
-Q 0.00344864
-S 7,EXTERNAL,i1
-Q 0.00288494
-S 6,EXTERNAL,i0
-Q 0.00260759
-S 5,INTERNAL
-Q 0
-S 4,EXTERNAL,vdd
-Q 0.00473727
-S 3,EXTERNAL,vss
-Q 0.00432598
-S 2,INTERNAL
-Q 0.00114171
-S 1,EXTERNAL,nq
-Q 0.00282024
-EOF
diff --git a/alliance/share/cells/sxlib/nao22_x1.ap b/alliance/share/cells/sxlib/nao22_x1.ap
deleted file mode 100644
index b99b0e5d..00000000
--- a/alliance/share/cells/sxlib/nao22_x1.ap
+++ /dev/null
@@ -1,77 +0,0 @@
-V ALLIANCE : 6
-H nao22_x1,P,30/ 8/2000,100
-A 0,0,3000,5000
-R 2000,1000,ref_ref,i2_10
-R 2000,4000,ref_ref,i2_40
-R 1500,4000,ref_ref,nq_40
-R 1000,4000,ref_ref,i1_40
-R 1000,3500,ref_ref,i1_35
-R 500,3500,ref_ref,i0_35
-R 500,4000,ref_ref,i0_40
-R 500,2000,ref_ref,i0_20
-R 500,2500,ref_ref,i0_25
-R 500,3000,ref_ref,i0_30
-R 1000,3000,ref_ref,i1_30
-R 1000,2500,ref_ref,i1_25
-R 1000,2000,ref_ref,i1_20
-R 2000,1500,ref_ref,i2_15
-R 2000,2000,ref_ref,i2_20
-R 2000,2500,ref_ref,i2_25
-R 2000,3000,ref_ref,i2_30
-R 2000,3500,ref_ref,i2_35
-R 1500,1500,ref_ref,nq_15
-R 1500,2000,ref_ref,nq_20
-R 1500,2500,ref_ref,nq_25
-R 1500,3000,ref_ref,nq_30
-R 1500,3500,ref_ref,nq_35
-S 500,2000,500,4000,200,i0,DOWN,CALU1
-S 1000,2000,1000,4000,200,i1,DOWN,CALU1
-S 2000,1000,2000,4000,200,i2,DOWN,CALU1
-S 1500,1500,1500,4000,200,nq,DOWN,CALU1
-S 2000,1000,2000,4000,100,*,DOWN,ALU1
-S 2700,500,2700,1700,200,*,DOWN,ALU1
-S 2700,2900,2700,4500,200,*,DOWN,ALU1
-S 0,3900,3000,3900,2400,*,RIGHT,NWELL
-S 0,4700,3000,4700,600,vdd,RIGHT,CALU1
-S 0,300,3000,300,600,vss,RIGHT,CALU1
-S 300,1000,1500,1000,100,*,RIGHT,ALU1
-S 500,2000,500,4000,100,*,UP,ALU1
-S 1000,2000,1000,4000,100,*,DOWN,ALU1
-S 900,300,900,1600,300,*,UP,NDIF
-S 1800,1400,1800,2600,100,*,DOWN,POLY
-S 1200,1400,1200,2600,100,*,DOWN,POLY
-S 600,1400,600,2600,100,*,DOWN,POLY
-S 2100,2800,2100,4700,300,*,DOWN,PDIF
-S 1800,2600,1800,4900,100,*,UP,PTRANS
-S 1500,2800,1500,4700,300,*,DOWN,PDIF
-S 300,2800,300,4700,300,*,DOWN,PDIF
-S 600,2600,600,4900,100,*,UP,PTRANS
-S 900,2800,900,4700,300,*,DOWN,PDIF
-S 1200,2600,1200,4900,100,*,UP,PTRANS
-S 600,100,600,1400,100,*,DOWN,NTRANS
-S 300,300,300,1200,300,*,UP,NDIF
-S 1200,100,1200,1400,100,*,DOWN,NTRANS
-S 1500,300,1500,1200,300,*,UP,NDIF
-S 1800,100,1800,1400,100,*,DOWN,NTRANS
-S 2100,300,2100,1200,300,*,UP,NDIF
-S 1800,2000,2000,2000,300,*,RIGHT,POLY
-S 1000,2000,1200,2000,300,*,RIGHT,POLY
-S 1500,1450,1500,4000,200,*,UP,ALU1
-S 900,1500,1550,1500,200,*,RIGHT,ALU1
-V 2700,300,CONT_BODY_P,*
-V 2700,4700,CONT_BODY_N,*
-V 2700,2900,CONT_BODY_N,*
-V 2700,1700,CONT_BODY_P,*
-V 2100,4500,CONT_DIF_P,*
-V 1500,3000,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 1500,3500,CONT_DIF_P,*
-V 900,1500,CONT_DIF_N,*
-V 300,4500,CONT_DIF_P,*
-V 2100,500,CONT_DIF_N,*
-V 1500,1000,CONT_DIF_N,*
-V 300,1000,CONT_DIF_N,*
-V 2000,2000,CONT_POLY,*
-V 1000,2000,CONT_POLY,*
-V 500,2000,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/sxlib/nao22_x1.sym b/alliance/share/cells/sxlib/nao22_x1.sym
deleted file mode 100644
index 865b45a3..00000000
Binary files a/alliance/share/cells/sxlib/nao22_x1.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/nao22_x1.vbe b/alliance/share/cells/sxlib/nao22_x1.vbe
deleted file mode 100644
index 13c4e6de..00000000
--- a/alliance/share/cells/sxlib/nao22_x1.vbe
+++ /dev/null
@@ -1,38 +0,0 @@
-ENTITY nao22_x1 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 1500;
-  CONSTANT cin_i0	 : NATURAL := 14;
-  CONSTANT cin_i1	 : NATURAL := 14;
-  CONSTANT cin_i2	 : NATURAL := 15;
-  CONSTANT rdown_i0_nq	 : NATURAL := 2850;
-  CONSTANT rdown_i1_nq	 : NATURAL := 2850;
-  CONSTANT rdown_i2_nq	 : NATURAL := 2850;
-  CONSTANT rup_i0_nq	 : NATURAL := 3210;
-  CONSTANT rup_i1_nq	 : NATURAL := 3210;
-  CONSTANT rup_i2_nq	 : NATURAL := 1790;
-  CONSTANT tphl_i2_nq	 : NATURAL := 165;
-  CONSTANT tphl_i1_nq	 : NATURAL := 218;
-  CONSTANT tplh_i0_nq	 : NATURAL := 226;
-  CONSTANT tplh_i2_nq	 : NATURAL := 238;
-  CONSTANT tplh_i1_nq	 : NATURAL := 287;
-  CONSTANT tphl_i0_nq	 : NATURAL := 294;
-  CONSTANT transistors	 : NATURAL := 6
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END nao22_x1;
-
-ARCHITECTURE behaviour_data_flow OF nao22_x1 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on nao22_x1"
-  SEVERITY WARNING;
-  nq <= not (((i0 or i1) and i2)) after 900 ps;
-END;
diff --git a/alliance/share/cells/sxlib/nao22_x1.vhd b/alliance/share/cells/sxlib/nao22_x1.vhd
deleted file mode 100644
index 7873413c..00000000
--- a/alliance/share/cells/sxlib/nao22_x1.vhd
+++ /dev/null
@@ -1,21 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY nao22_x1 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END nao22_x1;
-
-ARCHITECTURE RTL OF nao22_x1 IS
-BEGIN
-  nq <= NOT(((i0 OR i1) AND i2));
-END RTL;
diff --git a/alliance/share/cells/sxlib/nao22_x4.al b/alliance/share/cells/sxlib/nao22_x4.al
deleted file mode 100644
index 1be1c88a..00000000
--- a/alliance/share/cells/sxlib/nao22_x4.al
+++ /dev/null
@@ -1,41 +0,0 @@
-V ALLIANCE : 6
-H nao22_x4,L,30/10/99
-C i0,IN,EXTERNAL,7
-C i1,IN,EXTERNAL,6
-C i2,IN,EXTERNAL,5
-C nq,OUT,EXTERNAL,8
-C vdd,IN,EXTERNAL,9
-C vss,IN,EXTERNAL,4
-T P,0.35,2.9,10,6,3,0,0.75,0.75,7.3,7.3,3.9,11.25,tr_00012
-T P,0.35,2.9,9,7,10,0,0.75,0.75,7.3,7.3,5.7,11.25,tr_00011
-T P,0.35,2.9,3,5,9,0,0.75,0.75,7.3,7.3,2.1,11.25,tr_00010
-T P,0.35,2.9,9,3,2,0,0.75,0.75,7.3,7.3,9.3,9.75,tr_00009
-T P,0.35,5.9,9,2,8,0,0.75,0.75,13.3,13.3,12.9,11.25,tr_00008
-T P,0.35,5.9,8,2,9,0,0.75,0.75,13.3,13.3,11.1,11.25,tr_00007
-T N,0.35,1.4,4,5,1,0,0.75,0.75,4.3,4.3,2.1,3,tr_00006
-T N,0.35,2.9,4,2,8,0,0.75,0.75,7.3,7.3,11.1,2.25,tr_00005
-T N,0.35,1.4,1,6,3,0,0.75,0.75,4.3,4.3,3.9,3,tr_00004
-T N,0.35,1.4,3,7,1,0,0.75,0.75,4.3,4.3,5.7,3,tr_00003
-T N,0.35,1.4,2,3,4,0,0.75,0.75,4.3,4.3,9.3,3,tr_00002
-T N,0.35,2.9,8,2,4,0,0.75,0.75,7.3,7.3,12.9,2.25,tr_00001
-S 10,INTERNAL
-Q 0
-S 9,EXTERNAL,vdd
-Q 0.00768955
-S 8,EXTERNAL,nq
-Q 0.00258522
-S 7,EXTERNAL,i0
-Q 0.00358899
-S 6,EXTERNAL,i1
-Q 0.00295012
-S 5,EXTERNAL,i2
-Q 0.00379567
-S 4,EXTERNAL,vss
-Q 0.00616192
-S 3,INTERNAL
-Q 0.0066832
-S 2,INTERNAL
-Q 0.00580421
-S 1,INTERNAL
-Q 0.00114171
-EOF
diff --git a/alliance/share/cells/sxlib/nao22_x4.ap b/alliance/share/cells/sxlib/nao22_x4.ap
deleted file mode 100644
index 72b06b7a..00000000
--- a/alliance/share/cells/sxlib/nao22_x4.ap
+++ /dev/null
@@ -1,129 +0,0 @@
-V ALLIANCE : 6
-H nao22_x4,P,30/ 8/2000,100
-A 0,0,5000,5000
-R 500,1000,ref_ref,i2_10
-R 500,1500,ref_ref,i2_15
-R 500,2500,ref_ref,i2_25
-R 500,3000,ref_ref,i2_30
-R 4000,3500,ref_ref,nq_35
-R 4000,3000,ref_ref,nq_30
-R 4000,2000,ref_ref,nq_20
-R 4000,1000,ref_ref,nq_10
-R 4000,1500,ref_ref,nq_15
-R 4000,2500,ref_ref,nq_25
-R 2000,2000,ref_ref,i0_20
-R 2000,2500,ref_ref,i0_25
-R 2000,3000,ref_ref,i0_30
-R 1500,3000,ref_ref,i1_30
-R 1500,2500,ref_ref,i1_25
-R 1500,2000,ref_ref,i1_20
-R 500,2000,ref_ref,i2_20
-R 2000,3500,ref_ref,i0_35
-R 1500,3500,ref_ref,i1_35
-R 500,3500,ref_ref,i2_35
-R 500,4000,ref_ref,i2_40
-R 4000,4000,ref_ref,nq_40
-R 2500,1500,ref_ref,i0_15
-S 2000,2000,2400,2000,200,*,RIGHT,ALU1
-S 500,1000,500,4000,100,*,DOWN,ALU1
-S 2000,2000,2000,3500,100,*,DOWN,ALU1
-S 1000,1500,1600,1500,100,*,RIGHT,ALU1
-S 1500,2000,1500,3500,100,*,DOWN,ALU1
-S 1600,800,1600,1600,300,*,UP,NDIF
-S 400,400,400,1200,300,*,UP,NDIF
-S 4600,500,4600,1000,200,*,DOWN,ALU1
-S 4600,3000,4600,4500,200,*,DOWN,ALU1
-S 3400,4000,3400,4500,200,*,DOWN,ALU1
-S 2800,2000,3500,2000,100,*,RIGHT,ALU1
-S 3300,2500,3300,3500,100,*,DOWN,ALU1
-S 4000,1000,4000,4000,200,*,UP,ALU1
-S 1100,4000,2800,4000,100,*,LEFT,ALU1
-S 2800,3500,2800,4000,100,*,UP,ALU1
-S 2800,3500,3300,3500,100,*,LEFT,ALU1
-S 1000,1500,1000,4000,100,*,UP,ALU1
-S 0,4700,5000,4700,600,vdd,RIGHT,CALU1
-S 1000,1000,2200,1000,100,*,RIGHT,ALU1
-S 0,300,5000,300,600,vss,RIGHT,CALU1
-S 500,2000,700,2000,300,*,RIGHT,POLY
-S 1300,2000,1500,2000,300,*,RIGHT,POLY
-S 3500,2000,4300,2000,300,*,RIGHT,POLY
-S 3100,2500,3300,2500,300,*,RIGHT,POLY
-S 4300,1400,4300,2600,100,*,DOWN,POLY
-S 3700,1400,3700,2600,100,*,DOWN,POLY
-S 3100,1400,3100,2600,100,*,DOWN,POLY
-S 700,1400,700,3100,100,*,DOWN,POLY
-S 1300,1400,1300,3100,100,*,DOWN,POLY
-S 1900,1400,1900,3100,100,*,DOWN,POLY
-S 4300,100,4300,1400,100,*,DOWN,NTRANS
-S 3400,300,3400,1200,300,*,UP,NDIF
-S 4000,300,4000,1200,300,*,UP,NDIF
-S 4600,300,4600,1200,300,*,UP,NDIF
-S 3100,600,3100,1400,100,*,DOWN,NTRANS
-S 2800,800,2800,1200,300,*,UP,NDIF
-S 1900,600,1900,1400,100,*,DOWN,NTRANS
-S 1300,600,1300,1400,100,*,DOWN,NTRANS
-S 1000,800,1000,1200,300,*,UP,NDIF
-S 3700,100,3700,1400,100,*,DOWN,NTRANS
-S 2200,800,2200,1200,300,*,UP,NDIF
-S 700,600,700,1400,100,*,DOWN,NTRANS
-S 1000,3300,1000,4200,300,*,DOWN,PDIF
-S 3700,2600,3700,4900,100,*,UP,PTRANS
-S 4300,2600,4300,4900,100,*,UP,PTRANS
-S 4000,2800,4000,4700,300,*,DOWN,PDIF
-S 3400,2800,3400,4700,300,*,DOWN,PDIF
-S 4600,2800,4600,4700,300,*,DOWN,PDIF
-S 3100,2600,3100,3900,100,*,UP,PTRANS
-S 2800,2800,2800,3700,300,*,DOWN,PDIF
-S 0,3900,5000,3900,2400,*,RIGHT,NWELL
-S 400,3300,400,4600,300,*,DOWN,PDIF
-S 1600,3300,1600,4200,300,*,DOWN,PDIF
-S 2200,3300,2200,4600,300,*,DOWN,PDIF
-S 700,3100,700,4400,100,*,UP,PTRANS
-S 1900,3100,1900,4400,100,*,UP,PTRANS
-S 1300,3100,1300,4400,100,*,UP,PTRANS
-S 2400,1500,2400,2000,100,*,DOWN,ALU1
-S 2400,1500,2500,1500,100,*,RIGHT,ALU1
-S 3500,1000,3500,2000,100,*,DOWN,ALU1
-S 2800,1000,3500,1000,100,*,LEFT,ALU1
-S 2800,2000,2800,3000,100,*,UP,ALU1
-S 500,1000,500,4000,200,i2,DOWN,CALU1
-S 4000,1000,4000,4000,200,nq,DOWN,CALU1
-S 1500,2000,1500,3500,200,i1,DOWN,CALU1
-S 2000,2000,2000,3500,200,i0,DOWN,CALU1
-S 2500,1500,2500,1500,200,i0,LEFT,CALU1
-V 1600,1500,CONT_DIF_N,*
-V 400,500,CONT_DIF_N,*
-V 1600,300,CONT_BODY_P,*
-V 500,2000,CONT_POLY,*
-V 1500,2000,CONT_POLY,*
-V 3500,2000,CONT_POLY,*
-V 3300,2500,CONT_POLY,*
-V 2000,2000,CONT_POLY,*
-V 2200,300,CONT_BODY_P,*
-V 1000,300,CONT_BODY_P,*
-V 2800,300,CONT_BODY_P,*
-V 2800,1000,CONT_DIF_N,*
-V 3400,500,CONT_DIF_N,*
-V 4600,500,CONT_DIF_N,*
-V 4000,1000,CONT_DIF_N,*
-V 1000,1000,CONT_DIF_N,*
-V 2200,1000,CONT_DIF_N,*
-V 4600,1000,CONT_DIF_N,*
-V 3400,4000,CONT_DIF_P,*
-V 1000,4700,CONT_BODY_N,*
-V 2800,4700,CONT_BODY_N,*
-V 2800,3000,CONT_DIF_P,*
-V 4600,3000,CONT_DIF_P,*
-V 4600,3500,CONT_DIF_P,*
-V 4600,4000,CONT_DIF_P,*
-V 4600,4500,CONT_DIF_P,*
-V 3400,4500,CONT_DIF_P,*
-V 400,4500,CONT_DIF_P,*
-V 1600,4700,CONT_BODY_N,*
-V 1000,3500,CONT_DIF_P,*
-V 1000,4000,CONT_DIF_P,*
-V 2200,4500,CONT_DIF_P,*
-V 4000,3000,CONT_DIF_P,*
-V 4000,3500,CONT_DIF_P,*
-V 4000,4000,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/nao22_x4.sym b/alliance/share/cells/sxlib/nao22_x4.sym
deleted file mode 100644
index a7c777bd..00000000
Binary files a/alliance/share/cells/sxlib/nao22_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/nao22_x4.vbe b/alliance/share/cells/sxlib/nao22_x4.vbe
deleted file mode 100644
index ebdcfc51..00000000
--- a/alliance/share/cells/sxlib/nao22_x4.vbe
+++ /dev/null
@@ -1,38 +0,0 @@
-ENTITY nao22_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 2500;
-  CONSTANT cin_i0	 : NATURAL := 9;
-  CONSTANT cin_i1	 : NATURAL := 8;
-  CONSTANT cin_i2	 : NATURAL := 9;
-  CONSTANT rdown_i0_nq	 : NATURAL := 810;
-  CONSTANT rdown_i1_nq	 : NATURAL := 810;
-  CONSTANT rdown_i2_nq	 : NATURAL := 810;
-  CONSTANT rup_i0_nq	 : NATURAL := 890;
-  CONSTANT rup_i1_nq	 : NATURAL := 890;
-  CONSTANT rup_i2_nq	 : NATURAL := 890;
-  CONSTANT tphl_i2_nq	 : NATURAL := 596;
-  CONSTANT tplh_i2_nq	 : NATURAL := 636;
-  CONSTANT tplh_i0_nq	 : NATURAL := 650;
-  CONSTANT tphl_i1_nq	 : NATURAL := 664;
-  CONSTANT tplh_i1_nq	 : NATURAL := 723;
-  CONSTANT tphl_i0_nq	 : NATURAL := 732;
-  CONSTANT transistors	 : NATURAL := 12
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END nao22_x4;
-
-ARCHITECTURE behaviour_data_flow OF nao22_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on nao22_x4"
-  SEVERITY WARNING;
-  nq <= not (((i0 or i1) and i2)) after 1300 ps;
-END;
diff --git a/alliance/share/cells/sxlib/nao22_x4.vhd b/alliance/share/cells/sxlib/nao22_x4.vhd
deleted file mode 100644
index e45a87a3..00000000
--- a/alliance/share/cells/sxlib/nao22_x4.vhd
+++ /dev/null
@@ -1,21 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY nao22_x4 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END nao22_x4;
-
-ARCHITECTURE RTL OF nao22_x4 IS
-BEGIN
-  nq <= NOT(((i0 OR i1) AND i2));
-END RTL;
diff --git a/alliance/share/cells/sxlib/nao2o22_x1.al b/alliance/share/cells/sxlib/nao2o22_x1.al
deleted file mode 100644
index ebf99d47..00000000
--- a/alliance/share/cells/sxlib/nao2o22_x1.al
+++ /dev/null
@@ -1,38 +0,0 @@
-V ALLIANCE : 6
-H nao2o22_x1,L,30/10/99
-C i0,IN,EXTERNAL,10
-C i1,IN,EXTERNAL,8
-C i2,IN,EXTERNAL,9
-C i3,IN,EXTERNAL,7
-C nq,OUT,EXTERNAL,2
-C vdd,IN,EXTERNAL,4
-C vss,IN,EXTERNAL,3
-T P,0.35,5.9,2,8,5,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00008
-T P,0.35,5.9,5,10,4,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00007
-T P,0.35,5.9,6,7,2,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00006
-T P,0.35,5.9,4,9,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00005
-T N,0.35,2.9,3,9,1,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00004
-T N,0.35,2.9,1,7,3,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00003
-T N,0.35,2.9,2,8,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002
-T N,0.35,2.9,1,10,2,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00001
-S 10,EXTERNAL,i0
-Q 0.00260759
-S 9,EXTERNAL,i2
-Q 0.00288944
-S 8,EXTERNAL,i1
-Q 0.00288494
-S 7,EXTERNAL,i3
-Q 0.00316679
-S 6,INTERNAL
-Q 0
-S 5,INTERNAL
-Q 0
-S 4,EXTERNAL,vdd
-Q 0.00490248
-S 3,EXTERNAL,vss
-Q 0.00449119
-S 2,EXTERNAL,nq
-Q 0.00282024
-S 1,INTERNAL
-Q 0.00199441
-EOF
diff --git a/alliance/share/cells/sxlib/nao2o22_x1.ap b/alliance/share/cells/sxlib/nao2o22_x1.ap
deleted file mode 100644
index a1ae005a..00000000
--- a/alliance/share/cells/sxlib/nao2o22_x1.ap
+++ /dev/null
@@ -1,90 +0,0 @@
-V ALLIANCE : 6
-H nao2o22_x1,P,30/ 8/2000,100
-A 0,0,3500,5000
-R 1500,3500,ref_ref,nq_35
-R 1500,3000,ref_ref,nq_30
-R 1500,2500,ref_ref,nq_25
-R 1500,2000,ref_ref,nq_20
-R 1500,1500,ref_ref,nq_15
-R 2500,1500,ref_ref,i2_15
-R 2500,2000,ref_ref,i2_20
-R 2500,2500,ref_ref,i2_25
-R 2500,3000,ref_ref,i2_30
-R 2500,3500,ref_ref,i2_35
-R 2000,3500,ref_ref,i3_35
-R 2000,3000,ref_ref,i3_30
-R 2000,2500,ref_ref,i3_25
-R 2000,2000,ref_ref,i3_20
-R 2000,1500,ref_ref,i3_15
-R 1000,2000,ref_ref,i1_20
-R 1000,2500,ref_ref,i1_25
-R 1000,3000,ref_ref,i1_30
-R 500,3000,ref_ref,i0_30
-R 500,2500,ref_ref,i0_25
-R 500,2000,ref_ref,i0_20
-R 500,4000,ref_ref,i0_40
-R 500,3500,ref_ref,i0_35
-R 1000,3500,ref_ref,i1_35
-R 1000,4000,ref_ref,i1_40
-R 1500,4000,ref_ref,nq_40
-R 2000,4000,ref_ref,i3_40
-R 2500,4000,ref_ref,i2_40
-S 500,2000,500,4000,200,i0,DOWN,CALU1
-S 1000,2000,1000,4000,200,i1,DOWN,CALU1
-S 1500,1500,1500,4000,200,nq,DOWN,CALU1
-S 2000,1500,2000,4000,200,i3,DOWN,CALU1
-S 2500,1500,2500,4000,200,i2,DOWN,CALU1
-S 0,3900,3500,3900,2400,*,RIGHT,NWELL
-S 3200,500,3200,1700,200,*,DOWN,ALU1
-S 3200,2900,3200,4500,200,*,DOWN,ALU1
-S 2700,3400,2700,4700,300,*,DOWN,PDIF
-S 2700,300,2700,1200,300,*,UP,NDIF
-S 0,4700,3500,4700,600,vdd,RIGHT,CALU1
-S 0,300,3500,300,600,vss,RIGHT,CALU1
-S 1000,2000,1200,2000,300,*,RIGHT,POLY
-S 1800,2000,2000,2000,300,*,RIGHT,POLY
-S 2400,100,2400,1400,100,*,DOWN,NTRANS
-S 2100,300,2100,1200,300,*,UP,NDIF
-S 1800,100,1800,1400,100,*,DOWN,NTRANS
-S 1500,300,1500,1200,300,*,UP,NDIF
-S 1200,100,1200,1400,100,*,DOWN,NTRANS
-S 300,300,300,1200,300,*,UP,NDIF
-S 600,100,600,1400,100,*,DOWN,NTRANS
-S 1200,2600,1200,4900,100,*,UP,PTRANS
-S 900,2800,900,4700,300,*,DOWN,PDIF
-S 600,2600,600,4900,100,*,UP,PTRANS
-S 300,2800,300,4700,300,*,DOWN,PDIF
-S 1500,2800,1500,4700,300,*,DOWN,PDIF
-S 1800,2600,1800,4900,100,*,UP,PTRANS
-S 2100,2800,2100,4700,300,*,DOWN,PDIF
-S 2400,2600,2400,4900,100,*,UP,PTRANS
-S 600,1400,600,2600,100,*,DOWN,POLY
-S 1200,1400,1200,2600,100,*,DOWN,POLY
-S 1800,1400,1800,2600,100,*,DOWN,POLY
-S 2400,1400,2400,2600,100,*,DOWN,POLY
-S 900,300,900,1600,300,*,UP,NDIF
-S 1000,2000,1000,4000,100,*,DOWN,ALU1
-S 500,2000,500,4000,100,*,UP,ALU1
-S 300,1000,2700,1000,100,*,RIGHT,ALU1
-S 2000,1500,2000,4000,100,*,DOWN,ALU1
-S 2500,1500,2500,4000,100,*,DOWN,ALU1
-S 2600,2800,2600,3300,300,*,UP,PDIF
-S 1500,1450,1500,4000,200,*,UP,ALU1
-S 900,1500,1550,1500,200,*,RIGHT,ALU1
-V 3200,2900,CONT_BODY_N,*
-V 3200,1700,CONT_BODY_P,*
-V 500,2000,CONT_POLY,*
-V 2500,2000,CONT_POLY,*
-V 1000,2000,CONT_POLY,*
-V 2000,2000,CONT_POLY,*
-V 300,1000,CONT_DIF_N,*
-V 2700,1000,CONT_DIF_N,*
-V 1500,1000,CONT_DIF_N,*
-V 2100,500,CONT_DIF_N,*
-V 2700,4500,CONT_DIF_P,*
-V 300,4500,CONT_DIF_P,*
-V 900,1500,CONT_DIF_N,*
-V 1500,3500,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 1500,3000,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/nao2o22_x1.sym b/alliance/share/cells/sxlib/nao2o22_x1.sym
deleted file mode 100644
index 7030a68e..00000000
Binary files a/alliance/share/cells/sxlib/nao2o22_x1.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/nao2o22_x1.vbe b/alliance/share/cells/sxlib/nao2o22_x1.vbe
deleted file mode 100644
index 327e9976..00000000
--- a/alliance/share/cells/sxlib/nao2o22_x1.vbe
+++ /dev/null
@@ -1,44 +0,0 @@
-ENTITY nao2o22_x1 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 1750;
-  CONSTANT cin_i0	 : NATURAL := 14;
-  CONSTANT cin_i1	 : NATURAL := 14;
-  CONSTANT cin_i2	 : NATURAL := 14;
-  CONSTANT cin_i3	 : NATURAL := 14;
-  CONSTANT rdown_i0_nq	 : NATURAL := 2850;
-  CONSTANT rdown_i1_nq	 : NATURAL := 2850;
-  CONSTANT rdown_i2_nq	 : NATURAL := 2850;
-  CONSTANT rdown_i3_nq	 : NATURAL := 2850;
-  CONSTANT rup_i0_nq	 : NATURAL := 3210;
-  CONSTANT rup_i1_nq	 : NATURAL := 3210;
-  CONSTANT rup_i2_nq	 : NATURAL := 3210;
-  CONSTANT rup_i3_nq	 : NATURAL := 3210;
-  CONSTANT tphl_i3_nq	 : NATURAL := 174;
-  CONSTANT tphl_i1_nq	 : NATURAL := 218;
-  CONSTANT tplh_i0_nq	 : NATURAL := 226;
-  CONSTANT tphl_i2_nq	 : NATURAL := 237;
-  CONSTANT tplh_i1_nq	 : NATURAL := 287;
-  CONSTANT tphl_i0_nq	 : NATURAL := 294;
-  CONSTANT tplh_i2_nq	 : NATURAL := 307;
-  CONSTANT tplh_i3_nq	 : NATURAL := 382;
-  CONSTANT transistors	 : NATURAL := 8
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  i3	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END nao2o22_x1;
-
-ARCHITECTURE behaviour_data_flow OF nao2o22_x1 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on nao2o22_x1"
-  SEVERITY WARNING;
-  nq <= not (((i0 or i1) and (i2 or i3))) after 1000 ps;
-END;
diff --git a/alliance/share/cells/sxlib/nao2o22_x1.vhd b/alliance/share/cells/sxlib/nao2o22_x1.vhd
deleted file mode 100644
index 9ddd0b03..00000000
--- a/alliance/share/cells/sxlib/nao2o22_x1.vhd
+++ /dev/null
@@ -1,22 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY nao2o22_x1 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  i3	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END nao2o22_x1;
-
-ARCHITECTURE RTL OF nao2o22_x1 IS
-BEGIN
-  nq <= NOT(((i0 OR i1) AND (i2 OR i3)));
-END RTL;
diff --git a/alliance/share/cells/sxlib/nao2o22_x4.al b/alliance/share/cells/sxlib/nao2o22_x4.al
deleted file mode 100644
index ff51e2b9..00000000
--- a/alliance/share/cells/sxlib/nao2o22_x4.al
+++ /dev/null
@@ -1,48 +0,0 @@
-V ALLIANCE : 6
-H nao2o22_x4,L,30/10/99
-C i0,IN,EXTERNAL,6
-C i1,IN,EXTERNAL,4
-C i2,IN,EXTERNAL,7
-C i3,IN,EXTERNAL,5
-C nq,OUT,EXTERNAL,8
-C vdd,IN,EXTERNAL,10
-C vss,IN,EXTERNAL,1
-T P,0.35,2.9,10,3,9,0,0.75,0.75,7.3,7.3,10.8,9.75,tr_00014
-T P,0.35,5.9,10,9,8,0,0.75,0.75,13.3,13.3,14.4,11.25,tr_00013
-T P,0.35,5.9,8,9,10,0,0.75,0.75,13.3,13.3,12.6,11.25,tr_00012
-T P,0.35,2.9,11,6,10,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00011
-T P,0.35,2.9,12,5,3,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00010
-T P,0.35,2.9,10,7,12,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00009
-T P,0.35,2.9,3,4,11,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00008
-T N,0.35,1.4,9,3,1,0,0.75,0.75,4.3,4.3,10.8,3,tr_00007
-T N,0.35,2.9,8,9,1,0,0.75,0.75,7.3,7.3,14.4,2.25,tr_00006
-T N,0.35,2.9,1,9,8,0,0.75,0.75,7.3,7.3,12.6,2.25,tr_00005
-T N,0.35,1.4,2,5,1,0,0.75,0.75,4.3,4.3,5.4,3,tr_00004
-T N,0.35,1.4,1,7,2,0,0.75,0.75,4.3,4.3,7.2,3,tr_00003
-T N,0.35,1.4,2,6,3,0,0.75,0.75,4.3,4.3,1.8,3,tr_00002
-T N,0.35,1.4,3,4,2,0,0.75,0.75,4.3,4.3,3.6,3,tr_00001
-S 12,INTERNAL
-Q 0
-S 11,INTERNAL
-Q 0
-S 10,EXTERNAL,vdd
-Q 0.00820729
-S 9,INTERNAL
-Q 0.00518414
-S 8,EXTERNAL,nq
-Q 0.00258522
-S 7,EXTERNAL,i2
-Q 0.00295462
-S 6,EXTERNAL,i0
-Q 0.00295462
-S 5,EXTERNAL,i3
-Q 0.00323197
-S 4,EXTERNAL,i1
-Q 0.00323197
-S 3,INTERNAL
-Q 0.0066832
-S 2,INTERNAL
-Q 0.00199441
-S 1,EXTERNAL,vss
-Q 0.00726721
-EOF
diff --git a/alliance/share/cells/sxlib/nao2o22_x4.ap b/alliance/share/cells/sxlib/nao2o22_x4.ap
deleted file mode 100644
index 7a8c7082..00000000
--- a/alliance/share/cells/sxlib/nao2o22_x4.ap
+++ /dev/null
@@ -1,143 +0,0 @@
-V ALLIANCE : 6
-H nao2o22_x4,P,30/ 8/2000,100
-A 0,0,5500,5000
-R 4500,2500,ref_ref,nq_25
-R 4500,1500,ref_ref,nq_15
-R 4500,1000,ref_ref,nq_10
-R 4500,2000,ref_ref,nq_20
-R 4500,3000,ref_ref,nq_30
-R 4500,3500,ref_ref,nq_35
-R 500,2000,ref_ref,i0_20
-R 500,2500,ref_ref,i0_25
-R 500,3000,ref_ref,i0_30
-R 1000,3000,ref_ref,i1_30
-R 1000,2500,ref_ref,i1_25
-R 1000,2000,ref_ref,i1_20
-R 2000,1500,ref_ref,i3_15
-R 2000,2000,ref_ref,i3_20
-R 2000,2500,ref_ref,i3_25
-R 2000,3000,ref_ref,i3_30
-R 2500,3000,ref_ref,i2_30
-R 2500,2500,ref_ref,i2_25
-R 2500,2000,ref_ref,i2_20
-R 2500,1500,ref_ref,i2_15
-R 4500,4000,ref_ref,nq_40
-R 500,3500,ref_ref,i0_35
-R 500,4000,ref_ref,i0_40
-R 1000,4000,ref_ref,i1_40
-R 1000,3500,ref_ref,i1_35
-R 2000,3500,ref_ref,i3_35
-R 2500,3500,ref_ref,i2_35
-S 4500,1000,4500,4000,200,nq,DOWN,CALU1
-S 500,2000,500,4000,200,i0,DOWN,CALU1
-S 1000,2000,1000,4000,200,i1,DOWN,CALU1
-S 2000,1500,2000,3500,200,i3,DOWN,CALU1
-S 2500,1500,2500,3500,200,i2,DOWN,CALU1
-S 4500,1000,4500,4000,200,*,UP,ALU1
-S 0,3900,5500,3900,2400,*,RIGHT,NWELL
-S 3300,1000,3300,3000,100,*,DOWN,ALU1
-S 3300,800,3300,1200,300,*,UP,NDIF
-S 3300,2800,3300,3700,300,*,DOWN,PDIF
-S 3600,2600,3600,3900,100,*,UP,PTRANS
-S 5100,2800,5100,4700,300,*,DOWN,PDIF
-S 3900,2800,3900,4700,300,*,DOWN,PDIF
-S 4500,2800,4500,4700,300,*,DOWN,PDIF
-S 4800,2600,4800,4900,100,*,UP,PTRANS
-S 4200,2600,4200,4900,100,*,UP,PTRANS
-S 3600,600,3600,1400,100,*,DOWN,NTRANS
-S 5100,300,5100,1200,300,*,UP,NDIF
-S 4500,300,4500,1200,300,*,UP,NDIF
-S 3900,300,3900,1200,300,*,UP,NDIF
-S 4800,100,4800,1400,100,*,DOWN,NTRANS
-S 4200,100,4200,1400,100,*,DOWN,NTRANS
-S 0,4700,5500,4700,600,vdd,RIGHT,CALU1
-S 0,300,5500,300,600,vss,RIGHT,CALU1
-S 1800,2000,2000,2000,300,*,RIGHT,POLY
-S 1000,2000,1200,2000,300,*,RIGHT,POLY
-S 3800,2500,3800,3500,100,*,DOWN,ALU1
-S 3600,1400,3600,2600,100,*,DOWN,POLY
-S 4200,1400,4200,2600,100,*,DOWN,POLY
-S 4800,1400,4800,2600,100,*,DOWN,POLY
-S 3300,2000,4000,2000,100,*,RIGHT,ALU1
-S 3600,2500,3800,2500,300,*,RIGHT,POLY
-S 3900,4000,3900,4500,200,*,DOWN,ALU1
-S 5100,3000,5100,4500,200,*,DOWN,ALU1
-S 5100,500,5100,1000,200,*,DOWN,ALU1
-S 3900,500,3900,1000,200,*,DOWN,ALU1
-S 4000,2000,4800,2000,300,*,RIGHT,POLY
-S 900,3300,900,4200,300,*,DOWN,PDIF
-S 600,3100,600,4400,100,*,UP,PTRANS
-S 1500,3300,1500,4200,300,*,DOWN,PDIF
-S 1800,3100,1800,4400,100,*,UP,PTRANS
-S 2400,3100,2400,4400,100,*,UP,PTRANS
-S 1200,3100,1200,4400,100,*,UP,PTRANS
-S 1500,800,1500,1200,300,*,UP,NDIF
-S 1800,600,1800,1400,100,*,DOWN,NTRANS
-S 2400,600,2400,1400,100,*,DOWN,NTRANS
-S 600,600,600,1400,100,*,DOWN,NTRANS
-S 1200,600,1200,1400,100,*,DOWN,NTRANS
-S 2400,1400,2400,3100,100,*,DOWN,POLY
-S 1800,1400,1800,3100,100,*,DOWN,POLY
-S 1200,1400,1200,3100,100,*,DOWN,POLY
-S 600,1400,600,3100,100,*,DOWN,POLY
-S 2700,3300,2700,4600,300,*,DOWN,PDIF
-S 300,3300,300,4600,300,*,DOWN,PDIF
-S 2100,3300,2100,4200,300,*,DOWN,PDIF
-S 2100,400,2100,1200,300,*,UP,NDIF
-S 2700,800,2700,1200,300,*,UP,NDIF
-S 1500,1500,1500,4000,100,*,UP,ALU1
-S 300,1000,2700,1000,100,*,RIGHT,ALU1
-S 900,800,900,1600,300,*,UP,NDIF
-S 1000,2000,1000,4000,100,*,DOWN,ALU1
-S 500,2000,500,4000,100,*,UP,ALU1
-S 900,1500,1500,1500,100,*,RIGHT,ALU1
-S 2000,1500,2000,3500,100,*,DOWN,ALU1
-S 2500,1500,2500,3500,100,*,DOWN,ALU1
-S 3300,3500,3800,3500,100,*,LEFT,ALU1
-S 3300,3500,3300,4000,100,*,UP,ALU1
-S 1600,4000,3300,4000,100,*,LEFT,ALU1
-S 300,800,300,1200,300,*,UP,NDIF
-S 900,4700,2100,4700,300,*,RIGHT,NTIE
-S 300,300,1500,300,300,*,RIGHT,PTIE
-S 2700,300,3300,300,300,*,RIGHT,PTIE
-V 4500,1000,CONT_DIF_N,*
-V 3300,300,CONT_BODY_P,*
-V 5100,500,CONT_DIF_N,*
-V 3900,500,CONT_DIF_N,*
-V 2000,2000,CONT_POLY,*
-V 1000,2000,CONT_POLY,*
-V 2500,2000,CONT_POLY,*
-V 500,2000,CONT_POLY,*
-V 3800,2500,CONT_POLY,*
-V 3900,4000,CONT_DIF_P,*
-V 3900,4500,CONT_DIF_P,*
-V 5100,4500,CONT_DIF_P,*
-V 5100,4000,CONT_DIF_P,*
-V 5100,3500,CONT_DIF_P,*
-V 5100,3000,CONT_DIF_P,*
-V 3300,3000,CONT_DIF_P,*
-V 3300,1000,CONT_DIF_N,*
-V 3900,1000,CONT_DIF_N,*
-V 5100,1000,CONT_DIF_N,*
-V 4000,2000,CONT_POLY,*
-V 3300,4700,CONT_BODY_N,*
-V 1500,300,CONT_BODY_P,*
-V 1500,4700,CONT_BODY_N,*
-V 2700,4500,CONT_DIF_P,*
-V 300,4500,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 2100,500,CONT_DIF_N,*
-V 2700,1000,CONT_DIF_N,*
-V 1500,1000,CONT_DIF_N,*
-V 300,1000,CONT_DIF_N,*
-V 1500,3500,CONT_DIF_P,*
-V 900,1500,CONT_DIF_N,*
-V 2100,4700,CONT_BODY_N,*
-V 900,4700,CONT_BODY_N,*
-V 2700,300,CONT_BODY_P,*
-V 900,300,CONT_BODY_P,*
-V 300,300,CONT_BODY_P,*
-V 4500,3000,CONT_DIF_P,*
-V 4500,3500,CONT_DIF_P,*
-V 4500,4000,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/nao2o22_x4.sym b/alliance/share/cells/sxlib/nao2o22_x4.sym
deleted file mode 100644
index 886aab25..00000000
Binary files a/alliance/share/cells/sxlib/nao2o22_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/nao2o22_x4.vbe b/alliance/share/cells/sxlib/nao2o22_x4.vbe
deleted file mode 100644
index b5c506fe..00000000
--- a/alliance/share/cells/sxlib/nao2o22_x4.vbe
+++ /dev/null
@@ -1,44 +0,0 @@
-ENTITY nao2o22_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 2750;
-  CONSTANT cin_i0	 : NATURAL := 8;
-  CONSTANT cin_i1	 : NATURAL := 8;
-  CONSTANT cin_i2	 : NATURAL := 8;
-  CONSTANT cin_i3	 : NATURAL := 8;
-  CONSTANT rdown_i0_nq	 : NATURAL := 810;
-  CONSTANT rdown_i1_nq	 : NATURAL := 810;
-  CONSTANT rdown_i2_nq	 : NATURAL := 810;
-  CONSTANT rdown_i3_nq	 : NATURAL := 810;
-  CONSTANT rup_i0_nq	 : NATURAL := 890;
-  CONSTANT rup_i1_nq	 : NATURAL := 890;
-  CONSTANT rup_i2_nq	 : NATURAL := 890;
-  CONSTANT rup_i3_nq	 : NATURAL := 890;
-  CONSTANT tphl_i3_nq	 : NATURAL := 607;
-  CONSTANT tplh_i0_nq	 : NATURAL := 644;
-  CONSTANT tphl_i2_nq	 : NATURAL := 664;
-  CONSTANT tphl_i1_nq	 : NATURAL := 666;
-  CONSTANT tplh_i1_nq	 : NATURAL := 717;
-  CONSTANT tplh_i2_nq	 : NATURAL := 721;
-  CONSTANT tphl_i0_nq	 : NATURAL := 734;
-  CONSTANT tplh_i3_nq	 : NATURAL := 807;
-  CONSTANT transistors	 : NATURAL := 14
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  i3	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END nao2o22_x4;
-
-ARCHITECTURE behaviour_data_flow OF nao2o22_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on nao2o22_x4"
-  SEVERITY WARNING;
-  nq <= not (((i0 or i1) and (i2 or i3))) after 1400 ps;
-END;
diff --git a/alliance/share/cells/sxlib/nao2o22_x4.vhd b/alliance/share/cells/sxlib/nao2o22_x4.vhd
deleted file mode 100644
index 4bc6cef6..00000000
--- a/alliance/share/cells/sxlib/nao2o22_x4.vhd
+++ /dev/null
@@ -1,22 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY nao2o22_x4 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  i3	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END nao2o22_x4;
-
-ARCHITECTURE RTL OF nao2o22_x4 IS
-BEGIN
-  nq <= NOT(((i0 OR i1) AND (i2 OR i3)));
-END RTL;
diff --git a/alliance/share/cells/sxlib/nmx2_x1.al b/alliance/share/cells/sxlib/nmx2_x1.al
deleted file mode 100644
index 92138ed1..00000000
--- a/alliance/share/cells/sxlib/nmx2_x1.al
+++ /dev/null
@@ -1,41 +0,0 @@
-V ALLIANCE : 6
-H nmx2_x1,L,30/10/99
-C cmd,IN,EXTERNAL,9
-C i0,IN,EXTERNAL,10
-C i1,IN,EXTERNAL,11
-C nq,OUT,EXTERNAL,3
-C vdd,IN,EXTERNAL,7
-C vss,IN,EXTERNAL,1
-T P,0.35,5.9,3,5,6,0,0.75,0.75,13.3,13.3,6.9,11.25,tr_00010
-T P,0.35,5.9,8,9,3,0,0.75,0.75,13.3,13.3,5.1,11.25,tr_00009
-T P,0.35,5.9,6,11,7,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00008
-T P,0.35,5.9,7,10,8,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00007
-T P,0.35,2.9,5,9,7,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00006
-T N,0.35,2.9,2,9,3,0,0.75,0.75,7.3,7.3,6.9,2.25,tr_00005
-T N,0.35,2.9,3,5,4,0,0.75,0.75,7.3,7.3,5.1,2.25,tr_00004
-T N,0.35,2.9,1,11,2,0,0.75,0.75,7.3,7.3,8.7,2.25,tr_00003
-T N,0.35,2.9,4,10,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002
-T N,0.35,1.4,1,9,5,0,0.75,0.75,4.3,4.3,1.8,3,tr_00001
-S 11,EXTERNAL,i1
-Q 0.00271107
-S 10,EXTERNAL,i0
-Q 0.00265635
-S 9,EXTERNAL,cmd
-Q 0.00492843
-S 8,INTERNAL
-Q 0
-S 7,EXTERNAL,vdd
-Q 0.00384489
-S 6,INTERNAL
-Q 0
-S 5,INTERNAL
-Q 0.00698278
-S 4,INTERNAL
-Q 0
-S 3,EXTERNAL,nq
-Q 0.00270273
-S 2,INTERNAL
-Q 0
-S 1,EXTERNAL,vss
-Q 0.00384489
-EOF
diff --git a/alliance/share/cells/sxlib/nmx2_x1.ap b/alliance/share/cells/sxlib/nmx2_x1.ap
deleted file mode 100644
index ffdd8fa3..00000000
--- a/alliance/share/cells/sxlib/nmx2_x1.ap
+++ /dev/null
@@ -1,92 +0,0 @@
-V ALLIANCE : 6
-H nmx2_x1,P,30/ 8/2000,100
-A 0,0,3500,5000
-R 1500,2000,ref_ref,cmd_20
-R 1500,2500,ref_ref,cmd_25
-R 1500,3000,ref_ref,cmd_30
-R 1500,3500,ref_ref,cmd_35
-R 1000,1500,ref_ref,i0_15
-R 1000,2000,ref_ref,i0_20
-R 1000,2500,ref_ref,i0_25
-R 1000,3000,ref_ref,i0_30
-R 1000,3500,ref_ref,i0_35
-R 3000,1000,ref_ref,i1_10
-R 3000,1500,ref_ref,i1_15
-R 3000,2000,ref_ref,i1_20
-R 3000,2500,ref_ref,i1_25
-R 3000,3000,ref_ref,i1_30
-R 3000,3500,ref_ref,i1_35
-R 3000,4000,ref_ref,i1_40
-R 2000,3500,ref_ref,nq_35
-R 2000,3000,ref_ref,nq_30
-R 2000,2500,ref_ref,nq_25
-R 2500,1500,ref_ref,nq_15
-R 2000,2000,ref_ref,nq_20
-R 2000,1000,ref_ref,nq_10
-S 2100,950,2100,2050,200,*,UP,ALU1
-S 2050,1500,2500,1500,200,*,LEFT,ALU1
-S 3000,1000,3000,4000,100,*,DOWN,ALU1
-S 1000,1400,1200,1400,100,*,LEFT,POLY
-S 600,3100,600,4400,100,*,DOWN,PTRANS
-S 300,1000,300,4000,100,*,DOWN,ALU1
-S 300,3300,300,4200,300,*,DOWN,PDIF
-S 600,600,600,1400,100,*,UP,NTRANS
-S 600,1400,600,3100,100,*,DOWN,POLY
-S 300,800,300,1200,300,*,UP,NDIF
-S 0,300,3500,300,600,vss,RIGHT,CALU1
-S 0,4700,3500,4700,600,vdd,RIGHT,CALU1
-S 0,3900,3500,3900,2400,*,RIGHT,NWELL
-S 1200,100,1200,1400,100,*,UP,NTRANS
-S 900,300,900,1200,300,*,UP,NDIF
-S 900,2600,1200,2600,100,*,RIGHT,POLY
-S 2000,2800,2000,4700,500,*,DOWN,PDIF
-S 1200,2600,1200,4900,100,*,DOWN,PTRANS
-S 900,2800,900,4700,300,*,DOWN,PDIF
-S 1500,2000,1500,3500,100,*,UP,ALU1
-S 1000,1500,1000,3500,100,*,DOWN,ALU1
-S 3200,2800,3200,4700,300,*,DOWN,PDIF
-S 2900,2600,2900,4900,100,*,DOWN,PTRANS
-S 2900,100,2900,1400,100,*,UP,NTRANS
-S 3200,300,3200,1200,300,*,UP,NDIF
-S 300,4000,2500,4000,100,*,RIGHT,ALU1
-S 2500,2500,2500,4000,100,*,DOWN,ALU1
-S 2000,300,2000,1200,500,*,DOWN,NDIF
-S 1550,1000,1550,1500,100,*,UP,ALU1
-S 300,1000,1550,1000,100,*,RIGHT,ALU1
-S 1700,2600,1700,4900,100,*,DOWN,PTRANS
-S 1700,2000,1700,2600,100,*,UP,POLY
-S 1700,100,1700,1400,100,*,UP,NTRANS
-S 2300,100,2300,1400,100,*,UP,NTRANS
-S 2300,1400,2300,2000,100,*,DOWN,POLY
-S 600,2000,2300,2000,100,*,RIGHT,POLY
-S 2300,2600,2300,4900,100,*,DOWN,PTRANS
-S 2300,2600,2500,2600,100,*,RIGHT,POLY
-S 2600,2800,2600,4700,200,*,UP,PDIF
-S 2600,300,2600,1200,200,*,DOWN,NDIF
-S 2000,1950,2000,3500,200,*,DOWN,ALU1
-S 1500,2000,1500,3500,200,cmd,DOWN,CALU1
-S 1000,1500,1000,3500,200,i0,DOWN,CALU1
-S 3000,1000,3000,4000,200,i1,DOWN,CALU1
-S 2000,2000,2000,3500,200,nq,DOWN,CALU1
-S 2000,1000,2000,1000,200,nq,LEFT,CALU1
-S 2500,1500,2500,1500,200,nq,LEFT,CALU1
-V 1500,2000,CONT_POLY,*
-V 2000,3500,CONT_DIF_P,*
-V 300,3500,CONT_DIF_P,*
-V 300,4000,CONT_DIF_P,*
-V 1000,1500,CONT_POLY,*
-V 900,4500,CONT_DIF_P,*
-V 300,1000,CONT_DIF_N,*
-V 300,4700,CONT_BODY_N,*
-V 3000,1500,CONT_POLY,*
-V 1600,1500,CONT_POLY,*
-V 900,500,CONT_DIF_N,*
-V 300,300,CONT_BODY_P,*
-V 1000,2500,CONT_POLY,*
-V 3000,2500,CONT_POLY,*
-V 2000,3000,CONT_DIF_P,*
-V 3200,4500,CONT_DIF_P,*
-V 2500,2500,CONT_POLY,*
-V 3200,500,CONT_DIF_N,*
-V 2000,1000,CONT_DIF_N,*
-EOF
diff --git a/alliance/share/cells/sxlib/nmx2_x1.sym b/alliance/share/cells/sxlib/nmx2_x1.sym
deleted file mode 100644
index b7abb919..00000000
Binary files a/alliance/share/cells/sxlib/nmx2_x1.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/nmx2_x1.vbe b/alliance/share/cells/sxlib/nmx2_x1.vbe
deleted file mode 100644
index cd7873d4..00000000
--- a/alliance/share/cells/sxlib/nmx2_x1.vbe
+++ /dev/null
@@ -1,42 +0,0 @@
-ENTITY nmx2_x1 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 1750;
-  CONSTANT cin_cmd	 : NATURAL := 21;
-  CONSTANT cin_i0	 : NATURAL := 14;
-  CONSTANT cin_i1	 : NATURAL := 14;
-  CONSTANT rdown_cmd_nq	 : NATURAL := 2850;
-  CONSTANT rdown_cmd_nq	 : NATURAL := 2850;
-  CONSTANT rdown_i0_nq	 : NATURAL := 2850;
-  CONSTANT rdown_i1_nq	 : NATURAL := 2850;
-  CONSTANT rup_cmd_nq	 : NATURAL := 3210;
-  CONSTANT rup_cmd_nq	 : NATURAL := 3210;
-  CONSTANT rup_i0_nq	 : NATURAL := 3210;
-  CONSTANT rup_i1_nq	 : NATURAL := 3210;
-  CONSTANT tphl_i0_nq	 : NATURAL := 217;
-  CONSTANT tphl_i1_nq	 : NATURAL := 217;
-  CONSTANT tphl_cmd_nq	 : NATURAL := 218;
-  CONSTANT tplh_i0_nq	 : NATURAL := 256;
-  CONSTANT tplh_i1_nq	 : NATURAL := 256;
-  CONSTANT tplh_cmd_nq	 : NATURAL := 287;
-  CONSTANT tphh_cmd_nq	 : NATURAL := 379;
-  CONSTANT tpll_cmd_nq	 : NATURAL := 410;
-  CONSTANT transistors	 : NATURAL := 10
-);
-PORT (
-  cmd	 : in  BIT;
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END nmx2_x1;
-
-ARCHITECTURE behaviour_data_flow OF nmx2_x1 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on nmx2_x1"
-  SEVERITY WARNING;
-  nq <= not (((i0 and not (cmd)) or (i1 and cmd))) after 1000 ps;
-END;
diff --git a/alliance/share/cells/sxlib/nmx2_x1.vhd b/alliance/share/cells/sxlib/nmx2_x1.vhd
deleted file mode 100644
index 46309893..00000000
--- a/alliance/share/cells/sxlib/nmx2_x1.vhd
+++ /dev/null
@@ -1,21 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY nmx2_x1 IS
-PORT(
-  cmd	: IN STD_LOGIC;
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END nmx2_x1;
-
-ARCHITECTURE RTL OF nmx2_x1 IS
-BEGIN
-  nq <= NOT(((i0 AND NOT(cmd)) OR (i1 AND cmd)));
-END RTL;
diff --git a/alliance/share/cells/sxlib/nmx2_x4.al b/alliance/share/cells/sxlib/nmx2_x4.al
deleted file mode 100644
index 1af7115f..00000000
--- a/alliance/share/cells/sxlib/nmx2_x4.al
+++ /dev/null
@@ -1,51 +0,0 @@
-V ALLIANCE : 6
-H nmx2_x4,L,30/10/99
-C cmd,IN,EXTERNAL,7
-C i0,IN,EXTERNAL,8
-C i1,IN,EXTERNAL,6
-C nq,OUT,EXTERNAL,10
-C vdd,IN,EXTERNAL,11
-C vss,IN,EXTERNAL,1
-T P,0.35,2.9,11,8,12,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00016
-T P,0.35,2.9,3,4,13,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00015
-T P,0.35,2.9,12,7,3,0,0.75,0.75,7.3,7.3,4.8,11.25,tr_00014
-T P,0.35,2.9,4,7,11,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00013
-T P,0.35,2.9,13,6,11,0,0.75,0.75,7.3,7.3,8.4,11.25,tr_00012
-T P,0.35,2.9,11,3,9,0,0.75,0.75,7.3,7.3,10.2,11.25,tr_00011
-T P,0.35,5.9,11,9,10,0,0.75,0.75,13.3,13.3,14.1,11.25,tr_00010
-T P,0.35,5.9,10,9,11,0,0.75,0.75,13.3,13.3,15.9,11.25,tr_00009
-T N,0.35,1.4,5,8,1,0,0.75,0.75,4.3,4.3,3.6,1.5,tr_00008
-T N,0.35,1.4,3,4,5,0,0.75,0.75,4.3,4.3,4.8,1.5,tr_00007
-T N,0.35,1.4,1,7,4,0,0.75,0.75,4.3,4.3,1.8,1.5,tr_00006
-T N,0.35,1.4,2,7,3,0,0.75,0.75,4.3,4.3,7.2,1.5,tr_00005
-T N,0.35,1.4,1,6,2,0,0.75,0.75,4.3,4.3,8.4,1.5,tr_00004
-T N,0.35,1.4,9,3,1,0,0.75,0.75,4.3,4.3,10.2,1.5,tr_00003
-T N,0.35,2.9,10,9,1,0,0.75,0.75,7.3,7.3,14.1,2.25,tr_00002
-T N,0.35,2.9,1,9,10,0,0.75,0.75,7.3,7.3,15.9,2.25,tr_00001
-S 13,INTERNAL
-Q 0
-S 12,INTERNAL
-Q 0
-S 11,EXTERNAL,vdd
-Q 0.00966511
-S 10,EXTERNAL,nq
-Q 0.00258522
-S 9,INTERNAL
-Q 0.00573596
-S 8,EXTERNAL,i0
-Q 0.00336619
-S 7,EXTERNAL,cmd
-Q 0.00660261
-S 6,EXTERNAL,i1
-Q 0.00371745
-S 5,INTERNAL
-Q 0
-S 4,INTERNAL
-Q 0.00595297
-S 3,INTERNAL
-Q 0.00516493
-S 2,INTERNAL
-Q 0
-S 1,EXTERNAL,vss
-Q 0.00807873
-EOF
diff --git a/alliance/share/cells/sxlib/nmx2_x4.ap b/alliance/share/cells/sxlib/nmx2_x4.ap
deleted file mode 100644
index aa630ade..00000000
--- a/alliance/share/cells/sxlib/nmx2_x4.ap
+++ /dev/null
@@ -1,147 +0,0 @@
-V ALLIANCE : 6
-H nmx2_x4,P,30/ 8/2000,100
-A 0,0,6000,5000
-R 3000,4000,ref_ref,i1_40
-R 3000,3500,ref_ref,i1_35
-R 3000,3000,ref_ref,i1_30
-R 3000,2500,ref_ref,i1_25
-R 3000,2000,ref_ref,i1_20
-R 3000,1500,ref_ref,i1_15
-R 3000,1000,ref_ref,i1_10
-R 1000,4000,ref_ref,i0_40
-R 1000,3500,ref_ref,i0_35
-R 1000,3000,ref_ref,i0_30
-R 1000,2500,ref_ref,i0_25
-R 1000,2000,ref_ref,i0_20
-R 1000,1500,ref_ref,i0_15
-R 1500,4000,ref_ref,cmd_40
-R 1500,3500,ref_ref,cmd_35
-R 1500,3000,ref_ref,cmd_30
-R 1500,2500,ref_ref,cmd_25
-R 1500,2000,ref_ref,cmd_20
-R 1500,1500,ref_ref,cmd_15
-R 5000,4000,ref_ref,nq_40
-R 5000,3500,ref_ref,nq_35
-R 5000,2500,ref_ref,nq_25
-R 5000,1000,ref_ref,nq_10
-R 5000,3000,ref_ref,nq_30
-R 5000,2000,ref_ref,nq_20
-R 5000,1500,ref_ref,nq_15
-S 3000,1000,3000,4000,200,i1,DOWN,CALU1
-S 1000,1500,1000,4000,200,i0,DOWN,CALU1
-S 1500,1500,1500,4000,200,cmd,DOWN,CALU1
-S 5000,1000,5000,4000,200,nq,DOWN,CALU1
-S 5000,1000,5000,4000,200,*,DOWN,ALU1
-S 600,2000,2400,2000,100,*,RIGHT,POLY
-S 300,1000,2500,1000,100,*,RIGHT,ALU1
-S 1000,1500,1000,4000,100,*,DOWN,ALU1
-S 300,3300,300,4200,300,*,DOWN,PDIF
-S 300,1000,300,4000,100,*,DOWN,ALU1
-S 1600,2000,1600,3100,100,*,UP,POLY
-S 1200,3100,1200,4400,100,*,DOWN,PTRANS
-S 2400,3100,2400,4400,100,*,DOWN,PTRANS
-S 1600,3100,1600,4400,100,*,DOWN,PTRANS
-S 900,3300,900,4600,300,*,DOWN,PDIF
-S 600,3100,600,4400,100,*,DOWN,PTRANS
-S 2000,3300,2000,4200,500,*,DOWN,PDIF
-S 2000,1500,2000,4000,100,*,DOWN,ALU1
-S 2800,3100,2800,4400,100,*,DOWN,PTRANS
-S 2500,1000,2500,2700,100,*,UP,ALU1
-S 2400,2800,2400,3100,100,*,UP,POLY
-S 2800,3100,3100,3100,100,*,RIGHT,POLY
-S 900,3100,1200,3100,100,*,RIGHT,POLY
-S 2800,1400,3100,1400,100,*,RIGHT,POLY
-S 1200,100,1200,900,100,*,UP,NTRANS
-S 1600,100,1600,900,100,*,UP,NTRANS
-S 600,100,600,900,100,*,UP,NTRANS
-S 900,300,900,700,300,*,UP,NDIF
-S 600,900,600,3100,100,*,DOWN,POLY
-S 2400,100,2400,900,100,*,UP,NTRANS
-S 2800,100,2800,900,100,*,UP,NTRANS
-S 2400,900,2400,2000,100,*,DOWN,POLY
-S 2800,900,2800,1400,100,*,DOWN,POLY
-S 2000,300,2000,1600,300,*,DOWN,NDIF
-S 1000,1400,1200,1400,100,*,LEFT,POLY
-S 1200,900,1200,1400,100,*,DOWN,POLY
-S 1500,1500,1500,4000,100,*,UP,ALU1
-S 2000,300,2000,700,500,*,DOWN,NDIF
-S 1500,4700,2500,4700,300,*,RIGHT,NTIE
-S 2100,300,2100,1600,300,*,DOWN,NDIF
-S 3000,1000,3000,4000,100,*,DOWN,ALU1
-S 0,300,6000,300,600,vss,RIGHT,CALU1
-S 0,4700,6000,4700,600,vdd,RIGHT,CALU1
-S 0,3900,6000,3900,2400,*,RIGHT,NWELL
-S 3400,100,3400,900,100,*,UP,NTRANS
-S 3100,300,3100,700,300,*,DOWN,NDIF
-S 3700,300,3700,1100,300,*,DOWN,NDIF
-S 300,300,300,1100,300,*,UP,NDIF
-S 3400,3100,3400,4400,100,*,DOWN,PTRANS
-S 3700,3300,3700,4200,300,*,DOWN,PDIF
-S 3100,3300,3100,4600,300,*,DOWN,PDIF
-S 3700,1000,3700,4000,100,*,DOWN,ALU1
-S 3400,900,3400,3100,100,*,DOWN,POLY
-S 2000,2300,3400,2300,100,*,RIGHT,POLY
-S 5600,3000,5600,4500,200,*,UP,ALU1
-S 5600,500,5600,1700,200,*,DOWN,ALU1
-S 4400,500,4400,1700,200,*,DOWN,ALU1
-S 4400,3000,4400,4500,200,*,UP,ALU1
-S 5600,2900,5600,3300,300,*,DOWN,PDIF
-S 4700,100,4700,1400,100,*,UP,NTRANS
-S 5000,300,5000,1200,300,*,DOWN,NDIF
-S 5300,100,5300,1400,100,*,UP,NTRANS
-S 5600,300,5600,1200,300,*,DOWN,NDIF
-S 4400,300,4400,1200,300,*,DOWN,NDIF
-S 3800,2500,5300,2500,100,*,LEFT,POLY
-S 4700,1400,4700,2600,100,*,DOWN,POLY
-S 4700,2600,4700,4900,100,*,DOWN,PTRANS
-S 5300,1400,5300,2600,100,*,DOWN,POLY
-S 5300,2600,5300,4900,100,*,DOWN,PTRANS
-S 4400,2800,4400,4700,300,*,UP,PDIF
-S 5600,2800,5600,4700,300,*,UP,PDIF
-S 5000,2800,5000,4700,300,*,UP,PDIF
-V 3000,1500,CONT_POLY,*
-V 300,4700,CONT_BODY_N,*
-V 900,500,CONT_DIF_N,*
-V 300,1000,CONT_DIF_N,*
-V 900,4500,CONT_DIF_P,*
-V 1000,1500,CONT_POLY,*
-V 300,4000,CONT_DIF_P,*
-V 300,3500,CONT_DIF_P,*
-V 1000,3000,CONT_POLY,*
-V 3000,3000,CONT_POLY,*
-V 2000,1500,CONT_DIF_N,*
-V 2000,3500,CONT_DIF_P,*
-V 2000,4700,CONT_BODY_N,*
-V 2000,4000,CONT_DIF_P,*
-V 2500,2700,CONT_POLY,*
-V 2000,2400,CONT_POLY,*
-V 1500,2000,CONT_POLY,*
-V 1600,1000,CONT_POLY,*
-V 1500,4700,CONT_BODY_N,*
-V 2500,4700,CONT_BODY_N,*
-V 3100,500,CONT_DIF_N,*
-V 3700,1000,CONT_DIF_N,*
-V 3100,4500,CONT_DIF_P,*
-V 3700,4000,CONT_DIF_P,*
-V 3700,3400,CONT_DIF_P,*
-V 3700,4700,CONT_BODY_N,*
-V 3800,2500,CONT_POLY,*
-V 4400,1700,CONT_BODY_P,*
-V 5600,1700,CONT_BODY_P,*
-V 4400,3000,CONT_DIF_P,*
-V 4400,4500,CONT_DIF_P,*
-V 5600,3000,CONT_DIF_P,*
-V 5600,4500,CONT_DIF_P,*
-V 5600,4000,CONT_DIF_P,*
-V 5000,3000,CONT_DIF_P,*
-V 5000,4000,CONT_DIF_P,*
-V 5000,3500,CONT_DIF_P,*
-V 4400,4000,CONT_DIF_P,*
-V 4400,3500,CONT_DIF_P,*
-V 5600,3500,CONT_DIF_P,*
-V 4400,1000,CONT_DIF_N,*
-V 4400,500,CONT_DIF_N,*
-V 5600,500,CONT_DIF_N,*
-V 5600,1000,CONT_DIF_N,*
-V 5000,1000,CONT_DIF_N,*
-EOF
diff --git a/alliance/share/cells/sxlib/nmx2_x4.sym b/alliance/share/cells/sxlib/nmx2_x4.sym
deleted file mode 100644
index 2f3c726d..00000000
Binary files a/alliance/share/cells/sxlib/nmx2_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/nmx2_x4.vbe b/alliance/share/cells/sxlib/nmx2_x4.vbe
deleted file mode 100644
index b939997d..00000000
--- a/alliance/share/cells/sxlib/nmx2_x4.vbe
+++ /dev/null
@@ -1,42 +0,0 @@
-ENTITY nmx2_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 3000;
-  CONSTANT cin_cmd	 : NATURAL := 17;
-  CONSTANT cin_i0	 : NATURAL := 8;
-  CONSTANT cin_i1	 : NATURAL := 9;
-  CONSTANT rdown_cmd_nq	 : NATURAL := 810;
-  CONSTANT rdown_cmd_nq	 : NATURAL := 810;
-  CONSTANT rdown_i0_nq	 : NATURAL := 810;
-  CONSTANT rdown_i1_nq	 : NATURAL := 810;
-  CONSTANT rup_cmd_nq	 : NATURAL := 890;
-  CONSTANT rup_cmd_nq	 : NATURAL := 890;
-  CONSTANT rup_i0_nq	 : NATURAL := 890;
-  CONSTANT rup_i1_nq	 : NATURAL := 890;
-  CONSTANT tphl_i0_nq	 : NATURAL := 610;
-  CONSTANT tphl_i1_nq	 : NATURAL := 610;
-  CONSTANT tphl_cmd_nq	 : NATURAL := 632;
-  CONSTANT tplh_i0_nq	 : NATURAL := 653;
-  CONSTANT tplh_i1_nq	 : NATURAL := 653;
-  CONSTANT tphh_cmd_nq	 : NATURAL := 688;
-  CONSTANT tpll_cmd_nq	 : NATURAL := 703;
-  CONSTANT tplh_cmd_nq	 : NATURAL := 708;
-  CONSTANT transistors	 : NATURAL := 16
-);
-PORT (
-  cmd	 : in  BIT;
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END nmx2_x4;
-
-ARCHITECTURE behaviour_data_flow OF nmx2_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on nmx2_x4"
-  SEVERITY WARNING;
-  nq <= not (((i0 and not (cmd)) or (i1 and cmd))) after 1300 ps;
-END;
diff --git a/alliance/share/cells/sxlib/nmx2_x4.vhd b/alliance/share/cells/sxlib/nmx2_x4.vhd
deleted file mode 100644
index d8d2a999..00000000
--- a/alliance/share/cells/sxlib/nmx2_x4.vhd
+++ /dev/null
@@ -1,21 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY nmx2_x4 IS
-PORT(
-  cmd	: IN STD_LOGIC;
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END nmx2_x4;
-
-ARCHITECTURE RTL OF nmx2_x4 IS
-BEGIN
-  nq <= NOT(((i0 AND NOT(cmd)) OR (i1 AND cmd)));
-END RTL;
diff --git a/alliance/share/cells/sxlib/nmx3_x1.al b/alliance/share/cells/sxlib/nmx3_x1.al
deleted file mode 100644
index d88bd558..00000000
--- a/alliance/share/cells/sxlib/nmx3_x1.al
+++ /dev/null
@@ -1,65 +0,0 @@
-V ALLIANCE : 6
-H nmx3_x1,L,30/10/99
-C cmd0,IN,EXTERNAL,14
-C cmd1,IN,EXTERNAL,9
-C i0,IN,EXTERNAL,13
-C i1,IN,EXTERNAL,8
-C i2,IN,EXTERNAL,10
-C nq,OUT,EXTERNAL,1
-C vdd,IN,EXTERNAL,7
-C vss,IN,EXTERNAL,3
-T P,0.35,2.9,15,6,1,0,0.75,0.75,7.3,7.3,7.8,12.75,tr_00018
-T P,0.35,2.9,7,12,17,0,0.75,0.75,7.3,7.3,10.8,12.75,tr_00017
-T P,0.35,2.9,18,14,7,0,0.75,0.75,7.3,7.3,12.6,12.75,tr_00016
-T P,0.35,2.9,1,13,18,0,0.75,0.75,7.3,7.3,13.8,12.75,tr_00015
-T P,0.35,2.9,17,8,15,0,0.75,0.75,7.3,7.3,9,12.75,tr_00014
-T P,0.35,2.9,16,10,17,0,0.75,0.75,7.3,7.3,4.2,12.75,tr_00013
-T P,0.35,2.9,1,9,16,0,0.75,0.75,7.3,7.3,6,12.75,tr_00012
-T P,0.35,2,6,9,7,0,0.75,0.75,5.5,5.5,2.4,9.3,tr_00011
-T P,0.35,2,7,14,12,0,0.75,0.75,5.5,5.5,15.6,9.3,tr_00010
-T N,0.35,1.7,4,8,2,0,0.75,0.75,4.9,4.9,9,2.55,tr_00009
-T N,0.35,1.7,2,9,1,0,0.75,0.75,4.9,4.9,7.8,2.55,tr_00008
-T N,0.35,1.7,1,6,5,0,0.75,0.75,4.9,4.9,6,2.55,tr_00007
-T N,0.35,1.7,5,10,4,0,0.75,0.75,4.9,4.9,4.2,2.55,tr_00006
-T N,0.35,1.7,3,14,4,0,0.75,0.75,4.9,4.9,10.8,1.95,tr_00005
-T N,0.35,1.7,11,12,3,0,0.75,0.75,4.9,4.9,12.6,1.95,tr_00004
-T N,0.35,1.7,1,13,11,0,0.75,0.75,4.9,4.9,13.8,1.95,tr_00003
-T N,0.35,1.1,3,9,6,0,0.75,0.75,3.7,3.7,2.4,5.25,tr_00002
-T N,0.35,1.1,12,14,3,0,0.75,0.75,3.7,3.7,15.6,4.95,tr_00001
-S 18,INTERNAL
-Q 0
-S 17,INTERNAL
-Q 0.00170541
-S 16,INTERNAL
-Q 0
-S 15,INTERNAL
-Q 0
-S 14,EXTERNAL,cmd0
-Q 0.00553121
-S 13,EXTERNAL,i0
-Q 0.00386192
-S 12,INTERNAL
-Q 0.0057783
-S 11,INTERNAL
-Q 0
-S 10,EXTERNAL,i2
-Q 0.0021309
-S 9,EXTERNAL,cmd1
-Q 0.00604152
-S 8,EXTERNAL,i1
-Q 0.0025589
-S 7,EXTERNAL,vdd
-Q 0.00690363
-S 6,INTERNAL
-Q 0.00547335
-S 5,INTERNAL
-Q 0
-S 4,INTERNAL
-Q 0.00170541
-S 3,EXTERNAL,vss
-Q 0.00619857
-S 2,INTERNAL
-Q 0
-S 1,EXTERNAL,nq
-Q 0.00696213
-EOF
diff --git a/alliance/share/cells/sxlib/nmx3_x1.ap b/alliance/share/cells/sxlib/nmx3_x1.ap
deleted file mode 100644
index 5a6d6e6e..00000000
--- a/alliance/share/cells/sxlib/nmx3_x1.ap
+++ /dev/null
@@ -1,167 +0,0 @@
-V ALLIANCE : 6
-H nmx3_x1,P, 6/ 9/2000,100
-A 0,0,6000,5000
-R 5500,1000,ref_ref,nq_10
-R 5500,3000,ref_ref,nq_30
-R 5500,2500,ref_ref,nq_25
-R 5500,2000,ref_ref,nq_20
-R 5500,1500,ref_ref,nq_15
-R 5500,3500,ref_ref,nq_35
-R 500,1500,ref_ref,cmd1_15
-R 500,2000,ref_ref,cmd1_20
-R 500,2500,ref_ref,cmd1_25
-R 500,3000,ref_ref,cmd1_30
-R 500,3500,ref_ref,cmd1_35
-R 1500,2500,ref_ref,i2_25
-R 2500,2500,ref_ref,i1_25
-R 3500,2000,ref_ref,cmd0_20
-R 3500,2500,ref_ref,cmd0_25
-R 3500,3000,ref_ref,cmd0_30
-R 4000,2000,ref_ref,i0_20
-R 4000,3000,ref_ref,i0_30
-R 4500,2500,ref_ref,i0_25
-S 1800,1500,2000,1500,300,*,RIGHT,POLY
-S 4400,2000,4600,2000,300,*,RIGHT,POLY
-S 4400,3000,4600,3000,300,*,RIGHT,POLY
-S 1800,3500,2000,3500,300,*,RIGHT,POLY
-S 4000,2000,4000,2000,200,i0,LEFT,CALU1
-S 4500,2500,4500,2500,200,i0,LEFT,CALU1
-S 4000,3000,4000,3000,200,i0,LEFT,CALU1
-S 5500,1000,5500,3500,200,nq,DOWN,CALU1
-S 500,1500,500,3500,200,cmd1,DOWN,CALU1
-S 1500,2500,1500,2500,200,i2,LEFT,CALU1
-S 2500,2500,2500,2500,200,i1,LEFT,CALU1
-S 3500,2000,3500,3000,200,cmd0,DOWN,CALU1
-S 5500,4000,5500,4700,200,*,UP,ALU1
-S 5500,2800,5500,4000,300,*,DOWN,PDIF
-S 0,4700,6000,4700,600,vdd,RIGHT,CALU1
-S 0,3900,6000,3900,2400,*,RIGHT,NWELL
-S 0,300,6000,300,600,vss,RIGHT,CALU1
-S 5500,500,5500,1800,300,*,DOWN,NDIF
-S 3500,2000,3500,3000,100,*,DOWN,ALU1
-S 4000,2000,4400,2000,200,*,RIGHT,ALU1
-S 4000,3000,4400,3000,200,*,RIGHT,ALU1
-S 2800,1500,2800,2000,100,*,UP,ALU1
-S 2300,1500,2800,1500,100,*,RIGHT,ALU1
-S 1100,4000,3300,4000,100,*,RIGHT,ALU1
-S 1000,3000,1800,3000,100,*,LEFT,ALU1
-S 1800,2000,1900,2000,100,*,RIGHT,ALU1
-S 1800,1500,1800,2000,100,*,UP,ALU1
-S 500,1500,500,3500,100,*,DOWN,ALU1
-S 1000,1800,1000,3000,100,*,UP,ALU1
-S 2000,2000,2000,3000,100,*,UP,ALU1
-S 500,4000,500,4600,200,*,UP,ALU1
-S 500,3500,1800,3500,100,*,LEFT,ALU1
-S 1100,1000,3300,1000,100,*,RIGHT,ALU1
-S 500,400,500,1000,200,*,DOWN,ALU1
-S 2600,3000,2600,3600,100,*,UP,POLY
-S 3300,1500,3400,1500,100,*,LEFT,POLY
-S 3600,1100,3800,1100,100,*,RIGHT,POLY
-S 1800,1500,2000,1500,100,*,RIGHT,POLY
-S 800,2100,800,2600,100,*,DOWN,POLY
-S 500,2500,800,2500,300,*,RIGHT,POLY
-S 500,1000,500,1900,300,*,DOWN,NDIF
-S 2600,3600,2600,4900,100,*,UP,PTRANS
-S 3900,3800,3900,4700,200,*,UP,PDIF
-S 3600,3600,3600,4900,100,*,UP,PTRANS
-S 4200,3600,4200,4900,100,*,UP,PTRANS
-S 4900,3800,4900,4700,300,*,UP,PDIF
-S 4600,3600,4600,4900,100,*,UP,PTRANS
-S 3300,3800,3300,4700,200,*,UP,PDIF
-S 3000,3600,3000,4900,100,*,UP,PTRANS
-S 1100,3800,1100,4700,300,*,UP,PDIF
-S 1400,3600,1400,4900,100,*,UP,PTRANS
-S 1700,3800,1700,4700,200,*,DOWN,PDIF
-S 2300,3500,2300,4700,300,*,UP,PDIF
-S 2000,3600,2000,4900,100,*,UP,PTRANS
-S 500,2800,500,4000,300,*,UP,PDIF
-S 2000,2000,2000,3600,100,*,DOWN,POLY
-S 2000,2000,2600,2000,100,*,RIGHT,POLY
-S 2500,2500,3000,2500,100,*,RIGHT,POLY
-S 1800,3000,2500,3000,100,*,LEFT,ALU1
-S 2800,2000,3000,2000,100,*,RIGHT,ALU1
-S 3000,2000,3000,3500,100,*,UP,ALU1
-S 3400,1500,4900,1500,100,*,RIGHT,ALU1
-S 4400,3000,4600,3000,100,*,RIGHT,POLY
-S 4600,3000,4600,3600,100,*,UP,POLY
-S 4500,2000,4600,2000,100,*,RIGHT,POLY
-S 4000,1900,4000,3300,100,*,DOWN,POLY
-S 3800,1900,4000,1900,100,*,LEFT,POLY
-S 3800,1100,3800,1900,100,*,DOWN,POLY
-S 4000,2500,5200,2500,100,*,RIGHT,POLY
-S 4000,3600,4200,3600,100,*,LEFT,POLY
-S 4000,3300,4000,3600,100,*,UP,POLY
-S 4400,2000,4400,3000,100,*,UP,ALU1
-S 4900,3000,5000,3000,100,*,RIGHT,ALU1
-S 5000,1800,5000,3000,100,*,DOWN,ALU1
-S 3500,2500,3900,2500,200,*,RIGHT,ALU1
-S 4900,2800,4900,3400,300,*,UP,PDIF
-S 1400,1300,1400,3600,100,*,DOWN,POLY
-S 2000,1300,2000,1500,100,*,DOWN,POLY
-S 2600,1300,2600,2000,100,*,UP,POLY
-S 3000,1300,3000,3600,100,*,DOWN,POLY
-S 4200,1100,4200,1500,100,*,UP,POLY
-S 3900,400,3900,900,200,*,DOWN,NDIF
-S 4600,1100,4600,2000,100,*,DOWN,POLY
-S 800,2600,800,3600,100,*,UP,PTRANS
-S 5200,2600,5200,3600,100,*,UP,PTRANS
-S 1100,2800,1100,3400,300,*,UP,PDIF
-S 3000,400,3000,1300,100,*,UP,NTRANS
-S 2600,400,2600,1300,100,*,UP,NTRANS
-S 2000,400,2000,1300,100,*,UP,NTRANS
-S 1400,400,1400,1300,100,*,UP,NTRANS
-S 3600,200,3600,1100,100,*,UP,NTRANS
-S 4200,200,4200,1100,100,*,UP,NTRANS
-S 4600,200,4600,1100,100,*,UP,NTRANS
-S 3300,400,3300,1100,300,*,DOWN,NDIF
-S 2300,600,2300,1600,300,*,UP,NDIF
-S 1700,600,1700,1100,200,*,DOWN,NDIF
-S 1100,600,1100,1000,300,*,DOWN,NDIF
-S 4900,3500,4900,4000,100,*,DOWN,ALU1
-S 3500,1500,3500,3600,100,*,UP,POLY
-S 3500,3600,3600,3600,100,*,RIGHT,POLY
-S 800,1400,800,2100,100,*,DOWN,NTRANS
-S 1100,1600,1100,1900,300,*,UP,NDIF
-S 5500,1000,5500,3500,100,*,DOWN,ALU1
-S 2300,3500,5500,3500,100,*,RIGHT,ALU1
-S 4900,1000,5500,1000,100,*,RIGHT,ALU1
-S 5200,1300,5200,2000,100,*,DOWN,NTRANS
-S 5200,2000,5200,2600,100,*,DOWN,POLY
-S 4900,1700,5000,1700,100,*,LEFT,ALU1
-S 4900,1500,4900,1700,300,*,DOWN,NDIF
-S 4900,1500,4900,1700,200,*,DOWN,ALU1
-S 4900,400,4900,1000,300,*,UP,NDIF
-V 5600,4700,CONT_BODY_N,*
-V 5500,4000,CONT_DIF_P,*
-V 1800,3500,CONT_POLY,*
-V 4200,1500,CONT_POLY,*
-V 3400,1500,CONT_POLY,*
-V 1800,1500,CONT_POLY,*
-V 500,2500,CONT_POLY,*
-V 2500,2500,CONT_POLY,*
-V 1500,2500,CONT_POLY,*
-V 500,400,CONT_BODY_P,*
-V 2300,1500,CONT_DIF_N,*
-V 1100,1800,CONT_DIF_N,*
-V 1100,1800,CONT_DIF_N,*
-V 3300,1000,CONT_DIF_N,*
-V 4900,1000,CONT_DIF_N,*
-V 1100,1000,CONT_DIF_N,*
-V 500,1000,CONT_DIF_N,*
-V 3900,500,CONT_DIF_N,*
-V 3300,4000,CONT_DIF_P,*
-V 3900,4500,CONT_DIF_P,*
-V 2300,3500,CONT_DIF_P,*
-V 1100,4000,CONT_DIF_P,*
-V 4900,4000,CONT_DIF_P,*
-V 500,4000,CONT_DIF_P,*
-V 500,4600,CONT_BODY_N,*
-V 1100,3000,CONT_DIF_P,*
-V 4900,3000,CONT_DIF_P,*
-V 2500,3000,CONT_POLY,*
-V 4400,3000,CONT_POLY,*
-V 4400,2000,CONT_POLY,*
-V 5500,500,CONT_DIF_N,*
-V 3900,2500,CONT_POLY,*
-V 4900,1700,CONT_DIF_N,*
-EOF
diff --git a/alliance/share/cells/sxlib/nmx3_x1.vbe b/alliance/share/cells/sxlib/nmx3_x1.vbe
deleted file mode 100644
index e36e7d6f..00000000
--- a/alliance/share/cells/sxlib/nmx3_x1.vbe
+++ /dev/null
@@ -1,59 +0,0 @@
-ENTITY nmx3_x1 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 3000;
-  CONSTANT cin_cmd0	 : NATURAL := 15;
-  CONSTANT cin_cmd1	 : NATURAL := 15;
-  CONSTANT cin_i0	 : NATURAL := 9;
-  CONSTANT cin_i1	 : NATURAL := 8;
-  CONSTANT cin_i2	 : NATURAL := 8;
-  CONSTANT rdown_cmd0_nq	 : NATURAL := 5140;
-  CONSTANT rdown_cmd0_nq	 : NATURAL := 7420;
-  CONSTANT rdown_cmd1_nq	 : NATURAL := 7420;
-  CONSTANT rdown_cmd1_nq	 : NATURAL := 7420;
-  CONSTANT rdown_i0_nq	 : NATURAL := 5140;
-  CONSTANT rdown_i1_nq	 : NATURAL := 7420;
-  CONSTANT rdown_i2_nq	 : NATURAL := 7420;
-  CONSTANT rup_cmd0_nq	 : NATURAL := 6680;
-  CONSTANT rup_cmd0_nq	 : NATURAL := 9760;
-  CONSTANT rup_cmd1_nq	 : NATURAL := 9760;
-  CONSTANT rup_cmd1_nq	 : NATURAL := 9760;
-  CONSTANT rup_i0_nq	 : NATURAL := 6680;
-  CONSTANT rup_i1_nq	 : NATURAL := 9760;
-  CONSTANT rup_i2_nq	 : NATURAL := 9760;
-  CONSTANT tphl_i0_nq	 : NATURAL := 315;
-  CONSTANT tphl_cmd0_nq	 : NATURAL := 356;
-  CONSTANT tphl_cmd1_nq	 : NATURAL := 414;
-  CONSTANT tphl_i1_nq	 : NATURAL := 429;
-  CONSTANT tphl_i2_nq	 : NATURAL := 429;
-  CONSTANT tplh_i0_nq	 : NATURAL := 441;
-  CONSTANT tplh_cmd0_nq	 : NATURAL := 495;
-  CONSTANT tphh_cmd1_nq	 : NATURAL := 519;
-  CONSTANT tpll_cmd1_nq	 : NATURAL := 520;
-  CONSTANT tplh_cmd1_nq	 : NATURAL := 566;
-  CONSTANT tphh_cmd0_nq	 : NATURAL := 582;
-  CONSTANT tplh_i1_nq	 : NATURAL := 582;
-  CONSTANT tplh_i2_nq	 : NATURAL := 582;
-  CONSTANT tpll_cmd0_nq	 : NATURAL := 586;
-  CONSTANT transistors	 : NATURAL := 18
-);
-PORT (
-  cmd0	 : in  BIT;
-  cmd1	 : in  BIT;
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END nmx3_x1;
-
-ARCHITECTURE behaviour_data_flow OF nmx3_x1 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on nmx3_x1"
-  SEVERITY WARNING;
-  nq <= not (((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not
-  (cmd1) and i2))))) after 1200 ps;
-END;
diff --git a/alliance/share/cells/sxlib/nmx3_x1.vhd b/alliance/share/cells/sxlib/nmx3_x1.vhd
deleted file mode 100644
index 7fe6277f..00000000
--- a/alliance/share/cells/sxlib/nmx3_x1.vhd
+++ /dev/null
@@ -1,23 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY nmx3_x1 IS
-PORT(
-  cmd0	: IN STD_LOGIC;
-  cmd1	: IN STD_LOGIC;
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END nmx3_x1;
-
-ARCHITECTURE RTL OF nmx3_x1 IS
-BEGIN
-  nq <= NOT(((NOT(cmd0) AND i0) OR (cmd0 AND ((cmd1 AND i1) OR (NOT(cmd1) AND i2)))));
-END RTL;
diff --git a/alliance/share/cells/sxlib/nmx3_x4.al b/alliance/share/cells/sxlib/nmx3_x4.al
deleted file mode 100644
index eec6d89f..00000000
--- a/alliance/share/cells/sxlib/nmx3_x4.al
+++ /dev/null
@@ -1,75 +0,0 @@
-V ALLIANCE : 6
-H nmx3_x4,L,30/10/99
-C cmd0,IN,EXTERNAL,15
-C cmd1,IN,EXTERNAL,8
-C i0,IN,EXTERNAL,14
-C i1,IN,EXTERNAL,9
-C i2,IN,EXTERNAL,10
-C nq,OUT,EXTERNAL,12
-C vdd,IN,EXTERNAL,7
-C vss,IN,EXTERNAL,1
-T P,0.35,2,7,15,11,0,0.75,0.75,5.5,5.5,15.3,9.3,tr_00024
-T P,0.35,2,2,8,7,0,0.75,0.75,5.5,5.5,2.1,9.3,tr_00023
-T P,0.35,5.9,12,16,7,0,0.75,0.75,13.3,13.3,17.1,11.25,tr_00022
-T P,0.35,2.9,3,8,18,0,0.75,0.75,7.3,7.3,5.7,12.75,tr_00021
-T P,0.35,2.9,18,10,17,0,0.75,0.75,7.3,7.3,3.9,12.75,tr_00020
-T P,0.35,2.9,17,9,19,0,0.75,0.75,7.3,7.3,8.7,12.75,tr_00019
-T P,0.35,2.9,3,14,20,0,0.75,0.75,7.3,7.3,13.5,12.75,tr_00018
-T P,0.35,2.9,20,15,7,0,0.75,0.75,7.3,7.3,12.3,12.75,tr_00017
-T P,0.35,2.9,7,11,17,0,0.75,0.75,7.3,7.3,10.5,12.75,tr_00016
-T P,0.35,2.9,19,2,3,0,0.75,0.75,7.3,7.3,7.5,12.75,tr_00015
-T P,0.35,5.9,7,16,12,0,0.75,0.75,13.3,13.3,18.9,11.25,tr_00014
-T P,0.35,2.9,16,3,7,0,0.75,0.75,7.3,7.3,20.7,9.75,tr_00013
-T N,0.35,1.1,1,8,2,0,0.75,0.75,3.7,3.7,2.1,5.25,tr_00012
-T N,0.35,1.1,11,15,1,0,0.75,0.75,3.7,3.7,15.3,4.95,tr_00011
-T N,0.35,1.7,1,15,6,0,0.75,0.75,4.9,4.9,10.5,1.95,tr_00010
-T N,0.35,1.7,4,10,6,0,0.75,0.75,4.9,4.9,3.9,2.55,tr_00009
-T N,0.35,1.7,6,9,5,0,0.75,0.75,4.9,4.9,8.7,2.55,tr_00008
-T N,0.35,1.7,3,14,13,0,0.75,0.75,4.9,4.9,13.5,1.95,tr_00007
-T N,0.35,1.7,13,11,1,0,0.75,0.75,4.9,4.9,12.3,1.95,tr_00006
-T N,0.35,1.7,3,2,4,0,0.75,0.75,4.9,4.9,5.7,2.55,tr_00005
-T N,0.35,1.7,5,8,3,0,0.75,0.75,4.9,4.9,7.5,2.55,tr_00004
-T N,0.35,2.9,12,16,1,0,0.75,0.75,7.3,7.3,18.9,2.55,tr_00003
-T N,0.35,1.4,1,3,16,0,0.75,0.75,4.3,4.3,20.7,3.3,tr_00002
-T N,0.35,2.9,1,16,12,0,0.75,0.75,7.3,7.3,17.1,2.55,tr_00001
-S 20,INTERNAL
-Q 0
-S 19,INTERNAL
-Q 0
-S 18,INTERNAL
-Q 0
-S 17,INTERNAL
-Q 0.00170541
-S 16,INTERNAL
-Q 0.00532834
-S 15,EXTERNAL,cmd0
-Q 0.00547246
-S 14,EXTERNAL,i0
-Q 0.00397942
-S 13,INTERNAL
-Q 0
-S 12,EXTERNAL,nq
-Q 0.00232082
-S 11,INTERNAL
-Q 0.00589104
-S 10,EXTERNAL,i2
-Q 0.0021309
-S 9,EXTERNAL,i1
-Q 0.0025589
-S 8,EXTERNAL,cmd1
-Q 0.00604152
-S 7,EXTERNAL,vdd
-Q 0.00916191
-S 6,INTERNAL
-Q 0.00170541
-S 5,INTERNAL
-Q 0
-S 4,INTERNAL
-Q 0
-S 3,INTERNAL
-Q 0.0105263
-S 2,INTERNAL
-Q 0.00586794
-S 1,EXTERNAL,vss
-Q 0.00757552
-EOF
diff --git a/alliance/share/cells/sxlib/nmx3_x4.ap b/alliance/share/cells/sxlib/nmx3_x4.ap
deleted file mode 100644
index 2c669cc9..00000000
--- a/alliance/share/cells/sxlib/nmx3_x4.ap
+++ /dev/null
@@ -1,209 +0,0 @@
-V ALLIANCE : 6
-H nmx3_x4,P, 6/ 9/2000,100
-A 0,0,7500,5000
-R 500,1500,ref_ref,cmd1_15
-R 500,2000,ref_ref,cmd1_20
-R 500,2500,ref_ref,cmd1_25
-R 500,3000,ref_ref,cmd1_30
-R 500,3500,ref_ref,cmd1_35
-R 1500,2500,ref_ref,i2_25
-R 2500,2500,ref_ref,i1_25
-R 3500,2000,ref_ref,cmd0_20
-R 3500,2500,ref_ref,cmd0_25
-R 3500,3000,ref_ref,cmd0_30
-R 4000,2000,ref_ref,i0_20
-R 4000,3000,ref_ref,i0_30
-R 4500,2500,ref_ref,i0_25
-R 6000,1500,ref_ref,nq_15
-R 6000,2500,ref_ref,nq_25
-R 6000,3000,ref_ref,nq_30
-R 6000,3500,ref_ref,nq_35
-R 6000,4000,ref_ref,nq_40
-R 6000,2000,ref_ref,nq_20
-S 4300,2000,4500,2000,300,*,RIGHT,POLY
-S 4300,3000,4500,3000,300,*,RIGHT,POLY
-S 1300,2500,1500,2500,300,*,RIGHT,POLY
-S 1700,1500,1900,1500,300,*,RIGHT,POLY
-S 1700,3500,1900,3500,300,*,RIGHT,POLY
-S 500,3500,1700,3500,100,*,LEFT,ALU1
-S 500,1500,500,3500,100,*,DOWN,ALU1
-S 4000,2000,4000,2000,200,i0,LEFT,CALU1
-S 4000,3000,4000,3000,200,i0,LEFT,CALU1
-S 4500,2500,4500,2500,200,i0,LEFT,CALU1
-S 500,1500,500,3500,200,cmd1,DOWN,CALU1
-S 1500,2500,1500,2500,200,i2,LEFT,CALU1
-S 2500,2500,2500,2500,200,i1,LEFT,CALU1
-S 3500,2000,3500,3000,200,cmd0,DOWN,CALU1
-S 6000,1500,6000,4000,200,nq,DOWN,CALU1
-S 4800,400,4800,1000,300,*,UP,NDIF
-S 4800,1500,4800,1700,200,*,DOWN,ALU1
-S 400,4000,400,4600,200,*,UP,ALU1
-S 4800,3500,4800,4000,100,*,DOWN,ALU1
-S 4300,2000,4300,3000,100,*,UP,ALU1
-S 1000,4000,3200,4000,100,*,RIGHT,ALU1
-S 2200,1500,2700,1500,100,*,RIGHT,ALU1
-S 3300,1500,4800,1500,100,*,RIGHT,ALU1
-S 1700,3000,2400,3000,100,*,LEFT,ALU1
-S 6600,3000,6600,4600,200,*,UP,ALU1
-S 1700,1500,1700,2000,100,*,UP,ALU1
-S 2700,1500,2700,2000,100,*,UP,ALU1
-S 400,400,400,1000,200,*,DOWN,ALU1
-S 1000,1000,3200,1000,100,*,RIGHT,ALU1
-S 1900,1300,1900,1500,100,*,DOWN,POLY
-S 1300,1300,1300,3600,100,*,DOWN,POLY
-S 3900,3300,3900,3600,100,*,UP,POLY
-S 3900,3600,4100,3600,100,*,LEFT,POLY
-S 4500,1100,4500,2000,100,*,DOWN,POLY
-S 5100,2000,5100,2600,100,*,DOWN,POLY
-S 3400,3600,3500,3600,100,*,RIGHT,POLY
-S 3400,1500,3400,3600,100,*,UP,POLY
-S 3900,1900,3900,3300,100,*,DOWN,POLY
-S 4400,2000,4500,2000,100,*,RIGHT,POLY
-S 4500,3000,4500,3600,100,*,UP,POLY
-S 4300,3000,4500,3000,100,*,RIGHT,POLY
-S 2400,2500,2900,2500,100,*,RIGHT,POLY
-S 4100,1100,4100,1500,100,*,UP,POLY
-S 2900,1300,2900,3600,100,*,DOWN,POLY
-S 2500,1300,2500,2000,100,*,UP,POLY
-S 3500,1100,3700,1100,100,*,RIGHT,POLY
-S 3200,1500,3300,1500,100,*,LEFT,POLY
-S 2500,3000,2500,3600,100,*,UP,POLY
-S 1900,2000,2500,2000,100,*,RIGHT,POLY
-S 1900,2000,1900,3600,100,*,DOWN,POLY
-S 3900,2500,5100,2500,100,*,RIGHT,POLY
-S 3700,1100,3700,1900,100,*,DOWN,POLY
-S 3700,1900,3900,1900,100,*,LEFT,POLY
-S 400,2500,700,2500,300,*,RIGHT,POLY
-S 700,2100,700,2600,100,*,DOWN,POLY
-S 1700,1500,1900,1500,100,*,RIGHT,POLY
-S 1000,1600,1000,1900,300,*,UP,NDIF
-S 700,1400,700,2100,100,*,DOWN,NTRANS
-S 4800,1500,4800,1700,300,*,DOWN,NDIF
-S 5100,1300,5100,2000,100,*,DOWN,NTRANS
-S 1000,600,1000,1000,300,*,DOWN,NDIF
-S 1600,600,1600,1100,200,*,DOWN,NDIF
-S 2200,600,2200,1600,300,*,UP,NDIF
-S 3200,400,3200,1100,300,*,DOWN,NDIF
-S 3500,200,3500,1100,100,*,UP,NTRANS
-S 1300,400,1300,1300,100,*,UP,NTRANS
-S 2900,400,2900,1300,100,*,UP,NTRANS
-S 3800,400,3800,900,200,*,DOWN,NDIF
-S 4500,200,4500,1100,100,*,UP,NTRANS
-S 4100,200,4100,1100,100,*,UP,NTRANS
-S 1900,400,1900,1300,100,*,UP,NTRANS
-S 2500,400,2500,1300,100,*,UP,NTRANS
-S 400,1000,400,1900,300,*,DOWN,NDIF
-S 1000,2800,1000,3400,300,*,UP,PDIF
-S 5100,2600,5100,3600,100,*,UP,PTRANS
-S 700,2600,700,3600,100,*,UP,PTRANS
-S 4800,2800,4800,3400,300,*,UP,PDIF
-S 6000,2800,6000,4700,300,*,UP,PDIF
-S 5400,2800,5400,4600,300,*,DOWN,PDIF
-S 5700,2600,5700,4900,100,*,UP,PTRANS
-S 1900,3600,1900,4900,100,*,UP,PTRANS
-S 2200,3500,2200,4700,300,*,UP,PDIF
-S 1600,3800,1600,4700,200,*,DOWN,PDIF
-S 1300,3600,1300,4900,100,*,UP,PTRANS
-S 1000,3800,1000,4700,300,*,UP,PDIF
-S 2900,3600,2900,4900,100,*,UP,PTRANS
-S 3200,3800,3200,4700,200,*,UP,PDIF
-S 4500,3600,4500,4900,100,*,UP,PTRANS
-S 4800,3800,4800,4700,300,*,UP,PDIF
-S 4100,3600,4100,4900,100,*,UP,PTRANS
-S 3500,3600,3500,4900,100,*,UP,PTRANS
-S 3800,3800,3800,4700,200,*,UP,PDIF
-S 2500,3600,2500,4900,100,*,UP,PTRANS
-S 6300,2600,6300,4900,100,*,UP,PTRANS
-S 6600,2800,6600,4700,300,*,UP,PDIF
-S 400,2800,400,4000,300,*,UP,PDIF
-S 1000,1800,1000,3000,100,*,UP,ALU1
-S 1000,3000,1700,3000,100,*,LEFT,ALU1
-S 3500,2000,3500,3000,100,*,DOWN,ALU1
-S 4000,3000,4300,3000,200,*,RIGHT,ALU1
-S 4000,2000,4300,2000,200,*,RIGHT,ALU1
-S 4300,2500,4500,2500,200,*,LEFT,ALU1
-S 5500,1000,5500,3500,100,*,DOWN,ALU1
-S 4800,1000,5500,1000,100,*,RIGHT,ALU1
-S 2200,3500,5500,3500,100,*,RIGHT,ALU1
-S 4800,1750,5000,1750,100,*,LEFT,ALU1
-S 4800,2950,5000,2950,100,*,RIGHT,ALU1
-S 5000,1750,5000,2950,100,*,DOWN,ALU1
-S 3500,2500,3800,2500,200,*,RIGHT,ALU1
-S 3000,2000,3000,3500,100,*,UP,ALU1
-S 2700,2000,3000,2000,100,*,RIGHT,ALU1
-S 2000,2000,2000,3000,100,*,UP,ALU1
-S 1700,2000,2000,2000,100,*,RIGHT,ALU1
-S 2000,2950,2400,2950,100,*,RIGHT,ALU1
-S 0,300,7500,300,600,vss,RIGHT,CALU1
-S 0,3900,7500,3900,2400,*,RIGHT,NWELL
-S 0,4700,7500,4700,600,vdd,RIGHT,CALU1
-S 6900,2600,6900,3900,100,*,UP,PTRANS
-S 7200,2800,7200,3700,300,*,DOWN,PDIF
-S 6700,2500,6700,2600,100,*,UP,POLY
-S 6700,2600,6900,2600,100,*,RIGHT,POLY
-S 6300,1400,6300,2600,100,*,DOWN,POLY
-S 6700,1500,6700,1600,100,*,UP,POLY
-S 6700,1500,6900,1500,100,*,LEFT,POLY
-S 7200,900,7200,1300,300,*,DOWN,NDIF
-S 6300,200,6300,1500,100,*,DOWN,NTRANS
-S 6600,400,6600,1300,300,*,DOWN,NDIF
-S 6900,700,6900,1500,100,*,DOWN,NTRANS
-S 5700,200,5700,1500,100,*,DOWN,NTRANS
-S 5500,1000,6700,1000,100,*,RIGHT,ALU1
-S 6700,1000,6700,2500,100,*,UP,ALU1
-S 5400,500,5400,1800,300,*,DOWN,NDIF
-S 6000,1450,6000,4000,200,*,DOWN,ALU1
-S 5700,1500,5700,2600,100,*,DOWN,POLY
-S 5700,2100,7200,2100,100,*,RIGHT,POLY
-S 7200,1100,7200,3500,100,*,DOWN,ALU1
-S 6000,400,6000,1500,300,*,UP,NDIF
-V 3800,2500,CONT_POLY,*
-V 4300,2000,CONT_POLY,*
-V 4300,3000,CONT_POLY,*
-V 1700,1500,CONT_POLY,*
-V 3300,1500,CONT_POLY,*
-V 4100,1500,CONT_POLY,*
-V 1700,3500,CONT_POLY,*
-V 2400,3000,CONT_POLY,*
-V 400,2500,CONT_POLY,*
-V 400,400,CONT_BODY_P,*
-V 4800,1700,CONT_DIF_N,*
-V 1000,1800,CONT_DIF_N,*
-V 1000,1800,CONT_DIF_N,*
-V 2200,1500,CONT_DIF_N,*
-V 5400,500,CONT_DIF_N,*
-V 3800,500,CONT_DIF_N,*
-V 1000,1000,CONT_DIF_N,*
-V 4800,1000,CONT_DIF_N,*
-V 3200,1000,CONT_DIF_N,*
-V 400,1000,CONT_DIF_N,*
-V 1000,3000,CONT_DIF_P,*
-V 6600,3000,CONT_DIF_P,*
-V 6600,3500,CONT_DIF_P,*
-V 6600,4000,CONT_DIF_P,*
-V 6000,3000,CONT_DIF_P,*
-V 6000,4000,CONT_DIF_P,*
-V 6000,3500,CONT_DIF_P,*
-V 5400,4600,CONT_DIF_P,*
-V 4800,3000,CONT_DIF_P,*
-V 6600,4600,CONT_DIF_P,*
-V 4800,4000,CONT_DIF_P,*
-V 1000,4000,CONT_DIF_P,*
-V 2200,3500,CONT_DIF_P,*
-V 3800,4500,CONT_DIF_P,*
-V 3200,4000,CONT_DIF_P,*
-V 400,4600,CONT_BODY_N,*
-V 400,4000,CONT_DIF_P,*
-V 1500,2500,CONT_POLY,*
-V 2500,2500,CONT_POLY,*
-V 7200,3000,CONT_DIF_P,*
-V 7200,3500,CONT_DIF_P,*
-V 6700,2500,CONT_POLY,*
-V 7200,2100,CONT_POLY,*
-V 6700,1600,CONT_POLY,*
-V 7200,400,CONT_BODY_P,*
-V 7200,1100,CONT_DIF_N,*
-V 6600,500,CONT_DIF_N,*
-V 6000,1500,CONT_DIF_N,*
-V 7200,4600,CONT_BODY_N,*
-EOF
diff --git a/alliance/share/cells/sxlib/nmx3_x4.vbe b/alliance/share/cells/sxlib/nmx3_x4.vbe
deleted file mode 100644
index 1db2d242..00000000
--- a/alliance/share/cells/sxlib/nmx3_x4.vbe
+++ /dev/null
@@ -1,59 +0,0 @@
-ENTITY nmx3_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 3750;
-  CONSTANT cin_cmd0	 : NATURAL := 15;
-  CONSTANT cin_cmd1	 : NATURAL := 15;
-  CONSTANT cin_i0	 : NATURAL := 9;
-  CONSTANT cin_i1	 : NATURAL := 8;
-  CONSTANT cin_i2	 : NATURAL := 8;
-  CONSTANT rdown_cmd0_nq	 : NATURAL := 810;
-  CONSTANT rdown_cmd0_nq	 : NATURAL := 810;
-  CONSTANT rdown_cmd1_nq	 : NATURAL := 810;
-  CONSTANT rdown_cmd1_nq	 : NATURAL := 810;
-  CONSTANT rdown_i0_nq	 : NATURAL := 810;
-  CONSTANT rdown_i1_nq	 : NATURAL := 810;
-  CONSTANT rdown_i2_nq	 : NATURAL := 810;
-  CONSTANT rup_cmd0_nq	 : NATURAL := 890;
-  CONSTANT rup_cmd0_nq	 : NATURAL := 890;
-  CONSTANT rup_cmd1_nq	 : NATURAL := 890;
-  CONSTANT rup_cmd1_nq	 : NATURAL := 890;
-  CONSTANT rup_i0_nq	 : NATURAL := 890;
-  CONSTANT rup_i1_nq	 : NATURAL := 890;
-  CONSTANT rup_i2_nq	 : NATURAL := 890;
-  CONSTANT tphl_i0_nq	 : NATURAL := 748;
-  CONSTANT tphl_cmd0_nq	 : NATURAL := 790;
-  CONSTANT tphl_cmd1_nq	 : NATURAL := 866;
-  CONSTANT tphl_i1_nq	 : NATURAL := 869;
-  CONSTANT tphl_i2_nq	 : NATURAL := 869;
-  CONSTANT tplh_i0_nq	 : NATURAL := 900;
-  CONSTANT tplh_cmd0_nq	 : NATURAL := 936;
-  CONSTANT tpll_cmd1_nq	 : NATURAL := 952;
-  CONSTANT tphh_cmd1_nq	 : NATURAL := 981;
-  CONSTANT tpll_cmd0_nq	 : NATURAL := 993;
-  CONSTANT tphh_cmd0_nq	 : NATURAL := 1041;
-  CONSTANT tplh_cmd1_nq	 : NATURAL := 1048;
-  CONSTANT tplh_i1_nq	 : NATURAL := 1053;
-  CONSTANT tplh_i2_nq	 : NATURAL := 1053;
-  CONSTANT transistors	 : NATURAL := 24
-);
-PORT (
-  cmd0	 : in  BIT;
-  cmd1	 : in  BIT;
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END nmx3_x4;
-
-ARCHITECTURE behaviour_data_flow OF nmx3_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on nmx3_x4"
-  SEVERITY WARNING;
-  nq <= not (((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not
-  (cmd1) and i2))))) after 1700 ps;
-END;
diff --git a/alliance/share/cells/sxlib/nmx3_x4.vhd b/alliance/share/cells/sxlib/nmx3_x4.vhd
deleted file mode 100644
index ae619dda..00000000
--- a/alliance/share/cells/sxlib/nmx3_x4.vhd
+++ /dev/null
@@ -1,23 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY nmx3_x4 IS
-PORT(
-  cmd0	: IN STD_LOGIC;
-  cmd1	: IN STD_LOGIC;
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END nmx3_x4;
-
-ARCHITECTURE RTL OF nmx3_x4 IS
-BEGIN
-  nq <= NOT(((NOT(cmd0) AND i0) OR (cmd0 AND ((cmd1 AND i1) OR (NOT(cmd1) AND i2)))));
-END RTL;
diff --git a/alliance/share/cells/sxlib/no2_x1.al b/alliance/share/cells/sxlib/no2_x1.al
deleted file mode 100644
index 827dc1ee..00000000
--- a/alliance/share/cells/sxlib/no2_x1.al
+++ /dev/null
@@ -1,24 +0,0 @@
-V ALLIANCE : 6
-H no2_x1,L,30/10/99
-C i0,IN,EXTERNAL,5
-C i1,IN,EXTERNAL,6
-C nq,OUT,EXTERNAL,2
-C vdd,IN,EXTERNAL,3
-C vss,IN,EXTERNAL,1
-T P,0.35,5.9,4,6,2,0,0.75,0.75,13.3,13.3,3,11.25,tr_00004
-T P,0.35,5.9,3,5,4,0,0.75,0.75,13.3,13.3,4.2,11.25,tr_00003
-T N,0.35,1.4,2,5,1,0,0.75,0.75,4.3,4.3,3.9,3,tr_00002
-T N,0.35,1.4,1,6,2,0,0.75,0.75,4.3,4.3,2.1,3,tr_00001
-S 6,EXTERNAL,i1
-Q 0.00303982
-S 5,EXTERNAL,i0
-Q 0.00343734
-S 4,INTERNAL
-Q 0
-S 3,EXTERNAL,vdd
-Q 0.0026442
-S 2,EXTERNAL,nq
-Q 0.00305526
-S 1,EXTERNAL,vss
-Q 0.00299673
-EOF
diff --git a/alliance/share/cells/sxlib/no2_x1.ap b/alliance/share/cells/sxlib/no2_x1.ap
deleted file mode 100644
index 2adf55c9..00000000
--- a/alliance/share/cells/sxlib/no2_x1.ap
+++ /dev/null
@@ -1,61 +0,0 @@
-V ALLIANCE : 6
-H no2_x1,P,30/ 8/2000,100
-A 0,0,2000,5000
-R 1500,4000,ref_ref,i0_40
-R 1500,3500,ref_ref,i0_35
-R 1500,3000,ref_ref,i0_30
-R 1500,2500,ref_ref,i0_25
-R 1500,2000,ref_ref,i0_20
-R 1500,1500,ref_ref,i0_15
-R 1000,1500,ref_ref,i1_15
-R 1000,2000,ref_ref,i1_20
-R 1000,2500,ref_ref,i1_25
-R 1000,3000,ref_ref,i1_30
-R 1000,3500,ref_ref,i1_35
-R 1000,4000,ref_ref,i1_40
-R 500,1500,ref_ref,nq_15
-R 500,2000,ref_ref,nq_20
-R 500,2500,ref_ref,nq_25
-R 500,3000,ref_ref,nq_30
-R 500,3500,ref_ref,nq_35
-R 500,4000,ref_ref,nq_40
-R 500,1000,ref_ref,nq_10
-R 1500,1000,ref_ref,i0_10
-S 1000,1500,1000,4000,200,i1,DOWN,CALU1
-S 500,1000,500,4000,200,nq,DOWN,CALU1
-S 1500,1000,1500,4000,200,i0,DOWN,CALU1
-S 0,3900,2000,3900,2400,*,RIGHT,NWELL
-S 500,2800,500,4200,300,*,DOWN,PDIF
-S 1000,1500,1000,4000,100,*,UP,ALU1
-S 1000,2600,1000,4900,100,*,UP,PTRANS
-S 700,2800,700,4200,300,*,DOWN,PDIF
-S 1400,2600,1400,4900,100,*,UP,PTRANS
-S 0,4700,2000,4700,600,vdd,RIGHT,CALU1
-S 1500,1000,1500,4000,100,*,UP,ALU1
-S 0,300,2000,300,600,vss,RIGHT,CALU1
-S 1700,2800,1700,4700,300,*,UP,PDIF
-S 700,2400,1000,2400,100,*,LEFT,POLY
-S 1300,1900,1500,1900,100,*,LEFT,POLY
-S 700,1400,700,2400,100,*,DOWN,POLY
-S 400,400,400,1200,300,*,UP,NDIF
-S 1600,400,1600,1200,300,*,UP,NDIF
-S 1300,600,1300,1400,100,*,DOWN,NTRANS
-S 1000,800,1000,1200,300,*,UP,NDIF
-S 700,600,700,1400,100,*,DOWN,NTRANS
-S 1400,2050,1400,2600,100,*,DOWN,POLY
-S 1300,1400,1300,2000,100,*,UP,POLY
-S 450,1000,1000,1000,200,*,LEFT,ALU1
-S 500,950,500,4000,200,*,DOWN,ALU1
-V 500,4000,CONT_DIF_P,*
-V 500,3500,CONT_DIF_P,*
-V 500,3000,CONT_DIF_P,*
-V 300,4700,CONT_BODY_N,*
-V 1700,4500,CONT_DIF_P,*
-V 1000,300,CONT_BODY_P,*
-V 1000,1000,CONT_DIF_N,*
-V 1600,500,CONT_DIF_N,*
-V 400,500,CONT_DIF_N,*
-V 1600,500,CONT_DIF_N,*
-V 1000,2500,CONT_POLY,*
-V 1500,2000,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/sxlib/no2_x1.sym b/alliance/share/cells/sxlib/no2_x1.sym
deleted file mode 100644
index 0736b807..00000000
Binary files a/alliance/share/cells/sxlib/no2_x1.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/no2_x1.vbe b/alliance/share/cells/sxlib/no2_x1.vbe
deleted file mode 100644
index 37a91f3f..00000000
--- a/alliance/share/cells/sxlib/no2_x1.vbe
+++ /dev/null
@@ -1,32 +0,0 @@
-ENTITY no2_x1 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 1000;
-  CONSTANT cin_i0	 : NATURAL := 12;
-  CONSTANT cin_i1	 : NATURAL := 12;
-  CONSTANT rdown_i0_nq	 : NATURAL := 3640;
-  CONSTANT rdown_i1_nq	 : NATURAL := 3640;
-  CONSTANT rup_i0_nq	 : NATURAL := 3210;
-  CONSTANT rup_i1_nq	 : NATURAL := 3210;
-  CONSTANT tplh_i0_nq	 : NATURAL := 121;
-  CONSTANT tplh_i1_nq	 : NATURAL := 161;
-  CONSTANT tphl_i1_nq	 : NATURAL := 193;
-  CONSTANT tphl_i0_nq	 : NATURAL := 298;
-  CONSTANT transistors	 : NATURAL := 4
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END no2_x1;
-
-ARCHITECTURE behaviour_data_flow OF no2_x1 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on no2_x1"
-  SEVERITY WARNING;
-  nq <= not ((i0 or i1)) after 900 ps;
-END;
diff --git a/alliance/share/cells/sxlib/no2_x1.vhd b/alliance/share/cells/sxlib/no2_x1.vhd
deleted file mode 100644
index 095b74bf..00000000
--- a/alliance/share/cells/sxlib/no2_x1.vhd
+++ /dev/null
@@ -1,20 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY no2_x1 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END no2_x1;
-
-ARCHITECTURE RTL OF no2_x1 IS
-BEGIN
-  nq <= NOT((i0 OR i1));
-END RTL;
diff --git a/alliance/share/cells/sxlib/no2_x4.al b/alliance/share/cells/sxlib/no2_x4.al
deleted file mode 100644
index 368b9380..00000000
--- a/alliance/share/cells/sxlib/no2_x4.al
+++ /dev/null
@@ -1,34 +0,0 @@
-V ALLIANCE : 6
-H no2_x4,L,30/10/99
-C i0,IN,EXTERNAL,8
-C i1,IN,EXTERNAL,7
-C nq,OUT,EXTERNAL,3
-C vdd,IN,EXTERNAL,4
-C vss,IN,EXTERNAL,2
-T P,0.35,5.9,4,8,5,0,0.75,0.75,13.3,13.3,3,11.25,tr_00010
-T P,0.35,5.9,5,7,1,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00009
-T P,0.35,5.9,3,6,4,0,0.75,0.75,13.3,13.3,6.9,11.25,tr_00008
-T P,0.35,5.9,4,6,3,0,0.75,0.75,13.3,13.3,5.1,11.25,tr_00007
-T P,0.35,2.9,4,1,6,0,0.75,0.75,7.3,7.3,8.7,9.75,tr_00006
-T N,0.35,1.4,1,8,2,0,0.75,0.75,4.3,4.3,3.6,3,tr_00005
-T N,0.35,1.4,2,7,1,0,0.75,0.75,4.3,4.3,1.8,3,tr_00004
-T N,0.35,1.4,6,1,2,0,0.75,0.75,4.3,4.3,8.7,3,tr_00003
-T N,0.35,2.9,2,6,3,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00002
-T N,0.35,2.9,3,6,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00001
-S 8,EXTERNAL,i0
-Q 0.00275797
-S 7,EXTERNAL,i1
-Q 0.00260759
-S 6,INTERNAL
-Q 0.00628215
-S 5,INTERNAL
-Q 0
-S 4,EXTERNAL,vdd
-Q 0.00384489
-S 3,EXTERNAL,nq
-Q 0.00214456
-S 2,EXTERNAL,vss
-Q 0.0046087
-S 1,INTERNAL
-Q 0.00676363
-EOF
diff --git a/alliance/share/cells/sxlib/no2_x4.ap b/alliance/share/cells/sxlib/no2_x4.ap
deleted file mode 100644
index 8e38eb36..00000000
--- a/alliance/share/cells/sxlib/no2_x4.ap
+++ /dev/null
@@ -1,89 +0,0 @@
-V ALLIANCE : 6
-H no2_x4,P,30/ 8/2000,100
-A 0,0,3500,5000
-R 2000,1000,ref_ref,nq_10
-R 500,3500,ref_ref,i1_35
-R 500,3000,ref_ref,i1_30
-R 500,2500,ref_ref,i1_25
-R 500,2000,ref_ref,i1_20
-R 500,1500,ref_ref,i1_15
-R 1000,1500,ref_ref,i0_15
-R 1000,2000,ref_ref,i0_20
-R 1000,2500,ref_ref,i0_25
-R 1000,3000,ref_ref,i0_30
-R 1000,3500,ref_ref,i0_35
-R 2000,3500,ref_ref,nq_35
-R 2000,3000,ref_ref,nq_30
-R 2000,2500,ref_ref,nq_25
-R 2000,2000,ref_ref,nq_20
-R 2000,1500,ref_ref,nq_15
-S 500,1500,500,3500,200,i1,DOWN,CALU1
-S 1000,1500,1000,3500,200,i0,DOWN,CALU1
-S 2000,1000,2000,3500,200,nq,DOWN,CALU1
-S 300,500,300,1000,200,*,DOWN,ALU1
-S 2000,950,2000,3500,200,*,DOWN,ALU1
-S 3200,3000,3200,3500,100,*,DOWN,ALU1
-S 900,2400,1200,2400,100,*,LEFT,POLY
-S 1200,1400,1200,2400,100,*,UP,POLY
-S 1500,300,1500,1200,300,*,UP,NDIF
-S 900,1000,1500,1000,100,*,LEFT,ALU1
-S 1200,600,1200,1400,100,*,DOWN,NTRANS
-S 900,800,900,1200,300,*,UP,NDIF
-S 600,600,600,1400,100,*,DOWN,NTRANS
-S 300,400,300,1200,300,*,UP,NDIF
-S 600,1400,600,2600,100,*,DOWN,POLY
-S 1300,2800,1300,4700,300,*,DOWN,PDIF
-S 1000,2600,1000,4900,100,*,UP,PTRANS
-S 600,2600,600,4900,100,*,UP,PTRANS
-S 300,4000,2700,4000,100,*,RIGHT,ALU1
-S 300,2800,300,4700,300,*,DOWN,PDIF
-S 0,300,3500,300,600,vss,RIGHT,CALU1
-S 0,4700,3500,4700,600,vdd,RIGHT,CALU1
-S 2500,2000,3200,2000,100,*,RIGHT,ALU1
-S 2600,2500,2900,2500,300,*,RIGHT,POLY
-S 1700,2000,2600,2000,300,*,RIGHT,POLY
-S 1800,1400,1800,2100,100,*,DOWN,POLY
-S 1700,1900,1700,2600,100,*,UP,POLY
-S 2300,1900,2300,2600,100,*,DOWN,POLY
-S 2400,1400,2400,2100,100,*,UP,POLY
-S 2700,2500,2700,4000,100,*,DOWN,ALU1
-S 2900,1400,2900,2600,100,*,DOWN,POLY
-S 2100,300,2100,1200,300,*,DOWN,NDIF
-S 500,1500,500,3500,100,*,UP,ALU1
-S 1000,1500,1000,3500,100,*,UP,ALU1
-S 1500,1000,1500,4000,100,*,UP,ALU1
-S 2600,300,2600,1200,300,*,DOWN,NDIF
-S 2900,600,2900,1400,100,*,UP,NTRANS
-S 3200,800,3200,1200,300,*,DOWN,NDIF
-S 3200,2800,3200,3700,300,*,UP,PDIF
-S 2300,2600,2300,4900,100,*,DOWN,PTRANS
-S 1700,2600,1700,4900,100,*,DOWN,PTRANS
-S 2000,2800,2000,4700,300,*,UP,PDIF
-S 2600,2800,2600,4700,300,*,UP,PDIF
-S 2900,2600,2900,3900,100,*,DOWN,PTRANS
-S 1400,2800,1400,4700,300,*,UP,PDIF
-S 3200,1000,3200,3000,100,*,UP,ALU1
-S 2400,100,2400,1400,100,*,UP,NTRANS
-S 1800,100,1800,1400,100,*,UP,NTRANS
-S 0,3900,3500,3900,2400,*,RIGHT,NWELL
-V 300,1000,CONT_DIF_N,*
-V 3200,3500,CONT_DIF_P,*
-V 1500,400,CONT_DIF_N,*
-V 900,300,CONT_BODY_P,*
-V 900,1000,CONT_DIF_N,*
-V 300,500,CONT_DIF_N,*
-V 300,4000,CONT_DIF_P,*
-V 2500,2000,CONT_POLY,*
-V 2100,1000,CONT_DIF_N,*
-V 1000,2500,CONT_POLY,*
-V 500,2000,CONT_POLY,*
-V 3200,1000,CONT_DIF_N,*
-V 1400,4500,CONT_DIF_P,*
-V 2600,4500,CONT_DIF_P,*
-V 3200,3000,CONT_DIF_P,*
-V 3200,4700,CONT_BODY_N,*
-V 2700,2500,CONT_POLY,*
-V 2700,300,CONT_DIF_N,*
-V 2000,3000,CONT_DIF_P,*
-V 2000,3500,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/no2_x4.sym b/alliance/share/cells/sxlib/no2_x4.sym
deleted file mode 100644
index dfc6d710..00000000
Binary files a/alliance/share/cells/sxlib/no2_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/no2_x4.vbe b/alliance/share/cells/sxlib/no2_x4.vbe
deleted file mode 100644
index 5060db0e..00000000
--- a/alliance/share/cells/sxlib/no2_x4.vbe
+++ /dev/null
@@ -1,32 +0,0 @@
-ENTITY no2_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 1750;
-  CONSTANT cin_i0	 : NATURAL := 12;
-  CONSTANT cin_i1	 : NATURAL := 11;
-  CONSTANT rdown_i0_nq	 : NATURAL := 810;
-  CONSTANT rdown_i1_nq	 : NATURAL := 810;
-  CONSTANT rup_i0_nq	 : NATURAL := 890;
-  CONSTANT rup_i1_nq	 : NATURAL := 890;
-  CONSTANT tplh_i0_nq	 : NATURAL := 447;
-  CONSTANT tplh_i1_nq	 : NATURAL := 504;
-  CONSTANT tphl_i1_nq	 : NATURAL := 522;
-  CONSTANT tphl_i0_nq	 : NATURAL := 618;
-  CONSTANT transistors	 : NATURAL := 10
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END no2_x4;
-
-ARCHITECTURE behaviour_data_flow OF no2_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on no2_x4"
-  SEVERITY WARNING;
-  nq <= not ((i0 or i1)) after 1200 ps;
-END;
diff --git a/alliance/share/cells/sxlib/no2_x4.vhd b/alliance/share/cells/sxlib/no2_x4.vhd
deleted file mode 100644
index 43e59322..00000000
--- a/alliance/share/cells/sxlib/no2_x4.vhd
+++ /dev/null
@@ -1,20 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY no2_x4 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END no2_x4;
-
-ARCHITECTURE RTL OF no2_x4 IS
-BEGIN
-  nq <= NOT((i0 OR i1));
-END RTL;
diff --git a/alliance/share/cells/sxlib/no3_x1.al b/alliance/share/cells/sxlib/no3_x1.al
deleted file mode 100644
index ff99b0b4..00000000
--- a/alliance/share/cells/sxlib/no3_x1.al
+++ /dev/null
@@ -1,31 +0,0 @@
-V ALLIANCE : 6
-H no3_x1,L,30/10/99
-C i0,IN,EXTERNAL,6
-C i1,IN,EXTERNAL,7
-C i2,IN,EXTERNAL,8
-C nq,OUT,EXTERNAL,1
-C vdd,IN,EXTERNAL,4
-C vss,IN,EXTERNAL,2
-T P,0.35,5.9,5,6,3,0,0.75,0.75,13.3,13.3,4.2,11.25,tr_00006
-T P,0.35,5.9,3,7,1,0,0.75,0.75,13.3,13.3,3,11.25,tr_00005
-T P,0.35,5.9,4,8,5,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00004
-T N,0.35,1.4,1,7,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00003
-T N,0.35,1.4,1,8,2,0,0.75,0.75,4.3,4.3,5.4,3,tr_00002
-T N,0.35,1.4,2,6,1,0,0.75,0.75,4.3,4.3,3.6,3,tr_00001
-S 8,EXTERNAL,i2
-Q 0.00361086
-S 7,EXTERNAL,i1
-Q 0.00317863
-S 6,EXTERNAL,i0
-Q 0.0032596
-S 5,INTERNAL
-Q 0
-S 4,EXTERNAL,vdd
-Q 0.00298567
-S 3,INTERNAL
-Q 0
-S 2,EXTERNAL,vss
-Q 0.0033382
-S 1,EXTERNAL,nq
-Q 0.00381907
-EOF
diff --git a/alliance/share/cells/sxlib/no3_x1.ap b/alliance/share/cells/sxlib/no3_x1.ap
deleted file mode 100644
index 7d5a3e3c..00000000
--- a/alliance/share/cells/sxlib/no3_x1.ap
+++ /dev/null
@@ -1,78 +0,0 @@
-V ALLIANCE : 6
-H no3_x1,P,30/ 8/2000,100
-A 0,0,2500,5000
-R 2000,1000,ref_ref,i2_10
-R 500,4000,ref_ref,nq_40
-R 500,3500,ref_ref,nq_35
-R 500,3000,ref_ref,nq_30
-R 500,2500,ref_ref,nq_25
-R 500,2000,ref_ref,nq_20
-R 500,1500,ref_ref,nq_15
-R 1000,4000,ref_ref,i1_40
-R 1000,3500,ref_ref,i1_35
-R 1000,3000,ref_ref,i1_30
-R 1000,2500,ref_ref,i1_25
-R 1000,2000,ref_ref,i1_20
-R 1000,1500,ref_ref,i1_15
-R 1500,1500,ref_ref,i0_15
-R 1500,2000,ref_ref,i0_20
-R 1500,2500,ref_ref,i0_25
-R 1500,3000,ref_ref,i0_30
-R 1500,3500,ref_ref,i0_35
-R 1500,4000,ref_ref,i0_40
-R 2000,1500,ref_ref,i2_15
-R 2000,2000,ref_ref,i2_20
-R 2000,2500,ref_ref,i2_25
-R 2000,3000,ref_ref,i2_30
-R 2000,3500,ref_ref,i2_35
-R 2000,4000,ref_ref,i2_40
-R 500,1000,ref_ref,nq_10
-S 1000,1500,1000,4000,200,i1,DOWN,CALU1
-S 1500,1500,1500,4000,200,i0,DOWN,CALU1
-S 2000,1000,2000,4000,200,i2,DOWN,CALU1
-S 500,1000,500,4000,200,nq,DOWN,CALU1
-S 300,1000,500,1000,200,*,RIGHT,ALU1
-S 2000,1000,2000,4000,100,*,UP,ALU1
-S 1500,800,1500,1200,300,*,UP,NDIF
-S 2100,400,2100,1200,300,*,UP,NDIF
-S 300,800,300,1200,300,*,UP,NDIF
-S 900,400,900,1200,300,*,UP,NDIF
-S 2100,2800,2100,4700,300,*,DOWN,PDIF
-S 0,300,2500,300,600,vss,RIGHT,CALU1
-S 0,4700,2500,4700,600,vdd,RIGHT,CALU1
-S 600,600,600,1400,100,*,DOWN,NTRANS
-S 1800,600,1800,1400,100,*,DOWN,NTRANS
-S 1200,600,1200,1400,100,*,DOWN,NTRANS
-S 1400,2600,1400,4900,100,*,UP,PTRANS
-S 700,2800,700,4200,300,*,DOWN,PDIF
-S 1000,2600,1000,4900,100,*,UP,PTRANS
-S 1000,1500,1000,4000,100,*,UP,ALU1
-S 500,2800,500,4200,300,*,DOWN,PDIF
-S 1500,1500,1500,4000,100,*,UP,ALU1
-S 1800,2600,1800,4900,100,*,UP,PTRANS
-S 600,2400,1100,2400,100,*,LEFT,POLY
-S 600,1400,600,2400,100,*,DOWN,POLY
-S 1400,2000,1400,2600,100,*,DOWN,POLY
-S 1800,2600,1900,2600,100,*,RIGHT,POLY
-S 1900,1400,1900,2600,100,*,DOWN,POLY
-S 1800,1400,2100,1400,100,*,RIGHT,POLY
-S 1200,1900,1600,1900,100,*,LEFT,POLY
-S 1200,1400,1200,1900,100,*,DOWN,POLY
-S 0,3900,2500,3900,2400,*,RIGHT,NWELL
-S 300,1000,1500,1000,200,*,LEFT,ALU1
-S 500,1000,500,4000,200,*,DOWN,ALU1
-V 2100,500,CONT_DIF_N,*
-V 1500,300,CONT_BODY_P,*
-V 300,300,CONT_BODY_P,*
-V 900,500,CONT_DIF_N,*
-V 300,1000,CONT_DIF_N,*
-V 1500,1000,CONT_DIF_N,*
-V 2100,4500,CONT_DIF_P,*
-V 300,4700,CONT_BODY_N,*
-V 500,3000,CONT_DIF_P,*
-V 500,3500,CONT_DIF_P,*
-V 500,4000,CONT_DIF_P,*
-V 1000,2500,CONT_POLY,*
-V 2000,1500,CONT_POLY,*
-V 1500,2000,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/sxlib/no3_x1.sym b/alliance/share/cells/sxlib/no3_x1.sym
deleted file mode 100644
index ca5f63b1..00000000
Binary files a/alliance/share/cells/sxlib/no3_x1.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/no3_x1.vbe b/alliance/share/cells/sxlib/no3_x1.vbe
deleted file mode 100644
index 6711f8b1..00000000
--- a/alliance/share/cells/sxlib/no3_x1.vbe
+++ /dev/null
@@ -1,38 +0,0 @@
-ENTITY no3_x1 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 1250;
-  CONSTANT cin_i0	 : NATURAL := 12;
-  CONSTANT cin_i1	 : NATURAL := 12;
-  CONSTANT cin_i2	 : NATURAL := 12;
-  CONSTANT rdown_i0_nq	 : NATURAL := 3640;
-  CONSTANT rdown_i1_nq	 : NATURAL := 3640;
-  CONSTANT rdown_i2_nq	 : NATURAL := 3640;
-  CONSTANT rup_i0_nq	 : NATURAL := 4690;
-  CONSTANT rup_i1_nq	 : NATURAL := 4690;
-  CONSTANT rup_i2_nq	 : NATURAL := 4690;
-  CONSTANT tplh_i2_nq	 : NATURAL := 192;
-  CONSTANT tphl_i1_nq	 : NATURAL := 215;
-  CONSTANT tplh_i1_nq	 : NATURAL := 243;
-  CONSTANT tplh_i0_nq	 : NATURAL := 246;
-  CONSTANT tphl_i0_nq	 : NATURAL := 318;
-  CONSTANT tphl_i2_nq	 : NATURAL := 407;
-  CONSTANT transistors	 : NATURAL := 6
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END no3_x1;
-
-ARCHITECTURE behaviour_data_flow OF no3_x1 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on no3_x1"
-  SEVERITY WARNING;
-  nq <= not (((i0 or i1) or i2)) after 1000 ps;
-END;
diff --git a/alliance/share/cells/sxlib/no3_x1.vhd b/alliance/share/cells/sxlib/no3_x1.vhd
deleted file mode 100644
index 9ba7168a..00000000
--- a/alliance/share/cells/sxlib/no3_x1.vhd
+++ /dev/null
@@ -1,21 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY no3_x1 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END no3_x1;
-
-ARCHITECTURE RTL OF no3_x1 IS
-BEGIN
-  nq <= NOT(((i0 OR i1) OR i2));
-END RTL;
diff --git a/alliance/share/cells/sxlib/no3_x4.al b/alliance/share/cells/sxlib/no3_x4.al
deleted file mode 100644
index 1ec48c9c..00000000
--- a/alliance/share/cells/sxlib/no3_x4.al
+++ /dev/null
@@ -1,41 +0,0 @@
-V ALLIANCE : 6
-H no3_x4,L,30/10/99
-C i0,IN,EXTERNAL,8
-C i1,IN,EXTERNAL,9
-C i2,IN,EXTERNAL,10
-C nq,OUT,EXTERNAL,1
-C vdd,IN,EXTERNAL,4
-C vss,IN,EXTERNAL,2
-T P,0.35,2.9,4,3,7,0,0.75,0.75,7.3,7.3,10.2,9.75,tr_00012
-T P,0.35,5.9,4,7,1,0,0.75,0.75,13.3,13.3,6.6,11.25,tr_00011
-T P,0.35,5.9,1,7,4,0,0.75,0.75,13.3,13.3,8.4,11.25,tr_00010
-T P,0.35,5.9,6,10,3,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00009
-T P,0.35,5.9,5,9,6,0,0.75,0.75,13.3,13.3,3,11.25,tr_00008
-T P,0.35,5.9,4,8,5,0,0.75,0.75,13.3,13.3,4.2,11.25,tr_00007
-T N,0.35,2.9,1,7,2,0,0.75,0.75,7.3,7.3,6.9,2.25,tr_00006
-T N,0.35,2.9,2,7,1,0,0.75,0.75,7.3,7.3,8.7,2.25,tr_00005
-T N,0.35,1.4,7,3,2,0,0.75,0.75,4.3,4.3,10.2,3,tr_00004
-T N,0.35,1.4,2,9,3,0,0.75,0.75,4.3,4.3,3.6,3,tr_00003
-T N,0.35,1.4,3,8,2,0,0.75,0.75,4.3,4.3,5.4,3,tr_00002
-T N,0.35,1.4,3,10,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00001
-S 10,EXTERNAL,i2
-Q 0.00260759
-S 9,EXTERNAL,i1
-Q 0.00282737
-S 8,EXTERNAL,i0
-Q 0.00282737
-S 7,INTERNAL
-Q 0.00571129
-S 6,INTERNAL
-Q 0
-S 5,INTERNAL
-Q 0
-S 4,EXTERNAL,vdd
-Q 0.00418636
-S 3,INTERNAL
-Q 0.00784181
-S 2,EXTERNAL,vss
-Q 0.00436263
-S 1,EXTERNAL,nq
-Q 0.00214456
-EOF
diff --git a/alliance/share/cells/sxlib/no3_x4.ap b/alliance/share/cells/sxlib/no3_x4.ap
deleted file mode 100644
index 79e688d5..00000000
--- a/alliance/share/cells/sxlib/no3_x4.ap
+++ /dev/null
@@ -1,99 +0,0 @@
-V ALLIANCE : 6
-H no3_x4,P,30/ 8/2000,100
-A 0,0,4000,5000
-R 2500,1500,ref_ref,nq_15
-R 2500,2000,ref_ref,nq_20
-R 2500,2500,ref_ref,nq_25
-R 2500,3000,ref_ref,nq_30
-R 2500,3500,ref_ref,nq_35
-R 1500,3500,ref_ref,i0_35
-R 1500,3000,ref_ref,i0_30
-R 1500,2500,ref_ref,i0_25
-R 1500,2000,ref_ref,i0_20
-R 1500,1500,ref_ref,i0_15
-R 1000,1500,ref_ref,i1_15
-R 1000,2000,ref_ref,i1_20
-R 1000,2500,ref_ref,i1_25
-R 1000,3000,ref_ref,i1_30
-R 1000,3500,ref_ref,i1_35
-R 500,3000,ref_ref,i2_30
-R 500,2500,ref_ref,i2_25
-R 500,2000,ref_ref,i2_20
-R 500,1500,ref_ref,i2_15
-R 500,3500,ref_ref,i2_35
-R 2500,1000,ref_ref,nq_10
-S 1500,1500,1500,3500,200,i0,DOWN,CALU1
-S 1000,1500,1000,3500,200,i1,DOWN,CALU1
-S 500,1500,500,3500,200,i2,DOWN,CALU1
-S 2500,1000,2500,3500,200,nq,DOWN,CALU1
-S 0,3900,4000,3900,2400,*,RIGHT,NWELL
-S 2100,300,2100,1200,300,*,UP,NDIF
-S 2300,100,2300,1400,100,*,UP,NTRANS
-S 2900,100,2900,1400,100,*,UP,NTRANS
-S 0,300,4000,300,600,vss,RIGHT,CALU1
-S 0,4700,4000,4700,600,vdd,RIGHT,CALU1
-S 3700,1000,3700,3000,100,*,UP,ALU1
-S 1900,2800,1900,4700,300,*,UP,PDIF
-S 3400,2600,3400,3900,100,*,DOWN,PTRANS
-S 3100,2800,3100,4700,300,*,UP,PDIF
-S 2500,2800,2500,4700,300,*,UP,PDIF
-S 2200,2600,2200,4900,100,*,DOWN,PTRANS
-S 2800,2600,2800,4900,100,*,DOWN,PTRANS
-S 3700,2800,3700,3700,300,*,UP,PDIF
-S 3700,800,3700,1200,300,*,DOWN,NDIF
-S 3400,600,3400,1400,100,*,UP,NTRANS
-S 3100,300,3100,1200,300,*,DOWN,NDIF
-S 1200,600,1200,1400,100,*,DOWN,NTRANS
-S 1800,600,1800,1400,100,*,DOWN,NTRANS
-S 600,600,600,1400,100,*,DOWN,NTRANS
-S 900,400,900,1200,300,*,UP,NDIF
-S 300,800,300,1200,300,*,UP,NDIF
-S 1500,800,1500,1200,300,*,UP,NDIF
-S 300,2800,300,4700,300,*,DOWN,PDIF
-S 600,2600,600,4900,100,*,UP,PTRANS
-S 1000,2600,1000,4900,100,*,UP,PTRANS
-S 1400,2600,1400,4900,100,*,UP,PTRANS
-S 1700,2800,1700,4700,300,*,DOWN,PDIF
-S 600,1400,600,2600,100,*,DOWN,POLY
-S 2000,1000,2000,4000,100,*,UP,ALU1
-S 1500,1500,1500,3500,100,*,UP,ALU1
-S 1000,1500,1000,3500,100,*,UP,ALU1
-S 500,1500,500,3500,100,*,UP,ALU1
-S 1000,1400,1000,2600,100,*,DOWN,POLY
-S 1000,1400,1200,1400,100,*,RIGHT,POLY
-S 1800,1400,1800,2400,100,*,UP,POLY
-S 1400,2400,1800,2400,100,*,LEFT,POLY
-S 300,4000,3200,4000,100,*,RIGHT,ALU1
-S 300,1000,2000,1000,100,*,LEFT,ALU1
-S 2600,300,2600,1200,300,*,DOWN,NDIF
-S 3400,1400,3400,2600,100,*,DOWN,POLY
-S 3200,2500,3200,4000,100,*,DOWN,ALU1
-S 2900,1400,2900,2100,100,*,UP,POLY
-S 2800,1900,2800,2600,100,*,DOWN,POLY
-S 2200,1900,2200,2600,100,*,UP,POLY
-S 2300,1400,2300,2100,100,*,DOWN,POLY
-S 2200,2000,3100,2000,300,*,RIGHT,POLY
-S 3100,2500,3400,2500,300,*,RIGHT,POLY
-S 3000,2000,3700,2000,100,*,RIGHT,ALU1
-S 2500,950,2500,3500,200,*,DOWN,ALU1
-V 2500,3500,CONT_DIF_P,*
-V 2500,3000,CONT_DIF_P,*
-V 2000,300,CONT_DIF_N,*
-V 3200,300,CONT_DIF_N,*
-V 3200,2500,CONT_POLY,*
-V 3700,4700,CONT_BODY_N,*
-V 3700,3000,CONT_DIF_P,*
-V 3100,4500,CONT_DIF_P,*
-V 1900,4500,CONT_DIF_P,*
-V 3700,1000,CONT_DIF_N,*
-V 1500,1000,CONT_DIF_N,*
-V 300,1000,CONT_DIF_N,*
-V 900,500,CONT_DIF_N,*
-V 300,300,CONT_BODY_P,*
-V 300,4000,CONT_DIF_P,*
-V 1000,2000,CONT_POLY,*
-V 500,1500,CONT_POLY,*
-V 1500,2500,CONT_POLY,*
-V 2600,1000,CONT_DIF_N,*
-V 3000,2000,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/sxlib/no3_x4.sym b/alliance/share/cells/sxlib/no3_x4.sym
deleted file mode 100644
index bfea318a..00000000
Binary files a/alliance/share/cells/sxlib/no3_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/no3_x4.vbe b/alliance/share/cells/sxlib/no3_x4.vbe
deleted file mode 100644
index 52e3d602..00000000
--- a/alliance/share/cells/sxlib/no3_x4.vbe
+++ /dev/null
@@ -1,38 +0,0 @@
-ENTITY no3_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 2000;
-  CONSTANT cin_i0	 : NATURAL := 12;
-  CONSTANT cin_i1	 : NATURAL := 12;
-  CONSTANT cin_i2	 : NATURAL := 11;
-  CONSTANT rdown_i0_nq	 : NATURAL := 810;
-  CONSTANT rdown_i1_nq	 : NATURAL := 810;
-  CONSTANT rdown_i2_nq	 : NATURAL := 810;
-  CONSTANT rup_i0_nq	 : NATURAL := 890;
-  CONSTANT rup_i1_nq	 : NATURAL := 890;
-  CONSTANT rup_i2_nq	 : NATURAL := 890;
-  CONSTANT tphl_i2_nq	 : NATURAL := 545;
-  CONSTANT tplh_i0_nq	 : NATURAL := 561;
-  CONSTANT tplh_i1_nq	 : NATURAL := 623;
-  CONSTANT tphl_i1_nq	 : NATURAL := 638;
-  CONSTANT tplh_i2_nq	 : NATURAL := 640;
-  CONSTANT tphl_i0_nq	 : NATURAL := 722;
-  CONSTANT transistors	 : NATURAL := 12
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END no3_x4;
-
-ARCHITECTURE behaviour_data_flow OF no3_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on no3_x4"
-  SEVERITY WARNING;
-  nq <= not (((i0 or i1) or i2)) after 1300 ps;
-END;
diff --git a/alliance/share/cells/sxlib/no3_x4.vhd b/alliance/share/cells/sxlib/no3_x4.vhd
deleted file mode 100644
index 1d621496..00000000
--- a/alliance/share/cells/sxlib/no3_x4.vhd
+++ /dev/null
@@ -1,21 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY no3_x4 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END no3_x4;
-
-ARCHITECTURE RTL OF no3_x4 IS
-BEGIN
-  nq <= NOT(((i0 OR i1) OR i2));
-END RTL;
diff --git a/alliance/share/cells/sxlib/no4_x1.al b/alliance/share/cells/sxlib/no4_x1.al
deleted file mode 100644
index 315b53be..00000000
--- a/alliance/share/cells/sxlib/no4_x1.al
+++ /dev/null
@@ -1,38 +0,0 @@
-V ALLIANCE : 6
-H no4_x1,L,30/10/99
-C i0,IN,EXTERNAL,7
-C i1,IN,EXTERNAL,10
-C i2,IN,EXTERNAL,8
-C i3,IN,EXTERNAL,9
-C nq,OUT,EXTERNAL,2
-C vdd,IN,EXTERNAL,5
-C vss,IN,EXTERNAL,1
-T P,0.35,5.9,3,8,4,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00008
-T P,0.35,5.9,6,10,2,0,0.75,0.75,13.3,13.3,3,11.25,tr_00007
-T P,0.35,5.9,4,7,6,0,0.75,0.75,13.3,13.3,4.2,11.25,tr_00006
-T P,0.35,5.9,5,9,3,0,0.75,0.75,13.3,13.3,6.6,11.25,tr_00005
-T N,0.35,1.4,2,7,1,0,0.75,0.75,4.3,4.3,3.6,3,tr_00004
-T N,0.35,1.4,1,8,2,0,0.75,0.75,4.3,4.3,5.4,3,tr_00003
-T N,0.35,1.4,1,10,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00002
-T N,0.35,1.4,2,9,1,0,0.75,0.75,4.3,4.3,7.2,3,tr_00001
-S 10,EXTERNAL,i1
-Q 0.00317863
-S 9,EXTERNAL,i3
-Q 0.00310922
-S 8,EXTERNAL,i2
-Q 0.00332901
-S 7,EXTERNAL,i0
-Q 0.0032596
-S 6,INTERNAL
-Q 0
-S 5,EXTERNAL,vdd
-Q 0.00332715
-S 4,INTERNAL
-Q 0
-S 3,INTERNAL
-Q 0
-S 2,EXTERNAL,nq
-Q 0.00399534
-S 1,EXTERNAL,vss
-Q 0.00403221
-EOF
diff --git a/alliance/share/cells/sxlib/no4_x1.ap b/alliance/share/cells/sxlib/no4_x1.ap
deleted file mode 100644
index c9954ac3..00000000
--- a/alliance/share/cells/sxlib/no4_x1.ap
+++ /dev/null
@@ -1,93 +0,0 @@
-V ALLIANCE : 6
-H no4_x1,P,30/ 8/2000,100
-A 0,0,3000,5000
-R 2000,4000,ref_ref,i2_40
-R 2000,3500,ref_ref,i2_35
-R 2000,3000,ref_ref,i2_30
-R 2000,2500,ref_ref,i2_25
-R 2000,2000,ref_ref,i2_20
-R 2000,1500,ref_ref,i2_15
-R 1500,4000,ref_ref,i0_40
-R 1500,3500,ref_ref,i0_35
-R 1500,3000,ref_ref,i0_30
-R 1500,2500,ref_ref,i0_25
-R 1500,2000,ref_ref,i0_20
-R 1500,1500,ref_ref,i0_15
-R 1000,1500,ref_ref,i1_15
-R 1000,2000,ref_ref,i1_20
-R 1000,2500,ref_ref,i1_25
-R 1000,3000,ref_ref,i1_30
-R 1000,3500,ref_ref,i1_35
-R 1000,4000,ref_ref,i1_40
-R 2500,4000,ref_ref,i3_40
-R 2500,3500,ref_ref,i3_35
-R 2500,3000,ref_ref,i3_30
-R 2500,2500,ref_ref,i3_25
-R 2500,2000,ref_ref,i3_20
-R 2500,1500,ref_ref,i3_15
-R 500,4000,ref_ref,nq_40
-R 500,1500,ref_ref,nq_15
-R 500,2000,ref_ref,nq_20
-R 500,2500,ref_ref,nq_25
-R 500,3000,ref_ref,nq_30
-R 500,3500,ref_ref,nq_35
-R 500,1000,ref_ref,nq_10
-S 2000,1500,2000,4000,200,i2,DOWN,CALU1
-S 1500,1500,1500,4000,200,i0,DOWN,CALU1
-S 1000,1500,1000,4000,200,i1,DOWN,CALU1
-S 2500,1500,2500,4000,200,i3,DOWN,CALU1
-S 500,1000,500,4000,200,nq,DOWN,CALU1
-S 850,1000,2100,1000,200,*,LEFT,ALU1
-S 0,3900,3000,3900,2400,*,RIGHT,NWELL
-S 1200,1400,1200,1900,100,*,DOWN,POLY
-S 1200,1900,1600,1900,100,*,LEFT,POLY
-S 1800,1400,2100,1400,100,*,RIGHT,POLY
-S 1900,1400,1900,2600,100,*,DOWN,POLY
-S 1800,2600,1900,2600,100,*,RIGHT,POLY
-S 1400,2000,1400,2600,100,*,DOWN,POLY
-S 600,1400,600,2400,100,*,DOWN,POLY
-S 600,2400,1100,2400,100,*,LEFT,POLY
-S 1800,2600,1800,4900,100,*,UP,PTRANS
-S 2000,1500,2000,4000,100,*,UP,ALU1
-S 1500,1500,1500,4000,100,*,UP,ALU1
-S 500,2800,500,4200,300,*,DOWN,PDIF
-S 1000,1500,1000,4000,100,*,UP,ALU1
-S 300,400,300,1200,300,*,UP,NDIF
-S 1500,400,1500,1200,300,*,UP,NDIF
-S 1000,2600,1000,4900,100,*,UP,PTRANS
-S 700,2800,700,4200,300,*,DOWN,PDIF
-S 1400,2600,1400,4900,100,*,UP,PTRANS
-S 1200,600,1200,1400,100,*,DOWN,NTRANS
-S 900,800,900,1200,300,*,UP,NDIF
-S 2100,800,2100,1200,300,*,UP,NDIF
-S 1800,600,1800,1400,100,*,DOWN,NTRANS
-S 600,600,600,1400,100,*,DOWN,NTRANS
-S 2200,2600,2200,4900,100,*,UP,PTRANS
-S 2500,2800,2500,4700,300,*,DOWN,PDIF
-S 2400,600,2400,1400,100,*,DOWN,NTRANS
-S 2200,2600,2400,2600,100,*,RIGHT,POLY
-S 2400,1400,2400,2600,100,*,DOWN,POLY
-S 2500,1500,2500,4000,100,*,UP,ALU1
-S 2700,300,2700,1200,300,*,UP,NDIF
-S 0,300,3000,300,600,vss,RIGHT,CALU1
-S 0,4700,3000,4700,600,vdd,RIGHT,CALU1
-S 500,950,500,4000,200,*,DOWN,ALU1
-S 450,1000,850,1000,200,*,LEFT,ALU1
-V 1500,2000,CONT_POLY,*
-V 2000,1500,CONT_POLY,*
-V 1000,2500,CONT_POLY,*
-V 900,300,CONT_BODY_P,*
-V 2100,300,CONT_BODY_P,*
-V 300,500,CONT_DIF_N,*
-V 1500,500,CONT_DIF_N,*
-V 300,4700,CONT_BODY_N,*
-V 900,1000,CONT_DIF_N,*
-V 2100,1000,CONT_DIF_N,*
-V 1500,500,CONT_DIF_N,*
-V 2500,2000,CONT_POLY,*
-V 500,4000,CONT_DIF_P,*
-V 500,3500,CONT_DIF_P,*
-V 500,3000,CONT_DIF_P,*
-V 2500,4500,CONT_DIF_P,*
-V 2700,500,CONT_DIF_N,*
-EOF
diff --git a/alliance/share/cells/sxlib/no4_x1.sym b/alliance/share/cells/sxlib/no4_x1.sym
deleted file mode 100644
index b45e1477..00000000
Binary files a/alliance/share/cells/sxlib/no4_x1.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/no4_x1.vbe b/alliance/share/cells/sxlib/no4_x1.vbe
deleted file mode 100644
index 5d15a3cd..00000000
--- a/alliance/share/cells/sxlib/no4_x1.vbe
+++ /dev/null
@@ -1,44 +0,0 @@
-ENTITY no4_x1 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 1500;
-  CONSTANT cin_i0	 : NATURAL := 12;
-  CONSTANT cin_i1	 : NATURAL := 12;
-  CONSTANT cin_i2	 : NATURAL := 12;
-  CONSTANT cin_i3	 : NATURAL := 12;
-  CONSTANT rdown_i0_nq	 : NATURAL := 3640;
-  CONSTANT rdown_i1_nq	 : NATURAL := 3640;
-  CONSTANT rdown_i2_nq	 : NATURAL := 3640;
-  CONSTANT rdown_i3_nq	 : NATURAL := 3640;
-  CONSTANT rup_i0_nq	 : NATURAL := 6190;
-  CONSTANT rup_i1_nq	 : NATURAL := 6190;
-  CONSTANT rup_i2_nq	 : NATURAL := 6190;
-  CONSTANT rup_i3_nq	 : NATURAL := 6190;
-  CONSTANT tphl_i1_nq	 : NATURAL := 230;
-  CONSTANT tplh_i3_nq	 : NATURAL := 271;
-  CONSTANT tplh_i1_nq	 : NATURAL := 320;
-  CONSTANT tphl_i0_nq	 : NATURAL := 330;
-  CONSTANT tplh_i2_nq	 : NATURAL := 333;
-  CONSTANT tplh_i0_nq	 : NATURAL := 340;
-  CONSTANT tphl_i2_nq	 : NATURAL := 419;
-  CONSTANT tphl_i3_nq	 : NATURAL := 499;
-  CONSTANT transistors	 : NATURAL := 8
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  i3	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END no4_x1;
-
-ARCHITECTURE behaviour_data_flow OF no4_x1 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on no4_x1"
-  SEVERITY WARNING;
-  nq <= not ((((i0 or i1) or i2) or i3)) after 1100 ps;
-END;
diff --git a/alliance/share/cells/sxlib/no4_x1.vhd b/alliance/share/cells/sxlib/no4_x1.vhd
deleted file mode 100644
index 651a0b4f..00000000
--- a/alliance/share/cells/sxlib/no4_x1.vhd
+++ /dev/null
@@ -1,22 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY no4_x1 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  i3	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END no4_x1;
-
-ARCHITECTURE RTL OF no4_x1 IS
-BEGIN
-  nq <= NOT((((i0 OR i1) OR i2) OR i3));
-END RTL;
diff --git a/alliance/share/cells/sxlib/no4_x4.al b/alliance/share/cells/sxlib/no4_x4.al
deleted file mode 100644
index df49bccf..00000000
--- a/alliance/share/cells/sxlib/no4_x4.al
+++ /dev/null
@@ -1,48 +0,0 @@
-V ALLIANCE : 6
-H no4_x4,L,30/10/99
-C i0,IN,EXTERNAL,7
-C i1,IN,EXTERNAL,10
-C i2,IN,EXTERNAL,8
-C i3,IN,EXTERNAL,9
-C nq,OUT,EXTERNAL,11
-C vdd,IN,EXTERNAL,6
-C vss,IN,EXTERNAL,2
-T P,0.35,5.9,4,8,5,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00014
-T P,0.35,5.9,3,10,1,0,0.75,0.75,13.3,13.3,3,11.25,tr_00013
-T P,0.35,5.9,5,7,3,0,0.75,0.75,13.3,13.3,4.2,11.25,tr_00012
-T P,0.35,5.9,6,9,4,0,0.75,0.75,13.3,13.3,6.6,11.25,tr_00011
-T P,0.35,5.9,11,12,6,0,0.75,0.75,13.3,13.3,11.4,11.25,tr_00010
-T P,0.35,5.9,6,12,11,0,0.75,0.75,13.3,13.3,9.6,11.25,tr_00009
-T P,0.35,2.9,6,1,12,0,0.75,0.75,7.3,7.3,13.2,9.75,tr_00008
-T N,0.35,1.4,1,7,2,0,0.75,0.75,4.3,4.3,3.6,3,tr_00007
-T N,0.35,1.4,2,8,1,0,0.75,0.75,4.3,4.3,5.4,3,tr_00006
-T N,0.35,1.4,2,10,1,0,0.75,0.75,4.3,4.3,1.8,3,tr_00005
-T N,0.35,1.4,1,9,2,0,0.75,0.75,4.3,4.3,7.2,3,tr_00004
-T N,0.35,2.9,11,12,2,0,0.75,0.75,7.3,7.3,9.6,2.25,tr_00003
-T N,0.35,2.9,2,12,11,0,0.75,0.75,7.3,7.3,11.4,2.25,tr_00002
-T N,0.35,1.4,12,1,2,0,0.75,0.75,4.3,4.3,13.2,3,tr_00001
-S 12,INTERNAL
-Q 0.00586076
-S 11,EXTERNAL,nq
-Q 0.00229144
-S 10,EXTERNAL,i1
-Q 0.00317863
-S 9,EXTERNAL,i3
-Q 0.00310922
-S 8,EXTERNAL,i2
-Q 0.00332901
-S 7,EXTERNAL,i0
-Q 0.0032596
-S 6,EXTERNAL,vdd
-Q 0.00674947
-S 5,INTERNAL
-Q 0
-S 4,INTERNAL
-Q 0
-S 3,INTERNAL
-Q 0
-S 2,EXTERNAL,vss
-Q 0.00575064
-S 1,INTERNAL
-Q 0.00812639
-EOF
diff --git a/alliance/share/cells/sxlib/no4_x4.ap b/alliance/share/cells/sxlib/no4_x4.ap
deleted file mode 100644
index 2fa594d6..00000000
--- a/alliance/share/cells/sxlib/no4_x4.ap
+++ /dev/null
@@ -1,138 +0,0 @@
-V ALLIANCE : 6
-H no4_x4,P,30/ 8/2000,100
-A 0,0,5000,5000
-R 2000,4000,ref_ref,i2_40
-R 2000,3500,ref_ref,i2_35
-R 2000,3000,ref_ref,i2_30
-R 2000,2500,ref_ref,i2_25
-R 2000,2000,ref_ref,i2_20
-R 2000,1500,ref_ref,i2_15
-R 1500,4000,ref_ref,i0_40
-R 1500,3500,ref_ref,i0_35
-R 1500,3000,ref_ref,i0_30
-R 1500,2500,ref_ref,i0_25
-R 1500,2000,ref_ref,i0_20
-R 1500,1500,ref_ref,i0_15
-R 1000,1500,ref_ref,i1_15
-R 1000,2000,ref_ref,i1_20
-R 1000,2500,ref_ref,i1_25
-R 1000,3000,ref_ref,i1_30
-R 1000,3500,ref_ref,i1_35
-R 1000,4000,ref_ref,i1_40
-R 2500,4000,ref_ref,i3_40
-R 2500,3500,ref_ref,i3_35
-R 2500,3000,ref_ref,i3_30
-R 2500,2500,ref_ref,i3_25
-R 2500,2000,ref_ref,i3_20
-R 2500,1500,ref_ref,i3_15
-R 3500,3500,ref_ref,nq_35
-R 3500,4000,ref_ref,nq_40
-R 3500,1500,ref_ref,nq_15
-R 3500,2000,ref_ref,nq_20
-R 3500,2500,ref_ref,nq_25
-R 3500,3000,ref_ref,nq_30
-S 2000,1500,2000,4000,200,i2,DOWN,CALU1
-S 1500,1500,1500,4000,200,i0,DOWN,CALU1
-S 1000,1500,1000,4000,200,i1,DOWN,CALU1
-S 2500,1500,2500,4000,200,i3,DOWN,CALU1
-S 3500,1500,3500,4000,200,nq,DOWN,CALU1
-S 3500,1500,3500,4000,200,*,DOWN,ALU1
-S 0,3900,5000,3900,2400,*,RIGHT,NWELL
-S 1200,1400,1200,1900,100,*,DOWN,POLY
-S 1200,1900,1600,1900,100,*,LEFT,POLY
-S 1800,1400,2100,1400,100,*,RIGHT,POLY
-S 1900,1400,1900,2600,100,*,DOWN,POLY
-S 1800,2600,1900,2600,100,*,RIGHT,POLY
-S 1400,2000,1400,2600,100,*,DOWN,POLY
-S 600,1400,600,2400,100,*,DOWN,POLY
-S 600,2400,1100,2400,100,*,LEFT,POLY
-S 1800,2600,1800,4900,100,*,UP,PTRANS
-S 2000,1500,2000,4000,100,*,UP,ALU1
-S 1500,1500,1500,4000,100,*,UP,ALU1
-S 500,2800,500,4200,300,*,DOWN,PDIF
-S 1000,1500,1000,4000,100,*,UP,ALU1
-S 300,400,300,1200,300,*,UP,NDIF
-S 1500,400,1500,1200,300,*,UP,NDIF
-S 1000,2600,1000,4900,100,*,UP,PTRANS
-S 700,2800,700,4200,300,*,DOWN,PDIF
-S 1400,2600,1400,4900,100,*,UP,PTRANS
-S 1200,600,1200,1400,100,*,DOWN,NTRANS
-S 900,800,900,1200,300,*,UP,NDIF
-S 2100,800,2100,1200,300,*,UP,NDIF
-S 1800,600,1800,1400,100,*,DOWN,NTRANS
-S 600,600,600,1400,100,*,DOWN,NTRANS
-S 2200,2600,2200,4900,100,*,UP,PTRANS
-S 2500,2800,2500,4700,300,*,DOWN,PDIF
-S 2400,600,2400,1400,100,*,DOWN,NTRANS
-S 2200,2600,2400,2600,100,*,RIGHT,POLY
-S 2400,1400,2400,2600,100,*,DOWN,POLY
-S 2500,1500,2500,4000,100,*,UP,ALU1
-S 4000,2500,4200,2500,200,*,RIGHT,ALU1
-S 2900,300,2900,1200,300,*,DOWN,NDIF
-S 3200,100,3200,1400,100,*,UP,NTRANS
-S 4100,300,4100,1200,300,*,DOWN,NDIF
-S 3800,100,3800,1400,100,*,UP,NTRANS
-S 4400,600,4400,1400,100,*,UP,NTRANS
-S 4700,800,4700,1200,300,*,DOWN,NDIF
-S 4700,2800,4700,3700,300,*,UP,PDIF
-S 3800,2600,3800,4900,100,*,DOWN,PTRANS
-S 3200,2600,3200,4900,100,*,DOWN,PTRANS
-S 3500,2800,3500,4700,300,*,UP,PDIF
-S 4100,2800,4100,4700,300,*,UP,PDIF
-S 4400,2600,4400,3900,100,*,DOWN,PTRANS
-S 2900,2800,2900,4700,300,*,UP,PDIF
-S 3200,1400,3200,2600,100,*,UP,POLY
-S 3800,1400,3800,2600,100,*,UP,POLY
-S 4200,2500,4400,2500,300,*,RIGHT,POLY
-S 4700,1000,4700,3000,100,*,UP,ALU1
-S 3200,2000,4700,2000,300,*,RIGHT,POLY
-S 4200,1500,4400,1500,300,*,RIGHT,POLY
-S 4000,1500,4200,1500,200,*,RIGHT,ALU1
-S 0,4700,5000,4700,600,vdd,RIGHT,CALU1
-S 0,300,5000,300,600,vss,RIGHT,CALU1
-S 2800,2800,2800,4700,300,*,UP,PDIF
-S 2700,300,2700,1200,300,*,UP,NDIF
-S 4000,1000,4000,2500,100,*,UP,ALU1
-S 3500,300,3500,1600,300,*,DOWN,NDIF
-S 4100,3000,4100,4500,200,*,DOWN,ALU1
-S 500,1000,500,3000,100,*,DOWN,ALU1
-S 500,3000,500,4000,100,*,UP,ALU1
-S 500,1000,4000,1000,100,*,LEFT,ALU1
-S 500,1000,900,1000,200,*,LEFT,ALU1
-S 4700,3000,4700,3500,100,*,DOWN,ALU1
-V 1500,2000,CONT_POLY,*
-V 2000,1500,CONT_POLY,*
-V 1000,2500,CONT_POLY,*
-V 900,300,CONT_BODY_P,*
-V 2100,300,CONT_BODY_P,*
-V 300,500,CONT_DIF_N,*
-V 1500,500,CONT_DIF_N,*
-V 300,4700,CONT_BODY_N,*
-V 900,1000,CONT_DIF_N,*
-V 2100,1000,CONT_DIF_N,*
-V 1500,500,CONT_DIF_N,*
-V 2500,2000,CONT_POLY,*
-V 4700,1000,CONT_DIF_N,*
-V 4100,500,CONT_DIF_N,*
-V 4100,4500,CONT_DIF_P,*
-V 4700,3000,CONT_DIF_P,*
-V 4700,4700,CONT_BODY_N,*
-V 4700,300,CONT_BODY_P,*
-V 4200,2500,CONT_POLY,*
-V 4700,2000,CONT_POLY,*
-V 4200,1500,CONT_POLY,*
-V 2800,500,CONT_DIF_N,*
-V 3500,4000,CONT_DIF_P,*
-V 3500,3500,CONT_DIF_P,*
-V 3500,3000,CONT_DIF_P,*
-V 3500,1500,CONT_DIF_N,*
-V 500,3000,CONT_DIF_P,*
-V 4100,4000,CONT_DIF_P,*
-V 4100,3500,CONT_DIF_P,*
-V 4100,3000,CONT_DIF_P,*
-V 500,3500,CONT_DIF_P,*
-V 500,4000,CONT_DIF_P,*
-V 2500,4500,CONT_DIF_P,*
-V 2900,4500,CONT_DIF_P,*
-V 4700,3500,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/no4_x4.sym b/alliance/share/cells/sxlib/no4_x4.sym
deleted file mode 100644
index ca15cbb2..00000000
Binary files a/alliance/share/cells/sxlib/no4_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/no4_x4.vbe b/alliance/share/cells/sxlib/no4_x4.vbe
deleted file mode 100644
index cffb179c..00000000
--- a/alliance/share/cells/sxlib/no4_x4.vbe
+++ /dev/null
@@ -1,44 +0,0 @@
-ENTITY no4_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 2500;
-  CONSTANT cin_i0	 : NATURAL := 12;
-  CONSTANT cin_i1	 : NATURAL := 12;
-  CONSTANT cin_i2	 : NATURAL := 12;
-  CONSTANT cin_i3	 : NATURAL := 12;
-  CONSTANT rdown_i0_nq	 : NATURAL := 810;
-  CONSTANT rdown_i1_nq	 : NATURAL := 810;
-  CONSTANT rdown_i2_nq	 : NATURAL := 810;
-  CONSTANT rdown_i3_nq	 : NATURAL := 810;
-  CONSTANT rup_i0_nq	 : NATURAL := 890;
-  CONSTANT rup_i1_nq	 : NATURAL := 890;
-  CONSTANT rup_i2_nq	 : NATURAL := 890;
-  CONSTANT rup_i3_nq	 : NATURAL := 890;
-  CONSTANT tphl_i1_nq	 : NATURAL := 564;
-  CONSTANT tphl_i0_nq	 : NATURAL := 656;
-  CONSTANT tplh_i3_nq	 : NATURAL := 693;
-  CONSTANT tphl_i2_nq	 : NATURAL := 739;
-  CONSTANT tplh_i2_nq	 : NATURAL := 761;
-  CONSTANT tplh_i1_nq	 : NATURAL := 768;
-  CONSTANT tplh_i0_nq	 : NATURAL := 777;
-  CONSTANT tphl_i3_nq	 : NATURAL := 816;
-  CONSTANT transistors	 : NATURAL := 14
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  i3	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END no4_x4;
-
-ARCHITECTURE behaviour_data_flow OF no4_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on no4_x4"
-  SEVERITY WARNING;
-  nq <= not ((((i0 or i1) or i2) or i3)) after 1400 ps;
-END;
diff --git a/alliance/share/cells/sxlib/no4_x4.vhd b/alliance/share/cells/sxlib/no4_x4.vhd
deleted file mode 100644
index 855a29a7..00000000
--- a/alliance/share/cells/sxlib/no4_x4.vhd
+++ /dev/null
@@ -1,22 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY no4_x4 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  i3	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END no4_x4;
-
-ARCHITECTURE RTL OF no4_x4 IS
-BEGIN
-  nq <= NOT((((i0 OR i1) OR i2) OR i3));
-END RTL;
diff --git a/alliance/share/cells/sxlib/noa22_x1.al b/alliance/share/cells/sxlib/noa22_x1.al
deleted file mode 100644
index fe536c46..00000000
--- a/alliance/share/cells/sxlib/noa22_x1.al
+++ /dev/null
@@ -1,31 +0,0 @@
-V ALLIANCE : 6
-H noa22_x1,L,30/10/99
-C i0,IN,EXTERNAL,6
-C i1,IN,EXTERNAL,7
-C i2,IN,EXTERNAL,8
-C nq,OUT,EXTERNAL,2
-C vdd,IN,EXTERNAL,5
-C vss,IN,EXTERNAL,3
-T P,0.35,5.9,5,8,4,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00006
-T P,0.35,5.9,2,6,4,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00005
-T P,0.35,5.9,4,7,2,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00004
-T N,0.35,2.9,3,6,1,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00003
-T N,0.35,2.9,1,7,2,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002
-T N,0.35,2.9,2,8,3,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00001
-S 8,EXTERNAL,i2
-Q 0.00344864
-S 7,EXTERNAL,i1
-Q 0.00288494
-S 6,EXTERNAL,i0
-Q 0.00260759
-S 5,EXTERNAL,vdd
-Q 0.004561
-S 4,INTERNAL
-Q 0.00171257
-S 3,EXTERNAL,vss
-Q 0.00450225
-S 2,EXTERNAL,nq
-Q 0.0026146
-S 1,INTERNAL
-Q 0
-EOF
diff --git a/alliance/share/cells/sxlib/noa22_x1.ap b/alliance/share/cells/sxlib/noa22_x1.ap
deleted file mode 100644
index dcb02458..00000000
--- a/alliance/share/cells/sxlib/noa22_x1.ap
+++ /dev/null
@@ -1,78 +0,0 @@
-V ALLIANCE : 6
-H noa22_x1,P,30/ 8/2000,100
-A 0,0,3000,5000
-R 2000,4000,ref_ref,i2_40
-R 500,1000,ref_ref,i0_10
-R 500,1500,ref_ref,i0_15
-R 500,2000,ref_ref,i0_20
-R 500,2500,ref_ref,i0_25
-R 500,3000,ref_ref,i0_30
-R 1000,3000,ref_ref,i1_30
-R 1000,2500,ref_ref,i1_25
-R 1000,2000,ref_ref,i1_20
-R 1000,1500,ref_ref,i1_15
-R 1000,1000,ref_ref,i1_10
-R 2000,1000,ref_ref,i2_10
-R 2000,1500,ref_ref,i2_15
-R 2000,2000,ref_ref,i2_20
-R 2000,2500,ref_ref,i2_25
-R 2000,3000,ref_ref,i2_30
-R 2000,3500,ref_ref,i2_35
-R 1500,1000,ref_ref,nq_10
-R 1500,1500,ref_ref,nq_15
-R 1500,2000,ref_ref,nq_20
-R 1500,2500,ref_ref,nq_25
-R 1500,3000,ref_ref,nq_30
-R 1500,3500,ref_ref,nq_35
-S 500,1000,500,3000,200,i0,DOWN,CALU1
-S 1000,1000,1000,3000,200,i1,DOWN,CALU1
-S 2000,1000,2000,4000,200,i2,DOWN,CALU1
-S 1500,1000,1500,3500,200,nq,DOWN,CALU1
-S 0,3900,3000,3900,2400,*,LEFT,NWELL
-S 0,4700,3000,4700,600,vdd,RIGHT,CALU1
-S 0,300,3000,300,600,vss,RIGHT,CALU1
-S 2700,500,2700,1700,200,*,DOWN,ALU1
-S 2700,2900,2700,4500,200,*,DOWN,ALU1
-S 2000,1000,2000,4000,100,*,DOWN,ALU1
-S 300,4000,1500,4000,100,*,RIGHT,ALU1
-S 1800,1400,1800,2600,100,*,DOWN,POLY
-S 500,1000,500,3000,100,*,UP,ALU1
-S 1000,1000,1000,3000,100,*,DOWN,ALU1
-S 1200,1400,1200,2600,100,*,DOWN,POLY
-S 600,1400,600,2600,100,*,DOWN,POLY
-S 2100,2800,2100,4700,300,*,DOWN,PDIF
-S 1800,2600,1800,4900,100,*,UP,PTRANS
-S 1500,2800,1500,4700,300,*,DOWN,PDIF
-S 300,2800,300,4700,300,*,DOWN,PDIF
-S 600,2600,600,4900,100,*,UP,PTRANS
-S 900,2800,900,4700,300,*,DOWN,PDIF
-S 1200,2600,1200,4900,100,*,UP,PTRANS
-S 600,100,600,1400,100,*,DOWN,NTRANS
-S 300,300,300,1200,300,*,UP,NDIF
-S 900,300,900,1200,300,*,UP,NDIF
-S 1200,100,1200,1400,100,*,DOWN,NTRANS
-S 1500,300,1500,1200,300,*,UP,NDIF
-S 1800,100,1800,1400,100,*,DOWN,NTRANS
-S 2100,300,2100,1200,300,*,UP,NDIF
-S 1800,2000,2000,2000,300,*,RIGHT,POLY
-S 1000,2000,1200,2000,300,*,RIGHT,POLY
-S 900,3500,1500,3500,200,*,RIGHT,ALU1
-S 300,3500,300,4000,100,*,UP,ALU1
-S 1500,1000,1500,3550,200,*,UP,ALU1
-V 2700,300,CONT_BODY_P,*
-V 2700,4700,CONT_BODY_N,*
-V 2700,2900,CONT_BODY_N,*
-V 2700,1700,CONT_BODY_P,*
-V 2100,500,CONT_DIF_N,*
-V 1500,1000,CONT_DIF_N,*
-V 900,3500,CONT_DIF_P,*
-V 2100,4500,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 300,4000,CONT_DIF_P,*
-V 2000,2000,CONT_POLY,*
-V 1000,2000,CONT_POLY,*
-V 300,500,CONT_DIF_N,*
-V 1500,1000,CONT_DIF_N,*
-V 500,2000,CONT_POLY,*
-V 300,3500,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/noa22_x1.sym b/alliance/share/cells/sxlib/noa22_x1.sym
deleted file mode 100644
index feab1697..00000000
Binary files a/alliance/share/cells/sxlib/noa22_x1.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/noa22_x1.vbe b/alliance/share/cells/sxlib/noa22_x1.vbe
deleted file mode 100644
index 5c13864f..00000000
--- a/alliance/share/cells/sxlib/noa22_x1.vbe
+++ /dev/null
@@ -1,38 +0,0 @@
-ENTITY noa22_x1 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 1500;
-  CONSTANT cin_i0	 : NATURAL := 14;
-  CONSTANT cin_i1	 : NATURAL := 14;
-  CONSTANT cin_i2	 : NATURAL := 15;
-  CONSTANT rdown_i0_nq	 : NATURAL := 2850;
-  CONSTANT rdown_i1_nq	 : NATURAL := 2850;
-  CONSTANT rdown_i2_nq	 : NATURAL := 1620;
-  CONSTANT rup_i0_nq	 : NATURAL := 3210;
-  CONSTANT rup_i1_nq	 : NATURAL := 3210;
-  CONSTANT rup_i2_nq	 : NATURAL := 3210;
-  CONSTANT tphl_i0_nq	 : NATURAL := 151;
-  CONSTANT tphl_i1_nq	 : NATURAL := 218;
-  CONSTANT tphl_i2_nq	 : NATURAL := 218;
-  CONSTANT tplh_i2_nq	 : NATURAL := 241;
-  CONSTANT tplh_i1_nq	 : NATURAL := 287;
-  CONSTANT tplh_i0_nq	 : NATURAL := 327;
-  CONSTANT transistors	 : NATURAL := 6
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END noa22_x1;
-
-ARCHITECTURE behaviour_data_flow OF noa22_x1 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on noa22_x1"
-  SEVERITY WARNING;
-  nq <= not (((i0 and i1) or i2)) after 900 ps;
-END;
diff --git a/alliance/share/cells/sxlib/noa22_x1.vhd b/alliance/share/cells/sxlib/noa22_x1.vhd
deleted file mode 100644
index 50447019..00000000
--- a/alliance/share/cells/sxlib/noa22_x1.vhd
+++ /dev/null
@@ -1,21 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY noa22_x1 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END noa22_x1;
-
-ARCHITECTURE RTL OF noa22_x1 IS
-BEGIN
-  nq <= NOT(((i0 AND i1) OR i2));
-END RTL;
diff --git a/alliance/share/cells/sxlib/noa22_x4.al b/alliance/share/cells/sxlib/noa22_x4.al
deleted file mode 100644
index 8157586a..00000000
--- a/alliance/share/cells/sxlib/noa22_x4.al
+++ /dev/null
@@ -1,41 +0,0 @@
-V ALLIANCE : 6
-H noa22_x4,L,30/10/99
-C i0,IN,EXTERNAL,7
-C i1,IN,EXTERNAL,5
-C i2,IN,EXTERNAL,6
-C nq,OUT,EXTERNAL,8
-C vdd,IN,EXTERNAL,9
-C vss,IN,EXTERNAL,3
-T P,0.35,5.9,8,4,9,0,0.75,0.75,13.3,13.3,11.1,11.25,tr_00012
-T P,0.35,5.9,9,4,8,0,0.75,0.75,13.3,13.3,12.9,11.25,tr_00011
-T P,0.35,2.9,9,1,4,0,0.75,0.75,7.3,7.3,9.3,9.75,tr_00010
-T P,0.35,2.9,10,6,9,0,0.75,0.75,7.3,7.3,2.1,11.25,tr_00009
-T P,0.35,2.9,10,7,1,0,0.75,0.75,7.3,7.3,5.7,11.25,tr_00008
-T P,0.35,2.9,1,5,10,0,0.75,0.75,7.3,7.3,3.9,11.25,tr_00007
-T N,0.35,2.9,8,4,3,0,0.75,0.75,7.3,7.3,12.9,2.25,tr_00006
-T N,0.35,1.4,4,1,3,0,0.75,0.75,4.3,4.3,9.3,3,tr_00005
-T N,0.35,1.4,2,7,3,0,0.75,0.75,4.3,4.3,5.7,3,tr_00004
-T N,0.35,1.4,1,5,2,0,0.75,0.75,4.3,4.3,3.9,3,tr_00003
-T N,0.35,2.9,3,4,8,0,0.75,0.75,7.3,7.3,11.1,2.25,tr_00002
-T N,0.35,1.4,3,6,1,0,0.75,0.75,4.3,4.3,2.1,3,tr_00001
-S 10,INTERNAL
-Q 0.00114171
-S 9,EXTERNAL,vdd
-Q 0.00768955
-S 8,EXTERNAL,nq
-Q 0.00258522
-S 7,EXTERNAL,i0
-Q 0.00295462
-S 6,EXTERNAL,i2
-Q 0.00379567
-S 5,EXTERNAL,i1
-Q 0.00323197
-S 4,INTERNAL
-Q 0.00518414
-S 3,EXTERNAL,vss
-Q 0.00674947
-S 2,INTERNAL
-Q 0
-S 1,INTERNAL
-Q 0.00560501
-EOF
diff --git a/alliance/share/cells/sxlib/noa22_x4.ap b/alliance/share/cells/sxlib/noa22_x4.ap
deleted file mode 100644
index 090e7de7..00000000
--- a/alliance/share/cells/sxlib/noa22_x4.ap
+++ /dev/null
@@ -1,122 +0,0 @@
-V ALLIANCE : 6
-H noa22_x4,P,30/ 8/2000,100
-A 0,0,5000,5000
-R 500,4000,ref_ref,i2_40
-R 500,3500,ref_ref,i2_35
-R 4000,3500,ref_ref,nq_35
-R 4000,3000,ref_ref,nq_30
-R 4000,2000,ref_ref,nq_20
-R 4000,1000,ref_ref,nq_10
-R 4000,1500,ref_ref,nq_15
-R 4000,2500,ref_ref,nq_25
-R 500,1000,ref_ref,i2_10
-R 500,1500,ref_ref,i2_15
-R 500,2000,ref_ref,i2_20
-R 500,2500,ref_ref,i2_25
-R 500,3000,ref_ref,i2_30
-R 2000,2000,ref_ref,i0_20
-R 2000,2500,ref_ref,i0_25
-R 2000,3000,ref_ref,i0_30
-R 1500,3000,ref_ref,i1_30
-R 1500,2500,ref_ref,i1_25
-R 1500,2000,ref_ref,i1_20
-R 1500,1500,ref_ref,i1_15
-R 1500,1000,ref_ref,i1_10
-R 4000,4000,ref_ref,nq_40
-R 2000,1000,ref_ref,i0_10
-R 2000,1500,ref_ref,i0_15
-S 500,1000,500,4000,200,i2,DOWN,CALU1
-S 1500,1000,1500,3000,200,i1,DOWN,CALU1
-S 4000,1000,4000,4000,200,nq,DOWN,CALU1
-S 2000,1000,2000,3000,200,i0,DOWN,CALU1
-S 500,1000,500,4000,100,*,DOWN,ALU1
-S 400,3300,400,4600,300,*,DOWN,PDIF
-S 1600,3300,1600,4200,300,*,DOWN,PDIF
-S 1000,3500,3300,3500,100,*,RIGHT,ALU1
-S 1500,1000,1500,3000,100,*,DOWN,ALU1
-S 2800,1000,2800,3000,100,*,DOWN,ALU1
-S 1000,1000,1000,3500,100,*,UP,ALU1
-S 3400,500,3400,1000,200,*,DOWN,ALU1
-S 4600,500,4600,1000,200,*,DOWN,ALU1
-S 4600,3000,4600,4500,200,*,DOWN,ALU1
-S 3400,4000,3400,4500,200,*,DOWN,ALU1
-S 2800,2000,3500,2000,100,*,RIGHT,ALU1
-S 3300,2500,3300,3500,100,*,DOWN,ALU1
-S 2000,1000,2000,3000,100,*,DOWN,ALU1
-S 4000,1000,4000,4000,200,*,UP,ALU1
-S 1000,4000,2200,4000,100,*,RIGHT,ALU1
-S 0,4700,5000,4700,600,vdd,RIGHT,CALU1
-S 0,300,5000,300,600,vss,RIGHT,CALU1
-S 500,2000,700,2000,300,*,RIGHT,POLY
-S 1300,2000,1500,2000,300,*,RIGHT,POLY
-S 3500,2000,4300,2000,300,*,RIGHT,POLY
-S 3100,2500,3300,2500,300,*,RIGHT,POLY
-S 4300,1400,4300,2600,100,*,DOWN,POLY
-S 3700,1400,3700,2600,100,*,DOWN,POLY
-S 3100,1400,3100,2600,100,*,DOWN,POLY
-S 700,1400,700,3100,100,*,DOWN,POLY
-S 1300,1400,1300,3100,100,*,DOWN,POLY
-S 1900,1400,1900,3100,100,*,DOWN,POLY
-S 4300,100,4300,1400,100,*,DOWN,NTRANS
-S 3400,300,3400,1200,300,*,UP,NDIF
-S 4000,300,4000,1200,300,*,UP,NDIF
-S 4600,300,4600,1200,300,*,UP,NDIF
-S 3100,600,3100,1400,100,*,DOWN,NTRANS
-S 2800,800,2800,1200,300,*,UP,NDIF
-S 1900,600,1900,1400,100,*,DOWN,NTRANS
-S 1600,800,1600,1200,300,*,UP,NDIF
-S 1300,600,1300,1400,100,*,DOWN,NTRANS
-S 1000,800,1000,1200,300,*,UP,NDIF
-S 3700,100,3700,1400,100,*,DOWN,NTRANS
-S 2200,400,2200,1200,300,*,UP,NDIF
-S 700,600,700,1400,100,*,DOWN,NTRANS
-S 400,400,400,1200,300,*,UP,NDIF
-S 3700,2600,3700,4900,100,*,UP,PTRANS
-S 4300,2600,4300,4900,100,*,UP,PTRANS
-S 4000,2800,4000,4700,300,*,DOWN,PDIF
-S 3400,2800,3400,4700,300,*,DOWN,PDIF
-S 4600,2800,4600,4700,300,*,DOWN,PDIF
-S 3100,2600,3100,3900,100,*,UP,PTRANS
-S 2800,2800,2800,3700,300,*,DOWN,PDIF
-S 700,3100,700,4400,100,*,UP,PTRANS
-S 1900,3100,1900,4400,100,*,UP,PTRANS
-S 1300,3100,1300,4400,100,*,UP,PTRANS
-S 2200,3300,2200,4200,300,*,DOWN,PDIF
-S 1000,3300,1000,4200,300,*,DOWN,PDIF
-S 0,3900,5000,3900,2400,*,RIGHT,NWELL
-V 1600,4700,CONT_BODY_N,*
-V 400,4500,CONT_DIF_P,*
-V 1600,3500,CONT_DIF_P,*
-V 3500,2000,CONT_POLY,*
-V 3300,2500,CONT_POLY,*
-V 2000,2000,CONT_POLY,*
-V 500,2000,CONT_POLY,*
-V 1500,2000,CONT_POLY,*
-V 1600,300,CONT_BODY_P,*
-V 1000,300,CONT_BODY_P,*
-V 2800,300,CONT_BODY_P,*
-V 1000,1000,CONT_DIF_N,*
-V 4600,1000,CONT_DIF_N,*
-V 3400,1000,CONT_DIF_N,*
-V 2800,1000,CONT_DIF_N,*
-V 2200,500,CONT_DIF_N,*
-V 3400,500,CONT_DIF_N,*
-V 4600,500,CONT_DIF_N,*
-V 4000,1000,CONT_DIF_N,*
-V 400,500,CONT_DIF_N,*
-V 3400,4500,CONT_DIF_P,*
-V 3400,4000,CONT_DIF_P,*
-V 1000,4000,CONT_DIF_P,*
-V 2200,4000,CONT_DIF_P,*
-V 1000,4700,CONT_BODY_N,*
-V 2800,4700,CONT_BODY_N,*
-V 2800,3000,CONT_DIF_P,*
-V 4600,3000,CONT_DIF_P,*
-V 4600,3500,CONT_DIF_P,*
-V 4600,4000,CONT_DIF_P,*
-V 4600,4500,CONT_DIF_P,*
-V 2200,4700,CONT_BODY_N,*
-V 4000,3000,CONT_DIF_P,*
-V 4000,3500,CONT_DIF_P,*
-V 4000,4000,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/noa22_x4.sym b/alliance/share/cells/sxlib/noa22_x4.sym
deleted file mode 100644
index cbc2e448..00000000
Binary files a/alliance/share/cells/sxlib/noa22_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/noa22_x4.vbe b/alliance/share/cells/sxlib/noa22_x4.vbe
deleted file mode 100644
index 6288a32e..00000000
--- a/alliance/share/cells/sxlib/noa22_x4.vbe
+++ /dev/null
@@ -1,38 +0,0 @@
-ENTITY noa22_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 2500;
-  CONSTANT cin_i0	 : NATURAL := 8;
-  CONSTANT cin_i1	 : NATURAL := 8;
-  CONSTANT cin_i2	 : NATURAL := 9;
-  CONSTANT rdown_i0_nq	 : NATURAL := 810;
-  CONSTANT rdown_i1_nq	 : NATURAL := 810;
-  CONSTANT rdown_i2_nq	 : NATURAL := 810;
-  CONSTANT rup_i0_nq	 : NATURAL := 890;
-  CONSTANT rup_i1_nq	 : NATURAL := 890;
-  CONSTANT rup_i2_nq	 : NATURAL := 890;
-  CONSTANT tphl_i0_nq	 : NATURAL := 550;
-  CONSTANT tphl_i2_nq	 : NATURAL := 610;
-  CONSTANT tphl_i1_nq	 : NATURAL := 643;
-  CONSTANT tplh_i2_nq	 : NATURAL := 646;
-  CONSTANT tplh_i1_nq	 : NATURAL := 709;
-  CONSTANT tplh_i0_nq	 : NATURAL := 740;
-  CONSTANT transistors	 : NATURAL := 12
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END noa22_x4;
-
-ARCHITECTURE behaviour_data_flow OF noa22_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on noa22_x4"
-  SEVERITY WARNING;
-  nq <= not (((i0 and i1) or i2)) after 1300 ps;
-END;
diff --git a/alliance/share/cells/sxlib/noa22_x4.vhd b/alliance/share/cells/sxlib/noa22_x4.vhd
deleted file mode 100644
index 8723b663..00000000
--- a/alliance/share/cells/sxlib/noa22_x4.vhd
+++ /dev/null
@@ -1,21 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY noa22_x4 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END noa22_x4;
-
-ARCHITECTURE RTL OF noa22_x4 IS
-BEGIN
-  nq <= NOT(((i0 AND i1) OR i2));
-END RTL;
diff --git a/alliance/share/cells/sxlib/noa2a22_x1.al b/alliance/share/cells/sxlib/noa2a22_x1.al
deleted file mode 100644
index 3e8dac59..00000000
--- a/alliance/share/cells/sxlib/noa2a22_x1.al
+++ /dev/null
@@ -1,38 +0,0 @@
-V ALLIANCE : 6
-H noa2a22_x1,L,30/10/99
-C i0,IN,EXTERNAL,10
-C i1,IN,EXTERNAL,8
-C i2,IN,EXTERNAL,9
-C i3,IN,EXTERNAL,7
-C nq,OUT,EXTERNAL,3
-C vdd,IN,EXTERNAL,6
-C vss,IN,EXTERNAL,1
-T P,0.35,5.9,5,8,3,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00008
-T P,0.35,5.9,3,10,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00007
-T P,0.35,5.9,6,7,5,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00006
-T P,0.35,5.9,5,9,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00005
-T N,0.35,2.9,4,9,1,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00004
-T N,0.35,2.9,3,7,4,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00003
-T N,0.35,2.9,2,8,3,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002
-T N,0.35,2.9,1,10,2,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00001
-S 10,EXTERNAL,i0
-Q 0.00260759
-S 9,EXTERNAL,i2
-Q 0.00288944
-S 8,EXTERNAL,i1
-Q 0.00288494
-S 7,EXTERNAL,i3
-Q 0.00316679
-S 6,EXTERNAL,vdd
-Q 0.00472621
-S 5,INTERNAL
-Q 0.00199441
-S 4,INTERNAL
-Q 0
-S 3,EXTERNAL,nq
-Q 0.00264397
-S 2,INTERNAL
-Q 0
-S 1,EXTERNAL,vss
-Q 0.00466746
-EOF
diff --git a/alliance/share/cells/sxlib/noa2a22_x1.ap b/alliance/share/cells/sxlib/noa2a22_x1.ap
deleted file mode 100644
index 05679626..00000000
--- a/alliance/share/cells/sxlib/noa2a22_x1.ap
+++ /dev/null
@@ -1,89 +0,0 @@
-V ALLIANCE : 6
-H noa2a22_x1,P,30/ 8/2000,100
-A 0,0,3500,5000
-R 1500,3500,ref_ref,nq_35
-R 1500,3000,ref_ref,nq_30
-R 1500,2500,ref_ref,nq_25
-R 1500,2000,ref_ref,nq_20
-R 1500,1500,ref_ref,nq_15
-R 1500,1000,ref_ref,nq_10
-R 2500,1000,ref_ref,i2_10
-R 2500,1500,ref_ref,i2_15
-R 2500,2000,ref_ref,i2_20
-R 2500,2500,ref_ref,i2_25
-R 2500,3000,ref_ref,i2_30
-R 2500,3500,ref_ref,i2_35
-R 2000,3500,ref_ref,i3_35
-R 2000,3000,ref_ref,i3_30
-R 2000,2500,ref_ref,i3_25
-R 2000,2000,ref_ref,i3_20
-R 2000,1500,ref_ref,i3_15
-R 2000,1000,ref_ref,i3_10
-R 1000,1000,ref_ref,i1_10
-R 1000,1500,ref_ref,i1_15
-R 1000,2000,ref_ref,i1_20
-R 1000,2500,ref_ref,i1_25
-R 1000,3000,ref_ref,i1_30
-R 500,3000,ref_ref,i0_30
-R 500,2500,ref_ref,i0_25
-R 500,2000,ref_ref,i0_20
-R 500,1500,ref_ref,i0_15
-R 500,1000,ref_ref,i0_10
-S 1500,1000,1500,3500,200,nq,DOWN,CALU1
-S 2500,1000,2500,3500,200,i2,DOWN,CALU1
-S 2000,1000,2000,3500,200,i3,DOWN,CALU1
-S 1000,1000,1000,3000,200,i1,DOWN,CALU1
-S 500,1000,500,3000,200,i0,DOWN,CALU1
-S 0,3900,3500,3900,2400,*,LEFT,NWELL
-S 3200,500,3200,1700,200,*,DOWN,ALU1
-S 3200,2900,3200,4500,200,*,DOWN,ALU1
-S 2700,3400,2700,4700,300,*,DOWN,PDIF
-S 2700,300,2700,1200,300,*,UP,NDIF
-S 0,4700,3500,4700,600,vdd,RIGHT,CALU1
-S 0,300,3500,300,600,vss,RIGHT,CALU1
-S 1000,2000,1200,2000,300,*,RIGHT,POLY
-S 1800,2000,2000,2000,300,*,RIGHT,POLY
-S 2400,100,2400,1400,100,*,DOWN,NTRANS
-S 2100,300,2100,1200,300,*,UP,NDIF
-S 1800,100,1800,1400,100,*,DOWN,NTRANS
-S 1500,300,1500,1200,300,*,UP,NDIF
-S 1200,100,1200,1400,100,*,DOWN,NTRANS
-S 900,300,900,1200,300,*,UP,NDIF
-S 300,300,300,1200,300,*,UP,NDIF
-S 600,100,600,1400,100,*,DOWN,NTRANS
-S 1200,2600,1200,4900,100,*,UP,PTRANS
-S 900,2800,900,4700,300,*,DOWN,PDIF
-S 600,2600,600,4900,100,*,UP,PTRANS
-S 300,2800,300,4700,300,*,DOWN,PDIF
-S 1500,2800,1500,4700,300,*,DOWN,PDIF
-S 1800,2600,1800,4900,100,*,UP,PTRANS
-S 2100,2800,2100,4700,300,*,DOWN,PDIF
-S 2400,2600,2400,4900,100,*,UP,PTRANS
-S 600,1400,600,2600,100,*,DOWN,POLY
-S 1200,1400,1200,2600,100,*,DOWN,POLY
-S 300,4000,2700,4000,100,*,RIGHT,ALU1
-S 2000,1000,2000,3500,100,*,DOWN,ALU1
-S 2500,1000,2500,3500,100,*,DOWN,ALU1
-S 1000,1000,1000,3000,100,*,DOWN,ALU1
-S 500,1000,500,3000,100,*,UP,ALU1
-S 1800,1400,1800,2600,100,*,DOWN,POLY
-S 2400,1400,2400,2600,100,*,DOWN,POLY
-S 2600,2800,2600,3300,300,*,UP,PDIF
-S 1500,1000,1500,3550,200,*,UP,ALU1
-S 900,3500,1550,3500,200,*,RIGHT,ALU1
-V 3200,2900,CONT_BODY_N,*
-V 3200,1700,CONT_BODY_P,*
-V 500,2000,CONT_POLY,*
-V 2500,2000,CONT_POLY,*
-V 1500,1000,CONT_DIF_N,*
-V 300,500,CONT_DIF_N,*
-V 2700,500,CONT_DIF_N,*
-V 1000,2000,CONT_POLY,*
-V 2000,2000,CONT_POLY,*
-V 300,4000,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 2700,4000,CONT_DIF_P,*
-V 2100,4500,CONT_DIF_P,*
-V 900,3500,CONT_DIF_P,*
-V 1500,1000,CONT_DIF_N,*
-EOF
diff --git a/alliance/share/cells/sxlib/noa2a22_x1.sym b/alliance/share/cells/sxlib/noa2a22_x1.sym
deleted file mode 100644
index 8a5d4d5c..00000000
Binary files a/alliance/share/cells/sxlib/noa2a22_x1.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/noa2a22_x1.vbe b/alliance/share/cells/sxlib/noa2a22_x1.vbe
deleted file mode 100644
index d6348198..00000000
--- a/alliance/share/cells/sxlib/noa2a22_x1.vbe
+++ /dev/null
@@ -1,44 +0,0 @@
-ENTITY noa2a22_x1 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 1750;
-  CONSTANT cin_i0	 : NATURAL := 14;
-  CONSTANT cin_i1	 : NATURAL := 14;
-  CONSTANT cin_i2	 : NATURAL := 14;
-  CONSTANT cin_i3	 : NATURAL := 14;
-  CONSTANT rdown_i0_nq	 : NATURAL := 2850;
-  CONSTANT rdown_i1_nq	 : NATURAL := 2850;
-  CONSTANT rdown_i2_nq	 : NATURAL := 2850;
-  CONSTANT rdown_i3_nq	 : NATURAL := 2850;
-  CONSTANT rup_i0_nq	 : NATURAL := 3210;
-  CONSTANT rup_i1_nq	 : NATURAL := 3210;
-  CONSTANT rup_i2_nq	 : NATURAL := 3210;
-  CONSTANT rup_i3_nq	 : NATURAL := 3210;
-  CONSTANT tphl_i0_nq	 : NATURAL := 151;
-  CONSTANT tphl_i1_nq	 : NATURAL := 218;
-  CONSTANT tplh_i3_nq	 : NATURAL := 256;
-  CONSTANT tphl_i2_nq	 : NATURAL := 284;
-  CONSTANT tplh_i1_nq	 : NATURAL := 287;
-  CONSTANT tplh_i2_nq	 : NATURAL := 289;
-  CONSTANT tplh_i0_nq	 : NATURAL := 327;
-  CONSTANT tphl_i3_nq	 : NATURAL := 372;
-  CONSTANT transistors	 : NATURAL := 8
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  i3	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END noa2a22_x1;
-
-ARCHITECTURE behaviour_data_flow OF noa2a22_x1 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on noa2a22_x1"
-  SEVERITY WARNING;
-  nq <= not (((i0 and i1) or (i2 and i3))) after 1000 ps;
-END;
diff --git a/alliance/share/cells/sxlib/noa2a22_x1.vhd b/alliance/share/cells/sxlib/noa2a22_x1.vhd
deleted file mode 100644
index acb4a088..00000000
--- a/alliance/share/cells/sxlib/noa2a22_x1.vhd
+++ /dev/null
@@ -1,22 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY noa2a22_x1 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  i3	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END noa2a22_x1;
-
-ARCHITECTURE RTL OF noa2a22_x1 IS
-BEGIN
-  nq <= NOT(((i0 AND i1) OR (i2 AND i3)));
-END RTL;
diff --git a/alliance/share/cells/sxlib/noa2a22_x4.al b/alliance/share/cells/sxlib/noa2a22_x4.al
deleted file mode 100644
index d5b7bc86..00000000
--- a/alliance/share/cells/sxlib/noa2a22_x4.al
+++ /dev/null
@@ -1,48 +0,0 @@
-V ALLIANCE : 6
-H noa2a22_x4,L,30/10/99
-C i0,IN,EXTERNAL,6
-C i1,IN,EXTERNAL,5
-C i2,IN,EXTERNAL,8
-C i3,IN,EXTERNAL,7
-C nq,OUT,EXTERNAL,9
-C vdd,IN,EXTERNAL,11
-C vss,IN,EXTERNAL,1
-T P,0.35,2.9,12,5,3,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00014
-T P,0.35,2.9,12,8,11,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00013
-T P,0.35,2.9,11,7,12,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00012
-T P,0.35,2.9,3,6,12,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00011
-T P,0.35,5.9,9,10,11,0,0.75,0.75,13.3,13.3,12.6,11.25,tr_00010
-T P,0.35,5.9,11,10,9,0,0.75,0.75,13.3,13.3,14.4,11.25,tr_00009
-T P,0.35,2.9,11,3,10,0,0.75,0.75,7.3,7.3,10.8,9.75,tr_00008
-T N,0.35,1.4,2,5,3,0,0.75,0.75,4.3,4.3,3.6,3,tr_00007
-T N,0.35,1.4,1,6,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00006
-T N,0.35,1.4,4,8,1,0,0.75,0.75,4.3,4.3,7.2,3,tr_00005
-T N,0.35,1.4,3,7,4,0,0.75,0.75,4.3,4.3,5.4,3,tr_00004
-T N,0.35,2.9,1,10,9,0,0.75,0.75,7.3,7.3,12.6,2.25,tr_00003
-T N,0.35,2.9,9,10,1,0,0.75,0.75,7.3,7.3,14.4,2.25,tr_00002
-T N,0.35,1.4,10,3,1,0,0.75,0.75,4.3,4.3,10.8,3,tr_00001
-S 12,INTERNAL
-Q 0.00199441
-S 11,EXTERNAL,vdd
-Q 0.00803103
-S 10,INTERNAL
-Q 0.00518414
-S 9,EXTERNAL,nq
-Q 0.00258522
-S 8,EXTERNAL,i2
-Q 0.00295462
-S 7,EXTERNAL,i3
-Q 0.00323197
-S 6,EXTERNAL,i0
-Q 0.00295462
-S 5,EXTERNAL,i1
-Q 0.00323197
-S 4,INTERNAL
-Q 0
-S 3,INTERNAL
-Q 0.00594323
-S 2,INTERNAL
-Q 0
-S 1,EXTERNAL,vss
-Q 0.00726721
-EOF
diff --git a/alliance/share/cells/sxlib/noa2a22_x4.ap b/alliance/share/cells/sxlib/noa2a22_x4.ap
deleted file mode 100644
index 4f40230e..00000000
--- a/alliance/share/cells/sxlib/noa2a22_x4.ap
+++ /dev/null
@@ -1,137 +0,0 @@
-V ALLIANCE : 6
-H noa2a22_x4,P,30/ 8/2000,100
-A 0,0,5500,5000
-R 4500,4000,ref_ref,nq_40
-R 2500,1000,ref_ref,i2_10
-R 2500,1500,ref_ref,i2_15
-R 2500,2000,ref_ref,i2_20
-R 2500,2500,ref_ref,i2_25
-R 2500,3000,ref_ref,i2_30
-R 2000,3000,ref_ref,i3_30
-R 2000,2500,ref_ref,i3_25
-R 2000,2000,ref_ref,i3_20
-R 2000,1500,ref_ref,i3_15
-R 2000,1000,ref_ref,i3_10
-R 1000,1000,ref_ref,i1_10
-R 1000,1500,ref_ref,i1_15
-R 1000,2000,ref_ref,i1_20
-R 1000,2500,ref_ref,i1_25
-R 1000,3000,ref_ref,i1_30
-R 500,3000,ref_ref,i0_30
-R 500,2500,ref_ref,i0_25
-R 500,2000,ref_ref,i0_20
-R 500,1500,ref_ref,i0_15
-R 500,1000,ref_ref,i0_10
-R 4500,3500,ref_ref,nq_35
-R 4500,3000,ref_ref,nq_30
-R 4500,2000,ref_ref,nq_20
-R 4500,1000,ref_ref,nq_10
-R 4500,1500,ref_ref,nq_15
-R 4500,2500,ref_ref,nq_25
-S 2500,1000,2500,3000,200,i2,DOWN,CALU1
-S 2000,1000,2000,3000,200,i3,DOWN,CALU1
-S 1000,1000,1000,3000,200,i1,DOWN,CALU1
-S 500,1000,500,3000,200,i0,DOWN,CALU1
-S 4500,1000,4500,4000,200,nq,DOWN,CALU1
-S 4500,1000,4500,4000,200,*,UP,ALU1
-S 0,3900,5500,3900,2400,*,RIGHT,NWELL
-S 2700,400,2700,1200,300,*,UP,NDIF
-S 300,400,300,1200,300,*,UP,NDIF
-S 2100,3300,2100,4600,300,*,DOWN,PDIF
-S 600,1400,600,3100,100,*,DOWN,POLY
-S 1200,1400,1200,3100,100,*,DOWN,POLY
-S 1800,1400,1800,3100,100,*,DOWN,POLY
-S 2400,1400,2400,3100,100,*,DOWN,POLY
-S 1200,600,1200,1400,100,*,DOWN,NTRANS
-S 900,800,900,1200,300,*,UP,NDIF
-S 600,600,600,1400,100,*,DOWN,NTRANS
-S 2400,600,2400,1400,100,*,DOWN,NTRANS
-S 2100,800,2100,1200,300,*,UP,NDIF
-S 1800,600,1800,1400,100,*,DOWN,NTRANS
-S 1500,800,1500,1200,300,*,UP,NDIF
-S 1200,3100,1200,4400,100,*,UP,PTRANS
-S 2400,3100,2400,4400,100,*,UP,PTRANS
-S 1800,3100,1800,4400,100,*,UP,PTRANS
-S 2700,3300,2700,4200,300,*,DOWN,PDIF
-S 1500,3300,1500,4200,300,*,DOWN,PDIF
-S 300,3300,300,4200,300,*,DOWN,PDIF
-S 600,3100,600,4400,100,*,UP,PTRANS
-S 900,3300,900,4200,300,*,DOWN,PDIF
-S 4000,2000,4800,2000,300,*,RIGHT,POLY
-S 3900,500,3900,1000,200,*,DOWN,ALU1
-S 5100,500,5100,1000,200,*,DOWN,ALU1
-S 5100,3000,5100,4500,200,*,DOWN,ALU1
-S 3900,4000,3900,4500,200,*,DOWN,ALU1
-S 3600,2500,3800,2500,300,*,RIGHT,POLY
-S 3300,2000,4000,2000,100,*,RIGHT,ALU1
-S 4800,1400,4800,2600,100,*,DOWN,POLY
-S 4200,1400,4200,2600,100,*,DOWN,POLY
-S 3600,1400,3600,2600,100,*,DOWN,POLY
-S 3800,2500,3800,3500,100,*,DOWN,ALU1
-S 900,3500,3800,3500,100,*,RIGHT,ALU1
-S 2500,1000,2500,3000,100,*,DOWN,ALU1
-S 2000,1000,2000,3000,100,*,DOWN,ALU1
-S 1000,2000,1200,2000,300,*,RIGHT,POLY
-S 1800,2000,2000,2000,300,*,RIGHT,POLY
-S 300,4000,2700,4000,100,*,RIGHT,ALU1
-S 1000,1000,1000,3000,100,*,DOWN,ALU1
-S 500,1000,500,3000,100,*,UP,ALU1
-S 0,300,5500,300,600,vss,RIGHT,CALU1
-S 0,4700,5500,4700,600,vdd,RIGHT,CALU1
-S 4200,100,4200,1400,100,*,DOWN,NTRANS
-S 4800,100,4800,1400,100,*,DOWN,NTRANS
-S 3900,300,3900,1200,300,*,UP,NDIF
-S 4500,300,4500,1200,300,*,UP,NDIF
-S 5100,300,5100,1200,300,*,UP,NDIF
-S 3600,600,3600,1400,100,*,DOWN,NTRANS
-S 4200,2600,4200,4900,100,*,UP,PTRANS
-S 4800,2600,4800,4900,100,*,UP,PTRANS
-S 4500,2800,4500,4700,300,*,DOWN,PDIF
-S 3900,2800,3900,4700,300,*,DOWN,PDIF
-S 5100,2800,5100,4700,300,*,DOWN,PDIF
-S 3600,2600,3600,3900,100,*,UP,PTRANS
-S 3300,2800,3300,3700,300,*,DOWN,PDIF
-S 3300,800,3300,1200,300,*,UP,NDIF
-S 3300,1000,3300,3000,100,*,DOWN,ALU1
-S 1500,1000,1500,3500,100,*,UP,ALU1
-S 300,4700,1500,4700,300,*,RIGHT,NTIE
-S 900,300,2100,300,300,*,LEFT,PTIE
-V 1500,4700,CONT_BODY_N,*
-V 300,4700,CONT_BODY_N,*
-V 3300,4700,CONT_BODY_N,*
-V 4000,2000,CONT_POLY,*
-V 5100,1000,CONT_DIF_N,*
-V 3900,1000,CONT_DIF_N,*
-V 3300,1000,CONT_DIF_N,*
-V 3300,3000,CONT_DIF_P,*
-V 5100,3000,CONT_DIF_P,*
-V 5100,3500,CONT_DIF_P,*
-V 5100,4000,CONT_DIF_P,*
-V 5100,4500,CONT_DIF_P,*
-V 3900,4500,CONT_DIF_P,*
-V 3900,4000,CONT_DIF_P,*
-V 3800,2500,CONT_POLY,*
-V 500,2000,CONT_POLY,*
-V 2500,2000,CONT_POLY,*
-V 300,500,CONT_DIF_N,*
-V 2700,500,CONT_DIF_N,*
-V 1000,2000,CONT_POLY,*
-V 2000,2000,CONT_POLY,*
-V 300,4000,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 2700,4000,CONT_DIF_P,*
-V 2100,4500,CONT_DIF_P,*
-V 900,3500,CONT_DIF_P,*
-V 3900,500,CONT_DIF_N,*
-V 5100,500,CONT_DIF_N,*
-V 3300,300,CONT_BODY_P,*
-V 4500,1000,CONT_DIF_N,*
-V 1500,1000,CONT_DIF_N,*
-V 900,4700,CONT_BODY_N,*
-V 1500,300,CONT_BODY_P,*
-V 900,300,CONT_BODY_P,*
-V 2100,300,CONT_BODY_P,*
-V 4500,3000,CONT_DIF_P,*
-V 4500,3500,CONT_DIF_P,*
-V 4500,4000,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/noa2a22_x4.sym b/alliance/share/cells/sxlib/noa2a22_x4.sym
deleted file mode 100644
index aac4b28c..00000000
Binary files a/alliance/share/cells/sxlib/noa2a22_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/noa2a22_x4.vbe b/alliance/share/cells/sxlib/noa2a22_x4.vbe
deleted file mode 100644
index 93e31d34..00000000
--- a/alliance/share/cells/sxlib/noa2a22_x4.vbe
+++ /dev/null
@@ -1,44 +0,0 @@
-ENTITY noa2a22_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 2750;
-  CONSTANT cin_i0	 : NATURAL := 8;
-  CONSTANT cin_i1	 : NATURAL := 8;
-  CONSTANT cin_i2	 : NATURAL := 8;
-  CONSTANT cin_i3	 : NATURAL := 8;
-  CONSTANT rdown_i0_nq	 : NATURAL := 810;
-  CONSTANT rdown_i1_nq	 : NATURAL := 810;
-  CONSTANT rdown_i2_nq	 : NATURAL := 810;
-  CONSTANT rdown_i3_nq	 : NATURAL := 810;
-  CONSTANT rup_i0_nq	 : NATURAL := 890;
-  CONSTANT rup_i1_nq	 : NATURAL := 890;
-  CONSTANT rup_i2_nq	 : NATURAL := 890;
-  CONSTANT rup_i3_nq	 : NATURAL := 890;
-  CONSTANT tphl_i0_nq	 : NATURAL := 562;
-  CONSTANT tphl_i1_nq	 : NATURAL := 646;
-  CONSTANT tplh_i3_nq	 : NATURAL := 677;
-  CONSTANT tphl_i2_nq	 : NATURAL := 701;
-  CONSTANT tplh_i2_nq	 : NATURAL := 703;
-  CONSTANT tplh_i1_nq	 : NATURAL := 714;
-  CONSTANT tplh_i0_nq	 : NATURAL := 745;
-  CONSTANT tphl_i3_nq	 : NATURAL := 805;
-  CONSTANT transistors	 : NATURAL := 14
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  i3	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END noa2a22_x4;
-
-ARCHITECTURE behaviour_data_flow OF noa2a22_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on noa2a22_x4"
-  SEVERITY WARNING;
-  nq <= not (((i0 and i1) or (i2 and i3))) after 1400 ps;
-END;
diff --git a/alliance/share/cells/sxlib/noa2a22_x4.vhd b/alliance/share/cells/sxlib/noa2a22_x4.vhd
deleted file mode 100644
index 73870fd0..00000000
--- a/alliance/share/cells/sxlib/noa2a22_x4.vhd
+++ /dev/null
@@ -1,22 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY noa2a22_x4 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  i3	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END noa2a22_x4;
-
-ARCHITECTURE RTL OF noa2a22_x4 IS
-BEGIN
-  nq <= NOT(((i0 AND i1) OR (i2 AND i3)));
-END RTL;
diff --git a/alliance/share/cells/sxlib/noa2a2a23_x1.al b/alliance/share/cells/sxlib/noa2a2a23_x1.al
deleted file mode 100644
index c68647d7..00000000
--- a/alliance/share/cells/sxlib/noa2a2a23_x1.al
+++ /dev/null
@@ -1,52 +0,0 @@
-V ALLIANCE : 6
-H noa2a2a23_x1,L,30/10/99
-C i0,IN,EXTERNAL,13
-C i1,IN,EXTERNAL,14
-C i2,IN,EXTERNAL,9
-C i3,IN,EXTERNAL,8
-C i4,IN,EXTERNAL,7
-C i5,IN,EXTERNAL,10
-C nq,OUT,EXTERNAL,2
-C vdd,IN,EXTERNAL,12
-C vss,IN,EXTERNAL,1
-T P,0.35,5.9,5,7,2,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00012
-T P,0.35,5.9,2,10,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00011
-T P,0.35,5.9,5,9,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00010
-T P,0.35,5.9,6,8,5,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00009
-T P,0.35,5.9,12,13,6,0,0.75,0.75,13.3,13.3,13.2,11.25,tr_00008
-T P,0.35,5.9,6,14,12,0,0.75,0.75,13.3,13.3,11.4,11.25,tr_00007
-T N,0.35,2.9,4,8,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00006
-T N,0.35,2.9,2,7,3,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00005
-T N,0.35,2.9,1,13,11,0,0.75,0.75,7.3,7.3,13.2,2.25,tr_00004
-T N,0.35,2.9,11,14,2,0,0.75,0.75,7.3,7.3,12,2.25,tr_00003
-T N,0.35,2.9,1,9,4,0,0.75,0.75,7.3,7.3,6.6,2.25,tr_00002
-T N,0.35,2.9,3,10,1,0,0.75,0.75,7.3,7.3,2.4,2.25,tr_00001
-S 14,EXTERNAL,i1
-Q 0.0026959
-S 13,EXTERNAL,i0
-Q 0.00232574
-S 12,EXTERNAL,vdd
-Q 0.00651445
-S 11,INTERNAL
-Q 0
-S 10,EXTERNAL,i5
-Q 0.00276531
-S 9,EXTERNAL,i2
-Q 0.00254552
-S 8,EXTERNAL,i3
-Q 0.00262649
-S 7,EXTERNAL,i4
-Q 0.00304715
-S 6,INTERNAL
-Q 0.00198726
-S 5,INTERNAL
-Q 0.00199441
-S 4,INTERNAL
-Q 0
-S 3,INTERNAL
-Q 0
-S 2,EXTERNAL,nq
-Q 0.00458289
-S 1,EXTERNAL,vss
-Q 0.00575064
-EOF
diff --git a/alliance/share/cells/sxlib/noa2a2a23_x1.ap b/alliance/share/cells/sxlib/noa2a2a23_x1.ap
deleted file mode 100644
index a7d59c4a..00000000
--- a/alliance/share/cells/sxlib/noa2a2a23_x1.ap
+++ /dev/null
@@ -1,124 +0,0 @@
-V ALLIANCE : 6
-H noa2a2a23_x1,P,30/ 8/2000,100
-A 0,0,5000,5000
-R 1000,2000,ref_ref,i5_20
-R 1000,2500,ref_ref,i5_25
-R 1000,3000,ref_ref,i5_30
-R 1000,1500,ref_ref,i5_15
-R 2000,1500,ref_ref,i3_15
-R 2000,2500,ref_ref,i3_25
-R 2000,3000,ref_ref,i3_30
-R 2500,1500,ref_ref,i2_15
-R 2500,2000,ref_ref,i2_20
-R 2500,2500,ref_ref,i2_25
-R 2500,3000,ref_ref,i2_30
-R 2000,2000,ref_ref,i3_20
-R 1500,1500,ref_ref,i4_15
-R 1500,2000,ref_ref,i4_20
-R 1500,2500,ref_ref,i4_25
-R 500,2500,ref_ref,nq_25
-R 500,2000,ref_ref,nq_20
-R 500,1500,ref_ref,nq_15
-R 500,3500,ref_ref,nq_35
-R 500,3000,ref_ref,nq_30
-R 4000,2000,ref_ref,i1_20
-R 4500,2500,ref_ref,i0_25
-R 4500,2000,ref_ref,i0_20
-R 4500,1500,ref_ref,i0_15
-R 4500,3000,ref_ref,i0_30
-R 4000,3000,ref_ref,i1_30
-R 4000,2500,ref_ref,i1_25
-R 4000,1500,ref_ref,i1_15
-R 500,1000,ref_ref,nq_10
-R 1500,3000,ref_ref,i4_30
-R 1500,3500,ref_ref,i4_35
-S 1000,1500,1000,3000,200,i5,DOWN,CALU1
-S 2500,1500,2500,3000,200,i2,DOWN,CALU1
-S 2000,1500,2000,3000,200,i3,DOWN,CALU1
-S 4500,1500,4500,3000,200,i0,DOWN,CALU1
-S 4000,1500,4000,3000,200,i1,DOWN,CALU1
-S 500,1000,500,3500,200,nq,DOWN,CALU1
-S 1500,1500,1500,3500,200,i4,DOWN,CALU1
-S 300,4000,2700,4000,100,*,RIGHT,ALU1
-S 2400,1400,2400,2600,100,*,DOWN,POLY
-S 1800,100,1800,1400,100,*,UP,NTRANS
-S 1500,300,1500,1200,300,*,DOWN,NDIF
-S 1200,100,1200,1400,100,*,UP,NTRANS
-S 2100,2800,2100,4700,300,*,UP,PDIF
-S 900,2800,900,4700,300,*,UP,PDIF
-S 1500,2800,1500,4700,300,*,UP,PDIF
-S 1200,2600,1200,4900,100,*,UP,PTRANS
-S 600,2600,600,4900,100,*,UP,PTRANS
-S 2400,2600,2400,4900,100,*,UP,PTRANS
-S 1800,2600,1800,4900,100,*,UP,PTRANS
-S 300,2800,300,4700,300,*,UP,PDIF
-S 4700,300,4700,1000,200,*,DOWN,ALU1
-S 4400,1400,4400,2600,100,*,DOWN,POLY
-S 4400,100,4400,1400,100,*,UP,NTRANS
-S 4400,2600,4400,4900,100,*,UP,PTRANS
-S 4100,2800,4100,4700,300,*,UP,PDIF
-S 3800,2600,3800,4900,100,*,UP,PTRANS
-S 1000,1500,1000,3000,100,*,UP,ALU1
-S 2000,1500,2000,3000,100,*,UP,ALU1
-S 2500,1500,2500,3000,100,*,UP,ALU1
-S 1800,2600,1900,2600,100,*,RIGHT,POLY
-S 1900,1400,1900,2600,100,*,DOWN,POLY
-S 1800,1400,1900,1400,100,*,LEFT,POLY
-S 1200,1400,1400,1400,100,*,RIGHT,POLY
-S 1400,1400,1400,2600,100,*,UP,POLY
-S 1200,2600,1400,2600,100,*,LEFT,POLY
-S 600,2600,900,2600,100,*,RIGHT,POLY
-S 900,1400,900,2600,100,*,DOWN,POLY
-S 500,950,500,3550,200,*,DOWN,ALU1
-S 450,3500,900,3500,200,*,RIGHT,ALU1
-S 3500,4000,3500,4700,200,*,UP,ALU1
-S 2100,3500,4100,3500,100,*,RIGHT,ALU1
-S 4100,3500,4100,4000,100,*,UP,ALU1
-S 4700,2800,4700,4700,300,*,UP,PDIF
-S 4700,3500,4700,4600,200,*,DOWN,ALU1
-S 3700,300,3700,1200,300,*,DOWN,NDIF
-S 4000,100,4000,1400,100,*,UP,NTRANS
-S 4700,300,4700,1200,300,*,DOWN,NDIF
-S 4000,1400,4000,2500,100,*,UP,POLY
-S 3800,2500,4000,2500,100,*,LEFT,POLY
-S 3800,2500,3800,2700,100,*,UP,POLY
-S 2500,300,2500,1200,300,*,DOWN,NDIF
-S 2200,100,2200,1400,100,*,UP,NTRANS
-S 2200,1400,2400,1400,100,*,RIGHT,POLY
-S 800,100,800,1400,100,*,UP,NTRANS
-S 500,300,500,1200,300,*,DOWN,NDIF
-S 800,1400,900,1400,100,*,LEFT,POLY
-S 0,300,5000,300,600,vss,RIGHT,CALU1
-S 0,3900,5000,3900,2400,*,RIGHT,NWELL
-S 0,4700,5000,4700,600,vdd,RIGHT,CALU1
-S 4500,1500,4500,3000,100,*,UP,ALU1
-S 4000,1500,4000,3000,100,*,UP,ALU1
-S 1500,1500,1500,3500,100,*,UP,ALU1
-S 2700,2800,2700,4100,300,*,UP,PDIF
-S 3500,2800,3500,4100,300,*,UP,PDIF
-S 450,1000,3700,1000,200,*,LEFT,ALU1
-V 1500,1000,CONT_DIF_N,*
-V 900,3500,CONT_DIF_P,*
-V 2100,3500,CONT_DIF_P,*
-V 300,4000,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 2700,4000,CONT_DIF_P,*
-V 3900,2500,CONT_POLY,*
-V 4700,1000,CONT_DIF_N,*
-V 4100,4000,CONT_DIF_P,*
-V 4700,4000,CONT_DIF_P,*
-V 3100,4600,CONT_BODY_N,*
-V 2500,2500,CONT_POLY,*
-V 2000,2500,CONT_POLY,*
-V 1500,2000,CONT_POLY,*
-V 1000,2000,CONT_POLY,*
-V 3500,4000,CONT_DIF_P,*
-V 4700,4500,CONT_DIF_P,*
-V 4700,3500,CONT_DIF_P,*
-V 3700,1000,CONT_DIF_N,*
-V 4700,500,CONT_DIF_N,*
-V 2500,500,CONT_DIF_N,*
-V 500,500,CONT_DIF_N,*
-V 3100,400,CONT_BODY_P,*
-V 4500,2500,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/sxlib/noa2a2a23_x1.sym b/alliance/share/cells/sxlib/noa2a2a23_x1.sym
deleted file mode 100644
index 87e8c14f..00000000
Binary files a/alliance/share/cells/sxlib/noa2a2a23_x1.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/noa2a2a23_x1.vbe b/alliance/share/cells/sxlib/noa2a2a23_x1.vbe
deleted file mode 100644
index 2d90886a..00000000
--- a/alliance/share/cells/sxlib/noa2a2a23_x1.vbe
+++ /dev/null
@@ -1,56 +0,0 @@
-ENTITY noa2a2a23_x1 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 2500;
-  CONSTANT cin_i0	 : NATURAL := 13;
-  CONSTANT cin_i1	 : NATURAL := 14;
-  CONSTANT cin_i2	 : NATURAL := 14;
-  CONSTANT cin_i3	 : NATURAL := 14;
-  CONSTANT cin_i4	 : NATURAL := 14;
-  CONSTANT cin_i5	 : NATURAL := 14;
-  CONSTANT rdown_i0_nq	 : NATURAL := 2850;
-  CONSTANT rdown_i1_nq	 : NATURAL := 2850;
-  CONSTANT rdown_i2_nq	 : NATURAL := 2850;
-  CONSTANT rdown_i3_nq	 : NATURAL := 2850;
-  CONSTANT rdown_i4_nq	 : NATURAL := 2850;
-  CONSTANT rdown_i5_nq	 : NATURAL := 2850;
-  CONSTANT rup_i0_nq	 : NATURAL := 4690;
-  CONSTANT rup_i1_nq	 : NATURAL := 4690;
-  CONSTANT rup_i2_nq	 : NATURAL := 4690;
-  CONSTANT rup_i3_nq	 : NATURAL := 4690;
-  CONSTANT rup_i4_nq	 : NATURAL := 4690;
-  CONSTANT rup_i5_nq	 : NATURAL := 4690;
-  CONSTANT tphl_i5_nq	 : NATURAL := 178;
-  CONSTANT tphl_i4_nq	 : NATURAL := 250;
-  CONSTANT tphl_i2_nq	 : NATURAL := 307;
-  CONSTANT tplh_i1_nq	 : NATURAL := 388;
-  CONSTANT tphl_i3_nq	 : NATURAL := 398;
-  CONSTANT tplh_i4_nq	 : NATURAL := 416;
-  CONSTANT tplh_i0_nq	 : NATURAL := 425;
-  CONSTANT tplh_i3_nq	 : NATURAL := 438;
-  CONSTANT tplh_i5_nq	 : NATURAL := 464;
-  CONSTANT tplh_i2_nq	 : NATURAL := 479;
-  CONSTANT tphl_i0_nq	 : NATURAL := 525;
-  CONSTANT tphl_i1_nq	 : NATURAL := 643;
-  CONSTANT transistors	 : NATURAL := 12
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  i3	 : in  BIT;
-  i4	 : in  BIT;
-  i5	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END noa2a2a23_x1;
-
-ARCHITECTURE behaviour_data_flow OF noa2a2a23_x1 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on noa2a2a23_x1"
-  SEVERITY WARNING;
-  nq <= not ((((i0 and i1) or (i2 and i3)) or (i4 and i5))) after 1200 ps;
-END;
diff --git a/alliance/share/cells/sxlib/noa2a2a23_x1.vhd b/alliance/share/cells/sxlib/noa2a2a23_x1.vhd
deleted file mode 100644
index 13c08812..00000000
--- a/alliance/share/cells/sxlib/noa2a2a23_x1.vhd
+++ /dev/null
@@ -1,24 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY noa2a2a23_x1 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  i3	: IN STD_LOGIC;
-  i4	: IN STD_LOGIC;
-  i5	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END noa2a2a23_x1;
-
-ARCHITECTURE RTL OF noa2a2a23_x1 IS
-BEGIN
-  nq <= NOT((((i0 AND i1) OR (i2 AND i3)) OR (i4 AND i5)));
-END RTL;
diff --git a/alliance/share/cells/sxlib/noa2a2a23_x4.al b/alliance/share/cells/sxlib/noa2a2a23_x4.al
deleted file mode 100644
index 5bd111a2..00000000
--- a/alliance/share/cells/sxlib/noa2a2a23_x4.al
+++ /dev/null
@@ -1,62 +0,0 @@
-V ALLIANCE : 6
-H noa2a2a23_x4,L,30/10/99
-C i0,IN,EXTERNAL,15
-C i1,IN,EXTERNAL,16
-C i2,IN,EXTERNAL,9
-C i3,IN,EXTERNAL,10
-C i4,IN,EXTERNAL,7
-C i5,IN,EXTERNAL,8
-C nq,OUT,EXTERNAL,13
-C vdd,IN,EXTERNAL,14
-C vss,IN,EXTERNAL,1
-T P,0.35,2.9,11,4,14,0,0.75,0.75,7.3,7.3,17.7,9.75,tr_00018
-T P,0.35,5.9,5,16,14,0,0.75,0.75,13.3,13.3,10.5,11.25,tr_00017
-T P,0.35,5.9,13,11,14,0,0.75,0.75,13.3,13.3,14.1,11.25,tr_00016
-T P,0.35,5.9,14,11,13,0,0.75,0.75,13.3,13.3,15.9,11.25,tr_00015
-T P,0.35,5.9,14,15,5,0,0.75,0.75,13.3,13.3,12.3,11.25,tr_00014
-T P,0.35,5.9,5,10,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00013
-T P,0.35,5.9,6,9,5,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00012
-T P,0.35,5.9,4,8,6,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00011
-T P,0.35,5.9,6,7,4,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00010
-T N,0.35,1.4,1,4,11,0,0.75,0.75,4.3,4.3,17.7,3,tr_00009
-T N,0.35,2.9,1,15,12,0,0.75,0.75,7.3,7.3,12.3,2.25,tr_00008
-T N,0.35,2.9,12,16,4,0,0.75,0.75,7.3,7.3,11.1,2.25,tr_00007
-T N,0.35,2.9,13,11,1,0,0.75,0.75,7.3,7.3,14.1,2.25,tr_00006
-T N,0.35,2.9,13,11,1,0,0.75,0.75,7.3,7.3,15.9,2.25,tr_00005
-T N,0.35,2.9,3,8,1,0,0.75,0.75,7.3,7.3,2.4,2.25,tr_00004
-T N,0.35,2.9,1,9,2,0,0.75,0.75,7.3,7.3,6.6,2.25,tr_00003
-T N,0.35,2.9,4,7,3,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002
-T N,0.35,2.9,2,10,4,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00001
-S 16,EXTERNAL,i1
-Q 0.00247612
-S 15,EXTERNAL,i0
-Q 0.00232574
-S 14,EXTERNAL,vdd
-Q 0.00830269
-S 13,EXTERNAL,nq
-Q 0.0023502
-S 12,INTERNAL
-Q 0
-S 11,INTERNAL
-Q 0.0053368
-S 10,EXTERNAL,i3
-Q 0.00262649
-S 9,EXTERNAL,i2
-Q 0.00254552
-S 8,EXTERNAL,i5
-Q 0.0027653
-S 7,EXTERNAL,i4
-Q 0.00304715
-S 6,INTERNAL
-Q 0.00199441
-S 5,INTERNAL
-Q 0.00181815
-S 4,INTERNAL
-Q 0.00716684
-S 3,INTERNAL
-Q 0
-S 2,INTERNAL
-Q 0
-S 1,EXTERNAL,vss
-Q 0.00624627
-EOF
diff --git a/alliance/share/cells/sxlib/noa2a2a23_x4.ap b/alliance/share/cells/sxlib/noa2a2a23_x4.ap
deleted file mode 100644
index 2f058c38..00000000
--- a/alliance/share/cells/sxlib/noa2a2a23_x4.ap
+++ /dev/null
@@ -1,156 +0,0 @@
-V ALLIANCE : 6
-H noa2a2a23_x4,P, 6/ 9/2000,100
-A 0,0,6500,5000
-R 1000,2000,ref_ref,i5_20
-R 1000,2500,ref_ref,i5_25
-R 1000,3000,ref_ref,i5_30
-R 1000,1500,ref_ref,i5_15
-R 2000,1500,ref_ref,i3_15
-R 2000,2500,ref_ref,i3_25
-R 2000,3000,ref_ref,i3_30
-R 2500,1500,ref_ref,i2_15
-R 2500,2000,ref_ref,i2_20
-R 2500,2500,ref_ref,i2_25
-R 2500,3000,ref_ref,i2_30
-R 2000,2000,ref_ref,i3_20
-R 1500,1500,ref_ref,i4_15
-R 1500,2000,ref_ref,i4_20
-R 1500,2500,ref_ref,i4_25
-R 1500,3000,ref_ref,i4_30
-R 1500,3500,ref_ref,i4_35
-R 4000,2000,ref_ref,i0_20
-R 4000,2500,ref_ref,i0_25
-R 3500,2000,ref_ref,i1_20
-R 3500,1500,ref_ref,i1_15
-R 3500,2500,ref_ref,i1_25
-R 3500,3000,ref_ref,i1_30
-R 4000,3000,ref_ref,i0_30
-R 4000,1500,ref_ref,i0_15
-R 5000,2000,ref_ref,nq_20
-R 5000,2500,ref_ref,nq_25
-R 5000,3000,ref_ref,nq_30
-R 5000,3500,ref_ref,nq_35
-R 5000,1500,ref_ref,nq_15
-R 5000,4000,ref_ref,nq_40
-S 5700,1500,5900,1500,300,*,RIGHT,POLY
-S 5300,2000,5500,2000,300,*,LEFT,POLY
-S 5000,300,5000,1500,300,*,DOWN,NDIF
-S 300,4000,2700,4000,100,*,RIGHT,ALU1
-S 2400,1400,2400,2600,100,*,DOWN,POLY
-S 1800,100,1800,1400,100,*,UP,NTRANS
-S 1500,300,1500,1200,300,*,DOWN,NDIF
-S 1200,100,1200,1400,100,*,UP,NTRANS
-S 2100,2800,2100,4700,300,*,UP,PDIF
-S 900,2800,900,4700,300,*,UP,PDIF
-S 1500,2800,1500,4700,300,*,UP,PDIF
-S 1200,2600,1200,4900,100,*,UP,PTRANS
-S 600,2600,600,4900,100,*,UP,PTRANS
-S 2400,2600,2400,4900,100,*,UP,PTRANS
-S 1800,2600,1800,4900,100,*,UP,PTRANS
-S 300,2800,300,4700,300,*,UP,PDIF
-S 1000,1500,1000,3000,100,*,UP,ALU1
-S 2000,1500,2000,3000,100,*,UP,ALU1
-S 2500,1500,2500,3000,100,*,UP,ALU1
-S 1800,2600,1900,2600,100,*,RIGHT,POLY
-S 1900,1400,1900,2600,100,*,DOWN,POLY
-S 1800,1400,1900,1400,100,*,LEFT,POLY
-S 1200,1400,1400,1400,100,*,RIGHT,POLY
-S 1400,1400,1400,2600,100,*,UP,POLY
-S 1200,2600,1400,2600,100,*,LEFT,POLY
-S 600,2600,900,2600,100,*,RIGHT,POLY
-S 900,1400,900,2600,100,*,DOWN,POLY
-S 2500,300,2500,1200,300,*,DOWN,NDIF
-S 2200,100,2200,1400,100,*,UP,NTRANS
-S 2200,1400,2400,1400,100,*,RIGHT,POLY
-S 800,100,800,1400,100,*,UP,NTRANS
-S 500,300,500,1200,300,*,DOWN,NDIF
-S 800,1400,900,1400,100,*,LEFT,POLY
-S 1500,1500,1500,3500,100,*,UP,ALU1
-S 0,3900,6500,3900,2400,*,RIGHT,NWELL
-S 0,300,6500,300,600,vss,RIGHT,CALU1
-S 0,4700,6500,4700,600,vdd,RIGHT,CALU1
-S 500,3450,900,3450,100,*,LEFT,ALU1
-S 500,1000,500,3450,100,*,DOWN,ALU1
-S 3500,1500,3500,3000,100,*,UP,ALU1
-S 4000,1500,4000,3000,100,*,UP,ALU1
-S 4400,3500,4400,4600,200,*,DOWN,ALU1
-S 3800,3500,3800,4000,100,*,UP,ALU1
-S 5600,3500,5600,4600,200,*,DOWN,ALU1
-S 3500,1400,3500,2500,100,*,UP,POLY
-S 4100,1400,4100,2600,100,*,DOWN,POLY
-S 3500,1400,3700,1400,100,*,LEFT,POLY
-S 4700,1400,4700,2600,100,*,DOWN,POLY
-S 5300,1400,5300,2600,100,*,DOWN,POLY
-S 5300,100,5300,1400,100,*,DOWN,NTRANS
-S 4700,100,4700,1400,100,*,UP,NTRANS
-S 5600,300,5600,1200,300,*,DOWN,NDIF
-S 4400,300,4400,1200,300,*,DOWN,NDIF
-S 3400,300,3400,1200,300,*,DOWN,NDIF
-S 3700,100,3700,1400,100,*,UP,NTRANS
-S 4100,100,4100,1400,100,*,UP,NTRANS
-S 4100,2600,4100,4900,100,*,UP,PTRANS
-S 3800,2800,3800,4700,300,*,UP,PDIF
-S 4400,2800,4400,4700,300,*,UP,PDIF
-S 5600,2800,5600,4700,300,*,UP,PDIF
-S 5000,2800,5000,4700,300,*,UP,PDIF
-S 5300,2600,5300,4900,100,*,UP,PTRANS
-S 4700,2600,4700,4900,100,*,UP,PTRANS
-S 3500,2600,3500,4900,100,*,UP,PTRANS
-S 5900,600,5900,1400,100,*,DOWN,NTRANS
-S 5900,2600,5900,3900,100,*,UP,PTRANS
-S 6200,800,6200,1200,300,*,DOWN,NDIF
-S 6200,2800,6200,3700,300,*,UP,PDIF
-S 2700,2800,2700,4000,300,*,UP,PDIF
-S 3250,2800,3250,4600,200,*,DOWN,PDIF
-S 5000,1450,5000,4050,200,*,DOWN,ALU1
-S 5900,1400,5900,2600,100,*,UP,POLY
-S 4700,2000,5300,2000,100,*,RIGHT,POLY
-S 500,1000,5700,1000,100,*,RIGHT,ALU1
-S 5700,1000,5700,1500,100,*,UP,ALU1
-S 5500,2000,6200,2000,100,*,RIGHT,ALU1
-S 6200,1000,6200,3500,100,*,DOWN,ALU1
-S 2100,3500,3800,3500,100,*,RIGHT,ALU1
-S 1000,1500,1000,3000,200,i5,DOWN,CALU1
-S 2000,1500,2000,3000,200,i3,DOWN,CALU1
-S 2500,1500,2500,3000,200,i2,DOWN,CALU1
-S 1500,1500,1500,3500,200,i4,DOWN,CALU1
-S 4000,1500,4000,3000,200,i0,DOWN,CALU1
-S 3500,1500,3500,3000,200,i1,DOWN,CALU1
-S 5000,1500,5000,4000,200,nq,DOWN,CALU1
-V 5000,1500,CONT_DIF_N,*
-V 1500,1000,CONT_DIF_N,*
-V 900,3500,CONT_DIF_P,*
-V 2100,3500,CONT_DIF_P,*
-V 300,4000,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 2700,4000,CONT_DIF_P,*
-V 2500,2500,CONT_POLY,*
-V 2000,2500,CONT_POLY,*
-V 1500,2000,CONT_POLY,*
-V 1000,2000,CONT_POLY,*
-V 2500,500,CONT_DIF_N,*
-V 500,500,CONT_DIF_N,*
-V 4000,2500,CONT_POLY,*
-V 3500,2500,CONT_POLY,*
-V 5600,500,CONT_DIF_N,*
-V 3400,1000,CONT_DIF_N,*
-V 4400,500,CONT_DIF_N,*
-V 5000,3000,CONT_DIF_P,*
-V 5600,4000,CONT_DIF_P,*
-V 5600,4500,CONT_DIF_P,*
-V 5600,3500,CONT_DIF_P,*
-V 3800,4000,CONT_DIF_P,*
-V 4400,3500,CONT_DIF_P,*
-V 4400,4500,CONT_DIF_P,*
-V 4400,4000,CONT_DIF_P,*
-V 5000,4000,CONT_DIF_P,*
-V 5000,3500,CONT_DIF_P,*
-V 6200,1000,CONT_DIF_N,*
-V 6200,3000,CONT_DIF_P,*
-V 6200,3500,CONT_DIF_P,*
-V 6200,4600,CONT_BODY_N,*
-V 6200,300,CONT_BODY_P,*
-V 3200,4600,CONT_DIF_P,*
-V 5500,2000,CONT_POLY,*
-V 5700,1500,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/sxlib/noa2a2a23_x4.sym b/alliance/share/cells/sxlib/noa2a2a23_x4.sym
deleted file mode 100644
index 2fd94d25..00000000
Binary files a/alliance/share/cells/sxlib/noa2a2a23_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/noa2a2a23_x4.vbe b/alliance/share/cells/sxlib/noa2a2a23_x4.vbe
deleted file mode 100644
index 32820940..00000000
--- a/alliance/share/cells/sxlib/noa2a2a23_x4.vbe
+++ /dev/null
@@ -1,56 +0,0 @@
-ENTITY noa2a2a23_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 3250;
-  CONSTANT cin_i0	 : NATURAL := 13;
-  CONSTANT cin_i1	 : NATURAL := 14;
-  CONSTANT cin_i2	 : NATURAL := 14;
-  CONSTANT cin_i3	 : NATURAL := 14;
-  CONSTANT cin_i4	 : NATURAL := 14;
-  CONSTANT cin_i5	 : NATURAL := 14;
-  CONSTANT rdown_i0_nq	 : NATURAL := 810;
-  CONSTANT rdown_i1_nq	 : NATURAL := 810;
-  CONSTANT rdown_i2_nq	 : NATURAL := 810;
-  CONSTANT rdown_i3_nq	 : NATURAL := 810;
-  CONSTANT rdown_i4_nq	 : NATURAL := 810;
-  CONSTANT rdown_i5_nq	 : NATURAL := 810;
-  CONSTANT rup_i0_nq	 : NATURAL := 890;
-  CONSTANT rup_i1_nq	 : NATURAL := 890;
-  CONSTANT rup_i2_nq	 : NATURAL := 890;
-  CONSTANT rup_i3_nq	 : NATURAL := 890;
-  CONSTANT rup_i4_nq	 : NATURAL := 890;
-  CONSTANT rup_i5_nq	 : NATURAL := 890;
-  CONSTANT tphl_i5_nq	 : NATURAL := 496;
-  CONSTANT tphl_i4_nq	 : NATURAL := 574;
-  CONSTANT tphl_i2_nq	 : NATURAL := 620;
-  CONSTANT tphl_i3_nq	 : NATURAL := 716;
-  CONSTANT tplh_i1_nq	 : NATURAL := 778;
-  CONSTANT tplh_i0_nq	 : NATURAL := 814;
-  CONSTANT tplh_i4_nq	 : NATURAL := 819;
-  CONSTANT tplh_i3_nq	 : NATURAL := 833;
-  CONSTANT tphl_i0_nq	 : NATURAL := 834;
-  CONSTANT tplh_i5_nq	 : NATURAL := 865;
-  CONSTANT tplh_i2_nq	 : NATURAL := 873;
-  CONSTANT tphl_i1_nq	 : NATURAL := 955;
-  CONSTANT transistors	 : NATURAL := 18
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  i3	 : in  BIT;
-  i4	 : in  BIT;
-  i5	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END noa2a2a23_x4;
-
-ARCHITECTURE behaviour_data_flow OF noa2a2a23_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on noa2a2a23_x4"
-  SEVERITY WARNING;
-  nq <= not ((((i0 and i1) or (i2 and i3)) or (i4 and i5))) after 1600 ps;
-END;
diff --git a/alliance/share/cells/sxlib/noa2a2a23_x4.vhd b/alliance/share/cells/sxlib/noa2a2a23_x4.vhd
deleted file mode 100644
index c7141298..00000000
--- a/alliance/share/cells/sxlib/noa2a2a23_x4.vhd
+++ /dev/null
@@ -1,24 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY noa2a2a23_x4 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  i3	: IN STD_LOGIC;
-  i4	: IN STD_LOGIC;
-  i5	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END noa2a2a23_x4;
-
-ARCHITECTURE RTL OF noa2a2a23_x4 IS
-BEGIN
-  nq <= NOT((((i0 AND i1) OR (i2 AND i3)) OR (i4 AND i5)));
-END RTL;
diff --git a/alliance/share/cells/sxlib/noa2a2a2a24_x1.al b/alliance/share/cells/sxlib/noa2a2a2a24_x1.al
deleted file mode 100644
index 2221c84b..00000000
--- a/alliance/share/cells/sxlib/noa2a2a2a24_x1.al
+++ /dev/null
@@ -1,66 +0,0 @@
-V ALLIANCE : 6
-H noa2a2a2a24_x1,L,30/10/99
-C i0,IN,EXTERNAL,18
-C i1,IN,EXTERNAL,17
-C i2,IN,EXTERNAL,16
-C i3,IN,EXTERNAL,15
-C i4,IN,EXTERNAL,10
-C i5,IN,EXTERNAL,9
-C i6,IN,EXTERNAL,8
-C i7,IN,EXTERNAL,7
-C nq,OUT,EXTERNAL,3
-C vdd,IN,EXTERNAL,14
-C vss,IN,EXTERNAL,2
-T P,0.35,5.9,13,15,6,0,0.75,0.75,13.3,13.3,10.8,11.25,tr_00016
-T P,0.35,5.9,13,17,14,0,0.75,0.75,13.3,13.3,16.2,11.25,tr_00015
-T P,0.35,5.9,3,7,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00014
-T P,0.35,5.9,14,18,13,0,0.75,0.75,13.3,13.3,18,11.25,tr_00013
-T P,0.35,5.9,6,16,13,0,0.75,0.75,13.3,13.3,12.6,11.25,tr_00012
-T P,0.35,5.9,6,10,5,0,0.75,0.75,13.3,13.3,9,11.25,tr_00011
-T P,0.35,5.9,5,9,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00010
-T P,0.35,5.9,5,8,3,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00009
-T N,0.35,2.9,3,10,1,0,0.75,0.75,7.3,7.3,9,2.25,tr_00008
-T N,0.35,2.9,11,15,3,0,0.75,0.75,7.3,7.3,10.8,2.25,tr_00007
-T N,0.35,2.9,3,8,4,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00006
-T N,0.35,2.9,2,16,11,0,0.75,0.75,7.3,7.3,12.6,2.25,tr_00005
-T N,0.35,2.9,2,18,12,0,0.75,0.75,7.3,7.3,18,2.25,tr_00004
-T N,0.35,2.9,1,9,2,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00003
-T N,0.35,2.9,12,17,3,0,0.75,0.75,7.3,7.3,16.2,2.25,tr_00002
-T N,0.35,2.9,4,7,2,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00001
-S 18,EXTERNAL,i0
-Q 0.00260759
-S 17,EXTERNAL,i1
-Q 0.00260759
-S 16,EXTERNAL,i2
-Q 0.00232574
-S 15,EXTERNAL,i3
-Q 0.00232574
-S 14,EXTERNAL,vdd
-Q 0.00670525
-S 13,INTERNAL
-Q 0.00198726
-S 12,INTERNAL
-Q 0
-S 11,INTERNAL
-Q 0
-S 10,EXTERNAL,i4
-Q 0.00232574
-S 9,EXTERNAL,i5
-Q 0.00232574
-S 8,EXTERNAL,i6
-Q 0.00269068
-S 7,EXTERNAL,i7
-Q 0.00260759
-S 6,INTERNAL
-Q 0.00256527
-S 5,INTERNAL
-Q 0.00324886
-S 4,INTERNAL
-Q 0
-S 3,EXTERNAL,nq
-Q 0.00490604
-S 2,EXTERNAL,vss
-Q 0.00711654
-S 1,INTERNAL
-Q 0
-EOF
diff --git a/alliance/share/cells/sxlib/noa2a2a2a24_x1.ap b/alliance/share/cells/sxlib/noa2a2a2a24_x1.ap
deleted file mode 100644
index eb9e15df..00000000
--- a/alliance/share/cells/sxlib/noa2a2a2a24_x1.ap
+++ /dev/null
@@ -1,157 +0,0 @@
-V ALLIANCE : 6
-H noa2a2a2a24_x1,P, 6/ 9/2000,100
-A 0,0,7000,5000
-R 6000,3500,ref_ref,i0_35
-R 6000,3000,ref_ref,i0_30
-R 6000,2500,ref_ref,i0_25
-R 6000,2000,ref_ref,i0_20
-R 6000,1500,ref_ref,i0_15
-R 5500,3500,ref_ref,i1_35
-R 5500,3000,ref_ref,i1_30
-R 5500,2500,ref_ref,i1_25
-R 5500,2000,ref_ref,i1_20
-R 5500,1500,ref_ref,i1_15
-R 4000,3000,ref_ref,i2_30
-R 4000,2500,ref_ref,i2_25
-R 4000,2000,ref_ref,i2_20
-R 4000,1500,ref_ref,i2_15
-R 3500,3000,ref_ref,i3_30
-R 3500,2500,ref_ref,i3_25
-R 3500,2000,ref_ref,i3_20
-R 3500,1500,ref_ref,i3_15
-R 3000,3000,ref_ref,i4_30
-R 3000,2500,ref_ref,i4_25
-R 3000,2000,ref_ref,i4_20
-R 3000,1500,ref_ref,i4_15
-R 2500,3000,ref_ref,i5_30
-R 2500,2500,ref_ref,i5_25
-R 2500,2000,ref_ref,i5_20
-R 2500,1500,ref_ref,i5_15
-R 1500,3000,ref_ref,i6_30
-R 1500,2500,ref_ref,i6_25
-R 1500,2000,ref_ref,i6_20
-R 1500,1500,ref_ref,i6_15
-R 1000,3500,ref_ref,nq_35
-R 1000,3000,ref_ref,nq_30
-R 1000,2500,ref_ref,nq_25
-R 1000,2000,ref_ref,nq_20
-R 1000,1500,ref_ref,nq_15
-R 1000,1000,ref_ref,nq_10
-R 500,3000,ref_ref,i7_30
-R 500,2500,ref_ref,i7_25
-R 500,2000,ref_ref,i7_20
-R 500,1500,ref_ref,i7_15
-R 500,1000,ref_ref,i7_10
-S 4000,2500,4200,2500,300,*,RIGHT,POLY
-S 300,300,300,1200,300,*,DOWN,NDIF
-S 600,100,600,1400,100,*,UP,NTRANS
-S 5400,100,5400,1400,100,*,UP,NTRANS
-S 3900,300,3900,1200,300,*,DOWN,NDIF
-S 900,300,900,1200,300,*,DOWN,NDIF
-S 2100,300,2100,1200,300,*,DOWN,NDIF
-S 2400,100,2400,1400,100,*,UP,NTRANS
-S 6000,100,6000,1400,100,*,UP,NTRANS
-S 4200,100,4200,1400,100,*,UP,NTRANS
-S 5700,300,5700,1200,300,*,DOWN,NDIF
-S 1500,300,1500,1200,300,*,DOWN,NDIF
-S 1200,100,1200,1400,100,*,UP,NTRANS
-S 3600,100,3600,1400,100,*,UP,NTRANS
-S 4500,300,4500,1200,300,*,DOWN,NDIF
-S 3000,100,3000,1400,100,*,UP,NTRANS
-S 5100,300,5100,1200,300,*,DOWN,NDIF
-S 6300,800,6300,1200,300,*,DOWN,NDIF
-S 3300,300,3300,1200,300,*,DOWN,NDIF
-S 2700,300,2700,1200,300,*,DOWN,NDIF
-S 6000,1400,6000,2600,100,*,DOWN,POLY
-S 4200,1400,4200,2600,100,*,DOWN,POLY
-S 5400,1400,5400,2600,100,*,DOWN,POLY
-S 3600,1400,3600,2600,100,*,DOWN,POLY
-S 600,1400,600,2600,100,*,DOWN,POLY
-S 3000,1400,3000,2600,100,*,DOWN,POLY
-S 2400,1400,2400,2600,100,*,DOWN,POLY
-S 1200,1400,1200,2600,100,*,DOWN,POLY
-S 6300,300,6300,1000,200,*,DOWN,ALU1
-S 0,3900,7000,3900,2400,*,RIGHT,NWELL
-S 0,300,7000,300,600,vss,RIGHT,CALU1
-S 0,4700,7000,4700,600,vdd,RIGHT,CALU1
-S 1500,3500,1500,4000,100,*,DOWN,ALU1
-S 300,4000,1500,4000,100,*,RIGHT,ALU1
-S 2100,4000,4500,4000,100,*,RIGHT,ALU1
-S 1500,3500,2700,3500,100,*,RIGHT,ALU1
-S 1200,2600,1200,4900,100,*,UP,PTRANS
-S 2400,2600,2400,4900,100,*,UP,PTRANS
-S 3000,2600,3000,4900,100,*,UP,PTRANS
-S 3300,2800,3300,4700,300,*,UP,PDIF
-S 2700,2800,2700,4700,300,*,UP,PDIF
-S 3900,2800,3900,4700,300,*,UP,PDIF
-S 4500,2800,4500,4700,300,*,UP,PDIF
-S 4200,2600,4200,4900,100,*,UP,PTRANS
-S 6000,2600,6000,4900,100,*,UP,PTRANS
-S 5700,2800,5700,4700,300,*,UP,PDIF
-S 900,2800,900,4700,300,*,UP,PDIF
-S 1500,2800,1500,4700,300,*,UP,PDIF
-S 600,2600,600,4900,100,*,UP,PTRANS
-S 5100,2800,5100,4700,300,*,UP,PDIF
-S 5400,2600,5400,4900,100,*,UP,PTRANS
-S 2100,2800,2100,4700,300,*,UP,PDIF
-S 3600,2600,3600,4900,100,*,UP,PTRANS
-S 300,2800,300,4700,300,*,UP,PDIF
-S 6300,2800,6300,4200,300,*,UP,PDIF
-S 6300,4000,6300,4600,200,*,DOWN,ALU1
-S 1500,1500,1500,3000,100,*,UP,ALU1
-S 2500,1500,2500,3000,100,*,UP,ALU1
-S 3000,1500,3000,3000,100,*,UP,ALU1
-S 3500,1500,3500,3000,100,*,UP,ALU1
-S 4000,1500,4000,3000,100,*,UP,ALU1
-S 6000,1500,6000,3500,100,*,UP,ALU1
-S 5500,1500,5500,3500,100,*,UP,ALU1
-S 5000,4000,5700,4000,100,*,LEFT,ALU1
-S 5000,3500,5000,4000,100,*,DOWN,ALU1
-S 3900,3500,5000,3500,100,*,LEFT,ALU1
-S 950,1000,5100,1000,200,*,LEFT,ALU1
-S 1000,950,1000,3550,200,*,DOWN,ALU1
-S 500,1000,500,3000,100,*,UP,ALU1
-S 1200,2500,1500,2500,300,*,LEFT,POLY
-S 3300,3500,3300,4000,100,*,UP,ALU1
-S 300,3500,300,4000,100,*,UP,ALU1
-S 6000,1500,6000,3500,200,i0,DOWN,CALU1
-S 5500,1500,5500,3500,200,i1,DOWN,CALU1
-S 4000,1500,4000,3000,200,i2,DOWN,CALU1
-S 3500,1500,3500,3000,200,i3,DOWN,CALU1
-S 3000,1500,3000,3000,200,i4,DOWN,CALU1
-S 2500,1500,2500,3000,200,i5,DOWN,CALU1
-S 1500,1500,1500,3000,200,i6,DOWN,CALU1
-S 1000,1000,1000,3500,200,nq,DOWN,CALU1
-S 500,1000,500,3000,200,i7,DOWN,CALU1
-V 3300,1000,CONT_DIF_N,*
-V 1500,1000,CONT_DIF_N,*
-V 4500,500,CONT_DIF_N,*
-V 2100,500,CONT_DIF_N,*
-V 5100,1000,CONT_DIF_N,*
-V 300,500,CONT_DIF_N,*
-V 900,3500,CONT_DIF_P,*
-V 2700,3500,CONT_DIF_P,*
-V 5700,4000,CONT_DIF_P,*
-V 5100,4500,CONT_DIF_P,*
-V 4500,4000,CONT_DIF_P,*
-V 3300,4000,CONT_DIF_P,*
-V 2100,4000,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 3900,3500,CONT_DIF_P,*
-V 300,4000,CONT_DIF_P,*
-V 6700,4700,CONT_BODY_N,*
-V 6300,4000,CONT_DIF_P,*
-V 6300,1000,CONT_DIF_N,*
-V 6700,300,CONT_BODY_P,*
-V 500,2500,CONT_POLY,*
-V 1500,2500,CONT_POLY,*
-V 2500,2500,CONT_POLY,*
-V 3000,2500,CONT_POLY,*
-V 3500,2500,CONT_POLY,*
-V 4000,2500,CONT_POLY,*
-V 5500,2500,CONT_POLY,*
-V 6000,2500,CONT_POLY,*
-V 3300,3500,CONT_DIF_P,*
-V 300,3500,CONT_DIF_P,*
-V 1500,3500,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/noa2a2a2a24_x1.sym b/alliance/share/cells/sxlib/noa2a2a2a24_x1.sym
deleted file mode 100644
index 85b0df92..00000000
Binary files a/alliance/share/cells/sxlib/noa2a2a2a24_x1.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/noa2a2a2a24_x1.vbe b/alliance/share/cells/sxlib/noa2a2a2a24_x1.vbe
deleted file mode 100644
index ed253ca4..00000000
--- a/alliance/share/cells/sxlib/noa2a2a2a24_x1.vbe
+++ /dev/null
@@ -1,69 +0,0 @@
-ENTITY noa2a2a2a24_x1 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 3500;
-  CONSTANT cin_i0	 : NATURAL := 14;
-  CONSTANT cin_i1	 : NATURAL := 14;
-  CONSTANT cin_i2	 : NATURAL := 13;
-  CONSTANT cin_i3	 : NATURAL := 13;
-  CONSTANT cin_i4	 : NATURAL := 13;
-  CONSTANT cin_i5	 : NATURAL := 13;
-  CONSTANT cin_i6	 : NATURAL := 14;
-  CONSTANT cin_i7	 : NATURAL := 14;
-  CONSTANT rdown_i0_nq	 : NATURAL := 2850;
-  CONSTANT rdown_i1_nq	 : NATURAL := 2850;
-  CONSTANT rdown_i2_nq	 : NATURAL := 2850;
-  CONSTANT rdown_i3_nq	 : NATURAL := 2850;
-  CONSTANT rdown_i4_nq	 : NATURAL := 2850;
-  CONSTANT rdown_i5_nq	 : NATURAL := 2850;
-  CONSTANT rdown_i6_nq	 : NATURAL := 2850;
-  CONSTANT rdown_i7_nq	 : NATURAL := 2850;
-  CONSTANT rup_i0_nq	 : NATURAL := 6190;
-  CONSTANT rup_i1_nq	 : NATURAL := 6190;
-  CONSTANT rup_i2_nq	 : NATURAL := 6190;
-  CONSTANT rup_i3_nq	 : NATURAL := 6190;
-  CONSTANT rup_i4_nq	 : NATURAL := 6190;
-  CONSTANT rup_i5_nq	 : NATURAL := 6190;
-  CONSTANT rup_i6_nq	 : NATURAL := 6190;
-  CONSTANT rup_i7_nq	 : NATURAL := 6190;
-  CONSTANT tphl_i7_nq	 : NATURAL := 200;
-  CONSTANT tphl_i6_nq	 : NATURAL := 270;
-  CONSTANT tphl_i5_nq	 : NATURAL := 329;
-  CONSTANT tphl_i4_nq	 : NATURAL := 419;
-  CONSTANT tplh_i6_nq	 : NATURAL := 535;
-  CONSTANT tphl_i2_nq	 : NATURAL := 550;
-  CONSTANT tplh_i1_nq	 : NATURAL := 562;
-  CONSTANT tplh_i7_nq	 : NATURAL := 591;
-  CONSTANT tplh_i0_nq	 : NATURAL := 606;
-  CONSTANT tplh_i4_nq	 : NATURAL := 613;
-  CONSTANT tplh_i3_nq	 : NATURAL := 616;
-  CONSTANT tphl_i0_nq	 : NATURAL := 649;
-  CONSTANT tplh_i2_nq	 : NATURAL := 662;
-  CONSTANT tplh_i5_nq	 : NATURAL := 662;
-  CONSTANT tphl_i3_nq	 : NATURAL := 667;
-  CONSTANT tphl_i1_nq	 : NATURAL := 775;
-  CONSTANT transistors	 : NATURAL := 16
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  i3	 : in  BIT;
-  i4	 : in  BIT;
-  i5	 : in  BIT;
-  i6	 : in  BIT;
-  i7	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END noa2a2a2a24_x1;
-
-ARCHITECTURE behaviour_data_flow OF noa2a2a2a24_x1 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on noa2a2a2a24_x1"
-  SEVERITY WARNING;
-  nq <= not (((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and
-  i7))) after 1400 ps;
-END;
diff --git a/alliance/share/cells/sxlib/noa2a2a2a24_x1.vhd b/alliance/share/cells/sxlib/noa2a2a2a24_x1.vhd
deleted file mode 100644
index dbac8f6e..00000000
--- a/alliance/share/cells/sxlib/noa2a2a2a24_x1.vhd
+++ /dev/null
@@ -1,26 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY noa2a2a2a24_x1 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  i3	: IN STD_LOGIC;
-  i4	: IN STD_LOGIC;
-  i5	: IN STD_LOGIC;
-  i6	: IN STD_LOGIC;
-  i7	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END noa2a2a2a24_x1;
-
-ARCHITECTURE RTL OF noa2a2a2a24_x1 IS
-BEGIN
-  nq <= NOT(((((i0 AND i1) OR (i2 AND i3)) OR (i4 AND i5)) OR (i6 AND i7)));
-END RTL;
diff --git a/alliance/share/cells/sxlib/noa2a2a2a24_x4.al b/alliance/share/cells/sxlib/noa2a2a2a24_x4.al
deleted file mode 100644
index 63a60e34..00000000
--- a/alliance/share/cells/sxlib/noa2a2a2a24_x4.al
+++ /dev/null
@@ -1,76 +0,0 @@
-V ALLIANCE : 6
-H noa2a2a2a24_x4,L,30/10/99
-C i0,IN,EXTERNAL,20
-C i1,IN,EXTERNAL,15
-C i2,IN,EXTERNAL,16
-C i3,IN,EXTERNAL,17
-C i4,IN,EXTERNAL,7
-C i5,IN,EXTERNAL,8
-C i6,IN,EXTERNAL,9
-C i7,IN,EXTERNAL,10
-C nq,OUT,EXTERNAL,19
-C vdd,IN,EXTERNAL,14
-C vss,IN,EXTERNAL,3
-T P,0.35,2.9,18,2,14,0,0.75,0.75,7.3,7.3,23.7,9.75,tr_00022
-T P,0.35,5.9,13,15,14,0,0.75,0.75,13.3,13.3,16.5,11.25,tr_00021
-T P,0.35,5.9,14,18,19,0,0.75,0.75,13.3,13.3,21.9,11.25,tr_00020
-T P,0.35,5.9,19,18,14,0,0.75,0.75,13.3,13.3,20.1,11.25,tr_00019
-T P,0.35,5.9,14,20,13,0,0.75,0.75,13.3,13.3,18.3,11.25,tr_00018
-T P,0.35,5.9,5,9,2,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00017
-T P,0.35,5.9,5,8,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00016
-T P,0.35,5.9,6,7,5,0,0.75,0.75,13.3,13.3,9,11.25,tr_00015
-T P,0.35,5.9,6,16,13,0,0.75,0.75,13.3,13.3,12.6,11.25,tr_00014
-T P,0.35,5.9,2,10,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00013
-T P,0.35,5.9,13,17,6,0,0.75,0.75,13.3,13.3,10.8,11.25,tr_00012
-T N,0.35,1.4,3,2,18,0,0.75,0.75,4.3,4.3,23.7,3,tr_00011
-T N,0.35,2.9,3,20,12,0,0.75,0.75,7.3,7.3,18.3,2.25,tr_00010
-T N,0.35,2.9,19,18,3,0,0.75,0.75,7.3,7.3,21.9,2.25,tr_00009
-T N,0.35,2.9,12,15,2,0,0.75,0.75,7.3,7.3,17.1,2.25,tr_00008
-T N,0.35,2.9,19,18,3,0,0.75,0.75,7.3,7.3,20.1,2.25,tr_00007
-T N,0.35,2.9,1,10,3,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00006
-T N,0.35,2.9,2,9,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00005
-T N,0.35,2.9,11,17,2,0,0.75,0.75,7.3,7.3,10.8,2.25,tr_00004
-T N,0.35,2.9,2,7,4,0,0.75,0.75,7.3,7.3,9,2.25,tr_00003
-T N,0.35,2.9,3,16,11,0,0.75,0.75,7.3,7.3,12,2.25,tr_00002
-T N,0.35,2.9,4,8,3,0,0.75,0.75,7.3,7.3,7.8,2.25,tr_00001
-S 20,EXTERNAL,i0
-Q 0.00284261
-S 19,EXTERNAL,nq
-Q 0.0023502
-S 18,INTERNAL
-Q 0.00547561
-S 17,EXTERNAL,i3
-Q 0.00232574
-S 16,EXTERNAL,i2
-Q 0.00254552
-S 15,EXTERNAL,i1
-Q 0.00254552
-S 14,EXTERNAL,vdd
-Q 0.00984486
-S 13,INTERNAL
-Q 0.00193089
-S 12,INTERNAL
-Q 0
-S 11,INTERNAL
-Q 0
-S 10,EXTERNAL,i7
-Q 0.00260759
-S 9,EXTERNAL,i6
-Q 0.00269068
-S 8,EXTERNAL,i5
-Q 0.00232574
-S 7,EXTERNAL,i4
-Q 0.00232574
-S 6,INTERNAL
-Q 0.00256527
-S 5,INTERNAL
-Q 0.00324886
-S 4,INTERNAL
-Q 0
-S 3,EXTERNAL,vss
-Q 0.00778843
-S 2,INTERNAL
-Q 0.00816047
-S 1,INTERNAL
-Q 0
-EOF
diff --git a/alliance/share/cells/sxlib/noa2a2a2a24_x4.ap b/alliance/share/cells/sxlib/noa2a2a2a24_x4.ap
deleted file mode 100644
index 54f0b8c1..00000000
--- a/alliance/share/cells/sxlib/noa2a2a2a24_x4.ap
+++ /dev/null
@@ -1,194 +0,0 @@
-V ALLIANCE : 6
-H noa2a2a2a24_x4,P, 6/ 9/2000,100
-A 0,0,8500,5000
-R 6500,3500,ref_ref,i0_35
-R 5500,2000,ref_ref,i1_20
-R 5500,2500,ref_ref,i1_25
-R 5500,3000,ref_ref,i1_30
-R 5500,1500,ref_ref,i1_15
-R 6500,1500,ref_ref,i0_15
-R 6500,2000,ref_ref,i0_20
-R 6500,2500,ref_ref,i0_25
-R 6500,3000,ref_ref,i0_30
-R 7000,4000,ref_ref,nq_40
-R 7000,2000,ref_ref,nq_20
-R 7000,1500,ref_ref,nq_15
-R 7000,3500,ref_ref,nq_35
-R 7000,3000,ref_ref,nq_30
-R 7000,2500,ref_ref,nq_25
-R 500,1000,ref_ref,i7_10
-R 500,1500,ref_ref,i7_15
-R 500,2000,ref_ref,i7_20
-R 500,2500,ref_ref,i7_25
-R 500,3000,ref_ref,i7_30
-R 1500,1500,ref_ref,i6_15
-R 1500,2000,ref_ref,i6_20
-R 1500,2500,ref_ref,i6_25
-R 1500,3000,ref_ref,i6_30
-R 2500,1500,ref_ref,i5_15
-R 2500,2000,ref_ref,i5_20
-R 2500,2500,ref_ref,i5_25
-R 2500,3000,ref_ref,i5_30
-R 3000,1500,ref_ref,i4_15
-R 3000,2000,ref_ref,i4_20
-R 3000,2500,ref_ref,i4_25
-R 3000,3000,ref_ref,i4_30
-R 3500,1500,ref_ref,i3_15
-R 3500,2000,ref_ref,i3_20
-R 3500,2500,ref_ref,i3_25
-R 3500,3000,ref_ref,i3_30
-R 4000,1500,ref_ref,i2_15
-R 4000,2000,ref_ref,i2_20
-R 4000,2500,ref_ref,i2_25
-R 4000,3000,ref_ref,i2_30
-S 7700,1500,7900,1500,300,*,RIGHT,POLY
-S 7300,2000,7500,2000,300,*,LEFT,POLY
-S 7000,300,7000,1500,300,*,DOWN,NDIF
-S 4000,2600,4200,2600,100,*,LEFT,POLY
-S 4000,1400,4000,2600,100,*,DOWN,POLY
-S 2600,1400,2600,2600,100,*,DOWN,POLY
-S 2600,100,2600,1400,100,*,UP,NTRANS
-S 2300,300,2300,1200,300,*,DOWN,NDIF
-S 4000,100,4000,1400,100,*,UP,NTRANS
-S 4300,300,4300,1200,300,*,DOWN,NDIF
-S 1000,1000,1000,3500,100,*,DOWN,ALU1
-S 900,3500,1000,3500,100,*,RIGHT,ALU1
-S 300,3500,300,4000,100,*,UP,ALU1
-S 3300,3500,3300,4000,100,*,UP,ALU1
-S 1200,2500,1500,2500,300,*,LEFT,POLY
-S 500,1000,500,3000,100,*,UP,ALU1
-S 4000,1500,4000,3000,100,*,UP,ALU1
-S 3500,1500,3500,3000,100,*,UP,ALU1
-S 3000,1500,3000,3000,100,*,UP,ALU1
-S 2500,1500,2500,3000,100,*,UP,ALU1
-S 1500,1500,1500,3000,100,*,UP,ALU1
-S 300,2800,300,4700,300,*,UP,PDIF
-S 3600,2600,3600,4900,100,*,UP,PTRANS
-S 2100,2800,2100,4700,300,*,UP,PDIF
-S 600,2600,600,4900,100,*,UP,PTRANS
-S 1500,2800,1500,4700,300,*,UP,PDIF
-S 900,2800,900,4700,300,*,UP,PDIF
-S 4200,2600,4200,4900,100,*,UP,PTRANS
-S 3900,2800,3900,4700,300,*,UP,PDIF
-S 2700,2800,2700,4700,300,*,UP,PDIF
-S 3300,2800,3300,4700,300,*,UP,PDIF
-S 3000,2600,3000,4900,100,*,UP,PTRANS
-S 2400,2600,2400,4900,100,*,UP,PTRANS
-S 1200,2600,1200,4900,100,*,UP,PTRANS
-S 1500,3500,2700,3500,100,*,RIGHT,ALU1
-S 2100,4000,4500,4000,100,*,RIGHT,ALU1
-S 300,4000,1500,4000,100,*,RIGHT,ALU1
-S 1500,3500,1500,4000,100,*,DOWN,ALU1
-S 1200,1400,1200,2600,100,*,DOWN,POLY
-S 3000,1400,3000,2600,100,*,DOWN,POLY
-S 600,1400,600,2600,100,*,DOWN,POLY
-S 3600,1400,3600,2600,100,*,DOWN,POLY
-S 3300,300,3300,1200,300,*,DOWN,NDIF
-S 3000,100,3000,1400,100,*,UP,NTRANS
-S 3600,100,3600,1400,100,*,UP,NTRANS
-S 1200,100,1200,1400,100,*,UP,NTRANS
-S 1500,300,1500,1200,300,*,DOWN,NDIF
-S 900,300,900,1200,300,*,DOWN,NDIF
-S 600,100,600,1400,100,*,UP,NTRANS
-S 300,300,300,1200,300,*,DOWN,NDIF
-S 0,300,8500,300,600,vss,RIGHT,CALU1
-S 0,3900,8500,3900,2400,*,RIGHT,NWELL
-S 0,4700,8500,4700,600,vdd,RIGHT,CALU1
-S 4500,2800,4500,4700,300,*,UP,PDIF
-S 7600,3500,7600,4600,200,*,DOWN,ALU1
-S 5200,4000,5200,4600,200,*,DOWN,ALU1
-S 6400,4000,6400,4600,200,*,DOWN,ALU1
-S 5800,3500,5800,4000,100,*,UP,ALU1
-S 7300,1400,7300,2600,100,*,DOWN,POLY
-S 6700,1400,6700,2600,100,*,DOWN,POLY
-S 6700,100,6700,1400,100,*,UP,NTRANS
-S 5700,100,5700,1400,100,*,UP,NTRANS
-S 5400,300,5400,1200,300,*,DOWN,NDIF
-S 7300,100,7300,1400,100,*,DOWN,NTRANS
-S 6400,300,6400,1200,300,*,DOWN,NDIF
-S 7600,300,7600,1200,300,*,DOWN,NDIF
-S 6100,100,6100,1400,100,*,UP,NTRANS
-S 6100,2600,6100,4900,100,*,UP,PTRANS
-S 5800,2800,5800,4700,300,*,UP,PDIF
-S 7000,2800,7000,4700,300,*,UP,PDIF
-S 7600,2800,7600,4700,300,*,UP,PDIF
-S 6700,2600,6700,4900,100,*,UP,PTRANS
-S 6400,2800,6400,4700,300,*,UP,PDIF
-S 7300,2600,7300,4900,100,*,UP,PTRANS
-S 5500,2600,5500,4900,100,*,UP,PTRANS
-S 5200,2800,5200,4700,300,*,UP,PDIF
-S 6500,1500,6500,3500,100,*,UP,ALU1
-S 5500,1500,5500,3000,100,*,UP,ALU1
-S 1000,1000,5400,1000,100,*,RIGHT,ALU1
-S 7900,600,7900,1400,100,*,DOWN,NTRANS
-S 7900,2600,7900,3900,100,*,UP,PTRANS
-S 8200,800,8200,1200,300,*,UP,NDIF
-S 8200,2800,8200,3700,300,*,UP,PDIF
-S 8200,1000,8200,3500,100,*,UP,ALU1
-S 7000,1450,7000,4050,200,*,DOWN,ALU1
-S 7900,1400,7900,2600,100,*,UP,POLY
-S 5400,1000,7700,1000,100,*,RIGHT,ALU1
-S 7700,1000,7700,1500,100,*,UP,ALU1
-S 3900,3500,5800,3500,100,*,RIGHT,ALU1
-S 7500,2000,8200,2000,100,*,RIGHT,ALU1
-S 6200,2000,6400,2000,200,*,RIGHT,ALU1
-S 6700,2000,7500,2000,100,*,LEFT,POLY
-S 5500,1400,5700,1400,100,*,LEFT,POLY
-S 5500,1400,5500,2600,100,*,UP,POLY
-S 6100,1400,6100,2600,100,*,DOWN,POLY
-S 6500,1500,6500,3500,200,i0,DOWN,CALU1
-S 5500,1500,5500,3000,200,i1,DOWN,CALU1
-S 7000,1500,7000,4000,200,nq,DOWN,CALU1
-S 500,1000,500,3000,200,i7,DOWN,CALU1
-S 1500,1500,1500,3000,200,i6,DOWN,CALU1
-S 2500,1500,2500,3000,200,i5,DOWN,CALU1
-S 3000,1500,3000,3000,200,i4,DOWN,CALU1
-S 3500,1500,3500,3000,200,i3,DOWN,CALU1
-S 4000,1500,4000,3000,200,i2,DOWN,CALU1
-V 7000,1500,CONT_DIF_N,*
-V 2300,500,CONT_DIF_N,*
-V 4300,500,CONT_DIF_N,*
-V 3900,3500,CONT_DIF_P,*
-V 1500,3500,CONT_DIF_P,*
-V 300,3500,CONT_DIF_P,*
-V 3300,3500,CONT_DIF_P,*
-V 4000,2500,CONT_POLY,*
-V 3500,2500,CONT_POLY,*
-V 3000,2500,CONT_POLY,*
-V 2500,2500,CONT_POLY,*
-V 1500,2500,CONT_POLY,*
-V 500,2500,CONT_POLY,*
-V 300,4000,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 2100,4000,CONT_DIF_P,*
-V 3300,4000,CONT_DIF_P,*
-V 4500,4000,CONT_DIF_P,*
-V 2700,3500,CONT_DIF_P,*
-V 900,3500,CONT_DIF_P,*
-V 300,500,CONT_DIF_N,*
-V 1500,1000,CONT_DIF_N,*
-V 3300,1000,CONT_DIF_N,*
-V 8200,4600,CONT_BODY_N,*
-V 5400,1000,CONT_DIF_N,*
-V 6400,500,CONT_DIF_N,*
-V 7600,500,CONT_DIF_N,*
-V 7000,3500,CONT_DIF_P,*
-V 6400,4500,CONT_DIF_P,*
-V 7000,4000,CONT_DIF_P,*
-V 6400,4000,CONT_DIF_P,*
-V 7600,3500,CONT_DIF_P,*
-V 7600,4500,CONT_DIF_P,*
-V 5200,4000,CONT_DIF_P,*
-V 5800,4000,CONT_DIF_P,*
-V 7600,4000,CONT_DIF_P,*
-V 7000,3000,CONT_DIF_P,*
-V 5200,4500,CONT_DIF_P,*
-V 8200,300,CONT_BODY_P,*
-V 8200,2900,CONT_DIF_P,*
-V 8200,3500,CONT_DIF_P,*
-V 8200,1000,CONT_DIF_N,*
-V 7700,1500,CONT_POLY,*
-V 7500,2000,CONT_POLY,*
-V 6200,2000,CONT_POLY,*
-V 5500,2000,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/sxlib/noa2a2a2a24_x4.sym b/alliance/share/cells/sxlib/noa2a2a2a24_x4.sym
deleted file mode 100644
index 7df574ee..00000000
Binary files a/alliance/share/cells/sxlib/noa2a2a2a24_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/noa2a2a2a24_x4.vbe b/alliance/share/cells/sxlib/noa2a2a2a24_x4.vbe
deleted file mode 100644
index 2499cd71..00000000
--- a/alliance/share/cells/sxlib/noa2a2a2a24_x4.vbe
+++ /dev/null
@@ -1,69 +0,0 @@
-ENTITY noa2a2a2a24_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 4250;
-  CONSTANT cin_i0	 : NATURAL := 14;
-  CONSTANT cin_i1	 : NATURAL := 14;
-  CONSTANT cin_i2	 : NATURAL := 14;
-  CONSTANT cin_i3	 : NATURAL := 13;
-  CONSTANT cin_i4	 : NATURAL := 13;
-  CONSTANT cin_i5	 : NATURAL := 13;
-  CONSTANT cin_i6	 : NATURAL := 14;
-  CONSTANT cin_i7	 : NATURAL := 14;
-  CONSTANT rdown_i0_nq	 : NATURAL := 810;
-  CONSTANT rdown_i1_nq	 : NATURAL := 810;
-  CONSTANT rdown_i2_nq	 : NATURAL := 810;
-  CONSTANT rdown_i3_nq	 : NATURAL := 810;
-  CONSTANT rdown_i4_nq	 : NATURAL := 810;
-  CONSTANT rdown_i5_nq	 : NATURAL := 810;
-  CONSTANT rdown_i6_nq	 : NATURAL := 810;
-  CONSTANT rdown_i7_nq	 : NATURAL := 810;
-  CONSTANT rup_i0_nq	 : NATURAL := 890;
-  CONSTANT rup_i1_nq	 : NATURAL := 890;
-  CONSTANT rup_i2_nq	 : NATURAL := 890;
-  CONSTANT rup_i3_nq	 : NATURAL := 890;
-  CONSTANT rup_i4_nq	 : NATURAL := 890;
-  CONSTANT rup_i5_nq	 : NATURAL := 890;
-  CONSTANT rup_i6_nq	 : NATURAL := 890;
-  CONSTANT rup_i7_nq	 : NATURAL := 890;
-  CONSTANT tphl_i7_nq	 : NATURAL := 525;
-  CONSTANT tphl_i6_nq	 : NATURAL := 606;
-  CONSTANT tphl_i5_nq	 : NATURAL := 649;
-  CONSTANT tphl_i4_nq	 : NATURAL := 748;
-  CONSTANT tphl_i2_nq	 : NATURAL := 867;
-  CONSTANT tphl_i0_nq	 : NATURAL := 966;
-  CONSTANT tphl_i3_nq	 : NATURAL := 990;
-  CONSTANT tplh_i6_nq	 : NATURAL := 999;
-  CONSTANT tplh_i1_nq	 : NATURAL := 1005;
-  CONSTANT tplh_i0_nq	 : NATURAL := 1049;
-  CONSTANT tplh_i7_nq	 : NATURAL := 1052;
-  CONSTANT tplh_i3_nq	 : NATURAL := 1061;
-  CONSTANT tplh_i4_nq	 : NATURAL := 1061;
-  CONSTANT tphl_i1_nq	 : NATURAL := 1097;
-  CONSTANT tplh_i2_nq	 : NATURAL := 1106;
-  CONSTANT tplh_i5_nq	 : NATURAL := 1109;
-  CONSTANT transistors	 : NATURAL := 22
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  i3	 : in  BIT;
-  i4	 : in  BIT;
-  i5	 : in  BIT;
-  i6	 : in  BIT;
-  i7	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END noa2a2a2a24_x4;
-
-ARCHITECTURE behaviour_data_flow OF noa2a2a2a24_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on noa2a2a2a24_x4"
-  SEVERITY WARNING;
-  nq <= not (((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and
-  i7))) after 1700 ps;
-END;
diff --git a/alliance/share/cells/sxlib/noa2a2a2a24_x4.vhd b/alliance/share/cells/sxlib/noa2a2a2a24_x4.vhd
deleted file mode 100644
index e349c824..00000000
--- a/alliance/share/cells/sxlib/noa2a2a2a24_x4.vhd
+++ /dev/null
@@ -1,26 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY noa2a2a2a24_x4 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  i3	: IN STD_LOGIC;
-  i4	: IN STD_LOGIC;
-  i5	: IN STD_LOGIC;
-  i6	: IN STD_LOGIC;
-  i7	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END noa2a2a2a24_x4;
-
-ARCHITECTURE RTL OF noa2a2a2a24_x4 IS
-BEGIN
-  nq <= NOT(((((i0 AND i1) OR (i2 AND i3)) OR (i4 AND i5)) OR (i6 AND i7)));
-END RTL;
diff --git a/alliance/share/cells/sxlib/noa2ao222_x1.al b/alliance/share/cells/sxlib/noa2ao222_x1.al
deleted file mode 100644
index a39f8b03..00000000
--- a/alliance/share/cells/sxlib/noa2ao222_x1.al
+++ /dev/null
@@ -1,45 +0,0 @@
-V ALLIANCE : 6
-H noa2ao222_x1,L,30/10/99
-C i0,IN,EXTERNAL,12
-C i1,IN,EXTERNAL,11
-C i2,IN,EXTERNAL,9
-C i3,IN,EXTERNAL,8
-C i4,IN,EXTERNAL,10
-C nq,OUT,EXTERNAL,2
-C vdd,IN,EXTERNAL,7
-C vss,IN,EXTERNAL,1
-T P,0.35,5.9,2,10,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00010
-T P,0.35,5.9,5,9,2,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00009
-T P,0.35,4.25,7,12,6,0,0.75,0.75,10,10,1.8,10.42,tr_00008
-T P,0.35,4.25,6,11,7,0,0.75,0.75,10,10,3.6,10.42,tr_00007
-T P,0.35,5.9,6,8,5,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00006
-T N,0.35,2.6,3,8,1,0,0.75,0.75,6.7,6.7,8.7,3.9,tr_00005
-T N,0.35,2.6,4,12,1,0,0.75,0.75,6.7,6.7,1.8,3.9,tr_00004
-T N,0.35,2.6,1,9,3,0,0.75,0.75,6.7,6.7,6.9,3.9,tr_00003
-T N,0.35,2.6,3,10,2,0,0.75,0.75,6.7,6.7,5.1,3.9,tr_00002
-T N,0.35,2.6,2,11,4,0,0.75,0.75,6.7,6.7,3.3,3.9,tr_00001
-S 12,EXTERNAL,i0
-Q 0.00254241
-S 11,EXTERNAL,i1
-Q 0.00241094
-S 10,EXTERNAL,i4
-Q 0.00212909
-S 9,EXTERNAL
-Q 0.00212909
-S 8,EXTERNAL
-Q 0.00226057
-S 7,EXTERNAL,vdd
-Q 0.00366862
-S 6,INTERNAL
-Q 0.00227626
-S 5,INTERNAL
-Q 0
-S 4,INTERNAL
-Q 0
-S 3,INTERNAL
-Q 0.00114171
-S 2,EXTERNAL,nq
-Q 0.0026146
-S 1,EXTERNAL,vss
-Q 0.00419742
-EOF
diff --git a/alliance/share/cells/sxlib/noa2ao222_x1.ap b/alliance/share/cells/sxlib/noa2ao222_x1.ap
deleted file mode 100644
index ba84f0ff..00000000
--- a/alliance/share/cells/sxlib/noa2ao222_x1.ap
+++ /dev/null
@@ -1,104 +0,0 @@
-V ALLIANCE : 6
-H noa2ao222_x1,P, 6/ 9/2000,100
-A 0,0,3500,5000
-R 3000,3500,ref_ref,i3_35
-R 3000,3000,ref_ref,i3_30
-R 3000,2500,ref_ref,i3_25
-R 3000,2000,ref_ref,i3_20
-R 3000,1500,ref_ref,i3_15
-R 2500,3000,ref_ref,i2_30
-R 2500,2500,ref_ref,i2_25
-R 2500,2000,ref_ref,i2_20
-R 2500,1500,ref_ref,i2_15
-R 1500,1000,ref_ref,nq_10
-R 2000,1500,ref_ref,nq_15
-R 2000,2000,ref_ref,nq_20
-R 2000,2500,ref_ref,nq_25
-R 2000,3000,ref_ref,nq_30
-R 2000,3500,ref_ref,nq_35
-R 1500,2000,ref_ref,i4_20
-R 1500,2500,ref_ref,i4_25
-R 1500,3000,ref_ref,i4_30
-R 1500,3500,ref_ref,i4_35
-R 1000,1500,ref_ref,i1_15
-R 1000,2000,ref_ref,i1_20
-R 1000,2500,ref_ref,i1_25
-R 1000,3000,ref_ref,i1_30
-R 1000,3500,ref_ref,i1_35
-R 500,3500,ref_ref,i0_35
-R 500,3000,ref_ref,i0_30
-R 500,2500,ref_ref,i0_25
-R 500,2000,ref_ref,i0_20
-R 500,1500,ref_ref,i0_15
-R 500,1000,ref_ref,i0_10
-S 1500,2000,1700,2000,300,*,RIGHT,POLY
-S 1500,1000,1500,1500,200,nq,DOWN,CALU1
-S 2000,1500,2000,3500,200,nq,DOWN,CALU1
-S 3000,1500,3000,3500,200,i3,DOWN,CALU1
-S 2500,1500,2500,3000,200,i2,DOWN,CALU1
-S 1500,2000,1500,3500,200,i4,DOWN,CALU1
-S 1000,1500,1000,3500,200,i1,DOWN,CALU1
-S 500,1000,500,3500,200,i0,DOWN,CALU1
-S 2000,1450,2000,3550,200,*,UP,ALU1
-S 2500,1500,2500,3000,100,*,UP,ALU1
-S 0,4700,3500,4700,600,vdd,RIGHT,CALU1
-S 0,300,3500,300,600,vss,RIGHT,CALU1
-S 2000,1000,3200,1000,100,*,RIGHT,ALU1
-S 600,1900,600,2600,100,i0,UP,POLY
-S 1800,2600,1800,4900,100,*,UP,PTRANS
-S 2100,2800,2100,4700,200,*,UP,PDIF
-S 2400,2600,2400,4900,100,*,UP,PTRANS
-S 2700,2800,2700,4700,200,*,UP,PDIF
-S 300,2800,300,4150,300,*,UP,PDIF
-S 1500,2800,1500,4150,200,*,UP,PDIF
-S 600,2600,600,4350,100,*,UP,PTRANS
-S 1200,2600,1200,4350,100,*,UP,PTRANS
-S 900,2800,900,4450,300,*,UP,PDIF
-S 0,3900,3500,3900,2400,*,RIGHT,NWELL
-S 2900,2600,2900,4900,100,*,UP,PTRANS
-S 1100,2600,1200,2600,100,*,RIGHT,POLY
-S 1700,2600,1800,2600,100,*,RIGHT,POLY
-S 1000,1500,1000,3500,100,*,UP,ALU1
-S 1450,1500,2050,1500,200,*,RIGHT,ALU1
-S 1500,2000,1500,3500,100,*,UP,ALU1
-S 3000,1500,3000,3500,100,*,UP,ALU1
-S 300,4000,3200,4000,100,*,RIGHT,ALU1
-S 2300,1900,2400,1900,100,*,RIGHT,POLY
-S 2900,1900,2900,2600,100,i4,UP,POLY
-S 2400,1900,2400,2600,100,i3,UP,POLY
-S 1700,1900,1700,2600,100,i2,UP,POLY
-S 1100,1900,1100,2600,100,i1,UP,POLY
-S 2600,500,2600,1700,300,*,UP,NDIF
-S 3200,2800,3200,4700,300,*,UP,PDIF
-S 300,500,300,1700,300,*,UP,NDIF
-S 500,1000,500,3500,100,*,DOWN,ALU1
-S 1500,950,1500,1500,200,*,UP,ALU1
-S 1400,900,1400,1700,200,*,UP,NDIF
-S 2900,700,2900,1900,100,*,UP,NTRANS
-S 3200,900,3200,1700,300,*,UP,NDIF
-S 600,700,600,1900,100,*,UP,NTRANS
-S 2300,700,2300,1900,100,*,UP,NTRANS
-S 1700,700,1700,1900,100,*,UP,NTRANS
-S 2000,900,2000,1700,200,*,UP,NDIF
-S 1100,700,1100,1900,100,*,UP,NTRANS
-S 1200,400,2000,400,300,*,RIGHT,PTIE
-V 2100,3500,CONT_DIF_P,*
-V 2600,500,CONT_DIF_N,*
-V 3200,1000,CONT_DIF_N,*
-V 2000,1000,CONT_DIF_N,*
-V 1400,1000,CONT_DIF_N,*
-V 900,4500,CONT_DIF_P,*
-V 300,4700,CONT_BODY_N,*
-V 1500,4000,CONT_DIF_P,*
-V 300,4000,CONT_DIF_P,*
-V 3200,4000,CONT_DIF_P,*
-V 500,2000,CONT_POLY,*
-V 1000,2000,CONT_POLY,*
-V 1500,2000,CONT_POLY,*
-V 3000,2000,CONT_POLY,*
-V 2500,2000,CONT_POLY,*
-V 300,500,CONT_DIF_N,*
-V 2000,400,CONT_BODY_P,*
-V 1600,400,CONT_BODY_P,*
-V 1200,400,CONT_BODY_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/noa2ao222_x1.vbe b/alliance/share/cells/sxlib/noa2ao222_x1.vbe
deleted file mode 100644
index 034393fe..00000000
--- a/alliance/share/cells/sxlib/noa2ao222_x1.vbe
+++ /dev/null
@@ -1,50 +0,0 @@
-ENTITY noa2ao222_x1 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 1750;
-  CONSTANT cin_i0	 : NATURAL := 11;
-  CONSTANT cin_i1	 : NATURAL := 11;
-  CONSTANT cin_i2	 : NATURAL := 13;
-  CONSTANT cin_i3	 : NATURAL := 13;
-  CONSTANT cin_i4	 : NATURAL := 13;
-  CONSTANT rdown_i0_nq	 : NATURAL := 3210;
-  CONSTANT rdown_i1_nq	 : NATURAL := 3210;
-  CONSTANT rdown_i2_nq	 : NATURAL := 3210;
-  CONSTANT rdown_i3_nq	 : NATURAL := 3210;
-  CONSTANT rdown_i4_nq	 : NATURAL := 3210;
-  CONSTANT rup_i0_nq	 : NATURAL := 5260;
-  CONSTANT rup_i1_nq	 : NATURAL := 5260;
-  CONSTANT rup_i2_nq	 : NATURAL := 5260;
-  CONSTANT rup_i3_nq	 : NATURAL := 5260;
-  CONSTANT rup_i4_nq	 : NATURAL := 3750;
-  CONSTANT tphl_i2_nq	 : NATURAL := 186;
-  CONSTANT tphl_i4_nq	 : NATURAL := 240;
-  CONSTANT tphl_i3_nq	 : NATURAL := 256;
-  CONSTANT tplh_i4_nq	 : NATURAL := 309;
-  CONSTANT tphl_i0_nq	 : NATURAL := 348;
-  CONSTANT tplh_i1_nq	 : NATURAL := 378;
-  CONSTANT tplh_i0_nq	 : NATURAL := 422;
-  CONSTANT tphl_i1_nq	 : NATURAL := 440;
-  CONSTANT tplh_i3_nq	 : NATURAL := 459;
-  CONSTANT tplh_i2_nq	 : NATURAL := 473;
-  CONSTANT transistors	 : NATURAL := 10
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  i3	 : in  BIT;
-  i4	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END noa2ao222_x1;
-
-ARCHITECTURE behaviour_data_flow OF noa2ao222_x1 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on noa2ao222_x1"
-  SEVERITY WARNING;
-  nq <= not (((i0 and i1) or ((i2 or i3) and i4))) after 1100 ps;
-END;
diff --git a/alliance/share/cells/sxlib/noa2ao222_x1.vhd b/alliance/share/cells/sxlib/noa2ao222_x1.vhd
deleted file mode 100644
index 065e8073..00000000
--- a/alliance/share/cells/sxlib/noa2ao222_x1.vhd
+++ /dev/null
@@ -1,23 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY noa2ao222_x1 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  i3	: IN STD_LOGIC;
-  i4	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END noa2ao222_x1;
-
-ARCHITECTURE RTL OF noa2ao222_x1 IS
-BEGIN
-  nq <= NOT(((i0 AND i1) OR ((i2 OR i3) AND i4)));
-END RTL;
diff --git a/alliance/share/cells/sxlib/noa2ao222_x2.sym b/alliance/share/cells/sxlib/noa2ao222_x2.sym
deleted file mode 100644
index 0f226fcc..00000000
Binary files a/alliance/share/cells/sxlib/noa2ao222_x2.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/noa2ao222_x4.al b/alliance/share/cells/sxlib/noa2ao222_x4.al
deleted file mode 100644
index 3af0440f..00000000
--- a/alliance/share/cells/sxlib/noa2ao222_x4.al
+++ /dev/null
@@ -1,55 +0,0 @@
-V ALLIANCE : 6
-H noa2ao222_x4,L,30/10/99
-C i0,IN,EXTERNAL,12
-C i1,IN,EXTERNAL,11
-C i2,IN,EXTERNAL,9
-C i3,IN,EXTERNAL,8
-C i4,IN,EXTERNAL,10
-C nq,OUT,EXTERNAL,14
-C vdd,IN,EXTERNAL,7
-C vss,IN,EXTERNAL,2
-T P,0.35,5.9,1,10,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00016
-T P,0.35,5.9,5,9,1,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00015
-T P,0.35,4.25,7,12,6,0,0.75,0.75,10,10,1.8,10.42,tr_00014
-T P,0.35,4.25,6,11,7,0,0.75,0.75,10,10,3.6,10.42,tr_00013
-T P,0.35,5.9,6,8,5,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00012
-T P,0.35,5.9,14,13,7,0,0.75,0.75,13.3,13.3,14.1,11.25,tr_00011
-T P,0.35,2.9,7,1,13,0,0.75,0.75,7.3,7.3,12.3,9.75,tr_00010
-T P,0.35,5.9,7,13,14,0,0.75,0.75,13.3,13.3,15.9,11.25,tr_00009
-T N,0.35,1.7,3,10,1,0,0.75,0.75,4.9,4.9,5.1,4.35,tr_00008
-T N,0.35,2.6,4,12,2,0,0.75,0.75,6.7,6.7,1.8,3.9,tr_00007
-T N,0.35,2.6,1,11,4,0,0.75,0.75,6.7,6.7,3.3,3.9,tr_00006
-T N,0.35,1.7,3,8,2,0,0.75,0.75,4.9,4.9,8.7,4.35,tr_00005
-T N,0.35,1.7,2,9,3,0,0.75,0.75,4.9,4.9,6.9,4.35,tr_00004
-T N,0.35,1.4,13,1,2,0,0.75,0.75,4.3,4.3,12.3,4.5,tr_00003
-T N,0.35,2.9,14,13,2,0,0.75,0.75,7.3,7.3,15.9,3.75,tr_00002
-T N,0.35,2.9,2,13,14,0,0.75,0.75,7.3,7.3,14.1,3.75,tr_00001
-S 14,EXTERNAL,nq
-Q 0.00276148
-S 13,INTERNAL
-Q 0.00420824
-S 12,EXTERNAL,i0
-Q 0.00254241
-S 11,EXTERNAL,i1
-Q 0.00241094
-S 10,EXTERNAL,i4
-Q 0.00212909
-S 9,EXTERNAL
-Q 0.00212909
-S 8,EXTERNAL
-Q 0.00197871
-S 7,EXTERNAL,vdd
-Q 0.00825499
-S 6,INTERNAL
-Q 0.00227626
-S 5,INTERNAL
-Q 0
-S 4,INTERNAL
-Q 0
-S 3,INTERNAL
-Q 0.00114171
-S 2,EXTERNAL,vss
-Q 0.00913632
-S 1,INTERNAL
-Q 0.00576981
-EOF
diff --git a/alliance/share/cells/sxlib/noa2ao222_x4.ap b/alliance/share/cells/sxlib/noa2ao222_x4.ap
deleted file mode 100644
index 7b30dfec..00000000
--- a/alliance/share/cells/sxlib/noa2ao222_x4.ap
+++ /dev/null
@@ -1,158 +0,0 @@
-V ALLIANCE : 6
-H noa2ao222_x4,P, 6/ 9/2000,100
-A 0,0,6000,5000
-R 5000,4000,ref_ref,nq_40
-R 5000,2000,ref_ref,nq_20
-R 5000,2500,ref_ref,nq_25
-R 5000,3000,ref_ref,nq_30
-R 5000,1000,ref_ref,nq_10
-R 5000,3500,ref_ref,nq_35
-R 5000,1500,ref_ref,nq_15
-R 500,1000,ref_ref,i0_10
-R 500,1500,ref_ref,i0_15
-R 500,2000,ref_ref,i0_20
-R 500,2500,ref_ref,i0_25
-R 500,3000,ref_ref,i0_30
-R 500,3500,ref_ref,i0_35
-R 1000,3500,ref_ref,i1_35
-R 1000,3000,ref_ref,i1_30
-R 1000,2500,ref_ref,i1_25
-R 1000,2000,ref_ref,i1_20
-R 1000,1500,ref_ref,i1_15
-R 1500,3500,ref_ref,i4_35
-R 1500,3000,ref_ref,i4_30
-R 1500,2500,ref_ref,i4_25
-R 1500,2000,ref_ref,i4_20
-R 2500,1500,ref_ref,i2_15
-R 2500,2000,ref_ref,i2_20
-R 2500,2500,ref_ref,i2_25
-R 2500,3000,ref_ref,i2_30
-R 3000,1500,ref_ref,i3_15
-R 3000,2000,ref_ref,i3_20
-R 3000,2500,ref_ref,i3_25
-R 3000,3000,ref_ref,i3_30
-S 4100,2500,4300,2500,300,*,LEFT,POLY
-S 1500,2000,1700,2000,300,*,RIGHT,POLY
-S 2100,3500,4300,3500,100,*,LEFT,ALU1
-S 5300,2600,5300,4900,100,*,UP,PTRANS
-S 4100,2600,4100,3900,100,*,UP,PTRANS
-S 3800,2800,3800,3700,300,*,UP,PDIF
-S 5000,2800,5000,4700,300,*,DOWN,PDIF
-S 4700,2600,4700,4900,100,*,UP,PTRANS
-S 4400,2800,4400,4700,300,*,DOWN,PDIF
-S 5600,2800,5600,4700,300,*,DOWN,PDIF
-S 3800,1300,3800,1700,300,*,UP,NDIF
-S 4700,600,4700,1900,100,*,DOWN,NTRANS
-S 5000,800,5000,1700,300,*,UP,NDIF
-S 4400,800,4400,1700,300,*,UP,NDIF
-S 5300,600,5300,1900,100,*,DOWN,NTRANS
-S 5600,800,5600,1700,300,*,UP,NDIF
-S 4100,1100,4100,1900,100,*,DOWN,NTRANS
-S 4100,1900,4100,2600,100,*,DOWN,POLY
-S 4500,2000,5300,2000,300,*,RIGHT,POLY
-S 4700,1900,4700,2600,100,*,UP,POLY
-S 5300,1900,5300,2600,100,*,UP,POLY
-S 4400,300,4400,1500,200,*,DOWN,ALU1
-S 4400,4000,4400,4700,200,*,UP,ALU1
-S 5600,3000,5600,4700,200,*,UP,ALU1
-S 3800,1500,3800,3000,100,*,UP,ALU1
-S 3800,2000,4500,2000,100,*,LEFT,ALU1
-S 4300,2500,4300,3500,100,*,UP,ALU1
-S 5600,300,5600,1500,200,*,DOWN,ALU1
-S 5000,1000,5000,4000,200,*,DOWN,ALU1
-S 3000,1500,3000,3000,100,*,UP,ALU1
-S 2000,3500,2100,3500,100,*,RIGHT,ALU1
-S 2000,1500,2000,3500,100,*,UP,ALU1
-S 1500,1500,2000,1500,100,*,RIGHT,ALU1
-S 1500,1000,1500,1500,100,*,UP,ALU1
-S 1400,1000,1500,1000,100,*,RIGHT,ALU1
-S 1200,400,2000,400,300,*,RIGHT,PTIE
-S 2000,900,2000,1700,200,*,UP,NDIF
-S 3200,900,3200,1700,300,*,UP,NDIF
-S 1400,900,1400,1700,200,*,UP,NDIF
-S 500,1000,500,3500,100,*,DOWN,ALU1
-S 300,500,300,1700,300,*,UP,NDIF
-S 3200,2800,3200,4700,300,*,UP,PDIF
-S 2600,500,2600,1700,300,*,UP,NDIF
-S 1100,1900,1100,2600,100,i1,UP,POLY
-S 1700,1900,1700,2600,100,i2,UP,POLY
-S 2400,1900,2400,2600,100,i3,UP,POLY
-S 2900,1900,2900,2600,100,i4,UP,POLY
-S 2300,1900,2400,1900,100,*,RIGHT,POLY
-S 300,4000,3200,4000,100,*,RIGHT,ALU1
-S 1500,2000,1500,3500,100,*,UP,ALU1
-S 1000,1500,1000,3500,100,*,UP,ALU1
-S 1700,2600,1800,2600,100,*,RIGHT,POLY
-S 1100,2600,1200,2600,100,*,RIGHT,POLY
-S 2900,2600,2900,4900,100,*,UP,PTRANS
-S 900,2800,900,4450,300,*,UP,PDIF
-S 1200,2600,1200,4350,100,*,UP,PTRANS
-S 600,2600,600,4350,100,*,UP,PTRANS
-S 1500,2800,1500,4150,200,*,UP,PDIF
-S 300,2800,300,4150,300,*,UP,PDIF
-S 2700,2800,2700,4700,200,*,UP,PDIF
-S 2400,2600,2400,4900,100,*,UP,PTRANS
-S 2100,2800,2100,4700,200,*,UP,PDIF
-S 1800,2600,1800,4900,100,*,UP,PTRANS
-S 600,1900,600,2600,100,i0,UP,POLY
-S 2000,1000,3200,1000,100,*,RIGHT,ALU1
-S 2500,1500,2500,3000,100,*,UP,ALU1
-S 2300,1000,2300,1900,100,*,UP,NTRANS
-S 2900,1000,2900,1900,100,*,UP,NTRANS
-S 1100,700,1100,1900,100,*,UP,NTRANS
-S 600,700,600,1900,100,*,UP,NTRANS
-S 1700,1000,1700,1900,100,*,UP,NTRANS
-S 0,3900,6000,3900,2400,*,RIGHT,NWELL
-S 0,4700,6000,4700,600,vdd,RIGHT,CALU1
-S 0,300,6000,300,600,vss,RIGHT,CALU1
-S 5000,1000,5000,4000,200,nq,DOWN,CALU1
-S 500,1000,500,3500,200,i0,DOWN,CALU1
-S 1000,1500,1000,3500,200,i1,DOWN,CALU1
-S 1500,2000,1500,3500,200,i4,DOWN,CALU1
-S 2500,1500,2500,3000,200,i2,DOWN,CALU1
-S 3000,1500,3000,3000,200,i3,DOWN,CALU1
-V 5000,3000,CONT_DIF_P,*
-V 4400,4000,CONT_DIF_P,*
-V 3800,3000,CONT_DIF_P,*
-V 3800,4600,CONT_BODY_N,*
-V 5600,3000,CONT_DIF_P,*
-V 5000,3500,CONT_DIF_P,*
-V 4400,4500,CONT_DIF_P,*
-V 5000,4000,CONT_DIF_P,*
-V 5600,3500,CONT_DIF_P,*
-V 5600,4000,CONT_DIF_P,*
-V 5600,4500,CONT_DIF_P,*
-V 5000,1500,CONT_DIF_N,*
-V 4400,1000,CONT_DIF_N,*
-V 5600,1000,CONT_DIF_N,*
-V 5600,1500,CONT_DIF_N,*
-V 3800,1500,CONT_DIF_N,*
-V 4400,1500,CONT_DIF_N,*
-V 5000,1000,CONT_DIF_N,*
-V 3800,300,CONT_BODY_P,*
-V 5600,300,CONT_BODY_P,*
-V 4400,300,CONT_BODY_P,*
-V 5000,300,CONT_BODY_P,*
-V 4500,2000,CONT_POLY,*
-V 4300,2500,CONT_POLY,*
-V 1200,400,CONT_BODY_P,*
-V 1600,400,CONT_BODY_P,*
-V 2000,400,CONT_BODY_P,*
-V 300,500,CONT_DIF_N,*
-V 2500,2000,CONT_POLY,*
-V 3000,2000,CONT_POLY,*
-V 1500,2000,CONT_POLY,*
-V 1000,2000,CONT_POLY,*
-V 500,2000,CONT_POLY,*
-V 3200,4000,CONT_DIF_P,*
-V 300,4000,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 300,4700,CONT_BODY_N,*
-V 900,4500,CONT_DIF_P,*
-V 1400,1000,CONT_DIF_N,*
-V 2000,1000,CONT_DIF_N,*
-V 3200,1000,CONT_DIF_N,*
-V 2600,500,CONT_DIF_N,*
-V 2100,3500,CONT_DIF_P,*
-V 3200,300,CONT_BODY_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/noa2ao222_x4.sym b/alliance/share/cells/sxlib/noa2ao222_x4.sym
deleted file mode 100644
index 7315791a..00000000
Binary files a/alliance/share/cells/sxlib/noa2ao222_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/noa2ao222_x4.vbe b/alliance/share/cells/sxlib/noa2ao222_x4.vbe
deleted file mode 100644
index 89b9f12c..00000000
--- a/alliance/share/cells/sxlib/noa2ao222_x4.vbe
+++ /dev/null
@@ -1,50 +0,0 @@
-ENTITY noa2ao222_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 3000;
-  CONSTANT cin_i0	 : NATURAL := 11;
-  CONSTANT cin_i1	 : NATURAL := 11;
-  CONSTANT cin_i2	 : NATURAL := 11;
-  CONSTANT cin_i3	 : NATURAL := 11;
-  CONSTANT cin_i4	 : NATURAL := 11;
-  CONSTANT rdown_i0_nq	 : NATURAL := 810;
-  CONSTANT rdown_i1_nq	 : NATURAL := 810;
-  CONSTANT rdown_i2_nq	 : NATURAL := 810;
-  CONSTANT rdown_i3_nq	 : NATURAL := 810;
-  CONSTANT rdown_i4_nq	 : NATURAL := 810;
-  CONSTANT rup_i0_nq	 : NATURAL := 890;
-  CONSTANT rup_i1_nq	 : NATURAL := 890;
-  CONSTANT rup_i2_nq	 : NATURAL := 890;
-  CONSTANT rup_i3_nq	 : NATURAL := 890;
-  CONSTANT rup_i4_nq	 : NATURAL := 890;
-  CONSTANT tphl_i2_nq	 : NATURAL := 638;
-  CONSTANT tplh_i4_nq	 : NATURAL := 664;
-  CONSTANT tphl_i0_nq	 : NATURAL := 684;
-  CONSTANT tphl_i4_nq	 : NATURAL := 718;
-  CONSTANT tphl_i3_nq	 : NATURAL := 732;
-  CONSTANT tplh_i1_nq	 : NATURAL := 758;
-  CONSTANT tphl_i1_nq	 : NATURAL := 780;
-  CONSTANT tplh_i3_nq	 : NATURAL := 795;
-  CONSTANT tplh_i0_nq	 : NATURAL := 801;
-  CONSTANT tplh_i2_nq	 : NATURAL := 809;
-  CONSTANT transistors	 : NATURAL := 16
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  i3	 : in  BIT;
-  i4	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END noa2ao222_x4;
-
-ARCHITECTURE behaviour_data_flow OF noa2ao222_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on noa2ao222_x4"
-  SEVERITY WARNING;
-  nq <= not (((i0 and i1) or ((i2 or i3) and i4))) after 1400 ps;
-END;
diff --git a/alliance/share/cells/sxlib/noa2ao222_x4.vhd b/alliance/share/cells/sxlib/noa2ao222_x4.vhd
deleted file mode 100644
index b2e57b15..00000000
--- a/alliance/share/cells/sxlib/noa2ao222_x4.vhd
+++ /dev/null
@@ -1,23 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY noa2ao222_x4 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  i3	: IN STD_LOGIC;
-  i4	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END noa2ao222_x4;
-
-ARCHITECTURE RTL OF noa2ao222_x4 IS
-BEGIN
-  nq <= NOT(((i0 AND i1) OR ((i2 OR i3) AND i4)));
-END RTL;
diff --git a/alliance/share/cells/sxlib/noa3ao322_x1.al b/alliance/share/cells/sxlib/noa3ao322_x1.al
deleted file mode 100644
index 181eded8..00000000
--- a/alliance/share/cells/sxlib/noa3ao322_x1.al
+++ /dev/null
@@ -1,59 +0,0 @@
-V ALLIANCE : 6
-H noa3ao322_x1,L,30/10/99
-C i0,IN,EXTERNAL,12
-C i1,IN,EXTERNAL,9
-C i2,IN,EXTERNAL,10
-C i3,IN,EXTERNAL,11
-C i4,IN,EXTERNAL,15
-C i5,IN,EXTERNAL,16
-C i6,IN,EXTERNAL,8
-C nq,OUT,EXTERNAL,1
-C vdd,IN,EXTERNAL,7
-C vss,IN,EXTERNAL,4
-T P,0.35,4.4,6,12,7,0,0.75,0.75,10.3,10.3,1.8,10.5,tr_00014
-T P,0.35,4.4,7,9,6,0,0.75,0.75,10.3,10.3,3.6,10.5,tr_00013
-T P,0.35,4.4,6,10,7,0,0.75,0.75,10.3,10.3,5.1,10.5,tr_00012
-T P,0.35,5.9,6,16,14,0,0.75,0.75,13.3,13.3,11.7,11.25,tr_00011
-T P,0.35,5.9,14,15,13,0,0.75,0.75,13.3,13.3,10.2,11.25,tr_00010
-T P,0.35,5.9,1,8,6,0,0.75,0.75,13.3,13.3,6.9,11.25,tr_00009
-T P,0.35,5.9,13,11,1,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00008
-T N,0.35,2.6,4,16,3,0,0.75,0.75,6.7,6.7,11.7,3.9,tr_00007
-T N,0.35,2.6,3,15,4,0,0.75,0.75,6.7,6.7,9.9,3.9,tr_00006
-T N,0.35,2.6,4,11,3,0,0.75,0.75,6.7,6.7,8.4,3.9,tr_00005
-T N,0.35,2.6,3,8,1,0,0.75,0.75,6.7,6.7,6.6,3.9,tr_00004
-T N,0.35,3.5,1,10,2,0,0.75,0.75,8.5,8.5,4.8,3.45,tr_00003
-T N,0.35,3.5,2,9,5,0,0.75,0.75,8.5,8.5,3.3,3.45,tr_00002
-T N,0.35,3.5,5,12,4,0,0.75,0.75,8.5,8.5,1.8,3.45,tr_00001
-S 16,EXTERNAL,i5
-Q 0.00226056
-S 15,EXTERNAL,i4
-Q 0.00241094
-S 14,INTERNAL
-Q 0
-S 13,INTERNAL
-Q 0
-S 12,EXTERNAL,i0
-Q 0.00254241
-S 11,EXTERNAL,i3
-Q 0.00199028
-S 10,EXTERNAL,i2
-Q 0.00241094
-S 9,EXTERNAL,i1
-Q 0.00269279
-S 8,EXTERNAL,i6
-Q 0.00212909
-S 7,EXTERNAL,vdd
-Q 0.0052329
-S 6,INTERNAL
-Q 0.00250174
-S 5,INTERNAL
-Q 0
-S 4,EXTERNAL,vss
-Q 0.00558543
-S 3,INTERNAL
-Q 0.00108534
-S 2,INTERNAL
-Q 0
-S 1,EXTERNAL,nq
-Q 0.0026146
-EOF
diff --git a/alliance/share/cells/sxlib/noa3ao322_x1.ap b/alliance/share/cells/sxlib/noa3ao322_x1.ap
deleted file mode 100644
index ca0b1ae9..00000000
--- a/alliance/share/cells/sxlib/noa3ao322_x1.ap
+++ /dev/null
@@ -1,137 +0,0 @@
-V ALLIANCE : 6
-H noa3ao322_x1,P, 6/ 9/2000,100
-A 0,0,4500,5000
-R 500,3500,ref_ref,i0_35
-R 500,3000,ref_ref,i0_30
-R 500,2500,ref_ref,i0_25
-R 500,2000,ref_ref,i0_20
-R 500,1500,ref_ref,i0_15
-R 500,1000,ref_ref,i0_10
-R 4000,3500,ref_ref,i5_35
-R 4000,3000,ref_ref,i5_30
-R 4000,2500,ref_ref,i5_25
-R 4000,2000,ref_ref,i5_20
-R 4000,1500,ref_ref,i5_15
-R 3500,3500,ref_ref,i4_35
-R 3500,3000,ref_ref,i4_30
-R 3500,2500,ref_ref,i4_25
-R 3500,2000,ref_ref,i4_20
-R 3500,1500,ref_ref,i4_15
-R 3000,3000,ref_ref,i3_30
-R 3000,2500,ref_ref,i3_25
-R 3000,2000,ref_ref,i3_20
-R 3000,1500,ref_ref,i3_15
-R 2500,3500,ref_ref,nq_35
-R 2500,3000,ref_ref,nq_30
-R 2500,2500,ref_ref,nq_25
-R 2500,2000,ref_ref,nq_20
-R 2500,1500,ref_ref,nq_15
-R 2000,3500,ref_ref,i6_35
-R 2000,3000,ref_ref,i6_30
-R 2000,2500,ref_ref,i6_25
-R 2000,2000,ref_ref,i6_20
-R 2000,1000,ref_ref,nq_10
-R 1500,3500,ref_ref,i2_35
-R 1500,3000,ref_ref,i2_30
-R 1500,2500,ref_ref,i2_25
-R 1500,2000,ref_ref,i2_20
-R 1500,1500,ref_ref,i2_15
-R 1000,3500,ref_ref,i1_35
-R 1000,3000,ref_ref,i1_30
-R 1000,2500,ref_ref,i1_25
-R 1000,2000,ref_ref,i1_20
-R 1000,1500,ref_ref,i1_15
-R 1000,1000,ref_ref,i1_10
-S 2000,2000,2200,2000,300,*,RIGHT,POLY
-S 2000,1000,2000,1500,200,nq,DOWN,CALU1
-S 2500,1500,2500,3500,200,nq,DOWN,CALU1
-S 500,1000,500,3500,200,i0,DOWN,CALU1
-S 4000,1500,4000,3500,200,i5,DOWN,CALU1
-S 3500,1500,3500,3500,200,i4,DOWN,CALU1
-S 3000,1500,3000,3000,200,i3,DOWN,CALU1
-S 2000,2000,2000,3500,200,i6,DOWN,CALU1
-S 1500,1500,1500,3500,200,i2,DOWN,CALU1
-S 1000,1000,1000,3500,200,i1,DOWN,CALU1
-S 3700,400,4100,400,300,*,RIGHT,PTIE
-S 1900,600,1900,1700,200,*,UP,NDIF
-S 600,400,600,1900,100,*,UP,NTRANS
-S 1100,400,1100,1900,100,*,UP,NTRANS
-S 1600,400,1600,1900,100,*,UP,NTRANS
-S 450,4700,850,4700,300,*,RIGHT,NTIE
-S 2000,2000,2000,3500,100,*,UP,ALU1
-S 1950,1500,2550,1500,200,*,RIGHT,ALU1
-S 1500,1500,1500,3500,100,*,UP,ALU1
-S 3000,1500,3000,3000,100,*,UP,ALU1
-S 2500,1450,2500,3550,200,*,UP,ALU1
-S 2000,950,2000,1500,200,*,UP,ALU1
-S 1000,1000,1000,3500,100,*,DOWN,ALU1
-S 3500,1500,3500,3500,100,*,UP,ALU1
-S 900,4000,4200,4000,100,*,RIGHT,ALU1
-S 0,4700,4500,4700,600,vdd,RIGHT,CALU1
-S 300,4000,300,4700,200,*,UP,ALU1
-S 0,300,4500,300,600,vss,RIGHT,CALU1
-S 2200,2600,2300,2600,100,*,RIGHT,POLY
-S 1600,2600,1700,2600,100,*,RIGHT,POLY
-S 3400,1900,3400,2600,100,i4,UP,POLY
-S 600,1900,600,2600,100,i0,UP,POLY
-S 2200,1900,2200,2600,100,i6,UP,POLY
-S 3900,1900,3900,2600,100,i5,DOWN,POLY
-S 1100,2600,1200,2600,100,*,RIGHT,POLY
-S 1600,1900,1600,2600,100,i2,UP,POLY
-S 1100,1900,1100,2600,100,i1,UP,POLY
-S 2500,900,2500,1700,200,*,UP,NDIF
-S 2200,700,2200,1900,100,*,UP,NTRANS
-S 2800,700,2800,1900,100,*,UP,NTRANS
-S 300,500,300,1700,300,*,UP,NDIF
-S 3200,2800,3200,4700,200,*,UP,PDIF
-S 2900,2600,2900,4900,100,*,UP,PTRANS
-S 2600,2800,2600,4700,200,*,UP,PDIF
-S 2300,2600,2300,4900,100,*,UP,PTRANS
-S 3400,2600,3400,4900,100,*,UP,PTRANS
-S 4200,2800,4200,4700,300,*,UP,PDIF
-S 3900,2600,3900,4900,100,*,UP,PTRANS
-S 0,3900,4500,3900,2400,*,RIGHT,NWELL
-S 500,1000,500,3500,100,*,DOWN,ALU1
-S 2800,2400,2900,2400,100,*,RIGHT,POLY
-S 2800,1900,2800,2400,100,i3,UP,POLY
-S 3300,700,3300,1900,100,*,UP,NTRANS
-S 3600,900,3600,1700,300,*,UP,NDIF
-S 3900,700,3900,1900,100,*,UP,NTRANS
-S 2500,1000,3600,1000,100,*,RIGHT,ALU1
-S 3300,1900,3400,1900,100,*,RIGHT,POLY
-S 4000,1500,4000,3500,100,*,DOWN,ALU1
-S 4200,900,4200,1700,300,*,UP,NDIF
-S 4200,300,4200,1000,200,*,DOWN,ALU1
-S 2000,2800,2000,4200,200,*,UP,PDIF
-S 1700,2600,1700,4400,100,*,UP,PTRANS
-S 1200,2600,1200,4400,100,*,UP,PTRANS
-S 900,2800,900,4200,300,*,UP,PDIF
-S 600,2600,600,4400,100,*,UP,PTRANS
-S 300,2800,300,4200,300,*,UP,PDIF
-S 1450,2800,1450,4650,200,*,UP,PDIF
-S 3050,350,3050,1700,200,*,UP,NDIF
-V 3700,400,CONT_BODY_P,*
-V 4100,400,CONT_BODY_P,*
-V 2450,400,CONT_BODY_P,*
-V 450,4700,CONT_BODY_N,*
-V 2000,2000,CONT_POLY,*
-V 1500,2000,CONT_POLY,*
-V 1000,2000,CONT_POLY,*
-V 1900,1000,CONT_DIF_N,*
-V 2500,1000,CONT_DIF_N,*
-V 2000,4000,CONT_DIF_P,*
-V 2600,3500,CONT_DIF_P,*
-V 4200,4000,CONT_DIF_P,*
-V 900,4000,CONT_DIF_P,*
-V 850,4700,CONT_BODY_N,*
-V 300,4000,CONT_DIF_P,*
-V 500,2000,CONT_POLY,*
-V 3000,2500,CONT_POLY,*
-V 3500,2500,CONT_POLY,*
-V 3600,1000,CONT_DIF_N,*
-V 300,500,CONT_DIF_N,*
-V 4000,2000,CONT_POLY,*
-V 4200,1000,CONT_DIF_N,*
-V 3050,400,CONT_DIF_N,*
-V 1450,4700,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/noa3ao322_x1.vbe b/alliance/share/cells/sxlib/noa3ao322_x1.vbe
deleted file mode 100644
index ff022776..00000000
--- a/alliance/share/cells/sxlib/noa3ao322_x1.vbe
+++ /dev/null
@@ -1,62 +0,0 @@
-ENTITY noa3ao322_x1 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 2250;
-  CONSTANT cin_i0	 : NATURAL := 13;
-  CONSTANT cin_i1	 : NATURAL := 13;
-  CONSTANT cin_i2	 : NATURAL := 13;
-  CONSTANT cin_i3	 : NATURAL := 13;
-  CONSTANT cin_i4	 : NATURAL := 13;
-  CONSTANT cin_i5	 : NATURAL := 13;
-  CONSTANT cin_i6	 : NATURAL := 13;
-  CONSTANT rdown_i0_nq	 : NATURAL := 3370;
-  CONSTANT rdown_i1_nq	 : NATURAL := 3370;
-  CONSTANT rdown_i2_nq	 : NATURAL := 3370;
-  CONSTANT rdown_i3_nq	 : NATURAL := 3210;
-  CONSTANT rdown_i4_nq	 : NATURAL := 3210;
-  CONSTANT rdown_i5_nq	 : NATURAL := 3210;
-  CONSTANT rdown_i6_nq	 : NATURAL := 3210;
-  CONSTANT rup_i0_nq	 : NATURAL := 6700;
-  CONSTANT rup_i1_nq	 : NATURAL := 6700;
-  CONSTANT rup_i2_nq	 : NATURAL := 6700;
-  CONSTANT rup_i3_nq	 : NATURAL := 6700;
-  CONSTANT rup_i4_nq	 : NATURAL := 6700;
-  CONSTANT rup_i5_nq	 : NATURAL := 6700;
-  CONSTANT rup_i6_nq	 : NATURAL := 3690;
-  CONSTANT tphl_i3_nq	 : NATURAL := 196;
-  CONSTANT tphl_i6_nq	 : NATURAL := 246;
-  CONSTANT tphl_i4_nq	 : NATURAL := 264;
-  CONSTANT tplh_i6_nq	 : NATURAL := 311;
-  CONSTANT tphl_i5_nq	 : NATURAL := 328;
-  CONSTANT tphl_i0_nq	 : NATURAL := 396;
-  CONSTANT tphl_i1_nq	 : NATURAL := 486;
-  CONSTANT tplh_i2_nq	 : NATURAL := 488;
-  CONSTANT tphl_i2_nq	 : NATURAL := 546;
-  CONSTANT tplh_i1_nq	 : NATURAL := 552;
-  CONSTANT tplh_i5_nq	 : NATURAL := 581;
-  CONSTANT tplh_i3_nq	 : NATURAL := 599;
-  CONSTANT tplh_i4_nq	 : NATURAL := 608;
-  CONSTANT tplh_i0_nq	 : NATURAL := 616;
-  CONSTANT transistors	 : NATURAL := 14
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  i3	 : in  BIT;
-  i4	 : in  BIT;
-  i5	 : in  BIT;
-  i6	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END noa3ao322_x1;
-
-ARCHITECTURE behaviour_data_flow OF noa3ao322_x1 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on noa3ao322_x1"
-  SEVERITY WARNING;
-  nq <= not ((((i0 and i1) and i2) or (((i3 or i4) or i5) and i6))) after 1200 ps;
-END;
diff --git a/alliance/share/cells/sxlib/noa3ao322_x1.vhd b/alliance/share/cells/sxlib/noa3ao322_x1.vhd
deleted file mode 100644
index 56c06273..00000000
--- a/alliance/share/cells/sxlib/noa3ao322_x1.vhd
+++ /dev/null
@@ -1,25 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY noa3ao322_x1 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  i3	: IN STD_LOGIC;
-  i4	: IN STD_LOGIC;
-  i5	: IN STD_LOGIC;
-  i6	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END noa3ao322_x1;
-
-ARCHITECTURE RTL OF noa3ao322_x1 IS
-BEGIN
-  nq <= NOT((((i0 AND i1) AND i2) OR (((i3 OR i4) OR i5) AND i6)));
-END RTL;
diff --git a/alliance/share/cells/sxlib/noa3ao322_x4.al b/alliance/share/cells/sxlib/noa3ao322_x4.al
deleted file mode 100644
index b2d65294..00000000
--- a/alliance/share/cells/sxlib/noa3ao322_x4.al
+++ /dev/null
@@ -1,69 +0,0 @@
-V ALLIANCE : 6
-H noa3ao322_x4,L,30/10/99
-C i0,IN,EXTERNAL,7
-C i1,IN,EXTERNAL,8
-C i2,IN,EXTERNAL,18
-C i3,IN,EXTERNAL,17
-C i4,IN,EXTERNAL,14
-C i5,IN,EXTERNAL,15
-C i6,IN,EXTERNAL,16
-C nq,OUT,EXTERNAL,3
-C vdd,IN,EXTERNAL,5
-C vss,IN,EXTERNAL,1
-T P,0.35,4.4,11,17,6,0,0.75,0.75,10.3,10.3,14.7,10.5,tr_00020
-T P,0.35,5.9,5,4,3,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00019
-T P,0.35,3.5,6,16,12,0,0.75,0.75,8.5,8.5,12.6,10.95,tr_00018
-T P,0.35,3.2,12,18,5,0,0.75,0.75,7.9,7.9,10.8,11.1,tr_00017
-T P,0.35,5.9,3,4,5,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00016
-T P,0.35,3.2,12,7,5,0,0.75,0.75,7.9,7.9,7.2,11.1,tr_00015
-T P,0.35,4.4,13,14,11,0,0.75,0.75,10.3,10.3,16.2,10.5,tr_00014
-T P,0.35,4.4,12,15,13,0,0.75,0.75,10.3,10.3,17.7,10.5,tr_00013
-T P,0.35,3.2,5,8,12,0,0.75,0.75,7.9,7.9,9,11.1,tr_00012
-T P,0.35,3.5,5,6,4,0,0.75,0.75,8.5,8.5,1.8,10.05,tr_00011
-T N,0.35,1.7,9,16,6,0,0.75,0.75,4.9,4.9,12.3,3.45,tr_00010
-T N,0.35,2.3,10,8,2,0,0.75,0.75,6.1,6.1,9,3.75,tr_00009
-T N,0.35,1.1,9,14,1,0,0.75,0.75,3.7,3.7,15.9,3.15,tr_00008
-T N,0.35,2.3,6,18,10,0,0.75,0.75,6.1,6.1,10.5,3.75,tr_00007
-T N,0.35,2.3,2,7,1,0,0.75,0.75,6.1,6.1,7.5,3.75,tr_00006
-T N,0.35,1.1,1,17,9,0,0.75,0.75,3.7,3.7,14.1,3.15,tr_00005
-T N,0.35,1.1,1,15,9,0,0.75,0.75,3.7,3.7,17.7,3.15,tr_00004
-T N,0.35,2,4,6,1,0,0.75,0.75,5.5,5.5,1.8,3.3,tr_00003
-T N,0.35,2.9,3,4,1,0,0.75,0.75,7.3,7.3,5.4,2.85,tr_00002
-T N,0.35,2.9,1,4,3,0,0.75,0.75,7.3,7.3,3.6,2.85,tr_00001
-S 18,EXTERNAL,i2
-Q 0.00247612
-S 17,EXTERNAL,i3
-Q 0.00290834
-S 16,EXTERNAL,i6
-Q 0.00262649
-S 15,EXTERNAL,i5
-Q 0.00275797
-S 14,EXTERNAL,i4
-Q 0.00283894
-S 13,INTERNAL
-Q 0
-S 12,INTERNAL
-Q 0.00261448
-S 11,INTERNAL
-Q 0
-S 10,INTERNAL
-Q 0
-S 9,INTERNAL
-Q 0.00114171
-S 8,EXTERNAL,i1
-Q 0.00275797
-S 7,EXTERNAL,i0
-Q 0.00290834
-S 6,INTERNAL
-Q 0.00675598
-S 5,EXTERNAL,vdd
-Q 0.00900775
-S 4,INTERNAL
-Q 0.00543312
-S 3,EXTERNAL,nq
-Q 0.00258522
-S 2,INTERNAL
-Q 0
-S 1,EXTERNAL,vss
-Q 0.00847896
-EOF
diff --git a/alliance/share/cells/sxlib/noa3ao322_x4.ap b/alliance/share/cells/sxlib/noa3ao322_x4.ap
deleted file mode 100644
index 3e8b73c9..00000000
--- a/alliance/share/cells/sxlib/noa3ao322_x4.ap
+++ /dev/null
@@ -1,191 +0,0 @@
-V ALLIANCE : 6
-H noa3ao322_x4,P, 6/ 9/2000,100
-A 0,0,6500,5000
-R 1500,3000,ref_ref,nq_30
-R 1500,2500,ref_ref,nq_25
-R 1500,2000,ref_ref,nq_20
-R 1500,1500,ref_ref,nq_15
-R 1500,1000,ref_ref,nq_10
-R 1500,4000,ref_ref,nq_40
-R 2500,3500,ref_ref,i0_35
-R 5000,3500,ref_ref,i3_35
-R 6000,2500,ref_ref,i5_25
-R 6000,3000,ref_ref,i5_30
-R 6000,3500,ref_ref,i5_35
-R 2500,1500,ref_ref,i0_15
-R 2500,2000,ref_ref,i0_20
-R 2500,2500,ref_ref,i0_25
-R 2500,3000,ref_ref,i0_30
-R 5000,3000,ref_ref,i3_30
-R 5500,1500,ref_ref,i4_15
-R 5500,2000,ref_ref,i4_20
-R 5500,2500,ref_ref,i4_25
-R 5500,3000,ref_ref,i4_30
-R 5500,3500,ref_ref,i4_35
-R 6000,1500,ref_ref,i5_15
-R 6000,2000,ref_ref,i5_20
-R 5000,1500,ref_ref,i3_15
-R 5000,2000,ref_ref,i3_20
-R 5000,2500,ref_ref,i3_25
-R 3500,2500,ref_ref,i2_25
-R 3500,3000,ref_ref,i2_30
-R 3500,3500,ref_ref,i2_35
-R 4000,2000,ref_ref,i6_20
-R 4000,2500,ref_ref,i6_25
-R 4000,3000,ref_ref,i6_30
-R 4000,3500,ref_ref,i6_35
-R 3000,1500,ref_ref,i1_15
-R 3000,2000,ref_ref,i1_20
-R 3000,2500,ref_ref,i1_25
-R 3000,3000,ref_ref,i1_30
-R 3000,3500,ref_ref,i1_35
-R 1500,3500,ref_ref,nq_35
-R 3500,2000,ref_ref,i2_20
-S 4500,2800,4500,4200,300,*,DOWN,PDIF
-S 4000,2000,4200,2000,300,*,RIGHT,POLY
-S 0,3900,6500,3900,2400,*,RIGHT,NWELL
-S 600,2600,600,4100,100,*,UP,PTRANS
-S 300,2800,300,3900,300,*,UP,PDIF
-S 2100,2800,2100,4700,200,*,DOWN,PDIF
-S 3000,3000,3000,4400,100,*,UP,PTRANS
-S 3300,3200,3300,4500,300,*,DOWN,PDIF
-S 3900,3100,3900,4200,200,*,UP,PDIF
-S 5900,2600,5900,4400,100,*,UP,PTRANS
-S 5400,2600,5400,4400,100,*,UP,PTRANS
-S 2400,3000,2400,4400,100,*,UP,PTRANS
-S 900,2800,900,4700,300,*,UP,PDIF
-S 1200,2600,1200,4900,100,*,UP,PTRANS
-S 6200,2800,6200,4200,300,*,UP,PDIF
-S 3600,3000,3600,4400,100,*,UP,PTRANS
-S 4200,2900,4200,4400,100,*,UP,PTRANS
-S 1800,2600,1800,4900,100,*,UP,PTRANS
-S 1500,2800,1500,4700,300,*,DOWN,PDIF
-S 2700,3200,2700,4200,300,*,UP,PDIF
-S 4900,2600,4900,4400,100,*,UP,PTRANS
-S 5000,400,5000,1200,300,*,DOWN,NDIF
-S 1200,300,1200,1600,100,*,DOWN,NTRANS
-S 1800,300,1800,1600,100,*,DOWN,NTRANS
-S 1500,500,1500,1400,300,*,UP,NDIF
-S 2200,400,2200,1600,300,*,UP,NDIF
-S 900,500,900,1400,300,*,DOWN,NDIF
-S 600,600,600,1600,100,*,DOWN,NTRANS
-S 300,800,300,1400,300,*,DOWN,NDIF
-S 5900,700,5900,1400,100,*,UP,NTRANS
-S 6200,900,6200,1200,300,*,UP,NDIF
-S 4700,700,4700,1400,100,*,UP,NTRANS
-S 2500,700,2500,1800,100,*,UP,NTRANS
-S 3500,700,3500,1800,100,*,UP,NTRANS
-S 5300,700,5300,1400,100,*,UP,NTRANS
-S 3800,900,3800,1400,200,*,UP,NDIF
-S 3000,700,3000,1800,100,*,UP,NTRANS
-S 5600,900,5600,1200,300,*,UP,NDIF
-S 4100,700,4100,1600,100,*,UP,NTRANS
-S 4400,900,4400,1400,200,*,UP,NDIF
-S 2800,400,4300,400,300,*,RIGHT,PTIE
-S 5700,400,6100,400,300,*,RIGHT,PTIE
-S 600,1600,600,2600,100,*,DOWN,POLY
-S 1000,1600,1000,1700,100,*,DOWN,POLY
-S 1000,1600,1800,1600,100,*,RIGHT,POLY
-S 1000,2600,1800,2600,100,*,LEFT,POLY
-S 1000,2500,1000,2600,100,*,DOWN,POLY
-S 600,2100,2000,2100,100,*,LEFT,POLY
-S 5300,1400,5300,1900,100,*,UP,POLY
-S 4100,1600,4100,1900,100,*,UP,POLY
-S 4700,1900,4900,1900,100,*,RIGHT,POLY
-S 3600,1900,3600,3000,100,i2,UP,POLY
-S 3500,1800,3500,2000,100,*,UP,POLY
-S 4700,1400,4700,1900,100,*,UP,POLY
-S 4100,1900,4200,1900,100,*,LEFT,POLY
-S 2400,1900,2500,1900,100,*,RIGHT,POLY
-S 3000,1900,3000,3000,100,*,DOWN,POLY
-S 2500,1800,2500,2000,100,*,DOWN,POLY
-S 5900,1900,5900,2600,100,i5,DOWN,POLY
-S 5400,1900,5400,2600,100,i4,UP,POLY
-S 2400,1900,2400,3000,100,*,DOWN,POLY
-S 5300,1900,5400,1900,100,*,RIGHT,POLY
-S 3000,1800,3000,2000,100,*,UP,POLY
-S 5900,1400,5900,2000,100,*,UP,POLY
-S 4200,1900,4200,2900,100,i6,UP,POLY
-S 4900,1900,4900,2600,100,*,UP,POLY
-S 0,300,6500,300,600,vss,RIGHT,CALU1
-S 6200,300,6200,1000,200,*,DOWN,ALU1
-S 0,4700,6500,4700,600,vdd,RIGHT,CALU1
-S 300,2500,1000,2500,100,*,LEFT,ALU1
-S 300,1700,1000,1700,100,*,LEFT,ALU1
-S 300,1200,300,3500,100,*,DOWN,ALU1
-S 3500,2000,3500,3500,100,*,UP,ALU1
-S 900,3000,900,4500,200,*,UP,ALU1
-S 900,600,900,1200,200,*,DOWN,ALU1
-S 4400,1000,5600,1000,100,*,RIGHT,ALU1
-S 5000,1500,5000,3500,100,*,UP,ALU1
-S 4500,1500,4500,3500,100,*,DOWN,ALU1
-S 2000,1000,3800,1000,100,*,LEFT,ALU1
-S 1500,1000,1500,4000,200,*,UP,ALU1
-S 2100,4000,2100,4700,200,*,UP,ALU1
-S 3800,1500,4500,1500,100,*,RIGHT,ALU1
-S 3800,1000,3800,1500,100,*,UP,ALU1
-S 2500,1500,2500,3500,100,*,DOWN,ALU1
-S 3000,1500,3000,3500,100,*,DOWN,ALU1
-S 5500,1500,5500,3500,100,*,UP,ALU1
-S 4000,2000,4000,3500,100,*,UP,ALU1
-S 6000,1500,6000,3500,100,*,DOWN,ALU1
-S 2700,4000,6200,4000,100,*,RIGHT,ALU1
-S 2000,1000,2000,2000,100,*,UP,ALU1
-S 1500,1000,1500,4000,200,nq,DOWN,CALU1
-S 2500,1500,2500,3500,200,i0,DOWN,CALU1
-S 5000,1500,5000,3500,200,i3,DOWN,CALU1
-S 6000,1500,6000,3500,200,i5,DOWN,CALU1
-S 5500,1500,5500,3500,200,i4,DOWN,CALU1
-S 3500,2000,3500,3500,200,i2,DOWN,CALU1
-S 4000,2000,4000,3500,200,i6,DOWN,CALU1
-S 3000,1500,3000,3500,200,i1,DOWN,CALU1
-V 300,4700,CONT_BODY_N,*
-V 300,3000,CONT_DIF_P,*
-V 300,3500,CONT_DIF_P,*
-V 2700,4700,CONT_BODY_N,*
-V 6200,4000,CONT_DIF_P,*
-V 1500,3000,CONT_DIF_P,*
-V 2700,4000,CONT_DIF_P,*
-V 900,4500,CONT_DIF_P,*
-V 900,4000,CONT_DIF_P,*
-V 900,3500,CONT_DIF_P,*
-V 900,3000,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 4500,4700,CONT_BODY_N,*
-V 3900,4700,CONT_BODY_N,*
-V 2100,4000,CONT_DIF_P,*
-V 5700,4700,CONT_BODY_N,*
-V 4500,3000,CONT_DIF_P,*
-V 4500,3500,CONT_DIF_P,*
-V 3300,4500,CONT_DIF_P,*
-V 3900,4000,CONT_DIF_P,*
-V 5100,4700,CONT_BODY_N,*
-V 1500,3500,CONT_DIF_P,*
-V 2200,500,CONT_DIF_N,*
-V 5000,500,CONT_DIF_N,*
-V 300,1200,CONT_DIF_N,*
-V 4400,1000,CONT_DIF_N,*
-V 900,1200,CONT_DIF_N,*
-V 900,700,CONT_DIF_N,*
-V 1500,1000,CONT_DIF_N,*
-V 3800,1000,CONT_DIF_N,*
-V 6200,1000,CONT_DIF_N,*
-V 5600,1000,CONT_DIF_N,*
-V 300,300,CONT_BODY_P,*
-V 2800,400,CONT_BODY_P,*
-V 4350,400,CONT_BODY_P,*
-V 3300,400,CONT_BODY_P,*
-V 3800,400,CONT_BODY_P,*
-V 6100,400,CONT_BODY_P,*
-V 5700,400,CONT_BODY_P,*
-V 2500,2000,CONT_POLY,*
-V 3000,2000,CONT_POLY,*
-V 3500,2000,CONT_POLY,*
-V 1000,2500,CONT_POLY,*
-V 1000,1700,CONT_POLY,*
-V 5000,2500,CONT_POLY,*
-V 2000,2000,CONT_POLY,*
-V 4000,2000,CONT_POLY,*
-V 5500,2500,CONT_POLY,*
-V 6000,2000,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/sxlib/noa3ao322_x4.sym b/alliance/share/cells/sxlib/noa3ao322_x4.sym
deleted file mode 100644
index 25b1ee2e..00000000
Binary files a/alliance/share/cells/sxlib/noa3ao322_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/noa3ao322_x4.vbe b/alliance/share/cells/sxlib/noa3ao322_x4.vbe
deleted file mode 100644
index 1fc4b8a6..00000000
--- a/alliance/share/cells/sxlib/noa3ao322_x4.vbe
+++ /dev/null
@@ -1,62 +0,0 @@
-ENTITY noa3ao322_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 3250;
-  CONSTANT cin_i0	 : NATURAL := 10;
-  CONSTANT cin_i1	 : NATURAL := 9;
-  CONSTANT cin_i2	 : NATURAL := 9;
-  CONSTANT cin_i3	 : NATURAL := 9;
-  CONSTANT cin_i4	 : NATURAL := 9;
-  CONSTANT cin_i5	 : NATURAL := 9;
-  CONSTANT cin_i6	 : NATURAL := 9;
-  CONSTANT rdown_i0_nq	 : NATURAL := 810;
-  CONSTANT rdown_i1_nq	 : NATURAL := 810;
-  CONSTANT rdown_i2_nq	 : NATURAL := 810;
-  CONSTANT rdown_i3_nq	 : NATURAL := 810;
-  CONSTANT rdown_i4_nq	 : NATURAL := 810;
-  CONSTANT rdown_i5_nq	 : NATURAL := 810;
-  CONSTANT rdown_i6_nq	 : NATURAL := 810;
-  CONSTANT rup_i0_nq	 : NATURAL := 890;
-  CONSTANT rup_i1_nq	 : NATURAL := 890;
-  CONSTANT rup_i2_nq	 : NATURAL := 890;
-  CONSTANT rup_i3_nq	 : NATURAL := 890;
-  CONSTANT rup_i4_nq	 : NATURAL := 890;
-  CONSTANT rup_i5_nq	 : NATURAL := 890;
-  CONSTANT rup_i6_nq	 : NATURAL := 890;
-  CONSTANT tplh_i6_nq	 : NATURAL := 718;
-  CONSTANT tphl_i3_nq	 : NATURAL := 729;
-  CONSTANT tphl_i6_nq	 : NATURAL := 738;
-  CONSTANT tphl_i0_nq	 : NATURAL := 819;
-  CONSTANT tphl_i4_nq	 : NATURAL := 821;
-  CONSTANT tplh_i2_nq	 : NATURAL := 874;
-  CONSTANT tplh_i5_nq	 : NATURAL := 900;
-  CONSTANT tphl_i5_nq	 : NATURAL := 907;
-  CONSTANT tphl_i1_nq	 : NATURAL := 914;
-  CONSTANT tplh_i4_nq	 : NATURAL := 924;
-  CONSTANT tplh_i3_nq	 : NATURAL := 926;
-  CONSTANT tplh_i1_nq	 : NATURAL := 931;
-  CONSTANT tplh_i0_nq	 : NATURAL := 987;
-  CONSTANT tphl_i2_nq	 : NATURAL := 990;
-  CONSTANT transistors	 : NATURAL := 20
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  i3	 : in  BIT;
-  i4	 : in  BIT;
-  i5	 : in  BIT;
-  i6	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END noa3ao322_x4;
-
-ARCHITECTURE behaviour_data_flow OF noa3ao322_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on noa3ao322_x4"
-  SEVERITY WARNING;
-  nq <= not ((((i0 and i1) and i2) or (((i3 or i4) or i5) and i6))) after 1600 ps;
-END;
diff --git a/alliance/share/cells/sxlib/noa3ao322_x4.vhd b/alliance/share/cells/sxlib/noa3ao322_x4.vhd
deleted file mode 100644
index 610f1dff..00000000
--- a/alliance/share/cells/sxlib/noa3ao322_x4.vhd
+++ /dev/null
@@ -1,25 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY noa3ao322_x4 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  i3	: IN STD_LOGIC;
-  i4	: IN STD_LOGIC;
-  i5	: IN STD_LOGIC;
-  i6	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END noa3ao322_x4;
-
-ARCHITECTURE RTL OF noa3ao322_x4 IS
-BEGIN
-  nq <= NOT((((i0 AND i1) AND i2) OR (((i3 OR i4) OR i5) AND i6)));
-END RTL;
diff --git a/alliance/share/cells/sxlib/nts_x1.al b/alliance/share/cells/sxlib/nts_x1.al
deleted file mode 100644
index 69a2f5ec..00000000
--- a/alliance/share/cells/sxlib/nts_x1.al
+++ /dev/null
@@ -1,30 +0,0 @@
-V ALLIANCE : 6
-H nts_x1,L,30/10/99
-C cmd,IN,EXTERNAL,7
-C i,IN,EXTERNAL,8
-C nq,TRISTATE,EXTERNAL,1
-C vdd,IN,EXTERNAL,6
-C vss,IN,EXTERNAL,3
-T P,0.35,5.9,6,8,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00006
-T P,0.35,5.9,5,4,1,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00005
-T P,0.35,2.9,4,7,6,0,0.75,0.75,7.3,7.3,7.2,9.75,tr_00004
-T N,0.35,2.9,2,8,3,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00003
-T N,0.35,2.9,1,7,2,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002
-T N,0.35,1.4,3,7,4,0,0.75,0.75,4.3,4.3,7.2,3,tr_00001
-S 8,EXTERNAL,i
-Q 0.00317129
-S 7,EXTERNAL,cmd
-Q 0.00472134
-S 6,EXTERNAL,vdd
-Q 0.00497229
-S 5,INTERNAL
-Q 0
-S 4,INTERNAL
-Q 0.00329099
-S 3,EXTERNAL,vss
-Q 0.00420847
-S 2,INTERNAL
-Q 0
-S 1,EXTERNAL,nq
-Q 0.00258522
-EOF
diff --git a/alliance/share/cells/sxlib/nts_x1.ap b/alliance/share/cells/sxlib/nts_x1.ap
deleted file mode 100644
index 5f2664b5..00000000
--- a/alliance/share/cells/sxlib/nts_x1.ap
+++ /dev/null
@@ -1,78 +0,0 @@
-V ALLIANCE : 6
-H nts_x1,P,30/ 8/2000,100
-A 0,0,3000,5000
-R 500,3000,ref_ref,i_30
-R 500,3500,ref_ref,i_35
-R 1500,1500,ref_ref,nq_15
-R 1500,2000,ref_ref,nq_20
-R 1500,3000,ref_ref,nq_30
-R 1500,3500,ref_ref,nq_35
-R 1500,4000,ref_ref,nq_40
-R 1500,1000,ref_ref,nq_10
-R 1000,1000,ref_ref,cmd_10
-R 1000,1500,ref_ref,cmd_15
-R 1000,2000,ref_ref,cmd_20
-R 500,1000,ref_ref,i_10
-R 500,1500,ref_ref,i_15
-R 500,2000,ref_ref,i_20
-R 500,2500,ref_ref,i_25
-R 1500,2500,ref_ref,nq_25
-R 500,4000,ref_ref,i_40
-R 1000,2500,ref_ref,cmd_25
-R 1000,3000,ref_ref,cmd_30
-R 1000,3500,ref_ref,cmd_35
-R 1000,4000,ref_ref,cmd_40
-S 1500,1000,1500,4000,200,nq,DOWN,CALU1
-S 500,1000,500,4000,200,i,DOWN,CALU1
-S 1000,1000,1000,4000,200,cmd,DOWN,CALU1
-S 0,4700,3000,4700,600,vdd,RIGHT,CALU1
-S 0,3900,3000,3900,2400,*,RIGHT,NWELL
-S 0,300,3000,300,600,vss,RIGHT,CALU1
-S 2100,1000,2100,3500,100,*,DOWN,ALU1
-S 1200,2600,2000,2600,100,*,RIGHT,POLY
-S 2000,2500,2000,2600,100,*,DOWN,POLY
-S 2400,1400,2400,2600,100,*,DOWN,POLY
-S 600,100,600,1400,100,*,UP,NTRANS
-S 1500,300,1500,1200,300,*,DOWN,NDIF
-S 900,300,900,1200,300,*,UP,NDIF
-S 300,300,300,1200,300,*,UP,NDIF
-S 1200,100,1200,1400,100,*,UP,NTRANS
-S 2700,800,2700,1200,300,*,UP,NDIF
-S 2100,800,2100,1200,300,*,UP,NDIF
-S 2400,600,2400,1400,100,*,UP,NTRANS
-S 600,2600,600,4900,100,*,DOWN,PTRANS
-S 1200,2600,1200,4900,100,*,DOWN,PTRANS
-S 1500,2800,1500,4700,300,*,DOWN,PDIF
-S 900,2800,900,4700,300,*,DOWN,PDIF
-S 300,2800,300,4700,300,*,DOWN,PDIF
-S 2700,2800,2700,3700,300,*,DOWN,PDIF
-S 2100,2800,2100,3700,300,*,DOWN,PDIF
-S 2400,2600,2400,3900,100,*,DOWN,PTRANS
-S 500,1000,500,4000,100,*,UP,ALU1
-S 600,1400,600,2600,100,*,UP,POLY
-S 1500,1000,1500,4000,200,*,DOWN,ALU1
-S 1000,1000,1000,4000,100,*,DOWN,ALU1
-S 1200,1400,1200,2000,100,*,UP,POLY
-S 1000,2000,2400,2000,100,*,RIGHT,POLY
-S 2700,300,2700,1000,200,*,DOWN,ALU1
-S 2700,3000,2700,4700,200,*,UP,ALU1
-V 2000,2500,CONT_POLY,*
-V 2100,1000,CONT_DIF_N,*
-V 300,500,CONT_DIF_N,*
-V 1500,1000,CONT_DIF_N,*
-V 2700,1000,CONT_DIF_N,*
-V 1500,4000,CONT_DIF_P,*
-V 1500,3500,CONT_DIF_P,*
-V 1500,3000,CONT_DIF_P,*
-V 2700,3000,CONT_DIF_P,*
-V 2700,3500,CONT_DIF_P,*
-V 2100,3500,CONT_DIF_P,*
-V 2100,3000,CONT_DIF_P,*
-V 300,4500,CONT_DIF_P,*
-V 500,2000,CONT_POLY,*
-V 1000,2000,CONT_POLY,*
-V 2700,300,CONT_BODY_P,*
-V 2700,4700,CONT_BODY_N,*
-V 2100,300,CONT_BODY_P,*
-V 2100,4700,CONT_BODY_N,*
-EOF
diff --git a/alliance/share/cells/sxlib/nts_x1.sym b/alliance/share/cells/sxlib/nts_x1.sym
deleted file mode 100644
index f4ed35b4..00000000
Binary files a/alliance/share/cells/sxlib/nts_x1.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/nts_x1.vbe b/alliance/share/cells/sxlib/nts_x1.vbe
deleted file mode 100644
index f6cada4a..00000000
--- a/alliance/share/cells/sxlib/nts_x1.vbe
+++ /dev/null
@@ -1,37 +0,0 @@
-ENTITY nts_x1 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 1500;
-  CONSTANT cin_cmd	 : NATURAL := 14;
-  CONSTANT cin_i	 : NATURAL := 14;
-  CONSTANT rdown_cmd_nq	 : NATURAL := 2850;
-  CONSTANT rdown_i_nq	 : NATURAL := 2850;
-  CONSTANT rup_cmd_nq	 : NATURAL := 3210;
-  CONSTANT rup_i_nq	 : NATURAL := 3210;
-  CONSTANT tphl_cmd_nq	 : NATURAL := 41;
-  CONSTANT tphl_i_nq	 : NATURAL := 169;
-  CONSTANT tplh_i_nq	 : NATURAL := 201;
-  CONSTANT tphh_cmd_nq	 : NATURAL := 249;
-  CONSTANT transistors	 : NATURAL := 6
-);
-PORT (
-  cmd	 : in  BIT;
-  i	 : in  BIT;
-  nq	 : out MUX_BIT BUS;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END nts_x1;
-
-ARCHITECTURE behaviour_data_flow OF nts_x1 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on nts_x1"
-  SEVERITY WARNING;
-
-  label0 : BLOCK (cmd = '1')
-  BEGIN
-    nq <= GUARDED not (i) after 800 ps;
-  END BLOCK label0;
-
-END;
diff --git a/alliance/share/cells/sxlib/nts_x1.vhd b/alliance/share/cells/sxlib/nts_x1.vhd
deleted file mode 100644
index e1177332..00000000
--- a/alliance/share/cells/sxlib/nts_x1.vhd
+++ /dev/null
@@ -1,26 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY nts_x1 IS
-PORT(
-  cmd	: IN STD_LOGIC;
-  i	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END nts_x1;
-
-ARCHITECTURE RTL OF nts_x1 IS
-BEGIN
-  PROCESS ( i, cmd )
-  BEGIN
-    IF (cmd = '1')
-    THEN nq <= NOT(i);
-    ELSE nq <= 'Z';
-    END IF;
-  END PROCESS;
-END RTL;
diff --git a/alliance/share/cells/sxlib/nts_x2.al b/alliance/share/cells/sxlib/nts_x2.al
deleted file mode 100644
index c5f00858..00000000
--- a/alliance/share/cells/sxlib/nts_x2.al
+++ /dev/null
@@ -1,38 +0,0 @@
-V ALLIANCE : 6
-H nts_x2,L,30/10/99
-C cmd,IN,EXTERNAL,9
-C i,IN,EXTERNAL,10
-C nq,TRISTATE,EXTERNAL,2
-C vdd,IN,EXTERNAL,6
-C vss,IN,EXTERNAL,4
-T P,0.35,5.9,6,10,7,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00010
-T P,0.35,5.9,7,8,2,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00009
-T P,0.35,5.9,2,8,5,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00008
-T P,0.35,5.9,5,10,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00007
-T P,0.35,2.9,6,9,8,0,0.75,0.75,7.3,7.3,10.2,9.75,tr_00006
-T N,0.35,2.9,2,9,3,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00005
-T N,0.35,2.9,1,9,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00004
-T N,0.35,2.9,4,10,1,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00003
-T N,0.35,2.9,3,10,4,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00002
-T N,0.35,1.4,8,9,4,0,0.75,0.75,4.3,4.3,10.2,3,tr_00001
-S 10,EXTERNAL,i
-Q 0.00541538
-S 9,EXTERNAL,cmd
-Q 0.00510823
-S 8,INTERNAL
-Q 0.00545178
-S 7,INTERNAL
-Q 0
-S 6,EXTERNAL,vdd
-Q 0.00589026
-S 5,INTERNAL
-Q 0
-S 4,EXTERNAL,vss
-Q 0.00495018
-S 3,INTERNAL
-Q 0
-S 2,EXTERNAL,nq
-Q 0.00258522
-S 1,INTERNAL
-Q 0
-EOF
diff --git a/alliance/share/cells/sxlib/nts_x2.ap b/alliance/share/cells/sxlib/nts_x2.ap
deleted file mode 100644
index b50cc0a0..00000000
--- a/alliance/share/cells/sxlib/nts_x2.ap
+++ /dev/null
@@ -1,92 +0,0 @@
-V ALLIANCE : 6
-H nts_x2,P,30/ 8/2000,100
-A 0,0,4000,5000
-R 1000,4000,ref_ref,i_40
-R 1000,3500,ref_ref,i_35
-R 1000,3000,ref_ref,i_30
-R 1000,2500,ref_ref,i_25
-R 1000,2000,ref_ref,i_20
-R 1000,1500,ref_ref,i_15
-R 1000,1000,ref_ref,i_10
-R 1500,4000,ref_ref,nq_40
-R 1500,3500,ref_ref,nq_35
-R 1500,3000,ref_ref,nq_30
-R 1500,2500,ref_ref,nq_25
-R 1500,2000,ref_ref,nq_20
-R 1500,1500,ref_ref,nq_15
-R 1500,1000,ref_ref,nq_10
-R 3000,2000,ref_ref,cmd_20
-R 3000,1500,ref_ref,cmd_15
-R 3000,1000,ref_ref,cmd_10
-R 3000,2500,ref_ref,cmd_25
-R 3000,3000,ref_ref,cmd_30
-R 3000,3500,ref_ref,cmd_35
-S 1000,1000,1000,4000,200,i,DOWN,CALU1
-S 1500,1000,1500,4000,200,nq,DOWN,CALU1
-S 3000,1000,3000,3500,200,cmd,DOWN,CALU1
-S 300,500,300,1000,200,*,DOWN,ALU1
-S 2100,300,2100,1200,300,*,UP,NDIF
-S 1500,300,1500,1200,300,*,UP,NDIF
-S 900,300,900,1200,300,*,UP,NDIF
-S 300,300,300,1200,300,*,UP,NDIF
-S 1000,1000,1000,4000,100,*,DOWN,ALU1
-S 1200,2600,2000,2600,100,*,RIGHT,POLY
-S 1200,1400,2000,1400,100,*,RIGHT,POLY
-S 600,2000,2400,2000,100,*,RIGHT,POLY
-S 1200,100,1200,1400,100,*,UP,NTRANS
-S 1800,100,1800,1400,100,*,UP,NTRANS
-S 2400,100,2400,1400,100,*,UP,NTRANS
-S 2400,1400,2400,2600,100,*,DOWN,POLY
-S 600,2600,600,4900,100,*,DOWN,PTRANS
-S 1200,2600,1200,4900,100,*,DOWN,PTRANS
-S 1800,2600,1800,4900,100,*,DOWN,PTRANS
-S 2400,2600,2400,4900,100,*,DOWN,PTRANS
-S 300,2800,300,4700,300,*,DOWN,PDIF
-S 600,100,600,1400,100,*,UP,NTRANS
-S 600,1400,600,2600,100,*,UP,POLY
-S 900,2800,900,4700,300,*,DOWN,PDIF
-S 1500,2800,1500,4700,300,*,DOWN,PDIF
-S 2100,2800,2100,4700,300,*,DOWN,PDIF
-S 2700,2800,2700,4700,300,*,DOWN,PDIF
-S 0,3900,4000,3900,2400,*,RIGHT,NWELL
-S 3400,2600,3400,3900,100,*,DOWN,PTRANS
-S 3700,2800,3700,3700,300,*,DOWN,PDIF
-S 300,3000,300,4500,200,*,UP,ALU1
-S 0,4700,4000,4700,600,vdd,RIGHT,CALU1
-S 0,300,4000,300,600,vss,RIGHT,CALU1
-S 3400,600,3400,1400,100,*,UP,NTRANS
-S 3700,800,3700,1200,300,*,UP,NDIF
-S 3400,1400,3400,2600,100,*,DOWN,POLY
-S 2000,1500,3000,1500,100,*,RIGHT,ALU1
-S 3000,2000,3400,2000,300,*,RIGHT,POLY
-S 2000,4000,3700,4000,100,*,RIGHT,ALU1
-S 3700,1000,3700,4000,100,*,DOWN,ALU1
-S 2000,2500,2000,4000,100,*,DOWN,ALU1
-S 3000,1000,3000,3500,100,*,UP,ALU1
-S 2900,300,2900,1200,700,*,DOWN,NDIF
-S 2900,2800,2900,4700,700,*,UP,PDIF
-S 1500,1000,1500,4000,200,*,DOWN,ALU1
-V 3700,3500,CONT_DIF_P,*
-V 3700,1000,CONT_DIF_N,*
-V 1000,2000,CONT_POLY,*
-V 1500,3000,CONT_DIF_P,*
-V 1500,3500,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 1500,1000,CONT_DIF_N,*
-V 300,1000,CONT_DIF_N,*
-V 300,500,CONT_DIF_N,*
-V 2000,2500,CONT_POLY,*
-V 300,4000,CONT_DIF_P,*
-V 300,3500,CONT_DIF_P,*
-V 300,3000,CONT_DIF_P,*
-V 3700,3000,CONT_DIF_P,*
-V 3700,4700,CONT_BODY_N,*
-V 300,4500,CONT_DIF_P,*
-V 3700,300,CONT_BODY_P,*
-V 2000,1500,CONT_POLY,*
-V 3000,2000,CONT_POLY,*
-V 2700,4500,CONT_DIF_P,*
-V 2700,500,CONT_DIF_N,*
-V 3100,4500,CONT_DIF_P,*
-V 3100,500,CONT_DIF_N,*
-EOF
diff --git a/alliance/share/cells/sxlib/nts_x2.sym b/alliance/share/cells/sxlib/nts_x2.sym
deleted file mode 100644
index c821e1e9..00000000
Binary files a/alliance/share/cells/sxlib/nts_x2.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/nts_x2.vbe b/alliance/share/cells/sxlib/nts_x2.vbe
deleted file mode 100644
index 4bb47086..00000000
--- a/alliance/share/cells/sxlib/nts_x2.vbe
+++ /dev/null
@@ -1,37 +0,0 @@
-ENTITY nts_x2 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 2000;
-  CONSTANT cin_cmd	 : NATURAL := 18;
-  CONSTANT cin_i	 : NATURAL := 28;
-  CONSTANT rdown_cmd_nq	 : NATURAL := 1430;
-  CONSTANT rdown_i_nq	 : NATURAL := 1430;
-  CONSTANT rup_cmd_nq	 : NATURAL := 1600;
-  CONSTANT rup_i_nq	 : NATURAL := 1600;
-  CONSTANT tphl_cmd_nq	 : NATURAL := 33;
-  CONSTANT tphl_i_nq	 : NATURAL := 167;
-  CONSTANT tplh_i_nq	 : NATURAL := 201;
-  CONSTANT tphh_cmd_nq	 : NATURAL := 330;
-  CONSTANT transistors	 : NATURAL := 10
-);
-PORT (
-  cmd	 : in  BIT;
-  i	 : in  BIT;
-  nq	 : out MUX_BIT BUS;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END nts_x2;
-
-ARCHITECTURE behaviour_data_flow OF nts_x2 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on nts_x2"
-  SEVERITY WARNING;
-
-  label0 : BLOCK (cmd = '1')
-  BEGIN
-    nq <= GUARDED not (i) after 900 ps;
-  END BLOCK label0;
-
-END;
diff --git a/alliance/share/cells/sxlib/nts_x2.vhd b/alliance/share/cells/sxlib/nts_x2.vhd
deleted file mode 100644
index b982932d..00000000
--- a/alliance/share/cells/sxlib/nts_x2.vhd
+++ /dev/null
@@ -1,26 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY nts_x2 IS
-PORT(
-  cmd	: IN STD_LOGIC;
-  i	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END nts_x2;
-
-ARCHITECTURE RTL OF nts_x2 IS
-BEGIN
-  PROCESS ( i, cmd )
-  BEGIN
-    IF (cmd = '1')
-    THEN nq <= NOT(i);
-    ELSE nq <= 'Z';
-    END IF;
-  END PROCESS;
-END RTL;
diff --git a/alliance/share/cells/sxlib/nxr2_x1.al b/alliance/share/cells/sxlib/nxr2_x1.al
deleted file mode 100644
index be155f9d..00000000
--- a/alliance/share/cells/sxlib/nxr2_x1.al
+++ /dev/null
@@ -1,40 +0,0 @@
-V ALLIANCE : 6
-H nxr2_x1,L,30/10/99
-C i0,IN,EXTERNAL,8
-C i1,IN,EXTERNAL,10
-C nq,OUT,EXTERNAL,2
-C vdd,IN,EXTERNAL,7
-C vss,IN,EXTERNAL,4
-T P,0.35,5.9,7,9,6,0,0.75,0.75,13.3,13.3,9,11.25,tr_00012
-T P,0.35,5.9,6,5,2,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00011
-T P,0.35,5.9,6,8,7,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00010
-T P,0.35,5.9,2,10,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00009
-T P,0.35,2.9,7,8,5,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00008
-T P,0.35,2.9,9,10,7,0,0.75,0.75,7.3,7.3,10.8,11.25,tr_00007
-T N,0.35,2.9,4,8,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00006
-T N,0.35,2.9,1,9,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00005
-T N,0.35,2.9,2,5,3,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00004
-T N,0.35,2.9,3,10,4,0,0.75,0.75,7.3,7.3,9,2.25,tr_00003
-T N,0.35,1.4,4,10,9,0,0.75,0.75,4.3,4.3,10.8,3,tr_00002
-T N,0.35,1.4,5,8,4,0,0.75,0.75,4.3,4.3,1.8,3,tr_00001
-S 10,EXTERNAL,i1
-Q 0.00533757
-S 9,INTERNAL
-Q 0.00655161
-S 8,EXTERNAL,i0
-Q 0.00413388
-S 7,EXTERNAL,vdd
-Q 0.0047041
-S 6,INTERNAL
-Q 0.00217068
-S 5,INTERNAL
-Q 0.0053513
-S 4,EXTERNAL,vss
-Q 0.0047041
-S 3,INTERNAL
-Q 0
-S 2,EXTERNAL,nq
-Q 0.00299651
-S 1,INTERNAL
-Q 0
-EOF
diff --git a/alliance/share/cells/sxlib/nxr2_x1.ap b/alliance/share/cells/sxlib/nxr2_x1.ap
deleted file mode 100644
index 4cd41052..00000000
--- a/alliance/share/cells/sxlib/nxr2_x1.ap
+++ /dev/null
@@ -1,111 +0,0 @@
-V ALLIANCE : 6
-H nxr2_x1,P,30/ 8/2000,100
-A 0,0,4500,5000
-R 1500,2500,ref_ref,nq_25
-R 1500,2000,ref_ref,nq_20
-R 1500,1500,ref_ref,nq_15
-R 1500,1000,ref_ref,nq_10
-R 1500,3500,ref_ref,nq_35
-R 1500,3000,ref_ref,nq_30
-R 1000,1000,ref_ref,i0_10
-R 1000,1500,ref_ref,i0_15
-R 1000,2500,ref_ref,i0_25
-R 1000,2000,ref_ref,i0_20
-R 1000,3000,ref_ref,i0_30
-R 1000,3500,ref_ref,i0_35
-R 1000,4000,ref_ref,i0_40
-R 3500,1000,ref_ref,i1_10
-R 3500,1500,ref_ref,i1_15
-R 3500,2000,ref_ref,i1_20
-R 3500,2500,ref_ref,i1_25
-R 3500,3000,ref_ref,i1_30
-R 3500,3500,ref_ref,i1_35
-R 3500,4000,ref_ref,i1_40
-S 1500,1000,1500,3500,200,nq,DOWN,CALU1
-S 1000,1000,1000,4000,200,i0,DOWN,CALU1
-S 3500,1000,3500,4000,200,i1,DOWN,CALU1
-S 0,3900,4500,3900,2400,*,RIGHT,NWELL
-S 1500,4000,2700,4000,100,*,RIGHT,ALU1
-S 300,1000,300,3500,100,*,DOWN,ALU1
-S 1000,1000,1000,4000,100,*,UP,ALU1
-S 0,4700,4500,4700,600,vdd,RIGHT,CALU1
-S 0,300,4500,300,600,vss,RIGHT,CALU1
-S 300,2000,2400,2000,100,*,RIGHT,POLY
-S 600,1400,1200,1400,100,*,RIGHT,POLY
-S 2400,1400,2400,2600,100,*,DOWN,POLY
-S 600,2600,1200,2600,100,*,RIGHT,POLY
-S 600,2600,600,3100,100,*,DOWN,POLY
-S 3000,2600,3000,4900,100,*,UP,PTRANS
-S 2700,2800,2700,4700,300,*,DOWN,PDIF
-S 2400,2600,2400,4900,100,*,UP,PTRANS
-S 2100,2800,2100,4700,300,*,DOWN,PDIF
-S 900,2800,900,4700,300,*,DOWN,PDIF
-S 1200,2600,1200,4900,100,*,UP,PTRANS
-S 1500,2800,1500,4700,300,*,DOWN,PDIF
-S 1800,2600,1800,4900,100,*,UP,PTRANS
-S 300,3300,300,4200,300,*,UP,PDIF
-S 600,3100,600,4400,100,*,UP,PTRANS
-S 3300,2800,3300,4700,300,*,DOWN,PDIF
-S 3600,3100,3600,4400,100,*,UP,PTRANS
-S 3300,300,3300,1200,300,*,UP,NDIF
-S 1200,100,1200,1400,100,*,DOWN,NTRANS
-S 900,300,900,1200,300,*,UP,NDIF
-S 1500,300,1500,1200,300,*,UP,NDIF
-S 1800,100,1800,1400,100,*,DOWN,NTRANS
-S 2100,300,2100,1200,300,*,UP,NDIF
-S 2400,100,2400,1400,100,*,DOWN,NTRANS
-S 2700,300,2700,1200,300,*,UP,NDIF
-S 3000,100,3000,1400,100,*,DOWN,NTRANS
-S 300,800,300,1200,300,*,UP,NDIF
-S 3600,600,3600,1400,100,*,DOWN,NTRANS
-S 600,600,600,1400,100,*,DOWN,NTRANS
-S 3600,2600,3600,3100,100,*,DOWN,POLY
-S 3500,1000,3500,4000,100,*,DOWN,ALU1
-S 1800,2600,2100,2600,100,*,RIGHT,POLY
-S 1800,1400,2100,1400,100,*,RIGHT,POLY
-S 3000,2000,4000,2000,100,*,RIGHT,POLY
-S 4000,1000,4000,3500,100,*,DOWN,ALU1
-S 4000,3300,4000,4200,300,*,DOWN,PDIF
-S 4000,800,4000,1200,300,*,UP,NDIF
-S 3000,2000,3000,2600,100,*,DOWN,POLY
-S 2000,2500,3500,2500,100,*,RIGHT,ALU1
-S 3000,1400,3600,1400,100,*,RIGHT,POLY
-S 2000,1500,2500,1500,100,*,RIGHT,ALU1
-S 2500,1500,2500,2000,100,*,DOWN,ALU1
-S 2500,2000,3000,2000,100,*,RIGHT,ALU1
-S 1450,3500,2100,3500,200,*,RIGHT,ALU1
-S 1500,950,1500,3550,200,*,UP,ALU1
-S 1450,1000,2100,1000,200,*,RIGHT,ALU1
-S 300,3500,300,4000,100,*,DOWN,ALU1
-S 4000,3500,4000,4000,100,*,UP,ALU1
-S 2700,3000,2700,4000,100,*,UP,ALU1
-V 300,2000,CONT_POLY,*
-V 1000,1500,CONT_POLY,*
-V 1000,2500,CONT_POLY,*
-V 3900,300,CONT_BODY_P,*
-V 300,300,CONT_BODY_P,*
-V 3900,4700,CONT_BODY_N,*
-V 300,4700,CONT_BODY_N,*
-V 3300,4500,CONT_DIF_P,*
-V 300,3500,CONT_DIF_P,*
-V 2700,4000,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 900,4500,CONT_DIF_P,*
-V 3300,500,CONT_DIF_N,*
-V 900,500,CONT_DIF_N,*
-V 300,1000,CONT_DIF_N,*
-V 2100,1000,CONT_DIF_N,*
-V 2100,3500,CONT_DIF_P,*
-V 2000,1500,CONT_POLY,*
-V 2000,2500,CONT_POLY,*
-V 3500,1500,CONT_POLY,*
-V 3500,2500,CONT_POLY,*
-V 4000,2000,CONT_POLY,*
-V 4000,3500,CONT_DIF_P,*
-V 4000,1000,CONT_DIF_N,*
-V 3000,2000,CONT_POLY,*
-V 300,4000,CONT_DIF_P,*
-V 4000,4000,CONT_DIF_P,*
-V 2700,3500,CONT_DIF_P,*
-V 2700,3000,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/nxr2_x1.sym b/alliance/share/cells/sxlib/nxr2_x1.sym
deleted file mode 100644
index 94e1c85d..00000000
Binary files a/alliance/share/cells/sxlib/nxr2_x1.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/nxr2_x1.vbe b/alliance/share/cells/sxlib/nxr2_x1.vbe
deleted file mode 100644
index 6a25e761..00000000
--- a/alliance/share/cells/sxlib/nxr2_x1.vbe
+++ /dev/null
@@ -1,40 +0,0 @@
-ENTITY nxr2_x1 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 2250;
-  CONSTANT cin_i0	 : NATURAL := 21;
-  CONSTANT cin_i1	 : NATURAL := 22;
-  CONSTANT rdown_i0_nq	 : NATURAL := 2850;
-  CONSTANT rdown_i0_nq	 : NATURAL := 2850;
-  CONSTANT rdown_i1_nq	 : NATURAL := 2850;
-  CONSTANT rdown_i1_nq	 : NATURAL := 2850;
-  CONSTANT rup_i0_nq	 : NATURAL := 3210;
-  CONSTANT rup_i0_nq	 : NATURAL := 3210;
-  CONSTANT rup_i1_nq	 : NATURAL := 3210;
-  CONSTANT rup_i1_nq	 : NATURAL := 3210;
-  CONSTANT tphl_i1_nq	 : NATURAL := 156;
-  CONSTANT tphl_i0_nq	 : NATURAL := 288;
-  CONSTANT tplh_i0_nq	 : NATURAL := 293;
-  CONSTANT tplh_i1_nq	 : NATURAL := 327;
-  CONSTANT tphh_i0_nq	 : NATURAL := 366;
-  CONSTANT tpll_i0_nq	 : NATURAL := 389;
-  CONSTANT tphh_i1_nq	 : NATURAL := 395;
-  CONSTANT tpll_i1_nq	 : NATURAL := 503;
-  CONSTANT transistors	 : NATURAL := 12
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END nxr2_x1;
-
-ARCHITECTURE behaviour_data_flow OF nxr2_x1 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on nxr2_x1"
-  SEVERITY WARNING;
-  nq <= not ((i0 xor i1)) after 1100 ps;
-END;
diff --git a/alliance/share/cells/sxlib/nxr2_x1.vhd b/alliance/share/cells/sxlib/nxr2_x1.vhd
deleted file mode 100644
index 9ad239ca..00000000
--- a/alliance/share/cells/sxlib/nxr2_x1.vhd
+++ /dev/null
@@ -1,20 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY nxr2_x1 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END nxr2_x1;
-
-ARCHITECTURE RTL OF nxr2_x1 IS
-BEGIN
-  nq <= NOT((i0 XOR i1));
-END RTL;
diff --git a/alliance/share/cells/sxlib/nxr2_x4.al b/alliance/share/cells/sxlib/nxr2_x4.al
deleted file mode 100644
index eec8e730..00000000
--- a/alliance/share/cells/sxlib/nxr2_x4.al
+++ /dev/null
@@ -1,46 +0,0 @@
-V ALLIANCE : 6
-H nxr2_x4,L,30/10/99
-C i0,IN,EXTERNAL,8
-C i1,IN,EXTERNAL,10
-C nq,OUT,EXTERNAL,11
-C vdd,IN,EXTERNAL,6
-C vss,IN,EXTERNAL,1
-T P,0.35,2.9,9,10,6,0,0.75,0.75,7.3,7.3,10.8,9.75,tr_00016
-T P,0.35,2.9,6,8,4,0,0.75,0.75,7.3,7.3,1.8,9.75,tr_00015
-T P,0.35,5.9,11,2,6,0,0.75,0.75,13.3,13.3,14.4,11.25,tr_00014
-T P,0.35,5.9,6,2,11,0,0.75,0.75,13.3,13.3,16.2,11.25,tr_00013
-T P,0.35,5.9,2,9,7,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00012
-T P,0.35,5.9,7,8,6,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00011
-T P,0.35,5.9,7,4,2,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00010
-T P,0.35,5.9,6,10,7,0,0.75,0.75,13.3,13.3,9,11.25,tr_00009
-T N,0.35,2.9,11,2,1,0,0.75,0.75,7.3,7.3,16.2,2.25,tr_00008
-T N,0.35,2.9,1,2,11,0,0.75,0.75,7.3,7.3,14.4,2.25,tr_00007
-T N,0.35,1.4,4,8,1,0,0.75,0.75,4.3,4.3,1.8,3,tr_00006
-T N,0.35,1.4,1,10,9,0,0.75,0.75,4.3,4.3,10.8,3,tr_00005
-T N,0.35,2.9,3,9,1,0,0.75,0.75,7.3,7.3,9,2.25,tr_00004
-T N,0.35,2.9,2,4,3,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00003
-T N,0.35,2.9,5,10,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00002
-T N,0.35,2.9,1,8,5,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00001
-S 11,EXTERNAL,nq
-Q 0.00258522
-S 10,EXTERNAL,i1
-Q 0.00462772
-S 9,INTERNAL
-Q 0.00536068
-S 8,EXTERNAL,i0
-Q 0.00370588
-S 7,INTERNAL
-Q 0.00114171
-S 6,EXTERNAL,vdd
-Q 0.00866628
-S 5,INTERNAL
-Q 0
-S 4,INTERNAL
-Q 0.0044986
-S 3,INTERNAL
-Q 0
-S 2,INTERNAL
-Q 0.00780232
-S 1,EXTERNAL,vss
-Q 0.00666861
-EOF
diff --git a/alliance/share/cells/sxlib/nxr2_x4.ap b/alliance/share/cells/sxlib/nxr2_x4.ap
deleted file mode 100644
index 40f36fe5..00000000
--- a/alliance/share/cells/sxlib/nxr2_x4.ap
+++ /dev/null
@@ -1,135 +0,0 @@
-V ALLIANCE : 6
-H nxr2_x4,P, 6/ 9/2000,100
-A 0,0,6000,5000
-R 5000,4000,ref_ref,nq_40
-R 5000,1000,ref_ref,nq_10
-R 5000,3000,ref_ref,nq_30
-R 5000,3500,ref_ref,nq_35
-R 5000,2500,ref_ref,nq_25
-R 5000,2000,ref_ref,nq_20
-R 5000,1500,ref_ref,nq_15
-R 3500,4000,ref_ref,i1_40
-R 3500,3500,ref_ref,i1_35
-R 3500,3000,ref_ref,i1_30
-R 3500,2500,ref_ref,i1_25
-R 3500,2000,ref_ref,i1_20
-R 3500,1500,ref_ref,i1_15
-R 1000,4000,ref_ref,i0_40
-R 1000,3500,ref_ref,i0_35
-R 1000,3000,ref_ref,i0_30
-R 1000,2000,ref_ref,i0_20
-R 1000,2500,ref_ref,i0_25
-R 1000,1500,ref_ref,i0_15
-R 1000,1000,ref_ref,i0_10
-S 4500,2000,5400,2000,300,*,RIGHT,POLY
-S 5000,1000,5000,4000,200,nq,DOWN,CALU1
-S 3500,1500,3500,4000,200,i1,DOWN,CALU1
-S 1000,1000,1000,4000,200,i0,DOWN,CALU1
-S 300,1000,300,3000,100,*,DOWN,ALU1
-S 3000,2600,3600,2600,100,*,RIGHT,POLY
-S 3000,1400,3000,2000,100,*,DOWN,POLY
-S 2000,1500,3500,1500,100,*,RIGHT,ALU1
-S 2500,2000,2500,2500,100,*,DOWN,ALU1
-S 2000,2500,2500,2500,100,*,RIGHT,ALU1
-S 4500,300,4500,1000,300,*,UP,NDIF
-S 3900,800,3900,1600,300,*,UP,NDIF
-S 1500,1000,4500,1000,100,*,RIGHT,ALU1
-S 4500,1000,4500,2000,100,*,DOWN,ALU1
-S 4800,1400,4800,2600,100,*,DOWN,POLY
-S 5400,1400,5400,2600,100,*,DOWN,POLY
-S 5700,500,5700,1000,200,*,DOWN,ALU1
-S 5700,3000,5700,4500,200,*,DOWN,ALU1
-S 4500,3500,4500,4500,200,*,DOWN,ALU1
-S 3500,1500,3500,4000,100,*,DOWN,ALU1
-S 4000,1500,4000,2900,100,*,DOWN,ALU1
-S 0,300,6000,300,600,vss,RIGHT,CALU1
-S 0,4700,6000,4700,600,vdd,RIGHT,CALU1
-S 5700,300,5700,1200,300,*,UP,NDIF
-S 5100,300,5100,1200,300,*,UP,NDIF
-S 5400,100,5400,1400,100,*,DOWN,NTRANS
-S 4800,100,4800,1400,100,*,DOWN,NTRANS
-S 3900,2800,3900,3700,300,*,DOWN,PDIF
-S 4500,3400,4500,4700,300,*,DOWN,PDIF
-S 5100,2800,5100,4700,300,*,DOWN,PDIF
-S 3600,2600,3600,3900,100,*,UP,PTRANS
-S 600,2600,600,3900,100,*,UP,PTRANS
-S 300,2800,300,3700,300,*,UP,PDIF
-S 4800,2600,4800,4900,100,*,UP,PTRANS
-S 5400,2600,5400,4900,100,*,UP,PTRANS
-S 5700,2800,5700,4700,300,*,DOWN,PDIF
-S 2500,2000,3000,2000,100,*,RIGHT,ALU1
-S 3000,2000,4000,2000,100,*,RIGHT,POLY
-S 1800,1400,2100,1400,100,*,RIGHT,POLY
-S 1800,2600,2100,2600,100,*,RIGHT,POLY
-S 1500,3500,2100,3500,100,*,RIGHT,ALU1
-S 1500,1000,1500,3500,100,*,UP,ALU1
-S 600,600,600,1400,100,*,DOWN,NTRANS
-S 3600,600,3600,1400,100,*,DOWN,NTRANS
-S 300,800,300,1200,300,*,UP,NDIF
-S 3000,100,3000,1400,100,*,DOWN,NTRANS
-S 2700,300,2700,1200,300,*,UP,NDIF
-S 2400,100,2400,1400,100,*,DOWN,NTRANS
-S 2100,300,2100,1200,300,*,UP,NDIF
-S 1800,100,1800,1400,100,*,DOWN,NTRANS
-S 1500,300,1500,1200,300,*,UP,NDIF
-S 900,300,900,1200,300,*,UP,NDIF
-S 1200,100,1200,1400,100,*,DOWN,NTRANS
-S 3300,300,3300,1200,300,*,UP,NDIF
-S 3300,2800,3300,4700,300,*,DOWN,PDIF
-S 1800,2600,1800,4900,100,*,UP,PTRANS
-S 1500,2800,1500,4700,300,*,DOWN,PDIF
-S 1200,2600,1200,4900,100,*,UP,PTRANS
-S 900,2800,900,4700,300,*,DOWN,PDIF
-S 2100,2800,2100,4700,300,*,DOWN,PDIF
-S 2400,2600,2400,4900,100,*,UP,PTRANS
-S 2700,2800,2700,4700,300,*,DOWN,PDIF
-S 3000,2600,3000,4900,100,*,UP,PTRANS
-S 600,2600,1200,2600,100,*,RIGHT,POLY
-S 2400,1400,2400,2600,100,*,DOWN,POLY
-S 600,1400,1200,1400,100,*,RIGHT,POLY
-S 300,2000,2400,2000,100,*,RIGHT,POLY
-S 1000,1000,1000,4000,100,*,UP,ALU1
-S 1500,4000,2700,4000,100,*,RIGHT,ALU1
-S 0,3900,6000,3900,2400,*,LEFT,NWELL
-S 5000,1000,5000,4000,200,*,DOWN,ALU1
-V 4500,2000,CONT_POLY,*
-V 4000,2900,CONT_DIF_P,*
-V 4000,1500,CONT_DIF_N,*
-V 5100,1000,CONT_DIF_N,*
-V 5100,3000,CONT_DIF_P,*
-V 5100,3500,CONT_DIF_P,*
-V 5100,4000,CONT_DIF_P,*
-V 4500,4500,CONT_DIF_P,*
-V 4500,4000,CONT_DIF_P,*
-V 4500,3500,CONT_DIF_P,*
-V 5700,3000,CONT_DIF_P,*
-V 5700,3500,CONT_DIF_P,*
-V 5700,4000,CONT_DIF_P,*
-V 5700,4500,CONT_DIF_P,*
-V 5700,1000,CONT_DIF_N,*
-V 5700,500,CONT_DIF_N,*
-V 4500,500,CONT_DIF_N,*
-V 300,3000,CONT_DIF_P,*
-V 3000,2000,CONT_POLY,*
-V 4000,2000,CONT_POLY,*
-V 3500,2500,CONT_POLY,*
-V 3500,1500,CONT_POLY,*
-V 2000,2500,CONT_POLY,*
-V 2000,1500,CONT_POLY,*
-V 2100,3500,CONT_DIF_P,*
-V 2100,1000,CONT_DIF_N,*
-V 300,1000,CONT_DIF_N,*
-V 900,500,CONT_DIF_N,*
-V 3300,500,CONT_DIF_N,*
-V 900,4500,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 2700,4000,CONT_DIF_P,*
-V 3300,4500,CONT_DIF_P,*
-V 300,4700,CONT_BODY_N,*
-V 3900,4700,CONT_BODY_N,*
-V 300,300,CONT_BODY_P,*
-V 3900,300,CONT_BODY_P,*
-V 1000,2500,CONT_POLY,*
-V 1000,1500,CONT_POLY,*
-V 300,2000,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/sxlib/nxr2_x4.sym b/alliance/share/cells/sxlib/nxr2_x4.sym
deleted file mode 100644
index 4e7a0cde..00000000
Binary files a/alliance/share/cells/sxlib/nxr2_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/nxr2_x4.vbe b/alliance/share/cells/sxlib/nxr2_x4.vbe
deleted file mode 100644
index 69c3294a..00000000
--- a/alliance/share/cells/sxlib/nxr2_x4.vbe
+++ /dev/null
@@ -1,40 +0,0 @@
-ENTITY nxr2_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 3000;
-  CONSTANT cin_i0	 : NATURAL := 20;
-  CONSTANT cin_i1	 : NATURAL := 21;
-  CONSTANT rdown_i0_nq	 : NATURAL := 810;
-  CONSTANT rdown_i0_nq	 : NATURAL := 810;
-  CONSTANT rdown_i1_nq	 : NATURAL := 810;
-  CONSTANT rdown_i1_nq	 : NATURAL := 810;
-  CONSTANT rup_i0_nq	 : NATURAL := 890;
-  CONSTANT rup_i0_nq	 : NATURAL := 890;
-  CONSTANT rup_i1_nq	 : NATURAL := 890;
-  CONSTANT rup_i1_nq	 : NATURAL := 890;
-  CONSTANT tpll_i1_nq	 : NATURAL := 453;
-  CONSTANT tphh_i0_nq	 : NATURAL := 469;
-  CONSTANT tpll_i0_nq	 : NATURAL := 481;
-  CONSTANT tphl_i0_nq	 : NATURAL := 522;
-  CONSTANT tplh_i1_nq	 : NATURAL := 542;
-  CONSTANT tphl_i1_nq	 : NATURAL := 553;
-  CONSTANT tplh_i0_nq	 : NATURAL := 553;
-  CONSTANT tphh_i1_nq	 : NATURAL := 568;
-  CONSTANT transistors	 : NATURAL := 16
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END nxr2_x4;
-
-ARCHITECTURE behaviour_data_flow OF nxr2_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on nxr2_x4"
-  SEVERITY WARNING;
-  nq <= not ((i0 xor i1)) after 1200 ps;
-END;
diff --git a/alliance/share/cells/sxlib/nxr2_x4.vhd b/alliance/share/cells/sxlib/nxr2_x4.vhd
deleted file mode 100644
index 929c679a..00000000
--- a/alliance/share/cells/sxlib/nxr2_x4.vhd
+++ /dev/null
@@ -1,20 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY nxr2_x4 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  nq	: OUT STD_LOGIC
-);
-END nxr2_x4;
-
-ARCHITECTURE RTL OF nxr2_x4 IS
-BEGIN
-  nq <= NOT((i0 XOR i1));
-END RTL;
diff --git a/alliance/share/cells/sxlib/o2_x2.al b/alliance/share/cells/sxlib/o2_x2.al
deleted file mode 100644
index e0196360..00000000
--- a/alliance/share/cells/sxlib/o2_x2.al
+++ /dev/null
@@ -1,28 +0,0 @@
-V ALLIANCE : 6
-H o2_x2,L,30/10/99
-C i0,IN,EXTERNAL,6
-C i1,IN,EXTERNAL,7
-C q,OUT,EXTERNAL,3
-C vdd,IN,EXTERNAL,4
-C vss,IN,EXTERNAL,1
-T P,0.35,5.9,3,2,4,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00006
-T P,0.35,4.4,4,6,5,0,0.75,0.75,10.3,10.3,3.6,10.5,tr_00005
-T P,0.35,4.4,5,7,2,0,0.75,0.75,10.3,10.3,2.4,10.5,tr_00004
-T N,0.35,1.4,1,7,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00003
-T N,0.35,1.4,2,6,1,0,0.75,0.75,4.3,4.3,3.6,3,tr_00002
-T N,0.35,2.9,3,2,1,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00001
-S 7,EXTERNAL,i1
-Q 0.00282737
-S 6,EXTERNAL,i0
-Q 0.00344095
-S 5,INTERNAL
-Q 0
-S 4,EXTERNAL,vdd
-Q 0.00298567
-S 3,EXTERNAL,q
-Q 0.00264397
-S 2,INTERNAL
-Q 0.00463918
-S 1,EXTERNAL,vss
-Q 0.0033382
-EOF
diff --git a/alliance/share/cells/sxlib/o2_x2.ap b/alliance/share/cells/sxlib/o2_x2.ap
deleted file mode 100644
index 4b3c3f88..00000000
--- a/alliance/share/cells/sxlib/o2_x2.ap
+++ /dev/null
@@ -1,70 +0,0 @@
-V ALLIANCE : 6
-H o2_x2,P,30/ 8/2000,100
-A 0,0,2500,5000
-R 2000,1000,ref_ref,q_10
-R 2000,4000,ref_ref,q_40
-R 2000,3500,ref_ref,q_35
-R 2000,3000,ref_ref,q_30
-R 2000,2500,ref_ref,q_25
-R 2000,2000,ref_ref,q_20
-R 2000,1500,ref_ref,q_15
-R 1500,2000,ref_ref,i0_20
-R 1500,1500,ref_ref,i0_15
-R 1500,4000,ref_ref,i0_40
-R 1500,3500,ref_ref,i0_35
-R 1500,3000,ref_ref,i0_30
-R 1500,2500,ref_ref,i0_25
-R 1500,1000,ref_ref,i0_10
-R 500,2500,ref_ref,i1_25
-R 500,2000,ref_ref,i1_20
-R 500,1500,ref_ref,i1_15
-R 500,3500,ref_ref,i1_35
-R 500,3000,ref_ref,i1_30
-S 2000,1000,2000,4000,200,q,DOWN,CALU1
-S 1500,1000,1500,4000,200,i0,DOWN,CALU1
-S 500,1500,500,3500,200,i1,DOWN,CALU1
-S 2000,950,2000,4050,200,*,UP,ALU1
-S 1800,1400,1800,2600,100,*,DOWN,POLY
-S 1000,2000,1800,2000,100,*,RIGHT,POLY
-S 500,1500,500,3500,100,*,UP,ALU1
-S 600,2600,800,2600,100,*,RIGHT,POLY
-S 600,1400,600,2600,100,*,DOWN,POLY
-S 1200,2500,1500,2500,300,*,RIGHT,POLY
-S 1200,1500,1500,1500,300,*,RIGHT,POLY
-S 0,300,2500,300,600,vss,RIGHT,CALU1
-S 0,4700,2500,4700,600,vdd,RIGHT,CALU1
-S 1500,2800,1500,4700,300,*,UP,PDIF
-S 500,2800,500,4200,300,*,DOWN,PDIF
-S 300,2800,300,4200,300,*,DOWN,PDIF
-S 2100,2800,2100,4700,300,*,UP,PDIF
-S 1800,2600,1800,4900,100,*,UP,PTRANS
-S 1200,2600,1200,4400,100,*,UP,PTRANS
-S 800,2600,800,4400,100,*,UP,PTRANS
-S 600,600,600,1400,100,*,DOWN,NTRANS
-S 900,800,900,1200,300,*,UP,NDIF
-S 1200,600,1200,1400,100,*,DOWN,NTRANS
-S 300,400,300,1200,300,*,UP,NDIF
-S 1500,300,1500,1200,300,*,UP,NDIF
-S 1800,100,1800,1400,100,*,UP,NTRANS
-S 2100,300,2100,1200,300,*,UP,NDIF
-S 1500,1000,1500,4000,100,*,UP,ALU1
-S 0,3900,2500,3900,2400,*,LEFT,NWELL
-S 950,1000,950,4000,100,*,UP,ALU1
-S 300,4000,950,4000,100,*,LEFT,ALU1
-V 2100,4000,CONT_DIF_P,*
-V 2100,3500,CONT_DIF_P,*
-V 2100,3000,CONT_DIF_P,*
-V 500,2000,CONT_POLY,*
-V 1000,2000,CONT_POLY,*
-V 1400,2500,CONT_POLY,*
-V 1400,1500,CONT_POLY,*
-V 900,300,CONT_BODY_P,*
-V 300,4700,CONT_BODY_N,*
-V 1500,4500,CONT_DIF_P,*
-V 1500,500,CONT_DIF_N,*
-V 900,1000,CONT_DIF_N,*
-V 1500,500,CONT_DIF_N,*
-V 300,500,CONT_DIF_N,*
-V 2100,1000,CONT_DIF_N,*
-V 300,4000,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/o2_x2.sym b/alliance/share/cells/sxlib/o2_x2.sym
deleted file mode 100644
index d70269b2..00000000
Binary files a/alliance/share/cells/sxlib/o2_x2.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/o2_x2.vbe b/alliance/share/cells/sxlib/o2_x2.vbe
deleted file mode 100644
index 9e115a06..00000000
--- a/alliance/share/cells/sxlib/o2_x2.vbe
+++ /dev/null
@@ -1,32 +0,0 @@
-ENTITY o2_x2 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 1250;
-  CONSTANT cin_i0	 : NATURAL := 10;
-  CONSTANT cin_i1	 : NATURAL := 10;
-  CONSTANT rdown_i0_q	 : NATURAL := 1620;
-  CONSTANT rdown_i1_q	 : NATURAL := 1620;
-  CONSTANT rup_i0_q	 : NATURAL := 1790;
-  CONSTANT rup_i1_q	 : NATURAL := 1790;
-  CONSTANT tpll_i0_q	 : NATURAL := 310;
-  CONSTANT tphh_i1_q	 : NATURAL := 335;
-  CONSTANT tpll_i1_q	 : NATURAL := 364;
-  CONSTANT tphh_i0_q	 : NATURAL := 406;
-  CONSTANT transistors	 : NATURAL := 6
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END o2_x2;
-
-ARCHITECTURE behaviour_data_flow OF o2_x2 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on o2_x2"
-  SEVERITY WARNING;
-  q <= (i0 or i1) after 1000 ps;
-END;
diff --git a/alliance/share/cells/sxlib/o2_x2.vhd b/alliance/share/cells/sxlib/o2_x2.vhd
deleted file mode 100644
index 6ff6bde5..00000000
--- a/alliance/share/cells/sxlib/o2_x2.vhd
+++ /dev/null
@@ -1,20 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY o2_x2 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END o2_x2;
-
-ARCHITECTURE RTL OF o2_x2 IS
-BEGIN
-  q <= (i0 OR i1);
-END RTL;
diff --git a/alliance/share/cells/sxlib/o2_x4.al b/alliance/share/cells/sxlib/o2_x4.al
deleted file mode 100644
index 396b7653..00000000
--- a/alliance/share/cells/sxlib/o2_x4.al
+++ /dev/null
@@ -1,30 +0,0 @@
-V ALLIANCE : 6
-H o2_x4,L,30/10/99
-C i0,IN,EXTERNAL,6
-C i1,IN,EXTERNAL,7
-C q,OUT,EXTERNAL,3
-C vdd,IN,EXTERNAL,4
-C vss,IN,EXTERNAL,2
-T P,0.35,5.9,4,1,3,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00008
-T P,0.35,5.9,3,1,4,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00007
-T P,0.35,4.4,4,6,5,0,0.75,0.75,10.3,10.3,3.6,10.5,tr_00006
-T P,0.35,4.4,5,7,1,0,0.75,0.75,10.3,10.3,2.4,10.5,tr_00005
-T N,0.35,2.9,2,1,3,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00004
-T N,0.35,1.4,2,7,1,0,0.75,0.75,4.3,4.3,1.8,3,tr_00003
-T N,0.35,1.4,1,6,2,0,0.75,0.75,4.3,4.3,3.6,3,tr_00002
-T N,0.35,2.9,3,1,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00001
-S 7,EXTERNAL,i1
-Q 0.00282737
-S 6,EXTERNAL,i0
-Q 0.00344095
-S 5,INTERNAL
-Q 0
-S 4,EXTERNAL,vdd
-Q 0.00503104
-S 3,EXTERNAL,q
-Q 0.00264397
-S 2,EXTERNAL,vss
-Q 0.00444349
-S 1,INTERNAL
-Q 0.00596944
-EOF
diff --git a/alliance/share/cells/sxlib/o2_x4.ap b/alliance/share/cells/sxlib/o2_x4.ap
deleted file mode 100644
index 439a0eca..00000000
--- a/alliance/share/cells/sxlib/o2_x4.ap
+++ /dev/null
@@ -1,83 +0,0 @@
-V ALLIANCE : 6
-H o2_x4,P,30/ 8/2000,100
-A 0,0,3000,5000
-R 2000,1000,ref_ref,q_10
-R 2000,4000,ref_ref,q_40
-R 2000,3500,ref_ref,q_35
-R 2000,3000,ref_ref,q_30
-R 2000,2500,ref_ref,q_25
-R 2000,2000,ref_ref,q_20
-R 2000,1500,ref_ref,q_15
-R 1500,2000,ref_ref,i0_20
-R 1500,1500,ref_ref,i0_15
-R 1500,4000,ref_ref,i0_40
-R 1500,3500,ref_ref,i0_35
-R 1500,3000,ref_ref,i0_30
-R 1500,2500,ref_ref,i0_25
-R 1500,1000,ref_ref,i0_10
-R 500,2500,ref_ref,i1_25
-R 500,2000,ref_ref,i1_20
-R 500,1500,ref_ref,i1_15
-R 500,3500,ref_ref,i1_35
-R 500,3000,ref_ref,i1_30
-S 2000,1000,2000,4000,200,q,DOWN,CALU1
-S 1500,1000,1500,4000,200,i0,DOWN,CALU1
-S 500,1500,500,3500,200,i1,DOWN,CALU1
-S 2000,950,2000,4050,200,*,UP,ALU1
-S 2700,3000,2700,4500,200,*,UP,ALU1
-S 2700,500,2700,1000,200,*,DOWN,ALU1
-S 1000,2000,2400,2000,100,*,RIGHT,POLY
-S 2400,1400,2400,2600,100,*,DOWN,POLY
-S 2700,2800,2700,4700,300,*,UP,PDIF
-S 2400,2600,2400,4900,100,*,UP,PTRANS
-S 0,300,3000,300,600,vss,RIGHT,CALU1
-S 0,4700,3000,4700,600,vdd,RIGHT,CALU1
-S 2700,300,2700,1200,300,*,UP,NDIF
-S 2400,100,2400,1400,100,*,UP,NTRANS
-S 1800,1400,1800,2600,100,*,DOWN,POLY
-S 500,1500,500,3500,100,*,UP,ALU1
-S 600,2600,800,2600,100,*,RIGHT,POLY
-S 600,1400,600,2600,100,*,DOWN,POLY
-S 1200,2500,1500,2500,300,*,RIGHT,POLY
-S 1200,1500,1500,1500,300,*,RIGHT,POLY
-S 1500,2800,1500,4700,300,*,UP,PDIF
-S 500,2800,500,4200,300,*,DOWN,PDIF
-S 300,2800,300,4200,300,*,DOWN,PDIF
-S 2100,2800,2100,4700,300,*,UP,PDIF
-S 1800,2600,1800,4900,100,*,UP,PTRANS
-S 1200,2600,1200,4400,100,*,UP,PTRANS
-S 800,2600,800,4400,100,*,UP,PTRANS
-S 600,600,600,1400,100,*,DOWN,NTRANS
-S 900,800,900,1200,300,*,UP,NDIF
-S 1200,600,1200,1400,100,*,DOWN,NTRANS
-S 300,400,300,1200,300,*,UP,NDIF
-S 1500,300,1500,1200,300,*,UP,NDIF
-S 1800,100,1800,1400,100,*,UP,NTRANS
-S 2100,300,2100,1200,300,*,UP,NDIF
-S 1500,1000,1500,4000,100,*,UP,ALU1
-S 0,3900,3000,3900,2400,*,RIGHT,NWELL
-S 950,1000,950,4000,100,*,UP,ALU1
-S 300,4000,950,4000,100,*,LEFT,ALU1
-V 2700,500,CONT_DIF_N,*
-V 2700,1000,CONT_DIF_N,*
-V 2700,3000,CONT_DIF_P,*
-V 2700,3500,CONT_DIF_P,*
-V 2700,4000,CONT_DIF_P,*
-V 2700,4500,CONT_DIF_P,*
-V 2100,4000,CONT_DIF_P,*
-V 2100,3500,CONT_DIF_P,*
-V 2100,3000,CONT_DIF_P,*
-V 500,2000,CONT_POLY,*
-V 1000,2000,CONT_POLY,*
-V 1400,2500,CONT_POLY,*
-V 1400,1500,CONT_POLY,*
-V 900,300,CONT_BODY_P,*
-V 300,4700,CONT_BODY_N,*
-V 1500,4500,CONT_DIF_P,*
-V 1500,500,CONT_DIF_N,*
-V 900,1000,CONT_DIF_N,*
-V 1500,500,CONT_DIF_N,*
-V 300,500,CONT_DIF_N,*
-V 2100,1000,CONT_DIF_N,*
-V 300,4000,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/o2_x4.sym b/alliance/share/cells/sxlib/o2_x4.sym
deleted file mode 100644
index fe8d315f..00000000
Binary files a/alliance/share/cells/sxlib/o2_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/o2_x4.vbe b/alliance/share/cells/sxlib/o2_x4.vbe
deleted file mode 100644
index e22a9361..00000000
--- a/alliance/share/cells/sxlib/o2_x4.vbe
+++ /dev/null
@@ -1,32 +0,0 @@
-ENTITY o2_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 1500;
-  CONSTANT cin_i0	 : NATURAL := 10;
-  CONSTANT cin_i1	 : NATURAL := 10;
-  CONSTANT rdown_i0_q	 : NATURAL := 810;
-  CONSTANT rdown_i1_q	 : NATURAL := 810;
-  CONSTANT rup_i0_q	 : NATURAL := 890;
-  CONSTANT rup_i1_q	 : NATURAL := 890;
-  CONSTANT tpll_i0_q	 : NATURAL := 394;
-  CONSTANT tphh_i1_q	 : NATURAL := 427;
-  CONSTANT tpll_i1_q	 : NATURAL := 464;
-  CONSTANT tphh_i0_q	 : NATURAL := 491;
-  CONSTANT transistors	 : NATURAL := 8
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END o2_x4;
-
-ARCHITECTURE behaviour_data_flow OF o2_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on o2_x4"
-  SEVERITY WARNING;
-  q <= (i0 or i1) after 1100 ps;
-END;
diff --git a/alliance/share/cells/sxlib/o2_x4.vhd b/alliance/share/cells/sxlib/o2_x4.vhd
deleted file mode 100644
index c4dbf96e..00000000
--- a/alliance/share/cells/sxlib/o2_x4.vhd
+++ /dev/null
@@ -1,20 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY o2_x4 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END o2_x4;
-
-ARCHITECTURE RTL OF o2_x4 IS
-BEGIN
-  q <= (i0 OR i1);
-END RTL;
diff --git a/alliance/share/cells/sxlib/o3_x2.al b/alliance/share/cells/sxlib/o3_x2.al
deleted file mode 100644
index d476fb88..00000000
--- a/alliance/share/cells/sxlib/o3_x2.al
+++ /dev/null
@@ -1,35 +0,0 @@
-V ALLIANCE : 6
-H o3_x2,L,30/10/99
-C i0,IN,EXTERNAL,8
-C i1,IN,EXTERNAL,9
-C i2,IN,EXTERNAL,7
-C q,OUT,EXTERNAL,1
-C vdd,IN,EXTERNAL,4
-C vss,IN,EXTERNAL,2
-T P,0.35,5.9,1,3,4,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00008
-T P,0.35,4.4,6,7,3,0,0.75,0.75,10.3,10.3,1.8,10.5,tr_00007
-T P,0.35,4.4,5,9,6,0,0.75,0.75,10.3,10.3,3,10.5,tr_00006
-T P,0.35,4.4,4,8,5,0,0.75,0.75,10.3,10.3,4.2,10.5,tr_00005
-T N,0.35,2.9,2,3,1,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00004
-T N,0.35,1.4,2,9,3,0,0.75,0.75,4.3,4.3,3.6,3,tr_00003
-T N,0.35,1.4,3,8,2,0,0.75,0.75,4.3,4.3,5.4,3,tr_00002
-T N,0.35,1.4,3,7,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00001
-S 9,EXTERNAL,i1
-Q 0.00282737
-S 8,EXTERNAL,i0
-Q 0.00282737
-S 7,EXTERNAL,i2
-Q 0.00260759
-S 6,INTERNAL
-Q 0
-S 5,INTERNAL
-Q 0
-S 4,EXTERNAL,vdd
-Q 0.00350341
-S 3,INTERNAL
-Q 0.00620074
-S 2,EXTERNAL,vss
-Q 0.00367968
-S 1,EXTERNAL,q
-Q 0.00358405
-EOF
diff --git a/alliance/share/cells/sxlib/o3_x2.ap b/alliance/share/cells/sxlib/o3_x2.ap
deleted file mode 100644
index 75d6139b..00000000
--- a/alliance/share/cells/sxlib/o3_x2.ap
+++ /dev/null
@@ -1,86 +0,0 @@
-V ALLIANCE : 6
-H o3_x2,P,30/ 8/2000,100
-A 0,0,3000,5000
-R 2500,1000,ref_ref,q_10
-R 2500,1500,ref_ref,q_15
-R 2500,2000,ref_ref,q_20
-R 2500,2500,ref_ref,q_25
-R 2500,3000,ref_ref,q_30
-R 2500,3500,ref_ref,q_35
-R 2500,4000,ref_ref,q_40
-R 1500,3500,ref_ref,i0_35
-R 1500,3000,ref_ref,i0_30
-R 1500,2500,ref_ref,i0_25
-R 1500,2000,ref_ref,i0_20
-R 1500,1500,ref_ref,i0_15
-R 1000,1500,ref_ref,i1_15
-R 1000,2000,ref_ref,i1_20
-R 1000,2500,ref_ref,i1_25
-R 1000,3000,ref_ref,i1_30
-R 1000,3500,ref_ref,i1_35
-R 500,2500,ref_ref,i2_25
-R 500,2000,ref_ref,i2_20
-R 500,1500,ref_ref,i2_15
-R 500,3500,ref_ref,i2_35
-R 500,3000,ref_ref,i2_30
-S 2500,1000,2500,4000,200,q,DOWN,CALU1
-S 1500,1500,1500,3500,200,i0,DOWN,CALU1
-S 1000,1500,1000,3500,200,i1,DOWN,CALU1
-S 500,1500,500,3500,200,i2,DOWN,CALU1
-S 0,3900,3000,3900,2400,*,LEFT,NWELL
-S 2700,300,2700,1200,300,*,DOWN,NDIF
-S 2700,2800,2700,4700,300,*,UP,PDIF
-S 2400,2600,2400,4900,100,*,UP,PTRANS
-S 2400,100,2400,1400,100,*,DOWN,NTRANS
-S 0,300,3000,300,600,vss,RIGHT,CALU1
-S 0,4700,3000,4700,600,vdd,RIGHT,CALU1
-S 1200,600,1200,1400,100,*,DOWN,NTRANS
-S 1800,600,1800,1400,100,*,DOWN,NTRANS
-S 600,600,600,1400,100,*,DOWN,NTRANS
-S 2100,2800,2100,4700,300,*,DOWN,PDIF
-S 900,400,900,1200,300,*,UP,NDIF
-S 300,800,300,1200,300,*,UP,NDIF
-S 1500,800,1500,1200,300,*,UP,NDIF
-S 2100,300,2100,1200,300,*,UP,NDIF
-S 1500,1500,1500,3500,100,*,UP,ALU1
-S 1000,1500,1000,3500,100,*,UP,ALU1
-S 500,1500,500,3500,100,*,UP,ALU1
-S 600,1400,600,2600,100,*,DOWN,POLY
-S 300,1000,2000,1000,100,*,RIGHT,ALU1
-S 2000,1000,2000,4000,100,*,UP,ALU1
-S 2400,1400,2400,2600,100,*,DOWN,POLY
-S 2000,2000,2400,2000,100,*,RIGHT,POLY
-S 300,2800,300,4200,300,*,DOWN,PDIF
-S 300,4000,2000,4000,100,*,LEFT,ALU1
-S 600,2600,600,4400,100,*,UP,PTRANS
-S 1000,2600,1000,4400,100,*,UP,PTRANS
-S 1400,2600,1400,4400,100,*,UP,PTRANS
-S 1000,1400,1000,2600,100,*,DOWN,POLY
-S 1000,1400,1200,1400,100,*,RIGHT,POLY
-S 1600,1400,1800,1400,100,*,LEFT,POLY
-S 1600,1400,1600,2600,100,*,UP,POLY
-S 1800,2800,1800,4700,500,*,DOWN,PDIF
-S 2500,950,2500,4050,200,*,DOWN,ALU1
-S 2500,4000,2700,4000,200,*,RIGHT,ALU1
-S 2500,3500,2700,3500,200,*,LEFT,ALU1
-S 2500,3000,2700,3000,200,*,LEFT,ALU1
-S 2500,1000,2700,1000,200,*,LEFT,ALU1
-V 2700,1000,CONT_DIF_N,*
-V 2700,3000,CONT_DIF_P,*
-V 2700,3500,CONT_DIF_P,*
-V 2700,4000,CONT_DIF_P,*
-V 300,4700,CONT_BODY_N,*
-V 2100,4500,CONT_DIF_P,*
-V 1500,1000,CONT_DIF_N,*
-V 300,1000,CONT_DIF_N,*
-V 900,500,CONT_DIF_N,*
-V 300,300,CONT_BODY_P,*
-V 1500,300,CONT_BODY_P,*
-V 2100,500,CONT_DIF_N,*
-V 500,1500,CONT_POLY,*
-V 1000,2000,CONT_POLY,*
-V 2000,2000,CONT_POLY,*
-V 300,4000,CONT_DIF_P,*
-V 1500,2500,CONT_POLY,*
-V 1700,4500,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/o3_x2.sym b/alliance/share/cells/sxlib/o3_x2.sym
deleted file mode 100644
index 10ad4b42..00000000
Binary files a/alliance/share/cells/sxlib/o3_x2.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/o3_x2.vbe b/alliance/share/cells/sxlib/o3_x2.vbe
deleted file mode 100644
index 5aad7aba..00000000
--- a/alliance/share/cells/sxlib/o3_x2.vbe
+++ /dev/null
@@ -1,38 +0,0 @@
-ENTITY o3_x2 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 1500;
-  CONSTANT cin_i0	 : NATURAL := 10;
-  CONSTANT cin_i1	 : NATURAL := 10;
-  CONSTANT cin_i2	 : NATURAL := 9;
-  CONSTANT rdown_i0_q	 : NATURAL := 1620;
-  CONSTANT rdown_i1_q	 : NATURAL := 1620;
-  CONSTANT rdown_i2_q	 : NATURAL := 1620;
-  CONSTANT rup_i0_q	 : NATURAL := 1790;
-  CONSTANT rup_i1_q	 : NATURAL := 1790;
-  CONSTANT rup_i2_q	 : NATURAL := 1790;
-  CONSTANT tphh_i2_q	 : NATURAL := 360;
-  CONSTANT tpll_i0_q	 : NATURAL := 407;
-  CONSTANT tphh_i1_q	 : NATURAL := 430;
-  CONSTANT tpll_i1_q	 : NATURAL := 482;
-  CONSTANT tphh_i0_q	 : NATURAL := 494;
-  CONSTANT tpll_i2_q	 : NATURAL := 506;
-  CONSTANT transistors	 : NATURAL := 8
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END o3_x2;
-
-ARCHITECTURE behaviour_data_flow OF o3_x2 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on o3_x2"
-  SEVERITY WARNING;
-  q <= ((i0 or i1) or i2) after 1100 ps;
-END;
diff --git a/alliance/share/cells/sxlib/o3_x2.vhd b/alliance/share/cells/sxlib/o3_x2.vhd
deleted file mode 100644
index 020e5378..00000000
--- a/alliance/share/cells/sxlib/o3_x2.vhd
+++ /dev/null
@@ -1,21 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY o3_x2 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END o3_x2;
-
-ARCHITECTURE RTL OF o3_x2 IS
-BEGIN
-  q <= ((i0 OR i1) OR i2);
-END RTL;
diff --git a/alliance/share/cells/sxlib/o3_x4.al b/alliance/share/cells/sxlib/o3_x4.al
deleted file mode 100644
index c0ae14bd..00000000
--- a/alliance/share/cells/sxlib/o3_x4.al
+++ /dev/null
@@ -1,37 +0,0 @@
-V ALLIANCE : 6
-H o3_x4,L,30/10/99
-C i0,IN,EXTERNAL,7
-C i1,IN,EXTERNAL,9
-C i2,IN,EXTERNAL,8
-C q,OUT,EXTERNAL,1
-C vdd,IN,EXTERNAL,5
-C vss,IN,EXTERNAL,2
-T P,0.35,5.9,1,3,5,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00010
-T P,0.35,5.9,1,3,5,0,0.75,0.75,13.3,13.3,6.9,11.25,tr_00009
-T P,0.35,4.4,5,7,4,0,0.75,0.75,10.3,10.3,4.2,10.5,tr_00008
-T P,0.35,4.4,4,9,6,0,0.75,0.75,10.3,10.3,3,10.5,tr_00007
-T P,0.35,4.4,6,8,3,0,0.75,0.75,10.3,10.3,1.8,10.5,tr_00006
-T N,0.35,2.9,1,3,2,0,0.75,0.75,7.3,7.3,8.7,2.25,tr_00005
-T N,0.35,2.9,2,3,1,0,0.75,0.75,7.3,7.3,6.9,2.25,tr_00004
-T N,0.35,1.4,3,8,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00003
-T N,0.35,1.4,3,7,2,0,0.75,0.75,4.3,4.3,5.4,3,tr_00002
-T N,0.35,1.4,2,9,3,0,0.75,0.75,4.3,4.3,3.6,3,tr_00001
-S 9,EXTERNAL,i1
-Q 0.00282737
-S 8,EXTERNAL,i2
-Q 0.00260759
-S 7,EXTERNAL,i0
-Q 0.00282737
-S 6,INTERNAL
-Q 0
-S 5,EXTERNAL,vdd
-Q 0.00537252
-S 4,INTERNAL
-Q 0
-S 3,INTERNAL
-Q 0.00773401
-S 2,EXTERNAL,vss
-Q 0.00519625
-S 1,EXTERNAL,q
-Q 0.00258522
-EOF
diff --git a/alliance/share/cells/sxlib/o3_x4.ap b/alliance/share/cells/sxlib/o3_x4.ap
deleted file mode 100644
index f0ab0df9..00000000
--- a/alliance/share/cells/sxlib/o3_x4.ap
+++ /dev/null
@@ -1,94 +0,0 @@
-V ALLIANCE : 6
-H o3_x4,P,30/ 8/2000,100
-A 0,0,3500,5000
-R 2500,1000,ref_ref,q_10
-R 2500,1500,ref_ref,q_15
-R 2500,2000,ref_ref,q_20
-R 2500,2500,ref_ref,q_25
-R 2500,3000,ref_ref,q_30
-R 2500,3500,ref_ref,q_35
-R 2500,4000,ref_ref,q_40
-R 1500,3500,ref_ref,i0_35
-R 1500,3000,ref_ref,i0_30
-R 1500,2500,ref_ref,i0_25
-R 1500,2000,ref_ref,i0_20
-R 1500,1500,ref_ref,i0_15
-R 1000,1500,ref_ref,i1_15
-R 1000,2000,ref_ref,i1_20
-R 1000,2500,ref_ref,i1_25
-R 1000,3000,ref_ref,i1_30
-R 1000,3500,ref_ref,i1_35
-R 500,2500,ref_ref,i2_25
-R 500,2000,ref_ref,i2_20
-R 500,1500,ref_ref,i2_15
-R 500,3500,ref_ref,i2_35
-R 500,3000,ref_ref,i2_30
-S 2500,1000,2500,4000,200,*,DOWN,ALU1
-S 0,3900,3500,3900,2400,*,RIGHT,NWELL
-S 1200,600,1200,1400,100,*,DOWN,NTRANS
-S 1800,600,1800,1400,100,*,DOWN,NTRANS
-S 600,600,600,1400,100,*,DOWN,NTRANS
-S 2100,2800,2100,4700,300,*,DOWN,PDIF
-S 900,400,900,1200,300,*,UP,NDIF
-S 300,800,300,1200,300,*,UP,NDIF
-S 1500,800,1500,1200,300,*,UP,NDIF
-S 2100,300,2100,1200,300,*,UP,NDIF
-S 1500,1500,1500,3500,100,*,UP,ALU1
-S 1000,1500,1000,3500,100,*,UP,ALU1
-S 500,1500,500,3500,100,*,UP,ALU1
-S 600,1400,600,2600,100,*,DOWN,POLY
-S 300,1000,2000,1000,100,*,RIGHT,ALU1
-S 2000,1000,2000,4000,100,*,UP,ALU1
-S 300,2800,300,4200,300,*,DOWN,PDIF
-S 300,4000,2000,4000,100,*,LEFT,ALU1
-S 600,2600,600,4400,100,*,UP,PTRANS
-S 1000,2600,1000,4400,100,*,UP,PTRANS
-S 1400,2600,1400,4400,100,*,UP,PTRANS
-S 1000,1400,1000,2600,100,*,DOWN,POLY
-S 1000,1400,1200,1400,100,*,RIGHT,POLY
-S 1600,1400,1800,1400,100,*,LEFT,POLY
-S 1600,1400,1600,2600,100,*,UP,POLY
-S 1800,2800,1800,4700,500,*,DOWN,PDIF
-S 0,4700,3500,4700,600,vdd,RIGHT,CALU1
-S 2300,100,2300,1400,100,*,DOWN,NTRANS
-S 2300,1400,2300,2600,100,*,DOWN,POLY
-S 2300,2600,2300,4900,100,*,UP,PTRANS
-S 2600,300,2600,1200,300,*,DOWN,NDIF
-S 2600,2800,2600,4700,300,*,UP,PDIF
-S 2900,100,2900,1400,100,*,DOWN,NTRANS
-S 0,300,3500,300,600,vss,RIGHT,CALU1
-S 3200,300,3200,1200,300,*,DOWN,NDIF
-S 2900,2600,2900,4900,100,*,DOWN,PTRANS
-S 2900,1400,2900,2600,100,*,DOWN,POLY
-S 1900,2000,2900,2000,300,*,RIGHT,POLY
-S 3200,2800,3200,4700,300,*,UP,PDIF
-S 3200,3000,3200,4500,200,*,UP,ALU1
-S 3200,500,3200,1700,200,*,UP,ALU1
-S 2500,1000,2500,4000,200,q,DOWN,CALU1
-S 1500,1500,1500,3500,200,i0,DOWN,CALU1
-S 1000,1500,1000,3500,200,i1,DOWN,CALU1
-S 500,1500,500,3500,200,i2,DOWN,CALU1
-V 300,4700,CONT_BODY_N,*
-V 1500,1000,CONT_DIF_N,*
-V 300,1000,CONT_DIF_N,*
-V 900,500,CONT_DIF_N,*
-V 300,300,CONT_BODY_P,*
-V 500,1500,CONT_POLY,*
-V 1000,2000,CONT_POLY,*
-V 2000,2000,CONT_POLY,*
-V 300,4000,CONT_DIF_P,*
-V 1500,2500,CONT_POLY,*
-V 2000,300,CONT_DIF_N,*
-V 2000,4500,CONT_DIF_P,*
-V 2600,1000,CONT_DIF_N,*
-V 2600,3000,CONT_DIF_P,*
-V 2600,3500,CONT_DIF_P,*
-V 2600,4000,CONT_DIF_P,*
-V 3200,500,CONT_DIF_N,*
-V 3200,4500,CONT_DIF_P,*
-V 3200,4000,CONT_DIF_P,*
-V 3200,3500,CONT_DIF_P,*
-V 3200,3000,CONT_DIF_P,*
-V 3200,1000,CONT_DIF_N,*
-V 3200,1700,CONT_BODY_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/o3_x4.sym b/alliance/share/cells/sxlib/o3_x4.sym
deleted file mode 100644
index 6453b559..00000000
Binary files a/alliance/share/cells/sxlib/o3_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/o3_x4.vbe b/alliance/share/cells/sxlib/o3_x4.vbe
deleted file mode 100644
index 1e7ea94f..00000000
--- a/alliance/share/cells/sxlib/o3_x4.vbe
+++ /dev/null
@@ -1,38 +0,0 @@
-ENTITY o3_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 1750;
-  CONSTANT cin_i0	 : NATURAL := 10;
-  CONSTANT cin_i1	 : NATURAL := 10;
-  CONSTANT cin_i2	 : NATURAL := 9;
-  CONSTANT rdown_i0_q	 : NATURAL := 810;
-  CONSTANT rdown_i1_q	 : NATURAL := 810;
-  CONSTANT rdown_i2_q	 : NATURAL := 810;
-  CONSTANT rup_i0_q	 : NATURAL := 890;
-  CONSTANT rup_i1_q	 : NATURAL := 890;
-  CONSTANT rup_i2_q	 : NATURAL := 890;
-  CONSTANT tphh_i2_q	 : NATURAL := 447;
-  CONSTANT tpll_i0_q	 : NATURAL := 501;
-  CONSTANT tphh_i1_q	 : NATURAL := 510;
-  CONSTANT tphh_i0_q	 : NATURAL := 569;
-  CONSTANT tpll_i1_q	 : NATURAL := 585;
-  CONSTANT tpll_i2_q	 : NATURAL := 622;
-  CONSTANT transistors	 : NATURAL := 10
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END o3_x4;
-
-ARCHITECTURE behaviour_data_flow OF o3_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on o3_x4"
-  SEVERITY WARNING;
-  q <= ((i0 or i1) or i2) after 1200 ps;
-END;
diff --git a/alliance/share/cells/sxlib/o3_x4.vhd b/alliance/share/cells/sxlib/o3_x4.vhd
deleted file mode 100644
index 76e4c9ba..00000000
--- a/alliance/share/cells/sxlib/o3_x4.vhd
+++ /dev/null
@@ -1,21 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY o3_x4 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END o3_x4;
-
-ARCHITECTURE RTL OF o3_x4 IS
-BEGIN
-  q <= ((i0 OR i1) OR i2);
-END RTL;
diff --git a/alliance/share/cells/sxlib/o4_x2.al b/alliance/share/cells/sxlib/o4_x2.al
deleted file mode 100644
index 7be3125b..00000000
--- a/alliance/share/cells/sxlib/o4_x2.al
+++ /dev/null
@@ -1,42 +0,0 @@
-V ALLIANCE : 6
-H o4_x2,L,30/10/99
-C i0,IN,EXTERNAL,7
-C i1,IN,EXTERNAL,8
-C i2,IN,EXTERNAL,9
-C i3,IN,EXTERNAL,10
-C q,OUT,EXTERNAL,11
-C vdd,IN,EXTERNAL,4
-C vss,IN,EXTERNAL,1
-T P,0.35,4.4,3,10,2,0,0.75,0.75,10.3,10.3,1.8,10.5,tr_00010
-T P,0.35,4.4,6,8,3,0,0.75,0.75,10.3,10.3,3,10.5,tr_00009
-T P,0.35,4.4,5,7,6,0,0.75,0.75,10.3,10.3,4.2,10.5,tr_00008
-T P,0.35,4.4,4,9,5,0,0.75,0.75,10.3,10.3,5.4,10.5,tr_00007
-T P,0.35,5.9,4,2,11,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00006
-T N,0.35,1.4,2,9,1,0,0.75,0.75,4.3,4.3,7.2,3,tr_00005
-T N,0.35,1.4,1,10,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00004
-T N,0.35,1.4,1,7,2,0,0.75,0.75,4.3,4.3,5.4,3,tr_00003
-T N,0.35,1.4,2,8,1,0,0.75,0.75,4.3,4.3,3.6,3,tr_00002
-T N,0.35,2.9,11,2,1,0,0.75,0.75,7.3,7.3,8.7,2.25,tr_00001
-S 11,EXTERNAL,q
-Q 0.00258522
-S 10,EXTERNAL,i3
-Q 0.00260759
-S 9,EXTERNAL,i2
-Q 0.00318597
-S 8,EXTERNAL,i1
-Q 0.00282737
-S 7,EXTERNAL,i0
-Q 0.00319753
-S 6,INTERNAL
-Q 0
-S 5,INTERNAL
-Q 0
-S 4,EXTERNAL,vdd
-Q 0.00384489
-S 3,INTERNAL
-Q 0
-S 2,INTERNAL
-Q 0.0066641
-S 1,EXTERNAL,vss
-Q 0.00419742
-EOF
diff --git a/alliance/share/cells/sxlib/o4_x2.ap b/alliance/share/cells/sxlib/o4_x2.ap
deleted file mode 100644
index 25229dda..00000000
--- a/alliance/share/cells/sxlib/o4_x2.ap
+++ /dev/null
@@ -1,103 +0,0 @@
-V ALLIANCE : 6
-H o4_x2,P,30/ 8/2000,100
-A 0,0,3500,5000
-R 500,1500,ref_ref,i3_15
-R 500,3500,ref_ref,i3_35
-R 500,3000,ref_ref,i3_30
-R 500,2500,ref_ref,i3_25
-R 500,2000,ref_ref,i3_20
-R 3000,3500,ref_ref,q_35
-R 3000,4000,ref_ref,q_40
-R 3000,1500,ref_ref,q_15
-R 3000,1000,ref_ref,q_10
-R 3000,2000,ref_ref,q_20
-R 3000,2500,ref_ref,q_25
-R 3000,3000,ref_ref,q_30
-R 2000,3500,ref_ref,i2_35
-R 2000,3000,ref_ref,i2_30
-R 2000,2500,ref_ref,i2_25
-R 2000,2000,ref_ref,i2_20
-R 2000,1500,ref_ref,i2_15
-R 1500,3500,ref_ref,i0_35
-R 1500,3000,ref_ref,i0_30
-R 1500,2500,ref_ref,i0_25
-R 1500,2000,ref_ref,i0_20
-R 1500,1500,ref_ref,i0_15
-R 1000,1500,ref_ref,i1_15
-R 1000,2000,ref_ref,i1_20
-R 1000,2500,ref_ref,i1_25
-R 1000,3000,ref_ref,i1_30
-R 1000,3500,ref_ref,i1_35
-S 3000,1000,3200,1000,200,*,LEFT,ALU1
-S 3000,3000,3200,3000,200,*,LEFT,ALU1
-S 3000,3500,3200,3500,200,*,LEFT,ALU1
-S 3000,4000,3200,4000,200,*,LEFT,ALU1
-S 3000,1000,3000,4000,200,*,DOWN,ALU1
-S 900,1000,2550,1000,100,*,LEFT,ALU1
-S 300,4000,2550,4000,100,*,RIGHT,ALU1
-S 2550,1000,2550,4000,100,*,DOWN,ALU1
-S 2100,1400,2100,2600,100,*,DOWN,POLY
-S 1800,2600,2100,2600,100,*,RIGHT,POLY
-S 1600,1400,1800,1400,100,*,RIGHT,POLY
-S 1600,1400,1600,2100,100,*,DOWN,POLY
-S 1400,1900,1400,2600,100,*,DOWN,POLY
-S 1000,1400,1200,1400,100,*,RIGHT,POLY
-S 1000,1400,1000,2600,100,*,DOWN,POLY
-S 2700,300,2700,1200,300,*,DOWN,NDIF
-S 2900,100,2900,1400,100,*,UP,NTRANS
-S 3200,300,3200,1200,300,*,DOWN,NDIF
-S 2400,2000,2900,2000,300,*,RIGHT,POLY
-S 2900,1400,2900,2600,100,*,DOWN,POLY
-S 3200,2800,3200,4700,300,*,UP,PDIF
-S 2900,2600,2900,4900,100,*,DOWN,PTRANS
-S 2200,2800,2200,4700,500,*,DOWN,PDIF
-S 1800,2600,1800,4400,100,*,UP,PTRANS
-S 2100,1400,2400,1400,100,*,RIGHT,POLY
-S 1400,2600,1400,4400,100,*,UP,PTRANS
-S 1000,2600,1000,4400,100,*,UP,PTRANS
-S 600,2600,600,4400,100,*,UP,PTRANS
-S 300,2800,300,4200,300,*,DOWN,PDIF
-S 600,1400,600,2600,100,*,DOWN,POLY
-S 500,1500,500,3500,100,*,UP,ALU1
-S 1400,2000,1400,2100,100,*,DOWN,POLY
-S 2000,1500,2000,3500,100,*,UP,ALU1
-S 1500,1500,1500,3500,100,*,UP,ALU1
-S 1000,1500,1000,3500,100,*,UP,ALU1
-S 0,4700,3500,4700,600,vdd,RIGHT,CALU1
-S 0,300,3500,300,600,vss,RIGHT,CALU1
-S 300,400,300,1200,300,*,UP,NDIF
-S 1500,400,1500,1200,300,*,UP,NDIF
-S 1200,600,1200,1400,100,*,DOWN,NTRANS
-S 900,800,900,1200,300,*,UP,NDIF
-S 2100,800,2100,1200,300,*,UP,NDIF
-S 1800,600,1800,1400,100,*,DOWN,NTRANS
-S 600,600,600,1400,100,*,DOWN,NTRANS
-S 2500,2800,2500,4700,300,*,DOWN,PDIF
-S 2400,600,2400,1400,100,*,DOWN,NTRANS
-S 0,3900,3500,3900,2400,*,RIGHT,NWELL
-S 500,1500,500,3500,200,i3,DOWN,CALU1
-S 3000,1000,3000,4000,200,q,DOWN,CALU1
-S 2000,1500,2000,3500,200,i2,DOWN,CALU1
-S 1500,1500,1500,3500,200,i0,DOWN,CALU1
-S 1000,1500,1000,3500,200,i1,DOWN,CALU1
-V 2200,4500,CONT_DIF_P,*
-V 2600,4500,CONT_DIF_P,*
-V 2600,300,CONT_DIF_N,*
-V 3200,3500,CONT_DIF_P,*
-V 3200,3000,CONT_DIF_P,*
-V 3200,4000,CONT_DIF_P,*
-V 3200,1000,CONT_DIF_N,*
-V 300,4000,CONT_DIF_P,*
-V 2000,2000,CONT_POLY,*
-V 1000,2000,CONT_POLY,*
-V 2500,2000,CONT_POLY,*
-V 500,2000,CONT_POLY,*
-V 1500,2000,CONT_POLY,*
-V 900,300,CONT_BODY_P,*
-V 300,500,CONT_DIF_N,*
-V 1500,500,CONT_DIF_N,*
-V 300,4700,CONT_BODY_N,*
-V 900,1000,CONT_DIF_N,*
-V 2100,1000,CONT_DIF_N,*
-V 1500,500,CONT_DIF_N,*
-EOF
diff --git a/alliance/share/cells/sxlib/o4_x2.sym b/alliance/share/cells/sxlib/o4_x2.sym
deleted file mode 100644
index 4e5ebc9a..00000000
Binary files a/alliance/share/cells/sxlib/o4_x2.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/o4_x2.vbe b/alliance/share/cells/sxlib/o4_x2.vbe
deleted file mode 100644
index 09652e62..00000000
--- a/alliance/share/cells/sxlib/o4_x2.vbe
+++ /dev/null
@@ -1,44 +0,0 @@
-ENTITY o4_x2 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 1750;
-  CONSTANT cin_i0	 : NATURAL := 10;
-  CONSTANT cin_i1	 : NATURAL := 10;
-  CONSTANT cin_i2	 : NATURAL := 10;
-  CONSTANT cin_i3	 : NATURAL := 9;
-  CONSTANT rdown_i0_q	 : NATURAL := 1620;
-  CONSTANT rdown_i1_q	 : NATURAL := 1620;
-  CONSTANT rdown_i2_q	 : NATURAL := 1620;
-  CONSTANT rdown_i3_q	 : NATURAL := 1620;
-  CONSTANT rup_i0_q	 : NATURAL := 1790;
-  CONSTANT rup_i1_q	 : NATURAL := 1790;
-  CONSTANT rup_i2_q	 : NATURAL := 1790;
-  CONSTANT rup_i3_q	 : NATURAL := 1790;
-  CONSTANT tphh_i3_q	 : NATURAL := 378;
-  CONSTANT tphh_i1_q	 : NATURAL := 446;
-  CONSTANT tphh_i0_q	 : NATURAL := 508;
-  CONSTANT tpll_i2_q	 : NATURAL := 531;
-  CONSTANT tphh_i2_q	 : NATURAL := 567;
-  CONSTANT tpll_i0_q	 : NATURAL := 601;
-  CONSTANT tpll_i3_q	 : NATURAL := 626;
-  CONSTANT tpll_i1_q	 : NATURAL := 631;
-  CONSTANT transistors	 : NATURAL := 10
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  i3	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END o4_x2;
-
-ARCHITECTURE behaviour_data_flow OF o4_x2 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on o4_x2"
-  SEVERITY WARNING;
-  q <= (((i0 or i1) or i2) or i3) after 1200 ps;
-END;
diff --git a/alliance/share/cells/sxlib/o4_x2.vhd b/alliance/share/cells/sxlib/o4_x2.vhd
deleted file mode 100644
index b7b15c9d..00000000
--- a/alliance/share/cells/sxlib/o4_x2.vhd
+++ /dev/null
@@ -1,22 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY o4_x2 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  i3	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END o4_x2;
-
-ARCHITECTURE RTL OF o4_x2 IS
-BEGIN
-  q <= (((i0 OR i1) OR i2) OR i3);
-END RTL;
diff --git a/alliance/share/cells/sxlib/o4_x4.al b/alliance/share/cells/sxlib/o4_x4.al
deleted file mode 100644
index 9b33d0a1..00000000
--- a/alliance/share/cells/sxlib/o4_x4.al
+++ /dev/null
@@ -1,44 +0,0 @@
-V ALLIANCE : 6
-H o4_x4,L,30/10/99
-C i0,IN,EXTERNAL,8
-C i1,IN,EXTERNAL,10
-C i2,IN,EXTERNAL,9
-C i3,IN,EXTERNAL,7
-C q,OUT,EXTERNAL,11
-C vdd,IN,EXTERNAL,5
-C vss,IN,EXTERNAL,2
-T P,0.35,5.9,5,7,6,0,0.75,0.75,13.3,13.3,6.6,11.25,tr_00012
-T P,0.35,5.9,3,8,4,0,0.75,0.75,13.3,13.3,4.2,11.25,tr_00011
-T P,0.35,5.9,4,10,1,0,0.75,0.75,13.3,13.3,3,11.25,tr_00010
-T P,0.35,5.9,6,9,3,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00009
-T P,0.35,5.9,5,1,11,0,0.75,0.75,13.3,13.3,8.4,11.25,tr_00008
-T P,0.35,5.9,11,1,5,0,0.75,0.75,13.3,13.3,10.2,11.25,tr_00007
-T N,0.35,1.4,1,7,2,0,0.75,0.75,4.3,4.3,7.2,3,tr_00006
-T N,0.35,1.4,2,10,1,0,0.75,0.75,4.3,4.3,1.8,3,tr_00005
-T N,0.35,1.4,2,9,1,0,0.75,0.75,4.3,4.3,5.4,3,tr_00004
-T N,0.35,1.4,1,8,2,0,0.75,0.75,4.3,4.3,3.6,3,tr_00003
-T N,0.35,2.9,11,1,2,0,0.75,0.75,7.3,7.3,8.4,2.25,tr_00002
-T N,0.35,2.9,2,1,11,0,0.75,0.75,7.3,7.3,10.2,2.25,tr_00001
-S 11,EXTERNAL,q
-Q 0.00343717
-S 10,EXTERNAL,i1
-Q 0.00317863
-S 9,EXTERNAL,i2
-Q 0.00332901
-S 8,EXTERNAL,i0
-Q 0.0032596
-S 7,EXTERNAL,i3
-Q 0.00282737
-S 6,INTERNAL
-Q 0
-S 5,EXTERNAL,vdd
-Q 0.00524395
-S 4,INTERNAL
-Q 0
-S 3,INTERNAL
-Q 0
-S 2,EXTERNAL,vss
-Q 0.00471516
-S 1,INTERNAL
-Q 0.00811076
-EOF
diff --git a/alliance/share/cells/sxlib/o4_x4.ap b/alliance/share/cells/sxlib/o4_x4.ap
deleted file mode 100644
index dc223427..00000000
--- a/alliance/share/cells/sxlib/o4_x4.ap
+++ /dev/null
@@ -1,122 +0,0 @@
-V ALLIANCE : 6
-H o4_x4,P,30/ 8/2000,100
-A 0,0,4000,5000
-R 2500,2000,ref_ref,i3_20
-R 2500,2500,ref_ref,i3_25
-R 2500,3000,ref_ref,i3_30
-R 2500,3500,ref_ref,i3_35
-R 2500,4000,ref_ref,i3_40
-R 1000,4000,ref_ref,i1_40
-R 1000,3500,ref_ref,i1_35
-R 1000,3000,ref_ref,i1_30
-R 1000,2500,ref_ref,i1_25
-R 1000,2000,ref_ref,i1_20
-R 1000,1500,ref_ref,i1_15
-R 1500,1500,ref_ref,i0_15
-R 1500,2000,ref_ref,i0_20
-R 1500,2500,ref_ref,i0_25
-R 1500,3000,ref_ref,i0_30
-R 1500,3500,ref_ref,i0_35
-R 1500,4000,ref_ref,i0_40
-R 2000,1500,ref_ref,i2_15
-R 2000,2000,ref_ref,i2_20
-R 2000,2500,ref_ref,i2_25
-R 2000,3000,ref_ref,i2_30
-R 2000,3500,ref_ref,i2_35
-R 2000,4000,ref_ref,i2_40
-R 3500,2500,ref_ref,q_25
-R 3500,2000,ref_ref,q_20
-R 3500,1500,ref_ref,q_15
-R 3500,1000,ref_ref,q_10
-R 3000,4000,ref_ref,q_40
-R 3000,3500,ref_ref,q_35
-R 3000,3000,ref_ref,q_30
-S 2550,300,2550,1200,200,*,UP,NDIF
-S 2300,1400,2400,1400,100,*,RIGHT,POLY
-S 1700,1400,1900,1400,100,*,RIGHT,POLY
-S 2300,600,2300,1400,100,*,DOWN,NTRANS
-S 2000,1000,2500,1000,200,*,RIGHT,ALU1
-S 1700,600,1700,1400,100,*,DOWN,NTRANS
-S 1450,250,1450,1200,200,*,UP,NDIF
-S 0,3900,4000,3900,2400,*,RIGHT,NWELL
-S 500,1000,500,3000,100,*,DOWN,ALU1
-S 2400,1400,2400,2600,100,*,DOWN,POLY
-S 2200,2600,2400,2600,100,*,RIGHT,POLY
-S 2500,2800,2500,4700,300,*,DOWN,PDIF
-S 2200,2600,2200,4900,100,*,UP,PTRANS
-S 600,600,600,1400,100,*,DOWN,NTRANS
-S 2100,800,2100,1200,300,*,UP,NDIF
-S 900,800,900,1200,300,*,UP,NDIF
-S 1200,600,1200,1400,100,*,DOWN,NTRANS
-S 1400,2600,1400,4900,100,*,UP,PTRANS
-S 700,2800,700,4200,300,*,DOWN,PDIF
-S 1000,2600,1000,4900,100,*,UP,PTRANS
-S 300,400,300,1200,300,*,UP,NDIF
-S 1000,1500,1000,4000,100,*,UP,ALU1
-S 500,2800,500,4200,300,*,DOWN,PDIF
-S 1500,1500,1500,4000,100,*,UP,ALU1
-S 2000,1500,2000,4000,100,*,UP,ALU1
-S 1800,2600,1800,4900,100,*,UP,PTRANS
-S 600,2400,1100,2400,100,*,LEFT,POLY
-S 600,1400,600,2400,100,*,DOWN,POLY
-S 1400,2000,1400,2600,100,*,DOWN,POLY
-S 1800,2600,1900,2600,100,*,RIGHT,POLY
-S 1900,1400,1900,2600,100,*,DOWN,POLY
-S 1200,1900,1600,1900,100,*,LEFT,POLY
-S 1200,1400,1200,1900,100,*,DOWN,POLY
-S 2800,2600,2800,4900,100,*,DOWN,PTRANS
-S 3400,2600,3400,4900,100,*,DOWN,PTRANS
-S 3700,2800,3700,4700,300,*,UP,PDIF
-S 3100,2800,3100,4700,300,*,UP,PDIF
-S 3700,300,3700,1200,300,*,DOWN,NDIF
-S 2800,100,2800,1400,100,*,UP,NTRANS
-S 3400,100,3400,1400,100,*,UP,NTRANS
-S 0,300,4000,300,600,vss,RIGHT,CALU1
-S 3100,300,3100,1200,300,*,DOWN,NDIF
-S 2500,1500,3000,1500,100,*,LEFT,ALU1
-S 2500,1000,2500,1500,100,*,DOWN,ALU1
-S 500,1000,2500,1000,100,*,LEFT,ALU1
-S 2500,2000,2500,4000,100,*,UP,ALU1
-S 0,4700,4000,4700,600,vdd,RIGHT,CALU1
-S 2800,2600,3400,2600,100,*,RIGHT,POLY
-S 2800,1400,3400,1400,100,*,RIGHT,POLY
-S 3000,1500,3000,2500,100,*,DOWN,ALU1
-S 3100,1000,3500,1000,200,*,RIGHT,ALU1
-S 500,3000,500,4000,100,*,UP,ALU1
-S 3500,1000,3500,3050,200,*,DOWN,ALU1
-S 3100,3000,3500,3000,200,*,LEFT,ALU1
-S 3700,3500,3700,4500,200,*,UP,ALU1
-S 500,1000,900,1000,200,*,LEFT,ALU1
-S 2500,2000,2500,4000,200,i3,DOWN,CALU1
-S 1000,1500,1000,4000,200,i1,DOWN,CALU1
-S 1500,1500,1500,4000,200,i0,DOWN,CALU1
-S 2000,1500,2000,4000,200,i2,DOWN,CALU1
-S 3000,3000,3000,4000,200,*,UP,ALU1
-S 3500,1000,3500,3000,200,q,DOWN,CALU1
-S 3000,3000,3000,4000,200,q,DOWN,CALU1
-V 2000,2000,CONT_POLY,*
-V 2000,1000,CONT_DIF_N,*
-V 1500,300,CONT_DIF_N,*
-V 500,3000,CONT_DIF_P,*
-V 2500,2000,CONT_POLY,*
-V 900,1000,CONT_DIF_N,*
-V 300,4700,CONT_BODY_N,*
-V 300,500,CONT_DIF_N,*
-V 900,300,CONT_BODY_P,*
-V 1000,2500,CONT_POLY,*
-V 1500,2000,CONT_POLY,*
-V 3700,4500,CONT_DIF_P,*
-V 3700,500,CONT_DIF_N,*
-V 3000,1500,CONT_POLY,*
-V 2500,4500,CONT_DIF_P,*
-V 2500,300,CONT_DIF_N,*
-V 3000,2500,CONT_POLY,*
-V 3100,1000,CONT_DIF_N,*
-V 3100,3000,CONT_DIF_P,*
-V 3100,3500,CONT_DIF_P,*
-V 3100,4000,CONT_DIF_P,*
-V 500,3500,CONT_DIF_P,*
-V 500,4000,CONT_DIF_P,*
-V 3700,4000,CONT_DIF_P,*
-V 3700,3500,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/o4_x4.sym b/alliance/share/cells/sxlib/o4_x4.sym
deleted file mode 100644
index 390104b3..00000000
Binary files a/alliance/share/cells/sxlib/o4_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/o4_x4.vbe b/alliance/share/cells/sxlib/o4_x4.vbe
deleted file mode 100644
index bc869a8f..00000000
--- a/alliance/share/cells/sxlib/o4_x4.vbe
+++ /dev/null
@@ -1,44 +0,0 @@
-ENTITY o4_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 2000;
-  CONSTANT cin_i0	 : NATURAL := 12;
-  CONSTANT cin_i1	 : NATURAL := 12;
-  CONSTANT cin_i2	 : NATURAL := 12;
-  CONSTANT cin_i3	 : NATURAL := 12;
-  CONSTANT rdown_i0_q	 : NATURAL := 810;
-  CONSTANT rdown_i1_q	 : NATURAL := 810;
-  CONSTANT rdown_i2_q	 : NATURAL := 810;
-  CONSTANT rdown_i3_q	 : NATURAL := 810;
-  CONSTANT rup_i0_q	 : NATURAL := 890;
-  CONSTANT rup_i1_q	 : NATURAL := 890;
-  CONSTANT rup_i2_q	 : NATURAL := 890;
-  CONSTANT rup_i3_q	 : NATURAL := 890;
-  CONSTANT tphh_i1_q	 : NATURAL := 492;
-  CONSTANT tpll_i3_q	 : NATURAL := 536;
-  CONSTANT tphh_i0_q	 : NATURAL := 574;
-  CONSTANT tpll_i2_q	 : NATURAL := 611;
-  CONSTANT tpll_i0_q	 : NATURAL := 638;
-  CONSTANT tphh_i2_q	 : NATURAL := 649;
-  CONSTANT tpll_i1_q	 : NATURAL := 650;
-  CONSTANT tphh_i3_q	 : NATURAL := 721;
-  CONSTANT transistors	 : NATURAL := 12
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  i3	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END o4_x4;
-
-ARCHITECTURE behaviour_data_flow OF o4_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on o4_x4"
-  SEVERITY WARNING;
-  q <= (((i0 or i1) or i2) or i3) after 1300 ps;
-END;
diff --git a/alliance/share/cells/sxlib/o4_x4.vhd b/alliance/share/cells/sxlib/o4_x4.vhd
deleted file mode 100644
index 240d2176..00000000
--- a/alliance/share/cells/sxlib/o4_x4.vhd
+++ /dev/null
@@ -1,22 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY o4_x4 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  i3	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END o4_x4;
-
-ARCHITECTURE RTL OF o4_x4 IS
-BEGIN
-  q <= (((i0 OR i1) OR i2) OR i3);
-END RTL;
diff --git a/alliance/share/cells/sxlib/oa22_x2.al b/alliance/share/cells/sxlib/oa22_x2.al
deleted file mode 100644
index fea0e23c..00000000
--- a/alliance/share/cells/sxlib/oa22_x2.al
+++ /dev/null
@@ -1,35 +0,0 @@
-V ALLIANCE : 6
-H oa22_x2,L,30/10/99
-C i0,IN,EXTERNAL,8
-C i1,IN,EXTERNAL,6
-C i2,IN,EXTERNAL,7
-C q,OUT,EXTERNAL,4
-C vdd,IN,EXTERNAL,5
-C vss,IN,EXTERNAL,2
-T P,0.35,2.9,1,6,9,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00008
-T P,0.35,2.9,9,8,1,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00007
-T P,0.35,2.9,9,7,5,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00006
-T P,0.35,5.9,5,1,4,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00005
-T N,0.35,1.4,1,6,3,0,0.75,0.75,4.3,4.3,3.6,3,tr_00004
-T N,0.35,1.4,3,8,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00003
-T N,0.35,1.4,2,7,1,0,0.75,0.75,4.3,4.3,5.4,3,tr_00002
-T N,0.35,2.9,4,1,2,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00001
-S 9,INTERNAL
-Q 0.00171257
-S 8,EXTERNAL,i0
-Q 0.00295461
-S 7,EXTERNAL,i2
-Q 0.00383259
-S 6,EXTERNAL,i1
-Q 0.00270208
-S 5,EXTERNAL,vdd
-Q 0.00367968
-S 4,EXTERNAL,q
-Q 0.00358405
-S 3,INTERNAL
-Q 0
-S 2,EXTERNAL,vss
-Q 0.00367968
-S 1,INTERNAL
-Q 0.00439855
-EOF
diff --git a/alliance/share/cells/sxlib/oa22_x2.ap b/alliance/share/cells/sxlib/oa22_x2.ap
deleted file mode 100644
index abc74245..00000000
--- a/alliance/share/cells/sxlib/oa22_x2.ap
+++ /dev/null
@@ -1,96 +0,0 @@
-V ALLIANCE : 6
-H oa22_x2,P,30/ 8/2000,100
-A 0,0,3000,5000
-R 2500,4000,ref_ref,q_40
-R 2500,3500,ref_ref,q_35
-R 2500,3000,ref_ref,q_30
-R 2500,2500,ref_ref,q_25
-R 2500,2000,ref_ref,q_20
-R 2500,1500,ref_ref,q_15
-R 2500,1000,ref_ref,q_10
-R 2000,1000,ref_ref,i2_10
-R 2000,1500,ref_ref,i2_15
-R 2000,2000,ref_ref,i2_20
-R 2000,2500,ref_ref,i2_25
-R 2000,3000,ref_ref,i2_30
-R 2000,3500,ref_ref,i2_35
-R 2000,4000,ref_ref,i2_40
-R 1000,1000,ref_ref,i1_10
-R 1000,1500,ref_ref,i1_15
-R 1000,2000,ref_ref,i1_20
-R 1000,2500,ref_ref,i1_25
-R 1000,3000,ref_ref,i1_30
-R 500,3000,ref_ref,i0_30
-R 500,2500,ref_ref,i0_25
-R 500,2000,ref_ref,i0_20
-R 500,1500,ref_ref,i0_15
-R 500,1000,ref_ref,i0_10
-S 2500,1000,2500,4000,200,q,DOWN,CALU1
-S 2000,1000,2000,4000,200,i2,DOWN,CALU1
-S 1000,1000,1000,3000,200,i1,DOWN,CALU1
-S 500,1000,500,3000,200,i0,DOWN,CALU1
-S 1000,1000,1000,3000,100,*,UP,ALU1
-S 2000,1000,2000,4000,100,*,UP,ALU1
-S 500,1000,500,3000,100,*,UP,ALU1
-S 1500,1000,1500,3500,100,*,DOWN,ALU1
-S 300,4000,1500,4000,100,*,RIGHT,ALU1
-S 0,300,3000,300,600,vss,RIGHT,CALU1
-S 900,3500,1500,3500,100,*,RIGHT,ALU1
-S 0,4700,3000,4700,600,vdd,RIGHT,CALU1
-S 600,1400,600,3100,100,*,UP,POLY
-S 2400,1400,2400,2600,100,*,UP,POLY
-S 1500,800,1500,1200,300,*,DOWN,NDIF
-S 1200,600,1200,1400,100,*,UP,NTRANS
-S 900,800,900,1200,300,*,DOWN,NDIF
-S 600,600,600,1400,100,*,UP,NTRANS
-S 1800,600,1800,1400,100,*,UP,NTRANS
-S 300,400,300,1200,300,*,DOWN,NDIF
-S 2400,100,2400,1400,100,*,UP,NTRANS
-S 2700,300,2700,1200,300,*,DOWN,NDIF
-S 2100,300,2100,1200,300,*,DOWN,NDIF
-S 900,3300,900,4200,300,*,UP,PDIF
-S 1500,3300,1500,4200,300,*,UP,PDIF
-S 300,3300,300,4200,300,*,UP,PDIF
-S 1200,3100,1200,4400,100,*,DOWN,PTRANS
-S 600,3100,600,4400,100,*,DOWN,PTRANS
-S 1800,3100,1800,4400,100,*,DOWN,PTRANS
-S 2700,2800,2700,4700,300,*,UP,PDIF
-S 2400,2600,2400,4900,100,*,DOWN,PTRANS
-S 2100,2800,2100,4700,300,*,UP,PDIF
-S 0,3900,3000,3900,2400,*,RIGHT,NWELL
-S 2500,4000,2700,4000,200,*,RIGHT,ALU1
-S 2500,3500,2700,3500,200,*,RIGHT,ALU1
-S 2500,3000,2700,3000,200,*,LEFT,ALU1
-S 2500,1000,2700,1000,200,*,RIGHT,ALU1
-S 1800,2500,2000,2500,300,*,RIGHT,POLY
-S 1800,1500,2000,1500,300,*,RIGHT,POLY
-S 1800,2400,1800,3100,100,*,UP,POLY
-S 1000,1500,1200,1500,300,*,RIGHT,POLY
-S 1000,3000,1200,3000,300,*,RIGHT,POLY
-S 1500,2000,2400,2000,100,*,RIGHT,POLY
-S 2500,950,2500,4050,200,*,DOWN,ALU1
-S 300,3500,300,4000,100,*,UP,ALU1
-V 500,2000,CONT_POLY,*
-V 1500,300,CONT_BODY_P,*
-V 900,300,CONT_BODY_P,*
-V 2700,1000,CONT_DIF_N,*
-V 300,500,CONT_DIF_N,*
-V 1500,1000,CONT_DIF_N,*
-V 2100,500,CONT_DIF_N,*
-V 900,4700,CONT_BODY_N,*
-V 1500,4700,CONT_BODY_N,*
-V 300,4000,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 900,3500,CONT_DIF_P,*
-V 2100,4500,CONT_DIF_P,*
-V 300,4700,CONT_BODY_N,*
-V 2700,4000,CONT_DIF_P,*
-V 2700,3500,CONT_DIF_P,*
-V 2700,3000,CONT_DIF_P,*
-V 2000,1500,CONT_POLY,*
-V 2000,2500,CONT_POLY,*
-V 1000,1500,CONT_POLY,*
-V 1000,3000,CONT_POLY,*
-V 1500,2000,CONT_POLY,*
-V 300,3500,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/oa22_x2.sym b/alliance/share/cells/sxlib/oa22_x2.sym
deleted file mode 100644
index 803280de..00000000
Binary files a/alliance/share/cells/sxlib/oa22_x2.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/oa22_x2.vbe b/alliance/share/cells/sxlib/oa22_x2.vbe
deleted file mode 100644
index d2d26760..00000000
--- a/alliance/share/cells/sxlib/oa22_x2.vbe
+++ /dev/null
@@ -1,38 +0,0 @@
-ENTITY oa22_x2 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 1500;
-  CONSTANT cin_i0	 : NATURAL := 8;
-  CONSTANT cin_i1	 : NATURAL := 8;
-  CONSTANT cin_i2	 : NATURAL := 9;
-  CONSTANT rdown_i0_q	 : NATURAL := 1620;
-  CONSTANT rdown_i1_q	 : NATURAL := 1620;
-  CONSTANT rdown_i2_q	 : NATURAL := 1620;
-  CONSTANT rup_i0_q	 : NATURAL := 1790;
-  CONSTANT rup_i1_q	 : NATURAL := 1790;
-  CONSTANT rup_i2_q	 : NATURAL := 1790;
-  CONSTANT tphh_i0_q	 : NATURAL := 390;
-  CONSTANT tphh_i2_q	 : NATURAL := 438;
-  CONSTANT tpll_i2_q	 : NATURAL := 454;
-  CONSTANT tphh_i1_q	 : NATURAL := 488;
-  CONSTANT tpll_i1_q	 : NATURAL := 525;
-  CONSTANT tpll_i0_q	 : NATURAL := 555;
-  CONSTANT transistors	 : NATURAL := 8
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END oa22_x2;
-
-ARCHITECTURE behaviour_data_flow OF oa22_x2 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on oa22_x2"
-  SEVERITY WARNING;
-  q <= ((i0 and i1) or i2) after 1200 ps;
-END;
diff --git a/alliance/share/cells/sxlib/oa22_x2.vhd b/alliance/share/cells/sxlib/oa22_x2.vhd
deleted file mode 100644
index 882c5eac..00000000
--- a/alliance/share/cells/sxlib/oa22_x2.vhd
+++ /dev/null
@@ -1,21 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY oa22_x2 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END oa22_x2;
-
-ARCHITECTURE RTL OF oa22_x2 IS
-BEGIN
-  q <= ((i0 AND i1) OR i2);
-END RTL;
diff --git a/alliance/share/cells/sxlib/oa22_x4.al b/alliance/share/cells/sxlib/oa22_x4.al
deleted file mode 100644
index 63de95c1..00000000
--- a/alliance/share/cells/sxlib/oa22_x4.al
+++ /dev/null
@@ -1,37 +0,0 @@
-V ALLIANCE : 6
-H oa22_x4,L,30/10/99
-C i0,IN,EXTERNAL,6
-C i1,IN,EXTERNAL,8
-C i2,IN,EXTERNAL,7
-C q,OUT,EXTERNAL,4
-C vdd,IN,EXTERNAL,5
-C vss,IN,EXTERNAL,2
-T P,0.35,2.9,9,7,5,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00010
-T P,0.35,2.9,9,6,3,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00009
-T P,0.35,2.9,3,8,9,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00008
-T P,0.35,5.9,5,3,4,0,0.75,0.75,13.3,13.3,8.1,11.25,tr_00007
-T P,0.35,5.9,4,3,5,0,0.75,0.75,13.3,13.3,9.9,11.25,tr_00006
-T N,0.35,1.4,2,7,3,0,0.75,0.75,4.3,4.3,5.4,3,tr_00005
-T N,0.35,1.4,1,6,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00004
-T N,0.35,1.4,3,8,1,0,0.75,0.75,4.3,4.3,3.6,3,tr_00003
-T N,0.35,2.9,2,3,4,0,0.75,0.75,7.3,7.3,9.9,2.25,tr_00002
-T N,0.35,2.9,4,3,2,0,0.75,0.75,7.3,7.3,8.1,2.25,tr_00001
-S 9,INTERNAL
-Q 0.00114171
-S 8,EXTERNAL,i1
-Q 0.00270208
-S 7,EXTERNAL,i2
-Q 0.00383259
-S 6,EXTERNAL,i0
-Q 0.00295461
-S 5,EXTERNAL,vdd
-Q 0.00606652
-S 4,EXTERNAL,q
-Q 0.00258522
-S 3,INTERNAL
-Q 0.00611125
-S 2,EXTERNAL,vss
-Q 0.00512644
-S 1,INTERNAL
-Q 0
-EOF
diff --git a/alliance/share/cells/sxlib/oa22_x4.ap b/alliance/share/cells/sxlib/oa22_x4.ap
deleted file mode 100644
index 7fd5a166..00000000
--- a/alliance/share/cells/sxlib/oa22_x4.ap
+++ /dev/null
@@ -1,105 +0,0 @@
-V ALLIANCE : 6
-H oa22_x4,P,30/ 8/2000,100
-A 0,0,4000,5000
-R 500,1000,ref_ref,i0_10
-R 500,1500,ref_ref,i0_15
-R 500,2000,ref_ref,i0_20
-R 500,2500,ref_ref,i0_25
-R 500,3000,ref_ref,i0_30
-R 1000,3000,ref_ref,i1_30
-R 1000,2500,ref_ref,i1_25
-R 1000,2000,ref_ref,i1_20
-R 1000,1500,ref_ref,i1_15
-R 1000,1000,ref_ref,i1_10
-R 2000,4000,ref_ref,i2_40
-R 2000,3500,ref_ref,i2_35
-R 2000,3000,ref_ref,i2_30
-R 2000,2500,ref_ref,i2_25
-R 2000,2000,ref_ref,i2_20
-R 2000,1500,ref_ref,i2_15
-R 2000,1000,ref_ref,i2_10
-R 3000,4000,ref_ref,q_40
-R 3000,3500,ref_ref,q_35
-R 3000,3000,ref_ref,q_30
-R 3000,2500,ref_ref,q_25
-R 3000,2000,ref_ref,q_20
-R 3000,1500,ref_ref,q_15
-R 3000,1000,ref_ref,q_10
-S 500,1000,500,3000,200,i0,DOWN,CALU1
-S 1000,1000,1000,3000,200,i1,DOWN,CALU1
-S 2000,1000,2000,4000,200,i2,DOWN,CALU1
-S 3000,1000,3000,4000,200,q,DOWN,CALU1
-S 0,300,4000,300,600,vss,RIGHT,CALU1
-S 0,3900,4000,3900,2400,*,RIGHT,NWELL
-S 0,4700,4000,4700,600,vdd,RIGHT,CALU1
-S 1000,3000,1200,3000,300,*,RIGHT,POLY
-S 1000,1500,1200,1500,300,*,RIGHT,POLY
-S 1800,2400,1800,3100,100,*,UP,POLY
-S 1800,1500,2000,1500,300,*,RIGHT,POLY
-S 1800,2500,2000,2500,300,*,RIGHT,POLY
-S 2100,2800,2100,4700,300,*,UP,PDIF
-S 1800,3100,1800,4400,100,*,DOWN,PTRANS
-S 600,3100,600,4400,100,*,DOWN,PTRANS
-S 1200,3100,1200,4400,100,*,DOWN,PTRANS
-S 300,3300,300,4200,300,*,UP,PDIF
-S 1500,3300,1500,4200,300,*,UP,PDIF
-S 900,3300,900,4200,300,*,UP,PDIF
-S 2100,300,2100,1200,300,*,DOWN,NDIF
-S 300,400,300,1200,300,*,DOWN,NDIF
-S 1800,600,1800,1400,100,*,UP,NTRANS
-S 600,600,600,1400,100,*,UP,NTRANS
-S 900,800,900,1200,300,*,DOWN,NDIF
-S 1200,600,1200,1400,100,*,UP,NTRANS
-S 1500,800,1500,1200,300,*,DOWN,NDIF
-S 600,1400,600,3100,100,*,UP,POLY
-S 900,3500,1500,3500,100,*,RIGHT,ALU1
-S 300,4000,1500,4000,100,*,RIGHT,ALU1
-S 1500,1000,1500,3500,100,*,DOWN,ALU1
-S 500,1000,500,3000,100,*,UP,ALU1
-S 2000,1000,2000,4000,100,*,UP,ALU1
-S 1000,1000,1000,3000,100,*,UP,ALU1
-S 3600,3000,3600,4500,200,*,UP,ALU1
-S 3600,500,3600,1000,200,*,DOWN,ALU1
-S 3000,1000,3000,4000,200,*,DOWN,ALU1
-S 3300,1400,3300,2600,100,*,DOWN,POLY
-S 2700,1400,2700,2600,100,*,UP,POLY
-S 3600,300,3600,1200,300,*,DOWN,NDIF
-S 3300,100,3300,1400,100,*,UP,NTRANS
-S 3000,300,3000,1200,300,*,DOWN,NDIF
-S 2700,100,2700,1400,100,*,UP,NTRANS
-S 2700,2600,2700,4900,100,*,DOWN,PTRANS
-S 3000,2800,3000,4700,300,*,UP,PDIF
-S 3600,2800,3600,4700,300,*,UP,PDIF
-S 3300,2600,3300,4900,100,*,DOWN,PTRANS
-S 2300,2800,2300,4700,300,*,UP,PDIF
-S 2300,300,2300,1200,300,*,DOWN,NDIF
-S 1500,2000,3300,2000,200,*,RIGHT,POLY
-V 2300,500,CONT_DIF_N,*
-V 2300,4500,CONT_DIF_P,*
-V 1500,2000,CONT_POLY,*
-V 1000,3000,CONT_POLY,*
-V 1000,1500,CONT_POLY,*
-V 2000,2500,CONT_POLY,*
-V 2000,1500,CONT_POLY,*
-V 300,4700,CONT_BODY_N,*
-V 900,3500,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 300,4000,CONT_DIF_P,*
-V 1500,4700,CONT_BODY_N,*
-V 900,4700,CONT_BODY_N,*
-V 1500,1000,CONT_DIF_N,*
-V 300,500,CONT_DIF_N,*
-V 900,300,CONT_BODY_P,*
-V 1500,300,CONT_BODY_P,*
-V 500,2000,CONT_POLY,*
-V 3600,500,CONT_DIF_N,*
-V 3600,1000,CONT_DIF_N,*
-V 3000,1000,CONT_DIF_N,*
-V 3600,4000,CONT_DIF_P,*
-V 3600,4500,CONT_DIF_P,*
-V 3000,3000,CONT_DIF_P,*
-V 3000,3500,CONT_DIF_P,*
-V 3000,4000,CONT_DIF_P,*
-V 3600,3000,CONT_DIF_P,*
-V 3600,3500,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/oa22_x4.sym b/alliance/share/cells/sxlib/oa22_x4.sym
deleted file mode 100644
index 50b52fb7..00000000
Binary files a/alliance/share/cells/sxlib/oa22_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/oa22_x4.vbe b/alliance/share/cells/sxlib/oa22_x4.vbe
deleted file mode 100644
index fa425e33..00000000
--- a/alliance/share/cells/sxlib/oa22_x4.vbe
+++ /dev/null
@@ -1,38 +0,0 @@
-ENTITY oa22_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 2000;
-  CONSTANT cin_i0	 : NATURAL := 8;
-  CONSTANT cin_i1	 : NATURAL := 8;
-  CONSTANT cin_i2	 : NATURAL := 9;
-  CONSTANT rdown_i0_q	 : NATURAL := 810;
-  CONSTANT rdown_i1_q	 : NATURAL := 810;
-  CONSTANT rdown_i2_q	 : NATURAL := 810;
-  CONSTANT rup_i0_q	 : NATURAL := 890;
-  CONSTANT rup_i1_q	 : NATURAL := 890;
-  CONSTANT rup_i2_q	 : NATURAL := 890;
-  CONSTANT tphh_i0_q	 : NATURAL := 511;
-  CONSTANT tphh_i2_q	 : NATURAL := 523;
-  CONSTANT tpll_i2_q	 : NATURAL := 571;
-  CONSTANT tphh_i1_q	 : NATURAL := 615;
-  CONSTANT tpll_i1_q	 : NATURAL := 650;
-  CONSTANT tpll_i0_q	 : NATURAL := 677;
-  CONSTANT transistors	 : NATURAL := 10
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END oa22_x4;
-
-ARCHITECTURE behaviour_data_flow OF oa22_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on oa22_x4"
-  SEVERITY WARNING;
-  q <= ((i0 and i1) or i2) after 1300 ps;
-END;
diff --git a/alliance/share/cells/sxlib/oa22_x4.vhd b/alliance/share/cells/sxlib/oa22_x4.vhd
deleted file mode 100644
index 3c61d808..00000000
--- a/alliance/share/cells/sxlib/oa22_x4.vhd
+++ /dev/null
@@ -1,21 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY oa22_x4 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END oa22_x4;
-
-ARCHITECTURE RTL OF oa22_x4 IS
-BEGIN
-  q <= ((i0 AND i1) OR i2);
-END RTL;
diff --git a/alliance/share/cells/sxlib/oa2a22_x2.al b/alliance/share/cells/sxlib/oa2a22_x2.al
deleted file mode 100644
index e82135ab..00000000
--- a/alliance/share/cells/sxlib/oa2a22_x2.al
+++ /dev/null
@@ -1,42 +0,0 @@
-V ALLIANCE : 6
-H oa2a22_x2,L,30/10/99
-C i0,IN,EXTERNAL,6
-C i1,IN,EXTERNAL,5
-C i2,IN,EXTERNAL,7
-C i3,IN,EXTERNAL,8
-C q,OUT,EXTERNAL,9
-C vdd,IN,EXTERNAL,10
-C vss,IN,EXTERNAL,1
-T P,0.35,2.9,11,5,3,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00010
-T P,0.35,2.9,11,8,10,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00009
-T P,0.35,2.9,10,7,11,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00008
-T P,0.35,2.9,3,6,11,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00007
-T P,0.35,5.9,9,3,10,0,0.75,0.75,13.3,13.3,11.1,11.25,tr_00006
-T N,0.35,1.4,2,5,3,0,0.75,0.75,4.3,4.3,3.6,3,tr_00005
-T N,0.35,1.4,1,6,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00004
-T N,0.35,1.4,4,8,1,0,0.75,0.75,4.3,4.3,7.2,3,tr_00003
-T N,0.35,1.4,3,7,4,0,0.75,0.75,4.3,4.3,5.4,3,tr_00002
-T N,0.35,2.9,1,3,9,0,0.75,0.75,7.3,7.3,11.1,2.25,tr_00001
-S 11,INTERNAL
-Q 0.00199441
-S 10,EXTERNAL,vdd
-Q 0.00564418
-S 9,EXTERNAL,q
-Q 0.00258522
-S 8,EXTERNAL,i3
-Q 0.00295462
-S 7,EXTERNAL,i2
-Q 0.00323197
-S 6,EXTERNAL,i0
-Q 0.00295462
-S 5,EXTERNAL,i1
-Q 0.00323197
-S 4,INTERNAL
-Q 0
-S 3,INTERNAL
-Q 0.00577862
-S 2,INTERNAL
-Q 0
-S 1,EXTERNAL,vss
-Q 0.00564418
-EOF
diff --git a/alliance/share/cells/sxlib/oa2a22_x2.ap b/alliance/share/cells/sxlib/oa2a22_x2.ap
deleted file mode 100644
index 45e3abf5..00000000
--- a/alliance/share/cells/sxlib/oa2a22_x2.ap
+++ /dev/null
@@ -1,110 +0,0 @@
-V ALLIANCE : 6
-H oa2a22_x2,P, 6/ 9/2000,100
-A 0,0,4500,5000
-R 4000,2500,ref_ref,q_25
-R 4000,1500,ref_ref,q_15
-R 4000,1000,ref_ref,q_10
-R 4000,2000,ref_ref,q_20
-R 4000,3000,ref_ref,q_30
-R 4000,3500,ref_ref,q_35
-R 4000,4000,ref_ref,q_40
-R 500,1000,ref_ref,i0_10
-R 500,1500,ref_ref,i0_15
-R 500,2000,ref_ref,i0_20
-R 500,2500,ref_ref,i0_25
-R 500,3000,ref_ref,i0_30
-R 1000,3000,ref_ref,i1_30
-R 1000,2500,ref_ref,i1_25
-R 1000,2000,ref_ref,i1_20
-R 1000,1500,ref_ref,i1_15
-R 1000,1000,ref_ref,i1_10
-R 2000,1000,ref_ref,i2_10
-R 2000,1500,ref_ref,i2_15
-R 2000,2000,ref_ref,i2_20
-R 2000,2500,ref_ref,i2_25
-R 2000,3000,ref_ref,i2_30
-R 2500,3000,ref_ref,i3_30
-R 2500,2500,ref_ref,i3_25
-R 2500,2000,ref_ref,i3_20
-R 2500,1500,ref_ref,i3_15
-R 2500,1000,ref_ref,i3_10
-S 3500,2000,3700,2000,300,*,RIGHT,POLY
-S 0,300,4500,300,600,vss,RIGHT,CALU1
-S 0,3900,4500,3900,2400,*,RIGHT,NWELL
-S 0,4700,4500,4700,600,vdd,RIGHT,CALU1
-S 3500,2000,3500,3500,100,*,DOWN,ALU1
-S 900,3500,3500,3500,100,*,RIGHT,ALU1
-S 4000,2800,4000,4700,300,*,DOWN,PDIF
-S 3700,2600,3700,4900,100,*,UP,PTRANS
-S 3400,2800,3400,4700,300,*,DOWN,PDIF
-S 3700,100,3700,1400,100,*,DOWN,NTRANS
-S 4000,300,4000,1200,300,*,UP,NDIF
-S 3400,300,3400,1200,300,*,UP,NDIF
-S 3700,1400,3700,2600,100,*,DOWN,POLY
-S 3400,500,3400,1000,200,*,DOWN,ALU1
-S 4000,1000,4000,4000,200,*,UP,ALU1
-S 3400,4000,3400,4500,200,*,DOWN,ALU1
-S 1500,1000,1500,3500,100,*,UP,ALU1
-S 500,1000,500,3000,100,*,UP,ALU1
-S 1000,1000,1000,3000,100,*,DOWN,ALU1
-S 300,4000,2700,4000,100,*,RIGHT,ALU1
-S 1800,2000,2000,2000,300,*,RIGHT,POLY
-S 1000,2000,1200,2000,300,*,RIGHT,POLY
-S 2000,1000,2000,3000,100,*,DOWN,ALU1
-S 2500,1000,2500,3000,100,*,DOWN,ALU1
-S 900,3300,900,4200,300,*,DOWN,PDIF
-S 600,3100,600,4400,100,*,UP,PTRANS
-S 300,3300,300,4200,300,*,DOWN,PDIF
-S 1500,3300,1500,4200,300,*,DOWN,PDIF
-S 2700,3300,2700,4200,300,*,DOWN,PDIF
-S 1800,3100,1800,4400,100,*,UP,PTRANS
-S 2400,3100,2400,4400,100,*,UP,PTRANS
-S 1200,3100,1200,4400,100,*,UP,PTRANS
-S 1500,800,1500,1200,300,*,UP,NDIF
-S 1800,600,1800,1400,100,*,DOWN,NTRANS
-S 2100,800,2100,1200,300,*,UP,NDIF
-S 2400,600,2400,1400,100,*,DOWN,NTRANS
-S 600,600,600,1400,100,*,DOWN,NTRANS
-S 900,800,900,1200,300,*,UP,NDIF
-S 1200,600,1200,1400,100,*,DOWN,NTRANS
-S 2400,1400,2400,3100,100,*,DOWN,POLY
-S 1800,1400,1800,3100,100,*,DOWN,POLY
-S 1200,1400,1200,3100,100,*,DOWN,POLY
-S 600,1400,600,3100,100,*,DOWN,POLY
-S 2100,3300,2100,4600,300,*,DOWN,PDIF
-S 300,400,300,1200,300,*,UP,NDIF
-S 2700,400,2700,1200,300,*,UP,NDIF
-S 4000,1000,4000,4000,200,q,DOWN,CALU1
-S 500,1000,500,3000,200,i0,DOWN,CALU1
-S 1000,1000,1000,3000,200,i1,DOWN,CALU1
-S 2000,1000,2000,3000,200,i2,DOWN,CALU1
-S 2500,1000,2500,3000,200,i3,DOWN,CALU1
-V 2100,300,CONT_BODY_P,*
-V 900,300,CONT_BODY_P,*
-V 2700,4700,CONT_BODY_N,*
-V 900,4700,CONT_BODY_N,*
-V 3400,4000,CONT_DIF_P,*
-V 3400,4500,CONT_DIF_P,*
-V 3400,500,CONT_DIF_N,*
-V 3400,1000,CONT_DIF_N,*
-V 4000,1000,CONT_DIF_N,*
-V 3500,2000,CONT_POLY,*
-V 1500,1000,CONT_DIF_N,*
-V 900,3500,CONT_DIF_P,*
-V 2100,4500,CONT_DIF_P,*
-V 2700,4000,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 300,4000,CONT_DIF_P,*
-V 2000,2000,CONT_POLY,*
-V 1000,2000,CONT_POLY,*
-V 2700,500,CONT_DIF_N,*
-V 300,500,CONT_DIF_N,*
-V 2500,2000,CONT_POLY,*
-V 500,2000,CONT_POLY,*
-V 1500,300,CONT_BODY_P,*
-V 300,4700,CONT_BODY_N,*
-V 1500,4700,CONT_BODY_N,*
-V 4000,3000,CONT_DIF_P,*
-V 4000,3500,CONT_DIF_P,*
-V 4000,4000,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/oa2a22_x2.sym b/alliance/share/cells/sxlib/oa2a22_x2.sym
deleted file mode 100644
index 44737138..00000000
Binary files a/alliance/share/cells/sxlib/oa2a22_x2.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/oa2a22_x2.vbe b/alliance/share/cells/sxlib/oa2a22_x2.vbe
deleted file mode 100644
index 1c5c4088..00000000
--- a/alliance/share/cells/sxlib/oa2a22_x2.vbe
+++ /dev/null
@@ -1,44 +0,0 @@
-ENTITY oa2a22_x2 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 2250;
-  CONSTANT cin_i0	 : NATURAL := 8;
-  CONSTANT cin_i1	 : NATURAL := 8;
-  CONSTANT cin_i2	 : NATURAL := 8;
-  CONSTANT cin_i3	 : NATURAL := 8;
-  CONSTANT rdown_i0_q	 : NATURAL := 1620;
-  CONSTANT rdown_i1_q	 : NATURAL := 1620;
-  CONSTANT rdown_i2_q	 : NATURAL := 1620;
-  CONSTANT rdown_i3_q	 : NATURAL := 1620;
-  CONSTANT rup_i0_q	 : NATURAL := 1790;
-  CONSTANT rup_i1_q	 : NATURAL := 1790;
-  CONSTANT rup_i2_q	 : NATURAL := 1790;
-  CONSTANT rup_i3_q	 : NATURAL := 1790;
-  CONSTANT tphh_i0_q	 : NATURAL := 403;
-  CONSTANT tpll_i2_q	 : NATURAL := 487;
-  CONSTANT tphh_i1_q	 : NATURAL := 495;
-  CONSTANT tpll_i3_q	 : NATURAL := 512;
-  CONSTANT tpll_i1_q	 : NATURAL := 534;
-  CONSTANT tphh_i3_q	 : NATURAL := 537;
-  CONSTANT tpll_i0_q	 : NATURAL := 564;
-  CONSTANT tphh_i2_q	 : NATURAL := 646;
-  CONSTANT transistors	 : NATURAL := 10
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  i3	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END oa2a22_x2;
-
-ARCHITECTURE behaviour_data_flow OF oa2a22_x2 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on oa2a22_x2"
-  SEVERITY WARNING;
-  q <= ((i0 and i1) or (i2 and i3)) after 1200 ps;
-END;
diff --git a/alliance/share/cells/sxlib/oa2a22_x2.vhd b/alliance/share/cells/sxlib/oa2a22_x2.vhd
deleted file mode 100644
index fc749b4f..00000000
--- a/alliance/share/cells/sxlib/oa2a22_x2.vhd
+++ /dev/null
@@ -1,22 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY oa2a22_x2 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  i3	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END oa2a22_x2;
-
-ARCHITECTURE RTL OF oa2a22_x2 IS
-BEGIN
-  q <= ((i0 AND i1) OR (i2 AND i3));
-END RTL;
diff --git a/alliance/share/cells/sxlib/oa2a22_x4.al b/alliance/share/cells/sxlib/oa2a22_x4.al
deleted file mode 100644
index 1d11346d..00000000
--- a/alliance/share/cells/sxlib/oa2a22_x4.al
+++ /dev/null
@@ -1,44 +0,0 @@
-V ALLIANCE : 6
-H oa2a22_x4,L,30/10/99
-C i0,IN,EXTERNAL,7
-C i1,IN,EXTERNAL,5
-C i2,IN,EXTERNAL,6
-C i3,IN,EXTERNAL,8
-C q,OUT,EXTERNAL,9
-C vdd,IN,EXTERNAL,10
-C vss,IN,EXTERNAL,1
-T P,0.35,5.9,9,4,10,0,0.75,0.75,13.3,13.3,11.1,11.25,tr_00012
-T P,0.35,5.9,10,4,9,0,0.75,0.75,13.3,13.3,12.9,11.25,tr_00011
-T P,0.35,2.9,4,7,11,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00010
-T P,0.35,2.9,10,6,11,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00009
-T P,0.35,2.9,11,8,10,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00008
-T P,0.35,2.9,11,5,4,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00007
-T N,0.35,2.9,1,4,9,0,0.75,0.75,7.3,7.3,11.1,2.25,tr_00006
-T N,0.35,2.9,9,4,1,0,0.75,0.75,7.3,7.3,12.9,2.25,tr_00005
-T N,0.35,1.4,4,6,3,0,0.75,0.75,4.3,4.3,5.4,3,tr_00004
-T N,0.35,1.4,3,8,1,0,0.75,0.75,4.3,4.3,7.2,3,tr_00003
-T N,0.35,1.4,1,7,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00002
-T N,0.35,1.4,2,5,4,0,0.75,0.75,4.3,4.3,3.6,3,tr_00001
-S 11,INTERNAL
-Q 0.00199441
-S 10,EXTERNAL,vdd
-Q 0.00768955
-S 9,EXTERNAL,q
-Q 0.00258522
-S 8,EXTERNAL,i3
-Q 0.00295462
-S 7,EXTERNAL,i0
-Q 0.00295462
-S 6,EXTERNAL,i2
-Q 0.00323197
-S 5,EXTERNAL,i1
-Q 0.00323197
-S 4,INTERNAL
-Q 0.00732866
-S 3,INTERNAL
-Q 0
-S 2,INTERNAL
-Q 0
-S 1,EXTERNAL,vss
-Q 0.00674947
-EOF
diff --git a/alliance/share/cells/sxlib/oa2a22_x4.ap b/alliance/share/cells/sxlib/oa2a22_x4.ap
deleted file mode 100644
index 0954420e..00000000
--- a/alliance/share/cells/sxlib/oa2a22_x4.ap
+++ /dev/null
@@ -1,123 +0,0 @@
-V ALLIANCE : 6
-H oa2a22_x4,P,30/ 8/2000,100
-A 0,0,5000,5000
-R 4000,2500,ref_ref,q_25
-R 4000,1500,ref_ref,q_15
-R 4000,1000,ref_ref,q_10
-R 4000,2000,ref_ref,q_20
-R 4000,3000,ref_ref,q_30
-R 4000,3500,ref_ref,q_35
-R 4000,4000,ref_ref,q_40
-R 500,1000,ref_ref,i0_10
-R 500,1500,ref_ref,i0_15
-R 500,2000,ref_ref,i0_20
-R 500,2500,ref_ref,i0_25
-R 500,3000,ref_ref,i0_30
-R 1000,3000,ref_ref,i1_30
-R 1000,2500,ref_ref,i1_25
-R 1000,2000,ref_ref,i1_20
-R 1000,1500,ref_ref,i1_15
-R 1000,1000,ref_ref,i1_10
-R 2000,1000,ref_ref,i2_10
-R 2000,1500,ref_ref,i2_15
-R 2000,2000,ref_ref,i2_20
-R 2000,2500,ref_ref,i2_25
-R 2000,3000,ref_ref,i2_30
-R 2500,3000,ref_ref,i3_30
-R 2500,2500,ref_ref,i3_25
-R 2500,2000,ref_ref,i3_20
-R 2500,1500,ref_ref,i3_15
-R 2500,1000,ref_ref,i3_10
-S 4000,1000,4000,4000,200,q,DOWN,CALU1
-S 500,1000,500,3000,200,i0,DOWN,CALU1
-S 1000,1000,1000,3000,200,i1,DOWN,CALU1
-S 2000,1000,2000,3000,200,i2,DOWN,CALU1
-S 2500,1000,2500,3000,200,i3,DOWN,CALU1
-S 3500,2000,4300,2000,100,*,RIGHT,POLY
-S 3500,2000,3500,3500,100,*,DOWN,ALU1
-S 900,3500,3500,3500,100,*,RIGHT,ALU1
-S 4000,2800,4000,4700,300,*,DOWN,PDIF
-S 3700,2600,3700,4900,100,*,UP,PTRANS
-S 4300,2600,4300,4900,100,*,UP,PTRANS
-S 4600,2800,4600,4700,300,*,DOWN,PDIF
-S 3400,2800,3400,4700,300,*,DOWN,PDIF
-S 4600,300,4600,1200,300,*,UP,NDIF
-S 3700,100,3700,1400,100,*,DOWN,NTRANS
-S 4000,300,4000,1200,300,*,UP,NDIF
-S 3400,300,3400,1200,300,*,UP,NDIF
-S 4300,100,4300,1400,100,*,DOWN,NTRANS
-S 3700,1400,3700,2600,100,*,DOWN,POLY
-S 4300,1400,4300,2600,100,*,DOWN,POLY
-S 4600,3000,4600,4500,200,*,DOWN,ALU1
-S 3400,500,3400,1000,200,*,DOWN,ALU1
-S 4600,500,4600,1000,200,*,DOWN,ALU1
-S 4000,1000,4000,4000,200,*,UP,ALU1
-S 3400,4000,3400,4500,200,*,DOWN,ALU1
-S 0,300,5000,300,600,vss,RIGHT,CALU1
-S 0,3900,5000,3900,2400,*,RIGHT,NWELL
-S 0,4700,5000,4700,600,vdd,RIGHT,CALU1
-S 1500,1000,1500,3500,100,*,UP,ALU1
-S 500,1000,500,3000,100,*,UP,ALU1
-S 1000,1000,1000,3000,100,*,DOWN,ALU1
-S 300,4000,2700,4000,100,*,RIGHT,ALU1
-S 1800,2000,2000,2000,300,*,RIGHT,POLY
-S 1000,2000,1200,2000,300,*,RIGHT,POLY
-S 2000,1000,2000,3000,100,*,DOWN,ALU1
-S 2500,1000,2500,3000,100,*,DOWN,ALU1
-S 900,3300,900,4200,300,*,DOWN,PDIF
-S 600,3100,600,4400,100,*,UP,PTRANS
-S 300,3300,300,4200,300,*,DOWN,PDIF
-S 1500,3300,1500,4200,300,*,DOWN,PDIF
-S 2700,3300,2700,4200,300,*,DOWN,PDIF
-S 1800,3100,1800,4400,100,*,UP,PTRANS
-S 2400,3100,2400,4400,100,*,UP,PTRANS
-S 1200,3100,1200,4400,100,*,UP,PTRANS
-S 1500,800,1500,1200,300,*,UP,NDIF
-S 1800,600,1800,1400,100,*,DOWN,NTRANS
-S 2100,800,2100,1200,300,*,UP,NDIF
-S 2400,600,2400,1400,100,*,DOWN,NTRANS
-S 600,600,600,1400,100,*,DOWN,NTRANS
-S 900,800,900,1200,300,*,UP,NDIF
-S 1200,600,1200,1400,100,*,DOWN,NTRANS
-S 2400,1400,2400,3100,100,*,DOWN,POLY
-S 1800,1400,1800,3100,100,*,DOWN,POLY
-S 1200,1400,1200,3100,100,*,DOWN,POLY
-S 600,1400,600,3100,100,*,DOWN,POLY
-S 2100,3300,2100,4600,300,*,DOWN,PDIF
-S 300,400,300,1200,300,*,UP,NDIF
-S 2700,400,2700,1200,300,*,UP,NDIF
-V 2100,300,CONT_BODY_P,*
-V 900,300,CONT_BODY_P,*
-V 2700,4700,CONT_BODY_N,*
-V 900,4700,CONT_BODY_N,*
-V 4600,3000,CONT_DIF_P,*
-V 4600,3500,CONT_DIF_P,*
-V 4600,4000,CONT_DIF_P,*
-V 4600,4500,CONT_DIF_P,*
-V 3400,4000,CONT_DIF_P,*
-V 3400,4500,CONT_DIF_P,*
-V 4600,1000,CONT_DIF_N,*
-V 4600,500,CONT_DIF_N,*
-V 3400,500,CONT_DIF_N,*
-V 3400,1000,CONT_DIF_N,*
-V 4000,1000,CONT_DIF_N,*
-V 3500,2000,CONT_POLY,*
-V 1500,1000,CONT_DIF_N,*
-V 900,3500,CONT_DIF_P,*
-V 2100,4500,CONT_DIF_P,*
-V 2700,4000,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 300,4000,CONT_DIF_P,*
-V 2000,2000,CONT_POLY,*
-V 1000,2000,CONT_POLY,*
-V 2700,500,CONT_DIF_N,*
-V 300,500,CONT_DIF_N,*
-V 2500,2000,CONT_POLY,*
-V 500,2000,CONT_POLY,*
-V 1500,300,CONT_BODY_P,*
-V 300,4700,CONT_BODY_N,*
-V 1500,4700,CONT_BODY_N,*
-V 4000,3000,CONT_DIF_P,*
-V 4000,3500,CONT_DIF_P,*
-V 4000,4000,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/oa2a22_x4.sym b/alliance/share/cells/sxlib/oa2a22_x4.sym
deleted file mode 100644
index cc180c20..00000000
Binary files a/alliance/share/cells/sxlib/oa2a22_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/oa2a22_x4.vbe b/alliance/share/cells/sxlib/oa2a22_x4.vbe
deleted file mode 100644
index a233499c..00000000
--- a/alliance/share/cells/sxlib/oa2a22_x4.vbe
+++ /dev/null
@@ -1,44 +0,0 @@
-ENTITY oa2a22_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 2500;
-  CONSTANT cin_i0	 : NATURAL := 8;
-  CONSTANT cin_i1	 : NATURAL := 8;
-  CONSTANT cin_i2	 : NATURAL := 8;
-  CONSTANT cin_i3	 : NATURAL := 8;
-  CONSTANT rdown_i0_q	 : NATURAL := 810;
-  CONSTANT rdown_i1_q	 : NATURAL := 810;
-  CONSTANT rdown_i2_q	 : NATURAL := 810;
-  CONSTANT rdown_i3_q	 : NATURAL := 810;
-  CONSTANT rup_i0_q	 : NATURAL := 890;
-  CONSTANT rup_i1_q	 : NATURAL := 890;
-  CONSTANT rup_i2_q	 : NATURAL := 890;
-  CONSTANT rup_i3_q	 : NATURAL := 890;
-  CONSTANT tphh_i0_q	 : NATURAL := 519;
-  CONSTANT tpll_i2_q	 : NATURAL := 596;
-  CONSTANT tpll_i3_q	 : NATURAL := 619;
-  CONSTANT tphh_i1_q	 : NATURAL := 624;
-  CONSTANT tphh_i3_q	 : NATURAL := 644;
-  CONSTANT tpll_i1_q	 : NATURAL := 669;
-  CONSTANT tpll_i0_q	 : NATURAL := 696;
-  CONSTANT tphh_i2_q	 : NATURAL := 763;
-  CONSTANT transistors	 : NATURAL := 12
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  i3	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END oa2a22_x4;
-
-ARCHITECTURE behaviour_data_flow OF oa2a22_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on oa2a22_x4"
-  SEVERITY WARNING;
-  q <= ((i0 and i1) or (i2 and i3)) after 1400 ps;
-END;
diff --git a/alliance/share/cells/sxlib/oa2a22_x4.vhd b/alliance/share/cells/sxlib/oa2a22_x4.vhd
deleted file mode 100644
index 9cf43446..00000000
--- a/alliance/share/cells/sxlib/oa2a22_x4.vhd
+++ /dev/null
@@ -1,22 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY oa2a22_x4 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  i3	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END oa2a22_x4;
-
-ARCHITECTURE RTL OF oa2a22_x4 IS
-BEGIN
-  q <= ((i0 AND i1) OR (i2 AND i3));
-END RTL;
diff --git a/alliance/share/cells/sxlib/oa2a2a23_x2.al b/alliance/share/cells/sxlib/oa2a2a23_x2.al
deleted file mode 100644
index bcf6fd25..00000000
--- a/alliance/share/cells/sxlib/oa2a2a23_x2.al
+++ /dev/null
@@ -1,56 +0,0 @@
-V ALLIANCE : 6
-H oa2a2a23_x2,L,30/10/99
-C i0,IN,EXTERNAL,15
-C i1,IN,EXTERNAL,14
-C i2,IN,EXTERNAL,9
-C i3,IN,EXTERNAL,8
-C i4,IN,EXTERNAL,7
-C i5,IN,EXTERNAL,10
-C q,OUT,EXTERNAL,12
-C vdd,IN,EXTERNAL,13
-C vss,IN,EXTERNAL,1
-T P,0.35,5.9,5,7,2,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00014
-T P,0.35,5.9,2,10,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00013
-T P,0.35,5.9,5,9,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00012
-T P,0.35,5.9,6,8,5,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00011
-T P,0.35,5.9,6,14,13,0,0.75,0.75,13.3,13.3,12,11.25,tr_00010
-T P,0.35,5.9,13,15,6,0,0.75,0.75,13.3,13.3,13.8,11.25,tr_00009
-T P,0.35,5.9,12,2,13,0,0.75,0.75,13.3,13.3,15.6,11.25,tr_00008
-T N,0.35,2.9,4,8,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00007
-T N,0.35,2.9,2,7,3,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00006
-T N,0.35,2.9,1,9,4,0,0.75,0.75,7.3,7.3,6.6,2.25,tr_00005
-T N,0.35,2.9,3,10,1,0,0.75,0.75,7.3,7.3,2.4,2.25,tr_00004
-T N,0.35,2.9,11,14,2,0,0.75,0.75,7.3,7.3,12.6,2.25,tr_00003
-T N,0.35,2.9,1,15,11,0,0.75,0.75,7.3,7.3,13.8,2.25,tr_00002
-T N,0.35,2.9,12,2,1,0,0.75,0.75,7.3,7.3,15.6,2.25,tr_00001
-S 15,EXTERNAL,i0
-Q 0.00232574
-S 14,EXTERNAL,i1
-Q 0.00247612
-S 13,EXTERNAL,vdd
-Q 0.0071974
-S 12,EXTERNAL,q
-Q 0.00264397
-S 11,INTERNAL
-Q 0
-S 10,EXTERNAL,i5
-Q 0.00276531
-S 9,EXTERNAL,i2
-Q 0.00254552
-S 8,EXTERNAL,i3
-Q 0.00262649
-S 7,EXTERNAL,i4
-Q 0.00304715
-S 6,INTERNAL
-Q 0.0021
-S 5,INTERNAL
-Q 0.00199441
-S 4,INTERNAL
-Q 0
-S 3,INTERNAL
-Q 0
-S 2,INTERNAL
-Q 0.0070541
-S 1,EXTERNAL,vss
-Q 0.00572853
-EOF
diff --git a/alliance/share/cells/sxlib/oa2a2a23_x2.ap b/alliance/share/cells/sxlib/oa2a2a23_x2.ap
deleted file mode 100644
index afcf715b..00000000
--- a/alliance/share/cells/sxlib/oa2a2a23_x2.ap
+++ /dev/null
@@ -1,135 +0,0 @@
-V ALLIANCE : 6
-H oa2a2a23_x2,P, 6/ 9/2000,100
-A 0,0,6000,5000
-R 4500,1500,ref_ref,i0_15
-R 4500,3000,ref_ref,i0_30
-R 4000,3000,ref_ref,i1_30
-R 4000,2500,ref_ref,i1_25
-R 4000,1500,ref_ref,i1_15
-R 4000,2000,ref_ref,i1_20
-R 4500,2500,ref_ref,i0_25
-R 4500,2000,ref_ref,i0_20
-R 5500,1000,ref_ref,q_10
-R 5500,1500,ref_ref,q_15
-R 5500,3500,ref_ref,q_35
-R 5500,3000,ref_ref,q_30
-R 5500,2500,ref_ref,q_25
-R 5500,2000,ref_ref,q_20
-R 1500,3500,ref_ref,i4_35
-R 1500,3000,ref_ref,i4_30
-R 1500,2500,ref_ref,i4_25
-R 1500,2000,ref_ref,i4_20
-R 1500,1500,ref_ref,i4_15
-R 2000,2000,ref_ref,i3_20
-R 2500,3000,ref_ref,i2_30
-R 2500,2500,ref_ref,i2_25
-R 2500,2000,ref_ref,i2_20
-R 2500,1500,ref_ref,i2_15
-R 2000,3000,ref_ref,i3_30
-R 2000,2500,ref_ref,i3_25
-R 2000,1500,ref_ref,i3_15
-R 1000,1500,ref_ref,i5_15
-R 1000,3000,ref_ref,i5_30
-R 1000,2500,ref_ref,i5_25
-R 1000,2000,ref_ref,i5_20
-R 5500,4000,ref_ref,q_40
-S 5000,2000,5200,2000,300,*,RIGHT,POLY
-S 0,4700,6000,4700,600,vdd,RIGHT,CALU1
-S 0,3900,6000,3900,2400,*,RIGHT,NWELL
-S 0,300,6000,300,600,vss,RIGHT,CALU1
-S 5200,1400,5200,2600,100,*,DOWN,POLY
-S 5000,1000,5000,2000,100,*,UP,ALU1
-S 500,1000,5000,1000,100,*,RIGHT,ALU1
-S 500,1000,500,3450,100,*,DOWN,ALU1
-S 500,3450,900,3450,100,*,LEFT,ALU1
-S 2700,2800,2700,4700,300,*,UP,PDIF
-S 2100,3500,4300,3500,100,*,RIGHT,ALU1
-S 4000,1400,4200,1400,100,*,LEFT,POLY
-S 4600,1400,4600,2600,100,*,DOWN,POLY
-S 4000,1400,4000,2500,100,*,UP,POLY
-S 4500,1500,4500,3000,100,*,UP,ALU1
-S 4000,1500,4000,3000,100,*,UP,ALU1
-S 5200,2600,5200,4900,100,*,UP,PTRANS
-S 5500,2800,5500,4700,300,*,UP,PDIF
-S 4900,2800,4900,4700,300,*,UP,PDIF
-S 4300,2800,4300,4700,300,*,UP,PDIF
-S 4600,2600,4600,4900,100,*,UP,PTRANS
-S 4000,2600,4000,4900,100,*,UP,PTRANS
-S 3700,2800,3700,4100,300,*,UP,PDIF
-S 4900,300,4900,1200,300,*,DOWN,NDIF
-S 5500,300,5500,1200,300,*,DOWN,NDIF
-S 5200,100,5200,1400,100,*,UP,NTRANS
-S 4600,100,4600,1400,100,*,UP,NTRANS
-S 4200,100,4200,1400,100,*,UP,NTRANS
-S 3900,300,3900,1200,300,*,DOWN,NDIF
-S 5500,950,5500,4050,200,*,DOWN,ALU1
-S 3700,4000,3700,4700,200,*,UP,ALU1
-S 4300,3500,4300,4000,100,*,UP,ALU1
-S 4900,3500,4900,4600,200,*,DOWN,ALU1
-S 1500,1500,1500,3500,100,*,UP,ALU1
-S 800,1400,900,1400,100,*,LEFT,POLY
-S 500,300,500,1200,300,*,DOWN,NDIF
-S 800,100,800,1400,100,*,UP,NTRANS
-S 2200,1400,2400,1400,100,*,RIGHT,POLY
-S 2200,100,2200,1400,100,*,UP,NTRANS
-S 2500,300,2500,1200,300,*,DOWN,NDIF
-S 900,1400,900,2600,100,*,DOWN,POLY
-S 600,2600,900,2600,100,*,RIGHT,POLY
-S 1200,2600,1400,2600,100,*,LEFT,POLY
-S 1400,1400,1400,2600,100,*,UP,POLY
-S 1200,1400,1400,1400,100,*,RIGHT,POLY
-S 1800,1400,1900,1400,100,*,LEFT,POLY
-S 1900,1400,1900,2600,100,*,DOWN,POLY
-S 1800,2600,1900,2600,100,*,RIGHT,POLY
-S 2500,1500,2500,3000,100,*,UP,ALU1
-S 2000,1500,2000,3000,100,*,UP,ALU1
-S 1000,1500,1000,3000,100,*,UP,ALU1
-S 300,2800,300,4700,300,*,UP,PDIF
-S 1800,2600,1800,4900,100,*,UP,PTRANS
-S 2400,2600,2400,4900,100,*,UP,PTRANS
-S 600,2600,600,4900,100,*,UP,PTRANS
-S 1200,2600,1200,4900,100,*,UP,PTRANS
-S 1500,2800,1500,4700,300,*,UP,PDIF
-S 900,2800,900,4700,300,*,UP,PDIF
-S 2100,2800,2100,4700,300,*,UP,PDIF
-S 1200,100,1200,1400,100,*,UP,NTRANS
-S 1500,300,1500,1200,300,*,DOWN,NDIF
-S 1800,100,1800,1400,100,*,UP,NTRANS
-S 2400,1400,2400,2600,100,*,DOWN,POLY
-S 300,4000,2700,4000,100,*,RIGHT,ALU1
-S 4500,1500,4500,3000,200,i0,DOWN,CALU1
-S 4000,1500,4000,3000,200,i1,DOWN,CALU1
-S 5500,1000,5500,4000,200,q,DOWN,CALU1
-S 1500,1500,1500,3500,200,i4,DOWN,CALU1
-S 2000,1500,2000,3000,200,i3,DOWN,CALU1
-S 2500,1500,2500,3000,200,i2,DOWN,CALU1
-S 1000,1500,1000,3000,200,i5,DOWN,CALU1
-V 5000,2000,CONT_POLY,*
-V 3300,4600,CONT_BODY_N,*
-V 3200,400,CONT_BODY_P,*
-V 4000,2500,CONT_POLY,*
-V 4500,2500,CONT_POLY,*
-V 5500,3000,CONT_DIF_P,*
-V 5500,3500,CONT_DIF_P,*
-V 5500,4000,CONT_DIF_P,*
-V 4900,4000,CONT_DIF_P,*
-V 4900,4500,CONT_DIF_P,*
-V 4900,3500,CONT_DIF_P,*
-V 4300,4000,CONT_DIF_P,*
-V 3700,4000,CONT_DIF_P,*
-V 5500,1000,CONT_DIF_N,*
-V 4900,500,CONT_DIF_N,*
-V 3900,1000,CONT_DIF_N,*
-V 500,500,CONT_DIF_N,*
-V 2500,500,CONT_DIF_N,*
-V 1000,2000,CONT_POLY,*
-V 1500,2000,CONT_POLY,*
-V 2000,2500,CONT_POLY,*
-V 2500,2500,CONT_POLY,*
-V 2700,4000,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 300,4000,CONT_DIF_P,*
-V 2100,3500,CONT_DIF_P,*
-V 900,3500,CONT_DIF_P,*
-V 1500,1000,CONT_DIF_N,*
-EOF
diff --git a/alliance/share/cells/sxlib/oa2a2a23_x2.sym b/alliance/share/cells/sxlib/oa2a2a23_x2.sym
deleted file mode 100644
index 5bd6e787..00000000
Binary files a/alliance/share/cells/sxlib/oa2a2a23_x2.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/oa2a2a23_x2.vbe b/alliance/share/cells/sxlib/oa2a2a23_x2.vbe
deleted file mode 100644
index 189ed715..00000000
--- a/alliance/share/cells/sxlib/oa2a2a23_x2.vbe
+++ /dev/null
@@ -1,56 +0,0 @@
-ENTITY oa2a2a23_x2 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 3000;
-  CONSTANT cin_i0	 : NATURAL := 13;
-  CONSTANT cin_i1	 : NATURAL := 14;
-  CONSTANT cin_i2	 : NATURAL := 14;
-  CONSTANT cin_i3	 : NATURAL := 14;
-  CONSTANT cin_i4	 : NATURAL := 14;
-  CONSTANT cin_i5	 : NATURAL := 14;
-  CONSTANT rdown_i0_q	 : NATURAL := 1620;
-  CONSTANT rdown_i1_q	 : NATURAL := 1620;
-  CONSTANT rdown_i2_q	 : NATURAL := 1620;
-  CONSTANT rdown_i3_q	 : NATURAL := 1620;
-  CONSTANT rdown_i4_q	 : NATURAL := 1620;
-  CONSTANT rdown_i5_q	 : NATURAL := 1620;
-  CONSTANT rup_i0_q	 : NATURAL := 1790;
-  CONSTANT rup_i1_q	 : NATURAL := 1790;
-  CONSTANT rup_i2_q	 : NATURAL := 1790;
-  CONSTANT rup_i3_q	 : NATURAL := 1790;
-  CONSTANT rup_i4_q	 : NATURAL := 1790;
-  CONSTANT rup_i5_q	 : NATURAL := 1790;
-  CONSTANT tphh_i5_q	 : NATURAL := 321;
-  CONSTANT tphh_i4_q	 : NATURAL := 402;
-  CONSTANT tphh_i2_q	 : NATURAL := 441;
-  CONSTANT tphh_i3_q	 : NATURAL := 540;
-  CONSTANT tpll_i1_q	 : NATURAL := 542;
-  CONSTANT tpll_i0_q	 : NATURAL := 578;
-  CONSTANT tpll_i4_q	 : NATURAL := 591;
-  CONSTANT tpll_i3_q	 : NATURAL := 600;
-  CONSTANT tpll_i5_q	 : NATURAL := 636;
-  CONSTANT tpll_i2_q	 : NATURAL := 639;
-  CONSTANT tphh_i0_q	 : NATURAL := 653;
-  CONSTANT tphh_i1_q	 : NATURAL := 775;
-  CONSTANT transistors	 : NATURAL := 14
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  i3	 : in  BIT;
-  i4	 : in  BIT;
-  i5	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END oa2a2a23_x2;
-
-ARCHITECTURE behaviour_data_flow OF oa2a2a23_x2 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on oa2a2a23_x2"
-  SEVERITY WARNING;
-  q <= (((i0 and i1) or (i2 and i3)) or (i4 and i5)) after 1400 ps;
-END;
diff --git a/alliance/share/cells/sxlib/oa2a2a23_x2.vhd b/alliance/share/cells/sxlib/oa2a2a23_x2.vhd
deleted file mode 100644
index fc4cca2e..00000000
--- a/alliance/share/cells/sxlib/oa2a2a23_x2.vhd
+++ /dev/null
@@ -1,24 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY oa2a2a23_x2 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  i3	: IN STD_LOGIC;
-  i4	: IN STD_LOGIC;
-  i5	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END oa2a2a23_x2;
-
-ARCHITECTURE RTL OF oa2a2a23_x2 IS
-BEGIN
-  q <= (((i0 AND i1) OR (i2 AND i3)) OR (i4 AND i5));
-END RTL;
diff --git a/alliance/share/cells/sxlib/oa2a2a23_x4.al b/alliance/share/cells/sxlib/oa2a2a23_x4.al
deleted file mode 100644
index 5b478925..00000000
--- a/alliance/share/cells/sxlib/oa2a2a23_x4.al
+++ /dev/null
@@ -1,58 +0,0 @@
-V ALLIANCE : 6
-H oa2a2a23_x4,L,30/10/99
-C i0,IN,EXTERNAL,14
-C i1,IN,EXTERNAL,15
-C i2,IN,EXTERNAL,9
-C i3,IN,EXTERNAL,10
-C i4,IN,EXTERNAL,7
-C i5,IN,EXTERNAL,8
-C q,OUT,EXTERNAL,12
-C vdd,IN,EXTERNAL,13
-C vss,IN,EXTERNAL,1
-T P,0.35,5.9,12,4,13,0,0.75,0.75,13.3,13.3,15.6,11.25,tr_00016
-T P,0.35,5.9,13,4,12,0,0.75,0.75,13.3,13.3,17.4,11.25,tr_00015
-T P,0.35,5.9,13,14,5,0,0.75,0.75,13.3,13.3,13.8,11.25,tr_00014
-T P,0.35,5.9,5,15,13,0,0.75,0.75,13.3,13.3,12,11.25,tr_00013
-T P,0.35,5.9,5,10,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00012
-T P,0.35,5.9,6,9,5,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00011
-T P,0.35,5.9,4,8,6,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00010
-T P,0.35,5.9,6,7,4,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00009
-T N,0.35,2.9,12,4,1,0,0.75,0.75,7.3,7.3,15.6,2.25,tr_00008
-T N,0.35,2.9,12,4,1,0,0.75,0.75,7.3,7.3,17.4,2.25,tr_00007
-T N,0.35,2.9,1,14,11,0,0.75,0.75,7.3,7.3,13.8,2.25,tr_00006
-T N,0.35,2.9,11,15,4,0,0.75,0.75,7.3,7.3,12.6,2.25,tr_00005
-T N,0.35,2.9,3,8,1,0,0.75,0.75,7.3,7.3,2.4,2.25,tr_00004
-T N,0.35,2.9,1,9,2,0,0.75,0.75,7.3,7.3,6.6,2.25,tr_00003
-T N,0.35,2.9,4,7,3,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002
-T N,0.35,2.9,2,10,4,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00001
-S 15,EXTERNAL,i1
-Q 0.00247612
-S 14,EXTERNAL,i0
-Q 0.00232574
-S 13,EXTERNAL,vdd
-Q 0.00883149
-S 12,EXTERNAL,q
-Q 0.00264397
-S 11,INTERNAL
-Q 0
-S 10,EXTERNAL,i3
-Q 0.00262649
-S 9,EXTERNAL,i2
-Q 0.00254552
-S 8,EXTERNAL,i5
-Q 0.0027653
-S 7,EXTERNAL,i4
-Q 0.00304715
-S 6,INTERNAL
-Q 0.00199441
-S 5,INTERNAL
-Q 0.0021
-S 4,INTERNAL
-Q 0.00860414
-S 3,INTERNAL
-Q 0
-S 2,INTERNAL
-Q 0
-S 1,EXTERNAL,vss
-Q 0.00695133
-EOF
diff --git a/alliance/share/cells/sxlib/oa2a2a23_x4.ap b/alliance/share/cells/sxlib/oa2a2a23_x4.ap
deleted file mode 100644
index bef2d02c..00000000
--- a/alliance/share/cells/sxlib/oa2a2a23_x4.ap
+++ /dev/null
@@ -1,147 +0,0 @@
-V ALLIANCE : 6
-H oa2a2a23_x4,P,30/ 8/2000,100
-A 0,0,6500,5000
-R 4500,1500,ref_ref,i0_15
-R 4500,3000,ref_ref,i0_30
-R 4000,3000,ref_ref,i1_30
-R 4000,2500,ref_ref,i1_25
-R 4000,1500,ref_ref,i1_15
-R 4000,2000,ref_ref,i1_20
-R 4500,2500,ref_ref,i0_25
-R 4500,2000,ref_ref,i0_20
-R 5500,1000,ref_ref,q_10
-R 5500,1500,ref_ref,q_15
-R 5500,3500,ref_ref,q_35
-R 5500,3000,ref_ref,q_30
-R 5500,2500,ref_ref,q_25
-R 5500,2000,ref_ref,q_20
-R 1500,3500,ref_ref,i4_35
-R 1500,3000,ref_ref,i4_30
-R 1500,2500,ref_ref,i4_25
-R 1500,2000,ref_ref,i4_20
-R 1500,1500,ref_ref,i4_15
-R 2000,2000,ref_ref,i3_20
-R 2500,3000,ref_ref,i2_30
-R 2500,2500,ref_ref,i2_25
-R 2500,2000,ref_ref,i2_20
-R 2500,1500,ref_ref,i2_15
-R 2000,3000,ref_ref,i3_30
-R 2000,2500,ref_ref,i3_25
-R 2000,1500,ref_ref,i3_15
-R 1000,1500,ref_ref,i5_15
-R 1000,3000,ref_ref,i5_30
-R 1000,2500,ref_ref,i5_25
-R 1000,2000,ref_ref,i5_20
-R 5500,4000,ref_ref,q_40
-S 4000,1500,4000,3000,200,i1,DOWN,CALU1
-S 4500,1500,4500,3000,200,i0,DOWN,CALU1
-S 1500,1500,1500,3500,200,i4,DOWN,CALU1
-S 2500,1500,2500,3000,200,i2,DOWN,CALU1
-S 2000,1500,2000,3000,200,i3,DOWN,CALU1
-S 1000,1500,1000,3000,200,i5,DOWN,CALU1
-S 5500,1000,5500,4000,200,q,DOWN,CALU1
-S 5000,2000,5800,2000,100,*,RIGHT,POLY
-S 5800,1400,5800,2600,100,*,DOWN,POLY
-S 5200,1400,5200,2600,100,*,DOWN,POLY
-S 5000,1000,5000,2000,100,*,UP,ALU1
-S 500,1000,5000,1000,100,*,RIGHT,ALU1
-S 500,1000,500,3450,100,*,DOWN,ALU1
-S 500,3450,900,3450,100,*,LEFT,ALU1
-S 2700,2800,2700,4700,300,*,UP,PDIF
-S 2100,3500,4300,3500,100,*,RIGHT,ALU1
-S 4000,1400,4200,1400,100,*,LEFT,POLY
-S 4600,1400,4600,2600,100,*,DOWN,POLY
-S 4000,1400,4000,2500,100,*,UP,POLY
-S 4500,1500,4500,3000,100,*,UP,ALU1
-S 4000,1500,4000,3000,100,*,UP,ALU1
-S 5200,2600,5200,4900,100,*,UP,PTRANS
-S 5800,2600,5800,4900,100,*,UP,PTRANS
-S 5500,2800,5500,4700,300,*,UP,PDIF
-S 6100,2800,6100,4700,300,*,UP,PDIF
-S 4900,2800,4900,4700,300,*,UP,PDIF
-S 4300,2800,4300,4700,300,*,UP,PDIF
-S 4600,2600,4600,4900,100,*,UP,PTRANS
-S 4000,2600,4000,4900,100,*,UP,PTRANS
-S 3700,2800,3700,4100,300,*,UP,PDIF
-S 4900,300,4900,1200,300,*,DOWN,NDIF
-S 6100,300,6100,1200,300,*,DOWN,NDIF
-S 5500,300,5500,1200,300,*,DOWN,NDIF
-S 5200,100,5200,1400,100,*,UP,NTRANS
-S 5800,100,5800,1400,100,*,DOWN,NTRANS
-S 4600,100,4600,1400,100,*,UP,NTRANS
-S 4200,100,4200,1400,100,*,UP,NTRANS
-S 3900,300,3900,1200,300,*,DOWN,NDIF
-S 5500,950,5500,4050,200,*,DOWN,ALU1
-S 6100,300,6100,1000,200,*,DOWN,ALU1
-S 6100,3500,6100,4600,200,*,DOWN,ALU1
-S 3700,4000,3700,4700,200,*,UP,ALU1
-S 4300,3500,4300,4000,100,*,UP,ALU1
-S 4900,3500,4900,4600,200,*,DOWN,ALU1
-S 0,4700,6500,4700,600,vdd,RIGHT,CALU1
-S 0,300,6500,300,600,vss,RIGHT,CALU1
-S 0,3900,6500,3900,2400,*,RIGHT,NWELL
-S 1500,1500,1500,3500,100,*,UP,ALU1
-S 800,1400,900,1400,100,*,LEFT,POLY
-S 500,300,500,1200,300,*,DOWN,NDIF
-S 800,100,800,1400,100,*,UP,NTRANS
-S 2200,1400,2400,1400,100,*,RIGHT,POLY
-S 2200,100,2200,1400,100,*,UP,NTRANS
-S 2500,300,2500,1200,300,*,DOWN,NDIF
-S 900,1400,900,2600,100,*,DOWN,POLY
-S 600,2600,900,2600,100,*,RIGHT,POLY
-S 1200,2600,1400,2600,100,*,LEFT,POLY
-S 1400,1400,1400,2600,100,*,UP,POLY
-S 1200,1400,1400,1400,100,*,RIGHT,POLY
-S 1800,1400,1900,1400,100,*,LEFT,POLY
-S 1900,1400,1900,2600,100,*,DOWN,POLY
-S 1800,2600,1900,2600,100,*,RIGHT,POLY
-S 2500,1500,2500,3000,100,*,UP,ALU1
-S 2000,1500,2000,3000,100,*,UP,ALU1
-S 1000,1500,1000,3000,100,*,UP,ALU1
-S 300,2800,300,4700,300,*,UP,PDIF
-S 1800,2600,1800,4900,100,*,UP,PTRANS
-S 2400,2600,2400,4900,100,*,UP,PTRANS
-S 600,2600,600,4900,100,*,UP,PTRANS
-S 1200,2600,1200,4900,100,*,UP,PTRANS
-S 1500,2800,1500,4700,300,*,UP,PDIF
-S 900,2800,900,4700,300,*,UP,PDIF
-S 2100,2800,2100,4700,300,*,UP,PDIF
-S 1200,100,1200,1400,100,*,UP,NTRANS
-S 1500,300,1500,1200,300,*,DOWN,NDIF
-S 1800,100,1800,1400,100,*,UP,NTRANS
-S 2400,1400,2400,2600,100,*,DOWN,POLY
-S 300,4000,2700,4000,100,*,RIGHT,ALU1
-V 5000,2000,CONT_POLY,*
-V 3300,4600,CONT_BODY_N,*
-V 3200,400,CONT_BODY_P,*
-V 4000,2500,CONT_POLY,*
-V 4500,2500,CONT_POLY,*
-V 6100,3500,CONT_DIF_P,*
-V 6100,4500,CONT_DIF_P,*
-V 6100,4000,CONT_DIF_P,*
-V 5500,3000,CONT_DIF_P,*
-V 5500,3500,CONT_DIF_P,*
-V 5500,4000,CONT_DIF_P,*
-V 4900,4000,CONT_DIF_P,*
-V 4900,4500,CONT_DIF_P,*
-V 4900,3500,CONT_DIF_P,*
-V 4300,4000,CONT_DIF_P,*
-V 3700,4000,CONT_DIF_P,*
-V 6100,500,CONT_DIF_N,*
-V 6100,1000,CONT_DIF_N,*
-V 5500,1000,CONT_DIF_N,*
-V 4900,500,CONT_DIF_N,*
-V 3900,1000,CONT_DIF_N,*
-V 500,500,CONT_DIF_N,*
-V 2500,500,CONT_DIF_N,*
-V 1000,2000,CONT_POLY,*
-V 1500,2000,CONT_POLY,*
-V 2000,2500,CONT_POLY,*
-V 2500,2500,CONT_POLY,*
-V 2700,4000,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 300,4000,CONT_DIF_P,*
-V 2100,3500,CONT_DIF_P,*
-V 900,3500,CONT_DIF_P,*
-V 1500,1000,CONT_DIF_N,*
-EOF
diff --git a/alliance/share/cells/sxlib/oa2a2a23_x4.sym b/alliance/share/cells/sxlib/oa2a2a23_x4.sym
deleted file mode 100644
index 19dec265..00000000
Binary files a/alliance/share/cells/sxlib/oa2a2a23_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/oa2a2a23_x4.vbe b/alliance/share/cells/sxlib/oa2a2a23_x4.vbe
deleted file mode 100644
index c39f56f9..00000000
--- a/alliance/share/cells/sxlib/oa2a2a23_x4.vbe
+++ /dev/null
@@ -1,56 +0,0 @@
-ENTITY oa2a2a23_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 3250;
-  CONSTANT cin_i0	 : NATURAL := 13;
-  CONSTANT cin_i1	 : NATURAL := 14;
-  CONSTANT cin_i2	 : NATURAL := 14;
-  CONSTANT cin_i3	 : NATURAL := 14;
-  CONSTANT cin_i4	 : NATURAL := 14;
-  CONSTANT cin_i5	 : NATURAL := 14;
-  CONSTANT rdown_i0_q	 : NATURAL := 810;
-  CONSTANT rdown_i1_q	 : NATURAL := 810;
-  CONSTANT rdown_i2_q	 : NATURAL := 810;
-  CONSTANT rdown_i3_q	 : NATURAL := 810;
-  CONSTANT rdown_i4_q	 : NATURAL := 810;
-  CONSTANT rdown_i5_q	 : NATURAL := 810;
-  CONSTANT rup_i0_q	 : NATURAL := 890;
-  CONSTANT rup_i1_q	 : NATURAL := 890;
-  CONSTANT rup_i2_q	 : NATURAL := 890;
-  CONSTANT rup_i3_q	 : NATURAL := 890;
-  CONSTANT rup_i4_q	 : NATURAL := 890;
-  CONSTANT rup_i5_q	 : NATURAL := 890;
-  CONSTANT tphh_i5_q	 : NATURAL := 379;
-  CONSTANT tphh_i4_q	 : NATURAL := 464;
-  CONSTANT tphh_i2_q	 : NATURAL := 493;
-  CONSTANT tphh_i3_q	 : NATURAL := 594;
-  CONSTANT tpll_i1_q	 : NATURAL := 613;
-  CONSTANT tpll_i0_q	 : NATURAL := 648;
-  CONSTANT tpll_i4_q	 : NATURAL := 673;
-  CONSTANT tpll_i3_q	 : NATURAL := 677;
-  CONSTANT tphh_i0_q	 : NATURAL := 699;
-  CONSTANT tpll_i5_q	 : NATURAL := 714;
-  CONSTANT tpll_i2_q	 : NATURAL := 715;
-  CONSTANT tphh_i1_q	 : NATURAL := 822;
-  CONSTANT transistors	 : NATURAL := 16
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  i3	 : in  BIT;
-  i4	 : in  BIT;
-  i5	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END oa2a2a23_x4;
-
-ARCHITECTURE behaviour_data_flow OF oa2a2a23_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on oa2a2a23_x4"
-  SEVERITY WARNING;
-  q <= (((i0 and i1) or (i2 and i3)) or (i4 and i5)) after 1400 ps;
-END;
diff --git a/alliance/share/cells/sxlib/oa2a2a23_x4.vhd b/alliance/share/cells/sxlib/oa2a2a23_x4.vhd
deleted file mode 100644
index 61d3a82a..00000000
--- a/alliance/share/cells/sxlib/oa2a2a23_x4.vhd
+++ /dev/null
@@ -1,24 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY oa2a2a23_x4 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  i3	: IN STD_LOGIC;
-  i4	: IN STD_LOGIC;
-  i5	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END oa2a2a23_x4;
-
-ARCHITECTURE RTL OF oa2a2a23_x4 IS
-BEGIN
-  q <= (((i0 AND i1) OR (i2 AND i3)) OR (i4 AND i5));
-END RTL;
diff --git a/alliance/share/cells/sxlib/oa2a2a2a24_x2.al b/alliance/share/cells/sxlib/oa2a2a2a24_x2.al
deleted file mode 100644
index 56c387c7..00000000
--- a/alliance/share/cells/sxlib/oa2a2a2a24_x2.al
+++ /dev/null
@@ -1,70 +0,0 @@
-V ALLIANCE : 6
-H oa2a2a2a24_x2,L,30/10/99
-C i0,IN,EXTERNAL,19
-C i1,IN,EXTERNAL,17
-C i2,IN,EXTERNAL,15
-C i3,IN,EXTERNAL,16
-C i4,IN,EXTERNAL,10
-C i5,IN,EXTERNAL,9
-C i6,IN,EXTERNAL,8
-C i7,IN,EXTERNAL,7
-C q,OUT,EXTERNAL,18
-C vdd,IN,EXTERNAL,14
-C vss,IN,EXTERNAL,4
-T P,0.35,5.9,18,1,14,0,0.75,0.75,13.3,13.3,20.4,11.25,tr_00018
-T P,0.35,5.9,13,17,14,0,0.75,0.75,13.3,13.3,16.8,11.25,tr_00017
-T P,0.35,5.9,14,19,13,0,0.75,0.75,13.3,13.3,18.6,11.25,tr_00016
-T P,0.35,5.9,13,16,6,0,0.75,0.75,13.3,13.3,10.8,11.25,tr_00015
-T P,0.35,5.9,1,7,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00014
-T P,0.35,5.9,6,15,13,0,0.75,0.75,13.3,13.3,12.6,11.25,tr_00013
-T P,0.35,5.9,6,10,5,0,0.75,0.75,13.3,13.3,9,11.25,tr_00012
-T P,0.35,5.9,5,9,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00011
-T P,0.35,5.9,5,8,1,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00010
-T N,0.35,2.9,3,9,4,0,0.75,0.75,7.3,7.3,7.8,2.25,tr_00009
-T N,0.35,2.9,4,15,12,0,0.75,0.75,7.3,7.3,12,2.25,tr_00008
-T N,0.35,2.9,11,17,1,0,0.75,0.75,7.3,7.3,17.4,2.25,tr_00007
-T N,0.35,2.9,4,19,11,0,0.75,0.75,7.3,7.3,18.6,2.25,tr_00006
-T N,0.35,2.9,18,1,4,0,0.75,0.75,7.3,7.3,20.4,2.25,tr_00005
-T N,0.35,2.9,1,10,3,0,0.75,0.75,7.3,7.3,9,2.25,tr_00004
-T N,0.35,2.9,12,16,1,0,0.75,0.75,7.3,7.3,10.8,2.25,tr_00003
-T N,0.35,2.9,1,8,2,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002
-T N,0.35,2.9,2,7,4,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00001
-S 19,EXTERNAL,i0
-Q 0.00261741
-S 18,EXTERNAL,q
-Q 0.00264397
-S 17,EXTERNAL,i1
-Q 0.00210054
-S 16,EXTERNAL,i3
-Q 0.00232574
-S 15,EXTERNAL,i2
-Q 0.00254552
-S 14,EXTERNAL,vdd
-Q 0.00769303
-S 13,INTERNAL
-Q 0.00198726
-S 12,INTERNAL
-Q 0
-S 11,INTERNAL
-Q 0
-S 10,EXTERNAL,i4
-Q 0.00232574
-S 9,EXTERNAL,i5
-Q 0.00232574
-S 8,EXTERNAL,i6
-Q 0.00269068
-S 7,EXTERNAL,i7
-Q 0.00260759
-S 6,INTERNAL
-Q 0.00256527
-S 5,INTERNAL
-Q 0.00324886
-S 4,EXTERNAL,vss
-Q 0.00692922
-S 3,INTERNAL
-Q 0
-S 2,INTERNAL
-Q 0
-S 1,INTERNAL
-Q 0.00855851
-EOF
diff --git a/alliance/share/cells/sxlib/oa2a2a2a24_x2.ap b/alliance/share/cells/sxlib/oa2a2a2a24_x2.ap
deleted file mode 100644
index 4f989559..00000000
--- a/alliance/share/cells/sxlib/oa2a2a2a24_x2.ap
+++ /dev/null
@@ -1,171 +0,0 @@
-V ALLIANCE : 6
-H oa2a2a2a24_x2,P,30/ 8/2000,100
-A 0,0,7500,5000
-R 6500,3500,ref_ref,i0_35
-R 5500,2000,ref_ref,i1_20
-R 5500,2500,ref_ref,i1_25
-R 5500,3000,ref_ref,i1_30
-R 5500,1500,ref_ref,i1_15
-R 6500,1500,ref_ref,i0_15
-R 6500,2000,ref_ref,i0_20
-R 6500,2500,ref_ref,i0_25
-R 6500,3000,ref_ref,i0_30
-R 7000,1000,ref_ref,q_10
-R 7000,4000,ref_ref,q_40
-R 7000,2000,ref_ref,q_20
-R 7000,1500,ref_ref,q_15
-R 7000,3500,ref_ref,q_35
-R 7000,3000,ref_ref,q_30
-R 7000,2500,ref_ref,q_25
-R 500,1000,ref_ref,i7_10
-R 500,1500,ref_ref,i7_15
-R 500,2000,ref_ref,i7_20
-R 500,2500,ref_ref,i7_25
-R 500,3000,ref_ref,i7_30
-R 1500,1500,ref_ref,i6_15
-R 1500,2000,ref_ref,i6_20
-R 1500,2500,ref_ref,i6_25
-R 1500,3000,ref_ref,i6_30
-R 2500,1500,ref_ref,i5_15
-R 2500,2000,ref_ref,i5_20
-R 2500,2500,ref_ref,i5_25
-R 2500,3000,ref_ref,i5_30
-R 3000,1500,ref_ref,i4_15
-R 3000,2000,ref_ref,i4_20
-R 3000,2500,ref_ref,i4_25
-R 3000,3000,ref_ref,i4_30
-R 3500,1500,ref_ref,i3_15
-R 3500,2000,ref_ref,i3_20
-R 3500,2500,ref_ref,i3_25
-R 3500,3000,ref_ref,i3_30
-R 4000,1500,ref_ref,i2_15
-R 4000,2000,ref_ref,i2_20
-R 4000,2500,ref_ref,i2_25
-R 4000,3000,ref_ref,i2_30
-S 5500,1500,5500,3000,200,i1,DOWN,CALU1
-S 6500,1500,6500,3500,200,i0,DOWN,CALU1
-S 7000,1000,7000,4000,200,q,DOWN,CALU1
-S 500,1000,500,3000,200,i7,DOWN,CALU1
-S 1500,1500,1500,3000,200,i6,DOWN,CALU1
-S 2500,1500,2500,3000,200,i5,DOWN,CALU1
-S 3000,1500,3000,3000,200,i4,DOWN,CALU1
-S 3500,1500,3500,3000,200,i3,DOWN,CALU1
-S 4000,1500,4000,3000,200,i2,DOWN,CALU1
-S 6500,1500,6500,3500,100,*,UP,ALU1
-S 5500,1500,5700,1500,200,*,RIGHT,ALU1
-S 5500,1500,5500,3000,100,*,UP,ALU1
-S 4800,1000,4800,2000,100,*,UP,ALU1
-S 6300,1500,6500,1500,200,*,RIGHT,ALU1
-S 6300,2500,6500,2500,200,*,RIGHT,ALU1
-S 7000,950,7000,4050,200,*,DOWN,ALU1
-S 1000,1000,5500,1000,100,*,RIGHT,ALU1
-S 4000,2600,4200,2600,100,*,LEFT,POLY
-S 4000,1400,4000,2600,100,*,DOWN,POLY
-S 2600,1400,2600,2600,100,*,DOWN,POLY
-S 2600,100,2600,1400,100,*,UP,NTRANS
-S 2300,300,2300,1200,300,*,DOWN,NDIF
-S 4000,100,4000,1400,100,*,UP,NTRANS
-S 4300,300,4300,1200,300,*,DOWN,NDIF
-S 5800,100,5800,1400,100,*,UP,NTRANS
-S 5500,300,5500,1200,300,*,DOWN,NDIF
-S 5300,4000,5300,4600,200,*,DOWN,ALU1
-S 6500,4000,6500,4600,200,*,DOWN,ALU1
-S 5900,3500,5900,4000,100,*,UP,ALU1
-S 3900,3500,5900,3500,100,*,RIGHT,ALU1
-S 5300,2800,5300,4200,300,*,UP,PDIF
-S 4500,2800,4500,4200,300,*,UP,PDIF
-S 7100,2800,7100,4700,300,*,UP,PDIF
-S 6800,2600,6800,4900,100,*,UP,PTRANS
-S 6500,2800,6500,4700,300,*,UP,PDIF
-S 5600,2600,5600,4900,100,*,UP,PTRANS
-S 6200,2600,6200,4900,100,*,UP,PTRANS
-S 5900,2800,5900,4700,300,*,UP,PDIF
-S 6500,300,6500,1200,300,*,DOWN,NDIF
-S 6200,100,6200,1400,100,*,UP,NTRANS
-S 7100,300,7100,1200,300,*,DOWN,NDIF
-S 6800,100,6800,1400,100,*,UP,NTRANS
-S 6800,1400,6800,2600,100,*,DOWN,POLY
-S 1000,1000,1000,3500,100,*,DOWN,ALU1
-S 900,3500,1000,3500,100,*,RIGHT,ALU1
-S 300,3500,300,4000,100,*,UP,ALU1
-S 3300,3500,3300,4000,100,*,UP,ALU1
-S 1200,2500,1500,2500,300,*,LEFT,POLY
-S 500,1000,500,3000,100,*,UP,ALU1
-S 4000,1500,4000,3000,100,*,UP,ALU1
-S 3500,1500,3500,3000,100,*,UP,ALU1
-S 3000,1500,3000,3000,100,*,UP,ALU1
-S 2500,1500,2500,3000,100,*,UP,ALU1
-S 1500,1500,1500,3000,100,*,UP,ALU1
-S 300,2800,300,4700,300,*,UP,PDIF
-S 3600,2600,3600,4900,100,*,UP,PTRANS
-S 2100,2800,2100,4700,300,*,UP,PDIF
-S 600,2600,600,4900,100,*,UP,PTRANS
-S 1500,2800,1500,4700,300,*,UP,PDIF
-S 900,2800,900,4700,300,*,UP,PDIF
-S 4200,2600,4200,4900,100,*,UP,PTRANS
-S 3900,2800,3900,4700,300,*,UP,PDIF
-S 2700,2800,2700,4700,300,*,UP,PDIF
-S 3300,2800,3300,4700,300,*,UP,PDIF
-S 3000,2600,3000,4900,100,*,UP,PTRANS
-S 2400,2600,2400,4900,100,*,UP,PTRANS
-S 1200,2600,1200,4900,100,*,UP,PTRANS
-S 1500,3500,2700,3500,100,*,RIGHT,ALU1
-S 2100,4000,4500,4000,100,*,RIGHT,ALU1
-S 300,4000,1500,4000,100,*,RIGHT,ALU1
-S 1500,3500,1500,4000,100,*,DOWN,ALU1
-S 1200,1400,1200,2600,100,*,DOWN,POLY
-S 3000,1400,3000,2600,100,*,DOWN,POLY
-S 600,1400,600,2600,100,*,DOWN,POLY
-S 3600,1400,3600,2600,100,*,DOWN,POLY
-S 3300,300,3300,1200,300,*,DOWN,NDIF
-S 3000,100,3000,1400,100,*,UP,NTRANS
-S 3600,100,3600,1400,100,*,UP,NTRANS
-S 1200,100,1200,1400,100,*,UP,NTRANS
-S 1500,300,1500,1200,300,*,DOWN,NDIF
-S 900,300,900,1200,300,*,DOWN,NDIF
-S 600,100,600,1400,100,*,UP,NTRANS
-S 300,300,300,1200,300,*,DOWN,NDIF
-S 4800,2000,6800,2000,100,*,RIGHT,POLY
-S 0,300,7500,300,600,vss,RIGHT,CALU1
-S 0,3900,7500,3900,2400,*,RIGHT,NWELL
-S 0,4700,7500,4700,600,vdd,RIGHT,CALU1
-V 5700,1500,CONT_POLY,*
-V 5500,2500,CONT_POLY,*
-V 4800,2000,CONT_POLY,*
-V 6300,2500,CONT_POLY,*
-V 6300,1500,CONT_POLY,*
-V 4900,400,CONT_BODY_P,*
-V 2300,500,CONT_DIF_N,*
-V 4300,500,CONT_DIF_N,*
-V 5500,1000,CONT_DIF_N,*
-V 5300,4000,CONT_DIF_P,*
-V 5900,4000,CONT_DIF_P,*
-V 3900,3500,CONT_DIF_P,*
-V 4900,4700,CONT_BODY_N,*
-V 7100,3000,CONT_DIF_P,*
-V 7100,3500,CONT_DIF_P,*
-V 6500,4500,CONT_DIF_P,*
-V 7100,4000,CONT_DIF_P,*
-V 6500,4000,CONT_DIF_P,*
-V 6500,500,CONT_DIF_N,*
-V 7100,1000,CONT_DIF_N,*
-V 1500,3500,CONT_DIF_P,*
-V 300,3500,CONT_DIF_P,*
-V 3300,3500,CONT_DIF_P,*
-V 4000,2500,CONT_POLY,*
-V 3500,2500,CONT_POLY,*
-V 3000,2500,CONT_POLY,*
-V 2500,2500,CONT_POLY,*
-V 1500,2500,CONT_POLY,*
-V 500,2500,CONT_POLY,*
-V 300,4000,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 2100,4000,CONT_DIF_P,*
-V 3300,4000,CONT_DIF_P,*
-V 4500,4000,CONT_DIF_P,*
-V 2700,3500,CONT_DIF_P,*
-V 900,3500,CONT_DIF_P,*
-V 300,500,CONT_DIF_N,*
-V 1500,1000,CONT_DIF_N,*
-V 3300,1000,CONT_DIF_N,*
-EOF
diff --git a/alliance/share/cells/sxlib/oa2a2a2a24_x2.sym b/alliance/share/cells/sxlib/oa2a2a2a24_x2.sym
deleted file mode 100644
index f3db5d90..00000000
Binary files a/alliance/share/cells/sxlib/oa2a2a2a24_x2.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/oa2a2a2a24_x2.vbe b/alliance/share/cells/sxlib/oa2a2a2a24_x2.vbe
deleted file mode 100644
index 39a24492..00000000
--- a/alliance/share/cells/sxlib/oa2a2a2a24_x2.vbe
+++ /dev/null
@@ -1,68 +0,0 @@
-ENTITY oa2a2a2a24_x2 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 3750;
-  CONSTANT cin_i0	 : NATURAL := 14;
-  CONSTANT cin_i1	 : NATURAL := 13;
-  CONSTANT cin_i2	 : NATURAL := 14;
-  CONSTANT cin_i3	 : NATURAL := 13;
-  CONSTANT cin_i4	 : NATURAL := 13;
-  CONSTANT cin_i5	 : NATURAL := 13;
-  CONSTANT cin_i6	 : NATURAL := 14;
-  CONSTANT cin_i7	 : NATURAL := 14;
-  CONSTANT rdown_i0_q	 : NATURAL := 1620;
-  CONSTANT rdown_i1_q	 : NATURAL := 1620;
-  CONSTANT rdown_i2_q	 : NATURAL := 1620;
-  CONSTANT rdown_i3_q	 : NATURAL := 1620;
-  CONSTANT rdown_i4_q	 : NATURAL := 1620;
-  CONSTANT rdown_i5_q	 : NATURAL := 1620;
-  CONSTANT rdown_i6_q	 : NATURAL := 1620;
-  CONSTANT rdown_i7_q	 : NATURAL := 1620;
-  CONSTANT rup_i0_q	 : NATURAL := 1790;
-  CONSTANT rup_i1_q	 : NATURAL := 1790;
-  CONSTANT rup_i2_q	 : NATURAL := 1790;
-  CONSTANT rup_i3_q	 : NATURAL := 1790;
-  CONSTANT rup_i4_q	 : NATURAL := 1790;
-  CONSTANT rup_i5_q	 : NATURAL := 1790;
-  CONSTANT rup_i6_q	 : NATURAL := 1790;
-  CONSTANT rup_i7_q	 : NATURAL := 1790;
-  CONSTANT tphh_i7_q	 : NATURAL := 346;
-  CONSTANT tphh_i6_q	 : NATURAL := 426;
-  CONSTANT tphh_i5_q	 : NATURAL := 467;
-  CONSTANT tphh_i4_q	 : NATURAL := 565;
-  CONSTANT tphh_i2_q	 : NATURAL := 682;
-  CONSTANT tpll_i6_q	 : NATURAL := 748;
-  CONSTANT tpll_i1_q	 : NATURAL := 753;
-  CONSTANT tphh_i0_q	 : NATURAL := 780;
-  CONSTANT tpll_i0_q	 : NATURAL := 797;
-  CONSTANT tpll_i7_q	 : NATURAL := 800;
-  CONSTANT tphh_i3_q	 : NATURAL := 803;
-  CONSTANT tpll_i3_q	 : NATURAL := 810;
-  CONSTANT tpll_i4_q	 : NATURAL := 813;
-  CONSTANT tpll_i2_q	 : NATURAL := 856;
-  CONSTANT tpll_i5_q	 : NATURAL := 861;
-  CONSTANT tphh_i1_q	 : NATURAL := 909;
-  CONSTANT transistors	 : NATURAL := 18
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  i3	 : in  BIT;
-  i4	 : in  BIT;
-  i5	 : in  BIT;
-  i6	 : in  BIT;
-  i7	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END oa2a2a2a24_x2;
-
-ARCHITECTURE behaviour_data_flow OF oa2a2a2a24_x2 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on oa2a2a2a24_x2"
-  SEVERITY WARNING;
-  q <= ((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and i7)) after 1500 ps;
-END;
diff --git a/alliance/share/cells/sxlib/oa2a2a2a24_x2.vhd b/alliance/share/cells/sxlib/oa2a2a2a24_x2.vhd
deleted file mode 100644
index 3615b807..00000000
--- a/alliance/share/cells/sxlib/oa2a2a2a24_x2.vhd
+++ /dev/null
@@ -1,26 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY oa2a2a2a24_x2 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  i3	: IN STD_LOGIC;
-  i4	: IN STD_LOGIC;
-  i5	: IN STD_LOGIC;
-  i6	: IN STD_LOGIC;
-  i7	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END oa2a2a2a24_x2;
-
-ARCHITECTURE RTL OF oa2a2a2a24_x2 IS
-BEGIN
-  q <= ((((i0 AND i1) OR (i2 AND i3)) OR (i4 AND i5)) OR (i6 AND i7));
-END RTL;
diff --git a/alliance/share/cells/sxlib/oa2a2a2a24_x4.al b/alliance/share/cells/sxlib/oa2a2a2a24_x4.al
deleted file mode 100644
index 08c8f70f..00000000
--- a/alliance/share/cells/sxlib/oa2a2a2a24_x4.al
+++ /dev/null
@@ -1,72 +0,0 @@
-V ALLIANCE : 6
-H oa2a2a2a24_x4,L,30/10/99
-C i0,IN,EXTERNAL,19
-C i1,IN,EXTERNAL,17
-C i2,IN,EXTERNAL,15
-C i3,IN,EXTERNAL,16
-C i4,IN,EXTERNAL,7
-C i5,IN,EXTERNAL,8
-C i6,IN,EXTERNAL,9
-C i7,IN,EXTERNAL,10
-C q,OUT,EXTERNAL,18
-C vdd,IN,EXTERNAL,14
-C vss,IN,EXTERNAL,3
-T P,0.35,5.9,5,9,2,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00020
-T P,0.35,5.9,5,8,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00019
-T P,0.35,5.9,6,7,5,0,0.75,0.75,13.3,13.3,9,11.25,tr_00018
-T P,0.35,5.9,6,15,13,0,0.75,0.75,13.3,13.3,12.6,11.25,tr_00017
-T P,0.35,5.9,2,10,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00016
-T P,0.35,5.9,13,16,6,0,0.75,0.75,13.3,13.3,10.8,11.25,tr_00015
-T P,0.35,5.9,14,19,13,0,0.75,0.75,13.3,13.3,18.6,11.25,tr_00014
-T P,0.35,5.9,13,17,14,0,0.75,0.75,13.3,13.3,16.8,11.25,tr_00013
-T P,0.35,5.9,14,2,18,0,0.75,0.75,13.3,13.3,22.2,11.25,tr_00012
-T P,0.35,5.9,18,2,14,0,0.75,0.75,13.3,13.3,20.4,11.25,tr_00011
-T N,0.35,2.9,1,10,3,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00010
-T N,0.35,2.9,2,9,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00009
-T N,0.35,2.9,12,16,2,0,0.75,0.75,7.3,7.3,10.8,2.25,tr_00008
-T N,0.35,2.9,2,7,4,0,0.75,0.75,7.3,7.3,9,2.25,tr_00007
-T N,0.35,2.9,18,2,3,0,0.75,0.75,7.3,7.3,20.4,2.25,tr_00006
-T N,0.35,2.9,3,19,11,0,0.75,0.75,7.3,7.3,18.6,2.25,tr_00005
-T N,0.35,2.9,18,2,3,0,0.75,0.75,7.3,7.3,22.2,2.25,tr_00004
-T N,0.35,2.9,11,17,2,0,0.75,0.75,7.3,7.3,17.4,2.25,tr_00003
-T N,0.35,2.9,3,15,12,0,0.75,0.75,7.3,7.3,12,2.25,tr_00002
-T N,0.35,2.9,4,8,3,0,0.75,0.75,7.3,7.3,7.8,2.25,tr_00001
-S 19,EXTERNAL,i0
-Q 0.00261741
-S 18,EXTERNAL,q
-Q 0.00264397
-S 17,EXTERNAL,i1
-Q 0.00210054
-S 16,EXTERNAL,i3
-Q 0.00232574
-S 15,EXTERNAL,i2
-Q 0.00254552
-S 14,EXTERNAL,vdd
-Q 0.00932712
-S 13,INTERNAL
-Q 0.00198726
-S 12,INTERNAL
-Q 0
-S 11,INTERNAL
-Q 0
-S 10,EXTERNAL,i7
-Q 0.00260759
-S 9,EXTERNAL,i6
-Q 0.00269068
-S 8,EXTERNAL,i5
-Q 0.00232574
-S 7,EXTERNAL,i4
-Q 0.00232574
-S 6,INTERNAL
-Q 0.00256527
-S 5,INTERNAL
-Q 0.00324886
-S 4,INTERNAL
-Q 0
-S 3,EXTERNAL,vss
-Q 0.00815202
-S 2,INTERNAL
-Q 0.00988877
-S 1,INTERNAL
-Q 0
-EOF
diff --git a/alliance/share/cells/sxlib/oa2a2a2a24_x4.ap b/alliance/share/cells/sxlib/oa2a2a2a24_x4.ap
deleted file mode 100644
index 306d765a..00000000
--- a/alliance/share/cells/sxlib/oa2a2a2a24_x4.ap
+++ /dev/null
@@ -1,183 +0,0 @@
-V ALLIANCE : 6
-H oa2a2a2a24_x4,P,30/ 8/2000,100
-A 0,0,8000,5000
-R 4000,3000,ref_ref,i2_30
-R 4000,2500,ref_ref,i2_25
-R 4000,2000,ref_ref,i2_20
-R 4000,1500,ref_ref,i2_15
-R 3500,3000,ref_ref,i3_30
-R 3500,2500,ref_ref,i3_25
-R 3500,2000,ref_ref,i3_20
-R 3500,1500,ref_ref,i3_15
-R 3000,3000,ref_ref,i4_30
-R 3000,2500,ref_ref,i4_25
-R 3000,2000,ref_ref,i4_20
-R 3000,1500,ref_ref,i4_15
-R 2500,3000,ref_ref,i5_30
-R 2500,2500,ref_ref,i5_25
-R 2500,2000,ref_ref,i5_20
-R 2500,1500,ref_ref,i5_15
-R 1500,3000,ref_ref,i6_30
-R 1500,2500,ref_ref,i6_25
-R 1500,2000,ref_ref,i6_20
-R 1500,1500,ref_ref,i6_15
-R 500,3000,ref_ref,i7_30
-R 500,2500,ref_ref,i7_25
-R 500,2000,ref_ref,i7_20
-R 500,1500,ref_ref,i7_15
-R 500,1000,ref_ref,i7_10
-R 7000,2500,ref_ref,q_25
-R 7000,3000,ref_ref,q_30
-R 7000,3500,ref_ref,q_35
-R 7000,1500,ref_ref,q_15
-R 7000,2000,ref_ref,q_20
-R 7000,4000,ref_ref,q_40
-R 7000,1000,ref_ref,q_10
-R 6500,3000,ref_ref,i0_30
-R 6500,2500,ref_ref,i0_25
-R 6500,2000,ref_ref,i0_20
-R 6500,1500,ref_ref,i0_15
-R 5500,1500,ref_ref,i1_15
-R 5500,3000,ref_ref,i1_30
-R 5500,2500,ref_ref,i1_25
-R 5500,2000,ref_ref,i1_20
-R 6500,3500,ref_ref,i0_35
-S 4000,1500,4000,3000,200,i2,DOWN,CALU1
-S 3500,1500,3500,3000,200,i3,DOWN,CALU1
-S 3000,1500,3000,3000,200,i4,DOWN,CALU1
-S 2500,1500,2500,3000,200,i5,DOWN,CALU1
-S 1500,1500,1500,3000,200,i6,DOWN,CALU1
-S 500,1000,500,3000,200,i7,DOWN,CALU1
-S 7000,1000,7000,4000,200,q,DOWN,CALU1
-S 5500,1500,5500,3000,200,i1,DOWN,CALU1
-S 6500,1500,6500,3500,200,i0,DOWN,CALU1
-S 300,300,300,1200,300,*,DOWN,NDIF
-S 600,100,600,1400,100,*,UP,NTRANS
-S 900,300,900,1200,300,*,DOWN,NDIF
-S 1500,300,1500,1200,300,*,DOWN,NDIF
-S 1200,100,1200,1400,100,*,UP,NTRANS
-S 3600,100,3600,1400,100,*,UP,NTRANS
-S 3000,100,3000,1400,100,*,UP,NTRANS
-S 3300,300,3300,1200,300,*,DOWN,NDIF
-S 3600,1400,3600,2600,100,*,DOWN,POLY
-S 600,1400,600,2600,100,*,DOWN,POLY
-S 3000,1400,3000,2600,100,*,DOWN,POLY
-S 1200,1400,1200,2600,100,*,DOWN,POLY
-S 1500,3500,1500,4000,100,*,DOWN,ALU1
-S 300,4000,1500,4000,100,*,RIGHT,ALU1
-S 2100,4000,4500,4000,100,*,RIGHT,ALU1
-S 1500,3500,2700,3500,100,*,RIGHT,ALU1
-S 1200,2600,1200,4900,100,*,UP,PTRANS
-S 2400,2600,2400,4900,100,*,UP,PTRANS
-S 3000,2600,3000,4900,100,*,UP,PTRANS
-S 3300,2800,3300,4700,300,*,UP,PDIF
-S 2700,2800,2700,4700,300,*,UP,PDIF
-S 3900,2800,3900,4700,300,*,UP,PDIF
-S 4200,2600,4200,4900,100,*,UP,PTRANS
-S 900,2800,900,4700,300,*,UP,PDIF
-S 1500,2800,1500,4700,300,*,UP,PDIF
-S 600,2600,600,4900,100,*,UP,PTRANS
-S 2100,2800,2100,4700,300,*,UP,PDIF
-S 3600,2600,3600,4900,100,*,UP,PTRANS
-S 300,2800,300,4700,300,*,UP,PDIF
-S 1500,1500,1500,3000,100,*,UP,ALU1
-S 2500,1500,2500,3000,100,*,UP,ALU1
-S 3000,1500,3000,3000,100,*,UP,ALU1
-S 3500,1500,3500,3000,100,*,UP,ALU1
-S 4000,1500,4000,3000,100,*,UP,ALU1
-S 500,1000,500,3000,100,*,UP,ALU1
-S 1200,2500,1500,2500,300,*,LEFT,POLY
-S 3300,3500,3300,4000,100,*,UP,ALU1
-S 300,3500,300,4000,100,*,UP,ALU1
-S 0,300,8000,300,600,vss,RIGHT,CALU1
-S 0,3900,8000,3900,2400,*,RIGHT,NWELL
-S 0,4700,8000,4700,600,vdd,RIGHT,CALU1
-S 900,3500,1000,3500,100,*,RIGHT,ALU1
-S 1000,1000,1000,3500,100,*,DOWN,ALU1
-S 7700,3500,7700,4600,200,*,DOWN,ALU1
-S 7700,300,7700,1000,200,*,DOWN,ALU1
-S 7400,1400,7400,2600,100,*,DOWN,POLY
-S 6800,1400,6800,2600,100,*,DOWN,POLY
-S 6800,100,6800,1400,100,*,UP,NTRANS
-S 7100,300,7100,1200,300,*,DOWN,NDIF
-S 6200,100,6200,1400,100,*,UP,NTRANS
-S 7700,300,7700,1200,300,*,DOWN,NDIF
-S 6500,300,6500,1200,300,*,DOWN,NDIF
-S 7400,100,7400,1400,100,*,DOWN,NTRANS
-S 5900,2800,5900,4700,300,*,UP,PDIF
-S 6200,2600,6200,4900,100,*,UP,PTRANS
-S 5600,2600,5600,4900,100,*,UP,PTRANS
-S 7400,2600,7400,4900,100,*,UP,PTRANS
-S 6500,2800,6500,4700,300,*,UP,PDIF
-S 6800,2600,6800,4900,100,*,UP,PTRANS
-S 7700,2800,7700,4700,300,*,UP,PDIF
-S 7100,2800,7100,4700,300,*,UP,PDIF
-S 4500,2800,4500,4200,300,*,UP,PDIF
-S 5300,2800,5300,4200,300,*,UP,PDIF
-S 3900,3500,5900,3500,100,*,RIGHT,ALU1
-S 5900,3500,5900,4000,100,*,UP,ALU1
-S 6500,4000,6500,4600,200,*,DOWN,ALU1
-S 5300,4000,5300,4600,200,*,DOWN,ALU1
-S 5500,300,5500,1200,300,*,DOWN,NDIF
-S 5800,100,5800,1400,100,*,UP,NTRANS
-S 4300,300,4300,1200,300,*,DOWN,NDIF
-S 4000,100,4000,1400,100,*,UP,NTRANS
-S 2300,300,2300,1200,300,*,DOWN,NDIF
-S 2600,100,2600,1400,100,*,UP,NTRANS
-S 2600,1400,2600,2600,100,*,DOWN,POLY
-S 4000,1400,4000,2600,100,*,DOWN,POLY
-S 4000,2600,4200,2600,100,*,LEFT,POLY
-S 1000,1000,5500,1000,100,*,RIGHT,ALU1
-S 7000,950,7000,4050,200,*,DOWN,ALU1
-S 6300,2500,6500,2500,200,*,RIGHT,ALU1
-S 6300,1500,6500,1500,200,*,RIGHT,ALU1
-S 4800,1000,4800,2000,100,*,UP,ALU1
-S 5500,1500,5500,3000,100,*,UP,ALU1
-S 5500,1500,5700,1500,200,*,RIGHT,ALU1
-S 4800,2000,7400,2000,100,*,RIGHT,POLY
-S 6500,1500,6500,3500,100,*,UP,ALU1
-V 3300,1000,CONT_DIF_N,*
-V 1500,1000,CONT_DIF_N,*
-V 300,500,CONT_DIF_N,*
-V 900,3500,CONT_DIF_P,*
-V 2700,3500,CONT_DIF_P,*
-V 4500,4000,CONT_DIF_P,*
-V 3300,4000,CONT_DIF_P,*
-V 2100,4000,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 300,4000,CONT_DIF_P,*
-V 500,2500,CONT_POLY,*
-V 1500,2500,CONT_POLY,*
-V 2500,2500,CONT_POLY,*
-V 3000,2500,CONT_POLY,*
-V 3500,2500,CONT_POLY,*
-V 4000,2500,CONT_POLY,*
-V 3300,3500,CONT_DIF_P,*
-V 300,3500,CONT_DIF_P,*
-V 1500,3500,CONT_DIF_P,*
-V 7700,500,CONT_DIF_N,*
-V 7100,1000,CONT_DIF_N,*
-V 6500,500,CONT_DIF_N,*
-V 7700,1000,CONT_DIF_N,*
-V 7700,4500,CONT_DIF_P,*
-V 7700,3500,CONT_DIF_P,*
-V 6500,4000,CONT_DIF_P,*
-V 7100,4000,CONT_DIF_P,*
-V 6500,4500,CONT_DIF_P,*
-V 7100,3500,CONT_DIF_P,*
-V 7100,3000,CONT_DIF_P,*
-V 7700,4000,CONT_DIF_P,*
-V 4900,4700,CONT_BODY_N,*
-V 3900,3500,CONT_DIF_P,*
-V 5900,4000,CONT_DIF_P,*
-V 5300,4000,CONT_DIF_P,*
-V 5500,1000,CONT_DIF_N,*
-V 4300,500,CONT_DIF_N,*
-V 2300,500,CONT_DIF_N,*
-V 4900,400,CONT_BODY_P,*
-V 6300,1500,CONT_POLY,*
-V 6300,2500,CONT_POLY,*
-V 4800,2000,CONT_POLY,*
-V 5500,2500,CONT_POLY,*
-V 5700,1500,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/sxlib/oa2a2a2a24_x4.sym b/alliance/share/cells/sxlib/oa2a2a2a24_x4.sym
deleted file mode 100644
index 90d92064..00000000
Binary files a/alliance/share/cells/sxlib/oa2a2a2a24_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/oa2a2a2a24_x4.vbe b/alliance/share/cells/sxlib/oa2a2a2a24_x4.vbe
deleted file mode 100644
index 33d16844..00000000
--- a/alliance/share/cells/sxlib/oa2a2a2a24_x4.vbe
+++ /dev/null
@@ -1,68 +0,0 @@
-ENTITY oa2a2a2a24_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 4000;
-  CONSTANT cin_i0	 : NATURAL := 14;
-  CONSTANT cin_i1	 : NATURAL := 13;
-  CONSTANT cin_i2	 : NATURAL := 14;
-  CONSTANT cin_i3	 : NATURAL := 13;
-  CONSTANT cin_i4	 : NATURAL := 13;
-  CONSTANT cin_i5	 : NATURAL := 13;
-  CONSTANT cin_i6	 : NATURAL := 14;
-  CONSTANT cin_i7	 : NATURAL := 14;
-  CONSTANT rdown_i0_q	 : NATURAL := 810;
-  CONSTANT rdown_i1_q	 : NATURAL := 810;
-  CONSTANT rdown_i2_q	 : NATURAL := 810;
-  CONSTANT rdown_i3_q	 : NATURAL := 810;
-  CONSTANT rdown_i4_q	 : NATURAL := 810;
-  CONSTANT rdown_i5_q	 : NATURAL := 810;
-  CONSTANT rdown_i6_q	 : NATURAL := 810;
-  CONSTANT rdown_i7_q	 : NATURAL := 810;
-  CONSTANT rup_i0_q	 : NATURAL := 890;
-  CONSTANT rup_i1_q	 : NATURAL := 890;
-  CONSTANT rup_i2_q	 : NATURAL := 890;
-  CONSTANT rup_i3_q	 : NATURAL := 890;
-  CONSTANT rup_i4_q	 : NATURAL := 890;
-  CONSTANT rup_i5_q	 : NATURAL := 890;
-  CONSTANT rup_i6_q	 : NATURAL := 890;
-  CONSTANT rup_i7_q	 : NATURAL := 890;
-  CONSTANT tphh_i7_q	 : NATURAL := 399;
-  CONSTANT tphh_i6_q	 : NATURAL := 487;
-  CONSTANT tphh_i5_q	 : NATURAL := 515;
-  CONSTANT tphh_i4_q	 : NATURAL := 619;
-  CONSTANT tphh_i2_q	 : NATURAL := 726;
-  CONSTANT tphh_i0_q	 : NATURAL := 823;
-  CONSTANT tpll_i1_q	 : NATURAL := 835;
-  CONSTANT tpll_i6_q	 : NATURAL := 845;
-  CONSTANT tphh_i3_q	 : NATURAL := 851;
-  CONSTANT tpll_i0_q	 : NATURAL := 879;
-  CONSTANT tpll_i3_q	 : NATURAL := 895;
-  CONSTANT tpll_i7_q	 : NATURAL := 895;
-  CONSTANT tpll_i4_q	 : NATURAL := 902;
-  CONSTANT tpll_i2_q	 : NATURAL := 940;
-  CONSTANT tpll_i5_q	 : NATURAL := 949;
-  CONSTANT tphh_i1_q	 : NATURAL := 955;
-  CONSTANT transistors	 : NATURAL := 20
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  i3	 : in  BIT;
-  i4	 : in  BIT;
-  i5	 : in  BIT;
-  i6	 : in  BIT;
-  i7	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END oa2a2a2a24_x4;
-
-ARCHITECTURE behaviour_data_flow OF oa2a2a2a24_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on oa2a2a2a24_x4"
-  SEVERITY WARNING;
-  q <= ((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and i7)) after 1600 ps;
-END;
diff --git a/alliance/share/cells/sxlib/oa2a2a2a24_x4.vhd b/alliance/share/cells/sxlib/oa2a2a2a24_x4.vhd
deleted file mode 100644
index 480fb8b8..00000000
--- a/alliance/share/cells/sxlib/oa2a2a2a24_x4.vhd
+++ /dev/null
@@ -1,26 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY oa2a2a2a24_x4 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  i3	: IN STD_LOGIC;
-  i4	: IN STD_LOGIC;
-  i5	: IN STD_LOGIC;
-  i6	: IN STD_LOGIC;
-  i7	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END oa2a2a2a24_x4;
-
-ARCHITECTURE RTL OF oa2a2a2a24_x4 IS
-BEGIN
-  q <= ((((i0 AND i1) OR (i2 AND i3)) OR (i4 AND i5)) OR (i6 AND i7));
-END RTL;
diff --git a/alliance/share/cells/sxlib/oa2ao222_x2.al b/alliance/share/cells/sxlib/oa2ao222_x2.al
deleted file mode 100644
index 4491d151..00000000
--- a/alliance/share/cells/sxlib/oa2ao222_x2.al
+++ /dev/null
@@ -1,49 +0,0 @@
-V ALLIANCE : 6
-H oa2ao222_x2,L,30/10/99
-C i0,IN,EXTERNAL,12
-C i1,IN,EXTERNAL,11
-C i2,IN,EXTERNAL,8
-C i3,IN,EXTERNAL,9
-C i4,IN,EXTERNAL,10
-C q,OUT,EXTERNAL,13
-C vdd,IN,EXTERNAL,5
-C vss,IN,EXTERNAL,4
-T P,0.35,5.9,13,2,5,0,0.75,0.75,13.3,13.3,12.3,11.25,tr_00012
-T P,0.35,5.9,6,9,7,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00011
-T P,0.35,4.25,6,11,5,0,0.75,0.75,10,10,3.6,10.42,tr_00010
-T P,0.35,4.25,5,12,6,0,0.75,0.75,10,10,1.8,10.42,tr_00009
-T P,0.35,5.9,7,8,2,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00008
-T P,0.35,5.9,2,10,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00007
-T N,0.35,2.9,4,2,13,0,0.75,0.75,7.3,7.3,12.3,3.75,tr_00006
-T N,0.35,1.7,4,8,1,0,0.75,0.75,4.9,4.9,6.9,4.35,tr_00005
-T N,0.35,1.7,1,9,4,0,0.75,0.75,4.9,4.9,8.7,4.35,tr_00004
-T N,0.35,2.6,2,11,3,0,0.75,0.75,6.7,6.7,3.3,3.9,tr_00003
-T N,0.35,2.6,3,12,4,0,0.75,0.75,6.7,6.7,1.8,3.9,tr_00002
-T N,0.35,1.7,1,10,2,0,0.75,0.75,4.9,4.9,5.1,4.35,tr_00001
-S 13,EXTERNAL,q
-Q 0.00276148
-S 12,EXTERNAL,i0
-Q 0.00254241
-S 11,EXTERNAL,i1
-Q 0.00241094
-S 10,EXTERNAL,i4
-Q 0.00212909
-S 9,EXTERNAL,i3
-Q 0.00197871
-S 8,EXTERNAL
-Q 0.00212909
-S 7,INTERNAL
-Q 0
-S 6,INTERNAL
-Q 0.00227626
-S 5,EXTERNAL,vdd
-Q 0.00557437
-S 4,EXTERNAL,vss
-Q 0.00657321
-S 3,INTERNAL
-Q 0
-S 2,INTERNAL
-Q 0.00590927
-S 1,INTERNAL
-Q 0.00114171
-EOF
diff --git a/alliance/share/cells/sxlib/oa2ao222_x2.ap b/alliance/share/cells/sxlib/oa2ao222_x2.ap
deleted file mode 100644
index 739f64cc..00000000
--- a/alliance/share/cells/sxlib/oa2ao222_x2.ap
+++ /dev/null
@@ -1,129 +0,0 @@
-V ALLIANCE : 6
-H oa2ao222_x2,P, 6/ 9/2000,100
-A 0,0,5000,5000
-R 4500,4000,ref_ref,q_40
-R 4500,2000,ref_ref,q_20
-R 4500,2500,ref_ref,q_25
-R 4500,3000,ref_ref,q_30
-R 4500,1000,ref_ref,q_10
-R 4500,3500,ref_ref,q_35
-R 4500,1500,ref_ref,q_15
-R 500,1000,ref_ref,i0_10
-R 500,1500,ref_ref,i0_15
-R 500,2000,ref_ref,i0_20
-R 500,2500,ref_ref,i0_25
-R 500,3000,ref_ref,i0_30
-R 500,3500,ref_ref,i0_35
-R 1000,3500,ref_ref,i1_35
-R 1000,3000,ref_ref,i1_30
-R 1000,2500,ref_ref,i1_25
-R 1000,2000,ref_ref,i1_20
-R 1000,1500,ref_ref,i1_15
-R 1500,3500,ref_ref,i4_35
-R 1500,3000,ref_ref,i4_30
-R 1500,2500,ref_ref,i4_25
-R 1500,2000,ref_ref,i4_20
-R 2500,1500,ref_ref,i2_15
-R 2500,2000,ref_ref,i2_20
-R 2500,2500,ref_ref,i2_25
-R 2500,3000,ref_ref,i2_30
-R 3000,1500,ref_ref,i3_15
-R 3000,2000,ref_ref,i3_20
-R 3000,2500,ref_ref,i3_25
-R 3000,3000,ref_ref,i3_30
-S 1500,2000,1700,2000,300,*,RIGHT,POLY
-S 4500,1000,4500,4000,200,q,DOWN,CALU1
-S 500,1000,500,3500,200,i0,DOWN,CALU1
-S 1000,1500,1000,3500,200,i1,DOWN,CALU1
-S 1500,2000,1500,3500,200,i4,DOWN,CALU1
-S 2500,1500,2500,3000,200,i2,DOWN,CALU1
-S 3000,1500,3000,3000,200,i3,DOWN,CALU1
-S 4400,2800,4400,4700,300,*,DOWN,PDIF
-S 2100,3500,3900,3500,100,*,RIGHT,ALU1
-S 4100,2600,4100,4900,100,*,UP,PTRANS
-S 3800,2800,3800,4700,300,*,DOWN,PDIF
-S 3800,800,3800,1700,300,*,UP,NDIF
-S 4100,600,4100,1900,100,*,DOWN,NTRANS
-S 4400,800,4400,1700,300,*,UP,NDIF
-S 3800,2500,4100,2500,300,*,RIGHT,POLY
-S 4100,1900,4100,2600,100,*,UP,POLY
-S 3800,300,3800,1500,200,*,DOWN,ALU1
-S 3800,4000,3800,4700,200,*,UP,ALU1
-S 3900,2500,3900,3500,100,*,DOWN,ALU1
-S 3000,1500,3000,3000,100,*,UP,ALU1
-S 2000,3500,2100,3500,100,*,RIGHT,ALU1
-S 2000,1500,2000,3500,100,*,UP,ALU1
-S 1500,1500,2000,1500,100,*,RIGHT,ALU1
-S 1500,1000,1500,1500,100,*,UP,ALU1
-S 1400,1000,1500,1000,100,*,RIGHT,ALU1
-S 1200,400,2000,400,300,*,RIGHT,PTIE
-S 2000,900,2000,1700,200,*,UP,NDIF
-S 3200,900,3200,1700,300,*,UP,NDIF
-S 1400,900,1400,1700,200,*,UP,NDIF
-S 500,1000,500,3500,100,*,DOWN,ALU1
-S 300,500,300,1700,300,*,UP,NDIF
-S 3200,2800,3200,4700,300,*,UP,PDIF
-S 2600,500,2600,1700,300,*,UP,NDIF
-S 1100,1900,1100,2600,100,i1,UP,POLY
-S 1700,1900,1700,2600,100,i2,UP,POLY
-S 2400,1900,2400,2600,100,i3,UP,POLY
-S 2900,1900,2900,2600,100,i4,UP,POLY
-S 2300,1900,2400,1900,100,*,RIGHT,POLY
-S 300,4000,3200,4000,100,*,RIGHT,ALU1
-S 1500,2000,1500,3500,100,*,UP,ALU1
-S 1000,1500,1000,3500,100,*,UP,ALU1
-S 1700,2600,1800,2600,100,*,RIGHT,POLY
-S 1100,2600,1200,2600,100,*,RIGHT,POLY
-S 2900,2600,2900,4900,100,*,UP,PTRANS
-S 900,2800,900,4450,300,*,UP,PDIF
-S 1200,2600,1200,4350,100,*,UP,PTRANS
-S 600,2600,600,4350,100,*,UP,PTRANS
-S 1500,2800,1500,4150,200,*,UP,PDIF
-S 300,2800,300,4150,300,*,UP,PDIF
-S 2700,2800,2700,4700,200,*,UP,PDIF
-S 2400,2600,2400,4900,100,*,UP,PTRANS
-S 2100,2800,2100,4700,200,*,UP,PDIF
-S 1800,2600,1800,4900,100,*,UP,PTRANS
-S 600,1900,600,2600,100,i0,UP,POLY
-S 2000,1000,3200,1000,100,*,RIGHT,ALU1
-S 2500,1500,2500,3000,100,*,UP,ALU1
-S 0,300,5000,300,600,vss,RIGHT,CALU1
-S 0,4700,5000,4700,600,vdd,RIGHT,CALU1
-S 0,3900,5000,3900,2400,*,RIGHT,NWELL
-S 2300,1000,2300,1900,100,*,UP,NTRANS
-S 2900,1000,2900,1900,100,*,UP,NTRANS
-S 1100,700,1100,1900,100,*,UP,NTRANS
-S 600,700,600,1900,100,*,UP,NTRANS
-S 1700,1000,1700,1900,100,*,UP,NTRANS
-S 4500,1000,4500,4000,200,*,DOWN,ALU1
-V 4400,3000,CONT_DIF_P,*
-V 3800,4000,CONT_DIF_P,*
-V 4400,3500,CONT_DIF_P,*
-V 3800,4500,CONT_DIF_P,*
-V 4400,4000,CONT_DIF_P,*
-V 3800,1500,CONT_DIF_N,*
-V 4400,1000,CONT_DIF_N,*
-V 4400,1500,CONT_DIF_N,*
-V 3800,1000,CONT_DIF_N,*
-V 4400,300,CONT_BODY_P,*
-V 3900,2500,CONT_POLY,*
-V 1200,400,CONT_BODY_P,*
-V 1600,400,CONT_BODY_P,*
-V 2000,400,CONT_BODY_P,*
-V 300,500,CONT_DIF_N,*
-V 2500,2000,CONT_POLY,*
-V 3000,2000,CONT_POLY,*
-V 1500,2000,CONT_POLY,*
-V 1000,2000,CONT_POLY,*
-V 500,2000,CONT_POLY,*
-V 3200,4000,CONT_DIF_P,*
-V 300,4000,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 300,4700,CONT_BODY_N,*
-V 900,4500,CONT_DIF_P,*
-V 1400,1000,CONT_DIF_N,*
-V 2000,1000,CONT_DIF_N,*
-V 3200,1000,CONT_DIF_N,*
-V 2600,500,CONT_DIF_N,*
-V 2100,3500,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/oa2ao222_x2.sym b/alliance/share/cells/sxlib/oa2ao222_x2.sym
deleted file mode 100644
index 1e610a78..00000000
Binary files a/alliance/share/cells/sxlib/oa2ao222_x2.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/oa2ao222_x2.vbe b/alliance/share/cells/sxlib/oa2ao222_x2.vbe
deleted file mode 100644
index 2a96b29e..00000000
--- a/alliance/share/cells/sxlib/oa2ao222_x2.vbe
+++ /dev/null
@@ -1,50 +0,0 @@
-ENTITY oa2ao222_x2 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 2500;
-  CONSTANT cin_i0	 : NATURAL := 11;
-  CONSTANT cin_i1	 : NATURAL := 11;
-  CONSTANT cin_i2	 : NATURAL := 11;
-  CONSTANT cin_i3	 : NATURAL := 11;
-  CONSTANT cin_i4	 : NATURAL := 11;
-  CONSTANT rdown_i0_q	 : NATURAL := 1620;
-  CONSTANT rdown_i1_q	 : NATURAL := 1620;
-  CONSTANT rdown_i2_q	 : NATURAL := 1620;
-  CONSTANT rdown_i3_q	 : NATURAL := 1620;
-  CONSTANT rdown_i4_q	 : NATURAL := 1620;
-  CONSTANT rup_i0_q	 : NATURAL := 1790;
-  CONSTANT rup_i1_q	 : NATURAL := 1790;
-  CONSTANT rup_i2_q	 : NATURAL := 1790;
-  CONSTANT rup_i3_q	 : NATURAL := 1790;
-  CONSTANT rup_i4_q	 : NATURAL := 1790;
-  CONSTANT tpll_i4_q	 : NATURAL := 453;
-  CONSTANT tphh_i2_q	 : NATURAL := 464;
-  CONSTANT tphh_i0_q	 : NATURAL := 495;
-  CONSTANT tpll_i1_q	 : NATURAL := 539;
-  CONSTANT tphh_i3_q	 : NATURAL := 556;
-  CONSTANT tphh_i4_q	 : NATURAL := 558;
-  CONSTANT tpll_i3_q	 : NATURAL := 578;
-  CONSTANT tpll_i0_q	 : NATURAL := 581;
-  CONSTANT tphh_i1_q	 : NATURAL := 598;
-  CONSTANT tpll_i2_q	 : NATURAL := 604;
-  CONSTANT transistors	 : NATURAL := 12
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  i3	 : in  BIT;
-  i4	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END oa2ao222_x2;
-
-ARCHITECTURE behaviour_data_flow OF oa2ao222_x2 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on oa2ao222_x2"
-  SEVERITY WARNING;
-  q <= ((i0 and i1) or (i4 and (i2 or i3))) after 1200 ps;
-END;
diff --git a/alliance/share/cells/sxlib/oa2ao222_x2.vhd b/alliance/share/cells/sxlib/oa2ao222_x2.vhd
deleted file mode 100644
index 5ef47e62..00000000
--- a/alliance/share/cells/sxlib/oa2ao222_x2.vhd
+++ /dev/null
@@ -1,23 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY oa2ao222_x2 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  i3	: IN STD_LOGIC;
-  i4	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END oa2ao222_x2;
-
-ARCHITECTURE RTL OF oa2ao222_x2 IS
-BEGIN
-  q <= ((i0 AND i1) OR (i4 AND (i2 OR i3)));
-END RTL;
diff --git a/alliance/share/cells/sxlib/oa2ao222_x4.al b/alliance/share/cells/sxlib/oa2ao222_x4.al
deleted file mode 100644
index 3aafc2a2..00000000
--- a/alliance/share/cells/sxlib/oa2ao222_x4.al
+++ /dev/null
@@ -1,51 +0,0 @@
-V ALLIANCE : 6
-H oa2ao222_x4,L,30/10/99
-C i0,IN,EXTERNAL,12
-C i1,IN,EXTERNAL,11
-C i2,IN,EXTERNAL,8
-C i3,IN,EXTERNAL,9
-C i4,IN,EXTERNAL,10
-C q,OUT,EXTERNAL,13
-C vdd,IN,EXTERNAL,5
-C vss,IN,EXTERNAL,4
-T P,0.35,5.9,13,2,5,0,0.75,0.75,13.3,13.3,12.3,11.25,tr_00014
-T P,0.35,5.9,6,9,7,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00013
-T P,0.35,4.25,6,11,5,0,0.75,0.75,10,10,3.6,10.42,tr_00012
-T P,0.35,4.25,5,12,6,0,0.75,0.75,10,10,1.8,10.42,tr_00011
-T P,0.35,5.9,7,8,2,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00010
-T P,0.35,5.9,2,10,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00009
-T P,0.35,5.9,5,2,13,0,0.75,0.75,13.3,13.3,14.1,11.25,tr_00008
-T N,0.35,2.9,4,2,13,0,0.75,0.75,7.3,7.3,12.3,3.75,tr_00007
-T N,0.35,1.7,4,8,1,0,0.75,0.75,4.9,4.9,6.9,4.35,tr_00006
-T N,0.35,1.7,1,9,4,0,0.75,0.75,4.9,4.9,8.7,4.35,tr_00005
-T N,0.35,2.6,2,11,3,0,0.75,0.75,6.7,6.7,3.3,3.9,tr_00004
-T N,0.35,2.6,3,12,4,0,0.75,0.75,6.7,6.7,1.8,3.9,tr_00003
-T N,0.35,1.7,1,10,2,0,0.75,0.75,4.9,4.9,5.1,4.35,tr_00002
-T N,0.35,2.9,13,2,4,0,0.75,0.75,7.3,7.3,14.1,3.75,tr_00001
-S 13,EXTERNAL,q
-Q 0.00276148
-S 12,EXTERNAL,i0
-Q 0.00254241
-S 11,EXTERNAL,i1
-Q 0.00241094
-S 10,EXTERNAL,i4
-Q 0.00212909
-S 9,EXTERNAL,i3
-Q 0.00197871
-S 8,EXTERNAL
-Q 0.00212909
-S 7,INTERNAL
-Q 0
-S 6,INTERNAL
-Q 0.00227626
-S 5,EXTERNAL,vdd
-Q 0.00773725
-S 4,EXTERNAL,vss
-Q 0.00861858
-S 3,INTERNAL
-Q 0
-S 2,INTERNAL
-Q 0.00727894
-S 1,INTERNAL
-Q 0.00114171
-EOF
diff --git a/alliance/share/cells/sxlib/oa2ao222_x4.ap b/alliance/share/cells/sxlib/oa2ao222_x4.ap
deleted file mode 100644
index a57a27f7..00000000
--- a/alliance/share/cells/sxlib/oa2ao222_x4.ap
+++ /dev/null
@@ -1,146 +0,0 @@
-V ALLIANCE : 6
-H oa2ao222_x4,P, 6/ 9/2000,100
-A 0,0,5500,5000
-R 4500,4000,ref_ref,q_40
-R 4500,2000,ref_ref,q_20
-R 4500,2500,ref_ref,q_25
-R 4500,3000,ref_ref,q_30
-R 4500,1000,ref_ref,q_10
-R 4500,3500,ref_ref,q_35
-R 4500,1500,ref_ref,q_15
-R 500,1000,ref_ref,i0_10
-R 500,1500,ref_ref,i0_15
-R 500,2000,ref_ref,i0_20
-R 500,2500,ref_ref,i0_25
-R 500,3000,ref_ref,i0_30
-R 500,3500,ref_ref,i0_35
-R 1000,3500,ref_ref,i1_35
-R 1000,3000,ref_ref,i1_30
-R 1000,2500,ref_ref,i1_25
-R 1000,2000,ref_ref,i1_20
-R 1000,1500,ref_ref,i1_15
-R 1500,3500,ref_ref,i4_35
-R 1500,3000,ref_ref,i4_30
-R 1500,2500,ref_ref,i4_25
-R 1500,2000,ref_ref,i4_20
-R 2500,1500,ref_ref,i2_15
-R 2500,2000,ref_ref,i2_20
-R 2500,2500,ref_ref,i2_25
-R 2500,3000,ref_ref,i2_30
-R 3000,1500,ref_ref,i3_15
-R 3000,2000,ref_ref,i3_20
-R 3000,2500,ref_ref,i3_25
-R 3000,3000,ref_ref,i3_30
-S 1500,2000,1700,2000,300,*,RIGHT,POLY
-S 4500,1000,4500,4000,200,q,DOWN,CALU1
-S 500,1000,500,3500,200,i0,DOWN,CALU1
-S 1000,1500,1000,3500,200,i1,DOWN,CALU1
-S 1500,2000,1500,3500,200,i4,DOWN,CALU1
-S 2500,1500,2500,3000,200,i2,DOWN,CALU1
-S 3000,1500,3000,3000,200,i3,DOWN,CALU1
-S 4400,2800,4400,4700,300,*,DOWN,PDIF
-S 2100,3500,3900,3500,100,*,RIGHT,ALU1
-S 4100,2600,4100,4900,100,*,UP,PTRANS
-S 3800,2800,3800,4700,300,*,DOWN,PDIF
-S 3800,800,3800,1700,300,*,UP,NDIF
-S 4100,600,4100,1900,100,*,DOWN,NTRANS
-S 4400,800,4400,1700,300,*,UP,NDIF
-S 3800,2500,4100,2500,300,*,RIGHT,POLY
-S 4100,1900,4100,2600,100,*,UP,POLY
-S 3800,300,3800,1500,200,*,DOWN,ALU1
-S 3800,4000,3800,4700,200,*,UP,ALU1
-S 3900,2500,3900,3500,100,*,DOWN,ALU1
-S 3000,1500,3000,3000,100,*,UP,ALU1
-S 2000,3500,2100,3500,100,*,RIGHT,ALU1
-S 2000,1500,2000,3500,100,*,UP,ALU1
-S 1500,1500,2000,1500,100,*,RIGHT,ALU1
-S 1500,1000,1500,1500,100,*,UP,ALU1
-S 1400,1000,1500,1000,100,*,RIGHT,ALU1
-S 1200,400,2000,400,300,*,RIGHT,PTIE
-S 2000,900,2000,1700,200,*,UP,NDIF
-S 3200,900,3200,1700,300,*,UP,NDIF
-S 1400,900,1400,1700,200,*,UP,NDIF
-S 500,1000,500,3500,100,*,DOWN,ALU1
-S 300,500,300,1700,300,*,UP,NDIF
-S 3200,2800,3200,4700,300,*,UP,PDIF
-S 2600,500,2600,1700,300,*,UP,NDIF
-S 1100,1900,1100,2600,100,i1,UP,POLY
-S 1700,1900,1700,2600,100,i2,UP,POLY
-S 2400,1900,2400,2600,100,i3,UP,POLY
-S 2900,1900,2900,2600,100,i4,UP,POLY
-S 2300,1900,2400,1900,100,*,RIGHT,POLY
-S 300,4000,3200,4000,100,*,RIGHT,ALU1
-S 1500,2000,1500,3500,100,*,UP,ALU1
-S 1000,1500,1000,3500,100,*,UP,ALU1
-S 1700,2600,1800,2600,100,*,RIGHT,POLY
-S 1100,2600,1200,2600,100,*,RIGHT,POLY
-S 2900,2600,2900,4900,100,*,UP,PTRANS
-S 900,2800,900,4450,300,*,UP,PDIF
-S 1200,2600,1200,4350,100,*,UP,PTRANS
-S 600,2600,600,4350,100,*,UP,PTRANS
-S 1500,2800,1500,4150,200,*,UP,PDIF
-S 300,2800,300,4150,300,*,UP,PDIF
-S 2700,2800,2700,4700,200,*,UP,PDIF
-S 2400,2600,2400,4900,100,*,UP,PTRANS
-S 2100,2800,2100,4700,200,*,UP,PDIF
-S 1800,2600,1800,4900,100,*,UP,PTRANS
-S 600,1900,600,2600,100,i0,UP,POLY
-S 2000,1000,3200,1000,100,*,RIGHT,ALU1
-S 2500,1500,2500,3000,100,*,UP,ALU1
-S 2300,1000,2300,1900,100,*,UP,NTRANS
-S 2900,1000,2900,1900,100,*,UP,NTRANS
-S 1100,700,1100,1900,100,*,UP,NTRANS
-S 600,700,600,1900,100,*,UP,NTRANS
-S 1700,1000,1700,1900,100,*,UP,NTRANS
-S 0,4700,5500,4700,600,vdd,RIGHT,CALU1
-S 0,3900,5500,3900,2400,*,RIGHT,NWELL
-S 0,300,5500,300,600,vss,RIGHT,CALU1
-S 4700,600,4700,1900,100,*,DOWN,NTRANS
-S 4700,1900,4700,2600,100,*,UP,POLY
-S 4700,2600,4700,4900,100,*,UP,PTRANS
-S 5000,300,5000,1500,200,*,DOWN,ALU1
-S 5000,800,5000,1700,300,*,UP,NDIF
-S 5000,2800,5000,4700,300,*,DOWN,PDIF
-S 5000,3000,5000,4700,200,*,UP,ALU1
-S 3900,2500,4700,2500,300,*,RIGHT,POLY
-S 4500,1000,4500,4000,200,*,DOWN,ALU1
-V 4400,3000,CONT_DIF_P,*
-V 3800,4000,CONT_DIF_P,*
-V 4400,3500,CONT_DIF_P,*
-V 3800,4500,CONT_DIF_P,*
-V 4400,4000,CONT_DIF_P,*
-V 3800,1500,CONT_DIF_N,*
-V 4400,1000,CONT_DIF_N,*
-V 4400,1500,CONT_DIF_N,*
-V 3800,1000,CONT_DIF_N,*
-V 4400,300,CONT_BODY_P,*
-V 3900,2500,CONT_POLY,*
-V 1200,400,CONT_BODY_P,*
-V 1600,400,CONT_BODY_P,*
-V 2000,400,CONT_BODY_P,*
-V 300,500,CONT_DIF_N,*
-V 2500,2000,CONT_POLY,*
-V 3000,2000,CONT_POLY,*
-V 1500,2000,CONT_POLY,*
-V 1000,2000,CONT_POLY,*
-V 500,2000,CONT_POLY,*
-V 3200,4000,CONT_DIF_P,*
-V 300,4000,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 300,4700,CONT_BODY_N,*
-V 900,4500,CONT_DIF_P,*
-V 1400,1000,CONT_DIF_N,*
-V 2000,1000,CONT_DIF_N,*
-V 3200,1000,CONT_DIF_N,*
-V 2600,500,CONT_DIF_N,*
-V 2100,3500,CONT_DIF_P,*
-V 5000,1500,CONT_DIF_N,*
-V 5000,1000,CONT_DIF_N,*
-V 5000,4500,CONT_DIF_P,*
-V 5000,4000,CONT_DIF_P,*
-V 5000,3500,CONT_DIF_P,*
-V 5000,3000,CONT_DIF_P,*
-V 3800,300,CONT_BODY_P,*
-V 5000,300,CONT_BODY_P,*
-V 3200,300,CONT_BODY_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/oa2ao222_x4.sym b/alliance/share/cells/sxlib/oa2ao222_x4.sym
deleted file mode 100644
index d4716284..00000000
Binary files a/alliance/share/cells/sxlib/oa2ao222_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/oa2ao222_x4.vbe b/alliance/share/cells/sxlib/oa2ao222_x4.vbe
deleted file mode 100644
index d8e7b2ab..00000000
--- a/alliance/share/cells/sxlib/oa2ao222_x4.vbe
+++ /dev/null
@@ -1,50 +0,0 @@
-ENTITY oa2ao222_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 2750;
-  CONSTANT cin_i0	 : NATURAL := 11;
-  CONSTANT cin_i1	 : NATURAL := 11;
-  CONSTANT cin_i2	 : NATURAL := 11;
-  CONSTANT cin_i3	 : NATURAL := 11;
-  CONSTANT cin_i4	 : NATURAL := 11;
-  CONSTANT rdown_i0_q	 : NATURAL := 810;
-  CONSTANT rdown_i1_q	 : NATURAL := 810;
-  CONSTANT rdown_i2_q	 : NATURAL := 810;
-  CONSTANT rdown_i3_q	 : NATURAL := 810;
-  CONSTANT rdown_i4_q	 : NATURAL := 810;
-  CONSTANT rup_i0_q	 : NATURAL := 890;
-  CONSTANT rup_i1_q	 : NATURAL := 890;
-  CONSTANT rup_i2_q	 : NATURAL := 890;
-  CONSTANT rup_i3_q	 : NATURAL := 890;
-  CONSTANT rup_i4_q	 : NATURAL := 890;
-  CONSTANT tpll_i4_q	 : NATURAL := 529;
-  CONSTANT tphh_i2_q	 : NATURAL := 552;
-  CONSTANT tphh_i0_q	 : NATURAL := 553;
-  CONSTANT tpll_i1_q	 : NATURAL := 616;
-  CONSTANT tphh_i3_q	 : NATURAL := 640;
-  CONSTANT tphh_i4_q	 : NATURAL := 656;
-  CONSTANT tpll_i0_q	 : NATURAL := 657;
-  CONSTANT tpll_i3_q	 : NATURAL := 660;
-  CONSTANT tphh_i1_q	 : NATURAL := 662;
-  CONSTANT tpll_i2_q	 : NATURAL := 693;
-  CONSTANT transistors	 : NATURAL := 14
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  i3	 : in  BIT;
-  i4	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END oa2ao222_x4;
-
-ARCHITECTURE behaviour_data_flow OF oa2ao222_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on oa2ao222_x4"
-  SEVERITY WARNING;
-  q <= ((i0 and i1) or (i4 and (i2 or i3))) after 1300 ps;
-END;
diff --git a/alliance/share/cells/sxlib/oa2ao222_x4.vhd b/alliance/share/cells/sxlib/oa2ao222_x4.vhd
deleted file mode 100644
index 11ed1fc9..00000000
--- a/alliance/share/cells/sxlib/oa2ao222_x4.vhd
+++ /dev/null
@@ -1,23 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY oa2ao222_x4 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  i3	: IN STD_LOGIC;
-  i4	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END oa2ao222_x4;
-
-ARCHITECTURE RTL OF oa2ao222_x4 IS
-BEGIN
-  q <= ((i0 AND i1) OR (i4 AND (i2 OR i3)));
-END RTL;
diff --git a/alliance/share/cells/sxlib/oa3ao322_x1.sym b/alliance/share/cells/sxlib/oa3ao322_x1.sym
deleted file mode 100644
index 3b587ba7..00000000
Binary files a/alliance/share/cells/sxlib/oa3ao322_x1.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/oa3ao322_x2.al b/alliance/share/cells/sxlib/oa3ao322_x2.al
deleted file mode 100644
index 6f7a0954..00000000
--- a/alliance/share/cells/sxlib/oa3ao322_x2.al
+++ /dev/null
@@ -1,63 +0,0 @@
-V ALLIANCE : 6
-H oa3ao322_x2,L,30/10/99
-C i0,IN,EXTERNAL,10
-C i1,IN,EXTERNAL,9
-C i2,IN,EXTERNAL,8
-C i3,IN,EXTERNAL,17
-C i4,IN,EXTERNAL,15
-C i5,IN,EXTERNAL,16
-C i6,IN,EXTERNAL,11
-C q,OUT,EXTERNAL,4
-C vdd,IN,EXTERNAL,7
-C vss,IN,EXTERNAL,3
-T P,0.35,5.9,7,2,4,0,0.75,0.75,13.3,13.3,2.4,11.25,tr_00016
-T P,0.35,4.4,14,17,2,0,0.75,0.75,10.3,10.3,11.7,10.5,tr_00015
-T P,0.35,4.4,13,15,14,0,0.75,0.75,10.3,10.3,13.2,10.5,tr_00014
-T P,0.35,4.4,6,16,13,0,0.75,0.75,10.3,10.3,14.7,10.5,tr_00013
-T P,0.35,3.2,6,10,7,0,0.75,0.75,7.9,7.9,4.2,11.1,tr_00012
-T P,0.35,3.2,7,9,6,0,0.75,0.75,7.9,7.9,6,11.1,tr_00011
-T P,0.35,3.2,6,8,7,0,0.75,0.75,7.9,7.9,7.8,11.1,tr_00010
-T P,0.35,3.5,2,11,6,0,0.75,0.75,8.5,8.5,9.6,10.95,tr_00009
-T N,0.35,2.9,4,2,3,0,0.75,0.75,7.3,7.3,2.4,3.75,tr_00008
-T N,0.35,1.7,12,11,2,0,0.75,0.75,4.9,4.9,9.3,3.45,tr_00007
-T N,0.35,1.1,3,17,12,0,0.75,0.75,3.7,3.7,11.1,3.15,tr_00006
-T N,0.35,1.1,12,15,3,0,0.75,0.75,3.7,3.7,12.9,3.15,tr_00005
-T N,0.35,1.1,3,16,12,0,0.75,0.75,3.7,3.7,14.7,3.15,tr_00004
-T N,0.35,2.3,2,8,1,0,0.75,0.75,6.1,6.1,7.5,3.75,tr_00003
-T N,0.35,2.3,1,9,5,0,0.75,0.75,6.1,6.1,6,3.75,tr_00002
-T N,0.35,2.3,5,10,3,0,0.75,0.75,6.1,6.1,4.5,3.75,tr_00001
-S 17,EXTERNAL,i3
-Q 0.00290834
-S 16,EXTERNAL,i5
-Q 0.00275797
-S 15,EXTERNAL,i4
-Q 0.00283894
-S 14,INTERNAL
-Q 0
-S 13,INTERNAL
-Q 0
-S 12,INTERNAL
-Q 0.00114171
-S 11,EXTERNAL,i6
-Q 0.00262649
-S 10,EXTERNAL,i0
-Q 0.00290834
-S 9,EXTERNAL,i1
-Q 0.00275797
-S 8,EXTERNAL,i2
-Q 0.00247612
-S 7,EXTERNAL,vdd
-Q 0.00644464
-S 6,INTERNAL
-Q 0.00261448
-S 5,INTERNAL
-Q 0
-S 4,EXTERNAL,q
-Q 0.00258522
-S 3,EXTERNAL,vss
-Q 0.00679717
-S 2,INTERNAL
-Q 0.00549512
-S 1,INTERNAL
-Q 0
-EOF
diff --git a/alliance/share/cells/sxlib/oa3ao322_x2.ap b/alliance/share/cells/sxlib/oa3ao322_x2.ap
deleted file mode 100644
index f587d74e..00000000
--- a/alliance/share/cells/sxlib/oa3ao322_x2.ap
+++ /dev/null
@@ -1,161 +0,0 @@
-V ALLIANCE : 6
-H oa3ao322_x2,P, 6/ 9/2000,100
-A 0,0,5500,5000
-R 500,3500,ref_ref,q_35
-R 500,3000,ref_ref,q_30
-R 500,2500,ref_ref,q_25
-R 500,2000,ref_ref,q_20
-R 500,1500,ref_ref,q_15
-R 500,1000,ref_ref,q_10
-R 500,4000,ref_ref,q_40
-R 1500,3500,ref_ref,i0_35
-R 4000,3500,ref_ref,i3_35
-R 5000,2500,ref_ref,i5_25
-R 5000,3000,ref_ref,i5_30
-R 5000,3500,ref_ref,i5_35
-R 1500,1500,ref_ref,i0_15
-R 1500,2000,ref_ref,i0_20
-R 1500,2500,ref_ref,i0_25
-R 1500,3000,ref_ref,i0_30
-R 4000,3000,ref_ref,i3_30
-R 4500,1500,ref_ref,i4_15
-R 4500,2000,ref_ref,i4_20
-R 4500,2500,ref_ref,i4_25
-R 4500,3000,ref_ref,i4_30
-R 4500,3500,ref_ref,i4_35
-R 5000,1500,ref_ref,i5_15
-R 5000,2000,ref_ref,i5_20
-R 4000,1500,ref_ref,i3_15
-R 4000,2000,ref_ref,i3_20
-R 4000,2500,ref_ref,i3_25
-R 2500,2500,ref_ref,i2_25
-R 2500,3000,ref_ref,i2_30
-R 2500,3500,ref_ref,i2_35
-R 3000,2000,ref_ref,i6_20
-R 3000,2500,ref_ref,i6_25
-R 3000,3000,ref_ref,i6_30
-R 3000,3500,ref_ref,i6_35
-R 2000,1500,ref_ref,i1_15
-R 2000,2000,ref_ref,i1_20
-R 2000,2500,ref_ref,i1_25
-R 2000,3000,ref_ref,i1_30
-R 2000,3500,ref_ref,i1_35
-R 2500,2000,ref_ref,i2_20
-S 3000,2000,3200,2000,300,*,RIGHT,POLY
-S 800,2000,1000,2000,300,*,LEFT,POLY
-S 500,1000,500,4000,200,q,DOWN,CALU1
-S 1500,1500,1500,3500,200,i0,DOWN,CALU1
-S 4500,1500,4500,3500,200,i4,DOWN,CALU1
-S 5000,1500,5000,3500,200,i5,DOWN,CALU1
-S 4000,1500,4000,3500,200,i3,DOWN,CALU1
-S 3000,2000,3000,3500,200,i6,DOWN,CALU1
-S 2000,1500,2000,3500,200,i1,DOWN,CALU1
-S 2500,2000,2500,3500,200,i2,DOWN,CALU1
-S 3100,1900,3200,1900,100,*,LEFT,POLY
-S 1400,1900,1500,1900,100,*,RIGHT,POLY
-S 3900,1900,3900,2600,100,*,UP,POLY
-S 3700,1900,3900,1900,100,*,RIGHT,POLY
-S 800,2600,800,4900,100,*,UP,PTRANS
-S 500,2800,500,4700,300,*,DOWN,PDIF
-S 1100,2800,1100,4200,200,*,DOWN,PDIF
-S 500,800,500,1700,300,*,UP,NDIF
-S 800,600,800,1900,100,*,DOWN,NTRANS
-S 1200,500,1200,1700,300,*,UP,NDIF
-S 4700,400,5100,400,300,*,RIGHT,PTIE
-S 800,1900,800,2600,100,*,DOWN,POLY
-S 4900,1900,4900,2600,100,i5,DOWN,POLY
-S 4400,1900,4400,2600,100,i4,UP,POLY
-S 4300,1900,4400,1900,100,*,RIGHT,POLY
-S 0,300,5500,300,600,vss,RIGHT,CALU1
-S 500,1000,500,4000,200,*,UP,ALU1
-S 1100,4000,1100,4700,200,*,UP,ALU1
-S 0,4700,5500,4700,600,vdd,RIGHT,CALU1
-S 1000,1000,1000,2000,100,*,UP,ALU1
-S 3400,1000,4600,1000,100,*,RIGHT,ALU1
-S 4000,1500,4000,3500,100,*,UP,ALU1
-S 3500,1500,3500,3500,100,*,DOWN,ALU1
-S 1500,1500,1500,3500,100,*,DOWN,ALU1
-S 2000,1500,2000,3500,100,*,DOWN,ALU1
-S 4500,1500,4500,3500,100,*,UP,ALU1
-S 3000,2000,3000,3500,100,*,UP,ALU1
-S 5200,300,5200,1000,200,*,DOWN,ALU1
-S 5000,1500,5000,3500,100,*,DOWN,ALU1
-S 2500,2000,2500,3500,100,*,UP,ALU1
-S 2800,1000,2800,1500,100,*,UP,ALU1
-S 2800,1500,3500,1500,100,*,RIGHT,ALU1
-S 1000,1000,2800,1000,100,*,LEFT,ALU1
-S 1700,4000,5200,4000,100,*,RIGHT,ALU1
-S 3900,2600,3900,4400,100,*,UP,PTRANS
-S 4400,2600,4400,4400,100,*,UP,PTRANS
-S 4900,2600,4900,4400,100,*,UP,PTRANS
-S 3100,700,3100,1600,100,*,UP,NTRANS
-S 3700,700,3700,1400,100,*,UP,NTRANS
-S 4300,700,4300,1400,100,*,UP,NTRANS
-S 4900,700,4900,1400,100,*,UP,NTRANS
-S 5200,900,5200,1200,300,*,UP,NDIF
-S 4600,900,4600,1200,300,*,UP,NDIF
-S 4000,400,4000,1200,300,*,DOWN,NDIF
-S 3400,900,3400,1400,200,*,UP,NDIF
-S 2800,900,2800,1400,200,*,UP,NDIF
-S 3100,1600,3100,1900,100,*,UP,POLY
-S 3700,1400,3700,1900,100,*,UP,POLY
-S 4300,1400,4300,1900,100,*,UP,POLY
-S 1400,3000,1400,4400,100,*,UP,PTRANS
-S 2000,3000,2000,4400,100,*,UP,PTRANS
-S 2600,3000,2600,4400,100,*,UP,PTRANS
-S 3200,2900,3200,4400,100,*,UP,PTRANS
-S 5200,2800,5200,4200,300,*,UP,PDIF
-S 1700,3200,1700,4200,300,*,UP,PDIF
-S 2300,3200,2300,4500,300,*,DOWN,PDIF
-S 2900,3100,2900,4200,200,*,UP,PDIF
-S 3500,3100,3500,4200,400,*,DOWN,PDIF
-S 1400,1900,1400,3000,100,*,DOWN,POLY
-S 2000,1900,2000,3000,100,*,DOWN,POLY
-S 2600,1900,2600,3000,100,i2,UP,POLY
-S 3200,1900,3200,2900,100,i6,UP,POLY
-S 2500,700,2500,1800,100,*,UP,NTRANS
-S 2000,700,2000,1800,100,*,UP,NTRANS
-S 1500,700,1500,1800,100,*,UP,NTRANS
-S 1800,400,3300,400,300,*,RIGHT,PTIE
-S 0,3900,5500,3900,2400,*,RIGHT,NWELL
-S 1500,1800,1500,2000,100,*,DOWN,POLY
-S 2000,1800,2000,2000,100,*,UP,POLY
-S 2500,1800,2500,2000,100,*,UP,POLY
-S 4900,1400,4900,2000,100,*,UP,POLY
-V 500,3500,CONT_DIF_P,*
-V 1100,4000,CONT_DIF_P,*
-V 500,4000,CONT_DIF_P,*
-V 500,3000,CONT_DIF_P,*
-V 3500,3000,CONT_DIF_P,*
-V 3500,3500,CONT_DIF_P,*
-V 2300,4500,CONT_DIF_P,*
-V 1600,4700,CONT_BODY_N,*
-V 5200,4000,CONT_DIF_P,*
-V 500,1500,CONT_DIF_N,*
-V 4000,500,CONT_DIF_N,*
-V 2800,1000,CONT_DIF_N,*
-V 3400,1000,CONT_DIF_N,*
-V 1200,500,CONT_DIF_N,*
-V 5200,1000,CONT_DIF_N,*
-V 4600,1000,CONT_DIF_N,*
-V 5100,400,CONT_BODY_P,*
-V 4700,400,CONT_BODY_P,*
-V 1000,2000,CONT_POLY,*
-V 3000,2000,CONT_POLY,*
-V 5000,2000,CONT_POLY,*
-V 4500,2500,CONT_POLY,*
-V 4000,2500,CONT_POLY,*
-V 1500,2000,CONT_POLY,*
-V 2000,2000,CONT_POLY,*
-V 2500,2000,CONT_POLY,*
-V 2900,4000,CONT_DIF_P,*
-V 1700,4000,CONT_DIF_P,*
-V 2900,4700,CONT_BODY_N,*
-V 3500,4700,CONT_BODY_N,*
-V 4100,4700,CONT_BODY_N,*
-V 4700,4700,CONT_BODY_N,*
-V 2800,400,CONT_BODY_P,*
-V 2300,400,CONT_BODY_P,*
-V 1800,400,CONT_BODY_P,*
-V 3350,400,CONT_BODY_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/oa3ao322_x2.sym b/alliance/share/cells/sxlib/oa3ao322_x2.sym
deleted file mode 100644
index 5fbf4f56..00000000
Binary files a/alliance/share/cells/sxlib/oa3ao322_x2.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/oa3ao322_x2.vbe b/alliance/share/cells/sxlib/oa3ao322_x2.vbe
deleted file mode 100644
index dc2a7188..00000000
--- a/alliance/share/cells/sxlib/oa3ao322_x2.vbe
+++ /dev/null
@@ -1,62 +0,0 @@
-ENTITY oa3ao322_x2 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 2750;
-  CONSTANT cin_i0	 : NATURAL := 10;
-  CONSTANT cin_i1	 : NATURAL := 9;
-  CONSTANT cin_i2	 : NATURAL := 9;
-  CONSTANT cin_i3	 : NATURAL := 9;
-  CONSTANT cin_i4	 : NATURAL := 9;
-  CONSTANT cin_i5	 : NATURAL := 9;
-  CONSTANT cin_i6	 : NATURAL := 9;
-  CONSTANT rdown_i0_q	 : NATURAL := 1620;
-  CONSTANT rdown_i1_q	 : NATURAL := 1620;
-  CONSTANT rdown_i2_q	 : NATURAL := 1620;
-  CONSTANT rdown_i3_q	 : NATURAL := 1620;
-  CONSTANT rdown_i4_q	 : NATURAL := 1620;
-  CONSTANT rdown_i5_q	 : NATURAL := 1620;
-  CONSTANT rdown_i6_q	 : NATURAL := 1620;
-  CONSTANT rup_i0_q	 : NATURAL := 1790;
-  CONSTANT rup_i1_q	 : NATURAL := 1790;
-  CONSTANT rup_i2_q	 : NATURAL := 1790;
-  CONSTANT rup_i3_q	 : NATURAL := 1790;
-  CONSTANT rup_i4_q	 : NATURAL := 1790;
-  CONSTANT rup_i5_q	 : NATURAL := 1790;
-  CONSTANT rup_i6_q	 : NATURAL := 1790;
-  CONSTANT tpll_i6_q	 : NATURAL := 540;
-  CONSTANT tphh_i3_q	 : NATURAL := 560;
-  CONSTANT tphh_i6_q	 : NATURAL := 563;
-  CONSTANT tphh_i0_q	 : NATURAL := 638;
-  CONSTANT tphh_i4_q	 : NATURAL := 649;
-  CONSTANT tpll_i2_q	 : NATURAL := 707;
-  CONSTANT tphh_i5_q	 : NATURAL := 734;
-  CONSTANT tpll_i5_q	 : NATURAL := 734;
-  CONSTANT tphh_i1_q	 : NATURAL := 735;
-  CONSTANT tpll_i4_q	 : NATURAL := 760;
-  CONSTANT tpll_i1_q	 : NATURAL := 764;
-  CONSTANT tpll_i3_q	 : NATURAL := 765;
-  CONSTANT tphh_i2_q	 : NATURAL := 806;
-  CONSTANT tpll_i0_q	 : NATURAL := 820;
-  CONSTANT transistors	 : NATURAL := 16
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  i3	 : in  BIT;
-  i4	 : in  BIT;
-  i5	 : in  BIT;
-  i6	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END oa3ao322_x2;
-
-ARCHITECTURE behaviour_data_flow OF oa3ao322_x2 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on oa3ao322_x2"
-  SEVERITY WARNING;
-  q <= (((i0 and i1) and i2) or (i6 and ((i3 or i4) or i5))) after 1400 ps;
-END;
diff --git a/alliance/share/cells/sxlib/oa3ao322_x2.vhd b/alliance/share/cells/sxlib/oa3ao322_x2.vhd
deleted file mode 100644
index 23b695b4..00000000
--- a/alliance/share/cells/sxlib/oa3ao322_x2.vhd
+++ /dev/null
@@ -1,25 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY oa3ao322_x2 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  i3	: IN STD_LOGIC;
-  i4	: IN STD_LOGIC;
-  i5	: IN STD_LOGIC;
-  i6	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END oa3ao322_x2;
-
-ARCHITECTURE RTL OF oa3ao322_x2 IS
-BEGIN
-  q <= (((i0 AND i1) AND i2) OR (i6 AND ((i3 OR i4) OR i5)));
-END RTL;
diff --git a/alliance/share/cells/sxlib/oa3ao322_x4.al b/alliance/share/cells/sxlib/oa3ao322_x4.al
deleted file mode 100644
index eacaab98..00000000
--- a/alliance/share/cells/sxlib/oa3ao322_x4.al
+++ /dev/null
@@ -1,65 +0,0 @@
-V ALLIANCE : 6
-H oa3ao322_x4,L,30/10/99
-C i0,IN,EXTERNAL,6
-C i1,IN,EXTERNAL,7
-C i2,IN,EXTERNAL,9
-C i3,IN,EXTERNAL,16
-C i4,IN,EXTERNAL,14
-C i5,IN,EXTERNAL,15
-C i6,IN,EXTERNAL,17
-C q,OUT,EXTERNAL,2
-C vdd,IN,EXTERNAL,5
-C vss,IN,EXTERNAL,1
-T P,0.35,3.2,11,9,5,0,0.75,0.75,7.9,7.9,9.3,11.1,tr_00018
-T P,0.35,3.5,8,17,11,0,0.75,0.75,8.5,8.5,11.1,10.95,tr_00017
-T P,0.35,5.9,5,8,2,0,0.75,0.75,13.3,13.3,3.9,11.25,tr_00016
-T P,0.35,4.4,13,16,8,0,0.75,0.75,10.3,10.3,13.2,10.5,tr_00015
-T P,0.35,3.2,5,7,11,0,0.75,0.75,7.9,7.9,7.5,11.1,tr_00014
-T P,0.35,4.4,11,15,12,0,0.75,0.75,10.3,10.3,16.2,10.5,tr_00013
-T P,0.35,4.4,12,14,13,0,0.75,0.75,10.3,10.3,14.7,10.5,tr_00012
-T P,0.35,3.2,11,6,5,0,0.75,0.75,7.9,7.9,5.7,11.1,tr_00011
-T P,0.35,5.9,2,8,5,0,0.75,0.75,13.3,13.3,2.1,11.25,tr_00010
-T N,0.35,2.3,3,7,4,0,0.75,0.75,6.1,6.1,7.5,3.75,tr_00009
-T N,0.35,1.7,10,17,8,0,0.75,0.75,4.9,4.9,10.8,3.45,tr_00008
-T N,0.35,1.1,1,16,10,0,0.75,0.75,3.7,3.7,12.6,3.15,tr_00007
-T N,0.35,2.3,4,6,1,0,0.75,0.75,6.1,6.1,6,3.75,tr_00006
-T N,0.35,2.3,8,9,3,0,0.75,0.75,6.1,6.1,9,3.75,tr_00005
-T N,0.35,2.9,2,8,1,0,0.75,0.75,7.3,7.3,3.9,3.75,tr_00004
-T N,0.35,1.1,10,14,1,0,0.75,0.75,3.7,3.7,14.4,3.15,tr_00003
-T N,0.35,1.1,1,15,10,0,0.75,0.75,3.7,3.7,16.2,3.15,tr_00002
-T N,0.35,2.9,1,8,2,0,0.75,0.75,7.3,7.3,2.1,3.75,tr_00001
-S 17,EXTERNAL,i6
-Q 0.00262649
-S 16,EXTERNAL,i3
-Q 0.00290835
-S 15,EXTERNAL,i5
-Q 0.00275797
-S 14,EXTERNAL,i4
-Q 0.00283894
-S 13,INTERNAL
-Q 0
-S 12,INTERNAL
-Q 0
-S 11,INTERNAL
-Q 0.00261448
-S 10,INTERNAL
-Q 0.00114171
-S 9,EXTERNAL,i2
-Q 0.00247612
-S 8,INTERNAL
-Q 0.00668962
-S 7,EXTERNAL,i1
-Q 0.00275797
-S 6,EXTERNAL,i0
-Q 0.00290834
-S 5,EXTERNAL,vdd
-Q 0.00849001
-S 4,INTERNAL
-Q 0
-S 3,INTERNAL
-Q 0
-S 2,EXTERNAL,q
-Q 0.00258522
-S 1,EXTERNAL,vss
-Q 0.00825499
-EOF
diff --git a/alliance/share/cells/sxlib/oa3ao322_x4.ap b/alliance/share/cells/sxlib/oa3ao322_x4.ap
deleted file mode 100644
index 9bb123a6..00000000
--- a/alliance/share/cells/sxlib/oa3ao322_x4.ap
+++ /dev/null
@@ -1,174 +0,0 @@
-V ALLIANCE : 6
-H oa3ao322_x4,P, 6/ 9/2000,100
-A 0,0,6000,5000
-R 3500,3500,ref_ref,i6_35
-R 2500,1500,ref_ref,i1_15
-R 2500,2000,ref_ref,i1_20
-R 2500,2500,ref_ref,i1_25
-R 2500,3000,ref_ref,i1_30
-R 2500,3500,ref_ref,i1_35
-R 1000,3500,ref_ref,q_35
-R 3000,2000,ref_ref,i2_20
-R 4500,2000,ref_ref,i3_20
-R 4500,2500,ref_ref,i3_25
-R 3000,2500,ref_ref,i2_25
-R 3000,3000,ref_ref,i2_30
-R 3000,3500,ref_ref,i2_35
-R 3500,2000,ref_ref,i6_20
-R 3500,2500,ref_ref,i6_25
-R 3500,3000,ref_ref,i6_30
-R 5000,1500,ref_ref,i4_15
-R 5000,2000,ref_ref,i4_20
-R 5000,2500,ref_ref,i4_25
-R 5000,3000,ref_ref,i4_30
-R 5000,3500,ref_ref,i4_35
-R 5500,1500,ref_ref,i5_15
-R 5500,2000,ref_ref,i5_20
-R 4500,1500,ref_ref,i3_15
-R 5500,2500,ref_ref,i5_25
-R 5500,3000,ref_ref,i5_30
-R 5500,3500,ref_ref,i5_35
-R 2000,1500,ref_ref,i0_15
-R 2000,2000,ref_ref,i0_20
-R 2000,2500,ref_ref,i0_25
-R 2000,3000,ref_ref,i0_30
-R 4500,3000,ref_ref,i3_30
-R 1000,3000,ref_ref,q_30
-R 1000,2500,ref_ref,q_25
-R 1000,2000,ref_ref,q_20
-R 1000,1500,ref_ref,q_15
-R 1000,1000,ref_ref,q_10
-R 1000,4000,ref_ref,q_40
-R 2000,3500,ref_ref,i0_35
-R 4500,3500,ref_ref,i3_35
-S 4000,2800,4000,4200,300,*,DOWN,PDIF
-S 700,2000,1500,2000,300,*,LEFT,POLY
-S 3500,2000,3700,2000,300,*,RIGHT,POLY
-S 2500,1500,2500,3500,200,i1,DOWN,CALU1
-S 3000,2000,3000,3500,200,i2,DOWN,CALU1
-S 3500,2000,3500,3500,200,i6,DOWN,CALU1
-S 5000,1500,5000,3500,200,i4,DOWN,CALU1
-S 5500,1500,5500,3500,200,i5,DOWN,CALU1
-S 1000,1000,1000,4000,200,q,DOWN,CALU1
-S 2000,1500,2000,3500,200,i0,DOWN,CALU1
-S 4500,1500,4500,3500,200,i3,DOWN,CALU1
-S 2000,1500,2000,3500,100,*,DOWN,ALU1
-S 2500,1500,2500,3500,100,*,DOWN,ALU1
-S 5000,1500,5000,3500,100,*,UP,ALU1
-S 3500,2000,3500,3500,100,*,UP,ALU1
-S 5700,300,5700,1000,200,*,DOWN,ALU1
-S 5500,1500,5500,3500,100,*,DOWN,ALU1
-S 2200,4000,5700,4000,100,*,RIGHT,ALU1
-S 1500,1000,1500,2000,100,*,UP,ALU1
-S 3900,1000,5100,1000,100,*,RIGHT,ALU1
-S 4500,1500,4500,3500,100,*,UP,ALU1
-S 4000,1500,4000,3500,100,*,DOWN,ALU1
-S 1500,1000,3300,1000,100,*,LEFT,ALU1
-S 1000,1000,1000,4000,200,*,UP,ALU1
-S 1600,4000,1600,4700,200,*,UP,ALU1
-S 3300,1500,4000,1500,100,*,RIGHT,ALU1
-S 3300,1000,3300,1500,100,*,UP,ALU1
-S 3000,2000,3000,3500,100,*,UP,ALU1
-S 0,4700,6000,4700,600,vdd,RIGHT,CALU1
-S 400,400,400,1500,200,*,DOWN,ALU1
-S 400,3000,400,4500,200,*,UP,ALU1
-S 0,300,6000,300,600,vss,RIGHT,CALU1
-S 1300,1900,1300,2600,100,*,DOWN,POLY
-S 5400,1900,5400,2600,100,i5,DOWN,POLY
-S 4900,1900,4900,2600,100,i4,UP,POLY
-S 1900,1900,1900,3000,100,*,DOWN,POLY
-S 4800,1900,4900,1900,100,*,RIGHT,POLY
-S 2500,1800,2500,2000,100,*,UP,POLY
-S 5400,1400,5400,2000,100,*,UP,POLY
-S 3700,1900,3700,2900,100,i6,UP,POLY
-S 4400,1900,4400,2600,100,*,UP,POLY
-S 4200,1900,4400,1900,100,*,RIGHT,POLY
-S 3100,1900,3100,3000,100,i2,UP,POLY
-S 3000,1800,3000,2000,100,*,UP,POLY
-S 4200,1400,4200,1900,100,*,UP,POLY
-S 3600,1900,3700,1900,100,*,LEFT,POLY
-S 1900,1900,2000,1900,100,*,RIGHT,POLY
-S 2500,1900,2500,3000,100,*,DOWN,POLY
-S 2000,1800,2000,2000,100,*,DOWN,POLY
-S 4800,1400,4800,1900,100,*,UP,POLY
-S 3600,1600,3600,1900,100,*,UP,POLY
-S 700,1900,700,2600,100,*,DOWN,POLY
-S 2300,400,3800,400,300,*,RIGHT,PTIE
-S 5200,400,5600,400,300,*,RIGHT,PTIE
-S 2500,700,2500,1800,100,*,UP,NTRANS
-S 5100,900,5100,1200,300,*,UP,NDIF
-S 4500,400,4500,1200,300,*,DOWN,NDIF
-S 3600,700,3600,1600,100,*,UP,NTRANS
-S 1700,500,1700,1700,300,*,UP,NDIF
-S 3900,900,3900,1400,200,*,UP,NDIF
-S 4200,700,4200,1400,100,*,UP,NTRANS
-S 2000,700,2000,1800,100,*,UP,NTRANS
-S 3000,700,3000,1800,100,*,UP,NTRANS
-S 1000,800,1000,1700,300,*,UP,NDIF
-S 1300,600,1300,1900,100,*,DOWN,NTRANS
-S 4800,700,4800,1400,100,*,UP,NTRANS
-S 3300,900,3300,1400,200,*,UP,NDIF
-S 5400,700,5400,1400,100,*,UP,NTRANS
-S 5700,900,5700,1200,300,*,UP,NDIF
-S 400,800,400,1700,300,*,DOWN,NDIF
-S 700,600,700,1900,100,*,DOWN,NTRANS
-S 5700,2800,5700,4200,300,*,UP,PDIF
-S 3100,3000,3100,4400,100,*,UP,PTRANS
-S 3700,2900,3700,4400,100,*,UP,PTRANS
-S 1300,2600,1300,4900,100,*,UP,PTRANS
-S 1000,2800,1000,4700,300,*,DOWN,PDIF
-S 1600,2800,1600,4200,200,*,DOWN,PDIF
-S 2200,3200,2200,4200,300,*,UP,PDIF
-S 4400,2600,4400,4400,100,*,UP,PTRANS
-S 2500,3000,2500,4400,100,*,UP,PTRANS
-S 2800,3200,2800,4500,300,*,DOWN,PDIF
-S 3400,3100,3400,4200,200,*,UP,PDIF
-S 5400,2600,5400,4400,100,*,UP,PTRANS
-S 4900,2600,4900,4400,100,*,UP,PTRANS
-S 1900,3000,1900,4400,100,*,UP,PTRANS
-S 400,2800,400,4700,300,*,UP,PDIF
-S 700,2600,700,4900,100,*,UP,PTRANS
-S 0,3900,6000,3900,2400,*,RIGHT,NWELL
-V 1500,2000,CONT_POLY,*
-V 3500,2000,CONT_POLY,*
-V 5000,2500,CONT_POLY,*
-V 5500,2000,CONT_POLY,*
-V 4500,2500,CONT_POLY,*
-V 2000,2000,CONT_POLY,*
-V 2500,2000,CONT_POLY,*
-V 3000,2000,CONT_POLY,*
-V 2300,400,CONT_BODY_P,*
-V 3850,400,CONT_BODY_P,*
-V 2800,400,CONT_BODY_P,*
-V 3300,400,CONT_BODY_P,*
-V 5600,400,CONT_BODY_P,*
-V 5200,400,CONT_BODY_P,*
-V 5700,1000,CONT_DIF_N,*
-V 5100,1000,CONT_DIF_N,*
-V 1700,500,CONT_DIF_N,*
-V 1000,1500,CONT_DIF_N,*
-V 4500,500,CONT_DIF_N,*
-V 3300,1000,CONT_DIF_N,*
-V 3900,1000,CONT_DIF_N,*
-V 400,1500,CONT_DIF_N,*
-V 400,1000,CONT_DIF_N,*
-V 3400,4000,CONT_DIF_P,*
-V 4600,4700,CONT_BODY_N,*
-V 1000,3500,CONT_DIF_P,*
-V 1000,4000,CONT_DIF_P,*
-V 4000,4700,CONT_BODY_N,*
-V 3400,4700,CONT_BODY_N,*
-V 1600,4000,CONT_DIF_P,*
-V 5200,4700,CONT_BODY_N,*
-V 4000,3000,CONT_DIF_P,*
-V 4000,3500,CONT_DIF_P,*
-V 2800,4500,CONT_DIF_P,*
-V 2100,4700,CONT_BODY_N,*
-V 5700,4000,CONT_DIF_P,*
-V 1000,3000,CONT_DIF_P,*
-V 2200,4000,CONT_DIF_P,*
-V 400,4500,CONT_DIF_P,*
-V 400,4000,CONT_DIF_P,*
-V 400,3500,CONT_DIF_P,*
-V 400,3000,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/oa3ao322_x4.sym b/alliance/share/cells/sxlib/oa3ao322_x4.sym
deleted file mode 100644
index a6afb472..00000000
Binary files a/alliance/share/cells/sxlib/oa3ao322_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/oa3ao322_x4.vbe b/alliance/share/cells/sxlib/oa3ao322_x4.vbe
deleted file mode 100644
index 6f1ad976..00000000
--- a/alliance/share/cells/sxlib/oa3ao322_x4.vbe
+++ /dev/null
@@ -1,62 +0,0 @@
-ENTITY oa3ao322_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 3000;
-  CONSTANT cin_i0	 : NATURAL := 10;
-  CONSTANT cin_i1	 : NATURAL := 9;
-  CONSTANT cin_i2	 : NATURAL := 9;
-  CONSTANT cin_i3	 : NATURAL := 9;
-  CONSTANT cin_i4	 : NATURAL := 9;
-  CONSTANT cin_i5	 : NATURAL := 9;
-  CONSTANT cin_i6	 : NATURAL := 9;
-  CONSTANT rdown_i0_q	 : NATURAL := 810;
-  CONSTANT rdown_i1_q	 : NATURAL := 810;
-  CONSTANT rdown_i2_q	 : NATURAL := 810;
-  CONSTANT rdown_i3_q	 : NATURAL := 810;
-  CONSTANT rdown_i4_q	 : NATURAL := 810;
-  CONSTANT rdown_i5_q	 : NATURAL := 810;
-  CONSTANT rdown_i6_q	 : NATURAL := 810;
-  CONSTANT rup_i0_q	 : NATURAL := 890;
-  CONSTANT rup_i1_q	 : NATURAL := 890;
-  CONSTANT rup_i2_q	 : NATURAL := 890;
-  CONSTANT rup_i3_q	 : NATURAL := 890;
-  CONSTANT rup_i4_q	 : NATURAL := 890;
-  CONSTANT rup_i5_q	 : NATURAL := 890;
-  CONSTANT rup_i6_q	 : NATURAL := 890;
-  CONSTANT tpll_i6_q	 : NATURAL := 651;
-  CONSTANT tphh_i3_q	 : NATURAL := 673;
-  CONSTANT tphh_i6_q	 : NATURAL := 684;
-  CONSTANT tphh_i0_q	 : NATURAL := 717;
-  CONSTANT tphh_i4_q	 : NATURAL := 758;
-  CONSTANT tphh_i1_q	 : NATURAL := 818;
-  CONSTANT tpll_i2_q	 : NATURAL := 834;
-  CONSTANT tphh_i5_q	 : NATURAL := 839;
-  CONSTANT tpll_i5_q	 : NATURAL := 865;
-  CONSTANT tpll_i1_q	 : NATURAL := 890;
-  CONSTANT tphh_i2_q	 : NATURAL := 894;
-  CONSTANT tpll_i4_q	 : NATURAL := 896;
-  CONSTANT tpll_i3_q	 : NATURAL := 898;
-  CONSTANT tpll_i0_q	 : NATURAL := 946;
-  CONSTANT transistors	 : NATURAL := 18
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  i3	 : in  BIT;
-  i4	 : in  BIT;
-  i5	 : in  BIT;
-  i6	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END oa3ao322_x4;
-
-ARCHITECTURE behaviour_data_flow OF oa3ao322_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on oa3ao322_x4"
-  SEVERITY WARNING;
-  q <= (((i0 and i1) and i2) or (i6 and ((i3 or i4) or i5))) after 1500 ps;
-END;
diff --git a/alliance/share/cells/sxlib/oa3ao322_x4.vhd b/alliance/share/cells/sxlib/oa3ao322_x4.vhd
deleted file mode 100644
index 24b29df7..00000000
--- a/alliance/share/cells/sxlib/oa3ao322_x4.vhd
+++ /dev/null
@@ -1,25 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY oa3ao322_x4 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  i3	: IN STD_LOGIC;
-  i4	: IN STD_LOGIC;
-  i5	: IN STD_LOGIC;
-  i6	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END oa3ao322_x4;
-
-ARCHITECTURE RTL OF oa3ao322_x4 IS
-BEGIN
-  q <= (((i0 AND i1) AND i2) OR (i6 AND ((i3 OR i4) OR i5)));
-END RTL;
diff --git a/alliance/share/cells/sxlib/on12_x1.al b/alliance/share/cells/sxlib/on12_x1.al
deleted file mode 100644
index 209fc17f..00000000
--- a/alliance/share/cells/sxlib/on12_x1.al
+++ /dev/null
@@ -1,28 +0,0 @@
-V ALLIANCE : 6
-H on12_x1,L,30/10/99
-C i0,IN,EXTERNAL,5
-C i1,IN,EXTERNAL,6
-C q,OUT,EXTERNAL,1
-C vdd,IN,EXTERNAL,7
-C vss,IN,EXTERNAL,3
-T P,0.35,2.9,7,5,1,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00006
-T P,0.35,2.9,1,2,7,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00005
-T P,0.35,2.9,7,6,2,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00004
-T N,0.35,1.4,2,6,3,0,0.75,0.75,4.3,4.3,1.8,4.5,tr_00003
-T N,0.35,2.9,4,5,1,0,0.75,0.75,7.3,7.3,4.8,3.75,tr_00002
-T N,0.35,2.9,3,2,4,0,0.75,0.75,7.3,7.3,3.6,3.75,tr_00001
-S 7,EXTERNAL,vdd
-Q 0.0033382
-S 6,EXTERNAL,i1
-Q 0.00373582
-S 5,EXTERNAL,i0
-Q 0.00368237
-S 4,INTERNAL
-Q 0
-S 3,EXTERNAL,vss
-Q 0.00316194
-S 2,INTERNAL
-Q 0.00412385
-S 1,EXTERNAL,q
-Q 0.00279086
-EOF
diff --git a/alliance/share/cells/sxlib/on12_x1.ap b/alliance/share/cells/sxlib/on12_x1.ap
deleted file mode 100644
index a25d84a3..00000000
--- a/alliance/share/cells/sxlib/on12_x1.ap
+++ /dev/null
@@ -1,74 +0,0 @@
-V ALLIANCE : 6
-H on12_x1,P,30/ 8/2000,100
-A 0,0,2500,5000
-R 1500,1000,ref_ref,q_10
-R 1000,1000,ref_ref,i1_10
-R 1000,2500,ref_ref,i1_25
-R 1000,3000,ref_ref,i1_30
-R 1000,3500,ref_ref,i1_35
-R 1000,4000,ref_ref,i1_40
-R 2000,3500,ref_ref,i0_35
-R 2000,3000,ref_ref,i0_30
-R 2000,2500,ref_ref,i0_25
-R 2000,2000,ref_ref,i0_20
-R 2000,1500,ref_ref,i0_15
-R 1000,1500,ref_ref,i1_15
-R 1000,2000,ref_ref,i1_20
-R 1500,1500,ref_ref,q_15
-R 1500,2000,ref_ref,q_20
-R 1500,2500,ref_ref,q_25
-R 1500,3000,ref_ref,q_30
-R 1500,3500,ref_ref,q_35
-R 1500,4000,ref_ref,q_40
-R 2000,4000,ref_ref,i0_40
-S 300,3300,300,4200,300,*,UP,PDIF
-S 600,3100,600,4400,100,*,UP,PTRANS
-S 0,3900,2500,3900,2400,*,RIGHT,NWELL
-S 900,3300,900,4600,300,*,DOWN,PDIF
-S 2100,3300,2100,4600,300,*,DOWN,PDIF
-S 1200,3100,1200,4400,100,*,UP,PTRANS
-S 1500,3300,1500,4200,300,*,DOWN,PDIF
-S 1800,3100,1800,4400,100,*,UP,PTRANS
-S 900,400,900,1700,300,*,UP,NDIF
-S 1200,600,1200,1900,100,*,DOWN,NTRANS
-S 1600,600,1600,1900,100,*,DOWN,NTRANS
-S 1900,800,1900,1700,300,*,UP,NDIF
-S 300,1300,300,1700,300,*,DOWN,NDIF
-S 600,1100,600,1900,100,*,DOWN,NTRANS
-S 300,2500,1200,2500,100,*,RIGHT,POLY
-S 600,2000,800,2000,300,*,LEFT,POLY
-S 600,3000,800,3000,300,*,LEFT,POLY
-S 1200,1900,1200,3100,100,*,UP,POLY
-S 1600,1900,2100,1900,100,*,RIGHT,POLY
-S 1800,2000,2100,2000,300,*,RIGHT,POLY
-S 1800,1900,1800,3100,100,*,DOWN,POLY
-S 0,300,2500,300,600,vss,RIGHT,CALU1
-S 1000,1000,1000,4000,100,*,DOWN,ALU1
-S 1500,1000,1900,1000,200,*,RIGHT,ALU1
-S 1500,950,1500,4000,200,*,UP,ALU1
-S 300,1500,300,4000,100,*,UP,ALU1
-S 800,3000,1000,3000,200,*,RIGHT,ALU1
-S 0,4700,2500,4700,600,vdd,RIGHT,CALU1
-S 800,2000,1000,2000,200,*,RIGHT,ALU1
-S 2000,1500,2000,4000,100,*,DOWN,ALU1
-S 1500,1000,1500,4000,200,q,DOWN,CALU1
-S 1000,1000,1000,4000,200,i1,DOWN,CALU1
-S 2000,1500,2000,4000,200,i0,DOWN,CALU1
-V 300,4700,CONT_BODY_N,*
-V 300,4000,CONT_DIF_P,*
-V 300,3500,CONT_DIF_P,*
-V 900,4500,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 1500,3500,CONT_DIF_P,*
-V 1500,4700,CONT_BODY_N,*
-V 2100,4500,CONT_DIF_P,*
-V 900,500,CONT_DIF_N,*
-V 1900,1000,CONT_DIF_N,*
-V 300,1500,CONT_DIF_N,*
-V 300,300,CONT_BODY_P,*
-V 1750,300,CONT_BODY_P,*
-V 300,2500,CONT_POLY,*
-V 800,2000,CONT_POLY,*
-V 800,3000,CONT_POLY,*
-V 2000,2000,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/sxlib/on12_x1.sym b/alliance/share/cells/sxlib/on12_x1.sym
deleted file mode 100644
index 6b8b5019..00000000
Binary files a/alliance/share/cells/sxlib/on12_x1.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/on12_x1.vbe b/alliance/share/cells/sxlib/on12_x1.vbe
deleted file mode 100644
index 32688f42..00000000
--- a/alliance/share/cells/sxlib/on12_x1.vbe
+++ /dev/null
@@ -1,32 +0,0 @@
-ENTITY on12_x1 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 1250;
-  CONSTANT cin_i0	 : NATURAL := 11;
-  CONSTANT cin_i1	 : NATURAL := 9;
-  CONSTANT rdown_i0_q	 : NATURAL := 2850;
-  CONSTANT rdown_i1_q	 : NATURAL := 2850;
-  CONSTANT rup_i0_q	 : NATURAL := 3720;
-  CONSTANT rup_i1_q	 : NATURAL := 3720;
-  CONSTANT tphl_i0_q	 : NATURAL := 111;
-  CONSTANT tplh_i0_q	 : NATURAL := 234;
-  CONSTANT tpll_i1_q	 : NATURAL := 291;
-  CONSTANT tphh_i1_q	 : NATURAL := 314;
-  CONSTANT transistors	 : NATURAL := 6
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END on12_x1;
-
-ARCHITECTURE behaviour_data_flow OF on12_x1 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on on12_x1"
-  SEVERITY WARNING;
-  q <= (not (i0) or i1) after 900 ps;
-END;
diff --git a/alliance/share/cells/sxlib/on12_x1.vhd b/alliance/share/cells/sxlib/on12_x1.vhd
deleted file mode 100644
index 8e0928f3..00000000
--- a/alliance/share/cells/sxlib/on12_x1.vhd
+++ /dev/null
@@ -1,20 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY on12_x1 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END on12_x1;
-
-ARCHITECTURE RTL OF on12_x1 IS
-BEGIN
-  q <= (NOT(i0) OR i1);
-END RTL;
diff --git a/alliance/share/cells/sxlib/on12_x4.al b/alliance/share/cells/sxlib/on12_x4.al
deleted file mode 100644
index 3f58d0ad..00000000
--- a/alliance/share/cells/sxlib/on12_x4.al
+++ /dev/null
@@ -1,34 +0,0 @@
-V ALLIANCE : 6
-H on12_x4,L,30/10/99
-C i0,IN,EXTERNAL,7
-C i1,IN,EXTERNAL,6
-C q,OUT,EXTERNAL,8
-C vdd,IN,EXTERNAL,4
-C vss,IN,EXTERNAL,3
-T P,0.35,2.9,4,7,1,0,0.75,0.75,7.3,7.3,1.8,12.75,tr_00010
-T P,0.35,4.4,5,1,2,0,0.75,0.75,10.3,10.3,5.4,10.5,tr_00009
-T P,0.35,5.9,4,2,8,0,0.75,0.75,13.3,13.3,10.2,11.25,tr_00008
-T P,0.35,5.9,8,2,4,0,0.75,0.75,13.3,13.3,8.4,11.25,tr_00007
-T P,0.35,4.4,4,6,5,0,0.75,0.75,10.3,10.3,6.6,10.5,tr_00006
-T N,0.35,1.4,3,7,1,0,0.75,0.75,4.3,4.3,1.8,3,tr_00005
-T N,0.35,2.9,8,2,3,0,0.75,0.75,7.3,7.3,8.4,2.25,tr_00004
-T N,0.35,2.9,3,2,8,0,0.75,0.75,7.3,7.3,10.2,2.25,tr_00003
-T N,0.35,1.4,3,1,2,0,0.75,0.75,4.3,4.3,4.8,3,tr_00002
-T N,0.35,1.4,2,6,3,0,0.75,0.75,4.3,4.3,6.6,3,tr_00001
-S 8,EXTERNAL,q
-Q 0.00264397
-S 7,EXTERNAL,i0
-Q 0.00406025
-S 6,EXTERNAL,i1
-Q 0.00344095
-S 5,INTERNAL
-Q 0
-S 4,EXTERNAL,vdd
-Q 0.00589026
-S 3,EXTERNAL,vss
-Q 0.00547897
-S 2,INTERNAL
-Q 0.00629378
-S 1,INTERNAL
-Q 0.00472684
-EOF
diff --git a/alliance/share/cells/sxlib/on12_x4.ap b/alliance/share/cells/sxlib/on12_x4.ap
deleted file mode 100644
index 916e1f56..00000000
--- a/alliance/share/cells/sxlib/on12_x4.ap
+++ /dev/null
@@ -1,107 +0,0 @@
-V ALLIANCE : 6
-H on12_x4,P,30/ 8/2000,100
-A 0,0,4000,5000
-R 2500,2000,ref_ref,i1_20
-R 3000,1500,ref_ref,q_15
-R 3000,2000,ref_ref,q_20
-R 3000,2500,ref_ref,q_25
-R 3000,3000,ref_ref,q_30
-R 3000,3500,ref_ref,q_35
-R 3000,4000,ref_ref,q_40
-R 2500,2500,ref_ref,i1_25
-R 2500,3000,ref_ref,i1_30
-R 2500,3500,ref_ref,i1_35
-R 2500,4000,ref_ref,i1_40
-R 2500,1500,ref_ref,i1_15
-R 2500,1000,ref_ref,i1_10
-R 3000,1000,ref_ref,q_10
-R 1000,2500,ref_ref,i0_25
-R 1000,2000,ref_ref,i0_20
-R 1000,1500,ref_ref,i0_15
-R 1000,3500,ref_ref,i0_35
-R 1000,3000,ref_ref,i0_30
-R 1000,4000,ref_ref,i0_40
-R 1000,1000,ref_ref,i0_10
-S 1500,2900,1500,4000,100,*,DOWN,ALU1
-S 1900,1000,1900,2900,100,*,DOWN,ALU1
-S 1500,2900,1900,2900,100,*,RIGHT,ALU1
-S 3700,3000,3700,4500,200,*,UP,ALU1
-S 0,4700,4000,4700,600,vdd,RIGHT,CALU1
-S 2500,1000,2500,4000,100,*,UP,ALU1
-S 3700,500,3700,1000,200,*,DOWN,ALU1
-S 3000,950,3000,4050,200,*,UP,ALU1
-S 0,300,4000,300,600,vss,RIGHT,CALU1
-S 2200,2500,2500,2500,300,*,RIGHT,POLY
-S 1600,1400,1600,2600,100,*,DOWN,POLY
-S 1600,2600,1800,2600,100,*,RIGHT,POLY
-S 2800,1400,2800,2600,100,*,DOWN,POLY
-S 3400,1400,3400,2600,100,*,DOWN,POLY
-S 2000,2000,3400,2000,100,*,RIGHT,POLY
-S 2200,1500,2500,1500,300,*,RIGHT,POLY
-S 2200,600,2200,1400,100,*,DOWN,NTRANS
-S 1900,800,1900,1200,300,*,UP,NDIF
-S 1600,600,1600,1400,100,*,DOWN,NTRANS
-S 3400,100,3400,1400,100,*,UP,NTRANS
-S 3700,300,3700,1200,300,*,UP,NDIF
-S 3100,300,3100,1200,300,*,UP,NDIF
-S 2800,100,2800,1400,100,*,UP,NTRANS
-S 2500,300,2500,1200,300,*,UP,NDIF
-S 2200,2600,2200,4400,100,*,UP,PTRANS
-S 2800,2600,2800,4900,100,*,UP,PTRANS
-S 3100,2800,3100,4700,300,*,UP,PDIF
-S 2500,2800,2500,4700,300,*,UP,PDIF
-S 3400,2600,3400,4900,100,*,UP,PTRANS
-S 3700,2800,3700,4700,300,*,UP,PDIF
-S 1800,2600,1800,4400,100,*,UP,PTRANS
-S 0,3900,4000,3900,2400,*,RIGHT,NWELL
-S 1500,2800,1500,4200,300,*,DOWN,PDIF
-S 600,600,600,1400,100,*,UP,NTRANS
-S 1100,400,1100,1200,700,*,UP,NDIF
-S 300,800,300,1200,300,*,UP,NDIF
-S 600,1400,600,1600,100,*,UP,POLY
-S 600,1500,800,1500,100,*,RIGHT,POLY
-S 800,1500,1000,1500,200,*,RIGHT,ALU1
-S 300,2000,1600,2000,100,*,RIGHT,POLY
-S 1000,1000,1000,4000,100,*,UP,ALU1
-S 800,3500,1000,3500,200,*,RIGHT,ALU1
-S 600,3500,800,3500,100,*,RIGHT,POLY
-S 600,3400,600,3600,100,*,DOWN,POLY
-S 900,3800,900,4700,300,*,UP,PDIF
-S 600,3600,600,4900,100,*,UP,PTRANS
-S 300,3800,300,4700,300,*,UP,PDIF
-S 300,1000,300,4000,100,*,DOWN,ALU1
-S 2500,1000,2500,4000,200,i1,DOWN,CALU1
-S 3000,1000,3000,4000,200,q,DOWN,CALU1
-S 1000,1000,1000,4000,200,i0,DOWN,CALU1
-V 300,300,CONT_BODY_P,*
-V 2400,1500,CONT_POLY,*
-V 2400,2500,CONT_POLY,*
-V 2000,2000,CONT_POLY,*
-V 1900,300,CONT_BODY_P,*
-V 2500,500,CONT_DIF_N,*
-V 3700,1000,CONT_DIF_N,*
-V 3700,500,CONT_DIF_N,*
-V 3100,1000,CONT_DIF_N,*
-V 2500,500,CONT_DIF_N,*
-V 1900,1000,CONT_DIF_N,*
-V 1300,500,CONT_DIF_N,*
-V 3100,3500,CONT_DIF_P,*
-V 3100,4000,CONT_DIF_P,*
-V 3700,4500,CONT_DIF_P,*
-V 3700,4000,CONT_DIF_P,*
-V 3700,3500,CONT_DIF_P,*
-V 3700,3000,CONT_DIF_P,*
-V 2500,4500,CONT_DIF_P,*
-V 3100,3000,CONT_DIF_P,*
-V 300,1000,CONT_DIF_N,*
-V 900,500,CONT_DIF_N,*
-V 1500,4000,CONT_DIF_P,*
-V 800,1500,CONT_POLY,*
-V 300,2000,CONT_POLY,*
-V 1500,3000,CONT_DIF_P,*
-V 1500,3500,CONT_DIF_P,*
-V 800,3500,CONT_POLY,*
-V 300,4000,CONT_DIF_P,*
-V 900,4500,CONT_DIF_P,*
-V 1700,4700,CONT_BODY_N,*
-EOF
diff --git a/alliance/share/cells/sxlib/on12_x4.sym b/alliance/share/cells/sxlib/on12_x4.sym
deleted file mode 100644
index 6142c6ce..00000000
Binary files a/alliance/share/cells/sxlib/on12_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/on12_x4.vbe b/alliance/share/cells/sxlib/on12_x4.vbe
deleted file mode 100644
index c5f990c6..00000000
--- a/alliance/share/cells/sxlib/on12_x4.vbe
+++ /dev/null
@@ -1,32 +0,0 @@
-ENTITY on12_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 2000;
-  CONSTANT cin_i0	 : NATURAL := 9;
-  CONSTANT cin_i1	 : NATURAL := 10;
-  CONSTANT rdown_i0_q	 : NATURAL := 810;
-  CONSTANT rdown_i1_q	 : NATURAL := 810;
-  CONSTANT rup_i0_q	 : NATURAL := 890;
-  CONSTANT rup_i1_q	 : NATURAL := 890;
-  CONSTANT tpll_i1_q	 : NATURAL := 394;
-  CONSTANT tphl_i0_q	 : NATURAL := 474;
-  CONSTANT tphh_i1_q	 : NATURAL := 491;
-  CONSTANT tplh_i0_q	 : NATURAL := 499;
-  CONSTANT transistors	 : NATURAL := 10
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END on12_x4;
-
-ARCHITECTURE behaviour_data_flow OF on12_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on on12_x4"
-  SEVERITY WARNING;
-  q <= (not (i0) or i1) after 1100 ps;
-END;
diff --git a/alliance/share/cells/sxlib/on12_x4.vhd b/alliance/share/cells/sxlib/on12_x4.vhd
deleted file mode 100644
index 2e6b4193..00000000
--- a/alliance/share/cells/sxlib/on12_x4.vhd
+++ /dev/null
@@ -1,20 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY on12_x4 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END on12_x4;
-
-ARCHITECTURE RTL OF on12_x4 IS
-BEGIN
-  q <= (NOT(i0) OR i1);
-END RTL;
diff --git a/alliance/share/cells/sxlib/one_x0.al b/alliance/share/cells/sxlib/one_x0.al
deleted file mode 100644
index b41db892..00000000
--- a/alliance/share/cells/sxlib/one_x0.al
+++ /dev/null
@@ -1,13 +0,0 @@
-V ALLIANCE : 6
-H one_x0,L,30/10/99
-C q,OUT,EXTERNAL,2
-C vdd,IN,EXTERNAL,1
-C vss,IN,EXTERNAL,3
-T P,0.35,2.9,2,3,1,0,0.75,0.75,7.3,7.3,2.1,9.75,tr_00001
-S 3,EXTERNAL,vss
-Q 0.00473877
-S 2,EXTERNAL,q
-Q 0.00223269
-S 1,EXTERNAL,vdd
-Q 0.0037716
-EOF
diff --git a/alliance/share/cells/sxlib/one_x0.ap b/alliance/share/cells/sxlib/one_x0.ap
deleted file mode 100644
index c5943501..00000000
--- a/alliance/share/cells/sxlib/one_x0.ap
+++ /dev/null
@@ -1,37 +0,0 @@
-V ALLIANCE : 6
-H one_x0,P, 6/ 9/2000,100
-A 0,0,1500,5000
-R 1000,1000,ref_ref,q_10
-R 1000,1500,ref_ref,q_15
-R 1000,2000,ref_ref,q_20
-R 1000,2500,ref_ref,q_25
-R 1000,3000,ref_ref,q_30
-R 1000,3500,ref_ref,q_35
-R 1000,4000,ref_ref,q_40
-S 500,2500,700,2500,300,*,RIGHT,POLY
-S 500,500,1000,500,300,*,RIGHT,PTIE
-S 500,500,500,1500,300,*,DOWN,PTIE
-S 400,4500,1000,4500,300,*,RIGHT,NTIE
-S 500,300,500,2500,200,*,DOWN,ALU1
-S 700,2400,700,2600,100,*,DOWN,POLY
-S 400,3000,400,4700,200,*,UP,ALU1
-S 350,2800,350,3700,400,*,DOWN,PDIF
-S 0,3900,1500,3900,2400,*,RIGHT,NWELL
-S 0,4700,1500,4700,600,vdd,RIGHT,CALU1
-S 0,300,1500,300,600,vss,RIGHT,CALU1
-S 700,2600,700,3900,100,*,UP,PTRANS
-S 1000,2800,1000,3700,300,*,DOWN,PDIF
-S 1000,1000,1000,4000,200,*,DOWN,ALU1
-S 1000,1000,1000,4000,200,q,DOWN,CALU1
-V 400,4500,CONT_BODY_N,*
-V 1000,4500,CONT_BODY_N,*
-V 1000,500,CONT_BODY_P,*
-V 500,1500,CONT_BODY_P,*
-V 500,1000,CONT_BODY_P,*
-V 500,500,CONT_BODY_P,*
-V 500,2500,CONT_POLY,*
-V 400,3000,CONT_DIF_P,*
-V 400,3500,CONT_DIF_P,*
-V 1000,3500,CONT_DIF_P,*
-V 1000,3000,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/one_x0.sym b/alliance/share/cells/sxlib/one_x0.sym
deleted file mode 100644
index 9f9e2854..00000000
Binary files a/alliance/share/cells/sxlib/one_x0.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/one_x0.vbe b/alliance/share/cells/sxlib/one_x0.vbe
deleted file mode 100644
index e7439c59..00000000
--- a/alliance/share/cells/sxlib/one_x0.vbe
+++ /dev/null
@@ -1,20 +0,0 @@
-ENTITY one_x0 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 750;
-  CONSTANT transistors	 : NATURAL := 1
-);
-PORT (
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END one_x0;
-
-ARCHITECTURE behaviour_data_flow OF one_x0 IS
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on one_x0"
-  SEVERITY WARNING;
-  q <= '1';
-END;
diff --git a/alliance/share/cells/sxlib/one_x0.vhd b/alliance/share/cells/sxlib/one_x0.vhd
deleted file mode 100644
index 492070cb..00000000
--- a/alliance/share/cells/sxlib/one_x0.vhd
+++ /dev/null
@@ -1,18 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY one_x0 IS
-PORT(
-  q	: OUT STD_LOGIC
-);
-END one_x0;
-
-ARCHITECTURE RTL OF one_x0 IS
-BEGIN
-  q <= '1';
-END RTL;
diff --git a/alliance/share/cells/sxlib/powmid_x0.ap b/alliance/share/cells/sxlib/powmid_x0.ap
deleted file mode 100644
index 5f076308..00000000
--- a/alliance/share/cells/sxlib/powmid_x0.ap
+++ /dev/null
@@ -1,12 +0,0 @@
-V ALLIANCE : 6
-H powmid_x0,P,18/ 9/2000,100
-A 0,0,3500,5000
-S 0,300,3500,300,600,vss,RIGHT,CALU1
-S 0,4700,3500,4700,600,vdd,RIGHT,CALU1
-S 1000,0,1000,5000,1200,vdd,DOWN,CALU3
-S 2500,0,2500,5000,1200,vss,DOWN,CALU3
-B 2500,0,1200,200,CONT_VIA,*
-B 2500,0,1200,200,CONT_VIA2,*
-B 1000,5000,1200,200,CONT_VIA,*
-B 1000,5000,1200,200,CONT_VIA2,*
-EOF
diff --git a/alliance/share/cells/sxlib/powmid_x0.vbe b/alliance/share/cells/sxlib/powmid_x0.vbe
deleted file mode 100644
index 03293e5d..00000000
--- a/alliance/share/cells/sxlib/powmid_x0.vbe
+++ /dev/null
@@ -1,14 +0,0 @@
-ENTITY powmid_x0 IS
-PORT (
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END powmid_x0;
-
-ARCHITECTURE behaviour_data_flow OF powmid_x0 IS
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on powmid_x0"
-  SEVERITY WARNING;
-END;
diff --git a/alliance/share/cells/sxlib/powmid_x0.vhd b/alliance/share/cells/sxlib/powmid_x0.vhd
deleted file mode 100644
index e6b0b9d0..00000000
--- a/alliance/share/cells/sxlib/powmid_x0.vhd
+++ /dev/null
@@ -1,16 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY powmid_x0 IS
-PORT(
-);
-END powmid_x0;
-
-ARCHITECTURE RTL OF powmid_x0 IS
-BEGIN
-END RTL;
diff --git a/alliance/share/cells/sxlib/rowend_x0.al b/alliance/share/cells/sxlib/rowend_x0.al
deleted file mode 100644
index a54f5a21..00000000
--- a/alliance/share/cells/sxlib/rowend_x0.al
+++ /dev/null
@@ -1,9 +0,0 @@
-V ALLIANCE : 6
-H rowend_x0,L,30/10/99
-C vdd,IN,EXTERNAL,2
-C vss,IN,EXTERNAL,1
-S 2,EXTERNAL,vdd
-Q 0.00126725
-S 1,EXTERNAL,vss
-Q 0.00126725
-EOF
diff --git a/alliance/share/cells/sxlib/rowend_x0.ap b/alliance/share/cells/sxlib/rowend_x0.ap
deleted file mode 100644
index 5674d949..00000000
--- a/alliance/share/cells/sxlib/rowend_x0.ap
+++ /dev/null
@@ -1,7 +0,0 @@
-V ALLIANCE : 6
-H rowend_x0,P,30/ 8/2000,100
-A 0,0,500,5000
-S 0,4700,500,4700,600,vdd,RIGHT,CALU1
-S 0,300,500,300,600,vss,RIGHT,CALU1
-S 0,3900,500,3900,2400,*,RIGHT,NWELL
-EOF
diff --git a/alliance/share/cells/sxlib/rowend_x0.vbe b/alliance/share/cells/sxlib/rowend_x0.vbe
deleted file mode 100644
index a6aa24ba..00000000
--- a/alliance/share/cells/sxlib/rowend_x0.vbe
+++ /dev/null
@@ -1,14 +0,0 @@
-ENTITY rowend_x0 IS
-PORT (
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END rowend_x0;
-
-ARCHITECTURE behaviour_data_flow OF rowend_x0 IS
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on rowend_x0"
-  SEVERITY WARNING;
-END;
diff --git a/alliance/share/cells/sxlib/rowend_x0.vhd b/alliance/share/cells/sxlib/rowend_x0.vhd
deleted file mode 100644
index b21c2701..00000000
--- a/alliance/share/cells/sxlib/rowend_x0.vhd
+++ /dev/null
@@ -1,16 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY rowend_x0 IS
-PORT(
-);
-END rowend_x0;
-
-ARCHITECTURE RTL OF rowend_x0 IS
-BEGIN
-END RTL;
diff --git a/alliance/share/cells/sxlib/sff1_x4.al b/alliance/share/cells/sxlib/sff1_x4.al
deleted file mode 100644
index ea46bf2a..00000000
--- a/alliance/share/cells/sxlib/sff1_x4.al
+++ /dev/null
@@ -1,68 +0,0 @@
-V ALLIANCE : 6
-H sff1_x4,L,30/10/99
-C ck,IN,EXTERNAL,5
-C i,IN,EXTERNAL,6
-C q,OUT,EXTERNAL,13
-C vdd,IN,EXTERNAL,14
-C vss,IN,EXTERNAL,1
-T P,0.35,2.9,17,13,14,0,0.75,0.75,7.3,7.3,21.6,12.75,tr_00026
-T P,0.35,2.9,12,3,17,0,0.75,0.75,7.3,7.3,19.8,12.75,tr_00025
-T P,0.35,2.9,9,2,12,0,0.75,0.75,7.3,7.3,18,12.75,tr_00024
-T P,0.35,2.9,7,2,15,0,0.75,0.75,7.3,7.3,12.6,11.25,tr_00023
-T P,0.35,2.9,15,9,14,0,0.75,0.75,7.3,7.3,14.4,12.75,tr_00022
-T P,0.35,2.9,16,3,7,0,0.75,0.75,7.3,7.3,10.8,11.25,tr_00021
-T P,0.35,2.9,2,5,14,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00020
-T P,0.35,2.9,14,2,3,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00019
-T P,0.35,2.9,4,6,14,0,0.75,0.75,7.3,7.3,7.2,12.75,tr_00018
-T P,0.35,2.9,14,4,16,0,0.75,0.75,7.3,7.3,9,12.75,tr_00017
-T P,0.35,5.9,14,12,13,0,0.75,0.75,13.3,13.3,23.4,11.25,tr_00016
-T P,0.35,5.9,13,12,14,0,0.75,0.75,13.3,13.3,25.2,11.25,tr_00015
-T P,0.35,2.9,9,7,14,0,0.75,0.75,7.3,7.3,16.2,12.75,tr_00014
-T N,0.35,1.4,11,2,12,0,0.75,0.75,4.3,4.3,19.8,3,tr_00013
-T N,0.35,1.4,1,13,11,0,0.75,0.75,4.3,4.3,21.6,3,tr_00012
-T N,0.35,1.4,12,3,9,0,0.75,0.75,4.3,4.3,18,3,tr_00011
-T N,0.35,1.4,1,9,8,0,0.75,0.75,4.3,4.3,14.4,1.5,tr_00010
-T N,0.35,1.4,8,3,7,0,0.75,0.75,4.3,4.3,12.6,3,tr_00009
-T N,0.35,1.4,7,2,10,0,0.75,0.75,4.3,4.3,10.8,3,tr_00008
-T N,0.35,1.4,3,2,1,0,0.75,0.75,4.3,4.3,3.6,3,tr_00007
-T N,0.35,1.4,1,5,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00006
-T N,0.35,1.4,10,4,1,0,0.75,0.75,4.3,4.3,9,3,tr_00005
-T N,0.35,1.4,1,6,4,0,0.75,0.75,4.3,4.3,7.2,3,tr_00004
-T N,0.35,2.9,13,12,1,0,0.75,0.75,7.3,7.3,23.4,2.25,tr_00003
-T N,0.35,2.9,1,12,13,0,0.75,0.75,7.3,7.3,25.2,2.25,tr_00002
-T N,0.35,1.4,9,7,1,0,0.75,0.75,4.3,4.3,16.2,1.5,tr_00001
-S 17,INTERNAL
-Q 0
-S 16,INTERNAL
-Q 0
-S 15,INTERNAL
-Q 0
-S 14,EXTERNAL,vdd
-Q 0.0115377
-S 13,EXTERNAL,q
-Q 0.00615082
-S 12,INTERNAL,sff_s
-Q 0.00679978
-S 11,INTERNAL
-Q 0
-S 10,INTERNAL
-Q 0
-S 9,INTERNAL,y
-Q 0.00480814
-S 8,INTERNAL
-Q 0
-S 7,INTERNAL,sff_m
-Q 0.00642301
-S 6,EXTERNAL,i
-Q 0.00344388
-S 5,EXTERNAL,ck
-Q 0.00344095
-S 4,INTERNAL,u
-Q 0.00567853
-S 3,INTERNAL,ckr
-Q 0.0113963
-S 2,INTERNAL,nckr
-Q 0.0123833
-S 1,EXTERNAL,vss
-Q 0.0103626
-EOF
diff --git a/alliance/share/cells/sxlib/sff1_x4.ap b/alliance/share/cells/sxlib/sff1_x4.ap
deleted file mode 100644
index e8251622..00000000
--- a/alliance/share/cells/sxlib/sff1_x4.ap
+++ /dev/null
@@ -1,221 +0,0 @@
-V ALLIANCE : 6
-H sff1_x4,P,30/ 8/2000,100
-A 0,0,9000,5000
-R 8000,2000,ref_ref,q_20
-R 1000,4000,ref_ref,ck_40
-R 1000,3500,ref_ref,ck_35
-R 1000,3000,ref_ref,ck_30
-R 1000,2500,ref_ref,ck_25
-R 1000,2000,ref_ref,ck_20
-R 1000,1500,ref_ref,ck_15
-R 1000,1000,ref_ref,ck_10
-R 2500,3500,ref_ref,i_35
-R 2500,3000,ref_ref,i_30
-R 2500,2500,ref_ref,i_25
-R 2500,2000,ref_ref,i_20
-R 2500,1500,ref_ref,i_15
-R 3000,1000,ref_ref,i_10
-R 8000,4000,ref_ref,q_40
-R 8000,3500,ref_ref,q_35
-R 8000,3000,ref_ref,q_30
-R 8000,2500,ref_ref,q_25
-R 8000,1500,ref_ref,q_15
-R 8000,1000,ref_ref,q_10
-R 3000,4000,ref_ref,i_40
-S 7300,2000,8400,2000,300,sff_s,RIGHT,POLY
-S 6900,2000,7400,2000,100,*,RIGHT,ALU1
-S 7200,2400,7200,3600,100,*,UP,POLY
-S 2050,1000,2050,4000,100,*,DOWN,ALU1
-S 2550,4000,3000,4000,100,*,RIGHT,ALU1
-S 2550,1000,3000,1000,100,*,RIGHT,ALU1
-S 2550,1000,2550,4000,100,*,DOWN,ALU1
-S 6300,300,6900,300,300,*,RIGHT,PTIE
-S 3300,300,3900,300,300,*,RIGHT,PTIE
-S 1500,300,2100,300,300,*,RIGHT,PTIE
-S 300,3500,300,4000,100,*,DOWN,ALU1
-S 1500,1000,1500,3500,100,*,DOWN,ALU1
-S 5000,3500,5700,3500,100,*,LEFT,ALU1
-S 5700,1000,5700,4000,100,y,DOWN,ALU1
-S 7400,1500,8100,1500,100,*,RIGHT,ALU1
-S 7400,2500,8100,2500,100,*,RIGHT,ALU1
-S 7500,500,7500,1000,200,*,DOWN,ALU1
-S 8700,500,8700,1000,200,*,DOWN,ALU1
-S 7500,3000,7500,4500,200,*,DOWN,ALU1
-S 8700,3000,8700,4500,200,*,DOWN,ALU1
-S 4500,1500,5200,1500,100,*,LEFT,ALU1
-S 3900,1000,4500,1000,100,*,RIGHT,ALU1
-S 5000,1000,5700,1000,100,*,RIGHT,ALU1
-S 6300,2000,6300,3500,100,*,DOWN,ALU1
-S 4500,3000,5200,3000,100,*,RIGHT,ALU1
-S 0,4700,9000,4700,600,vdd,RIGHT,CALU1
-S 0,300,9000,300,600,vss,RIGHT,CALU1
-S 6600,1400,6600,2500,100,*,DOWN,POLY
-S 7800,1400,7800,2600,100,*,DOWN,POLY
-S 7200,1500,7500,1500,300,*,RIGHT,POLY
-S 7200,2500,7500,2500,300,*,RIGHT,POLY
-S 8400,1400,8400,2600,100,*,DOWN,POLY
-S 6000,1400,6000,2000,100,*,DOWN,POLY
-S 5400,900,5400,1500,100,*,UP,POLY
-S 5400,3000,5400,3600,100,*,DOWN,POLY
-S 6000,2500,6000,3600,100,*,DOWN,POLY
-S 4200,1400,4200,2000,100,*,DOWN,POLY
-S 5600,3800,5600,4700,300,*,DOWN,PDIF
-S 5000,3800,5000,4700,300,*,DOWN,PDIF
-S 5400,3600,5400,4900,100,*,UP,PTRANS
-S 8100,2800,8100,4700,300,*,DOWN,PDIF
-S 8400,2600,8400,4900,100,*,DOWN,PTRANS
-S 8700,2800,8700,4700,300,*,DOWN,PDIF
-S 7800,2600,7800,4900,100,*,DOWN,PTRANS
-S 7500,2800,7500,4700,300,*,DOWN,PDIF
-S 3000,3600,3000,4900,100,*,DOWN,PTRANS
-S 6900,3800,6900,4700,300,*,UP,PDIF
-S 2400,3600,2400,4900,100,*,DOWN,PTRANS
-S 2700,3800,2700,4700,300,*,UP,PDIF
-S 2100,3800,2100,4700,300,*,UP,PDIF
-S 5400,100,5400,900,100,*,UP,NTRANS
-S 5700,300,5700,700,300,*,DOWN,NDIF
-S 5100,300,5100,700,300,*,DOWN,NDIF
-S 5700,300,5700,1200,300,*,DOWN,NDIF
-S 7500,300,7500,1200,300,*,DOWN,NDIF
-S 8100,300,8100,1200,300,*,DOWN,NDIF
-S 8400,100,8400,1400,100,*,UP,NTRANS
-S 8700,300,8700,1200,300,*,DOWN,NDIF
-S 6900,800,6900,1200,300,*,DOWN,NDIF
-S 7800,100,7800,1400,100,*,UP,NTRANS
-S 3900,800,3900,1200,300,*,DOWN,NDIF
-S 4500,300,4500,1200,300,*,DOWN,NDIF
-S 2100,800,2100,1200,300,*,DOWN,NDIF
-S 2400,600,2400,1400,100,*,UP,NTRANS
-S 3000,600,3000,1400,100,*,UP,NTRANS
-S 2700,400,2700,1200,300,*,DOWN,NDIF
-S 0,3900,9000,3900,2400,*,RIGHT,NWELL
-S 1200,3100,1200,4400,100,*,DOWN,PTRANS
-S 600,3100,600,4400,100,*,DOWN,PTRANS
-S 300,3300,300,4200,300,*,UP,PDIF
-S 900,3300,900,4600,300,*,UP,PDIF
-S 3500,1500,3500,2500,100,*,DOWN,ALU1
-S 600,3000,900,3000,300,*,RIGHT,POLY
-S 6000,2000,6300,2000,300,*,RIGHT,POLY
-S 3900,2000,4200,2000,300,*,RIGHT,POLY
-S 5100,3000,5400,3000,300,*,RIGHT,POLY
-S 6300,3500,6600,3500,300,*,RIGHT,POLY
-S 4800,3500,5100,3500,300,*,RIGHT,POLY
-S 5100,1500,5400,1500,300,*,RIGHT,POLY
-S 4800,1000,5100,1000,300,*,RIGHT,POLY
-S 2000,3000,3000,3000,100,*,RIGHT,POLY
-S 300,800,300,1200,300,*,DOWN,NDIF
-S 600,600,600,1400,100,*,UP,NTRANS
-S 1500,800,1500,1200,300,*,DOWN,NDIF
-S 1200,600,1200,1400,100,*,UP,NTRANS
-S 300,1000,300,3500,100,*,DOWN,ALU1
-S 900,400,900,1200,300,*,DOWN,NDIF
-S 1200,1400,1200,3100,100,*,DOWN,POLY
-S 600,1500,900,1500,300,*,RIGHT,POLY
-S 1500,3300,1500,4200,300,*,UP,PDIF
-S 300,2500,6600,2500,100,nckr,RIGHT,POLY
-S 1600,2000,6000,2000,100,ckr,RIGHT,POLY
-S 3500,3000,4000,3000,100,*,RIGHT,ALU1
-S 3900,3300,3900,4200,300,*,UP,PDIF
-S 4200,2500,4200,3100,100,*,DOWN,POLY
-S 4000,2000,4000,3000,100,*,UP,ALU1
-S 4500,3300,4500,4700,300,*,UP,PDIF
-S 3000,3100,3000,3600,100,*,UP,POLY
-S 3000,1500,3000,3000,100,u,DOWN,ALU1
-S 3900,3500,4500,3500,100,*,RIGHT,ALU1
-S 6900,1000,6900,4000,100,*,DOWN,ALU1
-S 4500,1000,4500,3500,100,sff_m,DOWN,ALU1
-S 3300,3300,3300,4700,300,*,UP,PDIF
-S 3300,800,3300,1200,300,*,DOWN,NDIF
-S 3600,600,3600,1400,100,*,UP,NTRANS
-S 3600,3100,3600,4400,100,*,DOWN,PTRANS
-S 4800,3600,4800,4900,100,*,DOWN,PTRANS
-S 4200,3100,4200,4400,100,*,DOWN,PTRANS
-S 4200,600,4200,1400,100,*,UP,NTRANS
-S 4800,100,4800,900,100,*,UP,NTRANS
-S 6000,600,6000,1400,100,*,UP,NTRANS
-S 6000,3600,6000,4900,100,*,DOWN,PTRANS
-S 6600,3600,6600,4900,100,*,DOWN,PTRANS
-S 7200,3600,7200,4900,100,*,DOWN,PTRANS
-S 7200,600,7200,1400,100,*,UP,NTRANS
-S 6600,600,6600,1400,100,*,UP,NTRANS
-S 6300,3800,6300,4700,300,*,DOWN,PDIF
-S 6300,800,6300,1200,300,*,DOWN,NDIF
-S 6300,1000,6900,1000,100,*,RIGHT,ALU1
-S 6300,4000,6900,4000,100,*,RIGHT,ALU1
-S 8000,1000,8000,4000,200,q,DOWN,CALU1
-S 1000,1000,1000,4000,200,ck,DOWN,CALU1
-S 1000,1000,1000,4000,100,*,DOWN,ALU1
-S 800,3000,1000,3000,200,*,RIGHT,ALU1
-S 800,1500,1000,1500,200,*,RIGHT,ALU1
-S 2500,1500,2500,3500,200,i,DOWN,CALU1
-S 3000,4000,3000,4000,200,i,LEFT,CALU1
-S 3000,1000,3000,1000,200,i,LEFT,CALU1
-S 8000,1000,8000,4000,200,*,DOWN,ALU1
-V 7400,2000,CONT_POLY,*
-V 300,4000,CONT_DIF_P,*
-V 1500,3500,CONT_DIF_P,*
-V 5000,3500,CONT_POLY,*
-V 7400,2500,CONT_POLY,*
-V 7400,1500,CONT_POLY,*
-V 5200,1500,CONT_POLY,*
-V 6200,2000,CONT_POLY,*
-V 5200,3000,CONT_POLY,*
-V 4000,2000,CONT_POLY,*
-V 5000,1000,CONT_POLY,*
-V 6400,3500,CONT_POLY,*
-V 6300,4000,CONT_DIF_P,*
-V 5100,4500,CONT_DIF_P,*
-V 5700,4000,CONT_DIF_P,*
-V 8700,3000,CONT_DIF_P,*
-V 8100,3000,CONT_DIF_P,*
-V 7500,3000,CONT_DIF_P,*
-V 7500,3500,CONT_DIF_P,*
-V 7500,4000,CONT_DIF_P,*
-V 8700,4500,CONT_DIF_P,*
-V 7500,4500,CONT_DIF_P,*
-V 8700,4000,CONT_DIF_P,*
-V 8700,3500,CONT_DIF_P,*
-V 2700,4500,CONT_DIF_P,*
-V 6300,1000,CONT_DIF_N,*
-V 5100,500,CONT_DIF_N,*
-V 3900,1000,CONT_DIF_N,*
-V 5700,1000,CONT_DIF_N,*
-V 8700,500,CONT_DIF_N,*
-V 7500,500,CONT_DIF_N,*
-V 8700,1000,CONT_DIF_N,*
-V 7500,1000,CONT_DIF_N,*
-V 8100,1000,CONT_DIF_N,*
-V 2700,500,CONT_DIF_N,*
-V 2100,1000,CONT_DIF_N,*
-V 900,500,CONT_DIF_N,*
-V 300,3500,CONT_DIF_P,*
-V 900,4500,CONT_DIF_P,*
-V 800,3000,CONT_POLY,*
-V 300,2500,CONT_POLY,*
-V 1600,2000,CONT_POLY,*
-V 2000,3000,CONT_POLY,*
-V 300,4700,CONT_BODY_N,*
-V 1500,4700,CONT_BODY_N,*
-V 300,300,CONT_BODY_P,*
-V 1500,300,CONT_BODY_P,*
-V 2100,300,CONT_BODY_P,*
-V 3300,300,CONT_BODY_P,*
-V 3900,300,CONT_BODY_P,*
-V 2500,3500,CONT_POLY,*
-V 2500,1500,CONT_POLY,*
-V 3000,1500,CONT_POLY,*
-V 3000,3000,CONT_POLY,*
-V 3500,2500,CONT_POLY,*
-V 3500,1500,CONT_POLY,*
-V 300,1000,CONT_DIF_N,*
-V 1500,1000,CONT_DIF_N,*
-V 800,1500,CONT_POLY,*
-V 8100,4000,CONT_DIF_P,*
-V 8100,3500,CONT_DIF_P,*
-V 6300,300,CONT_BODY_P,*
-V 6900,300,CONT_BODY_P,*
-V 2100,4000,CONT_DIF_P,*
-V 3500,3000,CONT_POLY,*
-V 3900,4700,CONT_BODY_N,*
-V 3900,3500,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/sff1_x4.sym b/alliance/share/cells/sxlib/sff1_x4.sym
deleted file mode 100644
index 6702478b..00000000
Binary files a/alliance/share/cells/sxlib/sff1_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/sff1_x4.vbe b/alliance/share/cells/sxlib/sff1_x4.vbe
deleted file mode 100644
index 4756bfdd..00000000
--- a/alliance/share/cells/sxlib/sff1_x4.vbe
+++ /dev/null
@@ -1,39 +0,0 @@
-ENTITY sff1_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 4500;
-  CONSTANT cin_ck	 : NATURAL := 8;
-  CONSTANT cin_i	 : NATURAL := 8;
-  CONSTANT rdown_ck_q	 : NATURAL := 800;
-  CONSTANT rup_ck_q	 : NATURAL := 890;
-  CONSTANT taf_ck_q	 : NATURAL := 500;
-  CONSTANT tar_ck_q	 : NATURAL := 500;
-  CONSTANT thf_i_ck	 : NATURAL := 0;
-  CONSTANT thr_i_ck	 : NATURAL := 0;
-  CONSTANT tsf_i_ck	 : NATURAL := 585;
-  CONSTANT tsr_i_ck	 : NATURAL := 476;
-  CONSTANT transistors	 : NATURAL := 26
-);
-PORT (
-  ck	 : in  BIT;
-  i	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END sff1_x4;
-
-ARCHITECTURE VBE OF sff1_x4 IS
-  SIGNAL sff_m	 : REG_BIT REGISTER;
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on sff1_x4"
-  SEVERITY WARNING;
-
-  label0 : BLOCK ((ck and not (ck'STABLE)) = '1')
-  BEGIN
-    sff_m <= GUARDED i;
-  END BLOCK label0;
-
-  q <= sff_m after 1700 ps;
-END;
diff --git a/alliance/share/cells/sxlib/sff1_x4.vhd b/alliance/share/cells/sxlib/sff1_x4.vhd
deleted file mode 100644
index b274aa53..00000000
--- a/alliance/share/cells/sxlib/sff1_x4.vhd
+++ /dev/null
@@ -1,27 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY sff1_x4 IS
-PORT(
-  ck	: IN STD_LOGIC;
-  i	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END sff1_x4;
-
-ARCHITECTURE RTL OF sff1_x4 IS
-  SIGNAL sff_m	: STD_LOGIC;
-BEGIN
-  q <= sff_m;
-  PROCESS ( ck )
-  BEGIN
-    IF  ((ck = '1') AND ck'EVENT)
-    THEN sff_m <= i;
-    END IF;
-  END PROCESS;
-END RTL;
diff --git a/alliance/share/cells/sxlib/sff2_x4.al b/alliance/share/cells/sxlib/sff2_x4.al
deleted file mode 100644
index fe6cd3d3..00000000
--- a/alliance/share/cells/sxlib/sff2_x4.al
+++ /dev/null
@@ -1,92 +0,0 @@
-V ALLIANCE : 6
-H sff2_x4,L,30/10/99
-C ck,IN,EXTERNAL,11
-C cmd,IN,EXTERNAL,6
-C i0,IN,EXTERNAL,7
-C i1,IN,EXTERNAL,8
-C q,OUT,EXTERNAL,17
-C vdd,IN,EXTERNAL,19
-C vss,IN,EXTERNAL,1
-T P,0.35,5.9,19,16,17,0,0.75,0.75,13.3,13.3,32.4,11.25,tr_00034
-T P,0.35,2.9,19,3,23,0,0.75,0.75,7.3,7.3,18,12.75,tr_00033
-T P,0.35,2.9,15,14,19,0,0.75,0.75,7.3,7.3,25.2,12.75,tr_00032
-T P,0.35,5.9,17,16,19,0,0.75,0.75,13.3,13.3,34.2,11.25,tr_00031
-T P,0.35,2.9,10,11,19,0,0.75,0.75,7.3,7.3,12.6,11.25,tr_00030
-T P,0.35,2.9,19,10,9,0,0.75,0.75,7.3,7.3,14.4,11.25,tr_00029
-T P,0.35,2.9,3,5,20,0,0.75,0.75,7.3,7.3,7.5,11.25,tr_00028
-T P,0.35,2.9,21,6,3,0,0.75,0.75,7.3,7.3,4.8,11.25,tr_00027
-T P,0.35,2.9,20,8,19,0,0.75,0.75,7.3,7.3,8.7,11.25,tr_00026
-T P,0.35,2.9,5,6,19,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00025
-T P,0.35,2.9,19,7,21,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00024
-T P,0.35,2.9,23,9,14,0,0.75,0.75,7.3,7.3,19.8,11.25,tr_00023
-T P,0.35,2.9,14,10,22,0,0.75,0.75,7.3,7.3,21.6,11.25,tr_00022
-T P,0.35,2.9,22,15,19,0,0.75,0.75,7.3,7.3,23.4,12.75,tr_00021
-T P,0.35,2.9,15,10,16,0,0.75,0.75,7.3,7.3,27,12.75,tr_00020
-T P,0.35,2.9,16,9,24,0,0.75,0.75,7.3,7.3,28.8,12.75,tr_00019
-T P,0.35,2.9,24,17,19,0,0.75,0.75,7.3,7.3,30.6,12.75,tr_00018
-T N,0.35,1.4,12,3,1,0,0.75,0.75,4.3,4.3,18,3,tr_00017
-T N,0.35,2.9,17,16,1,0,0.75,0.75,7.3,7.3,32.4,2.25,tr_00016
-T N,0.35,2.9,1,16,17,0,0.75,0.75,7.3,7.3,34.2,2.25,tr_00015
-T N,0.35,1.4,15,14,1,0,0.75,0.75,4.3,4.3,25.2,1.5,tr_00014
-T N,0.35,1.4,1,11,10,0,0.75,0.75,4.3,4.3,12.6,3,tr_00013
-T N,0.35,1.4,9,10,1,0,0.75,0.75,4.3,4.3,14.4,3,tr_00012
-T N,0.35,1.4,1,8,2,0,0.75,0.75,4.3,4.3,8.7,3,tr_00011
-T N,0.35,1.4,3,5,4,0,0.75,0.75,4.3,4.3,4.8,3,tr_00010
-T N,0.35,1.4,2,6,3,0,0.75,0.75,4.3,4.3,7.5,3,tr_00009
-T N,0.35,1.4,4,7,1,0,0.75,0.75,4.3,4.3,3.6,3,tr_00008
-T N,0.35,1.4,1,6,5,0,0.75,0.75,4.3,4.3,1.8,3,tr_00007
-T N,0.35,1.4,14,10,12,0,0.75,0.75,4.3,4.3,19.8,3,tr_00006
-T N,0.35,1.4,13,9,14,0,0.75,0.75,4.3,4.3,21.6,3,tr_00005
-T N,0.35,1.4,1,15,13,0,0.75,0.75,4.3,4.3,23.4,1.5,tr_00004
-T N,0.35,1.4,16,9,15,0,0.75,0.75,4.3,4.3,27,3,tr_00003
-T N,0.35,1.4,18,10,16,0,0.75,0.75,4.3,4.3,28.8,3,tr_00002
-T N,0.35,1.4,1,17,18,0,0.75,0.75,4.3,4.3,30.6,3,tr_00001
-S 24,INTERNAL
-Q 0
-S 23,INTERNAL
-Q 0
-S 22,INTERNAL
-Q 0
-S 21,INTERNAL
-Q 0
-S 20,INTERNAL
-Q 0
-S 19,EXTERNAL,vdd
-Q 0.0144679
-S 18,INTERNAL
-Q 0
-S 17,EXTERNAL,q
-Q 0.00615082
-S 16,INTERNAL,sff_s
-Q 0.0067122
-S 15,INTERNAL,y
-Q 0.00480814
-S 14,INTERNAL,sff_m
-Q 0.00642301
-S 13,INTERNAL
-Q 0
-S 12,INTERNAL
-Q 0
-S 11,EXTERNAL,ck
-Q 0.0031591
-S 10,INTERNAL,nckr
-Q 0.011396
-S 9,INTERNAL,ckr
-Q 0.0110493
-S 8,EXTERNAL,i1
-Q 0.00242923
-S 7,EXTERNAL,i0
-Q 0.0031591
-S 6,EXTERNAL,cmd
-Q 0.00541426
-S 5,INTERNAL
-Q 0.00654862
-S 4,INTERNAL
-Q 0
-S 3,INTERNAL,u
-Q 0.00667128
-S 2,INTERNAL
-Q 0
-S 1,EXTERNAL,vss
-Q 0.0131165
-EOF
diff --git a/alliance/share/cells/sxlib/sff2_x4.ap b/alliance/share/cells/sxlib/sff2_x4.ap
deleted file mode 100644
index a9e3766c..00000000
--- a/alliance/share/cells/sxlib/sff2_x4.ap
+++ /dev/null
@@ -1,266 +0,0 @@
-V ALLIANCE : 6
-H sff2_x4,P,30/ 8/2000,100
-A 0,0,12000,5000
-R 4500,1000,ref_ref,ck_10
-R 4500,3500,ref_ref,ck_35
-R 4500,3000,ref_ref,ck_30
-R 4500,2500,ref_ref,ck_25
-R 4500,2000,ref_ref,ck_20
-R 4500,1500,ref_ref,ck_15
-R 1000,1500,ref_ref,i0_15
-R 1000,2000,ref_ref,i0_20
-R 1000,2500,ref_ref,i0_25
-R 1000,3500,ref_ref,i0_35
-R 1000,3000,ref_ref,i0_30
-R 1000,4000,ref_ref,i0_40
-R 3000,1000,ref_ref,i1_10
-R 3000,1500,ref_ref,i1_15
-R 3000,2000,ref_ref,i1_20
-R 3000,2500,ref_ref,i1_25
-R 3000,3000,ref_ref,i1_30
-R 3000,3500,ref_ref,i1_35
-R 1500,2500,ref_ref,cmd_25
-R 1500,3000,ref_ref,cmd_30
-R 1500,3500,ref_ref,cmd_35
-R 1500,4000,ref_ref,cmd_40
-R 11000,1000,ref_ref,q_10
-R 11000,1500,ref_ref,q_15
-R 11000,2500,ref_ref,q_25
-R 11000,3000,ref_ref,q_30
-R 11000,3500,ref_ref,q_35
-R 11000,4000,ref_ref,q_40
-R 11000,2000,ref_ref,q_20
-S 11000,1000,11000,4000,200,*,DOWN,ALU1
-S 10200,600,10200,1400,100,*,UP,NTRANS
-S 9600,600,9600,1400,100,*,UP,NTRANS
-S 10200,3600,10200,4900,100,*,DOWN,PTRANS
-S 9600,3600,9600,4900,100,*,DOWN,PTRANS
-S 9000,3600,9000,4900,100,*,DOWN,PTRANS
-S 9000,600,9000,1400,100,*,UP,NTRANS
-S 7800,100,7800,900,100,*,UP,NTRANS
-S 7200,600,7200,1400,100,*,UP,NTRANS
-S 7800,3600,7800,4900,100,*,DOWN,PTRANS
-S 7200,3100,7200,4400,100,*,DOWN,PTRANS
-S 6600,3100,6600,4400,100,*,DOWN,PTRANS
-S 6600,600,6600,1400,100,*,UP,NTRANS
-S 1500,4700,2500,4700,300,*,RIGHT,NTIE
-S 9300,300,9900,300,300,*,RIGHT,PTIE
-S 6300,300,6900,300,300,*,RIGHT,PTIE
-S 1500,300,2500,300,300,*,RIGHT,PTIE
-S 0,3900,12000,3900,2400,*,RIGHT,NWELL
-S 900,400,900,1200,300,*,UP,NDIF
-S 300,800,300,1200,300,*,UP,NDIF
-S 600,600,600,1400,100,*,UP,NTRANS
-S 1200,600,1200,1400,100,*,UP,NTRANS
-S 2500,600,2500,1400,100,*,UP,NTRANS
-S 1900,800,1900,1200,300,*,UP,NDIF
-S 1600,600,1600,1400,100,*,UP,NTRANS
-S 3200,400,3200,1200,300,*,UP,NDIF
-S 2900,600,2900,1400,100,*,UP,NTRANS
-S 2100,800,2100,1600,500,*,DOWN,NDIF
-S 4800,600,4800,1400,100,*,UP,NTRANS
-S 4500,400,4500,1200,300,*,DOWN,NDIF
-S 3900,800,3900,1200,300,*,DOWN,NDIF
-S 4200,600,4200,1400,100,*,UP,NTRANS
-S 5100,800,5100,1200,300,*,DOWN,NDIF
-S 8100,300,8100,700,300,*,DOWN,NDIF
-S 8700,300,8700,700,300,*,DOWN,NDIF
-S 8400,100,8400,900,100,*,UP,NTRANS
-S 11700,300,11700,1200,300,*,DOWN,NDIF
-S 11400,100,11400,1400,100,*,UP,NTRANS
-S 11100,300,11100,1200,300,*,DOWN,NDIF
-S 10500,300,10500,1200,300,*,DOWN,NDIF
-S 8700,300,8700,1200,300,*,DOWN,NDIF
-S 9300,800,9300,1200,300,*,DOWN,NDIF
-S 10800,100,10800,1400,100,*,UP,NTRANS
-S 9900,800,9900,1200,300,*,DOWN,NDIF
-S 5700,400,5700,1200,300,*,DOWN,NDIF
-S 6000,600,6000,1400,100,*,UP,NTRANS
-S 6300,800,6300,1200,300,*,DOWN,NDIF
-S 7500,300,7500,1200,300,*,DOWN,NDIF
-S 6900,800,6900,1200,300,*,DOWN,NDIF
-S 1200,3100,1200,4400,100,*,DOWN,PTRANS
-S 900,3300,900,4600,300,*,DOWN,PDIF
-S 300,3300,300,4200,300,*,DOWN,PDIF
-S 600,3100,600,4400,100,*,DOWN,PTRANS
-S 2900,3100,2900,4400,100,*,DOWN,PTRANS
-S 2000,3300,2000,4200,500,*,DOWN,PDIF
-S 1600,3100,1600,4400,100,*,DOWN,PTRANS
-S 3200,3300,3200,4600,300,*,DOWN,PDIF
-S 2500,3100,2500,4400,100,*,DOWN,PTRANS
-S 5100,3300,5100,4200,300,*,UP,PDIF
-S 4800,3100,4800,4400,100,*,DOWN,PTRANS
-S 4200,3100,4200,4400,100,*,DOWN,PTRANS
-S 3900,3300,3900,4200,300,*,UP,PDIF
-S 8000,3800,8000,4700,300,*,DOWN,PDIF
-S 9300,3800,9300,4700,300,*,DOWN,PDIF
-S 8600,3800,8600,4700,300,*,DOWN,PDIF
-S 4500,3300,4500,4600,300,*,UP,PDIF
-S 11700,2800,11700,4700,300,*,DOWN,PDIF
-S 11400,2600,11400,4900,100,*,DOWN,PTRANS
-S 11100,2800,11100,4700,300,*,DOWN,PDIF
-S 8400,3600,8400,4900,100,*,UP,PTRANS
-S 9900,3800,9900,4700,300,*,UP,PDIF
-S 6000,3600,6000,4900,100,*,DOWN,PTRANS
-S 10500,2800,10500,4700,300,*,DOWN,PDIF
-S 10800,2600,10800,4900,100,*,DOWN,PTRANS
-S 7500,3300,7500,4700,300,*,UP,PDIF
-S 6900,3300,6900,4200,300,*,UP,PDIF
-S 6300,3300,6300,4700,300,*,UP,PDIF
-S 5700,3800,5700,4700,300,*,UP,PDIF
-S 7800,1000,8100,1000,300,*,RIGHT,POLY
-S 8400,900,8400,1500,100,*,UP,POLY
-S 600,2500,2500,2500,100,*,RIGHT,POLY
-S 600,1400,600,3100,100,*,DOWN,POLY
-S 900,1500,1200,1500,300,*,RIGHT,POLY
-S 900,3000,1200,3000,300,*,RIGHT,POLY
-S 2500,1400,2500,2500,100,*,DOWN,POLY
-S 1600,1400,1600,2000,100,*,DOWN,POLY
-S 1600,2500,1600,3100,100,*,DOWN,POLY
-S 4200,3000,4500,3000,300,*,RIGHT,POLY
-S 5100,2000,9000,2000,100,ckr,RIGHT,POLY
-S 3900,2500,9600,2500,100,nckr,RIGHT,POLY
-S 10200,2500,10500,2500,300,*,RIGHT,POLY
-S 10200,1500,10500,1500,300,*,RIGHT,POLY
-S 10800,1400,10800,2600,100,*,DOWN,POLY
-S 9600,1400,9600,2500,100,*,DOWN,POLY
-S 4800,1400,4800,3100,100,*,DOWN,POLY
-S 4200,1500,4500,1500,300,*,RIGHT,POLY
-S 6900,2000,7200,2000,300,*,RIGHT,POLY
-S 9000,2000,9300,2000,300,*,RIGHT,POLY
-S 7200,1400,7200,2000,100,*,DOWN,POLY
-S 9000,2500,9000,3600,100,*,DOWN,POLY
-S 8400,3000,8400,3600,100,*,DOWN,POLY
-S 9000,1400,9000,2000,100,*,DOWN,POLY
-S 11400,1400,11400,2600,100,*,DOWN,POLY
-S 7200,2500,7200,3100,100,*,DOWN,POLY
-S 8100,1500,8400,1500,300,*,RIGHT,POLY
-S 7800,3500,8100,3500,300,*,RIGHT,POLY
-S 9300,3500,9600,3500,300,*,RIGHT,POLY
-S 8100,3000,8400,3000,300,*,RIGHT,POLY
-S 0,300,12000,300,600,vss,RIGHT,CALU1
-S 300,1000,2500,1000,100,*,RIGHT,ALU1
-S 300,1000,300,3500,100,*,DOWN,ALU1
-S 4500,1000,4500,3500,100,*,DOWN,ALU1
-S 5100,1000,5100,3500,100,*,DOWN,ALU1
-S 2500,1000,2500,3000,100,*,DOWN,ALU1
-S 1500,1000,1500,2000,100,*,UP,ALU1
-S 8700,1000,8700,4000,100,y,DOWN,ALU1
-S 3000,1000,3000,3500,100,*,DOWN,ALU1
-S 3900,1000,3900,3500,100,*,DOWN,ALU1
-S 8000,1000,8700,1000,100,*,RIGHT,ALU1
-S 6900,1000,7500,1000,100,*,RIGHT,ALU1
-S 9300,1000,9900,1000,100,*,RIGHT,ALU1
-S 11700,500,11700,1000,200,*,DOWN,ALU1
-S 10500,500,10500,1000,200,*,DOWN,ALU1
-S 0,4700,12000,4700,600,vdd,RIGHT,CALU1
-S 1000,1500,1000,4000,100,*,DOWN,ALU1
-S 2000,4000,6000,4000,100,*,RIGHT,ALU1
-S 1500,2500,1500,4000,100,*,DOWN,ALU1
-S 2000,1500,2000,4000,100,*,DOWN,ALU1
-S 8000,3500,8700,3500,100,*,LEFT,ALU1
-S 11700,3000,11700,4500,200,*,DOWN,ALU1
-S 10500,3000,10500,4500,200,*,DOWN,ALU1
-S 10400,2500,11100,2500,100,*,RIGHT,ALU1
-S 10400,1500,11100,1500,100,*,RIGHT,ALU1
-S 7500,3000,8200,3000,100,*,RIGHT,ALU1
-S 9300,2000,9300,3500,100,*,DOWN,ALU1
-S 7500,1500,8200,1500,100,*,LEFT,ALU1
-S 9300,4000,9900,4000,100,*,RIGHT,ALU1
-S 6900,3500,7500,3500,100,*,RIGHT,ALU1
-S 6000,1500,6000,4000,100,u,DOWN,ALU1
-S 7000,2000,7000,3000,100,*,UP,ALU1
-S 6500,3000,7000,3000,100,*,RIGHT,ALU1
-S 6500,1500,6500,2500,100,*,DOWN,ALU1
-S 7500,1000,7500,3500,100,sff_m,DOWN,ALU1
-S 9900,1000,9900,4000,100,sff_s,DOWN,ALU1
-S 10200,2400,10200,3600,100,*,DOWN,POLY
-S 9900,2000,10400,2000,100,*,RIGHT,ALU1
-S 10400,2000,11400,2000,300,*,RIGHT,POLY
-S 4500,1000,4500,3500,200,ck,DOWN,CALU1
-S 1000,1500,1000,4000,200,i0,DOWN,CALU1
-S 3000,1000,3000,3500,200,i1,DOWN,CALU1
-S 1500,2500,1500,4000,200,cmd,DOWN,CALU1
-S 11000,1000,11000,4000,200,q,DOWN,CALU1
-V 4000,2500,CONT_POLY,*
-V 900,500,CONT_DIF_N,*
-V 300,1000,CONT_DIF_N,*
-V 3200,500,CONT_DIF_N,*
-V 9300,1000,CONT_DIF_N,*
-V 5100,1000,CONT_DIF_N,*
-V 4500,500,CONT_DIF_N,*
-V 3900,1000,CONT_DIF_N,*
-V 11100,1000,CONT_DIF_N,*
-V 10500,1000,CONT_DIF_N,*
-V 11700,1000,CONT_DIF_N,*
-V 10500,500,CONT_DIF_N,*
-V 11700,500,CONT_DIF_N,*
-V 8700,1000,CONT_DIF_N,*
-V 6900,1000,CONT_DIF_N,*
-V 8100,500,CONT_DIF_N,*
-V 5700,500,CONT_DIF_N,*
-V 2000,1500,CONT_DIF_N,*
-V 900,4500,CONT_DIF_P,*
-V 300,3500,CONT_DIF_P,*
-V 3900,3500,CONT_DIF_P,*
-V 5100,3500,CONT_DIF_P,*
-V 3200,4500,CONT_DIF_P,*
-V 10500,3000,CONT_DIF_P,*
-V 11100,3000,CONT_DIF_P,*
-V 11700,3000,CONT_DIF_P,*
-V 8700,4000,CONT_DIF_P,*
-V 8100,4500,CONT_DIF_P,*
-V 9300,4000,CONT_DIF_P,*
-V 4500,4500,CONT_DIF_P,*
-V 2000,3500,CONT_DIF_P,*
-V 11100,4000,CONT_DIF_P,*
-V 5700,4500,CONT_DIF_P,*
-V 11700,3500,CONT_DIF_P,*
-V 11700,4000,CONT_DIF_P,*
-V 10500,4500,CONT_DIF_P,*
-V 11700,4500,CONT_DIF_P,*
-V 10500,4000,CONT_DIF_P,*
-V 10500,3500,CONT_DIF_P,*
-V 6900,3500,CONT_DIF_P,*
-V 11100,3500,CONT_DIF_P,*
-V 300,4700,CONT_BODY_N,*
-V 6900,4700,CONT_BODY_N,*
-V 3900,4700,CONT_BODY_N,*
-V 5100,4700,CONT_BODY_N,*
-V 2500,4700,CONT_BODY_N,*
-V 1500,4700,CONT_BODY_N,*
-V 300,300,CONT_BODY_P,*
-V 9900,300,CONT_BODY_P,*
-V 9300,300,CONT_BODY_P,*
-V 6900,300,CONT_BODY_P,*
-V 6300,300,CONT_BODY_P,*
-V 5100,300,CONT_BODY_P,*
-V 3900,300,CONT_BODY_P,*
-V 1500,300,CONT_BODY_P,*
-V 2500,300,CONT_BODY_P,*
-V 8000,1000,CONT_POLY,*
-V 1000,1500,CONT_POLY,*
-V 1000,3000,CONT_POLY,*
-V 2500,3000,CONT_POLY,*
-V 1500,2500,CONT_POLY,*
-V 1500,2000,CONT_POLY,*
-V 8000,3500,CONT_POLY,*
-V 4400,1500,CONT_POLY,*
-V 4400,3000,CONT_POLY,*
-V 3000,1500,CONT_POLY,*
-V 5200,2000,CONT_POLY,*
-V 5900,3500,CONT_POLY,*
-V 9400,3500,CONT_POLY,*
-V 7000,2000,CONT_POLY,*
-V 8200,3000,CONT_POLY,*
-V 9200,2000,CONT_POLY,*
-V 8200,1500,CONT_POLY,*
-V 10400,1500,CONT_POLY,*
-V 10400,2500,CONT_POLY,*
-V 6500,3000,CONT_POLY,*
-V 6500,1500,CONT_POLY,*
-V 6500,2500,CONT_POLY,*
-V 6000,1500,CONT_POLY,*
-V 3000,3000,CONT_POLY,*
-V 10400,2000,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/sxlib/sff2_x4.sym b/alliance/share/cells/sxlib/sff2_x4.sym
deleted file mode 100644
index 343c2625..00000000
Binary files a/alliance/share/cells/sxlib/sff2_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/sff2_x4.vbe b/alliance/share/cells/sxlib/sff2_x4.vbe
deleted file mode 100644
index 59eaa644..00000000
--- a/alliance/share/cells/sxlib/sff2_x4.vbe
+++ /dev/null
@@ -1,51 +0,0 @@
-ENTITY sff2_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 6000;
-  CONSTANT cin_ck	 : NATURAL := 8;
-  CONSTANT cin_cmd	 : NATURAL := 16;
-  CONSTANT cin_i0	 : NATURAL := 8;
-  CONSTANT cin_i1	 : NATURAL := 7;
-  CONSTANT rdown_ck_q	 : NATURAL := 800;
-  CONSTANT rup_ck_q	 : NATURAL := 890;
-  CONSTANT taf_ck_q	 : NATURAL := 500;
-  CONSTANT tar_ck_q	 : NATURAL := 500;
-  CONSTANT thf_cmd_ck	 : NATURAL := 0;
-  CONSTANT thf_i0_ck	 : NATURAL := 0;
-  CONSTANT thf_i1_ck	 : NATURAL := 0;
-  CONSTANT thr_cmd_ck	 : NATURAL := 0;
-  CONSTANT thr_i0_ck	 : NATURAL := 0;
-  CONSTANT thr_i1_ck	 : NATURAL := 0;
-  CONSTANT tsf_cmd_ck	 : NATURAL := 833;
-  CONSTANT tsf_i0_ck	 : NATURAL := 764;
-  CONSTANT tsf_i1_ck	 : NATURAL := 764;
-  CONSTANT tsr_cmd_ck	 : NATURAL := 770;
-  CONSTANT tsr_i0_ck	 : NATURAL := 666;
-  CONSTANT tsr_i1_ck	 : NATURAL := 666;
-  CONSTANT transistors	 : NATURAL := 34
-);
-PORT (
-  ck	 : in  BIT;
-  cmd	 : in  BIT;
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END sff2_x4;
-
-ARCHITECTURE VBE OF sff2_x4 IS
-  SIGNAL sff_m	 : REG_BIT REGISTER;
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on sff2_x4"
-  SEVERITY WARNING;
-
-  label0 : BLOCK ((ck and not (ck'STABLE)) = '1')
-  BEGIN
-    sff_m <= GUARDED ((i1 and cmd) or (i0 and not (cmd)));
-  END BLOCK label0;
-
-  q <= sff_m after 2000 ps;
-END;
diff --git a/alliance/share/cells/sxlib/sff2_x4.vhd b/alliance/share/cells/sxlib/sff2_x4.vhd
deleted file mode 100644
index f49ef60e..00000000
--- a/alliance/share/cells/sxlib/sff2_x4.vhd
+++ /dev/null
@@ -1,29 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY sff2_x4 IS
-PORT(
-  ck	: IN STD_LOGIC;
-  cmd	: IN STD_LOGIC;
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END sff2_x4;
-
-ARCHITECTURE RTL OF sff2_x4 IS
-  SIGNAL sff_m	: STD_LOGIC;
-BEGIN
-  q <= sff_m;
-  PROCESS ( ck )
-  BEGIN
-    IF  ((ck = '1') AND ck'EVENT)
-    THEN sff_m <= ((i1 AND cmd) OR (i0 AND NOT(cmd)));
-    END IF;
-  END PROCESS;
-END RTL;
diff --git a/alliance/share/cells/sxlib/sff3_x4.al b/alliance/share/cells/sxlib/sff3_x4.al
deleted file mode 100644
index fbf02fa2..00000000
--- a/alliance/share/cells/sxlib/sff3_x4.al
+++ /dev/null
@@ -1,116 +0,0 @@
-V ALLIANCE : 6
-H sff3_x4,L,30/10/99
-C ck,IN,EXTERNAL,15
-C cmd0,IN,EXTERNAL,14
-C cmd1,IN,EXTERNAL,8
-C i0,IN,EXTERNAL,13
-C i1,IN,EXTERNAL,9
-C i2,IN,EXTERNAL,10
-C q,OUT,EXTERNAL,24
-C vdd,IN,EXTERNAL,7
-C vss,IN,EXTERNAL,1
-T P,0.35,2.9,6,13,28,0,0.75,0.75,7.3,7.3,13.8,12.75,tr_00042
-T P,0.35,2,7,14,12,0,0.75,0.75,5.5,5.5,15.6,9.3,tr_00041
-T P,0.35,2.9,28,14,7,0,0.75,0.75,7.3,7.3,12.6,12.75,tr_00040
-T P,0.35,2.9,7,12,27,0,0.75,0.75,7.3,7.3,10.8,12.75,tr_00039
-T P,0.35,2.9,27,9,25,0,0.75,0.75,7.3,7.3,9,12.75,tr_00038
-T P,0.35,2.9,25,2,6,0,0.75,0.75,7.3,7.3,7.8,12.75,tr_00037
-T P,0.35,2,2,8,7,0,0.75,0.75,5.5,5.5,2.4,9.3,tr_00036
-T P,0.35,2.9,6,8,26,0,0.75,0.75,7.3,7.3,6,12.75,tr_00035
-T P,0.35,2.9,26,10,27,0,0.75,0.75,7.3,7.3,4.2,12.75,tr_00034
-T P,0.35,2.9,22,19,21,0,0.75,0.75,7.3,7.3,33,12.75,tr_00033
-T P,0.35,2.9,31,22,7,0,0.75,0.75,7.3,7.3,29.4,12.75,tr_00032
-T P,0.35,2.9,16,19,31,0,0.75,0.75,7.3,7.3,27.6,11.25,tr_00031
-T P,0.35,2.9,30,24,7,0,0.75,0.75,7.3,7.3,36.6,12.75,tr_00030
-T P,0.35,2.9,21,18,30,0,0.75,0.75,7.3,7.3,34.8,12.75,tr_00029
-T P,0.35,5.9,24,21,7,0,0.75,0.75,13.3,13.3,40.2,11.25,tr_00028
-T P,0.35,2.9,22,16,7,0,0.75,0.75,7.3,7.3,31.2,12.75,tr_00027
-T P,0.35,2.9,29,18,16,0,0.75,0.75,7.3,7.3,25.8,11.25,tr_00026
-T P,0.35,5.9,7,21,24,0,0.75,0.75,13.3,13.3,38.4,11.25,tr_00025
-T P,0.35,2.9,7,6,29,0,0.75,0.75,7.3,7.3,24,11.25,tr_00024
-T P,0.35,2.9,18,19,7,0,0.75,0.75,7.3,7.3,22.2,11.25,tr_00023
-T P,0.35,2.9,7,15,19,0,0.75,0.75,7.3,7.3,18.3,11.25,tr_00022
-T N,0.35,1.1,12,14,1,0,0.75,0.75,3.7,3.7,15.6,4.95,tr_00021
-T N,0.35,1.1,1,8,2,0,0.75,0.75,3.7,3.7,2.4,5.25,tr_00020
-T N,0.35,1.7,6,13,11,0,0.75,0.75,4.9,4.9,13.8,1.95,tr_00019
-T N,0.35,1.7,1,14,4,0,0.75,0.75,4.9,4.9,10.8,1.95,tr_00018
-T N,0.35,1.7,11,12,1,0,0.75,0.75,4.9,4.9,12.6,1.95,tr_00017
-T N,0.35,1.7,6,2,3,0,0.75,0.75,4.9,4.9,6,2.55,tr_00016
-T N,0.35,1.7,5,8,6,0,0.75,0.75,4.9,4.9,7.8,2.55,tr_00015
-T N,0.35,1.7,4,9,5,0,0.75,0.75,4.9,4.9,9,2.55,tr_00014
-T N,0.35,1.7,3,10,4,0,0.75,0.75,4.9,4.9,4.2,2.55,tr_00013
-T N,0.35,1.4,16,19,17,0,0.75,0.75,4.3,4.3,25.8,3,tr_00012
-T N,0.35,1.4,1,24,20,0,0.75,0.75,4.3,4.3,36.6,3,tr_00011
-T N,0.35,1.4,20,19,21,0,0.75,0.75,4.3,4.3,34.8,3,tr_00010
-T N,0.35,1.4,21,18,22,0,0.75,0.75,4.3,4.3,33,3,tr_00009
-T N,0.35,1.4,1,22,23,0,0.75,0.75,4.3,4.3,29.4,1.5,tr_00008
-T N,0.35,1.4,23,18,16,0,0.75,0.75,4.3,4.3,27.6,3,tr_00007
-T N,0.35,1.4,22,16,1,0,0.75,0.75,4.3,4.3,31.2,1.5,tr_00006
-T N,0.35,2.9,24,21,1,0,0.75,0.75,7.3,7.3,38.4,2.25,tr_00005
-T N,0.35,2.9,1,21,24,0,0.75,0.75,7.3,7.3,40.2,2.25,tr_00004
-T N,0.35,1.4,17,6,1,0,0.75,0.75,4.3,4.3,24,3,tr_00003
-T N,0.35,1.4,1,19,18,0,0.75,0.75,4.3,4.3,22.2,3,tr_00002
-T N,0.35,1.4,19,15,1,0,0.75,0.75,4.3,4.3,18.3,3,tr_00001
-S 31,INTERNAL
-Q 0
-S 30,INTERNAL
-Q 0
-S 29,INTERNAL
-Q 0
-S 28,INTERNAL
-Q 0
-S 27,INTERNAL
-Q 0.00170541
-S 26,INTERNAL
-Q 0
-S 25,INTERNAL
-Q 0
-S 24,EXTERNAL,q
-Q 0.00615082
-S 23,INTERNAL
-Q 0
-S 22,INTERNAL,y
-Q 0.00480814
-S 21,INTERNAL,sff_s
-Q 0.00671219
-S 20,INTERNAL
-Q 0
-S 19,INTERNAL,nckr
-Q 0.0114885
-S 18,INTERNAL,ckr
-Q 0.0113072
-S 17,INTERNAL
-Q 0
-S 16,INTERNAL,sff_m
-Q 0.00642301
-S 15,EXTERNAL,ck
-Q 0.00323647
-S 14,EXTERNAL,cmd0
-Q 0.00553121
-S 13,EXTERNAL,i0
-Q 0.00386191
-S 12,INTERNAL
-Q 0.0057783
-S 11,INTERNAL
-Q 0
-S 10,EXTERNAL,i2
-Q 0.0021309
-S 9,EXTERNAL,i1
-Q 0.0025589
-S 8,EXTERNAL,cmd1
-Q 0.00604152
-S 7,EXTERNAL,vdd
-Q 0.0159513
-S 6,INTERNAL,u
-Q 0.0112516
-S 5,INTERNAL
-Q 0
-S 4,INTERNAL
-Q 0.00170541
-S 3,INTERNAL
-Q 0
-S 2,INTERNAL
-Q 0.00547335
-S 1,EXTERNAL,vss
-Q 0.0145999
-EOF
diff --git a/alliance/share/cells/sxlib/sff3_x4.ap b/alliance/share/cells/sxlib/sff3_x4.ap
deleted file mode 100644
index 347549d1..00000000
--- a/alliance/share/cells/sxlib/sff3_x4.ap
+++ /dev/null
@@ -1,341 +0,0 @@
-V ALLIANCE : 6
-H sff3_x4,P, 6/ 9/2000,100
-A 0,0,14000,5000
-R 4500,2500,ref_ref,i0_25
-R 4000,3000,ref_ref,i0_30
-R 4000,2000,ref_ref,i0_20
-R 3500,3000,ref_ref,cmd0_30
-R 3500,2500,ref_ref,cmd0_25
-R 3500,2000,ref_ref,cmd0_20
-R 2500,2500,ref_ref,i1_25
-R 1500,2500,ref_ref,i2_25
-R 500,3500,ref_ref,cmd1_35
-R 500,3000,ref_ref,cmd1_30
-R 500,2500,ref_ref,cmd1_25
-R 500,2000,ref_ref,cmd1_20
-R 500,1500,ref_ref,cmd1_15
-R 13000,3500,ref_ref,q_35
-R 13000,4000,ref_ref,q_40
-R 13000,2000,ref_ref,q_20
-R 13000,1500,ref_ref,q_15
-R 13000,2500,ref_ref,q_25
-R 13000,3000,ref_ref,q_30
-R 13000,1000,ref_ref,q_10
-R 6000,2000,ref_ref,ck_20
-R 6000,1500,ref_ref,ck_15
-R 6000,2500,ref_ref,ck_25
-R 6000,3000,ref_ref,ck_30
-R 6000,3500,ref_ref,ck_35
-R 6000,1000,ref_ref,ck_10
-S 4400,3000,4600,3000,300,*,RIGHT,POLY
-S 4400,2000,4600,2000,300,*,RIGHT,POLY
-S 1800,3500,2000,3500,300,*,RIGHT,POLY
-S 1800,1500,2000,1500,300,*,RIGHT,POLY
-S 13000,1000,13000,4000,200,*,DOWN,ALU1
-S 4000,2000,4000,2000,200,i0,LEFT,CALU1
-S 4000,3000,4000,3000,200,i0,LEFT,CALU1
-S 4500,2500,4500,2500,200,i0,LEFT,CALU1
-S 3500,2000,3500,3000,200,cmd0,DOWN,CALU1
-S 2500,2500,2500,2500,200,i1,LEFT,CALU1
-S 1500,2500,1500,2500,200,i2,LEFT,CALU1
-S 500,1500,500,3500,200,cmd1,DOWN,CALU1
-S 13000,1000,13000,4000,200,q,DOWN,CALU1
-S 6000,1000,6000,3500,200,ck,DOWN,CALU1
-S 5000,1800,5000,3000,100,*,DOWN,ALU1
-S 4900,1700,5000,1700,100,*,LEFT,ALU1
-S 3500,2500,3900,2500,200,*,RIGHT,ALU1
-S 4900,1500,4900,1700,200,*,DOWN,ALU1
-S 4900,3500,4900,4000,100,*,DOWN,ALU1
-S 4000,3000,4400,3000,200,*,RIGHT,ALU1
-S 4000,2000,4400,2000,200,*,RIGHT,ALU1
-S 3500,2000,3500,3000,100,*,DOWN,ALU1
-S 3000,2000,3000,3500,100,*,UP,ALU1
-S 4900,3000,5000,3000,100,*,RIGHT,ALU1
-S 4400,2000,4400,3000,100,*,UP,ALU1
-S 3400,1500,4900,1500,100,*,RIGHT,ALU1
-S 1000,3000,1800,3000,100,*,LEFT,ALU1
-S 1100,4000,3300,4000,100,*,RIGHT,ALU1
-S 2300,1500,2800,1500,100,*,RIGHT,ALU1
-S 2800,1500,2800,2000,100,*,UP,ALU1
-S 500,3500,1800,3500,100,*,LEFT,ALU1
-S 500,4000,500,4600,200,*,UP,ALU1
-S 2000,2000,2000,3000,100,*,UP,ALU1
-S 1000,1800,1000,3000,100,*,UP,ALU1
-S 500,1500,500,3500,100,*,DOWN,ALU1
-S 1800,1500,1800,2000,100,*,UP,ALU1
-S 1800,2000,1900,2000,100,*,RIGHT,ALU1
-S 2300,3500,5500,3500,100,*,RIGHT,ALU1
-S 2800,2000,3000,2000,100,*,RIGHT,ALU1
-S 1800,3000,2500,3000,100,*,LEFT,ALU1
-S 5500,1000,5500,3500,100,*,DOWN,ALU1
-S 4900,1000,5500,1000,100,*,RIGHT,ALU1
-S 500,400,500,1000,200,*,DOWN,ALU1
-S 1100,1000,3300,1000,100,*,RIGHT,ALU1
-S 3500,1500,3500,3600,100,*,UP,POLY
-S 3500,3600,3600,3600,100,*,RIGHT,POLY
-S 4400,3000,4600,3000,100,*,RIGHT,POLY
-S 4600,3000,4600,3600,100,*,UP,POLY
-S 4000,1900,4000,3300,100,*,DOWN,POLY
-S 4500,2000,4600,2000,100,*,RIGHT,POLY
-S 4600,1100,4600,2000,100,*,DOWN,POLY
-S 4200,1100,4200,1500,100,*,UP,POLY
-S 5200,2000,5200,2600,100,*,DOWN,POLY
-S 4000,3600,4200,3600,100,*,LEFT,POLY
-S 4000,3300,4000,3600,100,*,UP,POLY
-S 3000,1300,3000,3600,100,*,DOWN,POLY
-S 3600,1100,3800,1100,100,*,RIGHT,POLY
-S 3300,1500,3400,1500,100,*,LEFT,POLY
-S 4000,2500,5200,2500,100,*,RIGHT,POLY
-S 3800,1100,3800,1900,100,*,DOWN,POLY
-S 3800,1900,4000,1900,100,*,LEFT,POLY
-S 2000,2000,2000,3600,100,*,DOWN,POLY
-S 500,2500,800,2500,300,*,RIGHT,POLY
-S 800,2100,800,2600,100,*,DOWN,POLY
-S 1800,1500,2000,1500,100,*,RIGHT,POLY
-S 2600,3000,2600,3600,100,*,UP,POLY
-S 2600,1300,2600,2000,100,*,UP,POLY
-S 2000,1300,2000,1500,100,*,DOWN,POLY
-S 1400,1300,1400,3600,100,*,DOWN,POLY
-S 2500,2500,3000,2500,100,*,RIGHT,POLY
-S 2000,2000,2600,2000,100,*,RIGHT,POLY
-S 4900,1500,4900,1700,300,*,DOWN,NDIF
-S 5200,1300,5200,2000,100,*,DOWN,NTRANS
-S 1100,1600,1100,1900,300,*,UP,NDIF
-S 800,1400,800,2100,100,*,DOWN,NTRANS
-S 3300,400,3300,1100,300,*,DOWN,NDIF
-S 4600,200,4600,1100,100,*,UP,NTRANS
-S 4900,500,4900,1000,300,*,UP,NDIF
-S 3600,200,3600,1100,100,*,UP,NTRANS
-S 3900,400,3900,900,200,*,DOWN,NDIF
-S 4200,200,4200,1100,100,*,UP,NTRANS
-S 2000,400,2000,1300,100,*,UP,NTRANS
-S 2600,400,2600,1300,100,*,UP,NTRANS
-S 3000,400,3000,1300,100,*,UP,NTRANS
-S 500,1000,500,1900,300,*,DOWN,NDIF
-S 1400,400,1400,1300,100,*,UP,NTRANS
-S 1100,600,1100,1000,300,*,DOWN,NDIF
-S 1700,600,1700,1100,200,*,DOWN,NDIF
-S 2300,600,2300,1600,300,*,UP,NDIF
-S 4900,3800,4900,4700,300,*,UP,PDIF
-S 3900,3800,3900,4700,200,*,UP,PDIF
-S 4600,3600,4600,4900,100,*,UP,PTRANS
-S 3300,3800,3300,4700,200,*,UP,PDIF
-S 4900,2800,4900,3400,300,*,UP,PDIF
-S 5200,2600,5200,3600,100,*,UP,PTRANS
-S 4200,3600,4200,4900,100,*,UP,PTRANS
-S 3600,3600,3600,4900,100,*,UP,PTRANS
-S 3000,3600,3000,4900,100,*,UP,PTRANS
-S 2600,3600,2600,4900,100,*,UP,PTRANS
-S 1100,2800,1100,3400,300,*,UP,PDIF
-S 800,2600,800,3600,100,*,UP,PTRANS
-S 500,2800,500,4000,300,*,UP,PDIF
-S 2000,3600,2000,4900,100,*,UP,PTRANS
-S 2300,3500,2300,4700,300,*,UP,PDIF
-S 1700,3800,1700,4700,200,*,DOWN,PDIF
-S 1400,3600,1400,4900,100,*,UP,PTRANS
-S 1100,3800,1100,4700,300,*,UP,PDIF
-S 10000,3500,10700,3500,100,*,LEFT,ALU1
-S 13700,3000,13700,4500,200,*,DOWN,ALU1
-S 12500,3000,12500,4500,200,*,DOWN,ALU1
-S 12400,2500,13100,2500,100,*,RIGHT,ALU1
-S 12400,1500,13100,1500,100,*,RIGHT,ALU1
-S 9500,3000,10200,3000,100,*,RIGHT,ALU1
-S 11300,2000,11300,3500,100,*,DOWN,ALU1
-S 9500,1500,10200,1500,100,*,LEFT,ALU1
-S 11300,4000,11900,4000,100,*,RIGHT,ALU1
-S 8900,3500,9500,3500,100,*,RIGHT,ALU1
-S 8000,1500,8000,4000,100,u,DOWN,ALU1
-S 8500,1500,8500,2500,100,*,DOWN,ALU1
-S 11900,2000,12400,2000,100,*,RIGHT,ALU1
-S 10700,1000,10700,4000,100,y,DOWN,ALU1
-S 8900,1000,9500,1000,100,*,RIGHT,ALU1
-S 11300,1000,11900,1000,100,*,RIGHT,ALU1
-S 13700,500,13700,1000,200,*,DOWN,ALU1
-S 12500,500,12500,1000,200,*,DOWN,ALU1
-S 9500,1000,9500,3500,100,sff_m,DOWN,ALU1
-S 11900,1000,11900,4000,100,sff_s,DOWN,ALU1
-S 10000,1000,10700,1000,100,*,RIGHT,ALU1
-S 12200,2500,12500,2500,300,*,RIGHT,POLY
-S 12200,1500,12500,1500,300,*,RIGHT,POLY
-S 12800,1400,12800,2600,100,*,DOWN,POLY
-S 11600,1400,11600,2500,100,*,DOWN,POLY
-S 8900,2000,9200,2000,300,*,RIGHT,POLY
-S 11000,2000,11300,2000,300,*,RIGHT,POLY
-S 9200,1400,9200,2000,100,*,DOWN,POLY
-S 11000,2500,11000,3600,100,*,DOWN,POLY
-S 10400,3000,10400,3600,100,*,DOWN,POLY
-S 11000,1400,11000,2000,100,*,DOWN,POLY
-S 10100,1500,10400,1500,300,*,RIGHT,POLY
-S 9800,3500,10100,3500,300,*,RIGHT,POLY
-S 11300,3500,11600,3500,300,*,RIGHT,POLY
-S 10100,3000,10400,3000,300,*,RIGHT,POLY
-S 12200,2400,12200,3600,100,*,DOWN,POLY
-S 12400,2000,13400,2000,300,*,RIGHT,POLY
-S 13400,1400,13400,2600,100,*,DOWN,POLY
-S 9200,2500,9200,3100,100,*,DOWN,POLY
-S 7100,3100,7400,3100,100,*,RIGHT,POLY
-S 7100,1400,7400,1400,100,*,RIGHT,POLY
-S 7100,1400,7100,3100,100,*,DOWN,POLY
-S 7500,2000,11000,2000,100,ckr,RIGHT,POLY
-S 9800,1000,10100,1000,300,*,RIGHT,POLY
-S 10400,900,10400,1500,100,*,UP,POLY
-S 11300,300,11900,300,300,*,RIGHT,PTIE
-S 8300,300,8900,300,300,*,RIGHT,PTIE
-S 8600,600,8600,1400,100,*,UP,NTRANS
-S 12200,600,12200,1400,100,*,UP,NTRANS
-S 11600,600,11600,1400,100,*,UP,NTRANS
-S 11000,600,11000,1400,100,*,UP,NTRANS
-S 9800,100,9800,900,100,*,UP,NTRANS
-S 9200,600,9200,1400,100,*,UP,NTRANS
-S 10700,300,10700,700,300,*,DOWN,NDIF
-S 10400,100,10400,900,100,*,UP,NTRANS
-S 12500,300,12500,1200,300,*,DOWN,NDIF
-S 10700,300,10700,1200,300,*,DOWN,NDIF
-S 11300,800,11300,1200,300,*,DOWN,NDIF
-S 12800,100,12800,1400,100,*,UP,NTRANS
-S 7100,800,7100,1200,300,*,DOWN,NDIF
-S 10100,300,10100,700,300,*,DOWN,NDIF
-S 8300,800,8300,1200,300,*,DOWN,NDIF
-S 9500,300,9500,1200,300,*,DOWN,NDIF
-S 8900,800,8900,1200,300,*,DOWN,NDIF
-S 13700,300,13700,1200,300,*,DOWN,NDIF
-S 13400,100,13400,1400,100,*,UP,NTRANS
-S 13100,300,13100,1200,300,*,DOWN,NDIF
-S 11900,800,11900,1200,300,*,DOWN,NDIF
-S 7700,400,7700,1200,300,*,DOWN,NDIF
-S 8000,600,8000,1400,100,*,UP,NTRANS
-S 7400,600,7400,1400,100,*,UP,NTRANS
-S 11000,3600,11000,4900,100,*,DOWN,PTRANS
-S 9800,3600,9800,4900,100,*,DOWN,PTRANS
-S 9200,3100,9200,4400,100,*,DOWN,PTRANS
-S 12200,3600,12200,4900,100,*,DOWN,PTRANS
-S 11600,3600,11600,4900,100,*,DOWN,PTRANS
-S 13700,2800,13700,4700,300,*,DOWN,PDIF
-S 13400,2600,13400,4900,100,*,DOWN,PTRANS
-S 13100,2800,13100,4700,300,*,DOWN,PDIF
-S 10400,3600,10400,4900,100,*,UP,PTRANS
-S 7100,3300,7100,4200,300,*,UP,PDIF
-S 8600,3100,8600,4400,100,*,DOWN,PTRANS
-S 9500,3300,9500,4700,300,*,UP,PDIF
-S 8900,3300,8900,4200,300,*,UP,PDIF
-S 10000,3800,10000,4700,300,*,DOWN,PDIF
-S 11300,3800,11300,4700,300,*,DOWN,PDIF
-S 10600,3800,10600,4700,300,*,DOWN,PDIF
-S 11900,3800,11900,4700,300,*,UP,PDIF
-S 12500,2800,12500,4700,300,*,DOWN,PDIF
-S 12800,2600,12800,4900,100,*,DOWN,PTRANS
-S 8300,3300,8300,4200,300,*,UP,PDIF
-S 7700,3300,7700,4600,300,*,UP,PDIF
-S 8000,3100,8000,4400,100,*,DOWN,PTRANS
-S 7400,3100,7400,4400,100,*,DOWN,PTRANS
-S 0,3900,14000,3900,2400,*,RIGHT,NWELL
-S 0,4700,14000,4700,600,vdd,RIGHT,CALU1
-S 0,300,14000,300,600,vss,RIGHT,CALU1
-S 4900,4000,8000,4000,100,*,RIGHT,ALU1
-S 6000,1000,6000,3500,100,*,DOWN,ALU1
-S 6100,1400,6100,3100,100,*,DOWN,POLY
-S 6100,3100,6100,4400,100,*,DOWN,PTRANS
-S 6100,600,6100,1400,100,*,UP,NTRANS
-S 6400,800,6400,1200,300,*,DOWN,NDIF
-S 6400,3300,6400,4200,300,*,UP,PDIF
-S 5600,2800,5600,4600,500,*,DOWN,PDIF
-S 5600,400,5600,1800,500,*,DOWN,NDIF
-S 6500,3300,6500,4200,300,*,UP,PDIF
-S 6500,800,6500,1200,300,*,DOWN,NDIF
-S 6500,1000,6500,3500,100,*,DOWN,ALU1
-S 8600,2950,9000,2950,100,*,RIGHT,ALU1
-S 7100,1050,7500,1050,100,*,RIGHT,ALU1
-S 9000,2000,9000,2950,100,*,UP,ALU1
-S 7100,3450,7500,3450,100,*,LEFT,ALU1
-S 7500,1050,7500,3450,100,*,UP,ALU1
-S 6600,2500,11600,2500,100,nckr,RIGHT,POLY
-V 5500,4500,CONT_DIF_P,*
-V 4400,3000,CONT_POLY,*
-V 4400,2000,CONT_POLY,*
-V 3900,2500,CONT_POLY,*
-V 4200,1500,CONT_POLY,*
-V 3400,1500,CONT_POLY,*
-V 2500,3000,CONT_POLY,*
-V 1500,2500,CONT_POLY,*
-V 2500,2500,CONT_POLY,*
-V 500,2500,CONT_POLY,*
-V 1800,1500,CONT_POLY,*
-V 1800,3500,CONT_POLY,*
-V 500,400,CONT_BODY_P,*
-V 4900,1700,CONT_DIF_N,*
-V 2300,1500,CONT_DIF_N,*
-V 1100,1800,CONT_DIF_N,*
-V 1100,1800,CONT_DIF_N,*
-V 3300,1000,CONT_DIF_N,*
-V 3900,500,CONT_DIF_N,*
-V 4900,1000,CONT_DIF_N,*
-V 5500,500,CONT_DIF_N,*
-V 500,1000,CONT_DIF_N,*
-V 1100,1000,CONT_DIF_N,*
-V 3300,4000,CONT_DIF_P,*
-V 3900,4500,CONT_DIF_P,*
-V 4900,4000,CONT_DIF_P,*
-V 4900,3000,CONT_DIF_P,*
-V 2300,3500,CONT_DIF_P,*
-V 1100,4000,CONT_DIF_P,*
-V 1100,3000,CONT_DIF_P,*
-V 500,4000,CONT_DIF_P,*
-V 500,4600,CONT_BODY_N,*
-V 10000,3500,CONT_POLY,*
-V 11400,3500,CONT_POLY,*
-V 9000,2000,CONT_POLY,*
-V 10200,3000,CONT_POLY,*
-V 11200,2000,CONT_POLY,*
-V 10200,1500,CONT_POLY,*
-V 12400,1500,CONT_POLY,*
-V 12400,2500,CONT_POLY,*
-V 8500,2500,CONT_POLY,*
-V 12400,2000,CONT_POLY,*
-V 7500,2000,CONT_POLY,*
-V 8600,3000,CONT_POLY,*
-V 8000,3000,CONT_POLY,*
-V 8600,1500,CONT_POLY,*
-V 8000,1500,CONT_POLY,*
-V 10000,1000,CONT_POLY,*
-V 7100,300,CONT_BODY_P,*
-V 8900,300,CONT_BODY_P,*
-V 11300,300,CONT_BODY_P,*
-V 11900,300,CONT_BODY_P,*
-V 8300,300,CONT_BODY_P,*
-V 7100,1000,CONT_DIF_N,*
-V 13100,1000,CONT_DIF_N,*
-V 12500,1000,CONT_DIF_N,*
-V 13700,1000,CONT_DIF_N,*
-V 12500,500,CONT_DIF_N,*
-V 13700,500,CONT_DIF_N,*
-V 10700,1000,CONT_DIF_N,*
-V 8900,1000,CONT_DIF_N,*
-V 11300,1000,CONT_DIF_N,*
-V 10100,500,CONT_DIF_N,*
-V 7700,500,CONT_DIF_N,*
-V 12500,3000,CONT_DIF_P,*
-V 13100,3000,CONT_DIF_P,*
-V 13700,3000,CONT_DIF_P,*
-V 10700,4000,CONT_DIF_P,*
-V 10100,4500,CONT_DIF_P,*
-V 13100,4000,CONT_DIF_P,*
-V 13700,3500,CONT_DIF_P,*
-V 13700,4000,CONT_DIF_P,*
-V 12500,4500,CONT_DIF_P,*
-V 7100,3500,CONT_DIF_P,*
-V 13700,4500,CONT_DIF_P,*
-V 12500,4000,CONT_DIF_P,*
-V 12500,3500,CONT_DIF_P,*
-V 8900,3500,CONT_DIF_P,*
-V 13100,3500,CONT_DIF_P,*
-V 8900,4700,CONT_BODY_N,*
-V 11300,4000,CONT_DIF_P,*
-V 7100,4700,CONT_BODY_N,*
-V 7700,4600,CONT_DIF_P,*
-V 6000,2500,CONT_POLY,*
-V 6600,2500,CONT_POLY,*
-V 6500,1000,CONT_DIF_N,*
-V 6500,3500,CONT_DIF_P,*
-V 6400,4700,CONT_BODY_N,*
-V 6400,300,CONT_BODY_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/sff3_x4.vbe b/alliance/share/cells/sxlib/sff3_x4.vbe
deleted file mode 100644
index a1953ab9..00000000
--- a/alliance/share/cells/sxlib/sff3_x4.vbe
+++ /dev/null
@@ -1,65 +0,0 @@
-ENTITY sff3_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 7000;
-  CONSTANT cin_ck	 : NATURAL := 8;
-  CONSTANT cin_cmd0	 : NATURAL := 15;
-  CONSTANT cin_cmd1	 : NATURAL := 15;
-  CONSTANT cin_i0	 : NATURAL := 9;
-  CONSTANT cin_i1	 : NATURAL := 8;
-  CONSTANT cin_i2	 : NATURAL := 8;
-  CONSTANT rdown_ck_q	 : NATURAL := 890;
-  CONSTANT rup_ck_q	 : NATURAL := 810;
-  CONSTANT taf_ck_q	 : NATURAL := 600;
-  CONSTANT tar_ck_q	 : NATURAL := 600;
-  CONSTANT thf_ck_q	 : NATURAL := 0;
-  CONSTANT thf_cmd0_ck	 : NATURAL := 0;
-  CONSTANT thf_cmd1_ck	 : NATURAL := 0;
-  CONSTANT thf_i0_ck	 : NATURAL := 0;
-  CONSTANT thf_i1_ck	 : NATURAL := 0;
-  CONSTANT thf_i2_ck	 : NATURAL := 0;
-  CONSTANT thr_ck_q	 : NATURAL := 0;
-  CONSTANT thr_cmd0_ck	 : NATURAL := 0;
-  CONSTANT thr_cmd1_ck	 : NATURAL := 0;
-  CONSTANT thr_i0_ck	 : NATURAL := 0;
-  CONSTANT thr_i1_ck	 : NATURAL := 0;
-  CONSTANT thr_i2_ck	 : NATURAL := 0;
-  CONSTANT tsf_cmd0_ck	 : NATURAL := 1200;
-  CONSTANT tsf_cmd1_ck	 : NATURAL := 1200;
-  CONSTANT tsf_i0_ck	 : NATURAL := 1200;
-  CONSTANT tsf_i1_ck	 : NATURAL := 1200;
-  CONSTANT tsf_i2_ck	 : NATURAL := 1200;
-  CONSTANT tsr_cmd0_ck	 : NATURAL := 1100;
-  CONSTANT tsr_cmd1_ck	 : NATURAL := 1100;
-  CONSTANT tsr_i0_ck	 : NATURAL := 850;
-  CONSTANT tsr_i1_ck	 : NATURAL := 950;
-  CONSTANT tsr_i2_ck	 : NATURAL := 950;
-  CONSTANT transistors	 : NATURAL := 42
-);
-PORT (
-  ck	 : in  BIT;
-  cmd0	 : in  BIT;
-  cmd1	 : in  BIT;
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  i2	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END sff3_x4;
-
-ARCHITECTURE behaviour_data_flow OF sff3_x4 IS
-  SIGNAL sff_m	 : REG_BIT REGISTER;
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on sff3_x4"
-  SEVERITY WARNING;
-
-  label0 : BLOCK ((ck and not (ck'STABLE)) = '1')
-  BEGIN
-    sff_m <= GUARDED ((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not (cmd1) and i2))));
-  END BLOCK label0;
-
-  q <= sff_m after 2400 ps;
-END;
diff --git a/alliance/share/cells/sxlib/sff3_x4.vhd b/alliance/share/cells/sxlib/sff3_x4.vhd
deleted file mode 100644
index a99d02f2..00000000
--- a/alliance/share/cells/sxlib/sff3_x4.vhd
+++ /dev/null
@@ -1,31 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY sff3_x4 IS
-PORT(
-  ck	: IN STD_LOGIC;
-  cmd0	: IN STD_LOGIC;
-  cmd1	: IN STD_LOGIC;
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  i2	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END sff3_x4;
-
-ARCHITECTURE RTL OF sff3_x4 IS
-  SIGNAL sff_m	: STD_LOGIC;
-BEGIN
-  q <= sff_m;
-  PROCESS ( ck )
-  BEGIN
-    IF  ((ck = '1') AND ck'EVENT)
-    THEN sff_m <= ((NOT(cmd0) AND i0) OR (cmd0 AND ((cmd1 AND i1) OR (NOT(cmd1) AND i2))));
-    END IF;
-  END PROCESS;
-END RTL;
diff --git a/alliance/share/cells/sxlib/sxlib.cct b/alliance/share/cells/sxlib/sxlib.cct
deleted file mode 100644
index c13bceff..00000000
--- a/alliance/share/cells/sxlib/sxlib.cct
+++ /dev/null
@@ -1,1018 +0,0 @@
-Circuit a2_x2 (
- Input    i0 ,
- Input    i1 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := (i0 and i1) ;
-EndCircuit
-Circuit a2_x4 (
- Input    i0 ,
- Input    i1 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := (i0 and i1) ;
-EndCircuit
-Circuit a3_x2 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := ((i0 and i1) and i2) ;
-EndCircuit
-Circuit a3_x4 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := ((i0 and i1) and i2) ;
-EndCircuit
-Circuit a4_x2 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Input    i3 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := (((i0 and i1) and i2) and i3) ;
-EndCircuit
-Circuit a4_x4 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Input    i3 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := (((i0 and i1) and i2) and i3) ;
-EndCircuit
-Circuit an12_x1 (
- Input    i0 ,
- Input    i1 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := (not i0 and i1) ;
-EndCircuit
-Circuit an12_x4 (
- Input    i0 ,
- Input    i1 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := (not i0 and i1) ;
-EndCircuit
-Circuit ao22_x2 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := ((i0 or i1) and i2) ;
-EndCircuit
-Circuit ao22_x4 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := ((i0 or i1) and i2) ;
-EndCircuit
-Circuit ao2o22_x2 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Input    i3 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := ((i0 or i1) and (i2 or i3)) ;
-EndCircuit
-Circuit ao2o22_x4 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Input    i3 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := ((i0 or i1) and (i2 or i3)) ;
-EndCircuit
-Circuit buf_x2 (
- Input    i ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := i ;
-EndCircuit
-Circuit buf_x4 (
- Input    i ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := i ;
-EndCircuit
-Circuit buf_x8 (
- Input    i ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := i ;
-EndCircuit
-Circuit fulladder_x2 (
- Input    a1 ,
- Input    a2 ,
- Input    a3 ,
- Input    a4 ,
- Input    b1 ,
- Input    b2 ,
- Input    b3 ,
- Input    b4 ,
- Input    cin1 ,
- Input    cin2 ,
- Input    cin3 ,
- Output   cout ,
- Output   sout ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE ncout := not ((a1 and b1) or ((a2 or b2) and cin1)) ;
-WIRE sout := (((a3 and b3) and cin2) or (((a4 or b4) or cin3) and ncout)) ;
-WIRE cout := not ncout ;
-EndCircuit
-Circuit fulladder_x4 (
- Input    a1 ,
- Input    a2 ,
- Input    a3 ,
- Input    a4 ,
- Input    b1 ,
- Input    b2 ,
- Input    b3 ,
- Input    b4 ,
- Input    cin1 ,
- Input    cin2 ,
- Input    cin3 ,
- Output   cout ,
- Output   sout ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE ncout := not ((a1 and b1) or ((a2 or b2) and cin1)) ;
-WIRE sout := (((a3 and b3) and cin2) or (((a4 or b4) or cin3) and ncout)) ;
-WIRE cout := not ncout ;
-EndCircuit
-Circuit halfadder_x2 (
- Input    a ,
- Input    b ,
- Output   cout ,
- Output   sout ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE sout := (a xor b) ;
-WIRE cout := (a and b) ;
-EndCircuit
-Circuit halfadder_x4 (
- Input    a ,
- Input    b ,
- Output   cout ,
- Output   sout ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE sout := (a xor b) ;
-WIRE cout := (a and b) ;
-EndCircuit
-Circuit inv_x1 (
- Input    i ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not i ;
-EndCircuit
-Circuit inv_x2 (
- Input    i ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not i ;
-EndCircuit
-Circuit inv_x4 (
- Input    i ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not i ;
-EndCircuit
-Circuit inv_x8 (
- Input    i ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not i ;
-EndCircuit
-Circuit mx2_x2 (
- Input    cmd ,
- Input    i0 ,
- Input    i1 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := ((i1 and cmd) or (not cmd and i0)) ;
-EndCircuit
-Circuit mx2_x4 (
- Input    cmd ,
- Input    i0 ,
- Input    i1 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := ((i1 and cmd) or (not cmd and i0)) ;
-EndCircuit
-Circuit mx3_x2 (
- Input    cmd0 ,
- Input    cmd1 ,
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := ((not cmd0 and i0) or (cmd0 and ((cmd1 and i1) or (not cmd1 and i2)))) ;
-EndCircuit
-Circuit mx3_x4 (
- Input    cmd0 ,
- Input    cmd1 ,
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := ((not cmd0 and i0) or (cmd0 and ((cmd1 and i1) or (not cmd1 and i2)))) ;
-EndCircuit
-Circuit na2_x1 (
- Input    i0 ,
- Input    i1 ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not (i0 and i1) ;
-EndCircuit
-Circuit na2_x4 (
- Input    i0 ,
- Input    i1 ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not (i0 and i1) ;
-EndCircuit
-Circuit na3_x1 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not ((i0 and i1) and i2) ;
-EndCircuit
-Circuit na3_x4 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not ((i0 and i1) and i2) ;
-EndCircuit
-Circuit na4_x1 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Input    i3 ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not (((i0 and i1) and i2) and i3) ;
-EndCircuit
-Circuit na4_x4 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Input    i3 ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not (((i0 and i1) and i2) and i3) ;
-EndCircuit
-Circuit nao22_x1 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not ((i0 or i1) and i2) ;
-EndCircuit
-Circuit nao22_x4 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not ((i0 or i1) and i2) ;
-EndCircuit
-Circuit nao2o22_x1 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Input    i3 ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not ((i0 or i1) and (i2 or i3)) ;
-EndCircuit
-Circuit nao2o22_x4 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Input    i3 ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not ((i0 or i1) and (i2 or i3)) ;
-EndCircuit
-Circuit nmx2_x1 (
- Input    cmd ,
- Input    i0 ,
- Input    i1 ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not ((i0 and not cmd) or (i1 and cmd)) ;
-EndCircuit
-Circuit nmx2_x4 (
- Input    cmd ,
- Input    i0 ,
- Input    i1 ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not ((i0 and not cmd) or (i1 and cmd)) ;
-EndCircuit
-Circuit nmx3_x1 (
- Input    cmd0 ,
- Input    cmd1 ,
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not ((not cmd0 and i0) or (cmd0 and ((cmd1 and i1) or (not cmd1 and i2)))) ;
-EndCircuit
-Circuit nmx3_x4 (
- Input    cmd0 ,
- Input    cmd1 ,
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not ((not cmd0 and i0) or (cmd0 and ((cmd1 and i1) or (not cmd1 and i2)))) ;
-EndCircuit
-Circuit no2_x1 (
- Input    i0 ,
- Input    i1 ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not (i0 or i1) ;
-EndCircuit
-Circuit no2_x4 (
- Input    i0 ,
- Input    i1 ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not (i0 or i1) ;
-EndCircuit
-Circuit no3_x1 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not ((i0 or i1) or i2) ;
-EndCircuit
-Circuit no3_x4 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not ((i0 or i1) or i2) ;
-EndCircuit
-Circuit no4_x1 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Input    i3 ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not (((i0 or i1) or i2) or i3) ;
-EndCircuit
-Circuit no4_x4 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Input    i3 ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not (((i0 or i1) or i2) or i3) ;
-EndCircuit
-Circuit noa22_x1 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not ((i0 and i1) or i2) ;
-EndCircuit
-Circuit noa22_x4 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not ((i0 and i1) or i2) ;
-EndCircuit
-Circuit noa2a22_x1 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Input    i3 ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not ((i0 and i1) or (i2 and i3)) ;
-EndCircuit
-Circuit noa2a22_x4 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Input    i3 ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not ((i0 and i1) or (i2 and i3)) ;
-EndCircuit
-Circuit noa2a2a23_x1 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Input    i3 ,
- Input    i4 ,
- Input    i5 ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not (((i0 and i1) or (i2 and i3)) or (i4 and i5)) ;
-EndCircuit
-Circuit noa2a2a23_x4 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Input    i3 ,
- Input    i4 ,
- Input    i5 ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not (((i0 and i1) or (i2 and i3)) or (i4 and i5)) ;
-EndCircuit
-Circuit noa2a2a2a24_x1 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Input    i3 ,
- Input    i4 ,
- Input    i5 ,
- Input    i6 ,
- Input    i7 ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not ((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and i7)) ;
-EndCircuit
-Circuit noa2a2a2a24_x4 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Input    i3 ,
- Input    i4 ,
- Input    i5 ,
- Input    i6 ,
- Input    i7 ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not ((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and i7)) ;
-EndCircuit
-Circuit noa2ao222_x1 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Input    i3 ,
- Input    i4 ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not ((i0 and i1) or ((i2 or i3) and i4)) ;
-EndCircuit
-Circuit noa2ao222_x4 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Input    i3 ,
- Input    i4 ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not ((i0 and i1) or ((i2 or i3) and i4)) ;
-EndCircuit
-Circuit noa3ao322_x1 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Input    i3 ,
- Input    i4 ,
- Input    i5 ,
- Input    i6 ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not (((i0 and i1) and i2) or (((i3 or i4) or i5) and i6)) ;
-EndCircuit
-Circuit noa3ao322_x4 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Input    i3 ,
- Input    i4 ,
- Input    i5 ,
- Input    i6 ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not (((i0 and i1) and i2) or (((i3 or i4) or i5) and i6)) ;
-EndCircuit
-Circuit nts_x1 (
- Input    cmd ,
- Input    i ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE commande_0_nq := cmd ;
-WIRE data_0_nq := not i ;
-TRI1 nq ;
-	BUFIF1 tri_0_nq (nq,data_0_nq,commande_0_nq) ;
-EndCircuit
-Circuit nts_x2 (
- Input    cmd ,
- Input    i ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE commande_0_nq := cmd ;
-WIRE data_0_nq := not i ;
-TRI1 nq ;
-	BUFIF1 tri_0_nq (nq,data_0_nq,commande_0_nq) ;
-EndCircuit
-Circuit nxr2_x1 (
- Input    i0 ,
- Input    i1 ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not (i0 xor i1) ;
-EndCircuit
-Circuit nxr2_x4 (
- Input    i0 ,
- Input    i1 ,
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := not (i0 xor i1) ;
-EndCircuit
-Circuit o2_x2 (
- Input    i0 ,
- Input    i1 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := (i0 or i1) ;
-EndCircuit
-Circuit o2_x4 (
- Input    i0 ,
- Input    i1 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := (i0 or i1) ;
-EndCircuit
-Circuit o3_x2 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := ((i0 or i1) or i2) ;
-EndCircuit
-Circuit o3_x4 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := ((i0 or i1) or i2) ;
-EndCircuit
-Circuit o4_x2 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Input    i3 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := (((i0 or i1) or i2) or i3) ;
-EndCircuit
-Circuit o4_x4 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Input    i3 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := (((i0 or i1) or i2) or i3) ;
-EndCircuit
-Circuit oa22_x2 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := ((i0 and i1) or i2) ;
-EndCircuit
-Circuit oa22_x4 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := ((i0 and i1) or i2) ;
-EndCircuit
-Circuit oa2a22_x2 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Input    i3 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := ((i0 and i1) or (i2 and i3)) ;
-EndCircuit
-Circuit oa2a22_x4 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Input    i3 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := ((i0 and i1) or (i2 and i3)) ;
-EndCircuit
-Circuit oa2a2a23_x2 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Input    i3 ,
- Input    i4 ,
- Input    i5 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := (((i0 and i1) or (i2 and i3)) or (i4 and i5)) ;
-EndCircuit
-Circuit oa2a2a23_x4 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Input    i3 ,
- Input    i4 ,
- Input    i5 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := (((i0 and i1) or (i2 and i3)) or (i4 and i5)) ;
-EndCircuit
-Circuit oa2a2a2a24_x2 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Input    i3 ,
- Input    i4 ,
- Input    i5 ,
- Input    i6 ,
- Input    i7 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := ((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and i7)) ;
-EndCircuit
-Circuit oa2a2a2a24_x4 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Input    i3 ,
- Input    i4 ,
- Input    i5 ,
- Input    i6 ,
- Input    i7 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := ((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and i7)) ;
-EndCircuit
-Circuit oa2ao222_x2 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Input    i3 ,
- Input    i4 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := ((i0 and i1) or (i4 and (i2 or i3))) ;
-EndCircuit
-Circuit oa2ao222_x4 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Input    i3 ,
- Input    i4 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := ((i0 and i1) or (i4 and (i2 or i3))) ;
-EndCircuit
-Circuit oa3ao322_x2 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Input    i3 ,
- Input    i4 ,
- Input    i5 ,
- Input    i6 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := (((i0 and i1) and i2) or (i6 and ((i3 or i4) or i5))) ;
-EndCircuit
-Circuit oa3ao322_x4 (
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Input    i3 ,
- Input    i4 ,
- Input    i5 ,
- Input    i6 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := (((i0 and i1) and i2) or (i6 and ((i3 or i4) or i5))) ;
-EndCircuit
-Circuit on12_x1 (
- Input    i0 ,
- Input    i1 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := (not i0 or i1) ;
-EndCircuit
-Circuit on12_x4 (
- Input    i0 ,
- Input    i1 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := (not i0 or i1) ;
-EndCircuit
-Circuit one_x0 (
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := 1 ;
-EndCircuit
-Circuit rowend_x0 (
- Supply1  vdd ,
- Supply0  vss 
- );
-EndCircuit
-Circuit sff1_x4 (
- Input    ck ,
- Input    i ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE sff_m_bcond_0 := ck ;
-REGISTER (1,1) sff_m ; 
-WHEN sff_m_bcond_0 (0 TO 1) DO sff_m := i ;
-WIRE q := sff_m ;
-EndCircuit
-Circuit sff2_x4 (
- Input    ck ,
- Input    cmd ,
- Input    i0 ,
- Input    i1 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE sff_m_bcond_0 := ck ;
-REGISTER (1,1) sff_m ; 
-WHEN sff_m_bcond_0 (0 TO 1) DO sff_m := ((i1 and cmd) or (i0 and not cmd)) ;
-WIRE q := sff_m ;
-EndCircuit
-Circuit sff3_x4 (
- Input    ck ,
- Input    cmd0 ,
- Input    cmd1 ,
- Input    i0 ,
- Input    i1 ,
- Input    i2 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE sff_m_bcond_0 := ck ;
-REGISTER (1,1) sff_m ; 
-WHEN sff_m_bcond_0 (0 TO 1) DO sff_m := ((not cmd0 and i0) or (cmd0 and ((cmd1 and i1) or (not cmd1 and i2)))) ;
-WIRE q := sff_m ;
-EndCircuit
-Circuit tie_x0 (
- Supply1  vdd ,
- Supply0  vss 
- );
-EndCircuit
-Circuit ts_x4 (
- Input    cmd ,
- Input    i ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE commande_0_q := cmd ;
-WIRE data_0_q := i ;
-TRI1 q ;
-	BUFIF1 tri_0_q (q,data_0_q,commande_0_q) ;
-EndCircuit
-Circuit ts_x8 (
- Input    cmd ,
- Input    i ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE commande_0_q := cmd ;
-WIRE data_0_q := i ;
-TRI1 q ;
-	BUFIF1 tri_0_q (q,data_0_q,commande_0_q) ;
-EndCircuit
-Circuit xr2_x1 (
- Input    i0 ,
- Input    i1 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := (i0 xor i1) ;
-EndCircuit
-Circuit xr2_x4 (
- Input    i0 ,
- Input    i1 ,
- Output   q ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE q := (i0 xor i1) ;
-EndCircuit
-Circuit zero_x0 (
- Output   nq ,
- Supply1  vdd ,
- Supply0  vss 
- );
-WIRE nq := 0 ;
-EndCircuit
diff --git a/alliance/share/cells/sxlib/sxlib.db b/alliance/share/cells/sxlib/sxlib.db
deleted file mode 100644
index c7915a1b..00000000
Binary files a/alliance/share/cells/sxlib/sxlib.db and /dev/null differ
diff --git a/alliance/share/cells/sxlib/sxlib.lef b/alliance/share/cells/sxlib/sxlib.lef
deleted file mode 100644
index cb2f2744..00000000
--- a/alliance/share/cells/sxlib/sxlib.lef
+++ /dev/null
@@ -1,8073 +0,0 @@
-
-MACRO a2_x2
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      25.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 39.00 21.00 41.00 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-            RECT 19.00 9.00 21.00 11.00 ;
-        END
-    END q
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 39.00 16.00 41.00 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-            RECT 14.00 9.00 16.00 11.00 ;
-        END
-    END i1
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 22.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 22.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 23.50 41.00 ;
-    END
-END a2_x2
-
-
-MACRO a2_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      30.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 39.00 21.00 41.00 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-            RECT 19.00 9.00 21.00 11.00 ;
-        END
-    END q
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 39.00 16.00 41.00 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-            RECT 14.00 9.00 16.00 11.00 ;
-        END
-    END i1
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 27.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 27.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 28.50 41.00 ;
-    END
-END a2_x4
-
-
-MACRO a3_x2
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      30.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 39.00 26.00 41.00 ;
-            RECT 24.00 34.00 26.00 36.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-            RECT 24.00 9.00 26.00 11.00 ;
-        END
-    END q
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-        END
-    END i2
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END i1
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 27.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 27.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 28.50 41.00 ;
-    END
-END a3_x2
-
-
-MACRO a3_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      35.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 39.00 26.00 41.00 ;
-            RECT 24.00 34.00 26.00 36.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-            RECT 24.00 9.00 26.00 11.00 ;
-        END
-    END q
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END i1
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-        END
-    END i2
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 32.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 32.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 33.50 41.00 ;
-    END
-END a3_x4
-
-
-MACRO a4_x2
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      35.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 39.00 31.00 41.00 ;
-            RECT 29.00 34.00 31.00 36.00 ;
-            RECT 29.00 29.00 31.00 31.00 ;
-            RECT 29.00 24.00 31.00 26.00 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-            RECT 29.00 14.00 31.00 16.00 ;
-            RECT 29.00 9.00 31.00 11.00 ;
-        END
-    END q
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END i0
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-            RECT 14.00 9.00 16.00 11.00 ;
-        END
-    END i2
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END i1
-    PIN i3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-        END
-    END i3
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 32.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 32.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 33.50 41.00 ;
-    END
-END a4_x2
-
-
-MACRO a4_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      40.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 39.00 31.00 41.00 ;
-            RECT 29.00 34.00 31.00 36.00 ;
-            RECT 29.00 29.00 31.00 31.00 ;
-            RECT 29.00 24.00 31.00 26.00 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-            RECT 29.00 14.00 31.00 16.00 ;
-            RECT 29.00 9.00 31.00 11.00 ;
-        END
-    END q
-    PIN i3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-        END
-    END i3
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END i1
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-            RECT 14.00 9.00 16.00 11.00 ;
-        END
-    END i2
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END i0
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 37.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 37.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 38.50 41.00 ;
-    END
-END a4_x4
-
-
-MACRO an12_x1
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      25.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-            LAYER L_ALU1 ;
-            RECT 4.00 39.00 6.00 41.00 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-        END
-    END q
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 39.00 16.00 41.00 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-            RECT 14.00 9.00 16.00 11.00 ;
-        END
-    END i1
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END i0
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 22.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 22.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 23.50 41.00 ;
-    END
-END an12_x1
-
-
-MACRO an12_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      40.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 39.00 31.00 41.00 ;
-            RECT 29.00 34.00 31.00 36.00 ;
-            RECT 29.00 29.00 31.00 31.00 ;
-            RECT 29.00 24.00 31.00 26.00 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-            RECT 29.00 14.00 31.00 16.00 ;
-            RECT 29.00 9.00 31.00 11.00 ;
-        END
-    END q
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 39.00 26.00 41.00 ;
-            RECT 24.00 34.00 26.00 36.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-            RECT 24.00 9.00 26.00 11.00 ;
-        END
-    END i1
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END i0
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 37.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 37.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 38.50 41.00 ;
-    END
-END an12_x4
-
-
-MACRO ao22_x2
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      30.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 39.00 26.00 41.00 ;
-            RECT 24.00 34.00 26.00 36.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-            RECT 24.00 9.00 26.00 11.00 ;
-        END
-    END q
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 39.00 6.00 41.00 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-        END
-    END i1
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 39.00 21.00 41.00 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-            RECT 19.00 9.00 21.00 11.00 ;
-        END
-    END i2
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 27.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 27.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 28.50 41.00 ;
-    END
-END ao22_x2
-
-
-MACRO ao22_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      40.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 39.00 31.00 41.00 ;
-            RECT 29.00 34.00 31.00 36.00 ;
-            RECT 29.00 29.00 31.00 31.00 ;
-            RECT 29.00 24.00 31.00 26.00 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-            RECT 29.00 14.00 31.00 16.00 ;
-            RECT 29.00 9.00 31.00 11.00 ;
-        END
-    END q
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 39.00 21.00 41.00 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-            RECT 19.00 9.00 21.00 11.00 ;
-        END
-    END i2
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 39.00 6.00 41.00 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-        END
-    END i1
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 37.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 37.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 38.50 41.00 ;
-    END
-END ao22_x4
-
-
-MACRO ao2o22_x2
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      45.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 39.00 39.00 41.00 41.00 ;
-            RECT 39.00 34.00 41.00 36.00 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-            RECT 39.00 24.00 41.00 26.00 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-            RECT 39.00 14.00 41.00 16.00 ;
-            RECT 39.00 9.00 41.00 11.00 ;
-        END
-    END q
-    PIN i3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 34.00 26.00 36.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-        END
-    END i3
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-        END
-    END i2
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-        END
-    END i1
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 39.00 6.00 41.00 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-        END
-    END i0
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 42.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 42.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 43.50 41.00 ;
-    END
-END ao2o22_x2
-
-
-MACRO ao2o22_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      50.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 39.00 39.00 41.00 41.00 ;
-            RECT 39.00 34.00 41.00 36.00 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-            RECT 39.00 24.00 41.00 26.00 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-            RECT 39.00 14.00 41.00 16.00 ;
-            RECT 39.00 9.00 41.00 11.00 ;
-        END
-    END q
-    PIN i3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 34.00 26.00 36.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-        END
-    END i3
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-        END
-    END i2
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-        END
-    END i1
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 39.00 6.00 41.00 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-        END
-    END i0
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 47.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 47.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 48.50 41.00 ;
-    END
-END ao2o22_x4
-
-
-MACRO buf_x2
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      20.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 39.00 16.00 41.00 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-            RECT 14.00 9.00 16.00 11.00 ;
-        END
-    END q
-    PIN i
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END i
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 17.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 17.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 18.50 41.00 ;
-    END
-END buf_x2
-
-
-MACRO buf_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      25.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 39.00 16.00 41.00 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-            RECT 14.00 9.00 16.00 11.00 ;
-        END
-    END q
-    PIN i
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END i
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 22.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 22.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 23.50 41.00 ;
-    END
-END buf_x4
-
-
-MACRO buf_x8
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      40.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 39.00 16.00 41.00 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-            RECT 14.00 9.00 16.00 11.00 ;
-        END
-    END q
-    PIN i
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END i
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 37.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 37.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 38.50 41.00 ;
-    END
-END buf_x8
-
-
-MACRO fulladder_x2
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      100.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN sout
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 49.00 34.00 51.00 36.00 ;
-            RECT 49.00 29.00 51.00 31.00 ;
-            RECT 49.00 24.00 51.00 26.00 ;
-            RECT 49.00 19.00 51.00 21.00 ;
-            RECT 49.00 14.00 51.00 16.00 ;
-            RECT 49.00 9.00 51.00 11.00 ;
-        END
-    END sout
-    PIN cout
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 39.00 14.00 41.00 16.00 ;
-            RECT 39.00 9.00 41.00 11.00 ;
-            LAYER L_ALU1 ;
-            RECT 34.00 29.00 36.00 31.00 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-            RECT 34.00 14.00 36.00 16.00 ;
-        END
-    END cout
-    PIN b4
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 94.00 34.00 96.00 36.00 ;
-            RECT 94.00 29.00 96.00 31.00 ;
-            RECT 94.00 24.00 96.00 26.00 ;
-            RECT 94.00 19.00 96.00 21.00 ;
-            RECT 94.00 14.00 96.00 16.00 ;
-        END
-    END b4
-    PIN a4
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 89.00 34.00 91.00 36.00 ;
-            RECT 89.00 29.00 91.00 31.00 ;
-            RECT 89.00 24.00 91.00 26.00 ;
-            RECT 89.00 19.00 91.00 21.00 ;
-            RECT 89.00 14.00 91.00 16.00 ;
-        END
-    END a4
-    PIN b1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END b1
-    PIN a1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END a1
-    PIN cin3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 84.00 29.00 86.00 31.00 ;
-            RECT 84.00 24.00 86.00 26.00 ;
-            RECT 84.00 19.00 86.00 21.00 ;
-            RECT 84.00 14.00 86.00 16.00 ;
-        END
-    END cin3
-    PIN cin2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 69.00 29.00 71.00 31.00 ;
-            RECT 69.00 24.00 71.00 26.00 ;
-            RECT 69.00 19.00 71.00 21.00 ;
-            RECT 69.00 14.00 71.00 16.00 ;
-        END
-    END cin2
-    PIN b3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 64.00 29.00 66.00 31.00 ;
-            RECT 64.00 24.00 66.00 26.00 ;
-            RECT 64.00 19.00 66.00 21.00 ;
-            RECT 64.00 14.00 66.00 16.00 ;
-        END
-    END b3
-    PIN a3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 59.00 29.00 61.00 31.00 ;
-            RECT 59.00 24.00 61.00 26.00 ;
-            RECT 59.00 19.00 61.00 21.00 ;
-            RECT 59.00 14.00 61.00 16.00 ;
-        END
-    END a3
-    PIN b2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 29.00 31.00 31.00 ;
-            RECT 29.00 24.00 31.00 26.00 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-            RECT 29.00 14.00 31.00 16.00 ;
-        END
-    END b2
-    PIN a2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-        END
-    END a2
-    PIN cin1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-        END
-    END cin1
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 97.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 97.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 98.50 41.00 ;
-    END
-END fulladder_x2
-
-
-MACRO fulladder_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      105.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN cout
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 44.00 34.00 46.00 36.00 ;
-            RECT 44.00 29.00 46.00 31.00 ;
-            RECT 44.00 24.00 46.00 26.00 ;
-            RECT 44.00 19.00 46.00 21.00 ;
-            RECT 44.00 14.00 46.00 16.00 ;
-            RECT 44.00 9.00 46.00 11.00 ;
-        END
-    END cout
-    PIN sout
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 54.00 34.00 56.00 36.00 ;
-            RECT 54.00 29.00 56.00 31.00 ;
-            RECT 54.00 24.00 56.00 26.00 ;
-            RECT 54.00 19.00 56.00 21.00 ;
-            RECT 54.00 14.00 56.00 16.00 ;
-            RECT 54.00 9.00 56.00 11.00 ;
-        END
-    END sout
-    PIN a3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 64.00 29.00 66.00 31.00 ;
-            RECT 64.00 24.00 66.00 26.00 ;
-            RECT 64.00 19.00 66.00 21.00 ;
-        END
-    END a3
-    PIN cin2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 74.00 29.00 76.00 31.00 ;
-            RECT 74.00 24.00 76.00 26.00 ;
-            RECT 74.00 19.00 76.00 21.00 ;
-            RECT 74.00 14.00 76.00 16.00 ;
-        END
-    END cin2
-    PIN b3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 69.00 29.00 71.00 31.00 ;
-            RECT 69.00 24.00 71.00 26.00 ;
-            RECT 69.00 19.00 71.00 21.00 ;
-            RECT 69.00 14.00 71.00 16.00 ;
-        END
-    END b3
-    PIN cin3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 89.00 29.00 91.00 31.00 ;
-            RECT 89.00 24.00 91.00 26.00 ;
-            RECT 89.00 19.00 91.00 21.00 ;
-            RECT 89.00 14.00 91.00 16.00 ;
-        END
-    END cin3
-    PIN a4
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 94.00 34.00 96.00 36.00 ;
-            RECT 94.00 29.00 96.00 31.00 ;
-            RECT 94.00 24.00 96.00 26.00 ;
-            RECT 94.00 19.00 96.00 21.00 ;
-            RECT 94.00 14.00 96.00 16.00 ;
-        END
-    END a4
-    PIN b4
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 99.00 34.00 101.00 36.00 ;
-            RECT 99.00 29.00 101.00 31.00 ;
-            RECT 99.00 24.00 101.00 26.00 ;
-            RECT 99.00 19.00 101.00 21.00 ;
-            RECT 99.00 14.00 101.00 16.00 ;
-        END
-    END b4
-    PIN b2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 29.00 31.00 31.00 ;
-            RECT 29.00 24.00 31.00 26.00 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-            RECT 29.00 14.00 31.00 16.00 ;
-        END
-    END b2
-    PIN a2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-        END
-    END a2
-    PIN cin1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-        END
-    END cin1
-    PIN b1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END b1
-    PIN a1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END a1
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 102.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 102.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 103.50 41.00 ;
-    END
-END fulladder_x4
-
-
-MACRO halfadder_x2
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      80.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN sout
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 74.00 39.00 76.00 41.00 ;
-            RECT 74.00 34.00 76.00 36.00 ;
-            RECT 74.00 29.00 76.00 31.00 ;
-            RECT 74.00 24.00 76.00 26.00 ;
-            RECT 74.00 19.00 76.00 21.00 ;
-            RECT 74.00 14.00 76.00 16.00 ;
-            RECT 74.00 9.00 76.00 11.00 ;
-        END
-    END sout
-    PIN cout
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 39.00 6.00 41.00 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END cout
-    PIN b
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 34.00 34.00 36.00 36.00 ;
-            RECT 34.00 29.00 36.00 31.00 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-            RECT 34.00 14.00 36.00 16.00 ;
-            RECT 34.00 9.00 36.00 11.00 ;
-        END
-    END b
-    PIN a
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END a
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 77.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 77.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 78.50 41.00 ;
-    END
-END halfadder_x2
-
-
-MACRO halfadder_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      90.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN cout
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END cout
-    PIN sout
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 79.00 39.00 81.00 41.00 ;
-            RECT 79.00 34.00 81.00 36.00 ;
-            RECT 79.00 29.00 81.00 31.00 ;
-            RECT 79.00 24.00 81.00 26.00 ;
-            RECT 79.00 19.00 81.00 21.00 ;
-            RECT 79.00 14.00 81.00 16.00 ;
-            RECT 79.00 9.00 81.00 11.00 ;
-        END
-    END sout
-    PIN a
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 39.00 16.00 41.00 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-            RECT 14.00 9.00 16.00 11.00 ;
-        END
-    END a
-    PIN b
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 39.00 34.00 41.00 36.00 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-            RECT 39.00 24.00 41.00 26.00 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-            RECT 39.00 14.00 41.00 16.00 ;
-            RECT 39.00 9.00 41.00 11.00 ;
-        END
-    END b
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 87.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 87.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 88.50 41.00 ;
-    END
-END halfadder_x4
-
-
-MACRO inv_x1
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      15.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END nq
-    PIN i
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 39.00 6.00 41.00 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END i
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 12.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 12.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 13.50 41.00 ;
-    END
-END inv_x1
-
-
-MACRO inv_x2
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      15.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END nq
-    PIN i
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 39.00 6.00 41.00 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END i
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 12.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 12.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 13.50 41.00 ;
-    END
-END inv_x2
-
-
-MACRO inv_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      20.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END nq
-    PIN i
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 39.00 6.00 41.00 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END i
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 17.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 17.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 18.50 41.00 ;
-    END
-END inv_x4
-
-
-MACRO inv_x8
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      35.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END nq
-    PIN i
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 39.00 6.00 41.00 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END i
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 32.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 32.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 33.50 41.00 ;
-    END
-END inv_x8
-
-
-MACRO mx2_x2
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      45.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 39.00 39.00 41.00 41.00 ;
-            RECT 39.00 34.00 41.00 36.00 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-            RECT 39.00 24.00 41.00 26.00 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-            RECT 39.00 14.00 41.00 16.00 ;
-            RECT 39.00 9.00 41.00 11.00 ;
-        END
-    END q
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 39.00 31.00 41.00 ;
-            RECT 29.00 34.00 31.00 36.00 ;
-            RECT 29.00 29.00 31.00 31.00 ;
-            RECT 29.00 24.00 31.00 26.00 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-            RECT 29.00 14.00 31.00 16.00 ;
-            RECT 29.00 9.00 31.00 11.00 ;
-        END
-    END i1
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END i0
-    PIN cmd
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 39.00 16.00 41.00 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-        END
-    END cmd
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 42.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 42.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 43.50 41.00 ;
-    END
-END mx2_x2
-
-
-MACRO mx2_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      50.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 39.00 39.00 41.00 41.00 ;
-            RECT 39.00 34.00 41.00 36.00 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-            RECT 39.00 24.00 41.00 26.00 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-            RECT 39.00 14.00 41.00 16.00 ;
-            RECT 39.00 9.00 41.00 11.00 ;
-        END
-    END q
-    PIN cmd
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 39.00 16.00 41.00 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-        END
-    END cmd
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 39.00 31.00 41.00 ;
-            RECT 29.00 34.00 31.00 36.00 ;
-            RECT 29.00 29.00 31.00 31.00 ;
-            RECT 29.00 24.00 31.00 26.00 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-            RECT 29.00 14.00 31.00 16.00 ;
-            RECT 29.00 9.00 31.00 11.00 ;
-        END
-    END i1
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 47.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 47.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 48.50 41.00 ;
-    END
-END mx2_x4
-
-
-MACRO mx3_x2
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      65.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 59.00 39.00 61.00 41.00 ;
-            RECT 59.00 34.00 61.00 36.00 ;
-            RECT 59.00 29.00 61.00 31.00 ;
-            RECT 59.00 24.00 61.00 26.00 ;
-            LAYER L_ALU1 ;
-            RECT 59.00 14.00 61.00 16.00 ;
-            RECT 59.00 9.00 61.00 11.00 ;
-        END
-    END q
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-            LAYER L_ALU1 ;
-            RECT 44.00 24.00 46.00 26.00 ;
-            LAYER L_ALU1 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-        END
-    END i0
-    PIN cmd0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 34.00 29.00 36.00 31.00 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-        END
-    END cmd0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-        END
-    END i1
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-        END
-    END i2
-    PIN cmd1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-        END
-    END cmd1
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 62.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 62.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 63.50 41.00 ;
-    END
-END mx3_x2
-
-
-MACRO mx3_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      70.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 59.00 39.00 61.00 41.00 ;
-            RECT 59.00 34.00 61.00 36.00 ;
-            RECT 59.00 29.00 61.00 31.00 ;
-            RECT 59.00 24.00 61.00 26.00 ;
-            LAYER L_ALU1 ;
-            RECT 59.00 14.00 61.00 16.00 ;
-            RECT 59.00 9.00 61.00 11.00 ;
-            LAYER L_ALU1 ;
-            RECT 64.00 19.00 66.00 21.00 ;
-        END
-    END q
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 44.00 24.00 46.00 26.00 ;
-            LAYER L_ALU1 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-            LAYER L_ALU1 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-        END
-    END i0
-    PIN cmd1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-        END
-    END cmd1
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-        END
-    END i2
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-        END
-    END i1
-    PIN cmd0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 34.00 29.00 36.00 31.00 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-        END
-    END cmd0
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 67.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 67.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 68.50 41.00 ;
-    END
-END mx3_x4
-
-
-MACRO na2_x1
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      20.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END nq
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 39.00 16.00 41.00 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-        END
-    END i1
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 39.00 6.00 41.00 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END i0
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 17.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 17.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 18.50 41.00 ;
-    END
-END na2_x1
-
-
-MACRO na2_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      35.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-            RECT 19.00 9.00 21.00 11.00 ;
-        END
-    END nq
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END i1
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 32.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 32.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 33.50 41.00 ;
-    END
-END na2_x4
-
-
-MACRO na3_x1
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      25.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 39.00 21.00 41.00 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-            RECT 19.00 9.00 21.00 11.00 ;
-        END
-    END nq
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-            RECT 14.00 9.00 16.00 11.00 ;
-        END
-    END i2
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END i1
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 39.00 6.00 41.00 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END i0
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 22.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 22.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 23.50 41.00 ;
-    END
-END na3_x1
-
-
-MACRO na3_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      40.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 34.00 26.00 36.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-            RECT 24.00 9.00 26.00 11.00 ;
-        END
-    END nq
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-        END
-    END i1
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END i2
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 37.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 37.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 38.50 41.00 ;
-    END
-END na3_x4
-
-
-MACRO na4_x1
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      30.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 39.00 26.00 41.00 ;
-            RECT 24.00 34.00 26.00 36.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-            RECT 24.00 9.00 26.00 11.00 ;
-        END
-    END nq
-    PIN i3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-            RECT 19.00 9.00 21.00 11.00 ;
-        END
-    END i3
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-            RECT 14.00 9.00 16.00 11.00 ;
-        END
-    END i2
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END i1
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END i0
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 27.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 27.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 28.50 41.00 ;
-    END
-END na4_x1
-
-
-MACRO na4_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      50.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-            RECT 14.00 9.00 16.00 11.00 ;
-        END
-    END nq
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 34.00 34.00 36.00 36.00 ;
-            RECT 34.00 29.00 36.00 31.00 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-            RECT 34.00 14.00 36.00 16.00 ;
-            RECT 34.00 9.00 36.00 11.00 ;
-        END
-    END i2
-    PIN i3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 39.00 34.00 41.00 36.00 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-            RECT 39.00 24.00 41.00 26.00 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-            RECT 39.00 14.00 41.00 16.00 ;
-            RECT 39.00 9.00 41.00 11.00 ;
-        END
-    END i3
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 34.00 31.00 36.00 ;
-            RECT 29.00 29.00 31.00 31.00 ;
-            RECT 29.00 24.00 31.00 26.00 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-            RECT 29.00 14.00 31.00 16.00 ;
-            RECT 29.00 9.00 31.00 11.00 ;
-        END
-    END i1
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 34.00 26.00 36.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-            RECT 24.00 9.00 26.00 11.00 ;
-        END
-    END i0
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 47.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 47.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 48.50 41.00 ;
-    END
-END na4_x4
-
-
-MACRO nao22_x1
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      30.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 39.00 16.00 41.00 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-        END
-    END nq
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 39.00 6.00 41.00 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-        END
-    END i1
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 39.00 21.00 41.00 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-            RECT 19.00 9.00 21.00 11.00 ;
-        END
-    END i2
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 27.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 27.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 28.50 41.00 ;
-    END
-END nao22_x1
-
-
-MACRO nao22_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      50.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 39.00 39.00 41.00 41.00 ;
-            RECT 39.00 34.00 41.00 36.00 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-            RECT 39.00 24.00 41.00 26.00 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-            RECT 39.00 14.00 41.00 16.00 ;
-            RECT 39.00 9.00 41.00 11.00 ;
-        END
-    END nq
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 39.00 6.00 41.00 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END i2
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-        END
-    END i1
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-            LAYER L_ALU1 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-        END
-    END i0
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 47.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 47.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 48.50 41.00 ;
-    END
-END nao22_x4
-
-
-MACRO nao2o22_x1
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      35.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 39.00 16.00 41.00 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-        END
-    END nq
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 39.00 6.00 41.00 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-        END
-    END i1
-    PIN i3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 39.00 21.00 41.00 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-        END
-    END i3
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 39.00 26.00 41.00 ;
-            RECT 24.00 34.00 26.00 36.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-        END
-    END i2
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 32.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 32.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 33.50 41.00 ;
-    END
-END nao2o22_x1
-
-
-MACRO nao2o22_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      55.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 44.00 39.00 46.00 41.00 ;
-            RECT 44.00 34.00 46.00 36.00 ;
-            RECT 44.00 29.00 46.00 31.00 ;
-            RECT 44.00 24.00 46.00 26.00 ;
-            RECT 44.00 19.00 46.00 21.00 ;
-            RECT 44.00 14.00 46.00 16.00 ;
-            RECT 44.00 9.00 46.00 11.00 ;
-        END
-    END nq
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 39.00 6.00 41.00 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-        END
-    END i1
-    PIN i3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-        END
-    END i3
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 34.00 26.00 36.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-        END
-    END i2
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 52.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 52.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 53.50 41.00 ;
-    END
-END nao2o22_x4
-
-
-MACRO nmx2_x1
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      35.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-            LAYER L_ALU1 ;
-            RECT 19.00 9.00 21.00 11.00 ;
-            LAYER L_ALU1 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-        END
-    END nq
-    PIN cmd
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-        END
-    END cmd
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 39.00 31.00 41.00 ;
-            RECT 29.00 34.00 31.00 36.00 ;
-            RECT 29.00 29.00 31.00 31.00 ;
-            RECT 29.00 24.00 31.00 26.00 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-            RECT 29.00 14.00 31.00 16.00 ;
-            RECT 29.00 9.00 31.00 11.00 ;
-        END
-    END i1
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 32.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 32.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 33.50 41.00 ;
-    END
-END nmx2_x1
-
-
-MACRO nmx2_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      60.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 49.00 39.00 51.00 41.00 ;
-            RECT 49.00 34.00 51.00 36.00 ;
-            RECT 49.00 29.00 51.00 31.00 ;
-            RECT 49.00 24.00 51.00 26.00 ;
-            RECT 49.00 19.00 51.00 21.00 ;
-            RECT 49.00 14.00 51.00 16.00 ;
-            RECT 49.00 9.00 51.00 11.00 ;
-        END
-    END nq
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 39.00 31.00 41.00 ;
-            RECT 29.00 34.00 31.00 36.00 ;
-            RECT 29.00 29.00 31.00 31.00 ;
-            RECT 29.00 24.00 31.00 26.00 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-            RECT 29.00 14.00 31.00 16.00 ;
-            RECT 29.00 9.00 31.00 11.00 ;
-        END
-    END i1
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END i0
-    PIN cmd
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 39.00 16.00 41.00 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-        END
-    END cmd
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 57.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 57.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 58.50 41.00 ;
-    END
-END nmx2_x4
-
-
-MACRO nmx3_x1
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      60.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 54.00 34.00 56.00 36.00 ;
-            RECT 54.00 29.00 56.00 31.00 ;
-            RECT 54.00 24.00 56.00 26.00 ;
-            RECT 54.00 19.00 56.00 21.00 ;
-            RECT 54.00 14.00 56.00 16.00 ;
-            RECT 54.00 9.00 56.00 11.00 ;
-        END
-    END nq
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-            LAYER L_ALU1 ;
-            RECT 44.00 24.00 46.00 26.00 ;
-            LAYER L_ALU1 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-        END
-    END i0
-    PIN cmd1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-        END
-    END cmd1
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-        END
-    END i2
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-        END
-    END i1
-    PIN cmd0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 34.00 29.00 36.00 31.00 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-        END
-    END cmd0
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 57.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 57.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 58.50 41.00 ;
-    END
-END nmx3_x1
-
-
-MACRO nmx3_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      75.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 59.00 39.00 61.00 41.00 ;
-            RECT 59.00 34.00 61.00 36.00 ;
-            RECT 59.00 29.00 61.00 31.00 ;
-            RECT 59.00 24.00 61.00 26.00 ;
-            RECT 59.00 19.00 61.00 21.00 ;
-            RECT 59.00 14.00 61.00 16.00 ;
-        END
-    END nq
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 44.00 24.00 46.00 26.00 ;
-            LAYER L_ALU1 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-            LAYER L_ALU1 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-        END
-    END i0
-    PIN cmd1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-        END
-    END cmd1
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-        END
-    END i2
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-        END
-    END i1
-    PIN cmd0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 34.00 29.00 36.00 31.00 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-        END
-    END cmd0
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 72.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 72.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 73.50 41.00 ;
-    END
-END nmx3_x4
-
-
-MACRO no2_x1
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      20.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 39.00 6.00 41.00 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END nq
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END i1
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 39.00 16.00 41.00 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-            RECT 14.00 9.00 16.00 11.00 ;
-        END
-    END i0
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 17.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 17.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 18.50 41.00 ;
-    END
-END no2_x1
-
-
-MACRO no2_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      35.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-            RECT 19.00 9.00 21.00 11.00 ;
-        END
-    END nq
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-        END
-    END i1
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END i0
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 32.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 32.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 33.50 41.00 ;
-    END
-END no2_x4
-
-
-MACRO no3_x1
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      25.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 39.00 6.00 41.00 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END nq
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END i1
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 39.00 16.00 41.00 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-        END
-    END i0
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 39.00 21.00 41.00 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-            RECT 19.00 9.00 21.00 11.00 ;
-        END
-    END i2
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 22.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 22.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 23.50 41.00 ;
-    END
-END no3_x1
-
-
-MACRO no3_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      40.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 34.00 26.00 36.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-            RECT 24.00 9.00 26.00 11.00 ;
-        END
-    END nq
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END i1
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-        END
-    END i2
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 37.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 37.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 38.50 41.00 ;
-    END
-END no3_x4
-
-
-MACRO no4_x1
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      30.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 39.00 6.00 41.00 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END nq
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 39.00 21.00 41.00 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-        END
-    END i2
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 39.00 16.00 41.00 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END i1
-    PIN i3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 39.00 26.00 41.00 ;
-            RECT 24.00 34.00 26.00 36.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-        END
-    END i3
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 27.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 27.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 28.50 41.00 ;
-    END
-END no4_x1
-
-
-MACRO no4_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      50.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 34.00 39.00 36.00 41.00 ;
-            RECT 34.00 34.00 36.00 36.00 ;
-            RECT 34.00 29.00 36.00 31.00 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-            RECT 34.00 14.00 36.00 16.00 ;
-        END
-    END nq
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 39.00 21.00 41.00 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-        END
-    END i2
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 39.00 16.00 41.00 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END i1
-    PIN i3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 39.00 26.00 41.00 ;
-            RECT 24.00 34.00 26.00 36.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-        END
-    END i3
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 47.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 47.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 48.50 41.00 ;
-    END
-END no4_x4
-
-
-MACRO noa22_x1
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      30.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-            RECT 14.00 9.00 16.00 11.00 ;
-        END
-    END nq
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END i1
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 39.00 21.00 41.00 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-            RECT 19.00 9.00 21.00 11.00 ;
-        END
-    END i2
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 27.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 27.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 28.50 41.00 ;
-    END
-END noa22_x1
-
-
-MACRO noa22_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      50.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 39.00 39.00 41.00 41.00 ;
-            RECT 39.00 34.00 41.00 36.00 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-            RECT 39.00 24.00 41.00 26.00 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-            RECT 39.00 14.00 41.00 16.00 ;
-            RECT 39.00 9.00 41.00 11.00 ;
-        END
-    END nq
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 39.00 6.00 41.00 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END i2
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-            RECT 14.00 9.00 16.00 11.00 ;
-        END
-    END i1
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-            RECT 19.00 9.00 21.00 11.00 ;
-        END
-    END i0
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 47.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 47.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 48.50 41.00 ;
-    END
-END noa22_x4
-
-
-MACRO noa2a22_x1
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      35.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-            RECT 14.00 9.00 16.00 11.00 ;
-        END
-    END nq
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 34.00 26.00 36.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-            RECT 24.00 9.00 26.00 11.00 ;
-        END
-    END i2
-    PIN i3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-            RECT 19.00 9.00 21.00 11.00 ;
-        END
-    END i3
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END i1
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END i0
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 32.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 32.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 33.50 41.00 ;
-    END
-END noa2a22_x1
-
-
-MACRO noa2a22_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      55.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 44.00 39.00 46.00 41.00 ;
-            RECT 44.00 34.00 46.00 36.00 ;
-            RECT 44.00 29.00 46.00 31.00 ;
-            RECT 44.00 24.00 46.00 26.00 ;
-            RECT 44.00 19.00 46.00 21.00 ;
-            RECT 44.00 14.00 46.00 16.00 ;
-            RECT 44.00 9.00 46.00 11.00 ;
-        END
-    END nq
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-            RECT 24.00 9.00 26.00 11.00 ;
-        END
-    END i2
-    PIN i3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-            RECT 19.00 9.00 21.00 11.00 ;
-        END
-    END i3
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END i1
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END i0
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 52.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 52.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 53.50 41.00 ;
-    END
-END noa2a22_x4
-
-
-MACRO noa2a2a23_x1
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      50.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END nq
-    PIN i5
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END i5
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-        END
-    END i2
-    PIN i3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-        END
-    END i3
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 44.00 29.00 46.00 31.00 ;
-            RECT 44.00 24.00 46.00 26.00 ;
-            RECT 44.00 19.00 46.00 21.00 ;
-            RECT 44.00 14.00 46.00 16.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-            RECT 39.00 24.00 41.00 26.00 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-            RECT 39.00 14.00 41.00 16.00 ;
-        END
-    END i1
-    PIN i4
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-        END
-    END i4
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 47.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 47.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 48.50 41.00 ;
-    END
-END noa2a2a23_x1
-
-
-MACRO noa2a2a23_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      65.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 49.00 39.00 51.00 41.00 ;
-            RECT 49.00 34.00 51.00 36.00 ;
-            RECT 49.00 29.00 51.00 31.00 ;
-            RECT 49.00 24.00 51.00 26.00 ;
-            RECT 49.00 19.00 51.00 21.00 ;
-            RECT 49.00 14.00 51.00 16.00 ;
-        END
-    END nq
-    PIN i5
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END i5
-    PIN i3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-        END
-    END i3
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-        END
-    END i2
-    PIN i4
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-        END
-    END i4
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-            RECT 39.00 24.00 41.00 26.00 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-            RECT 39.00 14.00 41.00 16.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 34.00 29.00 36.00 31.00 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-            RECT 34.00 14.00 36.00 16.00 ;
-        END
-    END i1
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 62.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 62.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 63.50 41.00 ;
-    END
-END noa2a2a23_x4
-
-
-MACRO noa2a2a2a24_x1
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      70.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END nq
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 59.00 34.00 61.00 36.00 ;
-            RECT 59.00 29.00 61.00 31.00 ;
-            RECT 59.00 24.00 61.00 26.00 ;
-            RECT 59.00 19.00 61.00 21.00 ;
-            RECT 59.00 14.00 61.00 16.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 54.00 34.00 56.00 36.00 ;
-            RECT 54.00 29.00 56.00 31.00 ;
-            RECT 54.00 24.00 56.00 26.00 ;
-            RECT 54.00 19.00 56.00 21.00 ;
-            RECT 54.00 14.00 56.00 16.00 ;
-        END
-    END i1
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-            RECT 39.00 24.00 41.00 26.00 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-            RECT 39.00 14.00 41.00 16.00 ;
-        END
-    END i2
-    PIN i3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 34.00 29.00 36.00 31.00 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-            RECT 34.00 14.00 36.00 16.00 ;
-        END
-    END i3
-    PIN i4
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 29.00 31.00 31.00 ;
-            RECT 29.00 24.00 31.00 26.00 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-            RECT 29.00 14.00 31.00 16.00 ;
-        END
-    END i4
-    PIN i5
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-        END
-    END i5
-    PIN i6
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-        END
-    END i6
-    PIN i7
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END i7
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 67.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 67.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 68.50 41.00 ;
-    END
-END noa2a2a2a24_x1
-
-
-MACRO noa2a2a2a24_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      85.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 69.00 39.00 71.00 41.00 ;
-            RECT 69.00 34.00 71.00 36.00 ;
-            RECT 69.00 29.00 71.00 31.00 ;
-            RECT 69.00 24.00 71.00 26.00 ;
-            RECT 69.00 19.00 71.00 21.00 ;
-            RECT 69.00 14.00 71.00 16.00 ;
-        END
-    END nq
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 64.00 34.00 66.00 36.00 ;
-            RECT 64.00 29.00 66.00 31.00 ;
-            RECT 64.00 24.00 66.00 26.00 ;
-            RECT 64.00 19.00 66.00 21.00 ;
-            RECT 64.00 14.00 66.00 16.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 54.00 29.00 56.00 31.00 ;
-            RECT 54.00 24.00 56.00 26.00 ;
-            RECT 54.00 19.00 56.00 21.00 ;
-            RECT 54.00 14.00 56.00 16.00 ;
-        END
-    END i1
-    PIN i7
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END i7
-    PIN i6
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-        END
-    END i6
-    PIN i5
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-        END
-    END i5
-    PIN i4
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 29.00 31.00 31.00 ;
-            RECT 29.00 24.00 31.00 26.00 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-            RECT 29.00 14.00 31.00 16.00 ;
-        END
-    END i4
-    PIN i3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 34.00 29.00 36.00 31.00 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-            RECT 34.00 14.00 36.00 16.00 ;
-        END
-    END i3
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-            RECT 39.00 24.00 41.00 26.00 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-            RECT 39.00 14.00 41.00 16.00 ;
-        END
-    END i2
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 82.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 82.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 83.50 41.00 ;
-    END
-END noa2a2a2a24_x4
-
-
-MACRO noa2ao222_x1
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      35.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-            LAYER L_ALU1 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-            RECT 14.00 9.00 16.00 11.00 ;
-        END
-    END nq
-    PIN i3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 34.00 31.00 36.00 ;
-            RECT 29.00 29.00 31.00 31.00 ;
-            RECT 29.00 24.00 31.00 26.00 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-            RECT 29.00 14.00 31.00 16.00 ;
-        END
-    END i3
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-        END
-    END i2
-    PIN i4
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-        END
-    END i4
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END i1
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END i0
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 32.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 32.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 33.50 41.00 ;
-    END
-END noa2ao222_x1
-
-
-MACRO noa2ao222_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      60.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 49.00 39.00 51.00 41.00 ;
-            RECT 49.00 34.00 51.00 36.00 ;
-            RECT 49.00 29.00 51.00 31.00 ;
-            RECT 49.00 24.00 51.00 26.00 ;
-            RECT 49.00 19.00 51.00 21.00 ;
-            RECT 49.00 14.00 51.00 16.00 ;
-            RECT 49.00 9.00 51.00 11.00 ;
-        END
-    END nq
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END i1
-    PIN i4
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-        END
-    END i4
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-        END
-    END i2
-    PIN i3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 29.00 31.00 31.00 ;
-            RECT 29.00 24.00 31.00 26.00 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-            RECT 29.00 14.00 31.00 16.00 ;
-        END
-    END i3
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 57.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 57.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 58.50 41.00 ;
-    END
-END noa2ao222_x4
-
-
-MACRO noa3ao322_x1
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      45.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 34.00 26.00 36.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-            LAYER L_ALU1 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-            RECT 19.00 9.00 21.00 11.00 ;
-        END
-    END nq
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END i0
-    PIN i5
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 39.00 34.00 41.00 36.00 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-            RECT 39.00 24.00 41.00 26.00 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-            RECT 39.00 14.00 41.00 16.00 ;
-        END
-    END i5
-    PIN i4
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 34.00 34.00 36.00 36.00 ;
-            RECT 34.00 29.00 36.00 31.00 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-            RECT 34.00 14.00 36.00 16.00 ;
-        END
-    END i4
-    PIN i3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 29.00 31.00 31.00 ;
-            RECT 29.00 24.00 31.00 26.00 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-            RECT 29.00 14.00 31.00 16.00 ;
-        END
-    END i3
-    PIN i6
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-        END
-    END i6
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-        END
-    END i2
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END i1
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 42.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 42.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 43.50 41.00 ;
-    END
-END noa3ao322_x1
-
-
-MACRO noa3ao322_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      65.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 39.00 16.00 41.00 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-            RECT 14.00 9.00 16.00 11.00 ;
-        END
-    END nq
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 34.00 26.00 36.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-        END
-    END i0
-    PIN i3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 49.00 34.00 51.00 36.00 ;
-            RECT 49.00 29.00 51.00 31.00 ;
-            RECT 49.00 24.00 51.00 26.00 ;
-            RECT 49.00 19.00 51.00 21.00 ;
-            RECT 49.00 14.00 51.00 16.00 ;
-        END
-    END i3
-    PIN i5
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 59.00 34.00 61.00 36.00 ;
-            RECT 59.00 29.00 61.00 31.00 ;
-            RECT 59.00 24.00 61.00 26.00 ;
-            RECT 59.00 19.00 61.00 21.00 ;
-            RECT 59.00 14.00 61.00 16.00 ;
-        END
-    END i5
-    PIN i4
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 54.00 34.00 56.00 36.00 ;
-            RECT 54.00 29.00 56.00 31.00 ;
-            RECT 54.00 24.00 56.00 26.00 ;
-            RECT 54.00 19.00 56.00 21.00 ;
-            RECT 54.00 14.00 56.00 16.00 ;
-        END
-    END i4
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 34.00 34.00 36.00 36.00 ;
-            RECT 34.00 29.00 36.00 31.00 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-        END
-    END i2
-    PIN i6
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 39.00 34.00 41.00 36.00 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-            RECT 39.00 24.00 41.00 26.00 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-        END
-    END i6
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 34.00 31.00 36.00 ;
-            RECT 29.00 29.00 31.00 31.00 ;
-            RECT 29.00 24.00 31.00 26.00 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-            RECT 29.00 14.00 31.00 16.00 ;
-        END
-    END i1
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 62.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 62.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 63.50 41.00 ;
-    END
-END noa3ao322_x4
-
-
-MACRO nts_x1
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      30.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT TRISTATE ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 39.00 16.00 41.00 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-            RECT 14.00 9.00 16.00 11.00 ;
-        END
-    END nq
-    PIN i
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 39.00 6.00 41.00 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END i
-    PIN cmd
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END cmd
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 27.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 27.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 28.50 41.00 ;
-    END
-END nts_x1
-
-
-MACRO nts_x2
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      40.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT TRISTATE ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 39.00 16.00 41.00 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-            RECT 14.00 9.00 16.00 11.00 ;
-        END
-    END nq
-    PIN i
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END i
-    PIN cmd
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 34.00 31.00 36.00 ;
-            RECT 29.00 29.00 31.00 31.00 ;
-            RECT 29.00 24.00 31.00 26.00 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-            RECT 29.00 14.00 31.00 16.00 ;
-            RECT 29.00 9.00 31.00 11.00 ;
-        END
-    END cmd
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 37.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 37.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 38.50 41.00 ;
-    END
-END nts_x2
-
-
-MACRO nxr2_x1
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      45.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-            RECT 14.00 9.00 16.00 11.00 ;
-        END
-    END nq
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 34.00 39.00 36.00 41.00 ;
-            RECT 34.00 34.00 36.00 36.00 ;
-            RECT 34.00 29.00 36.00 31.00 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-            RECT 34.00 14.00 36.00 16.00 ;
-            RECT 34.00 9.00 36.00 11.00 ;
-        END
-    END i1
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 42.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 42.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 43.50 41.00 ;
-    END
-END nxr2_x1
-
-
-MACRO nxr2_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      60.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 49.00 39.00 51.00 41.00 ;
-            RECT 49.00 34.00 51.00 36.00 ;
-            RECT 49.00 29.00 51.00 31.00 ;
-            RECT 49.00 24.00 51.00 26.00 ;
-            RECT 49.00 19.00 51.00 21.00 ;
-            RECT 49.00 14.00 51.00 16.00 ;
-            RECT 49.00 9.00 51.00 11.00 ;
-        END
-    END nq
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 34.00 39.00 36.00 41.00 ;
-            RECT 34.00 34.00 36.00 36.00 ;
-            RECT 34.00 29.00 36.00 31.00 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-            RECT 34.00 14.00 36.00 16.00 ;
-        END
-    END i1
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END i0
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 57.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 57.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 58.50 41.00 ;
-    END
-END nxr2_x4
-
-
-MACRO o2_x2
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      25.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 39.00 21.00 41.00 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-            RECT 19.00 9.00 21.00 11.00 ;
-        END
-    END q
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 39.00 16.00 41.00 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-            RECT 14.00 9.00 16.00 11.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-        END
-    END i1
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 22.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 22.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 23.50 41.00 ;
-    END
-END o2_x2
-
-
-MACRO o2_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      30.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 39.00 21.00 41.00 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-            RECT 19.00 9.00 21.00 11.00 ;
-        END
-    END q
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 39.00 16.00 41.00 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-            RECT 14.00 9.00 16.00 11.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-        END
-    END i1
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 27.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 27.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 28.50 41.00 ;
-    END
-END o2_x4
-
-
-MACRO o3_x2
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      30.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 39.00 26.00 41.00 ;
-            RECT 24.00 34.00 26.00 36.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-            RECT 24.00 9.00 26.00 11.00 ;
-        END
-    END q
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END i1
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-        END
-    END i2
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 27.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 27.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 28.50 41.00 ;
-    END
-END o3_x2
-
-
-MACRO o3_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      35.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 39.00 26.00 41.00 ;
-            RECT 24.00 34.00 26.00 36.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-            RECT 24.00 9.00 26.00 11.00 ;
-        END
-    END q
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END i1
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-        END
-    END i2
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 32.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 32.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 33.50 41.00 ;
-    END
-END o3_x4
-
-
-MACRO o4_x2
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      35.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 39.00 31.00 41.00 ;
-            RECT 29.00 34.00 31.00 36.00 ;
-            RECT 29.00 29.00 31.00 31.00 ;
-            RECT 29.00 24.00 31.00 26.00 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-            RECT 29.00 14.00 31.00 16.00 ;
-            RECT 29.00 9.00 31.00 11.00 ;
-        END
-    END q
-    PIN i3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-        END
-    END i3
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-        END
-    END i2
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END i1
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 32.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 32.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 33.50 41.00 ;
-    END
-END o4_x2
-
-
-MACRO o4_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      40.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 39.00 31.00 41.00 ;
-            RECT 29.00 34.00 31.00 36.00 ;
-            RECT 29.00 29.00 31.00 31.00 ;
-            LAYER L_ALU1 ;
-            RECT 34.00 29.00 36.00 31.00 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-            RECT 34.00 14.00 36.00 16.00 ;
-            RECT 34.00 9.00 36.00 11.00 ;
-        END
-    END q
-    PIN i3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 39.00 26.00 41.00 ;
-            RECT 24.00 34.00 26.00 36.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-        END
-    END i3
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END i1
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 39.00 16.00 41.00 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-        END
-    END i0
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 39.00 21.00 41.00 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-        END
-    END i2
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 37.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 37.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 38.50 41.00 ;
-    END
-END o4_x4
-
-
-MACRO oa22_x2
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      30.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 39.00 26.00 41.00 ;
-            RECT 24.00 34.00 26.00 36.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-            RECT 24.00 9.00 26.00 11.00 ;
-        END
-    END q
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 39.00 21.00 41.00 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-            RECT 19.00 9.00 21.00 11.00 ;
-        END
-    END i2
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END i1
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END i0
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 27.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 27.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 28.50 41.00 ;
-    END
-END oa22_x2
-
-
-MACRO oa22_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      40.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 39.00 31.00 41.00 ;
-            RECT 29.00 34.00 31.00 36.00 ;
-            RECT 29.00 29.00 31.00 31.00 ;
-            RECT 29.00 24.00 31.00 26.00 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-            RECT 29.00 14.00 31.00 16.00 ;
-            RECT 29.00 9.00 31.00 11.00 ;
-        END
-    END q
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END i1
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 39.00 21.00 41.00 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-            RECT 19.00 9.00 21.00 11.00 ;
-        END
-    END i2
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 37.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 37.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 38.50 41.00 ;
-    END
-END oa22_x4
-
-
-MACRO oa2a22_x2
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      45.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 39.00 39.00 41.00 41.00 ;
-            RECT 39.00 34.00 41.00 36.00 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-            RECT 39.00 24.00 41.00 26.00 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-            RECT 39.00 14.00 41.00 16.00 ;
-            RECT 39.00 9.00 41.00 11.00 ;
-        END
-    END q
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END i1
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-            RECT 19.00 9.00 21.00 11.00 ;
-        END
-    END i2
-    PIN i3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-            RECT 24.00 9.00 26.00 11.00 ;
-        END
-    END i3
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 42.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 42.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 43.50 41.00 ;
-    END
-END oa2a22_x2
-
-
-MACRO oa2a22_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      50.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 39.00 39.00 41.00 41.00 ;
-            RECT 39.00 34.00 41.00 36.00 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-            RECT 39.00 24.00 41.00 26.00 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-            RECT 39.00 14.00 41.00 16.00 ;
-            RECT 39.00 9.00 41.00 11.00 ;
-        END
-    END q
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END i1
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-            RECT 19.00 9.00 21.00 11.00 ;
-        END
-    END i2
-    PIN i3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-            RECT 24.00 9.00 26.00 11.00 ;
-        END
-    END i3
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 47.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 47.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 48.50 41.00 ;
-    END
-END oa2a22_x4
-
-
-MACRO oa2a2a23_x2
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      60.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 54.00 39.00 56.00 41.00 ;
-            RECT 54.00 34.00 56.00 36.00 ;
-            RECT 54.00 29.00 56.00 31.00 ;
-            RECT 54.00 24.00 56.00 26.00 ;
-            RECT 54.00 19.00 56.00 21.00 ;
-            RECT 54.00 14.00 56.00 16.00 ;
-            RECT 54.00 9.00 56.00 11.00 ;
-        END
-    END q
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 44.00 29.00 46.00 31.00 ;
-            RECT 44.00 24.00 46.00 26.00 ;
-            RECT 44.00 19.00 46.00 21.00 ;
-            RECT 44.00 14.00 46.00 16.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-            RECT 39.00 24.00 41.00 26.00 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-            RECT 39.00 14.00 41.00 16.00 ;
-        END
-    END i1
-    PIN i4
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-        END
-    END i4
-    PIN i3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-        END
-    END i3
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-        END
-    END i2
-    PIN i5
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END i5
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 57.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 57.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 58.50 41.00 ;
-    END
-END oa2a2a23_x2
-
-
-MACRO oa2a2a23_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      65.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 54.00 39.00 56.00 41.00 ;
-            RECT 54.00 34.00 56.00 36.00 ;
-            RECT 54.00 29.00 56.00 31.00 ;
-            RECT 54.00 24.00 56.00 26.00 ;
-            RECT 54.00 19.00 56.00 21.00 ;
-            RECT 54.00 14.00 56.00 16.00 ;
-            RECT 54.00 9.00 56.00 11.00 ;
-        END
-    END q
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-            RECT 39.00 24.00 41.00 26.00 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-            RECT 39.00 14.00 41.00 16.00 ;
-        END
-    END i1
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 44.00 29.00 46.00 31.00 ;
-            RECT 44.00 24.00 46.00 26.00 ;
-            RECT 44.00 19.00 46.00 21.00 ;
-            RECT 44.00 14.00 46.00 16.00 ;
-        END
-    END i0
-    PIN i4
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-        END
-    END i4
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-        END
-    END i2
-    PIN i3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-        END
-    END i3
-    PIN i5
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END i5
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 62.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 62.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 63.50 41.00 ;
-    END
-END oa2a2a23_x4
-
-
-MACRO oa2a2a2a24_x2
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      75.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 69.00 39.00 71.00 41.00 ;
-            RECT 69.00 34.00 71.00 36.00 ;
-            RECT 69.00 29.00 71.00 31.00 ;
-            RECT 69.00 24.00 71.00 26.00 ;
-            RECT 69.00 19.00 71.00 21.00 ;
-            RECT 69.00 14.00 71.00 16.00 ;
-            RECT 69.00 9.00 71.00 11.00 ;
-        END
-    END q
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 54.00 29.00 56.00 31.00 ;
-            RECT 54.00 24.00 56.00 26.00 ;
-            RECT 54.00 19.00 56.00 21.00 ;
-            RECT 54.00 14.00 56.00 16.00 ;
-        END
-    END i1
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 64.00 34.00 66.00 36.00 ;
-            RECT 64.00 29.00 66.00 31.00 ;
-            RECT 64.00 24.00 66.00 26.00 ;
-            RECT 64.00 19.00 66.00 21.00 ;
-            RECT 64.00 14.00 66.00 16.00 ;
-        END
-    END i0
-    PIN i7
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END i7
-    PIN i6
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-        END
-    END i6
-    PIN i5
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-        END
-    END i5
-    PIN i4
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 29.00 31.00 31.00 ;
-            RECT 29.00 24.00 31.00 26.00 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-            RECT 29.00 14.00 31.00 16.00 ;
-        END
-    END i4
-    PIN i3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 34.00 29.00 36.00 31.00 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-            RECT 34.00 14.00 36.00 16.00 ;
-        END
-    END i3
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-            RECT 39.00 24.00 41.00 26.00 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-            RECT 39.00 14.00 41.00 16.00 ;
-        END
-    END i2
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 72.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 72.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 73.50 41.00 ;
-    END
-END oa2a2a2a24_x2
-
-
-MACRO oa2a2a2a24_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      80.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 69.00 39.00 71.00 41.00 ;
-            RECT 69.00 34.00 71.00 36.00 ;
-            RECT 69.00 29.00 71.00 31.00 ;
-            RECT 69.00 24.00 71.00 26.00 ;
-            RECT 69.00 19.00 71.00 21.00 ;
-            RECT 69.00 14.00 71.00 16.00 ;
-            RECT 69.00 9.00 71.00 11.00 ;
-        END
-    END q
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-            RECT 39.00 24.00 41.00 26.00 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-            RECT 39.00 14.00 41.00 16.00 ;
-        END
-    END i2
-    PIN i3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 34.00 29.00 36.00 31.00 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-            RECT 34.00 14.00 36.00 16.00 ;
-        END
-    END i3
-    PIN i4
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 29.00 31.00 31.00 ;
-            RECT 29.00 24.00 31.00 26.00 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-            RECT 29.00 14.00 31.00 16.00 ;
-        END
-    END i4
-    PIN i5
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-        END
-    END i5
-    PIN i6
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-        END
-    END i6
-    PIN i7
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END i7
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 54.00 29.00 56.00 31.00 ;
-            RECT 54.00 24.00 56.00 26.00 ;
-            RECT 54.00 19.00 56.00 21.00 ;
-            RECT 54.00 14.00 56.00 16.00 ;
-        END
-    END i1
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 64.00 34.00 66.00 36.00 ;
-            RECT 64.00 29.00 66.00 31.00 ;
-            RECT 64.00 24.00 66.00 26.00 ;
-            RECT 64.00 19.00 66.00 21.00 ;
-            RECT 64.00 14.00 66.00 16.00 ;
-        END
-    END i0
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 77.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 77.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 78.50 41.00 ;
-    END
-END oa2a2a2a24_x4
-
-
-MACRO oa2ao222_x2
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      50.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 44.00 39.00 46.00 41.00 ;
-            RECT 44.00 34.00 46.00 36.00 ;
-            RECT 44.00 29.00 46.00 31.00 ;
-            RECT 44.00 24.00 46.00 26.00 ;
-            RECT 44.00 19.00 46.00 21.00 ;
-            RECT 44.00 14.00 46.00 16.00 ;
-            RECT 44.00 9.00 46.00 11.00 ;
-        END
-    END q
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END i1
-    PIN i4
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-        END
-    END i4
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-        END
-    END i2
-    PIN i3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 29.00 31.00 31.00 ;
-            RECT 29.00 24.00 31.00 26.00 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-            RECT 29.00 14.00 31.00 16.00 ;
-        END
-    END i3
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 47.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 47.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 48.50 41.00 ;
-    END
-END oa2ao222_x2
-
-
-MACRO oa2ao222_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      55.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 44.00 39.00 46.00 41.00 ;
-            RECT 44.00 34.00 46.00 36.00 ;
-            RECT 44.00 29.00 46.00 31.00 ;
-            RECT 44.00 24.00 46.00 26.00 ;
-            RECT 44.00 19.00 46.00 21.00 ;
-            RECT 44.00 14.00 46.00 16.00 ;
-            RECT 44.00 9.00 46.00 11.00 ;
-        END
-    END q
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END i1
-    PIN i4
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-        END
-    END i4
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-        END
-    END i2
-    PIN i3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 29.00 31.00 31.00 ;
-            RECT 29.00 24.00 31.00 26.00 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-            RECT 29.00 14.00 31.00 16.00 ;
-        END
-    END i3
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 52.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 52.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 53.50 41.00 ;
-    END
-END oa2ao222_x4
-
-
-MACRO oa3ao322_x2
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      55.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 39.00 6.00 41.00 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-            RECT 4.00 9.00 6.00 11.00 ;
-        END
-    END q
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-        END
-    END i0
-    PIN i4
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 44.00 34.00 46.00 36.00 ;
-            RECT 44.00 29.00 46.00 31.00 ;
-            RECT 44.00 24.00 46.00 26.00 ;
-            RECT 44.00 19.00 46.00 21.00 ;
-            RECT 44.00 14.00 46.00 16.00 ;
-        END
-    END i4
-    PIN i5
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 49.00 34.00 51.00 36.00 ;
-            RECT 49.00 29.00 51.00 31.00 ;
-            RECT 49.00 24.00 51.00 26.00 ;
-            RECT 49.00 19.00 51.00 21.00 ;
-            RECT 49.00 14.00 51.00 16.00 ;
-        END
-    END i5
-    PIN i3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 39.00 34.00 41.00 36.00 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-            RECT 39.00 24.00 41.00 26.00 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-            RECT 39.00 14.00 41.00 16.00 ;
-        END
-    END i3
-    PIN i6
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 34.00 31.00 36.00 ;
-            RECT 29.00 29.00 31.00 31.00 ;
-            RECT 29.00 24.00 31.00 26.00 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-        END
-    END i6
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-        END
-    END i1
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 34.00 26.00 36.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-        END
-    END i2
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 52.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 52.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 53.50 41.00 ;
-    END
-END oa3ao322_x2
-
-
-MACRO oa3ao322_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      60.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END q
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 34.00 26.00 36.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-        END
-    END i1
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 34.00 31.00 36.00 ;
-            RECT 29.00 29.00 31.00 31.00 ;
-            RECT 29.00 24.00 31.00 26.00 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-        END
-    END i2
-    PIN i6
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 34.00 34.00 36.00 36.00 ;
-            RECT 34.00 29.00 36.00 31.00 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-        END
-    END i6
-    PIN i4
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 49.00 34.00 51.00 36.00 ;
-            RECT 49.00 29.00 51.00 31.00 ;
-            RECT 49.00 24.00 51.00 26.00 ;
-            RECT 49.00 19.00 51.00 21.00 ;
-            RECT 49.00 14.00 51.00 16.00 ;
-        END
-    END i4
-    PIN i5
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 54.00 34.00 56.00 36.00 ;
-            RECT 54.00 29.00 56.00 31.00 ;
-            RECT 54.00 24.00 56.00 26.00 ;
-            RECT 54.00 19.00 56.00 21.00 ;
-            RECT 54.00 14.00 56.00 16.00 ;
-        END
-    END i5
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-        END
-    END i0
-    PIN i3
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 44.00 34.00 46.00 36.00 ;
-            RECT 44.00 29.00 46.00 31.00 ;
-            RECT 44.00 24.00 46.00 26.00 ;
-            RECT 44.00 19.00 46.00 21.00 ;
-            RECT 44.00 14.00 46.00 16.00 ;
-        END
-    END i3
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 57.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 57.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 58.50 41.00 ;
-    END
-END oa3ao322_x4
-
-
-MACRO on12_x1
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      25.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 39.00 16.00 41.00 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-            RECT 14.00 9.00 16.00 11.00 ;
-        END
-    END q
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END i1
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 39.00 21.00 41.00 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-            RECT 19.00 24.00 21.00 26.00 ;
-            RECT 19.00 19.00 21.00 21.00 ;
-            RECT 19.00 14.00 21.00 16.00 ;
-        END
-    END i0
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 22.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 22.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 23.50 41.00 ;
-    END
-END on12_x1
-
-
-MACRO on12_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      40.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 39.00 31.00 41.00 ;
-            RECT 29.00 34.00 31.00 36.00 ;
-            RECT 29.00 29.00 31.00 31.00 ;
-            RECT 29.00 24.00 31.00 26.00 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-            RECT 29.00 14.00 31.00 16.00 ;
-            RECT 29.00 9.00 31.00 11.00 ;
-        END
-    END q
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 39.00 26.00 41.00 ;
-            RECT 24.00 34.00 26.00 36.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-            RECT 24.00 9.00 26.00 11.00 ;
-        END
-    END i1
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END i0
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 37.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 37.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 38.50 41.00 ;
-    END
-END on12_x4
-
-
-MACRO one_x0
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      15.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END q
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 12.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 12.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 13.50 41.00 ;
-    END
-END one_x0
-
-
-MACRO powmid_x0
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      35.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 32.00 47.00 ;
-            LAYER L_ALU3 ;
-            WIDTH 12.00 ;
-            PATH 10.00 6.00 10.00 44.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 32.00 3.00 ;
-            LAYER L_ALU3 ;
-            WIDTH 12.00 ;
-            PATH 25.00 6.00 25.00 44.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 33.50 41.00 ;
-    END
-END powmid_x0
-
-
-MACRO rowend_x0
-    CLASS     CORE FEEDTHRU ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      5.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 2.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 2.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 3.50 41.00 ;
-    END
-END rowend_x0
-
-
-MACRO sff1_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      90.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 79.00 39.00 81.00 41.00 ;
-            RECT 79.00 34.00 81.00 36.00 ;
-            RECT 79.00 29.00 81.00 31.00 ;
-            RECT 79.00 24.00 81.00 26.00 ;
-            RECT 79.00 19.00 81.00 21.00 ;
-            RECT 79.00 14.00 81.00 16.00 ;
-            RECT 79.00 9.00 81.00 11.00 ;
-        END
-    END q
-    PIN ck
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END ck
-    PIN i
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 9.00 31.00 11.00 ;
-            LAYER L_ALU1 ;
-            RECT 29.00 39.00 31.00 41.00 ;
-            LAYER L_ALU1 ;
-            RECT 24.00 34.00 26.00 36.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-        END
-    END i
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 87.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 87.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 88.50 41.00 ;
-    END
-END sff1_x4
-
-
-MACRO sff2_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      120.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 109.00 39.00 111.00 41.00 ;
-            RECT 109.00 34.00 111.00 36.00 ;
-            RECT 109.00 29.00 111.00 31.00 ;
-            RECT 109.00 24.00 111.00 26.00 ;
-            RECT 109.00 19.00 111.00 21.00 ;
-            RECT 109.00 14.00 111.00 16.00 ;
-            RECT 109.00 9.00 111.00 11.00 ;
-        END
-    END q
-    PIN ck
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 44.00 34.00 46.00 36.00 ;
-            RECT 44.00 29.00 46.00 31.00 ;
-            RECT 44.00 24.00 46.00 26.00 ;
-            RECT 44.00 19.00 46.00 21.00 ;
-            RECT 44.00 14.00 46.00 16.00 ;
-            RECT 44.00 9.00 46.00 11.00 ;
-        END
-    END ck
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-        END
-    END i0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 34.00 31.00 36.00 ;
-            RECT 29.00 29.00 31.00 31.00 ;
-            RECT 29.00 24.00 31.00 26.00 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-            RECT 29.00 14.00 31.00 16.00 ;
-            RECT 29.00 9.00 31.00 11.00 ;
-        END
-    END i1
-    PIN cmd
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 39.00 16.00 41.00 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-        END
-    END cmd
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 117.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 117.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 118.50 41.00 ;
-    END
-END sff2_x4
-
-
-MACRO sff3_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      140.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 129.00 39.00 131.00 41.00 ;
-            RECT 129.00 34.00 131.00 36.00 ;
-            RECT 129.00 29.00 131.00 31.00 ;
-            RECT 129.00 24.00 131.00 26.00 ;
-            RECT 129.00 19.00 131.00 21.00 ;
-            RECT 129.00 14.00 131.00 16.00 ;
-            RECT 129.00 9.00 131.00 11.00 ;
-        END
-    END q
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 44.00 24.00 46.00 26.00 ;
-            LAYER L_ALU1 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-            LAYER L_ALU1 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-        END
-    END i0
-    PIN cmd0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 34.00 29.00 36.00 31.00 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-        END
-    END cmd0
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-        END
-    END i1
-    PIN i2
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-        END
-    END i2
-    PIN cmd1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 4.00 34.00 6.00 36.00 ;
-            RECT 4.00 29.00 6.00 31.00 ;
-            RECT 4.00 24.00 6.00 26.00 ;
-            RECT 4.00 19.00 6.00 21.00 ;
-            RECT 4.00 14.00 6.00 16.00 ;
-        END
-    END cmd1
-    PIN ck
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 59.00 34.00 61.00 36.00 ;
-            RECT 59.00 29.00 61.00 31.00 ;
-            RECT 59.00 24.00 61.00 26.00 ;
-            RECT 59.00 19.00 61.00 21.00 ;
-            RECT 59.00 14.00 61.00 16.00 ;
-            RECT 59.00 9.00 61.00 11.00 ;
-        END
-    END ck
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 137.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 137.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 138.50 41.00 ;
-    END
-END sff3_x4
-
-
-MACRO tie_x0
-    CLASS     CORE FEEDTHRU ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      10.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 7.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 7.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 8.50 41.00 ;
-    END
-END tie_x0
-
-
-MACRO ts_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      50.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT TRISTATE ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END q
-    PIN i
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 39.00 34.00 41.00 36.00 ;
-            RECT 39.00 29.00 41.00 31.00 ;
-            RECT 39.00 24.00 41.00 26.00 ;
-            RECT 39.00 19.00 41.00 21.00 ;
-            RECT 39.00 14.00 41.00 16.00 ;
-        END
-    END i
-    PIN cmd
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 14.00 39.00 16.00 41.00 ;
-            RECT 14.00 34.00 16.00 36.00 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-            RECT 14.00 9.00 16.00 11.00 ;
-        END
-    END cmd
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 47.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 47.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 48.50 41.00 ;
-    END
-END ts_x4
-
-
-MACRO ts_x8
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      65.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT TRISTATE ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 24.00 39.00 26.00 41.00 ;
-            RECT 24.00 34.00 26.00 36.00 ;
-            RECT 24.00 29.00 26.00 31.00 ;
-            RECT 24.00 24.00 26.00 26.00 ;
-            RECT 24.00 19.00 26.00 21.00 ;
-            RECT 24.00 14.00 26.00 16.00 ;
-            RECT 24.00 9.00 26.00 11.00 ;
-        END
-    END q
-    PIN i
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 54.00 34.00 56.00 36.00 ;
-            RECT 54.00 29.00 56.00 31.00 ;
-            RECT 54.00 24.00 56.00 26.00 ;
-            RECT 54.00 19.00 56.00 21.00 ;
-            RECT 54.00 14.00 56.00 16.00 ;
-        END
-    END i
-    PIN cmd
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 29.00 39.00 31.00 41.00 ;
-            RECT 29.00 34.00 31.00 36.00 ;
-            RECT 29.00 29.00 31.00 31.00 ;
-            RECT 29.00 24.00 31.00 26.00 ;
-            RECT 29.00 19.00 31.00 21.00 ;
-            RECT 29.00 14.00 31.00 16.00 ;
-            RECT 29.00 9.00 31.00 11.00 ;
-        END
-    END cmd
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 62.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 62.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 63.50 41.00 ;
-    END
-END ts_x8
-
-
-MACRO xr2_x1
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      45.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 19.00 9.00 21.00 11.00 ;
-            LAYER L_ALU1 ;
-            RECT 14.00 29.00 16.00 31.00 ;
-            RECT 14.00 24.00 16.00 26.00 ;
-            RECT 14.00 19.00 16.00 21.00 ;
-            RECT 14.00 14.00 16.00 16.00 ;
-            RECT 14.00 9.00 16.00 11.00 ;
-            LAYER L_ALU1 ;
-            RECT 19.00 34.00 21.00 36.00 ;
-            RECT 19.00 29.00 21.00 31.00 ;
-        END
-    END q
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 34.00 39.00 36.00 41.00 ;
-            RECT 34.00 34.00 36.00 36.00 ;
-            RECT 34.00 29.00 36.00 31.00 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-            RECT 34.00 14.00 36.00 16.00 ;
-            RECT 34.00 9.00 36.00 11.00 ;
-        END
-    END i1
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END i0
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 42.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 42.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 43.50 41.00 ;
-    END
-END xr2_x1
-
-
-MACRO xr2_x4
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      60.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN q
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 49.00 39.00 51.00 41.00 ;
-            RECT 49.00 34.00 51.00 36.00 ;
-            RECT 49.00 29.00 51.00 31.00 ;
-            RECT 49.00 24.00 51.00 26.00 ;
-            RECT 49.00 19.00 51.00 21.00 ;
-            RECT 49.00 14.00 51.00 16.00 ;
-            RECT 49.00 9.00 51.00 11.00 ;
-        END
-    END q
-    PIN i1
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 34.00 39.00 36.00 41.00 ;
-            RECT 34.00 34.00 36.00 36.00 ;
-            RECT 34.00 29.00 36.00 31.00 ;
-            RECT 34.00 24.00 36.00 26.00 ;
-            RECT 34.00 19.00 36.00 21.00 ;
-            RECT 34.00 14.00 36.00 16.00 ;
-        END
-    END i1
-    PIN i0
-        DIRECTION INPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END i0
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 57.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 57.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 58.50 41.00 ;
-    END
-END xr2_x4
-
-
-MACRO zero_x0
-    CLASS     CORE ;
-    ORIGIN    0.00 0.00 ;
-    SIZE      15.00 BY 50.00 ;
-    SYMMETRY  X Y ;
-    SITE      core ;
-    PIN nq
-        DIRECTION OUTPUT ;
-        PORT
-            LAYER L_ALU1 ;
-            RECT 9.00 39.00 11.00 41.00 ;
-            RECT 9.00 34.00 11.00 36.00 ;
-            RECT 9.00 29.00 11.00 31.00 ;
-            RECT 9.00 24.00 11.00 26.00 ;
-            RECT 9.00 19.00 11.00 21.00 ;
-            RECT 9.00 14.00 11.00 16.00 ;
-            RECT 9.00 9.00 11.00 11.00 ;
-        END
-    END nq
-    PIN vdd
-        DIRECTION INOUT ;
-        USE power ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 47.00 12.00 47.00 ;
-        END
-    END vdd
-    PIN vss
-        DIRECTION INOUT ;
-        USE ground ;
-        SHAPE ABUTMENT ;
-        PORT
-            LAYER L_ALU1 ;
-            WIDTH 6.00 ;
-            PATH 3.00 3.00 12.00 3.00 ;
-        END
-    END vss
-    OBS
-        LAYER L_ALU1 ;
-        RECT 1.50 9.00 13.50 41.00 ;
-    END
-END zero_x0
-
-
-END LIBRARY
diff --git a/alliance/share/cells/sxlib/sxlib.lib b/alliance/share/cells/sxlib/sxlib.lib
deleted file mode 100644
index 079af9c0..00000000
--- a/alliance/share/cells/sxlib/sxlib.lib
+++ /dev/null
@@ -1,5019 +0,0 @@
-/* --------------------------------------------- */
-/* written by Franck LE DU and Franck Wajsburt   */
-/*                                               */
-/* DEF_SXLIB    modified : Sep 27, 1999          */
-/*                                               */
-/* This file is obtained from                    */
-/* the technolocal parameters contained in the   */
-/* VHDL generic data included in the .vbe files. */
-/* This file should not be edited directly.      */
-/*                                               */
-/* NOTE FOR NEW REVISION THAT ALL NON ZERO VALUE */
-/* MUST BE UPDATED TO THE NEW TECHNOLOGY AND ALL */
-/* ZERO VALUE SHOULD REMAIN ZERO (CHANGE         */
-/* DEFAULT_WIRE_LOAD_RESISTANCE MAY HAVE NO      */
-/* EFFECT SINCE ALL USEFUL PARAMETER REQUIRED TO */
-/* TAKE RESISTANCE INTO ACCOUNT ARE NOT DEFINED  */
-/* IN THIS FILE                                  */
-/* --------------------------------------------- */
-
-library (sxlib) {
-
-    date        : "Thu Dec 21 11:24:55 MET 2000";
-    revision    : 1.2;
-
-    /* --------------------------------------------- */
-    /*  Set of default values required for Synopsys  */
-    /*  technology library generation                */
-    /* --------------------------------------------- */
-
-    /* --------------------------------------------- */
-    /* default values intended to represent a        */
-    /* typical na2_x1 cell                           */
-    /* --------------------------------------------- */
-
-    default_inout_pin_cap        :  0.011;	/* pf=<grid capa> + <pin capa> */
-    default_inout_pin_fall_res   :  2.850;	/* kOhms */
-    default_inout_pin_rise_res   :  3.720;	/* kOhms */
-    default_input_pin_cap        :  0.011;	/* pf=<grid capa> + <pin capa> */
-    default_intrinsic_fall       :  0.059;	/* ns */
-    default_intrinsic_rise       :  0.059;	/* ns */
-    default_output_pin_cap       :  0;   	/* must be 0 */
-    default_output_pin_fall_res  :  2.850;	/* kOhms */
-    default_output_pin_rise_res  :  3.720;	/* kOhms */
-    default_slope_fall           :  0.1; 	/* worst case meaning propagation */
-                                         	/* time is delayed of .1 the */
-                                         	/* transition time of the previous*/
-                                         	/* gate                           */
-    default_slope_rise           :  0.1; 	/* idem */
-    default_fanout_load          :  0.011;	/* max of input capacities in pF  */
-    default_max_fanout           :  0.078;	/* max output capacitance in pF   */
-                                         	/* computed in order to a inv_x1   */
-                                         	/* be able to drive 10 inv_x1      */
-
-    /* --------------------------------------------- */
-    /* default_wire_load_capacitance in pf/lambda    */
-    /* is capacitance-per-unit-length value of       */
-    /* the routing wire                              */
-    /* --------------------------------------------- */
-
-    default_wire_load_capacitance : 0.00015;/* pf/lambda */
-    default_wire_load_resistance  : 0;      /* must be 0 */
-    default_wire_load_area        : 0;      /* must be 0 */
-    default_wire_load_mode        : enclosed;/* top/segmented/enclosed */
-
-    /* --------------------------------------------- */
-    /* all these parameters are neglected since      */
-    /* we choose to only time design with worst case */
-    /* operating conditions (must be 0)              */
-    /* --------------------------------------------- */
-
-    k_process_drive_fall         : 0.0;
-    k_process_drive_rise         : 0.0;
-    k_process_intrinsic_fall     : 0.0;
-    k_process_intrinsic_rise     : 0.0;
-    k_process_pin_cap            : 0.0;
-    k_process_slope_fall         : 0.0;
-    k_process_slope_rise         : 0.0;
-    k_process_wire_cap           : 0.0;
-    k_process_wire_res           : 0.0;
-    k_temp_drive_fall            : 0.0;
-    k_temp_drive_rise            : 0.0;
-    k_temp_intrinsic_fall        : 0.0;
-    k_temp_intrinsic_rise        : 0.0;
-    k_temp_pin_cap               : 0.0;
-    k_temp_slope_fall            : 0.0;
-    k_temp_slope_rise            : 0.0;
-    k_temp_wire_cap              : 0.0;
-    k_temp_wire_res              : 0.0;
-    k_volt_drive_fall            : 0.0;
-    k_volt_drive_rise            : 0.0;
-    k_volt_intrinsic_fall        : 0.0;
-    k_volt_intrinsic_rise        : 0.0;
-    k_volt_pin_cap               : 0.0;
-    k_volt_slope_fall            : 0.0;
-    k_volt_slope_rise            : 0.0;
-    k_volt_wire_cap              : 0.0;
-    k_volt_wire_res              : 0.0;
-
-    /* -------------------------------------------- */
-    /* values given as information (unused for      */
-    /* timing design computation)                   */
-    /* -------------------------------------------- */
-
-    time_unit                    : "1ns";
-    voltage_unit                 : "1V";
-    current_unit                 : "1uA";
-    pulling_resistance_unit      : "1kohm";
-    capacitive_load_unit           (1,pf);
-
-    /* -------------------------------------------- */
-    /* Operating conditions                         */
-    /* -------------------------------------------- */
-
-    nom_process                  :  1.5;
-    nom_temperature              : 70.0;
-    nom_voltage                  :  3.0;
-
-    in_place_swap_mode           : match_footprint;
-
-    /* -------------------------------------------- */
-    /* slope and fanout_length are expressed        */
-    /* in lambda. it represents the average wire    */
-    /* length from the driver output to one of the  */
-    /* following input. It means it needs 50        */
-    /* lambdas of wire to connect 2 cells whatever  */
-    /* in small case                                */
-    /* -------------------------------------------- */
-
-    wire_load("small") {
-        resistance              : 0 ;       /* must be 0 */
-        capacitance             : 0.00015 ; /* pf/lambda */
-        area                    : 0 ;       /* must be 0 */
-        slope                   : 100;       /* lambda */
-        fanout_length(1,100) ; /* first parameter must be 1, second in lambda */
-    }
-    wire_load("medium") {
-        resistance              : 0 ;       /* must be 0 */
-        capacitance             : 0.00015 ; /* pf/lambda */
-        area                    : 0 ;       /* must be 0 */
-        slope                   : 200;       /* lambda */
-        fanout_length(1,200) ; /* first parameter must be 1, second in lambda */
-    }
-    wire_load("big") {
-        resistance              : 0 ;       /* must be 0 */
-        capacitance             : 0.00015 ; /* pf/lambda */
-        area                    : 0 ;       /* must be 0 */
-        slope                   : 400;       /* lambda */
-        fanout_length(1,400) ; /* first parameter must be 1, second in lambda */
-    }
-
-    wire_load_selection(medium) {
-        wire_load_from_area(0,500,"small");     /* less about  200 gates */
-        wire_load_from_area(500,1500,"medium"); /* less about  500 gates */
-        wire_load_from_area(1500,3000,"big");   /* less about 1000 gates */
-    }
-    default_wire_load_selection : medium
-
-    /*---------------------------------------------- */
-    /* Combinationnal cells part 1                   */
-    /*---------------------------------------------- */
-
-    cell (inv_x1) {
-        area : 1.0  /* pitchs */
-        cell_footprint : "inv";
-        pin(i) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.078;
-            function : "i'";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.101;
-                intrinsic_fall  : 0.139;
-                rise_resistance : 3.720;
-                fall_resistance : 3.640;
-                related_pin     : "i";
-            }
-        }
-    }
-    cell (inv_x2) {
-        area : 1.0  /* pitchs */
-        cell_footprint : "inv";
-        pin(i) {
-            direction   : input;
-            capacitance : 0.012;
-            fanout_load : 0.012;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.120;
-            function : "i'";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.069;
-                intrinsic_fall  : 0.163;
-                rise_resistance : 2.420;
-                fall_resistance : 1.620;
-                related_pin     : "i";
-            }
-        }
-    }
-    cell (inv_x4) {
-        area : 1.3  /* pitchs */
-        cell_footprint : "inv";
-        pin(i) {
-            direction   : input;
-            capacitance : 0.026;
-            fanout_load : 0.026;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.275;
-            function : "i'";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.071;
-                intrinsic_fall  : 0.143;
-                rise_resistance : 1.060;
-                fall_resistance : 0.810;
-                related_pin     : "i";
-            }
-        }
-    }
-    cell (inv_x8) {
-        area : 2.3  /* pitchs */
-        cell_footprint : "inv";
-        pin(i) {
-            direction   : input;
-            capacitance : 0.054;
-            fanout_load : 0.054;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.647;
-            function : "i'";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.086;
-                intrinsic_fall  : 0.133;
-                rise_resistance : 0.450;
-                fall_resistance : 0.400;
-                related_pin     : "i";
-            }
-        }
-    }
-    cell (an12_x1) {
-        area : 1.7  /* pitchs */
-        cell_footprint : "an12";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.012;
-            fanout_load : 0.012;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.080;
-            function : "i0' * i1";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.200;
-                intrinsic_fall  : 0.168;
-                rise_resistance : 3.210;
-                fall_resistance : 3.640;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.285;
-                intrinsic_fall  : 0.405;
-                rise_resistance : 3.210;
-                fall_resistance : 3.640;
-                related_pin     : "i1";
-            }
-        }
-    }
-    cell (an12_x4) {
-        area : 2.7  /* pitchs */
-        cell_footprint : "an12";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "i0' * i1";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.461;
-                intrinsic_fall  : 0.471;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.269;
-                intrinsic_fall  : 0.518;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-        }
-    }
-    cell (on12_x1) {
-        area : 1.7  /* pitchs */
-        cell_footprint : "on12";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.078;
-            function : "i0' + i1";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.111;
-                intrinsic_fall  : 0.234;
-                rise_resistance : 3.720;
-                fall_resistance : 2.850;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.314;
-                intrinsic_fall  : 0.291;
-                rise_resistance : 3.720;
-                fall_resistance : 2.850;
-                related_pin     : "i1";
-            }
-        }
-    }
-    cell (on12_x4) {
-        area : 2.7  /* pitchs */
-        cell_footprint : "on12";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.010;
-            fanout_load : 0.010;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "i0' + i1";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.474;
-                intrinsic_fall  : 0.499;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.491;
-                intrinsic_fall  : 0.394;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-        }
-    }
-    cell (na2_x1) {
-        area : 1.3  /* pitchs */
-        cell_footprint : "na2";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.078;
-            function : "(i0' + i1')";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.059;
-                intrinsic_fall  : 0.288;
-                rise_resistance : 3.720;
-                fall_resistance : 2.850;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.111;
-                intrinsic_fall  : 0.234;
-                rise_resistance : 3.720;
-                fall_resistance : 2.850;
-                related_pin     : "i1";
-            }
-        }
-    }
-    cell (na2_x4) {
-        area : 2.3  /* pitchs */
-        cell_footprint : "na2";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.010;
-            fanout_load : 0.010;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.010;
-            fanout_load : 0.010;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "(i0' + i1')";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.412;
-                intrinsic_fall  : 0.552;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.353;
-                intrinsic_fall  : 0.601;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-        }
-    }
-    cell (no2_x1) {
-        area : 1.3  /* pitchs */
-        cell_footprint : "no2";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.012;
-            fanout_load : 0.012;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.012;
-            fanout_load : 0.012;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.080;
-            function : "(i0' * i1')";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.298;
-                intrinsic_fall  : 0.121;
-                rise_resistance : 3.210;
-                fall_resistance : 3.640;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.193;
-                intrinsic_fall  : 0.161;
-                rise_resistance : 3.210;
-                fall_resistance : 3.640;
-                related_pin     : "i1";
-            }
-        }
-    }
-    cell (no2_x4) {
-        area : 2.3  /* pitchs */
-        cell_footprint : "no2";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.012;
-            fanout_load : 0.012;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "(i0' * i1')";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.618;
-                intrinsic_fall  : 0.447;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.522;
-                intrinsic_fall  : 0.504;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-        }
-    }
-    cell (na3_x1) {
-        area : 1.7  /* pitchs */
-        cell_footprint : "na3";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.071;
-            function : "(i0' + i1' + i2')";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.119;
-                intrinsic_fall  : 0.363;
-                rise_resistance : 3.720;
-                fall_resistance : 4.120;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.171;
-                intrinsic_fall  : 0.316;
-                rise_resistance : 3.720;
-                fall_resistance : 4.120;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.193;
-                intrinsic_fall  : 0.265;
-                rise_resistance : 3.720;
-                fall_resistance : 4.120;
-                related_pin     : "i2";
-            }
-        }
-    }
-    cell (na3_x4) {
-        area : 2.7  /* pitchs */
-        cell_footprint : "na3";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.010;
-            fanout_load : 0.010;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.010;
-            fanout_load : 0.010;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.010;
-            fanout_load : 0.010;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "(i0' + i1' + i2')";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.556;
-                intrinsic_fall  : 0.601;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.460;
-                intrinsic_fall  : 0.691;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.519;
-                intrinsic_fall  : 0.647;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i2";
-            }
-        }
-    }
-    cell (nao22_x1) {
-        area : 2.0  /* pitchs */
-        cell_footprint : "nao22";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.015;
-            fanout_load : 0.015;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.091;
-            function : "((i0' * i1') + i2')";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.294;
-                intrinsic_fall  : 0.226;
-                rise_resistance : 3.210;
-                fall_resistance : 2.850;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.218;
-                intrinsic_fall  : 0.287;
-                rise_resistance : 3.210;
-                fall_resistance : 2.850;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.165;
-                intrinsic_fall  : 0.238;
-                rise_resistance : 1.790;
-                fall_resistance : 2.850;
-                related_pin     : "i2";
-            }
-        }
-    }
-    cell (nao22_x4) {
-        area : 3.3  /* pitchs */
-        cell_footprint : "nao22";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "((i0' * i1') + i2')";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.732;
-                intrinsic_fall  : 0.650;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.664;
-                intrinsic_fall  : 0.723;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.596;
-                intrinsic_fall  : 0.636;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i2";
-            }
-        }
-    }
-    cell (nmx2_x1) {
-        area : 2.3  /* pitchs */
-        cell_footprint : "nmx2";
-        pin(cmd) {
-            direction   : input;
-            capacitance : 0.021;
-            fanout_load : 0.021;
-        }
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.091;
-            function : "((cmd + i0') * (cmd' + i1'))";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.218;
-                intrinsic_fall  : 0.287;
-                rise_resistance : 3.210;
-                fall_resistance : 2.850;
-                related_pin     : "cmd";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.217;
-                intrinsic_fall  : 0.256;
-                rise_resistance : 3.210;
-                fall_resistance : 2.850;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.217;
-                intrinsic_fall  : 0.256;
-                rise_resistance : 3.210;
-                fall_resistance : 2.850;
-                related_pin     : "i1";
-            }
-        }
-    }
-    cell (nmx2_x4) {
-        area : 4.0  /* pitchs */
-        cell_footprint : "nmx2";
-        pin(cmd) {
-            direction   : input;
-            capacitance : 0.017;
-            fanout_load : 0.017;
-        }
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "((cmd + i0') * (cmd' + i1'))";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.632;
-                intrinsic_fall  : 0.708;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "cmd";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.610;
-                intrinsic_fall  : 0.653;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.610;
-                intrinsic_fall  : 0.653;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-        }
-    }
-    cell (no3_x1) {
-        area : 1.7  /* pitchs */
-        cell_footprint : "no3";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.012;
-            fanout_load : 0.012;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.012;
-            fanout_load : 0.012;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.012;
-            fanout_load : 0.012;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.062;
-            function : "(i0' * i1' * i2')";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.318;
-                intrinsic_fall  : 0.246;
-                rise_resistance : 4.690;
-                fall_resistance : 3.640;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.215;
-                intrinsic_fall  : 0.243;
-                rise_resistance : 4.690;
-                fall_resistance : 3.640;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.407;
-                intrinsic_fall  : 0.192;
-                rise_resistance : 4.690;
-                fall_resistance : 3.640;
-                related_pin     : "i2";
-            }
-        }
-    }
-    cell (no3_x4) {
-        area : 2.7  /* pitchs */
-        cell_footprint : "no3";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.012;
-            fanout_load : 0.012;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.012;
-            fanout_load : 0.012;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "(i0' * i1' * i2')";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.722;
-                intrinsic_fall  : 0.561;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.638;
-                intrinsic_fall  : 0.623;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.545;
-                intrinsic_fall  : 0.640;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i2";
-            }
-        }
-    }
-    cell (noa22_x1) {
-        area : 2.0  /* pitchs */
-        cell_footprint : "noa22";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.015;
-            fanout_load : 0.015;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.091;
-            function : "((i0' + i1') * i2')";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.151;
-                intrinsic_fall  : 0.327;
-                rise_resistance : 3.210;
-                fall_resistance : 2.850;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.218;
-                intrinsic_fall  : 0.287;
-                rise_resistance : 3.210;
-                fall_resistance : 2.850;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.218;
-                intrinsic_fall  : 0.241;
-                rise_resistance : 3.210;
-                fall_resistance : 1.620;
-                related_pin     : "i2";
-            }
-        }
-    }
-    cell (noa22_x4) {
-        area : 3.3  /* pitchs */
-        cell_footprint : "noa22";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "((i0' + i1') * i2')";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.550;
-                intrinsic_fall  : 0.740;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.643;
-                intrinsic_fall  : 0.709;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.610;
-                intrinsic_fall  : 0.646;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i2";
-            }
-        }
-    }
-    cell (na4_x1) {
-        area : 2.0  /* pitchs */
-        cell_footprint : "na4";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.010;
-            fanout_load : 0.010;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(i3) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.054;
-            function : "(i0' + i1' + i2' + i3')";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.179;
-                intrinsic_fall  : 0.438;
-                rise_resistance : 3.720;
-                fall_resistance : 5.400;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.237;
-                intrinsic_fall  : 0.395;
-                rise_resistance : 3.720;
-                fall_resistance : 5.400;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.269;
-                intrinsic_fall  : 0.350;
-                rise_resistance : 3.720;
-                fall_resistance : 5.400;
-                related_pin     : "i2";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.282;
-                intrinsic_fall  : 0.302;
-                rise_resistance : 3.720;
-                fall_resistance : 5.400;
-                related_pin     : "i3";
-            }
-        }
-    }
-    cell (na4_x4) {
-        area : 3.3  /* pitchs */
-        cell_footprint : "na4";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.010;
-            fanout_load : 0.010;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(i3) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "(i0' + i1' + i2' + i3')";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.578;
-                intrinsic_fall  : 0.771;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.643;
-                intrinsic_fall  : 0.731;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.681;
-                intrinsic_fall  : 0.689;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i2";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.703;
-                intrinsic_fall  : 0.644;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i3";
-            }
-        }
-    }
-    cell (nao2o22_x1) {
-        area : 2.3  /* pitchs */
-        cell_footprint : "nao2o22";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i3) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.091;
-            function : "((i0' * i1') + (i2' * i3'))";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.294;
-                intrinsic_fall  : 0.226;
-                rise_resistance : 3.210;
-                fall_resistance : 2.850;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.218;
-                intrinsic_fall  : 0.287;
-                rise_resistance : 3.210;
-                fall_resistance : 2.850;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.237;
-                intrinsic_fall  : 0.307;
-                rise_resistance : 3.210;
-                fall_resistance : 2.850;
-                related_pin     : "i2";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.174;
-                intrinsic_fall  : 0.382;
-                rise_resistance : 3.210;
-                fall_resistance : 2.850;
-                related_pin     : "i3";
-            }
-        }
-    }
-    cell (nao2o22_x4) {
-        area : 3.7  /* pitchs */
-        cell_footprint : "nao2o22";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i3) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "((i0' * i1') + (i2' * i3'))";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.734;
-                intrinsic_fall  : 0.644;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.666;
-                intrinsic_fall  : 0.717;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.664;
-                intrinsic_fall  : 0.721;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i2";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.607;
-                intrinsic_fall  : 0.807;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i3";
-            }
-        }
-    }
-    cell (no4_x1) {
-        area : 2.0  /* pitchs */
-        cell_footprint : "no4";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.012;
-            fanout_load : 0.012;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.012;
-            fanout_load : 0.012;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.012;
-            fanout_load : 0.012;
-        }
-        pin(i3) {
-            direction   : input;
-            capacitance : 0.012;
-            fanout_load : 0.012;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.047;
-            function : "(i0' * i1' * i2' * i3')";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.330;
-                intrinsic_fall  : 0.340;
-                rise_resistance : 6.190;
-                fall_resistance : 3.640;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.230;
-                intrinsic_fall  : 0.320;
-                rise_resistance : 6.190;
-                fall_resistance : 3.640;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.419;
-                intrinsic_fall  : 0.333;
-                rise_resistance : 6.190;
-                fall_resistance : 3.640;
-                related_pin     : "i2";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.499;
-                intrinsic_fall  : 0.271;
-                rise_resistance : 6.190;
-                fall_resistance : 3.640;
-                related_pin     : "i3";
-            }
-        }
-    }
-    cell (no4_x4) {
-        area : 3.3  /* pitchs */
-        cell_footprint : "no4";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.012;
-            fanout_load : 0.012;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.012;
-            fanout_load : 0.012;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.012;
-            fanout_load : 0.012;
-        }
-        pin(i3) {
-            direction   : input;
-            capacitance : 0.012;
-            fanout_load : 0.012;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "(i0' * i1' * i2' * i3')";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.656;
-                intrinsic_fall  : 0.777;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.564;
-                intrinsic_fall  : 0.768;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.739;
-                intrinsic_fall  : 0.761;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i2";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.816;
-                intrinsic_fall  : 0.693;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i3";
-            }
-        }
-    }
-    cell (noa2a22_x1) {
-        area : 2.3  /* pitchs */
-        cell_footprint : "noa2a22";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i3) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.091;
-            function : "((i0' + i1') * (i2' + i3'))";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.151;
-                intrinsic_fall  : 0.327;
-                rise_resistance : 3.210;
-                fall_resistance : 2.850;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.218;
-                intrinsic_fall  : 0.287;
-                rise_resistance : 3.210;
-                fall_resistance : 2.850;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.284;
-                intrinsic_fall  : 0.289;
-                rise_resistance : 3.210;
-                fall_resistance : 2.850;
-                related_pin     : "i2";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.372;
-                intrinsic_fall  : 0.256;
-                rise_resistance : 3.210;
-                fall_resistance : 2.850;
-                related_pin     : "i3";
-            }
-        }
-    }
-    cell (noa2a22_x4) {
-        area : 3.7  /* pitchs */
-        cell_footprint : "noa2a22";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i3) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "((i0' + i1') * (i2' + i3'))";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.562;
-                intrinsic_fall  : 0.745;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.646;
-                intrinsic_fall  : 0.714;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.701;
-                intrinsic_fall  : 0.703;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i2";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.805;
-                intrinsic_fall  : 0.677;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i3";
-            }
-        }
-    }
-    cell (nmx3_x1) {
-        area : 4.0  /* pitchs */
-        cell_footprint : "nmx3";
-        pin(cmd0) {
-            direction   : input;
-            capacitance : 0.015;
-            fanout_load : 0.015;
-        }
-        pin(cmd1) {
-            direction   : input;
-            capacitance : 0.015;
-            fanout_load : 0.015;
-        }
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.030;
-            function : "((cmd0+i0')*(cmd0'+((cmd1'+i1')*(cmd1+i2'))))";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.356;
-                intrinsic_fall  : 0.495;
-                rise_resistance : 9.760;
-                fall_resistance : 7.420;
-                related_pin     : "cmd0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.414;
-                intrinsic_fall  : 0.566;
-                rise_resistance : 9.760;
-                fall_resistance : 7.420;
-                related_pin     : "cmd1";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.315;
-                intrinsic_fall  : 0.441;
-                rise_resistance : 6.680;
-                fall_resistance : 5.140;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.429;
-                intrinsic_fall  : 0.582;
-                rise_resistance : 9.760;
-                fall_resistance : 7.420;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.429;
-                intrinsic_fall  : 0.582;
-                rise_resistance : 9.760;
-                fall_resistance : 7.420;
-                related_pin     : "i2";
-            }
-        }
-    }
-    cell (nmx3_x4) {
-        area : 5.0  /* pitchs */
-        cell_footprint : "nmx3";
-        pin(cmd0) {
-            direction   : input;
-            capacitance : 0.015;
-            fanout_load : 0.015;
-        }
-        pin(cmd1) {
-            direction   : input;
-            capacitance : 0.015;
-            fanout_load : 0.015;
-        }
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "((cmd0+i0')*(cmd0'+((cmd1'+i1')*(cmd1+i2'))))";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.790;
-                intrinsic_fall  : 0.936;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "cmd0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.866;
-                intrinsic_fall  : 1.048;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "cmd1";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.748;
-                intrinsic_fall  : 0.900;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.869;
-                intrinsic_fall  : 1.053;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.869;
-                intrinsic_fall  : 1.053;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i2";
-            }
-        }
-    }
-    cell (noa2ao222_x1) {
-        area : 2.3  /* pitchs */
-        cell_footprint : "noa2ao222";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.013;
-            fanout_load : 0.013;
-        }
-        pin(i3) {
-            direction   : input;
-            capacitance : 0.013;
-            fanout_load : 0.013;
-        }
-        pin(i4) {
-            direction   : input;
-            capacitance : 0.013;
-            fanout_load : 0.013;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.055;
-            function : "((i0'+i1')*((i2'*i3')+i4'))";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.348;
-                intrinsic_fall  : 0.422;
-                rise_resistance : 5.260;
-                fall_resistance : 3.210;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.440;
-                intrinsic_fall  : 0.378;
-                rise_resistance : 5.260;
-                fall_resistance : 3.210;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.186;
-                intrinsic_fall  : 0.473;
-                rise_resistance : 5.260;
-                fall_resistance : 3.210;
-                related_pin     : "i2";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.256;
-                intrinsic_fall  : 0.459;
-                rise_resistance : 5.260;
-                fall_resistance : 3.210;
-                related_pin     : "i3";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.240;
-                intrinsic_fall  : 0.309;
-                rise_resistance : 3.750;
-                fall_resistance : 3.210;
-                related_pin     : "i4";
-            }
-        }
-    }
-    cell (noa2ao222_x4) {
-        area : 4.0  /* pitchs */
-        cell_footprint : "noa2ao222";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(i3) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(i4) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "((i0'+i1')*((i2'*i3')+i4'))";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.684;
-                intrinsic_fall  : 0.801;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.780;
-                intrinsic_fall  : 0.758;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.638;
-                intrinsic_fall  : 0.809;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i2";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.732;
-                intrinsic_fall  : 0.795;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i3";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.718;
-                intrinsic_fall  : 0.664;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i4";
-            }
-        }
-    }
-    cell (noa2a2a23_x1) {
-        area : 3.3  /* pitchs */
-        cell_footprint : "noa2a2a23";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.013;
-            fanout_load : 0.013;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i3) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i4) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i5) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.062;
-            function : "((i0'+i1')*(i2'+i3')*(i4'+i5'))";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.525;
-                intrinsic_fall  : 0.425;
-                rise_resistance : 4.690;
-                fall_resistance : 2.850;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.643;
-                intrinsic_fall  : 0.388;
-                rise_resistance : 4.690;
-                fall_resistance : 2.850;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.307;
-                intrinsic_fall  : 0.479;
-                rise_resistance : 4.690;
-                fall_resistance : 2.850;
-                related_pin     : "i2";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.398;
-                intrinsic_fall  : 0.438;
-                rise_resistance : 4.690;
-                fall_resistance : 2.850;
-                related_pin     : "i3";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.250;
-                intrinsic_fall  : 0.416;
-                rise_resistance : 4.690;
-                fall_resistance : 2.850;
-                related_pin     : "i4";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.178;
-                intrinsic_fall  : 0.464;
-                rise_resistance : 4.690;
-                fall_resistance : 2.850;
-                related_pin     : "i5";
-            }
-        }
-    }
-    cell (noa2a2a23_x4) {
-        area : 4.3  /* pitchs */
-        cell_footprint : "noa2a2a23";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.013;
-            fanout_load : 0.013;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i3) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i4) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i5) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "((i0'+i1')*(i2'+i3')*(i4'+i5'))";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.834;
-                intrinsic_fall  : 0.814;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.955;
-                intrinsic_fall  : 0.778;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.620;
-                intrinsic_fall  : 0.873;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i2";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.716;
-                intrinsic_fall  : 0.833;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i3";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.574;
-                intrinsic_fall  : 0.819;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i4";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.496;
-                intrinsic_fall  : 0.865;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i5";
-            }
-        }
-    }
-    cell (noa3ao322_x1) {
-        area : 3.0  /* pitchs */
-        cell_footprint : "noa3ao322";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.013;
-            fanout_load : 0.013;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.013;
-            fanout_load : 0.013;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.013;
-            fanout_load : 0.013;
-        }
-        pin(i3) {
-            direction   : input;
-            capacitance : 0.013;
-            fanout_load : 0.013;
-        }
-        pin(i4) {
-            direction   : input;
-            capacitance : 0.013;
-            fanout_load : 0.013;
-        }
-        pin(i5) {
-            direction   : input;
-            capacitance : 0.013;
-            fanout_load : 0.013;
-        }
-        pin(i6) {
-            direction   : input;
-            capacitance : 0.013;
-            fanout_load : 0.013;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.043;
-            function : "((i0'+i1'+i2')*(((i3'*i4')*i5')+i6'))";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.396;
-                intrinsic_fall  : 0.616;
-                rise_resistance : 6.700;
-                fall_resistance : 3.370;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.486;
-                intrinsic_fall  : 0.552;
-                rise_resistance : 6.700;
-                fall_resistance : 3.370;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.546;
-                intrinsic_fall  : 0.488;
-                rise_resistance : 6.700;
-                fall_resistance : 3.370;
-                related_pin     : "i2";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.196;
-                intrinsic_fall  : 0.599;
-                rise_resistance : 6.700;
-                fall_resistance : 3.210;
-                related_pin     : "i3";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.264;
-                intrinsic_fall  : 0.608;
-                rise_resistance : 6.700;
-                fall_resistance : 3.210;
-                related_pin     : "i4";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.328;
-                intrinsic_fall  : 0.581;
-                rise_resistance : 6.700;
-                fall_resistance : 3.210;
-                related_pin     : "i5";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.246;
-                intrinsic_fall  : 0.311;
-                rise_resistance : 3.690;
-                fall_resistance : 3.210;
-                related_pin     : "i6";
-            }
-        }
-    }
-    cell (noa3ao322_x4) {
-        area : 4.3  /* pitchs */
-        cell_footprint : "noa3ao322";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.010;
-            fanout_load : 0.010;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(i3) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(i4) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(i5) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(i6) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "((i0'+i1'+i2')*(((i3'*i4')*i5')+i6'))";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.819;
-                intrinsic_fall  : 0.987;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.914;
-                intrinsic_fall  : 0.931;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.990;
-                intrinsic_fall  : 0.874;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i2";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.729;
-                intrinsic_fall  : 0.926;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i3";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.821;
-                intrinsic_fall  : 0.924;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i4";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.907;
-                intrinsic_fall  : 0.900;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i5";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.738;
-                intrinsic_fall  : 0.718;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i6";
-            }
-        }
-    }
-    cell (noa2a2a2a24_x1) {
-        area : 4.7  /* pitchs */
-        cell_footprint : "noa2a2a2a24";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.013;
-            fanout_load : 0.013;
-        }
-        pin(i3) {
-            direction   : input;
-            capacitance : 0.013;
-            fanout_load : 0.013;
-        }
-        pin(i4) {
-            direction   : input;
-            capacitance : 0.013;
-            fanout_load : 0.013;
-        }
-        pin(i5) {
-            direction   : input;
-            capacitance : 0.013;
-            fanout_load : 0.013;
-        }
-        pin(i6) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i7) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.047;
-            function : "((i0'+i1')*(i2'+i3')*(i4'+i5')*(i6'+i7'))";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.649;
-                intrinsic_fall  : 0.606;
-                rise_resistance : 6.190;
-                fall_resistance : 2.850;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.775;
-                intrinsic_fall  : 0.562;
-                rise_resistance : 6.190;
-                fall_resistance : 2.850;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.550;
-                intrinsic_fall  : 0.662;
-                rise_resistance : 6.190;
-                fall_resistance : 2.850;
-                related_pin     : "i2";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.667;
-                intrinsic_fall  : 0.616;
-                rise_resistance : 6.190;
-                fall_resistance : 2.850;
-                related_pin     : "i3";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.419;
-                intrinsic_fall  : 0.613;
-                rise_resistance : 6.190;
-                fall_resistance : 2.850;
-                related_pin     : "i4";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.329;
-                intrinsic_fall  : 0.662;
-                rise_resistance : 6.190;
-                fall_resistance : 2.850;
-                related_pin     : "i5";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.270;
-                intrinsic_fall  : 0.535;
-                rise_resistance : 6.190;
-                fall_resistance : 2.850;
-                related_pin     : "i6";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.200;
-                intrinsic_fall  : 0.591;
-                rise_resistance : 6.190;
-                fall_resistance : 2.850;
-                related_pin     : "i7";
-            }
-        }
-    }
-    cell (noa2a2a2a24_x4) {
-        area : 5.7  /* pitchs */
-        cell_footprint : "noa2a2a2a24";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i3) {
-            direction   : input;
-            capacitance : 0.013;
-            fanout_load : 0.013;
-        }
-        pin(i4) {
-            direction   : input;
-            capacitance : 0.013;
-            fanout_load : 0.013;
-        }
-        pin(i5) {
-            direction   : input;
-            capacitance : 0.013;
-            fanout_load : 0.013;
-        }
-        pin(i6) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i7) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "((i0'+i1')*(i2'+i3')*(i4'+i5')*(i6'+i7'))";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.966;
-                intrinsic_fall  : 1.049;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 1.097;
-                intrinsic_fall  : 1.005;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.867;
-                intrinsic_fall  : 1.106;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i2";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.990;
-                intrinsic_fall  : 1.061;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i3";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.748;
-                intrinsic_fall  : 1.061;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i4";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.649;
-                intrinsic_fall  : 1.109;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i5";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.606;
-                intrinsic_fall  : 0.999;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i6";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.525;
-                intrinsic_fall  : 1.052;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i7";
-            }
-        }
-    }
-    cell (buf_x2) {
-        area : 1.3  /* pitchs */
-        cell_footprint : "buf";
-        pin(i) {
-            direction   : input;
-            capacitance : 0.006;
-            fanout_load : 0.006;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.163;
-            function : "i";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.409;
-                intrinsic_fall  : 0.391;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i";
-            }
-        }
-    }
-    cell (buf_x4) {
-        area : 1.7  /* pitchs */
-        cell_footprint : "buf";
-        pin(i) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "i";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.379;
-                intrinsic_fall  : 0.409;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i";
-            }
-        }
-    }
-    cell (buf_x8) {
-        area : 2.7  /* pitchs */
-        cell_footprint : "buf";
-        pin(i) {
-            direction   : input;
-            capacitance : 0.015;
-            fanout_load : 0.015;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.647;
-            function : "i";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.343;
-                intrinsic_fall  : 0.396;
-                rise_resistance : 0.450;
-                fall_resistance : 0.400;
-                related_pin     : "i";
-            }
-        }
-    }
-    cell (a2_x2) {
-        area : 1.7  /* pitchs */
-        cell_footprint : "a2";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.163;
-            function : "(i0 * i1)";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.261;
-                intrinsic_fall  : 0.388;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.203;
-                intrinsic_fall  : 0.434;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i1";
-            }
-        }
-    }
-    cell (a2_x4) {
-        area : 2.0  /* pitchs */
-        cell_footprint : "a2";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "(i0 * i1)";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.338;
-                intrinsic_fall  : 0.476;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.269;
-                intrinsic_fall  : 0.518;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-        }
-    }
-    cell (o2_x2) {
-        area : 1.7  /* pitchs */
-        cell_footprint : "o2";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.010;
-            fanout_load : 0.010;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.010;
-            fanout_load : 0.010;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.163;
-            function : "(i0 + i1)";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.406;
-                intrinsic_fall  : 0.310;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.335;
-                intrinsic_fall  : 0.364;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i1";
-            }
-        }
-    }
-    cell (o2_x4) {
-        area : 2.0  /* pitchs */
-        cell_footprint : "o2";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.010;
-            fanout_load : 0.010;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.010;
-            fanout_load : 0.010;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "(i0 + i1)";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.491;
-                intrinsic_fall  : 0.394;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.427;
-                intrinsic_fall  : 0.464;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-        }
-    }
-    cell (a3_x2) {
-        area : 2.0  /* pitchs */
-        cell_footprint : "a3";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.010;
-            fanout_load : 0.010;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.010;
-            fanout_load : 0.010;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.010;
-            fanout_load : 0.010;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.163;
-            function : "(i0 * i1 * i2)";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.395;
-                intrinsic_fall  : 0.435;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.353;
-                intrinsic_fall  : 0.479;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.290;
-                intrinsic_fall  : 0.521;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i2";
-            }
-        }
-    }
-    cell (a3_x4) {
-        area : 2.3  /* pitchs */
-        cell_footprint : "a3";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.010;
-            fanout_load : 0.010;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "(i0 * i1 * i2)";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.478;
-                intrinsic_fall  : 0.514;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.428;
-                intrinsic_fall  : 0.554;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.356;
-                intrinsic_fall  : 0.592;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i2";
-            }
-        }
-    }
-    cell (ao22_x2) {
-        area : 2.0  /* pitchs */
-        cell_footprint : "ao22";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.163;
-            function : "((i0 + i1) * i2)";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.558;
-                intrinsic_fall  : 0.447;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.493;
-                intrinsic_fall  : 0.526;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.420;
-                intrinsic_fall  : 0.425;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i2";
-            }
-        }
-    }
-    cell (ao22_x4) {
-        area : 2.7  /* pitchs */
-        cell_footprint : "ao22";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "((i0 + i1) * i2)";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.674;
-                intrinsic_fall  : 0.552;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.615;
-                intrinsic_fall  : 0.647;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.526;
-                intrinsic_fall  : 0.505;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i2";
-            }
-        }
-    }
-    cell (mx2_x2) {
-        area : 3.0  /* pitchs */
-        cell_footprint : "mx2";
-        pin(cmd) {
-            direction   : input;
-            capacitance : 0.017;
-            fanout_load : 0.017;
-        }
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.163;
-            function : "(cmd' * i0)+(cmd * i1)";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.484;
-                intrinsic_fall  : 0.522;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "cmd";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.451;
-                intrinsic_fall  : 0.469;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.451;
-                intrinsic_fall  : 0.469;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i1";
-            }
-        }
-    }
-    cell (mx2_x4) {
-        area : 3.3  /* pitchs */
-        cell_footprint : "mx2";
-        pin(cmd) {
-            direction   : input;
-            capacitance : 0.017;
-            fanout_load : 0.017;
-        }
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "(cmd' * i0)+(cmd * i1)";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.615;
-                intrinsic_fall  : 0.647;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "cmd";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.564;
-                intrinsic_fall  : 0.576;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.564;
-                intrinsic_fall  : 0.576;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-        }
-    }
-    cell (o3_x2) {
-        area : 2.0  /* pitchs */
-        cell_footprint : "o3";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.010;
-            fanout_load : 0.010;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.010;
-            fanout_load : 0.010;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.163;
-            function : "(i0 + i1 + i2)";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.494;
-                intrinsic_fall  : 0.407;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.430;
-                intrinsic_fall  : 0.482;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.360;
-                intrinsic_fall  : 0.506;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i2";
-            }
-        }
-    }
-    cell (o3_x4) {
-        area : 2.3  /* pitchs */
-        cell_footprint : "o3";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.010;
-            fanout_load : 0.010;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.010;
-            fanout_load : 0.010;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "(i0 + i1 + i2)";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.569;
-                intrinsic_fall  : 0.501;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.510;
-                intrinsic_fall  : 0.585;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.447;
-                intrinsic_fall  : 0.622;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i2";
-            }
-        }
-    }
-    cell (oa22_x2) {
-        area : 2.0  /* pitchs */
-        cell_footprint : "oa22";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.163;
-            function : "((i0 * i1) + i2)";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.390;
-                intrinsic_fall  : 0.555;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.488;
-                intrinsic_fall  : 0.525;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.438;
-                intrinsic_fall  : 0.454;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i2";
-            }
-        }
-    }
-    cell (oa22_x4) {
-        area : 2.7  /* pitchs */
-        cell_footprint : "oa22";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "((i0 * i1) + i2)";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.511;
-                intrinsic_fall  : 0.677;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.615;
-                intrinsic_fall  : 0.650;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.523;
-                intrinsic_fall  : 0.571;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i2";
-            }
-        }
-    }
-    cell (a4_x2) {
-        area : 2.3  /* pitchs */
-        cell_footprint : "a4";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.010;
-            fanout_load : 0.010;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.010;
-            fanout_load : 0.010;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(i3) {
-            direction   : input;
-            capacitance : 0.010;
-            fanout_load : 0.010;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.163;
-            function : "(i0 * i1 * i2 * i3)";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.374;
-                intrinsic_fall  : 0.578;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.441;
-                intrinsic_fall  : 0.539;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.482;
-                intrinsic_fall  : 0.498;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i2";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.506;
-                intrinsic_fall  : 0.455;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i3";
-            }
-        }
-    }
-    cell (a4_x4) {
-        area : 2.7  /* pitchs */
-        cell_footprint : "a4";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.010;
-            fanout_load : 0.010;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.010;
-            fanout_load : 0.010;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(i3) {
-            direction   : input;
-            capacitance : 0.010;
-            fanout_load : 0.010;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "(i0 * i1 * i2 * i3)";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.505;
-                intrinsic_fall  : 0.650;
-                rise_resistance : 0.890;
-                fall_resistance : 0.540;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.578;
-                intrinsic_fall  : 0.614;
-                rise_resistance : 0.890;
-                fall_resistance : 0.540;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.627;
-                intrinsic_fall  : 0.576;
-                rise_resistance : 0.890;
-                fall_resistance : 0.540;
-                related_pin     : "i2";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.661;
-                intrinsic_fall  : 0.538;
-                rise_resistance : 0.890;
-                fall_resistance : 0.540;
-                related_pin     : "i3";
-            }
-        }
-    }
-    cell (ao2o22_x2) {
-        area : 3.0  /* pitchs */
-        cell_footprint : "ao2o22";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i3) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.163;
-            function : "((i0 + i1) * (i2 + i3))";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.572;
-                intrinsic_fall  : 0.451;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.508;
-                intrinsic_fall  : 0.542;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.432;
-                intrinsic_fall  : 0.627;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i2";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.488;
-                intrinsic_fall  : 0.526;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i3";
-            }
-        }
-    }
-    cell (ao2o22_x4) {
-        area : 3.3  /* pitchs */
-        cell_footprint : "ao2o22";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i3) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "((i0 + i1) * (i2 + i3))";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.696;
-                intrinsic_fall  : 0.569;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.637;
-                intrinsic_fall  : 0.666;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.554;
-                intrinsic_fall  : 0.744;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i2";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.606;
-                intrinsic_fall  : 0.639;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i3";
-            }
-        }
-    }
-    cell (o4_x2) {
-        area : 2.3  /* pitchs */
-        cell_footprint : "o4";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.010;
-            fanout_load : 0.010;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.010;
-            fanout_load : 0.010;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.010;
-            fanout_load : 0.010;
-        }
-        pin(i3) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.163;
-            function : "(i0 + i1 + i2 + i3)";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.508;
-                intrinsic_fall  : 0.601;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.446;
-                intrinsic_fall  : 0.631;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.567;
-                intrinsic_fall  : 0.531;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i2";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.378;
-                intrinsic_fall  : 0.626;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i3";
-            }
-        }
-    }
-    cell (o4_x4) {
-        area : 2.7  /* pitchs */
-        cell_footprint : "o4";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.012;
-            fanout_load : 0.012;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.012;
-            fanout_load : 0.012;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.012;
-            fanout_load : 0.012;
-        }
-        pin(i3) {
-            direction   : input;
-            capacitance : 0.012;
-            fanout_load : 0.012;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "(i0 + i1 + i2 + i3)";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.574;
-                intrinsic_fall  : 0.638;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.492;
-                intrinsic_fall  : 0.650;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.649;
-                intrinsic_fall  : 0.611;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i2";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.721;
-                intrinsic_fall  : 0.536;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i3";
-            }
-        }
-    }
-    cell (oa2a22_x2) {
-        area : 3.0  /* pitchs */
-        cell_footprint : "oa2a22";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i3) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.163;
-            function : "((i0 * i1) + (i2 * i3))";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.403;
-                intrinsic_fall  : 0.564;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.495;
-                intrinsic_fall  : 0.534;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.646;
-                intrinsic_fall  : 0.487;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i2";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.537;
-                intrinsic_fall  : 0.512;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i3";
-            }
-        }
-    }
-    cell (oa2a22_x4) {
-        area : 3.3  /* pitchs */
-        cell_footprint : "oa2a22";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i3) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "((i0 * i1) + (i2 * i3))";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.519;
-                intrinsic_fall  : 0.696;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.624;
-                intrinsic_fall  : 0.669;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.763;
-                intrinsic_fall  : 0.596;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i2";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.644;
-                intrinsic_fall  : 0.619;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i3";
-            }
-        }
-    }
-    cell (mx3_x2) {
-        area : 4.3  /* pitchs */
-        cell_footprint : "mx3";
-        pin(cmd0) {
-            direction   : input;
-            capacitance : 0.015;
-            fanout_load : 0.015;
-        }
-        pin(cmd1) {
-            direction   : input;
-            capacitance : 0.015;
-            fanout_load : 0.015;
-        }
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.163;
-            function : "(cmd0'*i0)+(cmd0*((cmd1*i1)+(cmd1'*i2)))";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.573;
-                intrinsic_fall  : 0.680;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "cmd0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.664;
-                intrinsic_fall  : 0.817;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "cmd1";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.538;
-                intrinsic_fall  : 0.658;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.654;
-                intrinsic_fall  : 0.808;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.654;
-                intrinsic_fall  : 0.808;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i2";
-            }
-        }
-    }
-    cell (mx3_x4) {
-        area : 4.7  /* pitchs */
-        cell_footprint : "mx3";
-        pin(cmd0) {
-            direction   : input;
-            capacitance : 0.015;
-            fanout_load : 0.015;
-        }
-        pin(cmd1) {
-            direction   : input;
-            capacitance : 0.015;
-            fanout_load : 0.015;
-        }
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "(cmd0'*i0)+(cmd0*((cmd1*i1)+(cmd1'*i2)))";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.683;
-                intrinsic_fall  : 0.779;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "cmd0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.792;
-                intrinsic_fall  : 0.967;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "cmd1";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.640;
-                intrinsic_fall  : 0.774;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.770;
-                intrinsic_fall  : 0.948;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.770;
-                intrinsic_fall  : 0.948;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i2";
-            }
-        }
-    }
-    cell (oa2ao222_x2) {
-        area : 3.3  /* pitchs */
-        cell_footprint : "oa2ao222";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(i3) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(i4) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.163;
-            function : "(i0*i1)+(i4*(i2+i3))";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.495;
-                intrinsic_fall  : 0.581;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.598;
-                intrinsic_fall  : 0.539;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.464;
-                intrinsic_fall  : 0.604;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i2";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.556;
-                intrinsic_fall  : 0.578;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i3";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.558;
-                intrinsic_fall  : 0.453;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i4";
-            }
-        }
-    }
-    cell (oa2ao222_x4) {
-        area : 3.7  /* pitchs */
-        cell_footprint : "oa2ao222";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(i3) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(i4) {
-            direction   : input;
-            capacitance : 0.011;
-            fanout_load : 0.011;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "(i0*i1)+(i4*(i2+i3))";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.553;
-                intrinsic_fall  : 0.657;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.662;
-                intrinsic_fall  : 0.616;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.552;
-                intrinsic_fall  : 0.693;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i2";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.640;
-                intrinsic_fall  : 0.660;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i3";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.656;
-                intrinsic_fall  : 0.529;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i4";
-            }
-        }
-    }
-    cell (oa2a2a23_x2) {
-        area : 4.0  /* pitchs */
-        cell_footprint : "oa2a2a23";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.013;
-            fanout_load : 0.013;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i3) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i4) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i5) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.163;
-            function : "((i0*i1)+(i2*i3))+(i4*i5)";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.653;
-                intrinsic_fall  : 0.578;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.775;
-                intrinsic_fall  : 0.542;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.441;
-                intrinsic_fall  : 0.639;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i2";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.540;
-                intrinsic_fall  : 0.600;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i3";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.402;
-                intrinsic_fall  : 0.591;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i4";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.321;
-                intrinsic_fall  : 0.636;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i5";
-            }
-        }
-    }
-    cell (oa2a2a23_x4) {
-        area : 4.3  /* pitchs */
-        cell_footprint : "oa2a2a23";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.013;
-            fanout_load : 0.013;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i3) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i4) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i5) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "((i0*i1)+(i2*i3))+(i4*i5)";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.699;
-                intrinsic_fall  : 0.648;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.822;
-                intrinsic_fall  : 0.613;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.493;
-                intrinsic_fall  : 0.715;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i2";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.594;
-                intrinsic_fall  : 0.677;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i3";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.464;
-                intrinsic_fall  : 0.673;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i4";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.379;
-                intrinsic_fall  : 0.714;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i5";
-            }
-        }
-    }
-    cell (oa3ao322_x2) {
-        area : 3.7  /* pitchs */
-        cell_footprint : "oa3ao322";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.010;
-            fanout_load : 0.010;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(i3) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(i4) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(i5) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(i6) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.163;
-            function : "(i0*i1*i2)+(i6*((i3+i4)+i5))";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.638;
-                intrinsic_fall  : 0.820;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.735;
-                intrinsic_fall  : 0.764;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.806;
-                intrinsic_fall  : 0.707;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i2";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.560;
-                intrinsic_fall  : 0.765;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i3";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.649;
-                intrinsic_fall  : 0.760;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i4";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.734;
-                intrinsic_fall  : 0.734;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i5";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.563;
-                intrinsic_fall  : 0.540;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i6";
-            }
-        }
-    }
-    cell (oa3ao322_x4) {
-        area : 4.0  /* pitchs */
-        cell_footprint : "oa3ao322";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.010;
-            fanout_load : 0.010;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(i3) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(i4) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(i5) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(i6) {
-            direction   : input;
-            capacitance : 0.009;
-            fanout_load : 0.009;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "(i0*i1*i2)+(i6*((i3+i4)+i5))";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.717;
-                intrinsic_fall  : 0.946;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.818;
-                intrinsic_fall  : 0.890;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.894;
-                intrinsic_fall  : 0.834;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i2";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.673;
-                intrinsic_fall  : 0.898;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i3";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.758;
-                intrinsic_fall  : 0.896;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i4";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.839;
-                intrinsic_fall  : 0.865;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i5";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.684;
-                intrinsic_fall  : 0.651;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i6";
-            }
-        }
-    }
-    cell (oa2a2a2a24_x2) {
-        area : 5.0  /* pitchs */
-        cell_footprint : "oa2a2a2a24";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.013;
-            fanout_load : 0.013;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i3) {
-            direction   : input;
-            capacitance : 0.013;
-            fanout_load : 0.013;
-        }
-        pin(i4) {
-            direction   : input;
-            capacitance : 0.013;
-            fanout_load : 0.013;
-        }
-        pin(i5) {
-            direction   : input;
-            capacitance : 0.013;
-            fanout_load : 0.013;
-        }
-        pin(i6) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i7) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.163;
-            function : "(i0*i1)+(i2*i3)+(i4*i5)+(i6*i7)";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.780;
-                intrinsic_fall  : 0.797;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.909;
-                intrinsic_fall  : 0.753;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.682;
-                intrinsic_fall  : 0.856;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i2";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.803;
-                intrinsic_fall  : 0.810;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i3";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.565;
-                intrinsic_fall  : 0.813;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i4";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.467;
-                intrinsic_fall  : 0.861;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i5";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.426;
-                intrinsic_fall  : 0.748;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i6";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.346;
-                intrinsic_fall  : 0.800;
-                rise_resistance : 1.790;
-                fall_resistance : 1.620;
-                related_pin     : "i7";
-            }
-        }
-    }
-    cell (oa2a2a2a24_x4) {
-        area : 5.3  /* pitchs */
-        cell_footprint : "oa2a2a2a24";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.013;
-            fanout_load : 0.013;
-        }
-        pin(i2) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i3) {
-            direction   : input;
-            capacitance : 0.013;
-            fanout_load : 0.013;
-        }
-        pin(i4) {
-            direction   : input;
-            capacitance : 0.013;
-            fanout_load : 0.013;
-        }
-        pin(i5) {
-            direction   : input;
-            capacitance : 0.013;
-            fanout_load : 0.013;
-        }
-        pin(i6) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(i7) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "(i0*i1)+(i2*i3)+(i4*i5)+(i6*i7)";
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.823;
-                intrinsic_fall  : 0.879;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.955;
-                intrinsic_fall  : 0.835;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.726;
-                intrinsic_fall  : 0.940;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i2";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.851;
-                intrinsic_fall  : 0.895;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i3";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.619;
-                intrinsic_fall  : 0.902;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i4";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.515;
-                intrinsic_fall  : 0.949;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i5";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.487;
-                intrinsic_fall  : 0.845;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i6";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.399;
-                intrinsic_fall  : 0.895;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i7";
-            }
-        }
-    }
-    cell (nxr2_x1) {
-        area : 3.0  /* pitchs */
-        cell_footprint : "nxr2";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.021;
-            fanout_load : 0.021;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.022;
-            fanout_load : 0.022;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.091;
-            function : "(i0' ^ i1)";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.288;
-                intrinsic_fall  : 0.293;
-                rise_resistance : 3.210;
-                fall_resistance : 2.850;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.156;
-                intrinsic_fall  : 0.327;
-                rise_resistance : 3.210;
-                fall_resistance : 2.850;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.366;
-                intrinsic_fall  : 0.389;
-                rise_resistance : 3.210;
-                fall_resistance : 2.850;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.395;
-                intrinsic_fall  : 0.503;
-                rise_resistance : 3.210;
-                fall_resistance : 2.850;
-                related_pin     : "i1";
-            }
-        }
-    }
-    cell (nxr2_x4) {
-        area : 4.0  /* pitchs */
-        cell_footprint : "nxr2";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.020;
-            fanout_load : 0.020;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.021;
-            fanout_load : 0.021;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "(i0' ^ i1)";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.522;
-                intrinsic_fall  : 0.553;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.553;
-                intrinsic_fall  : 0.542;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.469;
-                intrinsic_fall  : 0.481;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.568;
-                intrinsic_fall  : 0.453;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-        }
-    }
-    cell (xr2_x1) {
-        area : 3.0  /* pitchs */
-        cell_footprint : "xr2";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.021;
-            fanout_load : 0.021;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.022;
-            fanout_load : 0.022;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.091;
-            function : "(i0 ^ i1)";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.292;
-                intrinsic_fall  : 0.293;
-                rise_resistance : 3.210;
-                fall_resistance : 2.850;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.377;
-                intrinsic_fall  : 0.261;
-                rise_resistance : 3.210;
-                fall_resistance : 2.850;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.366;
-                intrinsic_fall  : 0.389;
-                rise_resistance : 3.210;
-                fall_resistance : 2.850;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.405;
-                intrinsic_fall  : 0.388;
-                rise_resistance : 3.210;
-                fall_resistance : 2.850;
-                related_pin     : "i1";
-            }
-        }
-    }
-    cell (xr2_x4) {
-        area : 4.0  /* pitchs */
-        cell_footprint : "xr2";
-        pin(i0) {
-            direction   : input;
-            capacitance : 0.020;
-            fanout_load : 0.020;
-        }
-        pin(i1) {
-            direction   : input;
-            capacitance : 0.021;
-            fanout_load : 0.021;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "(i0 ^ i1)";
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.521;
-                intrinsic_fall  : 0.560;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.541;
-                intrinsic_fall  : 0.657;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.476;
-                intrinsic_fall  : 0.480;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i0";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.357;
-                intrinsic_fall  : 0.539;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i1";
-            }
-        }
-    }
-    /* --------------------------------------------- */
-    /* combinationnal cells part 2: Three-State      */
-    /* --------------------------------------------- */
-
-    cell (nts_x1) {
-        area : 2.0  /* pitchs */
-        cell_footprint : "nts";
-        pin(i) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(cmd) {
-            direction   : input;
-            capacitance : 0.014;
-            fanout_load : 0.014;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.091;
-            function : "i'";
-            three_state : "cmd'";
-            timing() {
-                intrinsic_rise  : 0.249;
-                intrinsic_fall  : 0.041;
-                rise_resistance : 3.210;
-                fall_resistance : 2.850;
-                related_pin     : "cmd";
-            }
-            timing() {
-                timing_type     : three_state_disable;
-                intrinsic_rise  : 0.249;
-                intrinsic_fall  : 0.041;
-                rise_resistance : 3.210;
-                fall_resistance : 2.850;
-                related_pin     : "cmd";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.169;
-                intrinsic_fall  : 0.201;
-                rise_resistance : 3.210;
-                fall_resistance : 2.850;
-                related_pin     : "i";
-            }
-        }
-    }
-    cell (nts_x2) {
-        area : 2.7  /* pitchs */
-        cell_footprint : "nts";
-        pin(i) {
-            direction   : input;
-            capacitance : 0.028;
-            fanout_load : 0.028;
-        }
-        pin(cmd) {
-            direction   : input;
-            capacitance : 0.018;
-            fanout_load : 0.018;
-        }
-        pin(nq) {
-            direction  : output;
-            max_fanout : 0.182;
-            function : "i'";
-            three_state : "cmd'";
-            timing() {
-                intrinsic_rise  : 0.330;
-                intrinsic_fall  : 0.033;
-                rise_resistance : 1.600;
-                fall_resistance : 1.430;
-                related_pin     : "cmd";
-            }
-            timing() {
-                timing_type     : three_state_disable;
-                intrinsic_rise  : 0.330;
-                intrinsic_fall  : 0.033;
-                rise_resistance : 1.600;
-                fall_resistance : 1.430;
-                related_pin     : "cmd";
-            }
-            timing() {
-                timing_sense    : negative_unate;
-                intrinsic_rise  : 0.167;
-                intrinsic_fall  : 0.201;
-                rise_resistance : 1.600;
-                fall_resistance : 1.430;
-                related_pin     : "i";
-            }
-        }
-    }
-    cell (ts_x4) {
-        area : 3.3  /* pitchs */
-        cell_footprint : "ts";
-        pin(i) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(cmd) {
-            direction   : input;
-            capacitance : 0.019;
-            fanout_load : 0.019;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "i";
-            three_state : "cmd'";
-            timing() {
-                intrinsic_rise  : 0.492;
-                intrinsic_fall  : 0.409;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "cmd";
-            }
-            timing() {
-                timing_type     : three_state_disable;
-                intrinsic_rise  : 0.492;
-                intrinsic_fall  : 0.409;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "cmd";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.475;
-                intrinsic_fall  : 0.444;
-                rise_resistance : 0.890;
-                fall_resistance : 0.810;
-                related_pin     : "i";
-            }
-        }
-    }
-    cell (ts_x8) {
-        area : 4.3  /* pitchs */
-        cell_footprint : "ts";
-        pin(i) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        pin(cmd) {
-            direction   : input;
-            capacitance : 0.019;
-            fanout_load : 0.019;
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.647;
-            function : "i";
-            three_state : "cmd'";
-            timing() {
-                intrinsic_rise  : 0.626;
-                intrinsic_fall  : 0.466;
-                rise_resistance : 0.450;
-                fall_resistance : 0.400;
-                related_pin     : "cmd";
-            }
-            timing() {
-                timing_type     : three_state_disable;
-                intrinsic_rise  : 0.626;
-                intrinsic_fall  : 0.466;
-                rise_resistance : 0.450;
-                fall_resistance : 0.400;
-                related_pin     : "cmd";
-            }
-            timing() {
-                timing_sense    : positive_unate;
-                intrinsic_rise  : 0.613;
-                intrinsic_fall  : 0.569;
-                rise_resistance : 0.450;
-                fall_resistance : 0.400;
-                related_pin     : "i";
-            }
-        }
-    }
-
-
-    /* --------------------------------------------- */
-    /* Pull-Up, Pull-Down Cells                      */
-    /* --------------------------------------------- */
-
-    cell (one_x0) {
-        area : 1.0  /* pitchs */
-        cell_footprint : "one";
-        pin(q) {
-            direction : output ;
-            max_fanout : 7.82796;
-            function  : "1";
-            driver_type : pull_up ;
-        }
-    }
-
-    cell (zero_x0) {
-        area : 1.0  /* pitchs */
-        cell_footprint : "zero";
-        pin(nq) {
-            direction : output ;
-            max_fanout : 7.82796;
-            function  : "0";
-            driver_type : pull_down ;
-        }
-    }
-
-    /* --------------------------------------------- */
-    /* Sequential cells part 1 : Flip-Flops          */
-    /* --------------------------------------------- */
-
-    cell (sff1_x4) {
-        area : 6.0  /* pitchs */
-        cell_footprint : "sff1";
-        pin(i) {
-            direction : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-            timing() {
-                timing_type : setup_rising;
-                intrinsic_rise : 0.476;
-                intrinsic_fall : 0.585;
-                related_pin : "ck";
-            }
-            timing() {
-                timing_type : hold_rising;
-                intrinsic_rise : 0.000;
-                intrinsic_fall : 0.000;
-                related_pin : "ck";
-            }
-        }
-        pin(ck) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        ff("IQ","IQN") {
-            next_state : "i";
-            clocked_on : "ck";
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "IQ";
-            timing() {
-                timing_type : rising_edge;
-                intrinsic_rise : 0.500;
-                intrinsic_fall : 0.500;
-                rise_resistance : 0.890;
-                fall_resistance : 0.890;
-                related_pin : "ck";
-            }
-        }
-    }
-    cell (sff2_x4) {
-        area : 8.0  /* pitchs */
-        cell_footprint : "sff2";
-        dont_use : false;
-        pin(i0) {
-            direction : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-            timing() {
-                timing_type : setup_rising;
-                intrinsic_rise : 0.666;
-                intrinsic_fall : 0.764;
-                related_pin : "ck";
-            }
-            timing() {
-                timing_type : hold_rising;
-                intrinsic_rise : 0.000;
-                intrinsic_fall : 0.000;
-                related_pin : "ck";
-            }
-        }
-        pin(i1) {
-            direction : input;
-            capacitance : 0.007;
-            fanout_load : 0.007;
-            timing() {
-                timing_type : setup_rising;
-                intrinsic_rise : 0.666;
-                intrinsic_fall : 0.764;
-                related_pin : "ck";
-            }
-            timing() {
-                timing_type : hold_rising;
-                intrinsic_rise : 0.000;
-                intrinsic_fall : 0.000;
-                related_pin : "ck";
-            }
-        }
-        pin(cmd) {
-            direction : input;
-            capacitance : 0.016;
-            fanout_load : 0.016;
-            timing() {
-                timing_type : setup_rising;
-                intrinsic_rise : 0.770;
-                intrinsic_fall : 0.833;
-                related_pin : "ck";
-            }
-            timing() {
-                timing_type : hold_rising;
-                intrinsic_rise : 0.000;
-                intrinsic_fall : 0.000;
-                related_pin : "ck";
-            }
-        }
-        pin(ck) {
-            direction   : input;
-            capacitance : 0.008;
-            fanout_load : 0.008;
-        }
-        ff("IQ","IQN") {
-            next_state : "(cmd * i1) + (cmd' * i0)";
-            clocked_on : "ck";
-        }
-        pin(q) {
-            direction  : output;
-            max_fanout : 0.327;
-            function : "IQ";
-            timing() {
-                timing_type : rising_edge;
-                intrinsic_rise : 0.500;
-                intrinsic_fall : 0.500;
-                rise_resistance : 0.890;
-                fall_resistance : 0.890;
-                related_pin : "ck";
-            }
-        }
-        test_cell() {
-        ff("IQ","IQN") {
-            next_state : "i0";
-            clocked_on : "ck";
-        }
-            pin(i0,ck) {
-                direction   : input;
-            }
-            pin(i1) {
-                direction   : input;
-                signal_type : test_scan_in;
-            }
-            pin(cmd) {
-                direction   : input;
-                signal_type : test_scan_enable;
-            }
-            pin(q) {
-                direction   : output;
-                function    : "IQ";
-                signal_type : test_scan_out;
-            }
-        }
-    }
-}
diff --git a/alliance/share/cells/sxlib/sxlib.sdb b/alliance/share/cells/sxlib/sxlib.sdb
deleted file mode 100644
index 86798ed2..00000000
Binary files a/alliance/share/cells/sxlib/sxlib.sdb and /dev/null differ
diff --git a/alliance/share/cells/sxlib/sxlib.slib b/alliance/share/cells/sxlib/sxlib.slib
deleted file mode 100644
index 6f4d0f4a..00000000
--- a/alliance/share/cells/sxlib/sxlib.slib
+++ /dev/null
@@ -1,472 +0,0 @@
-/******************************************************************************
- **
- **	FILE NAME: sclib.slib
- **
- **	Created by Mokhtar HIRECH (MASI laboratory) on 26 October 1995
- ** from $SYNOPSYS/libraries/syn/class.slib
- **
- ** Modified September 1, 1999 Franck
- **
- *****************************************************************************
-*/
-
-
-TRUE = 1;
-FALSE = 0;
-
-
-library("sxlib.sdb") {
-
-  ROUTE_GRID = 1024;
-  INCHES_PER_GRID = .1;
-  DB_PER_GRID = ROUTE_GRID;
-
-  CENTEMETERS_PER_GRID = INCHES_PER_GRID * 2.54;
-  METERS_PER_GRID = CENTEMETERS_PER_GRID / 100;
-  METERS_PER_DB = METERS_PER_GRID / DB_PER_GRID;
-
-  set_route_grid(ROUTE_GRID);
-  set_external_scale(METERS_PER_DB);
-  set_meter_scale(METERS_PER_DB);
-
-  grid_pins : TRUE ;
-
-
-
-  /* note: One ROUTE_GRID is equivalent to 13 / 2 "units" of the IEEE / ANSI symbol
-   * standard (Std 91 - 1984).  One ROUTE_GRID is equivalent to .2 MIL standard
-   * units (inches) (MIL - STD - 8086)
-   * Dimensions were derrived from these standards.
-   *
-   *        -          ***************************
-   *        |          *                          ****
-   *       	|          ***            -               **
-   *       	|          *  ****        |                 *
-   *        |    *******     ***     DYNAMIC HEIGHT      *  **** --------
-   *                   *  ****        |                  * *    *       |
-   *    AND_HEIGHT     ***            -                   **    * BUBBLE_DIAMETER
-   *                   *                                  **    *       |
-   *        |          <------->                         *. **** --------
-   *        |          *    DYNAMIC WIDTH                *.
-   *        |    *******                                * .
-   *        |          *                              **  .
-   *        |          *                           ***    .
-   *        -          ***************************        .
-   *                   .                                  .
-   *                   .                                  .
-   *                   .                                  .
-   *                   <-------------- AND_WIDTH --------->
-   *
-   *
-   *
-   *       	     XOR_GAP
-   *       	   <------->
-   *    	   .       .
-   *           .       .
-   *           .       .
-   *           .       .
-   *           *       ***********************                            -
-   *            *       *                  	  ********                    |
-   *             *       *                            ****                |
-   *              *       *                               **              |
-   *               *       *                               	**            |
-   *               *       *                               	  *
-   *  -.............*.......*..........+                	   *       OR_HEIGHT
-   *  |             *       *                           	   *
-   *  |            *       *.          .                      *.          |
-   * OR_Y_ORIGIN   *       *.      	   .                	** .          |
-   *  |           *       * .          .                  **   .          |
-   *  |          *       *  .          .              ****     .          |
-   *  |         *       *   .          .      ********         .          |
-   *  -........*.......***********************     		   .          -
-   *		        .          .
-   *                   <- OR_X_ORIGIN ->                       .
-   *                        .                                  .
-   *                        .                                  .
-   *                        <---------- OR_WIDTH -------------->
-   *
-   *
-   *
-   * NOTE:
-   *
-   * Both OR_HEIGHT and AND_HEIGHT are defined to be four.
-   * The rest of the parameters are under "user" control.
-   *
-   * The radius of the arcs in an OR gate are defined to be equal to the
-   * height of the OR gate (this seems to be an industry standard).  Thus,
-   * The radius of all three arcs are defined to be four.
-   *
-   * Both the MIL standard and the ANSI / IEEE standard have slightly different
-   * ideas on these dimensions, so choose the dimensions you like best:
-   *
-   */
-
-/* REQUIRED SIZES: */
-
-AND_HEIGHT = 4;
-OR_HEIGHT = 4;
-
-grid_pins : TRUE ;
-
-/* ANSI Dimensions: 
- * The ANSI dimensions have been commented out in favor of the MIL dimensions:
- *
- *   ANSI_AND_HEIGHT = 26.0;
- *   SCALE = AND_HEIGHT / ANSI_AND_HEIGHT;
- *
- *   AND_WIDTH = 32 * SCALE;
- *   OR_WIDTH = 32 * SCALE;
- *   INVERTER_HEIGHT = 22.5 * SCALE;
- *   XOR_GAP = 5 * SCALE;
- *   BUBBLE_DIAMETER = 4 * SCALE;
- *   DYNAMIC_HEIGHT = 4 * SCALE;
- *   DYNAMIC_WIDTH = 6 * SCALE;
- *   OFF_SHEET_HEIGHT = 8 * SCALE;   Not specified by ANSI,
- *			           this value from MIL
- *
- */
-
-
-/* MIL Dimensions: */
-
-GRIDS_PER_INCH = 1 / INCHES_PER_GRID;
-MIL_AND_HEIGHT = .8;
-SCALE = AND_HEIGHT / MIL_AND_HEIGHT;
-
-AND_WIDTH = 1.00 * SCALE;
-OR_WIDTH = 1.00 * SCALE;
-OR_INTERNAL_WIDTH = 0.50 * GRIDS_PER_INCH;
-INVERTER_HEIGHT = .70 * SCALE;
-XOR_GAP = (2.0 / 13.0) * SCALE;   /* Not specifed by MIL, this value from ANSI */
-BUBBLE_DIAMETER = .16 * SCALE;
-DYNAMIC_HEIGHT = .15 * SCALE;
-DYNAMIC_WIDTH = .30 * SCALE;
-OFF_SHEET_HEIGHT = .25 * SCALE;
-
-
-/* The following values are not specified by MIL or ANSI: */
-
-/* Origins are defined as offset from the lower left corner */
-OR_X_ORIGIN = 3;
-OR_Y_ORIGIN = 2;
-AND_X_ORIGIN = 3;
-AND_Y_ORIGIN = 2;
-INVERTER_X_ORIGIN = 1;
-INVERTER_Y_ORIGIN = INVERTER_HEIGHT / 2.0;
-
-EXTRA_WING_SPAN = .5; /* ON 3 + GATES, CONTROLS WING SIZE */
-GATE_GAP = 0;	       /* CONTROLS VERTICAL GAP ON STACKED GATES */
-
-/* The following values are deduced from the above values: */
-
-BUBBLE_RADIUS = BUBBLE_DIAMETER / 2.0;
-DYNAMIC_RADIUS = DYNAMIC_HEIGHT / 2.0;
-
-
-  symbol(and_outline) {
-    AND_LEFT_X = - AND_X_ORIGIN;
-    AND_BOTTOM_Y = - AND_Y_ORIGIN;
-
-    AND_TOP_Y = AND_BOTTOM_Y + AND_HEIGHT;
-    X_START_OF_ARC = AND_LEFT_X + AND_WIDTH - AND_HEIGHT / 2.0;
-    AND_MIDDLE_Y = AND_BOTTOM_Y + AND_HEIGHT / 2.0;
-    AND_RIGHT_X = AND_LEFT_X + AND_WIDTH;
-
-    line(AND_LEFT_X, AND_TOP_Y, X_START_OF_ARC, AND_TOP_Y);
-    line(AND_LEFT_X, AND_BOTTOM_Y, X_START_OF_ARC, AND_BOTTOM_Y);
-    arc(X_START_OF_ARC, AND_TOP_Y, X_START_OF_ARC, AND_BOTTOM_Y,       	      \
-	X_START_OF_ARC, AND_MIDDLE_Y);
-  }
-
-
-  symbol(inverter_triangle) {
-
-    /* The origins are defined to be the offset from the lower left corner */
-    INVERTER_LEFT_X = - INVERTER_X_ORIGIN;
-    INVERTER_BOTTOM_Y = - INVERTER_Y_ORIGIN;
-
-    INVERTER_RIGHT_X = INVERTER_LEFT_X + INVERTER_HEIGHT * SQRT(3) / 2.0;
-    INVERTER_TOP_Y = INVERTER_BOTTOM_Y + INVERTER_HEIGHT;
-    INVERTER_MIDDLE_Y = INVERTER_BOTTOM_Y + INVERTER_HEIGHT / 2.0;
-
-    line(INVERTER_LEFT_X, INVERTER_TOP_Y, INVERTER_RIGHT_X, INVERTER_MIDDLE_Y);
-    line(INVERTER_RIGHT_X, INVERTER_MIDDLE_Y,  	       	       	       	      \
-	 INVERTER_LEFT_X, INVERTER_BOTTOM_Y);
-    line(INVERTER_LEFT_X, INVERTER_BOTTOM_Y, INVERTER_LEFT_X, INVERTER_TOP_Y);
-  }
-
-  symbol(solder_dot) {
-    line( -.25,-.25,.25,-.25);
-    line(.25,.25,.25,-.25);
-    line(.25,.25,-.25,.25);
-    line( -.25,.25,-.25,-.25);
-    line( -.25,-.25,.25,.25);
-    line(.25,-.25,-.25,.25);
-  }
-
-/******************************************************************************
-**	
-**	New symbols added for SCLIB cells
-**
-******************************************************************************/
-
-  symbol(inv_x1) {
-    sub_symbol(inverter_triangle, 0,0,0);
-
-    circle(INVERTER_RIGHT_X + BUBBLE_RADIUS, INVERTER_MIDDLE_Y, BUBBLE_RADIUS);
-    pin(nq, INVERTER_RIGHT_X + BUBBLE_DIAMETER, INVERTER_MIDDLE_Y, RIGHT);
-    pin(i, INVERTER_LEFT_X, INVERTER_MIDDLE_Y, LEFT);
-  }
-
-  symbol(a2_x1) {
-    sub_symbol(and_outline, 0,0,0);
-
-    line(AND_LEFT_X, AND_BOTTOM_Y, AND_LEFT_X, AND_TOP_Y);
-
-    pin(i0, AND_LEFT_X, AND_BOTTOM_Y + 3, LEFT);
-    pin(i1, AND_LEFT_X, AND_BOTTOM_Y + 1, LEFT);
-    pin(q, AND_RIGHT_X, AND_MIDDLE_Y, RIGHT);
-  }
-
-  symbol(na2_x1) {
-    sub_symbol(and_outline, 0,0,0);
-
-    line(AND_LEFT_X, AND_BOTTOM_Y, AND_LEFT_X, AND_TOP_Y);
-    circle(AND_LEFT_X - BUBBLE_RADIUS, AND_BOTTOM_Y + 1, BUBBLE_RADIUS);
-
-    pin(i0, AND_LEFT_X, AND_BOTTOM_Y + 3, LEFT);
-    pin(i1, (AND_LEFT_X - BUBBLE_DIAMETER), AND_BOTTOM_Y + 1, LEFT);
-    pin(nq, AND_RIGHT_X, AND_MIDDLE_Y, RIGHT);
-  }
-
-  
-  OR_LEFT_X = - OR_X_ORIGIN;
-  OR_BOTTOM_Y = - OR_Y_ORIGIN;
-
-  OR_TOP_Y = OR_BOTTOM_Y + OR_HEIGHT;
-  OR_LEFT_ARC_CENTER_X = OR_LEFT_X - sqrt(.75 * OR_HEIGHT * OR_HEIGHT);
-  OR_MIDDLE_Y = OR_BOTTOM_Y + OR_HEIGHT / 2.0;
-  OR_RIGHT_X = OR_LEFT_ARC_CENTER_X + OR_HEIGHT + OR_INTERNAL_WIDTH;
-  OR_RIGHT_ARCS_X_START = OR_RIGHT_X - sqrt(.75 * OR_HEIGHT * OR_HEIGHT);
-/*
-  OR_WIDTH = OR_RIGHT_X - OR_LEFT_X;
-*/
-  symbol(left_side_of_or) {
-    arc(OR_LEFT_X,OR_TOP_Y,OR_LEFT_X, OR_BOTTOM_Y,                            \
-        OR_LEFT_ARC_CENTER_X, OR_MIDDLE_Y);
-  }
-
-
-  symbol(or_outline) {
-    sub_symbol(left_side_of_or, 0,0,0);
-
-
-    arc(OR_RIGHT_ARCS_X_START, OR_TOP_Y, OR_RIGHT_X, OR_MIDDLE_Y,             \
-        OR_RIGHT_ARCS_X_START, OR_BOTTOM_Y);
-    arc(OR_RIGHT_X, OR_MIDDLE_Y, OR_RIGHT_ARCS_X_START, OR_BOTTOM_Y,          \
-        OR_RIGHT_ARCS_X_START, OR_TOP_Y);
-
-    line(OR_LEFT_X, OR_TOP_Y, OR_RIGHT_ARCS_X_START, OR_TOP_Y);
-    line(OR_LEFT_X, OR_BOTTOM_Y, OR_RIGHT_ARCS_X_START, OR_BOTTOM_Y);
-  }
-
-  OR_EVEN_LEFT_PIN_X = OR_LEFT_ARC_CENTER_X + sqrt((15.0 / 16.0) *            \
-                                                   OR_HEIGHT * OR_HEIGHT);
-  OR_ODD_LEFT_PIN_X = OR_LEFT_ARC_CENTER_X + OR_HEIGHT;
-
-  symbol(o2_x1) {
-    sub_symbol(or_outline,0,0,0);
-
-    pin(i0, OR_EVEN_LEFT_PIN_X, OR_BOTTOM_Y + 3, LEFT);
-    pin(i1, OR_EVEN_LEFT_PIN_X, OR_BOTTOM_Y + 1, LEFT);
-    pin(q, OR_RIGHT_X, 0, RIGHT);
-  }
-
-  /* height assumed to be radius of or arc */
-  OR_NOT_CIRCLE_X = OR_LEFT_ARC_CENTER_X + sqrt(((OR_HEIGHT - BUBBLE_RADIUS) * \
-                                              (OR_HEIGHT - BUBBLE_RADIUS)) - 1);
-  symbol(no2_x1) {
-    sub_symbol(or_outline, 0,0,0);
-
-    circle(OR_NOT_CIRCLE_X, OR_BOTTOM_Y + 1, BUBBLE_RADIUS);
-
-    pin(i0, OR_EVEN_LEFT_PIN_X, OR_BOTTOM_Y + 3, LEFT);
-    pin(i1, OR_NOT_CIRCLE_X - BUBBLE_RADIUS, OR_BOTTOM_Y + 1, LEFT);
-    pin(nq, OR_RIGHT_X, 0, RIGHT);
-  }
-
-
-  symbol(B2I) {
-    LEFT_INVERTER_ORIGIN_X = - INVERTER_X_ORIGIN - 2;
-    sub_symbol(inverter_triangle, LEFT_INVERTER_ORIGIN_X,0,0);
-    circle(LEFT_INVERTER_ORIGIN_X + INVERTER_RIGHT_X + BUBBLE_RADIUS,  	      \
-             INVERTER_MIDDLE_Y, BUBBLE_RADIUS);
-
-    RIGHT_INVERTER_ORIGIN_X = INVERTER_X_ORIGIN + 2;
-    sub_symbol(inverter_triangle, RIGHT_INVERTER_ORIGIN_X,0,0);
-    circle(RIGHT_INVERTER_ORIGIN_X + INVERTER_RIGHT_X + BUBBLE_RADIUS, 	      \
-             INVERTER_MIDDLE_Y, BUBBLE_RADIUS);
-
-    line(LEFT_INVERTER_ORIGIN_X + INVERTER_RIGHT_X + BUBBLE_DIAMETER,  	      \
-         INVERTER_MIDDLE_Y,    	       	       	       	       	       	      \
-         RIGHT_INVERTER_ORIGIN_X + INVERTER_LEFT_X, INVERTER_MIDDLE_Y);
-    sub_symbol(solder_dot, INVERTER_X_ORIGIN,0,0);
-    line(INVERTER_X_ORIGIN, INVERTER_MIDDLE_Y, 	       	       	       	      \
-             INVERTER_X_ORIGIN, ceil(INVERTER_TOP_Y) + 1);
-    line(INVERTER_X_ORIGIN, ceil(INVERTER_TOP_Y) + 1,  	       	       	      \
-             RIGHT_INVERTER_ORIGIN_X + INVERTER_RIGHT_X + BUBBLE_DIAMETER,    \
-             ceil(INVERTER_TOP_Y) + 1);
-    pin(Z1, RIGHT_INVERTER_ORIGIN_X + INVERTER_RIGHT_X + BUBBLE_DIAMETER,     \
-             ceil(INVERTER_TOP_Y) + 1, RIGHT);
-    pin(Z2, RIGHT_INVERTER_ORIGIN_X + INVERTER_RIGHT_X + BUBBLE_DIAMETER,     \
-             INVERTER_MIDDLE_Y, RIGHT);
-    pin(A, LEFT_INVERTER_ORIGIN_X + INVERTER_LEFT_X, INVERTER_MIDDLE_Y, LEFT);
-  }
-  symbol(B2IP) {
-    sub_symbol(B2I, 0,0,0);
-  }
-  symbol(B3I) {
-    sub_symbol(B2I, 0,0,0);
-  }
-  symbol(B3IP) {
-    sub_symbol(B2I, 0,0,0);
-  }
-  symbol(mux2) {
-    MUX_WIDTH = 2.0;
-    MUX_X_ORIGIN = MUX_WIDTH / 2.0;
-    MUX_HEIGHT = 4.0;
-    MUX_Y_ORIGIN = MUX_HEIGHT / 2.0;
-
-    MUX_LEFT =   MUX_X_ORIGIN - (MUX_WIDTH / 2.0);
-    MUX_RIGHT =  MUX_X_ORIGIN + (MUX_WIDTH / 2.0);
-    MUX_TOP =    MUX_Y_ORIGIN + (MUX_HEIGHT / 2.0);
-    MUX_BOTTOM = MUX_Y_ORIGIN - (MUX_HEIGHT / 2.0);
-    line(MUX_LEFT, MUX_BOTTOM, MUX_RIGHT, MUX_BOTTOM);
-    line(MUX_LEFT, MUX_BOTTOM, MUX_LEFT, MUX_TOP);
-    line(MUX_RIGHT, MUX_TOP, MUX_RIGHT, MUX_BOTTOM);
-    line(MUX_RIGHT, MUX_TOP, MUX_LEFT, MUX_TOP);
-    pin(A,   MUX_LEFT,  MUX_Y_ORIGIN + 1, LEFT);
-    pin(B,   MUX_LEFT,  MUX_Y_ORIGIN - 1, LEFT);
-    pin(S,   MUX_X_ORIGIN, MUX_BOTTOM , DOWN);
-  }
-  symbol(MUX21H) {
-    sub_symbol(mux2, 0,0,0);
-    pin(Z,   MUX_RIGHT, MUX_Y_ORIGIN, RIGHT);
-  }
-  symbol(MUX21HP) {
-    sub_symbol(MUX21H, 0,0,0);
-  }
-  symbol(MUX21L) {
-    sub_symbol(mux2, 0,0,0);
-    pin(Z,   MUX_RIGHT + BUBBLE_DIAMETER, MUX_Y_ORIGIN, RIGHT);
-    circle(MUX_RIGHT + BUBBLE_RADIUS, MUX_Y_ORIGIN, BUBBLE_RADIUS);
-  }
-  symbol(MUX21LP) {
-    sub_symbol(MUX21L, 0,0,0);
-  }
-  symbol(mux2sel) {
-    MUX_WIDTH = 3.0;
-    MUX_X_ORIGIN = MUX_WIDTH / 2.0;
-    MUX_HEIGHT = 4.0;
-    MUX_Y_ORIGIN = MUX_HEIGHT / 2.0;
-
-    MUX_LEFT =   MUX_X_ORIGIN - (MUX_WIDTH / 2.0);
-    MUX_RIGHT =  MUX_X_ORIGIN + (MUX_WIDTH / 2.0);
-    MUX_TOP =    MUX_Y_ORIGIN + (MUX_HEIGHT / 2.0);
-    MUX_BOTTOM = MUX_Y_ORIGIN - (MUX_HEIGHT / 2.0);
-    line(MUX_LEFT, MUX_BOTTOM, MUX_RIGHT, MUX_BOTTOM);
-    line(MUX_LEFT, MUX_BOTTOM, MUX_LEFT, MUX_TOP);
-    line(MUX_RIGHT, MUX_TOP, MUX_RIGHT, MUX_BOTTOM);
-    line(MUX_RIGHT, MUX_TOP, MUX_LEFT, MUX_TOP);
-  }
-  symbol(MUX21LA) {
-    sub_symbol(mux2sel, 0,0,0);
-    pin(A,   MUX_LEFT,  MUX_Y_ORIGIN + 1, LEFT);
-    pin(B,   MUX_LEFT,  MUX_Y_ORIGIN - 1, LEFT);
-    pin(SN,  MUX_X_ORIGIN - 0.5, MUX_BOTTOM - BUBBLE_DIAMETER , DOWN);
-    circle(MUX_X_ORIGIN - 0.5, MUX_BOTTOM - BUBBLE_RADIUS, BUBBLE_RADIUS);
-    pin(S,   MUX_X_ORIGIN + 0.5, MUX_BOTTOM , DOWN);
-    circle(MUX_RIGHT + BUBBLE_RADIUS, MUX_Y_ORIGIN, BUBBLE_RADIUS);
-    pin(Z,   MUX_RIGHT + BUBBLE_DIAMETER, MUX_Y_ORIGIN, RIGHT);
-  }
-  symbol(MUX21LAP) {
-    sub_symbol(MUX21LA, 0,0,0);
-  }
-  symbol(MUX31L) {
-    sub_symbol(mux2sel, 0,0,0);
-    pin(D0,   MUX_LEFT,  MUX_Y_ORIGIN + 1, LEFT);
-    pin(D1,   MUX_LEFT,  MUX_Y_ORIGIN , LEFT);
-    pin(D2,   MUX_LEFT,  MUX_Y_ORIGIN - 1, LEFT);
-    pin(A,  MUX_X_ORIGIN - 0.5, MUX_BOTTOM , DOWN);
-    pin(B,   MUX_X_ORIGIN + 0.5, MUX_BOTTOM , DOWN);
-    circle(MUX_RIGHT + BUBBLE_RADIUS, MUX_Y_ORIGIN, BUBBLE_RADIUS);
-    pin(Z,   MUX_RIGHT + BUBBLE_DIAMETER, MUX_Y_ORIGIN, RIGHT);
-  }
-  symbol(MUX31LP) {
-    sub_symbol(MUX31L, 0,0,0);
-  }
-
-FFBOX_WIDTH = 6.0;
-FFBOX_X_ORIGIN = FFBOX_WIDTH / 2.0;
-FFBOX_HEIGHT = 10.0;
-FFBOX_Y_ORIGIN = FFBOX_HEIGHT / 2.0;
-
-FFBOX_LEFT =   FFBOX_X_ORIGIN - (FFBOX_WIDTH / 2.0);
-FFBOX_RIGHT =  FFBOX_X_ORIGIN + (FFBOX_WIDTH / 2.0);
-
-  symbol(ff_box) {
-    FFBOX_TOP =    FFBOX_Y_ORIGIN + (FFBOX_HEIGHT / 2.0);
-    FFBOX_BOTTOM = FFBOX_Y_ORIGIN - (FFBOX_HEIGHT / 2.0);
-    line(FFBOX_LEFT, FFBOX_BOTTOM, FFBOX_RIGHT, FFBOX_BOTTOM);
-    line(FFBOX_LEFT, FFBOX_BOTTOM, FFBOX_LEFT, FFBOX_TOP);
-    line(FFBOX_RIGHT, FFBOX_TOP, FFBOX_RIGHT, FFBOX_BOTTOM);
-    line(FFBOX_RIGHT, FFBOX_TOP, FFBOX_LEFT, FFBOX_TOP);
-    pin(Q,   FFBOX_RIGHT, FFBOX_Y_ORIGIN + 4 , RIGHT);
-    pin(QN,  FFBOX_RIGHT + BUBBLE_DIAMETER, FFBOX_Y_ORIGIN - 4 , RIGHT);
-    circle(FFBOX_RIGHT + BUBBLE_RADIUS, FFBOX_Y_ORIGIN - 4, BUBBLE_RADIUS);
-  }
-
-  symbol(FD1) {
-    sub_symbol(ff_box, 0,0,0);
-    pin(D,   FFBOX_LEFT,  FFBOX_Y_ORIGIN + 4,  LEFT);
-
-    CLOCK_Y = FFBOX_Y_ORIGIN - 4;
-    pin(CP, FFBOX_LEFT,  CLOCK_Y , LEFT);
-    line(FFBOX_LEFT, CLOCK_Y - 0.5, FFBOX_LEFT + 1, CLOCK_Y);
-    line(FFBOX_LEFT, CLOCK_Y + 0.5, FFBOX_LEFT + 1, CLOCK_Y);
-  }
-
-  symbol(FD1P) {
-    sub_symbol(FD1, 0,0,0);
-  }
-  symbol(FDW) {
-    sub_symbol(FD1, 0,0,0);
-    pin(CD,   FFBOX_X_ORIGIN,  FFBOX_BOTTOM - BUBBLE_DIAMETER,  DOWN);
-    circle(FFBOX_X_ORIGIN,FFBOX_BOTTOM - BUBBLE_RADIUS, BUBBLE_RADIUS);
-  }
-
-  symbol(FD4) {
-    sub_symbol(FD1, 0,0,0);
-    pin(SD,   FFBOX_X_ORIGIN,  FFBOX_TOP + BUBBLE_DIAMETER,  UP);
-    circle(FFBOX_X_ORIGIN,FFBOX_TOP + BUBBLE_RADIUS, BUBBLE_RADIUS);
-  }
-  symbol(box_3x6) {
-    BOX_3X6_WIDTH = 3.0;
-    BOX_3X6_X_ORIGIN = BOX_3X6_WIDTH / 2.0;
-    BOX_3X6_HEIGHT = 6.0;
-    BOX_3X6_Y_ORIGIN = BOX_3X6_HEIGHT / 2.0;
-
-    BOX_3X6_LEFT =   BOX_3X6_X_ORIGIN - (BOX_3X6_WIDTH / 2.0);
-    BOX_3X6_RIGHT =  BOX_3X6_X_ORIGIN + (BOX_3X6_WIDTH / 2.0);
-    BOX_3X6_TOP =    BOX_3X6_Y_ORIGIN + (BOX_3X6_HEIGHT / 2.0);
-    BOX_3X6_BOTTOM = BOX_3X6_Y_ORIGIN - (BOX_3X6_HEIGHT / 2.0);
-    line(BOX_3X6_LEFT, BOX_3X6_BOTTOM, BOX_3X6_RIGHT, BOX_3X6_BOTTOM);
-    line(BOX_3X6_LEFT, BOX_3X6_BOTTOM, BOX_3X6_LEFT, BOX_3X6_TOP);
-    line(BOX_3X6_RIGHT, BOX_3X6_TOP, BOX_3X6_RIGHT, BOX_3X6_BOTTOM);
-    line(BOX_3X6_RIGHT, BOX_3X6_TOP, BOX_3X6_LEFT, BOX_3X6_TOP);
-  }
-}
-
-
-
-/*****************************************************************************/
diff --git a/alliance/share/cells/sxlib/sxlib_FTGS.vhd b/alliance/share/cells/sxlib/sxlib_FTGS.vhd
deleted file mode 100644
index 6bc6ab6f..00000000
--- a/alliance/share/cells/sxlib/sxlib_FTGS.vhd
+++ /dev/null
@@ -1,12219 +0,0 @@
-
-----------------------------------------------------------------
--- 
--- Created by the Synopsys Library Compiler 1999.10
--- FILENAME     :    sxlib_FTGS.vhd
--- FILE CONTENTS:    Entity, Structural Architecture(FTGS),
---                   and Configuration
--- DATE CREATED :    Mon May  7 10:19:50 2001
--- 
--- LIBRARY      :    sxlib
--- DATE ENTERED :    Thu Dec 21 11:24:55 MET 2000
--- REVISION     :    1.200000
--- TECHNOLOGY   :    cmos
--- TIME SCALE   :    1 ns
--- LOGIC SYSTEM :    IEEE-1164
--- NOTES        :    FTGS, Timing_mesg(TRUE), Timing_xgen(FALSE), GLITCH_HANDLE
--- HISTORY      :
--- 
-----------------------------------------------------------------
-
------ CELL a2_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity a2_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.261 ns;
-      tpdi0_q_F                      :	Time := 0.388 ns;
-      tpdi1_q_R                      :	Time := 0.203 ns;
-      tpdi1_q_F                      :	Time := 0.434 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end a2_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of a2_x2 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U3/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U3/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U3/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U3/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   -- Netlist
-   U3 : TLU
-	generic map(
-		N => 2,
-		TruthTable => "0001",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 q",
-		delay_param =>
-			((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_a2_x2_FTGS of a2_x2 is
-   for FTGS
-   end for;
-end CFG_a2_x2_FTGS;
-
-
------ CELL a2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity a2_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.338 ns;
-      tpdi0_q_F                      :	Time := 0.476 ns;
-      tpdi1_q_R                      :	Time := 0.269 ns;
-      tpdi1_q_F                      :	Time := 0.518 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end a2_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of a2_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U3/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U3/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U3/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U3/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   -- Netlist
-   U3 : TLU
-	generic map(
-		N => 2,
-		TruthTable => "0001",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 q",
-		delay_param =>
-			((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_a2_x4_FTGS of a2_x4 is
-   for FTGS
-   end for;
-end CFG_a2_x4_FTGS;
-
-
------ CELL a3_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity a3_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.395 ns;
-      tpdi0_q_F                      :	Time := 0.435 ns;
-      tpdi1_q_R                      :	Time := 0.353 ns;
-      tpdi1_q_F                      :	Time := 0.479 ns;
-      tpdi2_q_R                      :	Time := 0.290 ns;
-      tpdi2_q_F                      :	Time := 0.521 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end a3_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of a3_x2 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is 
-	"U4/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is 
-	"U4/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U4/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U4/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U4/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U4/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   -- Netlist
-   U4 : TLU
-	generic map(
-		N => 3,
-		TruthTable => "00000001",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 q",
-		delay_param =>
-			((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_a3_x2_FTGS of a3_x2 is
-   for FTGS
-   end for;
-end CFG_a3_x2_FTGS;
-
-
------ CELL a3_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity a3_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.478 ns;
-      tpdi0_q_F                      :	Time := 0.514 ns;
-      tpdi1_q_R                      :	Time := 0.428 ns;
-      tpdi1_q_F                      :	Time := 0.554 ns;
-      tpdi2_q_R                      :	Time := 0.356 ns;
-      tpdi2_q_F                      :	Time := 0.592 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end a3_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of a3_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is 
-	"U4/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is 
-	"U4/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U4/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U4/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U4/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U4/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   -- Netlist
-   U4 : TLU
-	generic map(
-		N => 3,
-		TruthTable => "00000001",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 q",
-		delay_param =>
-			((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_a3_x4_FTGS of a3_x4 is
-   for FTGS
-   end for;
-end CFG_a3_x4_FTGS;
-
-
------ CELL a4_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity a4_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.374 ns;
-      tpdi0_q_F                      :	Time := 0.578 ns;
-      tpdi1_q_R                      :	Time := 0.441 ns;
-      tpdi1_q_F                      :	Time := 0.539 ns;
-      tpdi2_q_R                      :	Time := 0.482 ns;
-      tpdi2_q_F                      :	Time := 0.498 ns;
-      tpdi3_q_R                      :	Time := 0.506 ns;
-      tpdi3_q_F                      :	Time := 0.455 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end a4_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of a4_x2 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_q_F: constant is 
-	"U5/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi3_q_R: constant is 
-	"U5/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is 
-	"U5/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is 
-	"U5/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U5/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U5/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U5/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U5/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F))
-	port map( Input => i3, Output => connect(3));
-
-   -- Netlist
-   U5 : TLU
-	generic map(
-		N => 4,
-		TruthTable => "0000000000000001",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 i3 q",
-		delay_param =>
-			((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Input(3) => connect(3), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_a4_x2_FTGS of a4_x2 is
-   for FTGS
-   end for;
-end CFG_a4_x2_FTGS;
-
-
------ CELL a4_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity a4_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.505 ns;
-      tpdi0_q_F                      :	Time := 0.650 ns;
-      tpdi1_q_R                      :	Time := 0.578 ns;
-      tpdi1_q_F                      :	Time := 0.614 ns;
-      tpdi2_q_R                      :	Time := 0.627 ns;
-      tpdi2_q_F                      :	Time := 0.576 ns;
-      tpdi3_q_R                      :	Time := 0.661 ns;
-      tpdi3_q_F                      :	Time := 0.538 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end a4_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of a4_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_q_F: constant is 
-	"U5/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi3_q_R: constant is 
-	"U5/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is 
-	"U5/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is 
-	"U5/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U5/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U5/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U5/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U5/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F))
-	port map( Input => i3, Output => connect(3));
-
-   -- Netlist
-   U5 : TLU
-	generic map(
-		N => 4,
-		TruthTable => "0000000000000001",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 i3 q",
-		delay_param =>
-			((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Input(3) => connect(3), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_a4_x4_FTGS of a4_x4 is
-   for FTGS
-   end for;
-end CFG_a4_x4_FTGS;
-
-
------ CELL an12_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity an12_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.200 ns;
-      tpdi0_q_F                      :	Time := 0.168 ns;
-      tpdi1_q_R                      :	Time := 0.285 ns;
-      tpdi1_q_F                      :	Time := 0.405 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end an12_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of an12_x1 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U3/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U3/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U3/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U3/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   -- Netlist
-   U3 : TLU
-	generic map(
-		N => 2,
-		TruthTable => "0100",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 q",
-		delay_param =>
-			((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_an12_x1_FTGS of an12_x1 is
-   for FTGS
-   end for;
-end CFG_an12_x1_FTGS;
-
-
------ CELL an12_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity an12_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.461 ns;
-      tpdi0_q_F                      :	Time := 0.471 ns;
-      tpdi1_q_R                      :	Time := 0.269 ns;
-      tpdi1_q_F                      :	Time := 0.518 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end an12_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of an12_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U3/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U3/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U3/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U3/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   -- Netlist
-   U3 : TLU
-	generic map(
-		N => 2,
-		TruthTable => "0100",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 q",
-		delay_param =>
-			((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_an12_x4_FTGS of an12_x4 is
-   for FTGS
-   end for;
-end CFG_an12_x4_FTGS;
-
-
------ CELL ao2o22_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity ao2o22_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.572 ns;
-      tpdi0_q_F                      :	Time := 0.451 ns;
-      tpdi1_q_R                      :	Time := 0.508 ns;
-      tpdi1_q_F                      :	Time := 0.542 ns;
-      tpdi2_q_R                      :	Time := 0.432 ns;
-      tpdi2_q_F                      :	Time := 0.627 ns;
-      tpdi3_q_R                      :	Time := 0.488 ns;
-      tpdi3_q_F                      :	Time := 0.526 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end ao2o22_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of ao2o22_x2 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_q_F: constant is 
-	"U5/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi3_q_R: constant is 
-	"U5/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is 
-	"U5/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is 
-	"U5/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U5/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U5/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U5/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U5/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F))
-	port map( Input => i3, Output => connect(3));
-
-   -- Netlist
-   U5 : TLU
-	generic map(
-		N => 4,
-		TruthTable => "0000011101110111",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 i3 q",
-		delay_param =>
-			((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Input(3) => connect(3), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_ao2o22_x2_FTGS of ao2o22_x2 is
-   for FTGS
-   end for;
-end CFG_ao2o22_x2_FTGS;
-
-
------ CELL ao2o22_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity ao2o22_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.696 ns;
-      tpdi0_q_F                      :	Time := 0.569 ns;
-      tpdi1_q_R                      :	Time := 0.637 ns;
-      tpdi1_q_F                      :	Time := 0.666 ns;
-      tpdi2_q_R                      :	Time := 0.554 ns;
-      tpdi2_q_F                      :	Time := 0.744 ns;
-      tpdi3_q_R                      :	Time := 0.606 ns;
-      tpdi3_q_F                      :	Time := 0.639 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end ao2o22_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of ao2o22_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_q_F: constant is 
-	"U5/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi3_q_R: constant is 
-	"U5/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is 
-	"U5/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is 
-	"U5/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U5/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U5/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U5/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U5/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F))
-	port map( Input => i3, Output => connect(3));
-
-   -- Netlist
-   U5 : TLU
-	generic map(
-		N => 4,
-		TruthTable => "0000011101110111",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 i3 q",
-		delay_param =>
-			((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Input(3) => connect(3), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_ao2o22_x4_FTGS of ao2o22_x4 is
-   for FTGS
-   end for;
-end CFG_ao2o22_x4_FTGS;
-
-
------ CELL ao22_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity ao22_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.558 ns;
-      tpdi0_q_F                      :	Time := 0.447 ns;
-      tpdi1_q_R                      :	Time := 0.493 ns;
-      tpdi1_q_F                      :	Time := 0.526 ns;
-      tpdi2_q_R                      :	Time := 0.420 ns;
-      tpdi2_q_F                      :	Time := 0.425 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end ao22_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of ao22_x2 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is 
-	"U4/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is 
-	"U4/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U4/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U4/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U4/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U4/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   -- Netlist
-   U4 : TLU
-	generic map(
-		N => 3,
-		TruthTable => "00010101",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 q",
-		delay_param =>
-			((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_ao22_x2_FTGS of ao22_x2 is
-   for FTGS
-   end for;
-end CFG_ao22_x2_FTGS;
-
-
------ CELL ao22_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity ao22_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.674 ns;
-      tpdi0_q_F                      :	Time := 0.552 ns;
-      tpdi1_q_R                      :	Time := 0.615 ns;
-      tpdi1_q_F                      :	Time := 0.647 ns;
-      tpdi2_q_R                      :	Time := 0.526 ns;
-      tpdi2_q_F                      :	Time := 0.505 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end ao22_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of ao22_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is 
-	"U4/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is 
-	"U4/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U4/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U4/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U4/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U4/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   -- Netlist
-   U4 : TLU
-	generic map(
-		N => 3,
-		TruthTable => "00010101",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 q",
-		delay_param =>
-			((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_ao22_x4_FTGS of ao22_x4 is
-   for FTGS
-   end for;
-end CFG_ao22_x4_FTGS;
-
-
------ CELL buf_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity buf_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi_q_R                       :	Time := 0.409 ns;
-      tpdi_q_F                       :	Time := 0.391 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end buf_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of buf_x2 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi_q_F: constant is 
-	"U2/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi_q_R: constant is 
-	"U2/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F))
-	port map( Input => i, Output => connect(0));
-
-   -- Netlist
-   U2 : TLU
-	generic map(
-		N => 1,
-		TruthTable => "01",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i q",
-		delay_param =>
-			( 0 => (tpdi_q_R, tpdi_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "X",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_buf_x2_FTGS of buf_x2 is
-   for FTGS
-   end for;
-end CFG_buf_x2_FTGS;
-
-
------ CELL buf_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity buf_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi_q_R                       :	Time := 0.379 ns;
-      tpdi_q_F                       :	Time := 0.409 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end buf_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of buf_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi_q_F: constant is 
-	"U2/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi_q_R: constant is 
-	"U2/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F))
-	port map( Input => i, Output => connect(0));
-
-   -- Netlist
-   U2 : TLU
-	generic map(
-		N => 1,
-		TruthTable => "01",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i q",
-		delay_param =>
-			( 0 => (tpdi_q_R, tpdi_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "X",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_buf_x4_FTGS of buf_x4 is
-   for FTGS
-   end for;
-end CFG_buf_x4_FTGS;
-
-
------ CELL buf_x8 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity buf_x8 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi_q_R                       :	Time := 0.343 ns;
-      tpdi_q_F                       :	Time := 0.396 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end buf_x8;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of buf_x8 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi_q_F: constant is 
-	"U2/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi_q_R: constant is 
-	"U2/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F))
-	port map( Input => i, Output => connect(0));
-
-   -- Netlist
-   U2 : TLU
-	generic map(
-		N => 1,
-		TruthTable => "01",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i q",
-		delay_param =>
-			( 0 => (tpdi_q_R, tpdi_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "X",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_buf_x8_FTGS of buf_x8 is
-   for FTGS
-   end for;
-end CFG_buf_x8_FTGS;
-
-
------ CELL inv_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity inv_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi_nq_R                      :	Time := 0.101 ns;
-      tpdi_nq_F                      :	Time := 0.139 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end inv_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of inv_x1 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi_nq_F: constant is 
-	"U2/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi_nq_R: constant is 
-	"U2/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F))
-	port map( Input => i, Output => connect(0));
-
-   -- Netlist
-   U2 : TLU
-	generic map(
-		N => 1,
-		TruthTable => "10",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i nq",
-		delay_param =>
-			( 0 => (tpdi_nq_R, tpdi_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "X",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_inv_x1_FTGS of inv_x1 is
-   for FTGS
-   end for;
-end CFG_inv_x1_FTGS;
-
-
------ CELL inv_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity inv_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi_nq_R                      :	Time := 0.069 ns;
-      tpdi_nq_F                      :	Time := 0.163 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end inv_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of inv_x2 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi_nq_F: constant is 
-	"U2/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi_nq_R: constant is 
-	"U2/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F))
-	port map( Input => i, Output => connect(0));
-
-   -- Netlist
-   U2 : TLU
-	generic map(
-		N => 1,
-		TruthTable => "10",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i nq",
-		delay_param =>
-			( 0 => (tpdi_nq_R, tpdi_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "X",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_inv_x2_FTGS of inv_x2 is
-   for FTGS
-   end for;
-end CFG_inv_x2_FTGS;
-
-
------ CELL inv_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity inv_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi_nq_R                      :	Time := 0.071 ns;
-      tpdi_nq_F                      :	Time := 0.143 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end inv_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of inv_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi_nq_F: constant is 
-	"U2/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi_nq_R: constant is 
-	"U2/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F))
-	port map( Input => i, Output => connect(0));
-
-   -- Netlist
-   U2 : TLU
-	generic map(
-		N => 1,
-		TruthTable => "10",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i nq",
-		delay_param =>
-			( 0 => (tpdi_nq_R, tpdi_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "X",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_inv_x4_FTGS of inv_x4 is
-   for FTGS
-   end for;
-end CFG_inv_x4_FTGS;
-
-
------ CELL inv_x8 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity inv_x8 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi_nq_R                      :	Time := 0.086 ns;
-      tpdi_nq_F                      :	Time := 0.133 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end inv_x8;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of inv_x8 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi_nq_F: constant is 
-	"U2/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi_nq_R: constant is 
-	"U2/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F))
-	port map( Input => i, Output => connect(0));
-
-   -- Netlist
-   U2 : TLU
-	generic map(
-		N => 1,
-		TruthTable => "10",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i nq",
-		delay_param =>
-			( 0 => (tpdi_nq_R, tpdi_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "X",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_inv_x8_FTGS of inv_x8 is
-   for FTGS
-   end for;
-end CFG_inv_x8_FTGS;
-
-
------ CELL mx2_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity mx2_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd_q_R                     :	Time := 0.484 ns;
-      tpdcmd_q_F                     :	Time := 0.522 ns;
-      tpdi0_q_R                      :	Time := 0.451 ns;
-      tpdi0_q_F                      :	Time := 0.469 ns;
-      tpdi1_q_R                      :	Time := 0.451 ns;
-      tpdi1_q_F                      :	Time := 0.469 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      cmd                            :	in    STD_LOGIC;
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end mx2_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of mx2_x2 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U4/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U4/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U4/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U4/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is 
-	"U4/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is 
-	"U4/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdcmd_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdcmd_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F))
-	port map( Input => cmd, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(2));
-
-   -- Netlist
-   U4 : TLU
-	generic map(
-		N => 3,
-		TruthTable => "00110101",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "cmd i0 i1 q",
-		delay_param =>
-			((tpdcmd_q_R, tpdcmd_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_mx2_x2_FTGS of mx2_x2 is
-   for FTGS
-   end for;
-end CFG_mx2_x2_FTGS;
-
-
------ CELL mx2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity mx2_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd_q_R                     :	Time := 0.615 ns;
-      tpdcmd_q_F                     :	Time := 0.647 ns;
-      tpdi0_q_R                      :	Time := 0.564 ns;
-      tpdi0_q_F                      :	Time := 0.576 ns;
-      tpdi1_q_R                      :	Time := 0.564 ns;
-      tpdi1_q_F                      :	Time := 0.576 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      cmd                            :	in    STD_LOGIC;
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end mx2_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of mx2_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U4/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U4/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U4/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U4/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is 
-	"U4/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is 
-	"U4/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdcmd_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdcmd_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F))
-	port map( Input => cmd, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(2));
-
-   -- Netlist
-   U4 : TLU
-	generic map(
-		N => 3,
-		TruthTable => "00110101",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "cmd i0 i1 q",
-		delay_param =>
-			((tpdcmd_q_R, tpdcmd_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_mx2_x4_FTGS of mx2_x4 is
-   for FTGS
-   end for;
-end CFG_mx2_x4_FTGS;
-
-
------ CELL mx3_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity mx3_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd0_q_R                    :	Time := 0.573 ns;
-      tpdcmd0_q_F                    :	Time := 0.680 ns;
-      tpdcmd1_q_R                    :	Time := 0.664 ns;
-      tpdcmd1_q_F                    :	Time := 0.817 ns;
-      tpdi0_q_R                      :	Time := 0.538 ns;
-      tpdi0_q_F                      :	Time := 0.658 ns;
-      tpdi1_q_R                      :	Time := 0.654 ns;
-      tpdi1_q_F                      :	Time := 0.808 ns;
-      tpdi2_q_R                      :	Time := 0.654 ns;
-      tpdi2_q_F                      :	Time := 0.808 ns;
-      twdcmd0_R                      :	Time := 0.000 ns;
-      twdcmd0_F                      :	Time := 0.000 ns;
-      twdcmd1_R                      :	Time := 0.000 ns;
-      twdcmd1_F                      :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      cmd0                           :	in    STD_LOGIC;
-      cmd1                           :	in    STD_LOGIC;
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end mx3_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of mx3_x2 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is 
-	"U6/delay_param(4)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is 
-	"U6/delay_param(4)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U6/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U6/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U6/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U6/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdcmd1_q_F: constant is 
-	"U6/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdcmd1_q_R: constant is 
-	"U6/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdcmd0_q_F: constant is 
-	"U6/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdcmd0_q_R: constant is 
-	"U6/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U5/delay(TRAN_10), " &
-	"U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U5/delay(TRAN_01), " &
-	"U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdcmd1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdcmd1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdcmd0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdcmd0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdcmd0_R, twdcmd0_F, twdcmd0_R, twdcmd0_R, twdcmd0_F, twdcmd0_F))
-	port map( Input => cmd0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdcmd1_R, twdcmd1_F, twdcmd1_R, twdcmd1_R, twdcmd1_F, twdcmd1_F))
-	port map( Input => cmd1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(3));
-
-   U5 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(4));
-
-   -- Netlist
-   U6 : TLU
-	generic map(
-		N => 5,
-		TruthTable => "00001111000011110101010100110011",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "cmd0 cmd1 i0 i1 i2 q",
-		delay_param =>
-			((tpdcmd0_q_R, tpdcmd0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdcmd1_q_R, tpdcmd1_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Input(3) => connect(3), 
-		Input(4) => connect(4), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_mx3_x2_FTGS of mx3_x2 is
-   for FTGS
-   end for;
-end CFG_mx3_x2_FTGS;
-
-
------ CELL mx3_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity mx3_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd0_q_R                    :	Time := 0.683 ns;
-      tpdcmd0_q_F                    :	Time := 0.779 ns;
-      tpdcmd1_q_R                    :	Time := 0.792 ns;
-      tpdcmd1_q_F                    :	Time := 0.967 ns;
-      tpdi0_q_R                      :	Time := 0.640 ns;
-      tpdi0_q_F                      :	Time := 0.774 ns;
-      tpdi1_q_R                      :	Time := 0.770 ns;
-      tpdi1_q_F                      :	Time := 0.948 ns;
-      tpdi2_q_R                      :	Time := 0.770 ns;
-      tpdi2_q_F                      :	Time := 0.948 ns;
-      twdcmd0_R                      :	Time := 0.000 ns;
-      twdcmd0_F                      :	Time := 0.000 ns;
-      twdcmd1_R                      :	Time := 0.000 ns;
-      twdcmd1_F                      :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      cmd0                           :	in    STD_LOGIC;
-      cmd1                           :	in    STD_LOGIC;
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end mx3_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of mx3_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is 
-	"U6/delay_param(4)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is 
-	"U6/delay_param(4)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U6/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U6/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U6/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U6/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdcmd1_q_F: constant is 
-	"U6/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdcmd1_q_R: constant is 
-	"U6/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdcmd0_q_F: constant is 
-	"U6/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdcmd0_q_R: constant is 
-	"U6/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U5/delay(TRAN_10), " &
-	"U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U5/delay(TRAN_01), " &
-	"U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdcmd1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdcmd1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdcmd0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdcmd0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdcmd0_R, twdcmd0_F, twdcmd0_R, twdcmd0_R, twdcmd0_F, twdcmd0_F))
-	port map( Input => cmd0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdcmd1_R, twdcmd1_F, twdcmd1_R, twdcmd1_R, twdcmd1_F, twdcmd1_F))
-	port map( Input => cmd1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(3));
-
-   U5 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(4));
-
-   -- Netlist
-   U6 : TLU
-	generic map(
-		N => 5,
-		TruthTable => "00001111000011110101010100110011",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "cmd0 cmd1 i0 i1 i2 q",
-		delay_param =>
-			((tpdcmd0_q_R, tpdcmd0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdcmd1_q_R, tpdcmd1_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Input(3) => connect(3), 
-		Input(4) => connect(4), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_mx3_x4_FTGS of mx3_x4 is
-   for FTGS
-   end for;
-end CFG_mx3_x4_FTGS;
-
-
------ CELL na2_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity na2_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.059 ns;
-      tpdi0_nq_F                     :	Time := 0.288 ns;
-      tpdi1_nq_R                     :	Time := 0.111 ns;
-      tpdi1_nq_F                     :	Time := 0.234 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end na2_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of na2_x1 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is 
-	"U3/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is 
-	"U3/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is 
-	"U3/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is 
-	"U3/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   -- Netlist
-   U3 : TLU
-	generic map(
-		N => 2,
-		TruthTable => "1110",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 nq",
-		delay_param =>
-			((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_na2_x1_FTGS of na2_x1 is
-   for FTGS
-   end for;
-end CFG_na2_x1_FTGS;
-
-
------ CELL na2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity na2_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.412 ns;
-      tpdi0_nq_F                     :	Time := 0.552 ns;
-      tpdi1_nq_R                     :	Time := 0.353 ns;
-      tpdi1_nq_F                     :	Time := 0.601 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end na2_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of na2_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is 
-	"U3/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is 
-	"U3/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is 
-	"U3/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is 
-	"U3/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   -- Netlist
-   U3 : TLU
-	generic map(
-		N => 2,
-		TruthTable => "1110",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 nq",
-		delay_param =>
-			((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_na2_x4_FTGS of na2_x4 is
-   for FTGS
-   end for;
-end CFG_na2_x4_FTGS;
-
-
------ CELL na3_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity na3_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.119 ns;
-      tpdi0_nq_F                     :	Time := 0.363 ns;
-      tpdi1_nq_R                     :	Time := 0.171 ns;
-      tpdi1_nq_F                     :	Time := 0.316 ns;
-      tpdi2_nq_R                     :	Time := 0.193 ns;
-      tpdi2_nq_F                     :	Time := 0.265 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end na3_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of na3_x1 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is 
-	"U4/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is 
-	"U4/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is 
-	"U4/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is 
-	"U4/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is 
-	"U4/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is 
-	"U4/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   -- Netlist
-   U4 : TLU
-	generic map(
-		N => 3,
-		TruthTable => "11111110",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 nq",
-		delay_param =>
-			((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_na3_x1_FTGS of na3_x1 is
-   for FTGS
-   end for;
-end CFG_na3_x1_FTGS;
-
-
------ CELL na3_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity na3_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.556 ns;
-      tpdi0_nq_F                     :	Time := 0.601 ns;
-      tpdi1_nq_R                     :	Time := 0.460 ns;
-      tpdi1_nq_F                     :	Time := 0.691 ns;
-      tpdi2_nq_R                     :	Time := 0.519 ns;
-      tpdi2_nq_F                     :	Time := 0.647 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end na3_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of na3_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is 
-	"U4/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is 
-	"U4/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is 
-	"U4/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is 
-	"U4/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is 
-	"U4/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is 
-	"U4/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   -- Netlist
-   U4 : TLU
-	generic map(
-		N => 3,
-		TruthTable => "11111110",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 nq",
-		delay_param =>
-			((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_na3_x4_FTGS of na3_x4 is
-   for FTGS
-   end for;
-end CFG_na3_x4_FTGS;
-
-
------ CELL na4_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity na4_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.179 ns;
-      tpdi0_nq_F                     :	Time := 0.438 ns;
-      tpdi1_nq_R                     :	Time := 0.237 ns;
-      tpdi1_nq_F                     :	Time := 0.395 ns;
-      tpdi2_nq_R                     :	Time := 0.269 ns;
-      tpdi2_nq_F                     :	Time := 0.350 ns;
-      tpdi3_nq_R                     :	Time := 0.282 ns;
-      tpdi3_nq_F                     :	Time := 0.302 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end na4_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of na4_x1 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is 
-	"U5/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is 
-	"U5/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is 
-	"U5/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is 
-	"U5/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is 
-	"U5/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is 
-	"U5/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is 
-	"U5/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is 
-	"U5/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F))
-	port map( Input => i3, Output => connect(3));
-
-   -- Netlist
-   U5 : TLU
-	generic map(
-		N => 4,
-		TruthTable => "1111111111111110",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 i3 nq",
-		delay_param =>
-			((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Input(3) => connect(3), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_na4_x1_FTGS of na4_x1 is
-   for FTGS
-   end for;
-end CFG_na4_x1_FTGS;
-
-
------ CELL na4_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity na4_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.578 ns;
-      tpdi0_nq_F                     :	Time := 0.771 ns;
-      tpdi1_nq_R                     :	Time := 0.643 ns;
-      tpdi1_nq_F                     :	Time := 0.731 ns;
-      tpdi2_nq_R                     :	Time := 0.681 ns;
-      tpdi2_nq_F                     :	Time := 0.689 ns;
-      tpdi3_nq_R                     :	Time := 0.703 ns;
-      tpdi3_nq_F                     :	Time := 0.644 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end na4_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of na4_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is 
-	"U5/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is 
-	"U5/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is 
-	"U5/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is 
-	"U5/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is 
-	"U5/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is 
-	"U5/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is 
-	"U5/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is 
-	"U5/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F))
-	port map( Input => i3, Output => connect(3));
-
-   -- Netlist
-   U5 : TLU
-	generic map(
-		N => 4,
-		TruthTable => "1111111111111110",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 i3 nq",
-		delay_param =>
-			((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Input(3) => connect(3), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_na4_x4_FTGS of na4_x4 is
-   for FTGS
-   end for;
-end CFG_na4_x4_FTGS;
-
-
------ CELL nao2o22_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nao2o22_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.294 ns;
-      tpdi0_nq_F                     :	Time := 0.226 ns;
-      tpdi1_nq_R                     :	Time := 0.218 ns;
-      tpdi1_nq_F                     :	Time := 0.287 ns;
-      tpdi2_nq_R                     :	Time := 0.237 ns;
-      tpdi2_nq_F                     :	Time := 0.307 ns;
-      tpdi3_nq_R                     :	Time := 0.174 ns;
-      tpdi3_nq_F                     :	Time := 0.382 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nao2o22_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of nao2o22_x1 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is 
-	"U5/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is 
-	"U5/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is 
-	"U5/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is 
-	"U5/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is 
-	"U5/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is 
-	"U5/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is 
-	"U5/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is 
-	"U5/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F))
-	port map( Input => i3, Output => connect(3));
-
-   -- Netlist
-   U5 : TLU
-	generic map(
-		N => 4,
-		TruthTable => "1111100010001000",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 i3 nq",
-		delay_param =>
-			((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Input(3) => connect(3), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_nao2o22_x1_FTGS of nao2o22_x1 is
-   for FTGS
-   end for;
-end CFG_nao2o22_x1_FTGS;
-
-
------ CELL nao2o22_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nao2o22_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.734 ns;
-      tpdi0_nq_F                     :	Time := 0.644 ns;
-      tpdi1_nq_R                     :	Time := 0.666 ns;
-      tpdi1_nq_F                     :	Time := 0.717 ns;
-      tpdi2_nq_R                     :	Time := 0.664 ns;
-      tpdi2_nq_F                     :	Time := 0.721 ns;
-      tpdi3_nq_R                     :	Time := 0.607 ns;
-      tpdi3_nq_F                     :	Time := 0.807 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nao2o22_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of nao2o22_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is 
-	"U5/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is 
-	"U5/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is 
-	"U5/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is 
-	"U5/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is 
-	"U5/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is 
-	"U5/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is 
-	"U5/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is 
-	"U5/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F))
-	port map( Input => i3, Output => connect(3));
-
-   -- Netlist
-   U5 : TLU
-	generic map(
-		N => 4,
-		TruthTable => "1111100010001000",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 i3 nq",
-		delay_param =>
-			((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Input(3) => connect(3), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_nao2o22_x4_FTGS of nao2o22_x4 is
-   for FTGS
-   end for;
-end CFG_nao2o22_x4_FTGS;
-
-
------ CELL nao22_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nao22_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.294 ns;
-      tpdi0_nq_F                     :	Time := 0.226 ns;
-      tpdi1_nq_R                     :	Time := 0.218 ns;
-      tpdi1_nq_F                     :	Time := 0.287 ns;
-      tpdi2_nq_R                     :	Time := 0.165 ns;
-      tpdi2_nq_F                     :	Time := 0.238 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nao22_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of nao22_x1 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is 
-	"U4/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is 
-	"U4/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is 
-	"U4/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is 
-	"U4/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is 
-	"U4/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is 
-	"U4/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   -- Netlist
-   U4 : TLU
-	generic map(
-		N => 3,
-		TruthTable => "11101010",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 nq",
-		delay_param =>
-			((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_nao22_x1_FTGS of nao22_x1 is
-   for FTGS
-   end for;
-end CFG_nao22_x1_FTGS;
-
-
------ CELL nao22_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nao22_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.732 ns;
-      tpdi0_nq_F                     :	Time := 0.650 ns;
-      tpdi1_nq_R                     :	Time := 0.664 ns;
-      tpdi1_nq_F                     :	Time := 0.723 ns;
-      tpdi2_nq_R                     :	Time := 0.596 ns;
-      tpdi2_nq_F                     :	Time := 0.636 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nao22_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of nao22_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is 
-	"U4/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is 
-	"U4/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is 
-	"U4/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is 
-	"U4/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is 
-	"U4/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is 
-	"U4/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   -- Netlist
-   U4 : TLU
-	generic map(
-		N => 3,
-		TruthTable => "11101010",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 nq",
-		delay_param =>
-			((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_nao22_x4_FTGS of nao22_x4 is
-   for FTGS
-   end for;
-end CFG_nao22_x4_FTGS;
-
-
------ CELL nmx2_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nmx2_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd_nq_R                    :	Time := 0.218 ns;
-      tpdcmd_nq_F                    :	Time := 0.287 ns;
-      tpdi0_nq_R                     :	Time := 0.217 ns;
-      tpdi0_nq_F                     :	Time := 0.256 ns;
-      tpdi1_nq_R                     :	Time := 0.217 ns;
-      tpdi1_nq_F                     :	Time := 0.256 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      cmd                            :	in    STD_LOGIC;
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nmx2_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of nmx2_x1 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is 
-	"U4/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is 
-	"U4/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is 
-	"U4/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is 
-	"U4/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is 
-	"U4/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is 
-	"U4/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdcmd_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdcmd_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F))
-	port map( Input => cmd, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(2));
-
-   -- Netlist
-   U4 : TLU
-	generic map(
-		N => 3,
-		TruthTable => "11001010",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "cmd i0 i1 nq",
-		delay_param =>
-			((tpdcmd_nq_R, tpdcmd_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_nmx2_x1_FTGS of nmx2_x1 is
-   for FTGS
-   end for;
-end CFG_nmx2_x1_FTGS;
-
-
------ CELL nmx2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nmx2_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd_nq_R                    :	Time := 0.632 ns;
-      tpdcmd_nq_F                    :	Time := 0.708 ns;
-      tpdi0_nq_R                     :	Time := 0.610 ns;
-      tpdi0_nq_F                     :	Time := 0.653 ns;
-      tpdi1_nq_R                     :	Time := 0.610 ns;
-      tpdi1_nq_F                     :	Time := 0.653 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      cmd                            :	in    STD_LOGIC;
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nmx2_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of nmx2_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is 
-	"U4/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is 
-	"U4/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is 
-	"U4/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is 
-	"U4/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is 
-	"U4/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is 
-	"U4/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdcmd_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdcmd_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F))
-	port map( Input => cmd, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(2));
-
-   -- Netlist
-   U4 : TLU
-	generic map(
-		N => 3,
-		TruthTable => "11001010",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "cmd i0 i1 nq",
-		delay_param =>
-			((tpdcmd_nq_R, tpdcmd_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_nmx2_x4_FTGS of nmx2_x4 is
-   for FTGS
-   end for;
-end CFG_nmx2_x4_FTGS;
-
-
------ CELL nmx3_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nmx3_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd0_nq_R                   :	Time := 0.356 ns;
-      tpdcmd0_nq_F                   :	Time := 0.495 ns;
-      tpdcmd1_nq_R                   :	Time := 0.414 ns;
-      tpdcmd1_nq_F                   :	Time := 0.566 ns;
-      tpdi0_nq_R                     :	Time := 0.315 ns;
-      tpdi0_nq_F                     :	Time := 0.441 ns;
-      tpdi1_nq_R                     :	Time := 0.429 ns;
-      tpdi1_nq_F                     :	Time := 0.582 ns;
-      tpdi2_nq_R                     :	Time := 0.429 ns;
-      tpdi2_nq_F                     :	Time := 0.582 ns;
-      twdcmd0_R                      :	Time := 0.000 ns;
-      twdcmd0_F                      :	Time := 0.000 ns;
-      twdcmd1_R                      :	Time := 0.000 ns;
-      twdcmd1_F                      :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      cmd0                           :	in    STD_LOGIC;
-      cmd1                           :	in    STD_LOGIC;
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nmx3_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of nmx3_x1 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is 
-	"U6/delay_param(4)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is 
-	"U6/delay_param(4)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is 
-	"U6/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is 
-	"U6/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is 
-	"U6/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is 
-	"U6/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdcmd1_nq_F: constant is 
-	"U6/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdcmd1_nq_R: constant is 
-	"U6/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdcmd0_nq_F: constant is 
-	"U6/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdcmd0_nq_R: constant is 
-	"U6/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U5/delay(TRAN_10), " &
-	"U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U5/delay(TRAN_01), " &
-	"U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdcmd1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdcmd1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdcmd0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdcmd0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdcmd0_R, twdcmd0_F, twdcmd0_R, twdcmd0_R, twdcmd0_F, twdcmd0_F))
-	port map( Input => cmd0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdcmd1_R, twdcmd1_F, twdcmd1_R, twdcmd1_R, twdcmd1_F, twdcmd1_F))
-	port map( Input => cmd1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(3));
-
-   U5 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(4));
-
-   -- Netlist
-   U6 : TLU
-	generic map(
-		N => 5,
-		TruthTable => "11110000111100001010101011001100",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "cmd0 cmd1 i0 i1 i2 nq",
-		delay_param =>
-			((tpdcmd0_nq_R, tpdcmd0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdcmd1_nq_R, tpdcmd1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Input(3) => connect(3), 
-		Input(4) => connect(4), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_nmx3_x1_FTGS of nmx3_x1 is
-   for FTGS
-   end for;
-end CFG_nmx3_x1_FTGS;
-
-
------ CELL nmx3_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nmx3_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd0_nq_R                   :	Time := 0.790 ns;
-      tpdcmd0_nq_F                   :	Time := 0.936 ns;
-      tpdcmd1_nq_R                   :	Time := 0.866 ns;
-      tpdcmd1_nq_F                   :	Time := 1.048 ns;
-      tpdi0_nq_R                     :	Time := 0.748 ns;
-      tpdi0_nq_F                     :	Time := 0.900 ns;
-      tpdi1_nq_R                     :	Time := 0.869 ns;
-      tpdi1_nq_F                     :	Time := 1.053 ns;
-      tpdi2_nq_R                     :	Time := 0.869 ns;
-      tpdi2_nq_F                     :	Time := 1.053 ns;
-      twdcmd0_R                      :	Time := 0.000 ns;
-      twdcmd0_F                      :	Time := 0.000 ns;
-      twdcmd1_R                      :	Time := 0.000 ns;
-      twdcmd1_F                      :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      cmd0                           :	in    STD_LOGIC;
-      cmd1                           :	in    STD_LOGIC;
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nmx3_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of nmx3_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is 
-	"U6/delay_param(4)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is 
-	"U6/delay_param(4)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is 
-	"U6/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is 
-	"U6/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is 
-	"U6/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is 
-	"U6/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdcmd1_nq_F: constant is 
-	"U6/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdcmd1_nq_R: constant is 
-	"U6/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdcmd0_nq_F: constant is 
-	"U6/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdcmd0_nq_R: constant is 
-	"U6/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U5/delay(TRAN_10), " &
-	"U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U5/delay(TRAN_01), " &
-	"U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdcmd1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdcmd1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdcmd0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdcmd0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdcmd0_R, twdcmd0_F, twdcmd0_R, twdcmd0_R, twdcmd0_F, twdcmd0_F))
-	port map( Input => cmd0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdcmd1_R, twdcmd1_F, twdcmd1_R, twdcmd1_R, twdcmd1_F, twdcmd1_F))
-	port map( Input => cmd1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(3));
-
-   U5 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(4));
-
-   -- Netlist
-   U6 : TLU
-	generic map(
-		N => 5,
-		TruthTable => "11110000111100001010101011001100",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "cmd0 cmd1 i0 i1 i2 nq",
-		delay_param =>
-			((tpdcmd0_nq_R, tpdcmd0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdcmd1_nq_R, tpdcmd1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Input(3) => connect(3), 
-		Input(4) => connect(4), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_nmx3_x4_FTGS of nmx3_x4 is
-   for FTGS
-   end for;
-end CFG_nmx3_x4_FTGS;
-
-
------ CELL no2_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity no2_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.298 ns;
-      tpdi0_nq_F                     :	Time := 0.121 ns;
-      tpdi1_nq_R                     :	Time := 0.193 ns;
-      tpdi1_nq_F                     :	Time := 0.161 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end no2_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of no2_x1 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is 
-	"U3/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is 
-	"U3/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is 
-	"U3/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is 
-	"U3/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   -- Netlist
-   U3 : TLU
-	generic map(
-		N => 2,
-		TruthTable => "1000",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 nq",
-		delay_param =>
-			((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_no2_x1_FTGS of no2_x1 is
-   for FTGS
-   end for;
-end CFG_no2_x1_FTGS;
-
-
------ CELL no2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity no2_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.618 ns;
-      tpdi0_nq_F                     :	Time := 0.447 ns;
-      tpdi1_nq_R                     :	Time := 0.522 ns;
-      tpdi1_nq_F                     :	Time := 0.504 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end no2_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of no2_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is 
-	"U3/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is 
-	"U3/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is 
-	"U3/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is 
-	"U3/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   -- Netlist
-   U3 : TLU
-	generic map(
-		N => 2,
-		TruthTable => "1000",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 nq",
-		delay_param =>
-			((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_no2_x4_FTGS of no2_x4 is
-   for FTGS
-   end for;
-end CFG_no2_x4_FTGS;
-
-
------ CELL no3_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity no3_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.318 ns;
-      tpdi0_nq_F                     :	Time := 0.246 ns;
-      tpdi1_nq_R                     :	Time := 0.215 ns;
-      tpdi1_nq_F                     :	Time := 0.243 ns;
-      tpdi2_nq_R                     :	Time := 0.407 ns;
-      tpdi2_nq_F                     :	Time := 0.192 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end no3_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of no3_x1 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is 
-	"U4/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is 
-	"U4/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is 
-	"U4/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is 
-	"U4/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is 
-	"U4/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is 
-	"U4/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   -- Netlist
-   U4 : TLU
-	generic map(
-		N => 3,
-		TruthTable => "10000000",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 nq",
-		delay_param =>
-			((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_no3_x1_FTGS of no3_x1 is
-   for FTGS
-   end for;
-end CFG_no3_x1_FTGS;
-
-
------ CELL no3_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity no3_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.722 ns;
-      tpdi0_nq_F                     :	Time := 0.561 ns;
-      tpdi1_nq_R                     :	Time := 0.638 ns;
-      tpdi1_nq_F                     :	Time := 0.623 ns;
-      tpdi2_nq_R                     :	Time := 0.545 ns;
-      tpdi2_nq_F                     :	Time := 0.640 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end no3_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of no3_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is 
-	"U4/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is 
-	"U4/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is 
-	"U4/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is 
-	"U4/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is 
-	"U4/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is 
-	"U4/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   -- Netlist
-   U4 : TLU
-	generic map(
-		N => 3,
-		TruthTable => "10000000",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 nq",
-		delay_param =>
-			((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_no3_x4_FTGS of no3_x4 is
-   for FTGS
-   end for;
-end CFG_no3_x4_FTGS;
-
-
------ CELL no4_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity no4_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.330 ns;
-      tpdi0_nq_F                     :	Time := 0.340 ns;
-      tpdi1_nq_R                     :	Time := 0.230 ns;
-      tpdi1_nq_F                     :	Time := 0.320 ns;
-      tpdi2_nq_R                     :	Time := 0.419 ns;
-      tpdi2_nq_F                     :	Time := 0.333 ns;
-      tpdi3_nq_R                     :	Time := 0.499 ns;
-      tpdi3_nq_F                     :	Time := 0.271 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end no4_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of no4_x1 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is 
-	"U5/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is 
-	"U5/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is 
-	"U5/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is 
-	"U5/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is 
-	"U5/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is 
-	"U5/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is 
-	"U5/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is 
-	"U5/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F))
-	port map( Input => i3, Output => connect(3));
-
-   -- Netlist
-   U5 : TLU
-	generic map(
-		N => 4,
-		TruthTable => "1000000000000000",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 i3 nq",
-		delay_param =>
-			((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Input(3) => connect(3), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_no4_x1_FTGS of no4_x1 is
-   for FTGS
-   end for;
-end CFG_no4_x1_FTGS;
-
-
------ CELL no4_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity no4_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.656 ns;
-      tpdi0_nq_F                     :	Time := 0.777 ns;
-      tpdi1_nq_R                     :	Time := 0.564 ns;
-      tpdi1_nq_F                     :	Time := 0.768 ns;
-      tpdi2_nq_R                     :	Time := 0.739 ns;
-      tpdi2_nq_F                     :	Time := 0.761 ns;
-      tpdi3_nq_R                     :	Time := 0.816 ns;
-      tpdi3_nq_F                     :	Time := 0.693 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end no4_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of no4_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is 
-	"U5/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is 
-	"U5/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is 
-	"U5/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is 
-	"U5/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is 
-	"U5/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is 
-	"U5/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is 
-	"U5/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is 
-	"U5/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F))
-	port map( Input => i3, Output => connect(3));
-
-   -- Netlist
-   U5 : TLU
-	generic map(
-		N => 4,
-		TruthTable => "1000000000000000",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 i3 nq",
-		delay_param =>
-			((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Input(3) => connect(3), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_no4_x4_FTGS of no4_x4 is
-   for FTGS
-   end for;
-end CFG_no4_x4_FTGS;
-
-
------ CELL noa2a2a2a24_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa2a2a2a24_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.649 ns;
-      tpdi0_nq_F                     :	Time := 0.606 ns;
-      tpdi1_nq_R                     :	Time := 0.775 ns;
-      tpdi1_nq_F                     :	Time := 0.562 ns;
-      tpdi2_nq_R                     :	Time := 0.550 ns;
-      tpdi2_nq_F                     :	Time := 0.662 ns;
-      tpdi3_nq_R                     :	Time := 0.667 ns;
-      tpdi3_nq_F                     :	Time := 0.616 ns;
-      tpdi4_nq_R                     :	Time := 0.419 ns;
-      tpdi4_nq_F                     :	Time := 0.613 ns;
-      tpdi5_nq_R                     :	Time := 0.329 ns;
-      tpdi5_nq_F                     :	Time := 0.662 ns;
-      tpdi6_nq_R                     :	Time := 0.270 ns;
-      tpdi6_nq_F                     :	Time := 0.535 ns;
-      tpdi7_nq_R                     :	Time := 0.200 ns;
-      tpdi7_nq_F                     :	Time := 0.591 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns;
-      twdi6_R                        :	Time := 0.000 ns;
-      twdi6_F                        :	Time := 0.000 ns;
-      twdi7_R                        :	Time := 0.000 ns;
-      twdi7_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      i6                             :	in    STD_LOGIC;
-      i7                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa2a2a2a24_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of noa2a2a2a24_x1 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi7_nq_F: constant is 
-	"U9/delay_param(7)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi7_nq_R: constant is 
-	"U9/delay_param(7)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is 
-	"U9/delay_param(6)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is 
-	"U9/delay_param(6)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is 
-	"U9/delay_param(5)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is 
-	"U9/delay_param(5)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is 
-	"U9/delay_param(4)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is 
-	"U9/delay_param(4)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is 
-	"U9/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is 
-	"U9/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is 
-	"U9/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is 
-	"U9/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is 
-	"U9/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is 
-	"U9/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is 
-	"U9/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is 
-	"U9/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi7_F: constant is 
-	"U8/delay(TRAN_10), " &
-	"U8/delay(TRAN_1Z), U8/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi7_R: constant is 
-	"U8/delay(TRAN_01), " &
-	"U8/delay(TRAN_0Z), U8/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi6_F: constant is 
-	"U7/delay(TRAN_10), " &
-	"U7/delay(TRAN_1Z), U7/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi6_R: constant is 
-	"U7/delay(TRAN_01), " &
-	"U7/delay(TRAN_0Z), U7/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi5_F: constant is 
-	"U6/delay(TRAN_10), " &
-	"U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi5_R: constant is 
-	"U6/delay(TRAN_01), " &
-	"U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi4_F: constant is 
-	"U5/delay(TRAN_10), " &
-	"U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi4_R: constant is 
-	"U5/delay(TRAN_01), " &
-	"U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); 
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F))
-	port map( Input => i3, Output => connect(3));
-
-   U5 : WIREBUF
-	generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F))
-	port map( Input => i4, Output => connect(4));
-
-   U6 : WIREBUF
-	generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F))
-	port map( Input => i5, Output => connect(5));
-
-   U7 : WIREBUF
-	generic map(delay => (twdi6_R, twdi6_F, twdi6_R, twdi6_R, twdi6_F, twdi6_F))
-	port map( Input => i6, Output => connect(6));
-
-   U8 : WIREBUF
-	generic map(delay => (twdi7_R, twdi7_F, twdi7_R, twdi7_R, twdi7_F, twdi7_F))
-	port map( Input => i7, Output => connect(7));
-
-   -- Netlist
-   U9 : TLU
-	generic map(
-		N => 8,
-		TruthTable => "0001000100011111" &
-		              "10101000101010001010100000000000",
-		TT_size => (4, 5),
-		Node_Index => (0, 1, 2, 3, 
-		               4, 5, 6, 7, -1),
-		pin_names => "i2 i3 i4 i5 i0 i1 i6 i7 nq",
-		delay_param =>
-			((tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi4_nq_R, tpdi4_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi5_nq_R, tpdi5_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi6_nq_R, tpdi6_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi7_nq_R, tpdi7_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXXXXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(2), 
-		Input(1) => connect(3), 
-		Input(2) => connect(4), 
-		Input(3) => connect(5), 
-		Input(4) => connect(0), 
-		Input(5) => connect(1), 
-		Input(6) => connect(6), 
-		Input(7) => connect(7), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_noa2a2a2a24_x1_FTGS of noa2a2a2a24_x1 is
-   for FTGS
-   end for;
-end CFG_noa2a2a2a24_x1_FTGS;
-
-
------ CELL noa2a2a2a24_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa2a2a2a24_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.966 ns;
-      tpdi0_nq_F                     :	Time := 1.049 ns;
-      tpdi1_nq_R                     :	Time := 1.097 ns;
-      tpdi1_nq_F                     :	Time := 1.005 ns;
-      tpdi2_nq_R                     :	Time := 0.867 ns;
-      tpdi2_nq_F                     :	Time := 1.106 ns;
-      tpdi3_nq_R                     :	Time := 0.990 ns;
-      tpdi3_nq_F                     :	Time := 1.061 ns;
-      tpdi4_nq_R                     :	Time := 0.748 ns;
-      tpdi4_nq_F                     :	Time := 1.061 ns;
-      tpdi5_nq_R                     :	Time := 0.649 ns;
-      tpdi5_nq_F                     :	Time := 1.109 ns;
-      tpdi6_nq_R                     :	Time := 0.606 ns;
-      tpdi6_nq_F                     :	Time := 0.999 ns;
-      tpdi7_nq_R                     :	Time := 0.525 ns;
-      tpdi7_nq_F                     :	Time := 1.052 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns;
-      twdi6_R                        :	Time := 0.000 ns;
-      twdi6_F                        :	Time := 0.000 ns;
-      twdi7_R                        :	Time := 0.000 ns;
-      twdi7_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      i6                             :	in    STD_LOGIC;
-      i7                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa2a2a2a24_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of noa2a2a2a24_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi7_nq_F: constant is 
-	"U9/delay_param(7)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi7_nq_R: constant is 
-	"U9/delay_param(7)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is 
-	"U9/delay_param(6)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is 
-	"U9/delay_param(6)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is 
-	"U9/delay_param(5)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is 
-	"U9/delay_param(5)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is 
-	"U9/delay_param(4)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is 
-	"U9/delay_param(4)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is 
-	"U9/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is 
-	"U9/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is 
-	"U9/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is 
-	"U9/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is 
-	"U9/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is 
-	"U9/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is 
-	"U9/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is 
-	"U9/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi7_F: constant is 
-	"U8/delay(TRAN_10), " &
-	"U8/delay(TRAN_1Z), U8/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi7_R: constant is 
-	"U8/delay(TRAN_01), " &
-	"U8/delay(TRAN_0Z), U8/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi6_F: constant is 
-	"U7/delay(TRAN_10), " &
-	"U7/delay(TRAN_1Z), U7/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi6_R: constant is 
-	"U7/delay(TRAN_01), " &
-	"U7/delay(TRAN_0Z), U7/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi5_F: constant is 
-	"U6/delay(TRAN_10), " &
-	"U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi5_R: constant is 
-	"U6/delay(TRAN_01), " &
-	"U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi4_F: constant is 
-	"U5/delay(TRAN_10), " &
-	"U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi4_R: constant is 
-	"U5/delay(TRAN_01), " &
-	"U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); 
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F))
-	port map( Input => i3, Output => connect(3));
-
-   U5 : WIREBUF
-	generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F))
-	port map( Input => i4, Output => connect(4));
-
-   U6 : WIREBUF
-	generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F))
-	port map( Input => i5, Output => connect(5));
-
-   U7 : WIREBUF
-	generic map(delay => (twdi6_R, twdi6_F, twdi6_R, twdi6_R, twdi6_F, twdi6_F))
-	port map( Input => i6, Output => connect(6));
-
-   U8 : WIREBUF
-	generic map(delay => (twdi7_R, twdi7_F, twdi7_R, twdi7_R, twdi7_F, twdi7_F))
-	port map( Input => i7, Output => connect(7));
-
-   -- Netlist
-   U9 : TLU
-	generic map(
-		N => 8,
-		TruthTable => "0001000100011111" &
-		              "10101000101010001010100000000000",
-		TT_size => (4, 5),
-		Node_Index => (0, 1, 2, 3, 
-		               4, 5, 6, 7, -1),
-		pin_names => "i2 i3 i4 i5 i0 i1 i6 i7 nq",
-		delay_param =>
-			((tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi4_nq_R, tpdi4_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi5_nq_R, tpdi5_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi6_nq_R, tpdi6_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi7_nq_R, tpdi7_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXXXXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(2), 
-		Input(1) => connect(3), 
-		Input(2) => connect(4), 
-		Input(3) => connect(5), 
-		Input(4) => connect(0), 
-		Input(5) => connect(1), 
-		Input(6) => connect(6), 
-		Input(7) => connect(7), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_noa2a2a2a24_x4_FTGS of noa2a2a2a24_x4 is
-   for FTGS
-   end for;
-end CFG_noa2a2a2a24_x4_FTGS;
-
-
------ CELL noa2a2a23_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa2a2a23_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.525 ns;
-      tpdi0_nq_F                     :	Time := 0.425 ns;
-      tpdi1_nq_R                     :	Time := 0.643 ns;
-      tpdi1_nq_F                     :	Time := 0.388 ns;
-      tpdi2_nq_R                     :	Time := 0.307 ns;
-      tpdi2_nq_F                     :	Time := 0.479 ns;
-      tpdi3_nq_R                     :	Time := 0.398 ns;
-      tpdi3_nq_F                     :	Time := 0.438 ns;
-      tpdi4_nq_R                     :	Time := 0.250 ns;
-      tpdi4_nq_F                     :	Time := 0.416 ns;
-      tpdi5_nq_R                     :	Time := 0.178 ns;
-      tpdi5_nq_F                     :	Time := 0.464 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa2a2a23_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of noa2a2a23_x1 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is 
-	"U7/delay_param(5)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is 
-	"U7/delay_param(5)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is 
-	"U7/delay_param(4)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is 
-	"U7/delay_param(4)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is 
-	"U7/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is 
-	"U7/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is 
-	"U7/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is 
-	"U7/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is 
-	"U7/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is 
-	"U7/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is 
-	"U7/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is 
-	"U7/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi5_F: constant is 
-	"U6/delay(TRAN_10), " &
-	"U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi5_R: constant is 
-	"U6/delay(TRAN_01), " &
-	"U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi4_F: constant is 
-	"U5/delay(TRAN_10), " &
-	"U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi4_R: constant is 
-	"U5/delay(TRAN_01), " &
-	"U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); 
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F))
-	port map( Input => i3, Output => connect(3));
-
-   U5 : WIREBUF
-	generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F))
-	port map( Input => i4, Output => connect(4));
-
-   U6 : WIREBUF
-	generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F))
-	port map( Input => i5, Output => connect(5));
-
-   -- Netlist
-   U7 : TLU
-	generic map(
-		N => 6,
-		TruthTable => "0001000100011111" &
-		              "10101000",
-		TT_size => (4, 3),
-		Node_Index => (0, 1, 2, 3, 
-		               4, 5, -1),
-		pin_names => "i0 i1 i4 i5 i2 i3 nq",
-		delay_param =>
-			((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi4_nq_R, tpdi4_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi5_nq_R, tpdi5_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(4), 
-		Input(3) => connect(5), 
-		Input(4) => connect(2), 
-		Input(5) => connect(3), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_noa2a2a23_x1_FTGS of noa2a2a23_x1 is
-   for FTGS
-   end for;
-end CFG_noa2a2a23_x1_FTGS;
-
-
------ CELL noa2a2a23_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa2a2a23_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.834 ns;
-      tpdi0_nq_F                     :	Time := 0.814 ns;
-      tpdi1_nq_R                     :	Time := 0.955 ns;
-      tpdi1_nq_F                     :	Time := 0.778 ns;
-      tpdi2_nq_R                     :	Time := 0.620 ns;
-      tpdi2_nq_F                     :	Time := 0.873 ns;
-      tpdi3_nq_R                     :	Time := 0.716 ns;
-      tpdi3_nq_F                     :	Time := 0.833 ns;
-      tpdi4_nq_R                     :	Time := 0.574 ns;
-      tpdi4_nq_F                     :	Time := 0.819 ns;
-      tpdi5_nq_R                     :	Time := 0.496 ns;
-      tpdi5_nq_F                     :	Time := 0.865 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa2a2a23_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of noa2a2a23_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is 
-	"U7/delay_param(5)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is 
-	"U7/delay_param(5)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is 
-	"U7/delay_param(4)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is 
-	"U7/delay_param(4)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is 
-	"U7/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is 
-	"U7/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is 
-	"U7/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is 
-	"U7/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is 
-	"U7/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is 
-	"U7/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is 
-	"U7/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is 
-	"U7/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi5_F: constant is 
-	"U6/delay(TRAN_10), " &
-	"U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi5_R: constant is 
-	"U6/delay(TRAN_01), " &
-	"U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi4_F: constant is 
-	"U5/delay(TRAN_10), " &
-	"U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi4_R: constant is 
-	"U5/delay(TRAN_01), " &
-	"U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); 
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F))
-	port map( Input => i3, Output => connect(3));
-
-   U5 : WIREBUF
-	generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F))
-	port map( Input => i4, Output => connect(4));
-
-   U6 : WIREBUF
-	generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F))
-	port map( Input => i5, Output => connect(5));
-
-   -- Netlist
-   U7 : TLU
-	generic map(
-		N => 6,
-		TruthTable => "0001000100011111" &
-		              "10101000",
-		TT_size => (4, 3),
-		Node_Index => (0, 1, 2, 3, 
-		               4, 5, -1),
-		pin_names => "i0 i1 i4 i5 i2 i3 nq",
-		delay_param =>
-			((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi4_nq_R, tpdi4_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi5_nq_R, tpdi5_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(4), 
-		Input(3) => connect(5), 
-		Input(4) => connect(2), 
-		Input(5) => connect(3), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_noa2a2a23_x4_FTGS of noa2a2a23_x4 is
-   for FTGS
-   end for;
-end CFG_noa2a2a23_x4_FTGS;
-
-
------ CELL noa2a22_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa2a22_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.151 ns;
-      tpdi0_nq_F                     :	Time := 0.327 ns;
-      tpdi1_nq_R                     :	Time := 0.218 ns;
-      tpdi1_nq_F                     :	Time := 0.287 ns;
-      tpdi2_nq_R                     :	Time := 0.284 ns;
-      tpdi2_nq_F                     :	Time := 0.289 ns;
-      tpdi3_nq_R                     :	Time := 0.372 ns;
-      tpdi3_nq_F                     :	Time := 0.256 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa2a22_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of noa2a22_x1 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is 
-	"U5/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is 
-	"U5/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is 
-	"U5/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is 
-	"U5/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is 
-	"U5/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is 
-	"U5/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is 
-	"U5/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is 
-	"U5/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F))
-	port map( Input => i3, Output => connect(3));
-
-   -- Netlist
-   U5 : TLU
-	generic map(
-		N => 4,
-		TruthTable => "1110111011100000",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 i3 nq",
-		delay_param =>
-			((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Input(3) => connect(3), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_noa2a22_x1_FTGS of noa2a22_x1 is
-   for FTGS
-   end for;
-end CFG_noa2a22_x1_FTGS;
-
-
------ CELL noa2a22_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa2a22_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.562 ns;
-      tpdi0_nq_F                     :	Time := 0.745 ns;
-      tpdi1_nq_R                     :	Time := 0.646 ns;
-      tpdi1_nq_F                     :	Time := 0.714 ns;
-      tpdi2_nq_R                     :	Time := 0.701 ns;
-      tpdi2_nq_F                     :	Time := 0.703 ns;
-      tpdi3_nq_R                     :	Time := 0.805 ns;
-      tpdi3_nq_F                     :	Time := 0.677 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa2a22_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of noa2a22_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is 
-	"U5/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is 
-	"U5/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is 
-	"U5/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is 
-	"U5/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is 
-	"U5/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is 
-	"U5/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is 
-	"U5/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is 
-	"U5/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F))
-	port map( Input => i3, Output => connect(3));
-
-   -- Netlist
-   U5 : TLU
-	generic map(
-		N => 4,
-		TruthTable => "1110111011100000",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 i3 nq",
-		delay_param =>
-			((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Input(3) => connect(3), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_noa2a22_x4_FTGS of noa2a22_x4 is
-   for FTGS
-   end for;
-end CFG_noa2a22_x4_FTGS;
-
-
------ CELL noa2ao222_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa2ao222_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.348 ns;
-      tpdi0_nq_F                     :	Time := 0.422 ns;
-      tpdi1_nq_R                     :	Time := 0.440 ns;
-      tpdi1_nq_F                     :	Time := 0.378 ns;
-      tpdi2_nq_R                     :	Time := 0.186 ns;
-      tpdi2_nq_F                     :	Time := 0.473 ns;
-      tpdi3_nq_R                     :	Time := 0.256 ns;
-      tpdi3_nq_F                     :	Time := 0.459 ns;
-      tpdi4_nq_R                     :	Time := 0.240 ns;
-      tpdi4_nq_F                     :	Time := 0.309 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa2ao222_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of noa2ao222_x1 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is 
-	"U6/delay_param(4)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is 
-	"U6/delay_param(4)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is 
-	"U6/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is 
-	"U6/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is 
-	"U6/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is 
-	"U6/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is 
-	"U6/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is 
-	"U6/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is 
-	"U6/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is 
-	"U6/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi4_F: constant is 
-	"U5/delay(TRAN_10), " &
-	"U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi4_R: constant is 
-	"U5/delay(TRAN_01), " &
-	"U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F))
-	port map( Input => i3, Output => connect(3));
-
-   U5 : WIREBUF
-	generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F))
-	port map( Input => i4, Output => connect(4));
-
-   -- Netlist
-   U6 : TLU
-	generic map(
-		N => 5,
-		TruthTable => "11101010111010101110101000000000",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 i3 i4 nq",
-		delay_param =>
-			((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi4_nq_R, tpdi4_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Input(3) => connect(3), 
-		Input(4) => connect(4), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_noa2ao222_x1_FTGS of noa2ao222_x1 is
-   for FTGS
-   end for;
-end CFG_noa2ao222_x1_FTGS;
-
-
------ CELL noa2ao222_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa2ao222_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.684 ns;
-      tpdi0_nq_F                     :	Time := 0.801 ns;
-      tpdi1_nq_R                     :	Time := 0.780 ns;
-      tpdi1_nq_F                     :	Time := 0.758 ns;
-      tpdi2_nq_R                     :	Time := 0.638 ns;
-      tpdi2_nq_F                     :	Time := 0.809 ns;
-      tpdi3_nq_R                     :	Time := 0.732 ns;
-      tpdi3_nq_F                     :	Time := 0.795 ns;
-      tpdi4_nq_R                     :	Time := 0.718 ns;
-      tpdi4_nq_F                     :	Time := 0.664 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa2ao222_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of noa2ao222_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is 
-	"U6/delay_param(4)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is 
-	"U6/delay_param(4)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is 
-	"U6/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is 
-	"U6/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is 
-	"U6/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is 
-	"U6/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is 
-	"U6/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is 
-	"U6/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is 
-	"U6/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is 
-	"U6/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi4_F: constant is 
-	"U5/delay(TRAN_10), " &
-	"U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi4_R: constant is 
-	"U5/delay(TRAN_01), " &
-	"U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F))
-	port map( Input => i3, Output => connect(3));
-
-   U5 : WIREBUF
-	generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F))
-	port map( Input => i4, Output => connect(4));
-
-   -- Netlist
-   U6 : TLU
-	generic map(
-		N => 5,
-		TruthTable => "11101010111010101110101000000000",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 i3 i4 nq",
-		delay_param =>
-			((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi4_nq_R, tpdi4_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Input(3) => connect(3), 
-		Input(4) => connect(4), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_noa2ao222_x4_FTGS of noa2ao222_x4 is
-   for FTGS
-   end for;
-end CFG_noa2ao222_x4_FTGS;
-
-
------ CELL noa3ao322_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa3ao322_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.396 ns;
-      tpdi0_nq_F                     :	Time := 0.616 ns;
-      tpdi1_nq_R                     :	Time := 0.486 ns;
-      tpdi1_nq_F                     :	Time := 0.552 ns;
-      tpdi2_nq_R                     :	Time := 0.546 ns;
-      tpdi2_nq_F                     :	Time := 0.488 ns;
-      tpdi3_nq_R                     :	Time := 0.196 ns;
-      tpdi3_nq_F                     :	Time := 0.599 ns;
-      tpdi4_nq_R                     :	Time := 0.264 ns;
-      tpdi4_nq_F                     :	Time := 0.608 ns;
-      tpdi5_nq_R                     :	Time := 0.328 ns;
-      tpdi5_nq_F                     :	Time := 0.581 ns;
-      tpdi6_nq_R                     :	Time := 0.246 ns;
-      tpdi6_nq_F                     :	Time := 0.311 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns;
-      twdi6_R                        :	Time := 0.000 ns;
-      twdi6_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      i6                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa3ao322_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of noa3ao322_x1 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is 
-	"U8/delay_param(6)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is 
-	"U8/delay_param(6)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is 
-	"U8/delay_param(5)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is 
-	"U8/delay_param(5)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is 
-	"U8/delay_param(4)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is 
-	"U8/delay_param(4)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is 
-	"U8/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is 
-	"U8/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is 
-	"U8/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is 
-	"U8/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is 
-	"U8/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is 
-	"U8/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is 
-	"U8/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is 
-	"U8/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi6_F: constant is 
-	"U7/delay(TRAN_10), " &
-	"U7/delay(TRAN_1Z), U7/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi6_R: constant is 
-	"U7/delay(TRAN_01), " &
-	"U7/delay(TRAN_0Z), U7/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi5_F: constant is 
-	"U6/delay(TRAN_10), " &
-	"U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi5_R: constant is 
-	"U6/delay(TRAN_01), " &
-	"U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi4_F: constant is 
-	"U5/delay(TRAN_10), " &
-	"U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi4_R: constant is 
-	"U5/delay(TRAN_01), " &
-	"U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); 
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F))
-	port map( Input => i3, Output => connect(3));
-
-   U5 : WIREBUF
-	generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F))
-	port map( Input => i4, Output => connect(4));
-
-   U6 : WIREBUF
-	generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F))
-	port map( Input => i5, Output => connect(5));
-
-   U7 : WIREBUF
-	generic map(delay => (twdi6_R, twdi6_F, twdi6_R, twdi6_R, twdi6_F, twdi6_F))
-	port map( Input => i6, Output => connect(6));
-
-   -- Netlist
-   U8 : TLU
-	generic map(
-		N => 7,
-		TruthTable => "0001010101010101" &
-		              "1010101010101000",
-		TT_size => (4, 4),
-		Node_Index => (0, 1, 2, 3, 
-		               4, 5, 6, -1),
-		pin_names => "i3 i4 i5 i6 i0 i1 i2 nq",
-		delay_param =>
-			((tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi4_nq_R, tpdi4_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi5_nq_R, tpdi5_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi6_nq_R, tpdi6_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXXXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(3), 
-		Input(1) => connect(4), 
-		Input(2) => connect(5), 
-		Input(3) => connect(6), 
-		Input(4) => connect(0), 
-		Input(5) => connect(1), 
-		Input(6) => connect(2), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_noa3ao322_x1_FTGS of noa3ao322_x1 is
-   for FTGS
-   end for;
-end CFG_noa3ao322_x1_FTGS;
-
-
------ CELL noa3ao322_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa3ao322_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.819 ns;
-      tpdi0_nq_F                     :	Time := 0.987 ns;
-      tpdi1_nq_R                     :	Time := 0.914 ns;
-      tpdi1_nq_F                     :	Time := 0.931 ns;
-      tpdi2_nq_R                     :	Time := 0.990 ns;
-      tpdi2_nq_F                     :	Time := 0.874 ns;
-      tpdi3_nq_R                     :	Time := 0.729 ns;
-      tpdi3_nq_F                     :	Time := 0.926 ns;
-      tpdi4_nq_R                     :	Time := 0.821 ns;
-      tpdi4_nq_F                     :	Time := 0.924 ns;
-      tpdi5_nq_R                     :	Time := 0.907 ns;
-      tpdi5_nq_F                     :	Time := 0.900 ns;
-      tpdi6_nq_R                     :	Time := 0.738 ns;
-      tpdi6_nq_F                     :	Time := 0.718 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns;
-      twdi6_R                        :	Time := 0.000 ns;
-      twdi6_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      i6                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa3ao322_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of noa3ao322_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is 
-	"U8/delay_param(6)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is 
-	"U8/delay_param(6)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is 
-	"U8/delay_param(5)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is 
-	"U8/delay_param(5)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is 
-	"U8/delay_param(4)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is 
-	"U8/delay_param(4)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is 
-	"U8/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is 
-	"U8/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is 
-	"U8/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is 
-	"U8/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is 
-	"U8/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is 
-	"U8/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is 
-	"U8/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is 
-	"U8/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi6_F: constant is 
-	"U7/delay(TRAN_10), " &
-	"U7/delay(TRAN_1Z), U7/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi6_R: constant is 
-	"U7/delay(TRAN_01), " &
-	"U7/delay(TRAN_0Z), U7/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi5_F: constant is 
-	"U6/delay(TRAN_10), " &
-	"U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi5_R: constant is 
-	"U6/delay(TRAN_01), " &
-	"U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi4_F: constant is 
-	"U5/delay(TRAN_10), " &
-	"U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi4_R: constant is 
-	"U5/delay(TRAN_01), " &
-	"U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); 
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F))
-	port map( Input => i3, Output => connect(3));
-
-   U5 : WIREBUF
-	generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F))
-	port map( Input => i4, Output => connect(4));
-
-   U6 : WIREBUF
-	generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F))
-	port map( Input => i5, Output => connect(5));
-
-   U7 : WIREBUF
-	generic map(delay => (twdi6_R, twdi6_F, twdi6_R, twdi6_R, twdi6_F, twdi6_F))
-	port map( Input => i6, Output => connect(6));
-
-   -- Netlist
-   U8 : TLU
-	generic map(
-		N => 7,
-		TruthTable => "0001010101010101" &
-		              "1010101010101000",
-		TT_size => (4, 4),
-		Node_Index => (0, 1, 2, 3, 
-		               4, 5, 6, -1),
-		pin_names => "i3 i4 i5 i6 i0 i1 i2 nq",
-		delay_param =>
-			((tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi4_nq_R, tpdi4_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi5_nq_R, tpdi5_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi6_nq_R, tpdi6_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXXXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(3), 
-		Input(1) => connect(4), 
-		Input(2) => connect(5), 
-		Input(3) => connect(6), 
-		Input(4) => connect(0), 
-		Input(5) => connect(1), 
-		Input(6) => connect(2), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_noa3ao322_x4_FTGS of noa3ao322_x4 is
-   for FTGS
-   end for;
-end CFG_noa3ao322_x4_FTGS;
-
-
------ CELL noa22_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa22_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.151 ns;
-      tpdi0_nq_F                     :	Time := 0.327 ns;
-      tpdi1_nq_R                     :	Time := 0.218 ns;
-      tpdi1_nq_F                     :	Time := 0.287 ns;
-      tpdi2_nq_R                     :	Time := 0.218 ns;
-      tpdi2_nq_F                     :	Time := 0.241 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa22_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of noa22_x1 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is 
-	"U4/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is 
-	"U4/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is 
-	"U4/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is 
-	"U4/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is 
-	"U4/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is 
-	"U4/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   -- Netlist
-   U4 : TLU
-	generic map(
-		N => 3,
-		TruthTable => "10101000",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 nq",
-		delay_param =>
-			((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_noa22_x1_FTGS of noa22_x1 is
-   for FTGS
-   end for;
-end CFG_noa22_x1_FTGS;
-
-
------ CELL noa22_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa22_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.550 ns;
-      tpdi0_nq_F                     :	Time := 0.740 ns;
-      tpdi1_nq_R                     :	Time := 0.643 ns;
-      tpdi1_nq_F                     :	Time := 0.709 ns;
-      tpdi2_nq_R                     :	Time := 0.610 ns;
-      tpdi2_nq_F                     :	Time := 0.646 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa22_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of noa22_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is 
-	"U4/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is 
-	"U4/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is 
-	"U4/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is 
-	"U4/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is 
-	"U4/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is 
-	"U4/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   -- Netlist
-   U4 : TLU
-	generic map(
-		N => 3,
-		TruthTable => "10101000",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 nq",
-		delay_param =>
-			((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_noa22_x4_FTGS of noa22_x4 is
-   for FTGS
-   end for;
-end CFG_noa22_x4_FTGS;
-
-
------ CELL nts_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nts_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd_nq_R                    :	Time := 0.249 ns;
-      tpdcmd_nq_F                    :	Time := 0.041 ns;
-      tpdcmd_nq_LZ                   :	Time := 0.249 ns;
-      tpdcmd_nq_HZ                   :	Time := 0.041 ns;
-      tpdi_nq_R                      :	Time := 0.169 ns;
-      tpdi_nq_F                      :	Time := 0.201 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      cmd                            :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nts_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of nts_x1 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdcmd_nq_HZ: constant is 
-	"U3/delay_param(1)(TRAN_1Z)";
-   attribute PROPAGATE_VALUE of tpdcmd_nq_LZ: constant is 
-	"U3/delay_param(1)(TRAN_0Z)";
-   attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is 
-	"U3/delay_param(1)(TRAN_10), " &
-	"U3/delay_param(1)(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is 
-	"U3/delay_param(1)(TRAN_01), " &
-	"U3/delay_param(1)(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of tpdi_nq_F: constant is 
-	"U3/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi_nq_R: constant is 
-	"U3/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdcmd_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdcmd_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F))
-	port map( Input => i, Output => connect(1));
-
-   U2 : WIREBUF
-	generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F))
-	port map( Input => cmd, Output => connect(0));
-
-   -- Netlist
-   U3 : TLU
-	generic map(
-		N => 2,
-		TruthTable => "Z1Z0",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i cmd nq",
-		delay_param =>
-			((tpdi_nq_R, tpdi_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdcmd_nq_R, tpdcmd_nq_F, tpdcmd_nq_LZ, tpdcmd_nq_R, tpdcmd_nq_HZ, tpdcmd_nq_F)),
-		InMapZ => "XX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(1), 
-		Input(1) => connect(0), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_nts_x1_FTGS of nts_x1 is
-   for FTGS
-   end for;
-end CFG_nts_x1_FTGS;
-
-
------ CELL nts_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nts_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd_nq_R                    :	Time := 0.330 ns;
-      tpdcmd_nq_F                    :	Time := 0.033 ns;
-      tpdcmd_nq_LZ                   :	Time := 0.330 ns;
-      tpdcmd_nq_HZ                   :	Time := 0.033 ns;
-      tpdi_nq_R                      :	Time := 0.167 ns;
-      tpdi_nq_F                      :	Time := 0.201 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      cmd                            :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nts_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of nts_x2 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdcmd_nq_HZ: constant is 
-	"U3/delay_param(1)(TRAN_1Z)";
-   attribute PROPAGATE_VALUE of tpdcmd_nq_LZ: constant is 
-	"U3/delay_param(1)(TRAN_0Z)";
-   attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is 
-	"U3/delay_param(1)(TRAN_10), " &
-	"U3/delay_param(1)(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is 
-	"U3/delay_param(1)(TRAN_01), " &
-	"U3/delay_param(1)(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of tpdi_nq_F: constant is 
-	"U3/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi_nq_R: constant is 
-	"U3/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdcmd_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdcmd_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F))
-	port map( Input => i, Output => connect(1));
-
-   U2 : WIREBUF
-	generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F))
-	port map( Input => cmd, Output => connect(0));
-
-   -- Netlist
-   U3 : TLU
-	generic map(
-		N => 2,
-		TruthTable => "Z1Z0",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i cmd nq",
-		delay_param =>
-			((tpdi_nq_R, tpdi_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdcmd_nq_R, tpdcmd_nq_F, tpdcmd_nq_LZ, tpdcmd_nq_R, tpdcmd_nq_HZ, tpdcmd_nq_F)),
-		InMapZ => "XX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(1), 
-		Input(1) => connect(0), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_nts_x2_FTGS of nts_x2 is
-   for FTGS
-   end for;
-end CFG_nts_x2_FTGS;
-
-
------ CELL nxr2_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nxr2_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.288 ns;
-      tpdi0_nq_F                     :	Time := 0.293 ns;
-      tpdi1_nq_R                     :	Time := 0.156 ns;
-      tpdi1_nq_F                     :	Time := 0.327 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nxr2_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of nxr2_x1 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is 
-	"U3/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is 
-	"U3/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is 
-	"U3/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is 
-	"U3/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   -- Netlist
-   U3 : TLU
-	generic map(
-		N => 2,
-		TruthTable => "1001",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 nq",
-		delay_param =>
-			((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_nxr2_x1_FTGS of nxr2_x1 is
-   for FTGS
-   end for;
-end CFG_nxr2_x1_FTGS;
-
-
------ CELL nxr2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nxr2_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.522 ns;
-      tpdi0_nq_F                     :	Time := 0.553 ns;
-      tpdi1_nq_R                     :	Time := 0.553 ns;
-      tpdi1_nq_F                     :	Time := 0.542 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nxr2_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of nxr2_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is 
-	"U3/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is 
-	"U3/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is 
-	"U3/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is 
-	"U3/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   -- Netlist
-   U3 : TLU
-	generic map(
-		N => 2,
-		TruthTable => "1001",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 nq",
-		delay_param =>
-			((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Output => nq);
-
-
-end FTGS;
-
-configuration CFG_nxr2_x4_FTGS of nxr2_x4 is
-   for FTGS
-   end for;
-end CFG_nxr2_x4_FTGS;
-
-
------ CELL o2_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity o2_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.406 ns;
-      tpdi0_q_F                      :	Time := 0.310 ns;
-      tpdi1_q_R                      :	Time := 0.335 ns;
-      tpdi1_q_F                      :	Time := 0.364 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end o2_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of o2_x2 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U3/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U3/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U3/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U3/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   -- Netlist
-   U3 : TLU
-	generic map(
-		N => 2,
-		TruthTable => "0111",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 q",
-		delay_param =>
-			((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_o2_x2_FTGS of o2_x2 is
-   for FTGS
-   end for;
-end CFG_o2_x2_FTGS;
-
-
------ CELL o2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity o2_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.491 ns;
-      tpdi0_q_F                      :	Time := 0.394 ns;
-      tpdi1_q_R                      :	Time := 0.427 ns;
-      tpdi1_q_F                      :	Time := 0.464 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end o2_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of o2_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U3/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U3/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U3/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U3/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   -- Netlist
-   U3 : TLU
-	generic map(
-		N => 2,
-		TruthTable => "0111",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 q",
-		delay_param =>
-			((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_o2_x4_FTGS of o2_x4 is
-   for FTGS
-   end for;
-end CFG_o2_x4_FTGS;
-
-
------ CELL o3_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity o3_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.494 ns;
-      tpdi0_q_F                      :	Time := 0.407 ns;
-      tpdi1_q_R                      :	Time := 0.430 ns;
-      tpdi1_q_F                      :	Time := 0.482 ns;
-      tpdi2_q_R                      :	Time := 0.360 ns;
-      tpdi2_q_F                      :	Time := 0.506 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end o3_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of o3_x2 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is 
-	"U4/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is 
-	"U4/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U4/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U4/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U4/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U4/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   -- Netlist
-   U4 : TLU
-	generic map(
-		N => 3,
-		TruthTable => "01111111",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 q",
-		delay_param =>
-			((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_o3_x2_FTGS of o3_x2 is
-   for FTGS
-   end for;
-end CFG_o3_x2_FTGS;
-
-
------ CELL o3_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity o3_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.569 ns;
-      tpdi0_q_F                      :	Time := 0.501 ns;
-      tpdi1_q_R                      :	Time := 0.510 ns;
-      tpdi1_q_F                      :	Time := 0.585 ns;
-      tpdi2_q_R                      :	Time := 0.447 ns;
-      tpdi2_q_F                      :	Time := 0.622 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end o3_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of o3_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is 
-	"U4/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is 
-	"U4/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U4/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U4/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U4/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U4/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   -- Netlist
-   U4 : TLU
-	generic map(
-		N => 3,
-		TruthTable => "01111111",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 q",
-		delay_param =>
-			((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_o3_x4_FTGS of o3_x4 is
-   for FTGS
-   end for;
-end CFG_o3_x4_FTGS;
-
-
------ CELL o4_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity o4_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.508 ns;
-      tpdi0_q_F                      :	Time := 0.601 ns;
-      tpdi1_q_R                      :	Time := 0.446 ns;
-      tpdi1_q_F                      :	Time := 0.631 ns;
-      tpdi2_q_R                      :	Time := 0.567 ns;
-      tpdi2_q_F                      :	Time := 0.531 ns;
-      tpdi3_q_R                      :	Time := 0.378 ns;
-      tpdi3_q_F                      :	Time := 0.626 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end o4_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of o4_x2 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_q_F: constant is 
-	"U5/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi3_q_R: constant is 
-	"U5/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is 
-	"U5/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is 
-	"U5/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U5/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U5/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U5/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U5/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F))
-	port map( Input => i3, Output => connect(3));
-
-   -- Netlist
-   U5 : TLU
-	generic map(
-		N => 4,
-		TruthTable => "0111111111111111",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 i3 q",
-		delay_param =>
-			((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Input(3) => connect(3), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_o4_x2_FTGS of o4_x2 is
-   for FTGS
-   end for;
-end CFG_o4_x2_FTGS;
-
-
------ CELL o4_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity o4_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.574 ns;
-      tpdi0_q_F                      :	Time := 0.638 ns;
-      tpdi1_q_R                      :	Time := 0.492 ns;
-      tpdi1_q_F                      :	Time := 0.650 ns;
-      tpdi2_q_R                      :	Time := 0.649 ns;
-      tpdi2_q_F                      :	Time := 0.611 ns;
-      tpdi3_q_R                      :	Time := 0.721 ns;
-      tpdi3_q_F                      :	Time := 0.536 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end o4_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of o4_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_q_F: constant is 
-	"U5/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi3_q_R: constant is 
-	"U5/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is 
-	"U5/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is 
-	"U5/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U5/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U5/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U5/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U5/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F))
-	port map( Input => i3, Output => connect(3));
-
-   -- Netlist
-   U5 : TLU
-	generic map(
-		N => 4,
-		TruthTable => "0111111111111111",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 i3 q",
-		delay_param =>
-			((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Input(3) => connect(3), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_o4_x4_FTGS of o4_x4 is
-   for FTGS
-   end for;
-end CFG_o4_x4_FTGS;
-
-
------ CELL oa2a2a2a24_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa2a2a2a24_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.780 ns;
-      tpdi0_q_F                      :	Time := 0.797 ns;
-      tpdi1_q_R                      :	Time := 0.909 ns;
-      tpdi1_q_F                      :	Time := 0.753 ns;
-      tpdi2_q_R                      :	Time := 0.682 ns;
-      tpdi2_q_F                      :	Time := 0.856 ns;
-      tpdi3_q_R                      :	Time := 0.803 ns;
-      tpdi3_q_F                      :	Time := 0.810 ns;
-      tpdi4_q_R                      :	Time := 0.565 ns;
-      tpdi4_q_F                      :	Time := 0.813 ns;
-      tpdi5_q_R                      :	Time := 0.467 ns;
-      tpdi5_q_F                      :	Time := 0.861 ns;
-      tpdi6_q_R                      :	Time := 0.426 ns;
-      tpdi6_q_F                      :	Time := 0.748 ns;
-      tpdi7_q_R                      :	Time := 0.346 ns;
-      tpdi7_q_F                      :	Time := 0.800 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns;
-      twdi6_R                        :	Time := 0.000 ns;
-      twdi6_F                        :	Time := 0.000 ns;
-      twdi7_R                        :	Time := 0.000 ns;
-      twdi7_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      i6                             :	in    STD_LOGIC;
-      i7                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa2a2a2a24_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of oa2a2a2a24_x2 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_q_F: constant is 
-	"U9/delay_param(7)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi3_q_R: constant is 
-	"U9/delay_param(7)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is 
-	"U9/delay_param(6)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is 
-	"U9/delay_param(6)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U9/delay_param(5)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U9/delay_param(5)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U9/delay_param(4)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U9/delay_param(4)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi7_q_F: constant is 
-	"U9/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi7_q_R: constant is 
-	"U9/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi6_q_F: constant is 
-	"U9/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi6_q_R: constant is 
-	"U9/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi5_q_F: constant is 
-	"U9/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi5_q_R: constant is 
-	"U9/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi4_q_F: constant is 
-	"U9/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi4_q_R: constant is 
-	"U9/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi7_F: constant is 
-	"U8/delay(TRAN_10), " &
-	"U8/delay(TRAN_1Z), U8/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi7_R: constant is 
-	"U8/delay(TRAN_01), " &
-	"U8/delay(TRAN_0Z), U8/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi6_F: constant is 
-	"U7/delay(TRAN_10), " &
-	"U7/delay(TRAN_1Z), U7/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi6_R: constant is 
-	"U7/delay(TRAN_01), " &
-	"U7/delay(TRAN_0Z), U7/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi5_F: constant is 
-	"U6/delay(TRAN_10), " &
-	"U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi5_R: constant is 
-	"U6/delay(TRAN_01), " &
-	"U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi4_F: constant is 
-	"U5/delay(TRAN_10), " &
-	"U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi4_R: constant is 
-	"U5/delay(TRAN_01), " &
-	"U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); 
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F))
-	port map( Input => i3, Output => connect(3));
-
-   U5 : WIREBUF
-	generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F))
-	port map( Input => i4, Output => connect(4));
-
-   U6 : WIREBUF
-	generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F))
-	port map( Input => i5, Output => connect(5));
-
-   U7 : WIREBUF
-	generic map(delay => (twdi6_R, twdi6_F, twdi6_R, twdi6_R, twdi6_F, twdi6_F))
-	port map( Input => i6, Output => connect(6));
-
-   U8 : WIREBUF
-	generic map(delay => (twdi7_R, twdi7_F, twdi7_R, twdi7_R, twdi7_F, twdi7_F))
-	port map( Input => i7, Output => connect(7));
-
-   -- Netlist
-   U9 : TLU
-	generic map(
-		N => 8,
-		TruthTable => "0001000100011111" &
-		              "01010111010101110101011111111111",
-		TT_size => (4, 5),
-		Node_Index => (0, 1, 2, 3, 
-		               4, 5, 6, 7, -1),
-		pin_names => "i4 i5 i6 i7 i0 i1 i2 i3 q",
-		delay_param =>
-			((tpdi4_q_R, tpdi4_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi5_q_R, tpdi5_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi6_q_R, tpdi6_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi7_q_R, tpdi7_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXXXXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(4), 
-		Input(1) => connect(5), 
-		Input(2) => connect(6), 
-		Input(3) => connect(7), 
-		Input(4) => connect(0), 
-		Input(5) => connect(1), 
-		Input(6) => connect(2), 
-		Input(7) => connect(3), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_oa2a2a2a24_x2_FTGS of oa2a2a2a24_x2 is
-   for FTGS
-   end for;
-end CFG_oa2a2a2a24_x2_FTGS;
-
-
------ CELL oa2a2a2a24_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa2a2a2a24_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.823 ns;
-      tpdi0_q_F                      :	Time := 0.879 ns;
-      tpdi1_q_R                      :	Time := 0.955 ns;
-      tpdi1_q_F                      :	Time := 0.835 ns;
-      tpdi2_q_R                      :	Time := 0.726 ns;
-      tpdi2_q_F                      :	Time := 0.940 ns;
-      tpdi3_q_R                      :	Time := 0.851 ns;
-      tpdi3_q_F                      :	Time := 0.895 ns;
-      tpdi4_q_R                      :	Time := 0.619 ns;
-      tpdi4_q_F                      :	Time := 0.902 ns;
-      tpdi5_q_R                      :	Time := 0.515 ns;
-      tpdi5_q_F                      :	Time := 0.949 ns;
-      tpdi6_q_R                      :	Time := 0.487 ns;
-      tpdi6_q_F                      :	Time := 0.845 ns;
-      tpdi7_q_R                      :	Time := 0.399 ns;
-      tpdi7_q_F                      :	Time := 0.895 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns;
-      twdi6_R                        :	Time := 0.000 ns;
-      twdi6_F                        :	Time := 0.000 ns;
-      twdi7_R                        :	Time := 0.000 ns;
-      twdi7_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      i6                             :	in    STD_LOGIC;
-      i7                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa2a2a2a24_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of oa2a2a2a24_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_q_F: constant is 
-	"U9/delay_param(7)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi3_q_R: constant is 
-	"U9/delay_param(7)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is 
-	"U9/delay_param(6)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is 
-	"U9/delay_param(6)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U9/delay_param(5)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U9/delay_param(5)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U9/delay_param(4)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U9/delay_param(4)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi7_q_F: constant is 
-	"U9/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi7_q_R: constant is 
-	"U9/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi6_q_F: constant is 
-	"U9/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi6_q_R: constant is 
-	"U9/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi5_q_F: constant is 
-	"U9/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi5_q_R: constant is 
-	"U9/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi4_q_F: constant is 
-	"U9/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi4_q_R: constant is 
-	"U9/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi7_F: constant is 
-	"U8/delay(TRAN_10), " &
-	"U8/delay(TRAN_1Z), U8/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi7_R: constant is 
-	"U8/delay(TRAN_01), " &
-	"U8/delay(TRAN_0Z), U8/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi6_F: constant is 
-	"U7/delay(TRAN_10), " &
-	"U7/delay(TRAN_1Z), U7/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi6_R: constant is 
-	"U7/delay(TRAN_01), " &
-	"U7/delay(TRAN_0Z), U7/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi5_F: constant is 
-	"U6/delay(TRAN_10), " &
-	"U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi5_R: constant is 
-	"U6/delay(TRAN_01), " &
-	"U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi4_F: constant is 
-	"U5/delay(TRAN_10), " &
-	"U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi4_R: constant is 
-	"U5/delay(TRAN_01), " &
-	"U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); 
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F))
-	port map( Input => i3, Output => connect(3));
-
-   U5 : WIREBUF
-	generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F))
-	port map( Input => i4, Output => connect(4));
-
-   U6 : WIREBUF
-	generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F))
-	port map( Input => i5, Output => connect(5));
-
-   U7 : WIREBUF
-	generic map(delay => (twdi6_R, twdi6_F, twdi6_R, twdi6_R, twdi6_F, twdi6_F))
-	port map( Input => i6, Output => connect(6));
-
-   U8 : WIREBUF
-	generic map(delay => (twdi7_R, twdi7_F, twdi7_R, twdi7_R, twdi7_F, twdi7_F))
-	port map( Input => i7, Output => connect(7));
-
-   -- Netlist
-   U9 : TLU
-	generic map(
-		N => 8,
-		TruthTable => "0001000100011111" &
-		              "01010111010101110101011111111111",
-		TT_size => (4, 5),
-		Node_Index => (0, 1, 2, 3, 
-		               4, 5, 6, 7, -1),
-		pin_names => "i4 i5 i6 i7 i0 i1 i2 i3 q",
-		delay_param =>
-			((tpdi4_q_R, tpdi4_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi5_q_R, tpdi5_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi6_q_R, tpdi6_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi7_q_R, tpdi7_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXXXXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(4), 
-		Input(1) => connect(5), 
-		Input(2) => connect(6), 
-		Input(3) => connect(7), 
-		Input(4) => connect(0), 
-		Input(5) => connect(1), 
-		Input(6) => connect(2), 
-		Input(7) => connect(3), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_oa2a2a2a24_x4_FTGS of oa2a2a2a24_x4 is
-   for FTGS
-   end for;
-end CFG_oa2a2a2a24_x4_FTGS;
-
-
------ CELL oa2a2a23_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa2a2a23_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.653 ns;
-      tpdi0_q_F                      :	Time := 0.578 ns;
-      tpdi1_q_R                      :	Time := 0.775 ns;
-      tpdi1_q_F                      :	Time := 0.542 ns;
-      tpdi2_q_R                      :	Time := 0.441 ns;
-      tpdi2_q_F                      :	Time := 0.639 ns;
-      tpdi3_q_R                      :	Time := 0.540 ns;
-      tpdi3_q_F                      :	Time := 0.600 ns;
-      tpdi4_q_R                      :	Time := 0.402 ns;
-      tpdi4_q_F                      :	Time := 0.591 ns;
-      tpdi5_q_R                      :	Time := 0.321 ns;
-      tpdi5_q_F                      :	Time := 0.636 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa2a2a23_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of oa2a2a23_x2 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U7/delay_param(5)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U7/delay_param(5)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U7/delay_param(4)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U7/delay_param(4)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi5_q_F: constant is 
-	"U7/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi5_q_R: constant is 
-	"U7/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi4_q_F: constant is 
-	"U7/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi4_q_R: constant is 
-	"U7/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi3_q_F: constant is 
-	"U7/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi3_q_R: constant is 
-	"U7/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is 
-	"U7/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is 
-	"U7/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi5_F: constant is 
-	"U6/delay(TRAN_10), " &
-	"U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi5_R: constant is 
-	"U6/delay(TRAN_01), " &
-	"U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi4_F: constant is 
-	"U5/delay(TRAN_10), " &
-	"U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi4_R: constant is 
-	"U5/delay(TRAN_01), " &
-	"U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); 
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F))
-	port map( Input => i3, Output => connect(3));
-
-   U5 : WIREBUF
-	generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F))
-	port map( Input => i4, Output => connect(4));
-
-   U6 : WIREBUF
-	generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F))
-	port map( Input => i5, Output => connect(5));
-
-   -- Netlist
-   U7 : TLU
-	generic map(
-		N => 6,
-		TruthTable => "0001000100011111" &
-		              "01010111",
-		TT_size => (4, 3),
-		Node_Index => (0, 1, 2, 3, 
-		               4, 5, -1),
-		pin_names => "i2 i3 i4 i5 i0 i1 q",
-		delay_param =>
-			((tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi4_q_R, tpdi4_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi5_q_R, tpdi5_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(2), 
-		Input(1) => connect(3), 
-		Input(2) => connect(4), 
-		Input(3) => connect(5), 
-		Input(4) => connect(0), 
-		Input(5) => connect(1), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_oa2a2a23_x2_FTGS of oa2a2a23_x2 is
-   for FTGS
-   end for;
-end CFG_oa2a2a23_x2_FTGS;
-
-
------ CELL oa2a2a23_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa2a2a23_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.699 ns;
-      tpdi0_q_F                      :	Time := 0.648 ns;
-      tpdi1_q_R                      :	Time := 0.822 ns;
-      tpdi1_q_F                      :	Time := 0.613 ns;
-      tpdi2_q_R                      :	Time := 0.493 ns;
-      tpdi2_q_F                      :	Time := 0.715 ns;
-      tpdi3_q_R                      :	Time := 0.594 ns;
-      tpdi3_q_F                      :	Time := 0.677 ns;
-      tpdi4_q_R                      :	Time := 0.464 ns;
-      tpdi4_q_F                      :	Time := 0.673 ns;
-      tpdi5_q_R                      :	Time := 0.379 ns;
-      tpdi5_q_F                      :	Time := 0.714 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa2a2a23_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of oa2a2a23_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U7/delay_param(5)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U7/delay_param(5)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U7/delay_param(4)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U7/delay_param(4)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi5_q_F: constant is 
-	"U7/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi5_q_R: constant is 
-	"U7/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi4_q_F: constant is 
-	"U7/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi4_q_R: constant is 
-	"U7/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi3_q_F: constant is 
-	"U7/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi3_q_R: constant is 
-	"U7/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is 
-	"U7/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is 
-	"U7/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi5_F: constant is 
-	"U6/delay(TRAN_10), " &
-	"U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi5_R: constant is 
-	"U6/delay(TRAN_01), " &
-	"U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi4_F: constant is 
-	"U5/delay(TRAN_10), " &
-	"U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi4_R: constant is 
-	"U5/delay(TRAN_01), " &
-	"U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); 
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F))
-	port map( Input => i3, Output => connect(3));
-
-   U5 : WIREBUF
-	generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F))
-	port map( Input => i4, Output => connect(4));
-
-   U6 : WIREBUF
-	generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F))
-	port map( Input => i5, Output => connect(5));
-
-   -- Netlist
-   U7 : TLU
-	generic map(
-		N => 6,
-		TruthTable => "0001000100011111" &
-		              "01010111",
-		TT_size => (4, 3),
-		Node_Index => (0, 1, 2, 3, 
-		               4, 5, -1),
-		pin_names => "i2 i3 i4 i5 i0 i1 q",
-		delay_param =>
-			((tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi4_q_R, tpdi4_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi5_q_R, tpdi5_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(2), 
-		Input(1) => connect(3), 
-		Input(2) => connect(4), 
-		Input(3) => connect(5), 
-		Input(4) => connect(0), 
-		Input(5) => connect(1), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_oa2a2a23_x4_FTGS of oa2a2a23_x4 is
-   for FTGS
-   end for;
-end CFG_oa2a2a23_x4_FTGS;
-
-
------ CELL oa2a22_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa2a22_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.403 ns;
-      tpdi0_q_F                      :	Time := 0.564 ns;
-      tpdi1_q_R                      :	Time := 0.495 ns;
-      tpdi1_q_F                      :	Time := 0.534 ns;
-      tpdi2_q_R                      :	Time := 0.646 ns;
-      tpdi2_q_F                      :	Time := 0.487 ns;
-      tpdi3_q_R                      :	Time := 0.537 ns;
-      tpdi3_q_F                      :	Time := 0.512 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa2a22_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of oa2a22_x2 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_q_F: constant is 
-	"U5/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi3_q_R: constant is 
-	"U5/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is 
-	"U5/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is 
-	"U5/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U5/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U5/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U5/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U5/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F))
-	port map( Input => i3, Output => connect(3));
-
-   -- Netlist
-   U5 : TLU
-	generic map(
-		N => 4,
-		TruthTable => "0001000100011111",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 i3 q",
-		delay_param =>
-			((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Input(3) => connect(3), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_oa2a22_x2_FTGS of oa2a22_x2 is
-   for FTGS
-   end for;
-end CFG_oa2a22_x2_FTGS;
-
-
------ CELL oa2a22_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa2a22_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.519 ns;
-      tpdi0_q_F                      :	Time := 0.696 ns;
-      tpdi1_q_R                      :	Time := 0.624 ns;
-      tpdi1_q_F                      :	Time := 0.669 ns;
-      tpdi2_q_R                      :	Time := 0.763 ns;
-      tpdi2_q_F                      :	Time := 0.596 ns;
-      tpdi3_q_R                      :	Time := 0.644 ns;
-      tpdi3_q_F                      :	Time := 0.619 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa2a22_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of oa2a22_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_q_F: constant is 
-	"U5/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi3_q_R: constant is 
-	"U5/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is 
-	"U5/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is 
-	"U5/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U5/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U5/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U5/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U5/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F))
-	port map( Input => i3, Output => connect(3));
-
-   -- Netlist
-   U5 : TLU
-	generic map(
-		N => 4,
-		TruthTable => "0001000100011111",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 i3 q",
-		delay_param =>
-			((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Input(3) => connect(3), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_oa2a22_x4_FTGS of oa2a22_x4 is
-   for FTGS
-   end for;
-end CFG_oa2a22_x4_FTGS;
-
-
------ CELL oa2ao222_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa2ao222_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.495 ns;
-      tpdi0_q_F                      :	Time := 0.581 ns;
-      tpdi1_q_R                      :	Time := 0.598 ns;
-      tpdi1_q_F                      :	Time := 0.539 ns;
-      tpdi2_q_R                      :	Time := 0.464 ns;
-      tpdi2_q_F                      :	Time := 0.604 ns;
-      tpdi3_q_R                      :	Time := 0.556 ns;
-      tpdi3_q_F                      :	Time := 0.578 ns;
-      tpdi4_q_R                      :	Time := 0.558 ns;
-      tpdi4_q_F                      :	Time := 0.453 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa2ao222_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of oa2ao222_x2 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi4_q_F: constant is 
-	"U6/delay_param(4)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi4_q_R: constant is 
-	"U6/delay_param(4)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi3_q_F: constant is 
-	"U6/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi3_q_R: constant is 
-	"U6/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is 
-	"U6/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is 
-	"U6/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U6/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U6/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U6/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U6/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi4_F: constant is 
-	"U5/delay(TRAN_10), " &
-	"U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi4_R: constant is 
-	"U5/delay(TRAN_01), " &
-	"U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F))
-	port map( Input => i3, Output => connect(3));
-
-   U5 : WIREBUF
-	generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F))
-	port map( Input => i4, Output => connect(4));
-
-   -- Netlist
-   U6 : TLU
-	generic map(
-		N => 5,
-		TruthTable => "00010101000101010001010111111111",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 i3 i4 q",
-		delay_param =>
-			((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi4_q_R, tpdi4_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Input(3) => connect(3), 
-		Input(4) => connect(4), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_oa2ao222_x2_FTGS of oa2ao222_x2 is
-   for FTGS
-   end for;
-end CFG_oa2ao222_x2_FTGS;
-
-
------ CELL oa2ao222_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa2ao222_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.553 ns;
-      tpdi0_q_F                      :	Time := 0.657 ns;
-      tpdi1_q_R                      :	Time := 0.662 ns;
-      tpdi1_q_F                      :	Time := 0.616 ns;
-      tpdi2_q_R                      :	Time := 0.552 ns;
-      tpdi2_q_F                      :	Time := 0.693 ns;
-      tpdi3_q_R                      :	Time := 0.640 ns;
-      tpdi3_q_F                      :	Time := 0.660 ns;
-      tpdi4_q_R                      :	Time := 0.656 ns;
-      tpdi4_q_F                      :	Time := 0.529 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa2ao222_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of oa2ao222_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi4_q_F: constant is 
-	"U6/delay_param(4)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi4_q_R: constant is 
-	"U6/delay_param(4)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi3_q_F: constant is 
-	"U6/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi3_q_R: constant is 
-	"U6/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is 
-	"U6/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is 
-	"U6/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U6/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U6/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U6/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U6/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi4_F: constant is 
-	"U5/delay(TRAN_10), " &
-	"U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi4_R: constant is 
-	"U5/delay(TRAN_01), " &
-	"U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F))
-	port map( Input => i3, Output => connect(3));
-
-   U5 : WIREBUF
-	generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F))
-	port map( Input => i4, Output => connect(4));
-
-   -- Netlist
-   U6 : TLU
-	generic map(
-		N => 5,
-		TruthTable => "00010101000101010001010111111111",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 i3 i4 q",
-		delay_param =>
-			((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi4_q_R, tpdi4_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Input(3) => connect(3), 
-		Input(4) => connect(4), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_oa2ao222_x4_FTGS of oa2ao222_x4 is
-   for FTGS
-   end for;
-end CFG_oa2ao222_x4_FTGS;
-
-
------ CELL oa3ao322_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa3ao322_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.638 ns;
-      tpdi0_q_F                      :	Time := 0.820 ns;
-      tpdi1_q_R                      :	Time := 0.735 ns;
-      tpdi1_q_F                      :	Time := 0.764 ns;
-      tpdi2_q_R                      :	Time := 0.806 ns;
-      tpdi2_q_F                      :	Time := 0.707 ns;
-      tpdi3_q_R                      :	Time := 0.560 ns;
-      tpdi3_q_F                      :	Time := 0.765 ns;
-      tpdi4_q_R                      :	Time := 0.649 ns;
-      tpdi4_q_F                      :	Time := 0.760 ns;
-      tpdi5_q_R                      :	Time := 0.734 ns;
-      tpdi5_q_F                      :	Time := 0.734 ns;
-      tpdi6_q_R                      :	Time := 0.563 ns;
-      tpdi6_q_F                      :	Time := 0.540 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns;
-      twdi6_R                        :	Time := 0.000 ns;
-      twdi6_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      i6                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa3ao322_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of oa3ao322_x2 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is 
-	"U8/delay_param(6)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is 
-	"U8/delay_param(6)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U8/delay_param(5)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U8/delay_param(5)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U8/delay_param(4)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U8/delay_param(4)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi6_q_F: constant is 
-	"U8/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi6_q_R: constant is 
-	"U8/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi5_q_F: constant is 
-	"U8/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi5_q_R: constant is 
-	"U8/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi4_q_F: constant is 
-	"U8/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi4_q_R: constant is 
-	"U8/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi3_q_F: constant is 
-	"U8/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi3_q_R: constant is 
-	"U8/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi6_F: constant is 
-	"U7/delay(TRAN_10), " &
-	"U7/delay(TRAN_1Z), U7/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi6_R: constant is 
-	"U7/delay(TRAN_01), " &
-	"U7/delay(TRAN_0Z), U7/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi5_F: constant is 
-	"U6/delay(TRAN_10), " &
-	"U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi5_R: constant is 
-	"U6/delay(TRAN_01), " &
-	"U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi4_F: constant is 
-	"U5/delay(TRAN_10), " &
-	"U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi4_R: constant is 
-	"U5/delay(TRAN_01), " &
-	"U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); 
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F))
-	port map( Input => i3, Output => connect(3));
-
-   U5 : WIREBUF
-	generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F))
-	port map( Input => i4, Output => connect(4));
-
-   U6 : WIREBUF
-	generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F))
-	port map( Input => i5, Output => connect(5));
-
-   U7 : WIREBUF
-	generic map(delay => (twdi6_R, twdi6_F, twdi6_R, twdi6_R, twdi6_F, twdi6_F))
-	port map( Input => i6, Output => connect(6));
-
-   -- Netlist
-   U8 : TLU
-	generic map(
-		N => 7,
-		TruthTable => "0001010101010101" &
-		              "0101010101010111",
-		TT_size => (4, 4),
-		Node_Index => (0, 1, 2, 3, 
-		               4, 5, 6, -1),
-		pin_names => "i3 i4 i5 i6 i0 i1 i2 q",
-		delay_param =>
-			((tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi4_q_R, tpdi4_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi5_q_R, tpdi5_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi6_q_R, tpdi6_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXXXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(3), 
-		Input(1) => connect(4), 
-		Input(2) => connect(5), 
-		Input(3) => connect(6), 
-		Input(4) => connect(0), 
-		Input(5) => connect(1), 
-		Input(6) => connect(2), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_oa3ao322_x2_FTGS of oa3ao322_x2 is
-   for FTGS
-   end for;
-end CFG_oa3ao322_x2_FTGS;
-
-
------ CELL oa3ao322_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa3ao322_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.717 ns;
-      tpdi0_q_F                      :	Time := 0.946 ns;
-      tpdi1_q_R                      :	Time := 0.818 ns;
-      tpdi1_q_F                      :	Time := 0.890 ns;
-      tpdi2_q_R                      :	Time := 0.894 ns;
-      tpdi2_q_F                      :	Time := 0.834 ns;
-      tpdi3_q_R                      :	Time := 0.673 ns;
-      tpdi3_q_F                      :	Time := 0.898 ns;
-      tpdi4_q_R                      :	Time := 0.758 ns;
-      tpdi4_q_F                      :	Time := 0.896 ns;
-      tpdi5_q_R                      :	Time := 0.839 ns;
-      tpdi5_q_F                      :	Time := 0.865 ns;
-      tpdi6_q_R                      :	Time := 0.684 ns;
-      tpdi6_q_F                      :	Time := 0.651 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns;
-      twdi6_R                        :	Time := 0.000 ns;
-      twdi6_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      i6                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa3ao322_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of oa3ao322_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is 
-	"U8/delay_param(6)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is 
-	"U8/delay_param(6)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U8/delay_param(5)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U8/delay_param(5)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U8/delay_param(4)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U8/delay_param(4)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi6_q_F: constant is 
-	"U8/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi6_q_R: constant is 
-	"U8/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi5_q_F: constant is 
-	"U8/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi5_q_R: constant is 
-	"U8/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi4_q_F: constant is 
-	"U8/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi4_q_R: constant is 
-	"U8/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi3_q_F: constant is 
-	"U8/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi3_q_R: constant is 
-	"U8/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi6_F: constant is 
-	"U7/delay(TRAN_10), " &
-	"U7/delay(TRAN_1Z), U7/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi6_R: constant is 
-	"U7/delay(TRAN_01), " &
-	"U7/delay(TRAN_0Z), U7/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi5_F: constant is 
-	"U6/delay(TRAN_10), " &
-	"U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi5_R: constant is 
-	"U6/delay(TRAN_01), " &
-	"U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi4_F: constant is 
-	"U5/delay(TRAN_10), " &
-	"U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi4_R: constant is 
-	"U5/delay(TRAN_01), " &
-	"U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); 
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F))
-	port map( Input => i3, Output => connect(3));
-
-   U5 : WIREBUF
-	generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F))
-	port map( Input => i4, Output => connect(4));
-
-   U6 : WIREBUF
-	generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F))
-	port map( Input => i5, Output => connect(5));
-
-   U7 : WIREBUF
-	generic map(delay => (twdi6_R, twdi6_F, twdi6_R, twdi6_R, twdi6_F, twdi6_F))
-	port map( Input => i6, Output => connect(6));
-
-   -- Netlist
-   U8 : TLU
-	generic map(
-		N => 7,
-		TruthTable => "0001010101010101" &
-		              "0101010101010111",
-		TT_size => (4, 4),
-		Node_Index => (0, 1, 2, 3, 
-		               4, 5, 6, -1),
-		pin_names => "i3 i4 i5 i6 i0 i1 i2 q",
-		delay_param =>
-			((tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi4_q_R, tpdi4_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi5_q_R, tpdi5_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi6_q_R, tpdi6_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXXXXXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(3), 
-		Input(1) => connect(4), 
-		Input(2) => connect(5), 
-		Input(3) => connect(6), 
-		Input(4) => connect(0), 
-		Input(5) => connect(1), 
-		Input(6) => connect(2), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_oa3ao322_x4_FTGS of oa3ao322_x4 is
-   for FTGS
-   end for;
-end CFG_oa3ao322_x4_FTGS;
-
-
------ CELL oa22_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa22_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.390 ns;
-      tpdi0_q_F                      :	Time := 0.555 ns;
-      tpdi1_q_R                      :	Time := 0.488 ns;
-      tpdi1_q_F                      :	Time := 0.525 ns;
-      tpdi2_q_R                      :	Time := 0.438 ns;
-      tpdi2_q_F                      :	Time := 0.454 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa22_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of oa22_x2 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is 
-	"U4/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is 
-	"U4/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U4/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U4/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U4/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U4/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   -- Netlist
-   U4 : TLU
-	generic map(
-		N => 3,
-		TruthTable => "01010111",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 q",
-		delay_param =>
-			((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_oa22_x2_FTGS of oa22_x2 is
-   for FTGS
-   end for;
-end CFG_oa22_x2_FTGS;
-
-
------ CELL oa22_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa22_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.511 ns;
-      tpdi0_q_F                      :	Time := 0.677 ns;
-      tpdi1_q_R                      :	Time := 0.615 ns;
-      tpdi1_q_F                      :	Time := 0.650 ns;
-      tpdi2_q_R                      :	Time := 0.523 ns;
-      tpdi2_q_F                      :	Time := 0.571 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa22_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of oa22_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is 
-	"U4/delay_param(2)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is 
-	"U4/delay_param(2)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U4/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U4/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U4/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U4/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F))
-	port map( Input => i2, Output => connect(2));
-
-   -- Netlist
-   U4 : TLU
-	generic map(
-		N => 3,
-		TruthTable => "01010111",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 i2 q",
-		delay_param =>
-			((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XXX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Input(2) => connect(2), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_oa22_x4_FTGS of oa22_x4 is
-   for FTGS
-   end for;
-end CFG_oa22_x4_FTGS;
-
-
------ CELL on12_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity on12_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.111 ns;
-      tpdi0_q_F                      :	Time := 0.234 ns;
-      tpdi1_q_R                      :	Time := 0.314 ns;
-      tpdi1_q_F                      :	Time := 0.291 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end on12_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of on12_x1 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U3/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U3/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U3/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U3/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   -- Netlist
-   U3 : TLU
-	generic map(
-		N => 2,
-		TruthTable => "1101",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 q",
-		delay_param =>
-			((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_on12_x1_FTGS of on12_x1 is
-   for FTGS
-   end for;
-end CFG_on12_x1_FTGS;
-
-
------ CELL on12_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity on12_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.474 ns;
-      tpdi0_q_F                      :	Time := 0.499 ns;
-      tpdi1_q_R                      :	Time := 0.491 ns;
-      tpdi1_q_F                      :	Time := 0.394 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end on12_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of on12_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U3/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U3/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U3/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U3/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   -- Netlist
-   U3 : TLU
-	generic map(
-		N => 2,
-		TruthTable => "1101",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 q",
-		delay_param =>
-			((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_on12_x4_FTGS of on12_x4 is
-   for FTGS
-   end for;
-end CFG_on12_x4_FTGS;
-
-
------ CELL one_x0 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity one_x0 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False);
-
-   port(
-      q                              :	out   STD_LOGIC := '1');
-end one_x0;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of one_x0 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-
-
-
-begin
-
-   -- Netlist
-   q <= '1';
-
-end FTGS;
-
-configuration CFG_one_x0_FTGS of one_x0 is
-   for FTGS
-   end for;
-end CFG_one_x0_FTGS;
-
-
------ CELL sff1_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity sff1_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdck_q_R                      :	Time := 0.500 ns;
-      tpdck_q_F                      :	Time := 0.500 ns;
-      tsui_ck                        :	Time := 0.585 ns;
-      thck_i                         :	Time := 0.000 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns;
-      twdck_R                        :	Time := 0.000 ns;
-      twdck_F                        :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      ck                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end sff1_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of sff1_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of thck_i: constant is 
-	"U3/constraint_param(1).Check_time";
-   attribute PROPAGATE_VALUE of tsui_ck: constant is 
-	"U3/constraint_param(0).Check_time";
-   attribute PROPAGATE_VALUE of tpdck_q_F: constant is 
-	"U3/delay_param(0)(TRAN_10), " &
-	"U3/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdck_q_R: constant is 
-	"U3/delay_param(0)(TRAN_01), " &
-	"U3/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdck_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdck_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F))
-	port map( Input => i, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdck_R, twdck_F, twdck_R, twdck_R, twdck_F, twdck_F))
-	port map( Input => ck, Output => connect(1));
-
-   -- Netlist
-   U3 : SEQGEN
-	generic map(
-		N_enable => 0,
-		N_clock => 1,
-		N_clear => 0,
-		N_preset => 0,
-		N_data => 1,
-		N_cond_signal => 0,
-		lut_enable => "",
-		lut_clock => "01",
-		lut_clear => "",
-		lut_preset => "",
-		lut_data => "01",
-		TT_size_data => nil_integer_vector,
-		Node_Index_data => nil_integer_vector,
-		lut_next => "NN01NN01",
-		pin_names => "ck i q",
-		delay_param =>
-			((tpdck_q_R, tpdck_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdck_q_R, tpdck_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		constraint_param => 
-			((1, 0, setup_rising_ff, tsui_ck),
-			 (0, 1, hold_rising_ff, thck_i)),
-		InMapZ => "XX",
-		Q_feedback => FALSE,
-		Enable_feedback => FALSE,
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		Constraint_mesg => Timing_mesg,
-		Constraint_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(	Input(0) => connect(1),
-			Input(1) => connect(0),
-			Output => q);
-
-
-end FTGS;
-
-configuration CFG_sff1_x4_FTGS of sff1_x4 is
-   for FTGS
-   end for;
-end CFG_sff1_x4_FTGS;
-
-
------ CELL sff2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity sff2_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdck_q_R                      :	Time := 0.500 ns;
-      tpdck_q_F                      :	Time := 0.500 ns;
-      tsui0_ck                       :	Time := 0.764 ns;
-      thck_i0                        :	Time := 0.000 ns;
-      tsui1_ck                       :	Time := 0.764 ns;
-      thck_i1                        :	Time := 0.000 ns;
-      tsucmd_ck                      :	Time := 0.833 ns;
-      thck_cmd                       :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns;
-      twdck_R                        :	Time := 0.000 ns;
-      twdck_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      cmd                            :	in    STD_LOGIC;
-      ck                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end sff2_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of sff2_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of thck_cmd: constant is 
-	"U5/constraint_param(5).Check_time";
-   attribute PROPAGATE_VALUE of tsucmd_ck: constant is 
-	"U5/constraint_param(4).Check_time";
-   attribute PROPAGATE_VALUE of thck_i1: constant is 
-	"U5/constraint_param(3).Check_time";
-   attribute PROPAGATE_VALUE of tsui1_ck: constant is 
-	"U5/constraint_param(2).Check_time";
-   attribute PROPAGATE_VALUE of thck_i0: constant is 
-	"U5/constraint_param(1).Check_time";
-   attribute PROPAGATE_VALUE of tsui0_ck: constant is 
-	"U5/constraint_param(0).Check_time";
-   attribute PROPAGATE_VALUE of tpdck_q_F: constant is 
-	"U5/delay_param(0)(TRAN_10), " &
-	"U5/delay_param(1)(TRAN_10), U5/delay_param(2)(TRAN_10), " &
-	"U5/delay_param(3)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdck_q_R: constant is 
-	"U5/delay_param(0)(TRAN_01), " &
-	"U5/delay_param(1)(TRAN_01), U5/delay_param(2)(TRAN_01), " &
-	"U5/delay_param(3)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdck_F: constant is 
-	"U4/delay(TRAN_10), " &
-	"U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdck_R: constant is 
-	"U4/delay(TRAN_01), " &
-	"U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdcmd_F: constant is 
-	"U3/delay(TRAN_10), " &
-	"U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdcmd_R: constant is 
-	"U3/delay(TRAN_01), " &
-	"U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   U3 : WIREBUF
-	generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F))
-	port map( Input => cmd, Output => connect(2));
-
-   U4 : WIREBUF
-	generic map(delay => (twdck_R, twdck_F, twdck_R, twdck_R, twdck_F, twdck_F))
-	port map( Input => ck, Output => connect(3));
-
-   -- Netlist
-   U5 : SEQGEN
-	generic map(
-		N_enable => 0,
-		N_clock => 1,
-		N_clear => 0,
-		N_preset => 0,
-		N_data => 3,
-		N_cond_signal => 0,
-		lut_enable => "",
-		lut_clock => "01",
-		lut_clear => "",
-		lut_preset => "",
-		lut_data => "00011011",
-		TT_size_data => nil_integer_vector,
-		Node_Index_data => nil_integer_vector,
-		lut_next => "NN01NN01",
-		pin_names => "ck i0 i1 cmd q",
-		delay_param =>
-			((tpdck_q_R, tpdck_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdck_q_R, tpdck_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdck_q_R, tpdck_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdck_q_R, tpdck_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		constraint_param => 
-			((1, 0, setup_rising_ff, tsui0_ck),
-			 (0, 1, hold_rising_ff, thck_i0),
-			 (2, 0, setup_rising_ff, tsui1_ck),
-			 (0, 2, hold_rising_ff, thck_i1),
-			 (3, 0, setup_rising_ff, tsucmd_ck),
-			 (0, 3, hold_rising_ff, thck_cmd)),
-		InMapZ => "XXXX",
-		Q_feedback => FALSE,
-		Enable_feedback => FALSE,
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		Constraint_mesg => Timing_mesg,
-		Constraint_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(	Input(0) => connect(3),
-			Input(1) => connect(0),
-			Input(2) => connect(1),
-			Input(3) => connect(2),
-			Output => q);
-
-
-end FTGS;
-
-configuration CFG_sff2_x4_FTGS of sff2_x4 is
-   for FTGS
-   end for;
-end CFG_sff2_x4_FTGS;
-
-
------ CELL ts_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity ts_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd_q_R                     :	Time := 0.492 ns;
-      tpdcmd_q_F                     :	Time := 0.409 ns;
-      tpdcmd_q_LZ                    :	Time := 0.492 ns;
-      tpdcmd_q_HZ                    :	Time := 0.409 ns;
-      tpdi_q_R                       :	Time := 0.475 ns;
-      tpdi_q_F                       :	Time := 0.444 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      cmd                            :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end ts_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of ts_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdcmd_q_HZ: constant is 
-	"U3/delay_param(1)(TRAN_1Z)";
-   attribute PROPAGATE_VALUE of tpdcmd_q_LZ: constant is 
-	"U3/delay_param(1)(TRAN_0Z)";
-   attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is 
-	"U3/delay_param(1)(TRAN_10), " &
-	"U3/delay_param(1)(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is 
-	"U3/delay_param(1)(TRAN_01), " &
-	"U3/delay_param(1)(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of tpdi_q_F: constant is 
-	"U3/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi_q_R: constant is 
-	"U3/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdcmd_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdcmd_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F))
-	port map( Input => i, Output => connect(1));
-
-   U2 : WIREBUF
-	generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F))
-	port map( Input => cmd, Output => connect(0));
-
-   -- Netlist
-   U3 : TLU
-	generic map(
-		N => 2,
-		TruthTable => "Z0Z1",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i cmd q",
-		delay_param =>
-			((tpdi_q_R, tpdi_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdcmd_q_R, tpdcmd_q_F, tpdcmd_q_LZ, tpdcmd_q_R, tpdcmd_q_HZ, tpdcmd_q_F)),
-		InMapZ => "XX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(1), 
-		Input(1) => connect(0), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_ts_x4_FTGS of ts_x4 is
-   for FTGS
-   end for;
-end CFG_ts_x4_FTGS;
-
-
------ CELL ts_x8 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity ts_x8 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd_q_R                     :	Time := 0.626 ns;
-      tpdcmd_q_F                     :	Time := 0.466 ns;
-      tpdcmd_q_LZ                    :	Time := 0.626 ns;
-      tpdcmd_q_HZ                    :	Time := 0.466 ns;
-      tpdi_q_R                       :	Time := 0.613 ns;
-      tpdi_q_F                       :	Time := 0.569 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      cmd                            :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end ts_x8;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of ts_x8 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdcmd_q_HZ: constant is 
-	"U3/delay_param(1)(TRAN_1Z)";
-   attribute PROPAGATE_VALUE of tpdcmd_q_LZ: constant is 
-	"U3/delay_param(1)(TRAN_0Z)";
-   attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is 
-	"U3/delay_param(1)(TRAN_10), " &
-	"U3/delay_param(1)(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is 
-	"U3/delay_param(1)(TRAN_01), " &
-	"U3/delay_param(1)(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of tpdi_q_F: constant is 
-	"U3/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi_q_R: constant is 
-	"U3/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdcmd_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdcmd_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F))
-	port map( Input => i, Output => connect(1));
-
-   U2 : WIREBUF
-	generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F))
-	port map( Input => cmd, Output => connect(0));
-
-   -- Netlist
-   U3 : TLU
-	generic map(
-		N => 2,
-		TruthTable => "Z0Z1",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i cmd q",
-		delay_param =>
-			((tpdi_q_R, tpdi_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdcmd_q_R, tpdcmd_q_F, tpdcmd_q_LZ, tpdcmd_q_R, tpdcmd_q_HZ, tpdcmd_q_F)),
-		InMapZ => "XX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(1), 
-		Input(1) => connect(0), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_ts_x8_FTGS of ts_x8 is
-   for FTGS
-   end for;
-end CFG_ts_x8_FTGS;
-
-
------ CELL xr2_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity xr2_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.292 ns;
-      tpdi0_q_F                      :	Time := 0.293 ns;
-      tpdi1_q_R                      :	Time := 0.377 ns;
-      tpdi1_q_F                      :	Time := 0.261 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end xr2_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of xr2_x1 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U3/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U3/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U3/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U3/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   -- Netlist
-   U3 : TLU
-	generic map(
-		N => 2,
-		TruthTable => "0110",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 q",
-		delay_param =>
-			((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_xr2_x1_FTGS of xr2_x1 is
-   for FTGS
-   end for;
-end CFG_xr2_x1_FTGS;
-
-
------ CELL xr2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity xr2_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.521 ns;
-      tpdi0_q_F                      :	Time := 0.560 ns;
-      tpdi1_q_R                      :	Time := 0.541 ns;
-      tpdi1_q_F                      :	Time := 0.657 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end xr2_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of xr2_x4 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is 
-	"U3/delay_param(1)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is 
-	"U3/delay_param(1)(TRAN_01)";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is 
-	"U3/delay_param(0)(TRAN_10)";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is 
-	"U3/delay_param(0)(TRAN_01)";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is 
-	"U2/delay(TRAN_10), " &
-	"U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is 
-	"U2/delay(TRAN_01), " &
-	"U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is 
-	"U1/delay(TRAN_10), " &
-	"U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is 
-	"U1/delay(TRAN_01), " &
-	"U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 
-
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : WIREBUF
-	generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F))
-	port map( Input => i0, Output => connect(0));
-
-   U2 : WIREBUF
-	generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F))
-	port map( Input => i1, Output => connect(1));
-
-   -- Netlist
-   U3 : TLU
-	generic map(
-		N => 2,
-		TruthTable => "0110",
-		TT_size => nil_integer_vector,
-		Node_index => nil_integer_vector,
-		pin_names => "i0 i1 q",
-		delay_param =>
-			((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns),
-			 (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)),
-		InMapZ => "XX",
-		OutMapZ => 'Z',
-		PulseHandling => PH_GLITCH,
-		Timing_mesg => Timing_mesg,
-		Timing_xgen => Timing_xgen,
-		strn => strn_X01)
-	port map(
-		Input(0) => connect(0), 
-		Input(1) => connect(1), 
-		Output => q);
-
-
-end FTGS;
-
-configuration CFG_xr2_x4_FTGS of xr2_x4 is
-   for FTGS
-   end for;
-end CFG_xr2_x4_FTGS;
-
-
------ CELL zero_x0 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity zero_x0 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False);
-
-   port(
-      nq                             :	out   STD_LOGIC := '0');
-end zero_x0;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-library IEEE;
-use IEEE.GS_TYPES.all;
-library GSCOMP;
-use GSCOMP.GS_COMPONENTS.all;
-
-architecture FTGS of zero_x0 is
-   attribute PRIVATE of FTGS : architecture is TRUE;
-   attribute ASIC_CELL of FTGS : architecture is TRUE;
-
-   -- Backannotation attributes
-
-
-
-begin
-
-   -- Netlist
-   nq <= '0';
-
-end FTGS;
-
-configuration CFG_zero_x0_FTGS of zero_x0 is
-   for FTGS
-   end for;
-end CFG_zero_x0_FTGS;
-
-
----- end of library ----
diff --git a/alliance/share/cells/sxlib/sxlib_FTSM.vhd b/alliance/share/cells/sxlib/sxlib_FTSM.vhd
deleted file mode 100644
index f19acf59..00000000
--- a/alliance/share/cells/sxlib/sxlib_FTSM.vhd
+++ /dev/null
@@ -1,11368 +0,0 @@
-
-----------------------------------------------------------------
--- 
--- Created by the Synopsys Library Compiler 1999.10
--- FILENAME     :    sxlib_FTSM.vhd
--- FILE CONTENTS:    Entity, Structural Architecture(FTSM),
---                   and Configuration
--- DATE CREATED :    Mon May  7 10:19:50 2001
--- 
--- LIBRARY      :    sxlib
--- DATE ENTERED :    Thu Dec 21 11:24:55 MET 2000
--- REVISION     :    1.200000
--- TECHNOLOGY   :    cmos
--- TIME SCALE   :    1 ns
--- LOGIC SYSTEM :    IEEE-1164
--- NOTES        :    FTSM, Timing_mesg(TRUE)
--- HISTORY      :
--- 
-----------------------------------------------------------------
-
------ CELL a2_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity a2_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.261 ns;
-      tpdi0_q_F                      :	Time := 0.388 ns;
-      tpdi1_q_R                      :	Time := 0.203 ns;
-      tpdi1_q_F                      :	Time := 0.434 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end a2_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of a2_x2 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   -- Intrinsic delay buffers
-   U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   -- Netlist
-   U5 : AND2MAC
-	port map( I0 => prop_q(0), I1 => prop_q(1), Y => q);
-
-
-end FTSM;
-
-configuration CFG_a2_x2_FTSM of a2_x2 is
-   for FTSM
-   end for;
-end CFG_a2_x2_FTSM;
-
-
------ CELL a2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity a2_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.338 ns;
-      tpdi0_q_F                      :	Time := 0.476 ns;
-      tpdi1_q_R                      :	Time := 0.269 ns;
-      tpdi1_q_F                      :	Time := 0.518 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end a2_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of a2_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   -- Intrinsic delay buffers
-   U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   -- Netlist
-   U5 : AND2MAC
-	port map( I0 => prop_q(0), I1 => prop_q(1), Y => q);
-
-
-end FTSM;
-
-configuration CFG_a2_x4_FTSM of a2_x4 is
-   for FTSM
-   end for;
-end CFG_a2_x4_FTSM;
-
-
------ CELL a3_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity a3_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.395 ns;
-      tpdi0_q_F                      :	Time := 0.435 ns;
-      tpdi1_q_R                      :	Time := 0.353 ns;
-      tpdi1_q_F                      :	Time := 0.479 ns;
-      tpdi2_q_R                      :	Time := 0.290 ns;
-      tpdi2_q_F                      :	Time := 0.521 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end a3_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of a3_x2 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-
-   component AND3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   -- Intrinsic delay buffers
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F)
-	port map( Input => connect(2), Output => prop_q(2));
-
-   -- Netlist
-   U7 : AND3MAC
-	port map( I0 => prop_q(1), I1 => prop_q(2), I2 => prop_q(0), Y => 
-         q);
-
-
-end FTSM;
-
-configuration CFG_a3_x2_FTSM of a3_x2 is
-   for FTSM
-   end for;
-end CFG_a3_x2_FTSM;
-
-
------ CELL a3_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity a3_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.478 ns;
-      tpdi0_q_F                      :	Time := 0.514 ns;
-      tpdi1_q_R                      :	Time := 0.428 ns;
-      tpdi1_q_F                      :	Time := 0.554 ns;
-      tpdi2_q_R                      :	Time := 0.356 ns;
-      tpdi2_q_F                      :	Time := 0.592 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end a3_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of a3_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-
-   component AND3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   -- Intrinsic delay buffers
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F)
-	port map( Input => connect(2), Output => prop_q(2));
-
-   -- Netlist
-   U7 : AND3MAC
-	port map( I0 => prop_q(1), I1 => prop_q(2), I2 => prop_q(0), Y => 
-         q);
-
-
-end FTSM;
-
-configuration CFG_a3_x4_FTSM of a3_x4 is
-   for FTSM
-   end for;
-end CFG_a3_x4_FTSM;
-
-
------ CELL a4_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity a4_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.374 ns;
-      tpdi0_q_F                      :	Time := 0.578 ns;
-      tpdi1_q_R                      :	Time := 0.441 ns;
-      tpdi1_q_F                      :	Time := 0.539 ns;
-      tpdi2_q_R                      :	Time := 0.482 ns;
-      tpdi2_q_F                      :	Time := 0.498 ns;
-      tpdi3_q_R                      :	Time := 0.506 ns;
-      tpdi3_q_F                      :	Time := 0.455 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end a4_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of a4_x2 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
-
-   component AND4MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         I3                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi3_R, tHL => twdi3_F)
-	port map( Input => i3, Output => connect(3));
-
-   -- Intrinsic delay buffers
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F)
-	port map( Input => connect(2), Output => prop_q(2));
-
-   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F)
-	port map( Input => connect(3), Output => prop_q(3));
-
-   -- Netlist
-   U9 : AND4MAC
-	port map( I0 => prop_q(0), I1 => prop_q(1), I2 => prop_q(2), I3 => 
-         prop_q(3), Y => q);
-
-
-end FTSM;
-
-configuration CFG_a4_x2_FTSM of a4_x2 is
-   for FTSM
-   end for;
-end CFG_a4_x2_FTSM;
-
-
------ CELL a4_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity a4_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.505 ns;
-      tpdi0_q_F                      :	Time := 0.650 ns;
-      tpdi1_q_R                      :	Time := 0.578 ns;
-      tpdi1_q_F                      :	Time := 0.614 ns;
-      tpdi2_q_R                      :	Time := 0.627 ns;
-      tpdi2_q_F                      :	Time := 0.576 ns;
-      tpdi3_q_R                      :	Time := 0.661 ns;
-      tpdi3_q_F                      :	Time := 0.538 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end a4_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of a4_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
-
-   component AND4MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         I3                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi3_R, tHL => twdi3_F)
-	port map( Input => i3, Output => connect(3));
-
-   -- Intrinsic delay buffers
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F)
-	port map( Input => connect(2), Output => prop_q(2));
-
-   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F)
-	port map( Input => connect(3), Output => prop_q(3));
-
-   -- Netlist
-   U9 : AND4MAC
-	port map( I0 => prop_q(0), I1 => prop_q(1), I2 => prop_q(2), I3 => 
-         prop_q(3), Y => q);
-
-
-end FTSM;
-
-configuration CFG_a4_x4_FTSM of a4_x4 is
-   for FTSM
-   end for;
-end CFG_a4_x4_FTSM;
-
-
------ CELL an12_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity an12_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.200 ns;
-      tpdi0_q_F                      :	Time := 0.168 ns;
-      tpdi1_q_R                      :	Time := 0.285 ns;
-      tpdi1_q_F                      :	Time := 0.405 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end an12_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of an12_x1 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-   signal n1 : STD_LOGIC;
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component INVMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   -- Intrinsic delay buffers
-   U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_F, tHL => tpdi0_q_R)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   -- Netlist
-   U5 : AND2MAC
-	port map( I0 => prop_q(1), I1 => n1, Y => q);
-
-   U6 : INVMAC
-	port map( I0 => prop_q(0), Y => n1);
-
-
-end FTSM;
-
-configuration CFG_an12_x1_FTSM of an12_x1 is
-   for FTSM
-   end for;
-end CFG_an12_x1_FTSM;
-
-
------ CELL an12_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity an12_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.461 ns;
-      tpdi0_q_F                      :	Time := 0.471 ns;
-      tpdi1_q_R                      :	Time := 0.269 ns;
-      tpdi1_q_F                      :	Time := 0.518 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end an12_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of an12_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-   signal n1 : STD_LOGIC;
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component INVMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   -- Intrinsic delay buffers
-   U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_F, tHL => tpdi0_q_R)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   -- Netlist
-   U5 : AND2MAC
-	port map( I0 => prop_q(1), I1 => n1, Y => q);
-
-   U6 : INVMAC
-	port map( I0 => prop_q(0), Y => n1);
-
-
-end FTSM;
-
-configuration CFG_an12_x4_FTSM of an12_x4 is
-   for FTSM
-   end for;
-end CFG_an12_x4_FTSM;
-
-
------ CELL ao2o22_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity ao2o22_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.572 ns;
-      tpdi0_q_F                      :	Time := 0.451 ns;
-      tpdi1_q_R                      :	Time := 0.508 ns;
-      tpdi1_q_F                      :	Time := 0.542 ns;
-      tpdi2_q_R                      :	Time := 0.432 ns;
-      tpdi2_q_F                      :	Time := 0.627 ns;
-      tpdi3_q_R                      :	Time := 0.488 ns;
-      tpdi3_q_F                      :	Time := 0.526 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end ao2o22_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of ao2o22_x2 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
-   signal n1, n2 : STD_LOGIC;
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component OR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi3_R, tHL => twdi3_F)
-	port map( Input => i3, Output => connect(3));
-
-   -- Intrinsic delay buffers
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F)
-	port map( Input => connect(2), Output => prop_q(2));
-
-   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F)
-	port map( Input => connect(3), Output => prop_q(3));
-
-   -- Netlist
-   U9 : AND2MAC
-	port map( I0 => n1, I1 => n2, Y => q);
-
-   U10 : OR2MAC
-	port map( I0 => prop_q(3), I1 => prop_q(2), Y => n2);
-
-   U11 : OR2MAC
-	port map( I0 => prop_q(1), I1 => prop_q(0), Y => n1);
-
-
-end FTSM;
-
-configuration CFG_ao2o22_x2_FTSM of ao2o22_x2 is
-   for FTSM
-   end for;
-end CFG_ao2o22_x2_FTSM;
-
-
------ CELL ao2o22_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity ao2o22_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.696 ns;
-      tpdi0_q_F                      :	Time := 0.569 ns;
-      tpdi1_q_R                      :	Time := 0.637 ns;
-      tpdi1_q_F                      :	Time := 0.666 ns;
-      tpdi2_q_R                      :	Time := 0.554 ns;
-      tpdi2_q_F                      :	Time := 0.744 ns;
-      tpdi3_q_R                      :	Time := 0.606 ns;
-      tpdi3_q_F                      :	Time := 0.639 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end ao2o22_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of ao2o22_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
-   signal n1, n2 : STD_LOGIC;
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component OR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi3_R, tHL => twdi3_F)
-	port map( Input => i3, Output => connect(3));
-
-   -- Intrinsic delay buffers
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F)
-	port map( Input => connect(2), Output => prop_q(2));
-
-   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F)
-	port map( Input => connect(3), Output => prop_q(3));
-
-   -- Netlist
-   U9 : AND2MAC
-	port map( I0 => n1, I1 => n2, Y => q);
-
-   U10 : OR2MAC
-	port map( I0 => prop_q(3), I1 => prop_q(2), Y => n2);
-
-   U11 : OR2MAC
-	port map( I0 => prop_q(1), I1 => prop_q(0), Y => n1);
-
-
-end FTSM;
-
-configuration CFG_ao2o22_x4_FTSM of ao2o22_x4 is
-   for FTSM
-   end for;
-end CFG_ao2o22_x4_FTSM;
-
-
------ CELL ao22_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity ao22_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.558 ns;
-      tpdi0_q_F                      :	Time := 0.447 ns;
-      tpdi1_q_R                      :	Time := 0.493 ns;
-      tpdi1_q_F                      :	Time := 0.526 ns;
-      tpdi2_q_R                      :	Time := 0.420 ns;
-      tpdi2_q_F                      :	Time := 0.425 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end ao22_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of ao22_x2 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-   signal n1 : STD_LOGIC;
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component OR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   -- Intrinsic delay buffers
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F)
-	port map( Input => connect(2), Output => prop_q(2));
-
-   -- Netlist
-   U7 : AND2MAC
-	port map( I0 => prop_q(2), I1 => n1, Y => q);
-
-   U8 : OR2MAC
-	port map( I0 => prop_q(1), I1 => prop_q(0), Y => n1);
-
-
-end FTSM;
-
-configuration CFG_ao22_x2_FTSM of ao22_x2 is
-   for FTSM
-   end for;
-end CFG_ao22_x2_FTSM;
-
-
------ CELL ao22_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity ao22_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.674 ns;
-      tpdi0_q_F                      :	Time := 0.552 ns;
-      tpdi1_q_R                      :	Time := 0.615 ns;
-      tpdi1_q_F                      :	Time := 0.647 ns;
-      tpdi2_q_R                      :	Time := 0.526 ns;
-      tpdi2_q_F                      :	Time := 0.505 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end ao22_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of ao22_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-   signal n1 : STD_LOGIC;
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component OR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   -- Intrinsic delay buffers
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F)
-	port map( Input => connect(2), Output => prop_q(2));
-
-   -- Netlist
-   U7 : AND2MAC
-	port map( I0 => prop_q(2), I1 => n1, Y => q);
-
-   U8 : OR2MAC
-	port map( I0 => prop_q(1), I1 => prop_q(0), Y => n1);
-
-
-end FTSM;
-
-configuration CFG_ao22_x4_FTSM of ao22_x4 is
-   for FTSM
-   end for;
-end CFG_ao22_x4_FTSM;
-
-
------ CELL buf_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity buf_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi_q_R                       :	Time := 0.409 ns;
-      tpdi_q_F                       :	Time := 0.391 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end buf_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of buf_x2 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi_q_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of tpdi_q_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U');
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi_R, tHL => twdi_F)
-	port map( Input => i, Output => connect(0));
-
-   -- Concurrent assignments
-   U2 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi_q_R, tHL => tpdi_q_F)
-	port map( Input => connect(0), Output => q);
-
-
-end FTSM;
-
-configuration CFG_buf_x2_FTSM of buf_x2 is
-   for FTSM
-   end for;
-end CFG_buf_x2_FTSM;
-
-
------ CELL buf_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity buf_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi_q_R                       :	Time := 0.379 ns;
-      tpdi_q_F                       :	Time := 0.409 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end buf_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of buf_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi_q_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of tpdi_q_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U');
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi_R, tHL => twdi_F)
-	port map( Input => i, Output => connect(0));
-
-   -- Concurrent assignments
-   U2 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi_q_R, tHL => tpdi_q_F)
-	port map( Input => connect(0), Output => q);
-
-
-end FTSM;
-
-configuration CFG_buf_x4_FTSM of buf_x4 is
-   for FTSM
-   end for;
-end CFG_buf_x4_FTSM;
-
-
------ CELL buf_x8 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity buf_x8 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi_q_R                       :	Time := 0.343 ns;
-      tpdi_q_F                       :	Time := 0.396 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end buf_x8;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of buf_x8 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi_q_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of tpdi_q_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U');
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi_R, tHL => twdi_F)
-	port map( Input => i, Output => connect(0));
-
-   -- Concurrent assignments
-   U2 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi_q_R, tHL => tpdi_q_F)
-	port map( Input => connect(0), Output => q);
-
-
-end FTSM;
-
-configuration CFG_buf_x8_FTSM of buf_x8 is
-   for FTSM
-   end for;
-end CFG_buf_x8_FTSM;
-
-
------ CELL inv_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity inv_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi_nq_R                      :	Time := 0.101 ns;
-      tpdi_nq_F                      :	Time := 0.139 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end inv_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of inv_x1 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi_nq_F: constant is "U2/U1/tHL";
-   attribute PROPAGATE_VALUE of tpdi_nq_R: constant is "U2/U1/tLH";
-   attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U');
-
-   component INVMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi_R, tHL => twdi_F)
-	port map( Input => i, Output => connect(0));
-
-   -- Netlist
-   U2 : INVMAC
-	generic map( tpdY_R => tpdi_nq_R, tpdY_F => tpdi_nq_F )
-	port map( I0 => connect(0), Y => nq);
-
-
-end FTSM;
-
-configuration CFG_inv_x1_FTSM of inv_x1 is
-   for FTSM
-   end for;
-end CFG_inv_x1_FTSM;
-
-
------ CELL inv_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity inv_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi_nq_R                      :	Time := 0.069 ns;
-      tpdi_nq_F                      :	Time := 0.163 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end inv_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of inv_x2 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi_nq_F: constant is "U2/U1/tHL";
-   attribute PROPAGATE_VALUE of tpdi_nq_R: constant is "U2/U1/tLH";
-   attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U');
-
-   component INVMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi_R, tHL => twdi_F)
-	port map( Input => i, Output => connect(0));
-
-   -- Netlist
-   U2 : INVMAC
-	generic map( tpdY_R => tpdi_nq_R, tpdY_F => tpdi_nq_F )
-	port map( I0 => connect(0), Y => nq);
-
-
-end FTSM;
-
-configuration CFG_inv_x2_FTSM of inv_x2 is
-   for FTSM
-   end for;
-end CFG_inv_x2_FTSM;
-
-
------ CELL inv_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity inv_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi_nq_R                      :	Time := 0.071 ns;
-      tpdi_nq_F                      :	Time := 0.143 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end inv_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of inv_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi_nq_F: constant is "U2/U1/tHL";
-   attribute PROPAGATE_VALUE of tpdi_nq_R: constant is "U2/U1/tLH";
-   attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U');
-
-   component INVMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi_R, tHL => twdi_F)
-	port map( Input => i, Output => connect(0));
-
-   -- Netlist
-   U2 : INVMAC
-	generic map( tpdY_R => tpdi_nq_R, tpdY_F => tpdi_nq_F )
-	port map( I0 => connect(0), Y => nq);
-
-
-end FTSM;
-
-configuration CFG_inv_x4_FTSM of inv_x4 is
-   for FTSM
-   end for;
-end CFG_inv_x4_FTSM;
-
-
------ CELL inv_x8 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity inv_x8 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi_nq_R                      :	Time := 0.086 ns;
-      tpdi_nq_F                      :	Time := 0.133 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end inv_x8;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of inv_x8 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi_nq_F: constant is "U2/U1/tHL";
-   attribute PROPAGATE_VALUE of tpdi_nq_R: constant is "U2/U1/tLH";
-   attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U');
-
-   component INVMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi_R, tHL => twdi_F)
-	port map( Input => i, Output => connect(0));
-
-   -- Netlist
-   U2 : INVMAC
-	generic map( tpdY_R => tpdi_nq_R, tpdY_F => tpdi_nq_F )
-	port map( I0 => connect(0), Y => nq);
-
-
-end FTSM;
-
-configuration CFG_inv_x8_FTSM of inv_x8 is
-   for FTSM
-   end for;
-end CFG_inv_x8_FTSM;
-
-
------ CELL mx2_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity mx2_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd_q_R                     :	Time := 0.484 ns;
-      tpdcmd_q_F                     :	Time := 0.522 ns;
-      tpdi0_q_R                      :	Time := 0.451 ns;
-      tpdi0_q_F                      :	Time := 0.469 ns;
-      tpdi1_q_R                      :	Time := 0.451 ns;
-      tpdi1_q_F                      :	Time := 0.469 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      cmd                            :	in    STD_LOGIC;
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end mx2_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of mx2_x2 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdcmd_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdcmd_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-
-   component MUX2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         S0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdcmd_R, tHL => twdcmd_F)
-	port map( Input => cmd, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(2));
-
-   -- Intrinsic delay buffers
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdcmd_q_R, tHL => tpdcmd_q_F)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(2), Output => prop_q(2));
-
-   -- Netlist
-   U7 : MUX2MAC
-	port map( I0 => prop_q(1), I1 => prop_q(2), S0 => prop_q(0), Y => 
-         q);
-
-
-end FTSM;
-
-configuration CFG_mx2_x2_FTSM of mx2_x2 is
-   for FTSM
-   end for;
-end CFG_mx2_x2_FTSM;
-
-
------ CELL mx2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity mx2_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd_q_R                     :	Time := 0.615 ns;
-      tpdcmd_q_F                     :	Time := 0.647 ns;
-      tpdi0_q_R                      :	Time := 0.564 ns;
-      tpdi0_q_F                      :	Time := 0.576 ns;
-      tpdi1_q_R                      :	Time := 0.564 ns;
-      tpdi1_q_F                      :	Time := 0.576 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      cmd                            :	in    STD_LOGIC;
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end mx2_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of mx2_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdcmd_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdcmd_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-
-   component MUX2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         S0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdcmd_R, tHL => twdcmd_F)
-	port map( Input => cmd, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(2));
-
-   -- Intrinsic delay buffers
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdcmd_q_R, tHL => tpdcmd_q_F)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(2), Output => prop_q(2));
-
-   -- Netlist
-   U7 : MUX2MAC
-	port map( I0 => prop_q(1), I1 => prop_q(2), S0 => prop_q(0), Y => 
-         q);
-
-
-end FTSM;
-
-configuration CFG_mx2_x4_FTSM of mx2_x4 is
-   for FTSM
-   end for;
-end CFG_mx2_x4_FTSM;
-
-
------ CELL mx3_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity mx3_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd0_q_R                    :	Time := 0.573 ns;
-      tpdcmd0_q_F                    :	Time := 0.680 ns;
-      tpdcmd1_q_R                    :	Time := 0.664 ns;
-      tpdcmd1_q_F                    :	Time := 0.817 ns;
-      tpdi0_q_R                      :	Time := 0.538 ns;
-      tpdi0_q_F                      :	Time := 0.658 ns;
-      tpdi1_q_R                      :	Time := 0.654 ns;
-      tpdi1_q_F                      :	Time := 0.808 ns;
-      tpdi2_q_R                      :	Time := 0.654 ns;
-      tpdi2_q_F                      :	Time := 0.808 ns;
-      twdcmd0_R                      :	Time := 0.000 ns;
-      twdcmd0_F                      :	Time := 0.000 ns;
-      twdcmd1_R                      :	Time := 0.000 ns;
-      twdcmd1_F                      :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      cmd0                           :	in    STD_LOGIC;
-      cmd1                           :	in    STD_LOGIC;
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end mx3_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of mx3_x2 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U10/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U10/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U9/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U9/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of tpdcmd1_q_R: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of tpdcmd1_q_F: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of tpdcmd0_q_R: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdcmd0_q_F: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdcmd1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdcmd1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdcmd0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdcmd0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 4) := (others => 'U');
-   signal n1 : STD_LOGIC;
-
-   component MUX2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         S0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdcmd0_R, tHL => twdcmd0_F)
-	port map( Input => cmd0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdcmd1_R, tHL => twdcmd1_F)
-	port map( Input => cmd1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(3));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(4));
-
-   -- Intrinsic delay buffers
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdcmd0_q_R, tHL => tpdcmd0_q_F)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdcmd1_q_R, tHL => tpdcmd1_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F)
-	port map( Input => connect(2), Output => prop_q(2));
-
-   U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(3), Output => prop_q(3));
-
-   U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F)
-	port map( Input => connect(4), Output => prop_q(4));
-
-   -- Netlist
-   U11 : MUX2MAC
-	port map( I0 => prop_q(4), I1 => prop_q(3), S0 => prop_q(1), Y => 
-         n1);
-
-   U12 : MUX2MAC
-	port map( I0 => prop_q(2), I1 => n1, S0 => prop_q(0), Y => q);
-
-
-end FTSM;
-
-configuration CFG_mx3_x2_FTSM of mx3_x2 is
-   for FTSM
-   end for;
-end CFG_mx3_x2_FTSM;
-
-
------ CELL mx3_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity mx3_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd0_q_R                    :	Time := 0.683 ns;
-      tpdcmd0_q_F                    :	Time := 0.779 ns;
-      tpdcmd1_q_R                    :	Time := 0.792 ns;
-      tpdcmd1_q_F                    :	Time := 0.967 ns;
-      tpdi0_q_R                      :	Time := 0.640 ns;
-      tpdi0_q_F                      :	Time := 0.774 ns;
-      tpdi1_q_R                      :	Time := 0.770 ns;
-      tpdi1_q_F                      :	Time := 0.948 ns;
-      tpdi2_q_R                      :	Time := 0.770 ns;
-      tpdi2_q_F                      :	Time := 0.948 ns;
-      twdcmd0_R                      :	Time := 0.000 ns;
-      twdcmd0_F                      :	Time := 0.000 ns;
-      twdcmd1_R                      :	Time := 0.000 ns;
-      twdcmd1_F                      :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      cmd0                           :	in    STD_LOGIC;
-      cmd1                           :	in    STD_LOGIC;
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end mx3_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of mx3_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U10/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U10/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U9/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U9/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of tpdcmd1_q_R: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of tpdcmd1_q_F: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of tpdcmd0_q_R: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdcmd0_q_F: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdcmd1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdcmd1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdcmd0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdcmd0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 4) := (others => 'U');
-   signal n1 : STD_LOGIC;
-
-   component MUX2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         S0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdcmd0_R, tHL => twdcmd0_F)
-	port map( Input => cmd0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdcmd1_R, tHL => twdcmd1_F)
-	port map( Input => cmd1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(3));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(4));
-
-   -- Intrinsic delay buffers
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdcmd0_q_R, tHL => tpdcmd0_q_F)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdcmd1_q_R, tHL => tpdcmd1_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F)
-	port map( Input => connect(2), Output => prop_q(2));
-
-   U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(3), Output => prop_q(3));
-
-   U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F)
-	port map( Input => connect(4), Output => prop_q(4));
-
-   -- Netlist
-   U11 : MUX2MAC
-	port map( I0 => prop_q(4), I1 => prop_q(3), S0 => prop_q(1), Y => 
-         n1);
-
-   U12 : MUX2MAC
-	port map( I0 => prop_q(2), I1 => n1, S0 => prop_q(0), Y => q);
-
-
-end FTSM;
-
-configuration CFG_mx3_x4_FTSM of mx3_x4 is
-   for FTSM
-   end for;
-end CFG_mx3_x4_FTSM;
-
-
------ CELL na2_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity na2_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.059 ns;
-      tpdi0_nq_F                     :	Time := 0.288 ns;
-      tpdi1_nq_R                     :	Time := 0.111 ns;
-      tpdi1_nq_F                     :	Time := 0.234 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end na2_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of na2_x1 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   -- Intrinsic delay buffers
-   U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   -- Netlist
-   U5 : NAND2MAC
-	port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => nq);
-
-
-end FTSM;
-
-configuration CFG_na2_x1_FTSM of na2_x1 is
-   for FTSM
-   end for;
-end CFG_na2_x1_FTSM;
-
-
------ CELL na2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity na2_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.412 ns;
-      tpdi0_nq_F                     :	Time := 0.552 ns;
-      tpdi1_nq_R                     :	Time := 0.353 ns;
-      tpdi1_nq_F                     :	Time := 0.601 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end na2_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of na2_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   -- Intrinsic delay buffers
-   U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   -- Netlist
-   U5 : NAND2MAC
-	port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => nq);
-
-
-end FTSM;
-
-configuration CFG_na2_x4_FTSM of na2_x4 is
-   for FTSM
-   end for;
-end CFG_na2_x4_FTSM;
-
-
------ CELL na3_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity na3_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.119 ns;
-      tpdi0_nq_F                     :	Time := 0.363 ns;
-      tpdi1_nq_R                     :	Time := 0.171 ns;
-      tpdi1_nq_F                     :	Time := 0.316 ns;
-      tpdi2_nq_R                     :	Time := 0.193 ns;
-      tpdi2_nq_F                     :	Time := 0.265 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end na3_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of na3_x1 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-
-   component NAND3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   -- Intrinsic delay buffers
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R)
-	port map( Input => connect(2), Output => prop_nq(2));
-
-   -- Netlist
-   U7 : NAND3MAC
-	port map( I0 => prop_nq(1), I1 => prop_nq(2), I2 => prop_nq(0), Y => 
-         nq);
-
-
-end FTSM;
-
-configuration CFG_na3_x1_FTSM of na3_x1 is
-   for FTSM
-   end for;
-end CFG_na3_x1_FTSM;
-
-
------ CELL na3_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity na3_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.556 ns;
-      tpdi0_nq_F                     :	Time := 0.601 ns;
-      tpdi1_nq_R                     :	Time := 0.460 ns;
-      tpdi1_nq_F                     :	Time := 0.691 ns;
-      tpdi2_nq_R                     :	Time := 0.519 ns;
-      tpdi2_nq_F                     :	Time := 0.647 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end na3_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of na3_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-
-   component NAND3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   -- Intrinsic delay buffers
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R)
-	port map( Input => connect(2), Output => prop_nq(2));
-
-   -- Netlist
-   U7 : NAND3MAC
-	port map( I0 => prop_nq(1), I1 => prop_nq(2), I2 => prop_nq(0), Y => 
-         nq);
-
-
-end FTSM;
-
-configuration CFG_na3_x4_FTSM of na3_x4 is
-   for FTSM
-   end for;
-end CFG_na3_x4_FTSM;
-
-
------ CELL na4_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity na4_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.179 ns;
-      tpdi0_nq_F                     :	Time := 0.438 ns;
-      tpdi1_nq_R                     :	Time := 0.237 ns;
-      tpdi1_nq_F                     :	Time := 0.395 ns;
-      tpdi2_nq_R                     :	Time := 0.269 ns;
-      tpdi2_nq_F                     :	Time := 0.350 ns;
-      tpdi3_nq_R                     :	Time := 0.282 ns;
-      tpdi3_nq_F                     :	Time := 0.302 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end na4_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of na4_x1 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
-
-   component NAND4MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         I3                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi3_R, tHL => twdi3_F)
-	port map( Input => i3, Output => connect(3));
-
-   -- Intrinsic delay buffers
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R)
-	port map( Input => connect(2), Output => prop_nq(2));
-
-   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R)
-	port map( Input => connect(3), Output => prop_nq(3));
-
-   -- Netlist
-   U9 : NAND4MAC
-	port map( I0 => prop_nq(0), I1 => prop_nq(1), I2 => prop_nq(2), I3 => 
-         prop_nq(3), Y => nq);
-
-
-end FTSM;
-
-configuration CFG_na4_x1_FTSM of na4_x1 is
-   for FTSM
-   end for;
-end CFG_na4_x1_FTSM;
-
-
------ CELL na4_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity na4_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.578 ns;
-      tpdi0_nq_F                     :	Time := 0.771 ns;
-      tpdi1_nq_R                     :	Time := 0.643 ns;
-      tpdi1_nq_F                     :	Time := 0.731 ns;
-      tpdi2_nq_R                     :	Time := 0.681 ns;
-      tpdi2_nq_F                     :	Time := 0.689 ns;
-      tpdi3_nq_R                     :	Time := 0.703 ns;
-      tpdi3_nq_F                     :	Time := 0.644 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end na4_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of na4_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
-
-   component NAND4MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         I3                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi3_R, tHL => twdi3_F)
-	port map( Input => i3, Output => connect(3));
-
-   -- Intrinsic delay buffers
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R)
-	port map( Input => connect(2), Output => prop_nq(2));
-
-   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R)
-	port map( Input => connect(3), Output => prop_nq(3));
-
-   -- Netlist
-   U9 : NAND4MAC
-	port map( I0 => prop_nq(0), I1 => prop_nq(1), I2 => prop_nq(2), I3 => 
-         prop_nq(3), Y => nq);
-
-
-end FTSM;
-
-configuration CFG_na4_x4_FTSM of na4_x4 is
-   for FTSM
-   end for;
-end CFG_na4_x4_FTSM;
-
-
------ CELL nao2o22_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nao2o22_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.294 ns;
-      tpdi0_nq_F                     :	Time := 0.226 ns;
-      tpdi1_nq_R                     :	Time := 0.218 ns;
-      tpdi1_nq_F                     :	Time := 0.287 ns;
-      tpdi2_nq_R                     :	Time := 0.237 ns;
-      tpdi2_nq_F                     :	Time := 0.307 ns;
-      tpdi3_nq_R                     :	Time := 0.174 ns;
-      tpdi3_nq_F                     :	Time := 0.382 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nao2o22_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of nao2o22_x1 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
-   signal n1, n2 : STD_LOGIC;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component OR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi3_R, tHL => twdi3_F)
-	port map( Input => i3, Output => connect(3));
-
-   -- Intrinsic delay buffers
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R)
-	port map( Input => connect(2), Output => prop_nq(2));
-
-   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R)
-	port map( Input => connect(3), Output => prop_nq(3));
-
-   -- Netlist
-   U9 : NAND2MAC
-	port map( I0 => n1, I1 => n2, Y => nq);
-
-   U10 : OR2MAC
-	port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n2);
-
-   U11 : OR2MAC
-	port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1);
-
-
-end FTSM;
-
-configuration CFG_nao2o22_x1_FTSM of nao2o22_x1 is
-   for FTSM
-   end for;
-end CFG_nao2o22_x1_FTSM;
-
-
------ CELL nao2o22_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nao2o22_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.734 ns;
-      tpdi0_nq_F                     :	Time := 0.644 ns;
-      tpdi1_nq_R                     :	Time := 0.666 ns;
-      tpdi1_nq_F                     :	Time := 0.717 ns;
-      tpdi2_nq_R                     :	Time := 0.664 ns;
-      tpdi2_nq_F                     :	Time := 0.721 ns;
-      tpdi3_nq_R                     :	Time := 0.607 ns;
-      tpdi3_nq_F                     :	Time := 0.807 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nao2o22_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of nao2o22_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
-   signal n1, n2 : STD_LOGIC;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component OR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi3_R, tHL => twdi3_F)
-	port map( Input => i3, Output => connect(3));
-
-   -- Intrinsic delay buffers
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R)
-	port map( Input => connect(2), Output => prop_nq(2));
-
-   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R)
-	port map( Input => connect(3), Output => prop_nq(3));
-
-   -- Netlist
-   U9 : NAND2MAC
-	port map( I0 => n1, I1 => n2, Y => nq);
-
-   U10 : OR2MAC
-	port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n2);
-
-   U11 : OR2MAC
-	port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1);
-
-
-end FTSM;
-
-configuration CFG_nao2o22_x4_FTSM of nao2o22_x4 is
-   for FTSM
-   end for;
-end CFG_nao2o22_x4_FTSM;
-
-
------ CELL nao22_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nao22_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.294 ns;
-      tpdi0_nq_F                     :	Time := 0.226 ns;
-      tpdi1_nq_R                     :	Time := 0.218 ns;
-      tpdi1_nq_F                     :	Time := 0.287 ns;
-      tpdi2_nq_R                     :	Time := 0.165 ns;
-      tpdi2_nq_F                     :	Time := 0.238 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nao22_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of nao22_x1 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-   signal n1 : STD_LOGIC;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component OR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   -- Intrinsic delay buffers
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R)
-	port map( Input => connect(2), Output => prop_nq(2));
-
-   -- Netlist
-   U7 : NAND2MAC
-	port map( I0 => prop_nq(2), I1 => n1, Y => nq);
-
-   U8 : OR2MAC
-	port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1);
-
-
-end FTSM;
-
-configuration CFG_nao22_x1_FTSM of nao22_x1 is
-   for FTSM
-   end for;
-end CFG_nao22_x1_FTSM;
-
-
------ CELL nao22_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nao22_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.732 ns;
-      tpdi0_nq_F                     :	Time := 0.650 ns;
-      tpdi1_nq_R                     :	Time := 0.664 ns;
-      tpdi1_nq_F                     :	Time := 0.723 ns;
-      tpdi2_nq_R                     :	Time := 0.596 ns;
-      tpdi2_nq_F                     :	Time := 0.636 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nao22_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of nao22_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-   signal n1 : STD_LOGIC;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component OR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   -- Intrinsic delay buffers
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R)
-	port map( Input => connect(2), Output => prop_nq(2));
-
-   -- Netlist
-   U7 : NAND2MAC
-	port map( I0 => prop_nq(2), I1 => n1, Y => nq);
-
-   U8 : OR2MAC
-	port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1);
-
-
-end FTSM;
-
-configuration CFG_nao22_x4_FTSM of nao22_x4 is
-   for FTSM
-   end for;
-end CFG_nao22_x4_FTSM;
-
-
------ CELL nmx2_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nmx2_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd_nq_R                    :	Time := 0.218 ns;
-      tpdcmd_nq_F                    :	Time := 0.287 ns;
-      tpdi0_nq_R                     :	Time := 0.217 ns;
-      tpdi0_nq_F                     :	Time := 0.256 ns;
-      tpdi1_nq_R                     :	Time := 0.217 ns;
-      tpdi1_nq_F                     :	Time := 0.256 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      cmd                            :	in    STD_LOGIC;
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nmx2_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of nmx2_x1 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdcmd_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdcmd_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-   signal n1 : STD_LOGIC;
-
-   component MUX2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         S0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component INVMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdcmd_R, tHL => twdcmd_F)
-	port map( Input => cmd, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(2));
-
-   -- Intrinsic delay buffers
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdcmd_nq_F, tHL => tpdcmd_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R)
-	port map( Input => connect(2), Output => prop_nq(2));
-
-   -- Netlist
-   U7 : MUX2MAC
-	port map( I0 => prop_nq(1), I1 => prop_nq(2), S0 => prop_nq(0), Y => 
-         n1);
-
-   U8 : INVMAC
-	port map( I0 => n1, Y => nq);
-
-
-end FTSM;
-
-configuration CFG_nmx2_x1_FTSM of nmx2_x1 is
-   for FTSM
-   end for;
-end CFG_nmx2_x1_FTSM;
-
-
------ CELL nmx2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nmx2_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd_nq_R                    :	Time := 0.632 ns;
-      tpdcmd_nq_F                    :	Time := 0.708 ns;
-      tpdi0_nq_R                     :	Time := 0.610 ns;
-      tpdi0_nq_F                     :	Time := 0.653 ns;
-      tpdi1_nq_R                     :	Time := 0.610 ns;
-      tpdi1_nq_F                     :	Time := 0.653 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      cmd                            :	in    STD_LOGIC;
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nmx2_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of nmx2_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdcmd_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdcmd_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-   signal n1 : STD_LOGIC;
-
-   component MUX2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         S0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component INVMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdcmd_R, tHL => twdcmd_F)
-	port map( Input => cmd, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(2));
-
-   -- Intrinsic delay buffers
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdcmd_nq_F, tHL => tpdcmd_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R)
-	port map( Input => connect(2), Output => prop_nq(2));
-
-   -- Netlist
-   U7 : MUX2MAC
-	port map( I0 => prop_nq(1), I1 => prop_nq(2), S0 => prop_nq(0), Y => 
-         n1);
-
-   U8 : INVMAC
-	port map( I0 => n1, Y => nq);
-
-
-end FTSM;
-
-configuration CFG_nmx2_x4_FTSM of nmx2_x4 is
-   for FTSM
-   end for;
-end CFG_nmx2_x4_FTSM;
-
-
------ CELL nmx3_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nmx3_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd0_nq_R                   :	Time := 0.356 ns;
-      tpdcmd0_nq_F                   :	Time := 0.495 ns;
-      tpdcmd1_nq_R                   :	Time := 0.414 ns;
-      tpdcmd1_nq_F                   :	Time := 0.566 ns;
-      tpdi0_nq_R                     :	Time := 0.315 ns;
-      tpdi0_nq_F                     :	Time := 0.441 ns;
-      tpdi1_nq_R                     :	Time := 0.429 ns;
-      tpdi1_nq_F                     :	Time := 0.582 ns;
-      tpdi2_nq_R                     :	Time := 0.429 ns;
-      tpdi2_nq_F                     :	Time := 0.582 ns;
-      twdcmd0_R                      :	Time := 0.000 ns;
-      twdcmd0_F                      :	Time := 0.000 ns;
-      twdcmd1_R                      :	Time := 0.000 ns;
-      twdcmd1_F                      :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      cmd0                           :	in    STD_LOGIC;
-      cmd1                           :	in    STD_LOGIC;
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nmx3_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of nmx3_x1 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U10/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U10/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U9/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U9/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of tpdcmd1_nq_F: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of tpdcmd1_nq_R: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of tpdcmd0_nq_F: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdcmd0_nq_R: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdcmd1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdcmd1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdcmd0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdcmd0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 4) := (others => 'U');
-   signal n1, n2 : STD_LOGIC;
-
-   component MUX2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         S0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component INVMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdcmd0_R, tHL => twdcmd0_F)
-	port map( Input => cmd0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdcmd1_R, tHL => twdcmd1_F)
-	port map( Input => cmd1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(3));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(4));
-
-   -- Intrinsic delay buffers
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdcmd0_nq_F, tHL => tpdcmd0_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdcmd1_nq_F, tHL => tpdcmd1_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R)
-	port map( Input => connect(2), Output => prop_nq(2));
-
-   U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R)
-	port map( Input => connect(3), Output => prop_nq(3));
-
-   U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R)
-	port map( Input => connect(4), Output => prop_nq(4));
-
-   -- Netlist
-   U11 : MUX2MAC
-	port map( I0 => prop_nq(4), I1 => prop_nq(3), S0 => prop_nq(1), Y => 
-         n1);
-
-   U12 : MUX2MAC
-	port map( I0 => prop_nq(2), I1 => n1, S0 => prop_nq(0), Y => n2);
-
-   U13 : INVMAC
-	port map( I0 => n2, Y => nq);
-
-
-end FTSM;
-
-configuration CFG_nmx3_x1_FTSM of nmx3_x1 is
-   for FTSM
-   end for;
-end CFG_nmx3_x1_FTSM;
-
-
------ CELL nmx3_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nmx3_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd0_nq_R                   :	Time := 0.790 ns;
-      tpdcmd0_nq_F                   :	Time := 0.936 ns;
-      tpdcmd1_nq_R                   :	Time := 0.866 ns;
-      tpdcmd1_nq_F                   :	Time := 1.048 ns;
-      tpdi0_nq_R                     :	Time := 0.748 ns;
-      tpdi0_nq_F                     :	Time := 0.900 ns;
-      tpdi1_nq_R                     :	Time := 0.869 ns;
-      tpdi1_nq_F                     :	Time := 1.053 ns;
-      tpdi2_nq_R                     :	Time := 0.869 ns;
-      tpdi2_nq_F                     :	Time := 1.053 ns;
-      twdcmd0_R                      :	Time := 0.000 ns;
-      twdcmd0_F                      :	Time := 0.000 ns;
-      twdcmd1_R                      :	Time := 0.000 ns;
-      twdcmd1_F                      :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      cmd0                           :	in    STD_LOGIC;
-      cmd1                           :	in    STD_LOGIC;
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nmx3_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of nmx3_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U10/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U10/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U9/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U9/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of tpdcmd1_nq_F: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of tpdcmd1_nq_R: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of tpdcmd0_nq_F: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdcmd0_nq_R: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdcmd1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdcmd1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdcmd0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdcmd0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 4) := (others => 'U');
-   signal n1, n2 : STD_LOGIC;
-
-   component MUX2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         S0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component INVMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdcmd0_R, tHL => twdcmd0_F)
-	port map( Input => cmd0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdcmd1_R, tHL => twdcmd1_F)
-	port map( Input => cmd1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(3));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(4));
-
-   -- Intrinsic delay buffers
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdcmd0_nq_F, tHL => tpdcmd0_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdcmd1_nq_F, tHL => tpdcmd1_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R)
-	port map( Input => connect(2), Output => prop_nq(2));
-
-   U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R)
-	port map( Input => connect(3), Output => prop_nq(3));
-
-   U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R)
-	port map( Input => connect(4), Output => prop_nq(4));
-
-   -- Netlist
-   U11 : MUX2MAC
-	port map( I0 => prop_nq(4), I1 => prop_nq(3), S0 => prop_nq(1), Y => 
-         n1);
-
-   U12 : MUX2MAC
-	port map( I0 => prop_nq(2), I1 => n1, S0 => prop_nq(0), Y => n2);
-
-   U13 : INVMAC
-	port map( I0 => n2, Y => nq);
-
-
-end FTSM;
-
-configuration CFG_nmx3_x4_FTSM of nmx3_x4 is
-   for FTSM
-   end for;
-end CFG_nmx3_x4_FTSM;
-
-
------ CELL no2_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity no2_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.298 ns;
-      tpdi0_nq_F                     :	Time := 0.121 ns;
-      tpdi1_nq_R                     :	Time := 0.193 ns;
-      tpdi1_nq_F                     :	Time := 0.161 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end no2_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of no2_x1 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-
-   component NOR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   -- Intrinsic delay buffers
-   U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   -- Netlist
-   U5 : NOR2MAC
-	port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => nq);
-
-
-end FTSM;
-
-configuration CFG_no2_x1_FTSM of no2_x1 is
-   for FTSM
-   end for;
-end CFG_no2_x1_FTSM;
-
-
------ CELL no2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity no2_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.618 ns;
-      tpdi0_nq_F                     :	Time := 0.447 ns;
-      tpdi1_nq_R                     :	Time := 0.522 ns;
-      tpdi1_nq_F                     :	Time := 0.504 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end no2_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of no2_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-
-   component NOR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   -- Intrinsic delay buffers
-   U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   -- Netlist
-   U5 : NOR2MAC
-	port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => nq);
-
-
-end FTSM;
-
-configuration CFG_no2_x4_FTSM of no2_x4 is
-   for FTSM
-   end for;
-end CFG_no2_x4_FTSM;
-
-
------ CELL no3_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity no3_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.318 ns;
-      tpdi0_nq_F                     :	Time := 0.246 ns;
-      tpdi1_nq_R                     :	Time := 0.215 ns;
-      tpdi1_nq_F                     :	Time := 0.243 ns;
-      tpdi2_nq_R                     :	Time := 0.407 ns;
-      tpdi2_nq_F                     :	Time := 0.192 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end no3_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of no3_x1 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-
-   component NOR3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   -- Intrinsic delay buffers
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R)
-	port map( Input => connect(2), Output => prop_nq(2));
-
-   -- Netlist
-   U7 : NOR3MAC
-	port map( I0 => prop_nq(2), I1 => prop_nq(0), I2 => prop_nq(1), Y => 
-         nq);
-
-
-end FTSM;
-
-configuration CFG_no3_x1_FTSM of no3_x1 is
-   for FTSM
-   end for;
-end CFG_no3_x1_FTSM;
-
-
------ CELL no3_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity no3_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.722 ns;
-      tpdi0_nq_F                     :	Time := 0.561 ns;
-      tpdi1_nq_R                     :	Time := 0.638 ns;
-      tpdi1_nq_F                     :	Time := 0.623 ns;
-      tpdi2_nq_R                     :	Time := 0.545 ns;
-      tpdi2_nq_F                     :	Time := 0.640 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end no3_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of no3_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-
-   component NOR3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   -- Intrinsic delay buffers
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R)
-	port map( Input => connect(2), Output => prop_nq(2));
-
-   -- Netlist
-   U7 : NOR3MAC
-	port map( I0 => prop_nq(2), I1 => prop_nq(0), I2 => prop_nq(1), Y => 
-         nq);
-
-
-end FTSM;
-
-configuration CFG_no3_x4_FTSM of no3_x4 is
-   for FTSM
-   end for;
-end CFG_no3_x4_FTSM;
-
-
------ CELL no4_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity no4_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.330 ns;
-      tpdi0_nq_F                     :	Time := 0.340 ns;
-      tpdi1_nq_R                     :	Time := 0.230 ns;
-      tpdi1_nq_F                     :	Time := 0.320 ns;
-      tpdi2_nq_R                     :	Time := 0.419 ns;
-      tpdi2_nq_F                     :	Time := 0.333 ns;
-      tpdi3_nq_R                     :	Time := 0.499 ns;
-      tpdi3_nq_F                     :	Time := 0.271 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end no4_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of no4_x1 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
-
-   component NOR4MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         I3                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi3_R, tHL => twdi3_F)
-	port map( Input => i3, Output => connect(3));
-
-   -- Intrinsic delay buffers
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R)
-	port map( Input => connect(2), Output => prop_nq(2));
-
-   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R)
-	port map( Input => connect(3), Output => prop_nq(3));
-
-   -- Netlist
-   U9 : NOR4MAC
-	port map( I0 => prop_nq(0), I1 => prop_nq(1), I2 => prop_nq(2), I3 => 
-         prop_nq(3), Y => nq);
-
-
-end FTSM;
-
-configuration CFG_no4_x1_FTSM of no4_x1 is
-   for FTSM
-   end for;
-end CFG_no4_x1_FTSM;
-
-
------ CELL no4_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity no4_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.656 ns;
-      tpdi0_nq_F                     :	Time := 0.777 ns;
-      tpdi1_nq_R                     :	Time := 0.564 ns;
-      tpdi1_nq_F                     :	Time := 0.768 ns;
-      tpdi2_nq_R                     :	Time := 0.739 ns;
-      tpdi2_nq_F                     :	Time := 0.761 ns;
-      tpdi3_nq_R                     :	Time := 0.816 ns;
-      tpdi3_nq_F                     :	Time := 0.693 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end no4_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of no4_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
-
-   component NOR4MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         I3                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi3_R, tHL => twdi3_F)
-	port map( Input => i3, Output => connect(3));
-
-   -- Intrinsic delay buffers
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R)
-	port map( Input => connect(2), Output => prop_nq(2));
-
-   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R)
-	port map( Input => connect(3), Output => prop_nq(3));
-
-   -- Netlist
-   U9 : NOR4MAC
-	port map( I0 => prop_nq(0), I1 => prop_nq(1), I2 => prop_nq(2), I3 => 
-         prop_nq(3), Y => nq);
-
-
-end FTSM;
-
-configuration CFG_no4_x4_FTSM of no4_x4 is
-   for FTSM
-   end for;
-end CFG_no4_x4_FTSM;
-
-
------ CELL noa2a2a2a24_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa2a2a2a24_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.649 ns;
-      tpdi0_nq_F                     :	Time := 0.606 ns;
-      tpdi1_nq_R                     :	Time := 0.775 ns;
-      tpdi1_nq_F                     :	Time := 0.562 ns;
-      tpdi2_nq_R                     :	Time := 0.550 ns;
-      tpdi2_nq_F                     :	Time := 0.662 ns;
-      tpdi3_nq_R                     :	Time := 0.667 ns;
-      tpdi3_nq_F                     :	Time := 0.616 ns;
-      tpdi4_nq_R                     :	Time := 0.419 ns;
-      tpdi4_nq_F                     :	Time := 0.613 ns;
-      tpdi5_nq_R                     :	Time := 0.329 ns;
-      tpdi5_nq_F                     :	Time := 0.662 ns;
-      tpdi6_nq_R                     :	Time := 0.270 ns;
-      tpdi6_nq_F                     :	Time := 0.535 ns;
-      tpdi7_nq_R                     :	Time := 0.200 ns;
-      tpdi7_nq_F                     :	Time := 0.591 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns;
-      twdi6_R                        :	Time := 0.000 ns;
-      twdi6_F                        :	Time := 0.000 ns;
-      twdi7_R                        :	Time := 0.000 ns;
-      twdi7_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      i6                             :	in    STD_LOGIC;
-      i7                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa2a2a2a24_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of noa2a2a2a24_x1 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi7_nq_F: constant is "U16/tLH";
-   attribute PROPAGATE_VALUE of tpdi7_nq_R: constant is "U16/tHL";
-   attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is "U15/tLH";
-   attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is "U15/tHL";
-   attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is "U14/tLH";
-   attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is "U14/tHL";
-   attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U13/tLH";
-   attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U13/tHL";
-   attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U12/tLH";
-   attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U12/tHL";
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U11/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U11/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U10/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U10/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U9/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U9/tHL";
-   attribute PROPAGATE_VALUE of twdi7_F: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of twdi7_R: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 7) := (others => 'U');
-   signal n1, n2, n3, n4 : STD_LOGIC;
-
-   component AND4MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         I3                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi3_R, tHL => twdi3_F)
-	port map( Input => i3, Output => connect(3));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi4_R, tHL => twdi4_F)
-	port map( Input => i4, Output => connect(4));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi5_R, tHL => twdi5_F)
-	port map( Input => i5, Output => connect(5));
-
-   U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi6_R, tHL => twdi6_F)
-	port map( Input => i6, Output => connect(6));
-
-   U8 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi7_R, tHL => twdi7_F)
-	port map( Input => i7, Output => connect(7));
-
-   -- Intrinsic delay buffers
-   U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R)
-	port map( Input => connect(2), Output => prop_nq(2));
-
-   U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R)
-	port map( Input => connect(3), Output => prop_nq(3));
-
-   U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R)
-	port map( Input => connect(4), Output => prop_nq(4));
-
-   U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi5_nq_F, tHL => tpdi5_nq_R)
-	port map( Input => connect(5), Output => prop_nq(5));
-
-   U15 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi6_nq_F, tHL => tpdi6_nq_R)
-	port map( Input => connect(6), Output => prop_nq(6));
-
-   U16 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi7_nq_F, tHL => tpdi7_nq_R)
-	port map( Input => connect(7), Output => prop_nq(7));
-
-   -- Netlist
-   U17 : AND4MAC
-	port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => nq);
-
-   U18 : NAND2MAC
-	port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n4);
-
-   U19 : NAND2MAC
-	port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n3);
-
-   U20 : NAND2MAC
-	port map( I0 => prop_nq(4), I1 => prop_nq(5), Y => n2);
-
-   U21 : NAND2MAC
-	port map( I0 => prop_nq(6), I1 => prop_nq(7), Y => n1);
-
-
-end FTSM;
-
-configuration CFG_noa2a2a2a24_x1_FTSM of noa2a2a2a24_x1 is
-   for FTSM
-   end for;
-end CFG_noa2a2a2a24_x1_FTSM;
-
-
------ CELL noa2a2a2a24_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa2a2a2a24_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.966 ns;
-      tpdi0_nq_F                     :	Time := 1.049 ns;
-      tpdi1_nq_R                     :	Time := 1.097 ns;
-      tpdi1_nq_F                     :	Time := 1.005 ns;
-      tpdi2_nq_R                     :	Time := 0.867 ns;
-      tpdi2_nq_F                     :	Time := 1.106 ns;
-      tpdi3_nq_R                     :	Time := 0.990 ns;
-      tpdi3_nq_F                     :	Time := 1.061 ns;
-      tpdi4_nq_R                     :	Time := 0.748 ns;
-      tpdi4_nq_F                     :	Time := 1.061 ns;
-      tpdi5_nq_R                     :	Time := 0.649 ns;
-      tpdi5_nq_F                     :	Time := 1.109 ns;
-      tpdi6_nq_R                     :	Time := 0.606 ns;
-      tpdi6_nq_F                     :	Time := 0.999 ns;
-      tpdi7_nq_R                     :	Time := 0.525 ns;
-      tpdi7_nq_F                     :	Time := 1.052 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns;
-      twdi6_R                        :	Time := 0.000 ns;
-      twdi6_F                        :	Time := 0.000 ns;
-      twdi7_R                        :	Time := 0.000 ns;
-      twdi7_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      i6                             :	in    STD_LOGIC;
-      i7                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa2a2a2a24_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of noa2a2a2a24_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi7_nq_F: constant is "U16/tLH";
-   attribute PROPAGATE_VALUE of tpdi7_nq_R: constant is "U16/tHL";
-   attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is "U15/tLH";
-   attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is "U15/tHL";
-   attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is "U14/tLH";
-   attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is "U14/tHL";
-   attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U13/tLH";
-   attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U13/tHL";
-   attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U12/tLH";
-   attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U12/tHL";
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U11/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U11/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U10/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U10/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U9/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U9/tHL";
-   attribute PROPAGATE_VALUE of twdi7_F: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of twdi7_R: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 7) := (others => 'U');
-   signal n1, n2, n3, n4 : STD_LOGIC;
-
-   component AND4MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         I3                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi3_R, tHL => twdi3_F)
-	port map( Input => i3, Output => connect(3));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi4_R, tHL => twdi4_F)
-	port map( Input => i4, Output => connect(4));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi5_R, tHL => twdi5_F)
-	port map( Input => i5, Output => connect(5));
-
-   U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi6_R, tHL => twdi6_F)
-	port map( Input => i6, Output => connect(6));
-
-   U8 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi7_R, tHL => twdi7_F)
-	port map( Input => i7, Output => connect(7));
-
-   -- Intrinsic delay buffers
-   U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R)
-	port map( Input => connect(2), Output => prop_nq(2));
-
-   U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R)
-	port map( Input => connect(3), Output => prop_nq(3));
-
-   U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R)
-	port map( Input => connect(4), Output => prop_nq(4));
-
-   U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi5_nq_F, tHL => tpdi5_nq_R)
-	port map( Input => connect(5), Output => prop_nq(5));
-
-   U15 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi6_nq_F, tHL => tpdi6_nq_R)
-	port map( Input => connect(6), Output => prop_nq(6));
-
-   U16 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi7_nq_F, tHL => tpdi7_nq_R)
-	port map( Input => connect(7), Output => prop_nq(7));
-
-   -- Netlist
-   U17 : AND4MAC
-	port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => nq);
-
-   U18 : NAND2MAC
-	port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n4);
-
-   U19 : NAND2MAC
-	port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n3);
-
-   U20 : NAND2MAC
-	port map( I0 => prop_nq(4), I1 => prop_nq(5), Y => n2);
-
-   U21 : NAND2MAC
-	port map( I0 => prop_nq(6), I1 => prop_nq(7), Y => n1);
-
-
-end FTSM;
-
-configuration CFG_noa2a2a2a24_x4_FTSM of noa2a2a2a24_x4 is
-   for FTSM
-   end for;
-end CFG_noa2a2a2a24_x4_FTSM;
-
-
------ CELL noa2a2a23_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa2a2a23_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.525 ns;
-      tpdi0_nq_F                     :	Time := 0.425 ns;
-      tpdi1_nq_R                     :	Time := 0.643 ns;
-      tpdi1_nq_F                     :	Time := 0.388 ns;
-      tpdi2_nq_R                     :	Time := 0.307 ns;
-      tpdi2_nq_F                     :	Time := 0.479 ns;
-      tpdi3_nq_R                     :	Time := 0.398 ns;
-      tpdi3_nq_F                     :	Time := 0.438 ns;
-      tpdi4_nq_R                     :	Time := 0.250 ns;
-      tpdi4_nq_F                     :	Time := 0.416 ns;
-      tpdi5_nq_R                     :	Time := 0.178 ns;
-      tpdi5_nq_F                     :	Time := 0.464 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa2a2a23_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of noa2a2a23_x1 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is "U12/tLH";
-   attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is "U12/tHL";
-   attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U11/tLH";
-   attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U11/tHL";
-   attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U10/tLH";
-   attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U10/tHL";
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U9/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U9/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 5) := (others => 'U');
-   signal n1, n2, n3 : STD_LOGIC;
-
-   component AND3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi3_R, tHL => twdi3_F)
-	port map( Input => i3, Output => connect(3));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi4_R, tHL => twdi4_F)
-	port map( Input => i4, Output => connect(4));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi5_R, tHL => twdi5_F)
-	port map( Input => i5, Output => connect(5));
-
-   -- Intrinsic delay buffers
-   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R)
-	port map( Input => connect(2), Output => prop_nq(2));
-
-   U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R)
-	port map( Input => connect(3), Output => prop_nq(3));
-
-   U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R)
-	port map( Input => connect(4), Output => prop_nq(4));
-
-   U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi5_nq_F, tHL => tpdi5_nq_R)
-	port map( Input => connect(5), Output => prop_nq(5));
-
-   -- Netlist
-   U13 : AND3MAC
-	port map( I0 => n1, I1 => n2, I2 => n3, Y => nq);
-
-   U14 : NAND2MAC
-	port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n2);
-
-   U15 : NAND2MAC
-	port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1);
-
-   U16 : NAND2MAC
-	port map( I0 => prop_nq(4), I1 => prop_nq(5), Y => n3);
-
-
-end FTSM;
-
-configuration CFG_noa2a2a23_x1_FTSM of noa2a2a23_x1 is
-   for FTSM
-   end for;
-end CFG_noa2a2a23_x1_FTSM;
-
-
------ CELL noa2a2a23_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa2a2a23_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.834 ns;
-      tpdi0_nq_F                     :	Time := 0.814 ns;
-      tpdi1_nq_R                     :	Time := 0.955 ns;
-      tpdi1_nq_F                     :	Time := 0.778 ns;
-      tpdi2_nq_R                     :	Time := 0.620 ns;
-      tpdi2_nq_F                     :	Time := 0.873 ns;
-      tpdi3_nq_R                     :	Time := 0.716 ns;
-      tpdi3_nq_F                     :	Time := 0.833 ns;
-      tpdi4_nq_R                     :	Time := 0.574 ns;
-      tpdi4_nq_F                     :	Time := 0.819 ns;
-      tpdi5_nq_R                     :	Time := 0.496 ns;
-      tpdi5_nq_F                     :	Time := 0.865 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa2a2a23_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of noa2a2a23_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is "U12/tLH";
-   attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is "U12/tHL";
-   attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U11/tLH";
-   attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U11/tHL";
-   attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U10/tLH";
-   attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U10/tHL";
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U9/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U9/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 5) := (others => 'U');
-   signal n1, n2, n3 : STD_LOGIC;
-
-   component AND3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi3_R, tHL => twdi3_F)
-	port map( Input => i3, Output => connect(3));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi4_R, tHL => twdi4_F)
-	port map( Input => i4, Output => connect(4));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi5_R, tHL => twdi5_F)
-	port map( Input => i5, Output => connect(5));
-
-   -- Intrinsic delay buffers
-   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R)
-	port map( Input => connect(2), Output => prop_nq(2));
-
-   U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R)
-	port map( Input => connect(3), Output => prop_nq(3));
-
-   U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R)
-	port map( Input => connect(4), Output => prop_nq(4));
-
-   U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi5_nq_F, tHL => tpdi5_nq_R)
-	port map( Input => connect(5), Output => prop_nq(5));
-
-   -- Netlist
-   U13 : AND3MAC
-	port map( I0 => n1, I1 => n2, I2 => n3, Y => nq);
-
-   U14 : NAND2MAC
-	port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n2);
-
-   U15 : NAND2MAC
-	port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1);
-
-   U16 : NAND2MAC
-	port map( I0 => prop_nq(4), I1 => prop_nq(5), Y => n3);
-
-
-end FTSM;
-
-configuration CFG_noa2a2a23_x4_FTSM of noa2a2a23_x4 is
-   for FTSM
-   end for;
-end CFG_noa2a2a23_x4_FTSM;
-
-
------ CELL noa2a22_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa2a22_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.151 ns;
-      tpdi0_nq_F                     :	Time := 0.327 ns;
-      tpdi1_nq_R                     :	Time := 0.218 ns;
-      tpdi1_nq_F                     :	Time := 0.287 ns;
-      tpdi2_nq_R                     :	Time := 0.284 ns;
-      tpdi2_nq_F                     :	Time := 0.289 ns;
-      tpdi3_nq_R                     :	Time := 0.372 ns;
-      tpdi3_nq_F                     :	Time := 0.256 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa2a22_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of noa2a22_x1 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
-   signal n1, n2 : STD_LOGIC;
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi3_R, tHL => twdi3_F)
-	port map( Input => i3, Output => connect(3));
-
-   -- Intrinsic delay buffers
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R)
-	port map( Input => connect(2), Output => prop_nq(2));
-
-   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R)
-	port map( Input => connect(3), Output => prop_nq(3));
-
-   -- Netlist
-   U9 : AND2MAC
-	port map( I0 => n1, I1 => n2, Y => nq);
-
-   U10 : NAND2MAC
-	port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n2);
-
-   U11 : NAND2MAC
-	port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1);
-
-
-end FTSM;
-
-configuration CFG_noa2a22_x1_FTSM of noa2a22_x1 is
-   for FTSM
-   end for;
-end CFG_noa2a22_x1_FTSM;
-
-
------ CELL noa2a22_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa2a22_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.562 ns;
-      tpdi0_nq_F                     :	Time := 0.745 ns;
-      tpdi1_nq_R                     :	Time := 0.646 ns;
-      tpdi1_nq_F                     :	Time := 0.714 ns;
-      tpdi2_nq_R                     :	Time := 0.701 ns;
-      tpdi2_nq_F                     :	Time := 0.703 ns;
-      tpdi3_nq_R                     :	Time := 0.805 ns;
-      tpdi3_nq_F                     :	Time := 0.677 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa2a22_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of noa2a22_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
-   signal n1, n2 : STD_LOGIC;
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi3_R, tHL => twdi3_F)
-	port map( Input => i3, Output => connect(3));
-
-   -- Intrinsic delay buffers
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R)
-	port map( Input => connect(2), Output => prop_nq(2));
-
-   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R)
-	port map( Input => connect(3), Output => prop_nq(3));
-
-   -- Netlist
-   U9 : AND2MAC
-	port map( I0 => n1, I1 => n2, Y => nq);
-
-   U10 : NAND2MAC
-	port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n2);
-
-   U11 : NAND2MAC
-	port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1);
-
-
-end FTSM;
-
-configuration CFG_noa2a22_x4_FTSM of noa2a22_x4 is
-   for FTSM
-   end for;
-end CFG_noa2a22_x4_FTSM;
-
-
------ CELL noa2ao222_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa2ao222_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.348 ns;
-      tpdi0_nq_F                     :	Time := 0.422 ns;
-      tpdi1_nq_R                     :	Time := 0.440 ns;
-      tpdi1_nq_F                     :	Time := 0.378 ns;
-      tpdi2_nq_R                     :	Time := 0.186 ns;
-      tpdi2_nq_F                     :	Time := 0.473 ns;
-      tpdi3_nq_R                     :	Time := 0.256 ns;
-      tpdi3_nq_F                     :	Time := 0.459 ns;
-      tpdi4_nq_R                     :	Time := 0.240 ns;
-      tpdi4_nq_F                     :	Time := 0.309 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa2ao222_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of noa2ao222_x1 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U10/tLH";
-   attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U10/tHL";
-   attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U9/tLH";
-   attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U9/tHL";
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 4) := (others => 'U');
-   signal n1, n2, n3 : STD_LOGIC;
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component OR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi3_R, tHL => twdi3_F)
-	port map( Input => i3, Output => connect(3));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi4_R, tHL => twdi4_F)
-	port map( Input => i4, Output => connect(4));
-
-   -- Intrinsic delay buffers
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R)
-	port map( Input => connect(2), Output => prop_nq(2));
-
-   U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R)
-	port map( Input => connect(3), Output => prop_nq(3));
-
-   U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R)
-	port map( Input => connect(4), Output => prop_nq(4));
-
-   -- Netlist
-   U11 : AND2MAC
-	port map( I0 => n1, I1 => n2, Y => nq);
-
-   U12 : OR2MAC
-	port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n3);
-
-   U13 : NAND2MAC
-	port map( I0 => prop_nq(4), I1 => n3, Y => n2);
-
-   U14 : NAND2MAC
-	port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1);
-
-
-end FTSM;
-
-configuration CFG_noa2ao222_x1_FTSM of noa2ao222_x1 is
-   for FTSM
-   end for;
-end CFG_noa2ao222_x1_FTSM;
-
-
------ CELL noa2ao222_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa2ao222_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.684 ns;
-      tpdi0_nq_F                     :	Time := 0.801 ns;
-      tpdi1_nq_R                     :	Time := 0.780 ns;
-      tpdi1_nq_F                     :	Time := 0.758 ns;
-      tpdi2_nq_R                     :	Time := 0.638 ns;
-      tpdi2_nq_F                     :	Time := 0.809 ns;
-      tpdi3_nq_R                     :	Time := 0.732 ns;
-      tpdi3_nq_F                     :	Time := 0.795 ns;
-      tpdi4_nq_R                     :	Time := 0.718 ns;
-      tpdi4_nq_F                     :	Time := 0.664 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa2ao222_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of noa2ao222_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U10/tLH";
-   attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U10/tHL";
-   attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U9/tLH";
-   attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U9/tHL";
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 4) := (others => 'U');
-   signal n1, n2, n3 : STD_LOGIC;
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component OR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi3_R, tHL => twdi3_F)
-	port map( Input => i3, Output => connect(3));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi4_R, tHL => twdi4_F)
-	port map( Input => i4, Output => connect(4));
-
-   -- Intrinsic delay buffers
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R)
-	port map( Input => connect(2), Output => prop_nq(2));
-
-   U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R)
-	port map( Input => connect(3), Output => prop_nq(3));
-
-   U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R)
-	port map( Input => connect(4), Output => prop_nq(4));
-
-   -- Netlist
-   U11 : AND2MAC
-	port map( I0 => n1, I1 => n2, Y => nq);
-
-   U12 : OR2MAC
-	port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n3);
-
-   U13 : NAND2MAC
-	port map( I0 => prop_nq(4), I1 => n3, Y => n2);
-
-   U14 : NAND2MAC
-	port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1);
-
-
-end FTSM;
-
-configuration CFG_noa2ao222_x4_FTSM of noa2ao222_x4 is
-   for FTSM
-   end for;
-end CFG_noa2ao222_x4_FTSM;
-
-
------ CELL noa3ao322_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa3ao322_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.396 ns;
-      tpdi0_nq_F                     :	Time := 0.616 ns;
-      tpdi1_nq_R                     :	Time := 0.486 ns;
-      tpdi1_nq_F                     :	Time := 0.552 ns;
-      tpdi2_nq_R                     :	Time := 0.546 ns;
-      tpdi2_nq_F                     :	Time := 0.488 ns;
-      tpdi3_nq_R                     :	Time := 0.196 ns;
-      tpdi3_nq_F                     :	Time := 0.599 ns;
-      tpdi4_nq_R                     :	Time := 0.264 ns;
-      tpdi4_nq_F                     :	Time := 0.608 ns;
-      tpdi5_nq_R                     :	Time := 0.328 ns;
-      tpdi5_nq_F                     :	Time := 0.581 ns;
-      tpdi6_nq_R                     :	Time := 0.246 ns;
-      tpdi6_nq_F                     :	Time := 0.311 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns;
-      twdi6_R                        :	Time := 0.000 ns;
-      twdi6_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      i6                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa3ao322_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of noa3ao322_x1 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is "U14/tLH";
-   attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is "U14/tHL";
-   attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is "U13/tLH";
-   attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is "U13/tHL";
-   attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U12/tLH";
-   attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U12/tHL";
-   attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U11/tLH";
-   attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U11/tHL";
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U10/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U10/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U9/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U9/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 6) := (others => 'U');
-   signal n1, n2, n3 : STD_LOGIC;
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component OR3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi3_R, tHL => twdi3_F)
-	port map( Input => i3, Output => connect(3));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi4_R, tHL => twdi4_F)
-	port map( Input => i4, Output => connect(4));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi5_R, tHL => twdi5_F)
-	port map( Input => i5, Output => connect(5));
-
-   U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi6_R, tHL => twdi6_F)
-	port map( Input => i6, Output => connect(6));
-
-   -- Intrinsic delay buffers
-   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R)
-	port map( Input => connect(2), Output => prop_nq(2));
-
-   U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R)
-	port map( Input => connect(3), Output => prop_nq(3));
-
-   U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R)
-	port map( Input => connect(4), Output => prop_nq(4));
-
-   U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi5_nq_F, tHL => tpdi5_nq_R)
-	port map( Input => connect(5), Output => prop_nq(5));
-
-   U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi6_nq_F, tHL => tpdi6_nq_R)
-	port map( Input => connect(6), Output => prop_nq(6));
-
-   -- Netlist
-   U15 : AND2MAC
-	port map( I0 => n1, I1 => n2, Y => nq);
-
-   U16 : NAND3MAC
-	port map( I0 => prop_nq(1), I1 => prop_nq(2), I2 => prop_nq(0), Y => 
-         n2);
-
-   U17 : OR3MAC
-	port map( I0 => prop_nq(3), I1 => prop_nq(4), I2 => prop_nq(5), Y => 
-         n3);
-
-   U18 : NAND2MAC
-	port map( I0 => prop_nq(6), I1 => n3, Y => n1);
-
-
-end FTSM;
-
-configuration CFG_noa3ao322_x1_FTSM of noa3ao322_x1 is
-   for FTSM
-   end for;
-end CFG_noa3ao322_x1_FTSM;
-
-
------ CELL noa3ao322_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa3ao322_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.819 ns;
-      tpdi0_nq_F                     :	Time := 0.987 ns;
-      tpdi1_nq_R                     :	Time := 0.914 ns;
-      tpdi1_nq_F                     :	Time := 0.931 ns;
-      tpdi2_nq_R                     :	Time := 0.990 ns;
-      tpdi2_nq_F                     :	Time := 0.874 ns;
-      tpdi3_nq_R                     :	Time := 0.729 ns;
-      tpdi3_nq_F                     :	Time := 0.926 ns;
-      tpdi4_nq_R                     :	Time := 0.821 ns;
-      tpdi4_nq_F                     :	Time := 0.924 ns;
-      tpdi5_nq_R                     :	Time := 0.907 ns;
-      tpdi5_nq_F                     :	Time := 0.900 ns;
-      tpdi6_nq_R                     :	Time := 0.738 ns;
-      tpdi6_nq_F                     :	Time := 0.718 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns;
-      twdi6_R                        :	Time := 0.000 ns;
-      twdi6_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      i6                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa3ao322_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of noa3ao322_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is "U14/tLH";
-   attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is "U14/tHL";
-   attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is "U13/tLH";
-   attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is "U13/tHL";
-   attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U12/tLH";
-   attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U12/tHL";
-   attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U11/tLH";
-   attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U11/tHL";
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U10/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U10/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U9/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U9/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 6) := (others => 'U');
-   signal n1, n2, n3 : STD_LOGIC;
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component OR3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi3_R, tHL => twdi3_F)
-	port map( Input => i3, Output => connect(3));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi4_R, tHL => twdi4_F)
-	port map( Input => i4, Output => connect(4));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi5_R, tHL => twdi5_F)
-	port map( Input => i5, Output => connect(5));
-
-   U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi6_R, tHL => twdi6_F)
-	port map( Input => i6, Output => connect(6));
-
-   -- Intrinsic delay buffers
-   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R)
-	port map( Input => connect(2), Output => prop_nq(2));
-
-   U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R)
-	port map( Input => connect(3), Output => prop_nq(3));
-
-   U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R)
-	port map( Input => connect(4), Output => prop_nq(4));
-
-   U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi5_nq_F, tHL => tpdi5_nq_R)
-	port map( Input => connect(5), Output => prop_nq(5));
-
-   U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi6_nq_F, tHL => tpdi6_nq_R)
-	port map( Input => connect(6), Output => prop_nq(6));
-
-   -- Netlist
-   U15 : AND2MAC
-	port map( I0 => n1, I1 => n2, Y => nq);
-
-   U16 : NAND3MAC
-	port map( I0 => prop_nq(1), I1 => prop_nq(2), I2 => prop_nq(0), Y => 
-         n2);
-
-   U17 : OR3MAC
-	port map( I0 => prop_nq(3), I1 => prop_nq(4), I2 => prop_nq(5), Y => 
-         n3);
-
-   U18 : NAND2MAC
-	port map( I0 => prop_nq(6), I1 => n3, Y => n1);
-
-
-end FTSM;
-
-configuration CFG_noa3ao322_x4_FTSM of noa3ao322_x4 is
-   for FTSM
-   end for;
-end CFG_noa3ao322_x4_FTSM;
-
-
------ CELL noa22_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa22_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.151 ns;
-      tpdi0_nq_F                     :	Time := 0.327 ns;
-      tpdi1_nq_R                     :	Time := 0.218 ns;
-      tpdi1_nq_F                     :	Time := 0.287 ns;
-      tpdi2_nq_R                     :	Time := 0.218 ns;
-      tpdi2_nq_F                     :	Time := 0.241 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa22_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of noa22_x1 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-   signal n1 : STD_LOGIC;
-
-   component NOR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   -- Intrinsic delay buffers
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R)
-	port map( Input => connect(2), Output => prop_nq(2));
-
-   -- Netlist
-   U7 : NOR2MAC
-	port map( I0 => prop_nq(2), I1 => n1, Y => nq);
-
-   U8 : AND2MAC
-	port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1);
-
-
-end FTSM;
-
-configuration CFG_noa22_x1_FTSM of noa22_x1 is
-   for FTSM
-   end for;
-end CFG_noa22_x1_FTSM;
-
-
------ CELL noa22_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa22_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.550 ns;
-      tpdi0_nq_F                     :	Time := 0.740 ns;
-      tpdi1_nq_R                     :	Time := 0.643 ns;
-      tpdi1_nq_F                     :	Time := 0.709 ns;
-      tpdi2_nq_R                     :	Time := 0.610 ns;
-      tpdi2_nq_F                     :	Time := 0.646 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa22_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of noa22_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-   signal n1 : STD_LOGIC;
-
-   component NOR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   -- Intrinsic delay buffers
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R)
-	port map( Input => connect(2), Output => prop_nq(2));
-
-   -- Netlist
-   U7 : NOR2MAC
-	port map( I0 => prop_nq(2), I1 => n1, Y => nq);
-
-   U8 : AND2MAC
-	port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1);
-
-
-end FTSM;
-
-configuration CFG_noa22_x4_FTSM of noa22_x4 is
-   for FTSM
-   end for;
-end CFG_noa22_x4_FTSM;
-
-
------ CELL nts_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nts_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd_nq_R                    :	Time := 0.249 ns;
-      tpdcmd_nq_F                    :	Time := 0.041 ns;
-      tpdcmd_nq_LZ                   :	Time := 0.249 ns;
-      tpdcmd_nq_HZ                   :	Time := 0.041 ns;
-      tpdi_nq_R                      :	Time := 0.169 ns;
-      tpdi_nq_F                      :	Time := 0.201 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      cmd                            :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nts_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of nts_x1 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi_nq_F: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi_nq_R: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is "U3/tHL, U3/tLH";
-   attribute PROPAGATE_VALUE of tpdcmd_nq_HZ: constant is "U3/tLH, U3/tHL";
-   attribute PROPAGATE_VALUE of tpdcmd_nq_LZ: constant is "U3/tLH, U3/tHL";
-   attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is "U3/tLH, U3/tHL";
-   attribute PROPAGATE_VALUE of twdcmd_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdcmd_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-
-   component INV3SHEMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         OE                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi_R, tHL => twdi_F)
-	port map( Input => i, Output => connect(1));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdcmd_R, tHL => twdcmd_F)
-	port map( Input => cmd, Output => connect(0));
-
-   -- Intrinsic delay buffers
-   U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdcmd_nq_R, tHL => tpdcmd_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi_nq_F, tHL => tpdi_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   -- Netlist
-   U5 : INV3SHEMAC
-	port map( I0 => prop_nq(1), OE => prop_nq(0), Y => nq);
-
-
-end FTSM;
-
-configuration CFG_nts_x1_FTSM of nts_x1 is
-   for FTSM
-   end for;
-end CFG_nts_x1_FTSM;
-
-
------ CELL nts_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nts_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd_nq_R                    :	Time := 0.330 ns;
-      tpdcmd_nq_F                    :	Time := 0.033 ns;
-      tpdcmd_nq_LZ                   :	Time := 0.330 ns;
-      tpdcmd_nq_HZ                   :	Time := 0.033 ns;
-      tpdi_nq_R                      :	Time := 0.167 ns;
-      tpdi_nq_F                      :	Time := 0.201 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      cmd                            :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nts_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of nts_x2 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi_nq_F: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi_nq_R: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is "U3/tHL, U3/tLH";
-   attribute PROPAGATE_VALUE of tpdcmd_nq_HZ: constant is "U3/tLH, U3/tHL";
-   attribute PROPAGATE_VALUE of tpdcmd_nq_LZ: constant is "U3/tLH, U3/tHL";
-   attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is "U3/tLH, U3/tHL";
-   attribute PROPAGATE_VALUE of twdcmd_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdcmd_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-
-   component INV3SHEMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         OE                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi_R, tHL => twdi_F)
-	port map( Input => i, Output => connect(1));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdcmd_R, tHL => twdcmd_F)
-	port map( Input => cmd, Output => connect(0));
-
-   -- Intrinsic delay buffers
-   U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdcmd_nq_R, tHL => tpdcmd_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi_nq_F, tHL => tpdi_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   -- Netlist
-   U5 : INV3SHEMAC
-	port map( I0 => prop_nq(1), OE => prop_nq(0), Y => nq);
-
-
-end FTSM;
-
-configuration CFG_nts_x2_FTSM of nts_x2 is
-   for FTSM
-   end for;
-end CFG_nts_x2_FTSM;
-
-
------ CELL nxr2_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nxr2_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.288 ns;
-      tpdi0_nq_F                     :	Time := 0.293 ns;
-      tpdi1_nq_R                     :	Time := 0.156 ns;
-      tpdi1_nq_F                     :	Time := 0.327 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nxr2_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of nxr2_x1 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-
-   component NXOR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   -- Intrinsic delay buffers
-   U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   -- Netlist
-   U5 : NXOR2MAC
-	port map( I0 => prop_nq(1), I1 => prop_nq(0), Y => nq);
-
-
-end FTSM;
-
-configuration CFG_nxr2_x1_FTSM of nxr2_x1 is
-   for FTSM
-   end for;
-end CFG_nxr2_x1_FTSM;
-
-
------ CELL nxr2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nxr2_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.522 ns;
-      tpdi0_nq_F                     :	Time := 0.553 ns;
-      tpdi1_nq_R                     :	Time := 0.553 ns;
-      tpdi1_nq_F                     :	Time := 0.542 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nxr2_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of nxr2_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-   signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-
-   component NXOR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   -- Intrinsic delay buffers
-   U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R)
-	port map( Input => connect(0), Output => prop_nq(0));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R)
-	port map( Input => connect(1), Output => prop_nq(1));
-
-   -- Netlist
-   U5 : NXOR2MAC
-	port map( I0 => prop_nq(1), I1 => prop_nq(0), Y => nq);
-
-
-end FTSM;
-
-configuration CFG_nxr2_x4_FTSM of nxr2_x4 is
-   for FTSM
-   end for;
-end CFG_nxr2_x4_FTSM;
-
-
------ CELL o2_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity o2_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.406 ns;
-      tpdi0_q_F                      :	Time := 0.310 ns;
-      tpdi1_q_R                      :	Time := 0.335 ns;
-      tpdi1_q_F                      :	Time := 0.364 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end o2_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of o2_x2 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-
-   component OR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   -- Intrinsic delay buffers
-   U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   -- Netlist
-   U5 : OR2MAC
-	port map( I0 => prop_q(1), I1 => prop_q(0), Y => q);
-
-
-end FTSM;
-
-configuration CFG_o2_x2_FTSM of o2_x2 is
-   for FTSM
-   end for;
-end CFG_o2_x2_FTSM;
-
-
------ CELL o2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity o2_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.491 ns;
-      tpdi0_q_F                      :	Time := 0.394 ns;
-      tpdi1_q_R                      :	Time := 0.427 ns;
-      tpdi1_q_F                      :	Time := 0.464 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end o2_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of o2_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-
-   component OR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   -- Intrinsic delay buffers
-   U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   -- Netlist
-   U5 : OR2MAC
-	port map( I0 => prop_q(1), I1 => prop_q(0), Y => q);
-
-
-end FTSM;
-
-configuration CFG_o2_x4_FTSM of o2_x4 is
-   for FTSM
-   end for;
-end CFG_o2_x4_FTSM;
-
-
------ CELL o3_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity o3_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.494 ns;
-      tpdi0_q_F                      :	Time := 0.407 ns;
-      tpdi1_q_R                      :	Time := 0.430 ns;
-      tpdi1_q_F                      :	Time := 0.482 ns;
-      tpdi2_q_R                      :	Time := 0.360 ns;
-      tpdi2_q_F                      :	Time := 0.506 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end o3_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of o3_x2 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-
-   component OR3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   -- Intrinsic delay buffers
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F)
-	port map( Input => connect(2), Output => prop_q(2));
-
-   -- Netlist
-   U7 : OR3MAC
-	port map( I0 => prop_q(0), I1 => prop_q(1), I2 => prop_q(2), Y => 
-         q);
-
-
-end FTSM;
-
-configuration CFG_o3_x2_FTSM of o3_x2 is
-   for FTSM
-   end for;
-end CFG_o3_x2_FTSM;
-
-
------ CELL o3_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity o3_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.569 ns;
-      tpdi0_q_F                      :	Time := 0.501 ns;
-      tpdi1_q_R                      :	Time := 0.510 ns;
-      tpdi1_q_F                      :	Time := 0.585 ns;
-      tpdi2_q_R                      :	Time := 0.447 ns;
-      tpdi2_q_F                      :	Time := 0.622 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end o3_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of o3_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-
-   component OR3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   -- Intrinsic delay buffers
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F)
-	port map( Input => connect(2), Output => prop_q(2));
-
-   -- Netlist
-   U7 : OR3MAC
-	port map( I0 => prop_q(0), I1 => prop_q(1), I2 => prop_q(2), Y => 
-         q);
-
-
-end FTSM;
-
-configuration CFG_o3_x4_FTSM of o3_x4 is
-   for FTSM
-   end for;
-end CFG_o3_x4_FTSM;
-
-
------ CELL o4_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity o4_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.508 ns;
-      tpdi0_q_F                      :	Time := 0.601 ns;
-      tpdi1_q_R                      :	Time := 0.446 ns;
-      tpdi1_q_F                      :	Time := 0.631 ns;
-      tpdi2_q_R                      :	Time := 0.567 ns;
-      tpdi2_q_F                      :	Time := 0.531 ns;
-      tpdi3_q_R                      :	Time := 0.378 ns;
-      tpdi3_q_F                      :	Time := 0.626 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end o4_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of o4_x2 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
-
-   component OR4MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         I3                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi3_R, tHL => twdi3_F)
-	port map( Input => i3, Output => connect(3));
-
-   -- Intrinsic delay buffers
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F)
-	port map( Input => connect(2), Output => prop_q(2));
-
-   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F)
-	port map( Input => connect(3), Output => prop_q(3));
-
-   -- Netlist
-   U9 : OR4MAC
-	port map( I0 => prop_q(2), I1 => prop_q(3), I2 => prop_q(0), I3 => 
-         prop_q(1), Y => q);
-
-
-end FTSM;
-
-configuration CFG_o4_x2_FTSM of o4_x2 is
-   for FTSM
-   end for;
-end CFG_o4_x2_FTSM;
-
-
------ CELL o4_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity o4_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.574 ns;
-      tpdi0_q_F                      :	Time := 0.638 ns;
-      tpdi1_q_R                      :	Time := 0.492 ns;
-      tpdi1_q_F                      :	Time := 0.650 ns;
-      tpdi2_q_R                      :	Time := 0.649 ns;
-      tpdi2_q_F                      :	Time := 0.611 ns;
-      tpdi3_q_R                      :	Time := 0.721 ns;
-      tpdi3_q_F                      :	Time := 0.536 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end o4_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of o4_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
-
-   component OR4MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         I3                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi3_R, tHL => twdi3_F)
-	port map( Input => i3, Output => connect(3));
-
-   -- Intrinsic delay buffers
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F)
-	port map( Input => connect(2), Output => prop_q(2));
-
-   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F)
-	port map( Input => connect(3), Output => prop_q(3));
-
-   -- Netlist
-   U9 : OR4MAC
-	port map( I0 => prop_q(2), I1 => prop_q(3), I2 => prop_q(0), I3 => 
-         prop_q(1), Y => q);
-
-
-end FTSM;
-
-configuration CFG_o4_x4_FTSM of o4_x4 is
-   for FTSM
-   end for;
-end CFG_o4_x4_FTSM;
-
-
------ CELL oa2a2a2a24_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa2a2a2a24_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.780 ns;
-      tpdi0_q_F                      :	Time := 0.797 ns;
-      tpdi1_q_R                      :	Time := 0.909 ns;
-      tpdi1_q_F                      :	Time := 0.753 ns;
-      tpdi2_q_R                      :	Time := 0.682 ns;
-      tpdi2_q_F                      :	Time := 0.856 ns;
-      tpdi3_q_R                      :	Time := 0.803 ns;
-      tpdi3_q_F                      :	Time := 0.810 ns;
-      tpdi4_q_R                      :	Time := 0.565 ns;
-      tpdi4_q_F                      :	Time := 0.813 ns;
-      tpdi5_q_R                      :	Time := 0.467 ns;
-      tpdi5_q_F                      :	Time := 0.861 ns;
-      tpdi6_q_R                      :	Time := 0.426 ns;
-      tpdi6_q_F                      :	Time := 0.748 ns;
-      tpdi7_q_R                      :	Time := 0.346 ns;
-      tpdi7_q_F                      :	Time := 0.800 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns;
-      twdi6_R                        :	Time := 0.000 ns;
-      twdi6_F                        :	Time := 0.000 ns;
-      twdi7_R                        :	Time := 0.000 ns;
-      twdi7_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      i6                             :	in    STD_LOGIC;
-      i7                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa2a2a2a24_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of oa2a2a2a24_x2 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi7_q_R: constant is "U16/tLH";
-   attribute PROPAGATE_VALUE of tpdi7_q_F: constant is "U16/tHL";
-   attribute PROPAGATE_VALUE of tpdi6_q_R: constant is "U15/tLH";
-   attribute PROPAGATE_VALUE of tpdi6_q_F: constant is "U15/tHL";
-   attribute PROPAGATE_VALUE of tpdi5_q_R: constant is "U14/tLH";
-   attribute PROPAGATE_VALUE of tpdi5_q_F: constant is "U14/tHL";
-   attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U13/tLH";
-   attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U13/tHL";
-   attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U12/tLH";
-   attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U12/tHL";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U11/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U11/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U10/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U10/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U9/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U9/tHL";
-   attribute PROPAGATE_VALUE of twdi7_F: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of twdi7_R: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 7) := (others => 'U');
-   signal n1, n2, n3, n4 : STD_LOGIC;
-
-   component NAND4MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         I3                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi3_R, tHL => twdi3_F)
-	port map( Input => i3, Output => connect(3));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi4_R, tHL => twdi4_F)
-	port map( Input => i4, Output => connect(4));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi5_R, tHL => twdi5_F)
-	port map( Input => i5, Output => connect(5));
-
-   U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi6_R, tHL => twdi6_F)
-	port map( Input => i6, Output => connect(6));
-
-   U8 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi7_R, tHL => twdi7_F)
-	port map( Input => i7, Output => connect(7));
-
-   -- Intrinsic delay buffers
-   U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F)
-	port map( Input => connect(2), Output => prop_q(2));
-
-   U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F)
-	port map( Input => connect(3), Output => prop_q(3));
-
-   U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F)
-	port map( Input => connect(4), Output => prop_q(4));
-
-   U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi5_q_R, tHL => tpdi5_q_F)
-	port map( Input => connect(5), Output => prop_q(5));
-
-   U15 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi6_q_R, tHL => tpdi6_q_F)
-	port map( Input => connect(6), Output => prop_q(6));
-
-   U16 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi7_q_R, tHL => tpdi7_q_F)
-	port map( Input => connect(7), Output => prop_q(7));
-
-   -- Netlist
-   U17 : NAND4MAC
-	port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => q);
-
-   U18 : NAND2MAC
-	port map( I0 => prop_q(6), I1 => prop_q(7), Y => n4);
-
-   U19 : NAND2MAC
-	port map( I0 => prop_q(4), I1 => prop_q(5), Y => n3);
-
-   U20 : NAND2MAC
-	port map( I0 => prop_q(2), I1 => prop_q(3), Y => n2);
-
-   U21 : NAND2MAC
-	port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1);
-
-
-end FTSM;
-
-configuration CFG_oa2a2a2a24_x2_FTSM of oa2a2a2a24_x2 is
-   for FTSM
-   end for;
-end CFG_oa2a2a2a24_x2_FTSM;
-
-
------ CELL oa2a2a2a24_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa2a2a2a24_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.823 ns;
-      tpdi0_q_F                      :	Time := 0.879 ns;
-      tpdi1_q_R                      :	Time := 0.955 ns;
-      tpdi1_q_F                      :	Time := 0.835 ns;
-      tpdi2_q_R                      :	Time := 0.726 ns;
-      tpdi2_q_F                      :	Time := 0.940 ns;
-      tpdi3_q_R                      :	Time := 0.851 ns;
-      tpdi3_q_F                      :	Time := 0.895 ns;
-      tpdi4_q_R                      :	Time := 0.619 ns;
-      tpdi4_q_F                      :	Time := 0.902 ns;
-      tpdi5_q_R                      :	Time := 0.515 ns;
-      tpdi5_q_F                      :	Time := 0.949 ns;
-      tpdi6_q_R                      :	Time := 0.487 ns;
-      tpdi6_q_F                      :	Time := 0.845 ns;
-      tpdi7_q_R                      :	Time := 0.399 ns;
-      tpdi7_q_F                      :	Time := 0.895 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns;
-      twdi6_R                        :	Time := 0.000 ns;
-      twdi6_F                        :	Time := 0.000 ns;
-      twdi7_R                        :	Time := 0.000 ns;
-      twdi7_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      i6                             :	in    STD_LOGIC;
-      i7                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa2a2a2a24_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of oa2a2a2a24_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi7_q_R: constant is "U16/tLH";
-   attribute PROPAGATE_VALUE of tpdi7_q_F: constant is "U16/tHL";
-   attribute PROPAGATE_VALUE of tpdi6_q_R: constant is "U15/tLH";
-   attribute PROPAGATE_VALUE of tpdi6_q_F: constant is "U15/tHL";
-   attribute PROPAGATE_VALUE of tpdi5_q_R: constant is "U14/tLH";
-   attribute PROPAGATE_VALUE of tpdi5_q_F: constant is "U14/tHL";
-   attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U13/tLH";
-   attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U13/tHL";
-   attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U12/tLH";
-   attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U12/tHL";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U11/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U11/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U10/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U10/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U9/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U9/tHL";
-   attribute PROPAGATE_VALUE of twdi7_F: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of twdi7_R: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 7) := (others => 'U');
-   signal n1, n2, n3, n4 : STD_LOGIC;
-
-   component NAND4MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         I3                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi3_R, tHL => twdi3_F)
-	port map( Input => i3, Output => connect(3));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi4_R, tHL => twdi4_F)
-	port map( Input => i4, Output => connect(4));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi5_R, tHL => twdi5_F)
-	port map( Input => i5, Output => connect(5));
-
-   U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi6_R, tHL => twdi6_F)
-	port map( Input => i6, Output => connect(6));
-
-   U8 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi7_R, tHL => twdi7_F)
-	port map( Input => i7, Output => connect(7));
-
-   -- Intrinsic delay buffers
-   U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F)
-	port map( Input => connect(2), Output => prop_q(2));
-
-   U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F)
-	port map( Input => connect(3), Output => prop_q(3));
-
-   U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F)
-	port map( Input => connect(4), Output => prop_q(4));
-
-   U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi5_q_R, tHL => tpdi5_q_F)
-	port map( Input => connect(5), Output => prop_q(5));
-
-   U15 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi6_q_R, tHL => tpdi6_q_F)
-	port map( Input => connect(6), Output => prop_q(6));
-
-   U16 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi7_q_R, tHL => tpdi7_q_F)
-	port map( Input => connect(7), Output => prop_q(7));
-
-   -- Netlist
-   U17 : NAND4MAC
-	port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => q);
-
-   U18 : NAND2MAC
-	port map( I0 => prop_q(6), I1 => prop_q(7), Y => n4);
-
-   U19 : NAND2MAC
-	port map( I0 => prop_q(4), I1 => prop_q(5), Y => n3);
-
-   U20 : NAND2MAC
-	port map( I0 => prop_q(2), I1 => prop_q(3), Y => n2);
-
-   U21 : NAND2MAC
-	port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1);
-
-
-end FTSM;
-
-configuration CFG_oa2a2a2a24_x4_FTSM of oa2a2a2a24_x4 is
-   for FTSM
-   end for;
-end CFG_oa2a2a2a24_x4_FTSM;
-
-
------ CELL oa2a2a23_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa2a2a23_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.653 ns;
-      tpdi0_q_F                      :	Time := 0.578 ns;
-      tpdi1_q_R                      :	Time := 0.775 ns;
-      tpdi1_q_F                      :	Time := 0.542 ns;
-      tpdi2_q_R                      :	Time := 0.441 ns;
-      tpdi2_q_F                      :	Time := 0.639 ns;
-      tpdi3_q_R                      :	Time := 0.540 ns;
-      tpdi3_q_F                      :	Time := 0.600 ns;
-      tpdi4_q_R                      :	Time := 0.402 ns;
-      tpdi4_q_F                      :	Time := 0.591 ns;
-      tpdi5_q_R                      :	Time := 0.321 ns;
-      tpdi5_q_F                      :	Time := 0.636 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa2a2a23_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of oa2a2a23_x2 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi5_q_R: constant is "U12/tLH";
-   attribute PROPAGATE_VALUE of tpdi5_q_F: constant is "U12/tHL";
-   attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U11/tLH";
-   attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U11/tHL";
-   attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U10/tLH";
-   attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U10/tHL";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U9/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U9/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 5) := (others => 'U');
-   signal n1, n2, n3 : STD_LOGIC;
-
-   component NAND3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi3_R, tHL => twdi3_F)
-	port map( Input => i3, Output => connect(3));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi4_R, tHL => twdi4_F)
-	port map( Input => i4, Output => connect(4));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi5_R, tHL => twdi5_F)
-	port map( Input => i5, Output => connect(5));
-
-   -- Intrinsic delay buffers
-   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F)
-	port map( Input => connect(2), Output => prop_q(2));
-
-   U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F)
-	port map( Input => connect(3), Output => prop_q(3));
-
-   U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F)
-	port map( Input => connect(4), Output => prop_q(4));
-
-   U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi5_q_R, tHL => tpdi5_q_F)
-	port map( Input => connect(5), Output => prop_q(5));
-
-   -- Netlist
-   U13 : NAND3MAC
-	port map( I0 => n1, I1 => n2, I2 => n3, Y => q);
-
-   U14 : NAND2MAC
-	port map( I0 => prop_q(4), I1 => prop_q(5), Y => n2);
-
-   U15 : NAND2MAC
-	port map( I0 => prop_q(2), I1 => prop_q(3), Y => n1);
-
-   U16 : NAND2MAC
-	port map( I0 => prop_q(0), I1 => prop_q(1), Y => n3);
-
-
-end FTSM;
-
-configuration CFG_oa2a2a23_x2_FTSM of oa2a2a23_x2 is
-   for FTSM
-   end for;
-end CFG_oa2a2a23_x2_FTSM;
-
-
------ CELL oa2a2a23_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa2a2a23_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.699 ns;
-      tpdi0_q_F                      :	Time := 0.648 ns;
-      tpdi1_q_R                      :	Time := 0.822 ns;
-      tpdi1_q_F                      :	Time := 0.613 ns;
-      tpdi2_q_R                      :	Time := 0.493 ns;
-      tpdi2_q_F                      :	Time := 0.715 ns;
-      tpdi3_q_R                      :	Time := 0.594 ns;
-      tpdi3_q_F                      :	Time := 0.677 ns;
-      tpdi4_q_R                      :	Time := 0.464 ns;
-      tpdi4_q_F                      :	Time := 0.673 ns;
-      tpdi5_q_R                      :	Time := 0.379 ns;
-      tpdi5_q_F                      :	Time := 0.714 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa2a2a23_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of oa2a2a23_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi5_q_R: constant is "U12/tLH";
-   attribute PROPAGATE_VALUE of tpdi5_q_F: constant is "U12/tHL";
-   attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U11/tLH";
-   attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U11/tHL";
-   attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U10/tLH";
-   attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U10/tHL";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U9/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U9/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 5) := (others => 'U');
-   signal n1, n2, n3 : STD_LOGIC;
-
-   component NAND3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi3_R, tHL => twdi3_F)
-	port map( Input => i3, Output => connect(3));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi4_R, tHL => twdi4_F)
-	port map( Input => i4, Output => connect(4));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi5_R, tHL => twdi5_F)
-	port map( Input => i5, Output => connect(5));
-
-   -- Intrinsic delay buffers
-   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F)
-	port map( Input => connect(2), Output => prop_q(2));
-
-   U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F)
-	port map( Input => connect(3), Output => prop_q(3));
-
-   U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F)
-	port map( Input => connect(4), Output => prop_q(4));
-
-   U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi5_q_R, tHL => tpdi5_q_F)
-	port map( Input => connect(5), Output => prop_q(5));
-
-   -- Netlist
-   U13 : NAND3MAC
-	port map( I0 => n1, I1 => n2, I2 => n3, Y => q);
-
-   U14 : NAND2MAC
-	port map( I0 => prop_q(4), I1 => prop_q(5), Y => n2);
-
-   U15 : NAND2MAC
-	port map( I0 => prop_q(2), I1 => prop_q(3), Y => n1);
-
-   U16 : NAND2MAC
-	port map( I0 => prop_q(0), I1 => prop_q(1), Y => n3);
-
-
-end FTSM;
-
-configuration CFG_oa2a2a23_x4_FTSM of oa2a2a23_x4 is
-   for FTSM
-   end for;
-end CFG_oa2a2a23_x4_FTSM;
-
-
------ CELL oa2a22_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa2a22_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.403 ns;
-      tpdi0_q_F                      :	Time := 0.564 ns;
-      tpdi1_q_R                      :	Time := 0.495 ns;
-      tpdi1_q_F                      :	Time := 0.534 ns;
-      tpdi2_q_R                      :	Time := 0.646 ns;
-      tpdi2_q_F                      :	Time := 0.487 ns;
-      tpdi3_q_R                      :	Time := 0.537 ns;
-      tpdi3_q_F                      :	Time := 0.512 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa2a22_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of oa2a22_x2 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
-   signal n1, n2 : STD_LOGIC;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi3_R, tHL => twdi3_F)
-	port map( Input => i3, Output => connect(3));
-
-   -- Intrinsic delay buffers
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F)
-	port map( Input => connect(2), Output => prop_q(2));
-
-   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F)
-	port map( Input => connect(3), Output => prop_q(3));
-
-   -- Netlist
-   U9 : NAND2MAC
-	port map( I0 => n1, I1 => n2, Y => q);
-
-   U10 : NAND2MAC
-	port map( I0 => prop_q(2), I1 => prop_q(3), Y => n2);
-
-   U11 : NAND2MAC
-	port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1);
-
-
-end FTSM;
-
-configuration CFG_oa2a22_x2_FTSM of oa2a22_x2 is
-   for FTSM
-   end for;
-end CFG_oa2a22_x2_FTSM;
-
-
------ CELL oa2a22_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa2a22_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.519 ns;
-      tpdi0_q_F                      :	Time := 0.696 ns;
-      tpdi1_q_R                      :	Time := 0.624 ns;
-      tpdi1_q_F                      :	Time := 0.669 ns;
-      tpdi2_q_R                      :	Time := 0.763 ns;
-      tpdi2_q_F                      :	Time := 0.596 ns;
-      tpdi3_q_R                      :	Time := 0.644 ns;
-      tpdi3_q_F                      :	Time := 0.619 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa2a22_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of oa2a22_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
-   signal n1, n2 : STD_LOGIC;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi3_R, tHL => twdi3_F)
-	port map( Input => i3, Output => connect(3));
-
-   -- Intrinsic delay buffers
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F)
-	port map( Input => connect(2), Output => prop_q(2));
-
-   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F)
-	port map( Input => connect(3), Output => prop_q(3));
-
-   -- Netlist
-   U9 : NAND2MAC
-	port map( I0 => n1, I1 => n2, Y => q);
-
-   U10 : NAND2MAC
-	port map( I0 => prop_q(2), I1 => prop_q(3), Y => n2);
-
-   U11 : NAND2MAC
-	port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1);
-
-
-end FTSM;
-
-configuration CFG_oa2a22_x4_FTSM of oa2a22_x4 is
-   for FTSM
-   end for;
-end CFG_oa2a22_x4_FTSM;
-
-
------ CELL oa2ao222_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa2ao222_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.495 ns;
-      tpdi0_q_F                      :	Time := 0.581 ns;
-      tpdi1_q_R                      :	Time := 0.598 ns;
-      tpdi1_q_F                      :	Time := 0.539 ns;
-      tpdi2_q_R                      :	Time := 0.464 ns;
-      tpdi2_q_F                      :	Time := 0.604 ns;
-      tpdi3_q_R                      :	Time := 0.556 ns;
-      tpdi3_q_F                      :	Time := 0.578 ns;
-      tpdi4_q_R                      :	Time := 0.558 ns;
-      tpdi4_q_F                      :	Time := 0.453 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa2ao222_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of oa2ao222_x2 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U10/tLH";
-   attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U10/tHL";
-   attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U9/tLH";
-   attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U9/tHL";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 4) := (others => 'U');
-   signal n1, n2, n3 : STD_LOGIC;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component OR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi3_R, tHL => twdi3_F)
-	port map( Input => i3, Output => connect(3));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi4_R, tHL => twdi4_F)
-	port map( Input => i4, Output => connect(4));
-
-   -- Intrinsic delay buffers
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F)
-	port map( Input => connect(2), Output => prop_q(2));
-
-   U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F)
-	port map( Input => connect(3), Output => prop_q(3));
-
-   U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F)
-	port map( Input => connect(4), Output => prop_q(4));
-
-   -- Netlist
-   U11 : NAND2MAC
-	port map( I0 => n1, I1 => n2, Y => q);
-
-   U12 : OR2MAC
-	port map( I0 => prop_q(3), I1 => prop_q(2), Y => n3);
-
-   U13 : NAND2MAC
-	port map( I0 => prop_q(4), I1 => n3, Y => n2);
-
-   U14 : NAND2MAC
-	port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1);
-
-
-end FTSM;
-
-configuration CFG_oa2ao222_x2_FTSM of oa2ao222_x2 is
-   for FTSM
-   end for;
-end CFG_oa2ao222_x2_FTSM;
-
-
------ CELL oa2ao222_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa2ao222_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.553 ns;
-      tpdi0_q_F                      :	Time := 0.657 ns;
-      tpdi1_q_R                      :	Time := 0.662 ns;
-      tpdi1_q_F                      :	Time := 0.616 ns;
-      tpdi2_q_R                      :	Time := 0.552 ns;
-      tpdi2_q_F                      :	Time := 0.693 ns;
-      tpdi3_q_R                      :	Time := 0.640 ns;
-      tpdi3_q_F                      :	Time := 0.660 ns;
-      tpdi4_q_R                      :	Time := 0.656 ns;
-      tpdi4_q_F                      :	Time := 0.529 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa2ao222_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of oa2ao222_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U10/tLH";
-   attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U10/tHL";
-   attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U9/tLH";
-   attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U9/tHL";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 4) := (others => 'U');
-   signal n1, n2, n3 : STD_LOGIC;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component OR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi3_R, tHL => twdi3_F)
-	port map( Input => i3, Output => connect(3));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi4_R, tHL => twdi4_F)
-	port map( Input => i4, Output => connect(4));
-
-   -- Intrinsic delay buffers
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F)
-	port map( Input => connect(2), Output => prop_q(2));
-
-   U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F)
-	port map( Input => connect(3), Output => prop_q(3));
-
-   U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F)
-	port map( Input => connect(4), Output => prop_q(4));
-
-   -- Netlist
-   U11 : NAND2MAC
-	port map( I0 => n1, I1 => n2, Y => q);
-
-   U12 : OR2MAC
-	port map( I0 => prop_q(3), I1 => prop_q(2), Y => n3);
-
-   U13 : NAND2MAC
-	port map( I0 => prop_q(4), I1 => n3, Y => n2);
-
-   U14 : NAND2MAC
-	port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1);
-
-
-end FTSM;
-
-configuration CFG_oa2ao222_x4_FTSM of oa2ao222_x4 is
-   for FTSM
-   end for;
-end CFG_oa2ao222_x4_FTSM;
-
-
------ CELL oa3ao322_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa3ao322_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.638 ns;
-      tpdi0_q_F                      :	Time := 0.820 ns;
-      tpdi1_q_R                      :	Time := 0.735 ns;
-      tpdi1_q_F                      :	Time := 0.764 ns;
-      tpdi2_q_R                      :	Time := 0.806 ns;
-      tpdi2_q_F                      :	Time := 0.707 ns;
-      tpdi3_q_R                      :	Time := 0.560 ns;
-      tpdi3_q_F                      :	Time := 0.765 ns;
-      tpdi4_q_R                      :	Time := 0.649 ns;
-      tpdi4_q_F                      :	Time := 0.760 ns;
-      tpdi5_q_R                      :	Time := 0.734 ns;
-      tpdi5_q_F                      :	Time := 0.734 ns;
-      tpdi6_q_R                      :	Time := 0.563 ns;
-      tpdi6_q_F                      :	Time := 0.540 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns;
-      twdi6_R                        :	Time := 0.000 ns;
-      twdi6_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      i6                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa3ao322_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of oa3ao322_x2 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi6_q_R: constant is "U14/tLH";
-   attribute PROPAGATE_VALUE of tpdi6_q_F: constant is "U14/tHL";
-   attribute PROPAGATE_VALUE of tpdi5_q_R: constant is "U13/tLH";
-   attribute PROPAGATE_VALUE of tpdi5_q_F: constant is "U13/tHL";
-   attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U12/tLH";
-   attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U12/tHL";
-   attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U11/tLH";
-   attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U11/tHL";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U10/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U10/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U9/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U9/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 6) := (others => 'U');
-   signal n1, n2, n3 : STD_LOGIC;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component OR3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi3_R, tHL => twdi3_F)
-	port map( Input => i3, Output => connect(3));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi4_R, tHL => twdi4_F)
-	port map( Input => i4, Output => connect(4));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi5_R, tHL => twdi5_F)
-	port map( Input => i5, Output => connect(5));
-
-   U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi6_R, tHL => twdi6_F)
-	port map( Input => i6, Output => connect(6));
-
-   -- Intrinsic delay buffers
-   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F)
-	port map( Input => connect(2), Output => prop_q(2));
-
-   U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F)
-	port map( Input => connect(3), Output => prop_q(3));
-
-   U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F)
-	port map( Input => connect(4), Output => prop_q(4));
-
-   U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi5_q_R, tHL => tpdi5_q_F)
-	port map( Input => connect(5), Output => prop_q(5));
-
-   U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi6_q_R, tHL => tpdi6_q_F)
-	port map( Input => connect(6), Output => prop_q(6));
-
-   -- Netlist
-   U15 : NAND2MAC
-	port map( I0 => n1, I1 => n2, Y => q);
-
-   U16 : OR3MAC
-	port map( I0 => prop_q(3), I1 => prop_q(4), I2 => prop_q(5), Y => 
-         n3);
-
-   U17 : NAND3MAC
-	port map( I0 => prop_q(1), I1 => prop_q(2), I2 => prop_q(0), Y => 
-         n2);
-
-   U18 : NAND2MAC
-	port map( I0 => prop_q(6), I1 => n3, Y => n1);
-
-
-end FTSM;
-
-configuration CFG_oa3ao322_x2_FTSM of oa3ao322_x2 is
-   for FTSM
-   end for;
-end CFG_oa3ao322_x2_FTSM;
-
-
------ CELL oa3ao322_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa3ao322_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.717 ns;
-      tpdi0_q_F                      :	Time := 0.946 ns;
-      tpdi1_q_R                      :	Time := 0.818 ns;
-      tpdi1_q_F                      :	Time := 0.890 ns;
-      tpdi2_q_R                      :	Time := 0.894 ns;
-      tpdi2_q_F                      :	Time := 0.834 ns;
-      tpdi3_q_R                      :	Time := 0.673 ns;
-      tpdi3_q_F                      :	Time := 0.898 ns;
-      tpdi4_q_R                      :	Time := 0.758 ns;
-      tpdi4_q_F                      :	Time := 0.896 ns;
-      tpdi5_q_R                      :	Time := 0.839 ns;
-      tpdi5_q_F                      :	Time := 0.865 ns;
-      tpdi6_q_R                      :	Time := 0.684 ns;
-      tpdi6_q_F                      :	Time := 0.651 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns;
-      twdi6_R                        :	Time := 0.000 ns;
-      twdi6_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      i6                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa3ao322_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of oa3ao322_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi6_q_R: constant is "U14/tLH";
-   attribute PROPAGATE_VALUE of tpdi6_q_F: constant is "U14/tHL";
-   attribute PROPAGATE_VALUE of tpdi5_q_R: constant is "U13/tLH";
-   attribute PROPAGATE_VALUE of tpdi5_q_F: constant is "U13/tHL";
-   attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U12/tLH";
-   attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U12/tHL";
-   attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U11/tLH";
-   attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U11/tHL";
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U10/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U10/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U9/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U9/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U8/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U8/tHL";
-   attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL";
-   attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH";
-   attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 6) := (others => 'U');
-   signal n1, n2, n3 : STD_LOGIC;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component OR3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi3_R, tHL => twdi3_F)
-	port map( Input => i3, Output => connect(3));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi4_R, tHL => twdi4_F)
-	port map( Input => i4, Output => connect(4));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi5_R, tHL => twdi5_F)
-	port map( Input => i5, Output => connect(5));
-
-   U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi6_R, tHL => twdi6_F)
-	port map( Input => i6, Output => connect(6));
-
-   -- Intrinsic delay buffers
-   U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F)
-	port map( Input => connect(2), Output => prop_q(2));
-
-   U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F)
-	port map( Input => connect(3), Output => prop_q(3));
-
-   U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F)
-	port map( Input => connect(4), Output => prop_q(4));
-
-   U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi5_q_R, tHL => tpdi5_q_F)
-	port map( Input => connect(5), Output => prop_q(5));
-
-   U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi6_q_R, tHL => tpdi6_q_F)
-	port map( Input => connect(6), Output => prop_q(6));
-
-   -- Netlist
-   U15 : NAND2MAC
-	port map( I0 => n1, I1 => n2, Y => q);
-
-   U16 : OR3MAC
-	port map( I0 => prop_q(3), I1 => prop_q(4), I2 => prop_q(5), Y => 
-         n3);
-
-   U17 : NAND3MAC
-	port map( I0 => prop_q(1), I1 => prop_q(2), I2 => prop_q(0), Y => 
-         n2);
-
-   U18 : NAND2MAC
-	port map( I0 => prop_q(6), I1 => n3, Y => n1);
-
-
-end FTSM;
-
-configuration CFG_oa3ao322_x4_FTSM of oa3ao322_x4 is
-   for FTSM
-   end for;
-end CFG_oa3ao322_x4_FTSM;
-
-
------ CELL oa22_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa22_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.390 ns;
-      tpdi0_q_F                      :	Time := 0.555 ns;
-      tpdi1_q_R                      :	Time := 0.488 ns;
-      tpdi1_q_F                      :	Time := 0.525 ns;
-      tpdi2_q_R                      :	Time := 0.438 ns;
-      tpdi2_q_F                      :	Time := 0.454 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa22_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of oa22_x2 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-   signal n1 : STD_LOGIC;
-
-   component OR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   -- Intrinsic delay buffers
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F)
-	port map( Input => connect(2), Output => prop_q(2));
-
-   -- Netlist
-   U7 : OR2MAC
-	port map( I0 => n1, I1 => prop_q(2), Y => q);
-
-   U8 : AND2MAC
-	port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1);
-
-
-end FTSM;
-
-configuration CFG_oa22_x2_FTSM of oa22_x2 is
-   for FTSM
-   end for;
-end CFG_oa22_x2_FTSM;
-
-
------ CELL oa22_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa22_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.511 ns;
-      tpdi0_q_F                      :	Time := 0.677 ns;
-      tpdi1_q_R                      :	Time := 0.615 ns;
-      tpdi1_q_F                      :	Time := 0.650 ns;
-      tpdi2_q_R                      :	Time := 0.523 ns;
-      tpdi2_q_F                      :	Time := 0.571 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa22_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of oa22_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH";
-   attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U');
-   signal n1 : STD_LOGIC;
-
-   component OR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi2_R, tHL => twdi2_F)
-	port map( Input => i2, Output => connect(2));
-
-   -- Intrinsic delay buffers
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F)
-	port map( Input => connect(2), Output => prop_q(2));
-
-   -- Netlist
-   U7 : OR2MAC
-	port map( I0 => n1, I1 => prop_q(2), Y => q);
-
-   U8 : AND2MAC
-	port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1);
-
-
-end FTSM;
-
-configuration CFG_oa22_x4_FTSM of oa22_x4 is
-   for FTSM
-   end for;
-end CFG_oa22_x4_FTSM;
-
-
------ CELL on12_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity on12_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.111 ns;
-      tpdi0_q_F                      :	Time := 0.234 ns;
-      tpdi1_q_R                      :	Time := 0.314 ns;
-      tpdi1_q_F                      :	Time := 0.291 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end on12_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of on12_x1 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-   signal n1 : STD_LOGIC;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component INVMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   -- Intrinsic delay buffers
-   U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_F, tHL => tpdi0_q_R)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   -- Netlist
-   U5 : NAND2MAC
-	port map( I0 => prop_q(0), I1 => n1, Y => q);
-
-   U6 : INVMAC
-	port map( I0 => prop_q(1), Y => n1);
-
-
-end FTSM;
-
-configuration CFG_on12_x1_FTSM of on12_x1 is
-   for FTSM
-   end for;
-end CFG_on12_x1_FTSM;
-
-
------ CELL on12_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity on12_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.474 ns;
-      tpdi0_q_F                      :	Time := 0.499 ns;
-      tpdi1_q_R                      :	Time := 0.491 ns;
-      tpdi1_q_F                      :	Time := 0.394 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end on12_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of on12_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-   signal n1 : STD_LOGIC;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component INVMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   -- Intrinsic delay buffers
-   U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_F, tHL => tpdi0_q_R)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   -- Netlist
-   U5 : NAND2MAC
-	port map( I0 => prop_q(0), I1 => n1, Y => q);
-
-   U6 : INVMAC
-	port map( I0 => prop_q(1), Y => n1);
-
-
-end FTSM;
-
-configuration CFG_on12_x4_FTSM of on12_x4 is
-   for FTSM
-   end for;
-end CFG_on12_x4_FTSM;
-
-
------ CELL one_x0 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity one_x0 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False);
-
-   port(
-      q                              :	out   STD_LOGIC := '1');
-end one_x0;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of one_x0 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-
-
-begin
-
-   -- Netlist
-   q <= '1';
-
-end FTSM;
-
-configuration CFG_one_x0_FTSM of one_x0 is
-   for FTSM
-   end for;
-end CFG_one_x0_FTSM;
-
-
------ CELL sff1_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity sff1_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdck_q_R                      :	Time := 0.500 ns;
-      tpdck_q_F                      :	Time := 0.500 ns;
-      tsui_ck                        :	Time := 0.585 ns;
-      thck_i                         :	Time := 0.000 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns;
-      twdck_R                        :	Time := 0.000 ns;
-      twdck_F                        :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      ck                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end sff1_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of sff1_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of thck_i: constant is "FEC/F2/tHold";
-   attribute PROPAGATE_VALUE of tsui_ck: constant is "FEC/F1/tSetup";
-   attribute PROPAGATE_VALUE of tpdck_q_F: constant is "U3/U1/tHL";
-   attribute PROPAGATE_VALUE of tpdck_q_R: constant is "U3/U1/tLH";
-   attribute PROPAGATE_VALUE of twdck_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdck_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-   signal n1 : STD_LOGIC;
-
-   component DFFLMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         D                              :  in    STD_LOGIC;
-         CLK                            :  in    STD_LOGIC;
-         CLR                            :  in    STD_LOGIC;
-         Q                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi_R, tHL => twdi_F)
-	port map( Input => i, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdck_R, tHL => twdck_F)
-	port map( Input => ck, Output => connect(1));
-
-   -- Netlist
-   U3 : DFFLMAC
-	generic map( tpdY_R => tpdck_q_R, tpdY_F => tpdck_q_F )
-	port map( D => connect(0), CLK => connect(1), CLR => n1, Q => q);
-
-   n1 <= '1';
-
-   -- Forbidden Events
-   FEC : if Timing_mesg generate
-
-     F1 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK
-	  generic map( N => 1, tSetup => tsui_ck)
-	  port map( Data(1) => connect(0), Clock => connect(1));
-
-     F2 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK
-	  generic map( N => 1, tHold => thck_i)
-	  port map( Data(1) => connect(0), Clock => connect(1));
-
-   end generate FEC;
-
-end FTSM;
-
-configuration CFG_sff1_x4_FTSM of sff1_x4 is
-   for FTSM
-   end for;
-end CFG_sff1_x4_FTSM;
-
-
------ CELL sff2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity sff2_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdck_q_R                      :	Time := 0.500 ns;
-      tpdck_q_F                      :	Time := 0.500 ns;
-      tsui0_ck                       :	Time := 0.764 ns;
-      thck_i0                        :	Time := 0.000 ns;
-      tsui1_ck                       :	Time := 0.764 ns;
-      thck_i1                        :	Time := 0.000 ns;
-      tsucmd_ck                      :	Time := 0.833 ns;
-      thck_cmd                       :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns;
-      twdck_R                        :	Time := 0.000 ns;
-      twdck_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      cmd                            :	in    STD_LOGIC;
-      ck                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end sff2_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of sff2_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of thck_cmd: constant is "FEC/F6/tHold";
-   attribute PROPAGATE_VALUE of tsucmd_ck: constant is "FEC/F5/tSetup";
-   attribute PROPAGATE_VALUE of thck_i1: constant is "FEC/F4/tHold";
-   attribute PROPAGATE_VALUE of tsui1_ck: constant is "FEC/F3/tSetup";
-   attribute PROPAGATE_VALUE of thck_i0: constant is "FEC/F2/tHold";
-   attribute PROPAGATE_VALUE of tsui0_ck: constant is "FEC/F1/tSetup";
-   attribute PROPAGATE_VALUE of tpdck_q_F: constant is "U6/U1/tHL";
-   attribute PROPAGATE_VALUE of tpdck_q_R: constant is "U6/U1/tLH";
-   attribute PROPAGATE_VALUE of twdck_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of twdck_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of twdcmd_F: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdcmd_R: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U');
-   signal n1, n2 : STD_LOGIC;
-
-   component MUX2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         S0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component DFFLMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         D                              :  in    STD_LOGIC;
-         CLK                            :  in    STD_LOGIC;
-         CLR                            :  in    STD_LOGIC;
-         Q                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdcmd_R, tHL => twdcmd_F)
-	port map( Input => cmd, Output => connect(2));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdck_R, tHL => twdck_F)
-	port map( Input => ck, Output => connect(3));
-
-   -- Netlist
-   U5 : MUX2MAC
-	port map( I0 => connect(0), I1 => connect(1), S0 => connect(2), Y => 
-         n1);
-
-   U6 : DFFLMAC
-	generic map( tpdY_R => tpdck_q_R, tpdY_F => tpdck_q_F )
-	port map( D => n1, CLK => connect(3), CLR => n2, Q => q);
-
-   n2 <= '1';
-
-   -- Forbidden Events
-   FEC : if Timing_mesg generate
-
-     F1 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK
-	  generic map( N => 1, tSetup => tsui0_ck)
-	  port map( Data(1) => connect(0), Clock => connect(3));
-
-     F2 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK
-	  generic map( N => 1, tHold => thck_i0)
-	  port map( Data(1) => connect(0), Clock => connect(3));
-
-     F3 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK
-	  generic map( N => 1, tSetup => tsui1_ck)
-	  port map( Data(1) => connect(1), Clock => connect(3));
-
-     F4 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK
-	  generic map( N => 1, tHold => thck_i1)
-	  port map( Data(1) => connect(1), Clock => connect(3));
-
-     F5 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK
-	  generic map( N => 1, tSetup => tsucmd_ck)
-	  port map( Data(1) => connect(2), Clock => connect(3));
-
-     F6 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK
-	  generic map( N => 1, tHold => thck_cmd)
-	  port map( Data(1) => connect(2), Clock => connect(3));
-
-   end generate FEC;
-
-end FTSM;
-
-configuration CFG_sff2_x4_FTSM of sff2_x4 is
-   for FTSM
-   end for;
-end CFG_sff2_x4_FTSM;
-
-
------ CELL ts_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity ts_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd_q_R                     :	Time := 0.492 ns;
-      tpdcmd_q_F                     :	Time := 0.409 ns;
-      tpdcmd_q_LZ                    :	Time := 0.492 ns;
-      tpdcmd_q_HZ                    :	Time := 0.409 ns;
-      tpdi_q_R                       :	Time := 0.475 ns;
-      tpdi_q_F                       :	Time := 0.444 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      cmd                            :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end ts_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of ts_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi_q_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi_q_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is "U3/tHL, U3/tLH";
-   attribute PROPAGATE_VALUE of tpdcmd_q_HZ: constant is "U3/tLH, U3/tHL";
-   attribute PROPAGATE_VALUE of tpdcmd_q_LZ: constant is "U3/tLH, U3/tHL";
-   attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is "U3/tLH, U3/tHL";
-   attribute PROPAGATE_VALUE of twdcmd_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdcmd_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-
-   component BUF3SHEMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         OE                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi_R, tHL => twdi_F)
-	port map( Input => i, Output => connect(1));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdcmd_R, tHL => twdcmd_F)
-	port map( Input => cmd, Output => connect(0));
-
-   -- Intrinsic delay buffers
-   U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdcmd_q_R, tHL => tpdcmd_q_R)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi_q_R, tHL => tpdi_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   -- Netlist
-   U5 : BUF3SHEMAC
-	port map( I0 => prop_q(1), OE => prop_q(0), Y => q);
-
-
-end FTSM;
-
-configuration CFG_ts_x4_FTSM of ts_x4 is
-   for FTSM
-   end for;
-end CFG_ts_x4_FTSM;
-
-
------ CELL ts_x8 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity ts_x8 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd_q_R                     :	Time := 0.626 ns;
-      tpdcmd_q_F                     :	Time := 0.466 ns;
-      tpdcmd_q_LZ                    :	Time := 0.626 ns;
-      tpdcmd_q_HZ                    :	Time := 0.466 ns;
-      tpdi_q_R                       :	Time := 0.613 ns;
-      tpdi_q_F                       :	Time := 0.569 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      cmd                            :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end ts_x8;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of ts_x8 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi_q_R: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi_q_F: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is "U3/tHL, U3/tLH";
-   attribute PROPAGATE_VALUE of tpdcmd_q_HZ: constant is "U3/tLH, U3/tHL";
-   attribute PROPAGATE_VALUE of tpdcmd_q_LZ: constant is "U3/tLH, U3/tHL";
-   attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is "U3/tLH, U3/tHL";
-   attribute PROPAGATE_VALUE of twdcmd_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdcmd_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-
-   component BUF3SHEMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         OE                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi_R, tHL => twdi_F)
-	port map( Input => i, Output => connect(1));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdcmd_R, tHL => twdcmd_F)
-	port map( Input => cmd, Output => connect(0));
-
-   -- Intrinsic delay buffers
-   U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdcmd_q_R, tHL => tpdcmd_q_R)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi_q_R, tHL => tpdi_q_F)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   -- Netlist
-   U5 : BUF3SHEMAC
-	port map( I0 => prop_q(1), OE => prop_q(0), Y => q);
-
-
-end FTSM;
-
-configuration CFG_ts_x8_FTSM of ts_x8 is
-   for FTSM
-   end for;
-end CFG_ts_x8_FTSM;
-
-
------ CELL xr2_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity xr2_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.292 ns;
-      tpdi0_q_F                      :	Time := 0.293 ns;
-      tpdi1_q_R                      :	Time := 0.377 ns;
-      tpdi1_q_F                      :	Time := 0.261 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end xr2_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of xr2_x1 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-
-   component XOR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   -- Intrinsic delay buffers
-   U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_F, tHL => tpdi0_q_R)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_F, tHL => tpdi1_q_R)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   -- Netlist
-   U5 : XOR2MAC
-	port map( I0 => prop_q(1), I1 => prop_q(0), Y => q);
-
-
-end FTSM;
-
-configuration CFG_xr2_x1_FTSM of xr2_x1 is
-   for FTSM
-   end for;
-end CFG_xr2_x1_FTSM;
-
-
------ CELL xr2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity xr2_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.521 ns;
-      tpdi0_q_F                      :	Time := 0.560 ns;
-      tpdi1_q_R                      :	Time := 0.541 ns;
-      tpdi1_q_F                      :	Time := 0.657 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end xr2_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of xr2_x4 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-   attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tLH";
-   attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tHL";
-   attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tLH";
-   attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tHL";
-   attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL";
-   attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH";
-   attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL";
-   attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH";
-
-   signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-   signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U');
-
-   component XOR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Extrinsic delay buffers
-   U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi0_R, tHL => twdi0_F)
-	port map( Input => i0, Output => connect(0));
-
-   U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE
-	generic map( tLH => twdi1_R, tHL => twdi1_F)
-	port map( Input => i1, Output => connect(1));
-
-   -- Intrinsic delay buffers
-   U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi0_q_F, tHL => tpdi0_q_R)
-	port map( Input => connect(0), Output => prop_q(0));
-
-   U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => tpdi1_q_F, tHL => tpdi1_q_R)
-	port map( Input => connect(1), Output => prop_q(1));
-
-   -- Netlist
-   U5 : XOR2MAC
-	port map( I0 => prop_q(1), I1 => prop_q(0), Y => q);
-
-
-end FTSM;
-
-configuration CFG_xr2_x4_FTSM of xr2_x4 is
-   for FTSM
-   end for;
-end CFG_xr2_x4_FTSM;
-
-
------ CELL zero_x0 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity zero_x0 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False);
-
-   port(
-      nq                             :	out   STD_LOGIC := '0');
-end zero_x0;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-use SYNOPSYS.attributes.PROPAGATE_VALUE;
-
-architecture FTSM of zero_x0 is
-   attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of FTSM : architecture is TRUE;
-   attribute ASIC_CELL of FTSM : architecture is TRUE;
-
-   -- Backannotation attributes
-
-
-begin
-
-   -- Netlist
-   nq <= '0';
-
-end FTSM;
-
-configuration CFG_zero_x0_FTSM of zero_x0 is
-   for FTSM
-   end for;
-end CFG_zero_x0_FTSM;
-
-
----- end of library ----
diff --git a/alliance/share/cells/sxlib/sxlib_UDSM.vhd b/alliance/share/cells/sxlib/sxlib_UDSM.vhd
deleted file mode 100644
index e54da28c..00000000
--- a/alliance/share/cells/sxlib/sxlib_UDSM.vhd
+++ /dev/null
@@ -1,7175 +0,0 @@
-
-----------------------------------------------------------------
--- 
--- Created by the Synopsys Library Compiler 1999.10
--- FILENAME     :    sxlib_UDSM.vhd
--- FILE CONTENTS:    Entity, Structural Architecture(UDSM),
---                   and Configuration
--- DATE CREATED :    Mon May  7 10:19:50 2001
--- 
--- LIBRARY      :    sxlib
--- DATE ENTERED :    Thu Dec 21 11:24:55 MET 2000
--- REVISION     :    1.200000
--- TECHNOLOGY   :    cmos
--- TIME SCALE   :    1 ns
--- LOGIC SYSTEM :    IEEE-1164
--- NOTES        :    UDSM
--- HISTORY      :
--- 
-----------------------------------------------------------------
-
------ CELL a2_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity a2_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.261 ns;
-      tpdi0_q_F                      :	Time := 0.388 ns;
-      tpdi1_q_R                      :	Time := 0.203 ns;
-      tpdi1_q_F                      :	Time := 0.434 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end a2_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of a2_x2 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : AND2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i0, I1 => i1, Y => q);
-
-
-end UDSM;
-
-configuration CFG_a2_x2_UDSM of a2_x2 is
-   for UDSM
-   end for;
-end CFG_a2_x2_UDSM;
-
-
------ CELL a2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity a2_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.338 ns;
-      tpdi0_q_F                      :	Time := 0.476 ns;
-      tpdi1_q_R                      :	Time := 0.269 ns;
-      tpdi1_q_F                      :	Time := 0.518 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end a2_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of a2_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : AND2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i0, I1 => i1, Y => q);
-
-
-end UDSM;
-
-configuration CFG_a2_x4_UDSM of a2_x4 is
-   for UDSM
-   end for;
-end CFG_a2_x4_UDSM;
-
-
------ CELL a3_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity a3_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.395 ns;
-      tpdi0_q_F                      :	Time := 0.435 ns;
-      tpdi1_q_R                      :	Time := 0.353 ns;
-      tpdi1_q_F                      :	Time := 0.479 ns;
-      tpdi2_q_R                      :	Time := 0.290 ns;
-      tpdi2_q_F                      :	Time := 0.521 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end a3_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of a3_x2 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component AND3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : AND3MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i1, I1 => i2, I2 => i0, Y => q);
-
-
-end UDSM;
-
-configuration CFG_a3_x2_UDSM of a3_x2 is
-   for UDSM
-   end for;
-end CFG_a3_x2_UDSM;
-
-
------ CELL a3_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity a3_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.478 ns;
-      tpdi0_q_F                      :	Time := 0.514 ns;
-      tpdi1_q_R                      :	Time := 0.428 ns;
-      tpdi1_q_F                      :	Time := 0.554 ns;
-      tpdi2_q_R                      :	Time := 0.356 ns;
-      tpdi2_q_F                      :	Time := 0.592 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end a3_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of a3_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component AND3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : AND3MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i1, I1 => i2, I2 => i0, Y => q);
-
-
-end UDSM;
-
-configuration CFG_a3_x4_UDSM of a3_x4 is
-   for UDSM
-   end for;
-end CFG_a3_x4_UDSM;
-
-
------ CELL a4_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity a4_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.374 ns;
-      tpdi0_q_F                      :	Time := 0.578 ns;
-      tpdi1_q_R                      :	Time := 0.441 ns;
-      tpdi1_q_F                      :	Time := 0.539 ns;
-      tpdi2_q_R                      :	Time := 0.482 ns;
-      tpdi2_q_F                      :	Time := 0.498 ns;
-      tpdi3_q_R                      :	Time := 0.506 ns;
-      tpdi3_q_F                      :	Time := 0.455 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end a4_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of a4_x2 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component AND4MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         I3                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : AND4MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i0, I1 => i1, I2 => i2, I3 => i3, Y => q);
-
-
-end UDSM;
-
-configuration CFG_a4_x2_UDSM of a4_x2 is
-   for UDSM
-   end for;
-end CFG_a4_x2_UDSM;
-
-
------ CELL a4_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity a4_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.505 ns;
-      tpdi0_q_F                      :	Time := 0.650 ns;
-      tpdi1_q_R                      :	Time := 0.578 ns;
-      tpdi1_q_F                      :	Time := 0.614 ns;
-      tpdi2_q_R                      :	Time := 0.627 ns;
-      tpdi2_q_F                      :	Time := 0.576 ns;
-      tpdi3_q_R                      :	Time := 0.661 ns;
-      tpdi3_q_F                      :	Time := 0.538 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end a4_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of a4_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component AND4MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         I3                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : AND4MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i0, I1 => i1, I2 => i2, I3 => i3, Y => q);
-
-
-end UDSM;
-
-configuration CFG_a4_x4_UDSM of a4_x4 is
-   for UDSM
-   end for;
-end CFG_a4_x4_UDSM;
-
-
------ CELL an12_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity an12_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.200 ns;
-      tpdi0_q_F                      :	Time := 0.168 ns;
-      tpdi1_q_R                      :	Time := 0.285 ns;
-      tpdi1_q_F                      :	Time := 0.405 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end an12_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of an12_x1 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1 : STD_LOGIC;
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component INVMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : AND2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i1, I1 => n1, Y => q);
-
-   U2 : INVMAC
-	port map( I0 => i0, Y => n1);
-
-
-end UDSM;
-
-configuration CFG_an12_x1_UDSM of an12_x1 is
-   for UDSM
-   end for;
-end CFG_an12_x1_UDSM;
-
-
------ CELL an12_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity an12_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.461 ns;
-      tpdi0_q_F                      :	Time := 0.471 ns;
-      tpdi1_q_R                      :	Time := 0.269 ns;
-      tpdi1_q_F                      :	Time := 0.518 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end an12_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of an12_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1 : STD_LOGIC;
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component INVMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : AND2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i1, I1 => n1, Y => q);
-
-   U2 : INVMAC
-	port map( I0 => i0, Y => n1);
-
-
-end UDSM;
-
-configuration CFG_an12_x4_UDSM of an12_x4 is
-   for UDSM
-   end for;
-end CFG_an12_x4_UDSM;
-
-
------ CELL ao2o22_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity ao2o22_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.572 ns;
-      tpdi0_q_F                      :	Time := 0.451 ns;
-      tpdi1_q_R                      :	Time := 0.508 ns;
-      tpdi1_q_F                      :	Time := 0.542 ns;
-      tpdi2_q_R                      :	Time := 0.432 ns;
-      tpdi2_q_F                      :	Time := 0.627 ns;
-      tpdi3_q_R                      :	Time := 0.488 ns;
-      tpdi3_q_F                      :	Time := 0.526 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end ao2o22_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of ao2o22_x2 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1, n2 : STD_LOGIC;
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component OR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : AND2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => n1, I1 => n2, Y => q);
-
-   U2 : OR2MAC
-	port map( I0 => i3, I1 => i2, Y => n2);
-
-   U3 : OR2MAC
-	port map( I0 => i1, I1 => i0, Y => n1);
-
-
-end UDSM;
-
-configuration CFG_ao2o22_x2_UDSM of ao2o22_x2 is
-   for UDSM
-   end for;
-end CFG_ao2o22_x2_UDSM;
-
-
------ CELL ao2o22_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity ao2o22_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.696 ns;
-      tpdi0_q_F                      :	Time := 0.569 ns;
-      tpdi1_q_R                      :	Time := 0.637 ns;
-      tpdi1_q_F                      :	Time := 0.666 ns;
-      tpdi2_q_R                      :	Time := 0.554 ns;
-      tpdi2_q_F                      :	Time := 0.744 ns;
-      tpdi3_q_R                      :	Time := 0.606 ns;
-      tpdi3_q_F                      :	Time := 0.639 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end ao2o22_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of ao2o22_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1, n2 : STD_LOGIC;
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component OR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : AND2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => n1, I1 => n2, Y => q);
-
-   U2 : OR2MAC
-	port map( I0 => i3, I1 => i2, Y => n2);
-
-   U3 : OR2MAC
-	port map( I0 => i1, I1 => i0, Y => n1);
-
-
-end UDSM;
-
-configuration CFG_ao2o22_x4_UDSM of ao2o22_x4 is
-   for UDSM
-   end for;
-end CFG_ao2o22_x4_UDSM;
-
-
------ CELL ao22_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity ao22_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.558 ns;
-      tpdi0_q_F                      :	Time := 0.447 ns;
-      tpdi1_q_R                      :	Time := 0.493 ns;
-      tpdi1_q_F                      :	Time := 0.526 ns;
-      tpdi2_q_R                      :	Time := 0.420 ns;
-      tpdi2_q_F                      :	Time := 0.425 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end ao22_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of ao22_x2 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1 : STD_LOGIC;
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component OR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : AND2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i2, I1 => n1, Y => q);
-
-   U2 : OR2MAC
-	port map( I0 => i1, I1 => i0, Y => n1);
-
-
-end UDSM;
-
-configuration CFG_ao22_x2_UDSM of ao22_x2 is
-   for UDSM
-   end for;
-end CFG_ao22_x2_UDSM;
-
-
------ CELL ao22_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity ao22_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.674 ns;
-      tpdi0_q_F                      :	Time := 0.552 ns;
-      tpdi1_q_R                      :	Time := 0.615 ns;
-      tpdi1_q_F                      :	Time := 0.647 ns;
-      tpdi2_q_R                      :	Time := 0.526 ns;
-      tpdi2_q_F                      :	Time := 0.505 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end ao22_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of ao22_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1 : STD_LOGIC;
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component OR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : AND2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i2, I1 => n1, Y => q);
-
-   U2 : OR2MAC
-	port map( I0 => i1, I1 => i0, Y => n1);
-
-
-end UDSM;
-
-configuration CFG_ao22_x4_UDSM of ao22_x4 is
-   for UDSM
-   end for;
-end CFG_ao22_x4_UDSM;
-
-
------ CELL buf_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity buf_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi_q_R                       :	Time := 0.409 ns;
-      tpdi_q_F                       :	Time := 0.391 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end buf_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of buf_x2 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-begin
-
-   -- Concurrent assignments
-   U1 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => 1 ns, tHL => 1 ns)
-	port map( Input => i, Output => q);
-
-
-end UDSM;
-
-configuration CFG_buf_x2_UDSM of buf_x2 is
-   for UDSM
-   end for;
-end CFG_buf_x2_UDSM;
-
-
------ CELL buf_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity buf_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi_q_R                       :	Time := 0.379 ns;
-      tpdi_q_F                       :	Time := 0.409 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end buf_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of buf_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-begin
-
-   -- Concurrent assignments
-   U1 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => 1 ns, tHL => 1 ns)
-	port map( Input => i, Output => q);
-
-
-end UDSM;
-
-configuration CFG_buf_x4_UDSM of buf_x4 is
-   for UDSM
-   end for;
-end CFG_buf_x4_UDSM;
-
-
------ CELL buf_x8 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity buf_x8 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi_q_R                       :	Time := 0.343 ns;
-      tpdi_q_F                       :	Time := 0.396 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end buf_x8;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of buf_x8 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-begin
-
-   -- Concurrent assignments
-   U1 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE
-	generic map( tLH => 1 ns, tHL => 1 ns)
-	port map( Input => i, Output => q);
-
-
-end UDSM;
-
-configuration CFG_buf_x8_UDSM of buf_x8 is
-   for UDSM
-   end for;
-end CFG_buf_x8_UDSM;
-
-
------ CELL inv_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity inv_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi_nq_R                      :	Time := 0.101 ns;
-      tpdi_nq_F                      :	Time := 0.139 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end inv_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of inv_x1 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component INVMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : INVMAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i, Y => nq);
-
-
-end UDSM;
-
-configuration CFG_inv_x1_UDSM of inv_x1 is
-   for UDSM
-   end for;
-end CFG_inv_x1_UDSM;
-
-
------ CELL inv_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity inv_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi_nq_R                      :	Time := 0.069 ns;
-      tpdi_nq_F                      :	Time := 0.163 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end inv_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of inv_x2 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component INVMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : INVMAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i, Y => nq);
-
-
-end UDSM;
-
-configuration CFG_inv_x2_UDSM of inv_x2 is
-   for UDSM
-   end for;
-end CFG_inv_x2_UDSM;
-
-
------ CELL inv_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity inv_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi_nq_R                      :	Time := 0.071 ns;
-      tpdi_nq_F                      :	Time := 0.143 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end inv_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of inv_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component INVMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : INVMAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i, Y => nq);
-
-
-end UDSM;
-
-configuration CFG_inv_x4_UDSM of inv_x4 is
-   for UDSM
-   end for;
-end CFG_inv_x4_UDSM;
-
-
------ CELL inv_x8 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity inv_x8 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi_nq_R                      :	Time := 0.086 ns;
-      tpdi_nq_F                      :	Time := 0.133 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end inv_x8;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of inv_x8 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component INVMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : INVMAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i, Y => nq);
-
-
-end UDSM;
-
-configuration CFG_inv_x8_UDSM of inv_x8 is
-   for UDSM
-   end for;
-end CFG_inv_x8_UDSM;
-
-
------ CELL mx2_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity mx2_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd_q_R                     :	Time := 0.484 ns;
-      tpdcmd_q_F                     :	Time := 0.522 ns;
-      tpdi0_q_R                      :	Time := 0.451 ns;
-      tpdi0_q_F                      :	Time := 0.469 ns;
-      tpdi1_q_R                      :	Time := 0.451 ns;
-      tpdi1_q_F                      :	Time := 0.469 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      cmd                            :	in    STD_LOGIC;
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end mx2_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of mx2_x2 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component MUX2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         S0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : MUX2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i0, I1 => i1, S0 => cmd, Y => q);
-
-
-end UDSM;
-
-configuration CFG_mx2_x2_UDSM of mx2_x2 is
-   for UDSM
-   end for;
-end CFG_mx2_x2_UDSM;
-
-
------ CELL mx2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity mx2_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd_q_R                     :	Time := 0.615 ns;
-      tpdcmd_q_F                     :	Time := 0.647 ns;
-      tpdi0_q_R                      :	Time := 0.564 ns;
-      tpdi0_q_F                      :	Time := 0.576 ns;
-      tpdi1_q_R                      :	Time := 0.564 ns;
-      tpdi1_q_F                      :	Time := 0.576 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      cmd                            :	in    STD_LOGIC;
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end mx2_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of mx2_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component MUX2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         S0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : MUX2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i0, I1 => i1, S0 => cmd, Y => q);
-
-
-end UDSM;
-
-configuration CFG_mx2_x4_UDSM of mx2_x4 is
-   for UDSM
-   end for;
-end CFG_mx2_x4_UDSM;
-
-
------ CELL mx3_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity mx3_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd0_q_R                    :	Time := 0.573 ns;
-      tpdcmd0_q_F                    :	Time := 0.680 ns;
-      tpdcmd1_q_R                    :	Time := 0.664 ns;
-      tpdcmd1_q_F                    :	Time := 0.817 ns;
-      tpdi0_q_R                      :	Time := 0.538 ns;
-      tpdi0_q_F                      :	Time := 0.658 ns;
-      tpdi1_q_R                      :	Time := 0.654 ns;
-      tpdi1_q_F                      :	Time := 0.808 ns;
-      tpdi2_q_R                      :	Time := 0.654 ns;
-      tpdi2_q_F                      :	Time := 0.808 ns;
-      twdcmd0_R                      :	Time := 0.000 ns;
-      twdcmd0_F                      :	Time := 0.000 ns;
-      twdcmd1_R                      :	Time := 0.000 ns;
-      twdcmd1_F                      :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      cmd0                           :	in    STD_LOGIC;
-      cmd1                           :	in    STD_LOGIC;
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end mx3_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of mx3_x2 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1 : STD_LOGIC;
-
-   component MUX2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         S0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : MUX2MAC
-	port map( I0 => i2, I1 => i1, S0 => cmd1, Y => n1);
-
-   U2 : MUX2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i0, I1 => n1, S0 => cmd0, Y => q);
-
-
-end UDSM;
-
-configuration CFG_mx3_x2_UDSM of mx3_x2 is
-   for UDSM
-   end for;
-end CFG_mx3_x2_UDSM;
-
-
------ CELL mx3_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity mx3_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd0_q_R                    :	Time := 0.683 ns;
-      tpdcmd0_q_F                    :	Time := 0.779 ns;
-      tpdcmd1_q_R                    :	Time := 0.792 ns;
-      tpdcmd1_q_F                    :	Time := 0.967 ns;
-      tpdi0_q_R                      :	Time := 0.640 ns;
-      tpdi0_q_F                      :	Time := 0.774 ns;
-      tpdi1_q_R                      :	Time := 0.770 ns;
-      tpdi1_q_F                      :	Time := 0.948 ns;
-      tpdi2_q_R                      :	Time := 0.770 ns;
-      tpdi2_q_F                      :	Time := 0.948 ns;
-      twdcmd0_R                      :	Time := 0.000 ns;
-      twdcmd0_F                      :	Time := 0.000 ns;
-      twdcmd1_R                      :	Time := 0.000 ns;
-      twdcmd1_F                      :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      cmd0                           :	in    STD_LOGIC;
-      cmd1                           :	in    STD_LOGIC;
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end mx3_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of mx3_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1 : STD_LOGIC;
-
-   component MUX2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         S0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : MUX2MAC
-	port map( I0 => i2, I1 => i1, S0 => cmd1, Y => n1);
-
-   U2 : MUX2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i0, I1 => n1, S0 => cmd0, Y => q);
-
-
-end UDSM;
-
-configuration CFG_mx3_x4_UDSM of mx3_x4 is
-   for UDSM
-   end for;
-end CFG_mx3_x4_UDSM;
-
-
------ CELL na2_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity na2_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.059 ns;
-      tpdi0_nq_F                     :	Time := 0.288 ns;
-      tpdi1_nq_R                     :	Time := 0.111 ns;
-      tpdi1_nq_F                     :	Time := 0.234 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end na2_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of na2_x1 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : NAND2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i0, I1 => i1, Y => nq);
-
-
-end UDSM;
-
-configuration CFG_na2_x1_UDSM of na2_x1 is
-   for UDSM
-   end for;
-end CFG_na2_x1_UDSM;
-
-
------ CELL na2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity na2_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.412 ns;
-      tpdi0_nq_F                     :	Time := 0.552 ns;
-      tpdi1_nq_R                     :	Time := 0.353 ns;
-      tpdi1_nq_F                     :	Time := 0.601 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end na2_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of na2_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : NAND2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i0, I1 => i1, Y => nq);
-
-
-end UDSM;
-
-configuration CFG_na2_x4_UDSM of na2_x4 is
-   for UDSM
-   end for;
-end CFG_na2_x4_UDSM;
-
-
------ CELL na3_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity na3_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.119 ns;
-      tpdi0_nq_F                     :	Time := 0.363 ns;
-      tpdi1_nq_R                     :	Time := 0.171 ns;
-      tpdi1_nq_F                     :	Time := 0.316 ns;
-      tpdi2_nq_R                     :	Time := 0.193 ns;
-      tpdi2_nq_F                     :	Time := 0.265 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end na3_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of na3_x1 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component NAND3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : NAND3MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i1, I1 => i2, I2 => i0, Y => nq);
-
-
-end UDSM;
-
-configuration CFG_na3_x1_UDSM of na3_x1 is
-   for UDSM
-   end for;
-end CFG_na3_x1_UDSM;
-
-
------ CELL na3_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity na3_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.556 ns;
-      tpdi0_nq_F                     :	Time := 0.601 ns;
-      tpdi1_nq_R                     :	Time := 0.460 ns;
-      tpdi1_nq_F                     :	Time := 0.691 ns;
-      tpdi2_nq_R                     :	Time := 0.519 ns;
-      tpdi2_nq_F                     :	Time := 0.647 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end na3_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of na3_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component NAND3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : NAND3MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i1, I1 => i2, I2 => i0, Y => nq);
-
-
-end UDSM;
-
-configuration CFG_na3_x4_UDSM of na3_x4 is
-   for UDSM
-   end for;
-end CFG_na3_x4_UDSM;
-
-
------ CELL na4_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity na4_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.179 ns;
-      tpdi0_nq_F                     :	Time := 0.438 ns;
-      tpdi1_nq_R                     :	Time := 0.237 ns;
-      tpdi1_nq_F                     :	Time := 0.395 ns;
-      tpdi2_nq_R                     :	Time := 0.269 ns;
-      tpdi2_nq_F                     :	Time := 0.350 ns;
-      tpdi3_nq_R                     :	Time := 0.282 ns;
-      tpdi3_nq_F                     :	Time := 0.302 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end na4_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of na4_x1 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component NAND4MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         I3                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : NAND4MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i0, I1 => i1, I2 => i2, I3 => i3, Y => nq);
-
-
-end UDSM;
-
-configuration CFG_na4_x1_UDSM of na4_x1 is
-   for UDSM
-   end for;
-end CFG_na4_x1_UDSM;
-
-
------ CELL na4_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity na4_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.578 ns;
-      tpdi0_nq_F                     :	Time := 0.771 ns;
-      tpdi1_nq_R                     :	Time := 0.643 ns;
-      tpdi1_nq_F                     :	Time := 0.731 ns;
-      tpdi2_nq_R                     :	Time := 0.681 ns;
-      tpdi2_nq_F                     :	Time := 0.689 ns;
-      tpdi3_nq_R                     :	Time := 0.703 ns;
-      tpdi3_nq_F                     :	Time := 0.644 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end na4_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of na4_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component NAND4MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         I3                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : NAND4MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i0, I1 => i1, I2 => i2, I3 => i3, Y => nq);
-
-
-end UDSM;
-
-configuration CFG_na4_x4_UDSM of na4_x4 is
-   for UDSM
-   end for;
-end CFG_na4_x4_UDSM;
-
-
------ CELL nao2o22_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nao2o22_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.294 ns;
-      tpdi0_nq_F                     :	Time := 0.226 ns;
-      tpdi1_nq_R                     :	Time := 0.218 ns;
-      tpdi1_nq_F                     :	Time := 0.287 ns;
-      tpdi2_nq_R                     :	Time := 0.237 ns;
-      tpdi2_nq_F                     :	Time := 0.307 ns;
-      tpdi3_nq_R                     :	Time := 0.174 ns;
-      tpdi3_nq_F                     :	Time := 0.382 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nao2o22_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of nao2o22_x1 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1, n2 : STD_LOGIC;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component OR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : NAND2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => n1, I1 => n2, Y => nq);
-
-   U2 : OR2MAC
-	port map( I0 => i2, I1 => i3, Y => n2);
-
-   U3 : OR2MAC
-	port map( I0 => i0, I1 => i1, Y => n1);
-
-
-end UDSM;
-
-configuration CFG_nao2o22_x1_UDSM of nao2o22_x1 is
-   for UDSM
-   end for;
-end CFG_nao2o22_x1_UDSM;
-
-
------ CELL nao2o22_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nao2o22_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.734 ns;
-      tpdi0_nq_F                     :	Time := 0.644 ns;
-      tpdi1_nq_R                     :	Time := 0.666 ns;
-      tpdi1_nq_F                     :	Time := 0.717 ns;
-      tpdi2_nq_R                     :	Time := 0.664 ns;
-      tpdi2_nq_F                     :	Time := 0.721 ns;
-      tpdi3_nq_R                     :	Time := 0.607 ns;
-      tpdi3_nq_F                     :	Time := 0.807 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nao2o22_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of nao2o22_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1, n2 : STD_LOGIC;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component OR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : NAND2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => n1, I1 => n2, Y => nq);
-
-   U2 : OR2MAC
-	port map( I0 => i2, I1 => i3, Y => n2);
-
-   U3 : OR2MAC
-	port map( I0 => i0, I1 => i1, Y => n1);
-
-
-end UDSM;
-
-configuration CFG_nao2o22_x4_UDSM of nao2o22_x4 is
-   for UDSM
-   end for;
-end CFG_nao2o22_x4_UDSM;
-
-
------ CELL nao22_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nao22_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.294 ns;
-      tpdi0_nq_F                     :	Time := 0.226 ns;
-      tpdi1_nq_R                     :	Time := 0.218 ns;
-      tpdi1_nq_F                     :	Time := 0.287 ns;
-      tpdi2_nq_R                     :	Time := 0.165 ns;
-      tpdi2_nq_F                     :	Time := 0.238 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nao22_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of nao22_x1 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1 : STD_LOGIC;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component OR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : NAND2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i2, I1 => n1, Y => nq);
-
-   U2 : OR2MAC
-	port map( I0 => i0, I1 => i1, Y => n1);
-
-
-end UDSM;
-
-configuration CFG_nao22_x1_UDSM of nao22_x1 is
-   for UDSM
-   end for;
-end CFG_nao22_x1_UDSM;
-
-
------ CELL nao22_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nao22_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.732 ns;
-      tpdi0_nq_F                     :	Time := 0.650 ns;
-      tpdi1_nq_R                     :	Time := 0.664 ns;
-      tpdi1_nq_F                     :	Time := 0.723 ns;
-      tpdi2_nq_R                     :	Time := 0.596 ns;
-      tpdi2_nq_F                     :	Time := 0.636 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nao22_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of nao22_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1 : STD_LOGIC;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component OR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : NAND2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i2, I1 => n1, Y => nq);
-
-   U2 : OR2MAC
-	port map( I0 => i0, I1 => i1, Y => n1);
-
-
-end UDSM;
-
-configuration CFG_nao22_x4_UDSM of nao22_x4 is
-   for UDSM
-   end for;
-end CFG_nao22_x4_UDSM;
-
-
------ CELL nmx2_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nmx2_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd_nq_R                    :	Time := 0.218 ns;
-      tpdcmd_nq_F                    :	Time := 0.287 ns;
-      tpdi0_nq_R                     :	Time := 0.217 ns;
-      tpdi0_nq_F                     :	Time := 0.256 ns;
-      tpdi1_nq_R                     :	Time := 0.217 ns;
-      tpdi1_nq_F                     :	Time := 0.256 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      cmd                            :	in    STD_LOGIC;
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nmx2_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of nmx2_x1 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1 : STD_LOGIC;
-
-   component MUX2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         S0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component INVMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : MUX2MAC
-	port map( I0 => i0, I1 => i1, S0 => cmd, Y => n1);
-
-   U2 : INVMAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => n1, Y => nq);
-
-
-end UDSM;
-
-configuration CFG_nmx2_x1_UDSM of nmx2_x1 is
-   for UDSM
-   end for;
-end CFG_nmx2_x1_UDSM;
-
-
------ CELL nmx2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nmx2_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd_nq_R                    :	Time := 0.632 ns;
-      tpdcmd_nq_F                    :	Time := 0.708 ns;
-      tpdi0_nq_R                     :	Time := 0.610 ns;
-      tpdi0_nq_F                     :	Time := 0.653 ns;
-      tpdi1_nq_R                     :	Time := 0.610 ns;
-      tpdi1_nq_F                     :	Time := 0.653 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      cmd                            :	in    STD_LOGIC;
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nmx2_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of nmx2_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1 : STD_LOGIC;
-
-   component MUX2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         S0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component INVMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : MUX2MAC
-	port map( I0 => i0, I1 => i1, S0 => cmd, Y => n1);
-
-   U2 : INVMAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => n1, Y => nq);
-
-
-end UDSM;
-
-configuration CFG_nmx2_x4_UDSM of nmx2_x4 is
-   for UDSM
-   end for;
-end CFG_nmx2_x4_UDSM;
-
-
------ CELL nmx3_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nmx3_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd0_nq_R                   :	Time := 0.356 ns;
-      tpdcmd0_nq_F                   :	Time := 0.495 ns;
-      tpdcmd1_nq_R                   :	Time := 0.414 ns;
-      tpdcmd1_nq_F                   :	Time := 0.566 ns;
-      tpdi0_nq_R                     :	Time := 0.315 ns;
-      tpdi0_nq_F                     :	Time := 0.441 ns;
-      tpdi1_nq_R                     :	Time := 0.429 ns;
-      tpdi1_nq_F                     :	Time := 0.582 ns;
-      tpdi2_nq_R                     :	Time := 0.429 ns;
-      tpdi2_nq_F                     :	Time := 0.582 ns;
-      twdcmd0_R                      :	Time := 0.000 ns;
-      twdcmd0_F                      :	Time := 0.000 ns;
-      twdcmd1_R                      :	Time := 0.000 ns;
-      twdcmd1_F                      :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      cmd0                           :	in    STD_LOGIC;
-      cmd1                           :	in    STD_LOGIC;
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nmx3_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of nmx3_x1 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1, n2 : STD_LOGIC;
-
-   component MUX2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         S0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component INVMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : MUX2MAC
-	port map( I0 => i2, I1 => i1, S0 => cmd1, Y => n1);
-
-   U2 : MUX2MAC
-	port map( I0 => i0, I1 => n1, S0 => cmd0, Y => n2);
-
-   U3 : INVMAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => n2, Y => nq);
-
-
-end UDSM;
-
-configuration CFG_nmx3_x1_UDSM of nmx3_x1 is
-   for UDSM
-   end for;
-end CFG_nmx3_x1_UDSM;
-
-
------ CELL nmx3_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nmx3_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd0_nq_R                   :	Time := 0.790 ns;
-      tpdcmd0_nq_F                   :	Time := 0.936 ns;
-      tpdcmd1_nq_R                   :	Time := 0.866 ns;
-      tpdcmd1_nq_F                   :	Time := 1.048 ns;
-      tpdi0_nq_R                     :	Time := 0.748 ns;
-      tpdi0_nq_F                     :	Time := 0.900 ns;
-      tpdi1_nq_R                     :	Time := 0.869 ns;
-      tpdi1_nq_F                     :	Time := 1.053 ns;
-      tpdi2_nq_R                     :	Time := 0.869 ns;
-      tpdi2_nq_F                     :	Time := 1.053 ns;
-      twdcmd0_R                      :	Time := 0.000 ns;
-      twdcmd0_F                      :	Time := 0.000 ns;
-      twdcmd1_R                      :	Time := 0.000 ns;
-      twdcmd1_F                      :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      cmd0                           :	in    STD_LOGIC;
-      cmd1                           :	in    STD_LOGIC;
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nmx3_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of nmx3_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1, n2 : STD_LOGIC;
-
-   component MUX2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         S0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component INVMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : MUX2MAC
-	port map( I0 => i2, I1 => i1, S0 => cmd1, Y => n1);
-
-   U2 : MUX2MAC
-	port map( I0 => i0, I1 => n1, S0 => cmd0, Y => n2);
-
-   U3 : INVMAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => n2, Y => nq);
-
-
-end UDSM;
-
-configuration CFG_nmx3_x4_UDSM of nmx3_x4 is
-   for UDSM
-   end for;
-end CFG_nmx3_x4_UDSM;
-
-
------ CELL no2_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity no2_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.298 ns;
-      tpdi0_nq_F                     :	Time := 0.121 ns;
-      tpdi1_nq_R                     :	Time := 0.193 ns;
-      tpdi1_nq_F                     :	Time := 0.161 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end no2_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of no2_x1 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component NOR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : NOR2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i0, I1 => i1, Y => nq);
-
-
-end UDSM;
-
-configuration CFG_no2_x1_UDSM of no2_x1 is
-   for UDSM
-   end for;
-end CFG_no2_x1_UDSM;
-
-
------ CELL no2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity no2_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.618 ns;
-      tpdi0_nq_F                     :	Time := 0.447 ns;
-      tpdi1_nq_R                     :	Time := 0.522 ns;
-      tpdi1_nq_F                     :	Time := 0.504 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end no2_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of no2_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component NOR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : NOR2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i0, I1 => i1, Y => nq);
-
-
-end UDSM;
-
-configuration CFG_no2_x4_UDSM of no2_x4 is
-   for UDSM
-   end for;
-end CFG_no2_x4_UDSM;
-
-
------ CELL no3_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity no3_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.318 ns;
-      tpdi0_nq_F                     :	Time := 0.246 ns;
-      tpdi1_nq_R                     :	Time := 0.215 ns;
-      tpdi1_nq_F                     :	Time := 0.243 ns;
-      tpdi2_nq_R                     :	Time := 0.407 ns;
-      tpdi2_nq_F                     :	Time := 0.192 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end no3_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of no3_x1 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component NOR3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : NOR3MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i2, I1 => i0, I2 => i1, Y => nq);
-
-
-end UDSM;
-
-configuration CFG_no3_x1_UDSM of no3_x1 is
-   for UDSM
-   end for;
-end CFG_no3_x1_UDSM;
-
-
------ CELL no3_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity no3_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.722 ns;
-      tpdi0_nq_F                     :	Time := 0.561 ns;
-      tpdi1_nq_R                     :	Time := 0.638 ns;
-      tpdi1_nq_F                     :	Time := 0.623 ns;
-      tpdi2_nq_R                     :	Time := 0.545 ns;
-      tpdi2_nq_F                     :	Time := 0.640 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end no3_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of no3_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component NOR3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : NOR3MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i2, I1 => i0, I2 => i1, Y => nq);
-
-
-end UDSM;
-
-configuration CFG_no3_x4_UDSM of no3_x4 is
-   for UDSM
-   end for;
-end CFG_no3_x4_UDSM;
-
-
------ CELL no4_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity no4_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.330 ns;
-      tpdi0_nq_F                     :	Time := 0.340 ns;
-      tpdi1_nq_R                     :	Time := 0.230 ns;
-      tpdi1_nq_F                     :	Time := 0.320 ns;
-      tpdi2_nq_R                     :	Time := 0.419 ns;
-      tpdi2_nq_F                     :	Time := 0.333 ns;
-      tpdi3_nq_R                     :	Time := 0.499 ns;
-      tpdi3_nq_F                     :	Time := 0.271 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end no4_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of no4_x1 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component NOR4MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         I3                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : NOR4MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i0, I1 => i1, I2 => i2, I3 => i3, Y => nq);
-
-
-end UDSM;
-
-configuration CFG_no4_x1_UDSM of no4_x1 is
-   for UDSM
-   end for;
-end CFG_no4_x1_UDSM;
-
-
------ CELL no4_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity no4_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.656 ns;
-      tpdi0_nq_F                     :	Time := 0.777 ns;
-      tpdi1_nq_R                     :	Time := 0.564 ns;
-      tpdi1_nq_F                     :	Time := 0.768 ns;
-      tpdi2_nq_R                     :	Time := 0.739 ns;
-      tpdi2_nq_F                     :	Time := 0.761 ns;
-      tpdi3_nq_R                     :	Time := 0.816 ns;
-      tpdi3_nq_F                     :	Time := 0.693 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end no4_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of no4_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component NOR4MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         I3                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : NOR4MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i0, I1 => i1, I2 => i2, I3 => i3, Y => nq);
-
-
-end UDSM;
-
-configuration CFG_no4_x4_UDSM of no4_x4 is
-   for UDSM
-   end for;
-end CFG_no4_x4_UDSM;
-
-
------ CELL noa2a2a2a24_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa2a2a2a24_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.649 ns;
-      tpdi0_nq_F                     :	Time := 0.606 ns;
-      tpdi1_nq_R                     :	Time := 0.775 ns;
-      tpdi1_nq_F                     :	Time := 0.562 ns;
-      tpdi2_nq_R                     :	Time := 0.550 ns;
-      tpdi2_nq_F                     :	Time := 0.662 ns;
-      tpdi3_nq_R                     :	Time := 0.667 ns;
-      tpdi3_nq_F                     :	Time := 0.616 ns;
-      tpdi4_nq_R                     :	Time := 0.419 ns;
-      tpdi4_nq_F                     :	Time := 0.613 ns;
-      tpdi5_nq_R                     :	Time := 0.329 ns;
-      tpdi5_nq_F                     :	Time := 0.662 ns;
-      tpdi6_nq_R                     :	Time := 0.270 ns;
-      tpdi6_nq_F                     :	Time := 0.535 ns;
-      tpdi7_nq_R                     :	Time := 0.200 ns;
-      tpdi7_nq_F                     :	Time := 0.591 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns;
-      twdi6_R                        :	Time := 0.000 ns;
-      twdi6_F                        :	Time := 0.000 ns;
-      twdi7_R                        :	Time := 0.000 ns;
-      twdi7_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      i6                             :	in    STD_LOGIC;
-      i7                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa2a2a2a24_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of noa2a2a2a24_x1 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1, n2, n3, n4 : STD_LOGIC;
-
-   component AND4MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         I3                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : AND4MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => nq);
-
-   U2 : NAND2MAC
-	port map( I0 => i0, I1 => i1, Y => n4);
-
-   U3 : NAND2MAC
-	port map( I0 => i2, I1 => i3, Y => n3);
-
-   U4 : NAND2MAC
-	port map( I0 => i4, I1 => i5, Y => n2);
-
-   U5 : NAND2MAC
-	port map( I0 => i6, I1 => i7, Y => n1);
-
-
-end UDSM;
-
-configuration CFG_noa2a2a2a24_x1_UDSM of noa2a2a2a24_x1 is
-   for UDSM
-   end for;
-end CFG_noa2a2a2a24_x1_UDSM;
-
-
------ CELL noa2a2a2a24_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa2a2a2a24_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.966 ns;
-      tpdi0_nq_F                     :	Time := 1.049 ns;
-      tpdi1_nq_R                     :	Time := 1.097 ns;
-      tpdi1_nq_F                     :	Time := 1.005 ns;
-      tpdi2_nq_R                     :	Time := 0.867 ns;
-      tpdi2_nq_F                     :	Time := 1.106 ns;
-      tpdi3_nq_R                     :	Time := 0.990 ns;
-      tpdi3_nq_F                     :	Time := 1.061 ns;
-      tpdi4_nq_R                     :	Time := 0.748 ns;
-      tpdi4_nq_F                     :	Time := 1.061 ns;
-      tpdi5_nq_R                     :	Time := 0.649 ns;
-      tpdi5_nq_F                     :	Time := 1.109 ns;
-      tpdi6_nq_R                     :	Time := 0.606 ns;
-      tpdi6_nq_F                     :	Time := 0.999 ns;
-      tpdi7_nq_R                     :	Time := 0.525 ns;
-      tpdi7_nq_F                     :	Time := 1.052 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns;
-      twdi6_R                        :	Time := 0.000 ns;
-      twdi6_F                        :	Time := 0.000 ns;
-      twdi7_R                        :	Time := 0.000 ns;
-      twdi7_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      i6                             :	in    STD_LOGIC;
-      i7                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa2a2a2a24_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of noa2a2a2a24_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1, n2, n3, n4 : STD_LOGIC;
-
-   component AND4MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         I3                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : AND4MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => nq);
-
-   U2 : NAND2MAC
-	port map( I0 => i0, I1 => i1, Y => n4);
-
-   U3 : NAND2MAC
-	port map( I0 => i2, I1 => i3, Y => n3);
-
-   U4 : NAND2MAC
-	port map( I0 => i4, I1 => i5, Y => n2);
-
-   U5 : NAND2MAC
-	port map( I0 => i6, I1 => i7, Y => n1);
-
-
-end UDSM;
-
-configuration CFG_noa2a2a2a24_x4_UDSM of noa2a2a2a24_x4 is
-   for UDSM
-   end for;
-end CFG_noa2a2a2a24_x4_UDSM;
-
-
------ CELL noa2a2a23_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa2a2a23_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.525 ns;
-      tpdi0_nq_F                     :	Time := 0.425 ns;
-      tpdi1_nq_R                     :	Time := 0.643 ns;
-      tpdi1_nq_F                     :	Time := 0.388 ns;
-      tpdi2_nq_R                     :	Time := 0.307 ns;
-      tpdi2_nq_F                     :	Time := 0.479 ns;
-      tpdi3_nq_R                     :	Time := 0.398 ns;
-      tpdi3_nq_F                     :	Time := 0.438 ns;
-      tpdi4_nq_R                     :	Time := 0.250 ns;
-      tpdi4_nq_F                     :	Time := 0.416 ns;
-      tpdi5_nq_R                     :	Time := 0.178 ns;
-      tpdi5_nq_F                     :	Time := 0.464 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa2a2a23_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of noa2a2a23_x1 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1, n2, n3 : STD_LOGIC;
-
-   component AND3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : AND3MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => n1, I1 => n2, I2 => n3, Y => nq);
-
-   U2 : NAND2MAC
-	port map( I0 => i2, I1 => i3, Y => n2);
-
-   U3 : NAND2MAC
-	port map( I0 => i0, I1 => i1, Y => n1);
-
-   U4 : NAND2MAC
-	port map( I0 => i4, I1 => i5, Y => n3);
-
-
-end UDSM;
-
-configuration CFG_noa2a2a23_x1_UDSM of noa2a2a23_x1 is
-   for UDSM
-   end for;
-end CFG_noa2a2a23_x1_UDSM;
-
-
------ CELL noa2a2a23_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa2a2a23_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.834 ns;
-      tpdi0_nq_F                     :	Time := 0.814 ns;
-      tpdi1_nq_R                     :	Time := 0.955 ns;
-      tpdi1_nq_F                     :	Time := 0.778 ns;
-      tpdi2_nq_R                     :	Time := 0.620 ns;
-      tpdi2_nq_F                     :	Time := 0.873 ns;
-      tpdi3_nq_R                     :	Time := 0.716 ns;
-      tpdi3_nq_F                     :	Time := 0.833 ns;
-      tpdi4_nq_R                     :	Time := 0.574 ns;
-      tpdi4_nq_F                     :	Time := 0.819 ns;
-      tpdi5_nq_R                     :	Time := 0.496 ns;
-      tpdi5_nq_F                     :	Time := 0.865 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa2a2a23_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of noa2a2a23_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1, n2, n3 : STD_LOGIC;
-
-   component AND3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : AND3MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => n1, I1 => n2, I2 => n3, Y => nq);
-
-   U2 : NAND2MAC
-	port map( I0 => i2, I1 => i3, Y => n2);
-
-   U3 : NAND2MAC
-	port map( I0 => i0, I1 => i1, Y => n1);
-
-   U4 : NAND2MAC
-	port map( I0 => i4, I1 => i5, Y => n3);
-
-
-end UDSM;
-
-configuration CFG_noa2a2a23_x4_UDSM of noa2a2a23_x4 is
-   for UDSM
-   end for;
-end CFG_noa2a2a23_x4_UDSM;
-
-
------ CELL noa2a22_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa2a22_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.151 ns;
-      tpdi0_nq_F                     :	Time := 0.327 ns;
-      tpdi1_nq_R                     :	Time := 0.218 ns;
-      tpdi1_nq_F                     :	Time := 0.287 ns;
-      tpdi2_nq_R                     :	Time := 0.284 ns;
-      tpdi2_nq_F                     :	Time := 0.289 ns;
-      tpdi3_nq_R                     :	Time := 0.372 ns;
-      tpdi3_nq_F                     :	Time := 0.256 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa2a22_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of noa2a22_x1 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1, n2 : STD_LOGIC;
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : AND2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => n1, I1 => n2, Y => nq);
-
-   U2 : NAND2MAC
-	port map( I0 => i2, I1 => i3, Y => n2);
-
-   U3 : NAND2MAC
-	port map( I0 => i0, I1 => i1, Y => n1);
-
-
-end UDSM;
-
-configuration CFG_noa2a22_x1_UDSM of noa2a22_x1 is
-   for UDSM
-   end for;
-end CFG_noa2a22_x1_UDSM;
-
-
------ CELL noa2a22_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa2a22_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.562 ns;
-      tpdi0_nq_F                     :	Time := 0.745 ns;
-      tpdi1_nq_R                     :	Time := 0.646 ns;
-      tpdi1_nq_F                     :	Time := 0.714 ns;
-      tpdi2_nq_R                     :	Time := 0.701 ns;
-      tpdi2_nq_F                     :	Time := 0.703 ns;
-      tpdi3_nq_R                     :	Time := 0.805 ns;
-      tpdi3_nq_F                     :	Time := 0.677 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa2a22_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of noa2a22_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1, n2 : STD_LOGIC;
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : AND2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => n1, I1 => n2, Y => nq);
-
-   U2 : NAND2MAC
-	port map( I0 => i2, I1 => i3, Y => n2);
-
-   U3 : NAND2MAC
-	port map( I0 => i0, I1 => i1, Y => n1);
-
-
-end UDSM;
-
-configuration CFG_noa2a22_x4_UDSM of noa2a22_x4 is
-   for UDSM
-   end for;
-end CFG_noa2a22_x4_UDSM;
-
-
------ CELL noa2ao222_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa2ao222_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.348 ns;
-      tpdi0_nq_F                     :	Time := 0.422 ns;
-      tpdi1_nq_R                     :	Time := 0.440 ns;
-      tpdi1_nq_F                     :	Time := 0.378 ns;
-      tpdi2_nq_R                     :	Time := 0.186 ns;
-      tpdi2_nq_F                     :	Time := 0.473 ns;
-      tpdi3_nq_R                     :	Time := 0.256 ns;
-      tpdi3_nq_F                     :	Time := 0.459 ns;
-      tpdi4_nq_R                     :	Time := 0.240 ns;
-      tpdi4_nq_F                     :	Time := 0.309 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa2ao222_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of noa2ao222_x1 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1, n2, n3 : STD_LOGIC;
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component OR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : AND2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => n1, I1 => n2, Y => nq);
-
-   U2 : OR2MAC
-	port map( I0 => i2, I1 => i3, Y => n3);
-
-   U3 : NAND2MAC
-	port map( I0 => i4, I1 => n3, Y => n2);
-
-   U4 : NAND2MAC
-	port map( I0 => i0, I1 => i1, Y => n1);
-
-
-end UDSM;
-
-configuration CFG_noa2ao222_x1_UDSM of noa2ao222_x1 is
-   for UDSM
-   end for;
-end CFG_noa2ao222_x1_UDSM;
-
-
------ CELL noa2ao222_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa2ao222_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.684 ns;
-      tpdi0_nq_F                     :	Time := 0.801 ns;
-      tpdi1_nq_R                     :	Time := 0.780 ns;
-      tpdi1_nq_F                     :	Time := 0.758 ns;
-      tpdi2_nq_R                     :	Time := 0.638 ns;
-      tpdi2_nq_F                     :	Time := 0.809 ns;
-      tpdi3_nq_R                     :	Time := 0.732 ns;
-      tpdi3_nq_F                     :	Time := 0.795 ns;
-      tpdi4_nq_R                     :	Time := 0.718 ns;
-      tpdi4_nq_F                     :	Time := 0.664 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa2ao222_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of noa2ao222_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1, n2, n3 : STD_LOGIC;
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component OR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : AND2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => n1, I1 => n2, Y => nq);
-
-   U2 : OR2MAC
-	port map( I0 => i2, I1 => i3, Y => n3);
-
-   U3 : NAND2MAC
-	port map( I0 => i4, I1 => n3, Y => n2);
-
-   U4 : NAND2MAC
-	port map( I0 => i0, I1 => i1, Y => n1);
-
-
-end UDSM;
-
-configuration CFG_noa2ao222_x4_UDSM of noa2ao222_x4 is
-   for UDSM
-   end for;
-end CFG_noa2ao222_x4_UDSM;
-
-
------ CELL noa3ao322_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa3ao322_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.396 ns;
-      tpdi0_nq_F                     :	Time := 0.616 ns;
-      tpdi1_nq_R                     :	Time := 0.486 ns;
-      tpdi1_nq_F                     :	Time := 0.552 ns;
-      tpdi2_nq_R                     :	Time := 0.546 ns;
-      tpdi2_nq_F                     :	Time := 0.488 ns;
-      tpdi3_nq_R                     :	Time := 0.196 ns;
-      tpdi3_nq_F                     :	Time := 0.599 ns;
-      tpdi4_nq_R                     :	Time := 0.264 ns;
-      tpdi4_nq_F                     :	Time := 0.608 ns;
-      tpdi5_nq_R                     :	Time := 0.328 ns;
-      tpdi5_nq_F                     :	Time := 0.581 ns;
-      tpdi6_nq_R                     :	Time := 0.246 ns;
-      tpdi6_nq_F                     :	Time := 0.311 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns;
-      twdi6_R                        :	Time := 0.000 ns;
-      twdi6_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      i6                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa3ao322_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of noa3ao322_x1 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1, n2, n3 : STD_LOGIC;
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component OR3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : AND2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => n1, I1 => n2, Y => nq);
-
-   U2 : NAND3MAC
-	port map( I0 => i1, I1 => i2, I2 => i0, Y => n2);
-
-   U3 : OR3MAC
-	port map( I0 => i3, I1 => i4, I2 => i5, Y => n3);
-
-   U4 : NAND2MAC
-	port map( I0 => i6, I1 => n3, Y => n1);
-
-
-end UDSM;
-
-configuration CFG_noa3ao322_x1_UDSM of noa3ao322_x1 is
-   for UDSM
-   end for;
-end CFG_noa3ao322_x1_UDSM;
-
-
------ CELL noa3ao322_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa3ao322_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.819 ns;
-      tpdi0_nq_F                     :	Time := 0.987 ns;
-      tpdi1_nq_R                     :	Time := 0.914 ns;
-      tpdi1_nq_F                     :	Time := 0.931 ns;
-      tpdi2_nq_R                     :	Time := 0.990 ns;
-      tpdi2_nq_F                     :	Time := 0.874 ns;
-      tpdi3_nq_R                     :	Time := 0.729 ns;
-      tpdi3_nq_F                     :	Time := 0.926 ns;
-      tpdi4_nq_R                     :	Time := 0.821 ns;
-      tpdi4_nq_F                     :	Time := 0.924 ns;
-      tpdi5_nq_R                     :	Time := 0.907 ns;
-      tpdi5_nq_F                     :	Time := 0.900 ns;
-      tpdi6_nq_R                     :	Time := 0.738 ns;
-      tpdi6_nq_F                     :	Time := 0.718 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns;
-      twdi6_R                        :	Time := 0.000 ns;
-      twdi6_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      i6                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa3ao322_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of noa3ao322_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1, n2, n3 : STD_LOGIC;
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component OR3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : AND2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => n1, I1 => n2, Y => nq);
-
-   U2 : NAND3MAC
-	port map( I0 => i1, I1 => i2, I2 => i0, Y => n2);
-
-   U3 : OR3MAC
-	port map( I0 => i3, I1 => i4, I2 => i5, Y => n3);
-
-   U4 : NAND2MAC
-	port map( I0 => i6, I1 => n3, Y => n1);
-
-
-end UDSM;
-
-configuration CFG_noa3ao322_x4_UDSM of noa3ao322_x4 is
-   for UDSM
-   end for;
-end CFG_noa3ao322_x4_UDSM;
-
-
------ CELL noa22_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa22_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.151 ns;
-      tpdi0_nq_F                     :	Time := 0.327 ns;
-      tpdi1_nq_R                     :	Time := 0.218 ns;
-      tpdi1_nq_F                     :	Time := 0.287 ns;
-      tpdi2_nq_R                     :	Time := 0.218 ns;
-      tpdi2_nq_F                     :	Time := 0.241 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa22_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of noa22_x1 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1 : STD_LOGIC;
-
-   component NOR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : NOR2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i2, I1 => n1, Y => nq);
-
-   U2 : AND2MAC
-	port map( I0 => i0, I1 => i1, Y => n1);
-
-
-end UDSM;
-
-configuration CFG_noa22_x1_UDSM of noa22_x1 is
-   for UDSM
-   end for;
-end CFG_noa22_x1_UDSM;
-
-
------ CELL noa22_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity noa22_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.550 ns;
-      tpdi0_nq_F                     :	Time := 0.740 ns;
-      tpdi1_nq_R                     :	Time := 0.643 ns;
-      tpdi1_nq_F                     :	Time := 0.709 ns;
-      tpdi2_nq_R                     :	Time := 0.610 ns;
-      tpdi2_nq_F                     :	Time := 0.646 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end noa22_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of noa22_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1 : STD_LOGIC;
-
-   component NOR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : NOR2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i2, I1 => n1, Y => nq);
-
-   U2 : AND2MAC
-	port map( I0 => i0, I1 => i1, Y => n1);
-
-
-end UDSM;
-
-configuration CFG_noa22_x4_UDSM of noa22_x4 is
-   for UDSM
-   end for;
-end CFG_noa22_x4_UDSM;
-
-
------ CELL nts_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nts_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd_nq_R                    :	Time := 0.249 ns;
-      tpdcmd_nq_F                    :	Time := 0.041 ns;
-      tpdcmd_nq_LZ                   :	Time := 0.249 ns;
-      tpdcmd_nq_HZ                   :	Time := 0.041 ns;
-      tpdi_nq_R                      :	Time := 0.169 ns;
-      tpdi_nq_F                      :	Time := 0.201 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      cmd                            :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nts_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of nts_x1 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component INV3SHEMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         OE                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : INV3SHEMAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i, OE => cmd, Y => nq);
-
-
-end UDSM;
-
-configuration CFG_nts_x1_UDSM of nts_x1 is
-   for UDSM
-   end for;
-end CFG_nts_x1_UDSM;
-
-
------ CELL nts_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nts_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd_nq_R                    :	Time := 0.330 ns;
-      tpdcmd_nq_F                    :	Time := 0.033 ns;
-      tpdcmd_nq_LZ                   :	Time := 0.330 ns;
-      tpdcmd_nq_HZ                   :	Time := 0.033 ns;
-      tpdi_nq_R                      :	Time := 0.167 ns;
-      tpdi_nq_F                      :	Time := 0.201 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      cmd                            :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nts_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of nts_x2 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component INV3SHEMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         OE                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : INV3SHEMAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i, OE => cmd, Y => nq);
-
-
-end UDSM;
-
-configuration CFG_nts_x2_UDSM of nts_x2 is
-   for UDSM
-   end for;
-end CFG_nts_x2_UDSM;
-
-
------ CELL nxr2_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nxr2_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.288 ns;
-      tpdi0_nq_F                     :	Time := 0.293 ns;
-      tpdi1_nq_R                     :	Time := 0.156 ns;
-      tpdi1_nq_F                     :	Time := 0.327 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nxr2_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of nxr2_x1 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component NXOR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : NXOR2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i1, I1 => i0, Y => nq);
-
-
-end UDSM;
-
-configuration CFG_nxr2_x1_UDSM of nxr2_x1 is
-   for UDSM
-   end for;
-end CFG_nxr2_x1_UDSM;
-
-
------ CELL nxr2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity nxr2_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_nq_R                     :	Time := 0.522 ns;
-      tpdi0_nq_F                     :	Time := 0.553 ns;
-      tpdi1_nq_R                     :	Time := 0.553 ns;
-      tpdi1_nq_F                     :	Time := 0.542 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end nxr2_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of nxr2_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component NXOR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : NXOR2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i1, I1 => i0, Y => nq);
-
-
-end UDSM;
-
-configuration CFG_nxr2_x4_UDSM of nxr2_x4 is
-   for UDSM
-   end for;
-end CFG_nxr2_x4_UDSM;
-
-
------ CELL o2_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity o2_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.406 ns;
-      tpdi0_q_F                      :	Time := 0.310 ns;
-      tpdi1_q_R                      :	Time := 0.335 ns;
-      tpdi1_q_F                      :	Time := 0.364 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end o2_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of o2_x2 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component OR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : OR2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i1, I1 => i0, Y => q);
-
-
-end UDSM;
-
-configuration CFG_o2_x2_UDSM of o2_x2 is
-   for UDSM
-   end for;
-end CFG_o2_x2_UDSM;
-
-
------ CELL o2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity o2_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.491 ns;
-      tpdi0_q_F                      :	Time := 0.394 ns;
-      tpdi1_q_R                      :	Time := 0.427 ns;
-      tpdi1_q_F                      :	Time := 0.464 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end o2_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of o2_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component OR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : OR2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i1, I1 => i0, Y => q);
-
-
-end UDSM;
-
-configuration CFG_o2_x4_UDSM of o2_x4 is
-   for UDSM
-   end for;
-end CFG_o2_x4_UDSM;
-
-
------ CELL o3_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity o3_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.494 ns;
-      tpdi0_q_F                      :	Time := 0.407 ns;
-      tpdi1_q_R                      :	Time := 0.430 ns;
-      tpdi1_q_F                      :	Time := 0.482 ns;
-      tpdi2_q_R                      :	Time := 0.360 ns;
-      tpdi2_q_F                      :	Time := 0.506 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end o3_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of o3_x2 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component OR3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : OR3MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i0, I1 => i1, I2 => i2, Y => q);
-
-
-end UDSM;
-
-configuration CFG_o3_x2_UDSM of o3_x2 is
-   for UDSM
-   end for;
-end CFG_o3_x2_UDSM;
-
-
------ CELL o3_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity o3_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.569 ns;
-      tpdi0_q_F                      :	Time := 0.501 ns;
-      tpdi1_q_R                      :	Time := 0.510 ns;
-      tpdi1_q_F                      :	Time := 0.585 ns;
-      tpdi2_q_R                      :	Time := 0.447 ns;
-      tpdi2_q_F                      :	Time := 0.622 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end o3_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of o3_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component OR3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : OR3MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i0, I1 => i1, I2 => i2, Y => q);
-
-
-end UDSM;
-
-configuration CFG_o3_x4_UDSM of o3_x4 is
-   for UDSM
-   end for;
-end CFG_o3_x4_UDSM;
-
-
------ CELL o4_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity o4_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.508 ns;
-      tpdi0_q_F                      :	Time := 0.601 ns;
-      tpdi1_q_R                      :	Time := 0.446 ns;
-      tpdi1_q_F                      :	Time := 0.631 ns;
-      tpdi2_q_R                      :	Time := 0.567 ns;
-      tpdi2_q_F                      :	Time := 0.531 ns;
-      tpdi3_q_R                      :	Time := 0.378 ns;
-      tpdi3_q_F                      :	Time := 0.626 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end o4_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of o4_x2 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component OR4MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         I3                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : OR4MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i2, I1 => i3, I2 => i0, I3 => i1, Y => q);
-
-
-end UDSM;
-
-configuration CFG_o4_x2_UDSM of o4_x2 is
-   for UDSM
-   end for;
-end CFG_o4_x2_UDSM;
-
-
------ CELL o4_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity o4_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.574 ns;
-      tpdi0_q_F                      :	Time := 0.638 ns;
-      tpdi1_q_R                      :	Time := 0.492 ns;
-      tpdi1_q_F                      :	Time := 0.650 ns;
-      tpdi2_q_R                      :	Time := 0.649 ns;
-      tpdi2_q_F                      :	Time := 0.611 ns;
-      tpdi3_q_R                      :	Time := 0.721 ns;
-      tpdi3_q_F                      :	Time := 0.536 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end o4_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of o4_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component OR4MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         I3                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : OR4MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i2, I1 => i3, I2 => i0, I3 => i1, Y => q);
-
-
-end UDSM;
-
-configuration CFG_o4_x4_UDSM of o4_x4 is
-   for UDSM
-   end for;
-end CFG_o4_x4_UDSM;
-
-
------ CELL oa2a2a2a24_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa2a2a2a24_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.780 ns;
-      tpdi0_q_F                      :	Time := 0.797 ns;
-      tpdi1_q_R                      :	Time := 0.909 ns;
-      tpdi1_q_F                      :	Time := 0.753 ns;
-      tpdi2_q_R                      :	Time := 0.682 ns;
-      tpdi2_q_F                      :	Time := 0.856 ns;
-      tpdi3_q_R                      :	Time := 0.803 ns;
-      tpdi3_q_F                      :	Time := 0.810 ns;
-      tpdi4_q_R                      :	Time := 0.565 ns;
-      tpdi4_q_F                      :	Time := 0.813 ns;
-      tpdi5_q_R                      :	Time := 0.467 ns;
-      tpdi5_q_F                      :	Time := 0.861 ns;
-      tpdi6_q_R                      :	Time := 0.426 ns;
-      tpdi6_q_F                      :	Time := 0.748 ns;
-      tpdi7_q_R                      :	Time := 0.346 ns;
-      tpdi7_q_F                      :	Time := 0.800 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns;
-      twdi6_R                        :	Time := 0.000 ns;
-      twdi6_F                        :	Time := 0.000 ns;
-      twdi7_R                        :	Time := 0.000 ns;
-      twdi7_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      i6                             :	in    STD_LOGIC;
-      i7                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa2a2a2a24_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of oa2a2a2a24_x2 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1, n2, n3, n4 : STD_LOGIC;
-
-   component NAND4MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         I3                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : NAND4MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => q);
-
-   U2 : NAND2MAC
-	port map( I0 => i6, I1 => i7, Y => n4);
-
-   U3 : NAND2MAC
-	port map( I0 => i4, I1 => i5, Y => n3);
-
-   U4 : NAND2MAC
-	port map( I0 => i2, I1 => i3, Y => n2);
-
-   U5 : NAND2MAC
-	port map( I0 => i0, I1 => i1, Y => n1);
-
-
-end UDSM;
-
-configuration CFG_oa2a2a2a24_x2_UDSM of oa2a2a2a24_x2 is
-   for UDSM
-   end for;
-end CFG_oa2a2a2a24_x2_UDSM;
-
-
------ CELL oa2a2a2a24_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa2a2a2a24_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.823 ns;
-      tpdi0_q_F                      :	Time := 0.879 ns;
-      tpdi1_q_R                      :	Time := 0.955 ns;
-      tpdi1_q_F                      :	Time := 0.835 ns;
-      tpdi2_q_R                      :	Time := 0.726 ns;
-      tpdi2_q_F                      :	Time := 0.940 ns;
-      tpdi3_q_R                      :	Time := 0.851 ns;
-      tpdi3_q_F                      :	Time := 0.895 ns;
-      tpdi4_q_R                      :	Time := 0.619 ns;
-      tpdi4_q_F                      :	Time := 0.902 ns;
-      tpdi5_q_R                      :	Time := 0.515 ns;
-      tpdi5_q_F                      :	Time := 0.949 ns;
-      tpdi6_q_R                      :	Time := 0.487 ns;
-      tpdi6_q_F                      :	Time := 0.845 ns;
-      tpdi7_q_R                      :	Time := 0.399 ns;
-      tpdi7_q_F                      :	Time := 0.895 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns;
-      twdi6_R                        :	Time := 0.000 ns;
-      twdi6_F                        :	Time := 0.000 ns;
-      twdi7_R                        :	Time := 0.000 ns;
-      twdi7_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      i6                             :	in    STD_LOGIC;
-      i7                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa2a2a2a24_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of oa2a2a2a24_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1, n2, n3, n4 : STD_LOGIC;
-
-   component NAND4MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         I3                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : NAND4MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => q);
-
-   U2 : NAND2MAC
-	port map( I0 => i6, I1 => i7, Y => n4);
-
-   U3 : NAND2MAC
-	port map( I0 => i4, I1 => i5, Y => n3);
-
-   U4 : NAND2MAC
-	port map( I0 => i2, I1 => i3, Y => n2);
-
-   U5 : NAND2MAC
-	port map( I0 => i0, I1 => i1, Y => n1);
-
-
-end UDSM;
-
-configuration CFG_oa2a2a2a24_x4_UDSM of oa2a2a2a24_x4 is
-   for UDSM
-   end for;
-end CFG_oa2a2a2a24_x4_UDSM;
-
-
------ CELL oa2a2a23_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa2a2a23_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.653 ns;
-      tpdi0_q_F                      :	Time := 0.578 ns;
-      tpdi1_q_R                      :	Time := 0.775 ns;
-      tpdi1_q_F                      :	Time := 0.542 ns;
-      tpdi2_q_R                      :	Time := 0.441 ns;
-      tpdi2_q_F                      :	Time := 0.639 ns;
-      tpdi3_q_R                      :	Time := 0.540 ns;
-      tpdi3_q_F                      :	Time := 0.600 ns;
-      tpdi4_q_R                      :	Time := 0.402 ns;
-      tpdi4_q_F                      :	Time := 0.591 ns;
-      tpdi5_q_R                      :	Time := 0.321 ns;
-      tpdi5_q_F                      :	Time := 0.636 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa2a2a23_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of oa2a2a23_x2 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1, n2, n3 : STD_LOGIC;
-
-   component NAND3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : NAND3MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => n1, I1 => n2, I2 => n3, Y => q);
-
-   U2 : NAND2MAC
-	port map( I0 => i4, I1 => i5, Y => n2);
-
-   U3 : NAND2MAC
-	port map( I0 => i2, I1 => i3, Y => n1);
-
-   U4 : NAND2MAC
-	port map( I0 => i0, I1 => i1, Y => n3);
-
-
-end UDSM;
-
-configuration CFG_oa2a2a23_x2_UDSM of oa2a2a23_x2 is
-   for UDSM
-   end for;
-end CFG_oa2a2a23_x2_UDSM;
-
-
------ CELL oa2a2a23_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa2a2a23_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.699 ns;
-      tpdi0_q_F                      :	Time := 0.648 ns;
-      tpdi1_q_R                      :	Time := 0.822 ns;
-      tpdi1_q_F                      :	Time := 0.613 ns;
-      tpdi2_q_R                      :	Time := 0.493 ns;
-      tpdi2_q_F                      :	Time := 0.715 ns;
-      tpdi3_q_R                      :	Time := 0.594 ns;
-      tpdi3_q_F                      :	Time := 0.677 ns;
-      tpdi4_q_R                      :	Time := 0.464 ns;
-      tpdi4_q_F                      :	Time := 0.673 ns;
-      tpdi5_q_R                      :	Time := 0.379 ns;
-      tpdi5_q_F                      :	Time := 0.714 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa2a2a23_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of oa2a2a23_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1, n2, n3 : STD_LOGIC;
-
-   component NAND3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : NAND3MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => n1, I1 => n2, I2 => n3, Y => q);
-
-   U2 : NAND2MAC
-	port map( I0 => i4, I1 => i5, Y => n2);
-
-   U3 : NAND2MAC
-	port map( I0 => i2, I1 => i3, Y => n1);
-
-   U4 : NAND2MAC
-	port map( I0 => i0, I1 => i1, Y => n3);
-
-
-end UDSM;
-
-configuration CFG_oa2a2a23_x4_UDSM of oa2a2a23_x4 is
-   for UDSM
-   end for;
-end CFG_oa2a2a23_x4_UDSM;
-
-
------ CELL oa2a22_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa2a22_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.403 ns;
-      tpdi0_q_F                      :	Time := 0.564 ns;
-      tpdi1_q_R                      :	Time := 0.495 ns;
-      tpdi1_q_F                      :	Time := 0.534 ns;
-      tpdi2_q_R                      :	Time := 0.646 ns;
-      tpdi2_q_F                      :	Time := 0.487 ns;
-      tpdi3_q_R                      :	Time := 0.537 ns;
-      tpdi3_q_F                      :	Time := 0.512 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa2a22_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of oa2a22_x2 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1, n2 : STD_LOGIC;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : NAND2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => n1, I1 => n2, Y => q);
-
-   U2 : NAND2MAC
-	port map( I0 => i2, I1 => i3, Y => n2);
-
-   U3 : NAND2MAC
-	port map( I0 => i0, I1 => i1, Y => n1);
-
-
-end UDSM;
-
-configuration CFG_oa2a22_x2_UDSM of oa2a22_x2 is
-   for UDSM
-   end for;
-end CFG_oa2a22_x2_UDSM;
-
-
------ CELL oa2a22_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa2a22_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.519 ns;
-      tpdi0_q_F                      :	Time := 0.696 ns;
-      tpdi1_q_R                      :	Time := 0.624 ns;
-      tpdi1_q_F                      :	Time := 0.669 ns;
-      tpdi2_q_R                      :	Time := 0.763 ns;
-      tpdi2_q_F                      :	Time := 0.596 ns;
-      tpdi3_q_R                      :	Time := 0.644 ns;
-      tpdi3_q_F                      :	Time := 0.619 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa2a22_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of oa2a22_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1, n2 : STD_LOGIC;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : NAND2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => n1, I1 => n2, Y => q);
-
-   U2 : NAND2MAC
-	port map( I0 => i2, I1 => i3, Y => n2);
-
-   U3 : NAND2MAC
-	port map( I0 => i0, I1 => i1, Y => n1);
-
-
-end UDSM;
-
-configuration CFG_oa2a22_x4_UDSM of oa2a22_x4 is
-   for UDSM
-   end for;
-end CFG_oa2a22_x4_UDSM;
-
-
------ CELL oa2ao222_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa2ao222_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.495 ns;
-      tpdi0_q_F                      :	Time := 0.581 ns;
-      tpdi1_q_R                      :	Time := 0.598 ns;
-      tpdi1_q_F                      :	Time := 0.539 ns;
-      tpdi2_q_R                      :	Time := 0.464 ns;
-      tpdi2_q_F                      :	Time := 0.604 ns;
-      tpdi3_q_R                      :	Time := 0.556 ns;
-      tpdi3_q_F                      :	Time := 0.578 ns;
-      tpdi4_q_R                      :	Time := 0.558 ns;
-      tpdi4_q_F                      :	Time := 0.453 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa2ao222_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of oa2ao222_x2 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1, n2, n3 : STD_LOGIC;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component OR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : NAND2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => n1, I1 => n2, Y => q);
-
-   U2 : OR2MAC
-	port map( I0 => i3, I1 => i2, Y => n3);
-
-   U3 : NAND2MAC
-	port map( I0 => i4, I1 => n3, Y => n2);
-
-   U4 : NAND2MAC
-	port map( I0 => i0, I1 => i1, Y => n1);
-
-
-end UDSM;
-
-configuration CFG_oa2ao222_x2_UDSM of oa2ao222_x2 is
-   for UDSM
-   end for;
-end CFG_oa2ao222_x2_UDSM;
-
-
------ CELL oa2ao222_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa2ao222_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.553 ns;
-      tpdi0_q_F                      :	Time := 0.657 ns;
-      tpdi1_q_R                      :	Time := 0.662 ns;
-      tpdi1_q_F                      :	Time := 0.616 ns;
-      tpdi2_q_R                      :	Time := 0.552 ns;
-      tpdi2_q_F                      :	Time := 0.693 ns;
-      tpdi3_q_R                      :	Time := 0.640 ns;
-      tpdi3_q_F                      :	Time := 0.660 ns;
-      tpdi4_q_R                      :	Time := 0.656 ns;
-      tpdi4_q_F                      :	Time := 0.529 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa2ao222_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of oa2ao222_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1, n2, n3 : STD_LOGIC;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component OR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : NAND2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => n1, I1 => n2, Y => q);
-
-   U2 : OR2MAC
-	port map( I0 => i3, I1 => i2, Y => n3);
-
-   U3 : NAND2MAC
-	port map( I0 => i4, I1 => n3, Y => n2);
-
-   U4 : NAND2MAC
-	port map( I0 => i0, I1 => i1, Y => n1);
-
-
-end UDSM;
-
-configuration CFG_oa2ao222_x4_UDSM of oa2ao222_x4 is
-   for UDSM
-   end for;
-end CFG_oa2ao222_x4_UDSM;
-
-
------ CELL oa3ao322_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa3ao322_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.638 ns;
-      tpdi0_q_F                      :	Time := 0.820 ns;
-      tpdi1_q_R                      :	Time := 0.735 ns;
-      tpdi1_q_F                      :	Time := 0.764 ns;
-      tpdi2_q_R                      :	Time := 0.806 ns;
-      tpdi2_q_F                      :	Time := 0.707 ns;
-      tpdi3_q_R                      :	Time := 0.560 ns;
-      tpdi3_q_F                      :	Time := 0.765 ns;
-      tpdi4_q_R                      :	Time := 0.649 ns;
-      tpdi4_q_F                      :	Time := 0.760 ns;
-      tpdi5_q_R                      :	Time := 0.734 ns;
-      tpdi5_q_F                      :	Time := 0.734 ns;
-      tpdi6_q_R                      :	Time := 0.563 ns;
-      tpdi6_q_F                      :	Time := 0.540 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns;
-      twdi6_R                        :	Time := 0.000 ns;
-      twdi6_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      i6                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa3ao322_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of oa3ao322_x2 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1, n2, n3 : STD_LOGIC;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component OR3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : NAND2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => n1, I1 => n2, Y => q);
-
-   U2 : OR3MAC
-	port map( I0 => i3, I1 => i4, I2 => i5, Y => n3);
-
-   U3 : NAND3MAC
-	port map( I0 => i1, I1 => i2, I2 => i0, Y => n2);
-
-   U4 : NAND2MAC
-	port map( I0 => i6, I1 => n3, Y => n1);
-
-
-end UDSM;
-
-configuration CFG_oa3ao322_x2_UDSM of oa3ao322_x2 is
-   for UDSM
-   end for;
-end CFG_oa3ao322_x2_UDSM;
-
-
------ CELL oa3ao322_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa3ao322_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.717 ns;
-      tpdi0_q_F                      :	Time := 0.946 ns;
-      tpdi1_q_R                      :	Time := 0.818 ns;
-      tpdi1_q_F                      :	Time := 0.890 ns;
-      tpdi2_q_R                      :	Time := 0.894 ns;
-      tpdi2_q_F                      :	Time := 0.834 ns;
-      tpdi3_q_R                      :	Time := 0.673 ns;
-      tpdi3_q_F                      :	Time := 0.898 ns;
-      tpdi4_q_R                      :	Time := 0.758 ns;
-      tpdi4_q_F                      :	Time := 0.896 ns;
-      tpdi5_q_R                      :	Time := 0.839 ns;
-      tpdi5_q_F                      :	Time := 0.865 ns;
-      tpdi6_q_R                      :	Time := 0.684 ns;
-      tpdi6_q_F                      :	Time := 0.651 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns;
-      twdi6_R                        :	Time := 0.000 ns;
-      twdi6_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      i6                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa3ao322_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of oa3ao322_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1, n2, n3 : STD_LOGIC;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component OR3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component NAND3MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         I2                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : NAND2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => n1, I1 => n2, Y => q);
-
-   U2 : OR3MAC
-	port map( I0 => i3, I1 => i4, I2 => i5, Y => n3);
-
-   U3 : NAND3MAC
-	port map( I0 => i1, I1 => i2, I2 => i0, Y => n2);
-
-   U4 : NAND2MAC
-	port map( I0 => i6, I1 => n3, Y => n1);
-
-
-end UDSM;
-
-configuration CFG_oa3ao322_x4_UDSM of oa3ao322_x4 is
-   for UDSM
-   end for;
-end CFG_oa3ao322_x4_UDSM;
-
-
------ CELL oa22_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa22_x2 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.390 ns;
-      tpdi0_q_F                      :	Time := 0.555 ns;
-      tpdi1_q_R                      :	Time := 0.488 ns;
-      tpdi1_q_F                      :	Time := 0.525 ns;
-      tpdi2_q_R                      :	Time := 0.438 ns;
-      tpdi2_q_F                      :	Time := 0.454 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa22_x2;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of oa22_x2 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1 : STD_LOGIC;
-
-   component OR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : OR2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => n1, I1 => i2, Y => q);
-
-   U2 : AND2MAC
-	port map( I0 => i0, I1 => i1, Y => n1);
-
-
-end UDSM;
-
-configuration CFG_oa22_x2_UDSM of oa22_x2 is
-   for UDSM
-   end for;
-end CFG_oa22_x2_UDSM;
-
-
------ CELL oa22_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity oa22_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.511 ns;
-      tpdi0_q_F                      :	Time := 0.677 ns;
-      tpdi1_q_R                      :	Time := 0.615 ns;
-      tpdi1_q_F                      :	Time := 0.650 ns;
-      tpdi2_q_R                      :	Time := 0.523 ns;
-      tpdi2_q_F                      :	Time := 0.571 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end oa22_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of oa22_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1 : STD_LOGIC;
-
-   component OR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component AND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : OR2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => n1, I1 => i2, Y => q);
-
-   U2 : AND2MAC
-	port map( I0 => i0, I1 => i1, Y => n1);
-
-
-end UDSM;
-
-configuration CFG_oa22_x4_UDSM of oa22_x4 is
-   for UDSM
-   end for;
-end CFG_oa22_x4_UDSM;
-
-
------ CELL on12_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity on12_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.111 ns;
-      tpdi0_q_F                      :	Time := 0.234 ns;
-      tpdi1_q_R                      :	Time := 0.314 ns;
-      tpdi1_q_F                      :	Time := 0.291 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end on12_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of on12_x1 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1 : STD_LOGIC;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component INVMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : NAND2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i0, I1 => n1, Y => q);
-
-   U2 : INVMAC
-	port map( I0 => i1, Y => n1);
-
-
-end UDSM;
-
-configuration CFG_on12_x1_UDSM of on12_x1 is
-   for UDSM
-   end for;
-end CFG_on12_x1_UDSM;
-
-
------ CELL on12_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity on12_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.474 ns;
-      tpdi0_q_F                      :	Time := 0.499 ns;
-      tpdi1_q_R                      :	Time := 0.491 ns;
-      tpdi1_q_F                      :	Time := 0.394 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end on12_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of on12_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1 : STD_LOGIC;
-
-   component NAND2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component INVMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : NAND2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i0, I1 => n1, Y => q);
-
-   U2 : INVMAC
-	port map( I0 => i1, Y => n1);
-
-
-end UDSM;
-
-configuration CFG_on12_x4_UDSM of on12_x4 is
-   for UDSM
-   end for;
-end CFG_on12_x4_UDSM;
-
-
------ CELL one_x0 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity one_x0 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False);
-
-   port(
-      q                              :	out   STD_LOGIC := '1');
-end one_x0;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of one_x0 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-begin
-
-   -- Netlist
-   q <= '1';
-
-end UDSM;
-
-configuration CFG_one_x0_UDSM of one_x0 is
-   for UDSM
-   end for;
-end CFG_one_x0_UDSM;
-
-
------ CELL sff1_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity sff1_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdck_q_R                      :	Time := 0.500 ns;
-      tpdck_q_F                      :	Time := 0.500 ns;
-      tsui_ck                        :	Time := 0.585 ns;
-      thck_i                         :	Time := 0.000 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns;
-      twdck_R                        :	Time := 0.000 ns;
-      twdck_F                        :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      ck                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end sff1_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of sff1_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1 : STD_LOGIC;
-
-   component DFFLMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         D                              :  in    STD_LOGIC;
-         CLK                            :  in    STD_LOGIC;
-         CLR                            :  in    STD_LOGIC;
-         Q                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : DFFLMAC
-	generic map( tpdY_R => 2 ns, tpdY_F => 2 ns)
-	port map( D => i, CLK => ck, CLR => n1, Q => q);
-
-   n1 <= '1';
-
-end UDSM;
-
-configuration CFG_sff1_x4_UDSM of sff1_x4 is
-   for UDSM
-   end for;
-end CFG_sff1_x4_UDSM;
-
-
------ CELL sff2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity sff2_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdck_q_R                      :	Time := 0.500 ns;
-      tpdck_q_F                      :	Time := 0.500 ns;
-      tsui0_ck                       :	Time := 0.764 ns;
-      thck_i0                        :	Time := 0.000 ns;
-      tsui1_ck                       :	Time := 0.764 ns;
-      thck_i1                        :	Time := 0.000 ns;
-      tsucmd_ck                      :	Time := 0.833 ns;
-      thck_cmd                       :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns;
-      twdck_R                        :	Time := 0.000 ns;
-      twdck_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      cmd                            :	in    STD_LOGIC;
-      ck                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end sff2_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of sff2_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   signal n1, n2 : STD_LOGIC;
-
-   component MUX2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         S0                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-   component DFFLMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         D                              :  in    STD_LOGIC;
-         CLK                            :  in    STD_LOGIC;
-         CLR                            :  in    STD_LOGIC;
-         Q                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : MUX2MAC
-	port map( I0 => i0, I1 => i1, S0 => cmd, Y => n1);
-
-   U2 : DFFLMAC
-	generic map( tpdY_R => 2 ns, tpdY_F => 2 ns)
-	port map( D => n1, CLK => ck, CLR => n2, Q => q);
-
-   n2 <= '1';
-
-end UDSM;
-
-configuration CFG_sff2_x4_UDSM of sff2_x4 is
-   for UDSM
-   end for;
-end CFG_sff2_x4_UDSM;
-
-
------ CELL ts_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity ts_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd_q_R                     :	Time := 0.492 ns;
-      tpdcmd_q_F                     :	Time := 0.409 ns;
-      tpdcmd_q_LZ                    :	Time := 0.492 ns;
-      tpdcmd_q_HZ                    :	Time := 0.409 ns;
-      tpdi_q_R                       :	Time := 0.475 ns;
-      tpdi_q_F                       :	Time := 0.444 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      cmd                            :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end ts_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of ts_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component BUF3SHEMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         OE                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : BUF3SHEMAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i, OE => cmd, Y => q);
-
-
-end UDSM;
-
-configuration CFG_ts_x4_UDSM of ts_x4 is
-   for UDSM
-   end for;
-end CFG_ts_x4_UDSM;
-
-
------ CELL ts_x8 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity ts_x8 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdcmd_q_R                     :	Time := 0.626 ns;
-      tpdcmd_q_F                     :	Time := 0.466 ns;
-      tpdcmd_q_LZ                    :	Time := 0.626 ns;
-      tpdcmd_q_HZ                    :	Time := 0.466 ns;
-      tpdi_q_R                       :	Time := 0.613 ns;
-      tpdi_q_F                       :	Time := 0.569 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns);
-
-   port(
-      i                              :	in    STD_LOGIC;
-      cmd                            :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end ts_x8;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of ts_x8 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component BUF3SHEMAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         OE                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : BUF3SHEMAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i, OE => cmd, Y => q);
-
-
-end UDSM;
-
-configuration CFG_ts_x8_UDSM of ts_x8 is
-   for UDSM
-   end for;
-end CFG_ts_x8_UDSM;
-
-
------ CELL xr2_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity xr2_x1 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.292 ns;
-      tpdi0_q_F                      :	Time := 0.293 ns;
-      tpdi1_q_R                      :	Time := 0.377 ns;
-      tpdi1_q_F                      :	Time := 0.261 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end xr2_x1;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of xr2_x1 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component XOR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : XOR2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i1, I1 => i0, Y => q);
-
-
-end UDSM;
-
-configuration CFG_xr2_x1_UDSM of xr2_x1 is
-   for UDSM
-   end for;
-end CFG_xr2_x1_UDSM;
-
-
------ CELL xr2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity xr2_x4 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False;
-      tpdi0_q_R                      :	Time := 0.521 ns;
-      tpdi0_q_F                      :	Time := 0.560 ns;
-      tpdi1_q_R                      :	Time := 0.541 ns;
-      tpdi1_q_F                      :	Time := 0.657 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end xr2_x4;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of xr2_x4 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-   component XOR2MAC
-      generic(
-         tpdY_R                         :  Time := 0 ns;
-         tpdY_F                         :  Time := 0 ns;
-         strn                           :  STRENGTH := strn_X01);
-      port(
-         I0                             :  in    STD_LOGIC;
-         I1                             :  in    STD_LOGIC;
-         Y                              :  out   STD_LOGIC);
-   end component;
-
-begin
-
-   -- Netlist
-   U1 : XOR2MAC
-	generic map( tpdY_R => 1 ns, tpdY_F => 1 ns)
-	port map( I0 => i1, I1 => i0, Y => q);
-
-
-end UDSM;
-
-configuration CFG_xr2_x4_UDSM of xr2_x4 is
-   for UDSM
-   end for;
-end CFG_xr2_x4_UDSM;
-
-
------ CELL zero_x0 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library SYNOPSYS;
-use SYNOPSYS.attributes.REAL_NAME;
-
--- entity declaration --
-entity zero_x0 is
-   generic(
-      Timing_mesg: Boolean := True;
-      Timing_xgen: Boolean := False);
-
-   port(
-      nq                             :	out   STD_LOGIC := '0');
-end zero_x0;
-
--- architecture body --
-library IEEE_ASIC;
-use IEEE.STD_LOGIC_MISC.all;
-use SYNOPSYS.attributes.backplane;
-use SYNOPSYS.attributes.PRIVATE;
-use SYNOPSYS.attributes.ASIC_CELL;
-
-architecture UDSM of zero_x0 is
-   attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP;
-   attribute PRIVATE of UDSM : architecture is TRUE;
-   attribute ASIC_CELL of UDSM : architecture is TRUE;
-
-begin
-
-   -- Netlist
-   nq <= '0';
-
-end UDSM;
-
-configuration CFG_zero_x0_UDSM of zero_x0 is
-   for UDSM
-   end for;
-end CFG_zero_x0_UDSM;
-
-
----- end of library ----
diff --git a/alliance/share/cells/sxlib/sxlib_VITAL.vhd b/alliance/share/cells/sxlib/sxlib_VITAL.vhd
deleted file mode 100644
index c6203b0b..00000000
--- a/alliance/share/cells/sxlib/sxlib_VITAL.vhd
+++ /dev/null
@@ -1,8941 +0,0 @@
-
-----------------------------------------------------------------
--- 
--- Created by the Synopsys Library Compiler 1999.10
--- FILENAME     :    sxlib_VITAL.vhd
--- FILE CONTENTS:    Entity, Structural Architecture(VITAL),
---                   and Configuration
--- DATE CREATED :    Mon May  7 10:19:50 2001
--- 
--- LIBRARY      :    sxlib
--- DATE ENTERED :    Thu Dec 21 11:24:55 MET 2000
--- REVISION     :    1.200000
--- TECHNOLOGY   :    cmos
--- TIME SCALE   :    1 ns
--- LOGIC SYSTEM :    IEEE-1164
--- NOTES        :    VITAL, TimingChecksOn(TRUE), XGenerationOn(FALSE), TimingMessage(TRUE), OnDetect 
--- HISTORY      :
--- 
-----------------------------------------------------------------
-
------ CELL a2_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity a2_x2 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_q                       :	VitalDelayType01 := (0.261 ns, 0.388 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.203 ns, 0.434 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of a2_x2 : entity is TRUE;
-end a2_x2;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of a2_x2 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := (i1_ipd) AND (i0_ipd);
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_a2_x2_VITAL of a2_x2 is
-   for VITAL
-   end for;
-end CFG_a2_x2_VITAL;
-
-
------ CELL a2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity a2_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_q                       :	VitalDelayType01 := (0.338 ns, 0.476 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.269 ns, 0.518 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of a2_x4 : entity is TRUE;
-end a2_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of a2_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := (i1_ipd) AND (i0_ipd);
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_a2_x4_VITAL of a2_x4 is
-   for VITAL
-   end for;
-end CFG_a2_x4_VITAL;
-
-
------ CELL a3_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity a3_x2 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_q                       :	VitalDelayType01 := (0.395 ns, 0.435 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.353 ns, 0.479 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.290 ns, 0.521 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of a3_x2 : entity is TRUE;
-end a3_x2;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of a3_x2 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := (i1_ipd) AND (i0_ipd) AND (i2_ipd);
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_q, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_a3_x2_VITAL of a3_x2 is
-   for VITAL
-   end for;
-end CFG_a3_x2_VITAL;
-
-
------ CELL a3_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity a3_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_q                       :	VitalDelayType01 := (0.478 ns, 0.514 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.428 ns, 0.554 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.356 ns, 0.592 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of a3_x4 : entity is TRUE;
-end a3_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of a3_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := (i1_ipd) AND (i0_ipd) AND (i2_ipd);
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_q, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_a3_x4_VITAL of a3_x4 is
-   for VITAL
-   end for;
-end CFG_a3_x4_VITAL;
-
-
------ CELL a4_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity a4_x2 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_q                       :	VitalDelayType01 := (0.374 ns, 0.578 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.441 ns, 0.539 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.482 ns, 0.498 ns);
-      tpd_i3_q                       :	VitalDelayType01 := (0.506 ns, 0.455 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of a4_x2 : entity is TRUE;
-end a4_x2;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of a4_x2 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i3_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   VitalWireDelay (i3_ipd, i3, tipd_i3);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := (i1_ipd) AND (i0_ipd) AND (i2_ipd) AND (i3_ipd);
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_q, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_q, TRUE),
-                 3 => (i3_ipd'last_event, tpd_i3_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_a4_x2_VITAL of a4_x2 is
-   for VITAL
-   end for;
-end CFG_a4_x2_VITAL;
-
-
------ CELL a4_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity a4_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_q                       :	VitalDelayType01 := (0.505 ns, 0.650 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.578 ns, 0.614 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.627 ns, 0.576 ns);
-      tpd_i3_q                       :	VitalDelayType01 := (0.661 ns, 0.538 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of a4_x4 : entity is TRUE;
-end a4_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of a4_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i3_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   VitalWireDelay (i3_ipd, i3, tipd_i3);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := (i1_ipd) AND (i0_ipd) AND (i2_ipd) AND (i3_ipd);
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_q, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_q, TRUE),
-                 3 => (i3_ipd'last_event, tpd_i3_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_a4_x4_VITAL of a4_x4 is
-   for VITAL
-   end for;
-end CFG_a4_x4_VITAL;
-
-
------ CELL an12_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity an12_x1 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_q                       :	VitalDelayType01 := (0.200 ns, 0.168 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.285 ns, 0.405 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of an12_x1 : entity is TRUE;
-end an12_x1;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of an12_x1 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := (i1_ipd) AND ((NOT i0_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_an12_x1_VITAL of an12_x1 is
-   for VITAL
-   end for;
-end CFG_an12_x1_VITAL;
-
-
------ CELL an12_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity an12_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_q                       :	VitalDelayType01 := (0.461 ns, 0.471 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.269 ns, 0.518 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of an12_x4 : entity is TRUE;
-end an12_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of an12_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := (i1_ipd) AND ((NOT i0_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_an12_x4_VITAL of an12_x4 is
-   for VITAL
-   end for;
-end CFG_an12_x4_VITAL;
-
-
------ CELL ao2o22_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity ao2o22_x2 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_q                       :	VitalDelayType01 := (0.572 ns, 0.451 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.508 ns, 0.542 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.432 ns, 0.627 ns);
-      tpd_i3_q                       :	VitalDelayType01 := (0.488 ns, 0.526 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of ao2o22_x2 : entity is TRUE;
-end ao2o22_x2;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of ao2o22_x2 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i3_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   VitalWireDelay (i3_ipd, i3, tipd_i3);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := ((i3_ipd) OR (i2_ipd)) AND ((i1_ipd) OR (i0_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_q, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_q, TRUE),
-                 3 => (i3_ipd'last_event, tpd_i3_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_ao2o22_x2_VITAL of ao2o22_x2 is
-   for VITAL
-   end for;
-end CFG_ao2o22_x2_VITAL;
-
-
------ CELL ao2o22_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity ao2o22_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_q                       :	VitalDelayType01 := (0.696 ns, 0.569 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.637 ns, 0.666 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.554 ns, 0.744 ns);
-      tpd_i3_q                       :	VitalDelayType01 := (0.606 ns, 0.639 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of ao2o22_x4 : entity is TRUE;
-end ao2o22_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of ao2o22_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i3_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   VitalWireDelay (i3_ipd, i3, tipd_i3);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := ((i3_ipd) OR (i2_ipd)) AND ((i1_ipd) OR (i0_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_q, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_q, TRUE),
-                 3 => (i3_ipd'last_event, tpd_i3_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_ao2o22_x4_VITAL of ao2o22_x4 is
-   for VITAL
-   end for;
-end CFG_ao2o22_x4_VITAL;
-
-
------ CELL ao22_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity ao22_x2 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_q                       :	VitalDelayType01 := (0.558 ns, 0.447 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.493 ns, 0.526 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.420 ns, 0.425 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of ao22_x2 : entity is TRUE;
-end ao22_x2;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of ao22_x2 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := (i2_ipd) AND ((i1_ipd) OR (i0_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_q, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_ao22_x2_VITAL of ao22_x2 is
-   for VITAL
-   end for;
-end CFG_ao22_x2_VITAL;
-
-
------ CELL ao22_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity ao22_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_q                       :	VitalDelayType01 := (0.674 ns, 0.552 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.615 ns, 0.647 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.526 ns, 0.505 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of ao22_x4 : entity is TRUE;
-end ao22_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of ao22_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := (i2_ipd) AND ((i1_ipd) OR (i0_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_q, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_ao22_x4_VITAL of ao22_x4 is
-   for VITAL
-   end for;
-end CFG_ao22_x4_VITAL;
-
-
------ CELL buf_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity buf_x2 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i_q                        :	VitalDelayType01 := (0.409 ns, 0.391 ns);
-      tipd_i                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i                              :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of buf_x2 : entity is TRUE;
-end buf_x2;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of buf_x2 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i_ipd, i, tipd_i);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := TO_X01(i_ipd);
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i_ipd'last_event, tpd_i_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_buf_x2_VITAL of buf_x2 is
-   for VITAL
-   end for;
-end CFG_buf_x2_VITAL;
-
-
------ CELL buf_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity buf_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i_q                        :	VitalDelayType01 := (0.379 ns, 0.409 ns);
-      tipd_i                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i                              :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of buf_x4 : entity is TRUE;
-end buf_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of buf_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i_ipd, i, tipd_i);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := TO_X01(i_ipd);
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i_ipd'last_event, tpd_i_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_buf_x4_VITAL of buf_x4 is
-   for VITAL
-   end for;
-end CFG_buf_x4_VITAL;
-
-
------ CELL buf_x8 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity buf_x8 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i_q                        :	VitalDelayType01 := (0.343 ns, 0.396 ns);
-      tipd_i                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i                              :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of buf_x8 : entity is TRUE;
-end buf_x8;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of buf_x8 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i_ipd, i, tipd_i);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := TO_X01(i_ipd);
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i_ipd'last_event, tpd_i_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_buf_x8_VITAL of buf_x8 is
-   for VITAL
-   end for;
-end CFG_buf_x8_VITAL;
-
-
------ CELL inv_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity inv_x1 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i_nq                       :	VitalDelayType01 := (0.101 ns, 0.139 ns);
-      tipd_i                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i                              :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of inv_x1 : entity is TRUE;
-end inv_x1;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of inv_x1 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i_ipd, i, tipd_i);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd := (NOT i_ipd);
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (i_ipd'last_event, tpd_i_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_inv_x1_VITAL of inv_x1 is
-   for VITAL
-   end for;
-end CFG_inv_x1_VITAL;
-
-
------ CELL inv_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity inv_x2 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i_nq                       :	VitalDelayType01 := (0.069 ns, 0.163 ns);
-      tipd_i                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i                              :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of inv_x2 : entity is TRUE;
-end inv_x2;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of inv_x2 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i_ipd, i, tipd_i);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd := (NOT i_ipd);
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (i_ipd'last_event, tpd_i_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_inv_x2_VITAL of inv_x2 is
-   for VITAL
-   end for;
-end CFG_inv_x2_VITAL;
-
-
------ CELL inv_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity inv_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i_nq                       :	VitalDelayType01 := (0.071 ns, 0.143 ns);
-      tipd_i                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i                              :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of inv_x4 : entity is TRUE;
-end inv_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of inv_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i_ipd, i, tipd_i);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd := (NOT i_ipd);
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (i_ipd'last_event, tpd_i_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_inv_x4_VITAL of inv_x4 is
-   for VITAL
-   end for;
-end CFG_inv_x4_VITAL;
-
-
------ CELL inv_x8 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity inv_x8 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i_nq                       :	VitalDelayType01 := (0.086 ns, 0.133 ns);
-      tipd_i                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i                              :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of inv_x8 : entity is TRUE;
-end inv_x8;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of inv_x8 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i_ipd, i, tipd_i);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd := (NOT i_ipd);
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (i_ipd'last_event, tpd_i_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_inv_x8_VITAL of inv_x8 is
-   for VITAL
-   end for;
-end CFG_inv_x8_VITAL;
-
-
------ CELL mx2_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity mx2_x2 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_cmd_q                      :	VitalDelayType01 := (0.484 ns, 0.522 ns);
-      tpd_i0_q                       :	VitalDelayType01 := (0.451 ns, 0.469 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.451 ns, 0.469 ns);
-      tipd_cmd                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      cmd                            :	in    STD_ULOGIC;
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of mx2_x2 : entity is TRUE;
-end mx2_x2;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of mx2_x2 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL cmd_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (cmd_ipd, cmd, tipd_cmd);
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (cmd_ipd, i0_ipd, i1_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := VitalMUX
-                 (data => (i1_ipd, i0_ipd),
-                  dselect => (0 => cmd_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (cmd_ipd'last_event, tpd_cmd_q, TRUE),
-                 1 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 2 => (i1_ipd'last_event, tpd_i1_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_mx2_x2_VITAL of mx2_x2 is
-   for VITAL
-   end for;
-end CFG_mx2_x2_VITAL;
-
-
------ CELL mx2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity mx2_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_cmd_q                      :	VitalDelayType01 := (0.615 ns, 0.647 ns);
-      tpd_i0_q                       :	VitalDelayType01 := (0.564 ns, 0.576 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.564 ns, 0.576 ns);
-      tipd_cmd                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      cmd                            :	in    STD_ULOGIC;
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of mx2_x4 : entity is TRUE;
-end mx2_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of mx2_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL cmd_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (cmd_ipd, cmd, tipd_cmd);
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (cmd_ipd, i0_ipd, i1_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := VitalMUX
-                 (data => (i1_ipd, i0_ipd),
-                  dselect => (0 => cmd_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (cmd_ipd'last_event, tpd_cmd_q, TRUE),
-                 1 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 2 => (i1_ipd'last_event, tpd_i1_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_mx2_x4_VITAL of mx2_x4 is
-   for VITAL
-   end for;
-end CFG_mx2_x4_VITAL;
-
-
------ CELL mx3_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity mx3_x2 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_cmd0_q                     :	VitalDelayType01 := (0.573 ns, 0.680 ns);
-      tpd_cmd1_q                     :	VitalDelayType01 := (0.664 ns, 0.817 ns);
-      tpd_i0_q                       :	VitalDelayType01 := (0.538 ns, 0.658 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.654 ns, 0.808 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.654 ns, 0.808 ns);
-      tipd_cmd0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_cmd1                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      cmd0                           :	in    STD_ULOGIC;
-      cmd1                           :	in    STD_ULOGIC;
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of mx3_x2 : entity is TRUE;
-end mx3_x2;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of mx3_x2 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL cmd0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL cmd1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (cmd0_ipd, cmd0, tipd_cmd0);
-   VitalWireDelay (cmd1_ipd, cmd1, tipd_cmd1);
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (cmd0_ipd, cmd1_ipd, i0_ipd, i1_ipd, i2_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := VitalMUX
-                 (data => (i1_ipd, i2_ipd, i0_ipd, i0_ipd),
-                  dselect => (cmd0_ipd, cmd1_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (cmd0_ipd'last_event, tpd_cmd0_q, TRUE),
-                 1 => (cmd1_ipd'last_event, tpd_cmd1_q, TRUE),
-                 2 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 3 => (i1_ipd'last_event, tpd_i1_q, TRUE),
-                 4 => (i2_ipd'last_event, tpd_i2_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_mx3_x2_VITAL of mx3_x2 is
-   for VITAL
-   end for;
-end CFG_mx3_x2_VITAL;
-
-
------ CELL mx3_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity mx3_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_cmd0_q                     :	VitalDelayType01 := (0.683 ns, 0.779 ns);
-      tpd_cmd1_q                     :	VitalDelayType01 := (0.792 ns, 0.967 ns);
-      tpd_i0_q                       :	VitalDelayType01 := (0.640 ns, 0.774 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.770 ns, 0.948 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.770 ns, 0.948 ns);
-      tipd_cmd0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_cmd1                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      cmd0                           :	in    STD_ULOGIC;
-      cmd1                           :	in    STD_ULOGIC;
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of mx3_x4 : entity is TRUE;
-end mx3_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of mx3_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL cmd0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL cmd1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (cmd0_ipd, cmd0, tipd_cmd0);
-   VitalWireDelay (cmd1_ipd, cmd1, tipd_cmd1);
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (cmd0_ipd, cmd1_ipd, i0_ipd, i1_ipd, i2_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := VitalMUX
-                 (data => (i1_ipd, i2_ipd, i0_ipd, i0_ipd),
-                  dselect => (cmd0_ipd, cmd1_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (cmd0_ipd'last_event, tpd_cmd0_q, TRUE),
-                 1 => (cmd1_ipd'last_event, tpd_cmd1_q, TRUE),
-                 2 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 3 => (i1_ipd'last_event, tpd_i1_q, TRUE),
-                 4 => (i2_ipd'last_event, tpd_i2_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_mx3_x4_VITAL of mx3_x4 is
-   for VITAL
-   end for;
-end CFG_mx3_x4_VITAL;
-
-
------ CELL na2_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity na2_x1 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.059 ns, 0.288 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.111 ns, 0.234 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of na2_x1 : entity is TRUE;
-end na2_x1;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of na2_x1 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd := ((NOT i1_ipd)) OR ((NOT i0_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_na2_x1_VITAL of na2_x1 is
-   for VITAL
-   end for;
-end CFG_na2_x1_VITAL;
-
-
------ CELL na2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity na2_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.412 ns, 0.552 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.353 ns, 0.601 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of na2_x4 : entity is TRUE;
-end na2_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of na2_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd := ((NOT i1_ipd)) OR ((NOT i0_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_na2_x4_VITAL of na2_x4 is
-   for VITAL
-   end for;
-end CFG_na2_x4_VITAL;
-
-
------ CELL na3_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity na3_x1 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.119 ns, 0.363 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.171 ns, 0.316 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.193 ns, 0.265 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of na3_x1 : entity is TRUE;
-end na3_x1;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of na3_x1 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd := ((NOT i1_ipd)) OR ((NOT i0_ipd)) OR ((NOT i2_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_na3_x1_VITAL of na3_x1 is
-   for VITAL
-   end for;
-end CFG_na3_x1_VITAL;
-
-
------ CELL na3_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity na3_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.556 ns, 0.601 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.460 ns, 0.691 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.519 ns, 0.647 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of na3_x4 : entity is TRUE;
-end na3_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of na3_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd := ((NOT i1_ipd)) OR ((NOT i0_ipd)) OR ((NOT i2_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_na3_x4_VITAL of na3_x4 is
-   for VITAL
-   end for;
-end CFG_na3_x4_VITAL;
-
-
------ CELL na4_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity na4_x1 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.179 ns, 0.438 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.237 ns, 0.395 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.269 ns, 0.350 ns);
-      tpd_i3_nq                      :	VitalDelayType01 := (0.282 ns, 0.302 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of na4_x1 : entity is TRUE;
-end na4_x1;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of na4_x1 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i3_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   VitalWireDelay (i3_ipd, i3, tipd_i3);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd :=
-       ((NOT i1_ipd)) OR ((NOT i0_ipd)) OR ((NOT i2_ipd)) OR ((NOT i3_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE),
-                 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_na4_x1_VITAL of na4_x1 is
-   for VITAL
-   end for;
-end CFG_na4_x1_VITAL;
-
-
------ CELL na4_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity na4_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.578 ns, 0.771 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.643 ns, 0.731 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.681 ns, 0.689 ns);
-      tpd_i3_nq                      :	VitalDelayType01 := (0.703 ns, 0.644 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of na4_x4 : entity is TRUE;
-end na4_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of na4_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i3_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   VitalWireDelay (i3_ipd, i3, tipd_i3);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd :=
-       ((NOT i1_ipd)) OR ((NOT i0_ipd)) OR ((NOT i2_ipd)) OR ((NOT i3_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE),
-                 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_na4_x4_VITAL of na4_x4 is
-   for VITAL
-   end for;
-end CFG_na4_x4_VITAL;
-
-
------ CELL nao2o22_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity nao2o22_x1 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.294 ns, 0.226 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.218 ns, 0.287 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.237 ns, 0.307 ns);
-      tpd_i3_nq                      :	VitalDelayType01 := (0.174 ns, 0.382 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of nao2o22_x1 : entity is TRUE;
-end nao2o22_x1;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of nao2o22_x1 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i3_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   VitalWireDelay (i3_ipd, i3, tipd_i3);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd :=
-       (((NOT i3_ipd)) AND ((NOT i2_ipd))) OR (((NOT i1_ipd)) AND ((NOT
-         i0_ipd)));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE),
-                 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_nao2o22_x1_VITAL of nao2o22_x1 is
-   for VITAL
-   end for;
-end CFG_nao2o22_x1_VITAL;
-
-
------ CELL nao2o22_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity nao2o22_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.734 ns, 0.644 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.666 ns, 0.717 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.664 ns, 0.721 ns);
-      tpd_i3_nq                      :	VitalDelayType01 := (0.607 ns, 0.807 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of nao2o22_x4 : entity is TRUE;
-end nao2o22_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of nao2o22_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i3_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   VitalWireDelay (i3_ipd, i3, tipd_i3);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd :=
-       (((NOT i3_ipd)) AND ((NOT i2_ipd))) OR (((NOT i1_ipd)) AND ((NOT
-         i0_ipd)));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE),
-                 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_nao2o22_x4_VITAL of nao2o22_x4 is
-   for VITAL
-   end for;
-end CFG_nao2o22_x4_VITAL;
-
-
------ CELL nao22_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity nao22_x1 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.294 ns, 0.226 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.218 ns, 0.287 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.165 ns, 0.238 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of nao22_x1 : entity is TRUE;
-end nao22_x1;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of nao22_x1 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd := ((NOT i2_ipd)) OR (((NOT i1_ipd)) AND ((NOT i0_ipd)));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_nao22_x1_VITAL of nao22_x1 is
-   for VITAL
-   end for;
-end CFG_nao22_x1_VITAL;
-
-
------ CELL nao22_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity nao22_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.732 ns, 0.650 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.664 ns, 0.723 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.596 ns, 0.636 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of nao22_x4 : entity is TRUE;
-end nao22_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of nao22_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd := ((NOT i2_ipd)) OR (((NOT i1_ipd)) AND ((NOT i0_ipd)));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_nao22_x4_VITAL of nao22_x4 is
-   for VITAL
-   end for;
-end CFG_nao22_x4_VITAL;
-
-
------ CELL nmx2_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity nmx2_x1 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_cmd_nq                     :	VitalDelayType01 := (0.218 ns, 0.287 ns);
-      tpd_i0_nq                      :	VitalDelayType01 := (0.217 ns, 0.256 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.217 ns, 0.256 ns);
-      tipd_cmd                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      cmd                            :	in    STD_ULOGIC;
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of nmx2_x1 : entity is TRUE;
-end nmx2_x1;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of nmx2_x1 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL cmd_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (cmd_ipd, cmd, tipd_cmd);
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (cmd_ipd, i0_ipd, i1_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd := VitalMUX
-                 (data => (i1_ipd, i0_ipd),
-                  dselect => (0 => cmd_ipd));
-      nq_zd := NOT nq_zd;
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (cmd_ipd'last_event, tpd_cmd_nq, TRUE),
-                 1 => (i0_ipd'last_event, tpd_i0_nq, TRUE),
-                 2 => (i1_ipd'last_event, tpd_i1_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_nmx2_x1_VITAL of nmx2_x1 is
-   for VITAL
-   end for;
-end CFG_nmx2_x1_VITAL;
-
-
------ CELL nmx2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity nmx2_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_cmd_nq                     :	VitalDelayType01 := (0.632 ns, 0.708 ns);
-      tpd_i0_nq                      :	VitalDelayType01 := (0.610 ns, 0.653 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.610 ns, 0.653 ns);
-      tipd_cmd                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      cmd                            :	in    STD_ULOGIC;
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of nmx2_x4 : entity is TRUE;
-end nmx2_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of nmx2_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL cmd_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (cmd_ipd, cmd, tipd_cmd);
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (cmd_ipd, i0_ipd, i1_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd := VitalMUX
-                 (data => (i1_ipd, i0_ipd),
-                  dselect => (0 => cmd_ipd));
-      nq_zd := NOT nq_zd;
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (cmd_ipd'last_event, tpd_cmd_nq, TRUE),
-                 1 => (i0_ipd'last_event, tpd_i0_nq, TRUE),
-                 2 => (i1_ipd'last_event, tpd_i1_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_nmx2_x4_VITAL of nmx2_x4 is
-   for VITAL
-   end for;
-end CFG_nmx2_x4_VITAL;
-
-
------ CELL nmx3_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity nmx3_x1 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_cmd0_nq                    :	VitalDelayType01 := (0.356 ns, 0.495 ns);
-      tpd_cmd1_nq                    :	VitalDelayType01 := (0.414 ns, 0.566 ns);
-      tpd_i0_nq                      :	VitalDelayType01 := (0.315 ns, 0.441 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.429 ns, 0.582 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.429 ns, 0.582 ns);
-      tipd_cmd0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_cmd1                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      cmd0                           :	in    STD_ULOGIC;
-      cmd1                           :	in    STD_ULOGIC;
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of nmx3_x1 : entity is TRUE;
-end nmx3_x1;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of nmx3_x1 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL cmd0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL cmd1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (cmd0_ipd, cmd0, tipd_cmd0);
-   VitalWireDelay (cmd1_ipd, cmd1, tipd_cmd1);
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (cmd0_ipd, cmd1_ipd, i0_ipd, i1_ipd, i2_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd := VitalMUX
-                 (data => (i1_ipd, i2_ipd, i0_ipd, i0_ipd),
-                  dselect => (cmd0_ipd, cmd1_ipd));
-      nq_zd := NOT nq_zd;
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (cmd0_ipd'last_event, tpd_cmd0_nq, TRUE),
-                 1 => (cmd1_ipd'last_event, tpd_cmd1_nq, TRUE),
-                 2 => (i0_ipd'last_event, tpd_i0_nq, TRUE),
-                 3 => (i1_ipd'last_event, tpd_i1_nq, TRUE),
-                 4 => (i2_ipd'last_event, tpd_i2_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_nmx3_x1_VITAL of nmx3_x1 is
-   for VITAL
-   end for;
-end CFG_nmx3_x1_VITAL;
-
-
------ CELL nmx3_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity nmx3_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_cmd0_nq                    :	VitalDelayType01 := (0.790 ns, 0.936 ns);
-      tpd_cmd1_nq                    :	VitalDelayType01 := (0.866 ns, 1.048 ns);
-      tpd_i0_nq                      :	VitalDelayType01 := (0.748 ns, 0.900 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.869 ns, 1.053 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.869 ns, 1.053 ns);
-      tipd_cmd0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_cmd1                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      cmd0                           :	in    STD_ULOGIC;
-      cmd1                           :	in    STD_ULOGIC;
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of nmx3_x4 : entity is TRUE;
-end nmx3_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of nmx3_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL cmd0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL cmd1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (cmd0_ipd, cmd0, tipd_cmd0);
-   VitalWireDelay (cmd1_ipd, cmd1, tipd_cmd1);
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (cmd0_ipd, cmd1_ipd, i0_ipd, i1_ipd, i2_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd := VitalMUX
-                 (data => (i1_ipd, i2_ipd, i0_ipd, i0_ipd),
-                  dselect => (cmd0_ipd, cmd1_ipd));
-      nq_zd := NOT nq_zd;
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (cmd0_ipd'last_event, tpd_cmd0_nq, TRUE),
-                 1 => (cmd1_ipd'last_event, tpd_cmd1_nq, TRUE),
-                 2 => (i0_ipd'last_event, tpd_i0_nq, TRUE),
-                 3 => (i1_ipd'last_event, tpd_i1_nq, TRUE),
-                 4 => (i2_ipd'last_event, tpd_i2_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_nmx3_x4_VITAL of nmx3_x4 is
-   for VITAL
-   end for;
-end CFG_nmx3_x4_VITAL;
-
-
------ CELL no2_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity no2_x1 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.298 ns, 0.121 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.193 ns, 0.161 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of no2_x1 : entity is TRUE;
-end no2_x1;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of no2_x1 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd := ((NOT i1_ipd)) AND ((NOT i0_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_no2_x1_VITAL of no2_x1 is
-   for VITAL
-   end for;
-end CFG_no2_x1_VITAL;
-
-
------ CELL no2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity no2_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.618 ns, 0.447 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.522 ns, 0.504 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of no2_x4 : entity is TRUE;
-end no2_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of no2_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd := ((NOT i1_ipd)) AND ((NOT i0_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_no2_x4_VITAL of no2_x4 is
-   for VITAL
-   end for;
-end CFG_no2_x4_VITAL;
-
-
------ CELL no3_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity no3_x1 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.318 ns, 0.246 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.215 ns, 0.243 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.407 ns, 0.192 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of no3_x1 : entity is TRUE;
-end no3_x1;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of no3_x1 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd := ((NOT i1_ipd)) AND ((NOT i0_ipd)) AND ((NOT i2_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_no3_x1_VITAL of no3_x1 is
-   for VITAL
-   end for;
-end CFG_no3_x1_VITAL;
-
-
------ CELL no3_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity no3_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.722 ns, 0.561 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.638 ns, 0.623 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.545 ns, 0.640 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of no3_x4 : entity is TRUE;
-end no3_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of no3_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd := ((NOT i1_ipd)) AND ((NOT i0_ipd)) AND ((NOT i2_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_no3_x4_VITAL of no3_x4 is
-   for VITAL
-   end for;
-end CFG_no3_x4_VITAL;
-
-
------ CELL no4_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity no4_x1 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.330 ns, 0.340 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.230 ns, 0.320 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.419 ns, 0.333 ns);
-      tpd_i3_nq                      :	VitalDelayType01 := (0.499 ns, 0.271 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of no4_x1 : entity is TRUE;
-end no4_x1;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of no4_x1 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i3_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   VitalWireDelay (i3_ipd, i3, tipd_i3);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd :=
-       ((NOT i1_ipd)) AND ((NOT i0_ipd)) AND ((NOT i2_ipd)) AND ((NOT
-         i3_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE),
-                 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_no4_x1_VITAL of no4_x1 is
-   for VITAL
-   end for;
-end CFG_no4_x1_VITAL;
-
-
------ CELL no4_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity no4_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.656 ns, 0.777 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.564 ns, 0.768 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.739 ns, 0.761 ns);
-      tpd_i3_nq                      :	VitalDelayType01 := (0.816 ns, 0.693 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of no4_x4 : entity is TRUE;
-end no4_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of no4_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i3_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   VitalWireDelay (i3_ipd, i3, tipd_i3);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd :=
-       ((NOT i1_ipd)) AND ((NOT i0_ipd)) AND ((NOT i2_ipd)) AND ((NOT
-         i3_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE),
-                 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_no4_x4_VITAL of no4_x4 is
-   for VITAL
-   end for;
-end CFG_no4_x4_VITAL;
-
-
------ CELL noa2a2a2a24_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity noa2a2a2a24_x1 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.649 ns, 0.606 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.775 ns, 0.562 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.550 ns, 0.662 ns);
-      tpd_i3_nq                      :	VitalDelayType01 := (0.667 ns, 0.616 ns);
-      tpd_i4_nq                      :	VitalDelayType01 := (0.419 ns, 0.613 ns);
-      tpd_i5_nq                      :	VitalDelayType01 := (0.329 ns, 0.662 ns);
-      tpd_i6_nq                      :	VitalDelayType01 := (0.270 ns, 0.535 ns);
-      tpd_i7_nq                      :	VitalDelayType01 := (0.200 ns, 0.591 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      i4                             :	in    STD_ULOGIC;
-      i5                             :	in    STD_ULOGIC;
-      i6                             :	in    STD_ULOGIC;
-      i7                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of noa2a2a2a24_x1 : entity is TRUE;
-end noa2a2a2a24_x1;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of noa2a2a2a24_x1 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i3_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i4_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i5_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i6_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i7_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   VitalWireDelay (i3_ipd, i3, tipd_i3);
-   VitalWireDelay (i4_ipd, i4, tipd_i4);
-   VitalWireDelay (i5_ipd, i5, tipd_i5);
-   VitalWireDelay (i6_ipd, i6, tipd_i6);
-   VitalWireDelay (i7_ipd, i7, tipd_i7);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd, i6_ipd, i7_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd :=
-       (((NOT i3_ipd)) OR ((NOT i2_ipd))) AND (((NOT i1_ipd)) OR ((NOT
-         i0_ipd))) AND (((NOT i5_ipd)) OR ((NOT i4_ipd))) AND (((NOT i7_ipd))
-         OR ((NOT i6_ipd)));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE),
-                 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE),
-                 4 => (i4_ipd'last_event, tpd_i4_nq, TRUE),
-                 5 => (i5_ipd'last_event, tpd_i5_nq, TRUE),
-                 6 => (i6_ipd'last_event, tpd_i6_nq, TRUE),
-                 7 => (i7_ipd'last_event, tpd_i7_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_noa2a2a2a24_x1_VITAL of noa2a2a2a24_x1 is
-   for VITAL
-   end for;
-end CFG_noa2a2a2a24_x1_VITAL;
-
-
------ CELL noa2a2a2a24_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity noa2a2a2a24_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.966 ns, 1.049 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (1.097 ns, 1.005 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.867 ns, 1.106 ns);
-      tpd_i3_nq                      :	VitalDelayType01 := (0.990 ns, 1.061 ns);
-      tpd_i4_nq                      :	VitalDelayType01 := (0.748 ns, 1.061 ns);
-      tpd_i5_nq                      :	VitalDelayType01 := (0.649 ns, 1.109 ns);
-      tpd_i6_nq                      :	VitalDelayType01 := (0.606 ns, 0.999 ns);
-      tpd_i7_nq                      :	VitalDelayType01 := (0.525 ns, 1.052 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      i4                             :	in    STD_ULOGIC;
-      i5                             :	in    STD_ULOGIC;
-      i6                             :	in    STD_ULOGIC;
-      i7                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of noa2a2a2a24_x4 : entity is TRUE;
-end noa2a2a2a24_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of noa2a2a2a24_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i3_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i4_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i5_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i6_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i7_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   VitalWireDelay (i3_ipd, i3, tipd_i3);
-   VitalWireDelay (i4_ipd, i4, tipd_i4);
-   VitalWireDelay (i5_ipd, i5, tipd_i5);
-   VitalWireDelay (i6_ipd, i6, tipd_i6);
-   VitalWireDelay (i7_ipd, i7, tipd_i7);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd, i6_ipd, i7_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd :=
-       (((NOT i3_ipd)) OR ((NOT i2_ipd))) AND (((NOT i1_ipd)) OR ((NOT
-         i0_ipd))) AND (((NOT i5_ipd)) OR ((NOT i4_ipd))) AND (((NOT i7_ipd))
-         OR ((NOT i6_ipd)));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE),
-                 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE),
-                 4 => (i4_ipd'last_event, tpd_i4_nq, TRUE),
-                 5 => (i5_ipd'last_event, tpd_i5_nq, TRUE),
-                 6 => (i6_ipd'last_event, tpd_i6_nq, TRUE),
-                 7 => (i7_ipd'last_event, tpd_i7_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_noa2a2a2a24_x4_VITAL of noa2a2a2a24_x4 is
-   for VITAL
-   end for;
-end CFG_noa2a2a2a24_x4_VITAL;
-
-
------ CELL noa2a2a23_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity noa2a2a23_x1 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.525 ns, 0.425 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.643 ns, 0.388 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.307 ns, 0.479 ns);
-      tpd_i3_nq                      :	VitalDelayType01 := (0.398 ns, 0.438 ns);
-      tpd_i4_nq                      :	VitalDelayType01 := (0.250 ns, 0.416 ns);
-      tpd_i5_nq                      :	VitalDelayType01 := (0.178 ns, 0.464 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      i4                             :	in    STD_ULOGIC;
-      i5                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of noa2a2a23_x1 : entity is TRUE;
-end noa2a2a23_x1;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of noa2a2a23_x1 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i3_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i4_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i5_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   VitalWireDelay (i3_ipd, i3, tipd_i3);
-   VitalWireDelay (i4_ipd, i4, tipd_i4);
-   VitalWireDelay (i5_ipd, i5, tipd_i5);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd :=
-       (((NOT i3_ipd)) OR ((NOT i2_ipd))) AND (((NOT i1_ipd)) OR ((NOT
-         i0_ipd))) AND (((NOT i5_ipd)) OR ((NOT i4_ipd)));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE),
-                 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE),
-                 4 => (i4_ipd'last_event, tpd_i4_nq, TRUE),
-                 5 => (i5_ipd'last_event, tpd_i5_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_noa2a2a23_x1_VITAL of noa2a2a23_x1 is
-   for VITAL
-   end for;
-end CFG_noa2a2a23_x1_VITAL;
-
-
------ CELL noa2a2a23_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity noa2a2a23_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.834 ns, 0.814 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.955 ns, 0.778 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.620 ns, 0.873 ns);
-      tpd_i3_nq                      :	VitalDelayType01 := (0.716 ns, 0.833 ns);
-      tpd_i4_nq                      :	VitalDelayType01 := (0.574 ns, 0.819 ns);
-      tpd_i5_nq                      :	VitalDelayType01 := (0.496 ns, 0.865 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      i4                             :	in    STD_ULOGIC;
-      i5                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of noa2a2a23_x4 : entity is TRUE;
-end noa2a2a23_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of noa2a2a23_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i3_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i4_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i5_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   VitalWireDelay (i3_ipd, i3, tipd_i3);
-   VitalWireDelay (i4_ipd, i4, tipd_i4);
-   VitalWireDelay (i5_ipd, i5, tipd_i5);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd :=
-       (((NOT i3_ipd)) OR ((NOT i2_ipd))) AND (((NOT i1_ipd)) OR ((NOT
-         i0_ipd))) AND (((NOT i5_ipd)) OR ((NOT i4_ipd)));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE),
-                 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE),
-                 4 => (i4_ipd'last_event, tpd_i4_nq, TRUE),
-                 5 => (i5_ipd'last_event, tpd_i5_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_noa2a2a23_x4_VITAL of noa2a2a23_x4 is
-   for VITAL
-   end for;
-end CFG_noa2a2a23_x4_VITAL;
-
-
------ CELL noa2a22_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity noa2a22_x1 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.151 ns, 0.327 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.218 ns, 0.287 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.284 ns, 0.289 ns);
-      tpd_i3_nq                      :	VitalDelayType01 := (0.372 ns, 0.256 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of noa2a22_x1 : entity is TRUE;
-end noa2a22_x1;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of noa2a22_x1 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i3_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   VitalWireDelay (i3_ipd, i3, tipd_i3);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd :=
-       (((NOT i3_ipd)) OR ((NOT i2_ipd))) AND (((NOT i1_ipd)) OR ((NOT
-         i0_ipd)));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE),
-                 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_noa2a22_x1_VITAL of noa2a22_x1 is
-   for VITAL
-   end for;
-end CFG_noa2a22_x1_VITAL;
-
-
------ CELL noa2a22_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity noa2a22_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.562 ns, 0.745 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.646 ns, 0.714 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.701 ns, 0.703 ns);
-      tpd_i3_nq                      :	VitalDelayType01 := (0.805 ns, 0.677 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of noa2a22_x4 : entity is TRUE;
-end noa2a22_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of noa2a22_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i3_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   VitalWireDelay (i3_ipd, i3, tipd_i3);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd :=
-       (((NOT i3_ipd)) OR ((NOT i2_ipd))) AND (((NOT i1_ipd)) OR ((NOT
-         i0_ipd)));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE),
-                 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_noa2a22_x4_VITAL of noa2a22_x4 is
-   for VITAL
-   end for;
-end CFG_noa2a22_x4_VITAL;
-
-
------ CELL noa2ao222_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity noa2ao222_x1 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.348 ns, 0.422 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.440 ns, 0.378 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.186 ns, 0.473 ns);
-      tpd_i3_nq                      :	VitalDelayType01 := (0.256 ns, 0.459 ns);
-      tpd_i4_nq                      :	VitalDelayType01 := (0.240 ns, 0.309 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      i4                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of noa2ao222_x1 : entity is TRUE;
-end noa2ao222_x1;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of noa2ao222_x1 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i3_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i4_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   VitalWireDelay (i3_ipd, i3, tipd_i3);
-   VitalWireDelay (i4_ipd, i4, tipd_i4);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd :=
-       (((NOT i4_ipd)) OR (((NOT i3_ipd)) AND ((NOT i2_ipd)))) AND (((NOT
-         i1_ipd)) OR ((NOT i0_ipd)));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE),
-                 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE),
-                 4 => (i4_ipd'last_event, tpd_i4_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_noa2ao222_x1_VITAL of noa2ao222_x1 is
-   for VITAL
-   end for;
-end CFG_noa2ao222_x1_VITAL;
-
-
------ CELL noa2ao222_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity noa2ao222_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.684 ns, 0.801 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.780 ns, 0.758 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.638 ns, 0.809 ns);
-      tpd_i3_nq                      :	VitalDelayType01 := (0.732 ns, 0.795 ns);
-      tpd_i4_nq                      :	VitalDelayType01 := (0.718 ns, 0.664 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      i4                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of noa2ao222_x4 : entity is TRUE;
-end noa2ao222_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of noa2ao222_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i3_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i4_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   VitalWireDelay (i3_ipd, i3, tipd_i3);
-   VitalWireDelay (i4_ipd, i4, tipd_i4);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd :=
-       (((NOT i4_ipd)) OR (((NOT i3_ipd)) AND ((NOT i2_ipd)))) AND (((NOT
-         i1_ipd)) OR ((NOT i0_ipd)));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE),
-                 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE),
-                 4 => (i4_ipd'last_event, tpd_i4_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_noa2ao222_x4_VITAL of noa2ao222_x4 is
-   for VITAL
-   end for;
-end CFG_noa2ao222_x4_VITAL;
-
-
------ CELL noa3ao322_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity noa3ao322_x1 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.396 ns, 0.616 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.486 ns, 0.552 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.546 ns, 0.488 ns);
-      tpd_i3_nq                      :	VitalDelayType01 := (0.196 ns, 0.599 ns);
-      tpd_i4_nq                      :	VitalDelayType01 := (0.264 ns, 0.608 ns);
-      tpd_i5_nq                      :	VitalDelayType01 := (0.328 ns, 0.581 ns);
-      tpd_i6_nq                      :	VitalDelayType01 := (0.246 ns, 0.311 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      i4                             :	in    STD_ULOGIC;
-      i5                             :	in    STD_ULOGIC;
-      i6                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of noa3ao322_x1 : entity is TRUE;
-end noa3ao322_x1;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of noa3ao322_x1 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i3_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i4_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i5_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i6_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   VitalWireDelay (i3_ipd, i3, tipd_i3);
-   VitalWireDelay (i4_ipd, i4, tipd_i4);
-   VitalWireDelay (i5_ipd, i5, tipd_i5);
-   VitalWireDelay (i6_ipd, i6, tipd_i6);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd, i6_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd :=
-       (((NOT i6_ipd)) OR (((NOT i4_ipd)) AND ((NOT i3_ipd)) AND ((NOT
-         i5_ipd)))) AND (((NOT i1_ipd)) OR ((NOT i0_ipd)) OR ((NOT i2_ipd)));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE),
-                 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE),
-                 4 => (i4_ipd'last_event, tpd_i4_nq, TRUE),
-                 5 => (i5_ipd'last_event, tpd_i5_nq, TRUE),
-                 6 => (i6_ipd'last_event, tpd_i6_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_noa3ao322_x1_VITAL of noa3ao322_x1 is
-   for VITAL
-   end for;
-end CFG_noa3ao322_x1_VITAL;
-
-
------ CELL noa3ao322_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity noa3ao322_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.819 ns, 0.987 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.914 ns, 0.931 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.990 ns, 0.874 ns);
-      tpd_i3_nq                      :	VitalDelayType01 := (0.729 ns, 0.926 ns);
-      tpd_i4_nq                      :	VitalDelayType01 := (0.821 ns, 0.924 ns);
-      tpd_i5_nq                      :	VitalDelayType01 := (0.907 ns, 0.900 ns);
-      tpd_i6_nq                      :	VitalDelayType01 := (0.738 ns, 0.718 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      i4                             :	in    STD_ULOGIC;
-      i5                             :	in    STD_ULOGIC;
-      i6                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of noa3ao322_x4 : entity is TRUE;
-end noa3ao322_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of noa3ao322_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i3_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i4_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i5_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i6_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   VitalWireDelay (i3_ipd, i3, tipd_i3);
-   VitalWireDelay (i4_ipd, i4, tipd_i4);
-   VitalWireDelay (i5_ipd, i5, tipd_i5);
-   VitalWireDelay (i6_ipd, i6, tipd_i6);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd, i6_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd :=
-       (((NOT i6_ipd)) OR (((NOT i4_ipd)) AND ((NOT i3_ipd)) AND ((NOT
-         i5_ipd)))) AND (((NOT i1_ipd)) OR ((NOT i0_ipd)) OR ((NOT i2_ipd)));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE),
-                 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE),
-                 4 => (i4_ipd'last_event, tpd_i4_nq, TRUE),
-                 5 => (i5_ipd'last_event, tpd_i5_nq, TRUE),
-                 6 => (i6_ipd'last_event, tpd_i6_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_noa3ao322_x4_VITAL of noa3ao322_x4 is
-   for VITAL
-   end for;
-end CFG_noa3ao322_x4_VITAL;
-
-
------ CELL noa22_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity noa22_x1 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.151 ns, 0.327 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.218 ns, 0.287 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.218 ns, 0.241 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of noa22_x1 : entity is TRUE;
-end noa22_x1;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of noa22_x1 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd := ((NOT i2_ipd)) AND (((NOT i1_ipd)) OR ((NOT i0_ipd)));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_noa22_x1_VITAL of noa22_x1 is
-   for VITAL
-   end for;
-end CFG_noa22_x1_VITAL;
-
-
------ CELL noa22_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity noa22_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.550 ns, 0.740 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.643 ns, 0.709 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.610 ns, 0.646 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of noa22_x4 : entity is TRUE;
-end noa22_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of noa22_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd := ((NOT i2_ipd)) AND (((NOT i1_ipd)) OR ((NOT i0_ipd)));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_noa22_x4_VITAL of noa22_x4 is
-   for VITAL
-   end for;
-end CFG_noa22_x4_VITAL;
-
-
------ CELL nts_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity nts_x1 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_cmd_nq                     :	VitalDelayType01z := 
-               (0.249 ns, 0.041 ns, 0.249 ns, 0.249 ns, 0.041 ns, 0.041 ns);
-      tpd_i_nq                       :	VitalDelayType01 := (0.169 ns, 0.201 ns);
-      tipd_i                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_cmd                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i                              :	in    STD_ULOGIC;
-      cmd                            :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of nts_x1 : entity is TRUE;
-end nts_x1;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of nts_x1 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL cmd_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i_ipd, i, tipd_i);
-   VitalWireDelay (cmd_ipd, cmd, tipd_cmd);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i_ipd, cmd_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd := VitalBUFIF0 (data => (NOT i_ipd),
-              enable => (NOT cmd_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01Z (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (cmd_ipd'last_event, VitalExtendToFillDelay(tpd_cmd_nq), TRUE),
-                 1 => (i_ipd'last_event, VitalExtendToFillDelay(tpd_i_nq), TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING,
-       OutputMap => "UX01ZWLH-");
-
-end process;
-
-end VITAL;
-
-configuration CFG_nts_x1_VITAL of nts_x1 is
-   for VITAL
-   end for;
-end CFG_nts_x1_VITAL;
-
-
------ CELL nts_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity nts_x2 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_cmd_nq                     :	VitalDelayType01z := 
-               (0.330 ns, 0.033 ns, 0.330 ns, 0.330 ns, 0.033 ns, 0.033 ns);
-      tpd_i_nq                       :	VitalDelayType01 := (0.167 ns, 0.201 ns);
-      tipd_i                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_cmd                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i                              :	in    STD_ULOGIC;
-      cmd                            :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of nts_x2 : entity is TRUE;
-end nts_x2;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of nts_x2 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL cmd_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i_ipd, i, tipd_i);
-   VitalWireDelay (cmd_ipd, cmd, tipd_cmd);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i_ipd, cmd_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd := VitalBUFIF0 (data => (NOT i_ipd),
-              enable => (NOT cmd_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01Z (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (cmd_ipd'last_event, VitalExtendToFillDelay(tpd_cmd_nq), TRUE),
-                 1 => (i_ipd'last_event, VitalExtendToFillDelay(tpd_i_nq), TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING,
-       OutputMap => "UX01ZWLH-");
-
-end process;
-
-end VITAL;
-
-configuration CFG_nts_x2_VITAL of nts_x2 is
-   for VITAL
-   end for;
-end CFG_nts_x2_VITAL;
-
-
------ CELL nxr2_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity nxr2_x1 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.288 ns, 0.293 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.156 ns, 0.327 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of nxr2_x1 : entity is TRUE;
-end nxr2_x1;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of nxr2_x1 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd := (i1_ipd) XOR ((NOT i0_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_nxr2_x1_VITAL of nxr2_x1 is
-   for VITAL
-   end for;
-end CFG_nxr2_x1_VITAL;
-
-
------ CELL nxr2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity nxr2_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.522 ns, 0.553 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.553 ns, 0.542 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of nxr2_x4 : entity is TRUE;
-end nxr2_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of nxr2_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS nq_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE nq_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      nq_zd := (i1_ipd) XOR ((NOT i0_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => nq,
-       GlitchData => nq_GlitchData,
-       OutSignalName => "nq",
-       OutTemp => nq_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_nxr2_x4_VITAL of nxr2_x4 is
-   for VITAL
-   end for;
-end CFG_nxr2_x4_VITAL;
-
-
------ CELL o2_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity o2_x2 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_q                       :	VitalDelayType01 := (0.406 ns, 0.310 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.335 ns, 0.364 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of o2_x2 : entity is TRUE;
-end o2_x2;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of o2_x2 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := (i1_ipd) OR (i0_ipd);
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_o2_x2_VITAL of o2_x2 is
-   for VITAL
-   end for;
-end CFG_o2_x2_VITAL;
-
-
------ CELL o2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity o2_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_q                       :	VitalDelayType01 := (0.491 ns, 0.394 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.427 ns, 0.464 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of o2_x4 : entity is TRUE;
-end o2_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of o2_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := (i1_ipd) OR (i0_ipd);
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_o2_x4_VITAL of o2_x4 is
-   for VITAL
-   end for;
-end CFG_o2_x4_VITAL;
-
-
------ CELL o3_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity o3_x2 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_q                       :	VitalDelayType01 := (0.494 ns, 0.407 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.430 ns, 0.482 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.360 ns, 0.506 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of o3_x2 : entity is TRUE;
-end o3_x2;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of o3_x2 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := (i1_ipd) OR (i0_ipd) OR (i2_ipd);
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_q, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_o3_x2_VITAL of o3_x2 is
-   for VITAL
-   end for;
-end CFG_o3_x2_VITAL;
-
-
------ CELL o3_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity o3_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_q                       :	VitalDelayType01 := (0.569 ns, 0.501 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.510 ns, 0.585 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.447 ns, 0.622 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of o3_x4 : entity is TRUE;
-end o3_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of o3_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := (i1_ipd) OR (i0_ipd) OR (i2_ipd);
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_q, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_o3_x4_VITAL of o3_x4 is
-   for VITAL
-   end for;
-end CFG_o3_x4_VITAL;
-
-
------ CELL o4_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity o4_x2 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_q                       :	VitalDelayType01 := (0.508 ns, 0.601 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.446 ns, 0.631 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.567 ns, 0.531 ns);
-      tpd_i3_q                       :	VitalDelayType01 := (0.378 ns, 0.626 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of o4_x2 : entity is TRUE;
-end o4_x2;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of o4_x2 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i3_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   VitalWireDelay (i3_ipd, i3, tipd_i3);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := (i1_ipd) OR (i0_ipd) OR (i2_ipd) OR (i3_ipd);
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_q, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_q, TRUE),
-                 3 => (i3_ipd'last_event, tpd_i3_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_o4_x2_VITAL of o4_x2 is
-   for VITAL
-   end for;
-end CFG_o4_x2_VITAL;
-
-
------ CELL o4_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity o4_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_q                       :	VitalDelayType01 := (0.574 ns, 0.638 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.492 ns, 0.650 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.649 ns, 0.611 ns);
-      tpd_i3_q                       :	VitalDelayType01 := (0.721 ns, 0.536 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of o4_x4 : entity is TRUE;
-end o4_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of o4_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i3_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   VitalWireDelay (i3_ipd, i3, tipd_i3);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := (i1_ipd) OR (i0_ipd) OR (i2_ipd) OR (i3_ipd);
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_q, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_q, TRUE),
-                 3 => (i3_ipd'last_event, tpd_i3_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_o4_x4_VITAL of o4_x4 is
-   for VITAL
-   end for;
-end CFG_o4_x4_VITAL;
-
-
------ CELL oa2a2a2a24_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity oa2a2a2a24_x2 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_q                       :	VitalDelayType01 := (0.780 ns, 0.797 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.909 ns, 0.753 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.682 ns, 0.856 ns);
-      tpd_i3_q                       :	VitalDelayType01 := (0.803 ns, 0.810 ns);
-      tpd_i4_q                       :	VitalDelayType01 := (0.565 ns, 0.813 ns);
-      tpd_i5_q                       :	VitalDelayType01 := (0.467 ns, 0.861 ns);
-      tpd_i6_q                       :	VitalDelayType01 := (0.426 ns, 0.748 ns);
-      tpd_i7_q                       :	VitalDelayType01 := (0.346 ns, 0.800 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      i4                             :	in    STD_ULOGIC;
-      i5                             :	in    STD_ULOGIC;
-      i6                             :	in    STD_ULOGIC;
-      i7                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of oa2a2a2a24_x2 : entity is TRUE;
-end oa2a2a2a24_x2;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of oa2a2a2a24_x2 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i3_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i4_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i5_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i6_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i7_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   VitalWireDelay (i3_ipd, i3, tipd_i3);
-   VitalWireDelay (i4_ipd, i4, tipd_i4);
-   VitalWireDelay (i5_ipd, i5, tipd_i5);
-   VitalWireDelay (i6_ipd, i6, tipd_i6);
-   VitalWireDelay (i7_ipd, i7, tipd_i7);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd, i6_ipd, i7_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd :=
-       ((i3_ipd) AND (i2_ipd)) OR ((i1_ipd) AND (i0_ipd)) OR ((i5_ipd) AND
-         (i4_ipd)) OR ((i7_ipd) AND (i6_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_q, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_q, TRUE),
-                 3 => (i3_ipd'last_event, tpd_i3_q, TRUE),
-                 4 => (i4_ipd'last_event, tpd_i4_q, TRUE),
-                 5 => (i5_ipd'last_event, tpd_i5_q, TRUE),
-                 6 => (i6_ipd'last_event, tpd_i6_q, TRUE),
-                 7 => (i7_ipd'last_event, tpd_i7_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_oa2a2a2a24_x2_VITAL of oa2a2a2a24_x2 is
-   for VITAL
-   end for;
-end CFG_oa2a2a2a24_x2_VITAL;
-
-
------ CELL oa2a2a2a24_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity oa2a2a2a24_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_q                       :	VitalDelayType01 := (0.823 ns, 0.879 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.955 ns, 0.835 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.726 ns, 0.940 ns);
-      tpd_i3_q                       :	VitalDelayType01 := (0.851 ns, 0.895 ns);
-      tpd_i4_q                       :	VitalDelayType01 := (0.619 ns, 0.902 ns);
-      tpd_i5_q                       :	VitalDelayType01 := (0.515 ns, 0.949 ns);
-      tpd_i6_q                       :	VitalDelayType01 := (0.487 ns, 0.845 ns);
-      tpd_i7_q                       :	VitalDelayType01 := (0.399 ns, 0.895 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      i4                             :	in    STD_ULOGIC;
-      i5                             :	in    STD_ULOGIC;
-      i6                             :	in    STD_ULOGIC;
-      i7                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of oa2a2a2a24_x4 : entity is TRUE;
-end oa2a2a2a24_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of oa2a2a2a24_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i3_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i4_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i5_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i6_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i7_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   VitalWireDelay (i3_ipd, i3, tipd_i3);
-   VitalWireDelay (i4_ipd, i4, tipd_i4);
-   VitalWireDelay (i5_ipd, i5, tipd_i5);
-   VitalWireDelay (i6_ipd, i6, tipd_i6);
-   VitalWireDelay (i7_ipd, i7, tipd_i7);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd, i6_ipd, i7_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd :=
-       ((i3_ipd) AND (i2_ipd)) OR ((i1_ipd) AND (i0_ipd)) OR ((i5_ipd) AND
-         (i4_ipd)) OR ((i7_ipd) AND (i6_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_q, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_q, TRUE),
-                 3 => (i3_ipd'last_event, tpd_i3_q, TRUE),
-                 4 => (i4_ipd'last_event, tpd_i4_q, TRUE),
-                 5 => (i5_ipd'last_event, tpd_i5_q, TRUE),
-                 6 => (i6_ipd'last_event, tpd_i6_q, TRUE),
-                 7 => (i7_ipd'last_event, tpd_i7_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_oa2a2a2a24_x4_VITAL of oa2a2a2a24_x4 is
-   for VITAL
-   end for;
-end CFG_oa2a2a2a24_x4_VITAL;
-
-
------ CELL oa2a2a23_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity oa2a2a23_x2 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_q                       :	VitalDelayType01 := (0.653 ns, 0.578 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.775 ns, 0.542 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.441 ns, 0.639 ns);
-      tpd_i3_q                       :	VitalDelayType01 := (0.540 ns, 0.600 ns);
-      tpd_i4_q                       :	VitalDelayType01 := (0.402 ns, 0.591 ns);
-      tpd_i5_q                       :	VitalDelayType01 := (0.321 ns, 0.636 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      i4                             :	in    STD_ULOGIC;
-      i5                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of oa2a2a23_x2 : entity is TRUE;
-end oa2a2a23_x2;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of oa2a2a23_x2 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i3_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i4_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i5_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   VitalWireDelay (i3_ipd, i3, tipd_i3);
-   VitalWireDelay (i4_ipd, i4, tipd_i4);
-   VitalWireDelay (i5_ipd, i5, tipd_i5);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd :=
-       ((i3_ipd) AND (i2_ipd)) OR ((i1_ipd) AND (i0_ipd)) OR ((i5_ipd) AND
-         (i4_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_q, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_q, TRUE),
-                 3 => (i3_ipd'last_event, tpd_i3_q, TRUE),
-                 4 => (i4_ipd'last_event, tpd_i4_q, TRUE),
-                 5 => (i5_ipd'last_event, tpd_i5_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_oa2a2a23_x2_VITAL of oa2a2a23_x2 is
-   for VITAL
-   end for;
-end CFG_oa2a2a23_x2_VITAL;
-
-
------ CELL oa2a2a23_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity oa2a2a23_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_q                       :	VitalDelayType01 := (0.699 ns, 0.648 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.822 ns, 0.613 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.493 ns, 0.715 ns);
-      tpd_i3_q                       :	VitalDelayType01 := (0.594 ns, 0.677 ns);
-      tpd_i4_q                       :	VitalDelayType01 := (0.464 ns, 0.673 ns);
-      tpd_i5_q                       :	VitalDelayType01 := (0.379 ns, 0.714 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      i4                             :	in    STD_ULOGIC;
-      i5                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of oa2a2a23_x4 : entity is TRUE;
-end oa2a2a23_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of oa2a2a23_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i3_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i4_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i5_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   VitalWireDelay (i3_ipd, i3, tipd_i3);
-   VitalWireDelay (i4_ipd, i4, tipd_i4);
-   VitalWireDelay (i5_ipd, i5, tipd_i5);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd :=
-       ((i3_ipd) AND (i2_ipd)) OR ((i1_ipd) AND (i0_ipd)) OR ((i5_ipd) AND
-         (i4_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_q, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_q, TRUE),
-                 3 => (i3_ipd'last_event, tpd_i3_q, TRUE),
-                 4 => (i4_ipd'last_event, tpd_i4_q, TRUE),
-                 5 => (i5_ipd'last_event, tpd_i5_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_oa2a2a23_x4_VITAL of oa2a2a23_x4 is
-   for VITAL
-   end for;
-end CFG_oa2a2a23_x4_VITAL;
-
-
------ CELL oa2a22_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity oa2a22_x2 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_q                       :	VitalDelayType01 := (0.403 ns, 0.564 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.495 ns, 0.534 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.646 ns, 0.487 ns);
-      tpd_i3_q                       :	VitalDelayType01 := (0.537 ns, 0.512 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of oa2a22_x2 : entity is TRUE;
-end oa2a22_x2;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of oa2a22_x2 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i3_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   VitalWireDelay (i3_ipd, i3, tipd_i3);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := ((i3_ipd) AND (i2_ipd)) OR ((i1_ipd) AND (i0_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_q, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_q, TRUE),
-                 3 => (i3_ipd'last_event, tpd_i3_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_oa2a22_x2_VITAL of oa2a22_x2 is
-   for VITAL
-   end for;
-end CFG_oa2a22_x2_VITAL;
-
-
------ CELL oa2a22_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity oa2a22_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_q                       :	VitalDelayType01 := (0.519 ns, 0.696 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.624 ns, 0.669 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.763 ns, 0.596 ns);
-      tpd_i3_q                       :	VitalDelayType01 := (0.644 ns, 0.619 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of oa2a22_x4 : entity is TRUE;
-end oa2a22_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of oa2a22_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i3_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   VitalWireDelay (i3_ipd, i3, tipd_i3);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := ((i3_ipd) AND (i2_ipd)) OR ((i1_ipd) AND (i0_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_q, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_q, TRUE),
-                 3 => (i3_ipd'last_event, tpd_i3_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_oa2a22_x4_VITAL of oa2a22_x4 is
-   for VITAL
-   end for;
-end CFG_oa2a22_x4_VITAL;
-
-
------ CELL oa2ao222_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity oa2ao222_x2 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_q                       :	VitalDelayType01 := (0.495 ns, 0.581 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.598 ns, 0.539 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.464 ns, 0.604 ns);
-      tpd_i3_q                       :	VitalDelayType01 := (0.556 ns, 0.578 ns);
-      tpd_i4_q                       :	VitalDelayType01 := (0.558 ns, 0.453 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      i4                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of oa2ao222_x2 : entity is TRUE;
-end oa2ao222_x2;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of oa2ao222_x2 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i3_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i4_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   VitalWireDelay (i3_ipd, i3, tipd_i3);
-   VitalWireDelay (i4_ipd, i4, tipd_i4);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd :=
-       (((i3_ipd) OR (i2_ipd)) AND (i4_ipd)) OR ((i1_ipd) AND (i0_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_q, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_q, TRUE),
-                 3 => (i3_ipd'last_event, tpd_i3_q, TRUE),
-                 4 => (i4_ipd'last_event, tpd_i4_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_oa2ao222_x2_VITAL of oa2ao222_x2 is
-   for VITAL
-   end for;
-end CFG_oa2ao222_x2_VITAL;
-
-
------ CELL oa2ao222_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity oa2ao222_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_q                       :	VitalDelayType01 := (0.553 ns, 0.657 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.662 ns, 0.616 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.552 ns, 0.693 ns);
-      tpd_i3_q                       :	VitalDelayType01 := (0.640 ns, 0.660 ns);
-      tpd_i4_q                       :	VitalDelayType01 := (0.656 ns, 0.529 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      i4                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of oa2ao222_x4 : entity is TRUE;
-end oa2ao222_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of oa2ao222_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i3_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i4_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   VitalWireDelay (i3_ipd, i3, tipd_i3);
-   VitalWireDelay (i4_ipd, i4, tipd_i4);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd :=
-       (((i3_ipd) OR (i2_ipd)) AND (i4_ipd)) OR ((i1_ipd) AND (i0_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_q, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_q, TRUE),
-                 3 => (i3_ipd'last_event, tpd_i3_q, TRUE),
-                 4 => (i4_ipd'last_event, tpd_i4_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_oa2ao222_x4_VITAL of oa2ao222_x4 is
-   for VITAL
-   end for;
-end CFG_oa2ao222_x4_VITAL;
-
-
------ CELL oa3ao322_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity oa3ao322_x2 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_q                       :	VitalDelayType01 := (0.638 ns, 0.820 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.735 ns, 0.764 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.806 ns, 0.707 ns);
-      tpd_i3_q                       :	VitalDelayType01 := (0.560 ns, 0.765 ns);
-      tpd_i4_q                       :	VitalDelayType01 := (0.649 ns, 0.760 ns);
-      tpd_i5_q                       :	VitalDelayType01 := (0.734 ns, 0.734 ns);
-      tpd_i6_q                       :	VitalDelayType01 := (0.563 ns, 0.540 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      i4                             :	in    STD_ULOGIC;
-      i5                             :	in    STD_ULOGIC;
-      i6                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of oa3ao322_x2 : entity is TRUE;
-end oa3ao322_x2;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of oa3ao322_x2 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i3_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i4_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i5_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i6_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   VitalWireDelay (i3_ipd, i3, tipd_i3);
-   VitalWireDelay (i4_ipd, i4, tipd_i4);
-   VitalWireDelay (i5_ipd, i5, tipd_i5);
-   VitalWireDelay (i6_ipd, i6, tipd_i6);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd, i6_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd :=
-       (((i4_ipd) OR (i3_ipd) OR (i5_ipd)) AND (i6_ipd)) OR ((i1_ipd) AND
-         (i0_ipd) AND (i2_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_q, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_q, TRUE),
-                 3 => (i3_ipd'last_event, tpd_i3_q, TRUE),
-                 4 => (i4_ipd'last_event, tpd_i4_q, TRUE),
-                 5 => (i5_ipd'last_event, tpd_i5_q, TRUE),
-                 6 => (i6_ipd'last_event, tpd_i6_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_oa3ao322_x2_VITAL of oa3ao322_x2 is
-   for VITAL
-   end for;
-end CFG_oa3ao322_x2_VITAL;
-
-
------ CELL oa3ao322_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity oa3ao322_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_q                       :	VitalDelayType01 := (0.717 ns, 0.946 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.818 ns, 0.890 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.894 ns, 0.834 ns);
-      tpd_i3_q                       :	VitalDelayType01 := (0.673 ns, 0.898 ns);
-      tpd_i4_q                       :	VitalDelayType01 := (0.758 ns, 0.896 ns);
-      tpd_i5_q                       :	VitalDelayType01 := (0.839 ns, 0.865 ns);
-      tpd_i6_q                       :	VitalDelayType01 := (0.684 ns, 0.651 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      i4                             :	in    STD_ULOGIC;
-      i5                             :	in    STD_ULOGIC;
-      i6                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of oa3ao322_x4 : entity is TRUE;
-end oa3ao322_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of oa3ao322_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i3_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i4_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i5_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i6_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   VitalWireDelay (i3_ipd, i3, tipd_i3);
-   VitalWireDelay (i4_ipd, i4, tipd_i4);
-   VitalWireDelay (i5_ipd, i5, tipd_i5);
-   VitalWireDelay (i6_ipd, i6, tipd_i6);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd, i6_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd :=
-       (((i4_ipd) OR (i3_ipd) OR (i5_ipd)) AND (i6_ipd)) OR ((i1_ipd) AND
-         (i0_ipd) AND (i2_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_q, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_q, TRUE),
-                 3 => (i3_ipd'last_event, tpd_i3_q, TRUE),
-                 4 => (i4_ipd'last_event, tpd_i4_q, TRUE),
-                 5 => (i5_ipd'last_event, tpd_i5_q, TRUE),
-                 6 => (i6_ipd'last_event, tpd_i6_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_oa3ao322_x4_VITAL of oa3ao322_x4 is
-   for VITAL
-   end for;
-end CFG_oa3ao322_x4_VITAL;
-
-
------ CELL oa22_x2 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity oa22_x2 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_q                       :	VitalDelayType01 := (0.390 ns, 0.555 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.488 ns, 0.525 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.438 ns, 0.454 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of oa22_x2 : entity is TRUE;
-end oa22_x2;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of oa22_x2 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := (i2_ipd) OR ((i1_ipd) AND (i0_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_q, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_oa22_x2_VITAL of oa22_x2 is
-   for VITAL
-   end for;
-end CFG_oa22_x2_VITAL;
-
-
------ CELL oa22_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity oa22_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_q                       :	VitalDelayType01 := (0.511 ns, 0.677 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.615 ns, 0.650 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.523 ns, 0.571 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of oa22_x4 : entity is TRUE;
-end oa22_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of oa22_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i2_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (i2_ipd, i2, tipd_i2);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := (i2_ipd) OR ((i1_ipd) AND (i0_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_q, TRUE),
-                 2 => (i2_ipd'last_event, tpd_i2_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_oa22_x4_VITAL of oa22_x4 is
-   for VITAL
-   end for;
-end CFG_oa22_x4_VITAL;
-
-
------ CELL on12_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity on12_x1 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_q                       :	VitalDelayType01 := (0.111 ns, 0.234 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.314 ns, 0.291 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of on12_x1 : entity is TRUE;
-end on12_x1;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of on12_x1 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := (i1_ipd) OR ((NOT i0_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_on12_x1_VITAL of on12_x1 is
-   for VITAL
-   end for;
-end CFG_on12_x1_VITAL;
-
-
------ CELL on12_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity on12_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_q                       :	VitalDelayType01 := (0.474 ns, 0.499 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.491 ns, 0.394 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of on12_x4 : entity is TRUE;
-end on12_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of on12_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := (i1_ipd) OR ((NOT i0_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_on12_x4_VITAL of on12_x4 is
-   for VITAL
-   end for;
-end CFG_on12_x4_VITAL;
-
-
------ CELL one_x0 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity one_x0 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True);
-
-   port(
-      q                              :	out   STD_ULOGIC := '1');
-attribute VITAL_LEVEL0 of one_x0 : entity is TRUE;
-end one_x0;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of one_x0 is
-   attribute VITAL_LEVEL0 of VITAL : architecture is TRUE;
-
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   --  empty
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   q <= '1';
-
-
-end VITAL;
-
-configuration CFG_one_x0_VITAL of one_x0 is
-   for VITAL
-   end for;
-end CFG_one_x0_VITAL;
-
-
------ CELL sff1_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity sff1_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_ck_q                       :	VitalDelayType01 := (0.500 ns, 0.500 ns);
-      tsetup_i_ck                    :	VitalDelayType := 0.585 ns;
-      thold_i_ck                     :	VitalDelayType := 0.000 ns;
-      tipd_i                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_ck                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i                              :	in    STD_ULOGIC;
-      ck                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of sff1_x4 : entity is TRUE;
-end sff1_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of sff1_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL ck_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i_ipd, i, tipd_i);
-   VitalWireDelay (ck_ipd, ck, tipd_ck);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i_ipd, ck_ipd)
-
-   -- timing check results
-   VARIABLE Tviol_i_ck_posedge	: STD_ULOGIC := '0';
-   VARIABLE Tmkr_i_ck_posedge	: VitalTimingDataType := VitalTimingDataInit;
-
-   -- functionality results
-   VARIABLE Violation : STD_ULOGIC := '0';
-   VARIABLE PrevData_q : STD_LOGIC_VECTOR(0 to 2);
-   VARIABLE i_delayed : STD_ULOGIC := 'X';
-   VARIABLE ck_delayed : STD_ULOGIC := 'X';
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      ------------------------
-      --  Timing Check Section
-      ------------------------
-      if (TimingChecksOn) then
-         VitalSetupHoldCheck (
-          Violation               => Tviol_i_ck_posedge,
-          TimingData              => Tmkr_i_ck_posedge,
-          TestSignal              => i_ipd,
-          TestSignalName          => "i",
-          TestDelay               => 0 ns,
-          RefSignal               => ck_ipd,
-          RefSignalName          => "ck",
-          RefDelay                => 0 ns,
-          SetupHigh               => tsetup_i_ck,
-          SetupLow                => tsetup_i_ck,
-          HoldHigh                => thold_i_ck,
-          HoldLow                 => thold_i_ck,
-          CheckEnabled            => 
-                           TRUE,
-          RefTransition           => 'R',
-          HeaderMsg               => InstancePath & "/sff1_x4",
-          Xon                     => Xon,
-          MsgOn                   => MsgOn,
-          MsgSeverity             => WARNING);
-      end if;
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      Violation := Tviol_i_ck_posedge;
-      VitalStateTable(
-        Result => q_zd,
-        PreviousDataIn => PrevData_q,
-        StateTable => sff1_x4_q_tab,
-        DataIn => (
-               ck_delayed, i_delayed, ck_ipd));
-      q_zd := Violation XOR q_zd;
-      i_delayed := i_ipd;
-      ck_delayed := ck_ipd;
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (ck_ipd'last_event, tpd_ck_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_sff1_x4_VITAL of sff1_x4 is
-   for VITAL
-   end for;
-end CFG_sff1_x4_VITAL;
-
-
------ CELL sff2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity sff2_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_ck_q                       :	VitalDelayType01 := (0.500 ns, 0.500 ns);
-      tsetup_i0_ck                   :	VitalDelayType := 0.764 ns;
-      thold_i0_ck                    :	VitalDelayType := 0.000 ns;
-      tsetup_i1_ck                   :	VitalDelayType := 0.764 ns;
-      thold_i1_ck                    :	VitalDelayType := 0.000 ns;
-      tsetup_cmd_ck                  :	VitalDelayType := 0.833 ns;
-      thold_cmd_ck                   :	VitalDelayType := 0.000 ns;
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_cmd                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_ck                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      cmd                            :	in    STD_ULOGIC;
-      ck                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of sff2_x4 : entity is TRUE;
-end sff2_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of sff2_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL cmd_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL ck_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   VitalWireDelay (cmd_ipd, cmd, tipd_cmd);
-   VitalWireDelay (ck_ipd, ck, tipd_ck);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd, cmd_ipd, ck_ipd)
-
-   -- timing check results
-   VARIABLE Tviol_i0_ck_posedge	: STD_ULOGIC := '0';
-   VARIABLE Tmkr_i0_ck_posedge	: VitalTimingDataType := VitalTimingDataInit;
-   VARIABLE Tviol_i1_ck_posedge	: STD_ULOGIC := '0';
-   VARIABLE Tmkr_i1_ck_posedge	: VitalTimingDataType := VitalTimingDataInit;
-   VARIABLE Tviol_cmd_ck_posedge	: STD_ULOGIC := '0';
-   VARIABLE Tmkr_cmd_ck_posedge	: VitalTimingDataType := VitalTimingDataInit;
-
-   -- functionality results
-   VARIABLE Violation : STD_ULOGIC := '0';
-   VARIABLE PrevData_q : STD_LOGIC_VECTOR(0 to 4);
-   VARIABLE i0_delayed : STD_ULOGIC := 'X';
-   VARIABLE i1_delayed : STD_ULOGIC := 'X';
-   VARIABLE cmd_delayed : STD_ULOGIC := 'X';
-   VARIABLE ck_delayed : STD_ULOGIC := 'X';
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      ------------------------
-      --  Timing Check Section
-      ------------------------
-      if (TimingChecksOn) then
-         VitalSetupHoldCheck (
-          Violation               => Tviol_i0_ck_posedge,
-          TimingData              => Tmkr_i0_ck_posedge,
-          TestSignal              => i0_ipd,
-          TestSignalName          => "i0",
-          TestDelay               => 0 ns,
-          RefSignal               => ck_ipd,
-          RefSignalName          => "ck",
-          RefDelay                => 0 ns,
-          SetupHigh               => tsetup_i0_ck,
-          SetupLow                => tsetup_i0_ck,
-          HoldHigh                => thold_i0_ck,
-          HoldLow                 => thold_i0_ck,
-          CheckEnabled            => 
-                           TRUE,
-          RefTransition           => 'R',
-          HeaderMsg               => InstancePath & "/sff2_x4",
-          Xon                     => Xon,
-          MsgOn                   => MsgOn,
-          MsgSeverity             => WARNING);
-         VitalSetupHoldCheck (
-          Violation               => Tviol_i1_ck_posedge,
-          TimingData              => Tmkr_i1_ck_posedge,
-          TestSignal              => i1_ipd,
-          TestSignalName          => "i1",
-          TestDelay               => 0 ns,
-          RefSignal               => ck_ipd,
-          RefSignalName          => "ck",
-          RefDelay                => 0 ns,
-          SetupHigh               => tsetup_i1_ck,
-          SetupLow                => tsetup_i1_ck,
-          HoldHigh                => thold_i1_ck,
-          HoldLow                 => thold_i1_ck,
-          CheckEnabled            => 
-                           TRUE,
-          RefTransition           => 'R',
-          HeaderMsg               => InstancePath & "/sff2_x4",
-          Xon                     => Xon,
-          MsgOn                   => MsgOn,
-          MsgSeverity             => WARNING);
-         VitalSetupHoldCheck (
-          Violation               => Tviol_cmd_ck_posedge,
-          TimingData              => Tmkr_cmd_ck_posedge,
-          TestSignal              => cmd_ipd,
-          TestSignalName          => "cmd",
-          TestDelay               => 0 ns,
-          RefSignal               => ck_ipd,
-          RefSignalName          => "ck",
-          RefDelay                => 0 ns,
-          SetupHigh               => tsetup_cmd_ck,
-          SetupLow                => tsetup_cmd_ck,
-          HoldHigh                => thold_cmd_ck,
-          HoldLow                 => thold_cmd_ck,
-          CheckEnabled            => 
-                           TRUE,
-          RefTransition           => 'R',
-          HeaderMsg               => InstancePath & "/sff2_x4",
-          Xon                     => Xon,
-          MsgOn                   => MsgOn,
-          MsgSeverity             => WARNING);
-      end if;
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      Violation := Tviol_i0_ck_posedge or Tviol_i1_ck_posedge or Tviol_cmd_ck_posedge;
-      VitalStateTable(
-        Result => q_zd,
-        PreviousDataIn => PrevData_q,
-        StateTable => sff2_x4_q_tab,
-        DataIn => (
-               ck_delayed, i1_delayed, i0_delayed, cmd_delayed, ck_ipd));
-      q_zd := Violation XOR q_zd;
-      i0_delayed := i0_ipd;
-      i1_delayed := i1_ipd;
-      cmd_delayed := cmd_ipd;
-      ck_delayed := ck_ipd;
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (ck_ipd'last_event, tpd_ck_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_sff2_x4_VITAL of sff2_x4 is
-   for VITAL
-   end for;
-end CFG_sff2_x4_VITAL;
-
-
------ CELL ts_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity ts_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_cmd_q                      :	VitalDelayType01z := 
-               (0.492 ns, 0.409 ns, 0.492 ns, 0.492 ns, 0.409 ns, 0.409 ns);
-      tpd_i_q                        :	VitalDelayType01 := (0.475 ns, 0.444 ns);
-      tipd_i                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_cmd                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i                              :	in    STD_ULOGIC;
-      cmd                            :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of ts_x4 : entity is TRUE;
-end ts_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of ts_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL cmd_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i_ipd, i, tipd_i);
-   VitalWireDelay (cmd_ipd, cmd, tipd_cmd);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i_ipd, cmd_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := VitalBUFIF0 (data => i_ipd,
-              enable => (NOT cmd_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01Z (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (cmd_ipd'last_event, VitalExtendToFillDelay(tpd_cmd_q), TRUE),
-                 1 => (i_ipd'last_event, VitalExtendToFillDelay(tpd_i_q), TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING,
-       OutputMap => "UX01ZWLH-");
-
-end process;
-
-end VITAL;
-
-configuration CFG_ts_x4_VITAL of ts_x4 is
-   for VITAL
-   end for;
-end CFG_ts_x4_VITAL;
-
-
------ CELL ts_x8 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity ts_x8 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_cmd_q                      :	VitalDelayType01z := 
-               (0.626 ns, 0.466 ns, 0.626 ns, 0.626 ns, 0.466 ns, 0.466 ns);
-      tpd_i_q                        :	VitalDelayType01 := (0.613 ns, 0.569 ns);
-      tipd_i                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_cmd                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i                              :	in    STD_ULOGIC;
-      cmd                            :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of ts_x8 : entity is TRUE;
-end ts_x8;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of ts_x8 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL cmd_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i_ipd, i, tipd_i);
-   VitalWireDelay (cmd_ipd, cmd, tipd_cmd);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i_ipd, cmd_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := VitalBUFIF0 (data => i_ipd,
-              enable => (NOT cmd_ipd));
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01Z (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (cmd_ipd'last_event, VitalExtendToFillDelay(tpd_cmd_q), TRUE),
-                 1 => (i_ipd'last_event, VitalExtendToFillDelay(tpd_i_q), TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING,
-       OutputMap => "UX01ZWLH-");
-
-end process;
-
-end VITAL;
-
-configuration CFG_ts_x8_VITAL of ts_x8 is
-   for VITAL
-   end for;
-end CFG_ts_x8_VITAL;
-
-
------ CELL xr2_x1 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity xr2_x1 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_q                       :	VitalDelayType01 := (0.292 ns, 0.293 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.377 ns, 0.261 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of xr2_x1 : entity is TRUE;
-end xr2_x1;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of xr2_x1 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := (i1_ipd) XOR (i0_ipd);
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_xr2_x1_VITAL of xr2_x1 is
-   for VITAL
-   end for;
-end CFG_xr2_x1_VITAL;
-
-
------ CELL xr2_x4 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity xr2_x4 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True;
-      tpd_i0_q                       :	VitalDelayType01 := (0.521 ns, 0.560 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.541 ns, 0.657 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-attribute VITAL_LEVEL0 of xr2_x4 : entity is TRUE;
-end xr2_x4;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of xr2_x4 is
-   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;
-
-   SIGNAL i0_ipd	 : STD_ULOGIC := 'X';
-   SIGNAL i1_ipd	 : STD_ULOGIC := 'X';
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   VitalWireDelay (i0_ipd, i0, tipd_i0);
-   VitalWireDelay (i1_ipd, i1, tipd_i1);
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   VITALBehavior : process (i0_ipd, i1_ipd)
-
-
-   -- functionality results
-   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
-   ALIAS q_zd : STD_LOGIC is Results(1);
-
-   -- output glitch detection variables
-   VARIABLE q_GlitchData	: VitalGlitchDataType;
-
-   begin
-
-      -------------------------
-      --  Functionality Section
-      -------------------------
-      q_zd := (i1_ipd) XOR (i0_ipd);
-
-      ----------------------
-      --  Path Delay Section
-      ----------------------
-      VitalPathDelay01 (
-       OutSignal => q,
-       GlitchData => q_GlitchData,
-       OutSignalName => "q",
-       OutTemp => q_zd,
-       Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE),
-                 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)),
-       Mode => OnDetect,
-       Xon => Xon,
-       MsgOn => MsgOn,
-       MsgSeverity => WARNING);
-
-end process;
-
-end VITAL;
-
-configuration CFG_xr2_x4_VITAL of xr2_x4 is
-   for VITAL
-   end for;
-end CFG_xr2_x4_VITAL;
-
-
------ CELL zero_x0 -----
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library IEEE;
-use IEEE.VITAL_Timing.all;
-
-
--- entity declaration --
-entity zero_x0 is
-   generic(
-      TimingChecksOn: Boolean := True;
-      InstancePath: STRING := "*";
-      Xon: Boolean := False;
-      MsgOn: Boolean := True);
-
-   port(
-      nq                             :	out   STD_ULOGIC := '0');
-attribute VITAL_LEVEL0 of zero_x0 : entity is TRUE;
-end zero_x0;
-
--- architecture body --
-library IEEE;
-use IEEE.VITAL_Primitives.all;
-library sxlib;
-use sxlib.VTABLES.all;
-architecture VITAL of zero_x0 is
-   attribute VITAL_LEVEL0 of VITAL : architecture is TRUE;
-
-
-begin
-
-   ---------------------
-   --  INPUT PATH DELAYs
-   ---------------------
-   WireDelay : block
-   begin
-   --  empty
-   end block;
-   --------------------
-   --  BEHAVIOR SECTION
-   --------------------
-   nq <= '0';
-
-
-end VITAL;
-
-configuration CFG_zero_x0_VITAL of zero_x0 is
-   for VITAL
-   end for;
-end CFG_zero_x0_VITAL;
-
-
----- end of library ----
diff --git a/alliance/share/cells/sxlib/sxlib_Vcomponents.vhd b/alliance/share/cells/sxlib/sxlib_Vcomponents.vhd
deleted file mode 100644
index 5844b9e3..00000000
--- a/alliance/share/cells/sxlib/sxlib_Vcomponents.vhd
+++ /dev/null
@@ -1,2252 +0,0 @@
-
-----------------------------------------------------------------
--- 
--- Created by the Synopsys Library Compiler 1999.10
--- FILENAME     :    sxlib_Vcomponents.vhd
--- FILE CONTENTS:    VITAL Component Package
--- DATE CREATED :    Mon May  7 10:19:50 2001
--- 
--- LIBRARY      :    sxlib
--- DATE ENTERED :    Thu Dec 21 11:24:55 MET 2000
--- REVISION     :    1.200000
--- TECHNOLOGY   :    cmos
--- TIME SCALE   :    1 ns
--- LOGIC SYSTEM :    IEEE-1164
--- NOTES        :    
--- HISTORY      :
--- 
-----------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
--- synopsys translate_off
-
-library IEEE;
-use IEEE.VITAL_Timing.all;
--- synopsys translate_on
-
-package VCOMPONENTS is
-
-constant DefaultTimingChecksOn : Boolean := True;
-constant DefaultXon : Boolean := False;
-constant DefaultMsgOn : Boolean := True;
-
------ Component a2_x2 -----
-component a2_x2
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_q                       :	VitalDelayType01 := (0.261 ns, 0.388 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.203 ns, 0.434 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component a2_x4 -----
-component a2_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_q                       :	VitalDelayType01 := (0.338 ns, 0.476 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.269 ns, 0.518 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component a3_x2 -----
-component a3_x2
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_q                       :	VitalDelayType01 := (0.395 ns, 0.435 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.353 ns, 0.479 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.290 ns, 0.521 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component a3_x4 -----
-component a3_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_q                       :	VitalDelayType01 := (0.478 ns, 0.514 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.428 ns, 0.554 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.356 ns, 0.592 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component a4_x2 -----
-component a4_x2
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_q                       :	VitalDelayType01 := (0.374 ns, 0.578 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.441 ns, 0.539 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.482 ns, 0.498 ns);
-      tpd_i3_q                       :	VitalDelayType01 := (0.506 ns, 0.455 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component a4_x4 -----
-component a4_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_q                       :	VitalDelayType01 := (0.505 ns, 0.650 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.578 ns, 0.614 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.627 ns, 0.576 ns);
-      tpd_i3_q                       :	VitalDelayType01 := (0.661 ns, 0.538 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component an12_x1 -----
-component an12_x1
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_q                       :	VitalDelayType01 := (0.200 ns, 0.168 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.285 ns, 0.405 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component an12_x4 -----
-component an12_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_q                       :	VitalDelayType01 := (0.461 ns, 0.471 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.269 ns, 0.518 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component ao2o22_x2 -----
-component ao2o22_x2
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_q                       :	VitalDelayType01 := (0.572 ns, 0.451 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.508 ns, 0.542 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.432 ns, 0.627 ns);
-      tpd_i3_q                       :	VitalDelayType01 := (0.488 ns, 0.526 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component ao2o22_x4 -----
-component ao2o22_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_q                       :	VitalDelayType01 := (0.696 ns, 0.569 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.637 ns, 0.666 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.554 ns, 0.744 ns);
-      tpd_i3_q                       :	VitalDelayType01 := (0.606 ns, 0.639 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component ao22_x2 -----
-component ao22_x2
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_q                       :	VitalDelayType01 := (0.558 ns, 0.447 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.493 ns, 0.526 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.420 ns, 0.425 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component ao22_x4 -----
-component ao22_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_q                       :	VitalDelayType01 := (0.674 ns, 0.552 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.615 ns, 0.647 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.526 ns, 0.505 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component buf_x2 -----
-component buf_x2
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i_q                        :	VitalDelayType01 := (0.409 ns, 0.391 ns);
-      tipd_i                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i                              :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component buf_x4 -----
-component buf_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i_q                        :	VitalDelayType01 := (0.379 ns, 0.409 ns);
-      tipd_i                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i                              :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component buf_x8 -----
-component buf_x8
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i_q                        :	VitalDelayType01 := (0.343 ns, 0.396 ns);
-      tipd_i                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i                              :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component inv_x1 -----
-component inv_x1
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i_nq                       :	VitalDelayType01 := (0.101 ns, 0.139 ns);
-      tipd_i                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i                              :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component inv_x2 -----
-component inv_x2
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i_nq                       :	VitalDelayType01 := (0.069 ns, 0.163 ns);
-      tipd_i                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i                              :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component inv_x4 -----
-component inv_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i_nq                       :	VitalDelayType01 := (0.071 ns, 0.143 ns);
-      tipd_i                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i                              :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component inv_x8 -----
-component inv_x8
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i_nq                       :	VitalDelayType01 := (0.086 ns, 0.133 ns);
-      tipd_i                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i                              :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component mx2_x2 -----
-component mx2_x2
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_cmd_q                      :	VitalDelayType01 := (0.484 ns, 0.522 ns);
-      tpd_i0_q                       :	VitalDelayType01 := (0.451 ns, 0.469 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.451 ns, 0.469 ns);
-      tipd_cmd                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      cmd                            :	in    STD_ULOGIC;
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component mx2_x4 -----
-component mx2_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_cmd_q                      :	VitalDelayType01 := (0.615 ns, 0.647 ns);
-      tpd_i0_q                       :	VitalDelayType01 := (0.564 ns, 0.576 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.564 ns, 0.576 ns);
-      tipd_cmd                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      cmd                            :	in    STD_ULOGIC;
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component mx3_x2 -----
-component mx3_x2
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_cmd0_q                     :	VitalDelayType01 := (0.573 ns, 0.680 ns);
-      tpd_cmd1_q                     :	VitalDelayType01 := (0.664 ns, 0.817 ns);
-      tpd_i0_q                       :	VitalDelayType01 := (0.538 ns, 0.658 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.654 ns, 0.808 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.654 ns, 0.808 ns);
-      tipd_cmd0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_cmd1                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      cmd0                           :	in    STD_ULOGIC;
-      cmd1                           :	in    STD_ULOGIC;
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component mx3_x4 -----
-component mx3_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_cmd0_q                     :	VitalDelayType01 := (0.683 ns, 0.779 ns);
-      tpd_cmd1_q                     :	VitalDelayType01 := (0.792 ns, 0.967 ns);
-      tpd_i0_q                       :	VitalDelayType01 := (0.640 ns, 0.774 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.770 ns, 0.948 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.770 ns, 0.948 ns);
-      tipd_cmd0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_cmd1                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      cmd0                           :	in    STD_ULOGIC;
-      cmd1                           :	in    STD_ULOGIC;
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component na2_x1 -----
-component na2_x1
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.059 ns, 0.288 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.111 ns, 0.234 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component na2_x4 -----
-component na2_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.412 ns, 0.552 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.353 ns, 0.601 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component na3_x1 -----
-component na3_x1
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.119 ns, 0.363 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.171 ns, 0.316 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.193 ns, 0.265 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component na3_x4 -----
-component na3_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.556 ns, 0.601 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.460 ns, 0.691 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.519 ns, 0.647 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component na4_x1 -----
-component na4_x1
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.179 ns, 0.438 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.237 ns, 0.395 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.269 ns, 0.350 ns);
-      tpd_i3_nq                      :	VitalDelayType01 := (0.282 ns, 0.302 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component na4_x4 -----
-component na4_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.578 ns, 0.771 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.643 ns, 0.731 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.681 ns, 0.689 ns);
-      tpd_i3_nq                      :	VitalDelayType01 := (0.703 ns, 0.644 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component nao2o22_x1 -----
-component nao2o22_x1
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.294 ns, 0.226 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.218 ns, 0.287 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.237 ns, 0.307 ns);
-      tpd_i3_nq                      :	VitalDelayType01 := (0.174 ns, 0.382 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component nao2o22_x4 -----
-component nao2o22_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.734 ns, 0.644 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.666 ns, 0.717 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.664 ns, 0.721 ns);
-      tpd_i3_nq                      :	VitalDelayType01 := (0.607 ns, 0.807 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component nao22_x1 -----
-component nao22_x1
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.294 ns, 0.226 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.218 ns, 0.287 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.165 ns, 0.238 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component nao22_x4 -----
-component nao22_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.732 ns, 0.650 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.664 ns, 0.723 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.596 ns, 0.636 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component nmx2_x1 -----
-component nmx2_x1
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_cmd_nq                     :	VitalDelayType01 := (0.218 ns, 0.287 ns);
-      tpd_i0_nq                      :	VitalDelayType01 := (0.217 ns, 0.256 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.217 ns, 0.256 ns);
-      tipd_cmd                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      cmd                            :	in    STD_ULOGIC;
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component nmx2_x4 -----
-component nmx2_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_cmd_nq                     :	VitalDelayType01 := (0.632 ns, 0.708 ns);
-      tpd_i0_nq                      :	VitalDelayType01 := (0.610 ns, 0.653 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.610 ns, 0.653 ns);
-      tipd_cmd                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      cmd                            :	in    STD_ULOGIC;
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component nmx3_x1 -----
-component nmx3_x1
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_cmd0_nq                    :	VitalDelayType01 := (0.356 ns, 0.495 ns);
-      tpd_cmd1_nq                    :	VitalDelayType01 := (0.414 ns, 0.566 ns);
-      tpd_i0_nq                      :	VitalDelayType01 := (0.315 ns, 0.441 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.429 ns, 0.582 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.429 ns, 0.582 ns);
-      tipd_cmd0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_cmd1                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      cmd0                           :	in    STD_ULOGIC;
-      cmd1                           :	in    STD_ULOGIC;
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component nmx3_x4 -----
-component nmx3_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_cmd0_nq                    :	VitalDelayType01 := (0.790 ns, 0.936 ns);
-      tpd_cmd1_nq                    :	VitalDelayType01 := (0.866 ns, 1.048 ns);
-      tpd_i0_nq                      :	VitalDelayType01 := (0.748 ns, 0.900 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.869 ns, 1.053 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.869 ns, 1.053 ns);
-      tipd_cmd0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_cmd1                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      cmd0                           :	in    STD_ULOGIC;
-      cmd1                           :	in    STD_ULOGIC;
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component no2_x1 -----
-component no2_x1
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.298 ns, 0.121 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.193 ns, 0.161 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component no2_x4 -----
-component no2_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.618 ns, 0.447 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.522 ns, 0.504 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component no3_x1 -----
-component no3_x1
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.318 ns, 0.246 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.215 ns, 0.243 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.407 ns, 0.192 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component no3_x4 -----
-component no3_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.722 ns, 0.561 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.638 ns, 0.623 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.545 ns, 0.640 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component no4_x1 -----
-component no4_x1
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.330 ns, 0.340 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.230 ns, 0.320 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.419 ns, 0.333 ns);
-      tpd_i3_nq                      :	VitalDelayType01 := (0.499 ns, 0.271 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component no4_x4 -----
-component no4_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.656 ns, 0.777 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.564 ns, 0.768 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.739 ns, 0.761 ns);
-      tpd_i3_nq                      :	VitalDelayType01 := (0.816 ns, 0.693 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component noa2a2a2a24_x1 -----
-component noa2a2a2a24_x1
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.649 ns, 0.606 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.775 ns, 0.562 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.550 ns, 0.662 ns);
-      tpd_i3_nq                      :	VitalDelayType01 := (0.667 ns, 0.616 ns);
-      tpd_i4_nq                      :	VitalDelayType01 := (0.419 ns, 0.613 ns);
-      tpd_i5_nq                      :	VitalDelayType01 := (0.329 ns, 0.662 ns);
-      tpd_i6_nq                      :	VitalDelayType01 := (0.270 ns, 0.535 ns);
-      tpd_i7_nq                      :	VitalDelayType01 := (0.200 ns, 0.591 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      i4                             :	in    STD_ULOGIC;
-      i5                             :	in    STD_ULOGIC;
-      i6                             :	in    STD_ULOGIC;
-      i7                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component noa2a2a2a24_x4 -----
-component noa2a2a2a24_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.966 ns, 1.049 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (1.097 ns, 1.005 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.867 ns, 1.106 ns);
-      tpd_i3_nq                      :	VitalDelayType01 := (0.990 ns, 1.061 ns);
-      tpd_i4_nq                      :	VitalDelayType01 := (0.748 ns, 1.061 ns);
-      tpd_i5_nq                      :	VitalDelayType01 := (0.649 ns, 1.109 ns);
-      tpd_i6_nq                      :	VitalDelayType01 := (0.606 ns, 0.999 ns);
-      tpd_i7_nq                      :	VitalDelayType01 := (0.525 ns, 1.052 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      i4                             :	in    STD_ULOGIC;
-      i5                             :	in    STD_ULOGIC;
-      i6                             :	in    STD_ULOGIC;
-      i7                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component noa2a2a23_x1 -----
-component noa2a2a23_x1
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.525 ns, 0.425 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.643 ns, 0.388 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.307 ns, 0.479 ns);
-      tpd_i3_nq                      :	VitalDelayType01 := (0.398 ns, 0.438 ns);
-      tpd_i4_nq                      :	VitalDelayType01 := (0.250 ns, 0.416 ns);
-      tpd_i5_nq                      :	VitalDelayType01 := (0.178 ns, 0.464 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      i4                             :	in    STD_ULOGIC;
-      i5                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component noa2a2a23_x4 -----
-component noa2a2a23_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.834 ns, 0.814 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.955 ns, 0.778 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.620 ns, 0.873 ns);
-      tpd_i3_nq                      :	VitalDelayType01 := (0.716 ns, 0.833 ns);
-      tpd_i4_nq                      :	VitalDelayType01 := (0.574 ns, 0.819 ns);
-      tpd_i5_nq                      :	VitalDelayType01 := (0.496 ns, 0.865 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      i4                             :	in    STD_ULOGIC;
-      i5                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component noa2a22_x1 -----
-component noa2a22_x1
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.151 ns, 0.327 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.218 ns, 0.287 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.284 ns, 0.289 ns);
-      tpd_i3_nq                      :	VitalDelayType01 := (0.372 ns, 0.256 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component noa2a22_x4 -----
-component noa2a22_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.562 ns, 0.745 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.646 ns, 0.714 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.701 ns, 0.703 ns);
-      tpd_i3_nq                      :	VitalDelayType01 := (0.805 ns, 0.677 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component noa2ao222_x1 -----
-component noa2ao222_x1
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.348 ns, 0.422 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.440 ns, 0.378 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.186 ns, 0.473 ns);
-      tpd_i3_nq                      :	VitalDelayType01 := (0.256 ns, 0.459 ns);
-      tpd_i4_nq                      :	VitalDelayType01 := (0.240 ns, 0.309 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      i4                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component noa2ao222_x4 -----
-component noa2ao222_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.684 ns, 0.801 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.780 ns, 0.758 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.638 ns, 0.809 ns);
-      tpd_i3_nq                      :	VitalDelayType01 := (0.732 ns, 0.795 ns);
-      tpd_i4_nq                      :	VitalDelayType01 := (0.718 ns, 0.664 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      i4                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component noa3ao322_x1 -----
-component noa3ao322_x1
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.396 ns, 0.616 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.486 ns, 0.552 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.546 ns, 0.488 ns);
-      tpd_i3_nq                      :	VitalDelayType01 := (0.196 ns, 0.599 ns);
-      tpd_i4_nq                      :	VitalDelayType01 := (0.264 ns, 0.608 ns);
-      tpd_i5_nq                      :	VitalDelayType01 := (0.328 ns, 0.581 ns);
-      tpd_i6_nq                      :	VitalDelayType01 := (0.246 ns, 0.311 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      i4                             :	in    STD_ULOGIC;
-      i5                             :	in    STD_ULOGIC;
-      i6                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component noa3ao322_x4 -----
-component noa3ao322_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.819 ns, 0.987 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.914 ns, 0.931 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.990 ns, 0.874 ns);
-      tpd_i3_nq                      :	VitalDelayType01 := (0.729 ns, 0.926 ns);
-      tpd_i4_nq                      :	VitalDelayType01 := (0.821 ns, 0.924 ns);
-      tpd_i5_nq                      :	VitalDelayType01 := (0.907 ns, 0.900 ns);
-      tpd_i6_nq                      :	VitalDelayType01 := (0.738 ns, 0.718 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      i4                             :	in    STD_ULOGIC;
-      i5                             :	in    STD_ULOGIC;
-      i6                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component noa22_x1 -----
-component noa22_x1
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.151 ns, 0.327 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.218 ns, 0.287 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.218 ns, 0.241 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component noa22_x4 -----
-component noa22_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.550 ns, 0.740 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.643 ns, 0.709 ns);
-      tpd_i2_nq                      :	VitalDelayType01 := (0.610 ns, 0.646 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component nts_x1 -----
-component nts_x1
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_cmd_nq                     :	VitalDelayType01z := 
-               (0.249 ns, 0.041 ns, 0.249 ns, 0.249 ns, 0.041 ns, 0.041 ns);
-      tpd_i_nq                       :	VitalDelayType01 := (0.169 ns, 0.201 ns);
-      tipd_i                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_cmd                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i                              :	in    STD_ULOGIC;
-      cmd                            :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component nts_x2 -----
-component nts_x2
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_cmd_nq                     :	VitalDelayType01z := 
-               (0.330 ns, 0.033 ns, 0.330 ns, 0.330 ns, 0.033 ns, 0.033 ns);
-      tpd_i_nq                       :	VitalDelayType01 := (0.167 ns, 0.201 ns);
-      tipd_i                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_cmd                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i                              :	in    STD_ULOGIC;
-      cmd                            :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component nxr2_x1 -----
-component nxr2_x1
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.288 ns, 0.293 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.156 ns, 0.327 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component nxr2_x4 -----
-component nxr2_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_nq                      :	VitalDelayType01 := (0.522 ns, 0.553 ns);
-      tpd_i1_nq                      :	VitalDelayType01 := (0.553 ns, 0.542 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      nq                             :	out   STD_ULOGIC);
-end component;
-
-
------ Component o2_x2 -----
-component o2_x2
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_q                       :	VitalDelayType01 := (0.406 ns, 0.310 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.335 ns, 0.364 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component o2_x4 -----
-component o2_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_q                       :	VitalDelayType01 := (0.491 ns, 0.394 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.427 ns, 0.464 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component o3_x2 -----
-component o3_x2
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_q                       :	VitalDelayType01 := (0.494 ns, 0.407 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.430 ns, 0.482 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.360 ns, 0.506 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component o3_x4 -----
-component o3_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_q                       :	VitalDelayType01 := (0.569 ns, 0.501 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.510 ns, 0.585 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.447 ns, 0.622 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component o4_x2 -----
-component o4_x2
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_q                       :	VitalDelayType01 := (0.508 ns, 0.601 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.446 ns, 0.631 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.567 ns, 0.531 ns);
-      tpd_i3_q                       :	VitalDelayType01 := (0.378 ns, 0.626 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component o4_x4 -----
-component o4_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_q                       :	VitalDelayType01 := (0.574 ns, 0.638 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.492 ns, 0.650 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.649 ns, 0.611 ns);
-      tpd_i3_q                       :	VitalDelayType01 := (0.721 ns, 0.536 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component oa2a2a2a24_x2 -----
-component oa2a2a2a24_x2
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_q                       :	VitalDelayType01 := (0.780 ns, 0.797 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.909 ns, 0.753 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.682 ns, 0.856 ns);
-      tpd_i3_q                       :	VitalDelayType01 := (0.803 ns, 0.810 ns);
-      tpd_i4_q                       :	VitalDelayType01 := (0.565 ns, 0.813 ns);
-      tpd_i5_q                       :	VitalDelayType01 := (0.467 ns, 0.861 ns);
-      tpd_i6_q                       :	VitalDelayType01 := (0.426 ns, 0.748 ns);
-      tpd_i7_q                       :	VitalDelayType01 := (0.346 ns, 0.800 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      i4                             :	in    STD_ULOGIC;
-      i5                             :	in    STD_ULOGIC;
-      i6                             :	in    STD_ULOGIC;
-      i7                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component oa2a2a2a24_x4 -----
-component oa2a2a2a24_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_q                       :	VitalDelayType01 := (0.823 ns, 0.879 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.955 ns, 0.835 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.726 ns, 0.940 ns);
-      tpd_i3_q                       :	VitalDelayType01 := (0.851 ns, 0.895 ns);
-      tpd_i4_q                       :	VitalDelayType01 := (0.619 ns, 0.902 ns);
-      tpd_i5_q                       :	VitalDelayType01 := (0.515 ns, 0.949 ns);
-      tpd_i6_q                       :	VitalDelayType01 := (0.487 ns, 0.845 ns);
-      tpd_i7_q                       :	VitalDelayType01 := (0.399 ns, 0.895 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      i4                             :	in    STD_ULOGIC;
-      i5                             :	in    STD_ULOGIC;
-      i6                             :	in    STD_ULOGIC;
-      i7                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component oa2a2a23_x2 -----
-component oa2a2a23_x2
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_q                       :	VitalDelayType01 := (0.653 ns, 0.578 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.775 ns, 0.542 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.441 ns, 0.639 ns);
-      tpd_i3_q                       :	VitalDelayType01 := (0.540 ns, 0.600 ns);
-      tpd_i4_q                       :	VitalDelayType01 := (0.402 ns, 0.591 ns);
-      tpd_i5_q                       :	VitalDelayType01 := (0.321 ns, 0.636 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      i4                             :	in    STD_ULOGIC;
-      i5                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component oa2a2a23_x4 -----
-component oa2a2a23_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_q                       :	VitalDelayType01 := (0.699 ns, 0.648 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.822 ns, 0.613 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.493 ns, 0.715 ns);
-      tpd_i3_q                       :	VitalDelayType01 := (0.594 ns, 0.677 ns);
-      tpd_i4_q                       :	VitalDelayType01 := (0.464 ns, 0.673 ns);
-      tpd_i5_q                       :	VitalDelayType01 := (0.379 ns, 0.714 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      i4                             :	in    STD_ULOGIC;
-      i5                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component oa2a22_x2 -----
-component oa2a22_x2
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_q                       :	VitalDelayType01 := (0.403 ns, 0.564 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.495 ns, 0.534 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.646 ns, 0.487 ns);
-      tpd_i3_q                       :	VitalDelayType01 := (0.537 ns, 0.512 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component oa2a22_x4 -----
-component oa2a22_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_q                       :	VitalDelayType01 := (0.519 ns, 0.696 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.624 ns, 0.669 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.763 ns, 0.596 ns);
-      tpd_i3_q                       :	VitalDelayType01 := (0.644 ns, 0.619 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component oa2ao222_x2 -----
-component oa2ao222_x2
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_q                       :	VitalDelayType01 := (0.495 ns, 0.581 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.598 ns, 0.539 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.464 ns, 0.604 ns);
-      tpd_i3_q                       :	VitalDelayType01 := (0.556 ns, 0.578 ns);
-      tpd_i4_q                       :	VitalDelayType01 := (0.558 ns, 0.453 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      i4                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component oa2ao222_x4 -----
-component oa2ao222_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_q                       :	VitalDelayType01 := (0.553 ns, 0.657 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.662 ns, 0.616 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.552 ns, 0.693 ns);
-      tpd_i3_q                       :	VitalDelayType01 := (0.640 ns, 0.660 ns);
-      tpd_i4_q                       :	VitalDelayType01 := (0.656 ns, 0.529 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      i4                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component oa3ao322_x2 -----
-component oa3ao322_x2
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_q                       :	VitalDelayType01 := (0.638 ns, 0.820 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.735 ns, 0.764 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.806 ns, 0.707 ns);
-      tpd_i3_q                       :	VitalDelayType01 := (0.560 ns, 0.765 ns);
-      tpd_i4_q                       :	VitalDelayType01 := (0.649 ns, 0.760 ns);
-      tpd_i5_q                       :	VitalDelayType01 := (0.734 ns, 0.734 ns);
-      tpd_i6_q                       :	VitalDelayType01 := (0.563 ns, 0.540 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      i4                             :	in    STD_ULOGIC;
-      i5                             :	in    STD_ULOGIC;
-      i6                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component oa3ao322_x4 -----
-component oa3ao322_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_q                       :	VitalDelayType01 := (0.717 ns, 0.946 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.818 ns, 0.890 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.894 ns, 0.834 ns);
-      tpd_i3_q                       :	VitalDelayType01 := (0.673 ns, 0.898 ns);
-      tpd_i4_q                       :	VitalDelayType01 := (0.758 ns, 0.896 ns);
-      tpd_i5_q                       :	VitalDelayType01 := (0.839 ns, 0.865 ns);
-      tpd_i6_q                       :	VitalDelayType01 := (0.684 ns, 0.651 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      i3                             :	in    STD_ULOGIC;
-      i4                             :	in    STD_ULOGIC;
-      i5                             :	in    STD_ULOGIC;
-      i6                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component oa22_x2 -----
-component oa22_x2
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_q                       :	VitalDelayType01 := (0.390 ns, 0.555 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.488 ns, 0.525 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.438 ns, 0.454 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component oa22_x4 -----
-component oa22_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_q                       :	VitalDelayType01 := (0.511 ns, 0.677 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.615 ns, 0.650 ns);
-      tpd_i2_q                       :	VitalDelayType01 := (0.523 ns, 0.571 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      i2                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component on12_x1 -----
-component on12_x1
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_q                       :	VitalDelayType01 := (0.111 ns, 0.234 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.314 ns, 0.291 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component on12_x4 -----
-component on12_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_q                       :	VitalDelayType01 := (0.474 ns, 0.499 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.491 ns, 0.394 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component one_x0 -----
-component one_x0
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn);
-
--- synopsys translate_on
-   port(
-      q                              :	out   STD_ULOGIC := '1');
-end component;
-
-
------ Component sff1_x4 -----
-component sff1_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_ck_q                       :	VitalDelayType01 := (0.500 ns, 0.500 ns);
-      tsetup_i_ck                    :	VitalDelayType := 0.585 ns;
-      thold_i_ck                     :	VitalDelayType := 0.000 ns;
-      tipd_i                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_ck                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i                              :	in    STD_ULOGIC;
-      ck                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component sff2_x4 -----
-component sff2_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_ck_q                       :	VitalDelayType01 := (0.500 ns, 0.500 ns);
-      tsetup_i0_ck                   :	VitalDelayType := 0.764 ns;
-      thold_i0_ck                    :	VitalDelayType := 0.000 ns;
-      tsetup_i1_ck                   :	VitalDelayType := 0.764 ns;
-      thold_i1_ck                    :	VitalDelayType := 0.000 ns;
-      tsetup_cmd_ck                  :	VitalDelayType := 0.833 ns;
-      thold_cmd_ck                   :	VitalDelayType := 0.000 ns;
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_cmd                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_ck                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      cmd                            :	in    STD_ULOGIC;
-      ck                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component ts_x4 -----
-component ts_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_cmd_q                      :	VitalDelayType01z := 
-               (0.492 ns, 0.409 ns, 0.492 ns, 0.492 ns, 0.409 ns, 0.409 ns);
-      tpd_i_q                        :	VitalDelayType01 := (0.475 ns, 0.444 ns);
-      tipd_i                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_cmd                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i                              :	in    STD_ULOGIC;
-      cmd                            :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component ts_x8 -----
-component ts_x8
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_cmd_q                      :	VitalDelayType01z := 
-               (0.626 ns, 0.466 ns, 0.626 ns, 0.626 ns, 0.466 ns, 0.466 ns);
-      tpd_i_q                        :	VitalDelayType01 := (0.613 ns, 0.569 ns);
-      tipd_i                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_cmd                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i                              :	in    STD_ULOGIC;
-      cmd                            :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component xr2_x1 -----
-component xr2_x1
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_q                       :	VitalDelayType01 := (0.292 ns, 0.293 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.377 ns, 0.261 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component xr2_x4 -----
-component xr2_x4
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn;
-      tpd_i0_q                       :	VitalDelayType01 := (0.521 ns, 0.560 ns);
-      tpd_i1_q                       :	VitalDelayType01 := (0.541 ns, 0.657 ns);
-      tipd_i0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
-      tipd_i1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_ULOGIC;
-      i1                             :	in    STD_ULOGIC;
-      q                              :	out   STD_ULOGIC);
-end component;
-
-
------ Component zero_x0 -----
-component zero_x0
--- synopsys translate_off
-   generic(
-      TimingChecksOn: Boolean := DefaultTimingChecksOn;
-      InstancePath: STRING := "*";
-      Xon: Boolean := DefaultXon;
-      MsgOn: Boolean := DefaultMsgOn);
-
--- synopsys translate_on
-   port(
-      nq                             :	out   STD_ULOGIC := '0');
-end component;
-
-
-end VCOMPONENTS;
-
----- end of VITAL components library ----
diff --git a/alliance/share/cells/sxlib/sxlib_Vtables.vhd b/alliance/share/cells/sxlib/sxlib_Vtables.vhd
deleted file mode 100644
index 85db0e88..00000000
--- a/alliance/share/cells/sxlib/sxlib_Vtables.vhd
+++ /dev/null
@@ -1,58 +0,0 @@
-
-----------------------------------------------------------------
--- 
--- Created by the Synopsys Library Compiler 1999.10
--- FILENAME     :    sxlib_Vtables.vhd
--- FILE CONTENTS:    VITAL Table Package
--- DATE CREATED :    Mon May  7 10:19:50 2001
--- 
--- LIBRARY      :    sxlib
--- DATE ENTERED :    Thu Dec 21 11:24:55 MET 2000
--- REVISION     :    1.200000
--- TECHNOLOGY   :    cmos
--- TIME SCALE   :    1 ns
--- LOGIC SYSTEM :    IEEE-1164
--- NOTES        :    
--- HISTORY      :
--- 
-----------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
--- synopsys translate_off
-
-library IEEE;
-use IEEE.VITAL_Timing.all;
-use IEEE.VITAL_Primitives.all;
--- synopsys translate_on
-
-package VTABLES is
-
-   CONSTANT L : VitalTableSymbolType := '0';
-   CONSTANT H : VitalTableSymbolType := '1';
-   CONSTANT x : VitalTableSymbolType := '-';
-   CONSTANT S : VitalTableSymbolType := 'S';
-   CONSTANT R : VitalTableSymbolType := '/';
-   CONSTANT U : VitalTableSymbolType := 'X';
-   CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-
-   CONSTANT sff1_x4_q_tab : VitalStateTableType := (
-    ( L,  L,  H,  x,  L ),
-    ( L,  H,  H,  x,  H ),
-    ( H,  x,  x,  x,  S ),
-    ( x,  x,  L,  x,  S ));
-
-   CONSTANT sff2_x4_q_tab : VitalStateTableType := (
-    ( L,  L,  L,  x,  H,  x,  L ),
-    ( L,  L,  x,  H,  H,  x,  L ),
-    ( L,  H,  H,  x,  H,  x,  H ),
-    ( L,  H,  x,  H,  H,  x,  H ),
-    ( L,  x,  L,  L,  H,  x,  L ),
-    ( L,  x,  H,  L,  H,  x,  H ),
-    ( H,  x,  x,  x,  x,  x,  S ),
-    ( x,  x,  x,  x,  L,  x,  S ));
-
-
-end VTABLES;
-
----- end of VITAL tables library ----
diff --git a/alliance/share/cells/sxlib/sxlib_components.vhd b/alliance/share/cells/sxlib/sxlib_components.vhd
deleted file mode 100644
index 0978efc2..00000000
--- a/alliance/share/cells/sxlib/sxlib_components.vhd
+++ /dev/null
@@ -1,2677 +0,0 @@
-
-----------------------------------------------------------------
--- 
--- Created by the Synopsys Library Compiler 1999.10
--- FILENAME     :    sxlib_components.vhd
--- FILE CONTENTS:    Component Package
--- DATE CREATED :    Mon May  7 10:19:50 2001
--- 
--- LIBRARY      :    sxlib
--- DATE ENTERED :    Thu Dec 21 11:24:55 MET 2000
--- REVISION     :    1.200000
--- TECHNOLOGY   :    cmos
--- TIME SCALE   :    1 ns
--- LOGIC SYSTEM :    IEEE-1164
--- NOTES        :    
--- HISTORY      :
--- 
-----------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
--- synopsys translate_off
-use IEEE.GS_TYPES.sdt_values_t;
--- synopsys translate_on
-
-package COMPONENTS is
-
-constant Default_Timing_mesg : Boolean := True;
-constant Default_Timing_xgen : Boolean := False;
-
------ Component a2_x2 -----
-component a2_x2
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_q_R                      :	Time := 0.261 ns;
-      tpdi0_q_F                      :	Time := 0.388 ns;
-      tpdi1_q_R                      :	Time := 0.203 ns;
-      tpdi1_q_F                      :	Time := 0.434 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component a2_x4 -----
-component a2_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_q_R                      :	Time := 0.338 ns;
-      tpdi0_q_F                      :	Time := 0.476 ns;
-      tpdi1_q_R                      :	Time := 0.269 ns;
-      tpdi1_q_F                      :	Time := 0.518 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component a3_x2 -----
-component a3_x2
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_q_R                      :	Time := 0.395 ns;
-      tpdi0_q_F                      :	Time := 0.435 ns;
-      tpdi1_q_R                      :	Time := 0.353 ns;
-      tpdi1_q_F                      :	Time := 0.479 ns;
-      tpdi2_q_R                      :	Time := 0.290 ns;
-      tpdi2_q_F                      :	Time := 0.521 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component a3_x4 -----
-component a3_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_q_R                      :	Time := 0.478 ns;
-      tpdi0_q_F                      :	Time := 0.514 ns;
-      tpdi1_q_R                      :	Time := 0.428 ns;
-      tpdi1_q_F                      :	Time := 0.554 ns;
-      tpdi2_q_R                      :	Time := 0.356 ns;
-      tpdi2_q_F                      :	Time := 0.592 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component a4_x2 -----
-component a4_x2
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_q_R                      :	Time := 0.374 ns;
-      tpdi0_q_F                      :	Time := 0.578 ns;
-      tpdi1_q_R                      :	Time := 0.441 ns;
-      tpdi1_q_F                      :	Time := 0.539 ns;
-      tpdi2_q_R                      :	Time := 0.482 ns;
-      tpdi2_q_F                      :	Time := 0.498 ns;
-      tpdi3_q_R                      :	Time := 0.506 ns;
-      tpdi3_q_F                      :	Time := 0.455 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component a4_x4 -----
-component a4_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_q_R                      :	Time := 0.505 ns;
-      tpdi0_q_F                      :	Time := 0.650 ns;
-      tpdi1_q_R                      :	Time := 0.578 ns;
-      tpdi1_q_F                      :	Time := 0.614 ns;
-      tpdi2_q_R                      :	Time := 0.627 ns;
-      tpdi2_q_F                      :	Time := 0.576 ns;
-      tpdi3_q_R                      :	Time := 0.661 ns;
-      tpdi3_q_F                      :	Time := 0.538 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component an12_x1 -----
-component an12_x1
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_q_R                      :	Time := 0.200 ns;
-      tpdi0_q_F                      :	Time := 0.168 ns;
-      tpdi1_q_R                      :	Time := 0.285 ns;
-      tpdi1_q_F                      :	Time := 0.405 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component an12_x4 -----
-component an12_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_q_R                      :	Time := 0.461 ns;
-      tpdi0_q_F                      :	Time := 0.471 ns;
-      tpdi1_q_R                      :	Time := 0.269 ns;
-      tpdi1_q_F                      :	Time := 0.518 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component ao2o22_x2 -----
-component ao2o22_x2
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_q_R                      :	Time := 0.572 ns;
-      tpdi0_q_F                      :	Time := 0.451 ns;
-      tpdi1_q_R                      :	Time := 0.508 ns;
-      tpdi1_q_F                      :	Time := 0.542 ns;
-      tpdi2_q_R                      :	Time := 0.432 ns;
-      tpdi2_q_F                      :	Time := 0.627 ns;
-      tpdi3_q_R                      :	Time := 0.488 ns;
-      tpdi3_q_F                      :	Time := 0.526 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component ao2o22_x4 -----
-component ao2o22_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_q_R                      :	Time := 0.696 ns;
-      tpdi0_q_F                      :	Time := 0.569 ns;
-      tpdi1_q_R                      :	Time := 0.637 ns;
-      tpdi1_q_F                      :	Time := 0.666 ns;
-      tpdi2_q_R                      :	Time := 0.554 ns;
-      tpdi2_q_F                      :	Time := 0.744 ns;
-      tpdi3_q_R                      :	Time := 0.606 ns;
-      tpdi3_q_F                      :	Time := 0.639 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component ao22_x2 -----
-component ao22_x2
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_q_R                      :	Time := 0.558 ns;
-      tpdi0_q_F                      :	Time := 0.447 ns;
-      tpdi1_q_R                      :	Time := 0.493 ns;
-      tpdi1_q_F                      :	Time := 0.526 ns;
-      tpdi2_q_R                      :	Time := 0.420 ns;
-      tpdi2_q_F                      :	Time := 0.425 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component ao22_x4 -----
-component ao22_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_q_R                      :	Time := 0.674 ns;
-      tpdi0_q_F                      :	Time := 0.552 ns;
-      tpdi1_q_R                      :	Time := 0.615 ns;
-      tpdi1_q_F                      :	Time := 0.647 ns;
-      tpdi2_q_R                      :	Time := 0.526 ns;
-      tpdi2_q_F                      :	Time := 0.505 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component buf_x2 -----
-component buf_x2
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi_q_R                       :	Time := 0.409 ns;
-      tpdi_q_F                       :	Time := 0.391 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i                              :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component buf_x4 -----
-component buf_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi_q_R                       :	Time := 0.379 ns;
-      tpdi_q_F                       :	Time := 0.409 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i                              :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component buf_x8 -----
-component buf_x8
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi_q_R                       :	Time := 0.343 ns;
-      tpdi_q_F                       :	Time := 0.396 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i                              :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component inv_x1 -----
-component inv_x1
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi_nq_R                      :	Time := 0.101 ns;
-      tpdi_nq_F                      :	Time := 0.139 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i                              :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component inv_x2 -----
-component inv_x2
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi_nq_R                      :	Time := 0.069 ns;
-      tpdi_nq_F                      :	Time := 0.163 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i                              :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component inv_x4 -----
-component inv_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi_nq_R                      :	Time := 0.071 ns;
-      tpdi_nq_F                      :	Time := 0.143 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i                              :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component inv_x8 -----
-component inv_x8
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi_nq_R                      :	Time := 0.086 ns;
-      tpdi_nq_F                      :	Time := 0.133 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i                              :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component mx2_x2 -----
-component mx2_x2
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdcmd_q_R                     :	Time := 0.484 ns;
-      tpdcmd_q_F                     :	Time := 0.522 ns;
-      tpdi0_q_R                      :	Time := 0.451 ns;
-      tpdi0_q_F                      :	Time := 0.469 ns;
-      tpdi1_q_R                      :	Time := 0.451 ns;
-      tpdi1_q_F                      :	Time := 0.469 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      cmd                            :	in    STD_LOGIC;
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component mx2_x4 -----
-component mx2_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdcmd_q_R                     :	Time := 0.615 ns;
-      tpdcmd_q_F                     :	Time := 0.647 ns;
-      tpdi0_q_R                      :	Time := 0.564 ns;
-      tpdi0_q_F                      :	Time := 0.576 ns;
-      tpdi1_q_R                      :	Time := 0.564 ns;
-      tpdi1_q_F                      :	Time := 0.576 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      cmd                            :	in    STD_LOGIC;
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component mx3_x2 -----
-component mx3_x2
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdcmd0_q_R                    :	Time := 0.573 ns;
-      tpdcmd0_q_F                    :	Time := 0.680 ns;
-      tpdcmd1_q_R                    :	Time := 0.664 ns;
-      tpdcmd1_q_F                    :	Time := 0.817 ns;
-      tpdi0_q_R                      :	Time := 0.538 ns;
-      tpdi0_q_F                      :	Time := 0.658 ns;
-      tpdi1_q_R                      :	Time := 0.654 ns;
-      tpdi1_q_F                      :	Time := 0.808 ns;
-      tpdi2_q_R                      :	Time := 0.654 ns;
-      tpdi2_q_F                      :	Time := 0.808 ns;
-      twdcmd0_R                      :	Time := 0.000 ns;
-      twdcmd0_F                      :	Time := 0.000 ns;
-      twdcmd1_R                      :	Time := 0.000 ns;
-      twdcmd1_F                      :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      cmd0                           :	in    STD_LOGIC;
-      cmd1                           :	in    STD_LOGIC;
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component mx3_x4 -----
-component mx3_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdcmd0_q_R                    :	Time := 0.683 ns;
-      tpdcmd0_q_F                    :	Time := 0.779 ns;
-      tpdcmd1_q_R                    :	Time := 0.792 ns;
-      tpdcmd1_q_F                    :	Time := 0.967 ns;
-      tpdi0_q_R                      :	Time := 0.640 ns;
-      tpdi0_q_F                      :	Time := 0.774 ns;
-      tpdi1_q_R                      :	Time := 0.770 ns;
-      tpdi1_q_F                      :	Time := 0.948 ns;
-      tpdi2_q_R                      :	Time := 0.770 ns;
-      tpdi2_q_F                      :	Time := 0.948 ns;
-      twdcmd0_R                      :	Time := 0.000 ns;
-      twdcmd0_F                      :	Time := 0.000 ns;
-      twdcmd1_R                      :	Time := 0.000 ns;
-      twdcmd1_F                      :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      cmd0                           :	in    STD_LOGIC;
-      cmd1                           :	in    STD_LOGIC;
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component na2_x1 -----
-component na2_x1
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_nq_R                     :	Time := 0.059 ns;
-      tpdi0_nq_F                     :	Time := 0.288 ns;
-      tpdi1_nq_R                     :	Time := 0.111 ns;
-      tpdi1_nq_F                     :	Time := 0.234 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component na2_x4 -----
-component na2_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_nq_R                     :	Time := 0.412 ns;
-      tpdi0_nq_F                     :	Time := 0.552 ns;
-      tpdi1_nq_R                     :	Time := 0.353 ns;
-      tpdi1_nq_F                     :	Time := 0.601 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component na3_x1 -----
-component na3_x1
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_nq_R                     :	Time := 0.119 ns;
-      tpdi0_nq_F                     :	Time := 0.363 ns;
-      tpdi1_nq_R                     :	Time := 0.171 ns;
-      tpdi1_nq_F                     :	Time := 0.316 ns;
-      tpdi2_nq_R                     :	Time := 0.193 ns;
-      tpdi2_nq_F                     :	Time := 0.265 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component na3_x4 -----
-component na3_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_nq_R                     :	Time := 0.556 ns;
-      tpdi0_nq_F                     :	Time := 0.601 ns;
-      tpdi1_nq_R                     :	Time := 0.460 ns;
-      tpdi1_nq_F                     :	Time := 0.691 ns;
-      tpdi2_nq_R                     :	Time := 0.519 ns;
-      tpdi2_nq_F                     :	Time := 0.647 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component na4_x1 -----
-component na4_x1
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_nq_R                     :	Time := 0.179 ns;
-      tpdi0_nq_F                     :	Time := 0.438 ns;
-      tpdi1_nq_R                     :	Time := 0.237 ns;
-      tpdi1_nq_F                     :	Time := 0.395 ns;
-      tpdi2_nq_R                     :	Time := 0.269 ns;
-      tpdi2_nq_F                     :	Time := 0.350 ns;
-      tpdi3_nq_R                     :	Time := 0.282 ns;
-      tpdi3_nq_F                     :	Time := 0.302 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component na4_x4 -----
-component na4_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_nq_R                     :	Time := 0.578 ns;
-      tpdi0_nq_F                     :	Time := 0.771 ns;
-      tpdi1_nq_R                     :	Time := 0.643 ns;
-      tpdi1_nq_F                     :	Time := 0.731 ns;
-      tpdi2_nq_R                     :	Time := 0.681 ns;
-      tpdi2_nq_F                     :	Time := 0.689 ns;
-      tpdi3_nq_R                     :	Time := 0.703 ns;
-      tpdi3_nq_F                     :	Time := 0.644 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component nao2o22_x1 -----
-component nao2o22_x1
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_nq_R                     :	Time := 0.294 ns;
-      tpdi0_nq_F                     :	Time := 0.226 ns;
-      tpdi1_nq_R                     :	Time := 0.218 ns;
-      tpdi1_nq_F                     :	Time := 0.287 ns;
-      tpdi2_nq_R                     :	Time := 0.237 ns;
-      tpdi2_nq_F                     :	Time := 0.307 ns;
-      tpdi3_nq_R                     :	Time := 0.174 ns;
-      tpdi3_nq_F                     :	Time := 0.382 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component nao2o22_x4 -----
-component nao2o22_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_nq_R                     :	Time := 0.734 ns;
-      tpdi0_nq_F                     :	Time := 0.644 ns;
-      tpdi1_nq_R                     :	Time := 0.666 ns;
-      tpdi1_nq_F                     :	Time := 0.717 ns;
-      tpdi2_nq_R                     :	Time := 0.664 ns;
-      tpdi2_nq_F                     :	Time := 0.721 ns;
-      tpdi3_nq_R                     :	Time := 0.607 ns;
-      tpdi3_nq_F                     :	Time := 0.807 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component nao22_x1 -----
-component nao22_x1
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_nq_R                     :	Time := 0.294 ns;
-      tpdi0_nq_F                     :	Time := 0.226 ns;
-      tpdi1_nq_R                     :	Time := 0.218 ns;
-      tpdi1_nq_F                     :	Time := 0.287 ns;
-      tpdi2_nq_R                     :	Time := 0.165 ns;
-      tpdi2_nq_F                     :	Time := 0.238 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component nao22_x4 -----
-component nao22_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_nq_R                     :	Time := 0.732 ns;
-      tpdi0_nq_F                     :	Time := 0.650 ns;
-      tpdi1_nq_R                     :	Time := 0.664 ns;
-      tpdi1_nq_F                     :	Time := 0.723 ns;
-      tpdi2_nq_R                     :	Time := 0.596 ns;
-      tpdi2_nq_F                     :	Time := 0.636 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component nmx2_x1 -----
-component nmx2_x1
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdcmd_nq_R                    :	Time := 0.218 ns;
-      tpdcmd_nq_F                    :	Time := 0.287 ns;
-      tpdi0_nq_R                     :	Time := 0.217 ns;
-      tpdi0_nq_F                     :	Time := 0.256 ns;
-      tpdi1_nq_R                     :	Time := 0.217 ns;
-      tpdi1_nq_F                     :	Time := 0.256 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      cmd                            :	in    STD_LOGIC;
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component nmx2_x4 -----
-component nmx2_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdcmd_nq_R                    :	Time := 0.632 ns;
-      tpdcmd_nq_F                    :	Time := 0.708 ns;
-      tpdi0_nq_R                     :	Time := 0.610 ns;
-      tpdi0_nq_F                     :	Time := 0.653 ns;
-      tpdi1_nq_R                     :	Time := 0.610 ns;
-      tpdi1_nq_F                     :	Time := 0.653 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      cmd                            :	in    STD_LOGIC;
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component nmx3_x1 -----
-component nmx3_x1
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdcmd0_nq_R                   :	Time := 0.356 ns;
-      tpdcmd0_nq_F                   :	Time := 0.495 ns;
-      tpdcmd1_nq_R                   :	Time := 0.414 ns;
-      tpdcmd1_nq_F                   :	Time := 0.566 ns;
-      tpdi0_nq_R                     :	Time := 0.315 ns;
-      tpdi0_nq_F                     :	Time := 0.441 ns;
-      tpdi1_nq_R                     :	Time := 0.429 ns;
-      tpdi1_nq_F                     :	Time := 0.582 ns;
-      tpdi2_nq_R                     :	Time := 0.429 ns;
-      tpdi2_nq_F                     :	Time := 0.582 ns;
-      twdcmd0_R                      :	Time := 0.000 ns;
-      twdcmd0_F                      :	Time := 0.000 ns;
-      twdcmd1_R                      :	Time := 0.000 ns;
-      twdcmd1_F                      :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      cmd0                           :	in    STD_LOGIC;
-      cmd1                           :	in    STD_LOGIC;
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component nmx3_x4 -----
-component nmx3_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdcmd0_nq_R                   :	Time := 0.790 ns;
-      tpdcmd0_nq_F                   :	Time := 0.936 ns;
-      tpdcmd1_nq_R                   :	Time := 0.866 ns;
-      tpdcmd1_nq_F                   :	Time := 1.048 ns;
-      tpdi0_nq_R                     :	Time := 0.748 ns;
-      tpdi0_nq_F                     :	Time := 0.900 ns;
-      tpdi1_nq_R                     :	Time := 0.869 ns;
-      tpdi1_nq_F                     :	Time := 1.053 ns;
-      tpdi2_nq_R                     :	Time := 0.869 ns;
-      tpdi2_nq_F                     :	Time := 1.053 ns;
-      twdcmd0_R                      :	Time := 0.000 ns;
-      twdcmd0_F                      :	Time := 0.000 ns;
-      twdcmd1_R                      :	Time := 0.000 ns;
-      twdcmd1_F                      :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      cmd0                           :	in    STD_LOGIC;
-      cmd1                           :	in    STD_LOGIC;
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component no2_x1 -----
-component no2_x1
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_nq_R                     :	Time := 0.298 ns;
-      tpdi0_nq_F                     :	Time := 0.121 ns;
-      tpdi1_nq_R                     :	Time := 0.193 ns;
-      tpdi1_nq_F                     :	Time := 0.161 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component no2_x4 -----
-component no2_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_nq_R                     :	Time := 0.618 ns;
-      tpdi0_nq_F                     :	Time := 0.447 ns;
-      tpdi1_nq_R                     :	Time := 0.522 ns;
-      tpdi1_nq_F                     :	Time := 0.504 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component no3_x1 -----
-component no3_x1
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_nq_R                     :	Time := 0.318 ns;
-      tpdi0_nq_F                     :	Time := 0.246 ns;
-      tpdi1_nq_R                     :	Time := 0.215 ns;
-      tpdi1_nq_F                     :	Time := 0.243 ns;
-      tpdi2_nq_R                     :	Time := 0.407 ns;
-      tpdi2_nq_F                     :	Time := 0.192 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component no3_x4 -----
-component no3_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_nq_R                     :	Time := 0.722 ns;
-      tpdi0_nq_F                     :	Time := 0.561 ns;
-      tpdi1_nq_R                     :	Time := 0.638 ns;
-      tpdi1_nq_F                     :	Time := 0.623 ns;
-      tpdi2_nq_R                     :	Time := 0.545 ns;
-      tpdi2_nq_F                     :	Time := 0.640 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component no4_x1 -----
-component no4_x1
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_nq_R                     :	Time := 0.330 ns;
-      tpdi0_nq_F                     :	Time := 0.340 ns;
-      tpdi1_nq_R                     :	Time := 0.230 ns;
-      tpdi1_nq_F                     :	Time := 0.320 ns;
-      tpdi2_nq_R                     :	Time := 0.419 ns;
-      tpdi2_nq_F                     :	Time := 0.333 ns;
-      tpdi3_nq_R                     :	Time := 0.499 ns;
-      tpdi3_nq_F                     :	Time := 0.271 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component no4_x4 -----
-component no4_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_nq_R                     :	Time := 0.656 ns;
-      tpdi0_nq_F                     :	Time := 0.777 ns;
-      tpdi1_nq_R                     :	Time := 0.564 ns;
-      tpdi1_nq_F                     :	Time := 0.768 ns;
-      tpdi2_nq_R                     :	Time := 0.739 ns;
-      tpdi2_nq_F                     :	Time := 0.761 ns;
-      tpdi3_nq_R                     :	Time := 0.816 ns;
-      tpdi3_nq_F                     :	Time := 0.693 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component noa2a2a2a24_x1 -----
-component noa2a2a2a24_x1
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_nq_R                     :	Time := 0.649 ns;
-      tpdi0_nq_F                     :	Time := 0.606 ns;
-      tpdi1_nq_R                     :	Time := 0.775 ns;
-      tpdi1_nq_F                     :	Time := 0.562 ns;
-      tpdi2_nq_R                     :	Time := 0.550 ns;
-      tpdi2_nq_F                     :	Time := 0.662 ns;
-      tpdi3_nq_R                     :	Time := 0.667 ns;
-      tpdi3_nq_F                     :	Time := 0.616 ns;
-      tpdi4_nq_R                     :	Time := 0.419 ns;
-      tpdi4_nq_F                     :	Time := 0.613 ns;
-      tpdi5_nq_R                     :	Time := 0.329 ns;
-      tpdi5_nq_F                     :	Time := 0.662 ns;
-      tpdi6_nq_R                     :	Time := 0.270 ns;
-      tpdi6_nq_F                     :	Time := 0.535 ns;
-      tpdi7_nq_R                     :	Time := 0.200 ns;
-      tpdi7_nq_F                     :	Time := 0.591 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns;
-      twdi6_R                        :	Time := 0.000 ns;
-      twdi6_F                        :	Time := 0.000 ns;
-      twdi7_R                        :	Time := 0.000 ns;
-      twdi7_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      i6                             :	in    STD_LOGIC;
-      i7                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component noa2a2a2a24_x4 -----
-component noa2a2a2a24_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_nq_R                     :	Time := 0.966 ns;
-      tpdi0_nq_F                     :	Time := 1.049 ns;
-      tpdi1_nq_R                     :	Time := 1.097 ns;
-      tpdi1_nq_F                     :	Time := 1.005 ns;
-      tpdi2_nq_R                     :	Time := 0.867 ns;
-      tpdi2_nq_F                     :	Time := 1.106 ns;
-      tpdi3_nq_R                     :	Time := 0.990 ns;
-      tpdi3_nq_F                     :	Time := 1.061 ns;
-      tpdi4_nq_R                     :	Time := 0.748 ns;
-      tpdi4_nq_F                     :	Time := 1.061 ns;
-      tpdi5_nq_R                     :	Time := 0.649 ns;
-      tpdi5_nq_F                     :	Time := 1.109 ns;
-      tpdi6_nq_R                     :	Time := 0.606 ns;
-      tpdi6_nq_F                     :	Time := 0.999 ns;
-      tpdi7_nq_R                     :	Time := 0.525 ns;
-      tpdi7_nq_F                     :	Time := 1.052 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns;
-      twdi6_R                        :	Time := 0.000 ns;
-      twdi6_F                        :	Time := 0.000 ns;
-      twdi7_R                        :	Time := 0.000 ns;
-      twdi7_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      i6                             :	in    STD_LOGIC;
-      i7                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component noa2a2a23_x1 -----
-component noa2a2a23_x1
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_nq_R                     :	Time := 0.525 ns;
-      tpdi0_nq_F                     :	Time := 0.425 ns;
-      tpdi1_nq_R                     :	Time := 0.643 ns;
-      tpdi1_nq_F                     :	Time := 0.388 ns;
-      tpdi2_nq_R                     :	Time := 0.307 ns;
-      tpdi2_nq_F                     :	Time := 0.479 ns;
-      tpdi3_nq_R                     :	Time := 0.398 ns;
-      tpdi3_nq_F                     :	Time := 0.438 ns;
-      tpdi4_nq_R                     :	Time := 0.250 ns;
-      tpdi4_nq_F                     :	Time := 0.416 ns;
-      tpdi5_nq_R                     :	Time := 0.178 ns;
-      tpdi5_nq_F                     :	Time := 0.464 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component noa2a2a23_x4 -----
-component noa2a2a23_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_nq_R                     :	Time := 0.834 ns;
-      tpdi0_nq_F                     :	Time := 0.814 ns;
-      tpdi1_nq_R                     :	Time := 0.955 ns;
-      tpdi1_nq_F                     :	Time := 0.778 ns;
-      tpdi2_nq_R                     :	Time := 0.620 ns;
-      tpdi2_nq_F                     :	Time := 0.873 ns;
-      tpdi3_nq_R                     :	Time := 0.716 ns;
-      tpdi3_nq_F                     :	Time := 0.833 ns;
-      tpdi4_nq_R                     :	Time := 0.574 ns;
-      tpdi4_nq_F                     :	Time := 0.819 ns;
-      tpdi5_nq_R                     :	Time := 0.496 ns;
-      tpdi5_nq_F                     :	Time := 0.865 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component noa2a22_x1 -----
-component noa2a22_x1
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_nq_R                     :	Time := 0.151 ns;
-      tpdi0_nq_F                     :	Time := 0.327 ns;
-      tpdi1_nq_R                     :	Time := 0.218 ns;
-      tpdi1_nq_F                     :	Time := 0.287 ns;
-      tpdi2_nq_R                     :	Time := 0.284 ns;
-      tpdi2_nq_F                     :	Time := 0.289 ns;
-      tpdi3_nq_R                     :	Time := 0.372 ns;
-      tpdi3_nq_F                     :	Time := 0.256 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component noa2a22_x4 -----
-component noa2a22_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_nq_R                     :	Time := 0.562 ns;
-      tpdi0_nq_F                     :	Time := 0.745 ns;
-      tpdi1_nq_R                     :	Time := 0.646 ns;
-      tpdi1_nq_F                     :	Time := 0.714 ns;
-      tpdi2_nq_R                     :	Time := 0.701 ns;
-      tpdi2_nq_F                     :	Time := 0.703 ns;
-      tpdi3_nq_R                     :	Time := 0.805 ns;
-      tpdi3_nq_F                     :	Time := 0.677 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component noa2ao222_x1 -----
-component noa2ao222_x1
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_nq_R                     :	Time := 0.348 ns;
-      tpdi0_nq_F                     :	Time := 0.422 ns;
-      tpdi1_nq_R                     :	Time := 0.440 ns;
-      tpdi1_nq_F                     :	Time := 0.378 ns;
-      tpdi2_nq_R                     :	Time := 0.186 ns;
-      tpdi2_nq_F                     :	Time := 0.473 ns;
-      tpdi3_nq_R                     :	Time := 0.256 ns;
-      tpdi3_nq_F                     :	Time := 0.459 ns;
-      tpdi4_nq_R                     :	Time := 0.240 ns;
-      tpdi4_nq_F                     :	Time := 0.309 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component noa2ao222_x4 -----
-component noa2ao222_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_nq_R                     :	Time := 0.684 ns;
-      tpdi0_nq_F                     :	Time := 0.801 ns;
-      tpdi1_nq_R                     :	Time := 0.780 ns;
-      tpdi1_nq_F                     :	Time := 0.758 ns;
-      tpdi2_nq_R                     :	Time := 0.638 ns;
-      tpdi2_nq_F                     :	Time := 0.809 ns;
-      tpdi3_nq_R                     :	Time := 0.732 ns;
-      tpdi3_nq_F                     :	Time := 0.795 ns;
-      tpdi4_nq_R                     :	Time := 0.718 ns;
-      tpdi4_nq_F                     :	Time := 0.664 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component noa3ao322_x1 -----
-component noa3ao322_x1
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_nq_R                     :	Time := 0.396 ns;
-      tpdi0_nq_F                     :	Time := 0.616 ns;
-      tpdi1_nq_R                     :	Time := 0.486 ns;
-      tpdi1_nq_F                     :	Time := 0.552 ns;
-      tpdi2_nq_R                     :	Time := 0.546 ns;
-      tpdi2_nq_F                     :	Time := 0.488 ns;
-      tpdi3_nq_R                     :	Time := 0.196 ns;
-      tpdi3_nq_F                     :	Time := 0.599 ns;
-      tpdi4_nq_R                     :	Time := 0.264 ns;
-      tpdi4_nq_F                     :	Time := 0.608 ns;
-      tpdi5_nq_R                     :	Time := 0.328 ns;
-      tpdi5_nq_F                     :	Time := 0.581 ns;
-      tpdi6_nq_R                     :	Time := 0.246 ns;
-      tpdi6_nq_F                     :	Time := 0.311 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns;
-      twdi6_R                        :	Time := 0.000 ns;
-      twdi6_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      i6                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component noa3ao322_x4 -----
-component noa3ao322_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_nq_R                     :	Time := 0.819 ns;
-      tpdi0_nq_F                     :	Time := 0.987 ns;
-      tpdi1_nq_R                     :	Time := 0.914 ns;
-      tpdi1_nq_F                     :	Time := 0.931 ns;
-      tpdi2_nq_R                     :	Time := 0.990 ns;
-      tpdi2_nq_F                     :	Time := 0.874 ns;
-      tpdi3_nq_R                     :	Time := 0.729 ns;
-      tpdi3_nq_F                     :	Time := 0.926 ns;
-      tpdi4_nq_R                     :	Time := 0.821 ns;
-      tpdi4_nq_F                     :	Time := 0.924 ns;
-      tpdi5_nq_R                     :	Time := 0.907 ns;
-      tpdi5_nq_F                     :	Time := 0.900 ns;
-      tpdi6_nq_R                     :	Time := 0.738 ns;
-      tpdi6_nq_F                     :	Time := 0.718 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns;
-      twdi6_R                        :	Time := 0.000 ns;
-      twdi6_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      i6                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component noa22_x1 -----
-component noa22_x1
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_nq_R                     :	Time := 0.151 ns;
-      tpdi0_nq_F                     :	Time := 0.327 ns;
-      tpdi1_nq_R                     :	Time := 0.218 ns;
-      tpdi1_nq_F                     :	Time := 0.287 ns;
-      tpdi2_nq_R                     :	Time := 0.218 ns;
-      tpdi2_nq_F                     :	Time := 0.241 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component noa22_x4 -----
-component noa22_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_nq_R                     :	Time := 0.550 ns;
-      tpdi0_nq_F                     :	Time := 0.740 ns;
-      tpdi1_nq_R                     :	Time := 0.643 ns;
-      tpdi1_nq_F                     :	Time := 0.709 ns;
-      tpdi2_nq_R                     :	Time := 0.610 ns;
-      tpdi2_nq_F                     :	Time := 0.646 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component nts_x1 -----
-component nts_x1
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdcmd_nq_R                    :	Time := 0.249 ns;
-      tpdcmd_nq_F                    :	Time := 0.041 ns;
-      tpdcmd_nq_LZ                   :	Time := 0.249 ns;
-      tpdcmd_nq_HZ                   :	Time := 0.041 ns;
-      tpdi_nq_R                      :	Time := 0.169 ns;
-      tpdi_nq_F                      :	Time := 0.201 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i                              :	in    STD_LOGIC;
-      cmd                            :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component nts_x2 -----
-component nts_x2
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdcmd_nq_R                    :	Time := 0.330 ns;
-      tpdcmd_nq_F                    :	Time := 0.033 ns;
-      tpdcmd_nq_LZ                   :	Time := 0.330 ns;
-      tpdcmd_nq_HZ                   :	Time := 0.033 ns;
-      tpdi_nq_R                      :	Time := 0.167 ns;
-      tpdi_nq_F                      :	Time := 0.201 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i                              :	in    STD_LOGIC;
-      cmd                            :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component nxr2_x1 -----
-component nxr2_x1
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_nq_R                     :	Time := 0.288 ns;
-      tpdi0_nq_F                     :	Time := 0.293 ns;
-      tpdi1_nq_R                     :	Time := 0.156 ns;
-      tpdi1_nq_F                     :	Time := 0.327 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component nxr2_x4 -----
-component nxr2_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_nq_R                     :	Time := 0.522 ns;
-      tpdi0_nq_F                     :	Time := 0.553 ns;
-      tpdi1_nq_R                     :	Time := 0.553 ns;
-      tpdi1_nq_F                     :	Time := 0.542 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      nq                             :	out   STD_LOGIC);
-end component;
-
-
------ Component o2_x2 -----
-component o2_x2
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_q_R                      :	Time := 0.406 ns;
-      tpdi0_q_F                      :	Time := 0.310 ns;
-      tpdi1_q_R                      :	Time := 0.335 ns;
-      tpdi1_q_F                      :	Time := 0.364 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component o2_x4 -----
-component o2_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_q_R                      :	Time := 0.491 ns;
-      tpdi0_q_F                      :	Time := 0.394 ns;
-      tpdi1_q_R                      :	Time := 0.427 ns;
-      tpdi1_q_F                      :	Time := 0.464 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component o3_x2 -----
-component o3_x2
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_q_R                      :	Time := 0.494 ns;
-      tpdi0_q_F                      :	Time := 0.407 ns;
-      tpdi1_q_R                      :	Time := 0.430 ns;
-      tpdi1_q_F                      :	Time := 0.482 ns;
-      tpdi2_q_R                      :	Time := 0.360 ns;
-      tpdi2_q_F                      :	Time := 0.506 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component o3_x4 -----
-component o3_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_q_R                      :	Time := 0.569 ns;
-      tpdi0_q_F                      :	Time := 0.501 ns;
-      tpdi1_q_R                      :	Time := 0.510 ns;
-      tpdi1_q_F                      :	Time := 0.585 ns;
-      tpdi2_q_R                      :	Time := 0.447 ns;
-      tpdi2_q_F                      :	Time := 0.622 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component o4_x2 -----
-component o4_x2
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_q_R                      :	Time := 0.508 ns;
-      tpdi0_q_F                      :	Time := 0.601 ns;
-      tpdi1_q_R                      :	Time := 0.446 ns;
-      tpdi1_q_F                      :	Time := 0.631 ns;
-      tpdi2_q_R                      :	Time := 0.567 ns;
-      tpdi2_q_F                      :	Time := 0.531 ns;
-      tpdi3_q_R                      :	Time := 0.378 ns;
-      tpdi3_q_F                      :	Time := 0.626 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component o4_x4 -----
-component o4_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_q_R                      :	Time := 0.574 ns;
-      tpdi0_q_F                      :	Time := 0.638 ns;
-      tpdi1_q_R                      :	Time := 0.492 ns;
-      tpdi1_q_F                      :	Time := 0.650 ns;
-      tpdi2_q_R                      :	Time := 0.649 ns;
-      tpdi2_q_F                      :	Time := 0.611 ns;
-      tpdi3_q_R                      :	Time := 0.721 ns;
-      tpdi3_q_F                      :	Time := 0.536 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component oa2a2a2a24_x2 -----
-component oa2a2a2a24_x2
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_q_R                      :	Time := 0.780 ns;
-      tpdi0_q_F                      :	Time := 0.797 ns;
-      tpdi1_q_R                      :	Time := 0.909 ns;
-      tpdi1_q_F                      :	Time := 0.753 ns;
-      tpdi2_q_R                      :	Time := 0.682 ns;
-      tpdi2_q_F                      :	Time := 0.856 ns;
-      tpdi3_q_R                      :	Time := 0.803 ns;
-      tpdi3_q_F                      :	Time := 0.810 ns;
-      tpdi4_q_R                      :	Time := 0.565 ns;
-      tpdi4_q_F                      :	Time := 0.813 ns;
-      tpdi5_q_R                      :	Time := 0.467 ns;
-      tpdi5_q_F                      :	Time := 0.861 ns;
-      tpdi6_q_R                      :	Time := 0.426 ns;
-      tpdi6_q_F                      :	Time := 0.748 ns;
-      tpdi7_q_R                      :	Time := 0.346 ns;
-      tpdi7_q_F                      :	Time := 0.800 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns;
-      twdi6_R                        :	Time := 0.000 ns;
-      twdi6_F                        :	Time := 0.000 ns;
-      twdi7_R                        :	Time := 0.000 ns;
-      twdi7_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      i6                             :	in    STD_LOGIC;
-      i7                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component oa2a2a2a24_x4 -----
-component oa2a2a2a24_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_q_R                      :	Time := 0.823 ns;
-      tpdi0_q_F                      :	Time := 0.879 ns;
-      tpdi1_q_R                      :	Time := 0.955 ns;
-      tpdi1_q_F                      :	Time := 0.835 ns;
-      tpdi2_q_R                      :	Time := 0.726 ns;
-      tpdi2_q_F                      :	Time := 0.940 ns;
-      tpdi3_q_R                      :	Time := 0.851 ns;
-      tpdi3_q_F                      :	Time := 0.895 ns;
-      tpdi4_q_R                      :	Time := 0.619 ns;
-      tpdi4_q_F                      :	Time := 0.902 ns;
-      tpdi5_q_R                      :	Time := 0.515 ns;
-      tpdi5_q_F                      :	Time := 0.949 ns;
-      tpdi6_q_R                      :	Time := 0.487 ns;
-      tpdi6_q_F                      :	Time := 0.845 ns;
-      tpdi7_q_R                      :	Time := 0.399 ns;
-      tpdi7_q_F                      :	Time := 0.895 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns;
-      twdi6_R                        :	Time := 0.000 ns;
-      twdi6_F                        :	Time := 0.000 ns;
-      twdi7_R                        :	Time := 0.000 ns;
-      twdi7_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      i6                             :	in    STD_LOGIC;
-      i7                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component oa2a2a23_x2 -----
-component oa2a2a23_x2
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_q_R                      :	Time := 0.653 ns;
-      tpdi0_q_F                      :	Time := 0.578 ns;
-      tpdi1_q_R                      :	Time := 0.775 ns;
-      tpdi1_q_F                      :	Time := 0.542 ns;
-      tpdi2_q_R                      :	Time := 0.441 ns;
-      tpdi2_q_F                      :	Time := 0.639 ns;
-      tpdi3_q_R                      :	Time := 0.540 ns;
-      tpdi3_q_F                      :	Time := 0.600 ns;
-      tpdi4_q_R                      :	Time := 0.402 ns;
-      tpdi4_q_F                      :	Time := 0.591 ns;
-      tpdi5_q_R                      :	Time := 0.321 ns;
-      tpdi5_q_F                      :	Time := 0.636 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component oa2a2a23_x4 -----
-component oa2a2a23_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_q_R                      :	Time := 0.699 ns;
-      tpdi0_q_F                      :	Time := 0.648 ns;
-      tpdi1_q_R                      :	Time := 0.822 ns;
-      tpdi1_q_F                      :	Time := 0.613 ns;
-      tpdi2_q_R                      :	Time := 0.493 ns;
-      tpdi2_q_F                      :	Time := 0.715 ns;
-      tpdi3_q_R                      :	Time := 0.594 ns;
-      tpdi3_q_F                      :	Time := 0.677 ns;
-      tpdi4_q_R                      :	Time := 0.464 ns;
-      tpdi4_q_F                      :	Time := 0.673 ns;
-      tpdi5_q_R                      :	Time := 0.379 ns;
-      tpdi5_q_F                      :	Time := 0.714 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component oa2a22_x2 -----
-component oa2a22_x2
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_q_R                      :	Time := 0.403 ns;
-      tpdi0_q_F                      :	Time := 0.564 ns;
-      tpdi1_q_R                      :	Time := 0.495 ns;
-      tpdi1_q_F                      :	Time := 0.534 ns;
-      tpdi2_q_R                      :	Time := 0.646 ns;
-      tpdi2_q_F                      :	Time := 0.487 ns;
-      tpdi3_q_R                      :	Time := 0.537 ns;
-      tpdi3_q_F                      :	Time := 0.512 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component oa2a22_x4 -----
-component oa2a22_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_q_R                      :	Time := 0.519 ns;
-      tpdi0_q_F                      :	Time := 0.696 ns;
-      tpdi1_q_R                      :	Time := 0.624 ns;
-      tpdi1_q_F                      :	Time := 0.669 ns;
-      tpdi2_q_R                      :	Time := 0.763 ns;
-      tpdi2_q_F                      :	Time := 0.596 ns;
-      tpdi3_q_R                      :	Time := 0.644 ns;
-      tpdi3_q_F                      :	Time := 0.619 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component oa2ao222_x2 -----
-component oa2ao222_x2
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_q_R                      :	Time := 0.495 ns;
-      tpdi0_q_F                      :	Time := 0.581 ns;
-      tpdi1_q_R                      :	Time := 0.598 ns;
-      tpdi1_q_F                      :	Time := 0.539 ns;
-      tpdi2_q_R                      :	Time := 0.464 ns;
-      tpdi2_q_F                      :	Time := 0.604 ns;
-      tpdi3_q_R                      :	Time := 0.556 ns;
-      tpdi3_q_F                      :	Time := 0.578 ns;
-      tpdi4_q_R                      :	Time := 0.558 ns;
-      tpdi4_q_F                      :	Time := 0.453 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component oa2ao222_x4 -----
-component oa2ao222_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_q_R                      :	Time := 0.553 ns;
-      tpdi0_q_F                      :	Time := 0.657 ns;
-      tpdi1_q_R                      :	Time := 0.662 ns;
-      tpdi1_q_F                      :	Time := 0.616 ns;
-      tpdi2_q_R                      :	Time := 0.552 ns;
-      tpdi2_q_F                      :	Time := 0.693 ns;
-      tpdi3_q_R                      :	Time := 0.640 ns;
-      tpdi3_q_F                      :	Time := 0.660 ns;
-      tpdi4_q_R                      :	Time := 0.656 ns;
-      tpdi4_q_F                      :	Time := 0.529 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component oa3ao322_x2 -----
-component oa3ao322_x2
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_q_R                      :	Time := 0.638 ns;
-      tpdi0_q_F                      :	Time := 0.820 ns;
-      tpdi1_q_R                      :	Time := 0.735 ns;
-      tpdi1_q_F                      :	Time := 0.764 ns;
-      tpdi2_q_R                      :	Time := 0.806 ns;
-      tpdi2_q_F                      :	Time := 0.707 ns;
-      tpdi3_q_R                      :	Time := 0.560 ns;
-      tpdi3_q_F                      :	Time := 0.765 ns;
-      tpdi4_q_R                      :	Time := 0.649 ns;
-      tpdi4_q_F                      :	Time := 0.760 ns;
-      tpdi5_q_R                      :	Time := 0.734 ns;
-      tpdi5_q_F                      :	Time := 0.734 ns;
-      tpdi6_q_R                      :	Time := 0.563 ns;
-      tpdi6_q_F                      :	Time := 0.540 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns;
-      twdi6_R                        :	Time := 0.000 ns;
-      twdi6_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      i6                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component oa3ao322_x4 -----
-component oa3ao322_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_q_R                      :	Time := 0.717 ns;
-      tpdi0_q_F                      :	Time := 0.946 ns;
-      tpdi1_q_R                      :	Time := 0.818 ns;
-      tpdi1_q_F                      :	Time := 0.890 ns;
-      tpdi2_q_R                      :	Time := 0.894 ns;
-      tpdi2_q_F                      :	Time := 0.834 ns;
-      tpdi3_q_R                      :	Time := 0.673 ns;
-      tpdi3_q_F                      :	Time := 0.898 ns;
-      tpdi4_q_R                      :	Time := 0.758 ns;
-      tpdi4_q_F                      :	Time := 0.896 ns;
-      tpdi5_q_R                      :	Time := 0.839 ns;
-      tpdi5_q_F                      :	Time := 0.865 ns;
-      tpdi6_q_R                      :	Time := 0.684 ns;
-      tpdi6_q_F                      :	Time := 0.651 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns;
-      twdi3_R                        :	Time := 0.000 ns;
-      twdi3_F                        :	Time := 0.000 ns;
-      twdi4_R                        :	Time := 0.000 ns;
-      twdi4_F                        :	Time := 0.000 ns;
-      twdi5_R                        :	Time := 0.000 ns;
-      twdi5_F                        :	Time := 0.000 ns;
-      twdi6_R                        :	Time := 0.000 ns;
-      twdi6_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      i3                             :	in    STD_LOGIC;
-      i4                             :	in    STD_LOGIC;
-      i5                             :	in    STD_LOGIC;
-      i6                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component oa22_x2 -----
-component oa22_x2
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_q_R                      :	Time := 0.390 ns;
-      tpdi0_q_F                      :	Time := 0.555 ns;
-      tpdi1_q_R                      :	Time := 0.488 ns;
-      tpdi1_q_F                      :	Time := 0.525 ns;
-      tpdi2_q_R                      :	Time := 0.438 ns;
-      tpdi2_q_F                      :	Time := 0.454 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component oa22_x4 -----
-component oa22_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_q_R                      :	Time := 0.511 ns;
-      tpdi0_q_F                      :	Time := 0.677 ns;
-      tpdi1_q_R                      :	Time := 0.615 ns;
-      tpdi1_q_F                      :	Time := 0.650 ns;
-      tpdi2_q_R                      :	Time := 0.523 ns;
-      tpdi2_q_F                      :	Time := 0.571 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdi2_R                        :	Time := 0.000 ns;
-      twdi2_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      i2                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component on12_x1 -----
-component on12_x1
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_q_R                      :	Time := 0.111 ns;
-      tpdi0_q_F                      :	Time := 0.234 ns;
-      tpdi1_q_R                      :	Time := 0.314 ns;
-      tpdi1_q_F                      :	Time := 0.291 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component on12_x4 -----
-component on12_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_q_R                      :	Time := 0.474 ns;
-      tpdi0_q_F                      :	Time := 0.499 ns;
-      tpdi1_q_R                      :	Time := 0.491 ns;
-      tpdi1_q_F                      :	Time := 0.394 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component one_x0 -----
-component one_x0
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen);
-
--- synopsys translate_on
-   port(
-      q                              :	out   STD_LOGIC := '1');
-end component;
-
-
------ Component sff1_x4 -----
-component sff1_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdck_q_R                      :	Time := 0.500 ns;
-      tpdck_q_F                      :	Time := 0.500 ns;
-      tsui_ck                        :	Time := 0.585 ns;
-      thck_i                         :	Time := 0.000 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns;
-      twdck_R                        :	Time := 0.000 ns;
-      twdck_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i                              :	in    STD_LOGIC;
-      ck                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component sff2_x4 -----
-component sff2_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdck_q_R                      :	Time := 0.500 ns;
-      tpdck_q_F                      :	Time := 0.500 ns;
-      tsui0_ck                       :	Time := 0.764 ns;
-      thck_i0                        :	Time := 0.000 ns;
-      tsui1_ck                       :	Time := 0.764 ns;
-      thck_i1                        :	Time := 0.000 ns;
-      tsucmd_ck                      :	Time := 0.833 ns;
-      thck_cmd                       :	Time := 0.000 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns;
-      twdck_R                        :	Time := 0.000 ns;
-      twdck_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      cmd                            :	in    STD_LOGIC;
-      ck                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component ts_x4 -----
-component ts_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdcmd_q_R                     :	Time := 0.492 ns;
-      tpdcmd_q_F                     :	Time := 0.409 ns;
-      tpdcmd_q_LZ                    :	Time := 0.492 ns;
-      tpdcmd_q_HZ                    :	Time := 0.409 ns;
-      tpdi_q_R                       :	Time := 0.475 ns;
-      tpdi_q_F                       :	Time := 0.444 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i                              :	in    STD_LOGIC;
-      cmd                            :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component ts_x8 -----
-component ts_x8
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdcmd_q_R                     :	Time := 0.626 ns;
-      tpdcmd_q_F                     :	Time := 0.466 ns;
-      tpdcmd_q_LZ                    :	Time := 0.626 ns;
-      tpdcmd_q_HZ                    :	Time := 0.466 ns;
-      tpdi_q_R                       :	Time := 0.613 ns;
-      tpdi_q_F                       :	Time := 0.569 ns;
-      twdi_R                         :	Time := 0.000 ns;
-      twdi_F                         :	Time := 0.000 ns;
-      twdcmd_R                       :	Time := 0.000 ns;
-      twdcmd_F                       :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i                              :	in    STD_LOGIC;
-      cmd                            :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component xr2_x1 -----
-component xr2_x1
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_q_R                      :	Time := 0.292 ns;
-      tpdi0_q_F                      :	Time := 0.293 ns;
-      tpdi1_q_R                      :	Time := 0.377 ns;
-      tpdi1_q_F                      :	Time := 0.261 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component xr2_x4 -----
-component xr2_x4
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen;
-      tpdi0_q_R                      :	Time := 0.521 ns;
-      tpdi0_q_F                      :	Time := 0.560 ns;
-      tpdi1_q_R                      :	Time := 0.541 ns;
-      tpdi1_q_F                      :	Time := 0.657 ns;
-      twdi0_R                        :	Time := 0.000 ns;
-      twdi0_F                        :	Time := 0.000 ns;
-      twdi1_R                        :	Time := 0.000 ns;
-      twdi1_F                        :	Time := 0.000 ns);
-
--- synopsys translate_on
-   port(
-      i0                             :	in    STD_LOGIC;
-      i1                             :	in    STD_LOGIC;
-      q                              :	out   STD_LOGIC);
-end component;
-
-
------ Component zero_x0 -----
-component zero_x0
--- synopsys translate_off
-   generic(
-      Timing_mesg: Boolean := Default_Timing_mesg;
-      Timing_xgen: Boolean := Default_Timing_xgen);
-
--- synopsys translate_on
-   port(
-      nq                             :	out   STD_LOGIC := '0');
-end component;
-
-
-end COMPONENTS;
-
----- end of components library ----
diff --git a/alliance/share/cells/sxlib/tie_x0.al b/alliance/share/cells/sxlib/tie_x0.al
deleted file mode 100644
index 49929218..00000000
--- a/alliance/share/cells/sxlib/tie_x0.al
+++ /dev/null
@@ -1,19 +0,0 @@
-V ALLIANCE : 6
-H tie_x0,L,30/10/99
-C vdd,IN,EXTERNAL,5
-C vss,IN,EXTERNAL,2
-S 7,INTERNAL
-Q 0.000176265
-S 6,INTERNAL
-Q 0.000176265
-S 5,EXTERNAL,vdd
-Q 0.00178498
-S 4,INTERNAL
-Q 0.000176265
-S 3,INTERNAL
-Q 0.000176265
-S 2,EXTERNAL,vss
-Q 0.00178498
-S 1,INTERNAL
-Q 0.000176265
-EOF
diff --git a/alliance/share/cells/sxlib/tie_x0.ap b/alliance/share/cells/sxlib/tie_x0.ap
deleted file mode 100644
index 725bab2b..00000000
--- a/alliance/share/cells/sxlib/tie_x0.ap
+++ /dev/null
@@ -1,16 +0,0 @@
-V ALLIANCE : 6
-H tie_x0,P,30/ 8/2000,100
-A 0,0,1000,5000
-S 500,3000,500,4500,300,*,UP,NTIE
-S 500,500,500,1500,300,*,DOWN,PTIE
-S 0,4700,1000,4700,600,vdd,RIGHT,CALU1
-S 0,3900,1000,3900,2400,*,RIGHT,NWELL
-S 0,300,1000,300,600,vss,RIGHT,CALU1
-V 500,1500,CONT_BODY_P,*
-V 500,1000,CONT_BODY_P,*
-V 500,500,CONT_BODY_P,*
-V 500,3000,CONT_BODY_N,*
-V 500,3500,CONT_BODY_N,*
-V 500,4000,CONT_BODY_N,*
-V 500,4500,CONT_BODY_N,*
-EOF
diff --git a/alliance/share/cells/sxlib/tie_x0.vbe b/alliance/share/cells/sxlib/tie_x0.vbe
deleted file mode 100644
index 133f4326..00000000
--- a/alliance/share/cells/sxlib/tie_x0.vbe
+++ /dev/null
@@ -1,14 +0,0 @@
-ENTITY tie_x0 IS
-PORT (
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END tie_x0;
-
-ARCHITECTURE behaviour_data_flow OF tie_x0 IS
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on tie_x0"
-  SEVERITY WARNING;
-END;
diff --git a/alliance/share/cells/sxlib/tie_x0.vhd b/alliance/share/cells/sxlib/tie_x0.vhd
deleted file mode 100644
index 0049a9c6..00000000
--- a/alliance/share/cells/sxlib/tie_x0.vhd
+++ /dev/null
@@ -1,16 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY tie_x0 IS
-PORT(
-);
-END tie_x0;
-
-ARCHITECTURE RTL OF tie_x0 IS
-BEGIN
-END RTL;
diff --git a/alliance/share/cells/sxlib/ts_x4.al b/alliance/share/cells/sxlib/ts_x4.al
deleted file mode 100644
index a0d92c79..00000000
--- a/alliance/share/cells/sxlib/ts_x4.al
+++ /dev/null
@@ -1,36 +0,0 @@
-V ALLIANCE : 6
-H ts_x4,L,30/10/99
-C cmd,IN,EXTERNAL,7
-C i,IN,EXTERNAL,8
-C q,TRISTATE,EXTERNAL,1
-C vdd,IN,EXTERNAL,5
-C vss,IN,EXTERNAL,3
-T P,0.35,2.9,2,7,5,0,0.75,0.75,7.3,7.3,5.4,12.75,tr_00012
-T P,0.35,5.9,1,6,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00011
-T P,0.35,2.9,6,8,5,0,0.75,0.75,7.3,7.3,13.2,11.25,tr_00010
-T P,0.35,2.9,6,2,4,0,0.75,0.75,7.3,7.3,9.6,11.25,tr_00009
-T P,0.35,2.9,5,7,6,0,0.75,0.75,7.3,7.3,11.4,11.25,tr_00008
-T P,0.35,5.9,5,6,1,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00007
-T N,0.35,2.9,1,4,3,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00006
-T N,0.35,2.9,3,4,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00005
-T N,0.35,1.4,2,7,3,0,0.75,0.75,4.3,4.3,5.4,3,tr_00004
-T N,0.35,1.4,6,7,4,0,0.75,0.75,4.3,4.3,13.2,3,tr_00003
-T N,0.35,1.4,3,2,4,0,0.75,0.75,4.3,4.3,9.6,3,tr_00002
-T N,0.35,1.4,4,8,3,0,0.75,0.75,4.3,4.3,11.4,3,tr_00001
-S 8,EXTERNAL,i
-Q 0.0029371
-S 7,EXTERNAL,cmd
-Q 0.00891222
-S 6,INTERNAL
-Q 0.00768869
-S 5,EXTERNAL,vdd
-Q 0.00692574
-S 4,INTERNAL
-Q 0.00628498
-S 3,EXTERNAL,vss
-Q 0.00616192
-S 2,INTERNAL
-Q 0.00506239
-S 1,EXTERNAL,q
-Q 0.00264397
-EOF
diff --git a/alliance/share/cells/sxlib/ts_x4.ap b/alliance/share/cells/sxlib/ts_x4.ap
deleted file mode 100644
index 7420d780..00000000
--- a/alliance/share/cells/sxlib/ts_x4.ap
+++ /dev/null
@@ -1,136 +0,0 @@
-V ALLIANCE : 6
-H ts_x4,P, 6/ 9/2000,100
-A 0,0,5000,5000
-R 1000,1000,ref_ref,q_10
-R 1000,1500,ref_ref,q_15
-R 1000,2000,ref_ref,q_20
-R 1000,2500,ref_ref,q_25
-R 1000,3000,ref_ref,q_30
-R 1000,3500,ref_ref,q_35
-R 1000,4000,ref_ref,q_40
-R 4000,2000,ref_ref,i_20
-R 4000,2500,ref_ref,i_25
-R 4000,3000,ref_ref,i_30
-R 4000,3500,ref_ref,i_35
-R 4000,1500,ref_ref,i_15
-R 1500,1000,ref_ref,cmd_10
-R 1500,3000,ref_ref,cmd_30
-R 1500,3500,ref_ref,cmd_35
-R 1500,4000,ref_ref,cmd_40
-R 1500,1500,ref_ref,cmd_15
-R 1500,2000,ref_ref,cmd_20
-R 1500,2500,ref_ref,cmd_25
-S 600,2300,4700,2300,100,*,RIGHT,POLY
-S 2300,3100,3200,3100,100,*,RIGHT,POLY
-S 3500,3500,3500,4000,100,*,UP,ALU1
-S 1000,950,1000,4050,200,*,UP,ALU1
-S 2100,4000,2400,4000,200,*,RIGHT,ALU1
-S 300,500,300,1000,200,*,DOWN,ALU1
-S 300,3000,300,4500,200,*,DOWN,ALU1
-S 900,2800,900,4700,300,*,UP,PDIF
-S 1500,2800,1500,4700,300,*,UP,PDIF
-S 1200,2300,1200,2600,100,*,DOWN,POLY
-S 1200,2600,1200,4900,100,*,UP,PTRANS
-S 1900,2800,1900,3000,300,*,UP,POLY
-S 1500,3000,1900,3000,200,*,RIGHT,ALU1
-S 600,2300,600,2600,100,*,UP,POLY
-S 1800,2800,3800,2800,100,*,RIGHT,POLY
-S 3800,2800,3800,3100,100,*,DOWN,POLY
-S 1800,2800,1800,3600,100,*,DOWN,POLY
-S 3400,1800,3400,2700,100,*,DOWN,ALU1
-S 4200,3000,4400,3000,300,*,RIGHT,POLY
-S 4000,3000,4200,3000,200,*,LEFT,ALU1
-S 2700,4700,3500,4700,300,*,RIGHT,NTIE
-S 0,3900,5000,3900,2400,*,LEFT,NWELL
-S 3500,3300,3500,4200,300,*,UP,PDIF
-S 3800,3100,3800,4400,100,*,UP,PTRANS
-S 2900,3300,2900,4200,300,*,UP,PDIF
-S 3200,3100,3200,4400,100,*,UP,PTRANS
-S 4400,1400,4400,1900,100,*,DOWN,POLY
-S 3400,1900,4400,1900,100,*,RIGHT,POLY
-S 600,1900,2900,1900,100,*,RIGHT,POLY
-S 1200,1400,1200,1900,100,*,DOWN,POLY
-S 600,1400,600,1900,100,*,DOWN,POLY
-S 4100,3300,4100,4700,300,*,UP,PDIF
-S 4700,3300,4700,4200,300,*,UP,PDIF
-S 4400,3100,4400,4400,100,*,UP,PTRANS
-S 4100,300,4700,300,300,*,RIGHT,PTIE
-S 2100,300,2900,300,300,*,RIGHT,PTIE
-S 4000,1500,4000,3500,100,*,DOWN,ALU1
-S 300,2800,300,4700,300,*,UP,PDIF
-S 600,2600,600,4900,100,*,UP,PTRANS
-S 3500,400,3500,1200,300,*,UP,NDIF
-S 2900,1000,2900,4000,100,*,DOWN,ALU1
-S 2900,1000,4100,1000,100,*,RIGHT,ALU1
-S 3800,600,3800,1400,100,*,UP,NTRANS
-S 3200,600,3200,1400,100,*,UP,NTRANS
-S 4700,800,4700,1200,300,*,UP,NDIF
-S 4400,600,4400,1400,100,*,UP,NTRANS
-S 2900,800,2900,1200,300,*,UP,NDIF
-S 4100,800,4100,1200,300,*,UP,NDIF
-S 4700,1000,4700,4000,100,*,DOWN,ALU1
-S 3800,1500,4000,1500,300,*,RIGHT,POLY
-S 3500,4000,4700,4000,100,*,RIGHT,ALU1
-S 2100,3800,2100,4700,300,*,UP,PDIF
-S 1800,3600,1800,4900,100,*,UP,PTRANS
-S 1500,1000,1500,4000,100,*,UP,ALU1
-S 0,4700,5000,4700,600,vdd,RIGHT,CALU1
-S 2100,800,2100,1200,300,*,UP,NDIF
-S 1800,600,1800,1400,100,*,UP,NTRANS
-S 300,300,300,1200,300,*,UP,NDIF
-S 1200,100,1200,1400,100,*,UP,NTRANS
-S 600,100,600,1400,100,*,UP,NTRANS
-S 1500,300,1500,1200,300,*,UP,NDIF
-S 900,300,900,1200,300,*,UP,NDIF
-S 0,300,5000,300,600,vss,RIGHT,CALU1
-S 1600,1500,1800,1500,300,*,RIGHT,POLY
-S 1500,1500,1600,1500,100,*,RIGHT,ALU1
-S 2400,1000,2400,4000,100,*,DOWN,ALU1
-S 2300,1400,3200,1400,100,*,RIGHT,POLY
-S 2100,1000,2400,1000,200,*,RIGHT,ALU1
-S 1000,1000,1000,4000,200,q,DOWN,CALU1
-S 4000,1500,4000,3500,200,i,DOWN,CALU1
-S 1500,1000,1500,4000,200,cmd,DOWN,CALU1
-V 2400,3200,CONT_POLY,*
-V 2900,3500,CONT_DIF_P,*
-V 4700,3500,CONT_DIF_P,*
-V 3500,3500,CONT_DIF_P,*
-V 1900,3000,CONT_POLY,*
-V 4200,3000,CONT_POLY,*
-V 3500,4700,CONT_BODY_N,*
-V 2700,4700,CONT_BODY_N,*
-V 4700,2300,CONT_POLY,*
-V 3400,2700,CONT_POLY,*
-V 900,3000,CONT_DIF_P,*
-V 3400,1800,CONT_POLY,*
-V 4700,4700,CONT_BODY_N,*
-V 2100,300,CONT_BODY_P,*
-V 4100,300,CONT_BODY_P,*
-V 4700,300,CONT_BODY_P,*
-V 2900,300,CONT_BODY_P,*
-V 300,1000,CONT_DIF_N,*
-V 900,1000,CONT_DIF_N,*
-V 900,3500,CONT_DIF_P,*
-V 900,4000,CONT_DIF_P,*
-V 300,3000,CONT_DIF_P,*
-V 1500,4500,CONT_DIF_P,*
-V 3500,4000,CONT_DIF_P,*
-V 4100,1000,CONT_DIF_N,*
-V 3500,500,CONT_DIF_N,*
-V 4700,1000,CONT_DIF_N,*
-V 2900,1000,CONT_DIF_N,*
-V 4000,1500,CONT_POLY,*
-V 4100,4500,CONT_DIF_P,*
-V 2900,4000,CONT_DIF_P,*
-V 4700,4000,CONT_DIF_P,*
-V 2100,4000,CONT_DIF_P,*
-V 2100,1000,CONT_DIF_N,*
-V 300,500,CONT_DIF_N,*
-V 1500,500,CONT_DIF_N,*
-V 300,4500,CONT_DIF_P,*
-V 300,3500,CONT_DIF_P,*
-V 300,4000,CONT_DIF_P,*
-V 1600,1500,CONT_POLY,*
-V 2900,1800,CONT_POLY,*
-V 2400,1500,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/sxlib/ts_x4.sym b/alliance/share/cells/sxlib/ts_x4.sym
deleted file mode 100644
index a013224e..00000000
Binary files a/alliance/share/cells/sxlib/ts_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/ts_x4.vbe b/alliance/share/cells/sxlib/ts_x4.vbe
deleted file mode 100644
index 25d28a49..00000000
--- a/alliance/share/cells/sxlib/ts_x4.vbe
+++ /dev/null
@@ -1,37 +0,0 @@
-ENTITY ts_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 2500;
-  CONSTANT cin_cmd	 : NATURAL := 19;
-  CONSTANT cin_i	 : NATURAL := 8;
-  CONSTANT rdown_cmd_q	 : NATURAL := 810;
-  CONSTANT rdown_i_q	 : NATURAL := 810;
-  CONSTANT rup_cmd_q	 : NATURAL := 890;
-  CONSTANT rup_i_q	 : NATURAL := 890;
-  CONSTANT tphl_cmd_q	 : NATURAL := 409;
-  CONSTANT tpll_i_q	 : NATURAL := 444;
-  CONSTANT tphh_i_q	 : NATURAL := 475;
-  CONSTANT tphh_cmd_q	 : NATURAL := 492;
-  CONSTANT transistors	 : NATURAL := 12
-);
-PORT (
-  cmd	 : in  BIT;
-  i	 : in  BIT;
-  q	 : out MUX_BIT BUS;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END ts_x4;
-
-ARCHITECTURE behaviour_data_flow OF ts_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on ts_x4"
-  SEVERITY WARNING;
-
-  label0 : BLOCK (cmd = '1')
-  BEGIN
-    q <= GUARDED i after 1100 ps;
-  END BLOCK label0;
-
-END;
diff --git a/alliance/share/cells/sxlib/ts_x4.vhd b/alliance/share/cells/sxlib/ts_x4.vhd
deleted file mode 100644
index c5c71db9..00000000
--- a/alliance/share/cells/sxlib/ts_x4.vhd
+++ /dev/null
@@ -1,26 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY ts_x4 IS
-PORT(
-  cmd	: IN STD_LOGIC;
-  i	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END ts_x4;
-
-ARCHITECTURE RTL OF ts_x4 IS
-BEGIN
-  PROCESS ( i, cmd )
-  BEGIN
-    IF (cmd = '1')
-    THEN q <= i;
-    ELSE q <= 'Z';
-    END IF;
-  END PROCESS;
-END RTL;
diff --git a/alliance/share/cells/sxlib/ts_x8.al b/alliance/share/cells/sxlib/ts_x8.al
deleted file mode 100644
index 6dbe0365..00000000
--- a/alliance/share/cells/sxlib/ts_x8.al
+++ /dev/null
@@ -1,40 +0,0 @@
-V ALLIANCE : 6
-H ts_x8,L,30/10/99
-C cmd,IN,EXTERNAL,7
-C i,IN,EXTERNAL,8
-C q,TRISTATE,EXTERNAL,2
-C vdd,IN,EXTERNAL,3
-C vss,IN,EXTERNAL,1
-T P,0.35,5.9,3,5,2,0,0.75,0.75,13.3,13.3,4.5,11.25,tr_00016
-T P,0.35,5.9,2,5,3,0,0.75,0.75,13.3,13.3,2.7,11.25,tr_00015
-T P,0.35,5.9,3,5,2,0,0.75,0.75,13.3,13.3,8.1,11.25,tr_00014
-T P,0.35,2.9,5,6,4,0,0.75,0.75,7.3,7.3,14.1,11.25,tr_00013
-T P,0.35,2.9,3,7,5,0,0.75,0.75,7.3,7.3,15.9,11.25,tr_00012
-T P,0.35,2.9,6,7,3,0,0.75,0.75,7.3,7.3,9.9,12.75,tr_00011
-T P,0.35,5.9,2,5,3,0,0.75,0.75,13.3,13.3,6.3,11.25,tr_00010
-T P,0.35,2.9,5,8,3,0,0.75,0.75,7.3,7.3,17.7,11.25,tr_00009
-T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,4.5,2.25,tr_00008
-T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,2.7,2.25,tr_00007
-T N,0.35,1.4,1,6,4,0,0.75,0.75,4.3,4.3,14.1,3,tr_00006
-T N,0.35,1.4,4,8,1,0,0.75,0.75,4.3,4.3,15.9,3,tr_00005
-T N,0.35,1.4,6,7,1,0,0.75,0.75,4.3,4.3,9.9,3,tr_00004
-T N,0.35,1.4,5,7,4,0,0.75,0.75,4.3,4.3,17.7,3,tr_00003
-T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,6.3,2.25,tr_00002
-T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,8.1,2.25,tr_00001
-S 8,EXTERNAL,i
-Q 0.0029371
-S 7,EXTERNAL,cmd
-Q 0.00891222
-S 6,INTERNAL
-Q 0.00502769
-S 5,INTERNAL
-Q 0.00909993
-S 4,INTERNAL
-Q 0.00797383
-S 3,EXTERNAL,vdd
-Q 0.00965406
-S 2,EXTERNAL,q
-Q 0.00611052
-S 1,EXTERNAL,vss
-Q 0.00795016
-EOF
diff --git a/alliance/share/cells/sxlib/ts_x8.ap b/alliance/share/cells/sxlib/ts_x8.ap
deleted file mode 100644
index ea489a48..00000000
--- a/alliance/share/cells/sxlib/ts_x8.ap
+++ /dev/null
@@ -1,162 +0,0 @@
-V ALLIANCE : 6
-H ts_x8,P, 6/ 9/2000,100
-A 0,0,6500,5000
-R 5500,1500,ref_ref,i_15
-R 3000,1000,ref_ref,cmd_10
-R 3000,3000,ref_ref,cmd_30
-R 3000,3500,ref_ref,cmd_35
-R 3000,4000,ref_ref,cmd_40
-R 3000,1500,ref_ref,cmd_15
-R 3000,2000,ref_ref,cmd_20
-R 3000,2500,ref_ref,cmd_25
-R 2500,2500,ref_ref,q_25
-R 2500,3000,ref_ref,q_30
-R 2500,3500,ref_ref,q_35
-R 2500,4000,ref_ref,q_40
-R 5500,2000,ref_ref,i_20
-R 5500,2500,ref_ref,i_25
-R 5500,3000,ref_ref,i_30
-R 5500,3500,ref_ref,i_35
-R 2500,1000,ref_ref,q_10
-R 2500,1500,ref_ref,q_15
-R 2500,2000,ref_ref,q_20
-S 900,2300,6200,2300,100,*,RIGHT,POLY
-S 1200,2100,2500,2100,200,*,RIGHT,ALU1
-S 1200,1000,1200,4000,200,*,DOWN,ALU1
-S 4400,1000,5600,1000,100,*,RIGHT,ALU1
-S 6200,1000,6200,4000,100,*,DOWN,ALU1
-S 5000,4000,6200,4000,100,*,RIGHT,ALU1
-S 3000,1000,3000,4000,100,*,UP,ALU1
-S 3000,1500,3100,1500,100,*,RIGHT,ALU1
-S 3000,3000,3400,3000,200,*,RIGHT,ALU1
-S 3900,1000,3900,4000,100,*,DOWN,ALU1
-S 4900,1800,4900,2700,100,*,DOWN,ALU1
-S 5500,3000,5700,3000,200,*,LEFT,ALU1
-S 5500,1500,5500,3500,100,*,DOWN,ALU1
-S 4400,1000,4400,4000,100,*,DOWN,ALU1
-S 3600,4000,3900,4000,200,*,RIGHT,ALU1
-S 1800,500,1800,1000,200,*,DOWN,ALU1
-S 1800,3000,1800,4500,200,*,DOWN,ALU1
-S 3600,1000,3900,1000,200,*,RIGHT,ALU1
-S 600,3000,600,4500,200,*,DOWN,ALU1
-S 600,500,600,1000,200,*,DOWN,ALU1
-S 0,300,6500,300,600,vss,RIGHT,CALU1
-S 0,4700,6500,4700,600,vdd,RIGHT,CALU1
-S 5900,1400,5900,1900,100,*,DOWN,POLY
-S 4900,1900,5900,1900,100,*,RIGHT,POLY
-S 2700,1400,2700,1900,100,*,DOWN,POLY
-S 2100,1400,2100,1900,100,*,DOWN,POLY
-S 5300,1500,5500,1500,300,*,RIGHT,POLY
-S 3100,1500,3300,1500,300,*,RIGHT,POLY
-S 3400,2800,3400,3000,300,*,UP,POLY
-S 2100,2300,2100,2600,100,*,UP,POLY
-S 3300,2800,5300,2800,100,*,RIGHT,POLY
-S 5300,2800,5300,3100,100,*,DOWN,POLY
-S 3300,2800,3300,3600,100,*,DOWN,POLY
-S 5700,3000,5900,3000,300,*,RIGHT,POLY
-S 2700,2300,2700,2600,100,*,DOWN,POLY
-S 3800,1400,4700,1400,100,*,RIGHT,POLY
-S 900,1900,4400,1900,100,*,RIGHT,POLY
-S 900,2300,900,2600,100,*,DOWN,POLY
-S 1500,2300,1500,2600,100,*,UP,POLY
-S 900,1400,900,1900,100,*,DOWN,POLY
-S 1500,1400,1500,1900,100,*,DOWN,POLY
-S 5600,300,6200,300,300,*,RIGHT,PTIE
-S 3600,300,4400,300,300,*,RIGHT,PTIE
-S 4200,4700,5000,4700,300,*,RIGHT,NTIE
-S 5900,3100,5900,4400,100,*,UP,PTRANS
-S 1800,2800,1800,4700,300,*,UP,PDIF
-S 2100,2600,2100,4900,100,*,UP,PTRANS
-S 3600,3800,3600,4700,300,*,UP,PDIF
-S 3300,3600,3300,4900,100,*,UP,PTRANS
-S 5000,3300,5000,4200,300,*,UP,PDIF
-S 5300,3100,5300,4400,100,*,UP,PTRANS
-S 4400,3300,4400,4200,300,*,UP,PDIF
-S 4700,3100,4700,4400,100,*,UP,PTRANS
-S 6200,3300,6200,4200,300,*,UP,PDIF
-S 2400,2800,2400,4700,300,*,UP,PDIF
-S 3000,2800,3000,4700,300,*,UP,PDIF
-S 2700,2600,2700,4900,100,*,UP,PTRANS
-S 1200,2800,1200,4700,300,*,UP,PDIF
-S 900,2600,900,4900,100,*,UP,PTRANS
-S 1500,2600,1500,4900,100,*,UP,PTRANS
-S 600,2800,600,4700,300,*,UP,PDIF
-S 1800,300,1800,1200,300,*,UP,NDIF
-S 2700,100,2700,1400,100,*,UP,NTRANS
-S 2100,100,2100,1400,100,*,UP,NTRANS
-S 3000,300,3000,1200,300,*,UP,NDIF
-S 2400,300,2400,1200,300,*,UP,NDIF
-S 6200,800,6200,1200,300,*,UP,NDIF
-S 5900,600,5900,1400,100,*,UP,NTRANS
-S 4400,800,4400,1200,300,*,UP,NDIF
-S 5600,800,5600,1200,300,*,UP,NDIF
-S 3600,800,3600,1200,300,*,UP,NDIF
-S 3300,600,3300,1400,100,*,UP,NTRANS
-S 5000,400,5000,1200,300,*,UP,NDIF
-S 5300,600,5300,1400,100,*,UP,NTRANS
-S 4700,600,4700,1400,100,*,UP,NTRANS
-S 600,300,600,1200,300,*,UP,NDIF
-S 1200,300,1200,1200,300,*,UP,NDIF
-S 900,100,900,1400,100,*,UP,NTRANS
-S 1500,100,1500,1400,100,*,UP,NTRANS
-S 0,3900,6500,3900,2400,*,LEFT,NWELL
-S 2500,950,2500,4050,200,*,UP,ALU1
-S 5000,3500,5000,4000,100,*,UP,ALU1
-S 3850,3100,4700,3100,100,*,RIGHT,POLY
-S 5600,3300,5600,4550,300,*,UP,PDIF
-S 5500,1500,5500,3500,200,i,DOWN,CALU1
-S 3000,1000,3000,4000,200,cmd,DOWN,CALU1
-S 2500,1000,2500,4000,200,q,DOWN,CALU1
-V 3400,3000,CONT_POLY,*
-V 6200,2300,CONT_POLY,*
-V 4900,2700,CONT_POLY,*
-V 4900,1800,CONT_POLY,*
-V 5700,3000,CONT_POLY,*
-V 5500,1500,CONT_POLY,*
-V 3100,1500,CONT_POLY,*
-V 3900,1500,CONT_POLY,*
-V 4400,1800,CONT_POLY,*
-V 3600,300,CONT_BODY_P,*
-V 5600,300,CONT_BODY_P,*
-V 6200,300,CONT_BODY_P,*
-V 4400,300,CONT_BODY_P,*
-V 5000,4700,CONT_BODY_N,*
-V 4200,4700,CONT_BODY_N,*
-V 6200,4700,CONT_BODY_N,*
-V 3600,4000,CONT_DIF_P,*
-V 1800,4500,CONT_DIF_P,*
-V 1800,3500,CONT_DIF_P,*
-V 1800,4000,CONT_DIF_P,*
-V 2400,3500,CONT_DIF_P,*
-V 2400,4000,CONT_DIF_P,*
-V 1800,3000,CONT_DIF_P,*
-V 3000,4500,CONT_DIF_P,*
-V 5000,4000,CONT_DIF_P,*
-V 5600,4500,CONT_DIF_P,*
-V 4400,4000,CONT_DIF_P,*
-V 6200,4000,CONT_DIF_P,*
-V 2400,3000,CONT_DIF_P,*
-V 600,4000,CONT_DIF_P,*
-V 600,3500,CONT_DIF_P,*
-V 600,3000,CONT_DIF_P,*
-V 600,4500,CONT_DIF_P,*
-V 1200,3000,CONT_DIF_P,*
-V 1200,3500,CONT_DIF_P,*
-V 1200,4000,CONT_DIF_P,*
-V 4400,1000,CONT_DIF_N,*
-V 3600,1000,CONT_DIF_N,*
-V 1800,500,CONT_DIF_N,*
-V 3000,500,CONT_DIF_N,*
-V 1800,1000,CONT_DIF_N,*
-V 2400,1000,CONT_DIF_N,*
-V 5600,1000,CONT_DIF_N,*
-V 5000,500,CONT_DIF_N,*
-V 6200,1000,CONT_DIF_N,*
-V 1200,1000,CONT_DIF_N,*
-V 600,1000,CONT_DIF_N,*
-V 600,500,CONT_DIF_N,*
-V 5000,3500,CONT_DIF_P,*
-V 6200,3500,CONT_DIF_P,*
-V 3900,3200,CONT_POLY,*
-V 4400,3500,CONT_DIF_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/ts_x8.sym b/alliance/share/cells/sxlib/ts_x8.sym
deleted file mode 100644
index 4f9e57eb..00000000
Binary files a/alliance/share/cells/sxlib/ts_x8.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/ts_x8.vbe b/alliance/share/cells/sxlib/ts_x8.vbe
deleted file mode 100644
index c92f94f5..00000000
--- a/alliance/share/cells/sxlib/ts_x8.vbe
+++ /dev/null
@@ -1,37 +0,0 @@
-ENTITY ts_x8 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 3250;
-  CONSTANT cin_cmd	 : NATURAL := 19;
-  CONSTANT cin_i	 : NATURAL := 8;
-  CONSTANT rdown_cmd_q	 : NATURAL := 400;
-  CONSTANT rdown_i_q	 : NATURAL := 400;
-  CONSTANT rup_cmd_q	 : NATURAL := 450;
-  CONSTANT rup_i_q	 : NATURAL := 450;
-  CONSTANT tphl_cmd_q	 : NATURAL := 466;
-  CONSTANT tpll_i_q	 : NATURAL := 569;
-  CONSTANT tphh_i_q	 : NATURAL := 613;
-  CONSTANT tphh_cmd_q	 : NATURAL := 626;
-  CONSTANT transistors	 : NATURAL := 16
-);
-PORT (
-  cmd	 : in  BIT;
-  i	 : in  BIT;
-  q	 : out MUX_BIT BUS;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END ts_x8;
-
-ARCHITECTURE behaviour_data_flow OF ts_x8 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on ts_x8"
-  SEVERITY WARNING;
-
-  label0 : BLOCK (cmd = '1')
-  BEGIN
-    q <= GUARDED i after 1200 ps;
-  END BLOCK label0;
-
-END;
diff --git a/alliance/share/cells/sxlib/ts_x8.vhd b/alliance/share/cells/sxlib/ts_x8.vhd
deleted file mode 100644
index 464e2931..00000000
--- a/alliance/share/cells/sxlib/ts_x8.vhd
+++ /dev/null
@@ -1,26 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY ts_x8 IS
-PORT(
-  cmd	: IN STD_LOGIC;
-  i	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END ts_x8;
-
-ARCHITECTURE RTL OF ts_x8 IS
-BEGIN
-  PROCESS ( i, cmd )
-  BEGIN
-    IF (cmd = '1')
-    THEN q <= i;
-    ELSE q <= 'Z';
-    END IF;
-  END PROCESS;
-END RTL;
diff --git a/alliance/share/cells/sxlib/xr2_x1.al b/alliance/share/cells/sxlib/xr2_x1.al
deleted file mode 100644
index dbd8a28b..00000000
--- a/alliance/share/cells/sxlib/xr2_x1.al
+++ /dev/null
@@ -1,40 +0,0 @@
-V ALLIANCE : 6
-H xr2_x1,L,30/10/99
-C i0,IN,EXTERNAL,8
-C i1,IN,EXTERNAL,10
-C q,OUT,EXTERNAL,2
-C vdd,IN,EXTERNAL,7
-C vss,IN,EXTERNAL,4
-T P,0.35,5.9,7,10,6,0,0.75,0.75,13.3,13.3,9,11.25,tr_00012
-T P,0.35,5.9,6,5,2,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00011
-T P,0.35,5.9,6,8,7,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00010
-T P,0.35,5.9,2,9,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00009
-T P,0.35,2.9,7,8,5,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00008
-T P,0.35,2.9,9,10,7,0,0.75,0.75,7.3,7.3,10.8,11.25,tr_00007
-T N,0.35,2.9,4,8,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00006
-T N,0.35,2.9,1,10,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00005
-T N,0.35,2.9,2,5,3,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00004
-T N,0.35,2.9,3,9,4,0,0.75,0.75,7.3,7.3,9,2.25,tr_00003
-T N,0.35,1.4,4,10,9,0,0.75,0.75,4.3,4.3,10.8,3,tr_00002
-T N,0.35,1.4,5,8,4,0,0.75,0.75,4.3,4.3,1.8,3,tr_00001
-S 10,EXTERNAL,i1
-Q 0.00533757
-S 9,INTERNAL
-Q 0.00655161
-S 8,EXTERNAL,i0
-Q 0.00413388
-S 7,EXTERNAL,vdd
-Q 0.0047041
-S 6,INTERNAL
-Q 0.00274153
-S 5,INTERNAL
-Q 0.0053513
-S 4,EXTERNAL,vss
-Q 0.0047041
-S 3,INTERNAL
-Q 0
-S 2,EXTERNAL,q
-Q 0.0029965
-S 1,INTERNAL
-Q 0
-EOF
diff --git a/alliance/share/cells/sxlib/xr2_x1.ap b/alliance/share/cells/sxlib/xr2_x1.ap
deleted file mode 100644
index 80714b10..00000000
--- a/alliance/share/cells/sxlib/xr2_x1.ap
+++ /dev/null
@@ -1,116 +0,0 @@
-V ALLIANCE : 6
-H xr2_x1,P,30/ 8/2000,100
-A 0,0,4500,5000
-R 2000,3000,ref_ref,q_30
-R 2000,3500,ref_ref,q_35
-R 3500,4000,ref_ref,i1_40
-R 3500,3500,ref_ref,i1_35
-R 3500,3000,ref_ref,i1_30
-R 3500,2500,ref_ref,i1_25
-R 3500,2000,ref_ref,i1_20
-R 3500,1500,ref_ref,i1_15
-R 3500,1000,ref_ref,i1_10
-R 1000,4000,ref_ref,i0_40
-R 1000,3500,ref_ref,i0_35
-R 1000,3000,ref_ref,i0_30
-R 1000,2000,ref_ref,i0_20
-R 1000,2500,ref_ref,i0_25
-R 1000,1500,ref_ref,i0_15
-R 1000,1000,ref_ref,i0_10
-R 1500,1000,ref_ref,q_10
-R 1500,1500,ref_ref,q_15
-R 1500,2000,ref_ref,q_20
-R 1500,2500,ref_ref,q_25
-S 1500,3500,1500,4000,100,*,UP,ALU1
-S 4000,3500,4000,4000,100,*,DOWN,ALU1
-S 1500,950,1500,3050,200,*,UP,ALU1
-S 1500,3000,2000,3000,200,*,LEFT,ALU1
-S 2000,3000,2000,3500,200,*,DOWN,ALU1
-S 2700,3000,2700,4000,100,*,UP,ALU1
-S 300,3500,300,4000,100,*,DOWN,ALU1
-S 4000,800,4000,1200,300,*,UP,NDIF
-S 4000,3300,4000,4200,300,*,DOWN,PDIF
-S 4000,1000,4000,3500,100,*,DOWN,ALU1
-S 2000,2500,2500,2500,100,*,RIGHT,ALU1
-S 2500,2000,3000,2000,100,*,RIGHT,ALU1
-S 2500,2000,2500,2500,100,*,DOWN,ALU1
-S 3000,2000,4000,2000,100,*,RIGHT,POLY
-S 3000,1400,3000,2000,100,*,DOWN,POLY
-S 3000,2600,3600,2600,100,*,RIGHT,POLY
-S 1800,1400,2100,1400,100,*,RIGHT,POLY
-S 1800,2600,2100,2600,100,*,RIGHT,POLY
-S 2000,1500,3500,1500,100,*,RIGHT,ALU1
-S 3500,1000,3500,4000,100,*,DOWN,ALU1
-S 3600,2600,3600,3100,100,*,DOWN,POLY
-S 600,600,600,1400,100,*,DOWN,NTRANS
-S 3600,600,3600,1400,100,*,DOWN,NTRANS
-S 300,800,300,1200,300,*,UP,NDIF
-S 3000,100,3000,1400,100,*,DOWN,NTRANS
-S 2700,300,2700,1200,300,*,UP,NDIF
-S 2400,100,2400,1400,100,*,DOWN,NTRANS
-S 2100,300,2100,1200,300,*,UP,NDIF
-S 1800,100,1800,1400,100,*,DOWN,NTRANS
-S 1500,300,1500,1200,300,*,UP,NDIF
-S 900,300,900,1200,300,*,UP,NDIF
-S 1200,100,1200,1400,100,*,DOWN,NTRANS
-S 3300,300,3300,1200,300,*,UP,NDIF
-S 3600,3100,3600,4400,100,*,UP,PTRANS
-S 3300,2800,3300,4700,300,*,DOWN,PDIF
-S 600,3100,600,4400,100,*,UP,PTRANS
-S 300,3300,300,4200,300,*,UP,PDIF
-S 1800,2600,1800,4900,100,*,UP,PTRANS
-S 1500,2800,1500,4700,300,*,DOWN,PDIF
-S 1200,2600,1200,4900,100,*,UP,PTRANS
-S 900,2800,900,4700,300,*,DOWN,PDIF
-S 2100,2800,2100,4700,300,*,DOWN,PDIF
-S 2400,2600,2400,4900,100,*,UP,PTRANS
-S 2700,2800,2700,4700,300,*,DOWN,PDIF
-S 3000,2600,3000,4900,100,*,UP,PTRANS
-S 600,2600,600,3100,100,*,DOWN,POLY
-S 600,2600,1200,2600,100,*,RIGHT,POLY
-S 2400,1400,2400,2600,100,*,DOWN,POLY
-S 600,1400,1200,1400,100,*,RIGHT,POLY
-S 300,2000,2400,2000,100,*,RIGHT,POLY
-S 0,300,4500,300,600,vss,RIGHT,CALU1
-S 0,4700,4500,4700,600,vdd,RIGHT,CALU1
-S 1000,1000,1000,4000,100,*,UP,ALU1
-S 300,1000,300,3500,100,*,DOWN,ALU1
-S 1500,4000,2700,4000,100,*,RIGHT,ALU1
-S 0,3900,4500,3900,2400,*,RIGHT,NWELL
-S 1500,1000,2100,1000,200,*,RIGHT,ALU1
-S 3500,1000,3500,4000,200,i1,DOWN,CALU1
-S 1000,1000,1000,4000,200,i0,DOWN,CALU1
-S 2000,3000,2000,3500,200,q,DOWN,CALU1
-S 1500,1000,1500,3000,200,q,DOWN,CALU1
-S 2000,1000,2000,1000,200,q,LEFT,CALU1
-V 1500,3500,CONT_DIF_P,*
-V 4000,4000,CONT_DIF_P,*
-V 2700,3000,CONT_DIF_P,*
-V 2700,3500,CONT_DIF_P,*
-V 300,4000,CONT_DIF_P,*
-V 4000,1000,CONT_DIF_N,*
-V 4000,3500,CONT_DIF_P,*
-V 4000,2000,CONT_POLY,*
-V 3000,2000,CONT_POLY,*
-V 3500,2500,CONT_POLY,*
-V 3500,1500,CONT_POLY,*
-V 2000,2500,CONT_POLY,*
-V 2000,1500,CONT_POLY,*
-V 2100,3500,CONT_DIF_P,*
-V 2100,1000,CONT_DIF_N,*
-V 300,1000,CONT_DIF_N,*
-V 900,500,CONT_DIF_N,*
-V 3300,500,CONT_DIF_N,*
-V 900,4500,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 2700,4000,CONT_DIF_P,*
-V 300,3500,CONT_DIF_P,*
-V 3300,4500,CONT_DIF_P,*
-V 300,4700,CONT_BODY_N,*
-V 3900,4700,CONT_BODY_N,*
-V 300,300,CONT_BODY_P,*
-V 3900,300,CONT_BODY_P,*
-V 1000,2500,CONT_POLY,*
-V 1000,1500,CONT_POLY,*
-V 300,2000,CONT_POLY,*
-EOF
diff --git a/alliance/share/cells/sxlib/xr2_x1.sym b/alliance/share/cells/sxlib/xr2_x1.sym
deleted file mode 100644
index 2e21e7d4..00000000
Binary files a/alliance/share/cells/sxlib/xr2_x1.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/xr2_x1.vbe b/alliance/share/cells/sxlib/xr2_x1.vbe
deleted file mode 100644
index aef426b0..00000000
--- a/alliance/share/cells/sxlib/xr2_x1.vbe
+++ /dev/null
@@ -1,40 +0,0 @@
-ENTITY xr2_x1 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 2250;
-  CONSTANT cin_i0	 : NATURAL := 21;
-  CONSTANT cin_i1	 : NATURAL := 22;
-  CONSTANT rdown_i0_q	 : NATURAL := 2850;
-  CONSTANT rdown_i0_q	 : NATURAL := 2850;
-  CONSTANT rdown_i1_q	 : NATURAL := 2850;
-  CONSTANT rdown_i1_q	 : NATURAL := 2850;
-  CONSTANT rup_i0_q	 : NATURAL := 3210;
-  CONSTANT rup_i0_q	 : NATURAL := 3210;
-  CONSTANT rup_i1_q	 : NATURAL := 3210;
-  CONSTANT rup_i1_q	 : NATURAL := 3210;
-  CONSTANT tplh_i1_q	 : NATURAL := 261;
-  CONSTANT tphl_i0_q	 : NATURAL := 292;
-  CONSTANT tplh_i0_q	 : NATURAL := 293;
-  CONSTANT tphh_i0_q	 : NATURAL := 366;
-  CONSTANT tphl_i1_q	 : NATURAL := 377;
-  CONSTANT tpll_i1_q	 : NATURAL := 388;
-  CONSTANT tpll_i0_q	 : NATURAL := 389;
-  CONSTANT tphh_i1_q	 : NATURAL := 405;
-  CONSTANT transistors	 : NATURAL := 12
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END xr2_x1;
-
-ARCHITECTURE behaviour_data_flow OF xr2_x1 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on xr2_x1"
-  SEVERITY WARNING;
-  q <= (i0 xor i1) after 1000 ps;
-END;
diff --git a/alliance/share/cells/sxlib/xr2_x1.vhd b/alliance/share/cells/sxlib/xr2_x1.vhd
deleted file mode 100644
index dca01149..00000000
--- a/alliance/share/cells/sxlib/xr2_x1.vhd
+++ /dev/null
@@ -1,20 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY xr2_x1 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END xr2_x1;
-
-ARCHITECTURE RTL OF xr2_x1 IS
-BEGIN
-  q <= (i0 XOR i1);
-END RTL;
diff --git a/alliance/share/cells/sxlib/xr2_x4.al b/alliance/share/cells/sxlib/xr2_x4.al
deleted file mode 100644
index c2255927..00000000
--- a/alliance/share/cells/sxlib/xr2_x4.al
+++ /dev/null
@@ -1,46 +0,0 @@
-V ALLIANCE : 6
-H xr2_x4,L,30/10/99
-C i0,IN,EXTERNAL,8
-C i1,IN,EXTERNAL,9
-C q,OUT,EXTERNAL,11
-C vdd,IN,EXTERNAL,7
-C vss,IN,EXTERNAL,1
-T P,0.35,2.9,10,9,7,0,0.75,0.75,7.3,7.3,10.8,9.75,tr_00016
-T P,0.35,2.9,7,8,4,0,0.75,0.75,7.3,7.3,1.8,9.75,tr_00015
-T P,0.35,5.9,11,2,7,0,0.75,0.75,13.3,13.3,14.4,11.25,tr_00014
-T P,0.35,5.9,7,2,11,0,0.75,0.75,13.3,13.3,16.2,11.25,tr_00013
-T P,0.35,5.9,2,9,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00012
-T P,0.35,5.9,6,8,7,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00011
-T P,0.35,5.9,6,4,2,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00010
-T P,0.35,5.9,7,10,6,0,0.75,0.75,13.3,13.3,9,11.25,tr_00009
-T N,0.35,2.9,11,2,1,0,0.75,0.75,7.3,7.3,16.2,2.25,tr_00008
-T N,0.35,2.9,1,2,11,0,0.75,0.75,7.3,7.3,14.4,2.25,tr_00007
-T N,0.35,1.4,4,8,1,0,0.75,0.75,4.3,4.3,1.8,3,tr_00006
-T N,0.35,1.4,1,9,10,0,0.75,0.75,4.3,4.3,10.8,3,tr_00005
-T N,0.35,2.9,3,9,1,0,0.75,0.75,7.3,7.3,9,2.25,tr_00004
-T N,0.35,2.9,2,4,3,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00003
-T N,0.35,2.9,5,10,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00002
-T N,0.35,2.9,1,8,5,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00001
-S 11,EXTERNAL,q
-Q 0.00258522
-S 10,INTERNAL
-Q 0.00536068
-S 9,EXTERNAL,i1
-Q 0.00462772
-S 8,EXTERNAL,i0
-Q 0.00370588
-S 7,EXTERNAL,vdd
-Q 0.00866628
-S 6,INTERNAL
-Q 0.00274153
-S 5,INTERNAL
-Q 0
-S 4,INTERNAL
-Q 0.00506945
-S 3,INTERNAL
-Q 0
-S 2,INTERNAL
-Q 0.00791506
-S 1,EXTERNAL,vss
-Q 0.00737367
-EOF
diff --git a/alliance/share/cells/sxlib/xr2_x4.ap b/alliance/share/cells/sxlib/xr2_x4.ap
deleted file mode 100644
index 25fa815e..00000000
--- a/alliance/share/cells/sxlib/xr2_x4.ap
+++ /dev/null
@@ -1,145 +0,0 @@
-V ALLIANCE : 6
-H xr2_x4,P, 6/ 9/2000,100
-A 0,0,6000,5000
-R 5000,4000,ref_ref,q_40
-R 5000,1000,ref_ref,q_10
-R 5000,3000,ref_ref,q_30
-R 5000,3500,ref_ref,q_35
-R 5000,2500,ref_ref,q_25
-R 5000,2000,ref_ref,q_20
-R 5000,1500,ref_ref,q_15
-R 3500,4000,ref_ref,i1_40
-R 3500,3500,ref_ref,i1_35
-R 3500,3000,ref_ref,i1_30
-R 3500,2500,ref_ref,i1_25
-R 3500,2000,ref_ref,i1_20
-R 3500,1500,ref_ref,i1_15
-R 1000,4000,ref_ref,i0_40
-R 1000,3500,ref_ref,i0_35
-R 1000,3000,ref_ref,i0_30
-R 1000,2000,ref_ref,i0_20
-R 1000,2500,ref_ref,i0_25
-R 1000,1500,ref_ref,i0_15
-R 1000,1000,ref_ref,i0_10
-S 4500,2000,5400,2000,300,*,RIGHT,POLY
-S 5000,1000,5000,4000,200,q,DOWN,CALU1
-S 3500,1500,3500,4000,200,i1,DOWN,CALU1
-S 1000,1000,1000,4000,200,i0,DOWN,CALU1
-S 0,3900,6000,3900,2400,*,LEFT,NWELL
-S 4500,300,4500,1000,300,*,UP,NDIF
-S 3900,800,3900,1600,300,*,UP,NDIF
-S 1500,1000,4500,1000,100,*,RIGHT,ALU1
-S 4500,1000,4500,2000,100,*,DOWN,ALU1
-S 4800,1400,4800,2600,100,*,DOWN,POLY
-S 5400,1400,5400,2600,100,*,DOWN,POLY
-S 5700,500,5700,1000,200,*,DOWN,ALU1
-S 5700,3000,5700,4500,200,*,DOWN,ALU1
-S 4500,3500,4500,4500,200,*,DOWN,ALU1
-S 3500,1500,3500,4000,100,*,DOWN,ALU1
-S 4000,1500,4000,2900,100,*,DOWN,ALU1
-S 0,300,6000,300,600,vss,RIGHT,CALU1
-S 0,4700,6000,4700,600,vdd,RIGHT,CALU1
-S 5700,300,5700,1200,300,*,UP,NDIF
-S 5100,300,5100,1200,300,*,UP,NDIF
-S 5400,100,5400,1400,100,*,DOWN,NTRANS
-S 4800,100,4800,1400,100,*,DOWN,NTRANS
-S 3900,2800,3900,3700,300,*,DOWN,PDIF
-S 4500,3400,4500,4700,300,*,DOWN,PDIF
-S 5100,2800,5100,4700,300,*,DOWN,PDIF
-S 3600,2600,3600,3900,100,*,UP,PTRANS
-S 600,2600,600,3900,100,*,UP,PTRANS
-S 300,2800,300,3700,300,*,UP,PDIF
-S 4800,2600,4800,4900,100,*,UP,PTRANS
-S 5400,2600,5400,4900,100,*,UP,PTRANS
-S 5700,2800,5700,4700,300,*,DOWN,PDIF
-S 2500,2000,3000,2000,100,*,RIGHT,ALU1
-S 2500,1500,2500,2000,100,*,DOWN,ALU1
-S 2000,1500,2500,1500,100,*,RIGHT,ALU1
-S 3000,1400,3600,1400,100,*,RIGHT,POLY
-S 2000,2500,3500,2500,100,*,RIGHT,ALU1
-S 3000,2000,3000,2600,100,*,DOWN,POLY
-S 3000,2000,4000,2000,100,*,RIGHT,POLY
-S 1800,1400,2100,1400,100,*,RIGHT,POLY
-S 1800,2600,2100,2600,100,*,RIGHT,POLY
-S 600,600,600,1400,100,*,DOWN,NTRANS
-S 3600,600,3600,1400,100,*,DOWN,NTRANS
-S 300,800,300,1200,300,*,UP,NDIF
-S 3000,100,3000,1400,100,*,DOWN,NTRANS
-S 2700,300,2700,1200,300,*,UP,NDIF
-S 2400,100,2400,1400,100,*,DOWN,NTRANS
-S 2100,300,2100,1200,300,*,UP,NDIF
-S 1800,100,1800,1400,100,*,DOWN,NTRANS
-S 1500,300,1500,1200,300,*,UP,NDIF
-S 900,300,900,1200,300,*,UP,NDIF
-S 1200,100,1200,1400,100,*,DOWN,NTRANS
-S 3300,300,3300,1200,300,*,UP,NDIF
-S 3300,2800,3300,4700,300,*,DOWN,PDIF
-S 1800,2600,1800,4900,100,*,UP,PTRANS
-S 1500,2800,1500,4700,300,*,DOWN,PDIF
-S 1200,2600,1200,4900,100,*,UP,PTRANS
-S 900,2800,900,4700,300,*,DOWN,PDIF
-S 2100,2800,2100,4700,300,*,DOWN,PDIF
-S 2400,2600,2400,4900,100,*,UP,PTRANS
-S 2700,2800,2700,4700,300,*,DOWN,PDIF
-S 3000,2600,3000,4900,100,*,UP,PTRANS
-S 600,2600,1200,2600,100,*,RIGHT,POLY
-S 2400,1400,2400,2600,100,*,DOWN,POLY
-S 600,1400,1200,1400,100,*,RIGHT,POLY
-S 300,2000,2400,2000,100,*,RIGHT,POLY
-S 1000,1000,1000,4000,100,*,UP,ALU1
-S 1500,4000,2700,4000,100,*,RIGHT,ALU1
-S 300,1000,300,3000,100,*,DOWN,ALU1
-S 2100,3000,2100,3500,100,*,DOWN,ALU1
-S 1500,3000,2100,3000,100,*,LEFT,ALU1
-S 1500,1000,1500,3000,100,*,UP,ALU1
-S 1500,3500,1500,4000,100,*,UP,ALU1
-S 2700,3000,2700,4000,100,*,DOWN,ALU1
-S 300,3000,300,3500,100,*,UP,ALU1
-S 5700,1000,5700,1700,200,*,UP,ALU1
-S 5000,1000,5000,4000,200,*,DOWN,ALU1
-V 4500,2000,CONT_POLY,*
-V 4000,2900,CONT_DIF_P,*
-V 4000,1500,CONT_DIF_N,*
-V 5100,1000,CONT_DIF_N,*
-V 5100,3000,CONT_DIF_P,*
-V 5100,3500,CONT_DIF_P,*
-V 5100,4000,CONT_DIF_P,*
-V 4500,4500,CONT_DIF_P,*
-V 4500,4000,CONT_DIF_P,*
-V 4500,3500,CONT_DIF_P,*
-V 5700,3000,CONT_DIF_P,*
-V 5700,3500,CONT_DIF_P,*
-V 5700,4000,CONT_DIF_P,*
-V 5700,4500,CONT_DIF_P,*
-V 5700,1000,CONT_DIF_N,*
-V 5700,500,CONT_DIF_N,*
-V 4500,500,CONT_DIF_N,*
-V 300,3000,CONT_DIF_P,*
-V 3000,2000,CONT_POLY,*
-V 4000,2000,CONT_POLY,*
-V 3500,2500,CONT_POLY,*
-V 3500,1500,CONT_POLY,*
-V 2000,2500,CONT_POLY,*
-V 2000,1500,CONT_POLY,*
-V 2100,3500,CONT_DIF_P,*
-V 2100,1000,CONT_DIF_N,*
-V 300,1000,CONT_DIF_N,*
-V 900,500,CONT_DIF_N,*
-V 3300,500,CONT_DIF_N,*
-V 900,4500,CONT_DIF_P,*
-V 1500,4000,CONT_DIF_P,*
-V 2700,4000,CONT_DIF_P,*
-V 3300,4500,CONT_DIF_P,*
-V 300,4700,CONT_BODY_N,*
-V 3900,4700,CONT_BODY_N,*
-V 300,300,CONT_BODY_P,*
-V 3900,300,CONT_BODY_P,*
-V 1000,2500,CONT_POLY,*
-V 1000,1500,CONT_POLY,*
-V 300,2000,CONT_POLY,*
-V 1500,3500,CONT_DIF_P,*
-V 2700,3500,CONT_DIF_P,*
-V 2700,3000,CONT_DIF_P,*
-V 300,3500,CONT_DIF_P,*
-V 5700,1700,CONT_BODY_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/xr2_x4.sym b/alliance/share/cells/sxlib/xr2_x4.sym
deleted file mode 100644
index 8198a29b..00000000
Binary files a/alliance/share/cells/sxlib/xr2_x4.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/xr2_x4.vbe b/alliance/share/cells/sxlib/xr2_x4.vbe
deleted file mode 100644
index 047882b4..00000000
--- a/alliance/share/cells/sxlib/xr2_x4.vbe
+++ /dev/null
@@ -1,40 +0,0 @@
-ENTITY xr2_x4 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 3000;
-  CONSTANT cin_i0	 : NATURAL := 20;
-  CONSTANT cin_i1	 : NATURAL := 21;
-  CONSTANT rdown_i0_q	 : NATURAL := 810;
-  CONSTANT rdown_i0_q	 : NATURAL := 810;
-  CONSTANT rdown_i1_q	 : NATURAL := 810;
-  CONSTANT rdown_i1_q	 : NATURAL := 810;
-  CONSTANT rup_i0_q	 : NATURAL := 890;
-  CONSTANT rup_i0_q	 : NATURAL := 890;
-  CONSTANT rup_i1_q	 : NATURAL := 890;
-  CONSTANT rup_i1_q	 : NATURAL := 890;
-  CONSTANT tphh_i1_q	 : NATURAL := 357;
-  CONSTANT tphh_i0_q	 : NATURAL := 476;
-  CONSTANT tpll_i0_q	 : NATURAL := 480;
-  CONSTANT tphl_i0_q	 : NATURAL := 521;
-  CONSTANT tpll_i1_q	 : NATURAL := 539;
-  CONSTANT tphl_i1_q	 : NATURAL := 541;
-  CONSTANT tplh_i0_q	 : NATURAL := 560;
-  CONSTANT tplh_i1_q	 : NATURAL := 657;
-  CONSTANT transistors	 : NATURAL := 16
-);
-PORT (
-  i0	 : in  BIT;
-  i1	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END xr2_x4;
-
-ARCHITECTURE behaviour_data_flow OF xr2_x4 IS
-
-BEGIN
-  ASSERT ((vdd and not (vss)) = '1')
-  REPORT "power supply is missing on xr2_x4"
-  SEVERITY WARNING;
-  q <= (i0 xor i1) after 1300 ps;
-END;
diff --git a/alliance/share/cells/sxlib/xr2_x4.vhd b/alliance/share/cells/sxlib/xr2_x4.vhd
deleted file mode 100644
index 404a3949..00000000
--- a/alliance/share/cells/sxlib/xr2_x4.vhd
+++ /dev/null
@@ -1,20 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY xr2_x4 IS
-PORT(
-  i0	: IN STD_LOGIC;
-  i1	: IN STD_LOGIC;
-  q	: OUT STD_LOGIC
-);
-END xr2_x4;
-
-ARCHITECTURE RTL OF xr2_x4 IS
-BEGIN
-  q <= (i0 XOR i1);
-END RTL;
diff --git a/alliance/share/cells/sxlib/zero_x0.al b/alliance/share/cells/sxlib/zero_x0.al
deleted file mode 100644
index aafb6a73..00000000
--- a/alliance/share/cells/sxlib/zero_x0.al
+++ /dev/null
@@ -1,13 +0,0 @@
-V ALLIANCE : 6
-H zero_x0,L,30/10/99
-C nq,OUT,EXTERNAL,1
-C vdd,IN,EXTERNAL,3
-C vss,IN,EXTERNAL,2
-T N,0.35,1.4,2,3,1,0,0.75,0.75,4.3,4.3,2.1,4.5,tr_00001
-S 3,EXTERNAL,vdd
-Q 0.00535397
-S 2,EXTERNAL,vss
-Q 0.00330156
-S 1,EXTERNAL,nq
-Q 0.00205642
-EOF
diff --git a/alliance/share/cells/sxlib/zero_x0.ap b/alliance/share/cells/sxlib/zero_x0.ap
deleted file mode 100644
index 92c72144..00000000
--- a/alliance/share/cells/sxlib/zero_x0.ap
+++ /dev/null
@@ -1,35 +0,0 @@
-V ALLIANCE : 6
-H zero_x0,P,30/ 8/2000,100
-A 0,0,1500,5000
-R 1000,4000,ref_ref,nq_40
-R 1000,3500,ref_ref,nq_35
-R 1000,3000,ref_ref,nq_30
-R 1000,2500,ref_ref,nq_25
-R 1000,2000,ref_ref,nq_20
-R 1000,1500,ref_ref,nq_15
-R 1000,1000,ref_ref,nq_10
-S 1000,1000,1000,4000,200,nq,DOWN,CALU1
-S 500,3000,500,4600,300,*,UP,NTIE
-S 1000,1000,1000,4000,200,*,DOWN,ALU1
-S 0,300,1500,300,600,vss,RIGHT,CALU1
-S 0,4700,1500,4700,600,vdd,RIGHT,CALU1
-S 0,3900,1500,3900,2400,*,RIGHT,NWELL
-S 500,4500,1000,4500,300,*,LEFT,NTIE
-S 400,2000,700,2000,300,*,RIGHT,POLY
-S 350,1300,350,1700,400,*,UP,NDIF
-S 1000,1300,1000,1700,300,*,UP,NDIF
-S 700,1100,700,1900,100,*,DOWN,NTRANS
-S 500,2000,500,4700,200,*,DOWN,ALU1
-S 400,300,400,1500,200,*,DOWN,ALU1
-S 400,500,1000,500,300,*,RIGHT,PTIE
-V 500,4000,CONT_BODY_N,*
-V 500,3500,CONT_BODY_N,*
-V 500,3000,CONT_BODY_N,*
-V 1000,4500,CONT_BODY_N,*
-V 500,4500,CONT_BODY_N,*
-V 500,2000,CONT_POLY,*
-V 400,1500,CONT_DIF_N,*
-V 1000,1500,CONT_DIF_N,*
-V 1000,500,CONT_BODY_P,*
-V 400,500,CONT_BODY_P,*
-EOF
diff --git a/alliance/share/cells/sxlib/zero_x0.sym b/alliance/share/cells/sxlib/zero_x0.sym
deleted file mode 100644
index 5452045b..00000000
Binary files a/alliance/share/cells/sxlib/zero_x0.sym and /dev/null differ
diff --git a/alliance/share/cells/sxlib/zero_x0.vbe b/alliance/share/cells/sxlib/zero_x0.vbe
deleted file mode 100644
index 535efebc..00000000
--- a/alliance/share/cells/sxlib/zero_x0.vbe
+++ /dev/null
@@ -1,20 +0,0 @@
-ENTITY zero_x0 IS
-GENERIC (
-  CONSTANT area 	 : NATURAL := 750;
-  CONSTANT transistors	 : NATURAL := 1
-);
-PORT (
-  nq	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-);
-END zero_x0;
-
-ARCHITECTURE behaviour_data_flow OF zero_x0 IS
-
-BEGIN
-  ASSERT (vdd and not (vss))
-  REPORT "power supply is missing on zero_x0"
-  SEVERITY WARNING;
-  nq <= '0';
-END;
diff --git a/alliance/share/cells/sxlib/zero_x0.vhd b/alliance/share/cells/sxlib/zero_x0.vhd
deleted file mode 100644
index c662155c..00000000
--- a/alliance/share/cells/sxlib/zero_x0.vhd
+++ /dev/null
@@ -1,18 +0,0 @@
-
---
--- Generated by VASY
---
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-
-ENTITY zero_x0 IS
-PORT(
-  nq	: OUT STD_LOGIC
-);
-END zero_x0;
-
-ARCHITECTURE RTL OF zero_x0 IS
-BEGIN
-  nq <= '0';
-END RTL;
diff --git a/alliance/share/doc/overview.pdf b/alliance/share/doc/overview.pdf
deleted file mode 100644
index 021ee597..00000000
Binary files a/alliance/share/doc/overview.pdf and /dev/null differ
diff --git a/alliance/share/doc/overview.ps b/alliance/share/doc/overview.ps
deleted file mode 100644
index d8afa6cb..00000000
--- a/alliance/share/doc/overview.ps
+++ /dev/null
@@ -1,25107 +0,0 @@
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-  cvi
-  /gray_packet exch def
-  compression 0 gt
-  {
-    /number_pixels 1 def
-  }
-  {
-    currentfile byte readhexstring pop 0 get
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-
-/PseudoClassPacket
-{
-  %
-  % Get a PseudoClass packet.
-  %
-  % Parameters:
-  %   index: index into the colormap.
-  %   length: number of pixels minus one of this color (optional).
-  %
-  currentfile byte readhexstring pop 0 get
-  /offset exch 3 mul def
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-  {
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-
-/PseudoClassImage
-{
-  %
-  % Display a PseudoClass image.
-  %
-  % Parameters:
-  %   class: 0-PseudoClass or 1-Grayscale.
-  %
-  currentfile buffer readline pop
-  token pop /class exch def pop
-  class 0 gt
-  {
-    currentfile buffer readline pop
-    token pop /depth exch def pop
-    /grays columns 8 add depth sub depth mul 8 idiv string def
-    columns rows depth
-    [
-      columns 0 0
-      rows neg 0 rows
-    ]
-    { currentfile grays readhexstring pop } image
-  }
-  {
-    %
-    % Parameters:
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-    %   colormap: red, green, blue color packets.
-    %
-    currentfile buffer readline pop
-    token pop /colors exch def pop
-    /colors colors 3 mul def
-    /colormap colors string def
-    currentfile colormap readhexstring pop pop
-    systemdict /colorimage known
-    {
-      columns rows 8
-      [
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-        rows neg 0 rows
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-      { PseudoClassPacket } false 3 colorimage
-    }
-    {
-      %
-      % No colorimage operator;  convert to grayscale.
-      %
-      columns rows 8
-      [
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-        rows neg 0 rows
-      ]
-      { GrayPseudoClassPacket } image
-    } ifelse
-  } ifelse
-} bind def
-
-/DisplayImage
-{
-  %
-  % Display a DirectClass or PseudoClass image.
-  %
-  % Parameters:
-  %   x & y translation.
-  %   x & y scale.
-  %   label pointsize.
-  %   image label.
-  %   image columns & rows.
-  %   class: 0-DirectClass or 1-PseudoClass.
-  %   compression: 0-RunlengthEncodedCompression or 1-NoCompression.
-  %   hex color packets.
-  %
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-  x y translate
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-  currentfile buffer readline pop
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-  /Helvetica findfont pointsize scalefont setfont
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-  token pop /columns exch def
-  token pop /rows exch def pop
-  currentfile buffer readline pop
-  token pop /class exch def pop
-  currentfile buffer readline pop
-  token pop /compression exch def pop
-  class 0 gt { PseudoClassImage } { DirectClassImage } ifelse
-  grestore
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-%%EndProlog
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-{
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-{
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-{
-  %
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-	{29 29} {29 30} {28 30} {27 30} {26 30} {25 30} {24 30} {23 30} {23 29} {23 28}
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-     {2 13} {2 17} {2 21} {2 25} {2 29} {3 0} {3 2} {3 4} {3 6} 
-     {3 8} {3 10} {3 12} {3 14} {3 16} {3 18} {3 20} {3 22} {3 24} 
-     {3 26} {3 28} {3 30} {4 1} {4 2} {4 3} {4 7} {4 9} {4 10} 
-     {4 11} {4 15} {4 17} {4 18} {4 19} {4 23} {4 25} {4 26} {4 27} 
-     {4 31} {5 0} {5 1} {5 2} {5 3} {5 4} {5 6} {5 8} {5 9} 
-     {5 10} {5 11} {5 12} {5 14} {5 16} {5 17} {5 18} {5 19} {5 20} 
-     {5 22} {5 24} {5 25} {5 26} {5 27} {5 28} {5 30} {6 1} {6 2} 
-     {6 3} {6 5} {6 9} {6 10} {6 11} {6 13} {6 17} {6 18} {6 19} 
-     {6 21} {6 25} {6 26} {6 27} {6 29} {7 0} {7 2} {7 4} {7 6} 
-     {7 8} {7 10} {7 12} {7 14} {7 16} {7 18} {7 20} {7 22} {7 24} 
-     {7 26} {7 28} {7 30} {8 3} {8 7} {8 11} {8 15} {8 19} {8 23} 
-     {8 27} {8 31} {9 0} {9 2} {9 4} {9 6} {9 8} {9 10} {9 12} 
-     {9 14} {9 16} {9 18} {9 20} {9 22} {9 24} {9 26} {9 28} {9 30} 
-     {10 1} {10 5} {10 9} {10 13} {10 17} {10 21} {10 25} {10 29} {11 0} 
-     {11 2} {11 4} {11 6} {11 8} {11 10} {11 12} {11 14} {11 16} {11 18} 
-     {11 20} {11 22} {11 24} {11 26} {11 28} {11 30} {12 1} {12 2} {12 3} 
-     {12 7} {12 9} {12 10} {12 11} {12 15} {12 17} {12 18} {12 19} {12 23} 
-     {12 25} {12 26} {12 27} {12 31} {13 0} {13 1} {13 2} {13 3} {13 4} 
-     {13 6} {13 8} {13 9} {13 10} {13 11} {13 12} {13 14} {13 16} {13 17} 
-     {13 18} {13 19} {13 20} {13 22} {13 24} {13 25} {13 26} {13 27} {13 28} 
-     {13 30} {14 1} {14 2} {14 3} {14 5} {14 9} {14 10} {14 11} {14 13} 
-     {14 17} {14 18} {14 19} {14 21} {14 25} {14 26} {14 27} {14 29} {15 0} 
-     {15 2} {15 4} {15 6} {15 8} {15 10} {15 12} {15 14} {15 16} {15 18} 
-     {15 20} {15 22} {15 24} {15 26} {15 28} {15 30} {16 3} {16 7} {16 11} 
-     {16 15} {16 19} {16 23} {16 27} {16 31} {17 0} {17 2} {17 4} {17 6} 
-     {17 8} {17 10} {17 12} {17 14} {17 16} {17 18} {17 20} {17 22} {17 24} 
-     {17 26} {17 28} {17 30} {18 1} {18 5} {18 9} {18 13} {18 17} {18 21} 
-     {18 25} {18 29} {19 0} {19 2} {19 4} {19 6} {19 8} {19 10} {19 12} 
-     {19 14} {19 16} {19 18} {19 20} {19 22} {19 24} {19 26} {19 28} {19 30} 
-     {20 1} {20 2} {20 3} {20 7} {20 9} {20 10} {20 11} {20 15} {20 17} 
-     {20 18} {20 19} {20 23} {20 25} {20 26} {20 27} {20 31} {21 0} {21 1} 
-     {21 2} {21 3} {21 4} {21 6} {21 8} {21 9} {21 10} {21 11} {21 12} 
-     {21 14} {21 16} {21 17} {21 18} {21 19} {21 20} {21 22} {21 24} {21 25} 
-     {21 26} {21 27} {21 28} {21 30} {22 1} {22 2} {22 3} {22 5} {22 9} 
-     {22 10} {22 11} {22 13} {22 17} {22 18} {22 19} {22 21} {22 25} {22 26} 
-     {22 27} {22 29} {23 0} {23 2} {23 4} {23 6} {23 8} {23 10} {23 12} 
-     {23 14} {23 16} {23 18} {23 20} {23 22} {23 24} {23 26} {23 28} {23 30} 
-     {24 3} {24 7} {24 11} {24 15} {24 19} {24 23} {24 27} {24 31} {25 0} 
-     {25 2} {25 4} {25 6} {25 8} {25 10} {25 12} {25 14} {25 16} {25 18} 
-     {25 20} {25 22} {25 24} {25 26} {25 28} {25 30} {26 1} {26 5} {26 9} 
-     {26 13} {26 17} {26 21} {26 25} {26 29} {27 0} {27 2} {27 4} {27 6} 
-     {27 8} {27 10} {27 12} {27 14} {27 16} {27 18} {27 20} {27 22} {27 24} 
-     {27 26} {27 28} {27 30} {28 1} {28 2} {28 3} {28 7} {28 9} {28 10} 
-     {28 11} {28 15} {28 17} {28 18} {28 19} {28 23} {28 25} {28 26} {28 27} 
-     {28 31} {29 0} {29 1} {29 2} {29 3} {29 4} {29 6} {29 8} {29 9} 
-     {29 10} {29 11} {29 12} {29 14} {29 16} {29 17} {29 18} {29 19} {29 20} 
-     {29 22} {29 24} {29 25} {29 26} {29 27} {29 28} {29 30} {30 1} {30 2} 
-     {30 3} {30 5} {30 9} {30 10} {30 11} {30 13} {30 17} {30 18} {30 19} 
-     {30 21} {30 25} {30 26} {30 27} {30 29} {31 0} {31 2} {31 4} {31 6} 
-     {31 8} {31 10} {31 12} {31 14} {31 16} {31 18} {31 20} {31 22} {31 24} 
-     {31 26} {31 28} {31 30} 
-       ] def
-        /hach3 [
-     {0 7} {0 23} {1 6} {1 8} {1 22} {1 24} {2 5} {2 9} {2 21}
-     {2 25} {3 4} {3 10} {3 20} {3 26} {4 3} {4 11} {4 19} {4 27}
-     {5 2} {5 12} {5 18} {5 28} {6 1} {6 13} {6 17} {6 29} {7 0}
-     {7 14} {7 16} {7 30} {8 1} {8 15} {8 31} {9 2} {9 14} {9 16}
-     {9 30} {10 3} {10 13} {10 17} {10 29} {11 4} {11 12} {11 18} {11 28}
-     {12 5} {12 11} {12 19} {12 27} {13 6} {13 10} {13 20} {13 26} {14 7}
-     {14 9} {14 21} {14 25} {15 8} {15 22} {15 24} {16 7} {16 9} {16 23}
-     {17 6} {17 10} {17 22} {17 24} {18 5} {18 11} {18 21} {18 25} {19 4}
-     {19 12} {19 20} {19 26} {20 3} {20 13} {20 19} {20 27} {21 2} {21 14}
-     {21 18} {21 28} {22 1} {22 15} {22 17} {22 29} {23 0} {23 16} {23 30}
-     {24 1} {24 15} {24 17} {24 31} {25 2} {25 14} {25 18} {25 30} {26 3}
-     {26 13} {26 19} {26 29} {27 4} {27 12} {27 20} {27 28} {28 5} {28 11}
-     {28 21} {28 27} {29 6} {29 10} {29 22} {29 26} {30 7} {30 9} {30 23}
-     {30 25} {31 8} {31 24}
-       ] def
-        /point2 [
-     {0 6} {0 7} {0 8} {0 22} {0 23} {0 24} {1 7} {1 23} {7 15}
-     {7 31} {8 0} {8 14} {8 15} {8 16} {8 30} {8 31} {9 15} {9 31}
-     {15 7} {15 23} {16 6} {16 7} {16 8} {16 22} {16 23} {16 24} {17 7}
-     {17 23} {23 15} {23 31} {24 0} {24 14} {24 15} {24 16} {24 30} {24 31}
-     {25 15} {25 31} {31 7} {31 23}
-       ] def
-      /square [
-	{7 8} {8 8} {9 8} {10 8} {11 8} {12 8} {13 8} {7 9} {7 10} {7 11} {7 12} {7 13} {7 14}
-	{13 9} {13 10} {13 14} {13 11} {13 12} {13 13} {8 14} {9 14} {10 14} {11 14} {12 14}
-	{23 24} {24 24} {25 24} {26 24} {27 24} {28 24} {29 24} {29 25} {29 26} {29 27} {29 28}
-	{29 29} {29 30} {28 30} {27 30} {26 30} {25 30} {24 30} {23 30} {23 29} {23 28}
-	{23 27} {23 26} {23 25}
-      ] def
-      /triangle [
-	{21 9} {22 9} {23 9} {24 9} {25 9} {26 9} {27 9} {28 9} {29 9} {30 9} {31 9}
-	{22 10} {23 11} {24 12} {25 13} {26 14} {27 13} {28 12} {29 11} {30 10}
-      ] def
-      /octogone [
-	{9 24} {10 24} {11 24} {12 25} {13 26} {13 27} {13 28} {12 29} {11 30} {10 30} {9 30}
-	{8 29} {7 28} {7 27} {7 26} {8 25}
-      ] def
-        /point1 [
-     {0 7} {0 23} {8 15} {8 31} {16 7} {16 23} {24 15} {24 31}
-       ] def
-      /x [
-	{23 8}{29 8}{24 9}{28 9}{25 10}{27 10}{26 11}{27 12}{25 12}{28 13}
-        {24 13}{29 14}{23 14}{7 24}{13 24}{8 25}{12 25}{9 26}{11 26}{10 27}
-        {11 28}{9 28}{12 29}{8 29}{13 30}{7 30}
-      ] def
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-     {3 4} {3 10} {3 16} {3 22} {3 26} {3 30} {4 3} {4 9} {4 15} 
-     {4 21} {4 25} {4 29} {5 2} {5 8} {5 14} {5 20} {5 24} {5 28} 
-     {6 1} {6 7} {6 13} {6 19} {6 23} {6 27} {6 31} {7 0} {7 6} 
-     {7 12} {7 18} {7 22} {7 26} {7 30} {8 5} {8 11} {8 17} {8 21} 
-     {8 25} {8 29} {9 4} {9 10} {9 16} {9 20} {9 24} {9 28} {10 3} 
-     {10 9} {10 15} {10 19} {10 23} {10 27} {11 2} {11 8} {11 14} {11 18} 
-     {11 22} {11 26} {12 1} {12 7} {12 13} {12 17} {12 21} {12 25} {12 31} 
-     {13 0} {13 6} {13 12} {13 16} {13 20} {13 24} {13 30} {14 5} {14 11} 
-     {14 15} {14 19} {14 23} {14 29} {15 4} {15 10} {15 14} {15 18} {15 22} 
-     {15 28} {16 3} {16 9} {16 13} {16 17} {16 21} {16 27} {17 2} {17 8} 
-     {17 12} {17 16} {17 20} {17 26} {18 1} {18 7} {18 11} {18 15} {18 19} 
-     {18 25} {18 31} {19 0} {19 6} {19 10} {19 14} {19 18} {19 24} {19 30} 
-     {20 5} {20 9} {20 13} {20 17} {20 23} {20 29} {21 4} {21 8} {21 12} 
-     {21 16} {21 22} {21 28} {22 3} {22 7} {22 11} {22 15} {22 21} {22 27} 
-     {23 2} {23 6} {23 10} {23 14} {23 20} {23 26} {24 1} {24 5} {24 9} 
-     {24 13} {24 19} {24 25} {24 31} {25 0} {25 4} {25 8} {25 12} {25 18} 
-     {25 24} {25 30} {26 3} {26 7} {26 11} {26 17} {26 23} {26 29} {27 2} 
-     {27 6} {27 10} {27 16} {27 22} {27 28} {28 1} {28 5} {28 9} {28 15} 
-     {28 21} {28 27} {29 0} {29 4} {29 8} {29 14} {29 20} {29 26} {30 3} 
-     {30 7} {30 13} {30 19} {30 25} {30 31} {31 2} {31 6} {31 12} {31 18} 
-     {31 24} {31 30} 
-       ] def
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diff --git a/alliance/share/doc/overview/Makefile b/alliance/share/doc/overview/Makefile
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index dbaadc3b..00000000
--- a/alliance/share/doc/overview/Makefile
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diff --git a/alliance/share/doc/overview/na3y.ps b/alliance/share/doc/overview/na3y.ps
deleted file mode 100644
index 52218371..00000000
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-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-%
-% Author : Frederic Petrot
-% Modified by : Olivier Sirol
-% $Id: overview.tex,v 1.4 2000/04/17 12:02:03 czo Exp $
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\documentclass{article}
-\usepackage{t1enc,isolatin1}
-\usepackage{palatino,psfig,here}
-\textheight 9.0in
-\textwidth 6.0in
-\topmargin -0.0in
-\oddsidemargin +0.3in
-\evensidemargin -0.3in
-\marginparwidth +0.5in
-\parskip 8pt plus 2pt minus 2pt % space beetween paragraphe
-\parindent 0em % indentation of the first line
-\topsep 0pt % space beetween list and text
-\parsep 8pt % space beetween 2 par.
-\partopsep 0pt % space beetween 2 par.
-\itemsep 0pt % space beetween 2 items
-\raggedbottom
-\begin{document}
-%\psdraft
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\begin{center}
-\Large \textbf{Alliance}: A Complete CAD System for \textbf{VLSI} Design\\
-\vspace*{1cm}
-\large
-Équipe Achitecture des Systèmes et Micro-Électronique\\
-Laboratoire d'Informatique de Paris 6\\
-Université Pierre et Marie Curie\\
-4, Place Jussieu 75252 Paris Cedex 05,\\
-France\\
-\texttt{http://www-asim.lip6.fr/alliance/}\\*
-\texttt{ftp://ftp-asim.lip6.fr/pub/alliance/}\\*
-\texttt{mailto:alliance-support@asim.lip6.fr}\\*
-\end{center}
-
-%%%%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\section*{\centerline{Abstract}}
-\begin{quote}\em
-The \textbf{Alliance} package is a complete set of CAD tools for the
-specification, design and validation of digital \textbf{VLSI} circuits.
-Beside the tools, \textbf{Alliance} includes also a set of cell 
-libraries, from standard cells for automatic place and route tools, 
-to custom block generators to be used in high performance circuits.
-This package is used in more than 250 universities worldwide.
-
-Each \textbf{Alliance} tool can operate as a standalone program as 
-well as a part of the complete design framework.
-After introducing briefly the design methodology, we outline the
-functionnality of the tools.
-Experiemental results conclude the presentation.
-
-\textbf{Alliance} runs on any \textbf{Unix} system and has been recently
-ported to \textbf{Windows} NT.
-It is freely available on \texttt{ftp}, 
-and includes binaries, leaf
-cells libraries, on-line documentation, and tutorials.
-\rm\end{quote}
-
-
-
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%
-\section{Introduction}
-
-The \textbf{Alliance} package is the result of a ten years effort 
-spent at the \textbf{LIP6} Laboratory (formerly \textbf{MASI}) 
-of the Pierre et Marie Curie University (UPMC), in Paris.
-During these years, our major goal was to provide our undergraduate 
-and graduate students with a complete CAD framework, designed to 
-assist them in digital \textbf{VLSI} \textbf{CMOS} course.
-The \textit{Architecture} team at \textbf{LIP6} focuses its activity on 
-two key issues: computer architectures using high complexity ASICs, 
-and innovative CAD tools for \textbf{VLSI} design.
-Strong interaction exists between the people working on computer 
-architectures and the one working on CAD tools.
-The main CAD action aims at fulfilling both the needs of experienced 
-designers by providing practical answers to state-of-the-art problems 
-(logic synthesis, procedural generation, layout verification, test and
-interoperability), and novice designers, by providing a simple and
-consistent set of tools.
-Our \textbf{VLSI} design flow is therefore based on both advanced CAD tools 
-that are not available within commercial CAD systems, such as 
-functional abstraction or static timing 
-analysis, and standard design/validation tools.
-
-\textbf{Alliance} VLSI CAD System is free software. Binaries, source code and 
-cells libraries are freely available under the GNU General Public Licence (\textbf{GPL}).
-You are welcome to use the software package even for commercial designs whithout 
-any fee. You are just required to mention : "Designed with Alliance © LIP6/Université 
-Pierre et Marie Curie". For any questions please mail to : 
-\texttt{alliance-support@asim.lip6.fr}.
-
-
-
-%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{Process independence}
-
-To be useful, a CAD system must provide a way to the silicon,
-therefore \textbf{Alliance} provides a large set of cell libraries
-also available at the layout level.
-The target technologies of \textbf{Alliance} is \textbf{CMOS}.
-The layout libraries rely on a symbolic layout approach that provides 
-process independence in order to allow the designers to easily
-port their designs from one silicon supplier to another.
-The main point in this approach is that the pitch matching constraints
-in both \textit{x} and \textit{y} direction are kept through
-technological retargetting.
-The translation, fully automated, relies on a technological file
-suited to a given process.
-
-These files can be generated directly from the process design rules.
-Also technological files for several processes are available through
-the CMP and EuroPractice services, provided you signed a NDA for the
-process.
-
-%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{Software portability}
-
-The \textbf{Alliance} package has been designed so to run on an
-heterogeneous network of workstations.
-The only requirements are a \textbf{C} compiler and a \textbf{Unix} system.
-For the graphical applications, the XWindow library is used.
-Several hardware platforms, from Intel 386 based microcomputers to
-SparcStations and DEC Stations, are supported.
-
-%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-\subsection{Modularity}
-
-According to the interoperability constraints, each \textbf{Alliance} 
-tool can operate as a standalone program as well as a part of the 
-complete \textbf{Alliance} design framework.
-Each \textbf{Alliance} tool therefore supports several standard \textbf{VLSI} 
-description formats : \textbf{SPICE}, \textbf{EDIF}, \textbf{VHDL}, \textbf{CIF},
-\textbf{GDS2}.
-In that respect, the tools ouputs are fully usable under the
-\textbf{Compass} and \textbf{Cadence Opus} environnement, provided these
-tools have the necessary configuration files.
-The \textbf{Alliance} tools support a zero-default top-down design
-methodology with not only construction tools --- layout editor, automatic
-place \& route --- but also validation tools, from design rule checker to
-functional abstraction and formal proof.
-
-%%%%%%%%%%%%%%%%%%%%%     
-%                                                                    
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%                                   
-\subsection{Compactness}
-
-Unlike commercially available CAD systems, the \textbf{Alliance} CAD 
-Framework suits the limited ressources of low-cost workstations.
-For small educational projects --- 5000 gates ---, a \textbf{Unix} 
-system with 8 to 20 Mbytes of memory, appropriate disk storage (30 
-Mbytes per user), and graphic capabilities (X-Window) is sufficient.
-
-%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{Easiness}
-
-All tools and the proposed design flow are simple to teach and to 
-learn.
-In any situation, easiness and simplicity have been prefered to 
-sophisticated approaches.
-
-To each tool correspond a unique behavior and utility.
-Each step of the design methodology corresponds to the use of one or a
-few tools, for which the usage is well identified.
-
-From a pratical point of view, both on-line documentation (\textbf{Unix}
-\texttt{man}) and paper are available with each tool of the
-\textbf{Alliance} package.
-
-%%%%%%%%%%%%%%%%%%%%%        
-%        
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%        
-\section{Alliance design flow}
-
-We refer to the term "design flow" as a sequenced set of 
-operations performed when realizing a \textbf{VLSI} circuit.
-In the design flow, we rely on a strict definition of all the
-objects and design functions found in the process of designing a
-\textbf{VLSI} chip.
-The design flow is based on the Mead-Conway model and is 
-characterized by its top-down aspect.
-Below we introduce the major steps of the basic design methodology.
-It emphasizes the top-down aspect of the design flow, and points out 
-that our methodology is breaked up into 5 distinct parts, the latter 
-being not available yet within \textbf{Alliance}:
-\begin{itemize}
-\item capture and simulation of the behavioral view,
-\item capture and validation of the structural view,
-\item physical implementation of the design,
-\item layout verification,
-\item test and coverage evaluation.
-\end{itemize}
-
-The design flow also includes miscellaneous tools like layout editor
-for the design of the cell libraries, and a PostScript plotter for
-documentation.
-
-%%%%%%%%%%%%%%%%%%%%%        
-%        
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%        
-\subsection{Capture and simulation of the behavioral view}
-
-Like we just saw, the capture of the behavioral view is the
-very first step of our design flow.
-Within \textbf{Alliance}, any \textbf{VLSI} design begins with a timing 
-independent description of the circuit with a subset of \textbf{VHDL} 
-behavior primitives.
-This subset of \textbf{VHDL}, called \texttt{vbe}, is fairly 
-restricted: it is the data-flow subset of this language.
-It is not very easy to modelize an architecture using this subset, 
-but it has the great advantage of allowing simulation, logic synthesis
-and bit level formal proof on the same files.
-
-Patterns, \textbf{VHDL} simulation stimuli, are described in a specific 
-formalism that can be captured using a dedicated language \texttt{genpat}.
-Once a \textbf{VHDL} behavioral description written and a set of test vectors 
-have been determined, a functional simulation is ran.
-The behavioral \textbf{VHDL} simulator is called \texttt{asimut}.
-It validates the input behavior, according to the input/output vectors.
-
-
-%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{Capture and validation of the structural view}
-
-The structural view can be captured once the data flow description 
-is validated.
-The actual capture of the netlist relies either on specific 
-description languages, \texttt{genlib} for standard cells or \texttt{fpgen}
-for data-path, or on direct synthesis from the data flow  using the
-\texttt{bop} tool for optimization and the \texttt{scmap} tool to map
-on a cell library.
-\texttt{Genlib} and \texttt{fpgen} are netlist-oriented libraries of C 
-functions.
-In the design methodology, it is essential for the students to get 
-acquainted with the \textbf{C} language basics.
-The advantage of such an approach is that designers do not have to 
-learn several language with specific syntax and semantics.
-
-Usually, the main behavior is partitionned in several sub-behaviors.
-Some are described recursively using the \texttt{genlib} language, other
-using \texttt{fpgen}, and the other ones can be directly synthesized 
-from a \textbf{VHDL} description of the corresponding sub-behaviors.
-The \texttt{scmap} tool takes an \textbf{RTL} description and 
-generates a netlist of standard cell gates.
-An other subset of \textbf{VHDL} allows to capture finite state machines.
-This subset, called \texttt{fsm}, can be translated into a 
-\textbf{RTL} description using the tool \texttt{syf}, and then the 
-resulting description optimized usign \texttt{bop} and finally 
-syntesized as a netlist using once more \texttt{scmap}.
-
-Since \texttt{asimut} can operate on both \textbf{RTL} and structural views,
-the structural description is checked against the behavioral 
-description by using the same set of patterns that has been used for
-behavioral validation.
-
-%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{Physical design}
-
-Once the circuit netlist has been captured and validated, each leaf of
-the hierarchy has to be physically implemented.
-A netlist issued from \texttt{scmap} is usually placed and routed using
-the standard cell router \texttt{scr}.
-If the netlist has been captured using \texttt{genlib} and if it has a
-high degree of regularity, it can be placed manually for optimisation
-using other \texttt{genlib} functions.
-The netlist resulting from the use of \texttt{fpgen} are placed and
-routed using the datapath router \texttt{dpr}.
-
-These part can be assembled together using a gridless channel router
-called \texttt{bbr}, and this generates what we call a \textit{core}.
-The circuit core is now ready to be connected to external pads.
-The core-to-pads router, \texttt{ring}, aims at doing this operation 
-automatically, provided the user has given an appropriate netlist and
-some indications on pad placement.
-
-The last stage of the physical implementation is the translation of
-the symbolic layout to a foundry compliant layout using the 
-\texttt{s2r} tool.
-After that, the tape containing the circuit can be processed by the
-silicon supplier.
-
-%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{Verification}
-
-In our \textbf{VLSI} class, we intend to show that \textbf{VLSI} 
-verification is at least as important as \textbf{VLSI} physical 
-design.
-For that reason, we have introduced in the design flow powerful tools 
-to perform behavior, netlist and layout verifications.
-
-The correctness of the design rules is checked using the design rule
-checker \texttt{druc}.
-
-An extracted netlist can be obtained from the resulting layout.
-\texttt{Lynx}, the layout extractor operates on both hierarchical and 
-flattened layout and can output both flattened netlists (transistor 
-netlist) and hierarchical netlists.
-The transistor netlist is the input of the \texttt{yagle} functional 
-abstractor.
-\texttt{Yagle} provides a \textbf{VHDL} data-flow behavioral 
-description, identical to the one that feeds \texttt{asimut},  from 
-the transistor netlist of a circuit.
-The resulting behavior can be compared to the initial specifications
-using either \texttt{asimut} with the functionnal vectors used for the
-validation of the behavioral specification, or formally proved
-equivalent, thanks to the formal proof analyzer \texttt{proof}.
-
-When extracted hierarchically, the resulting netlist can be compared 
-with the original netlist by using the \texttt{lvx} tool.
-\texttt{Lvx}, that stands for Logical Versus Extracted, is a netlist 
-comparator that matches every design object found in both netlists.
-
-The critical path of the circuit, and an estimate of its delay, can be
-obtained using the static timming analyzer \texttt{tas}.
-
-%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{Test and coverage evaluation}
-
-For now, the fault coverage provided by the functional patterns is
-evaluated using a commercial fault simulator, as \textbf{Alliance}
-doesn't provide one yet.
-
-%%%%%%%%%%%%%%%%%%%%%                            
-%                            
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%                            
-\section{Tools and layout libraries of the \textbf{Alliance} package}
-
-Every \textbf{Alliance} tool has been designed to simply interface with 
-each other, in order to support the proposed design flow.
-Nevertheless, each tool can also be used independently, thanks to the 
-multiple standard formats used for input and output files.
-
-One of the most important characteristics of the \textbf{Alliance} system is 
-that it provides a common internal data structure to represent the 
-three basic views of a chip: 
-\begin{itemize}
-\item the behavioral view,
-\item the structural view,
-\item the physical view.
-\end{itemize}
-
-Figure~\ref{tools} details how all the \textbf{Alliance} tools are linked 
-together around the basic behavioral, structural and physical 
-data structures.
-
-\begin{figure}\center
-\leavevmode\psfig{file=tools.eps,width=8cm}
-\caption{\label{tools}How the tools are linked on the data structures.}
-\end{figure}
-
-The process independence goal is achieved with a thin fixed-grid 
-symbolic layout approach.
-All the library of the system use this approach successfully.
-Layouts have been targetted to ES2 2$\mu$m, 1.5$\mu$m, 1.2$\mu$m,
-1.0$\mu$m and 0.7$\mu$m technologies, the AMS 1.2$\mu$m technology and
-SGS-Thomson 0.5$\mu$m technology.
-Chips have been fabricated successfully through the \textbf{CMP} services on
-these technologies.
-
-%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{Tools}
-
-\begin{itemize}
-\item \texttt{asimut} is a \textbf{VHDL} logic simulator.
-      The supported \textbf{VHDL} subset allows both structural and behavioral 
-      data-flow description (without timing information).  
-      Complex systems and microprocessors, including \textbf{INTEL} 8086 and 
-      \textbf{MIPS} R3000 have been successfully simulated with \texttt{asimut}.
-      \texttt{Asimut} is based on an event-driven algorithm and powerful 
-      representation of boolean functions using binary decision
-      diagrams.
-
-\item \texttt{genpat} is a language interpreter dedicated to efficient 
-      descriptions of simulation stimuli.
-      It generates an \textbf{ASCII} file that can act as an input of 
-      \texttt{asimut}.
-      A \texttt{genpat} file format to \textbf{MSA} translator allows the 
-      generation of appropriate simulation patterns for the Tektronix 
-      LV500 tester.
-      This allows to perform functional tests when the circuits comes
-      back from the foundry.
-
-\item \texttt{glop} is a gate level netlist optimizer.
-      If the output of the logic synthesis takes into account the
-      internal delays of the cells during the mapping phase, it 
-      doesn't take into account the fan-out problems.
-      \texttt{Netoptim} work is to ensure that the drive capabilities of
-      all cells are correct, and to try to minimize the delays on the
-      critical pathes in inserting buffers where appropriate.
-
-\item \texttt{genlib} is a procedural language for netlist capture and 
-      placement description (there is no schematic editor in the
-      \textbf{Alliance} system).
-      \texttt{Genlib} provides a consistent set of \textbf{C} 
-      primitives, giving the designers the ability to describe 
-      \textbf{VLSI} circuit netlists in terms of terminals, signals 
-      and instances, or circuit topologies in terms of placement of 
-      abutment boxes.  
-      \texttt{Genlib} is mainly used to build parameterized netlist and
-      layout generators.
-
-\item \texttt{genview} is a debugging tool for the development of the
-      layout view of parameterized generators.
-      It is a graphical environment that integrates a \texttt{genlib}
-      interpreter, a step by step debugger, and a window in the which 
-      the circuit under construction is visualized.
-      All the parameterized generators of \textbf{Alliance} have been
-      developed using this tool.
-      Part of the \textit{ROM} generator \texttt{grog} under construction
-      is shown figure~\ref{genview}.
-      
-      \begin{figure}\center
-%      ,angle=-90}
-         \leavevmode\psfig{file=genview.eps,width=5cm}         
-         \caption{\label{genview}A typical run of \texttt{genview}.}
-      \end{figure}
-
-      \texttt{Genview} uses the GNU \texttt{gcc} compiler parameterized for
-      a virtual architecture as basis to its \texttt{genlib} interpreter.
-
-\item \texttt{fpgen} is a language that has moreorless the same
-      functionalities as \texttt{genlib}, but it is dedicated to datapath
-      description.
-      Its primary difference with \texttt{genlib} is that it allows to
-      manipulate vectors of cells, like 32 two inputs \texttt{nand} gates
-      or a 32 bits adder.
-      It contains many primitives that greatly simplify the
-      description of operative parts, in an optimized manner.
-
-\item \texttt{bop} is a logic optimizer and logic synthesis tool.
-      The input file is a behavioral description of the circuit using 
-      the same \textbf{VHDL} subset as the logic simulator.
-      The boolean equations described in \textbf{VHDL} are optimized so
-      to minimize the number of boolean operators.
-      The output is a new, optimized, data flow description.
-
-\item \texttt{scmap} is a logic synthesis tool.
-      The output is a netlist of gates.
-      \texttt{scmap} can map a data-flow description on any 
-      standard-cell library, as long as a \textbf{VHDL} data-flow
-      description is provided with each cell.
-
-\item \texttt{c4map} is a logic synthesis tool.
-      It has the same functionnality than \texttt{scmap}, but runs 
-      without a predefined standard-cell library, thanks to an 
-      internal cell compiler.
-
-\item \texttt{syf} is a finite state machine synthesizer.
-      More precisely, \texttt{syf} assigns values to the symbolic states
-      used for the automaton description, and aims at minimizing the
-      resulting logic for both state transistion and output generation.
-      The input is a \texttt{fsm} description, using a dedicated subset
-      of \textbf{VHDL} that includes process description.
-      The output is a behavioral description of the circuit using 
-      the same \textbf{VHDL} subset as the logic simulator.
-      The output of \texttt{syf} is to be synthesized into a netlsit of
-      gates using \texttt{scmap}.
-
-\item \texttt{scr} is a place and route tool for standard-cells.
-      The placement system is based on simulated annealing.
-      The channel router is an adaptation of the greedy router of
-      Rivest-Fidducia.
-      Feed-throughs and power routing wires are automatically 
-      inserted where needed.
-      The input is a netlist of gates.
-      The output is either an hierarchical (channels are 
-      instanciated) or flattened (channels are inserted) chip core 
-      layout without external pads.  
-      A specialized router is used for core to pad routing.
-      
-\item \texttt{Dpr} is a place and route tool for bit slice oriented 
-      datapath.
-      It privilegies the direct connexions between cells, and allows
-      to used optimized blocks, like a fast multiplier or a register
-      file, within the datapath.
-      \begin{figure}\center
-      \leavevmode\psfig{file=datapath.eps,width=5cm}
-      \caption{\label{dpr} Part of a datapath.}
-      \end{figure}
-      Most parameterized generators available in \textbf{Alliance} follow
-      the bit-slice structure of this datapath compiler.
-      This tool allows to mix some glue logic directly within a
-      datapath.
-      This functionnality doesn't exist in commercial tools.
-
-\item \texttt{bbr} is a gridless channel router that allows to route
-      together two blocks having different topologies.
-      For example the control part of a microprocessor realized in
-      standard cell, and its operative part done as a datapath.
-      \texttt{Bbr} is pretty tricky, and should be used with care.
-
-\item \texttt{Ring} is a specific router dedicated to the final routing 
-      of chip core and input/output pads.
-      \texttt{Ring} takes into account the various problems of pad 
-      placement optimization, power and ground distribution.
-      A set of symbolic pads is included in the package.
-
-\item \texttt{S2r} is the ultimate tool used in our design flow to 
-      perform process mapping.
-      \texttt{S2r} stands for "symbolic to real", and translates the 
-      hierarchical symbolic layout description into physical layout 
-      required by a given silicon supplier.
-      The translation process involves complex operations such as 
-      denotching, oversizing, gap-filling and layer adaptation.
-      Output formats are either \textbf{CIF} or \textbf{GDSII}.
-      \texttt{S2r} requires a parameter file for each technology aimed at.
-      This file is shared with \texttt{druc}, \texttt{lynx}, \texttt{graal},
-      \texttt{dreal} and \texttt{genview}.
-      From an implementation point of view, these tools use a 
-      bin-based data-structure that has very good performances.
-
-\item \texttt{druc} is a design rule checker.
-      The input file is a - possibly hierarchical - symbolic layout.
-      It checks that a layout is correct regarding the set of symbolic
-      design rules.
-      This correctness must be ensured in order for \texttt{s2r} to
-      produce a layout compatible with the target silicon foundry.
-
-\item \texttt{Lynx} is a layout extractor.
-      The input is a - possibly hierarchical - layout.
-      The layout can be either symbolic or real.
-      The output is an extracted netlist with parasitic capacitances.
-      The resulting netlist can either be hierarchical or flattened 
-      (transistor netlist).
-
-
-\item \texttt{Lvx} is a logical versus extracted net-compare tool.
-      The result of a run indicates if the two netlist match together,
-      or if there are different.
-      Note that \texttt{lvx} doesn't work at the transistor level.
-
-\item \texttt{yagle} is a functional asbtractor/disassembler for
-      \textbf{CMOS} circuits.
-      It provides a \textbf{VHDL} Data-Flow behavioral description from 
-      the transistor netlist of a circuit, by first extracting a 
-      pseudo-gate netlist, and second translating each pseudo-gate in
-      boolean equations.
-      The input file is a - possibly extracted - flattened transistor 
-      netlist.
-      The output is a simulable behavioral \textbf{VHDL} model 
-      (data-flow without timing informations).
-      \texttt{Yagle} can be distinguished from commercial CAD 
-      abstractors by the fact that it does not need a predefined cell 
-      library or transistor patterns.  
-      Furthermore, the use of a purely algorithmic approach compared
-      to a pattern matching one implies a huge gain in performance.
-      Yagle is not anymore part of Alliance, but is freely available 
-      at \texttt{http://www.avertec.com}.
-
-\item \texttt{tas} is a static timing analyzer.
-      It takes as input a transistor netlist and produces a file
-      containing all the combinatorial paths of the circuit,
-      the critical path being outlined. 
-      Tas is not anymore part of Alliance, but is freely available 
-      at \texttt{http://www.avertec.com}.
-
-\item \texttt{proof} performs a formal comparison between two data
-      flow \textbf{VHDL} descriptions that share the same register set.
-      \texttt{Proof} supports the same subset of \textbf{VHDL} as 
-      \texttt{asimut}, \texttt{bop}, \texttt{scmap} and \texttt{yagle}.
-
-\item \texttt{graal} is an hierarchical symbolic layout editor.
-      It requires a X-Window graphical environment and the Motif libraries.
-      \texttt{Graal} is used for cell layout design or hierarchical 
-      block construction.
-      It provides an on-line \textbf{DRC} and automatic display of 
-      equipotential nets.
-      Editing a cell under \texttt{graal} is shown figure~\ref{graal}.
-      
-       \begin{figure}\center
-          \leavevmode\psfig{file=graal.eps,width=5cm}
-          \caption{\label{graal}Editing some custom layout using \texttt{graal}.}
-       \end{figure}
-
-\item \texttt{L2p} creates a Postscript file from a layout, symbolic or
-      real.
-\end{itemize}
-
-%%%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{Cell libraries}
-
-The \textbf{Alliance} package provide a wide range of libraries, either
-static, ie. fixed cells, or dynamic, as the block is produced by
-running a parameterized generator.
-These libraries are compatible with any two metals/one polysilicon
-technology.
-
-Each object in the library has, for static ones, or produces, for
-dynamics ones, three views at least :
-\begin{itemize}
-\item the symbolic layout, that describes the cell topology.
-\item the netlist, in terms of transistor interconnections.
-\item the behavior, specified in \textbf{VHDL} data flow form.
-\end{itemize}
-
-Area loss due to the symbolic layout compared to micron design has 
-been estimated ranging from 10\% to 20\%.
-In any case, loosing area is affordable, where loosing years is not.
-
-%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsubsection{Standard cell library}
-
-The \texttt{sclib} library contains boolean functions, buffers, mux,
-latches, flip-flops, $\ldots$ (around 70 cells).
-All the cells have the same height, share the power and ground lines 
-on east and west side, and have pitched I/Os in metal2 on north and 
-south side.
-They are supposed to be used with a usual standard cells place and
-route tool, such as \textbf{Alliance}'s \texttt{scr}, \textbf{Compass} or
-\textbf{Cadence}.
-These cells are to be used primary for glue logic, since optimized
-operators can be obtained using dedicated generators, as stated 
-paragraph~\ref{gene}.
-The \texttt{logic} tool can map a behaviral VHDL onto this library.
-
-
-The figure~\ref{trs} below shows the difference between \texttt{sclib}
-and \texttt{dplib} regarding the shape and contents of a cell.
-\begin{figure}[H]\center
-      \hfill
-      \begin{minipage}[b]{4cm}
-         \leavevmode\psfig{file=na3y.ps,width=4cm}
-         \caption{\textit{Sclib} version of a three inputs \texttt{and} gate}
-      \end{minipage}\hfill%
-      \begin{minipage}[b]{4cm}
-         \leavevmode\psfig{file=na3dp.ps,width=4cm}
-         \caption{\textit{Dplib} version of a three inputs \texttt{and} gate}
-      \end{minipage}
-      \hfill
-      \label{trs}
-\end{figure}
-\noindent
-
-
-%%%%%%%%%%%%%%%%%%
-%%
-%%%%%%%%%%
-\subsubsection{Datapath libraries}
-\label{gene}
-
-There are two kinds of datapath libraries:
-\begin{itemize}
-\item \texttt{dplib} is a cell library dedicated to high density data-paths.
-      It must be used in conjunction with the data-path tools
-      \texttt{fpgen} and \texttt{dpr}.
-      The cells in \texttt{dplib} have the same functionnalities as the
-      ones in \texttt{sclib}, but have a topology that is usable only
-      within a datapath.
-      \texttt{Scmap} can also map a behavior onto the \texttt{dplib}
-      library.
-      
-\item \texttt{fplib} is a set of above 30 regular functions that are
-      useful in the design of a datapath.
-      These functions range from a \textit{n} inputs \texttt{nand} gate to
-      a \textit{n $times$ m} register file.
-\end{itemize}
-
-
-Here the cells share the power and ground lines in metal2.
-A powerful dedicated over the cell router can route custom
-blocks and logic glue in the same structure.
-Among the \texttt{fplib} functionnalities, four optimized blocks 
-generators should be presented in more details, as they reflect the
-quality of this library.
-All the generators are build with a tiler using a dedicated leaf cell
-library.
-Their output is a symbolic layout, a \textbf{VHDL} behavior, a set of 
-pattern for test purpose, a netlist, an icon, and a datasheet 
-indicating size and timing estimation for a given technology.
-The structural parameters varies according to their functionalities.
-\begin{itemize}
-\item optimized generators for datapath operators:
-      \begin{description}
-      \item[\tt rsa\rm ,] a fast adder generator, with propagation time
-           in log \textit{nb} and size in \textit{nb\/ \rm log \it nb},
-           where \textit{nb} is the number of bits.
-           Its has 2 or 3 input buses, and if needed a carry input.
-           It may be used as a substractor or adder/substractor.~\\
-           \begin{tabular}{|p{7ex}|p{45ex}|p{15ex}|}
-           \hline
-           Params & Meaning            & Range \\
-           \hline
-           nb         & number of bits     & 3 to 128\\
-           cin        & carry in           & true or false\\
-           csa        & three inputs adder & true or false\\
-           ovr        & overflow flag      & true or false\\
-           \hline
-           \end{tabular}
-      \item[\tt rfg\rm ,] a static register file generator.
-           It has one write address , and one or two read address.
-           It may be operated as a set of level-sensitive latches
-           or edge triggered flip-flops.~\\
-           \begin{tabular}{|p{7ex}|p{45ex}|p{15ex}|}
-           \hline
-           Params & Meaning            & Range \\
-           \hline
-           nb         & number of bits     & 2 to 64\\
-           nw         & number of words    & 2 to 256\\
-           bus        & number of read bus & 1 or 2\\
-           op         & mode of operation  & latch or flip-flop\\
-           low power  & reduce power consumption & true or false\\
-           \hline
-           \end{tabular}
-      \item[\tt bsg\rm ,] a barrel shifter generator.
-           Possible operations are :
-           \begin{itemize}
-           \item logical right shift
-           \item arithmetical right shift
-           \item logical left shift
-           \item arithmetical left shift
-           \item right rotation
-           \item left rotation
-           \end{itemize}
-           \begin{tabular}{|p{7ex}|p{45ex}|p{15ex}|}
-           \hline
-           Params & Meaning            & Range \\
-           \hline
-           nb         & number of bits     & 3 to 64\\
-           \hline
-           \end{tabular}
-      \item[\tt amg\rm ,] an integer modified booth algorithm array
-           multiplier.
-           the \textit{x} and \textit{y\/} inputs are independent,
-           and pipeline stages can be inserted in the circuit.~\\
-           \begin{tabular}{|p{7ex}|p{45ex}|p{15ex}|}
-           \hline
-           Params & Meaning & Range \\
-           \hline
-           nx  & number of bits of the \textit{x} operand & 8 to 64\\
-           ny  & number of bits of the \textit{y} operand & 8 to 64\\
-           ps  & number of pipeline stages to be inserted in the
-                 circuit & 0 to min($\frac{\rm nx}{\rm 2}$\rm,
-                               $\frac{\rm ny}{\rm 2}$)-\rm 1\\
-           \hline
-           \end{tabular}
-\end{description}
-\end{itemize}
-
-%%%%%%%%%%%%%%%%%%
-%%
-%%%%%%%%%%
-\subsubsection{Custom libraries}
-Two full-custom parameterized generators are also available.
-They produce stand-alone blocks, that are to be routed only at the
-floorplan level with other blocks, using either \texttt{bbr} or better 
-\texttt{xcheops}.
-
-\begin{itemize}
-\item \textit{ROM} and \textit{RAM\/} generators:
-      \begin{description}
-      \item[\tt grog\rm ,] a generic \textit{ROM} generator.
-           The interface is an address bus, a clock and an output
-           enable signal, and a data out bus.
-           The coding format to specify the \textit{ROM} contents
-           is a limited subset of VHDL.~\\
-           \begin{tabular}{|p{7ex}|p{45ex}|p{15ex}|}
-           \hline
-           Params & Meaning            & Range \\
-           \hline
-           nb         & number of bits     & 1 to 64\\
-           nw         & number of words    & 64, 128, 256,
-                          \textit{n~\rm 512,~1~$\leq$~\it n~$\leq$~\rm 8}\\
-           hz         & tri-state output   & true or false\\
-           \hline
-           \end{tabular}
-      \item[\tt rage\rm ,] a \textit{RAM} generator.
-           The interface has a read/write address, a write signal
-           indicating if a read or a write is to be performed, and a
-           clock.~\\
-           \begin{tabular}{|p{7ex}|p{45ex}|p{15ex}|}
-           \hline
-           Params & Meaning            & Range \\
-           \hline
-           nb         & number of bits     & 2 to 128\\
-           nw         & number of words    & 128 to 4096\\
-           aspect     & aspect ratio       & narrow, medium or large\\
-           ud         & unidirectional, ie share the same bus for data in
-                        and out            & true or false\\
-           \hline
-           \end{tabular}
-      \end{description}
-\end{itemize}
-All these generators have been designed using the \textbf{Alliance} CAD
-tools, for both design and verification phases.
-
-%%%%%%%%%%%%%%%%%%
-%%
-%%%%%%%%%%
-\subsubsection{Pad library}
-
-\textbf{Alliance} provides also a pad library.
-This library also uses a symbolic layout approach, and therefore a
-whole chip can be targeted on several technology without even the core
-to pad routing.
-A very robust approach has been enforced, as the pads are subject to
-electrostatic discharge, and also more sensible to latch-up than the
-other parts of the circuit due to the amount of current that flows
-through them.
-
-Chips using these pads have been fabricated on ES2 1.0$\mu$m,
-AMS 1.2$\mu$m and SGS-Thomson 0.5$\mu$m technology and work as 
-expected.
-%%%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\section{Supported exchange formats}
-
-The \textbf{Alliance} CAD system handles many file formats.
-They are summarized here.
-A file can be either read, using a \textit{parser}, or written, using a
-\textit{driver}.
-
-\begin{itemize}
-\item Behavioral view:
-      \begin{itemize}
-      \item dataflow \textbf{VHDL} parser and driver.
-      \end{itemize}
-\item Structural view:
-      \begin{itemize}
-      \item \textbf{VHDL} parser and driver.
-      \item \textbf{EDIF} parser and driver.
-      \item \textbf{Spice} parser and driver.
-      \item \textbf{Compass} parser and driver.
-      \item \textbf{Alliance} parser and driver.
-      \item \textbf{Hilo} driver
-      \end{itemize}
-
-\item Physical view:
-      \begin{itemize}
-      \item \textbf{Alliance} parser and driver, for symbolic layout.
-      \item \textbf{Compass} parser and driver, for symbolic layout.
-      \item \textbf{Modgen} parser and driver, for symbolic layout.
-      \item \textbf{CIF} parser and driver, for real layout.
-      \item \textbf{GDSII} parser and driver, for real layout.
-      \end{itemize}
-\end{itemize}
-
-Being able to understand and write many file formats is a must.
-First, in a development environment, as it allows to check the 
-validity of tools on other CAD systems.
-Second, because some tools are not available or desirable within
-\textbf{Alliance}, but may be useful however: it is possible to feed an
-other software with a design in that situation.
-
-The experience showa that many of these formats are used daily.
-For example, the design that we fabricate through the CMP
-services are transmitted using the \textbf{GDSII} format.
-The final \textbf{DRC} on these files are performed using \textbf{Cadence}
-\texttt{pdverify}.
-
-An other example: \textbf{Alliance} does not have a fault simulator yet.
-However this kind of tool is very useful to evaluate the fault
-coverage of a set of vectors and must be introduced in a \textbf{VLSI}
-class.
-This is hopefully easilly done using the \textbf{Hilo} output of
-\textbf{Alliance} that feed the \texttt{hifault} simulator.
-
-%%%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\section{\textbf{Alliance} internal organization}
-
-The complete \textbf{Alliance} CAD system contains about 600 000 
-lines of C code, and over 600 leaf cells.
-It compiles and runs on most \textbf{Unix} system, and requires the basic 
-X-Window library X11 plus Motif.
-The distribution tape shows that there are three kinds of files:
-
-\begin{itemize}
-\item common data structures and manipulation primitives.
-\item parsers/drivers to read and write external file formats.
-\item actual tools.
-\end{itemize}
-
-\textbf{Alliance} as been developed in order to simplify cooperative 
-work between the CAD tool designers.
-The existence of a common data structure framework releaves the
-developer of many burdens: reading and writing many file format,
-conceptualizing the VLSI objects, writing classical high level and 
-nevertheless complex functions, ...
-All the \textbf{Alliance} tools share these data structures and their
-related functions.
-So each tool communicates with the other ones smoothly, by construction.
-
-%%%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\section{Use of \textbf{Alliance} inside our laboratory}
-
-\textbf{Alliance} is used for both educational and research purposes.
-We relate our experience below.
-
-\subsection*{Educational aspects}
-
-The \textbf{Alliance} System has been extensively used during the past 
-eight academic years (89-97) as a practical support of two 
-undergraduate courses: one on \textbf{CMOS} \textbf{VLSI} design, the other
-one on \textbf{advanced computer architecture}.
-These initiation courses lasts 13 weeks with a 2 hours lecture and 4 
-hours spent using the \textbf{Alliance} system per week, and involves 60 
-students and 3 teachers.
-
-The `\textbf{VLSI} design' course is for students that have no previous 
-knowledge on \textbf{VLSI} design and mainly come from two distinct 
-channels: 
-"computer science" and "electrical engineering" masters of sciences.
-During this course, students are required to design and implement an 
-\textbf{AMD2901} compatible processor, starting from a commercial data-sheet.
-The chip, with a complexity of about 2000 transistors, is designed by 
-groups of 2 or 3 students.
-The main interest in this course is to teach the design methodology.
-Most of the \textbf{Alliance} tools are used during this class.
-
-The `architecture' course focuses on the way processor architecture, from
-the system point of view and not from an implementation one.
-Typical \textbf{CISC} and \textbf{RISC} processors are studied, and part of
-them modelized using our \textbf{VHDL} subset.
-In that class, only the \texttt{asimut} simulator is used.
-
-\textbf{Alliance} is also used in an intensive graduate course, for the
-design of the 32 bits microprocessor \texttt{dlx} \textbf{RISC} processor
--- 30000 transistors --.
-This course lasts two months, and aims only at the implementation~: 
-the high level behavioral model of the processor is given to the 
-students.
-During that period of time, all the \textbf{Alliance} tools are 
-used.
-
-\subsection*{Research projects}
-
-These projects range from medium complexity ASICs developed in 6 
-months by a couple of designers \textbf{Data-safe}, \textbf{TNT},
-\textbf{Smal}, \textbf{Rf264},etc...) to high complexity circuits
-(\textbf{FRISC}, \textbf{Multick}, \textbf{StaCS}, \textbf{Rapid2}, \textbf{Rcube}) 
-developed by a team of PhD students.
-
-\begin{figure}\center
-\begin{tabular}{|c|c|l|}
-\hline
-Project         & transistors & Functionality\\
-\hline
-\textbf{Smal}      & 17 000  & one bit processor for SIMD architectures\\
-\hline
-\textbf{Data-safe} & 35 000  & dynamic data encryption chips\\
-\hline
-\textbf{TNT}       & 60 000  & switch-router for T800 transputerss\\
-\hline
-\textbf{FRISC}     & 200 000 & floating-point \textbf{RISC} microprocessor\\
-\hline
-\textbf{StaCS}     & 875 000 & Very Long Instruction Word processor\\
-\hline
-\textbf{Rapid2}    & 650 000 & SIMD systolic and associative processor\\
-\hline
-\textbf{Rcube}     & 350 000 & Message router for parallel machines\\
-\hline
-\end{tabular}
-\caption{\label{chip}Various chips designed with \textbf{Alliance}.}
-\end{figure}
-
-\begin{figure}\center
-\leavevmode\psfig{file=stacs.eps,width=5cm}
-\caption{\label{stacs} The 875 000 VLIW StaCS processor.}
-\end{figure}
-
-The three largest circuits described in table~\ref{chip} use not only 
-standard-cells but also parameterized generators for regular blocks 
-like \textit{RAM}s, data-paths, or floating-point operators.  
-The \textbf{FRISC} and \textbf{TNT} projects successfully used the
-\textbf{Cadence} and \textbf{Compass} place and route tools, and 
-therefore prove the interoperability of the \textbf{Alliance} system.
-
-A picture of the \textbf{StaCS} processor is shown figure~\ref{stacs}.
-
-%%%%%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\section{Conclusion}
-
-We are very satisfied to use a set of tools of our own for teaching 
-\textbf{CMOS} \textbf{VLSI} design for two good reasons.
-First, we simply can't afford 50 high end workstations to run 
-commercial CAD systems like \textbf{Compass}, \textbf{Mentor Graphics} or 
-\textbf{Cadence}.
-Second, both the \textbf{Compass} and \textbf{Cadence} system have been 
-used in research project at \textbf{LIP6}.
-They are powerful and sophisticated environments but are much too 
-complex for novice undergraduate students.
-The great advantage of the \textbf{Alliance} CAD system is that we 
-have done our best to stick to the basic yet powerful concepts of 
-\textbf{VLSI} design.
-To each tool correspond a unique functionnality, that cannot be
-changed or worked around by parameter files.
-At last, we experienced that the technology migration and process 
-independence are key issues.
-Hence, it is crucial to rely on a portable library at the symbolic
-layout level.
-
-The \textbf{Alliance} package is now in use all over the world, and more
-than 250 sites have registered today.
-It is available through anonymous \texttt{ftp} at  
-\texttt{ftp://ftp-asim.lip6.fr/pub/alliance/} \texttt{distribution/}, 
-or through a \texttt{Web} browser at 
-\texttt{http://www-asim.lip6.fr/pub/alliance/} \texttt{distribution/}.
-
-There is an \textbf{Alliance} mailing list, where users can share their
-views and problems, and our team is always ready to answer questions.
-The address of this mailing list is 
-\texttt{alliance-users@asim.} \texttt{lip6.fr}.
-The support of \textbf{Alliance} can be joined at
-\texttt{alliance-support@asim.lip6.fr}.
-
-%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-%\bibliography{/users/cao4/fred/tex/articles/bib/article,/users/cao4/fred/tex/articles/padp/pplace,./thesis}
-%\bibliography{/users/cao4/fred/faq}
-%\bibliographystyle{unsrt}
-\end{document}
diff --git a/alliance/share/doc/overview/stacs.gif b/alliance/share/doc/overview/stacs.gif
deleted file mode 100644
index 148a4fc0..00000000
Binary files a/alliance/share/doc/overview/stacs.gif and /dev/null differ
diff --git a/alliance/share/doc/overview/thesis.bib b/alliance/share/doc/overview/thesis.bib
deleted file mode 100644
index 8912240e..00000000
--- a/alliance/share/doc/overview/thesis.bib
+++ /dev/null
@@ -1,8 +0,0 @@
-@PHDTHESIS{mythesis,
-   author       = "Fr{\'e}d{\'e}ric P{\'e}trot",
-   month        = jul,
-   school       = "Universit{\'e} Pierre et Marie Curie, Laboratoire MASI",
-   title        = "Outils d'aide au d\'eveloppement de biblioth\`eques
-	   {VLSI} portables",
-   year         = "1994"
-}
diff --git a/alliance/share/doc/overview/tools.fig b/alliance/share/doc/overview/tools.fig
deleted file mode 100644
index fafab837..00000000
--- a/alliance/share/doc/overview/tools.fig
+++ /dev/null
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diff --git a/alliance/share/doc/process_mapping.pdf b/alliance/share/doc/process_mapping.pdf
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-     {29 22} {29 24} {29 25} {29 26} {29 27} {29 28} {29 30} {30 1} {30 2} 
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-     {31 8} {31 10} {31 12} {31 14} {31 16} {31 18} {31 20} {31 22} {31 24} 
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-     {12 5} {12 11} {12 19} {12 27} {13 6} {13 10} {13 20} {13 26} {14 7}
-     {14 9} {14 21} {14 25} {15 8} {15 22} {15 24} {16 7} {16 9} {16 23}
-     {17 6} {17 10} {17 22} {17 24} {18 5} {18 11} {18 21} {18 25} {19 4}
-     {19 12} {19 20} {19 26} {20 3} {20 13} {20 19} {20 27} {21 2} {21 14}
-     {21 18} {21 28} {22 1} {22 15} {22 17} {22 29} {23 0} {23 16} {23 30}
-     {24 1} {24 15} {24 17} {24 31} {25 2} {25 14} {25 18} {25 30} {26 3}
-     {26 13} {26 19} {26 29} {27 4} {27 12} {27 20} {27 28} {28 5} {28 11}
-     {28 21} {28 27} {29 6} {29 10} {29 22} {29 26} {30 7} {30 9} {30 23}
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-        {24 13}{29 14}{23 14}{7 24}{13 24}{8 25}{12 25}{9 26}{11 26}{10 27}
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-     {30 7} {30 13} {30 19} {30 25} {30 31} {31 2} {31 6} {31 12} {31 18} 
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-     {13 18} {13 19} {13 20} {13 22} {13 24} {13 25} {13 26} {13 27} {13 28} 
-     {13 30} {14 1} {14 2} {14 3} {14 5} {14 9} {14 10} {14 11} {14 13} 
-     {14 17} {14 18} {14 19} {14 21} {14 25} {14 26} {14 27} {14 29} {15 0} 
-     {15 2} {15 4} {15 6} {15 8} {15 10} {15 12} {15 14} {15 16} {15 18} 
-     {15 20} {15 22} {15 24} {15 26} {15 28} {15 30} {16 3} {16 7} {16 11} 
-     {16 15} {16 19} {16 23} {16 27} {16 31} {17 0} {17 2} {17 4} {17 6} 
-     {17 8} {17 10} {17 12} {17 14} {17 16} {17 18} {17 20} {17 22} {17 24} 
-     {17 26} {17 28} {17 30} {18 1} {18 5} {18 9} {18 13} {18 17} {18 21} 
-     {18 25} {18 29} {19 0} {19 2} {19 4} {19 6} {19 8} {19 10} {19 12} 
-     {19 14} {19 16} {19 18} {19 20} {19 22} {19 24} {19 26} {19 28} {19 30} 
-     {20 1} {20 2} {20 3} {20 7} {20 9} {20 10} {20 11} {20 15} {20 17} 
-     {20 18} {20 19} {20 23} {20 25} {20 26} {20 27} {20 31} {21 0} {21 1} 
-     {21 2} {21 3} {21 4} {21 6} {21 8} {21 9} {21 10} {21 11} {21 12} 
-     {21 14} {21 16} {21 17} {21 18} {21 19} {21 20} {21 22} {21 24} {21 25} 
-     {21 26} {21 27} {21 28} {21 30} {22 1} {22 2} {22 3} {22 5} {22 9} 
-     {22 10} {22 11} {22 13} {22 17} {22 18} {22 19} {22 21} {22 25} {22 26} 
-     {22 27} {22 29} {23 0} {23 2} {23 4} {23 6} {23 8} {23 10} {23 12} 
-     {23 14} {23 16} {23 18} {23 20} {23 22} {23 24} {23 26} {23 28} {23 30} 
-     {24 3} {24 7} {24 11} {24 15} {24 19} {24 23} {24 27} {24 31} {25 0} 
-     {25 2} {25 4} {25 6} {25 8} {25 10} {25 12} {25 14} {25 16} {25 18} 
-     {25 20} {25 22} {25 24} {25 26} {25 28} {25 30} {26 1} {26 5} {26 9} 
-     {26 13} {26 17} {26 21} {26 25} {26 29} {27 0} {27 2} {27 4} {27 6} 
-     {27 8} {27 10} {27 12} {27 14} {27 16} {27 18} {27 20} {27 22} {27 24} 
-     {27 26} {27 28} {27 30} {28 1} {28 2} {28 3} {28 7} {28 9} {28 10} 
-     {28 11} {28 15} {28 17} {28 18} {28 19} {28 23} {28 25} {28 26} {28 27} 
-     {28 31} {29 0} {29 1} {29 2} {29 3} {29 4} {29 6} {29 8} {29 9} 
-     {29 10} {29 11} {29 12} {29 14} {29 16} {29 17} {29 18} {29 19} {29 20} 
-     {29 22} {29 24} {29 25} {29 26} {29 27} {29 28} {29 30} {30 1} {30 2} 
-     {30 3} {30 5} {30 9} {30 10} {30 11} {30 13} {30 17} {30 18} {30 19} 
-     {30 21} {30 25} {30 26} {30 27} {30 29} {31 0} {31 2} {31 4} {31 6} 
-     {31 8} {31 10} {31 12} {31 14} {31 16} {31 18} {31 20} {31 22} {31 24} 
-     {31 26} {31 28} {31 30} 
-       ] def
-        /hach3 [
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-     {2 25} {3 4} {3 10} {3 20} {3 26} {4 3} {4 11} {4 19} {4 27}
-     {5 2} {5 12} {5 18} {5 28} {6 1} {6 13} {6 17} {6 29} {7 0}
-     {7 14} {7 16} {7 30} {8 1} {8 15} {8 31} {9 2} {9 14} {9 16}
-     {9 30} {10 3} {10 13} {10 17} {10 29} {11 4} {11 12} {11 18} {11 28}
-     {12 5} {12 11} {12 19} {12 27} {13 6} {13 10} {13 20} {13 26} {14 7}
-     {14 9} {14 21} {14 25} {15 8} {15 22} {15 24} {16 7} {16 9} {16 23}
-     {17 6} {17 10} {17 22} {17 24} {18 5} {18 11} {18 21} {18 25} {19 4}
-     {19 12} {19 20} {19 26} {20 3} {20 13} {20 19} {20 27} {21 2} {21 14}
-     {21 18} {21 28} {22 1} {22 15} {22 17} {22 29} {23 0} {23 16} {23 30}
-     {24 1} {24 15} {24 17} {24 31} {25 2} {25 14} {25 18} {25 30} {26 3}
-     {26 13} {26 19} {26 29} {27 4} {27 12} {27 20} {27 28} {28 5} {28 11}
-     {28 21} {28 27} {29 6} {29 10} {29 22} {29 26} {30 7} {30 9} {30 23}
-     {30 25} {31 8} {31 24}
-       ] def
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-     {7 31} {8 0} {8 14} {8 15} {8 16} {8 30} {8 31} {9 15} {9 31}
-     {15 7} {15 23} {16 6} {16 7} {16 8} {16 22} {16 23} {16 24} {17 7}
-     {17 23} {23 15} {23 31} {24 0} {24 14} {24 15} {24 16} {24 30} {24 31}
-     {25 15} {25 31} {31 7} {31 23}
-       ] def
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-	{13 9} {13 10} {13 14} {13 11} {13 12} {13 13} {8 14} {9 14} {10 14} {11 14} {12 14}
-	{23 24} {24 24} {25 24} {26 24} {27 24} {28 24} {29 24} {29 25} {29 26} {29 27} {29 28}
-	{29 29} {29 30} {28 30} {27 30} {26 30} {25 30} {24 30} {23 30} {23 29} {23 28}
-	{23 27} {23 26} {23 25}
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-	{22 10} {23 11} {24 12} {25 13} {26 14} {27 13} {28 12} {29 11} {30 10}
-      ] def
-      /octogone [
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-	{8 29} {7 28} {7 27} {7 26} {8 25}
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-       ] def
-      /x [
-	{23 8}{29 8}{24 9}{28 9}{25 10}{27 10}{26 11}{27 12}{25 12}{28 13}
-        {24 13}{29 14}{23 14}{7 24}{13 24}{8 25}{12 25}{9 26}{11 26}{10 27}
-        {11 28}{9 28}{12 29}{8 29}{13 30}{7 30}
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-     {7 12} {7 18} {7 22} {7 26} {7 30} {8 5} {8 11} {8 17} {8 21} 
-     {8 25} {8 29} {9 4} {9 10} {9 16} {9 20} {9 24} {9 28} {10 3} 
-     {10 9} {10 15} {10 19} {10 23} {10 27} {11 2} {11 8} {11 14} {11 18} 
-     {11 22} {11 26} {12 1} {12 7} {12 13} {12 17} {12 21} {12 25} {12 31} 
-     {13 0} {13 6} {13 12} {13 16} {13 20} {13 24} {13 30} {14 5} {14 11} 
-     {14 15} {14 19} {14 23} {14 29} {15 4} {15 10} {15 14} {15 18} {15 22} 
-     {15 28} {16 3} {16 9} {16 13} {16 17} {16 21} {16 27} {17 2} {17 8} 
-     {17 12} {17 16} {17 20} {17 26} {18 1} {18 7} {18 11} {18 15} {18 19} 
-     {18 25} {18 31} {19 0} {19 6} {19 10} {19 14} {19 18} {19 24} {19 30} 
-     {20 5} {20 9} {20 13} {20 17} {20 23} {20 29} {21 4} {21 8} {21 12} 
-     {21 16} {21 22} {21 28} {22 3} {22 7} {22 11} {22 15} {22 21} {22 27} 
-     {23 2} {23 6} {23 10} {23 14} {23 20} {23 26} {24 1} {24 5} {24 9} 
-     {24 13} {24 19} {24 25} {24 31} {25 0} {25 4} {25 8} {25 12} {25 18} 
-     {25 24} {25 30} {26 3} {26 7} {26 11} {26 17} {26 23} {26 29} {27 2} 
-     {27 6} {27 10} {27 16} {27 22} {27 28} {28 1} {28 5} {28 9} {28 15} 
-     {28 21} {28 27} {29 0} {29 4} {29 8} {29 14} {29 20} {29 26} {30 3} 
-     {30 7} {30 13} {30 19} {30 25} {30 31} {31 2} {31 6} {31 12} {31 18} 
-     {31 24} {31 30} 
-       ] def
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- @endspecial 120 2741 a(F)p Fn(IG)p Fr(.)d(A.4:)23 b(Symbolic)14
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-     {3 3} {3 4} {4 3} {4 4} {4 5} {5 4} {5 5} {5 6} {6 5}
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-     {27 4} {27 20} {28 3} {28 19} {29 2} {29 18} {30 1} {30 17} {31 0}
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-     {4 19} {5 5} {5 20} {6 6} {6 21} {7 7} {7 22} {8 8} {8 23}
-     {9 9} {9 24} {10 10} {10 25} {11 11} {11 26} {12 12} {12 27} {13 13}
-     {13 28} {14 14} {14 29} {15 0} {15 15} {15 30} {16 1} {16 16} {16 31}
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-     {21 21} {22 7} {22 22} {23 8} {23 23} {24 9} {24 24} {25 10} {25 25}
-     {26 11} {26 26} {27 12} {27 27} {28 13} {28 28} {29 14} {29 29} {30 15}
-     {30 30} {31 16} {31 31}
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-     {0 3} {0 7} {0 11} {0 15} {0 19} {0 23} {0 27} {0 31} {1 0} 
-     {1 2} {1 4} {1 6} {1 8} {1 10} {1 12} {1 14} {1 16} {1 18} 
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-     {2 13} {2 17} {2 21} {2 25} {2 29} {3 0} {3 2} {3 4} {3 6} 
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-     {3 26} {3 28} {3 30} {4 1} {4 2} {4 3} {4 7} {4 9} {4 10} 
-     {4 11} {4 15} {4 17} {4 18} {4 19} {4 23} {4 25} {4 26} {4 27} 
-     {4 31} {5 0} {5 1} {5 2} {5 3} {5 4} {5 6} {5 8} {5 9} 
-     {5 10} {5 11} {5 12} {5 14} {5 16} {5 17} {5 18} {5 19} {5 20} 
-     {5 22} {5 24} {5 25} {5 26} {5 27} {5 28} {5 30} {6 1} {6 2} 
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-     {11 2} {11 4} {11 6} {11 8} {11 10} {11 12} {11 14} {11 16} {11 18} 
-     {11 20} {11 22} {11 24} {11 26} {11 28} {11 30} {12 1} {12 2} {12 3} 
-     {12 7} {12 9} {12 10} {12 11} {12 15} {12 17} {12 18} {12 19} {12 23} 
-     {12 25} {12 26} {12 27} {12 31} {13 0} {13 1} {13 2} {13 3} {13 4} 
-     {13 6} {13 8} {13 9} {13 10} {13 11} {13 12} {13 14} {13 16} {13 17} 
-     {13 18} {13 19} {13 20} {13 22} {13 24} {13 25} {13 26} {13 27} {13 28} 
-     {13 30} {14 1} {14 2} {14 3} {14 5} {14 9} {14 10} {14 11} {14 13} 
-     {14 17} {14 18} {14 19} {14 21} {14 25} {14 26} {14 27} {14 29} {15 0} 
-     {15 2} {15 4} {15 6} {15 8} {15 10} {15 12} {15 14} {15 16} {15 18} 
-     {15 20} {15 22} {15 24} {15 26} {15 28} {15 30} {16 3} {16 7} {16 11} 
-     {16 15} {16 19} {16 23} {16 27} {16 31} {17 0} {17 2} {17 4} {17 6} 
-     {17 8} {17 10} {17 12} {17 14} {17 16} {17 18} {17 20} {17 22} {17 24} 
-     {17 26} {17 28} {17 30} {18 1} {18 5} {18 9} {18 13} {18 17} {18 21} 
-     {18 25} {18 29} {19 0} {19 2} {19 4} {19 6} {19 8} {19 10} {19 12} 
-     {19 14} {19 16} {19 18} {19 20} {19 22} {19 24} {19 26} {19 28} {19 30} 
-     {20 1} {20 2} {20 3} {20 7} {20 9} {20 10} {20 11} {20 15} {20 17} 
-     {20 18} {20 19} {20 23} {20 25} {20 26} {20 27} {20 31} {21 0} {21 1} 
-     {21 2} {21 3} {21 4} {21 6} {21 8} {21 9} {21 10} {21 11} {21 12} 
-     {21 14} {21 16} {21 17} {21 18} {21 19} {21 20} {21 22} {21 24} {21 25} 
-     {21 26} {21 27} {21 28} {21 30} {22 1} {22 2} {22 3} {22 5} {22 9} 
-     {22 10} {22 11} {22 13} {22 17} {22 18} {22 19} {22 21} {22 25} {22 26} 
-     {22 27} {22 29} {23 0} {23 2} {23 4} {23 6} {23 8} {23 10} {23 12} 
-     {23 14} {23 16} {23 18} {23 20} {23 22} {23 24} {23 26} {23 28} {23 30} 
-     {24 3} {24 7} {24 11} {24 15} {24 19} {24 23} {24 27} {24 31} {25 0} 
-     {25 2} {25 4} {25 6} {25 8} {25 10} {25 12} {25 14} {25 16} {25 18} 
-     {25 20} {25 22} {25 24} {25 26} {25 28} {25 30} {26 1} {26 5} {26 9} 
-     {26 13} {26 17} {26 21} {26 25} {26 29} {27 0} {27 2} {27 4} {27 6} 
-     {27 8} {27 10} {27 12} {27 14} {27 16} {27 18} {27 20} {27 22} {27 24} 
-     {27 26} {27 28} {27 30} {28 1} {28 2} {28 3} {28 7} {28 9} {28 10} 
-     {28 11} {28 15} {28 17} {28 18} {28 19} {28 23} {28 25} {28 26} {28 27} 
-     {28 31} {29 0} {29 1} {29 2} {29 3} {29 4} {29 6} {29 8} {29 9} 
-     {29 10} {29 11} {29 12} {29 14} {29 16} {29 17} {29 18} {29 19} {29 20} 
-     {29 22} {29 24} {29 25} {29 26} {29 27} {29 28} {29 30} {30 1} {30 2} 
-     {30 3} {30 5} {30 9} {30 10} {30 11} {30 13} {30 17} {30 18} {30 19} 
-     {30 21} {30 25} {30 26} {30 27} {30 29} {31 0} {31 2} {31 4} {31 6} 
-     {31 8} {31 10} {31 12} {31 14} {31 16} {31 18} {31 20} {31 22} {31 24} 
-     {31 26} {31 28} {31 30} 
-       ] def
-        /hach3 [
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-     {2 25} {3 4} {3 10} {3 20} {3 26} {4 3} {4 11} {4 19} {4 27}
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-     {9 30} {10 3} {10 13} {10 17} {10 29} {11 4} {11 12} {11 18} {11 28}
-     {12 5} {12 11} {12 19} {12 27} {13 6} {13 10} {13 20} {13 26} {14 7}
-     {14 9} {14 21} {14 25} {15 8} {15 22} {15 24} {16 7} {16 9} {16 23}
-     {17 6} {17 10} {17 22} {17 24} {18 5} {18 11} {18 21} {18 25} {19 4}
-     {19 12} {19 20} {19 26} {20 3} {20 13} {20 19} {20 27} {21 2} {21 14}
-     {21 18} {21 28} {22 1} {22 15} {22 17} {22 29} {23 0} {23 16} {23 30}
-     {24 1} {24 15} {24 17} {24 31} {25 2} {25 14} {25 18} {25 30} {26 3}
-     {26 13} {26 19} {26 29} {27 4} {27 12} {27 20} {27 28} {28 5} {28 11}
-     {28 21} {28 27} {29 6} {29 10} {29 22} {29 26} {30 7} {30 9} {30 23}
-     {30 25} {31 8} {31 24}
-       ] def
-        /point2 [
-     {0 6} {0 7} {0 8} {0 22} {0 23} {0 24} {1 7} {1 23} {7 15}
-     {7 31} {8 0} {8 14} {8 15} {8 16} {8 30} {8 31} {9 15} {9 31}
-     {15 7} {15 23} {16 6} {16 7} {16 8} {16 22} {16 23} {16 24} {17 7}
-     {17 23} {23 15} {23 31} {24 0} {24 14} {24 15} {24 16} {24 30} {24 31}
-     {25 15} {25 31} {31 7} {31 23}
-       ] def
-      /square [
-	{7 8} {8 8} {9 8} {10 8} {11 8} {12 8} {13 8} {7 9} {7 10} {7 11} {7 12} {7 13} {7 14}
-	{13 9} {13 10} {13 14} {13 11} {13 12} {13 13} {8 14} {9 14} {10 14} {11 14} {12 14}
-	{23 24} {24 24} {25 24} {26 24} {27 24} {28 24} {29 24} {29 25} {29 26} {29 27} {29 28}
-	{29 29} {29 30} {28 30} {27 30} {26 30} {25 30} {24 30} {23 30} {23 29} {23 28}
-	{23 27} {23 26} {23 25}
-      ] def
-      /triangle [
-	{21 9} {22 9} {23 9} {24 9} {25 9} {26 9} {27 9} {28 9} {29 9} {30 9} {31 9}
-	{22 10} {23 11} {24 12} {25 13} {26 14} {27 13} {28 12} {29 11} {30 10}
-      ] def
-      /octogone [
-	{9 24} {10 24} {11 24} {12 25} {13 26} {13 27} {13 28} {12 29} {11 30} {10 30} {9 30}
-	{8 29} {7 28} {7 27} {7 26} {8 25}
-      ] def
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-     {0 7} {0 23} {8 15} {8 31} {16 7} {16 23} {24 15} {24 31}
-       ] def
-      /x [
-	{23 8}{29 8}{24 9}{28 9}{25 10}{27 10}{26 11}{27 12}{25 12}{28 13}
-        {24 13}{29 14}{23 14}{7 24}{13 24}{8 25}{12 25}{9 26}{11 26}{10 27}
-        {11 28}{9 28}{12 29}{8 29}{13 30}{7 30}
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-     {6 1} {6 7} {6 13} {6 19} {6 23} {6 27} {6 31} {7 0} {7 6} 
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-     {10 9} {10 15} {10 19} {10 23} {10 27} {11 2} {11 8} {11 14} {11 18} 
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-     {15 28} {16 3} {16 9} {16 13} {16 17} {16 21} {16 27} {17 2} {17 8} 
-     {17 12} {17 16} {17 20} {17 26} {18 1} {18 7} {18 11} {18 15} {18 19} 
-     {18 25} {18 31} {19 0} {19 6} {19 10} {19 14} {19 18} {19 24} {19 30} 
-     {20 5} {20 9} {20 13} {20 17} {20 23} {20 29} {21 4} {21 8} {21 12} 
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-     {23 2} {23 6} {23 10} {23 14} {23 20} {23 26} {24 1} {24 5} {24 9} 
-     {24 13} {24 19} {24 25} {24 31} {25 0} {25 4} {25 8} {25 12} {25 18} 
-     {25 24} {25 30} {26 3} {26 7} {26 11} {26 17} {26 23} {26 29} {27 2} 
-     {27 6} {27 10} {27 16} {27 22} {27 28} {28 1} {28 5} {28 9} {28 15} 
-     {28 21} {28 27} {29 0} {29 4} {29 8} {29 14} {29 20} {29 26} {30 3} 
-     {30 7} {30 13} {30 19} {30 25} {30 31} {31 2} {31 6} {31 12} {31 18} 
-     {31 24} {31 30} 
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-%%Page: 21 21
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-%%Trailer
-end
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diff --git a/alliance/share/doc/symb_rules/symb_rules-orig.ps b/alliance/share/doc/symb_rules/symb_rules-orig.ps
deleted file mode 100644
index 8efd579d..00000000
--- a/alliance/share/doc/symb_rules/symb_rules-orig.ps
+++ /dev/null
@@ -1,2377 +0,0 @@
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-  pop pop pop pop pop		% -
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-% PATkshow - kshow with the current pattezn
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-  0 1 4 index length 2 sub {
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-    PATsstr dup 0 4 -1 roll put	% string proc chr+1 chr chr+1 (chr)
-    false charpath		% string proc char+1 char char+1
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-    % Move past the character (charpath modified the current point)
-    currentpoint newpath moveto
-    % Execute the user proc (should consume char and char+1)
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-    4 index exec		% string proc char+1 mark...
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-  pop pop			% -
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-% PATmp - the makepattern equivalent
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-% Save the original routines so that we can use them later on
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-% left45
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-8#302 /Acircumflex 8#303 /Atilde 8#304 /Adieresis 8#305 /Aring
-8#306 /AE 8#307 /Ccedilla 8#310 /Egrave 8#311 /Eacute
-8#312 /Ecircumflex 8#313 /Edieresis 8#314 /Igrave 8#315 /Iacute
-8#316 /Icircumflex 8#317 /Idieresis 8#320 /Eth 8#321 /Ntilde 8#322 /Ograve
-8#323 /Oacute 8#324 /Ocircumflex 8#325 /Otilde 8#326 /Odieresis 8#327 /multiply
-8#330 /Oslash 8#331 /Ugrave 8#332 /Uacute 8#333 /Ucircumflex
-8#334 /Udieresis 8#335 /Yacute 8#336 /Thorn 8#337 /germandbls 8#340 /agrave
-8#341 /aacute 8#342 /acircumflex 8#343 /atilde 8#344 /adieresis 8#345 /aring
-8#346 /ae 8#347 /ccedilla 8#350 /egrave 8#351 /eacute
-8#352 /ecircumflex 8#353 /edieresis 8#354 /igrave 8#355 /iacute
-8#356 /icircumflex 8#357 /idieresis 8#360 /eth 8#361 /ntilde 8#362 /ograve
-8#363 /oacute 8#364 /ocircumflex 8#365 /otilde 8#366 /odieresis 8#367 /divide
-8#370 /oslash 8#371 /ugrave 8#372 /uacute 8#373 /ucircumflex
-8#374 /udieresis 8#375 /yacute 8#376 /thorn 8#377 /ydieresis] def
-/Times-Roman /Times-Roman-iso isovec ReEncode
-/$F2psBegin {$F2psDict begin /$F2psEnteredState save def} def
-/$F2psEnd {$F2psEnteredState restore end} def
-%%EndProlog
-
-$F2psBegin
-10 setmiterlimit
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- 0.02652 0.02652 sc
-%%Page: 1 1
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-15.00 15.00 sc P4 [16 0 0 -16 90.00 274.80] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-75.000 slw
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-% Polyline
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-15.00 15.00 sc P4 [16 0 0 -16 390.00 708.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
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-15.00 15.00 sc P4 [16 0 0 -16 330.00 708.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 6075 14625 m 8505 14625 l 8505 15480 l 6075 15480 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 405.00 975.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 8325 14625 m 11117 14625 l 11117 15480 l 8325 15480 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 555.00 975.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 9675 10620 m 11970 10620 l 11970 12375 l 9675 12375 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 645.00 708.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 11701 10620 m 12600 10620 l 12600 12375 l 11701 12375 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 780.07 708.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 2476 3015 m 4725 3015 l 4725 7043 l 2476 7043 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 165.07 201.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 10531 4346 m 12783 4346 l 12783 7031 l 10531 7031 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 702.07 289.73] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 7831 3003 m 10082 3003 l 10082 7031 l 7831 7031 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 522.07 200.20] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-7.500 slw
-n 4951 3226 m 4951 5913 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 330.07 215.07] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-30.000 slw
-n 4275 3031 m 5625 3031 l 5625 6165 l 4275 6165 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 285.00 202.07] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-7.500 slw
-n 16246 931 m 16246 3618 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1083.07 62.07] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-30.000 slw
-n 15300 540 m 17145 540 l 17145 4140 l 15300 4140 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1020.00 36.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-75.000 slw
-n 18450 9910 m 18450 540 l gs col0 s gr 
-% Polyline
-30.000 slw
-n 20025 6615 m 21380 6615 l 21380 7920 l 20025 7920 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
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-% Polyline
-7.500 slw
-n 7650 3195 m 7651 5419 l 7651 6853 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 510.00 213.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 12962 4615 m 12962 6853 l 12962 6763 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 864.13 307.67] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-30.000 slw
-n 19174 9047 m 22325 9047 l 22325 9941 l 19174 9941 l cp gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1278.27 603.13] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19125 767 m 22276 767 l 22276 1215 l 19125 1215 l cp gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 1275.00 51.13] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19125 9047 m 22321 9047 l 22321 9945 l 19125 9945 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1275.00 603.13] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19125 11295 m 22325 11295 l 22325 12180 l 19125 12180 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1275.00 753.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 24075 988 m 27276 988 l 27276 1890 l 24075 1890 l cp gs /PC [[0.00 0.69 0.69] [0.00 0.00 0.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 1605.00 65.87] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 24075 3226 m 27276 3226 l 27276 4095 l 24075 4095 l cp gs /PC [[0.00 0.69 0.69] [0.00 0.00 0.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 1605.00 215.07] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 1800 3015 m 2699 3015 l 2699 5701 l 1800 5701 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 120.00 201.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 12600 4346 m 13500 4346 l 13500 7031 l 12600 7031 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 840.00 289.73] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19125 2522 m 22276 2522 l 22276 2970 l 19125 2970 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 1275.00 168.13] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19125 765 m 22276 765 l 22276 1213 l 19125 1213 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 1275.00 51.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 7202 3003 m 8102 3003 l 8102 7031 l 7202 7031 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 480.13 200.20] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19125 4770 m 22276 4770 l 22276 5220 l 19125 5220 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 1275.00 318.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19534 17104 m 22144 17104 l 22235 17104 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P17 [8 0 0 -8 1302.27 1140.27] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-45.000 slw
-n 19350 9495 m 22050 9495 l gs col0 s gr 
-% Polyline
-30.000 slw
-n 24075 5490 m 27276 5490 l 27276 6390 l 24075 6390 l cp gs /PC [[0.00 0.69 0.69] [0.00 0.00 0.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 1605.00 366.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 24075 7695 m 27276 7695 l 27276 8595 l 24075 8595 l cp gs /PC [[0.00 0.69 0.69] [0.00 0.00 0.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 1605.00 513.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19125 7020 m 22280 7020 l 22280 7470 l 19125 7470 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 1275.00 468.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19080 13980 m 22325 13980 l 22325 14850 l 19080 14850 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1272.00 932.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19125 16648 m 22325 16648 l 22325 17550 l 19125 17550 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1275.00 1109.87] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-45.000 slw
-n 24395 8151 m 27006 8151 l 27096 8151 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P17 [8 0 0 -8 1626.33 543.40] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 24300 5895 m 27006 5913 l 27096 5913 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P17 [8 0 0 -8 1620.00 393.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-30.000 slw
-n 9900 3003 m 10799 3003 l 10799 7031 l 9900 7031 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 660.00 200.20] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-7.500 slw
-n 19444 7254 m 22055 7254 l 22144 7254 l gs col0 s gr 
-% Polyline
-30.000 slw
-n 3375 8145 m 3825 8145 l 3825 10164 l 3375 10164 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 3825 9720 m 4275 9720 l 4275 16425 l 3825 16425 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 3825 15975 m 4275 15975 l 4275 16425 l 3825 16425 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 3825 15975 m 4275 15975 l 4275 16425 l 3825 16425 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-75.000 slw
-n 13050 9495 m 15750 9495 l 16200 9495 l 18405 9495 l gs col0 s gr 
-% Polyline
-30.000 slw
-n 6075 13746 m 7426 13746 l 7426 15089 l 6075 15089 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 405.00 916.40] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 6975 5670 m 8325 5670 l 8325 7020 l 6975 7020 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 465.00 378.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 6931 3003 m 8325 3003 l 8325 4365 l 6931 4365 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 462.07 200.20] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 9675 3003 m 11070 3003 l 11070 4365 l 9675 4365 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 645.00 200.20] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 9675 5689 m 11025 5689 l 11025 7031 l 9675 7031 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 645.00 379.27] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 12375 4770 m 13725 4770 l 13725 6113 l 12375 6113 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 825.00 318.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 25200 7695 m 26100 7695 l 26100 8595 l 25200 8595 l cp gs col1 0.75 shd ef gr gs col0 s gr 
-% Polyline
-n 10125 14618 m 11431 14618 l 11431 15930 l 10125 15930 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 675.00 974.53] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 25245 5490 m 26100 5490 l 26100 6390 l 25245 6390 l cp gs col1 0.75 shd ef gr gs col0 s gr 
-% Polyline
-n 7200 5895 m 8100 5895 l 8100 6795 l 7200 6795 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 480.00 393.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 9900 5895 m 10800 5895 l 10800 6808 l 9900 6808 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 660.00 393.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 12600 4995 m 13500 4995 l 13500 5895 l 12600 5895 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 840.00 333.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 6300 13995 m 7198 13995 l 7198 14850 l 6300 14850 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 420.00 933.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 10350 14940 m 11250 14940 l 11250 15750 l 10350 15750 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.69 0.69]] def
-15.00 15.00 sc P5 [16 0 0 -16 690.00 996.00] PATmp PATsp ef gr PATusp gs col16 s gr 
-% Polyline
-n 4725 10620 m 6075 10620 l 6075 11962 l 4725 11962 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 315.00 708.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 11475 10628 m 12825 10628 l 12825 11970 l 11475 11970 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 765.00 708.53] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 2025 10620 m 3375 10620 l 3375 11970 l 2025 11970 l cp gs /PC [[1.00 0.84 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 135.00 708.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 2250 10845 m 3150 10845 l 3150 11745 l 2250 11745 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 150.00 723.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 12375 1665 m 13726 1665 l 13726 3015 l 12375 3015 l cp gs /PC [[0.00 0.69 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 825.00 111.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 12645 1890 m 13500 1890 l 13500 2745 l 12645 2745 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 843.00 126.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 4275 3015 m 5625 3015 l 5625 4365 l 4275 4365 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 285.00 201.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 4276 4808 m 5626 4808 l 5626 6150 l 4276 6150 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 285.07 320.53] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 15570 2513 m 16920 2513 l 16920 3855 l 15570 3855 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1038.00 167.53] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 15570 728 m 16920 728 l 16920 2070 l 15570 2070 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1038.00 48.53] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 15795 990 m 16695 990 l 16695 1845 l 15795 1845 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 1053.00 66.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 15795 2790 m 16695 2790 l 16695 3645 l 15795 3645 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 1053.00 186.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 4500 5040 m 5400 5040 l 5400 5895 l 4500 5895 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 300.00 336.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 1575 4823 m 2925 4823 l 2925 6165 l 1575 6165 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 105.00 321.53] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 1800 4999 m 2700 4999 l 2700 5895 l 1800 5895 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 120.00 333.27] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-45.000 slw
-n 19395 7245 m 22095 7245 l gs col0 s gr 
-% Polyline
-30.000 slw
-n 4950 10849 m 5850 10849 l 5850 11745 l 4950 11745 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 330.00 723.27] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 11700 10849 m 12600 10849 l 12600 11745 l 11700 11745 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 780.00 723.27] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-7.500 slw
- [90 45 15 45] 0 sd
-n 18454 8599 m 23404 8599 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1230.27 573.27] PATmp PATsp ef gr PATusp gs col0 s gr  [] 0 sd
-% Polyline
-60.000 slw
- [90 45 15 45] 0 sd
-n 23175 541 m 23220 18000 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1545.00 36.07] PATmp PATsp ef gr PATusp gs col0 s gr  [] 0 sd
-% Polyline
- [90 45 15 45] 0 sd
-n 18522 8595 m 23091 8595 l gs col7 0.05 shd ef gr gs col0 s gr  [] 0 sd
-% Polyline
- [90 45 15 45] 0 sd
-n 23247 9045 m 27900 9045 l gs col7 0.05 shd ef gr gs col0 s gr  [] 0 sd
-% Polyline
-30.000 slw
-n 24975 12420 m 26370 12420 l 26370 13725 l 24975 13725 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 24120 12825 m 27270 12825 l 27270 13275 l 24120 13275 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 24075 9722 m 27271 9722 l 27271 10170 l 24075 10170 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 24075 11072 m 27271 11072 l 27271 11520 l 24075 11520 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 23540 17327 m 24980 17327 l 24980 17775 l 23540 17775 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 25020 16431 m 25471 16431 l 25471 17775 l 25020 17775 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 25920 17327 m 27269 17327 l 27269 17775 l 25920 17775 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 10578 9941 m 11026 9941 l 11026 13523 l 10578 13523 l cp gs col4 0.95 shd ef gr gs col0 s gr 
-% Polyline
-45.000 slw
-n 26196 17552 m 27006 17552 l gs col7 0.35 shd ef gr gs col0 s gr 
-% Polyline
-30.000 slw
-n 26820 16470 m 27270 16470 l 27270 17775 l 26820 17775 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 11475 3674 m 11925 3674 l 11925 8151 l 11475 8151 l cp gs col4 0.95 shd ef gr gs col0 s gr 
-% Polyline
-n 25020 14670 m 26370 14670 l 26370 15976 l 25020 15976 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 24030 15030 m 27276 15030 l 27276 15525 l 24030 15525 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 7200 3240 m 8100 3240 l 8100 4140 l 7200 4140 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 480.00 216.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 9900 3240 m 10800 3240 l 10800 4140 l 9900 4140 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 660.00 216.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 4493 3240 m 5400 3240 l 5400 4133 l 4493 4133 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 299.53 216.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-45.000 slw
-n 19350 2745 m 22050 2745 l gs col0 s gr 
-% Polyline
-n 19350 990 m 22050 990 l gs col0 s gr 
-% Polyline
-n 19350 4995 m 22050 4995 l gs col0 s gr 
-% Polyline
-30.000 slw
-n 6526 14194 m 6976 14194 l 6976 14642 l 6526 14642 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-45.000 slw
-n 24305 1436 m 26916 1436 l 27006 1436 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P17 [8 0 0 -8 1620.33 95.73] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 24345 11295 m 27000 11295 l 27045 11295 l gs col0 s gr 
-% Polyline
-n 24345 9945 m 27090 9945 l gs col0 s gr 
-% Polyline
-60.000 slw
- [90 45 15 45] 0 sd
-n 23220 16245 m 27900 16245 l gs col0 s gr  [] 0 sd
-% Polyline
-30.000 slw
-n 2026 5211 m 2475 5211 l 2475 5659 l 2026 5659 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 7425 3427 m 7875 3427 l 7875 3870 l 7425 3870 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 7425 6120 m 7875 6120 l 7875 6615 l 7425 6615 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 10126 3423 m 10575 3423 l 10575 3870 l 10126 3870 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 10127 6122 m 10576 6122 l 10576 6570 l 10127 6570 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 5176 11061 m 5625 11061 l 5625 11509 l 5176 11509 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 11926 11061 m 12375 11061 l 12375 11509 l 11926 11509 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 12825 5223 m 13275 5223 l 13275 5670 l 12825 5670 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 11025 7476 m 12377 7476 l 12377 8820 l 11025 8820 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 13952 9941 m 15303 9941 l 15303 11284 l 13952 11284 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 16654 10389 m 18003 10389 l 18003 11732 l 16654 11732 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 10125 12831 m 11477 12831 l 11477 14175 l 10125 14175 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 13952 13075 m 15303 13075 l 15303 14418 l 13952 14418 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 16654 16209 m 18003 16209 l 18003 17552 l 16654 17552 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 25470 5718 m 25920 5718 l 25920 6165 l 25470 6165 l cp gs col3 0.75 shd ef gr gs col0 s gr 
-% Polyline
-n 25425 7920 m 25875 7920 l 25875 8368 l 25425 8368 l cp gs col3 0.75 shd ef gr gs col0 s gr 
-% Polyline
-n 12825 2115 m 13275 2115 l 13275 2565 l 12825 2565 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 3374 2325 m 3825 2325 l 3825 8145 l 3374 8145 l cp gs col4 0.95 shd ef gr gs col0 s gr 
-% Polyline
-n 8775 2322 m 9226 2322 l 9226 7695 l 8775 7695 l cp gs col4 0.95 shd ef gr gs col0 s gr 
-% Polyline
-n 8325 9941 m 8776 9941 l 8776 13075 l 8325 13075 l cp gs col4 0.95 shd ef gr gs col0 s gr 
-% Polyline
-n 6525 9916 m 6976 9916 l 6976 13050 l 6525 13050 l cp gs col4 0.95 shd ef gr gs col0 s gr 
-% Polyline
-n 8777 13970 m 9226 13970 l 9226 16209 l 8777 16209 l cp gs col4 0.95 shd ef gr gs col0 s gr 
-% Polyline
-7.500 slw
-n 4726 5256 m 5175 5256 l 5175 5704 l 4726 5704 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 4725 3427 m 5175 3427 l 5175 3870 l 4725 3870 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 16021 2961 m 16470 2961 l 16470 3409 l 16021 3409 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 16020 1177 m 16470 1177 l 16470 1620 l 16020 1620 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-45.000 slw
-n 6750 9931 m 6750 12170 l 6750 13050 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 450.00 662.07] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 8550 9931 m 8550 12170 l 8550 13050 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 570.00 662.07] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19355 14418 m 21964 14418 l 22055 14418 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P17 [8 0 0 -8 1290.33 961.20] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19355 17104 m 21964 17104 l 22055 17104 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P17 [8 0 0 -8 1290.33 1140.27] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-30.000 slw
-n 3375 7920 m 3825 7920 l 3825 8370 l 3375 8370 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 20025 13725 m 21375 13725 l 21375 15030 l 20025 15030 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1335.00 915.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 20025 16388 m 21375 16388 l 21375 17730 l 20025 17730 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1335.00 1092.53] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 20250 13970 m 21150 13970 l 21150 14850 l 20250 14850 l cp gs col1 0.75 shd ef gr gs col0 s gr 
-% Polyline
-n 2880 7476 m 4232 7476 l 4232 8820 l 2880 8820 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 3150 7698 m 4050 7698 l 4050 8595 l 3150 8595 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 210.00 513.20] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-7.500 slw
-n 3375 9720 m 4275 9720 l 4275 10170 l 3375 10170 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-30.000 slw
-n 3825 15975 m 9225 15975 l 9225 16425 l 3825 16425 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-45.000 slw
-n 24435 15390 m 24250 15175 l gs col0 s gr 
-% Polyline
-n 24440 15175 m 24255 15390 l gs col0 s gr 
-% Polyline
-n 24435 13140 m 24250 12925 l gs col0 s gr 
-% Polyline
-n 24440 12925 m 24255 13140 l gs col0 s gr 
-% Polyline
-30.000 slw
-n 20250 16657 m 21155 16657 l 21155 17550 l 20250 17550 l cp gs col1 0.75 shd ef gr gs col0 s gr 
-% Polyline
-45.000 slw
-n 27135 15390 m 26950 15175 l gs col0 s gr 
-% Polyline
-n 27140 15175 m 26955 15390 l gs col0 s gr 
-% Polyline
-n 27135 13140 m 26950 12925 l gs col0 s gr 
-% Polyline
-n 27140 12925 m 26955 13140 l gs col0 s gr 
-% Polyline
-7.500 slw
-n 19355 9493 m 21964 9493 l 22055 9493 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1290.33 632.87] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-45.000 slw
-n 24305 3674 m 26916 3674 l 27006 3674 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P17 [8 0 0 -8 1620.33 244.93] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19355 11732 m 21964 11732 l 22055 11732 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1290.33 782.13] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 24395 15300 m 27006 15300 l 27096 15300 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P17 [8 0 0 -8 1626.33 1020.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 24395 13050 m 27006 13050 l 27096 13050 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P17 [8 0 0 -8 1626.33 870.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-30.000 slw
-n 11250 7698 m 12150 7698 l 12150 8595 l 11250 8595 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 750.00 513.20] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 10350 13095 m 11250 13095 l 11250 13992 l 10350 13992 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.69 0.69]] def
-15.00 15.00 sc P5 [16 0 0 -16 690.00 873.00] PATmp PATsp ef gr PATusp gs col16 s gr 
-% Polyline
-45.000 slw
-n 9000 2340 m 9000 7695 l gs col0 s gr 
-% Polyline
-n 3600 2385 m 3600 8145 l gs col0 s gr 
-% Polyline
-30.000 slw
-n 25200 14850 m 26145 14850 l 26145 15750 l 25200 15750 l cp gs col1 0.75 shd ef gr gs col0 s gr 
-% Polyline
-n 25200 12600 m 26100 12600 l 26100 13500 l 25200 13500 l cp gs col1 0.75 shd ef gr gs col0 s gr 
-% Polyline
-n 20475 16877 m 20925 16877 l 20925 17325 l 20475 17325 l cp gs col23 0.75 shd ef gr gs col0 s gr 
-% Polyline
-n 25470 15120 m 25877 15120 l 25877 15525 l 25470 15525 l cp gs col23 0.75 shd ef gr gs col0 s gr 
-% Polyline
-n 25425 12825 m 25875 12825 l 25875 13275 l 25425 13275 l cp gs col23 0.75 shd ef gr gs col0 s gr 
-% Polyline
-n 26820 17325 m 27270 17325 l gs col23 0.75 shd ef gr gs col0 s gr 
-% Polyline
-n 26820 17550 m 27000 17550 l gs col23 0.75 shd ef gr gs col0 s gr 
-% Polyline
-n 3375 7922 m 11927 7922 l 11927 8370 l 3375 8370 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 225.00 528.13] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-45.000 slw
-n 27090 11385 m 26905 11170 l gs col0 s gr 
-% Polyline
-n 27095 11170 m 26910 11385 l gs col0 s gr 
-% Polyline
-n 24390 10035 m 24205 9820 l gs col0 s gr 
-% Polyline
-n 24395 9820 m 24210 10035 l gs col0 s gr 
-% Polyline
-n 27090 10035 m 26905 9820 l gs col0 s gr 
-% Polyline
-n 27095 9820 m 26910 10035 l gs col0 s gr 
-% Polyline
-n 24390 11385 m 24205 11170 l gs col0 s gr 
-% Polyline
-n 24395 11170 m 24210 11385 l gs col0 s gr 
-% Polyline
-n 24435 8235 m 24250 8020 l gs col0 s gr 
-% Polyline
-n 24440 8020 m 24255 8235 l gs col0 s gr 
-% Polyline
-n 27090 8235 m 26905 8020 l gs col0 s gr 
-% Polyline
-n 27095 8020 m 26910 8235 l gs col0 s gr 
-% Polyline
-n 27135 6030 m 26950 5815 l gs col0 s gr 
-% Polyline
-n 27140 5815 m 26955 6030 l gs col0 s gr 
-% Polyline
-n 24390 6030 m 24205 5815 l gs col0 s gr 
-% Polyline
-n 24395 5815 m 24210 6030 l gs col0 s gr 
-% Polyline
-n 24435 3780 m 24250 3565 l gs col0 s gr 
-% Polyline
-n 24440 3565 m 24255 3780 l gs col0 s gr 
-% Polyline
-n 27090 3780 m 26905 3565 l gs col0 s gr 
-% Polyline
-n 27095 3565 m 26910 3780 l gs col0 s gr 
-% Polyline
-n 24390 1530 m 24205 1315 l gs col0 s gr 
-% Polyline
-n 24395 1315 m 24210 1530 l gs col0 s gr 
-% Polyline
-n 27045 1530 m 26860 1315 l gs col0 s gr 
-% Polyline
-n 27050 1315 m 26865 1530 l gs col0 s gr 
-% Polyline
-n 19440 1080 m 19255 865 l gs col0 s gr 
-% Polyline
-n 19445 865 m 19260 1080 l gs col0 s gr 
-% Polyline
-n 22095 1080 m 21910 865 l gs col0 s gr 
-% Polyline
-n 22100 865 m 21915 1080 l gs col0 s gr 
-% Polyline
-n 22095 2835 m 21910 2620 l gs col0 s gr 
-% Polyline
-n 22100 2620 m 21915 2835 l gs col0 s gr 
-% Polyline
-n 19440 2835 m 19255 2620 l gs col0 s gr 
-% Polyline
-n 19445 2620 m 19260 2835 l gs col0 s gr 
-% Polyline
-n 19440 5085 m 19255 4870 l gs col0 s gr 
-% Polyline
-n 19445 4870 m 19260 5085 l gs col0 s gr 
-% Polyline
-n 22095 5085 m 21910 4870 l gs col0 s gr 
-% Polyline
-n 22100 4870 m 21915 5085 l gs col0 s gr 
-% Polyline
-n 22140 9585 m 21955 9370 l gs col0 s gr 
-% Polyline
-n 22145 9370 m 21960 9585 l gs col0 s gr 
-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
-30.000 slw
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-% Polyline
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-% Polyline
-30.000 slw
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-15.00 15.00 sc P5 [16 0 0 -16 690.07 871.60] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
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-% arrowhead
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-clip
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-105.000 slw
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-105.000 slw
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-clip
-n 16290 14445 m 16290 16155 l gs col0 s gr gr
-
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-105.000 slw
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-% arrowhead
-n 16320 15754 m 16290 15897 l 16260 15754 l 16290 15778 l 16320 15754 l  cp gs 0.00 setgray ef gr  col0 s
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-clip
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-30.000 slw
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-clip
-n 27315 3240 m 27315 2790 l 27315 4590 l 27315 4140 l gs col7 1.00 shd ef gr gs col0 s gr gr
-
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-105.000 slw
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-clip
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-clip
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-
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-105.000 slw
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-% arrowhead
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-clip
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-clip
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-clip
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-clip
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-gs 1 -1 sc  270.0 rot (Drawing by Xavier LELOUP  DESS 99-00) col0 sh gr
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-/col13 {0.000 0.690 0.000 srgb} bind def
-/col14 {0.000 0.820 0.000 srgb} bind def
-/col15 {0.000 0.560 0.560 srgb} bind def
-/col16 {0.000 0.690 0.690 srgb} bind def
-/col17 {0.000 0.820 0.820 srgb} bind def
-/col18 {0.560 0.000 0.000 srgb} bind def
-/col19 {0.690 0.000 0.000 srgb} bind def
-/col20 {0.820 0.000 0.000 srgb} bind def
-/col21 {0.560 0.000 0.560 srgb} bind def
-/col22 {0.690 0.000 0.690 srgb} bind def
-/col23 {0.820 0.000 0.820 srgb} bind def
-/col24 {0.500 0.190 0.000 srgb} bind def
-/col25 {0.630 0.250 0.000 srgb} bind def
-/col26 {0.750 0.380 0.000 srgb} bind def
-/col27 {1.000 0.500 0.500 srgb} bind def
-/col28 {1.000 0.630 0.630 srgb} bind def
-/col29 {1.000 0.750 0.750 srgb} bind def
-/col30 {1.000 0.880 0.880 srgb} bind def
-/col31 {1.000 0.840 0.000 srgb} bind def
-/col32 {0.000 0.600 1.000 srgb} bind def
-/col33 {0.945 0.753 0.518 srgb} bind def
-
-end
-save
--11.0 478.0 translate
-1 -1 scale
-.9 .9 scale % to make patterns same scale as in xfig
-
-% This junk string is used by the show operators
-/PATsstr 1 string def
-/PATawidthshow { 	% cx cy cchar rx ry string
-  % Loop over each character in the string
-  {  % cx cy cchar rx ry char
-    % Show the character
-    dup				% cx cy cchar rx ry char char
-    PATsstr dup 0 4 -1 roll put	% cx cy cchar rx ry char (char)
-    false charpath		% cx cy cchar rx ry char
-    /clip load PATdraw
-    % Move past the character (charpath modified the
-    % current point)
-    currentpoint			% cx cy cchar rx ry char x y
-    newpath
-    moveto			% cx cy cchar rx ry char
-    % Reposition by cx,cy if the character in the string is cchar
-    3 index eq {			% cx cy cchar rx ry
-      4 index 4 index rmoveto
-    } if
-    % Reposition all characters by rx ry
-    2 copy rmoveto		% cx cy cchar rx ry
-  } forall
-  pop pop pop pop pop		% -
-  currentpoint
-  newpath
-  moveto
-} bind def
-/PATcg {
-  7 dict dup begin
-    /lw currentlinewidth def
-    /lc currentlinecap def
-    /lj currentlinejoin def
-    /ml currentmiterlimit def
-    /ds [ currentdash ] def
-    /cc [ currentrgbcolor ] def
-    /cm matrix currentmatrix def
-  end
-} bind def
-% PATdraw - calculates the boundaries of the object and
-% fills it with the current pattern
-/PATdraw {			% proc
-  save exch
-    PATpcalc			% proc nw nh px py
-    5 -1 roll exec		% nw nh px py
-    newpath
-    PATfill			% -
-  restore
-} bind def
-% PATfill - performs the tiling for the shape
-/PATfill { % nw nh px py PATfill -
-  PATDict /CurrentPattern get dup begin
-    setfont
-    % Set the coordinate system to Pattern Space
-    PatternGState PATsg
-    % Set the color for uncolored pattezns
-    PaintType 2 eq { PATDict /PColor get PATsc } if
-    % Create the string for showing
-    3 index string		% nw nh px py str
-    % Loop for each of the pattern sources
-    0 1 Multi 1 sub {		% nw nh px py str source
-	% Move to the starting location
-	3 index 3 index		% nw nh px py str source px py
-	moveto			% nw nh px py str source
-	% For multiple sources, set the appropriate color
-	Multi 1 ne { dup PC exch get PATsc } if
-	% Set the appropriate string for the source
-	0 1 7 index 1 sub { 2 index exch 2 index put } for pop
-	% Loop over the number of vertical cells
-	3 index 		% nw nh px py str nh
-	{			% nw nh px py str
-	  currentpoint		% nw nh px py str cx cy
-	  2 index show		% nw nh px py str cx cy
-	  YStep add moveto	% nw nh px py str
-	} repeat		% nw nh px py str
-    } for
-    5 { pop } repeat
-  end
-} bind def
-
-% PATkshow - kshow with the current pattezn
-/PATkshow {			% proc string
-  exch bind			% string proc
-  1 index 0 get			% string proc char
-  % Loop over all but the last character in the string
-  0 1 4 index length 2 sub {
-				% string proc char idx
-    % Find the n+1th character in the string
-    3 index exch 1 add get	% string proe char char+1
-    exch 2 copy			% strinq proc char+1 char char+1 char
-    % Now show the nth character
-    PATsstr dup 0 4 -1 roll put	% string proc chr+1 chr chr+1 (chr)
-    false charpath		% string proc char+1 char char+1
-    /clip load PATdraw
-    % Move past the character (charpath modified the current point)
-    currentpoint newpath moveto
-    % Execute the user proc (should consume char and char+1)
-    mark 3 1 roll		% string proc char+1 mark char char+1
-    4 index exec		% string proc char+1 mark...
-    cleartomark			% string proc char+1
-  } for
-  % Now display the last character
-  PATsstr dup 0 4 -1 roll put	% string proc (char+1)
-  false charpath		% string proc
-  /clip load PATdraw
-  neewath
-  pop pop			% -
-} bind def
-% PATmp - the makepattern equivalent
-/PATmp {			% patdict patmtx PATmp patinstance
-  exch dup length 7 add		% We will add 6 new entries plus 1 FID
-  dict copy			% Create a new dictionary
-  begin
-    % Matrix to install when painting the pattern
-    TilingType PATtcalc
-    /PatternGState PATcg def
-    PatternGState /cm 3 -1 roll put
-    % Check for multi pattern sources (Level 1 fast color patterns)
-    currentdict /Multi known not { /Multi 1 def } if
-    % Font dictionary definitions
-    /FontType 3 def
-    % Create a dummy encoding vector
-    /Encoding 256 array def
-    3 string 0 1 255 {
-      Encoding exch dup 3 index cvs cvn put } for pop
-    /FontMatrix matrix def
-    /FontBBox BBox def
-    /BuildChar {
-	mark 3 1 roll		% mark dict char
-	exch begin
-	Multi 1 ne {PaintData exch get}{pop} ifelse  % mark [paintdata]
-	  PaintType 2 eq Multi 1 ne or
-	  { XStep 0 FontBBox aload pop setcachedevice }
-	  { XStep 0 setcharwidth } ifelse
-	  currentdict		% mark [paintdata] dict
-	  /PaintProc load	% mark [paintdata] dict paintproc
-	end
-	gsave
-	  false PATredef exec true PATredef
-	grestore
-	cleartomark		% -
-    } bind def
-    currentdict
-  end				% newdict
-  /foo exch			% /foo newlict
-  definefont			% newfont
-} bind def
-% PATpcalc - calculates the starting point and width/height
-% of the tile fill for the shape
-/PATpcalc {	% - PATpcalc nw nh px py
-  PATDict /CurrentPattern get begin
-    gsave
-	% Set up the coordinate system to Pattern Space
-	% and lock down pattern
-	PatternGState /cm get setmatrix
-	BBox aload pop pop pop translate
-	% Determine the bounding box of the shape
-	pathbbox			% llx lly urx ury
-    grestore
-    % Determine (nw, nh) the # of cells to paint width and height
-    PatHeight div ceiling		% llx lly urx qh
-    4 1 roll				% qh llx lly urx
-    PatWidth div ceiling		% qh llx lly qw
-    4 1 roll				% qw qh llx lly
-    PatHeight div floor			% qw qh llx ph
-    4 1 roll				% ph qw qh llx
-    PatWidth div floor			% ph qw qh pw
-    4 1 roll				% pw ph qw qh
-    2 index sub cvi abs			% pw ph qs qh-ph
-    exch 3 index sub cvi abs exch	% pw ph nw=qw-pw nh=qh-ph
-    % Determine the starting point of the pattern fill
-    %(px, py)
-    4 2 roll				% nw nh pw ph
-    PatHeight mul			% nw nh pw py
-    exch				% nw nh py pw
-    PatWidth mul exch			% nw nh px py
-  end
-} bind def
-
-% Save the original routines so that we can use them later on
-/oldfill	/fill load def
-/oldeofill	/eofill load def
-/oldstroke	/stroke load def
-/oldshow	/show load def
-/oldashow	/ashow load def
-/oldwidthshow	/widthshow load def
-/oldawidthshow	/awidthshow load def
-/oldkshow	/kshow load def
-
-% These defs are necessary so that subsequent procs don't bind in
-% the originals
-/fill	   { oldfill } bind def
-/eofill	   { oldeofill } bind def
-/stroke	   { oldstroke } bind def
-/show	   { oldshow } bind def
-/ashow	   { oldashow } bind def
-/widthshow { oldwidthshow } bind def
-/awidthshow { oldawidthshow } bind def
-/kshow 	   { oldkshow } bind def
-/PATredef {
-  MyAppDict begin
-    {
-    /fill { /clip load PATdraw newpath } bind def
-    /eofill { /eoclip load PATdraw newpath } bind def
-    /stroke { PATstroke } bind def
-    /show { 0 0 null 0 0 6 -1 roll PATawidthshow } bind def
-    /ashow { 0 0 null 6 3 roll PATawidthshow }
-    bind def
-    /widthshow { 0 0 3 -1 roll PATawidthshow }
-    bind def
-    /awidthshow { PATawidthshow } bind def
-    /kshow { PATkshow } bind def
-  } {
-    /fill   { oldfill } bind def
-    /eofill { oldeofill } bind def
-    /stroke { oldstroke } bind def
-    /show   { oldshow } bind def
-    /ashow  { oldashow } bind def
-    /widthshow { oldwidthshow } bind def
-    /awidthshow { oldawidthshow } bind def
-    /kshow  { oldkshow } bind def
-    } ifelse
-  end
-} bind def
-false PATredef
-% Conditionally define setcmykcolor if not available
-/setcmykcolor where { pop } {
-  /setcmykcolor {
-    1 sub 4 1 roll
-    3 {
-	3 index add neg dup 0 lt { pop 0 } if 3 1 roll
-    } repeat
-    setrgbcolor - pop
-  } bind def
-} ifelse
-/PATsc {		% colorarray
-  aload length		% c1 ... cn length
-    dup 1 eq { pop setgray } { 3 eq { setrgbcolor } { setcmykcolor
-  } ifelse } ifelse
-} bind def
-/PATsg {		% dict
-  begin
-    lw setlinewidth
-    lc setlinecap
-    lj setlinejoin
-    ml setmiterlimit
-    ds aload pop setdash
-    cc aload pop setrgbcolor
-    cm setmatrix
-  end
-} bind def
-
-/PATDict 3 dict def
-/PATsp {
-  true PATredef
-  PATDict begin
-    /CurrentPattern exch def
-    % If it's an uncolored pattern, save the color
-    CurrentPattern /PaintType get 2 eq {
-      /PColor exch def
-    } if
-    /CColor [ currentrgbcolor ] def
-  end
-} bind def
-% PATstroke - stroke with the current pattern
-/PATstroke {
-  countdictstack
-  save
-  mark
-  {
-    currentpoint strokepath moveto
-    PATpcalc				% proc nw nh px py
-    clip newpath PATfill
-    } stopped {
-	(*** PATstroke Warning: Path is too complex, stroking
-	  with gray) =
-    cleartomark
-    restore
-    countdictstack exch sub dup 0 gt
-	{ { end } repeat } { pop } ifelse
-    gsave 0.5 setgray oldstroke grestore
-  } { pop restore pop } ifelse
-  newpath
-} bind def
-/PATtcalc {		% modmtx tilingtype PATtcalc tilematrix
-  % Note: tiling types 2 and 3 are not supported
-  gsave
-    exch concat					% tilingtype
-    matrix currentmatrix exch			% cmtx tilingtype
-    % Tiling type 1 and 3: constant spacing
-    2 ne {
-	% Distort the pattern so that it occupies
-	% an integral number of device pixels
-	dup 4 get exch dup 5 get exch		% tx ty cmtx
-	XStep 0 dtransform
-	round exch round exch			% tx ty cmtx dx.x dx.y
-	XStep div exch XStep div exch		% tx ty cmtx a b
-	0 YStep dtransform
-	round exch round exch			% tx ty cmtx a b dy.x dy.y
-	YStep div exch YStep div exch		% tx ty cmtx a b c d
-	7 -3 roll astore			% { a b c d tx ty }
-    } if
-  grestore
-} bind def
-/PATusp {
-  false PATredef
-  PATDict begin
-    CColor PATsc
-  end
-} bind def
-
-% left45
-11 dict begin
-/PaintType 1 def
-/PatternType 1 def
-/TilingType 1 def
-/BBox [0 0 1 1] def
-/XStep 1 def
-/YStep 1 def
-/PatWidth 1 def
-/PatHeight 1 def
-/Multi 2 def
-/PaintData [
-  { clippath } bind
-  { 32 32 true [ 32 0 0 -32 0 32 ]
-	{<808080804040404020202020101010100808080804040404
-	020202020101010180808080404040402020202010101010
-	080808080404040402020202010101018080808040404040
-	202020201010101008080808040404040202020201010101
-	808080804040404020202020101010100808080804040404
-	0202020201010101>}
-     imagemask } bind
-] def
-/PaintProc {
-	pop
-	exec fill
-} def
-currentdict
-end
-/P4 exch def
-
-% right45
-11 dict begin
-/PaintType 1 def
-/PatternType 1 def
-/TilingType 1 def
-/BBox [0 0 1 1] def
-/XStep 1 def
-/YStep 1 def
-/PatWidth 1 def
-/PatHeight 1 def
-/Multi 2 def
-/PaintData [
-  { clippath } bind
-  { 32 32 true [ 32 0 0 -32 0 32 ]
-	{<010101010202020204040404080808081010101020202020
-	404040408080808001010101020202020404040408080808
-	101010102020202040404040808080800101010102020202
-	040404040808080810101010202020204040404080808080
-	010101010202020204040404080808081010101020202020
-	4040404080808080>}
-     imagemask } bind
-] def
-/PaintProc {
-	pop
-	exec fill
-} def
-currentdict
-end
-/P5 exch def
-
-% small fishscales
-11 dict begin
-/PaintType 1 def
-/PatternType 1 def
-/TilingType 1 def
-/BBox [0 0 1 1] def
-/XStep 1 def
-/YStep 1 def
-/PatWidth 1 def
-/PatHeight 1 def
-/Multi 2 def
-/PaintData [
-  { clippath } bind
-  { 16 16 true [ 16 0 0 -16 0 16 ]
-	{<008000800080014001400220
-	0c187007c001800080004001
-	40012002180c0770>}
-     imagemask } bind
-] def
-/PaintProc {
-	pop
-	exec fill
-} def
-currentdict
-end
-/P17 exch def
-1.1111 1.1111 scale %restore scale
-
-/cp {closepath} bind def
-/ef {eofill} bind def
-/gr {grestore} bind def
-/gs {gsave} bind def
-/sa {save} bind def
-/rs {restore} bind def
-/l {lineto} bind def
-/m {moveto} bind def
-/rm {rmoveto} bind def
-/n {newpath} bind def
-/s {stroke} bind def
-/sh {show} bind def
-/slc {setlinecap} bind def
-/slj {setlinejoin} bind def
-/slw {setlinewidth} bind def
-/srgb {setrgbcolor} bind def
-/rot {rotate} bind def
-/sc {scale} bind def
-/sd {setdash} bind def
-/ff {findfont} bind def
-/sf {setfont} bind def
-/scf {scalefont} bind def
-/sw {stringwidth} bind def
-/tr {translate} bind def
-/tnt {dup dup currentrgbcolor
-  4 -2 roll dup 1 exch sub 3 -1 roll mul add
-  4 -2 roll dup 1 exch sub 3 -1 roll mul add
-  4 -2 roll dup 1 exch sub 3 -1 roll mul add srgb}
-  bind def
-/shd {dup dup currentrgbcolor 4 -2 roll mul 4 -2 roll mul
-  4 -2 roll mul srgb} bind def
-/reencdict 12 dict def /ReEncode { reencdict begin
-/newcodesandnames exch def /newfontname exch def /basefontname exch def
-/basefontdict basefontname findfont def /newfont basefontdict maxlength dict def
-basefontdict { exch dup /FID ne { dup /Encoding eq
-{ exch dup length array copy newfont 3 1 roll put }
-{ exch newfont 3 1 roll put } ifelse } { pop pop } ifelse } forall
-newfont /FontName newfontname put newcodesandnames aload pop
-128 1 255 { newfont /Encoding get exch /.notdef put } for
-newcodesandnames length 2 idiv { newfont /Encoding get 3 1 roll put } repeat
-newfontname newfont definefont pop end } def
-/isovec [
-8#200 /grave 8#201 /acute 8#202 /circumflex 8#203 /tilde
-8#204 /macron 8#205 /breve 8#206 /dotaccent 8#207 /dieresis
-8#210 /ring 8#211 /cedilla 8#212 /hungarumlaut 8#213 /ogonek 8#214 /caron
-8#220 /dotlessi 8#230 /oe 8#231 /OE
-8#240 /space 8#241 /exclamdown 8#242 /cent 8#243 /sterling
-8#244 /currency 8#245 /yen 8#246 /brokenbar 8#247 /section 8#250 /dieresis
-8#251 /copyright 8#252 /ordfeminine 8#253 /guillemotleft 8#254 /logicalnot
-8#255 /endash 8#256 /registered 8#257 /macron 8#260 /degree 8#261 /plusminus
-8#262 /twosuperior 8#263 /threesuperior 8#264 /acute 8#265 /mu 8#266 /paragraph
-8#267 /periodcentered 8#270 /cedilla 8#271 /onesuperior 8#272 /ordmasculine
-8#273 /guillemotright 8#274 /onequarter 8#275 /onehalf
-8#276 /threequarters 8#277 /questiondown 8#300 /Agrave 8#301 /Aacute
-8#302 /Acircumflex 8#303 /Atilde 8#304 /Adieresis 8#305 /Aring
-8#306 /AE 8#307 /Ccedilla 8#310 /Egrave 8#311 /Eacute
-8#312 /Ecircumflex 8#313 /Edieresis 8#314 /Igrave 8#315 /Iacute
-8#316 /Icircumflex 8#317 /Idieresis 8#320 /Eth 8#321 /Ntilde 8#322 /Ograve
-8#323 /Oacute 8#324 /Ocircumflex 8#325 /Otilde 8#326 /Odieresis 8#327 /multiply
-8#330 /Oslash 8#331 /Ugrave 8#332 /Uacute 8#333 /Ucircumflex
-8#334 /Udieresis 8#335 /Yacute 8#336 /Thorn 8#337 /germandbls 8#340 /agrave
-8#341 /aacute 8#342 /acircumflex 8#343 /atilde 8#344 /adieresis 8#345 /aring
-8#346 /ae 8#347 /ccedilla 8#350 /egrave 8#351 /eacute
-8#352 /ecircumflex 8#353 /edieresis 8#354 /igrave 8#355 /iacute
-8#356 /icircumflex 8#357 /idieresis 8#360 /eth 8#361 /ntilde 8#362 /ograve
-8#363 /oacute 8#364 /ocircumflex 8#365 /otilde 8#366 /odieresis 8#367 /divide
-8#370 /oslash 8#371 /ugrave 8#372 /uacute 8#373 /ucircumflex
-8#374 /udieresis 8#375 /yacute 8#376 /thorn 8#377 /ydieresis] def
-/Times-Roman /Times-Roman-iso isovec ReEncode
-/$F2psBegin {$F2psDict begin /$F2psEnteredState save def} def
-/$F2psEnd {$F2psEnteredState restore end} def
-%%EndProlog
-
-$F2psBegin
-10 setmiterlimit
-n -1000 19065 m -1000 -1000 l 30444 -1000 l 30444 19065 l cp clip
- 0.02646 0.02646 sc
-% Polyline
-7.500 slw
-n 25205 18000 m 25205 540 l gs col0 s gr 
-% Polyline
-n 25655 18000 m 25655 540 l gs col0 s gr 
-% Polyline
-n 26106 18000 m 26106 540 l gs col0 s gr 
-% Polyline
-n 26556 18000 m 26556 540 l gs col0 s gr 
-% Polyline
-n 27006 18000 m 27006 540 l gs col0 s gr 
-% Polyline
-n 27456 18000 m 27456 540 l gs col0 s gr 
-% Polyline
-n 27907 18000 m 27907 540 l gs col0 s gr 
-% Polyline
-n 22505 18000 m 22505 540 l gs col0 s gr 
-% Polyline
-n 22955 18000 m 22955 540 l gs col0 s gr 
-% Polyline
-n 23404 18000 m 23404 540 l gs col0 s gr 
-% Polyline
-n 23855 18000 m 23855 540 l gs col0 s gr 
-% Polyline
-n 24305 18000 m 24305 540 l gs col0 s gr 
-% Polyline
-n 24756 18000 m 24756 540 l gs col0 s gr 
-% Polyline
-n 19803 18000 m 19803 540 l gs col0 s gr 
-% Polyline
-n 20254 18000 m 20254 540 l gs col0 s gr 
-% Polyline
-n 20704 18000 m 20704 540 l gs col0 s gr 
-% Polyline
-n 21155 18000 m 21155 540 l gs col0 s gr 
-% Polyline
-n 21604 18000 m 21604 540 l gs col0 s gr 
-% Polyline
-n 22055 18000 m 22055 540 l gs col0 s gr 
-% Polyline
-n 17103 18000 m 17103 540 l gs col0 s gr 
-% Polyline
-n 17554 18000 m 17554 540 l gs col0 s gr 
-% Polyline
-n 18003 18000 m 18003 540 l gs col0 s gr 
-% Polyline
-n 18454 18000 m 18454 540 l gs col0 s gr 
-% Polyline
-n 18904 18000 m 18904 540 l gs col0 s gr 
-% Polyline
-n 19355 18000 m 19355 540 l gs col0 s gr 
-% Polyline
-n 14403 18000 m 14403 540 l gs col0 s gr 
-% Polyline
-n 14852 18000 m 14852 540 l gs col0 s gr 
-% Polyline
-n 15303 18000 m 15303 540 l gs col0 s gr 
-% Polyline
-n 15754 18000 m 15754 540 l gs col0 s gr 
-% Polyline
-n 16203 18000 m 16203 540 l gs col0 s gr 
-% Polyline
-n 16654 18000 m 16654 540 l gs col0 s gr 
-% Polyline
-n 11702 18000 m 11702 540 l gs col0 s gr 
-% Polyline
-n 12152 18000 m 12152 540 l gs col0 s gr 
-% Polyline
-n 12603 18000 m 12603 540 l gs col0 s gr 
-% Polyline
-n 13952 18000 m 13952 540 l gs col0 s gr 
-% Polyline
-n 9002 18000 m 9002 540 l gs col0 s gr 
-% Polyline
-n 9451 18000 m 9451 540 l gs col0 s gr 
-% Polyline
-n 9902 18000 m 9902 540 l gs col0 s gr 
-% Polyline
-n 10352 18000 m 10352 540 l gs col0 s gr 
-% Polyline
-n 10803 18000 m 10803 540 l gs col0 s gr 
-% Polyline
-n 11251 18000 m 11251 540 l gs col0 s gr 
-% Polyline
-n 6301 18000 m 6301 540 l gs col0 s gr 
-% Polyline
-n 6751 18000 m 6751 540 l gs col0 s gr 
-% Polyline
-n 7202 18000 m 7202 540 l gs col0 s gr 
-% Polyline
-n 7651 18000 m 7651 540 l gs col0 s gr 
-% Polyline
-n 8102 18000 m 8102 540 l gs col0 s gr 
-% Polyline
-n 8551 18000 m 8551 540 l gs col0 s gr 
-% Polyline
-n 3600 18000 m 3600 540 l gs col0 s gr 
-% Polyline
-n 4050 18000 m 4050 540 l gs col0 s gr 
-% Polyline
-n 4500 18000 m 4500 540 l gs col0 s gr 
-% Polyline
-n 4951 18000 m 4951 540 l gs col0 s gr 
-% Polyline
-n 5401 18000 m 5401 540 l gs col0 s gr 
-% Polyline
-n 5850 18000 m 5850 540 l gs col0 s gr 
-% Polyline
-n 1800 18000 m 1800 540 l gs col0 s gr 
-% Polyline
-n 2250 18000 m 2250 540 l gs col0 s gr 
-% Polyline
-n 3150 18000 m 3150 540 l gs col0 s gr 
-% Polyline
-n 899 16209 m 27907 16209 l gs col0 s gr 
-% Polyline
-n 899 16657 m 27907 16657 l gs col0 s gr 
-% Polyline
-n 899 17104 m 27907 17104 l gs col0 s gr 
-% Polyline
-n 899 17552 m 27907 17552 l gs col0 s gr 
-% Polyline
-n 899 13970 m 27907 13970 l gs col0 s gr 
-% Polyline
-n 899 14418 m 27907 14418 l gs col0 s gr 
-% Polyline
-n 899 14866 m 27907 14866 l gs col0 s gr 
-% Polyline
-n 899 15314 m 27907 15314 l gs col0 s gr 
-% Polyline
-n 899 15761 m 27907 15761 l gs col0 s gr 
-% Polyline
-n 899 11732 m 27907 11732 l gs col0 s gr 
-% Polyline
-n 899 12180 m 27907 12180 l gs col0 s gr 
-% Polyline
-n 899 12627 m 27907 12627 l gs col0 s gr 
-% Polyline
-n 899 13075 m 27907 13075 l gs col0 s gr 
-% Polyline
-n 899 13523 m 27907 13523 l gs col0 s gr 
-% Polyline
-n 899 9941 m 27907 9941 l gs col0 s gr 
-% Polyline
-n 899 10389 m 27907 10389 l gs col0 s gr 
-% Polyline
-n 899 10836 m 27907 10836 l gs col0 s gr 
-% Polyline
-n 899 11284 m 27907 11284 l gs col0 s gr 
-% Polyline
-n 899 7256 m 27907 7256 l gs col0 s gr 
-% Polyline
-n 899 7704 m 27907 7704 l gs col0 s gr 
-% Polyline
-n 899 8151 m 27907 8151 l gs col0 s gr 
-% Polyline
-n 899 8599 m 27907 8599 l gs col0 s gr 
-% Polyline
-n 899 9047 m 27907 9047 l gs col0 s gr 
-% Polyline
-n 899 5017 m 27907 5017 l gs col0 s gr 
-% Polyline
-n 899 5465 m 27907 5465 l gs col0 s gr 
-% Polyline
-n 899 5913 m 27907 5913 l gs col0 s gr 
-% Polyline
-n 899 6360 m 27907 6360 l gs col0 s gr 
-% Polyline
-n 899 6808 m 27907 6808 l gs col0 s gr 
-% Polyline
-n 899 18000 m 27907 18000 l gs col0 s gr 
-% Polyline
-n 899 540 m 27907 540 l gs col0 s gr 
-% Polyline
-n 899 18000 m 899 540 l gs col0 s gr 
-% Polyline
-n 899 2779 m 27907 2779 l gs col0 s gr 
-% Polyline
-n 899 3226 m 27907 3226 l gs col0 s gr 
-% Polyline
-n 899 3674 m 27907 3674 l gs col0 s gr 
-% Polyline
-n 899 4122 m 27907 4122 l gs col0 s gr 
-% Polyline
-n 899 4570 m 27907 4570 l gs col0 s gr 
-% Polyline
-n 899 1436 m 27907 1436 l gs col0 s gr 
-% Polyline
-n 899 1883 m 27907 1883 l gs col0 s gr 
-% Polyline
-n 899 2331 m 27907 2331 l gs col0 s gr 
-% Polyline
-n 2699 18000 m 2699 540 l gs col0 s gr 
-% Polyline
-n 899 988 m 27907 988 l gs col0 s gr 
-% Polyline
-n 13491 18000 m 13491 540 l gs col0 s gr 
-% Polyline
-n 1343 18000 m 1343 540 l gs col0 s gr 
-% Polyline
-n 899 9491 m 27907 9491 l gs col0 s gr 
-% Polyline
-n 13047 18000 m 13047 540 l gs col0 s gr 
-% Polyline
-75.000 slw
-n 14850 9540 m 14850 540 l gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-30.000 slw
-n 1350 988 m 13952 988 l 13952 7256 l 1350 7256 l cp gs col33 0.95 shd ef gr gs col0 s gr 
-% Polyline
-n 13952 4122 m 1350 4122 l 1439 4122 l gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 90.00 274.80] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-75.000 slw
-n 18450 17999 m 18450 9318 l gs col7 0.95 shd ef gr gs col0 s gr 
-% Polyline
-30.000 slw
-n 5850 10620 m 9675 10620 l 9675 12375 l 5850 12375 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 390.00 708.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 4950 10620 m 5940 10620 l 5940 12375 l 4950 12375 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 330.00 708.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 6075 14625 m 8505 14625 l 8505 15480 l 6075 15480 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 405.00 975.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 8325 14625 m 11117 14625 l 11117 15480 l 8325 15480 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 555.00 975.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 9675 10620 m 11970 10620 l 11970 12375 l 9675 12375 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 645.00 708.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 11701 10620 m 12600 10620 l 12600 12375 l 11701 12375 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 780.07 708.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 2476 3015 m 4725 3015 l 4725 7043 l 2476 7043 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 165.07 201.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 10531 4346 m 12783 4346 l 12783 7031 l 10531 7031 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 702.07 289.73] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 7831 3003 m 10082 3003 l 10082 7031 l 7831 7031 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 522.07 200.20] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-7.500 slw
-n 4951 3226 m 4951 5913 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 330.07 215.07] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-30.000 slw
-n 4275 3031 m 5625 3031 l 5625 6165 l 4275 6165 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 285.00 202.07] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-7.500 slw
-n 16246 931 m 16246 3618 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1083.07 62.07] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-30.000 slw
-n 15300 540 m 17145 540 l 17145 4140 l 15300 4140 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1020.00 36.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-75.000 slw
-n 18450 9910 m 18450 540 l gs col0 s gr 
-% Polyline
-30.000 slw
-n 20025 6615 m 21380 6615 l 21380 7920 l 20025 7920 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 20025 4343 m 21379 4343 l 21379 5715 l 20025 5715 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-7.500 slw
-n 7650 3195 m 7651 5419 l 7651 6853 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 510.00 213.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 12962 4615 m 12962 6853 l 12962 6763 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 864.13 307.67] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-30.000 slw
-n 19174 9047 m 22325 9047 l 22325 9941 l 19174 9941 l cp gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1278.27 603.13] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19125 767 m 22276 767 l 22276 1215 l 19125 1215 l cp gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 1275.00 51.13] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19125 9047 m 22321 9047 l 22321 9945 l 19125 9945 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1275.00 603.13] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19125 11295 m 22325 11295 l 22325 12180 l 19125 12180 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1275.00 753.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 24075 988 m 27276 988 l 27276 1890 l 24075 1890 l cp gs /PC [[0.00 0.69 0.69] [0.00 0.00 0.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 1605.00 65.87] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 24075 3226 m 27276 3226 l 27276 4095 l 24075 4095 l cp gs /PC [[0.00 0.69 0.69] [0.00 0.00 0.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 1605.00 215.07] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 1800 3015 m 2699 3015 l 2699 5701 l 1800 5701 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 120.00 201.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 12600 4346 m 13500 4346 l 13500 7031 l 12600 7031 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 840.00 289.73] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19125 2522 m 22276 2522 l 22276 2970 l 19125 2970 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 1275.00 168.13] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19125 765 m 22276 765 l 22276 1213 l 19125 1213 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 1275.00 51.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 7202 3003 m 8102 3003 l 8102 7031 l 7202 7031 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 480.13 200.20] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19125 4770 m 22276 4770 l 22276 5220 l 19125 5220 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 1275.00 318.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19534 17104 m 22144 17104 l 22235 17104 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P17 [8 0 0 -8 1302.27 1140.27] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-45.000 slw
-n 19350 9495 m 22050 9495 l gs col0 s gr 
-% Polyline
-30.000 slw
-n 24075 5490 m 27276 5490 l 27276 6390 l 24075 6390 l cp gs /PC [[0.00 0.69 0.69] [0.00 0.00 0.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 1605.00 366.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 24075 7695 m 27276 7695 l 27276 8595 l 24075 8595 l cp gs /PC [[0.00 0.69 0.69] [0.00 0.00 0.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 1605.00 513.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19125 7020 m 22280 7020 l 22280 7470 l 19125 7470 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 1275.00 468.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19080 13980 m 22325 13980 l 22325 14850 l 19080 14850 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1272.00 932.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19125 16648 m 22325 16648 l 22325 17550 l 19125 17550 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1275.00 1109.87] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-45.000 slw
-n 24395 8151 m 27006 8151 l 27096 8151 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P17 [8 0 0 -8 1626.33 543.40] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 24300 5895 m 27006 5913 l 27096 5913 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P17 [8 0 0 -8 1620.00 393.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-30.000 slw
-n 9900 3003 m 10799 3003 l 10799 7031 l 9900 7031 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 660.00 200.20] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-7.500 slw
-n 19444 7254 m 22055 7254 l 22144 7254 l gs col0 s gr 
-% Polyline
-30.000 slw
-n 3375 8145 m 3825 8145 l 3825 10164 l 3375 10164 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 3825 9720 m 4275 9720 l 4275 16425 l 3825 16425 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 3825 15975 m 4275 15975 l 4275 16425 l 3825 16425 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 3825 15975 m 4275 15975 l 4275 16425 l 3825 16425 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-75.000 slw
-n 13050 9495 m 15750 9495 l 16200 9495 l 18405 9495 l gs col0 s gr 
-% Polyline
-30.000 slw
-n 6075 13746 m 7426 13746 l 7426 15089 l 6075 15089 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 405.00 916.40] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 6975 5670 m 8325 5670 l 8325 7020 l 6975 7020 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 465.00 378.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 6931 3003 m 8325 3003 l 8325 4365 l 6931 4365 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 462.07 200.20] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 9675 3003 m 11070 3003 l 11070 4365 l 9675 4365 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 645.00 200.20] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 9675 5689 m 11025 5689 l 11025 7031 l 9675 7031 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 645.00 379.27] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 12375 4770 m 13725 4770 l 13725 6113 l 12375 6113 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 825.00 318.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 25200 7695 m 26100 7695 l 26100 8595 l 25200 8595 l cp gs col1 0.75 shd ef gr gs col0 s gr 
-% Polyline
-n 10125 14618 m 11431 14618 l 11431 15930 l 10125 15930 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 675.00 974.53] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 25245 5490 m 26100 5490 l 26100 6390 l 25245 6390 l cp gs col1 0.75 shd ef gr gs col0 s gr 
-% Polyline
-n 7200 5895 m 8100 5895 l 8100 6795 l 7200 6795 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 480.00 393.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 9900 5895 m 10800 5895 l 10800 6808 l 9900 6808 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 660.00 393.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 12600 4995 m 13500 4995 l 13500 5895 l 12600 5895 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 840.00 333.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 6300 13995 m 7198 13995 l 7198 14850 l 6300 14850 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 420.00 933.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 10350 14940 m 11250 14940 l 11250 15750 l 10350 15750 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.69 0.69]] def
-15.00 15.00 sc P5 [16 0 0 -16 690.00 996.00] PATmp PATsp ef gr PATusp gs col16 s gr 
-% Polyline
-n 4725 10620 m 6075 10620 l 6075 11962 l 4725 11962 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 315.00 708.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 11475 10628 m 12825 10628 l 12825 11970 l 11475 11970 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 765.00 708.53] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 2025 10620 m 3375 10620 l 3375 11970 l 2025 11970 l cp gs /PC [[1.00 0.84 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 135.00 708.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 2250 10845 m 3150 10845 l 3150 11745 l 2250 11745 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 150.00 723.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 12375 1665 m 13726 1665 l 13726 3015 l 12375 3015 l cp gs /PC [[0.00 0.69 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 825.00 111.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 12645 1890 m 13500 1890 l 13500 2745 l 12645 2745 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 843.00 126.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 4275 3015 m 5625 3015 l 5625 4365 l 4275 4365 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 285.00 201.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 4276 4808 m 5626 4808 l 5626 6150 l 4276 6150 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 285.07 320.53] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 15570 2513 m 16920 2513 l 16920 3855 l 15570 3855 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1038.00 167.53] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 15570 728 m 16920 728 l 16920 2070 l 15570 2070 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1038.00 48.53] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 15795 990 m 16695 990 l 16695 1845 l 15795 1845 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 1053.00 66.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 15795 2790 m 16695 2790 l 16695 3645 l 15795 3645 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 1053.00 186.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 4500 5040 m 5400 5040 l 5400 5895 l 4500 5895 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 300.00 336.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 1575 4823 m 2925 4823 l 2925 6165 l 1575 6165 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 105.00 321.53] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 1800 4999 m 2700 4999 l 2700 5895 l 1800 5895 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 120.00 333.27] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-45.000 slw
-n 19395 7245 m 22095 7245 l gs col0 s gr 
-% Polyline
-30.000 slw
-n 4950 10849 m 5850 10849 l 5850 11745 l 4950 11745 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 330.00 723.27] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 11700 10849 m 12600 10849 l 12600 11745 l 11700 11745 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 780.00 723.27] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-7.500 slw
- [90 45 15 45] 0 sd
-n 18454 8599 m 23404 8599 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1230.27 573.27] PATmp PATsp ef gr PATusp gs col0 s gr  [] 0 sd
-% Polyline
-60.000 slw
- [90 45 15 45] 0 sd
-n 23175 541 m 23220 18000 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1545.00 36.07] PATmp PATsp ef gr PATusp gs col0 s gr  [] 0 sd
-% Polyline
- [90 45 15 45] 0 sd
-n 18522 8595 m 23091 8595 l gs col7 0.05 shd ef gr gs col0 s gr  [] 0 sd
-% Polyline
- [90 45 15 45] 0 sd
-n 23247 9045 m 27900 9045 l gs col7 0.05 shd ef gr gs col0 s gr  [] 0 sd
-% Polyline
-30.000 slw
-n 24975 12420 m 26370 12420 l 26370 13725 l 24975 13725 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 24120 12825 m 27270 12825 l 27270 13275 l 24120 13275 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
-45.000 slw
-n 26196 17552 m 27006 17552 l gs col7 0.35 shd ef gr gs col0 s gr 
-% Polyline
-30.000 slw
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-15.00 15.00 sc P5 [16 0 0 -16 480.00 216.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 9900 3240 m 10800 3240 l 10800 4140 l 9900 4140 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 660.00 216.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 4493 3240 m 5400 3240 l 5400 4133 l 4493 4133 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 299.53 216.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-45.000 slw
-n 19350 2745 m 22050 2745 l gs col0 s gr 
-% Polyline
-n 19350 990 m 22050 990 l gs col0 s gr 
-% Polyline
-n 19350 4995 m 22050 4995 l gs col0 s gr 
-% Polyline
-30.000 slw
-n 6526 14194 m 6976 14194 l 6976 14642 l 6526 14642 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-45.000 slw
-n 24305 1436 m 26916 1436 l 27006 1436 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P17 [8 0 0 -8 1620.33 95.73] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 24345 11295 m 27000 11295 l 27045 11295 l gs col0 s gr 
-% Polyline
-n 24345 9945 m 27090 9945 l gs col0 s gr 
-% Polyline
-60.000 slw
- [90 45 15 45] 0 sd
-n 23220 16245 m 27900 16245 l gs col0 s gr  [] 0 sd
-% Polyline
-30.000 slw
-n 2026 5211 m 2475 5211 l 2475 5659 l 2026 5659 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 7425 3427 m 7875 3427 l 7875 3870 l 7425 3870 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
-7.500 slw
-n 4726 5256 m 5175 5256 l 5175 5704 l 4726 5704 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 4725 3427 m 5175 3427 l 5175 3870 l 4725 3870 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
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-% Polyline
-n 16020 1177 m 16470 1177 l 16470 1620 l 16020 1620 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-45.000 slw
-n 6750 9931 m 6750 12170 l 6750 13050 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 450.00 662.07] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 8550 9931 m 8550 12170 l 8550 13050 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 570.00 662.07] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19355 14418 m 21964 14418 l 22055 14418 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P17 [8 0 0 -8 1290.33 961.20] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19355 17104 m 21964 17104 l 22055 17104 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P17 [8 0 0 -8 1290.33 1140.27] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-30.000 slw
-n 3375 7920 m 3825 7920 l 3825 8370 l 3375 8370 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 20025 13725 m 21375 13725 l 21375 15030 l 20025 15030 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1335.00 915.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 20025 16388 m 21375 16388 l 21375 17730 l 20025 17730 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1335.00 1092.53] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 20250 13970 m 21150 13970 l 21150 14850 l 20250 14850 l cp gs col1 0.75 shd ef gr gs col0 s gr 
-% Polyline
-n 2880 7476 m 4232 7476 l 4232 8820 l 2880 8820 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 3150 7698 m 4050 7698 l 4050 8595 l 3150 8595 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 210.00 513.20] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-7.500 slw
-n 3375 9720 m 4275 9720 l 4275 10170 l 3375 10170 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-30.000 slw
-n 3825 15975 m 9225 15975 l 9225 16425 l 3825 16425 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-45.000 slw
-n 24435 15390 m 24250 15175 l gs col0 s gr 
-% Polyline
-n 24440 15175 m 24255 15390 l gs col0 s gr 
-% Polyline
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-% Polyline
-n 24440 12925 m 24255 13140 l gs col0 s gr 
-% Polyline
-30.000 slw
-n 20250 16657 m 21155 16657 l 21155 17550 l 20250 17550 l cp gs col1 0.75 shd ef gr gs col0 s gr 
-% Polyline
-45.000 slw
-n 27135 15390 m 26950 15175 l gs col0 s gr 
-% Polyline
-n 27140 15175 m 26955 15390 l gs col0 s gr 
-% Polyline
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-% Polyline
-n 27140 12925 m 26955 13140 l gs col0 s gr 
-% Polyline
-7.500 slw
-n 19355 9493 m 21964 9493 l 22055 9493 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1290.33 632.87] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-45.000 slw
-n 24305 3674 m 26916 3674 l 27006 3674 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P17 [8 0 0 -8 1620.33 244.93] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19355 11732 m 21964 11732 l 22055 11732 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1290.33 782.13] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 24395 15300 m 27006 15300 l 27096 15300 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P17 [8 0 0 -8 1626.33 1020.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 24395 13050 m 27006 13050 l 27096 13050 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P17 [8 0 0 -8 1626.33 870.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-30.000 slw
-n 11250 7698 m 12150 7698 l 12150 8595 l 11250 8595 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 750.00 513.20] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 10350 13095 m 11250 13095 l 11250 13992 l 10350 13992 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.69 0.69]] def
-15.00 15.00 sc P5 [16 0 0 -16 690.00 873.00] PATmp PATsp ef gr PATusp gs col16 s gr 
-% Polyline
-45.000 slw
-n 9000 2340 m 9000 7695 l gs col0 s gr 
-% Polyline
-n 3600 2385 m 3600 8145 l gs col0 s gr 
-% Polyline
-30.000 slw
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-15.00 15.00 sc P5 [16 0 0 -16 225.00 528.13] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-45.000 slw
-n 27090 11385 m 26905 11170 l gs col0 s gr 
-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
-45.000 slw
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-105.000 slw
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- [60] 0 sd
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- [60] 0 sd
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-rs
-end
diff --git a/alliance/share/doc/symb_rules/symb_rules.fig b/alliance/share/doc/symb_rules/symb_rules.fig
deleted file mode 100644
index 3a62b4d1..00000000
--- a/alliance/share/doc/symb_rules/symb_rules.fig
+++ /dev/null
@@ -1,1516 +0,0 @@
-#FIG 3.2
-Landscape
-Center
-Metric
-A4      
-42.10
-Single
--2
-1200 2
-0 32 #0099ff
-0 33 #f1c084
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-4 0 0 0 0 0 47 4.7124 4 495 6465 28714 5652 SYMBOLIC   RULES \001
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-	 899 10389 27907 10389
-2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
-	 899 10836 27907 10836
-2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
-	 899 11284 27907 11284
-2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
-	 899 7256 27907 7256
-2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
-	 899 7704 27907 7704
-2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
-	 899 8151 27907 8151
-2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
-	 899 8599 27907 8599
-2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
-	 899 9047 27907 9047
-2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
-	 899 5017 27907 5017
-2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
-	 899 5465 27907 5465
-2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
-	 899 5913 27907 5913
-2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
-	 899 6360 27907 6360
-2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
-	 899 6808 27907 6808
-2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
-	 899 18000 27907 18000
-2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
-	 899 540 27907 540
-2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
-	 899 18000 899 540
-2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
-	 899 2779 27907 2779
-2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
-	 899 3226 27907 3226
-2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
-	 899 3674 27907 3674
-2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
-	 899 4122 27907 4122
-2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
-	 899 4570 27907 4570
-2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
-	 899 1436 27907 1436
-2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
-	 899 1883 27907 1883
-2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
-	 899 2331 27907 2331
-2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
-	 2699 18000 2699 540
-2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
-	 899 988 27907 988
-2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
-	 13491 18000 13491 540
-2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
-	 1343 18000 1343 540
-2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
-	 899 9491 27907 9491
-2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
-	 13047 18000 13047 540
--6
-6 26865 11115 27135 11430
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 27090 11385 26905 11170
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 27095 11170 26910 11385
--6
-6 24165 9765 24435 10080
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 24390 10035 24205 9820
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 24395 9820 24210 10035
--6
-6 26865 9765 27135 10080
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 27090 10035 26905 9820
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 27095 9820 26910 10035
--6
-6 24165 11115 24435 11430
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 24390 11385 24205 11170
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 24395 11170 24210 11385
--6
-6 24210 7965 24480 8280
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 24435 8235 24250 8020
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 24440 8020 24255 8235
--6
-6 26865 7965 27135 8280
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 27090 8235 26905 8020
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 27095 8020 26910 8235
--6
-6 26910 5760 27180 6075
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 27135 6030 26950 5815
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 27140 5815 26955 6030
--6
-6 24165 5760 24435 6075
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 24390 6030 24205 5815
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 24395 5815 24210 6030
--6
-6 24210 3510 24480 3825
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 24435 3780 24250 3565
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 24440 3565 24255 3780
--6
-6 26865 3510 27135 3825
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 27090 3780 26905 3565
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 27095 3565 26910 3780
--6
-6 24165 1260 24435 1575
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 24390 1530 24205 1315
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 24395 1315 24210 1530
--6
-6 26820 1260 27090 1575
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 27045 1530 26860 1315
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 27050 1315 26865 1530
--6
-6 19215 810 19485 1125
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 19440 1080 19255 865
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 19445 865 19260 1080
--6
-6 21870 810 22140 1125
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 22095 1080 21910 865
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 22100 865 21915 1080
--6
-6 21870 2565 22140 2880
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 22095 2835 21910 2620
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 22100 2620 21915 2835
--6
-6 19215 2565 19485 2880
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 19440 2835 19255 2620
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 19445 2620 19260 2835
--6
-6 19215 4815 19485 5130
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 19440 5085 19255 4870
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 19445 4870 19260 5085
--6
-6 21870 4815 22140 5130
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 22095 5085 21910 4870
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 22100 4870 21915 5085
--6
-6 21915 9315 22185 9630
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 22140 9585 21955 9370
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 22145 9370 21960 9585
--6
-6 19215 9315 19485 9630
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 19440 9585 19255 9370
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 19445 9370 19260 9585
--6
-6 19215 11565 19485 11880
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 19440 11835 19255 11620
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 19445 11620 19260 11835
--6
-6 21915 11565 22185 11880
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 22140 11835 21955 11620
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 22145 11620 21960 11835
--6
-6 21915 14220 22185 14535
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 22140 14490 21955 14275
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 22145 14275 21960 14490
--6
-6 19215 14265 19485 14580
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 19440 14535 19255 14320
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 19445 14320 19260 14535
--6
-6 19215 16920 19485 17235
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 19440 17190 19255 16975
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 19445 16975 19260 17190
--6
-6 21915 16920 22185 17235
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 22140 17190 21955 16975
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 22145 16975 21960 17190
--6
-6 23670 17370 23940 17685
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 23895 17640 23710 17425
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 23900 17425 23715 17640
--6
-6 24570 17370 24840 17685
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 24795 17640 24610 17425
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 24800 17425 24615 17640
--6
-6 25110 17325 25380 17640
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 25335 17595 25150 17380
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 25340 17380 25155 17595
--6
-6 25110 16470 25380 16785
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 25335 16740 25150 16525
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 25340 16525 25155 16740
--6
-6 26010 17370 26280 17685
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 26235 17640 26050 17425
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 26240 17425 26055 17640
--6
-6 26865 17370 27135 17685
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 27090 17640 26905 17425
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 27095 17425 26910 17640
--6
-6 26865 16515 27135 16830
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 27090 16785 26905 16570
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 27095 16570 26910 16785
--6
-6 12015 11970 12285 12285
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 12240 12240 12055 12025
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 12245 12025 12060 12240
--6
-6 8415 9765 8685 10080
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 8640 10035 8455 9820
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 8645 9820 8460 10035
--6
-6 8415 12915 8685 13230
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 8640 13185 8455 12970
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 8645 12970 8460 13185
--6
-6 6615 9765 6885 10080
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 6840 10035 6655 9820
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 6845 9820 6660 10035
--6
-6 7065 15165 7335 15480
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 7290 15435 7105 15220
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 7295 15220 7110 15435
--6
-6 8865 13815 9135 14130
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 9090 14085 8905 13870
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 9095 13870 8910 14085
--6
-6 8865 16020 9135 16335
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 9090 16290 8905 16075
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 9095 16075 8910 16290
--6
-6 3915 16020 4185 16335
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 4140 16290 3955 16075
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 4145 16075 3960 16290
--6
-6 8865 7515 9135 7830
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 9090 7785 8905 7570
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 9095 7570 8910 7785
--6
-6 8865 2160 9135 2475
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 9090 2430 8905 2215
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 9095 2215 8910 2430
--6
-6 12915 4410 13185 4725
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 13140 4680 12955 4465
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 13145 4465 12960 4680
--6
-6 3465 2160 3735 2475
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 3690 2430 3505 2215
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 3695 2215 3510 2430
--6
-6 1215 3960 1485 4275
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 1440 4230 1255 4015
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 1445 4015 1260 4230
--6
-6 13815 3960 14085 4275
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 14040 4230 13855 4015
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 14045 4015 13860 4230
--6
-6 11565 3510 11835 3825
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 11790 3780 11605 3565
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 11795 3565 11610 3780
--6
-6 12915 6615 13185 6930
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 13140 6885 12955 6670
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 13145 6670 12960 6885
--6
-6 2115 3060 2385 3375
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 2340 3330 2155 3115
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 2345 3115 2160 3330
--6
-6 3960 9765 4230 10080
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 4185 10035 4000 9820
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 4190 9820 4005 10035
--6
-6 5265 12015 5535 12330
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 5490 12285 5305 12070
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 5495 12070 5310 12285
--6
-6 6615 12915 6885 13230
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 6840 13185 6655 12970
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 6845 12970 6660 13185
--6
-6 3465 9765 3735 10080
-2 1 0 4 0 20 61 0 15 0.000 0 0 -1 0 0 2
-	 3690 10035 3505 9820
-2 1 0 4 0 20 61 0 15 0.000 0 0 -1 0 0 2
-	 3695 9820 3510 10035
--6
-6 6480 14175 7020 14670
-6 6480 14175 7020 14670
-6 6480 14175 7020 14670
-2 2 0 3 0 21 70 0 25 0.000 0 0 -1 0 0 5
-	 6526 14194 6976 14194 6976 14642 6526 14642 6526 14194
--6
--6
--6
-6 26910 15120 27180 15435
-2 1 0 4 0 7 65 0 -1 0.000 0 0 -1 0 0 2
-	 27135 15390 26950 15175
-2 1 0 4 0 7 65 0 -1 0.000 0 0 -1 0 0 2
-	 27140 15175 26955 15390
--6
-6 26910 12870 27180 13185
-2 1 0 4 0 7 65 0 -1 0.000 0 0 -1 0 0 2
-	 27135 13140 26950 12925
-2 1 0 4 0 7 65 0 -1 0.000 0 0 -1 0 0 2
-	 27140 12925 26955 13140
--6
-6 10665 9765 10980 10080
-2 1 0 3 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 10927 10035 10712 9820
-2 1 0 3 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 10933 9820 10717 10035
--6
-6 6930 10845 8415 11520
-6 7155 10881 8100 11295
-2 2 0 1 0 7 0 0 20 0.000 0 0 -1 0 0 5
-	 7178 10904 8076 10904 8076 11272 7178 11272 7178 10904
-4 0 0 0 0 0 24 0.0000 4 255 630 7339 11203 3.00\001
--6
-2 1 0 3 0 7 0 0 20 0.000 0 0 -1 1 1 2
-	2 1 8.00 60.00 120.00
-	2 1 8.00 60.00 120.00
-	 6975 11475 8370 11475
--6
-6 7065 14670 7335 14985
-2 1 0 4 0 7 56 0 -1 0.000 0 0 -1 0 0 2
-	 7290 14940 7105 14725
-2 1 0 4 0 7 56 0 -1 0.000 0 0 -1 0 0 2
-	 7295 14725 7110 14940
--6
-6 12015 11115 12285 11430
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 12240 11385 12055 11170
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 12245 11170 12060 11385
--6
-6 2115 5265 2385 5580
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 2340 5535 2155 5320
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 2345 5320 2160 5535
--6
-6 7515 6210 7785 6525
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 7740 6480 7555 6265
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 7745 6265 7560 6480
--6
-6 7515 3465 7785 3780
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 7740 3735 7555 3520
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 7745 3520 7560 3735
--6
-6 10215 6210 10485 6525
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 10440 6480 10255 6265
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 10445 6265 10260 6480
--6
-6 10215 3465 10485 3780
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 10440 3735 10255 3520
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 10445 3520 10260 3735
--6
-6 5265 11115 5535 11430
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 5490 11385 5305 11170
-2 1 0 4 0 7 61 0 -1 0.000 0 0 -1 0 0 2
-	 5495 11170 5310 11385
--6
-6 861 539 27907 18000
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 25206 17999 25206 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 25655 17999 25655 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 26104 17999 26104 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 26555 17999 26555 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 27005 17999 27005 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 27455 17999 27455 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 27906 17999 27906 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 22502 17999 22502 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 22953 17999 22953 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 23403 17999 23403 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 23854 17999 23854 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 24305 17999 24305 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 24756 17999 24756 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 19802 17999 19802 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 20254 17999 20254 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 20703 17999 20703 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 21154 17999 21154 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 21603 17999 21603 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 22054 17999 22054 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 17102 17999 17102 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 17554 17999 17554 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 18003 17999 18003 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 18453 17999 18453 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 18902 17999 18902 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 19354 17999 19354 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 14400 17999 14400 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 14852 17999 14852 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 15301 17999 15301 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 15753 17999 15753 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 16202 17999 16202 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 16654 17999 16654 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 11701 17999 11701 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 12150 17999 12150 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 12602 17999 12602 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 13051 17999 13051 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 13503 17999 13503 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 13952 17999 13952 540
-2 1 1 1 0 7 0 0 -1 4.000 0 0 -1 0 0 2
-	 9001 17999 9001 540
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--6
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--6
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--6
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--6
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--6
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--6
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--6
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--6
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--6
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--6
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--6
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--6
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--6
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--6
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--6
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--6
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--6
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--6
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--6
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-/col4 {1.000 0.000 0.000 srgb} bind def
-/col5 {1.000 0.000 1.000 srgb} bind def
-/col6 {1.000 1.000 0.000 srgb} bind def
-/col7 {1.000 1.000 1.000 srgb} bind def
-/col8 {0.000 0.000 0.560 srgb} bind def
-/col9 {0.000 0.000 0.690 srgb} bind def
-/col10 {0.000 0.000 0.820 srgb} bind def
-/col11 {0.530 0.810 1.000 srgb} bind def
-/col12 {0.000 0.560 0.000 srgb} bind def
-/col13 {0.000 0.690 0.000 srgb} bind def
-/col14 {0.000 0.820 0.000 srgb} bind def
-/col15 {0.000 0.560 0.560 srgb} bind def
-/col16 {0.000 0.690 0.690 srgb} bind def
-/col17 {0.000 0.820 0.820 srgb} bind def
-/col18 {0.560 0.000 0.000 srgb} bind def
-/col19 {0.690 0.000 0.000 srgb} bind def
-/col20 {0.820 0.000 0.000 srgb} bind def
-/col21 {0.560 0.000 0.560 srgb} bind def
-/col22 {0.690 0.000 0.690 srgb} bind def
-/col23 {0.820 0.000 0.820 srgb} bind def
-/col24 {0.500 0.190 0.000 srgb} bind def
-/col25 {0.630 0.250 0.000 srgb} bind def
-/col26 {0.750 0.380 0.000 srgb} bind def
-/col27 {1.000 0.500 0.500 srgb} bind def
-/col28 {1.000 0.630 0.630 srgb} bind def
-/col29 {1.000 0.750 0.750 srgb} bind def
-/col30 {1.000 0.880 0.880 srgb} bind def
-/col31 {1.000 0.840 0.000 srgb} bind def
-/col32 {0.000 0.600 1.000 srgb} bind def
-/col33 {0.945 0.753 0.518 srgb} bind def
-
-end
-save
-52.5 26.0 translate
- 90 rotate
-1 -1 scale
-.9 .9 scale % to make patterns same scale as in xfig
-
-% This junk string is used by the show operators
-/PATsstr 1 string def
-/PATawidthshow { 	% cx cy cchar rx ry string
-  % Loop over each character in the string
-  {  % cx cy cchar rx ry char
-    % Show the character
-    dup				% cx cy cchar rx ry char char
-    PATsstr dup 0 4 -1 roll put	% cx cy cchar rx ry char (char)
-    false charpath		% cx cy cchar rx ry char
-    /clip load PATdraw
-    % Move past the character (charpath modified the
-    % current point)
-    currentpoint			% cx cy cchar rx ry char x y
-    newpath
-    moveto			% cx cy cchar rx ry char
-    % Reposition by cx,cy if the character in the string is cchar
-    3 index eq {			% cx cy cchar rx ry
-      4 index 4 index rmoveto
-    } if
-    % Reposition all characters by rx ry
-    2 copy rmoveto		% cx cy cchar rx ry
-  } forall
-  pop pop pop pop pop		% -
-  currentpoint
-  newpath
-  moveto
-} bind def
-/PATcg {
-  7 dict dup begin
-    /lw currentlinewidth def
-    /lc currentlinecap def
-    /lj currentlinejoin def
-    /ml currentmiterlimit def
-    /ds [ currentdash ] def
-    /cc [ currentrgbcolor ] def
-    /cm matrix currentmatrix def
-  end
-} bind def
-% PATdraw - calculates the boundaries of the object and
-% fills it with the current pattern
-/PATdraw {			% proc
-  save exch
-    PATpcalc			% proc nw nh px py
-    5 -1 roll exec		% nw nh px py
-    newpath
-    PATfill			% -
-  restore
-} bind def
-% PATfill - performs the tiling for the shape
-/PATfill { % nw nh px py PATfill -
-  PATDict /CurrentPattern get dup begin
-    setfont
-    % Set the coordinate system to Pattern Space
-    PatternGState PATsg
-    % Set the color for uncolored pattezns
-    PaintType 2 eq { PATDict /PColor get PATsc } if
-    % Create the string for showing
-    3 index string		% nw nh px py str
-    % Loop for each of the pattern sources
-    0 1 Multi 1 sub {		% nw nh px py str source
-	% Move to the starting location
-	3 index 3 index		% nw nh px py str source px py
-	moveto			% nw nh px py str source
-	% For multiple sources, set the appropriate color
-	Multi 1 ne { dup PC exch get PATsc } if
-	% Set the appropriate string for the source
-	0 1 7 index 1 sub { 2 index exch 2 index put } for pop
-	% Loop over the number of vertical cells
-	3 index 		% nw nh px py str nh
-	{			% nw nh px py str
-	  currentpoint		% nw nh px py str cx cy
-	  2 index show		% nw nh px py str cx cy
-	  YStep add moveto	% nw nh px py str
-	} repeat		% nw nh px py str
-    } for
-    5 { pop } repeat
-  end
-} bind def
-
-% PATkshow - kshow with the current pattezn
-/PATkshow {			% proc string
-  exch bind			% string proc
-  1 index 0 get			% string proc char
-  % Loop over all but the last character in the string
-  0 1 4 index length 2 sub {
-				% string proc char idx
-    % Find the n+1th character in the string
-    3 index exch 1 add get	% string proe char char+1
-    exch 2 copy			% strinq proc char+1 char char+1 char
-    % Now show the nth character
-    PATsstr dup 0 4 -1 roll put	% string proc chr+1 chr chr+1 (chr)
-    false charpath		% string proc char+1 char char+1
-    /clip load PATdraw
-    % Move past the character (charpath modified the current point)
-    currentpoint newpath moveto
-    % Execute the user proc (should consume char and char+1)
-    mark 3 1 roll		% string proc char+1 mark char char+1
-    4 index exec		% string proc char+1 mark...
-    cleartomark			% string proc char+1
-  } for
-  % Now display the last character
-  PATsstr dup 0 4 -1 roll put	% string proc (char+1)
-  false charpath		% string proc
-  /clip load PATdraw
-  neewath
-  pop pop			% -
-} bind def
-% PATmp - the makepattern equivalent
-/PATmp {			% patdict patmtx PATmp patinstance
-  exch dup length 7 add		% We will add 6 new entries plus 1 FID
-  dict copy			% Create a new dictionary
-  begin
-    % Matrix to install when painting the pattern
-    TilingType PATtcalc
-    /PatternGState PATcg def
-    PatternGState /cm 3 -1 roll put
-    % Check for multi pattern sources (Level 1 fast color patterns)
-    currentdict /Multi known not { /Multi 1 def } if
-    % Font dictionary definitions
-    /FontType 3 def
-    % Create a dummy encoding vector
-    /Encoding 256 array def
-    3 string 0 1 255 {
-      Encoding exch dup 3 index cvs cvn put } for pop
-    /FontMatrix matrix def
-    /FontBBox BBox def
-    /BuildChar {
-	mark 3 1 roll		% mark dict char
-	exch begin
-	Multi 1 ne {PaintData exch get}{pop} ifelse  % mark [paintdata]
-	  PaintType 2 eq Multi 1 ne or
-	  { XStep 0 FontBBox aload pop setcachedevice }
-	  { XStep 0 setcharwidth } ifelse
-	  currentdict		% mark [paintdata] dict
-	  /PaintProc load	% mark [paintdata] dict paintproc
-	end
-	gsave
-	  false PATredef exec true PATredef
-	grestore
-	cleartomark		% -
-    } bind def
-    currentdict
-  end				% newdict
-  /foo exch			% /foo newlict
-  definefont			% newfont
-} bind def
-% PATpcalc - calculates the starting point and width/height
-% of the tile fill for the shape
-/PATpcalc {	% - PATpcalc nw nh px py
-  PATDict /CurrentPattern get begin
-    gsave
-	% Set up the coordinate system to Pattern Space
-	% and lock down pattern
-	PatternGState /cm get setmatrix
-	BBox aload pop pop pop translate
-	% Determine the bounding box of the shape
-	pathbbox			% llx lly urx ury
-    grestore
-    % Determine (nw, nh) the # of cells to paint width and height
-    PatHeight div ceiling		% llx lly urx qh
-    4 1 roll				% qh llx lly urx
-    PatWidth div ceiling		% qh llx lly qw
-    4 1 roll				% qw qh llx lly
-    PatHeight div floor			% qw qh llx ph
-    4 1 roll				% ph qw qh llx
-    PatWidth div floor			% ph qw qh pw
-    4 1 roll				% pw ph qw qh
-    2 index sub cvi abs			% pw ph qs qh-ph
-    exch 3 index sub cvi abs exch	% pw ph nw=qw-pw nh=qh-ph
-    % Determine the starting point of the pattern fill
-    %(px, py)
-    4 2 roll				% nw nh pw ph
-    PatHeight mul			% nw nh pw py
-    exch				% nw nh py pw
-    PatWidth mul exch			% nw nh px py
-  end
-} bind def
-
-% Save the original routines so that we can use them later on
-/oldfill	/fill load def
-/oldeofill	/eofill load def
-/oldstroke	/stroke load def
-/oldshow	/show load def
-/oldashow	/ashow load def
-/oldwidthshow	/widthshow load def
-/oldawidthshow	/awidthshow load def
-/oldkshow	/kshow load def
-
-% These defs are necessary so that subsequent procs don't bind in
-% the originals
-/fill	   { oldfill } bind def
-/eofill	   { oldeofill } bind def
-/stroke	   { oldstroke } bind def
-/show	   { oldshow } bind def
-/ashow	   { oldashow } bind def
-/widthshow { oldwidthshow } bind def
-/awidthshow { oldawidthshow } bind def
-/kshow 	   { oldkshow } bind def
-/PATredef {
-  MyAppDict begin
-    {
-    /fill { /clip load PATdraw newpath } bind def
-    /eofill { /eoclip load PATdraw newpath } bind def
-    /stroke { PATstroke } bind def
-    /show { 0 0 null 0 0 6 -1 roll PATawidthshow } bind def
-    /ashow { 0 0 null 6 3 roll PATawidthshow }
-    bind def
-    /widthshow { 0 0 3 -1 roll PATawidthshow }
-    bind def
-    /awidthshow { PATawidthshow } bind def
-    /kshow { PATkshow } bind def
-  } {
-    /fill   { oldfill } bind def
-    /eofill { oldeofill } bind def
-    /stroke { oldstroke } bind def
-    /show   { oldshow } bind def
-    /ashow  { oldashow } bind def
-    /widthshow { oldwidthshow } bind def
-    /awidthshow { oldawidthshow } bind def
-    /kshow  { oldkshow } bind def
-    } ifelse
-  end
-} bind def
-false PATredef
-% Conditionally define setcmykcolor if not available
-/setcmykcolor where { pop } {
-  /setcmykcolor {
-    1 sub 4 1 roll
-    3 {
-	3 index add neg dup 0 lt { pop 0 } if 3 1 roll
-    } repeat
-    setrgbcolor - pop
-  } bind def
-} ifelse
-/PATsc {		% colorarray
-  aload length		% c1 ... cn length
-    dup 1 eq { pop setgray } { 3 eq { setrgbcolor } { setcmykcolor
-  } ifelse } ifelse
-} bind def
-/PATsg {		% dict
-  begin
-    lw setlinewidth
-    lc setlinecap
-    lj setlinejoin
-    ml setmiterlimit
-    ds aload pop setdash
-    cc aload pop setrgbcolor
-    cm setmatrix
-  end
-} bind def
-
-/PATDict 3 dict def
-/PATsp {
-  true PATredef
-  PATDict begin
-    /CurrentPattern exch def
-    % If it's an uncolored pattern, save the color
-    CurrentPattern /PaintType get 2 eq {
-      /PColor exch def
-    } if
-    /CColor [ currentrgbcolor ] def
-  end
-} bind def
-% PATstroke - stroke with the current pattern
-/PATstroke {
-  countdictstack
-  save
-  mark
-  {
-    currentpoint strokepath moveto
-    PATpcalc				% proc nw nh px py
-    clip newpath PATfill
-    } stopped {
-	(*** PATstroke Warning: Path is too complex, stroking
-	  with gray) =
-    cleartomark
-    restore
-    countdictstack exch sub dup 0 gt
-	{ { end } repeat } { pop } ifelse
-    gsave 0.5 setgray oldstroke grestore
-  } { pop restore pop } ifelse
-  newpath
-} bind def
-/PATtcalc {		% modmtx tilingtype PATtcalc tilematrix
-  % Note: tiling types 2 and 3 are not supported
-  gsave
-    exch concat					% tilingtype
-    matrix currentmatrix exch			% cmtx tilingtype
-    % Tiling type 1 and 3: constant spacing
-    2 ne {
-	% Distort the pattern so that it occupies
-	% an integral number of device pixels
-	dup 4 get exch dup 5 get exch		% tx ty cmtx
-	XStep 0 dtransform
-	round exch round exch			% tx ty cmtx dx.x dx.y
-	XStep div exch XStep div exch		% tx ty cmtx a b
-	0 YStep dtransform
-	round exch round exch			% tx ty cmtx a b dy.x dy.y
-	YStep div exch YStep div exch		% tx ty cmtx a b c d
-	7 -3 roll astore			% { a b c d tx ty }
-    } if
-  grestore
-} bind def
-/PATusp {
-  false PATredef
-  PATDict begin
-    CColor PATsc
-  end
-} bind def
-
-% left45
-11 dict begin
-/PaintType 1 def
-/PatternType 1 def
-/TilingType 1 def
-/BBox [0 0 1 1] def
-/XStep 1 def
-/YStep 1 def
-/PatWidth 1 def
-/PatHeight 1 def
-/Multi 2 def
-/PaintData [
-  { clippath } bind
-  { 32 32 true [ 32 0 0 -32 0 32 ]
-	{<808080804040404020202020101010100808080804040404
-	020202020101010180808080404040402020202010101010
-	080808080404040402020202010101018080808040404040
-	202020201010101008080808040404040202020201010101
-	808080804040404020202020101010100808080804040404
-	0202020201010101>}
-     imagemask } bind
-] def
-/PaintProc {
-	pop
-	exec fill
-} def
-currentdict
-end
-/P4 exch def
-
-% right45
-11 dict begin
-/PaintType 1 def
-/PatternType 1 def
-/TilingType 1 def
-/BBox [0 0 1 1] def
-/XStep 1 def
-/YStep 1 def
-/PatWidth 1 def
-/PatHeight 1 def
-/Multi 2 def
-/PaintData [
-  { clippath } bind
-  { 32 32 true [ 32 0 0 -32 0 32 ]
-	{<010101010202020204040404080808081010101020202020
-	404040408080808001010101020202020404040408080808
-	101010102020202040404040808080800101010102020202
-	040404040808080810101010202020204040404080808080
-	010101010202020204040404080808081010101020202020
-	4040404080808080>}
-     imagemask } bind
-] def
-/PaintProc {
-	pop
-	exec fill
-} def
-currentdict
-end
-/P5 exch def
-
-% small fishscales
-11 dict begin
-/PaintType 1 def
-/PatternType 1 def
-/TilingType 1 def
-/BBox [0 0 1 1] def
-/XStep 1 def
-/YStep 1 def
-/PatWidth 1 def
-/PatHeight 1 def
-/Multi 2 def
-/PaintData [
-  { clippath } bind
-  { 16 16 true [ 16 0 0 -16 0 16 ]
-	{<008000800080014001400220
-	0c187007c001800080004001
-	40012002180c0770>}
-     imagemask } bind
-] def
-/PaintProc {
-	pop
-	exec fill
-} def
-currentdict
-end
-/P17 exch def
-1.1111 1.1111 scale %restore scale
-
-/cp {closepath} bind def
-/ef {eofill} bind def
-/gr {grestore} bind def
-/gs {gsave} bind def
-/sa {save} bind def
-/rs {restore} bind def
-/l {lineto} bind def
-/m {moveto} bind def
-/rm {rmoveto} bind def
-/n {newpath} bind def
-/s {stroke} bind def
-/sh {show} bind def
-/slc {setlinecap} bind def
-/slj {setlinejoin} bind def
-/slw {setlinewidth} bind def
-/srgb {setrgbcolor} bind def
-/rot {rotate} bind def
-/sc {scale} bind def
-/sd {setdash} bind def
-/ff {findfont} bind def
-/sf {setfont} bind def
-/scf {scalefont} bind def
-/sw {stringwidth} bind def
-/tr {translate} bind def
-/tnt {dup dup currentrgbcolor
-  4 -2 roll dup 1 exch sub 3 -1 roll mul add
-  4 -2 roll dup 1 exch sub 3 -1 roll mul add
-  4 -2 roll dup 1 exch sub 3 -1 roll mul add srgb}
-  bind def
-/shd {dup dup currentrgbcolor 4 -2 roll mul 4 -2 roll mul
-  4 -2 roll mul srgb} bind def
-/reencdict 12 dict def /ReEncode { reencdict begin
-/newcodesandnames exch def /newfontname exch def /basefontname exch def
-/basefontdict basefontname findfont def /newfont basefontdict maxlength dict def
-basefontdict { exch dup /FID ne { dup /Encoding eq
-{ exch dup length array copy newfont 3 1 roll put }
-{ exch newfont 3 1 roll put } ifelse } { pop pop } ifelse } forall
-newfont /FontName newfontname put newcodesandnames aload pop
-128 1 255 { newfont /Encoding get exch /.notdef put } for
-newcodesandnames length 2 idiv { newfont /Encoding get 3 1 roll put } repeat
-newfontname newfont definefont pop end } def
-/isovec [
-8#200 /grave 8#201 /acute 8#202 /circumflex 8#203 /tilde
-8#204 /macron 8#205 /breve 8#206 /dotaccent 8#207 /dieresis
-8#210 /ring 8#211 /cedilla 8#212 /hungarumlaut 8#213 /ogonek 8#214 /caron
-8#220 /dotlessi 8#230 /oe 8#231 /OE
-8#240 /space 8#241 /exclamdown 8#242 /cent 8#243 /sterling
-8#244 /currency 8#245 /yen 8#246 /brokenbar 8#247 /section 8#250 /dieresis
-8#251 /copyright 8#252 /ordfeminine 8#253 /guillemotleft 8#254 /logicalnot
-8#255 /endash 8#256 /registered 8#257 /macron 8#260 /degree 8#261 /plusminus
-8#262 /twosuperior 8#263 /threesuperior 8#264 /acute 8#265 /mu 8#266 /paragraph
-8#267 /periodcentered 8#270 /cedilla 8#271 /onesuperior 8#272 /ordmasculine
-8#273 /guillemotright 8#274 /onequarter 8#275 /onehalf
-8#276 /threequarters 8#277 /questiondown 8#300 /Agrave 8#301 /Aacute
-8#302 /Acircumflex 8#303 /Atilde 8#304 /Adieresis 8#305 /Aring
-8#306 /AE 8#307 /Ccedilla 8#310 /Egrave 8#311 /Eacute
-8#312 /Ecircumflex 8#313 /Edieresis 8#314 /Igrave 8#315 /Iacute
-8#316 /Icircumflex 8#317 /Idieresis 8#320 /Eth 8#321 /Ntilde 8#322 /Ograve
-8#323 /Oacute 8#324 /Ocircumflex 8#325 /Otilde 8#326 /Odieresis 8#327 /multiply
-8#330 /Oslash 8#331 /Ugrave 8#332 /Uacute 8#333 /Ucircumflex
-8#334 /Udieresis 8#335 /Yacute 8#336 /Thorn 8#337 /germandbls 8#340 /agrave
-8#341 /aacute 8#342 /acircumflex 8#343 /atilde 8#344 /adieresis 8#345 /aring
-8#346 /ae 8#347 /ccedilla 8#350 /egrave 8#351 /eacute
-8#352 /ecircumflex 8#353 /edieresis 8#354 /igrave 8#355 /iacute
-8#356 /icircumflex 8#357 /idieresis 8#360 /eth 8#361 /ntilde 8#362 /ograve
-8#363 /oacute 8#364 /ocircumflex 8#365 /otilde 8#366 /odieresis 8#367 /divide
-8#370 /oslash 8#371 /ugrave 8#372 /uacute 8#373 /ucircumflex
-8#374 /udieresis 8#375 /yacute 8#376 /thorn 8#377 /ydieresis] def
-/Times-Roman /Times-Roman-iso isovec ReEncode
-/$F2psBegin {$F2psDict begin /$F2psEnteredState save def} def
-/$F2psEnd {$F2psEnteredState restore end} def
-%%EndProlog
-
-$F2psBegin
-10 setmiterlimit
-n -1000 19065 m -1000 -1000 l 30444 -1000 l 30444 19065 l cp clip
- 0.02646 0.02646 sc
-%%Page: 1 1
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-n 899 16209 m 27907 16209 l gs col0 s gr 
-% Polyline
-n 899 16657 m 27907 16657 l gs col0 s gr 
-% Polyline
-n 899 17104 m 27907 17104 l gs col0 s gr 
-% Polyline
-n 899 17552 m 27907 17552 l gs col0 s gr 
-% Polyline
-n 899 13970 m 27907 13970 l gs col0 s gr 
-% Polyline
-n 899 14418 m 27907 14418 l gs col0 s gr 
-% Polyline
-n 899 14866 m 27907 14866 l gs col0 s gr 
-% Polyline
-n 899 15314 m 27907 15314 l gs col0 s gr 
-% Polyline
-n 899 15761 m 27907 15761 l gs col0 s gr 
-% Polyline
-n 899 11732 m 27907 11732 l gs col0 s gr 
-% Polyline
-n 899 12180 m 27907 12180 l gs col0 s gr 
-% Polyline
-n 899 12627 m 27907 12627 l gs col0 s gr 
-% Polyline
-n 899 13075 m 27907 13075 l gs col0 s gr 
-% Polyline
-n 899 13523 m 27907 13523 l gs col0 s gr 
-% Polyline
-n 899 9941 m 27907 9941 l gs col0 s gr 
-% Polyline
-n 899 10389 m 27907 10389 l gs col0 s gr 
-% Polyline
-n 899 10836 m 27907 10836 l gs col0 s gr 
-% Polyline
-n 899 11284 m 27907 11284 l gs col0 s gr 
-% Polyline
-n 899 7256 m 27907 7256 l gs col0 s gr 
-% Polyline
-n 899 7704 m 27907 7704 l gs col0 s gr 
-% Polyline
-n 899 8151 m 27907 8151 l gs col0 s gr 
-% Polyline
-n 899 8599 m 27907 8599 l gs col0 s gr 
-% Polyline
-n 899 9047 m 27907 9047 l gs col0 s gr 
-% Polyline
-n 899 5017 m 27907 5017 l gs col0 s gr 
-% Polyline
-n 899 5465 m 27907 5465 l gs col0 s gr 
-% Polyline
-n 899 5913 m 27907 5913 l gs col0 s gr 
-% Polyline
-n 899 6360 m 27907 6360 l gs col0 s gr 
-% Polyline
-n 899 6808 m 27907 6808 l gs col0 s gr 
-% Polyline
-n 899 18000 m 27907 18000 l gs col0 s gr 
-% Polyline
-n 899 540 m 27907 540 l gs col0 s gr 
-% Polyline
-n 899 18000 m 899 540 l gs col0 s gr 
-% Polyline
-n 899 2779 m 27907 2779 l gs col0 s gr 
-% Polyline
-n 899 3226 m 27907 3226 l gs col0 s gr 
-% Polyline
-n 899 3674 m 27907 3674 l gs col0 s gr 
-% Polyline
-n 899 4122 m 27907 4122 l gs col0 s gr 
-% Polyline
-n 899 4570 m 27907 4570 l gs col0 s gr 
-% Polyline
-n 899 1436 m 27907 1436 l gs col0 s gr 
-% Polyline
-n 899 1883 m 27907 1883 l gs col0 s gr 
-% Polyline
-n 899 2331 m 27907 2331 l gs col0 s gr 
-% Polyline
-n 2699 18000 m 2699 540 l gs col0 s gr 
-% Polyline
-n 899 988 m 27907 988 l gs col0 s gr 
-% Polyline
-n 13491 18000 m 13491 540 l gs col0 s gr 
-% Polyline
-n 1343 18000 m 1343 540 l gs col0 s gr 
-% Polyline
-n 899 9491 m 27907 9491 l gs col0 s gr 
-% Polyline
-n 13047 18000 m 13047 540 l gs col0 s gr 
-% Polyline
-75.000 slw
-n 14850 9540 m 14850 540 l gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-30.000 slw
-n 1350 988 m 13952 988 l 13952 7256 l 1350 7256 l cp gs col33 0.95 shd ef gr gs col0 s gr 
-% Polyline
-n 13952 4122 m 1350 4122 l 1439 4122 l gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 90.00 274.80] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-75.000 slw
-n 18450 17999 m 18450 9318 l gs col7 0.95 shd ef gr gs col0 s gr 
-% Polyline
-30.000 slw
-n 5850 10620 m 9675 10620 l 9675 12375 l 5850 12375 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 390.00 708.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 4950 10620 m 5940 10620 l 5940 12375 l 4950 12375 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 330.00 708.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 6075 14625 m 8505 14625 l 8505 15480 l 6075 15480 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 405.00 975.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 8325 14625 m 11117 14625 l 11117 15480 l 8325 15480 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 555.00 975.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 9675 10620 m 11970 10620 l 11970 12375 l 9675 12375 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 645.00 708.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 11701 10620 m 12600 10620 l 12600 12375 l 11701 12375 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 780.07 708.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 2476 3015 m 4725 3015 l 4725 7043 l 2476 7043 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 165.07 201.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 10531 4346 m 12783 4346 l 12783 7031 l 10531 7031 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 702.07 289.73] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 7831 3003 m 10082 3003 l 10082 7031 l 7831 7031 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 522.07 200.20] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-7.500 slw
-n 4951 3226 m 4951 5913 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 330.07 215.07] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-30.000 slw
-n 4275 3031 m 5625 3031 l 5625 6165 l 4275 6165 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 285.00 202.07] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-7.500 slw
-n 16246 931 m 16246 3618 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1083.07 62.07] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-30.000 slw
-n 15300 540 m 17145 540 l 17145 4140 l 15300 4140 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1020.00 36.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-75.000 slw
-n 18450 9910 m 18450 540 l gs col0 s gr 
-% Polyline
-30.000 slw
-n 20025 6615 m 21380 6615 l 21380 7920 l 20025 7920 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 20025 4343 m 21379 4343 l 21379 5715 l 20025 5715 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-7.500 slw
-n 7650 3195 m 7651 5419 l 7651 6853 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 510.00 213.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 12962 4615 m 12962 6853 l 12962 6763 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 864.13 307.67] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-30.000 slw
-n 19174 9047 m 22325 9047 l 22325 9941 l 19174 9941 l cp gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1278.27 603.13] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19125 767 m 22276 767 l 22276 1215 l 19125 1215 l cp gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 1275.00 51.13] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19125 9047 m 22321 9047 l 22321 9945 l 19125 9945 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1275.00 603.13] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19125 11295 m 22325 11295 l 22325 12180 l 19125 12180 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1275.00 753.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 24075 988 m 27276 988 l 27276 1890 l 24075 1890 l cp gs /PC [[0.00 0.69 0.69] [0.00 0.00 0.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 1605.00 65.87] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 24075 3226 m 27276 3226 l 27276 4095 l 24075 4095 l cp gs /PC [[0.00 0.69 0.69] [0.00 0.00 0.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 1605.00 215.07] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 1800 3015 m 2699 3015 l 2699 5701 l 1800 5701 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 120.00 201.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 12600 4346 m 13500 4346 l 13500 7031 l 12600 7031 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 840.00 289.73] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19125 2522 m 22276 2522 l 22276 2970 l 19125 2970 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 1275.00 168.13] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19125 765 m 22276 765 l 22276 1213 l 19125 1213 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 1275.00 51.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 7202 3003 m 8102 3003 l 8102 7031 l 7202 7031 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 480.13 200.20] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19125 4770 m 22276 4770 l 22276 5220 l 19125 5220 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 1275.00 318.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19534 17104 m 22144 17104 l 22235 17104 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P17 [8 0 0 -8 1302.27 1140.27] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-45.000 slw
-n 19350 9495 m 22050 9495 l gs col0 s gr 
-% Polyline
-30.000 slw
-n 24075 5490 m 27276 5490 l 27276 6390 l 24075 6390 l cp gs /PC [[0.00 0.69 0.69] [0.00 0.00 0.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 1605.00 366.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 24075 7695 m 27276 7695 l 27276 8595 l 24075 8595 l cp gs /PC [[0.00 0.69 0.69] [0.00 0.00 0.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 1605.00 513.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19125 7020 m 22280 7020 l 22280 7470 l 19125 7470 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 1275.00 468.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19080 13980 m 22325 13980 l 22325 14850 l 19080 14850 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1272.00 932.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19125 16648 m 22325 16648 l 22325 17550 l 19125 17550 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1275.00 1109.87] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-45.000 slw
-n 24395 8151 m 27006 8151 l 27096 8151 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P17 [8 0 0 -8 1626.33 543.40] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 24300 5895 m 27006 5913 l 27096 5913 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P17 [8 0 0 -8 1620.00 393.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-30.000 slw
-n 9900 3003 m 10799 3003 l 10799 7031 l 9900 7031 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 660.00 200.20] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-7.500 slw
-n 19444 7254 m 22055 7254 l 22144 7254 l gs col0 s gr 
-% Polyline
-30.000 slw
-n 3375 8145 m 3825 8145 l 3825 10164 l 3375 10164 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 3825 9720 m 4275 9720 l 4275 16425 l 3825 16425 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 3825 15975 m 4275 15975 l 4275 16425 l 3825 16425 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 3825 15975 m 4275 15975 l 4275 16425 l 3825 16425 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-75.000 slw
-n 13050 9495 m 15750 9495 l 16200 9495 l 18405 9495 l gs col0 s gr 
-% Polyline
-30.000 slw
-n 6075 13746 m 7426 13746 l 7426 15089 l 6075 15089 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 405.00 916.40] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 6975 5670 m 8325 5670 l 8325 7020 l 6975 7020 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 465.00 378.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 6931 3003 m 8325 3003 l 8325 4365 l 6931 4365 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 462.07 200.20] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 9675 3003 m 11070 3003 l 11070 4365 l 9675 4365 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 645.00 200.20] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 9675 5689 m 11025 5689 l 11025 7031 l 9675 7031 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 645.00 379.27] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 12375 4770 m 13725 4770 l 13725 6113 l 12375 6113 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 825.00 318.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 25200 7695 m 26100 7695 l 26100 8595 l 25200 8595 l cp gs col1 0.75 shd ef gr gs col0 s gr 
-% Polyline
-n 10125 14618 m 11431 14618 l 11431 15930 l 10125 15930 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 675.00 974.53] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 25245 5490 m 26100 5490 l 26100 6390 l 25245 6390 l cp gs col1 0.75 shd ef gr gs col0 s gr 
-% Polyline
-n 7200 5895 m 8100 5895 l 8100 6795 l 7200 6795 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 480.00 393.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 9900 5895 m 10800 5895 l 10800 6808 l 9900 6808 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 660.00 393.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 12600 4995 m 13500 4995 l 13500 5895 l 12600 5895 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 840.00 333.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 6300 13995 m 7198 13995 l 7198 14850 l 6300 14850 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 420.00 933.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 10350 14940 m 11250 14940 l 11250 15750 l 10350 15750 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.69 0.69]] def
-15.00 15.00 sc P5 [16 0 0 -16 690.00 996.00] PATmp PATsp ef gr PATusp gs col16 s gr 
-% Polyline
-n 4725 10620 m 6075 10620 l 6075 11962 l 4725 11962 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 315.00 708.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 11475 10628 m 12825 10628 l 12825 11970 l 11475 11970 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 765.00 708.53] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 2025 10620 m 3375 10620 l 3375 11970 l 2025 11970 l cp gs /PC [[1.00 0.84 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 135.00 708.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 2250 10845 m 3150 10845 l 3150 11745 l 2250 11745 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 150.00 723.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 12375 1665 m 13726 1665 l 13726 3015 l 12375 3015 l cp gs /PC [[0.00 0.69 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 825.00 111.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 12645 1890 m 13500 1890 l 13500 2745 l 12645 2745 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 843.00 126.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 4275 3015 m 5625 3015 l 5625 4365 l 4275 4365 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 285.00 201.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 4276 4808 m 5626 4808 l 5626 6150 l 4276 6150 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 285.07 320.53] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 15570 2513 m 16920 2513 l 16920 3855 l 15570 3855 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1038.00 167.53] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 15570 728 m 16920 728 l 16920 2070 l 15570 2070 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1038.00 48.53] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 15795 990 m 16695 990 l 16695 1845 l 15795 1845 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 1053.00 66.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 15795 2790 m 16695 2790 l 16695 3645 l 15795 3645 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 1053.00 186.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 4500 5040 m 5400 5040 l 5400 5895 l 4500 5895 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 300.00 336.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 1575 4823 m 2925 4823 l 2925 6165 l 1575 6165 l cp gs /PC [[1.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 105.00 321.53] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 1800 4999 m 2700 4999 l 2700 5895 l 1800 5895 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 120.00 333.27] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-45.000 slw
-n 19395 7245 m 22095 7245 l gs col0 s gr 
-% Polyline
-30.000 slw
-n 4950 10849 m 5850 10849 l 5850 11745 l 4950 11745 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 330.00 723.27] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 11700 10849 m 12600 10849 l 12600 11745 l 11700 11745 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 780.00 723.27] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-7.500 slw
- [90 45 15 45] 0 sd
-n 18454 8599 m 23404 8599 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1230.27 573.27] PATmp PATsp ef gr PATusp gs col0 s gr  [] 0 sd
-% Polyline
-60.000 slw
- [90 45 15 45] 0 sd
-n 23175 541 m 23220 18000 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1545.00 36.07] PATmp PATsp ef gr PATusp gs col0 s gr  [] 0 sd
-% Polyline
- [90 45 15 45] 0 sd
-n 18522 8595 m 23091 8595 l gs col7 0.05 shd ef gr gs col0 s gr  [] 0 sd
-% Polyline
- [90 45 15 45] 0 sd
-n 23247 9045 m 27900 9045 l gs col7 0.05 shd ef gr gs col0 s gr  [] 0 sd
-% Polyline
-30.000 slw
-n 24975 12420 m 26370 12420 l 26370 13725 l 24975 13725 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 24120 12825 m 27270 12825 l 27270 13275 l 24120 13275 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 24075 9722 m 27271 9722 l 27271 10170 l 24075 10170 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
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-% Polyline
-n 23540 17327 m 24980 17327 l 24980 17775 l 23540 17775 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
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-% Polyline
-n 25920 17327 m 27269 17327 l 27269 17775 l 25920 17775 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
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-% Polyline
-45.000 slw
-n 26196 17552 m 27006 17552 l gs col7 0.35 shd ef gr gs col0 s gr 
-% Polyline
-30.000 slw
-n 26820 16470 m 27270 16470 l 27270 17775 l 26820 17775 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 11475 3674 m 11925 3674 l 11925 8151 l 11475 8151 l cp gs col4 0.95 shd ef gr gs col0 s gr 
-% Polyline
-n 25020 14670 m 26370 14670 l 26370 15976 l 25020 15976 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
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-% Polyline
-n 7200 3240 m 8100 3240 l 8100 4140 l 7200 4140 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 480.00 216.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 9900 3240 m 10800 3240 l 10800 4140 l 9900 4140 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 660.00 216.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 4493 3240 m 5400 3240 l 5400 4133 l 4493 4133 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 299.53 216.00] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-45.000 slw
-n 19350 2745 m 22050 2745 l gs col0 s gr 
-% Polyline
-n 19350 990 m 22050 990 l gs col0 s gr 
-% Polyline
-n 19350 4995 m 22050 4995 l gs col0 s gr 
-% Polyline
-30.000 slw
-n 6526 14194 m 6976 14194 l 6976 14642 l 6526 14642 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-45.000 slw
-n 24305 1436 m 26916 1436 l 27006 1436 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P17 [8 0 0 -8 1620.33 95.73] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 24345 11295 m 27000 11295 l 27045 11295 l gs col0 s gr 
-% Polyline
-n 24345 9945 m 27090 9945 l gs col0 s gr 
-% Polyline
-60.000 slw
- [90 45 15 45] 0 sd
-n 23220 16245 m 27900 16245 l gs col0 s gr  [] 0 sd
-% Polyline
-30.000 slw
-n 2026 5211 m 2475 5211 l 2475 5659 l 2026 5659 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 7425 3427 m 7875 3427 l 7875 3870 l 7425 3870 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 7425 6120 m 7875 6120 l 7875 6615 l 7425 6615 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
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-% Polyline
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-% Polyline
-n 5176 11061 m 5625 11061 l 5625 11509 l 5176 11509 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 11926 11061 m 12375 11061 l 12375 11509 l 11926 11509 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 12825 5223 m 13275 5223 l 13275 5670 l 12825 5670 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 11025 7476 m 12377 7476 l 12377 8820 l 11025 8820 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 13952 9941 m 15303 9941 l 15303 11284 l 13952 11284 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 16654 10389 m 18003 10389 l 18003 11732 l 16654 11732 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 10125 12831 m 11477 12831 l 11477 14175 l 10125 14175 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 13952 13075 m 15303 13075 l 15303 14418 l 13952 14418 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 16654 16209 m 18003 16209 l 18003 17552 l 16654 17552 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 25470 5718 m 25920 5718 l 25920 6165 l 25470 6165 l cp gs col3 0.75 shd ef gr gs col0 s gr 
-% Polyline
-n 25425 7920 m 25875 7920 l 25875 8368 l 25425 8368 l cp gs col3 0.75 shd ef gr gs col0 s gr 
-% Polyline
-n 12825 2115 m 13275 2115 l 13275 2565 l 12825 2565 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 3374 2325 m 3825 2325 l 3825 8145 l 3374 8145 l cp gs col4 0.95 shd ef gr gs col0 s gr 
-% Polyline
-n 8775 2322 m 9226 2322 l 9226 7695 l 8775 7695 l cp gs col4 0.95 shd ef gr gs col0 s gr 
-% Polyline
-n 8325 9941 m 8776 9941 l 8776 13075 l 8325 13075 l cp gs col4 0.95 shd ef gr gs col0 s gr 
-% Polyline
-n 6525 9916 m 6976 9916 l 6976 13050 l 6525 13050 l cp gs col4 0.95 shd ef gr gs col0 s gr 
-% Polyline
-n 8777 13970 m 9226 13970 l 9226 16209 l 8777 16209 l cp gs col4 0.95 shd ef gr gs col0 s gr 
-% Polyline
-7.500 slw
-n 4726 5256 m 5175 5256 l 5175 5704 l 4726 5704 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 4725 3427 m 5175 3427 l 5175 3870 l 4725 3870 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 16021 2961 m 16470 2961 l 16470 3409 l 16021 3409 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 16020 1177 m 16470 1177 l 16470 1620 l 16020 1620 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-45.000 slw
-n 6750 9931 m 6750 12170 l 6750 13050 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 450.00 662.07] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 8550 9931 m 8550 12170 l 8550 13050 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 570.00 662.07] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19355 14418 m 21964 14418 l 22055 14418 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P17 [8 0 0 -8 1290.33 961.20] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19355 17104 m 21964 17104 l 22055 17104 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P17 [8 0 0 -8 1290.33 1140.27] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-30.000 slw
-n 3375 7920 m 3825 7920 l 3825 8370 l 3375 8370 l cp gs col21 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 20025 13725 m 21375 13725 l 21375 15030 l 20025 15030 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1335.00 915.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 20025 16388 m 21375 16388 l 21375 17730 l 20025 17730 l cp gs /PC [[0.00 1.00 0.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1335.00 1092.53] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 20250 13970 m 21150 13970 l 21150 14850 l 20250 14850 l cp gs col1 0.75 shd ef gr gs col0 s gr 
-% Polyline
-n 2880 7476 m 4232 7476 l 4232 8820 l 2880 8820 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-n 3150 7698 m 4050 7698 l 4050 8595 l 3150 8595 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 210.00 513.20] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-7.500 slw
-n 3375 9720 m 4275 9720 l 4275 10170 l 3375 10170 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-30.000 slw
-n 3825 15975 m 9225 15975 l 9225 16425 l 3825 16425 l cp gs col4 0.25 tnt ef gr gs col0 s gr 
-% Polyline
-45.000 slw
-n 24435 15390 m 24250 15175 l gs col0 s gr 
-% Polyline
-n 24440 15175 m 24255 15390 l gs col0 s gr 
-% Polyline
-n 24435 13140 m 24250 12925 l gs col0 s gr 
-% Polyline
-n 24440 12925 m 24255 13140 l gs col0 s gr 
-% Polyline
-30.000 slw
-n 20250 16657 m 21155 16657 l 21155 17550 l 20250 17550 l cp gs col1 0.75 shd ef gr gs col0 s gr 
-% Polyline
-45.000 slw
-n 27135 15390 m 26950 15175 l gs col0 s gr 
-% Polyline
-n 27140 15175 m 26955 15390 l gs col0 s gr 
-% Polyline
-n 27135 13140 m 26950 12925 l gs col0 s gr 
-% Polyline
-n 27140 12925 m 26955 13140 l gs col0 s gr 
-% Polyline
-7.500 slw
-n 19355 9493 m 21964 9493 l 22055 9493 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1290.33 632.87] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-45.000 slw
-n 24305 3674 m 26916 3674 l 27006 3674 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P17 [8 0 0 -8 1620.33 244.93] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 19355 11732 m 21964 11732 l 22055 11732 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P4 [16 0 0 -16 1290.33 782.13] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 24395 15300 m 27006 15300 l 27096 15300 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P17 [8 0 0 -8 1626.33 1020.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-n 24395 13050 m 27006 13050 l 27096 13050 l gs /PC [[1.00 1.00 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P17 [8 0 0 -8 1626.33 870.00] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-30.000 slw
-n 11250 7698 m 12150 7698 l 12150 8595 l 11250 8595 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 1.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 750.00 513.20] PATmp PATsp ef gr PATusp gs col1 s gr 
-% Polyline
-n 10350 13095 m 11250 13095 l 11250 13992 l 10350 13992 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.69 0.69]] def
-15.00 15.00 sc P5 [16 0 0 -16 690.00 873.00] PATmp PATsp ef gr PATusp gs col16 s gr 
-% Polyline
-45.000 slw
-n 9000 2340 m 9000 7695 l gs col0 s gr 
-% Polyline
-n 3600 2385 m 3600 8145 l gs col0 s gr 
-% Polyline
-30.000 slw
-n 25200 14850 m 26145 14850 l 26145 15750 l 25200 15750 l cp gs col1 0.75 shd ef gr gs col0 s gr 
-% Polyline
-n 25200 12600 m 26100 12600 l 26100 13500 l 25200 13500 l cp gs col1 0.75 shd ef gr gs col0 s gr 
-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
-n 26820 17550 m 27000 17550 l gs col23 0.75 shd ef gr gs col0 s gr 
-% Polyline
-n 3375 7922 m 11927 7922 l 11927 8370 l 3375 8370 l cp gs /PC [[0.00 0.60 1.00] [0.00 0.00 0.00]] def
-15.00 15.00 sc P5 [16 0 0 -16 225.00 528.13] PATmp PATsp ef gr PATusp gs col0 s gr 
-% Polyline
-45.000 slw
-n 27090 11385 m 26905 11170 l gs col0 s gr 
-% Polyline
-n 27095 11170 m 26910 11385 l gs col0 s gr 
-% Polyline
-n 24390 10035 m 24205 9820 l gs col0 s gr 
-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
-n 24390 11385 m 24205 11170 l gs col0 s gr 
-% Polyline
-n 24395 11170 m 24210 11385 l gs col0 s gr 
-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
-n 27090 3780 m 26905 3565 l gs col0 s gr 
-% Polyline
-n 27095 3565 m 26910 3780 l gs col0 s gr 
-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
-n 22095 1080 m 21910 865 l gs col0 s gr 
-% Polyline
-n 22100 865 m 21915 1080 l gs col0 s gr 
-% Polyline
-n 22095 2835 m 21910 2620 l gs col0 s gr 
-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
-n 3690 10035 m 3505 9820 l gs col20 0.75 shd ef gr gs col0 s gr 
-% Polyline
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-% Polyline
-30.000 slw
-n 10927 10035 m 10712 9820 l gs col0 s gr 
-% Polyline
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-% Polyline
-45.000 slw
-n 12240 11385 m 12055 11170 l gs col0 s gr 
-% Polyline
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-% Polyline
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-% Polyline
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-% Polyline
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-105.000 slw
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-105.000 slw
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-clip
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- [60] 0 sd
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- [60] 0 sd
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- [60] 0 sd
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- [60] 0 sd
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- [60] 0 sd
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- [60] 0 sd
-n 11249 17999 m 11249 540 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 6302 17999 m 6302 540 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 6750 17999 m 6750 540 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 7201 17999 m 7201 540 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 7649 17999 m 7649 540 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 8101 17999 m 8101 540 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 8550 17999 m 8550 540 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 3599 17999 m 3599 540 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 4048 17999 m 4048 540 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 4500 17999 m 4500 540 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 4950 17999 m 4950 540 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 5401 17999 m 5401 540 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 5850 17999 m 5850 540 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 17999 m 898 540 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 1349 17999 m 1349 540 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 1800 17999 m 1800 540 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 2249 17999 m 2249 540 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 2699 17999 m 2699 540 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 3148 17999 m 3148 540 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 16207 m 27906 16207 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 16655 m 27906 16655 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 17103 m 27906 17103 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 17551 m 27906 17551 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 17999 m 27906 17999 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 13969 m 27906 13969 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 14417 m 27906 14417 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 14866 m 27906 14866 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 15314 m 27906 15314 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 15761 m 27906 15761 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 11729 m 27906 11729 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 12177 m 27906 12177 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 12625 m 27906 12625 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 13073 m 27906 13073 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 13521 m 27906 13521 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 9491 m 27906 9491 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 9939 m 27906 9939 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 10388 m 27906 10388 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 10835 m 27906 10835 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 11283 m 27906 11283 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 7256 m 27906 7256 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 7704 m 27906 7704 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 8151 m 27906 8151 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 8600 m 27906 8600 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 9048 m 27906 9048 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 5018 m 27906 5018 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 5466 m 27906 5466 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 5914 m 27906 5914 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 6362 m 27906 6362 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 6810 m 27906 6810 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 2778 m 27906 2778 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 3225 m 27906 3225 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 3673 m 27906 3673 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 4122 m 27906 4122 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 4570 m 27906 4570 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 540 m 27906 540 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 988 m 27906 988 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 1436 m 27906 1436 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 1884 m 27906 1884 l gs col0 s gr  [] 0 sd
-% Polyline
- [60] 0 sd
-n 898 2332 m 27906 2332 l gs col0 s gr  [] 0 sd
-% Polyline
-n 15525 15067 m 17458 15067 l 17458 15435 l 15525 15435 l cp gs col7 1.00 shd ef gr gs col0 s gr 
-/Times-Roman-iso ff 360.00 scf sf
-15660 15390 m
-gs 1 -1 sc (YES   4.00 ) col0 sh gr
-% Polyline
-n 13095 15255 m 15345 15255 l 15345 17963 l 13095 17963 l cp gs col7 1.00 shd ef gr gs col0 s gr 
-/Times-Roman-iso ff 510.00 scf sf
-13140 15660 m
-gs 1 -1 sc (Any layers) col0 sh gr
-/Times-Roman-iso ff 510.00 scf sf
-13230 16200 m
-gs 1 -1 sc (Measures) col0 sh gr
-/Times-Roman-iso ff 510.00 scf sf
-13410 16785 m
-gs 1 -1 sc (are only) col0 sh gr
-/Times-Roman-iso ff 510.00 scf sf
-13320 17325 m
-gs 1 -1 sc (taken on) col0 sh gr
-/Times-Roman-iso ff 510.00 scf sf
-13365 17865 m
-gs 1 -1 sc (the axes) col0 sh gr
-% Polyline
-n 19397 1702 m 20295 1702 l 20295 2070 l 19397 2070 l cp gs col7 1.00 shd ef gr gs col0 s gr 
-/Times-Roman-iso ff 360.00 scf sf
-19530 2025 m
-gs 1 -1 sc (3.00) col0 sh gr
-% Polyline
-n 24977 2377 m 25875 2377 l 25875 2745 l 24977 2745 l cp gs col7 1.00 shd ef gr gs col0 s gr 
-/Times-Roman-iso ff 360.00 scf sf
-25110 2700 m
-gs 1 -1 sc (3.00) col0 sh gr
-% Polyline
-n 19577 10432 m 20475 10432 l 20475 10800 l 19577 10800 l cp gs col7 1.00 shd ef gr gs col0 s gr 
-/Times-Roman-iso ff 360.00 scf sf
-19710 10755 m
-gs 1 -1 sc (3.00) col0 sh gr
-% Polyline
-n 27315 3457 m 28080 3457 l 28080 3915 l 27315 3915 l cp gs col7 1.00 shd ef gr gs col0 s gr 
-/Times-Roman-iso ff 360.00 scf sf
-27360 3825 m
-gs 1 -1 sc (2.00) col0 sh gr
-% Polyline
-n 22410 2512 m 23175 2512 l 23175 2970 l 22410 2970 l cp gs col7 1.00 shd ef gr gs col0 s gr 
-/Times-Roman-iso ff 360.00 scf sf
-22500 2835 m
-gs 1 -1 sc (1.00) col0 sh gr
-% Polyline
-n 27405 9622 m 28170 9622 l 28170 10080 l 27405 10080 l cp gs col7 1.00 shd ef gr gs col0 s gr 
-/Times-Roman-iso ff 360.00 scf sf
-27495 9945 m
-gs 1 -1 sc (1.00) col0 sh gr
-% Polyline
-n 15210 4500 m 18090 4500 l 18090 9270 l 15210 9270 l cp gs col7 1.00 shd ef gr gs col0 s gr 
-/Times-Roman-iso ff 510.00 scf sf
-16649 9042 m
-gs 1 -1 sc (identical) dup sw pop 2 div neg 0 rm  col0 sh gr
-/Times-Roman-iso ff 510.00 scf sf
-16649 8481 m
-gs 1 -1 sc (are not) dup sw pop 2 div neg 0 rm  col0 sh gr
-/Times-Roman-iso ff 510.00 scf sf
-16649 7920 m
-gs 1 -1 sc (if VIA) dup sw pop 2 div neg 0 rm  col0 sh gr
-/Times-Roman-iso ff 510.00 scf sf
-16649 7359 m
-gs 1 -1 sc (But No Rule) dup sw pop 2 div neg 0 rm  col0 sh gr
-/Times-Roman-iso ff 300.00 scf sf
-16650 6438 m
-gs 1 -1 sc (Center to center) dup sw pop 2 div neg 0 rm  col0 sh gr
-/Times-Roman-iso ff 510.00 scf sf
-16649 6027 m
-gs 1 -1 sc (VIAS : 4) dup sw pop 2 div neg 0 rm  col0 sh gr
-/Times-Roman-iso ff 510.00 scf sf
-16649 5466 m
-gs 1 -1 sc (Identical) dup sw pop 2 div neg 0 rm  col0 sh gr
-/Times-Roman-iso ff 510.00 scf sf
-16650 4905 m
-gs 1 -1 sc (For all) dup sw pop 2 div neg 0 rm  col0 sh gr
-% Polyline
-30.000 slw
-gs  clippath
-11794 9690 m 11937 9720 l 11794 9750 l 12240 9750 l 12240 9690 l cp
-11201 9750 m 11057 9720 l 11201 9690 l 10755 9690 l 10755 9750 l cp
-clip
-n 10800 9720 m 12195 9720 l gs col7 1.00 shd ef gr gs col0 s gr gr
-
-% arrowhead
-105.000 slw
-n 11201 9750 m 11057 9720 l 11201 9690 l 11177 9720 l 11201 9750 l  cp gs 0.00 setgray ef gr  col0 s
-% arrowhead
-n 11794 9690 m 11937 9720 l 11794 9750 l 11818 9720 l 11794 9690 l  cp gs 0.00 setgray ef gr  col0 s
-% Polyline
-7.500 slw
-n 13365 3007 m 14263 3007 l 14263 3375 l 13365 3375 l cp gs col7 1.00 shd ef gr gs col0 s gr 
-% Polyline
-30.000 slw
-n 9855 11700 m 11340 11700 l 11340 12195 l 9855 12195 l cp gs col7 1.00 shd ef gr gs col0 s gr 
-% Polyline
-n 1935 12195 m 3420 12195 l 3420 12690 l 1935 12690 l cp gs col7 1.00 shd ef gr gs col0 s gr 
-% Polyline
-7.500 slw
-n 3983 12218 m 4881 12218 l 4881 12586 l 3983 12586 l cp gs col7 1.00 shd ef gr gs col0 s gr 
-% Polyline
-n 11003 9149 m 11901 9149 l 11901 9517 l 11003 9517 l cp gs col7 1.00 shd ef gr gs col0 s gr 
-% Polyline
-n 13187 12007 m 15120 12007 l 15120 12375 l 13187 12375 l cp gs col7 1.00 shd ef gr gs col0 s gr 
-% Polyline
-n 15480 12232 m 16875 12232 l 16875 12600 l 15480 12600 l cp gs col7 1.00 shd ef gr gs col0 s gr 
-% Polyline
-n 25875 16642 m 26730 16642 l 26730 17010 l 25875 17010 l cp gs col7 1.00 shd ef gr gs col0 s gr 
-% Polyline
-n 23535 16642 m 24300 16642 l 24300 17010 l 23535 17010 l cp gs col7 1.00 shd ef gr gs col0 s gr 
-% Polyline
-n 24705 13987 m 26910 13987 l 26910 14400 l 24705 14400 l cp gs col7 1.00 shd ef gr gs col0 s gr 
-% Polyline
-n 19710 3412 m 21015 3412 l 21015 3825 l 19710 3825 l cp gs col7 1.00 shd ef gr gs col0 s gr 
-% Polyline
-n 24660 4500 m 26460 4500 l 26460 4950 l 24660 4950 l cp gs col7 1.00 shd ef gr gs col0 s gr 
-% Polyline
-n 24347 10432 m 25245 10432 l 25245 10800 l 24347 10800 l cp gs col7 1.00 shd ef gr gs col0 s gr 
-% Polyline
-n 22320 9307 m 23085 9307 l 23085 9765 l 22320 9765 l cp gs col7 1.00 shd ef gr gs col0 s gr 
-% Polyline
-15.000 slw
-n 4500 1932 m 5985 1932 l 5985 2385 l 4500 2385 l cp gs col7 1.00 shd ef gr gs col0 s gr 
-% Polyline
-30.000 slw
-n 12330 810 m 13680 810 l 13680 1305 l 12330 1305 l cp gs col7 1.00 shd ef gr gs col0 s gr 
-% Polyline
-15.000 slw
-n 2880 6346 m 4364 6346 l 4364 6840 l 2880 6840 l cp gs col7 1.00 shd ef gr gs col0 s gr 
-% Polyline
-7.500 slw
-n 9000 8843 m 9876 8843 l 9876 9225 l 9000 9225 l cp gs col7 1.00 shd ef gr gs col0 s gr 
-% Polyline
-n 19575 12637 m 21915 12637 l 21915 13500 l 19575 13500 l cp gs col7 1.00 shd ef gr gs col0 s gr 
-% Polyline
-n 5582 4402 m 6480 4402 l 6480 4770 l 5582 4770 l cp gs col7 1.00 shd ef gr gs col0 s gr 
-% Polyline
-n 16877 2062 m 17775 2062 l 17775 2430 l 16877 2430 l cp gs col7 1.00 shd ef gr gs col0 s gr 
-/Times-Roman-iso ff 360.00 scf sf
-13500 3330 m
-gs 1 -1 sc (0.50) col0 sh gr
-/Times-Roman-iso ff 360.00 scf sf
-9990 12060 m
-gs 1 -1 sc (N_Trans) col0 sh gr
-/Times-Roman-iso ff 360.00 scf sf
-2070 12555 m
-gs 1 -1 sc (Body P) col0 sh gr
-/Times-Roman-iso ff 360.00 scf sf
-4144 12517 m
-gs 1 -1 sc (1.00) col0 sh gr
-/Times-Roman-iso ff 360.00 scf sf
-11164 9448 m
-gs 1 -1 sc (3.00) col0 sh gr
-/Times-Roman-iso ff 360.00 scf sf
-13275 12330 m
-gs 1 -1 sc (YES   4.00 ) col0 sh gr
-/Times-Roman-iso ff 360.00 scf sf
-15570 12555 m
-gs 1 -1 sc (NO 4.24) col0 sh gr
-/Times-Roman-iso ff 360.00 scf sf
-23625 16965 m
-gs 1 -1 sc (NO) col0 sh gr
-/Times-Roman-iso ff 360.00 scf sf
-25965 16965 m
-gs 1 -1 sc (YES) col0 sh gr
-/Times-Roman-iso ff 360.00 scf sf
-24840 14310 m
-gs 1 -1 sc (POLY WIRE) col0 sh gr
-/Times-Roman-iso ff 360.00 scf sf
-19890 3735 m
-gs 1 -1 sc (ALU 1) col0 sh gr
-/Times-Roman-iso ff 360.00 scf sf
-24705 4860 m
-gs 1 -1 sc (ALU 2,3,4) col0 sh gr
-/Times-Roman-iso ff 360.00 scf sf
-24480 10755 m
-gs 1 -1 sc (2.00) col0 sh gr
-/Times-Roman-iso ff 360.00 scf sf
-22365 9675 m
-gs 1 -1 sc (2.00) col0 sh gr
-/Times-Roman-iso ff 360.00 scf sf
-12420 1170 m
-gs 1 -1 sc (Body N) col0 sh gr
-/Times-Roman-iso ff 375.00 scf sf
-4635 2264 m
-gs 1 -1 sc (NWELL) col0 sh gr
-/Times-Roman-iso ff 375.00 scf sf
-2975 6705 m
-gs 1 -1 sc (P_Trans) col0 sh gr
-/Times-Roman-iso ff 360.00 scf sf
-9139 9142 m
-gs 1 -1 sc (7.50) col0 sh gr
-/Times-Roman-iso ff 360.00 scf sf
-20250 12960 m
-gs 1 -1 sc (DIFF) col0 sh gr
-/Times-Roman-iso ff 360.00 scf sf
-19710 13410 m
-gs 1 -1 sc (SAME WELL) col0 sh gr
-/Times-Roman-iso ff 360.00 scf sf
-5760 4725 m
-gs 1 -1 sc (4.00) col0 sh gr
-/Times-Roman-iso ff 360.00 scf sf
-17010 2385 m
-gs 1 -1 sc (4.00) col0 sh gr
-$F2psEnd
-rs
-end
-showpage
diff --git a/alliance/share/doc/symb_rules/symb_rules.sld b/alliance/share/doc/symb_rules/symb_rules.sld
deleted file mode 100644
index 5f1865ad..00000000
Binary files a/alliance/share/doc/symb_rules/symb_rules.sld and /dev/null differ
diff --git a/alliance/share/etc/Alliance Home Page.url b/alliance/share/etc/Alliance Home Page.url
deleted file mode 100644
index 687fafbb..00000000
--- a/alliance/share/etc/Alliance Home Page.url	
+++ /dev/null
@@ -1,5 +0,0 @@
-[DEFAULT]
-BASEURL=http://www-asim.lip6.fr/alliance/
-[InternetShortcut]
-URL=http://www-asim.lip6.fr/alliance/
-Modified=50A3F1A20C73BF01C5
diff --git a/alliance/share/etc/alc_env.bat.in b/alliance/share/etc/alc_env.bat.in
deleted file mode 100755
index 5a56be7d..00000000
--- a/alliance/share/etc/alc_env.bat.in
+++ /dev/null
@@ -1,80 +0,0 @@
-@ECHO OFF
-REM vim: set filetype=dosbatch:
-REM              ,,,
-REM             (o o)
-REM ###=====oOO--(_)--OOO=========================================####
-REM 
-REM   Alliance CAD system environnement
-REM   Usage (in C-shell) : source alc_env.csh
-REM   (C) 1997 Czo  -- (Olivier.Sirol@lip6.fr)
-REM   $Id: alc_env.bat.in,v 1.3 2001/10/25 09:28:34 czo Exp $
-REM   Generated from alc_env.bat.in on @DATE@
-REM
-REM  $ALLIANCE_OS and %ALLIANCE_TOP% are the only variables you will
-REM  have to modify if something goes wrong
-
-REM  Which platform for Alliance CAD
-REM
-REM  WARNING : if changing this remember to do it on the 3 config files :
-REM  configure.in alc_env.sh.in and alc_env.csh.in
-
-set ALLIANCE_OS=Cygwin
-
-REM  Where t:he Alliance CAD is installed
-
-set ALLIANCE_TOP=@ALLIANCE_TOP@/%ALLIANCE_OS%
-
-REM  User def 
-set MBK_IN_LO=vst
-set MBK_OUT_LO=vst
-set MBK_IN_PH=ap
-set MBK_OUT_PH=ap
-
-set MBK_WORK_LIB=.
-set MBK_CATAL_NAME=CATAL
-
-set MBK_SCALE_X=100
-
-set VH_MAXERR=10
-set VH_BEHSFX=vbe
-set VH_PATSFX=pat
-set VH_DLYSFX=dly
-
-set MBK_CATA_LIB=.:%ALLIANCE_TOP%/cells/sxlib:%ALLIANCE_TOP%/cells/dp_sxlib:%ALLIANCE_TOP%/cells/padlib
-set MBK_TARGET_LIB=%ALLIANCE_TOP%/cells/sxlib
-set MBK_C4_LIB=./cellsC4 
-
-set MBK_VDD=vdd
-set MBK_VSS=vss
-
-set XPAT_PARAM_NAME=%ALLIANCE_TOP%/etc/xpat.par
-set XFSM_PARAM_NAME=%ALLIANCE_TOP%/etc/xfsm.par
-set XSCH_PARAM_NAME=%ALLIANCE_TOP%/etc/xsch.par
-
-set DREAL_TECHNO_NAME=%ALLIANCE_TOP%/etc/cmos_7.dreal
-set GRAAL_TECHNO_NAME=%ALLIANCE_TOP%/etc/cmos_12.graal
-set RDS_TECHNO_NAME=%ALLIANCE_TOP%/etc/cmos_12.rds
-
-set RDS_IN=cif
-set RDS_OUT=cif
-
-set ELP_TECHNO_NAME=%ALLIANCE_TOP%/etc/prol035.elp
-
-REM  Cygwin 
-
-set MAKE_MODE=UNIX
-set DISPLAY=:0
-
-REM  Update PATH and MANPATH 
-
-set MANPATH=%ALLIANCE_TOP%/man;%MANPATH%
-
-REM The path var should be written in dos style here, not unix
-REM You might need to modify this by hand
-REM set PATH=%ALLIANCE_TOP%/bin;%PATH%
-
-set PATH=c:\usr\local\alliance\archi\%ALLIANCE_OS%\bin;%PATH%
-
-
-REM  EOF 
-
diff --git a/alliance/share/etc/alc_env.csh.in b/alliance/share/etc/alc_env.csh.in
deleted file mode 100755
index d011044d..00000000
--- a/alliance/share/etc/alc_env.csh.in
+++ /dev/null
@@ -1,123 +0,0 @@
-# -*- Mode: Shell-script     -*- 
-# -*- vim: set filetype=csh: -*-
-#             ,,,
-#            (o o)
-####=====oOO--(_)--OOO=========================================####
-#
-#  Alliance CAD system environnement
-#  Usage (in C-shell) : > source alc_env.csh
-#  (C) 1997 Czo  -- <Olivier.Sirol@lip6.fr>
-#  $Id: alc_env.csh.in,v 1.14 2001/10/25 09:28:34 czo Exp $
-#  Generated from alc_env.csh.in on @DATE@
-
-# $ALLIANCE_OS and $ALLIANCE_TOP are the only variables you will
-# have to modify if something goes wrong
-
-# Which platform for Alliance CAD
-
-# WARNING : if changing this remember to do it on the 3 config files :
-# configure.in alc_env.sh.in and alc_env.csh.in
-
-switch (`uname`)
- case Linux*:
-  if ( `uname -r` =~ 1.* ) then
-      setenv ALLIANCE_OS Linux_aout
-  else
-   if ( `uname -r` =~ 2.0* ) then
-      setenv ALLIANCE_OS Linux_elf
-   else
-      setenv ALLIANCE_OS Linux
-   endif
-  endif
- breaksw
-
- case SunOS*:
-  if ( `uname -r` =~ 5* ) then
-      setenv ALLIANCE_OS Solaris
-  else
-      setenv ALLIANCE_OS SunOS
-  endif
- breaksw
-
- case FreeBSD*:
-      setenv ALLIANCE_OS FreeBSD
- breaksw
-
- case NetBSD*:
-      setenv ALLIANCE_OS NetBSD
- breaksw
-
- case HP-UX*:
-      setenv ALLIANCE_OS HPUX
- breaksw
-
- case OSF1*:
-      setenv ALLIANCE_OS OSF
- breaksw
-
- case CYGWIN*:
-      setenv ALLIANCE_OS Cygwin
- breaksw
-
-default:
-  setenv ALLIANCE_OS Unknown
- breaksw
-endsw
-
-# Where the Alliance CAD is installed
-
-setenv ALLIANCE_TOP @ALLIANCE_TOP@/$ALLIANCE_OS
-
-# User def 
-
-setenv MBK_IN_LO         vst
-setenv MBK_OUT_LO        vst
-setenv MBK_IN_PH         ap
-setenv MBK_OUT_PH        ap
-
-setenv MBK_WORK_LIB      .
-setenv MBK_CATAL_NAME    CATAL
-
-setenv MBK_SCALE_X 100
-
-setenv VH_MAXERR 10
-setenv VH_BEHSFX vbe
-setenv VH_PATSFX pat
-setenv VH_DLYSFX dly
-
-setenv MBK_CATA_LIB      .:$ALLIANCE_TOP/cells/sxlib:$ALLIANCE_TOP/cells/dp_sxlib:$ALLIANCE_TOP/cells/padlib
-setenv MBK_TARGET_LIB    $ALLIANCE_TOP/cells/sxlib
-setenv MBK_C4_LIB        ./cellsC4 
-
-setenv MBK_VDD           vdd
-setenv MBK_VSS           vss
-
-setenv XPAT_PARAM_NAME   $ALLIANCE_TOP/etc/xpat.par
-setenv XFSM_PARAM_NAME   $ALLIANCE_TOP/etc/xfsm.par
-setenv XSCH_PARAM_NAME   $ALLIANCE_TOP/etc/xsch.par
-
-setenv RDS_IN cif
-setenv RDS_OUT cif
-
-setenv DREAL_TECHNO_NAME   $ALLIANCE_TOP/etc/cmos_7.dreal
-setenv GRAAL_TECHNO_NAME   $ALLIANCE_TOP/etc/cmos_12.graal
-setenv GENVIEW_TECHNO_NAME $ALLIANCE_TOP/etc/cmos_11.genview
-
-setenv RDS_TECHNO_NAME   $ALLIANCE_TOP/etc/cmos_12.rds
-setenv ELP_TECHNO_NAME   $ALLIANCE_TOP/etc/prol035.elp
-
-# Update PATH and MANPATH
-if $?PATH then
- setenv PATH $ALLIANCE_TOP/bin:$PATH
-else
- setenv PATH $ALLIANCE_TOP/bin
-endif
-
-if $?MANPATH then
- setenv MANPATH $ALLIANCE_TOP/man:$MANPATH
-else
- setenv MANPATH $ALLIANCE_TOP/man:/usr/share/man:/usr/man:/usr/local/man:/usr/X11R6/man:/usr/lib/perl5/man
-endif
-
-# EOF 
-
diff --git a/alliance/share/etc/alc_env.sh.in b/alliance/share/etc/alc_env.sh.in
deleted file mode 100755
index 179d9570..00000000
--- a/alliance/share/etc/alc_env.sh.in
+++ /dev/null
@@ -1,119 +0,0 @@
-# -*- Mode: Shell-script    -*- 
-# -*- vim: set filetype=sh: -*-
-#             ,,,
-#            (o o)
-####=====oOO--(_)--OOO=========================================####
-#
-#  Alliance CAD system environnement
-#  Usage (in Bourne-shell) : > . alc_env.sh
-#  (C) 1997 Czo  -- <Olivier.Sirol@lip6.fr>
-#  $Id: alc_env.sh.in,v 1.14 2001/10/25 09:28:34 czo Exp $
-#  Generated from alc_env.sh.in on @DATE@
-
-# $ALLIANCE_OS and $ALLIANCE_TOP are the only variables you will
-# have to modify if something goes wrong
-
-# Which platform for Alliance CAD
-
-# WARNING : if changing this remember to do it on the 3 config files :
-# configure.in alc_env.sh.in and alc_env.csh.in
-
-ALLIANCE_OS=Unknown
- 
-case `uname` in
-
-  Linux*) case `uname -r` in
-           1.*) ALLIANCE_OS=Linux_aout ;;
-          2.0*) ALLIANCE_OS=Linux_elf  ;;            
-             *) ALLIANCE_OS=Linux  ;;
-          esac ;;
-
-  SunOS*) case `uname -r` in
-            5*) ALLIANCE_OS=Solaris ;;
-             *) ALLIANCE_OS=SunOS ;;
-          esac ;;
-
-  FreeBSD*)     ALLIANCE_OS=FreeBSD ;;
-
-  NetBSD*)      ALLIANCE_OS=NetBSD ;;
-
-  HP-UX*)       ALLIANCE_OS=HPUX ;;
-
-  OSF1*)        ALLIANCE_OS=OSF ;;
-
-  CYGWIN*)      ALLIANCE_OS=Cygwin ;;
-
-  *)            ALLIANCE_OS=Unknown ;;
-
-esac
-
-export ALLIANCE_OS
-
-# Where the Alliance CAD is installed
-
- ALLIANCE_TOP=@ALLIANCE_TOP@/$ALLIANCE_OS ;      export ALLIANCE_TOP
-
-# User def 
-
-         MBK_IN_LO=vst;                   export MBK_IN_LO
-        MBK_OUT_LO=vst;                   export MBK_OUT_LO 
-         MBK_IN_PH=ap;                    export MBK_IN_PH
-        MBK_OUT_PH=ap;                    export MBK_OUT_PH
-
-      MBK_WORK_LIB=.;                     export MBK_WORK_LIB
-    MBK_CATAL_NAME=CATAL;                 export MBK_CATAL_NAME
-
-       MBK_SCALE_X=100;                   export MBK_SCALE_X
-
-          VH_MAXERR=10;                   export VH_MAXERR
-         VH_BEHSFX=vbe;                   export VH_BEHSFX
-         VH_PATSFX=pat;                   export VH_PATSFX
-         VH_DLYSFX=dly;                   export VH_DLYSFX
-
-      MBK_CATA_LIB=.:$ALLIANCE_TOP/cells/sxlib:$ALLIANCE_TOP/cells/dp_sxlib:$ALLIANCE_TOP/cells/padlib;    export MBK_CATA_LIB
-    MBK_TARGET_LIB=$ALLIANCE_TOP/cells/sxlib;      export MBK_TARGET_LIB
-        MBK_C4_LIB=./cellsC4;             export MBK_C4_LIB
-
-           MBK_VDD=vdd;                    export MBK_VDD
-           MBK_VSS=vss;                    export MBK_VSS
-
-XPAT_PARAM_NAME=$ALLIANCE_TOP/etc/xpat.par
-export XPAT_PARAM_NAME
-XFSM_PARAM_NAME=$ALLIANCE_TOP/etc/xfsm.par
-export XFSM_PARAM_NAME
-XSCH_PARAM_NAME=$ALLIANCE_TOP/etc/xsch.par
-export XSCH_PARAM_NAME
-
-RDS_IN=cif
-export RDS_IN
-RDS_OUT=cif
-export RDS_OUT
-
-DREAL_TECHNO_NAME=$ALLIANCE_TOP/etc/cmos_7.dreal
-export DREAL_TECHNO_NAME
-GRAAL_TECHNO_NAME=$ALLIANCE_TOP/etc/cmos_12.graal
-export GRAAL_TECHNO_NAME
-GENVIEW_TECHNO_NAME=$ALLIANCE_TOP/etc/cmos_11.genview
-export GENVIEW_TECHNO_NAME
-
-RDS_TECHNO_NAME=$ALLIANCE_TOP/etc/cmos_12.rds
-export RDS_TECHNO_NAME
-ELP_TECHNO_NAME=$ALLIANCE_TOP/etc/prol035.elp
-export ELP_TECHNO_NAME
-
-
-## Update PATH and MANPATH
-#PATH=$HOME/labo/$ALLIANCE_OS/bin:$ALLIANCE_TOP/bin:$PATH
-PATH=$ALLIANCE_TOP/bin:$PATH
-export PATH
-
-if [ "X${MANPATH}Y" != "XY" ]
-then
- MANPATH=$ALLIANCE_TOP/man:$MANPATH
-else
- MANPATH=$ALLIANCE_TOP/man:/usr/share/man:/usr/man:/usr/local/man:/usr/X11R6/man:/usr/lib/perl5/man
-fi
-export MANPATH
-
-# EOF 
-
diff --git a/alliance/share/etc/algue/Dialogue.tcl b/alliance/share/etc/algue/Dialogue.tcl
deleted file mode 100644
index f393bccc..00000000
--- a/alliance/share/etc/algue/Dialogue.tcl
+++ /dev/null
@@ -1,82 +0,0 @@
-proc Dialogue.tcl {w titre texte bitmap defaut args} {
-  
-  # pompe dans  J.K OUSTERHOUT pp 269
-  # La boite de dialogue peut contenir un "texte" avec eventuellement
-  # un  "bitmap" si celui ci est  {} pas de bitmap.
-  # Un des bouton peut etre specifie en en "defaut" (sinon -1).
-  # Dans ce cas il insere dans une frame sunken. La boite attend 
-  # une reponse. Dans ce cas la boite est detruite et retourne l'indice 
-  # du bouton invoque. Sur un retour chariot est avec un "defaut"
-  # specifie, l'indice du defautest retourne 
-
-  global bouton_diag
-  global fontes
-  
-  if {[winfo exists $w]} {destroy $w}
-  #set w $w.dialogue
-  
-  # cree la boite et la divise en deux
-
-  toplevel $w -class Dialog
-  wm title $w $titre
-  wm geometry $w +300+400
-  
-  raise $w  
-
-  
- 
-  frame $w.haut -relief raised -bd 1
-  pack $w.haut -side top -fill both
-  frame $w.bas -relief raised -bd 1
-  pack $w.bas -side bottom -fill both
-
-  # on remplie le haut
-  
-  message $w.haut.msg -width 3i -text $texte \
-            -font $fontes(1)
-  pack $w.haut.msg -side right -expand 1 -fill both \
-     -padx 3m -pady 3m
-  if {$bitmap != ""} {
-   label $w.haut.bitmap -bitmap $bitmap
-   pack $w.haut.bitmap -side left -padx 3m -pady 3m
-  }
-  
-  # cree une ligne de boutons
-  set i 0
-  foreach but $args {
-    button  $w.bas.button$i -text $but -font $fontes(1) -command \
-       "set bouton_diag $i"
-    if {$i == $defaut} {
-      frame $w.bas.defaut -relief sunken -bd 1
-      raise $w.bas.button$i
-      pack $w.bas.defaut -side left -expand 1 \
-           -padx 3m -pady 2m
-      pack $w.bas.button$i -in $w.bas.defaut \
-         -side left -padx 2m -pady 2m -ipadx 2m -ipady 1m
-    } else {
-      pack $w.bas.button$i -side left -expand 1 \
-         -padx 3m -pady 3m -ipadx 2m -ipady 1m
-    }
-    incr i
-  }
-
-  # execute une sortie sur RC  et garde le controle
-  
-  if {$defaut >= 0} {
-   bind $w <Return> "$w.bas.button$defaut flash; \
-    set bouton_diag $defaut"
-  }
-  bell  
-  set oldFocus [focus]
-  #grab set $w
-  focus $w
-
-  # attend une reponse et retourne l'indice du bouton selectionne
-
-  tkwait variable bouton_diag
-  destroy $w
-  focus $oldFocus
-  return $bouton_diag
-  
-  
-}
diff --git a/alliance/share/etc/algue/Supervision_cmdunix.tcl b/alliance/share/etc/algue/Supervision_cmdunix.tcl
deleted file mode 100644
index 0ff1c0fc..00000000
--- a/alliance/share/etc/algue/Supervision_cmdunix.tcl
+++ /dev/null
@@ -1,131 +0,0 @@
-proc Supervision_cmdunix.tcl { commande code_cmd } { 
-
-  # genere une commande unix en tache de fond 
-  # et gere le flot de sortie
-  # adapte du B.B. Welch p 104
-  # si code_cmd est a 1 , on court-circuite la commande
-  # execution . 
-
-            # ---------- procedures internes ------------
-
-    proc Mk_cmdunix { } {
-      # lance la commande et lit le flot de sortie
-      global cmdunix entree blabla bouton 
-       
-      if [catch {open "|$cmdunix |& cat"} entree] {
-        $blabla insert end $entree\n
-      } else {
-        fileevent $entree readable Supervision 
-        $blabla insert end $cmdunix\n
-        $bouton config -state disabled 
-      }
-    }
-    proc Supervision { } {
-      # supervise le flot de sortie
-      global bouton num_process
-      global entree blabla  code_erreur_comdiac
-      if [eof $entree] {
-        # bell ; # bell  
-        Stop_cmdunix 0
-      } else {
-        gets $entree line
-        if [string match *COMDIAC_PID* $line] {
-          set num_process [lrange $line 1 1] 
-          set num_process [expr $num_process-2]
-        }
-        if [string match *COMDIAC_OK* $line] {
-          # bell 
-          Stop_cmdunix 1  
-        }
-        $blabla insert end $line\n
-        $blabla see end
-  
-      }
-    }
-    proc Stop_cmdunix { code } {
-    # arrete et revalide l'execution 
-      global entree bouton code_erreur_comdiac num_process
-      if  { $code == 0 } {
-        bell ;  bell
-        set code_erreur_comdiac 0
-      }
-      if  { $code == 1 } { 
-        set code_erreur_comdiac 1 
-      }
-      if  { $code == -1 } { 
-        exec kill -9 $num_process 
-        bell ;  bell
-        set code_erreur_comdiac 0
-      }
-      catch {close $entree} 
-      $bouton config -state normal   
-    }                    
-
-               #--------------------------------------
-
-   global blabla cmdunix entree bouton
-   global code_erreur_comdiac num_process
-   global fontes
-
-   set num_process 0
-   set cmdunix $commande
-   set w .cmd_unix
-   set poub [winfo exists $w]
-   if {$poub == 1} { 
-     raise $w 
-     if { $code_cmd == 1 } { Mk_cmdunix }
-   }
-   if {$poub == 0} { 
-     toplevel $w -class Cmd_unix
-     wm title  $w "ALGUE : console output"
-     wm iconname $w Supervision
-     wm geometry $w +30+30 
-     raise $w
-
-    # creation de la frame haute
-
-    frame $w.haut -borderwidth 10
-    pack  $w.haut -side top -fill x 
- 
-    # creation des boutons de commande
-    
-    frame $w.haut.1 
-    pack  $w.haut.1 -side right -fill x 
-
-    button $w.haut.1.stop -text STOP -font $fontes(1) \
-      -command "Stop_cmdunix -1"
-     
-    $w.haut.1.stop config -cursor {hand2}
-    set bouton [button $w.haut.1.exec -text EXECUTION -font $fontes(1) -command Mk_cmdunix]
-    $w.haut.1.exec config -cursor {hand2}
-    button $w.haut.1.sortie -text SORTIE -font $fontes(1) -command "destroy .cmd_unix"
-    $w.haut.1.sortie config -cursor {hand2}
-    pack $w.haut.1.sortie $w.haut.1.stop $w.haut.1.exec -side right
-
-  
-    # creation du label
-
-    label $w.haut.label -font $fontes(1) -text "Commande UNIX: " -padx 0
-    entry $w.haut.entree -width 80 -relief sunken -textvariable cmdunix
-    pack $w.haut.label -side left
-    pack $w.haut.entree -side left -fill x -expand true
-    
-    focus $w.haut.entree
-
-    # creation de la frame basse pour scruter l'execution
-
-    frame $w.bas 
-#    set blabla [text $w.bas.text -width 80 -height 5 -font $fontes(1)
-
-    set blabla [text $w.bas.text -width 80 -height 16  \
-      -borderwidth 5 -relief ridge -setgrid true \
-      -yscrollcommand {.cmd_unix.bas.scroll set}] 
-    scrollbar $w.bas.scroll -command {.cmd_unix.bas.text yview}
-    pack  $w.bas.text -side left -fill both -expand true
-    pack  $w.bas.scroll -side right -fill y
-    pack $w.bas -side top -fill both -expand true
-
-    if { $code_cmd == 1 } { Mk_cmdunix }
-  } 
-    
-}
diff --git a/alliance/share/etc/algue/alliance.gif b/alliance/share/etc/algue/alliance.gif
deleted file mode 100644
index 664b8835..00000000
Binary files a/alliance/share/etc/algue/alliance.gif and /dev/null differ
diff --git a/alliance/share/etc/algue/alliance.tk b/alliance/share/etc/algue/alliance.tk
deleted file mode 100644
index 554cea69..00000000
--- a/alliance/share/etc/algue/alliance.tk
+++ /dev/null
@@ -1,955 +0,0 @@
-#! /usr/local/bin/wish
-#
-# ALliance Graphic User Environment
-#
-# Auteur            :  G. POMMIER
-# Date              : 29/03/99
-#
-# Utilise TCL/Tk http://www.scriptics.com/
-#
-# $Id: alliance.tk,v 1.3 1999/09/28 13:52:43 czo Exp $
-#
-        
-  proc Library_UpdateIndex { libdir } {
-    if ![file exists $libdir/tclIndex] {
-	set doit 1
-    } else {
-	set age [file mtime $libdir/tclIndex]
-	set doit 0
-	if {[file mtime $libdir] > $age} {
-	    set doit 1
-	} else {
-	    foreach file [glob $libdir/*.tcl] {
-		if {[file mtime $file] > $age} {
-		    set doit 1
-		    break
-		}
-	    }
-	}
-    }
-    if { $doit } {
-	auto_mkindex $libdir *.tcl
-    }
-  }
- 
-  set alcgraph $env(ALLIANCE_TOP)/etc/algue
-
-  lappend auto_path   $alcgraph
- 
-  Library_UpdateIndex $alcgraph
-
- global fontes
-         set fontes(1) -adobe-helvetica-bold-r-normal-*-12-*-*-*-*-*-*-*
-         set fontes(2) -adobe-helvetica-bold-r-normal-*-10-*-*-*-*-*-*-*
-         set fontes(3) -adobe-helvetica-bold-r-normal-*-34-*-*-*-*-*-*-*
-         set fontes(4) -adobe-helvetica-bold-r-normal-*-8-*-75-*-*-*-*-*
-         set fontes(5) -adobe-helvetica-bold-r-normal-*-24-*-*-*-*-*-*-*
-         set fontes(6) -adobe-helvetica-bold-r-normal-*-20-*-*-*-*-*-*-*
-         set fontes(7) -adobe-helvetica-bold-r-normal-*-16-*-*-*-*-*-*-*
-
-
-        option add *foreground black
-        option add *Button.background #eef
-        option add *Menubutton.background #eef
-        
-        option add *Checkbutton.background #fff
-        option add *Radiobutton.background #fff
-        option add *Frame.background #fff
-        option add *Canvas.background #fff
-        option add *Canvas.background #fff
-        option add *Label.background #fff
-        option add *Toplevel.background #fff
-        option add *Entry.background #fff
-        option add *Scrollbar.background #eef
-        option add *Listbox.background bisque
-        option add *Text.background white
-
-    set w .alliance
-
-    toplevel    $w -class Cairo_otacsrndmos 
-    wm title    $w "A L L I A N C E"
-    raise       $w
-    wm geometry $w  +20+20
-    wm iconify  .
-global currentlang
-set currentlang "francais"
-
-global paramlaunch
-set  paramlaunch(changelang) "Switch to English"
-set  paramlaunch(exit) "SORTIE"
-
-
-
-##################
-# Procedures....
-#
-#
-########################
-#
-
-
-########################
-#
-proc dlg_reset {exec file_conf  } {
-global fontes
-global button_press
-
-
- set win .dgl
- set texte "Voulez-vous vraiment remettre les parametres a leurs valeurs \
- initiales ?"
- 
- toplevel $win -class Dialog
-
- wm title $win "Confirmation"
- wm geometry $win +300+400
- raise $win
-
- frame $win.haut -relief raised -bd 1
- pack  $win.haut -side top -fill both
- frame $win.bas  -relief raised -bd 1
- pack  $win.bas  -side bottom -fill both
-
- message $win.haut.msg -width 3i -text $texte
-
- pack  $win.haut.msg -side right -expand 1 -fill both -padx 3 -pady 3
-
- button $win.bas.1 -text "Oui" -command "set button_press 0" 
- pack   $win.bas.1 -expand 1 -side left -padx 5 -pady 5 -ipadx 3 -ipady 3 
-
- button $win.bas.2 -text "Non" -command "set button_press 1" 
- pack   $win.bas.2 -expand 1  -side left -padx 5 -pady 5 -ipadx 3 -ipady 3 
-
-  tkwait  variable button_press
- destroy $win
-
-return $button_press
-}
-
-
-######
-#
-proc askforshell { } {
-global fontes
-global button_press
-global currentlang
-
-  set win .dgl
-switch $currentlang {
- "francais" {
- set texte "A quel shell voulez vous que le script se conforme ?"
- set titlefile "Choix du shell"
- }
-
- "anglais" {
- set texte "Witch Shell do you want to use ?"
- set titlefile "Shell Choose"
- }
- }
-
- toplevel $win -class Dialog
-
- wm title $win "$titlefile"
-
- wm geometry $win +300+400
- raise $win
-
- frame $win.haut -relief raised -bd 1
- pack  $win.haut -side top -fill both
- frame $win.bas  -relief raised -bd 1
- pack  $win.bas  -side bottom -fill both
-
- message $win.haut.msg -width 3i -text $texte
-
- pack  $win.haut.msg -side right -expand 1 -fill both -padx 3 -pady 3
-
- button $win.bas.1 -text "TCSH" -command "set button_press TCSH" 
- pack   $win.bas.1 -expand 1 -side left -padx 5 -pady 5 -ipadx 3 -ipady 3 
-
- button $win.bas.2 -text "BASH" -command "set button_press BASH" 
- pack   $win.bas.2 -expand 1  -side left -padx 5 -pady 5 -ipadx 3 -ipady 3 
-
-set oldfocus [focus]
-
-focus $win
-
-  tkwait  variable button_press
- destroy $win
- focus $oldfocus
-
-return $button_press
-}
-
-########################
-proc dump_env_file { file } {
- global env
- global dir_env_file
-
- 
- if ![file exists $env(PWD)/$file] { 
-  eval "exec cp ${dir_env_file}/${file} ." 
- }
-return 0
-}
-
-
-########################
-proc reset_env_file { file execut } {
- global env
- global dir_env_file
- global  result_dialog
- global liste_variables
-
-set result_dialog [ dlg_reset $execut $file]
-
-if { $result_dialog == 0 } {
- if [file exists $env(PWD)/$file] {
-  eval "exec cp ${dir_env_file}/${file} ." 
-  }
- }
- 
-########
-# on devrait lire les nouvelles valeurs..
-#ABCD
- 
-return $result_dialog
-}
-
-
-#######
-#
-proc config_binaire { executable file_config } { 
- global fontes
- global largeur    
- global entry_val
- global exec_dupfile
- global do_pack
- set exec_dupfile $executable
- global env
-
- global liste_variables
- global dir_env_file
-
-set dir_env_file $env(ALLIANCE_TOP)/etc/algue
-
- global liste_topack
-
- global currentlang
- 
- switch $currentlang {
-  
-   "francais"  {
-	set paramlaunch(title)  "Configuration de l' environnement de "
-	set paramlaunch(var)    "Variable"
-	set paramlaunch(val)    "Valeur"
-	set paramlaunch(cmd)    "Commande"
-	set paramlaunch(launch) "Execution"
-	set paramlaunch(defaut) "Valeurs par defaut"
-	set paramlaunch(save)   "Sauvegarde"
-	set paramlaunch(script) "Genere script"
-	set paramlaunch(exit)   "SORTIE" 
-	
-	}
-	"anglais" {
-	set paramlaunch(title)  "Environnement of "
-	set paramlaunch(var)    "Variable"
-	set paramlaunch(val)    "Value"
-	set paramlaunch(cmd)    "Command"
-	set paramlaunch(launch) "Launch"
-	set paramlaunch(defaut) "Default Values"
-	set paramlaunch(save)   "Save"
-	set paramlaunch(script) "Drive script"
-	set paramlaunch(exit)   "EXIT" 
-
-	}
-}
-  
-
-
-
-
-
- 
-  	toplevel    .config 
-	wm title    .config "Alliance Configurator"
-	wm iconname .config  Config 
-	wm geometry .config +10+10
-	
-   set h_scrol 100
-
-############
-# si executable.env n existe pas dans le repertoire courant on le copie  
-# 
-set exe_env [dump_env_file ${executable}.env]
-
-		
-	frame  .config.top  -relief flat
-	pack   .config.top  -side top -fill both 
-   frame  .config.cmd  -relief flat
-	pack   .config.cmd  -fill both 
-   frame  .config.bot  -relief raised -bd 1 
-	pack   .config.bot  -side bottom -fill both
-	
-   label  .config.top.titre  -font $fontes(6) \
-  -text "$paramlaunch(title) $executable" -foreground #0000CC
-
-	pack   .config.top.titre  -side top -padx 3 -pady 10
-
-   canvas .config.top.canvas  -relief flat -borderwidth 0 -background #fff -width 40 -height 10 \
-          -scrollregion "0 0 0 $h_scrol" -yscrollcommand ".config.top.scrol set"
-  
-
-   scrollbar  .config.top.scrol -width 8 -orient vertical -command ".config.top.canvas  yview" \
-	-width 8
-
-   pack .config.top.scrol  -side right -fill y
-        .config.top.scrol  config -cursor {hand2} 
-   pack .config.top.canvas  -expand yes -side left  -fill both  
-
-
-  if [catch {open $file_config r} fichier] {
-             set pouba "L'erreur est humaine"
-             set poubb "Probleme a l'ouverture du fichier $file_config !!"           
-             Dialogue.tcl .d $pouba $poubb error -1 SORTIE
-           } else {
-              set gocalcul 1
-    global do_pack
-    global liste_topack
-             #bell
-				    set largeur 0
-					 set largeur_maxi 2
-					 set ligne_act 1
-					 set liste_topack ""
-					 set liste_variables ""
-					 set wdtent 35
-					 set wdtlbl 20
-                set topady 5        
-                set topadx 5        
-
-				 frame  .config.top.canvas.titre  -relief raised -bd 1 
-	          pack   .config.top.canvas.titre  -side top -fill both 
-
-             label  .config.top.canvas.titre.col1  -width $wdtlbl -font $fontes(1) \
-				 -text  "$paramlaunch(var)" -fg #CC0000
-         	 label  .config.top.canvas.titre.col2  -width $wdtent -font $fontes(1) \
- 				 -text  "$paramlaunch(val)" -fg #CC0000  
-				 label  .config.top.canvas.titre.col3  -width $wdtlbl -font $fontes(1) \
-				 -text  "$paramlaunch(var)" -fg #CC0000
-             label  .config.top.canvas.titre.col4  -width $wdtent -font $fontes(1) \
-				 -text  "$paramlaunch(val)" -fg #CC0000
-  
-    
-	          pack .config.top.canvas.titre.col1 .config.top.canvas.titre.col2 \
-				 .config.top.canvas.titre.col3 .config.top.canvas.titre.col4  -side left -padx $topadx -pady $topady
-
-             frame  .config.top.canvas.${ligne_act}  -relief raised -bd 1 
-	          pack   .config.top.canvas.${ligne_act}  -side top -fill both 
-				 
-              while {[gets $fichier ligne] >= 0} {
-				    
-						global do_pack			
-
-                set parametre [lrange $ligne 0 0] 
-                set val_parametre  [lrange $ligne 1 1]
-				    set allval_param   [lrange $ligne 1 end] 
-				   	set do_pack 1 
-					   set lengthval [string length $val_parametre ] 	
-						set lengthval [expr $lengthval - 2]
-						set firstval  [string index  $val_parametre 0]
-						set lastval   [string index  $val_parametre $lengthval]
-						
-						if { $firstval == "\{" } { 
-                  set goodval [ string range $val_parametre 1 $lengthval ]
-						set val_parametre $goodval
-						}
-
-switch $parametre {
-
-
- "commande" {  
-	 
-	 switch $currentlang {
-	 "francais" { 
-	      label .config.cmd.lbl -width $wdtlbl -font $fontes(7) \
-    	       -text "commande" -fg #CC0000  
-				  }
-	 "anglais" { 
-	      label .config.cmd.lbl -width $wdtlbl -font $fontes(7) \
-    	       -text "command" -fg #CC0000  
-				  }
-			 }
-
- 
-  set  entry_val(commande) $allval_param
-  
-  lappend liste_variables "commande"
-
-  entry .config.cmd.ent -width $wdtent \
-  -textvariable entry_val(commande) 
-#XXX
-
-button .config.cmd.lance  -font $fontes(7) -fg #0000CC -text "$paramlaunch(launch)" -underline 0 -width 14 -command\
-			 {  
-		
- global exec_dupfile
- global liste_variables
- global entry_val
- global filewrite 
- global shellused
-
-
- 
-set filewrite ${exec_dupfile}.tmpsh
-
-if [catch {open $filewrite w+ } fichier] {
-             set pouba "L'erreur est humaine"
-             set poubb "Probleme a l'ouverture du fichier $filewrite !!"           
-             Dialogue.tcl .d $pouba $poubb error -1 SORTIE
-           } else {
-set ii 0
-
-
-foreach vartowrite $liste_variables {
- incr ii
-  if {$vartowrite == "commande" } { 
-	   puts $fichier "$entry_val($vartowrite)" 
-
-  } else {
-  puts $fichier "$vartowrite=$entry_val($vartowrite)"
-  puts $fichier "export $vartowrite"
-  
-  }
- 
-}
- close $fichier 
-	 
-	 } 
-
-eval "exec chmod 755 $filewrite" 
-
-set comd  "${filewrite}" 
-
-Supervision_cmdunix.tcl $env(PWD)/$comd 1 ;
-
-# puts "$filewrite"
-# set comd2 "rm $filewrite" 
-# Supervision_cmdunix.tcl $comd2 1 ;
-
-# eval "exec rm -rf $filewrite" 
-
- }
-
- pack .config.cmd.lbl .config.cmd.ent .config.cmd.lance -side left -padx $topadx -pady 15
-			 
-			 
-			 } 
-
-	   
-		
-	 default {	
-global liste_topack
-	 
-                if {$largeur < $largeur_maxi} { 
-					     set largeur [expr $largeur + 1]
-
-						  set liste_topack "$liste_topack .config.top.canvas.$ligne_act.$ligne_act${largeur}lbl"
-						  set liste_topack "$liste_topack .config.top.canvas.$ligne_act.$ligne_act${largeur}ent"
-						  
-						  label .config.top.canvas.$ligne_act.$ligne_act${largeur}lbl -width $wdtlbl -font $fontes(1) \
-   						  -text $parametre -bg #DDDDDD -fg #0000CC 
-#						  set  entry_val($ligne_act$largeur) $val_parametre
-						  set  entry_val($parametre) $val_parametre
-
-entry .config.top.canvas.$ligne_act.$ligne_act${largeur}ent -width $wdtent \
-						  -textvariable entry_val($parametre) 
-						  lappend liste_variables $parametre
-						  set do_pack 1
-
-						  } else {
-						  set topack " pack $liste_topack -side left -padx $topadx -pady $topady"
-						  eval $topack
-						    set largeur 1 
-							 set liste_topack ""
-							 incr ligne_act
-                   frame  .config.top.canvas.${ligne_act}  -relief raised -bd 1 
-	                pack   .config.top.canvas.${ligne_act}  -side top -fill both 
-						 
-
-                    set liste_topack "$liste_topack .config.top.canvas.$ligne_act.$ligne_act${largeur}lbl"
-						  set liste_topack "$liste_topack .config.top.canvas.$ligne_act.$ligne_act${largeur}ent"
-						  
-						  label .config.top.canvas.$ligne_act.$ligne_act${largeur}lbl -width $wdtlbl -font $fontes(1) \
-   						  -text $parametre -bg #DDDDDD -fg #0000CC 
-#						  set  entry_val($ligne_act$largeur) $val_parametre
-						  set  entry_val($parametre) $val_parametre
-						  entry .config.top.canvas.$ligne_act.$ligne_act${largeur}ent -width $wdtent \
-						  -textvariable entry_val($parametre) 
-						  lappend liste_variables $parametre
-
-						 
-							 set do_pack 0
-							 } 
-					 
-					 
-                if { $parametre != "*" } { 
-                  if { $parametre == "AD0" } { 
-                    set dim_otacsrndmos(ad0) $val_parametre 
-                  } elseif { $parametre == "VC3" } { 
-                    set dim_otacsrndmos(vc3) [format "%6.3f" $val_parametre]
-                  } elseif { $parametre == "AIRE" } { 
-                    set dim_otacsrndmos(aire)  $val_parametre
-                  }
-                }
-              }
-
-  }
-}
-
-
-					set topack " pack $liste_topack -side left -padx $topadx -pady $topady"
-
-#   if { $do_pack == 1 } {
-  eval $topack
-#  }
-				  
-              close $fichier
-
-	 }
-				  
-####################
-# Bouttons du bas  
- 
-  button .config.bot.reset  -font $fontes(1) -text "$paramlaunch(defaut)" -underline 0 -width 14 -command\
-			 { } 
-
-  button .config.bot.save   -font $fontes(1) -text "$paramlaunch(save)" -underline 0 -width 14  -command\
-			 {} 
- 
-  button .config.bot.lance  -font $fontes(1) -text "$paramlaunch(script)" -underline 0 -width 14 -command\
-			 {} 
- 
-  button .config.bot.exit   -font $fontes(1) -text "$paramlaunch(exit)" -underline 0 -width 14 -command\
-           "destroy .config"
-
-
-  pack .config.bot.reset .config.bot.save .config.bot.lance .config.bot.exit  -side left -expand 1\
-	    -padx 9 -pady 6 -ipadx 6 -ipady 3  
-
-
-
-bind .config.bot.reset  <1> {
- global exec_dupfile
- global allval_param
- global entry_val
-
- set okresult [ reset_env_file ${exec_dupfile}.env ${exec_dupfile} ]
-
- if { $okresult == 0} {
- #on doit reconfigurer ....
-
-# pack forget .config.bot.reset .config.bot.save    .config.bot.lance  
-# .config.bot.exit   configure -text "Restart !"
-# .config.bot.exit   configure -command "destroy .config ; return 11"
-
- }
-set fich ${exec_dupfile}.env
- 
-  if [catch {open $fich r} fichier] {
-             set pouba "L'erreur est humaine"
-             set poubb "Probleme a l'ouverture du fichier $file_config !!"           
-             Dialogue.tcl .d $pouba $poubb error -1 SORTIE
-           } else {
-              set gocalcul 1
-    global do_pack
-    global liste_topack
-					 set liste_topack ""
-					 set liste_variables ""
-
-              while {[gets $fichier ligne] >= 0} {
-				    
-
-                set parametre [lrange $ligne 0 0] 
-                set val_parametre  [lrange $ligne 1 1]
-				    set allval_param   [lrange $ligne 1 end] 
-
-   set entry_val($parametre) $allval_param 
-
-
-    }
-   }
- }
-
-bind .config.bot.save  <1> {
- global exec_dupfile
- global liste_variables
- global entry_val
- global filewrite 
-    set types_circuit_files {
-      {{ENV Files} {.env}  }
-      {{ALL Files} {*.*}   }
-   }
-
-
-  set filewrite [ tk_getSaveFile -title "ALLIANCE Loader" -filetypes $types_circuit_files -initialdir $env(PWD) -initialfile ${exec_dupfile}.env ]
-
-if {$filewrite != ""} {
-
-if [catch {open $filewrite w} fichier] {
-             set pouba "L'erreur est humaine"
-             set poubb "Probleme a l'ouverture du fichier $filewrite !!"           
-             Dialogue.tcl .d $pouba $poubb error -1 SORTIE
-           } else {
-set ii 0
-
-
-foreach vartowrite $liste_variables {
- incr ii
-  if {$vartowrite == "commande" } { 
-  puts $fichier "$vartowrite    $entry_val($vartowrite)"
-  } else {
-  puts $fichier "$vartowrite    $entry_val($vartowrite)"
-  }
- 
-}
- close $fichier 
-	 
-	 } 
- }
-
-}
-
-bind .config.bot.lance  <1> {
- global exec_dupfile
- global liste_variables
- global entry_val
- global filewrite 
- global shellused
- 
-    set types_circuit_files {
-      {{Script Files} {.sh}  }
-      {{ALL Files} {*.*}   }
-   }
-
-set shellused [askforshell]
-
-
-  set filewrite [ tk_getSaveFile -title "ALLIANCE Loader" -filetypes $types_circuit_files -initialdir $env(PWD) -initialfile ${exec_dupfile}.sh ]
-if {$filewrite != ""} {
-  #ABC
-
-if [catch {open $filewrite w} fichier] {
-             set pouba "L'erreur est humaine"
-             set poubb "Probleme a l'ouverture du fichier $filewrite !!"           
-             Dialogue.tcl .d $pouba $poubb error -1 SORTIE
-           } else {
-set ii 0
-
-  if { $shellused == "TCSH" } {
-  puts $fichier "#!/bin/csh"
-  }
-  if { $shellused == "BASH" } {
-  puts $fichier "#!/bin/sh"
-  }
-
-foreach vartowrite $liste_variables {
- incr ii
-  if {$vartowrite == "commande" } { 
-	   puts $fichier "$entry_val($vartowrite)" 
-
-  } else {
-  if { $shellused == "TCSH" } {
-  puts $fichier "setenv $vartowrite   $entry_val($vartowrite)"
-  }
-  if { $shellused == "BASH" } {
-  puts $fichier "$vartowrite=$entry_val($vartowrite)"
-  puts $fichier "export $vartowrite"
-  }
-  
-  }
- 
-}
-
-eval "exec chmod 755 $filewrite"
-
- close $fichier 
-	 
-	 } 
-
- }
-
-}
-
-
-
-}
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-###################
-# FRAME DU HAUT     
-###################
-   set widthcanvastitre    700
-	set heigthcanvastitre   80
-
-     frame $w.haut -relief raised -bd 1
-     pack  $w.haut -side top -fill both
-    
-     frame $w.haut.1 -relief ridge -bd 3
-     pack  $w.haut.1 -side top  -anchor w -fill both
-
-    canvas $w.haut.1.c -relief flat -borderwidth 0 -background #fff \
-  	 -width $widthcanvastitre -height $heigthcanvastitre \
- 
-     pack $w.haut.1.c   -expand true -side left  -fill both  
-     
-	  set chemin $env(ALLIANCE_TOP)/etc/algue/asim.gif
-     set imh [image create photo -file $chemin]
- 
-	  $w.haut.1.c create image  70 40 -image $imh
-
-     set chemin $env(ALLIANCE_TOP)/etc/algue/alliance.gif
-     set imh [image create photo -file $chemin]
- 
-	  $w.haut.1.c create image  370 40 -image $imh
-
-     set chemin $env(ALLIANCE_TOP)/etc/algue/lip6.gif
-     set imh [image create photo -file $chemin]
- 
-	  $w.haut.1.c create image  660 40 -image $imh
-
-
-###################
-# FRAME      
-###################
-
-   frame  $w.princ  -relief raised -bd 1 
-   pack   $w.princ  -fill both
- 	frame  $w.princ.1  -relief ridge -bd 3 
-   pack   $w.princ.1  -fill both
-
-   set widthcanvas    720
-	set heigthcanvas   410
-	
-   set widthboutton    100
-	set heigthboutton   40
-
-	set widthlabel     580
-	set heigthlabel     40
-
-	set h_scrol        200
-   
-	set color_boutton #AA0000  
-	set color_label   #0000CC
-	
-	set y1 50;
-   set defautx1 55;
-   set x1	$defautx1
-	
-	set file_config "$env(ALLIANCE_TOP)/etc/algue/main.cfg"
-	
- 
-   canvas $w.princ.1.c -relief flat -borderwidth 0 -background #fff \
-	-width $widthcanvas -height $heigthcanvas \
-	-scrollregion "0 0 0 $h_scrol" -yscrollcommand  "$w.princ.1.scl set" 
-
-   scrollbar $w.princ.1.scl  -width 8 -orient vertical -command "$w.princ.1.c  yview "
-        
-   pack $w.princ.1.scl -side right -fill y
-        $w.princ.1.scl config -cursor {hand2}
-		  
-   pack $w.princ.1.c   -expand true -side left  -fill both  
-
-###########################
-# Debut du parssage
-# du fichier de config
-
- if [catch {open $file_config r} fichier] {
-             set mesg1 "L'erreur est humaine"
-             set mesg2 "Probleme a l'ouverture du fichier $file_config !"           
-             Dialogue.tcl .d $mesg1 $mesg2 error -1 SORTIE
-           } else {
-
-  set num 0
- 
-   	
-	while {[gets $fichier ligne] >= 0} {
-
-      incr num
-                
-			set parametre [lrange $ligne 0 0] 
-         set val_parametre  [lrange $ligne 1 1]
-	      set allval_param   [lrange $ligne 1 end] 
-		
-		   set lengthval [string length $val_parametre ] 
-
-			
-
-## On force la taille du texte ....
-  set allval_param [ string range $allval_param 0 70 ]
-
-    label  $w.princ.1.lbl$num -font $fontes(1) \
-    -text $allval_param -anchor w -foreground $color_label  -font $fontes(7) -width 60 
-
-
-   set paramsend [string tolower $parametre]
-
-	 button $w.princ.1.bout$num   -font $fontes(7) \
-       -text $parametre -command  "config_binaire $paramsend ${paramsend}.env" \
-		 -foreground $color_boutton
-
-	 pack $w.princ.1.lbl$num $w.princ.1.bout$num -side left  -expand 1 -padx 5 -pady 5 -ipadx 3 -ipady 3	 
-    $w.princ.1.c create window $x1 $y1  -window $w.princ.1.bout$num  \
-    -width $widthboutton  -height $heigthboutton 
-
-   set x1 [expr $x1 + 360 ] ;
-	 $w.princ.1.c create window $x1 $y1  -window $w.princ.1.lbl$num  \
-    -width $widthlabel -height $heigthlabel 
-	 
-	set y1 [expr $y1 + 55]
-	set x1 $defautx1
-  }
-
-  
- }
-
-   set h_scrol  $y1 
-	$w.princ.1.c configure -scrollregion "0 0 0 $h_scrol" 
-
-###################
-# FRAME BAS
-###################
-
-###
-# Debut reconfiguration language
-proc switchlang { } {
-global fontes color_label
-global currentlang
-global paramlaunch
-global w env
-	
-global  widthboutton  heigthboutton 
-global  widthlabel  heigthlabel  
-
-  switch $currentlang {
-  "francais" {
-  set currentlang "anglais"
-  set paramlaunch(changelang) "Passer en Francais"
-  set  paramlaunch(exit) "EXIT"
-  $w.bot.switch configure -text $paramlaunch(changelang) 
-  $w.bot.quit configure -text $paramlaunch(exit) 
-  set file_to_read $env(ALLIANCE_TOP)/etc/algue/maine.cfg
-  }
-  "anglais" {
-  set currentlang "francais"
-  set paramlaunch(changelang) "Switch to English"
-  set  paramlaunch(exit) "SORTIE"
-  $w.bot.switch configure -text $paramlaunch(changelang) 
-  $w.bot.quit configure -text $paramlaunch(exit) 
-  set file_to_read  $env(ALLIANCE_TOP)/etc/algue/main.cfg
-    } 
-  }
-
-#XXX
-#on efface tout le canvas
-
-    $w.princ.1.c delete all
-###########################
-
-# Debut du parssage
-# du fichier de config
-	
-	set y1 50;
-   set defautx1 55;
-   set x1	$defautx1
-
-	set file_config "$env(ALLIANCE_TOP)/etc/algue/main.cfg"
-	
- if [catch {open $file_to_read r} fichier] {
-             set mesg1 "L'erreur est humaine"
-             set mesg2 "Probleme a l'ouverture du fichier $file_config !"           
-             Dialogue.tcl .d $mesg1 $mesg2 error -1 SORTIE
-           } else {
-
-  set num 0
-   	
-	while {[gets $fichier ligne] >= 0} {
-
-      incr num
-                
-			set parametre [lrange $ligne 0 0] 
-         set val_parametre  [lrange $ligne 1 1]
-	      set allval_param   [lrange $ligne 1 end] 
-		
-		   set lengthval [string length $val_parametre ] 
-
-## On force la taille du texte ....
-  set allval_param [ string range $allval_param 0 70 ]
-
-  #  label  $w.princ.1.lbl$num -font $fontes(1) \
-  #  -text $allval_param -anchor w -foreground $color_label  -font $fontes(7) -width 60 
-     $w.princ.1.lbl$num configure -text $allval_param 
-
-
-
-#   set paramsend [string tolower $parametre]
-
-#	 button $w.princ.1.bout$num   -font $fontes(7) \
-#		 -text $parametre -command  "config_binaire $paramsend ${paramsend}.env" \
-#		 -foreground $color_boutton
-
-#	 pack $w.princ.1.lbl$num $w.princ.1.bout$num -side left  -expand 1 -padx 5 -pady 5 -ipadx 3 -ipady 3	 
-
-	 $w.princ.1.c create window $x1 $y1  -window $w.princ.1.bout$num  \
-    -width $widthboutton  -height $heigthboutton 
-
-   set x1 [expr $x1 + 360 ] ;
-
-	 $w.princ.1.c create window $x1 $y1  -window $w.princ.1.lbl$num  \
-    -width $widthlabel -height $heigthlabel 
-	 
-	set y1 [expr $y1 + 55]
-   set x1 $defautx1
-  }
-}
-
-	 
-}
-
-#fin procedure switchlang 
-# reconfiguration du language
-####################################3
-
-
-
-    frame  $w.bot  -relief raised -bd 1 
-	 pack   $w.bot  -side bottom -fill both
-
-    button $w.bot.quit  -font $fontes(1) -text "$paramlaunch(exit)" \
-          -command "destroy $w ; exit" -width 15
-			 
-    button $w.bot.switch  -font $fontes(1) -text "$paramlaunch(changelang)" \
-	 -command { switchlang } -width 15
-
-			 
-    pack  $w.bot.quit $w.bot.switch -side left -expand 1 -padx 9 -pady 6 -ipadx 6 -ipady 3 
-	 
-     $w.bot.quit  config -cursor {hand2}
-
-    raise       $w
diff --git a/alliance/share/etc/algue/asim.gif b/alliance/share/etc/algue/asim.gif
deleted file mode 100644
index feecbfc2..00000000
Binary files a/alliance/share/etc/algue/asim.gif and /dev/null differ
diff --git a/alliance/share/etc/algue/asimut.env b/alliance/share/etc/algue/asimut.env
deleted file mode 100644
index b3355772..00000000
--- a/alliance/share/etc/algue/asimut.env
+++ /dev/null
@@ -1,16 +0,0 @@
-ALLIANCE_TOP    /asim/alliance
-FPLIB    ${ALLIANCE_TOP}/cells/fplib
-RSALIB    ${ALLIANCE_TOP}/cells/rsa
-SCLIB    ${ALLIANCE_TOP}/cells/sclib
-PADLIB    ${ALLIANCE_TOP}/cells/padlib
-DPLIB    ${ALLIANCE_TOP}/cells/dplib
-BSGLIB    ${ALLIANCE_TOP}/cells/bsg
-RFGLIB    ${ALLIANCE_TOP}/cells/rfg
-MBK_IN_LO    vst
-MBK_WORK_LIB .    
-VH_PATSFX pat
-VH_MAXERR 10
-VH_BEHSFX vbe
-VH_DLYSFX dly
-MBK_CATA_LIB    ${FPLIB}:${RSALIB}:${SCLIB}:${PADLIB}:${DPLIB}:${BSGLIB}:${RFGLIB}
-commande    asimut
diff --git a/alliance/share/etc/algue/bbr.env b/alliance/share/etc/algue/bbr.env
deleted file mode 100644
index dddcc76b..00000000
--- a/alliance/share/etc/algue/bbr.env
+++ /dev/null
@@ -1,14 +0,0 @@
-ALLIANCE_TOP    /asim/alliance
-FPLIB    ${ALLIANCE_TOP}/cells/fplib
-RSALIB    ${ALLIANCE_TOP}/cells/rsa
-SCLIB    ${ALLIANCE_TOP}/cells/sclib
-PADLIB    ${ALLIANCE_TOP}/cells/padlib
-DPLIB    ${ALLIANCE_TOP}/cells/dplib
-BSGLIB    ${ALLIANCE_TOP}/cells/bsg
-RFGLIB    ${ALLIANCE_TOP}/cells/rfg
-MBK_WORK_LIB .
-MBK_IN_LO    vst
-MBK_IN_PH    ap
-MBK_OUT_PH    ap
-MBK_CATA_LIB    ${FPLIB}:${RSALIB}:${SCLIB}:${PADLIB}:${DPLIB}:${BSGLIB}:${RFGLIB}
-commande    bbr 
diff --git a/alliance/share/etc/algue/bop.env b/alliance/share/etc/algue/bop.env
deleted file mode 100644
index ff4acf94..00000000
--- a/alliance/share/etc/algue/bop.env
+++ /dev/null
@@ -1,16 +0,0 @@
-ALLIANCE_TOP    /asim/alliance
-FPLIB    ${ALLIANCE_TOP}/cells/fplib
-RSALIB    ${ALLIANCE_TOP}/cells/rsa
-SCLIB    ${ALLIANCE_TOP}/cells/sclib
-PADLIB    ${ALLIANCE_TOP}/cells/padlib
-DPLIB    ${ALLIANCE_TOP}/cells/dplib
-BSGLIB    ${ALLIANCE_TOP}/cells/bsg
-RFGLIB    ${ALLIANCE_TOP}/cells/rfg
-MBK_WORK_LIB    . 
-MBK_IN_LO    vst
-MBK_OUT_LO    al
-MBK_IN_PH    ap
-MBK_OUT_PH    ap
-MBK_CATA_LIB    ${FPLIB}:${RSALIB}:${SCLIB}:${PADLIB}:${DPLIB}:${BSGLIB}:${RFGLIB}
-commande    bop
-
diff --git a/alliance/share/etc/algue/bsg.env b/alliance/share/etc/algue/bsg.env
deleted file mode 100644
index 760f7e29..00000000
--- a/alliance/share/etc/algue/bsg.env
+++ /dev/null
@@ -1,17 +0,0 @@
-ALLIANCE_TOP    /asim/alliance
-FPLIB    ${ALLIANCE_TOP}/cells/fplib
-RSALIB    ${ALLIANCE_TOP}/cells/rsa
-SCLIB    ${ALLIANCE_TOP}/cells/sclib
-PADLIB    ${ALLIANCE_TOP}/cells/padlib
-DPLIB    ${ALLIANCE_TOP}/cells/dplib
-BSGLIB    ${ALLIANCE_TOP}/cells/bsg
-RFGLIB    ${ALLIANCE_TOP}/cells/rfg
-GROGLIB    ${ALLIANCE_TOP}/cells/grog
-MBK_WORK_LIB .
-MBK_IN_LO    vst
-MBK_OUT_LO    al
-MBK_IN_PH    ap
-MBK_OUT_PH    ap
-ICON_OUT 
-MBK_CATA_LIB    ${FPLIB}:${RSALIB}:${SCLIB}:${PADLIB}:${DPLIB}:${BSGLIB}:${RFGLIB}:${GROGLIB}
-commande    bsg
diff --git a/alliance/share/etc/algue/dpr.env b/alliance/share/etc/algue/dpr.env
deleted file mode 100644
index a11fc5b6..00000000
--- a/alliance/share/etc/algue/dpr.env
+++ /dev/null
@@ -1,15 +0,0 @@
-ALLIANCE_TOP    /asim/alliance
-FPLIB    ${ALLIANCE_TOP}/cells/fplib
-RSALIB    ${ALLIANCE_TOP}/cells/rsa
-SCLIB    ${ALLIANCE_TOP}/cells/sclib
-PADLIB    ${ALLIANCE_TOP}/cells/padlib
-DPLIB    ${ALLIANCE_TOP}/cells/dplib
-BSGLIB    ${ALLIANCE_TOP}/cells/bsg
-RFGLIB    ${ALLIANCE_TOP}/cells/rfg
-MBK_WORK_LIB .
-MBK_IN_LO    vst
-MBK_OUT_LO    al
-MBK_IN_PH    ap
-MBK_OUT_PH    ap
-MBK_CATA_LIB    ${FPLIB}:${RSALIB}:${SCLIB}:${PADLIB}:${DPLIB}:${BSGLIB}:${RFGLIB}
-commande    dpr 
diff --git a/alliance/share/etc/algue/dreal.env b/alliance/share/etc/algue/dreal.env
deleted file mode 100644
index 83f2f9a7..00000000
--- a/alliance/share/etc/algue/dreal.env
+++ /dev/null
@@ -1,18 +0,0 @@
-ALLIANCE_TOP    /asim/alliance
-FPLIB    ${ALLIANCE_TOP}/cells/fplib
-RSALIB    ${ALLIANCE_TOP}/cells/rsa
-SCLIB    ${ALLIANCE_TOP}/cells/sclib
-PADLIB    ${ALLIANCE_TOP}/cells/padlib
-DPLIB    ${ALLIANCE_TOP}/cells/dplib
-BSGLIB    ${ALLIANCE_TOP}/cells/bsg
-RFGLIB    ${ALLIANCE_TOP}/cells/rfg
-MBK_WORK_LIB .
-MBK_IN_LO    vst
-RDS_IN file format for cells
-RDS_TECHNO_NAME
-DREAL_TECHNO_NAME
-MBK_OUT_LO    al
-MBK_IN_PH    ap
-MBK_OUT_PH    ap
-MBK_CATA_LIB    ${FPLIB}:${RSALIB}:${SCLIB}:${PADLIB}:${DPLIB}:${BSGLIB}:${RFGLIB}
-commande    dreal
diff --git a/alliance/share/etc/algue/druc.env b/alliance/share/etc/algue/druc.env
deleted file mode 100644
index 3d6d22b0..00000000
--- a/alliance/share/etc/algue/druc.env
+++ /dev/null
@@ -1,17 +0,0 @@
-ALLIANCE_TOP    /asim/alliance
-FPLIB    ${ALLIANCE_TOP}/cells/fplib
-RSALIB    ${ALLIANCE_TOP}/cells/rsa
-SCLIB    ${ALLIANCE_TOP}/cells/sclib
-PADLIB    ${ALLIANCE_TOP}/cells/padlib
-DPLIB    ${ALLIANCE_TOP}/cells/dplib
-BSGLIB    ${ALLIANCE_TOP}/cells/bsg
-RFGLIB    ${ALLIANCE_TOP}/cells/rfg
-RDS_OUT_PH
-RDS_TECHNO_NAME
-MBK_WORK_LIB .
-MBK_IN_LO    vst
-MBK_OUT_LO    al
-MBK_IN_PH    ap
-MBK_OUT_PH    ap
-MBK_CATA_LIB    ${FPLIB}:${RSALIB}:${SCLIB}:${PADLIB}:${DPLIB}:${BSGLIB}:${RFGLIB}
-commande    druc 
diff --git a/alliance/share/etc/algue/fpgen.env b/alliance/share/etc/algue/fpgen.env
deleted file mode 100644
index f734c28b..00000000
--- a/alliance/share/etc/algue/fpgen.env
+++ /dev/null
@@ -1,16 +0,0 @@
-ALLIANCE_TOP    /asim/alliance
-FPLIB    ${ALLIANCE_TOP}/cells/fplib
-RSALIB    ${ALLIANCE_TOP}/cells/rsa
-SCLIB    ${ALLIANCE_TOP}/cells/sclib
-PADLIB    ${ALLIANCE_TOP}/cells/padlib
-DPLIB    ${ALLIANCE_TOP}/cells/dplib
-BSGLIB    ${ALLIANCE_TOP}/cells/bsg
-RFGLIB    ${ALLIANCE_TOP}/cells/rfg
-FPGEN_LIB
-MBK_WORK_LIB .
-MBK_IN_LO    vst
-MBK_OUT_LO    al
-MBK_IN_PH    ap
-MBK_OUT_PH    ap
-MBK_CATA_LIB    ${FPLIB}:${RSALIB}:${SCLIB}:${PADLIB}:${DPLIB}:${BSGLIB}:${RFGLIB}
-commande    fpgen 
diff --git a/alliance/share/etc/algue/fpmap.env b/alliance/share/etc/algue/fpmap.env
deleted file mode 100644
index 1e3da9f2..00000000
--- a/alliance/share/etc/algue/fpmap.env
+++ /dev/null
@@ -1,15 +0,0 @@
-ALLIANCE_TOP    /asim/alliance
-FPLIB    ${ALLIANCE_TOP}/cells/fplib
-RSALIB    ${ALLIANCE_TOP}/cells/rsa
-SCLIB    ${ALLIANCE_TOP}/cells/sclib
-PADLIB    ${ALLIANCE_TOP}/cells/padlib
-DPLIB    ${ALLIANCE_TOP}/cells/dplib
-BSGLIB    ${ALLIANCE_TOP}/cells/bsg
-RFGLIB    ${ALLIANCE_TOP}/cells/rfg
-MBK_WORK_LIB .
-MBK_IN_LO    vst
-MBK_OUT_LO    al
-MBK_IN_PH    ap
-MBK_OUT_PH    ap
-MBK_CATA_LIB    ${FPLIB}:${RSALIB}:${SCLIB}:${PADLIB}:${DPLIB}:${BSGLIB}:${RFGLIB}
-commande    fpmap 
diff --git a/alliance/share/etc/algue/genlib.env b/alliance/share/etc/algue/genlib.env
deleted file mode 100644
index ecb60535..00000000
--- a/alliance/share/etc/algue/genlib.env
+++ /dev/null
@@ -1,15 +0,0 @@
-ALLIANCE_TOP    /asim/alliance
-FPLIB    ${ALLIANCE_TOP}/cells/fplib
-RSALIB    ${ALLIANCE_TOP}/cells/rsa
-SCLIB    ${ALLIANCE_TOP}/cells/sclib
-PADLIB    ${ALLIANCE_TOP}/cells/padlib
-DPLIB    ${ALLIANCE_TOP}/cells/dplib
-BSGLIB    ${ALLIANCE_TOP}/cells/bsg
-RFGLIB    ${ALLIANCE_TOP}/cells/rfg
-MBK_WORK_LIB .
-MBK_IN_LO    vst
-MBK_OUT_LO    al
-MBK_IN_PH    ap
-MBK_OUT_PH    ap
-MBK_CATA_LIB    ${FPLIB}:${RSALIB}:${SCLIB}:${PADLIB}:${DPLIB}:${BSGLIB}:${RFGLIB}
-commande    genlib 
diff --git a/alliance/share/etc/algue/genpat.env b/alliance/share/etc/algue/genpat.env
deleted file mode 100644
index 55e92f14..00000000
--- a/alliance/share/etc/algue/genpat.env
+++ /dev/null
@@ -1,16 +0,0 @@
-ALLIANCE_TOP    /asim/alliance
-FPLIB    ${ALLIANCE_TOP}/cells/fplib
-RSALIB    ${ALLIANCE_TOP}/cells/rsa
-SCLIB    ${ALLIANCE_TOP}/cells/sclib
-PADLIB    ${ALLIANCE_TOP}/cells/padlib
-DPLIB    ${ALLIANCE_TOP}/cells/dplib
-BSGLIB    ${ALLIANCE_TOP}/cells/bsg
-RFGLIB    ${ALLIANCE_TOP}/cells/rfg
-MBK_WORK_LIB .
-VH_PATSFX pat
-MBK_IN_LO    vst
-MBK_OUT_LO    al
-MBK_IN_PH    ap
-MBK_OUT_PH    ap
-MBK_CATA_LIB    ${FPLIB}:${RSALIB}:${SCLIB}:${PADLIB}:${DPLIB}:${BSGLIB}:${RFGLIB}
-commande     genpat 
diff --git a/alliance/share/etc/algue/genview.env b/alliance/share/etc/algue/genview.env
deleted file mode 100644
index 122f003c..00000000
--- a/alliance/share/etc/algue/genview.env
+++ /dev/null
@@ -1,15 +0,0 @@
-ALLIANCE_TOP    /asim/alliance
-FPLIB    ${ALLIANCE_TOP}/cells/fplib
-RSALIB    ${ALLIANCE_TOP}/cells/rsa
-SCLIB    ${ALLIANCE_TOP}/cells/sclib
-PADLIB    ${ALLIANCE_TOP}/cells/padlib
-DPLIB    ${ALLIANCE_TOP}/cells/dplib
-BSGLIB    ${ALLIANCE_TOP}/cells/bsg
-RFGLIB    ${ALLIANCE_TOP}/cells/rfg
-MBK_WORK_LIB .
-MBK_IN_LO    vst
-MBK_OUT_LO    al
-MBK_IN_PH    ap
-MBK_OUT_PH    ap
-MBK_CATA_LIB    ${FPLIB}:${RSALIB}:${SCLIB}:${PADLIB}:${DPLIB}:${BSGLIB}:${RFGLIB}
-commande    genview 
diff --git a/alliance/share/etc/algue/glop.env b/alliance/share/etc/algue/glop.env
deleted file mode 100644
index 400b77fd..00000000
--- a/alliance/share/etc/algue/glop.env
+++ /dev/null
@@ -1,15 +0,0 @@
-ALLIANCE_TOP    /asim/alliance
-FPLIB    ${ALLIANCE_TOP}/cells/fplib
-RSALIB    ${ALLIANCE_TOP}/cells/rsa
-SCLIB    ${ALLIANCE_TOP}/cells/sclib
-PADLIB    ${ALLIANCE_TOP}/cells/padlib
-DPLIB    ${ALLIANCE_TOP}/cells/dplib
-BSGLIB    ${ALLIANCE_TOP}/cells/bsg
-RFGLIB    ${ALLIANCE_TOP}/cells/rfg
-MBK_WORK_LIB .
-MBK_IN_LO    vst
-MBK_OUT_LO    al
-MBK_IN_PH    ap
-MBK_OUT_PH    ap
-MBK_CATA_LIB    ${FPLIB}:${RSALIB}:${SCLIB}:${PADLIB}:${DPLIB}:${BSGLIB}:${RFGLIB}
-commande    glop
diff --git a/alliance/share/etc/algue/graal.env b/alliance/share/etc/algue/graal.env
deleted file mode 100644
index d7ad9622..00000000
--- a/alliance/share/etc/algue/graal.env
+++ /dev/null
@@ -1,15 +0,0 @@
-ALLIANCE_TOP    /asim/alliance
-FPLIB    ${ALLIANCE_TOP}/cells/fplib
-RSALIB    ${ALLIANCE_TOP}/cells/rsa
-SCLIB    ${ALLIANCE_TOP}/cells/sclib
-PADLIB    ${ALLIANCE_TOP}/cells/padlib
-DPLIB    ${ALLIANCE_TOP}/cells/dplib
-BSGLIB    ${ALLIANCE_TOP}/cells/bsg
-RFGLIB    ${ALLIANCE_TOP}/cells/rfg
-MBK_WORK_LIB .
-MBK_IN_LO    vst
-MBK_OUT_LO    al
-MBK_IN_PH    ap
-MBK_OUT_PH    ap
-MBK_CATA_LIB    ${FPLIB}:${RSALIB}:${SCLIB}:${PADLIB}:${DPLIB}:${BSGLIB}:${RFGLIB}
-commande    graal -l
diff --git a/alliance/share/etc/algue/grog.env b/alliance/share/etc/algue/grog.env
deleted file mode 100644
index 3f0080b9..00000000
--- a/alliance/share/etc/algue/grog.env
+++ /dev/null
@@ -1,17 +0,0 @@
-ALLIANCE_TOP    /asim/alliance
-FPLIB    ${ALLIANCE_TOP}/cells/fplib
-RSALIB    ${ALLIANCE_TOP}/cells/rsa
-SCLIB    ${ALLIANCE_TOP}/cells/sclib
-PADLIB    ${ALLIANCE_TOP}/cells/padlib
-DPLIB    ${ALLIANCE_TOP}/cells/dplib
-BSGLIB    ${ALLIANCE_TOP}/cells/bsg
-RFGLIB    ${ALLIANCE_TOP}/cells/rfg
-GROGLIB    ${ALLIANCE_TOP}/cells/grog
-MBK_WORK_LIB .
-MBK_IN_LO    vst
-MBK_OUT_LO    al
-MBK_IN_PH    ap
-MBK_OUT_PH    ap
-ICON_OUT 
-MBK_CATA_LIB    ${FPLIB}:${RSALIB}:${SCLIB}:${PADLIB}:${DPLIB}:${BSGLIB}:${RFGLIB}:${GROGLIB}
-commande    grog
diff --git a/alliance/share/etc/algue/lip6.gif b/alliance/share/etc/algue/lip6.gif
deleted file mode 100644
index 9d4bcbfa..00000000
Binary files a/alliance/share/etc/algue/lip6.gif and /dev/null differ
diff --git a/alliance/share/etc/algue/lvx.env b/alliance/share/etc/algue/lvx.env
deleted file mode 100644
index 1ffedc8c..00000000
--- a/alliance/share/etc/algue/lvx.env
+++ /dev/null
@@ -1,15 +0,0 @@
-ALLIANCE_TOP    /asim/alliance
-FPLIB    ${ALLIANCE_TOP}/cells/fplib
-RSALIB    ${ALLIANCE_TOP}/cells/rsa
-SCLIB    ${ALLIANCE_TOP}/cells/sclib
-PADLIB    ${ALLIANCE_TOP}/cells/padlib
-DPLIB    ${ALLIANCE_TOP}/cells/dplib
-BSGLIB    ${ALLIANCE_TOP}/cells/bsg
-RFGLIB    ${ALLIANCE_TOP}/cells/rfg
-MBK_WORK_LIB .
-MBK_IN_LO    vst
-MBK_OUT_LO    al
-MBK_IN_PH    ap
-MBK_OUT_PH    ap
-MBK_CATA_LIB    ${FPLIB}:${RSALIB}:${SCLIB}:${PADLIB}:${DPLIB}:${BSGLIB}:${RFGLIB}
-commande    lvx 
diff --git a/alliance/share/etc/algue/lynx.env b/alliance/share/etc/algue/lynx.env
deleted file mode 100644
index f7183350..00000000
--- a/alliance/share/etc/algue/lynx.env
+++ /dev/null
@@ -1,16 +0,0 @@
-ALLIANCE_TOP    /asim/alliance
-FPLIB    ${ALLIANCE_TOP}/cells/fplib
-RSALIB    ${ALLIANCE_TOP}/cells/rsa
-SCLIB    ${ALLIANCE_TOP}/cells/sclib
-PADLIB    ${ALLIANCE_TOP}/cells/padlib
-DPLIB    ${ALLIANCE_TOP}/cells/dplib
-BSGLIB    ${ALLIANCE_TOP}/cells/bsg
-RFGLIB    ${ALLIANCE_TOP}/cells/rfg
-RDS_TECHNO_NAME ${ALLIANCE_TOP}/etc/prol05.rds
-MBK_WORK_LIB .
-MBK_IN_LO    vst
-MBK_OUT_LO    al
-MBK_IN_PH    ap
-MBK_OUT_PH    ap
-MBK_CATA_LIB    ${FPLIB}:${RSALIB}:${SCLIB}:${PADLIB}:${DPLIB}:${BSGLIB}:${RFGLIB}
-commande    lynx 
diff --git a/alliance/share/etc/algue/main.cfg b/alliance/share/etc/algue/main.cfg
deleted file mode 100644
index adf13fdd..00000000
--- a/alliance/share/etc/algue/main.cfg
+++ /dev/null
@@ -1,28 +0,0 @@
-ASIMUT Compilateur/Simulateur VHDL
-BBR Routeur Canal
-BOP Optimisation de reseaux Booleen
-BSG Generateur de decaleur
-DPR Routeur de chemin de donnees
-DREAL Visualisation de circuit 
-DRUC Verification des regles de dessins
-FPGEN Compilateur de chemin de donnees
-FPMAP Synthese logique pour circuit FPGA
-GENLIB Langage de description de circuits
-GENPAT Langage de description de stimuli
-GENVIEW Environnement graphique procedural pour genlib
-GLOP Optimisation de netlist
-GRAAL Editeur graphique
-GROG Generateur de PROM parametrable
-LVX Comparaison de netlists 
-LYNX Extracteur de vue structurelle a partir d'une vue physique symbolique 
-PROOF Logiciel de preuve formelle
-RAGE Generateur de Ram
-RFG Generateur de banc de registres
-RING Routeur de plots
-RSA Generateur d'additionneur
-S2R Expansion de dessin symbolique
-SCMAP Logiciel de synthese sur bibliotheque de cellules
-SCR Placement/Routage de cellules precaracterisees
-SYF Synthese d' automates d'etats finis
-TAS Analyse temporelle
-YAGLE Abstraction fonctionelle
diff --git a/alliance/share/etc/algue/maine.cfg b/alliance/share/etc/algue/maine.cfg
deleted file mode 100644
index 2c348631..00000000
--- a/alliance/share/etc/algue/maine.cfg
+++ /dev/null
@@ -1,28 +0,0 @@
-ASIMUT  A simulation tool for VHDL descriptions
-BBR  Channel router 
-BOP  Boolean optimization of a data flow VHDL description 
-BSG Barrel shifter generator
-DPR  Data path router  
-DREAL  Graphic real layout viewer  
-DRUC  Design rules cheker 
-FPGEN  Data path compiler 
-FPMAP  Mapper of a logic description onto FPGA
-GENLIB  Procedurall design language
-GENPAT  Procedural pattern file generator 
-GENVIEW  Genlib graphical source level debugger 
-GLOP  Global optimizer and timing analyser of a gate netlist
-GRAAL Graphic editor
-GROG A generic ROM generator 
-LVX  Netlists comparator 
-LYNX  Hierarchical netlist extractor
-PROOF Formal proof between two behavioural descriptions 
-RAGE Random access memory generator
-RFG register file generator
-RING  Pads ring router 
-RSA Recurrence solver adder generator
-S2R  Process mapping from symbolic layout to physical layout 
-SCMAP  Mapper of a logic description onto a standard cell library
-SCR  A standard cell router
-SYF  Finite state machine synthesizer 
-TAS  A switch level static timing analyser
-YAGLE  Disassembly and functionnal abstraction of circuits 
diff --git a/alliance/share/etc/algue/proof.env b/alliance/share/etc/algue/proof.env
deleted file mode 100644
index 807a9adc..00000000
--- a/alliance/share/etc/algue/proof.env
+++ /dev/null
@@ -1,15 +0,0 @@
-ALLIANCE_TOP    /asim/alliance
-FPLIB    ${ALLIANCE_TOP}/cells/fplib
-RSALIB    ${ALLIANCE_TOP}/cells/rsa
-SCLIB    ${ALLIANCE_TOP}/cells/sclib
-PADLIB    ${ALLIANCE_TOP}/cells/padlib
-DPLIB    ${ALLIANCE_TOP}/cells/dplib
-BSGLIB    ${ALLIANCE_TOP}/cells/bsg
-RFGLIB    ${ALLIANCE_TOP}/cells/rfg
-MBK_WORK_LIB .
-MBK_IN_LO    vst
-MBK_OUT_LO    al
-MBK_IN_PH    ap
-MBK_OUT_PH    ap
-MBK_CATA_LIB    ${FPLIB}:${RSALIB}:${SCLIB}:${PADLIB}:${DPLIB}:${BSGLIB}:${RFGLIB}
-commande    proof 
diff --git a/alliance/share/etc/algue/rage.env b/alliance/share/etc/algue/rage.env
deleted file mode 100644
index 52707dac..00000000
--- a/alliance/share/etc/algue/rage.env
+++ /dev/null
@@ -1,17 +0,0 @@
-ALLIANCE_TOP    /asim/alliance
-FPLIB    ${ALLIANCE_TOP}/cells/fplib
-RSALIB    ${ALLIANCE_TOP}/cells/rsa
-SCLIB    ${ALLIANCE_TOP}/cells/sclib
-PADLIB    ${ALLIANCE_TOP}/cells/padlib
-DPLIB    ${ALLIANCE_TOP}/cells/dplib
-BSGLIB    ${ALLIANCE_TOP}/cells/bsg
-RFGLIB    ${ALLIANCE_TOP}/cells/rfg
-GROGLIB    ${ALLIANCE_TOP}/cells/grog
-MBK_WORK_LIB .
-MBK_IN_LO    vst
-MBK_OUT_LO    al
-MBK_IN_PH    ap
-MBK_OUT_PH    ap
-ICON_OUT 
-MBK_CATA_LIB    ${FPLIB}:${RSALIB}:${SCLIB}:${PADLIB}:${DPLIB}:${BSGLIB}:${RFGLIB}:${GROGLIB}
-commande    rage
diff --git a/alliance/share/etc/algue/rfg.env b/alliance/share/etc/algue/rfg.env
deleted file mode 100644
index 4e4323bc..00000000
--- a/alliance/share/etc/algue/rfg.env
+++ /dev/null
@@ -1,17 +0,0 @@
-ALLIANCE_TOP    /asim/alliance
-FPLIB    ${ALLIANCE_TOP}/cells/fplib
-RSALIB    ${ALLIANCE_TOP}/cells/rsa
-SCLIB    ${ALLIANCE_TOP}/cells/sclib
-PADLIB    ${ALLIANCE_TOP}/cells/padlib
-DPLIB    ${ALLIANCE_TOP}/cells/dplib
-BSGLIB    ${ALLIANCE_TOP}/cells/bsg
-RFGLIB    ${ALLIANCE_TOP}/cells/rfg
-GROGLIB    ${ALLIANCE_TOP}/cells/grog
-MBK_WORK_LIB .
-MBK_IN_LO    vst
-MBK_OUT_LO    al
-MBK_IN_PH    ap
-MBK_OUT_PH    ap
-ICON_OUT 
-MBK_CATA_LIB    ${FPLIB}:${RSALIB}:${SCLIB}:${PADLIB}:${DPLIB}:${BSGLIB}:${RFGLIB}:${GROGLIB}
-commande    rfg
diff --git a/alliance/share/etc/algue/ring.env b/alliance/share/etc/algue/ring.env
deleted file mode 100644
index baeb6629..00000000
--- a/alliance/share/etc/algue/ring.env
+++ /dev/null
@@ -1,16 +0,0 @@
-ALLIANCE_TOP    /asim/alliance
-FPLIB    ${ALLIANCE_TOP}/cells/fplib
-RSALIB    ${ALLIANCE_TOP}/cells/rsa
-SCLIB    ${ALLIANCE_TOP}/cells/sclib
-PADLIB    ${ALLIANCE_TOP}/cells/padlib
-DPLIB    ${ALLIANCE_TOP}/cells/dplib
-BSGLIB    ${ALLIANCE_TOP}/cells/bsg
-RFGLIB    ${ALLIANCE_TOP}/cells/rfg
-MBK_WORK_LIB .
-MBK_CATA_LIB .
-MBK_IN_LO    vst
-MBK_OUT_LO    al
-MBK_IN_PH    ap
-MBK_OUT_PH    ap
-MBK_CATA_LIB    ${FPLIB}:${RSALIB}:${SCLIB}:${PADLIB}:${DPLIB}:${BSGLIB}:${RFGLIB}
-commande    ring 
diff --git a/alliance/share/etc/algue/rsa.env b/alliance/share/etc/algue/rsa.env
deleted file mode 100644
index fdf32345..00000000
--- a/alliance/share/etc/algue/rsa.env
+++ /dev/null
@@ -1,17 +0,0 @@
-ALLIANCE_TOP    /asim/alliance
-FPLIB    ${ALLIANCE_TOP}/cells/fplib
-RSALIB    ${ALLIANCE_TOP}/cells/rsa
-SCLIB    ${ALLIANCE_TOP}/cells/sclib
-PADLIB    ${ALLIANCE_TOP}/cells/padlib
-DPLIB    ${ALLIANCE_TOP}/cells/dplib
-BSGLIB    ${ALLIANCE_TOP}/cells/bsg
-RFGLIB    ${ALLIANCE_TOP}/cells/rfg
-GROGLIB    ${ALLIANCE_TOP}/cells/grog
-MBK_WORK_LIB .
-MBK_IN_LO    vst
-MBK_OUT_LO    al
-MBK_IN_PH    ap
-MBK_OUT_PH    ap
-ICON_OUT 
-MBK_CATA_LIB    ${FPLIB}:${RSALIB}:${SCLIB}:${PADLIB}:${DPLIB}:${BSGLIB}:${RFGLIB}:${GROGLIB}
-commande    rsa
diff --git a/alliance/share/etc/algue/s2r.env b/alliance/share/etc/algue/s2r.env
deleted file mode 100644
index ef149515..00000000
--- a/alliance/share/etc/algue/s2r.env
+++ /dev/null
@@ -1,15 +0,0 @@
-ALLIANCE_TOP /asim/alliance
-MBK_IN_PH ap
-SCLIB    ${ALLIANCE_TOP}/cells/sclib
-PADLIB   ${ALLIANCE_TOP}/cells/padlib
-FPLIB    ${ALLIANCE_TOP}/cells/fplib
-DPLIB    ${ALLIANCE_TOP}/cells/dplib
-RSALIB   ${ALLIANCE_TOP}/cells/rsa
-RFGLIB   ${ALLIANCE_TOP}/cells/rfg
-BSGLIB   ${ALLIANCE_TOP}/cells/bsg
-RDS_IN cif
-RDS_OUT cif
-RDS_TECHNO_NAME ${ALLIANCE_TOP}/etc/cmos_7.rds  
-MBK_WORK_LIB .
-MBK_CATA_LIB ${SCLIB}:${PADLIB}:${FPLIB}:${DPLIB}:${RSALIB}:${RFGLIB}:${BSG}
-commande s2r
diff --git a/alliance/share/etc/algue/scmap.env b/alliance/share/etc/algue/scmap.env
deleted file mode 100644
index 9e5ef6d9..00000000
--- a/alliance/share/etc/algue/scmap.env
+++ /dev/null
@@ -1,17 +0,0 @@
-ALLIANCE_TOP    /asim/alliance
-FPLIB    ${ALLIANCE_TOP}/cells/fplib
-RSALIB    ${ALLIANCE_TOP}/cells/rsa
-SCLIB    ${ALLIANCE_TOP}/cells/sclib
-PADLIB    ${ALLIANCE_TOP}/cells/padlib
-DPLIB    ${ALLIANCE_TOP}/cells/dplib
-BSGLIB    ${ALLIANCE_TOP}/cells/bsg
-RFGLIB    ${ALLIANCE_TOP}/cells/rfg
-MBK_WORK_LIB .
-MBK_TARGET_LIB
-MBK_C4_LIB
-MBK_IN_LO    vst
-MBK_OUT_LO    al
-MBK_IN_PH    ap
-MBK_OUT_PH    ap
-MBK_CATA_LIB    ${FPLIB}:${RSALIB}:${SCLIB}:${PADLIB}:${DPLIB}:${BSGLIB}:${RFGLIB}
-commande    scmap 
diff --git a/alliance/share/etc/algue/scr.env b/alliance/share/etc/algue/scr.env
deleted file mode 100644
index 5799e4ae..00000000
--- a/alliance/share/etc/algue/scr.env
+++ /dev/null
@@ -1,15 +0,0 @@
-ALLIANCE_TOP    /asim/alliance
-FPLIB    ${ALLIANCE_TOP}/cells/fplib
-RSALIB    ${ALLIANCE_TOP}/cells/rsa
-SCLIB    ${ALLIANCE_TOP}/cells/sclib
-PADLIB    ${ALLIANCE_TOP}/cells/padlib
-DPLIB    ${ALLIANCE_TOP}/cells/dplib
-BSGLIB    ${ALLIANCE_TOP}/cells/bsg
-RFGLIB    ${ALLIANCE_TOP}/cells/rfg
-MBK_WORK_LIB .
-MBK_IN_LO    vst
-MBK_OUT_LO    al
-MBK_IN_PH    ap
-MBK_OUT_PH    ap
-MBK_CATA_LIB    ${FPLIB}:${RSALIB}:${SCLIB}:${PADLIB}:${DPLIB}:${BSGLIB}:${RFGLIB}
-commande    scr 
diff --git a/alliance/share/etc/algue/syf.env b/alliance/share/etc/algue/syf.env
deleted file mode 100644
index 881eeb10..00000000
--- a/alliance/share/etc/algue/syf.env
+++ /dev/null
@@ -1,15 +0,0 @@
-ALLIANCE_TOP    /asim/alliance
-FPLIB    ${ALLIANCE_TOP}/cells/fplib
-RSALIB    ${ALLIANCE_TOP}/cells/rsa
-SCLIB    ${ALLIANCE_TOP}/cells/sclib
-PADLIB    ${ALLIANCE_TOP}/cells/padlib
-DPLIB    ${ALLIANCE_TOP}/cells/dplib
-BSGLIB    ${ALLIANCE_TOP}/cells/bsg
-RFGLIB    ${ALLIANCE_TOP}/cells/rfg
-MBK_WORK_LIB .
-MBK_IN_LO    vst
-MBK_OUT_LO    al
-MBK_IN_PH    ap
-MBK_OUT_PH    ap
-MBK_CATA_LIB    ${FPLIB}:${RSALIB}:${SCLIB}:${PADLIB}:${DPLIB}:${BSGLIB}:${RFGLIB}
-commande    syf 
diff --git a/alliance/share/etc/algue/tas.env b/alliance/share/etc/algue/tas.env
deleted file mode 100644
index 01b713a6..00000000
--- a/alliance/share/etc/algue/tas.env
+++ /dev/null
@@ -1,19 +0,0 @@
-ALLIANCE_TOP    /asim/alliance
-FPLIB    ${ALLIANCE_TOP}/cells/fplib
-RSALIB    ${ALLIANCE_TOP}/cells/rsa
-SCLIB    ${ALLIANCE_TOP}/cells/sclib
-PADLIB    ${ALLIANCE_TOP}/cells/padlib
-DPLIB    ${ALLIANCE_TOP}/cells/dplib
-BSGLIB    ${ALLIANCE_TOP}/cells/bsg
-RFGLIB    ${ALLIANCE_TOP}/cells/rfg
-MBK_WORK_LIB .
-MBK_SPI_TN tn
-MBK_SPI_TP tp
-ELP_TECHNO_NAME ${ALLIANCE_TOP}/etc/prol05.elp
-FCL_LIB_NAME FBLIBRARY
-MBK_IN_LO    vst
-MBK_OUT_LO    al
-MBK_IN_PH    ap
-MBK_OUT_PH    ap
-MBK_CATA_LIB    ${FPLIB}:${RSALIB}:${SCLIB}:${PADLIB}:${DPLIB}:${BSGLIB}:${RFGLIB}
-commande    tas 
diff --git a/alliance/share/etc/algue/tclIndex b/alliance/share/etc/algue/tclIndex
deleted file mode 100644
index 3cf903f5..00000000
--- a/alliance/share/etc/algue/tclIndex
+++ /dev/null
@@ -1,10 +0,0 @@
-# Tcl autoload index file, version 2.0
-# This file is generated by the "auto_mkindex" command
-# and sourced to set up indexing information for one or
-# more commands.  Typically each line is a command that
-# sets an element in the auto_index array, where the
-# element name is the name of a command and the value is
-# a script that loads the command.
-
-set auto_index(Dialogue.tcl) [list source [file join $dir Dialogue.tcl]]
-set auto_index(Supervision_cmdunix.tcl) [list source [file join $dir Supervision_cmdunix.tcl]]
diff --git a/alliance/share/etc/algue/yagle.env b/alliance/share/etc/algue/yagle.env
deleted file mode 100644
index f7ba7ead..00000000
--- a/alliance/share/etc/algue/yagle.env
+++ /dev/null
@@ -1,26 +0,0 @@
-ALLIANCE_TOP    /asim/alliance
-FPLIB    ${ALLIANCE_TOP}/cells/fplib
-RSALIB    ${ALLIANCE_TOP}/cells/rsa
-SCLIB    ${ALLIANCE_TOP}/cells/sclib
-PADLIB    ${ALLIANCE_TOP}/cells/padlib
-DPLIB    ${ALLIANCE_TOP}/cells/dplib
-BSGLIB    ${ALLIANCE_TOP}/cells/bsg
-RFGLIB    ${ALLIANCE_TOP}/cells/rfg
-MBK_WORK_LIB .
-CNS_VDDNAME vdd
-CNS_VSSNAME vss
-CNS_GRIDNAME grid
-CNS_SOURCENAME source
-CNS_DRAINNAME drain
-ELP_TECHNO_NAME ${ALLIANCE_TOP}/etc/prol05.elp
-VH_BEHSFX beh
-YAGLE_LANGUAGE F
-YAGLE_STAT_MODE Y
-FCL_LIB_PATH
-FCL_LIB_NAME
-MBK_IN_LO    vst
-MBK_OUT_LO    al
-MBK_IN_PH    ap
-MBK_OUT_PH    ap
-MBK_CATA_LIB    ${FPLIB}:${RSALIB}:${SCLIB}:${PADLIB}:${DPLIB}:${BSGLIB}:${RFGLIB}
-commande    yagle
diff --git a/alliance/share/etc/alliance.ico b/alliance/share/etc/alliance.ico
deleted file mode 100644
index 3e01a788..00000000
Binary files a/alliance/share/etc/alliance.ico and /dev/null differ
diff --git a/alliance/share/etc/alliance_os.mk.in b/alliance/share/etc/alliance_os.mk.in
deleted file mode 100644
index 693496e5..00000000
--- a/alliance/share/etc/alliance_os.mk.in
+++ /dev/null
@@ -1,58 +0,0 @@
-# -*- Mode: Makefile -*-
-#
-####---------------------------------------------------------###
-# description	: Alliance include file for Makefiles
-# architecture	: @HOST@
-# date		: @DATE@
-# file		: @ALLIANCE_OS@.mk
-#
-
-# The variables $ALLIANCE_* are set by
-# alc_env.[c]sh script or libraries.mk
-
-PROGRAM_SUFFIX=@PROGRAM_SUFFIX@
-
-GNU_LIB          = @GNU_LIB_LOC@
-GNU_INCLUDE      = @GNU_INC_LOC@
-
-X11_LIB          = . @X_LIBS@ @X_EXTRA_LIBS@ @X_PRE_LIBS@
-X11_INCLUDE      = . @X_CFLAGS@
-
-MOTIF_LIB        = @MOTIF_LIB_LOC@
-MOTIF_INCLUDE    = @MOTIF_INC_LOC@
-
-XPM_LIB          = @XPM_LIBS_LOC@
-XPM_INCLUDE      = @XPM_CFLAGS_LOC@
-
-SHELL		= @SHELL@
-CSH		= @CSH@
-CP		= @CP@
-CAT		= @CAT@
-MV		= @MV@
-RM		= @RM@
-MKDIR		= @MKDIR@
-FIND		= @FIND@
-SED		= @SED@
-AWK		= @AWK@
-TR		= @TR@
-TOUCH		= @TOUCH@
-STRIP		= @STRIP@
-RANLIB		= @RANLIB@
-
-MAKE             = @MAKE@
-MAKEFLAGS        = @MAKEFLAGS@
-
-CC               = @FULL_CC@
-CFLAGS           = @CFLAGS@ @AUTO_HAS@
-CPPFLAGS         = @CPPFLAGS@
-
-YACC             = @FULL_YACC@
-YACCFLAGS        = @YACCFLAGS@
-
-LEX              = @FULL_LEX@
-LEXFLAGS         = @LEXFLAGS@
-
-AR               = @AR@
-ARFLAGS          = @ARFLAGS@
-
-# EOF
diff --git a/alliance/share/etc/asga_7.dreal b/alliance/share/etc/asga_7.dreal
deleted file mode 100644
index c902044c..00000000
--- a/alliance/share/etc/asga_7.dreal
+++ /dev/null
@@ -1,101 +0,0 @@
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Title      :      Parameters File for Dreal                 |
-# |                                                             |
-# | Technology :              Asga V7                           |
-# |                                                             |
-# | Date       :             02/08/95                           |
-# |                                                             |
-# \------------------------------------------------------------*/
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                   Lower Grid Step in pixel                  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE DREAL_LOWER_GRID_STEP 10
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |               Lower Figure Text Step in pixel               |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE DREAL_LOWER_FIGURE_STEP 0.1
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |              Lower Instance Text Step in pixel              |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE DREAL_LOWER_INSTANCE_STEP 0.1
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |             Lower Connector Text Step in pixel              |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE DREAL_LOWER_CONNECTOR_STEP 0.5
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |               Lower Segment Text Step in pixel              |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE DREAL_LOWER_SEGMENT_STEP 0.7
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |              Lower Reference Text Step in pixel             |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE DREAL_LOWER_REFERENCE_STEP 1.0
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                 Dreal Cursor Color Name                     |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE DREAL_CURSOR_COLOR_NAME  Black
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                 Dreal Cursor Size in pixel                  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE DREAL_CURSOR_SIZE 10
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# | View Layer Panel Button Label, Foreground, Background Color |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE DREAL_RDS_LAYER_NAME
-
-  RDS_NDIF     Ohm     lawn_green        Black
-  RDS_ACTIV    Active  brown             Black
-  RDS_NIMP     Nimp    forest_green      Black
-  RDS_POLY     Gate    red               Black
-  RDS_TPOLY    Tgate   light_pink        Black
-  RDS_CONT     Cont    dark_violet       Black
-  RDS_ALU1     Alu1    royal_blue        Black
-  RDS_TALU1    Talu1   light_steel_blue  Black
-  RDS_VIA1     Via1    deep_sky_blue     Black
-  RDS_ALU2     Alu2    Cyan              Black
-  RDS_TALU2    Talu2   light_cyan        Black
-  RDS_VIA2     Via2    chocolate         Black
-  RDS_ALU3     Alu3    peach_puff        Black
-  RDS_TALU3    Talu3   bisque            Black
-  RDS_VIA3     Via3    snow4             Black
-  RDS_ALU4     Alu4    aquamarine        Black
-  RDS_REF      Ref     coral             Black
-  RDS_ABOX     Abox    pink              Black
-
-END
diff --git a/alliance/share/etc/asga_7.genview b/alliance/share/etc/asga_7.genview
deleted file mode 100644
index 56ab24da..00000000
--- a/alliance/share/etc/asga_7.genview
+++ /dev/null
@@ -1,152 +0,0 @@
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Title      :      Parameters File for Genview               |
-# |                                                             |
-# | Technology :               Asga                             |
-# |                                                             |
-# | Date       :             17.08.95                           |
-# |                                                             |
-# \------------------------------------------------------------*/
-# /*------------------------------------------------------------\
-# |                                                             |
-# |               Genview Peek Bound in lambda                  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GENVIEW_PEEK_BOUND 7
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |  Segment Panel Button Label, Foreground , Background Color  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GENVIEW_SEGMENT_NAME
-
-  NDIF     Ohm    
-  POLY     Gate  
-  ALU1     Alu1 
-  ALU2     Alu2 
-  ALU3     Alu3 
-  TPOLY    Tgate
-  TALU1    Talu1
-  TALU2    Talu2
-  TALU3    Talu3
-  NTRANS   Etrans
-  PTRANS   Dtrans
-  NWELL    Dtrans 
-
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Connector Panel Button Label, Foreground , Background Color |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GENVIEW_CONNECTOR_NAME
-
-  NDIF     Ohm    
-  POLY     Gate  
-  ALU1     Alu1 
-  ALU2     Alu2 
-  ALU3     Alu3
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Reference Panel Button Label, Foreground, Background Color  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GENVIEW_REFERENCE_NAME
-
-  REF_CON  Ref_Con
-  REF_REF  Ref_Ref
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |     Via Panel Button Label, Foreground , Background Color   |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GENVIEW_VIA_NAME
-
-  CONT_DIF_N   Cont_Ohm
-  CONT_POLY    Cont_Gate
-  CONT_VIA     Cont_Via
-  CONT_VIA2    Cont_Via2
-  CONT_VIA3    Cont_Via3
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |   Orient Panel Button Label, Foreground , Background Color  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GENVIEW_ORIENT_NAME 
-
-  NORTH  North
-  SOUTH  South
-  EAST   East
-  WEST   West
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Symmetry Panel Button Label, Foreground , Background Color  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GENVIEW_SYMMETRY_NAME
-
-  NOSYM No_Sym
-  SYM_X Sym_X
-  SYM_Y Sym_Y
-  SYMXY Sym_XY
-  ROT_P Rot_P
-  ROT_M Rot_M
-  SY_RP Sym_RP
-  SY_RM Sym_RM
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# | View Layer Panel Button Label, Foreground, Background Color |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GENVIEW_RDS_LAYER_NAME
-
-  RDS_NDIF     Ohm     lawn_green
-  RDS_ACTIV    Active  brown
-  RDS_NIMP     Nimp    forest_green
-  RDS_POLY     Gate    red
-  RDS_TPOLY    Tgate   light_pink
-  RDS_CONT     Cont    dark_violet
-  RDS_ALU1     Alu1    royal_blue
-  RDS_TALU1    Talu1   light_steel_blue
-  RDS_VIA1     Via1    deep_sky_blue
-  RDS_ALU2     Alu2    Cyan
-  RDS_TALU2    Talu2   light_cyan
-  RDS_VIA2     Via2    chocolate
-  RDS_ALU3     Alu3    peach_puff
-  RDS_TALU3    Talu3   bisque
-  RDS_VIA3     Via3    snow4
-  RDS_ALU4     Alu4    aquamarine
-  RDS_CPAS     Cpas    gray
-  RDS_REF      Ref     coral
-  RDS_USER0    User0   White
-  RDS_USER1    User1   Gray
-  RDS_USER2    User2   Gray
-  RDS_ABOX     Abox    pink
-
-END
diff --git a/alliance/share/etc/asga_7.graal b/alliance/share/etc/asga_7.graal
deleted file mode 100644
index 07db2f1a..00000000
--- a/alliance/share/etc/asga_7.graal
+++ /dev/null
@@ -1,239 +0,0 @@
-# /*---------------------------------------------------------------------------\
-# |                                                                            |
-# | Title      :      Parameter File for Graal : asga_7.graal                  |
-# |                                                                            |
-# | Technology :      Asga (symbolic grid)                                     |
-# |                                                                            |
-# | Date       :      July 02 1995                                             |
-# |                                                                            |
-# \---------------------------------------------------------------------------*/
-# /*---------------------------\
-# |                            |
-# | Graal Peek Bound in lambda |
-# |                            |
-# \---------------------------*/
-
-DEFINE GRAAL_PEEK_BOUND 7
-
-# /*-----------------------------------\
-# |                                    |
-# | Lower Grid Step in pixel by lambda |
-# |                                    |
-# \-----------------------------------*/
-
-DEFINE GRAAL_LOWER_GRID_STEP 10
-
-# /*------------------------------------------\
-# |                                           |
-# | Lower Figure Text Step in pixel by lambda |
-# |                                           |
-# \------------------------------------------*/
-
-DEFINE GRAAL_LOWER_FIGURE_STEP 1
-
-# /*--------------------------------------------\
-# |                                             |
-# | Lower Instance Text Step in pixel by lambda |
-# |                                             |
-# \--------------------------------------------*/
-
-DEFINE GRAAL_LOWER_INSTANCE_STEP 1
-
-# /*---------------------------------------------\
-# |                                              |
-# | Lower Connector Text Step in pixel by lambda |
-# |                                              |
-# \---------------------------------------------*/
-
-DEFINE GRAAL_LOWER_CONNECTOR_STEP 5
-
-# /*-------------------------------------------\
-# |                                            |
-# | Lower Segment Text Step in pixel by lambda |
-# |                                            |
-# \-------------------------------------------*/
-
-DEFINE GRAAL_LOWER_SEGMENT_STEP 7
-
-# /*---------------------------------------------\
-# |                                              |
-# | Lower Reference Text Step in pixel by lambda |
-# |                                              |
-# \---------------------------------------------*/
-
-DEFINE GRAAL_LOWER_REFERENCE_STEP 10
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                 Graal Cursor Color Name                     |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_CURSOR_COLOR_NAME  Black
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                 Graal Cursor Size in pixel                  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_CURSOR_SIZE 10
-
-# /*----------------------------------------------------------------\
-# |                                                                 |
-# | Segment, Panel Button Label, Foreground Color, Background Color |
-# |                                                                 |
-# \----------------------------------------------------------------*/
-
-TABLE GRAAL_SEGMENT_NAME
-
-  NDIF     Ohm    lawn_green       Black
-  POLY     Gate   red              Black
-  ALU1     Alu1   royal_blue       Black
-  ALU2     Alu2   Cyan             Black
-  ALU3     Alu3   peach_puff       Black
-  TPOLY    Tgate  light_pink       Black
-  TALU1    Talu1  light_steel_blue Black
-  TALU2    Talu2  light_cyan       Black
-  TALU3    Talu3  bisque           Black
-
-END
-
-TABLE GRAAL_TRANSISTOR_NAME
-
-  NTRANS   Etrans lawn_green       Black
-  PTRANS   Trans0 yellow           Black
-  NWELL    Dtrans pink             Black
-
-END
-
-# /*------------------------------------------------------------------\
-# |                                                                   |
-# | Connector, Panel Button Label, Foreground Color, Background Color |
-# |                                                                   |
-# \------------------------------------------------------------------*/
-
-TABLE GRAAL_CONNECTOR_NAME
-
-  NDIF     Ohm    lawn_green       Black
-  POLY     Gate   red              Black
-  ALU1     Alu1   royal_blue       Black
-  ALU2     Alu2   Cyan             Black
-  ALU3     Alu3   peach_puff       Black
-
-END
-
-# /*---------------------------------------------\
-# |                                              |
-# | Minimun Length and Width of symbolic Segment |
-# |                                              |
-# \---------------------------------------------*/
-
-TABLE GRAAL_SEGMENT_VALUE
-
-  NDIF     2   1
-  NTRANS   1   6
-  PTRANS   1   6
-  NWELL    1   6
-  POLY     1   1
-  ALU1     1   1
-  ALU2     2   1
-  ALU3     5   1
-  TPOLY    1   1
-  TALU1    1   1
-  TALU2    2   1
-  TALU3    5   1
-
-END
-
-# /*------------------------------------------------------------------\
-# |                                                                   |
-# | Reference, Panel Button Label, Foreground Color, Background Color |
-# |                                                                   |
-# \------------------------------------------------------------------*/
-
-TABLE GRAAL_REFERENCE_NAME
-
-  REF_CON  Ref_Con Cyan Black
-  REF_REF  Ref_Ref red  Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Via, Panel Button Label, Foreground Color, Background Color |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_VIA_NAME
-
-  CONT_DIF_N   Cont_Ohm    lawn_green    Black
-  CONT_POLY    Cont_Gate   red           Black
-  CONT_VIA     Cont_Via    deep_sky_blue Black
-  CONT_VIA2    Cont_Via2   chocolate     Black
-  CONT_VIA3    Cont_Via3   snow4         Black
-
-END
-
-# /*--------------------------------------------------------------------\
-# |                                                                     |
-# | Orientation, Panel Button Label, Foreground Color, Background Color |
-# |                                                                     |
-# \--------------------------------------------------------------------*/
-
-TABLE GRAAL_ORIENT_NAME 
-
-  NORTH  North   lawn_green  Black
-  SOUTH  South   yellow      Black
-  EAST   East    tan         Black
-  WEST   West    red         Black
-
-END
-
-# /*-----------------------------------------------------------------\
-# |                                                                  |
-# | Symmetry, Panel Button Label, Foreground Color, Background Color |
-# |                                                                  |
-# \-----------------------------------------------------------------*/
-
-TABLE GRAAL_SYMMETRY_NAME
-
-  NOSYM No_Sym  LightBlue         Black
-  SYM_X Sym_X   turquoise         Black
-  SYM_Y Sym_Y   cyan              Black
-  SYMXY Sym_XY  LightCyan         Black
-  ROT_P Rot_P   MediumAquamarine  Black
-  ROT_M Rot_M   aquamarine        Black
-  SY_RP Sym_RP  green             Black
-  SY_RM Sym_RM  MediumSpringGreen Black
-
-END
-
-# /*-------------------------------------------------------------------\
-# |                                                                    |
-# | View Layer, Panel Button Label, Foreground Color, Background Color |
-# |                                                                    |
-# \-------------------------------------------------------------------*/
-
-TABLE GRAAL_RDS_LAYER_NAME
-
-  RDS_NDIF     Ohm     lawn_green        Black
-  RDS_ACTIV    Active  brown             Black
-  RDS_NIMP     Nimp    forest_green      Black
-  RDS_POLY     Gate    red               Black
-  RDS_TPOLY    Tgate   light_pink        Black
-  RDS_CONT     Cont    dark_violet       Black
-  RDS_ALU1     Alu1    royal_blue        Black
-  RDS_TALU1    Talu1   light_steel_blue  Black
-  RDS_VIA1     Via1    deep_sky_blue     Black
-  RDS_ALU2     Alu2    Cyan              Black
-  RDS_TALU2    Talu2   light_cyan        Black
-  RDS_VIA2     Via2    chocolate         Black
-  RDS_ALU3     Alu3    peach_puff        Black
-  RDS_TALU3    Talu3   bisque            Black
-  RDS_VIA3     Via3    snow4             Black
-  RDS_ALU4     Alu4    aquamarine        Black
-  RDS_REF      Ref     coral             Black
-  RDS_ABOX     Abox    pink              Black
-
-END
diff --git a/alliance/share/etc/asga_7.rds b/alliance/share/etc/asga_7.rds
deleted file mode 100644
index cfb54b70..00000000
--- a/alliance/share/etc/asga_7.rds
+++ /dev/null
@@ -1,996 +0,0 @@
-#===============================================================================
-#
-#                          ALLIANCE VLSI CAD SYSTEM
-#                (R)ectangle (D)ata (S)tructure parameter file for GaAs
-#            (c) copyright 1995 Laboratoire UPMC/MASI/CAO-VLSI   
-#                           all rights reserved                 
-#                    e-mail     : cao-vlsi@masi.ibp.fr            
-#
-#                    file       : asga_6.rds
-#                    version    : 6
-#                    last modif : July 02, 1995
-#
-#===============================================================================
-
-#-------------------------------------------------------------------------------
-# Title of the file : Symbolic to Symbolic on a 'one lambda equals lambda
-# microns' basis for Vitesse 0.8 micron GaAs technology
-#
-#-------------------------------------------------------------------------------
-#
-# Description of the file :
-# This file contains all the needed parameters to translate a symbolic layout to
-# a real layout. 
-#
-#-------------------------------------------------------------------------------
-#
-# Note : all numeric values are in microns unless otherwise indicated.
-#
-#-------------------------------------------------------------------------------
-#
-# General information :
-# A few words on symbolic layout versus real layout :
-#
-#   Symbolic layout is used to ease the designers work by using objects that
-#   have a well specified semantic.
-#   The C data structure used for the internal representation of these objects
-#   is called ``MBK'', and comprehends, on a strictly layout point of view :
-#
-#     - Connectors, they are the terminals for routers, simulation tools, etc...
-#       these MBK primitives may be:
-#                     NWELL       N type bulk connector
-#                     PWELL       P type bulk connector
-#                     NTIE        N type implant in P bulk connector
-#                     PTIE        P type implant in N bulk connector
-#                     NDIF        N type diffusion connector
-#                     PDIF        P type diffusion connector
-#                     NTRANS      N type transistor connector
-#                     PTRANS      P type transistor connector
-#                     POLY        polysilicon connector
-#                     ALU1        first metal connector
-#                     ALU2        second metal connector
-#                     ALU3        third metal connector
-#                     TPOLY       polysilicon through route connector
-#                     TALU1       first metal through route connector
-#                     TALU2       second metal through route connector
-#                     TALU3       third metal through route connector
-#
-#     - Segments, they are runs of a layer for leaf cells construction and
-#       for routing; these may be:
-#                     NWELL       N type bulk segment
-#                     PWELL       P type bulk segment
-#                     NTIE        N type implant in P bulk segment
-#                     PTIE        P type implant in N bulk segment
-#                     NDIF        N type diffusion segment
-#                     PDIF        P type diffusion segment
-#                     NTRANS      N type transistor segment
-#                     PTRANS      P type transistor segment
-#                     POLY        polysilicon segment
-#                     ALU1        first metal segment
-#                     ALU2        second metal segment
-#                     ALU3        third metal segment
-#                     TPOLY       polysilicon through route segment
-#                     TALU1       first metal through route segment
-#                     TALU2       second metal through route segment
-#                     TALU3       third metal through route segment
-#       note that transistors also are considered as segments.
-#
-#     - References, for assigning a name to a symbolic object; these may be:
-#                     REF_CON     used for multi-access connectors
-#                     REF_REF     used for any other purpose
-#
-#     - Vias, for connecting two segments of distinct layers together; these
-#       MBK primitives may be:
-#                     CONT_BODY_P connects PWELL and ALU1
-#                     CONT_BODY_N connects NWELL and ALU1
-#                     CONT_DIF_N  connects NDIF and ALU1
-#                     CONT_DIF_P  connects PDIF and ALU1
-#                     CONT_POLY   connects POLY and ALU1
-#                     CONT_VIA    connects ALU1 and ALU2
-#                     CONT_VIA2   connects ALU2 and ALU3
-#                     CONT_VIA3   connects ALU3 and ALU4
-#                     C_X_N       L shaped N transistor corner filling
-#                     C_X_P       L shaped P transistor corner filling
-#
-#   Factories usually only understand real layout which is given in terms of
-#   rectangles or polygons. And some tools work only with rectangles. The data
-#   structure based on such rectangles is called ``RDS'', for Rectangle Data
-#   Structure. Extractors and DRCs also need rectangles to work on. Here is the
-#   complete set of RDS layers:
-#                     RDS_NWELL   N type bulk
-#                     RDS_PWELL   P type bulk
-#                     RDS_NTIE    N type implant in P type bulk
-#                     RDS_PTIE    P type implant in N type bulk
-#                     RDS_NDIF    N type diffusion
-#                     RDS_PDIF    P type diffusion
-#                     RDS_ACTIV   active area layer
-#                     RDS_NIMP    N type implant
-#                     RDS_PIMP    P type implant
-#                     RDS_POLY    polysilicon
-#                     RDS_TPOLY   polysilicon through route
-#                     RDS_CONT    contact hole in isolation between a low
-#                                 level layer and first metal
-#                     RDS_GATE    transistor gate layer
-#                     RDS_ALU1    first metal
-#                     RDS_TALU1   first metal through route
-#                     RDS_VIA1    via hole in isolation between first metal
-#                                 and second metal
-#                     RDS_ALU2    second metal
-#                     RDS_TALU2   second metal through route
-#                     RDS_VIA2    via hole in isolation between second metal
-#                                 and third metal
-#                     RDS_ALU3    third metal
-#                     RDS_TALU3   third metal through route
-#                     RDS_VIA3    via hole in isolation between third metal
-#                                 and fourth metal
-#                     RDS_ALU4    fourth metal
-#                     RDS_CPAS    passivation contact layer
-#                     RDS_REF     virtual layer for the representation of
-#                                 symbolic references
-#                     RDS_USER0   user oriented layer
-#                     RDS_USER1   user oriented layer
-#                     RDS_USER2   user oriented layer
-#                     RDS_ABOX    virtual layer containing information on the
-#                                 abutment box of a model
-#
-#   (Refer to documentation for more information)
-#-------------------------------------------------------------------------------
-
-#-------------------------------------------------------------------------------
-# physical_grid :
-#
-#   Warning : physical_grid must be the first value to be declared.
-#
-#   Most technolgies require that a layout be aligned on a physical grid. This
-#   implies that all the coordinates and values given here after have to be
-#   multiples of the value physical_grid. Misaligned objects in an input figure
-#   is a problem that some tools like s2r solve by allowing themselves to expand
-#   the width of these objects to have them snap to the grid.
-#-------------------------------------------------------------------------------
-
-DEFINE PHYSICAL_GRID 0.5
-
-#-------------------------------------------------------------------------------
-# lambda : 
-#
-#   Defines the value of lambda in the real or pseudo real (1 lambda = 1 micron)
-#   technology. It is chosen, after a carefull observation of real design
-#   rules.
-#
-#   (Refer to documentation for more information)
-#-------------------------------------------------------------------------------
-
-DEFINE LAMBDA 1.0
-
-#-------------------------------------------------------------------------------
-# mbk_to_rds_segment table :
-#
-# This table describes how to translate one symbolic segment (MBK data
-# structure) to 1, 2, 3 or more physical rectangles (RDS data structure).
-#
-# o A transistor segment (MBK NTRANS or PTRANS layer) will generate in
-#   general 3 to 6 rectangles (RDS_ACTIV, RDS_NIMP, RDS_POLY, [RDS_NDIF]*2).
-#
-# o An ohmic metal segment (MBK NDIF layer) will generate 2 rectangles 
-#   (RDS_ACTIV, RDS_NDIF).
-#
-# o All other MBK layers will generate one rectangle.
-#
-# For each physical rectangle (RDS layer) generated from an MBK segment, five
-# parameters are given :
-#   - the RDS layer
-#   - the type of offset of the rectangle : (L)eft, (R)igth, (U)p, (D)own, or
-#     ()no offset
-#   - the type of width of the rectangle : variable width (VW) or constant
-#     width (CW)
-#   - the physical length extension : DLR 
-#   and
-#   - the physical width oversize   : DWR for variable width rectangles
-#   or
-#   - the physical width            :  WR for constant width rectangles
-#   and
-#   - the value of the offset which is defined as the distance between the
-#     edge of the RDS rectangle being processed that is closest to the center
-#     of the given segment and the (R)ight or (L)eft edge of that segment
-#   - the tool(s) concerned by the given translation. This parameter is needed
-#     for Alliance editor graal (DRC) and extractor lynx (EXT) that require a
-#     special transistor representation in order to properly detect
-#     equipotential signals (i.e. no possible equipotential signal propagation
-#     under transistors)
-#
-# The physical length of a rectangle is then given by :
-#   - Physical LENGTH = Symbolic LENGTH * lambda + (2 * DLR)
-#
-# The physical width of a variable width rectangle is then given by :
-#   - Physical WIDTH  = Symbolic WIDTH  * lambda + DWR
-#
-# The physical width of a constant width rectangle is then given by :
-#   - Physical WIDTH  = WR
-#
-# Note that most cases concern variable width rectangles where as constant
-# width rectangles are rarely encountered.
-#
-# This table is defined as follows :
-# The first column gives the MBK layer name that needs to be translated, the
-# following columns each represent an RDS layer with its associated parameters
-# described above. It is important that the first RDS layer of each composed
-# segment be the most representative, that it stands as the back bone of the
-# segment.
-#
-# MBK    RDS layer i
-# name   name  type  DLR  (D)WR  OFFSET  TOOL\
-#        name  type  DLR  (D)WR  OFFSET  TOOL\
-#        ...
-#        name  type  DLR  (D)WR  OFFSET  TOOL
-#-------------------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_SEGMENT
-
-  NDIF    RDS_NDIF   VW  1.0  0.0  0.0  ALL
-  NTRANS  RDS_POLY   VW  0.0  0.0  0.0  ALL \
-          RDS_NDIF  LCW -2.0  2.0  1.5  ALL \
-          RDS_NDIF  RCW -2.0  2.0  1.5  ALL \
-          RDS_ACTIV  VW -2.0  7.0  0.0  ALL 
-# this layer is present only for educational and aesthetical purposes
-  NWELL   RDS_POLY   VW  0.0  0.0  0.0  ALL \
-          RDS_NDIF  LCW -2.0  2.0  1.5  ALL \
-          RDS_NDIF  RCW -2.0  2.0  1.5  ALL \
-          RDS_ACTIV LCW -2.0  3.0  0.5  ALL \
-          RDS_ACTIV RCW -2.0  3.0  0.5  ALL \
-          RDS_NIMP   VW -1.5  1.0  0.0  ALL
- # these 3 layers are present only for educational and aesthetical purposes
-  PTRANS  RDS_POLY   VW  0.0  0.0  0.0  ALL \
-          RDS_POLY  RCW  0.0  1.5  0.0  ALL \
-          RDS_NDIF  LCW -2.0  2.0  1.5  ALL \
-          RDS_NDIF  RCW -2.0  3.5  0.0  ALL \
-          RDS_ACTIV LCW -2.0  3.0  0.5  ALL \
-          RDS_ACTIV RCW -2.0  1.5  2.0  ALL \
-          RDS_NIMP   VW -1.5  1.0  0.0  ALL \
-          RDS_NIMP  RCW -1.5  2.0  0.0  ALL
-# these 4 last layers are present only for educational and aesthetical purposes
-  POLY    RDS_POLY   VW  0.5  0.0  0.0  ALL
-  ALU1    RDS_ALU1   VW  0.5  0.0  0.0  ALL
-  ALU2    RDS_ALU2   VW  1.0  0.0  0.0  ALL
-  ALU3    RDS_ALU3   VW  2.5  0.0  0.0  ALL
-  TPOLY   RDS_TPOLY  VW  0.5  0.0  0.0  ALL
-  TALU1   RDS_TALU1  VW  0.5  0.0  0.0  ALL
-  TALU2   RDS_TALU2  VW  1.0  0.0  0.0  ALL
-  TALU3   RDS_TALU3  VW  2.5  0.0  0.0  ALL
-
-END
-
-#-------------------------------------------------------------------------------
-# mbk_to_rds_connector table :
-#
-# This table explains how to translate symbolic connectors.
-#
-# one symbolic connector (MBK data structure) is translated into one physical
-# rectangle (RDS data structure) using 3 parameters :
-#   - RDS layer
-#   - physical width oversize                             : DWR 
-#   - physical extension on each side of the ABUTMENT BOX : DER 
-#
-# Physical WIDTH  = Symbolic WIDTH  * lambda + DWR
-# Physical EXTENSION = 2 * DER
-#
-# This table is defined below :
-# The first column is the MBK layer name to be translated, after which there is
-# an RDS layer name, it's DWR value and it's DER value.
-#
-# MBK    RDS layer 
-# name   name     DER DWR 
-#-------------------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_CONNECTOR
-
-  NDIF    RDS_NDIF  1.0  0
-  POLY    RDS_POLY  0.5  0  
-  ALU1    RDS_ALU1  0.5  0  
-  ALU2    RDS_ALU2  1.0  0  
-  ALU3    RDS_ALU3  2.5  0  
-
-END
-
-#-------------------------------------------------------------------------------
-# mbk_to_rds_reference table :
-#
-# This table explains how to translate symbolic references. These references,
-# both translated into an RDS_REF RDS layer offer the possibility to associate
-# a name to a point (a couple of coordinates). The REF_CON primitive is
-# exclusively used for the naming of vias while the other primitive is
-# reserved for any other naming purpose.
-#
-# (Refer to documentation for more information)
-#
-# MBK reference   RDS layer
-# name            name  width
-#-------------------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_REFERENCE
-
-  REF_CON  RDS_REF    1
-  REF_REF  RDS_REF    1
-
-END
-
-#-------------------------------------------------------------------------------
-# mbk_to_rds_via table :
-#
-# This table describes how to translate one symbolic via or primitive, (MBK
-# data structure) into 2, 3 or 4 physical rectangles (RDS data structure).
-#
-# This table is defined as follows :
-# The first column is the MBK via name to translate, after which comes a certain
-# number of groups of 2 columns. In a group the first column is the RDS layer
-# name, the second one is the RDS layer width.
-#
-# MBK via      RDS layer 1  RDS  layer 2  RDS  layer 3  RDS layer 4      
-# name         name  width  name   width  name   width  name  width  
-#-------------------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_VIA
-
-  CONT_DIF_N  RDS_NDIF 2.0 ALL RDS_CONT 1.0 ALL RDS_ALU1 1.0 ALL
-  CONT_POLY   RDS_POLY 2.0 ALL RDS_CONT 1.0 ALL RDS_ALU1 1.0 ALL
-  CONT_VIA    RDS_ALU1 2.0 ALL RDS_VIA1 2.0 ALL RDS_ALU2 3.0 ALL
-  CONT_VIA2   RDS_ALU2 5.0 ALL RDS_VIA2 3.0 ALL RDS_ALU3 5.0 ALL
-  CONT_VIA3   RDS_ALU3 6.0 ALL RDS_VIA3 4.0 ALL RDS_ALU4 10.0 ALL
-
-END
-
-#-------------------------------------------------------------------------------
-# lynx_graph table :
-#
-# This table gives all the possible interconnections between RDS layers for
-# the propagation of equipotential signals. Each line in this table is to be
-# read independently as follows : RDS layer of first column is connected to
-# an RDS layer of another column if they overlap or touch. This table is useful
-# to any tool requirering equipotential analysis like lynx or graal.
-#-------------------------------------------------------------------------------
-
-TABLE LYNX_GRAPH
- 
-  RDS_NDIF  RDS_POLY  RDS_CONT  RDS_NDIF
-  RDS_POLY  RDS_NDIF  RDS_CONT  RDS_POLY
-  RDS_CONT  RDS_NDIF  RDS_POLY  RDS_ALU1  RDS_CONT
-  RDS_ALU1  RDS_CONT  RDS_VIA1  RDS_REF   RDS_ALU1
-  RDS_VIA1  RDS_ALU1  RDS_ALU2  RDS_VIA1
-  RDS_ALU2  RDS_VIA1  RDS_VIA2  RDS_ALU2
-  RDS_VIA2  RDS_ALU2  RDS_ALU3  RDS_VIA2
-  RDS_ALU3  RDS_VIA2  RDS_VIA3  RDS_ALU3
-  RDS_VIA3  RDS_ALU3  RDS_ALU4  RDS_VIA3
-  RDS_ALU4  RDS_VIA3  RDS_ALU4
-  RDS_REF   RDS_ALU1  RDS_REF
-  
-END
-
-#-------------------------------------------------------------------------------
-# lynx_capa table : 
-#
-# RDS layer   Capacitance
-# name        pF / Lambda^2
-#-------------------------------------------------------------------------------
- 
-TABLE LYNX_CAPA
-
-  RDS_POLY  	0.791e-04
-  RDS_ALU1  	0.574e-04
-  RDS_ALU2  	0.347e-04
-  RDS_ALU3  	0.227e-04
-  RDS_ALU4  	0.083e-04
-  
-END
-
-#---------------------------------------------------------------------
-# TABLE LYNX_RESISTOR :
-#
-# RDS layer   Surface resistor
-# name        Ohm / Micron^2
-#---------------------------------------------------------------------
-
-TABLE LYNX_RESISTOR
-END
-
-#-------------------------------------------------------------------------------
-# lynx_transistor table : 
-#
-# MBK layer		RDS layer	Corner junction
-# name			name			name
-#-------------------------------------------------------------------------------
- 
-TABLE LYNX_TRANSISTOR
-
-  NTRANS  NTRANS  C_X_N  RDS_POLY  RDS_NDIF  RDS_ACTIV
-  PTRANS  PTRANS  C_X_P  RDS_POLY  RDS_NDIF  RDS_ACTIV
-  NWELL	  PTRANS  C_X_N  RDS_POLY  RDS_NDIF  NULL     
-  
-END
-
-#-------------------------------------------------------------------------------
-# lynx_diffusion table :
-#
-# RDS layer RDS layer
-# name      name    
-#-------------------------------------------------------------------------------
-
-TABLE LYNX_DIFFUSION
-END
-
-#-------------------------------------------------------------------------------
-# cif_layer table :
-# 
-# Equivalency table between RDS layer names and cif layer names.
-# RDS/cif parser and driver typically need this table.
-#-------------------------------------------------------------------------------
-
-TABLE CIF_LAYER
-
-  RDS_NDIF     LNDIF
-  RDS_NIMP     LNIMP
-  RDS_ACTIV    LACTIV
-  RDS_POLY     LPOLY
-  RDS_TPOLY    LTPOLY
-  RDS_CONT     LCONT
-  RDS_ALU1     LALU1
-  RDS_TALU1    LTALU1
-  RDS_VIA1     LVIA1
-  RDS_ALU2     LALU2
-  RDS_TALU2    LTALU2
-  RDS_VIA2     LVIA2
-  RDS_ALU3     LALU3
-  RDS_TALU3    LTALU3
-  RDS_VIA3     LVIA3
-  RDS_ALU4     LALU4
-  RDS_REF      LREF
-
-END
-
-#-------------------------------------------------------------------------------
-# gds_layer table :
-#
-# Equivalency table between RDS layer names and gds layer number.
-# RDS/gds parser and driver typically need this table.
-#-------------------------------------------------------------------------------
-
-TABLE GDS_LAYER
-
-  RDS_NDIF     1
-  RDS_NIMP     2
-  RDS_ACTIV    3
-  RDS_POLY     4
-  RDS_TPOLY    5
-  RDS_CONT     6
-  RDS_ALU1     7
-  RDS_TALU1    8
-  RDS_VIA1     9
-  RDS_ALU2     10
-  RDS_TALU2    11
-  RDS_VIA2     12
-  RDS_ALU3     13
-  RDS_TALU3    14
-  RDS_VIA3     15
-  RDS_ALU4     16
-  RDS_REF      17
-
-END
-
-#-------------------------------------------------------------------------------
-# oversize_denotch table :
-#
-# This table contains the oversize value needed to erase notches. All the
-# rectangles in the same RDS layer are oversized by this value and then merged
-# all together and finally undersized by the same value.
-#
-# For some RDS layers, like RDS_NWELL, RDS_NIMP and RDS_PIMP, if two rectangles
-# are separated from a distance that is smaller or equal to the minimun spacing
-# design rule, then they must be merged as a single one. In this case, the
-# oversize value is equal to the minimum spacing rule between two edges of the
-# same layer divided by 2. 
-#
-# Some other RDS layers, like RDS_ALU1, ..., must not be merged. In this case,
-# the oversize value is equal to the minimum spacing rule between two edges of
-# the same layer divided by 2, minus the physical grid. 
-#
-# Some layers never create notches, such as RDS_VIA1 or RDS_CONT, so the
-# oversize value is null.
-#
-# This table is useful for tools like s2r that work on a real level.
-#-------------------------------------------------------------------------------
-
-TABLE S2R_OVERSIZE_DENOTCH
-
-# RDS_NDIF    0
-# RDS_ACTIV   0
-# RDS_NIMP    0
-# RDS_POLY    0
-# RDS_TPOLY   0
-# RDS_CONT    0
-# RDS_ALU1    0
-# RDS_TALU1   0
-# RDS_VIA1    0
-# RDS_ALU2    0
-# RDS_TALU2   0
-# RDS_VIA2    0
-# RDS_ALU3    0
-# RDS_TALU3   0
-# RDS_VIA3    0
-# RDS_ALU4    0
-# RDS_CPAS    0
-# RDS_REF     0
-# RDS_USER0   0
-# RDS_USER1   0
-# RDS_USER2   0
-# RDS_ABOX    0
-
-END
-
-#-------------------------------------------------------------------------------
-# bloc_ring_width table :
-#
-# The normal ring width is the minimum spacing design rule between 2 segments of
-# the same RDS layer. 
-#
-# A zero means that no ring is wanted for that RDS layer. 
-#
-# s2r for example must merge segments to erase notches even if those segments
-# are in two different hierarchical level blocs, for example, two blocs abuted
-# side by side. So, it must be able to fetch segments inside blocs. It is not
-# needed to flatten the entire bloc, only a ring is necessary. The ring is
-# computed from the abutment box edges or from the envelope edges of the
-# overlapping blocs.
-#
-# This table is useful for tools like s2r and druc that work on a real level.
-#-------------------------------------------------------------------------------
-
-TABLE S2R_BLOC_RING_WIDTH
-
-  RDS_NDIF    2.0
-  RDS_ACTIV   0
-  RDS_NIMP    0
-  RDS_POLY    2.0
-  RDS_TPOLY   0
-#  RDS_CONT    2.0
-  RDS_ALU1    2.5
-  RDS_TALU1   0
-#  RDS_VIA1    3.0 
-  RDS_ALU2    2.0
-  RDS_TALU2   0
-#  RDS_VIA2    3.0
-  RDS_ALU3    6.0
-  RDS_TALU3   0 
-#  RDS_VIA3    4.0
-  RDS_ALU4    0
-  RDS_CPAS    0
-  RDS_REF     0 
-  RDS_USER0   0
-  RDS_USER1   0
-  RDS_USER2   0
-  RDS_ABOX    0 
-
-END
-
-#-------------------------------------------------------------------------------
-# minimum_layer_width table :
-#
-# This table contains the minimum width of each RDS layer. It is used by s2r for
-# example to avoid creating rectangles having widths that are below the required
-# minimum, during the merging operation.
-#
-# A zero can be specified, when it is certain that the given layer will not be
-# merged.
-#
-# This table is useful for tools like s2r and druc that work on a real level.
-#-------------------------------------------------------------------------------
-
-TABLE S2R_MINIMUM_LAYER_WIDTH
-
-  RDS_NDIF    2.0
-  RDS_ACTIV   0
-  RDS_NIMP    0
-  RDS_POLY    1.0
-  RDS_TPOLY   0
-  RDS_CONT    1.0
-  RDS_ALU1    1.0
-  RDS_TALU1   0
-  RDS_VIA1    1.0
-  RDS_ALU2    2.0
-  RDS_TALU2   0
-  RDS_VIA2    3.0
-  RDS_ALU3    5.0
-  RDS_TALU3   0
-  RDS_VIA3    4.0
-  RDS_ALU4    0
-  RDS_CPAS    0
-  RDS_REF     0
-  RDS_USER0   0
-  RDS_USER1   0
-  RDS_USER2   0
-  RDS_ABOX    0
-
-END
-
-#-------------------------------------------------------------------------------
-# s2r_post_treat table :
-#
-# This table tells s2r which RDS layers must be post-treated. And more
-# specificaly if a layer is only to be be translated, or if it has to be
-# translated and then post-treated.
-# To translate means to translate and fit from symbolic to real.
-# To post-treat means that it should also be merged with its neighbours.
-# For example, it is not necessary to merge cut layers such as RDS_CONT. 
-#
-# If set to NOTREAT, the first parameter indicates a translation.
-# If set to TREAT, then the layer is translated and then post-treated.
-#
-# To post-treat creates problems with implantation layers. It is possible to
-# have a good symbolic layout (no symbolic design rule errors), and have a
-# resulting layout with drc violations; this case is usually the result of a
-# poor post-treatement. This is due to the fact that these layers do not exist
-# in symbolic, so it is not possible to apply to them any symbolic drc
-# verifications. If two rectangles of these layers are too close (less than a
-# given value), they must be merged. Generally, there is no problem, but when
-# corners are too near it is impossible to merge with the classical algorithms :
-#     expand,
-#     merge, 
-#     shrink.
-# Rectangles, known as scotches, are in such a case created for merging.
-# Here is an example :
-#
-#   +--------+              +--------+             +-----+--+
-#   |////////|              |////////|             |/////|//|
-#   |//+--+//|              |//+--+//|             |//+--|//|
-#   |//|  |//|    gives ->  |//|  |//|       or -> |//|  |//|
-#   |//+--+//|              +-----------+          |//+--|//|
-#   |////////|              |///////////|          |/////|//|
-#   +--------+              +--------+//|          +-----|//|     
-#       ^    +--------+              |//|-----+          |//+--------+
-#       |    |////////|              |//|/////|          |///////////|
-#       o--->|//+--+//|              |//|--+//|          +-----------+
-#       |    |//|  |//|              |//|  |//|             |//|  |//|
-#   implant  |//+--+//|              |//|--+//|             |//|--+//|
-#    areas   |////////|              |//|/////|             |//|/////|
-#            +--------+              +--+-----+             +--+-----+
-#
-#   An N implantation layer should not overlap a P implantation layer. We say
-#   that P implantations and N implantations are complementary. A scotch will
-#   not be created if it intersects with any of the rectangles of the
-#   complementary layers.
-#
-#   If a record contains in the second field an RDS layer that is different
-#   from NULL, it indicates the complementary layer. This implies that if it
-#   is a layer that might need scotches the algorithm will try not to intersect
-#   with it when creating scotches.
-#-------------------------------------------------------------------------------
-
-TABLE S2R_POST_TREAT
-
-  RDS_NDIF         TREAT NULL
-  RDS_ACTIV      NOTREAT NULL
-  RDS_NIMP       NOTREAT NULL
-  RDS_POLY         TREAT NULL
-  RDS_TPOLY      NOTREAT NULL
-  RDS_CONT       NOTREAT NULL
-  RDS_ALU1         TREAT NULL
-  RDS_TALU1      NOTREAT NULL
-  RDS_VIA1       NOTREAT NULL
-  RDS_ALU2         TREAT NULL
-  RDS_TALU2      NOTREAT NULL
-  RDS_VIA2       NOTREAT NULL
-  RDS_ALU3         TREAT NULL
-  RDS_TALU3      NOTREAT NULL
-  RDS_VIA3       NOTREAT NULL
-  RDS_ALU4       NOTREAT NULL
-  RDS_CPAS       NOTREAT NULL
-  RDS_REF        NOTREAT NULL
-  RDS_USER0      NOTREAT NULL
-  RDS_USER1      NOTREAT NULL
-  RDS_USER2      NOTREAT NULL
-  RDS_ABOX       NOTREAT NULL
-
-END
-DRC_RULES
-layer RDS_ACTIV 2.0;
-layer RDS_POLY  1.0;
-layer RDS_NDIF  2.0;
-layer RDS_ALU1  1.0;
-layer RDS_CONT  1.0;
-layer RDS_ALU2  2.0;
-layer RDS_VIA1  2.0;
-layer RDS_ALU3  5.0;
-layer RDS_VIA2  3.0;
-layer RDS_VIA3  4.0;
-
-regles
-
-caracterise RDS_POLY (
-    regle 100 : longueur_inter min 1.0;
-    regle 101 : notch >= 2.0;
-);
-
-relation RDS_POLY, RDS_POLY (
-    regle 102 : distance axiale min 2.0;
-);
-
-relation RDS_POLY, RDS_NDIF (
-    regle 103 : distance axiale min 1.5;
-    regle 104 : enveloppe inferieure min 1.0;
-    regle 105 : marge penetre_inter min 1.5;
-    regle 106 : marge inferieure min 1.0;
-    regle 107 : croix perpendiculaire_inter min 1.5;
-    regle 108 : croix longueur_min min 1.0;
-);
-
-relation RDS_POLY, RDS_NDIF (
-    regle 109 : intersection longueur_inter min 2.0;
-    regle 110 : intersection largeur_inter min 1.5;
-    regle 111 : intersection inferieure min 1.0;
-    regle 112 : extension largeur_inter min 1.5;
-    regle 113 : extension longueur_min min 1.0;
-);
-
-caracterise RDS_NDIF (
-    regle 120 : longueur_inter min 2.0;
-    regle 121 : notch >= 2.0;
-);
-
-relation RDS_NDIF, RDS_NDIF (
-    regle 122 : distance axiale min 2.0;
-);
-
-relation RDS_NDIF, RDS_POLY (
-    regle 123 : enveloppe superieure min 2.0;
-    regle 124 : enveloppe inferieure min 1.0;
-    regle 125 : enveloppe largeur_inter min 1.5;
-    regle 126 : marge longueur_max min 2.0;
-    regle 127 : marge inferieure min 1.0;
-);
-
-relation RDS_NDIF, RDS_POLY (
-    regle 128 : croix longueur_max min 2.0;
-    regle 129 : croix longueur_min min 1.0;
-    regle 130 : intersection longueur_max min 2.0;
-    regle 131 : intersection largeur_min min 1.0;
-    regle 132 : extension longueur_min min 2.0;
-);
-
-caracterise RDS_ALU1 (
-    regle 140 : longueur_inter min 1.0;
-    regle 141 : notch >= 3.0;
-);
-
-relation RDS_ALU1, RDS_ALU1 (
-    regle 142 : distance axiale min 3.0;
-);
-
-caracterise RDS_CONT (
-    regle 160 : longueur_inter min 1.0;
-    regle 161 : notch >= 2.0;
-);
-
-relation RDS_CONT, RDS_CONT (
-    regle 162 : distance axiale min 2.0;
-);
-
-define RDS_CONT, RDS_POLY inclusion  -> CONTinPOLY;
-
-relation CONTinPOLY, CONTinPOLY (
-    regle 163 : distance axiale min 4.0;
-);
-
-define RDS_CONT, RDS_NDIF inclusion -> CONTinNDIF;
-
-relation RDS_NDIF, CONTinNDIF (
-    regle 170 : distance axiale min 3.0;
-);
-
-#relation RDS_ACTIV, CONTinNDIF (
-#    regle 171 : distance axiale <> 2.5;
-#);
-
-relation CONTinNDIF, CONTinPOLY (
-    regle 172 : distance axiale min 4.0;
-);
-
-relation CONTinNDIF, CONTinNDIF (
-    regle 173 : distance axiale min 4.0;
-);
-
-define RDS_CONT, CONTinNDIF exclusion -> CONT_NDIF;
-
-relation CONT_NDIF, RDS_NDIF (
-    regle 174 : distance axiale min 1.0;
-    regle 175 : enveloppe surface_inter < 0.0;
-    regle 176 : marge surface_inter < 0.0;
-    regle 177 : croix surface_inter < 0.0;
-    regle 178 : intersection surface_inter < 0.0;
-    regle 179 : extension surface_inter < 0.0;
-);
-
-undefine CONT_NDIF;
-undefine CONTinNDIF;
-undefine CONTinPOLY;
-
-caracterise RDS_VIA1 (
-    regle 180 : longueur < 6.0;
-    regle 181 : longueur_inter min 2.0;
-    regle 182 : notch >= 2.0;
-);
-
-relation RDS_VIA1, RDS_VIA1 (
-    regle 183 : distance axiale min 2.0;
-);
-
-relation RDS_VIA1, RDS_CONT (
-    regle 184 : distance axiale min 1.5;
-    regle 185 : enveloppe longueur_inter < 0.0;
-    regle 186 : marge longueur_inter < 0.0;
-    regle 187 : croix longueur_inter < 0.0;
-    regle 188 : intersection longueur_inter < 0.0;
-    regle 189 : extension longueur_inter < 0.0;
-    regle 190 : inclusion longueur_inter < 0.0;
-);
-
-caracterise RDS_ALU2 (
-    regle 200 : longueur_inter min 2.0;
-    regle 201 : notch >= 2.0;
-);
-
-relation RDS_ALU2, RDS_ALU2 (
-    regle 202 : distance axiale min 2.0;
-);
-
-caracterise RDS_VIA2 (
-    regle 220 : longueur_inter min 3.0;
-    regle 221 : notch >= 3.0;
-);
-
-relation RDS_VIA2, RDS_VIA2 (
-    regle 222 : distance axiale min 3.0;
-);
-
-relation RDS_VIA2, RDS_VIA1 (
-    regle 223 : distance axiale min 1.0;
-    regle 224 : enveloppe longueur_inter < 0.0;
-    regle 225 : marge longueur_inter < 0.0;
-    regle 226 : croix longueur_inter < 0.0;
-    regle 227 : intersection longueur_inter < 0.0;
-    regle 228 : extension longueur_inter < 0.0;
-    regle 229 : inclusion longueur_inter < 0.0;
-);
-
-caracterise RDS_ALU3 (
-    regle 240 : longueur_inter min 5.0;
-    regle 241 : notch >= 6.0;
-);
-
-relation RDS_ALU3, RDS_ALU3 (
-    regle 242 : distance axiale min 6.0;
-);
-
-relation RDS_VIA1, RDS_ALU3 (
-    regle 250 : enveloppe superieure max 3.0;
-    regle 251 : marge superieure max 3.0;
-    regle 252 : croix longueur_max max 3.0;
-    regle 253 : intersection superieure max 3.0;
-    regle 254 : extension longueur_max max 3.0;
-);
-
-caracterise RDS_VIA3 (
-    regle 260 : longueur_inter min 4.0;
-    regle 261 : notch >= 4.0;
-);
-
-relation RDS_VIA3, RDS_VIA3 (
-    regle 262 : distance axiale min 4.0;
-);
-
-define RDS_NDIF, RDS_POLY intersection -> CONT_O;
-
-relation CONT_O, RDS_CONT (
-    regle 300 : marge frontale min 2.0;
-    regle 301 : enveloppe inferieure min 2.0;
-);
-
-define RDS_CONT, RDS_NDIF inclusion -> CONTinNDIF;
-
-relation CONT_O, CONTinNDIF (
-    regle 302 : distance axiale min 1.0;
-    regle 303 : croix surface_inter < 0.0;
-    regle 304 : intersection surface_inter < 0.0;
-    regle 305 : extension surface_inter < 0.0;
-    regle 306 : inclusion longueur_inter < 0.0;
-);
-
-undefine CONTinNDIF;
-undefine CONT_O;
-
-fin regles
-END_DRC_RULES
-DRC_COMMENT
-END_DRC_COMMENT
-100 error : minimum Gate intersection width is 1.0
-101 error : minimum Gate notch is 2.0
-102 error : minimum Gate/Gate edge to edge distance is 2.0
-103 error : minimum Gate/Ohm edge to edge distance is 1.5
-104 error : minimum Gate/Ohm extension is 1.0 for a contact0 structure
-105 warning : minimum Gate/Ohm intersection geometry is 1.5 x 2.0 for a contact0 structure
-106 error : minimum Gate/Ohm extension is 1.0 for a contact0 structure
-107 warning : minimum Gate/Ohm intersection geometry is 1.5 x 2.0 for a contact0 structure
-108 error : minimum Gate/Ohm extension is 1.0 for a contact0 structure
-109 warning : minimum Gate/Ohm intersection geometry is 1.5 x 2.0 for a contact0 structure
-110 warning : minimum Gate/Ohm intersection geometry is 1.5 x 2.0 for a contact0 structure
-111 error : minimum Gate/Ohm extension is 1.0 for a contact0 structure
-112 warning : minimum Gate/Ohm intersection geometry is 1.5 x 2.0 for a contact0 structure
-113 error : minimum Gate/Ohm extension is 1.0 for a contact0 structure
-120 error : minimum Ohm intersection width is 2.0
-121 error : minimum Ohm notch is 2.0
-122 error : minimum Ohm/Ohm edge to edge distance is 2.0
-123 error : Ohm/Gate extension must be at least 2.0 on one of the largest side of a contact0 structure
-124 error : minimum Ohm/Gate extension is 1.0 for a contact0 structure
-125 warning : minimum Gate/Ohm intersection geometry is 1.5 x 2.0 for a contact0 structure
-126 error : Ohm/Gate extension must be at least 2.0 on one of the largest side of a contact0 structure
-127 error : minimum Ohm/Gate extension is 1.0 for a contact0 structure
-128 error : Ohm/Gate extension must be at least 2.0 on one of the largest side of a contact0 structure
-129 error : minimum Ohm/Gate extension is 1.0 for a contact0 structure
-130 error : Ohm/Gate extension must be at least 2.0 on one of the largest side of a contact0 structure
-131 error : minimum Ohm/Gate extension is 1.0 for a contact0 structure
-132 error : Ohm/Gate extension must be at least 2.0 on one of the largest side of a contact0 structure
-140 error : minimum Alu1 intersection width is 1.0
-141 error : minimum Alu1 notch is 3.0
-142 error : minimum Alu1/Alu1 edge to edge distance is 3.0
-160 error : minimum via1 intersection width is 1.0
-161 error : minimum via1 notch is 2.0
-162 error : minimum via1/via1 edge to edge distance is 2.0
-163 error : minimum Cont_Gate/Cont_Gate edge to edge distance is 3.0
-170 error : minimum Cont_Ohm/Ohm edge to edge distance is 2.5
-#171 error : minimum Cont_Ohm/Active edge to edge distance is 2.5
-172 error : minimum Cont_Ohm/Cont_Gate edge to edge distance is 3.0
-173 error : minimum Cont_Ohm/Cont_Ohm edge to edge distance is 3.0
-174 error : minimum via1/Ohm edge to edge distance is 1.0
-175 error : via1 must be either completely internal to or external to Ohm
-176 error : via1 must be either completely internal to or external to Ohm
-177 error : via1 must be either completely internal to or external to Ohm
-178 error : via1 must be either completely internal to or external to Ohm
-179 error : via1 must be either completely internal to or external to Ohm
-180 warning : maximum geometry of intersecting via2s is 5 x 5
-181 error : minimum via2 intersection width is 2.0
-182 error : minimum via2 notch is 2.0
-183 error : minimum via2/via2 edge to edge distance is 2.0
-184 error : minimum via2/via1 edge to edge distance is 1.5
-185 error : via1 may not be nested in via2
-186 error : via2 and via1 may not intersect
-187 error : via2 and via1 may not intersect
-188 error : via2 and via1 may not intersect
-189 error : via2 and via1 may not intersect
-190 error : via2 may not be nested in via1
-200 error : minimum Alu2 intersection width is 2.0
-201 error : minimum Alu2 notch is 2.0
-202 error : minimum Alu2/Alu2 edge to edge distance is 2.0
-220 error : minimum via3 intersection width is 3.0
-221 error : minimum via3 notch is 3.0
-222 error : minimum via3/via3 edge to edge distance is 3.0
-223 error : minimum via3/via2 edge to edge distance is 1.0
-224 error : via2 may not be nested in via3
-225 error : via3 and via2 may not intersect
-226 error : via3 and via2 may not intersect
-227 error : via3 and via2 may not intersect
-228 error : via3 and via2 may not intersect
-229 error : via3 may not be nested in via2
-240 error : minimum Alu3 intersection width is 5.0
-241 error : minimum Alu3 notch is 6.0
-242 error : minimum Alu3/Alu3 edge to edge distance is 6.0
-250 error : minimum via2/Alu3 extension may not exceed 3
-251 error : minimum via2/Alu3 extension may not exceed 3
-252 error : minimum via2/Alu3 extension may not exceed 3
-253 error : minimum via2/Alu3 extension may not exceed 3
-254 error : minimum via2/Alu3 extension may not exceed 3
-260 error : minimum via4 intersection width is 4.0
-261 error : minimum via4 notch is 4.0
-262 error : minimum via4/via4 edge to edge distance is 4.0
-300 error : minimum cont0/via1 frontal extension is 2.0
-301 error : minimum cont0/via1 extension is 2.0
-302 error : minimum cont0/via1 edge to edge distance is 1.0
-303 error : contact0 and via1 may not intersect in this way
-304 error : contact0 and via1 may not intersect in this way
-305 error : contact0 and via1 may not intersect in this way
-306 error : contact0 and via1 may not intersect in this way
diff --git a/alliance/share/etc/cmos_10.rds b/alliance/share/etc/cmos_10.rds
deleted file mode 100644
index 178e6b1f..00000000
--- a/alliance/share/etc/cmos_10.rds
+++ /dev/null
@@ -1,840 +0,0 @@
-#=====================================================================
-#
-#                         ALLIANCE VLSI CAD                  
-#            (R)eal (D)ata (S)tructure parameter file
-#         (c) copyright 1992 Laboratory UPMC/MASI/CAO-VLSI   
-#                        all rights reserved                 
-#                   e-mail : cao-vlsi@masi.ibp.fr            
-#
-#                   file       : cmos_9.rds
-#                   version    : 10
-#                   last modif : Nov 4, 1999
-#
-##-------------------------------------------------------------------
-# Symbolic to micron on a 'one lambda equals one micron' basis
-##-------------------------------------------------------------------
-# Refer to the documentation for more precise information.
-#=====================================================================
-# 99/11/3 ALU5/6 rules
-# . theses rules are preliminary rules, we hope that they wil change
-#   in future. For now, ALU5/6 are dedicated to supplies an clock.
-# 
-# 99/3/22 new symbolics rules
-# . ALU1 width remains 1, ALU2/3/4 is 2
-# . ALU1/2/3/4 distance (edge to edge) is now 3 for all
-# . GATE to GATE distance is 3 but POLY wire to POLY wire remains 2
-# . All via stacking are allowed
-#
-# 98/12/1 drc rules were updated
-# distance VIA to POLY or gate is one rather 2
-# VIA2 and ALU3 appeared
-# . ALU3 width is 3
-# . ALU2/VIA2/ALU3 is resp. 3/1/3
-# . ALU3 edge distance is 2
-# . stacked VIA/VIA2 is allowed
-# . if they are not stacked they must distant of 2
-# . CONT/VIA2 is free
-# note
-# . stacked CONT/VIA is always not allowed
-# NWELL is automatically drawn with the DIFN and NTIE layers
-#=====================================================================
-
-##-------------------------------------------------------------------
-# PHYSICAL_GRID :
-##-------------------------------------------------------------------
-
-DEFINE  PHYSICAL_GRID  .5
-
-##-------------------------------------------------------------------
-# LAMBDA : 
-##-------------------------------------------------------------------
-
-DEFINE  LAMBDA         1
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_SEGMENT :
-#
-# MBK      RDS layer 1                 RDS layer 2         
-# name     name TRANS DLR DWR OFFSET   name TRANS DLR DWR OFFSET  ...
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_SEGMENT
-
-  PWELL    RDS_PWELL  VW  0.0  0.0  0.0  EXT
-  NWELL    RDS_NWELL  VW  0.0  0.0  0.0  ALL
-  NDIF     RDS_NDIF   VW  0.5  0.0  0.0  ALL
-  PDIF     RDS_PDIF   VW  0.5  0.0  0.0  ALL \
-           RDS_NWELL  VW  1.0  1.0  0.0  ALL
-  NTIE     RDS_NTIE   VW  0.5  0.0  0.0  ALL \
-           RDS_NWELL  VW  1.0  1.0  0.0  ALL
-  PTIE     RDS_PTIE   VW  0.5  0.0  0.0  ALL
-  NTRANS   RDS_POLY   VW  0.0  0.0  0.0  ALL \
-           RDS_NDIF  LCW -1.5  2.0  0.0  EXT \
-           RDS_NDIF  RCW -1.5  2.0  0.0  EXT \
-           RDS_NDIF   VW -1.5  4.0  0.0  DRC \
-	   RDS_PWELL  VW -1.5  0.0  0.0  EXT
-
-  PTRANS   RDS_POLY   VW  0.0  0.0  0.0  ALL \
-           RDS_PDIF  LCW -1.5  2.0  0.0  EXT \
-           RDS_PDIF  RCW -1.5  2.0  0.0  EXT \
-           RDS_PDIF   VW -1.5  4.0  0.0  DRC \
-           RDS_NWELL  VW -1.0  5.0  0.0  ALL 
-  POLY     RDS_POLY   VW  0.5  0.0  0.0  ALL
-  ALU1     RDS_ALU1   VW  0.5  0.0  0.0  ALL
-  ALU2     RDS_ALU2   VW  1.0  0.0  0.0  ALL
-  ALU3     RDS_ALU3   VW  1.0  0.0  0.0  ALL
-  ALU4     RDS_ALU4   VW  1.0  0.0  0.0  ALL
-  ALU5     RDS_ALU5   VW  1.0  0.0  0.0  ALL 
-  ALU6     RDS_ALU6   VW  1.0  0.0  0.0  ALL 
-  TPOLY    RDS_TPOLY  VW  0.5  0.0  0.0  ALL
-  TALU1    RDS_TALU1  VW  0.5  0.0  0.0  ALL
-  TALU2    RDS_TALU2  VW  1.0  0.0  0.0  ALL
-  TALU3    RDS_TALU3  VW  1.0  0.0  0.0  ALL
-  TALU4    RDS_TALU4  VW  1.0  0.0  0.0  ALL
-  TALU5    RDS_TALU5  VW  1.0  0.0  0.0  ALL
-  TALU6    RDS_TALU6  VW  1.0  0.0  0.0  ALL
-
-END
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_CONNECTOR :
-#
-# MBK      RDS layer 
-# name     name     DER DWR 
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_CONNECTOR
-
-  POLY    RDS_POLY  .5  0  
-  ALU1    RDS_ALU1  .5  0  
-  ALU2    RDS_ALU2 1.0  0  
-  ALU3    RDS_ALU3 1.0  0  
-  ALU4    RDS_ALU4 1.0  0  
-  ALU5    RDS_ALU4 1.0  0  
-  ALU6    RDS_ALU4 1.0  0  
-
-END
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_REFERENCE :
-#
-# MBK ref    RDS layer 
-# name       name       width
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_REFERENCE
-
-  REF_REF    RDS_REF    1
-  REF_CON    RDS_VALU1  2  RDS_TVIA1 1  RDS_TALU2  2
-
-END
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_VIA1 :
-#
-# MBK via      RDS layer 1  RDS  layer 2  RDS  layer 3  RDS layer 4      
-# name         name  width  name   width  name   width  name  width  
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_VIA
-
-  CONT_BODY_P  RDS_ALU1 2 ALL  RDS_CONT 1 ALL  RDS_PTIE 3 ALL  
-  CONT_BODY_N  RDS_ALU1 2 ALL  RDS_CONT 1 ALL  RDS_NTIE 3 ALL  RDS_NWELL 4 ALL
-  CONT_DIF_N   RDS_ALU1 2 ALL  RDS_CONT 1 ALL  RDS_NDIF 3 ALL
-  CONT_DIF_P   RDS_ALU1 2 ALL  RDS_CONT 1 ALL  RDS_PDIF 3 ALL  RDS_NWELL 4 ALL
-  CONT_POLY    RDS_ALU1 2 ALL  RDS_CONT 1 ALL  RDS_POLY 3 ALL
-  CONT_VIA     RDS_ALU1 2 ALL  RDS_VIA1 1 ALL  RDS_ALU2 2 ALL
-  CONT_VIA2    RDS_ALU2 2 ALL  RDS_VIA2 1 ALL  RDS_ALU3 2 ALL
-  CONT_VIA3    RDS_ALU3 2 ALL  RDS_VIA3 1 ALL  RDS_ALU4 2 ALL
-  CONT_VIA4    RDS_ALU4 2 ALL  RDS_VIA4 1 ALL  RDS_ALU5 2 ALL
-  CONT_VIA5    RDS_ALU5 2 ALL  RDS_VIA5 1 ALL  RDS_ALU6 2 ALL
-  C_X_N        RDS_POLY 1 ALL  RDS_NDIF 5 ALL
-  C_X_P        RDS_POLY 1 ALL  RDS_PDIF 5 ALL  RDS_NWELL 6 ALL
-
-END
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_BIGVIA_HOLE :
-#
-# MBK via      RDS Hole        
-# name         name  side step mode
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_BIGVIA_HOLE
-
-# CONT_VIA  RDS_VIA1 1 2 ALL
-
-END
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_BIGVIA_METAL :
-#
-# MBK via      RDS layer 1                      ...
-# name         name  delta-width overlap mode
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_BIGVIA_METAL
-
-# CONT_VIA  RDS_ALU1 3 4 ALL RDS_ALU2 4 5 ALL
-
-END 
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_TURNVIA :
-#
-# MBK via      RDS layer 1                      ...
-# name         name  delta-width overlap mode
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_TURNVIA
-
-# CONT_TURN1 
-
-END
-
-
-##-------------------------------------------------------------------
-# TABLE LYNX_GRAPH :
-#
-# RDS layer   Rds layer 1   Rds layer 2    ...
-# name        name          name           ...
-##-------------------------------------------------------------------
-
-TABLE LYNX_GRAPH
-
-##---------------------------
-#
-# Modifie par L.Jacomme (Pb Bulk/Alim avec Lynx)
-# 23.11.99
-#
-# RDS_NWELL  RDS_NTIE   RDS_NWELL
-# RDS_PWELL  RDS_PTIE   RDS_PWELL
-# RDS_NDIF  RDS_CONT RDS_NDIF
-# RDS_PDIF  RDS_CONT RDS_PDIF
-# RDS_NTIE  RDS_CONT RDS_NTIE RDS_NWELL
-# RDS_PTIE  RDS_CONT RDS_PTIE RDS_PWELL
-
-  RDS_NDIF  RDS_CONT RDS_NDIF
-  RDS_PDIF  RDS_CONT RDS_PDIF
-  RDS_NTIE  RDS_CONT RDS_NTIE
-  RDS_PTIE  RDS_CONT RDS_PTIE
-
-  RDS_POLY  RDS_CONT RDS_POLY 
-  RDS_CONT  RDS_PDIF RDS_NDIF RDS_POLY RDS_PTIE  RDS_NTIE RDS_ALU1 RDS_CONT
-  RDS_ALU1  RDS_CONT RDS_VIA1 RDS_ALU1 RDS_VALU1 RDS_ALU1
-  RDS_VALU1 RDS_CONT RDS_VIA1 RDS_ALU1 RDS_VALU1
-  RDS_VIA1  RDS_ALU1 RDS_ALU2 RDS_VIA1
-  RDS_VIA2  RDS_ALU2 RDS_ALU3 RDS_VIA2
-  RDS_VIA3  RDS_ALU3 RDS_ALU4 RDS_VIA3
-  RDS_VIA4  RDS_ALU4 RDS_ALU5 RDS_VIA4
-  RDS_VIA5  RDS_ALU5 RDS_ALU6 RDS_VIA5
-  RDS_ALU2  RDS_VIA1 RDS_VIA2 RDS_ALU2 
-  RDS_ALU3  RDS_VIA2 RDS_VIA3 RDS_ALU3
-  RDS_ALU4  RDS_VIA3 RDS_VIA4 RDS_ALU4 
-  RDS_ALU5  RDS_VIA4 RDS_VIA5 RDS_ALU5 
-  RDS_ALU6  RDS_VIA5          RDS_ALU6 
-
-END
-
-##-------------------------------------------------------------------
-# TABLE LYNX_CAPA : 
-#
-# RDS layer   Surface capacitance  Perimetric capacitance
-# name        piF / Micron^2       piF / Micron 
-##-------------------------------------------------------------------
-
-TABLE LYNX_CAPA
-
-  RDS_POLY    1.00e-04    1.00e-04
-  RDS_ALU1    0.50e-04    0.90e-04
-  RDS_ALU2    0.25e-04    0.95e-04
-  RDS_ALU3    0.25e-04    0.95e-04
-  RDS_ALU4    0.25e-04    0.95e-04
-  RDS_ALU5    0.25e-04    0.95e-04
-  RDS_ALU6    0.25e-04    0.95e-04
-
-END
-
-##-------------------------------------------------------------------
-# TABLE LYNX_RESISTOR :
-#
-# RDS layer   Surface resistor
-# name        Ohm / Micron^2 
-##-------------------------------------------------------------------
-
-TABLE LYNX_RESISTOR
-
-  RDS_POLY    50.0
-  RDS_ALU1     0.1
-  RDS_ALU2     0.05
-  RDS_ALU3     0.05
-  RDS_ALU4     0.05
-  RDS_ALU5     0.05
-  RDS_ALU6     0.05
-
-END
-
-##-------------------------------------------------------------------
-# TABLE LYNX_TRANSISTOR : 
-#
-# MBK layer  Transistor Type  MBK via
-# name       name             name
-##-------------------------------------------------------------------
-
-TABLE LYNX_TRANSISTOR
-
-  NTRANS  NTRANS  C_X_N   RDS_POLY   RDS_NDIF  RDS_NDIF  RDS_PWELL
-  PTRANS  PTRANS  C_X_P   RDS_POLY   RDS_PDIF  RDS_PDIF  RDS_NWELL
-
-END
-
-##-------------------------------------------------------------------
-# TABLE LYNX_DIFFUSION :
-#
-# RDS layer  RDS layer
-# name       name    
-##-------------------------------------------------------------------
-
-TABLE LYNX_DIFFUSION
-END
-
-##-------------------------------------------------------------------
-# TABLE LYNX_BULK_IMPLICIT :
-#
-# RDS layer  Bulk type
-# name       EXPLICIT/IMPLICIT
-##-------------------------------------------------------------------
-
-TABLE LYNX_BULK_IMPLICIT
-
-##---------------------------
-#
-# Modifie par L.Jacomme (Pb Bulk/Alim avec Lynx)
-# 23.11.99
-#
-# NWELL  EXPLICIT
-# PWELL  IMPLICIT
-
-END
-
-
-
-##-------------------------------------------------------------------
-# TABLE S2R_OVERSIZE_DENOTCH :
-##-------------------------------------------------------------------
-
-TABLE S2R_OVERSIZE_DENOTCH 
-END
-
-##-------------------------------------------------------------------
-# TABLE S2R_BLOC_RING_WIDTH :
-##-------------------------------------------------------------------
-
-TABLE S2R_BLOC_RING_WIDTH
-END
-
-##-------------------------------------------------------------------
-# TABLE S2R_MINIMUM_LAYER_WIDTH :
-##-------------------------------------------------------------------
-
-TABLE S2R_MINIMUM_LAYER_WIDTH 
-
-  RDS_NWELL   4
-  RDS_PDIF    2
-  RDS_NTIE    2
-  RDS_PTIE    2
-  RDS_POLY    1
-  RDS_TPOLY   1
-  RDS_CONT    1
-  RDS_ALU1    1
-  RDS_TALU1   1
-  RDS_VIA1    1
-  RDS_ALU2    2
-  RDS_TALU2   2
-  RDS_VIA2    1
-  RDS_ALU3    2
-  RDS_TALU3   2
-  RDS_VIA3    1
-  RDS_ALU4    2
-  RDS_TALU4   2
-  RDS_VIA4    1
-  RDS_ALU5    2
-  RDS_TALU5   2
-  RDS_VIA5    1
-  RDS_ALU6    2
-  RDS_TALU6   2
-
-END
-
-##-------------------------------------------------------------------
-# TABLE CIF_LAYER :
-##-------------------------------------------------------------------
-
-TABLE CIF_LAYER
-
-  RDS_NWELL    LNWELL
-  RDS_NDIF     LNDIF
-  RDS_PDIF     LPDIF
-  RDS_NTIE     LNTIE
-  RDS_PTIE     LPTIE
-  RDS_POLY     LPOLY
-  RDS_TPOLY    LTPOLY
-  RDS_CONT     LCONT
-  RDS_ALU1     LALU1
-  RDS_VALU1    LVALU1
-  RDS_TALU1    LTALU1
-  RDS_VIA1     LVIA
-  RDS_TVIA1    LTVIA1
-  RDS_ALU2     LALU2
-  RDS_TALU2    LTALU2
-  RDS_VIA2     LVIA2
-  RDS_ALU3     LALU3
-  RDS_TALU3    LTALU3
-  RDS_VIA3     LVIA3
-  RDS_ALU4     LALU4
-  RDS_TALU4    LTALU4
-  RDS_VIA4     LVIA4
-  RDS_ALU5     LALU5
-  RDS_TALU5    LTALU5
-  RDS_VIA5     LVIA5
-  RDS_ALU6     LALU6
-  RDS_TALU6    LTALU6
-  RDS_REF      LREF
-
-END
-
-##-------------------------------------------------------------------
-# TABLE GDS_LAYER :
-##-------------------------------------------------------------------
-
-TABLE GDS_LAYER
-
-  RDS_NWELL    1
-  RDS_NDIF     3
-  RDS_PDIF     4
-  RDS_NTIE     5
-  RDS_PTIE     6
-  RDS_POLY     7
-  RDS_TPOLY    9
-  RDS_CONT    10
-  RDS_ALU1    11
-  RDS_VALU1   12
-  RDS_TALU1   13
-  RDS_VIA1    14
-  RDS_TVIA1   15
-  RDS_ALU2    16
-  RDS_TALU2   17
-  RDS_VIA2    18
-  RDS_ALU3    19
-  RDS_TALU3   20
-  RDS_VIA3    21
-  RDS_ALU4    22
-  RDS_TALU4   23
-  RDS_VIA4    25
-  RDS_ALU5    26
-  RDS_TALU5   27
-  RDS_VIA5    28
-  RDS_ALU6    29
-  RDS_TALU6   30
-  RDS_REF     24
-
-END
-
-##-------------------------------------------------------------------
-# TABLE S2R_POST_TREAT :
-##-------------------------------------------------------------------
-
-TABLE S2R_POST_TREAT
-
-END
-DRC_RULES
-
-layer RDS_NWELL 4.;
-layer RDS_NTIE 2.;
-layer RDS_PTIE 2.;
-layer RDS_NDIF 2.;
-layer RDS_PDIF 2.;
-layer RDS_CONT 1.;
-layer RDS_VIA1 1.;
-layer RDS_VIA2 1.;
-layer RDS_VIA3 1.;
-layer RDS_VIA4 1.;
-layer RDS_VIA5 1.;
-layer RDS_POLY 1.;
-layer RDS_ALU1 1.;
-layer RDS_ALU2 2.;
-layer RDS_ALU3 2.;
-layer RDS_ALU4 2.;
-layer RDS_ALU5 2.;
-layer RDS_ALU6 2.;
-layer RDS_USER0 1.;
-layer RDS_USER1 1.;
-layer RDS_USER2 1.;
-
-regles
-
-# Note : ``min'' is different from ``>=''. 
-# min is applied on polygons and >= is applied on rectangles.
-# There is the same difference between max and <=.
-# >= is faster than min, but min must be used where it is
-# required to consider polygons, for example distance of
-# two objects in the same layer 
-#
-# There is no rule to check NTIE and PDIF are included in NWELL
-# since this is necessarily true
-#----------------------------------------------------------- 
-
-# Check the NWELL shapes
-#-----------------------
-caracterise RDS_NWELL (
-  regle 1 : largeur >= 4. ;
-  regle 2 : longueur_inter min 4. ;
-  regle 3 : notch >= 12. ;
-);
-relation RDS_NWELL , RDS_NWELL (
-  regle 4 : distance axiale min 12. ;
-);
-
-# Check RDS_PTIE is really excluded outside NWELL
-#------------------------------------------------
-relation RDS_PTIE , RDS_NWELL (
-  regle 5 : distance axiale >= 7.5;
-  regle 6 : enveloppe longueur_inter < 0. ;
-  regle 7 : marge longueur_inter < 0. ;
-  regle 8 : croix longueur_inter < 0. ;
-  regle 9 : intersection longueur_inter < 0. ;
-  regle 10 : extension longueur_inter < 0. ;
-  regle 11 : inclusion longueur_inter < 0. ;
-);
-
-# Check RDS_NDIF is really excluded outside NWELL
-#------------------------------------------------
-relation RDS_NDIF , RDS_NWELL (
-  regle 12 : distance axiale >= 7.5;
-  regle 13 : enveloppe longueur_inter < 0. ;
-  regle 14 : marge longueur_inter < 0. ;
-  regle 15 : croix longueur_inter < 0. ;
-  regle 16 : intersection longueur_inter < 0. ;
-  regle 17 : extension longueur_inter < 0. ;
-  regle 18 : inclusion longueur_inter < 0. ;
-);
-
-# Check the RDS_PDIF shapes
-#--------------------------
-caracterise RDS_PDIF (
-  regle 19 : largeur >= 2. ;
-  regle 20 : longueur_inter min 2. ;
-  regle 21 : notch >= 2. ;
-);
-relation RDS_PDIF , RDS_PDIF (
-  regle 22 : distance axiale min 3. ;
-);
-
-# Check the RDS_NDIF shapes
-#--------------------------
-caracterise RDS_NDIF (
-  regle 23 : largeur >= 2. ;
-  regle 24 : longueur_inter min 2. ;
-  regle 25 : notch >= 2. ;
-);
-relation RDS_NDIF , RDS_NDIF (
-  regle 26 : distance axiale min 3. ;
-);
-
-# Check the RDS_PTIE shapes
-#--------------------------
-caracterise RDS_PTIE (
-  regle 27 : largeur >= 2. ;
-  regle 28 : longueur_inter min 2. ;
-  regle 29 : notch >= 2. ;
-);
-relation RDS_PTIE , RDS_PTIE (
-  regle 30 : distance axiale min 3. ;
-);
-
-# Check the RDS_NTIE shapes
-#--------------------------
-caracterise RDS_NTIE (
-  regle 31 : largeur >= 2. ;
-  regle 32 : longueur_inter min 2. ;
-  regle 33 : notch >= 2. ;
-);
-relation RDS_NTIE , RDS_NTIE (
-  regle 34 : distance axiale min 3. ;
-);
-
-define RDS_PDIF , RDS_PTIE union -> ANY_P_DIF;
-define RDS_NDIF , RDS_NTIE union -> ANY_N_DIF;
-
-# Check the ANY_N_DIF ANY_P_DIFF exclusion
-#--------------------------------------
-relation ANY_N_DIF , ANY_P_DIF (
-  regle 35 : distance axiale >= 3. ;
-  regle 36 : enveloppe longueur_inter < 0. ;
-  regle 37 : marge longueur_inter < 0. ;
-  regle 38 : croix longueur_inter < 0. ;
-  regle 39 : intersection longueur_inter < 0. ;
-  regle 40 : extension longueur_inter < 0. ;
-  regle 41 : inclusion longueur_inter < 0. ;
-);
-
-# Check RDS_POLY is distant from ANY_DIF
-#---------------------------------------
-relation RDS_POLY , ANY_P_DIF (
-  regle 42 : distance axiale >= 1. ;
-);
-relation RDS_POLY , ANY_N_DIF (
-  regle 43 : distance axiale >= 1. ;
-);
-
-undefine ANY_P_DIF;
-undefine ANY_N_DIF;
-
-define RDS_NDIF , RDS_PDIF union -> NP_DIF;
-define NP_DIF , RDS_POLY intersection -> CHANNEL;
-
-# Check the RDS_POLY shapes
-#--------------------------
-caracterise RDS_POLY (
-  regle 44 : largeur >= 1. ;
-  regle 45 : longueur_inter min 1. ;
-  regle 46 : notch >= 2. ;
-);
-relation RDS_POLY , RDS_POLY (
-  regle 47 : distance axiale min 2.;
-);
-
-# Check the CHANNEL shapes
-#--------------------------
-caracterise CHANNEL (
-  regle 48 : notch >= 3. ;
-);
-relation CHANNEL , CHANNEL (
-  regle 49 : distance axiale min 3.;
-);
-
-# Check the RDS_POLY distance
-#----------------------------
-relation RDS_POLY , RDS_POLY (
-  regle 50 : distance axiale min 2.;
-);
-
-undefine CHANNEL;
-
-define NP_DIF , RDS_CONT intersection -> CONT_DIFF;
-relation RDS_POLY , CONT_DIFF (
-  regle 79 : distance axiale >= 2. ;
-);
-
-undefine CONT_DIFF;
-undefine NP_DIF;
-
-
-# Check RDS_ALU1 shapes
-#----------------------
-caracterise RDS_ALU1 (
-  regle 51 : largeur >= 1. ;
-  regle 52 : longueur_inter min 1. ;
-  regle 53 : notch >= 3. ;
-);
-relation RDS_ALU1 , RDS_ALU1 (
-  regle 54 : distance axiale min 3. ;
-);
-
-# Check RDS_ALU2 shapes
-#----------------------
-caracterise RDS_ALU2 (
-  regle 55 : largeur >= 2. ;
-  regle 56 : longueur_inter min 2. ;
-  regle 57 : notch >= 3. ;
-);
-relation RDS_ALU2 , RDS_ALU2 (
-  regle 58 : distance axiale min 3. ;
-);
-
-# Check RDS_ALU3 shapes
-#----------------------
-caracterise RDS_ALU3 (
-  regle 59 : largeur >= 2. ;
-  regle 60 : longueur_inter min 2. ;
-  regle 61 : notch >= 3. ;
-);
-relation RDS_ALU3 , RDS_ALU3 (
-  regle 62 : distance axiale min 3. ;
-);
-
-# Check RDS_ALU4 shapes
-#----------------------
-caracterise RDS_ALU4 (
-  regle 63 : largeur >= 2. ;
-  regle 64 : longueur_inter min 2. ;
-  regle 65 : notch >= 3. ;
-);
-relation RDS_ALU4 , RDS_ALU4 (
-  regle 66 : distance axiale min 3. ;
-);
-
-# Check RDS_ALU5 shapes
-#----------------------
-caracterise RDS_ALU5 (
-  regle 80 : largeur >= 2. ;
-  regle 81 : longueur_inter min 2. ;
-  regle 82 : notch >= 8. ;
-);
-relation RDS_ALU5 , RDS_ALU5 (
-  regle 83 : distance axiale min 8. ;
-);
-
-# Check RDS_ALU6 shapes
-#----------------------
-caracterise RDS_ALU6 (
-  regle 84 : largeur >= 2. ;
-  regle 85 : longueur_inter min 2. ;
-  regle 86 : notch >= 12. ;
-);
-relation RDS_ALU6 , RDS_ALU6 (
-  regle 87 : distance axiale min 12. ;
-);
-
-# Check ANY_VIA layers, stacking are free
-#----------------------------------------
-relation RDS_CONT , RDS_CONT (
-  regle 67 : distance axiale >= 3. ;
-);
-relation RDS_VIA , RDS_VIA (
-  regle 68 : distance axiale >= 4. ;
-);
-relation RDS_VIA2 , RDS_VIA2 (
-  regle 69 : distance axiale >= 4. ;
-);
-relation RDS_VIA3 , RDS_VIA3 (
-  regle 70 : distance axiale >= 4. ;
-);
-relation RDS_VIA4 , RDS_VIA4 (
-  regle 88 : distance axiale >= 5. ;
-);
-relation RDS_VIA5 , RDS_VIA5 (
-  regle 89 : distance axiale >= 5. ;
-);
-caracterise RDS_CONT (
-  regle 71 : largeur >= 1. ;
-  regle 72 : longueur <= 1. ;
-);
-caracterise RDS_VIA (
-  regle 73 : largeur >= 1. ;
-  regle 74 : longueur <= 1. ;
-);
-caracterise RDS_VIA2 (
-  regle 75 : largeur >= 1. ;
-  regle 76 : longueur <= 1. ;
-);
-caracterise RDS_VIA3 (
-  regle 77 : largeur >= 1. ;
-  regle 78 : longueur <= 1. ;
-);
-caracterise RDS_VIA4 (
-  regle 90 : largeur >= 1. ;
-  regle 91 : longueur <= 1. ;
-);
-caracterise RDS_VIA5 (
-  regle 92 : largeur >= 1. ;
-  regle 93 : longueur <= 1. ;
-);
-
-fin regles
-DRC_COMMENT
-1 (RDS_NWELL) minimum width 4. 
-2 (RDS_NWELL) minimum width 4. 
-3 (RDS_NWELL) Manhatan distance min 12. 
-4 (RDS_NWELL,RDS_NWELL) Manhatan distance min 12. 
-5 (RDS_PTIE,RDS_NWELL) Manhatan distance min 7.5
-6 (RDS_PTIE,RDS_NWELL) must never been in contact
-7 (RDS_PTIE,RDS_NWELL) must never been in contact
-8 (RDS_PTIE,RDS_NWELL) must never been in contact
-9 (RDS_PTIE,RDS_NWELL) must never been in contact
-10 (RDS_PTIE,RDS_NWELL) must never been in contact
-11 (RDS_PTIE,RDS_NWELL) must never been in contact
-12 (RDS_NDIF,RDS_NWELL) Manhatan distance min 7.5
-13 (RDS_NDIF,RDS_NWELL) must never been in contact
-14 (RDS_NDIF,RDS_NWELL) must never been in contact
-15 (RDS_NDIF,RDS_NWELL) must never been in contact
-16 (RDS_NDIF,RDS_NWELL) must never been in contact
-17 (RDS_NDIF,RDS_NWELL) must never been in contact
-18 (RDS_NDIF,RDS_NWELL) must never been in contact
-19 (RDS_PDIF) minimum width 2. 
-20 (RDS_PDIF) minimum width 2. 
-21 (RDS_PDIF) Manhatan distance min 2. 
-22 (RDS_PDIF,RDS_PDIF) Manhatan distance min 3. 
-23 (RDS_NDIF) minimum width 2. 
-24 (RDS_NDIF) minimum width 2. 
-25 (RDS_NDIF) Manhatan distance min 2. 
-26 (RDS_NDIF,RDS_NDIF) Manhatan distance min 3. 
-27 (RDS_PTIE) minimum width 2. 
-28 (RDS_PTIE) minimum width 2. 
-29 (RDS_PTIE) Manhatan distance min 2. 
-30 (RDS_PTIE,RDS_PTIE) Manhatan distance min 3. 
-31 (RDS_NTIE) minimum width 2. 
-32 (RDS_NTIE) minimum width 2. 
-33 (RDS_NTIE) Manhatan distance min 2. 
-34 (RDS_NTIE,RDS_NTIE) Manhatan distance min 3. 
-35 (ANY_N_DIF,ANY_P_DIF) Manhatan distance min 3. 
-36 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-37 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-38 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-39 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-40 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-41 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-42 (RDS_POLY,ANY_N_DIF) Manhatan distance min 1. 
-43 (RDS_POLY,ANY_P_DIF) Manhatan distance min 1. 
-44 (RDS_POLY) minimum width 1. 
-45 (RDS_POLY) minimum width 1. 
-46 (RDS_POLY) Manhatan distance min 2. 
-47 (RDS_POLY,RDS_POLY) Manhatan distance min 2.
-48 (CHANNEL) Manhatan distance min 3. 
-49 (CHANNEL,CHANNEL) Manhatan distance min 3.
-50 (RDS_POLY,RDS_POLY) Manhatan distance min 2.
-51 (RDS_ALU1) minimum width 1. 
-52 (RDS_ALU1) minimum width 1. 
-53 (RDS_ALU1) Manhatan distance min 3.
-54 (RDS_ALU1,RDS_ALU1) Manhatan distance min 3.
-55 (RDS_ALU2) minimum width 2. 
-56 (RDS_ALU2) minimum width 2. 
-57 (RDS_ALU2) Manhatan distance min 3. 
-58 (RDS_ALU2,RDS_ALU2) Manhatan distance min 3. 
-59 (RDS_ALU3) minimum width 2. 
-60 (RDS_ALU3) minimum width 2. 
-61 (RDS_ALU3) Manhatan distance min 3. 
-62 (RDS_ALU3,RDS_ALU3) Manhatan distance min 3. 
-63 (RDS_ALU4) minimum width 2. 
-64 (RDS_ALU4) minimum width 2. 
-65 (RDS_ALU4) Manhatan distance min 3. 
-66 (RDS_ALU4,RDS_ALU4) Manhatan distance min 3. 
-67 (RDS_CONT,RDS_CONT) Manhatan distance min 3. 
-68 (RDS_VIA,RDS_VIA) Manhatan distance min 4. 
-69 (RDS_VIA2,RDS_VIA2) Manhatan distance min 4. 
-70 (RDS_VIA3,RDS_VIA3) Manhatan distance min 4. 
-71 (RDS_CONT) minimum width 1. 
-72 (RDS_CONT) maximum length 1. 
-73 (RDS_VIA) minimum width 1. 
-74 (RDS_VIA) maximum length 1. 
-75 (RDS_VIA2) minimum width 1. 
-76 (RDS_VIA2) maximum length 1. 
-77 (RDS_VIA3) minimum width 1. 
-78 (RDS_VIA3) maximum length 1. 
-79 (RDS_POLY,CONT_DIFF) Manhatan distance min 2. 
-80 (RDS_ALU5) minimum width 2. 
-81 (RDS_ALU5) minimum width 2. 
-82 (RDS_ALU5) Manhatan distance min 8. 
-83 (RDS_ALU5,RDS_ALU5) Manhatan distance min 8. 
-84 (RDS_ALU6) minimum width 2. 
-85 (RDS_ALU6) minimum width 2. 
-86 (RDS_ALU6) Manhatan distance min 12. 
-87 (RDS_ALU6,RDS_ALU6) Manhatan distance min 12. 
-88 (RDS_VIA4,RDS_VIA4) Manhatan distance min 5. 
-89 (RDS_VIA5,RDS_VIA5) Manhatan distance min 5. 
-90 (RDS_VIA4) minimum width 1. 
-91 (RDS_VIA4) maximum length 1. 
-92 (RDS_VIA5) minimum width 1. 
-93 (RDS_VIA5) maximum length 1. 
-END_DRC_COMMENT
-END_DRC_RULES
diff --git a/alliance/share/etc/cmos_11.genview b/alliance/share/etc/cmos_11.genview
deleted file mode 100644
index 2c20f648..00000000
--- a/alliance/share/etc/cmos_11.genview
+++ /dev/null
@@ -1,190 +0,0 @@
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Title      :      Parameters File for Genview               |
-# |                                                             |
-# | Technology :               Cmos                             |
-# |                                                             |
-# | Date       :             17.08.95                           |
-# |                                                             |
-# \------------------------------------------------------------*/
-# /*------------------------------------------------------------\
-# |                                                             |
-# |               Genview Peek Bound in lambda                  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GENVIEW_PEEK_BOUND 7
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                       Segment name                          |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GENVIEW_SEGMENT_NAME
-
-  NWELL    Nwell
-  PWELL    Pwell
-  NDIF     Ndif
-  PDIF     Pdif
-  NTIE     Ntie
-  PTIE     Ptie
-  POLY     Poly
-  ALU1     Alu1
-  ALU2     Alu2
-  ALU3     Alu3
-  ALU4     Alu4
-  ALU5     Alu5
-  ALU6     Alu6
-  TPOLY    Tpoly
-  TALU1    Talu1
-  TALU2    Talu2
-  TALU3    Talu3
-  TALU4    Talu4
-  TALU5    Talu5
-  TALU6    Talu6
-  CALU1    CAlu1
-  CALU2    CAlu2
-  CALU3    CAlu3
-  CALU4    CAlu4
-  CALU5    CAlu5
-  CALU6    CAlu6
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                     Connector Name                          |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GENVIEW_CONNECTOR_NAME
-
-  POLY     Poly
-  ALU1     Alu1
-  ALU2     Alu2
-  ALU3     Alu3
-  ALU4     Alu4
-  ALU5     Alu5
-  ALU6     Alu6
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                      Reference Name                         |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GENVIEW_REFERENCE_NAME
-
-  REF_REF  Ref_Ref
-  REF_CON  Ref_Con
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                          Via Name                           |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GENVIEW_VIA_NAME
-
-  CONT_DIF_N   Cont_NDif
-  CONT_DIF_P   Cont_PDif
-  CONT_BODY_N  Cont_NTie
-  CONT_BODY_P  Cont_PTie
-  CONT_POLY    Cont_Poly
-  CONT_VIA     Via_1-2
-  CONT_VIA2    Via_2-3
-  CONT_VIA3    Via_3-4
-  CONT_VIA4    Via_4-5
-  CONT_VIA5    Via_5-6
-  C_X_N        Cont_CxN
-  C_X_P        Cont_CxP
-  CONT_TURN1   Turn_Via_1
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                    Connector Orient Name                    |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GENVIEW_ORIENT_NAME 
-
-  NORTH  North
-  SOUTH  South
-  EAST   East 
-  WEST   West
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                          Symmetry Name                      |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GENVIEW_SYMMETRY_NAME
-
-  NOSYM No_Sym
-  SYM_X Sym_X
-  SYM_Y Sym_Y
-  SYMXY Sym_XY
-  ROT_P Rot_P
-  ROT_M Rot_M
-  SY_RP Sym_RP
-  SY_RM Sym_RM
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                   Rds Layer Name and Color                  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GENVIEW_RDS_LAYER_NAME
-
-  RDS_NWELL    Nwell   tan
-  RDS_PWELL    Pwell   light_yellow
-  RDS_NIMP     Nimp    forest_green
-  RDS_PIMP     Pimp    goldenrod
-  RDS_ACTIV    Activ   brown
-  RDS_NDIF     Ndif    lawn_green
-  RDS_PDIF     Pdif    yellow
-  RDS_NTIE     Ntie    spring_green
-  RDS_PTIE     Ptie    light_goldenrod
-  RDS_POLY     Poly    red
-  RDS_VPOLY    VPoly   coral
-  RDS_GATE     Gate    orange
-  RDS_TPOLY    Tpoly   hot_pink
-  RDS_CONT     Cont    dark_violet
-  RDS_TCONT    TCont   orchid
-  RDS_ALU1     Alu1    royal_blue
-  RDS_VALU1    VAlu1   sky_blue
-  RDS_TALU1    Talu1   royal_blue
-  RDS_VIA1     Via1    deep_sky_blue
-  RDS_TVIA1    TVia1   dodger_blue
-  RDS_ALU2     Alu2    cyan
-  RDS_TALU2    Talu2   turquoise
-  RDS_VIA2     Via2    deep_pink
-  RDS_ALU3     Alu3    light_pink
-  RDS_TALU3    Talu3   light_pink
-  RDS_VIA3     Via3    sea_green
-  RDS_ALU4     Alu4    green
-  RDS_TALU4    Talu4   green
-  RDS_VIA4     Via4    gold
-  RDS_ALU5     Alu5    yellow
-  RDS_TALU5    Talu5   yellow
-  RDS_VIA5     Via5    violet_red
-  RDS_ALU6     Alu6    violet
-  RDS_TALU6    Talu6   violet
-  RDS_CPAS     Cpas    gray
-  RDS_REF      Ref     coral
-  RDS_ABOX     Abox    pink
-
-END
diff --git a/alliance/share/etc/cmos_11.graal b/alliance/share/etc/cmos_11.graal
deleted file mode 100644
index 58645acf..00000000
--- a/alliance/share/etc/cmos_11.graal
+++ /dev/null
@@ -1,343 +0,0 @@
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Title      :      Parameters File for Graal                 |
-# |                                                             |
-# | Technology :              Cmos V7                           |
-# |                                                             |
-# | Date       :             27/06/95                           |
-# |                                                             |
-# \------------------------------------------------------------*/
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                 Graal Peek Bound in lambda                  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_PEEK_BOUND 7
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |               Lower Grid Step in pixel by lambda            |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_LOWER_GRID_STEP 10
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |          Lower Figure Text Step in pixel by lambda          |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_LOWER_FIGURE_STEP 1
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |         Lower Instance Text Step in pixel by lambda         |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_LOWER_INSTANCE_STEP 1
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |        Lower Connector Text Step in pixel by lambda         |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_LOWER_CONNECTOR_STEP 5
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |          Lower Segment Text Step in pixel by lambda         |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_LOWER_SEGMENT_STEP 7
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |         Lower Reference Text Step in pixel by lambda        |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_LOWER_REFERENCE_STEP 10
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                 Graal Cursor Color Name                     |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_CURSOR_COLOR_NAME  Gray
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                 Graal Cursor Size in pixel                  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_CURSOR_SIZE 10 
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |  Segment Panel Button Label, Foreground , Background Color  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_SEGMENT_NAME
-
-  NWELL    Nwell  tan              Black
-  PWELL    Pwell  light_yellow     Black
-  NDIF     Ndif   lawn_green       Black
-  PDIF     Pdif   yellow           Black
-  NTIE     Ntie   spring_green     Black
-  PTIE     Ptie   light_goldenrod  Black
-  POLY     Poly   red              Black
-  ALU1     Alu1   royal_blue       Black
-  ALU2     Alu2   Cyan             Black
-  ALU3     Alu3   light_pink       Black
-  ALU4     Alu4   green            Black
-  ALU5     Alu5   yellow           Black
-  ALU6     Alu6   violet           Black
-  TPOLY    Tpoly  hot_pink         Black
-  TALU1    Talu1  royal_blue       Black
-  TALU2    Talu2  turquoise        Black
-  TALU3    Talu3  light_pink       Black
-  TALU4    Talu4  green            Black
-  TALU5    Talu5  yellow           Black
-  TALU6    Talu6  violet           Black
-  CALU1    CAlu1  royal_blue       Black
-  CALU2    CAlu2  Cyan             Black
-  CALU3    CAlu3  light_pink       Black
-  CALU4    CAlu4  green            Black
-  CALU5    CAlu5  yellow           Black
-  CALU6    CAlu6  violet           Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Transistor Panel Button Label, Foreground, Background Color |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_TRANSISTOR_NAME
-
-  NTRANS   Ntrans lawn_green       Black
-  PTRANS   Ptrans yellow           Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Connector Panel Button Label, Foreground , Background Color |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_CONNECTOR_NAME
-
-  POLY     Poly   red              Black
-  ALU1     Alu1   royal_blue       Black
-  ALU2     Alu2   Cyan             Black
-  ALU3     Alu3   light_pink       Black
-  ALU4     Alu4   green            Black
-  ALU5     Alu5   yellow           Black
-  ALU6     Alu6   violet           Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |       Minimun Length and Width for a symbolic Segment       |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_SEGMENT_VALUE
-
-  NWELL    4   4
-  PWELL    4   4
-  NDIF     2   2
-  PDIF     2   2
-  NTIE     2   2
-  PTIE     2   2
-  NTRANS   1   4
-  PTRANS   1   4
-  POLY     1   1
-  ALU1     1   1
-  ALU2     2   2
-  ALU3     2   2
-  ALU4     2   2
-  ALU5     4   4
-  ALU6     4   4
-  TPOLY    1   1
-  TALU1    1   1
-  TALU2    2   2
-  TALU3    2   2
-  TALU4    2   2
-  TALU5    2   2
-  TALU6    2   2
-  CALU1    1   0
-  CALU2    2   0
-  CALU3    2   0
-  CALU4    2   0
-  CALU5    4   0
-  CALU6    4   0
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Reference Panel Button Label, Foreground, Background Color  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_REFERENCE_NAME
-
-  REF_REF  Ref_Ref red  Black
-  REF_CON  Ref_Con Cyan Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |     Via Panel Button Label, Foreground , Background Color   |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_VIA_NAME
-
-  CONT_DIF_N   Cont_NDif   lawn_green       Black
-  CONT_DIF_P   Cont_PDif   yellow           Black
-  CONT_BODY_N  Cont_NTie   spring_green     Black
-  CONT_BODY_P  Cont_PTie   light_goldenrod  Black
-  CONT_POLY    Cont_Poly   red              Black
-  CONT_VIA     Via_1-2     cyan             Black
-  CONT_VIA2    Via_2-3     light_pink       Black
-  CONT_VIA3    Via_3-4     green            Black
-  CONT_VIA4    Via_4-5     yellow           Black
-  CONT_VIA5    Via_5-6     violet           Black
-  C_X_N        Cont_CxN    orange           Black
-  C_X_P        Cont_CxP    orange           Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |  Big Via Panel Button Label, Foreground , Background Color  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_BIGVIA_NAME
-
-  CONT_VIA     Big_Via_1-2  cyan       Black
-  CONT_VIA2    Big_Via_2-3  light_pink Black
-  CONT_VIA3    Big_Via_3-4  green      Black
-
-  CONT_TURN1   Turn_Via_1   royal_blue Black
-  CONT_TURN2   Turn_Via_2   Cyan       Black
-  CONT_TURN3   Turn_Via_3   light_pink Black
-  CONT_TURN4   Turn_Via_4   green      Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |            Minimun Size for a symbolic Big Via              |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_BIGVIA_VALUE
-
-  CONT_VIA     2
-  CONT_VIA2    2
-  CONT_VIA3    2
-
-  CONT_TURN1   2
-  CONT_TURN2   2
-  CONT_TURN3   2
-  CONT_TURN4   2
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |   Orient Panel Button Label, Foreground , Background Color  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_ORIENT_NAME 
-
-  NORTH  North   lawn_green  Black
-  SOUTH  South   yellow      Black
-  EAST   East    tan         Black
-  WEST   West    red         Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Symmetry Panel Button Label, Foreground , Background Color  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_SYMMETRY_NAME
-
-  NOSYM No_Sym  LightBlue         Black
-  SYM_X Sym_X   turquoise         Black
-  SYM_Y Sym_Y   cyan              Black
-  SYMXY Sym_XY  LightCyan         Black
-  ROT_P Rot_P   MediumAquamarine  Black
-  ROT_M Rot_M   aquamarine        Black
-  SY_RP Sym_RP  green             Black
-  SY_RM Sym_RM  MediumSpringGreen Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# | View Layer Panel Button Label, Foreground, Background Color |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_RDS_LAYER_NAME
-
-  RDS_NWELL    Nwell   tan               Black
-  RDS_PWELL    Pwell   light_yellow      Black
-  RDS_NIMP     Nimp    forest_green      Black
-  RDS_PIMP     Pimp    goldenrod         Black
-  RDS_ACTIV    Activ   brown             Black
-  RDS_NDIF     Ndif    lawn_green        Black
-  RDS_PDIF     Pdif    yellow            Black
-  RDS_NTIE     Ntie    spring_green      Black
-  RDS_PTIE     Ptie    light_goldenrod   Black
-  RDS_POLY     Poly    red               Black
-  RDS_VPOLY    VPoly   coral             Black
-  RDS_GATE     Gate    orange            Black
-  RDS_TPOLY    Tpoly   hot_pink          Black
-  RDS_CONT     Cont    dark_violet       Black
-  RDS_TCONT    TCont   orchid            Black
-  RDS_ALU1     Alu1    royal_blue        Black
-  RDS_VALU1    VAlu1   sky_blue          Black
-  RDS_TALU1    Talu1   royal_blue        Black
-  RDS_VIA1     Via1    deep_sky_blue     Black
-  RDS_TVIA1    TVia1   dodger_blue       Black
-  RDS_ALU2     Alu2    cyan              Black
-  RDS_TALU2    Talu2   turquoise         Black
-  RDS_VIA2     Via2    deep_pink         Black
-  RDS_ALU3     Alu3    light_pink        Black
-  RDS_TALU3    Talu3   light_pink        Black
-  RDS_VIA3     Via3    sea_green         Black
-  RDS_ALU4     Alu4    green             Black
-  RDS_TALU4    Talu4   green             Black
-  RDS_VIA4     Via4    gold              Black
-  RDS_ALU5     Alu5    yellow            Black
-  RDS_TALU5    Talu5   yellow            Black
-  RDS_VIA5     Via5    violet_red        Black
-  RDS_ALU6     Alu6    violet            Black
-  RDS_TALU6    Talu6   violet            Black
-  RDS_CPAS     Cpas    gray              Black
-  RDS_REF      Ref     coral             Black
-  RDS_ABOX     Abox    pink              Black
-
-END
diff --git a/alliance/share/etc/cmos_11.rds b/alliance/share/etc/cmos_11.rds
deleted file mode 100644
index 2a3b4c9f..00000000
--- a/alliance/share/etc/cmos_11.rds
+++ /dev/null
@@ -1,854 +0,0 @@
-#=====================================================================
-#
-#                         ALLIANCE VLSI CAD                  
-#            (R)eal (D)ata (S)tructure parameter file
-#         (c) copyright 1992 Laboratory UPMC/MASI/CAO-VLSI   
-#                        all rights reserved                 
-#                   e-mail : cao-vlsi@masi.ibp.fr            
-#
-#                   file       : cmos_9.rds
-#                   version    : 10
-#                   last modif : Nov 4, 1999
-#
-##-------------------------------------------------------------------
-# Symbolic to micron on a 'one lambda equals one micron' basis
-##-------------------------------------------------------------------
-# Refer to the documentation for more precise information.
-#=====================================================================
-# 99/11/3 ALU5/6 rules
-# . theses rules are preliminary rules, we hope that they wil change
-#   in future. For now, ALU5/6 are dedicated to supplies an clock.
-# 
-# 99/3/22 new symbolics rules
-# . ALU1 width remains 1, ALU2/3/4 is 2
-# . ALU1/2/3/4 distance (edge to edge) is now 3 for all
-# . GATE to GATE distance is 3 but POLY wire to POLY wire remains 2
-# . All via stacking are allowed
-#
-# 98/12/1 drc rules were updated
-# distance VIA to POLY or gate is one rather 2
-# VIA2 and ALU3 appeared
-# . ALU3 width is 3
-# . ALU2/VIA2/ALU3 is resp. 3/1/3
-# . ALU3 edge distance is 2
-# . stacked VIA/VIA2 is allowed
-# . if they are not stacked they must distant of 2
-# . CONT/VIA2 is free
-# note
-# . stacked CONT/VIA is always not allowed
-# NWELL is automatically drawn with the DIFN and NTIE layers
-#=====================================================================
-
-##-------------------------------------------------------------------
-# PHYSICAL_GRID :
-##-------------------------------------------------------------------
-
-DEFINE  PHYSICAL_GRID  .5
-
-##-------------------------------------------------------------------
-# LAMBDA : 
-##-------------------------------------------------------------------
-
-DEFINE  LAMBDA         1
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_SEGMENT :
-#
-# MBK      RDS layer 1                 RDS layer 2         
-# name     name TRANS DLR DWR OFFSET   name TRANS DLR DWR OFFSET  ...
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_SEGMENT
-
-  PWELL    RDS_PWELL  VW  0.0  0.0  0.0  EXT
-  NWELL    RDS_NWELL  VW  0.0  0.0  0.0  ALL
-  NDIF     RDS_NDIF   VW  0.5  0.0  0.0  ALL
-  PDIF     RDS_PDIF   VW  0.5  0.0  0.0  ALL \
-           RDS_NWELL  VW  1.0  1.0  0.0  ALL
-  NTIE     RDS_NTIE   VW  0.5  0.0  0.0  ALL \
-           RDS_NWELL  VW  1.0  1.0  0.0  ALL
-  PTIE     RDS_PTIE   VW  0.5  0.0  0.0  ALL
-  NTRANS   RDS_POLY   VW  0.0  0.0  0.0  ALL \
-           RDS_NDIF  LCW -1.5  2.0  0.0  EXT \
-           RDS_NDIF  RCW -1.5  2.0  0.0  EXT \
-           RDS_NDIF   VW -1.5  4.0  0.0  DRC \
-	   RDS_PWELL  VW -1.5  0.0  0.0  EXT
-
-  PTRANS   RDS_POLY   VW  0.0  0.0  0.0  ALL \
-           RDS_PDIF  LCW -1.5  2.0  0.0  EXT \
-           RDS_PDIF  RCW -1.5  2.0  0.0  EXT \
-           RDS_PDIF   VW -1.5  4.0  0.0  DRC \
-           RDS_NWELL  VW -1.0  5.0  0.0  ALL 
-  POLY     RDS_POLY   VW  0.5  0.0  0.0  ALL
-  ALU1     RDS_ALU1   VW  0.5  0.0  0.0  ALL
-  ALU2     RDS_ALU2   VW  1.0  0.0  0.0  ALL
-  ALU3     RDS_ALU3   VW  1.0  0.0  0.0  ALL
-  ALU4     RDS_ALU4   VW  1.0  0.0  0.0  ALL
-  ALU5     RDS_ALU5   VW  1.0  0.0  0.0  ALL 
-  ALU6     RDS_ALU6   VW  1.0  0.0  0.0  ALL 
-  CALU1    RDS_ALU1   VW  0.5  0.0  0.0  ALL
-  CALU2    RDS_ALU2   VW  1.0  0.0  0.0  ALL
-  CALU3    RDS_ALU3   VW  1.0  0.0  0.0  ALL
-  CALU4    RDS_ALU4   VW  1.0  0.0  0.0  ALL
-  CALU5    RDS_ALU5   VW  1.0  0.0  0.0  ALL 
-  CALU6    RDS_ALU6   VW  1.0  0.0  0.0  ALL 
-  TPOLY    RDS_TPOLY  VW  0.5  0.0  0.0  ALL
-  TALU1    RDS_TALU1  VW  0.5  0.0  0.0  ALL
-  TALU2    RDS_TALU2  VW  1.0  0.0  0.0  ALL
-  TALU3    RDS_TALU3  VW  1.0  0.0  0.0  ALL
-  TALU4    RDS_TALU4  VW  1.0  0.0  0.0  ALL
-  TALU5    RDS_TALU5  VW  1.0  0.0  0.0  ALL
-  TALU6    RDS_TALU6  VW  1.0  0.0  0.0  ALL
-
-END
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_CONNECTOR :
-#
-# MBK      RDS layer 
-# name     name     DER DWR 
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_CONNECTOR
-
-  POLY    RDS_POLY  .5  0  
-  ALU1    RDS_ALU1  .5  0  
-  ALU2    RDS_ALU2 1.0  0  
-  ALU3    RDS_ALU3 1.0  0  
-  ALU4    RDS_ALU4 1.0  0  
-  ALU5    RDS_ALU4 1.0  0  
-  ALU6    RDS_ALU4 1.0  0  
-
-END
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_REFERENCE :
-#
-# MBK ref    RDS layer 
-# name       name       width
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_REFERENCE
-
-  REF_REF    RDS_REF    1
-  REF_CON    RDS_VALU1  2  RDS_TVIA1 1  RDS_TALU2  2
-
-END
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_VIA1 :
-#
-# MBK via      RDS layer 1  RDS  layer 2  RDS  layer 3  RDS layer 4      
-# name         name  width  name   width  name   width  name  width  
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_VIA
-
-  CONT_BODY_P  RDS_ALU1 2 ALL  RDS_CONT 1 ALL  RDS_PTIE 3 ALL  
-  CONT_BODY_N  RDS_ALU1 2 ALL  RDS_CONT 1 ALL  RDS_NTIE 3 ALL  RDS_NWELL 4 ALL
-  CONT_DIF_N   RDS_ALU1 2 ALL  RDS_CONT 1 ALL  RDS_NDIF 3 ALL
-  CONT_DIF_P   RDS_ALU1 2 ALL  RDS_CONT 1 ALL  RDS_PDIF 3 ALL  RDS_NWELL 4 ALL
-  CONT_POLY    RDS_ALU1 2 ALL  RDS_CONT 1 ALL  RDS_POLY 3 ALL
-  CONT_VIA     RDS_ALU1 2 ALL  RDS_VIA1 1 ALL  RDS_ALU2 2 ALL
-  CONT_VIA2    RDS_ALU2 2 ALL  RDS_VIA2 1 ALL  RDS_ALU3 2 ALL
-  CONT_VIA3    RDS_ALU3 2 ALL  RDS_VIA3 1 ALL  RDS_ALU4 2 ALL
-  CONT_VIA4    RDS_ALU4 2 ALL  RDS_VIA4 1 ALL  RDS_ALU5 2 ALL
-  CONT_VIA5    RDS_ALU5 2 ALL  RDS_VIA5 1 ALL  RDS_ALU6 2 ALL
-  C_X_N        RDS_POLY 1 ALL  RDS_NDIF 5 ALL
-  C_X_P        RDS_POLY 1 ALL  RDS_PDIF 5 ALL  RDS_NWELL 6 ALL
-
-END
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_BIGVIA_HOLE :
-#
-# MBK via      RDS Hole        
-# name         name  side step mode
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_BIGVIA_HOLE
-
-CONT_VIA   RDS_VIA1 1 3 ALL
-CONT_VIA2  RDS_VIA2 1 3 ALL
-CONT_VIA3  RDS_VIA3 1 3 ALL
-
-END
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_BIGVIA_METAL :
-#
-# MBK via      RDS layer 1                      ...
-# name         name  delta-width overlap mode
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_BIGVIA_METAL
-
-CONT_VIA  RDS_ALU1 0.0 0.5 ALL RDS_ALU2 0.0 0.5 ALL
-CONT_VIA2 RDS_ALU2 0.0 0.5 ALL RDS_ALU3 0.0 0.5 ALL
-CONT_VIA3 RDS_ALU3 0.0 0.5 ALL RDS_ALU4 0.0 0.5 ALL
-
-END 
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_TURNVIA :
-#
-# MBK via      RDS layer 1                      ...
-# name         name  DWR MODE
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_TURNVIA
-
-CONT_TURN1 RDS_ALU1 0 ALL
-CONT_TURN2 RDS_ALU2 0 ALL
-CONT_TURN3 RDS_ALU3 0 ALL
-CONT_TURN4 RDS_ALU4 0 ALL
-
-END
-
-
-##-------------------------------------------------------------------
-# TABLE LYNX_GRAPH :
-#
-# RDS layer   Rds layer 1   Rds layer 2    ...
-# name        name          name           ...
-##-------------------------------------------------------------------
-
-TABLE LYNX_GRAPH
-
-##---------------------------
-#
-# Modifie par L.Jacomme (Pb Bulk/Alim avec Lynx)
-# 23.11.99
-#
-# RDS_NWELL  RDS_NTIE   RDS_NWELL
-# RDS_PWELL  RDS_PTIE   RDS_PWELL
-# RDS_NDIF  RDS_CONT RDS_NDIF
-# RDS_PDIF  RDS_CONT RDS_PDIF
-# RDS_NTIE  RDS_CONT RDS_NTIE RDS_NWELL
-# RDS_PTIE  RDS_CONT RDS_PTIE RDS_PWELL
-
-  RDS_NDIF  RDS_CONT RDS_NDIF
-  RDS_PDIF  RDS_CONT RDS_PDIF
-  RDS_NTIE  RDS_CONT RDS_NTIE
-  RDS_PTIE  RDS_CONT RDS_PTIE
-
-  RDS_POLY  RDS_CONT RDS_POLY 
-  RDS_CONT  RDS_PDIF RDS_NDIF RDS_POLY RDS_PTIE  RDS_NTIE RDS_ALU1 RDS_CONT
-  RDS_ALU1  RDS_CONT RDS_VIA1 RDS_ALU1 RDS_VALU1 RDS_ALU1
-  RDS_VALU1 RDS_CONT RDS_VIA1 RDS_ALU1 RDS_VALU1
-  RDS_VIA1  RDS_ALU1 RDS_ALU2 RDS_VIA1
-  RDS_VIA2  RDS_ALU2 RDS_ALU3 RDS_VIA2
-  RDS_VIA3  RDS_ALU3 RDS_ALU4 RDS_VIA3
-  RDS_VIA4  RDS_ALU4 RDS_ALU5 RDS_VIA4
-  RDS_VIA5  RDS_ALU5 RDS_ALU6 RDS_VIA5
-  RDS_ALU2  RDS_VIA1 RDS_VIA2 RDS_ALU2 
-  RDS_ALU3  RDS_VIA2 RDS_VIA3 RDS_ALU3
-  RDS_ALU4  RDS_VIA3 RDS_VIA4 RDS_ALU4 
-  RDS_ALU5  RDS_VIA4 RDS_VIA5 RDS_ALU5 
-  RDS_ALU6  RDS_VIA5          RDS_ALU6 
-
-END
-
-##-------------------------------------------------------------------
-# TABLE LYNX_CAPA : 
-#
-# RDS layer   Surface capacitance  Perimetric capacitance
-# name        piF / Micron^2       piF / Micron 
-##-------------------------------------------------------------------
-
-TABLE LYNX_CAPA
-
-  RDS_POLY    1.00e-04    1.00e-04
-  RDS_ALU1    0.50e-04    0.90e-04
-  RDS_ALU2    0.25e-04    0.95e-04
-  RDS_ALU3    0.25e-04    0.95e-04
-  RDS_ALU4    0.25e-04    0.95e-04
-  RDS_ALU5    0.25e-04    0.95e-04
-  RDS_ALU6    0.25e-04    0.95e-04
-
-END
-
-##-------------------------------------------------------------------
-# TABLE LYNX_RESISTOR :
-#
-# RDS layer   Surface resistor
-# name        Ohm / Micron^2 
-##-------------------------------------------------------------------
-
-TABLE LYNX_RESISTOR
-
-  RDS_POLY    50.0
-  RDS_ALU1     0.1
-  RDS_ALU2     0.05
-  RDS_ALU3     0.05
-  RDS_ALU4     0.05
-  RDS_ALU5     0.05
-  RDS_ALU6     0.05
-
-END
-
-##-------------------------------------------------------------------
-# TABLE LYNX_TRANSISTOR : 
-#
-# MBK layer  Transistor Type  MBK via
-# name       name             name
-##-------------------------------------------------------------------
-
-TABLE LYNX_TRANSISTOR
-
-  NTRANS  NTRANS  C_X_N   RDS_POLY   RDS_NDIF  RDS_NDIF  RDS_PWELL
-  PTRANS  PTRANS  C_X_P   RDS_POLY   RDS_PDIF  RDS_PDIF  RDS_NWELL
-
-END
-
-##-------------------------------------------------------------------
-# TABLE LYNX_DIFFUSION :
-#
-# RDS layer  RDS layer
-# name       name    
-##-------------------------------------------------------------------
-
-TABLE LYNX_DIFFUSION
-END
-
-##-------------------------------------------------------------------
-# TABLE LYNX_BULK_IMPLICIT :
-#
-# RDS layer  Bulk type
-# name       EXPLICIT/IMPLICIT
-##-------------------------------------------------------------------
-
-TABLE LYNX_BULK_IMPLICIT
-
-##---------------------------
-#
-# Modifie par L.Jacomme (Pb Bulk/Alim avec Lynx)
-# 23.11.99
-#
-# NWELL  EXPLICIT
-# PWELL  IMPLICIT
-
-END
-
-
-
-##-------------------------------------------------------------------
-# TABLE S2R_OVERSIZE_DENOTCH :
-##-------------------------------------------------------------------
-
-TABLE S2R_OVERSIZE_DENOTCH 
-END
-
-##-------------------------------------------------------------------
-# TABLE S2R_BLOC_RING_WIDTH :
-##-------------------------------------------------------------------
-
-TABLE S2R_BLOC_RING_WIDTH
-END
-
-##-------------------------------------------------------------------
-# TABLE S2R_MINIMUM_LAYER_WIDTH :
-##-------------------------------------------------------------------
-
-TABLE S2R_MINIMUM_LAYER_WIDTH 
-
-  RDS_NWELL   4
-  RDS_PDIF    2
-  RDS_NTIE    2
-  RDS_PTIE    2
-  RDS_POLY    1
-  RDS_TPOLY   1
-  RDS_CONT    1
-  RDS_ALU1    1
-  RDS_TALU1   1
-  RDS_VIA1    1
-  RDS_ALU2    2
-  RDS_TALU2   2
-  RDS_VIA2    1
-  RDS_ALU3    2
-  RDS_TALU3   2
-  RDS_VIA3    1
-  RDS_ALU4    2
-  RDS_TALU4   2
-  RDS_VIA4    1
-  RDS_ALU5    2
-  RDS_TALU5   2
-  RDS_VIA5    1
-  RDS_ALU6    2
-  RDS_TALU6   2
-
-END
-
-##-------------------------------------------------------------------
-# TABLE CIF_LAYER :
-##-------------------------------------------------------------------
-
-TABLE CIF_LAYER
-
-  RDS_NWELL    LNWELL
-  RDS_NDIF     LNDIF
-  RDS_PDIF     LPDIF
-  RDS_NTIE     LNTIE
-  RDS_PTIE     LPTIE
-  RDS_POLY     LPOLY
-  RDS_TPOLY    LTPOLY
-  RDS_CONT     LCONT
-  RDS_ALU1     LALU1
-  RDS_VALU1    LVALU1
-  RDS_TALU1    LTALU1
-  RDS_VIA1     LVIA
-  RDS_TVIA1    LTVIA1
-  RDS_ALU2     LALU2
-  RDS_TALU2    LTALU2
-  RDS_VIA2     LVIA2
-  RDS_ALU3     LALU3
-  RDS_TALU3    LTALU3
-  RDS_VIA3     LVIA3
-  RDS_ALU4     LALU4
-  RDS_TALU4    LTALU4
-  RDS_VIA4     LVIA4
-  RDS_ALU5     LALU5
-  RDS_TALU5    LTALU5
-  RDS_VIA5     LVIA5
-  RDS_ALU6     LALU6
-  RDS_TALU6    LTALU6
-  RDS_REF      LREF
-
-END
-
-##-------------------------------------------------------------------
-# TABLE GDS_LAYER :
-##-------------------------------------------------------------------
-
-TABLE GDS_LAYER
-
-  RDS_NWELL    1
-  RDS_NDIF     3
-  RDS_PDIF     4
-  RDS_NTIE     5
-  RDS_PTIE     6
-  RDS_POLY     7
-  RDS_TPOLY    9
-  RDS_CONT    10
-  RDS_ALU1    11
-  RDS_VALU1   12
-  RDS_TALU1   13
-  RDS_VIA1    14
-  RDS_TVIA1   15
-  RDS_ALU2    16
-  RDS_TALU2   17
-  RDS_VIA2    18
-  RDS_ALU3    19
-  RDS_TALU3   20
-  RDS_VIA3    21
-  RDS_ALU4    22
-  RDS_TALU4   23
-  RDS_VIA4    25
-  RDS_ALU5    26
-  RDS_TALU5   27
-  RDS_VIA5    28
-  RDS_ALU6    29
-  RDS_TALU6   30
-  RDS_REF     24
-
-END
-
-##-------------------------------------------------------------------
-# TABLE S2R_POST_TREAT :
-##-------------------------------------------------------------------
-
-TABLE S2R_POST_TREAT
-
-END
-DRC_RULES
-
-layer RDS_NWELL 4.;
-layer RDS_NTIE 2.;
-layer RDS_PTIE 2.;
-layer RDS_NDIF 2.;
-layer RDS_PDIF 2.;
-layer RDS_CONT 1.;
-layer RDS_VIA1 1.;
-layer RDS_VIA2 1.;
-layer RDS_VIA3 1.;
-layer RDS_VIA4 1.;
-layer RDS_VIA5 1.;
-layer RDS_POLY 1.;
-layer RDS_ALU1 1.;
-layer RDS_ALU2 2.;
-layer RDS_ALU3 2.;
-layer RDS_ALU4 2.;
-layer RDS_ALU5 2.;
-layer RDS_ALU6 2.;
-layer RDS_USER0 1.;
-layer RDS_USER1 1.;
-layer RDS_USER2 1.;
-
-regles
-
-# Note : ``min'' is different from ``>=''. 
-# min is applied on polygons and >= is applied on rectangles.
-# There is the same difference between max and <=.
-# >= is faster than min, but min must be used where it is
-# required to consider polygons, for example distance of
-# two objects in the same layer 
-#
-# There is no rule to check NTIE and PDIF are included in NWELL
-# since this is necessarily true
-#----------------------------------------------------------- 
-
-# Check the NWELL shapes
-#-----------------------
-caracterise RDS_NWELL (
-  regle 1 : largeur >= 4. ;
-  regle 2 : longueur_inter min 4. ;
-  regle 3 : notch >= 12. ;
-);
-relation RDS_NWELL , RDS_NWELL (
-  regle 4 : distance axiale min 12. ;
-);
-
-# Check RDS_PTIE is really excluded outside NWELL
-#------------------------------------------------
-relation RDS_PTIE , RDS_NWELL (
-  regle 5 : distance axiale >= 7.5;
-  regle 6 : enveloppe longueur_inter < 0. ;
-  regle 7 : marge longueur_inter < 0. ;
-  regle 8 : croix longueur_inter < 0. ;
-  regle 9 : intersection longueur_inter < 0. ;
-  regle 10 : extension longueur_inter < 0. ;
-  regle 11 : inclusion longueur_inter < 0. ;
-);
-
-# Check RDS_NDIF is really excluded outside NWELL
-#------------------------------------------------
-relation RDS_NDIF , RDS_NWELL (
-  regle 12 : distance axiale >= 7.5;
-  regle 13 : enveloppe longueur_inter < 0. ;
-  regle 14 : marge longueur_inter < 0. ;
-  regle 15 : croix longueur_inter < 0. ;
-  regle 16 : intersection longueur_inter < 0. ;
-  regle 17 : extension longueur_inter < 0. ;
-  regle 18 : inclusion longueur_inter < 0. ;
-);
-
-# Check the RDS_PDIF shapes
-#--------------------------
-caracterise RDS_PDIF (
-  regle 19 : largeur >= 2. ;
-  regle 20 : longueur_inter min 2. ;
-  regle 21 : notch >= 2. ;
-);
-relation RDS_PDIF , RDS_PDIF (
-  regle 22 : distance axiale min 3. ;
-);
-
-# Check the RDS_NDIF shapes
-#--------------------------
-caracterise RDS_NDIF (
-  regle 23 : largeur >= 2. ;
-  regle 24 : longueur_inter min 2. ;
-  regle 25 : notch >= 2. ;
-);
-relation RDS_NDIF , RDS_NDIF (
-  regle 26 : distance axiale min 3. ;
-);
-
-# Check the RDS_PTIE shapes
-#--------------------------
-caracterise RDS_PTIE (
-  regle 27 : largeur >= 2. ;
-  regle 28 : longueur_inter min 2. ;
-  regle 29 : notch >= 2. ;
-);
-relation RDS_PTIE , RDS_PTIE (
-  regle 30 : distance axiale min 3. ;
-);
-
-# Check the RDS_NTIE shapes
-#--------------------------
-caracterise RDS_NTIE (
-  regle 31 : largeur >= 2. ;
-  regle 32 : longueur_inter min 2. ;
-  regle 33 : notch >= 2. ;
-);
-relation RDS_NTIE , RDS_NTIE (
-  regle 34 : distance axiale min 3. ;
-);
-
-define RDS_PDIF , RDS_PTIE union -> ANY_P_DIF;
-define RDS_NDIF , RDS_NTIE union -> ANY_N_DIF;
-
-# Check the ANY_N_DIF ANY_P_DIFF exclusion
-#--------------------------------------
-relation ANY_N_DIF , ANY_P_DIF (
-  regle 35 : distance axiale >= 3. ;
-  regle 36 : enveloppe longueur_inter < 0. ;
-  regle 37 : marge longueur_inter < 0. ;
-  regle 38 : croix longueur_inter < 0. ;
-  regle 39 : intersection longueur_inter < 0. ;
-  regle 40 : extension longueur_inter < 0. ;
-  regle 41 : inclusion longueur_inter < 0. ;
-);
-
-# Check RDS_POLY is distant from ANY_DIF
-#---------------------------------------
-relation RDS_POLY , ANY_P_DIF (
-  regle 42 : distance axiale >= 1. ;
-);
-relation RDS_POLY , ANY_N_DIF (
-  regle 43 : distance axiale >= 1. ;
-);
-
-undefine ANY_P_DIF;
-undefine ANY_N_DIF;
-
-define RDS_NDIF , RDS_PDIF union -> NP_DIF;
-define NP_DIF , RDS_POLY intersection -> CHANNEL;
-
-# Check the RDS_POLY shapes
-#--------------------------
-caracterise RDS_POLY (
-  regle 44 : largeur >= 1. ;
-  regle 45 : longueur_inter min 1. ;
-  regle 46 : notch >= 2. ;
-);
-relation RDS_POLY , RDS_POLY (
-  regle 47 : distance axiale min 2.;
-);
-
-# Check the CHANNEL shapes
-#--------------------------
-caracterise CHANNEL (
-  regle 48 : notch >= 2. ;
-);
-relation CHANNEL , CHANNEL (
-  regle 49 : distance axiale min 2.;
-);
-
-
-# Check the RDS_POLY distance
-#----------------------------
-relation RDS_POLY , RDS_POLY (
-  regle 50 : distance axiale min 2.;
-);
-
-undefine CHANNEL;
-
-define NP_DIF , RDS_CONT intersection -> CONT_DIFF;
-relation RDS_POLY , CONT_DIFF (
-  regle 79 : distance axiale >= 2. ;
-);
-
-undefine CONT_DIFF;
-undefine NP_DIF;
-
-
-# Check RDS_ALU1 shapes
-#----------------------
-caracterise RDS_ALU1 (
-  regle 51 : largeur >= 1. ;
-  regle 52 : longueur_inter min 1. ;
-  regle 53 : notch >= 2.5 ;
-);
-relation RDS_ALU1 , RDS_ALU1 (
-  regle 54 : distance axiale min 2.5 ;
-);
-
-# Check RDS_ALU2 shapes
-#----------------------
-caracterise RDS_ALU2 (
-  regle 55 : largeur >= 2. ;
-  regle 56 : longueur_inter min 2. ;
-  regle 57 : notch >= 2. ;
-);
-relation RDS_ALU2 , RDS_ALU2 (
-  regle 58 : distance axiale min 2. ;
-);
-
-# Check RDS_ALU3 shapes
-#----------------------
-caracterise RDS_ALU3 (
-  regle 59 : largeur >= 2. ;
-  regle 60 : longueur_inter min 2. ;
-  regle 61 : notch >= 3. ;
-);
-relation RDS_ALU3 , RDS_ALU3 (
-  regle 62 : distance axiale min 3. ;
-);
-
-# Check RDS_ALU4 shapes
-#----------------------
-caracterise RDS_ALU4 (
-  regle 63 : largeur >= 2. ;
-  regle 64 : longueur_inter min 2. ;
-  regle 65 : notch >= 3. ;
-);
-relation RDS_ALU4 , RDS_ALU4 (
-  regle 66 : distance axiale min 3. ;
-);
-
-# Check RDS_ALU5 shapes
-#----------------------
-caracterise RDS_ALU5 (
-  regle 80 : largeur >= 2. ;
-  regle 81 : longueur_inter min 2. ;
-  regle 82 : notch >= 12. ;
-);
-relation RDS_ALU5 , RDS_ALU5 (
-  regle 83 : distance axiale min 12. ;
-);
-
-# Check RDS_ALU6 shapes
-#----------------------
-caracterise RDS_ALU6 (
-  regle 84 : largeur >= 2. ;
-  regle 85 : longueur_inter min 2. ;
-  regle 86 : notch >= 12. ;
-);
-relation RDS_ALU6 , RDS_ALU6 (
-  regle 87 : distance axiale min 12. ;
-);
-
-# Check ANY_VIA layers, stacking are free
-#----------------------------------------
-relation RDS_CONT , RDS_CONT (
-  regle 67 : distance axiale >= 3. ;
-);
-relation RDS_VIA , RDS_VIA (
-  regle 68 : distance axiale >= 3. ;
-);
-relation RDS_VIA2 , RDS_VIA2 (
-  regle 69 : distance axiale >= 3. ;
-);
-relation RDS_VIA3 , RDS_VIA3 (
-  regle 70 : distance axiale >= 3. ;
-);
-relation RDS_VIA4 , RDS_VIA4 (
-  regle 88 : distance axiale >= 5. ;
-);
-relation RDS_VIA5 , RDS_VIA5 (
-  regle 89 : distance axiale >= 5. ;
-);
-caracterise RDS_CONT (
-  regle 71 : largeur >= 1. ;
-  regle 72 : longueur <= 1. ;
-);
-caracterise RDS_VIA (
-  regle 73 : largeur >= 1. ;
-  regle 74 : longueur <= 1. ;
-);
-caracterise RDS_VIA2 (
-  regle 75 : largeur >= 1. ;
-  regle 76 : longueur <= 1. ;
-);
-caracterise RDS_VIA3 (
-  regle 77 : largeur >= 1. ;
-  regle 78 : longueur <= 1. ;
-);
-caracterise RDS_VIA4 (
-  regle 90 : largeur >= 1. ;
-  regle 91 : longueur <= 1. ;
-);
-caracterise RDS_VIA5 (
-  regle 92 : largeur >= 1. ;
-  regle 93 : longueur <= 1. ;
-);
-
-fin regles
-DRC_COMMENT
-1 (RDS_NWELL) minimum width 4. 
-2 (RDS_NWELL) minimum width 4. 
-3 (RDS_NWELL) Manhatan distance min 12. 
-4 (RDS_NWELL,RDS_NWELL) Manhatan distance min 12. 
-5 (RDS_PTIE,RDS_NWELL) Manhatan distance min 7.5
-6 (RDS_PTIE,RDS_NWELL) must never been in contact
-7 (RDS_PTIE,RDS_NWELL) must never been in contact
-8 (RDS_PTIE,RDS_NWELL) must never been in contact
-9 (RDS_PTIE,RDS_NWELL) must never been in contact
-10 (RDS_PTIE,RDS_NWELL) must never been in contact
-11 (RDS_PTIE,RDS_NWELL) must never been in contact
-12 (RDS_NDIF,RDS_NWELL) Manhatan distance min 7.5
-13 (RDS_NDIF,RDS_NWELL) must never been in contact
-14 (RDS_NDIF,RDS_NWELL) must never been in contact
-15 (RDS_NDIF,RDS_NWELL) must never been in contact
-16 (RDS_NDIF,RDS_NWELL) must never been in contact
-17 (RDS_NDIF,RDS_NWELL) must never been in contact
-18 (RDS_NDIF,RDS_NWELL) must never been in contact
-19 (RDS_PDIF) minimum width 2. 
-20 (RDS_PDIF) minimum width 2. 
-21 (RDS_PDIF) Manhatan distance min 2. 
-22 (RDS_PDIF,RDS_PDIF) Manhatan distance min 3. 
-23 (RDS_NDIF) minimum width 2. 
-24 (RDS_NDIF) minimum width 2. 
-25 (RDS_NDIF) Manhatan distance min 2. 
-26 (RDS_NDIF,RDS_NDIF) Manhatan distance min 3. 
-27 (RDS_PTIE) minimum width 2. 
-28 (RDS_PTIE) minimum width 2. 
-29 (RDS_PTIE) Manhatan distance min 2. 
-30 (RDS_PTIE,RDS_PTIE) Manhatan distance min 3. 
-31 (RDS_NTIE) minimum width 2. 
-32 (RDS_NTIE) minimum width 2. 
-33 (RDS_NTIE) Manhatan distance min 2. 
-34 (RDS_NTIE,RDS_NTIE) Manhatan distance min 3. 
-35 (ANY_N_DIF,ANY_P_DIF) Manhatan distance min 3. 
-36 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-37 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-38 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-39 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-40 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-41 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-42 (RDS_POLY,ANY_N_DIF) Manhatan distance min 1. 
-43 (RDS_POLY,ANY_P_DIF) Manhatan distance min 1. 
-44 (RDS_POLY) minimum width 1. 
-45 (RDS_POLY) minimum width 1. 
-46 (RDS_POLY) Manhatan distance min 2. 
-47 (RDS_POLY,RDS_POLY) Manhatan distance min 2.
-48 (CHANNEL) Manhatan distance min 2. 
-49 (CHANNEL,CHANNEL) Manhatan distance min 2.
-50 (RDS_POLY,RDS_POLY) Manhatan distance min 2.
-51 (RDS_ALU1) minimum width 1. 
-52 (RDS_ALU1) minimum width 1. 
-53 (RDS_ALU1) Manhatan distance min 2.5
-54 (RDS_ALU1,RDS_ALU1) Manhatan distance min 2.5
-55 (RDS_ALU2) minimum width 2. 
-56 (RDS_ALU2) minimum width 2. 
-57 (RDS_ALU2) Manhatan distance min 2. 
-58 (RDS_ALU2,RDS_ALU2) Manhatan distance min 2. 
-59 (RDS_ALU3) minimum width 2. 
-60 (RDS_ALU3) minimum width 2. 
-61 (RDS_ALU3) Manhatan distance min 3. 
-62 (RDS_ALU3,RDS_ALU3) Manhatan distance min 3. 
-63 (RDS_ALU4) minimum width 2. 
-64 (RDS_ALU4) minimum width 2. 
-65 (RDS_ALU4) Manhatan distance min 3. 
-66 (RDS_ALU4,RDS_ALU4) Manhatan distance min 3. 
-67 (RDS_CONT,RDS_CONT) Manhatan distance min 3. 
-68 (RDS_VIA,RDS_VIA) Manhatan distance min 3. 
-69 (RDS_VIA2,RDS_VIA2) Manhatan distance min 3. 
-70 (RDS_VIA3,RDS_VIA3) Manhatan distance min 3. 
-71 (RDS_CONT) minimum width 1. 
-72 (RDS_CONT) maximum length 1. 
-73 (RDS_VIA) minimum width 1. 
-74 (RDS_VIA) maximum length 1. 
-75 (RDS_VIA2) minimum width 1. 
-76 (RDS_VIA2) maximum length 1. 
-77 (RDS_VIA3) minimum width 1. 
-78 (RDS_VIA3) maximum length 1. 
-79 (RDS_POLY,CONT_DIFF) Manhatan distance min 2. 
-80 (RDS_ALU5) minimum width 2. 
-81 (RDS_ALU5) minimum width 2. 
-82 (RDS_ALU5) Manhatan distance min 12. 
-83 (RDS_ALU5,RDS_ALU5) Manhatan distance min 12. 
-84 (RDS_ALU6) minimum width 2. 
-85 (RDS_ALU6) minimum width 2. 
-86 (RDS_ALU6) Manhatan distance min 12. 
-87 (RDS_ALU6,RDS_ALU6) Manhatan distance min 12. 
-88 (RDS_VIA4,RDS_VIA4) Manhatan distance min 5. 
-89 (RDS_VIA5,RDS_VIA5) Manhatan distance min 5. 
-90 (RDS_VIA4) minimum width 1. 
-91 (RDS_VIA4) maximum length 1. 
-92 (RDS_VIA5) minimum width 1. 
-93 (RDS_VIA5) maximum length 1. 
-END_DRC_COMMENT
-END_DRC_RULES
diff --git a/alliance/share/etc/cmos_12.graal b/alliance/share/etc/cmos_12.graal
deleted file mode 100644
index 29cfc32a..00000000
--- a/alliance/share/etc/cmos_12.graal
+++ /dev/null
@@ -1,348 +0,0 @@
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Title      :      Parameters File for Graal                 |
-# |                                                             |
-# | Technology :              Cmos V7                           |
-# |                                                             |
-# | Date       :             27/06/95                           |
-# |                                                             |
-# \------------------------------------------------------------*/
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                 Graal Peek Bound in lambda                  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_PEEK_BOUND 7
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |               Lower Grid Step in pixel by lambda            |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_LOWER_GRID_STEP 10
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |          Lower Figure Text Step in pixel by lambda          |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_LOWER_FIGURE_STEP 1
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |         Lower Instance Text Step in pixel by lambda         |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_LOWER_INSTANCE_STEP 1
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |        Lower Connector Text Step in pixel by lambda         |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_LOWER_CONNECTOR_STEP 5
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |          Lower Segment Text Step in pixel by lambda         |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_LOWER_SEGMENT_STEP 7
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |         Lower Reference Text Step in pixel by lambda        |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_LOWER_REFERENCE_STEP 10
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                 Graal Cursor Color Name                     |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_CURSOR_COLOR_NAME  Gray
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                 Graal Cursor Size in pixel                  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_CURSOR_SIZE 10 
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |  Segment Panel Button Label, Foreground , Background Color  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_SEGMENT_NAME
-
-  NWELL    Nwell  tan              Black
-  PWELL    Pwell  light_yellow     Black
-  NDIF     Ndif   lawn_green       Black
-  PDIF     Pdif   yellow           Black
-  NTIE     Ntie   spring_green     Black
-  PTIE     Ptie   light_goldenrod  Black
-  POLY     Poly   red              Black
-  POLY2    Poly2  orange           Black
-  ALU1     Alu1   royal_blue       Black
-  ALU2     Alu2   Cyan             Black
-  ALU3     Alu3   light_pink       Black
-  ALU4     Alu4   green            Black
-  ALU5     Alu5   yellow           Black
-  ALU6     Alu6   violet           Black
-  TPOLY    Tpoly  hot_pink         Black
-  TALU1    Talu1  royal_blue       Black
-  TALU2    Talu2  turquoise        Black
-  TALU3    Talu3  light_pink       Black
-  TALU4    Talu4  green            Black
-  TALU5    Talu5  yellow           Black
-  TALU6    Talu6  violet           Black
-  CALU1    CAlu1  royal_blue       Black
-  CALU2    CAlu2  Cyan             Black
-  CALU3    CAlu3  light_pink       Black
-  CALU4    CAlu4  green            Black
-  CALU5    CAlu5  yellow           Black
-  CALU6    CAlu6  violet           Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Transistor Panel Button Label, Foreground, Background Color |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_TRANSISTOR_NAME
-
-  NTRANS   Ntrans lawn_green       Black
-  PTRANS   Ptrans yellow           Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Connector Panel Button Label, Foreground , Background Color |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_CONNECTOR_NAME
-
-  POLY     Poly   red              Black
-  POLY2    Poly2  orange           Black
-  ALU1     Alu1   royal_blue       Black
-  ALU2     Alu2   Cyan             Black
-  ALU3     Alu3   light_pink       Black
-  ALU4     Alu4   green            Black
-  ALU5     Alu5   yellow           Black
-  ALU6     Alu6   violet           Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |       Minimun Length and Width for a symbolic Segment       |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_SEGMENT_VALUE
-
-  NWELL    4   4
-  PWELL    4   4
-  NDIF     2   2
-  PDIF     2   2
-  NTIE     2   2
-  PTIE     2   2
-  NTRANS   1   4
-  PTRANS   1   4
-  POLY     1   1
-  POLY2    1   1
-  ALU1     1   1
-  ALU2     2   1
-  ALU3     2   1
-  ALU4     2   1
-  ALU5     2   1
-  ALU6     2   1
-  TPOLY    1   1
-  TALU1    1   1
-  TALU2    2   2
-  TALU3    2   2
-  TALU4    2   2
-  TALU5    2   2
-  TALU6    2   2
-  CALU1    2   0
-  CALU2    2   0
-  CALU3    2   0
-  CALU4    2   0
-  CALU5    2   0
-  CALU6    2   0
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Reference Panel Button Label, Foreground, Background Color  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_REFERENCE_NAME
-
-  REF_REF  Ref_Ref red  Black
-  REF_CON  Ref_Con Cyan Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |     Via Panel Button Label, Foreground , Background Color   |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_VIA_NAME
-
-  CONT_DIF_N   Cont_NDif   lawn_green       Black
-  CONT_DIF_P   Cont_PDif   yellow           Black
-  CONT_BODY_N  Cont_NTie   spring_green     Black
-  CONT_BODY_P  Cont_PTie   light_goldenrod  Black
-  CONT_POLY    Cont_Poly   red              Black
-  CONT_POLY2   Cont_Poly2  orange           Black
-  CONT_VIA     Via_1-2     cyan             Black
-  CONT_VIA2    Via_2-3     light_pink       Black
-  CONT_VIA3    Via_3-4     green            Black
-  CONT_VIA4    Via_4-5     yellow           Black
-  CONT_VIA5    Via_5-6     violet           Black
-  C_X_N        Cont_CxN    orange           Black
-  C_X_P        Cont_CxP    orange           Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |  Big Via Panel Button Label, Foreground , Background Color  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_BIGVIA_NAME
-
-  CONT_VIA     Big_Via_1-2  cyan       Black
-  CONT_VIA2    Big_Via_2-3  light_pink Black
-  CONT_VIA3    Big_Via_3-4  green      Black
-
-  CONT_TURN1   Turn_Via_1   royal_blue Black
-  CONT_TURN2   Turn_Via_2   Cyan       Black
-  CONT_TURN3   Turn_Via_3   light_pink Black
-  CONT_TURN4   Turn_Via_4   green      Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |            Minimun Size for a symbolic Big Via              |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_BIGVIA_VALUE
-
-  CONT_VIA     2
-  CONT_VIA2    2
-  CONT_VIA3    2
-
-  CONT_TURN1   2
-  CONT_TURN2   2
-  CONT_TURN3   2
-  CONT_TURN4   2
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |   Orient Panel Button Label, Foreground , Background Color  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_ORIENT_NAME 
-
-  NORTH  North   lawn_green  Black
-  SOUTH  South   yellow      Black
-  EAST   East    tan         Black
-  WEST   West    red         Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Symmetry Panel Button Label, Foreground , Background Color  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_SYMMETRY_NAME
-
-  NOSYM No_Sym  LightBlue         Black
-  SYM_X Sym_X   turquoise         Black
-  SYM_Y Sym_Y   cyan              Black
-  SYMXY Sym_XY  LightCyan         Black
-  ROT_P Rot_P   MediumAquamarine  Black
-  ROT_M Rot_M   aquamarine        Black
-  SY_RP Sym_RP  green             Black
-  SY_RM Sym_RM  MediumSpringGreen Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# | View Layer Panel Button Label, Foreground, Background Color |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_RDS_LAYER_NAME
-
-  RDS_NWELL    Nwell   tan               Black
-  RDS_PWELL    Pwell   light_yellow      Black
-  RDS_NIMP     Nimp    forest_green      Black
-  RDS_PIMP     Pimp    goldenrod         Black
-  RDS_ACTIV    Activ   brown             Black
-  RDS_NDIF     Ndif    lawn_green        Black
-  RDS_PDIF     Pdif    yellow            Black
-  RDS_NTIE     Ntie    spring_green      Black
-  RDS_PTIE     Ptie    light_goldenrod   Black
-  RDS_POLY     Poly    red               Black
-  RDS_POLY2    Poly2   orange            Black
-  RDS_VPOLY    VPoly   coral             Black
-  RDS_GATE     Gate    orange            Black
-  RDS_TPOLY    Tpoly   hot_pink          Black
-  RDS_CONT     Cont    dark_violet       Black
-  RDS_TCONT    TCont   orchid            Black
-  RDS_ALU1     Alu1    royal_blue        Black
-  RDS_VALU1    VAlu1   sky_blue          Black
-  RDS_TALU1    Talu1   royal_blue        Black
-  RDS_VIA1     Via1    deep_sky_blue     Black
-  RDS_TVIA1    TVia1   dodger_blue       Black
-  RDS_ALU2     Alu2    cyan              Black
-  RDS_TALU2    Talu2   turquoise         Black
-  RDS_VIA2     Via2    deep_pink         Black
-  RDS_ALU3     Alu3    light_pink        Black
-  RDS_TALU3    Talu3   light_pink        Black
-  RDS_VIA3     Via3    sea_green         Black
-  RDS_ALU4     Alu4    green             Black
-  RDS_TALU4    Talu4   green             Black
-  RDS_VIA4     Via4    gold              Black
-  RDS_ALU5     Alu5    yellow            Black
-  RDS_TALU5    Talu5   yellow            Black
-  RDS_VIA5     Via5    violet_red        Black
-  RDS_ALU6     Alu6    violet            Black
-  RDS_TALU6    Talu6   violet            Black
-  RDS_CPAS     Cpas    gray              Black
-  RDS_REF      Ref     coral             Black
-  RDS_ABOX     Abox    pink              Black
-
-END
diff --git a/alliance/share/etc/cmos_12.lef b/alliance/share/etc/cmos_12.lef
deleted file mode 100644
index a6dc31bf..00000000
--- a/alliance/share/etc/cmos_12.lef
+++ /dev/null
@@ -1,432 +0,0 @@
-#
-# $Id: cmos_12.lef,v 1.1 2000/09/01 17:07:26 jpc Exp $
-#
-# /------------------------------------------------------------------\
-# |                                                                  |
-# |        A l l i a n c e   C A D   S y s t e m                     |
-# |  S i l i c o n   E n s e m b l e / A l l i a n c e               |
-# |                                                                  |
-# |  Author    :                      Jean-Paul CHAPUT               |
-# |  E-mail    :         alliance-support@asim.lip6.fr               |
-# | ================================================================ |
-# |  LEF       :         "./cmos_12.lef"                             |
-# | **************************************************************** |
-# |  U p d a t e s                                                   |
-# |                                                                  |
-# \------------------------------------------------------------------/
-#
-
-
-NAMESCASESENSITIVE    ON ;
-
-#NOWIREEXTENSIONATPIN ON ;
-
-
-UNITS
-    DATABASE MICRONS 100  ;
-END UNITS
-
-
-LAYER L_POLY
-    TYPE MASTERSLICE ;
-END L_POLY
-
-
-LAYER L_CONT
-    TYPE CUT ;
-END L_CONT
-
-
-LAYER L_ALU1
-    TYPE ROUTING ;
-    WIDTH 2.00 ;
-    SPACING 3.00 ;
-    PITCH 5.00 ;
-    DIRECTION VERTICAL ;
-    CAPACITANCE CPERSQDIST 0.000032 ;
-    RESISTANCE RPERSQ 0.100000 ;
-END L_ALU1
-
-
-LAYER L_VIA1
-    TYPE CUT ;
-END L_VIA1
-
-
-LAYER L_ALU2
-    TYPE ROUTING ;
-    WIDTH 2.00 ;
-    SPACING 3.00 ;
-    PITCH 5.00 ;
-    DIRECTION HORIZONTAL ;
-    CAPACITANCE CPERSQDIST 0.000032 ;
-    RESISTANCE RPERSQ 0.100000 ;
-END L_ALU2
-
-
-LAYER L_VIA2
-    TYPE CUT ;
-END L_VIA2
-
-
-LAYER L_ALU3
-    TYPE ROUTING ;
-    WIDTH 2.00 ;
-    SPACING 3.00 ;
-    PITCH 5.00 ;
-    DIRECTION VERTICAL ;
-    CAPACITANCE CPERSQDIST 0.000032 ;
-    RESISTANCE RPERSQ 0.100000 ;
-END L_ALU3
-
-
-LAYER L_VIA3
-    TYPE CUT ;
-END L_VIA3
-
-
-LAYER L_ALU4
-    TYPE ROUTING ;
-    WIDTH 2.00 ;
-    SPACING 3.00 ;
-    PITCH 5.00 ;
-    DIRECTION HORIZONTAL ;
-    CAPACITANCE CPERSQDIST 0.000032 ;
-    RESISTANCE RPERSQ 0.100000 ;
-END L_ALU4
-
-
-LAYER L_VIA4
-    TYPE CUT ;
-END L_VIA4
-
-
-LAYER L_ALU5
-    TYPE ROUTING ;
-    WIDTH 2.00 ;
-    SPACING 3.00 ;
-    PITCH 5.00 ;
-    DIRECTION VERTICAL ;
-    CAPACITANCE CPERSQDIST 0.000032 ;
-    RESISTANCE RPERSQ 0.100000 ;
-END L_ALU5
-
-
-LAYER L_VIA5
-    TYPE CUT ;
-END L_VIA5
-
-
-LAYER L_ALU6
-    TYPE ROUTING ;
-    WIDTH 2.00 ;
-    SPACING 3.00 ;
-    PITCH 5.00 ;
-    DIRECTION HORIZONTAL ;
-    CAPACITANCE CPERSQDIST 0.000032 ;
-    RESISTANCE RPERSQ 0.100000 ;
-END L_ALU6
-
-
-#VIA CONT_POLY DEFAULT
-#    LAYER L_POLY ;
-#        RECT -1.50 -1.50 1.50 1.50 ;
-#    LAYER L_CONT ;
-#        RECT -0.50 -0.50 0.50 0.50 ;
-#    LAYER L_ALU1 ;
-#        RECT -1.00 -1.00 1.00 1.00 ;
-#END CONT_POLY
-
-
-VIA CONT_VIA DEFAULT
-    LAYER L_ALU1 ;
-        RECT -1.00 -1.00 1.00 1.00 ;
-    LAYER L_VIA1 ;
-        RECT -0.50 -0.50 0.50 0.50 ;
-    LAYER L_ALU2 ;
-        RECT -1.00 -1.00 1.00 1.00 ;
-END CONT_VIA
-
-
-VIA CONT_VIA2 DEFAULT
-    LAYER L_ALU3 ;
-        RECT -1.00 -1.00 1.00 1.00 ;
-    LAYER L_VIA2 ;
-        RECT -0.50 -0.50 0.50 0.50 ;
-    LAYER L_ALU2 ;
-        RECT -1.00 -1.00 1.00 1.00 ;
-END CONT_VIA2
-
-
-VIA CONT_VIA3 DEFAULT
-    LAYER L_ALU4 ;
-        RECT -1.00 -1.00 1.00 1.00 ;
-    LAYER L_VIA3 ;
-        RECT -0.50 -0.50 0.50 0.50 ;
-    LAYER L_ALU3 ;
-        RECT -1.00 -1.00 1.00 1.00 ;
-END CONT_VIA3
-
-
-VIA CONT_VIA4 DEFAULT
-    LAYER L_ALU5 ;
-        RECT -1.00 -1.00 1.00 1.00 ;
-    LAYER L_VIA4 ;
-        RECT -0.50 -0.50 0.50 0.50 ;
-    LAYER L_ALU4 ;
-        RECT -1.00 -1.00 1.00 1.00 ;
-END CONT_VIA4
-
-
-VIA CONT_VIA5 DEFAULT
-    LAYER L_ALU6 ;
-        RECT -1.00 -1.00 1.00 1.00 ;
-    LAYER L_VIA5 ;
-        RECT -0.50 -0.50 0.50 0.50 ;
-    LAYER L_ALU5 ;
-        RECT -1.00 -1.00 1.00 1.00 ;
-END CONT_VIA5
-
-
-VIARULE TURN_ALU1 GENERATE
-    LAYER L_ALU1 ;
-        DIRECTION vertical ;
-
-    LAYER L_ALU1 ;
-        DIRECTION horizontal ;
-END TURN_ALU1
-
-
-VIARULE TURN_ALU2 GENERATE
-    LAYER L_ALU2 ;
-        DIRECTION vertical ;
-
-    LAYER L_ALU2 ;
-        DIRECTION horizontal ;
-END TURN_ALU2
-
-
-VIARULE TURN_ALU3 GENERATE
-    LAYER L_ALU3 ;
-        DIRECTION vertical ;
-
-    LAYER L_ALU3 ;
-        DIRECTION horizontal ;
-END TURN_ALU3
-
-
-VIARULE TURN_ALU4 GENERATE
-    LAYER L_ALU4 ;
-        DIRECTION vertical ;
-
-    LAYER L_ALU4 ;
-        DIRECTION horizontal ;
-END TURN_ALU4
-
-
-VIARULE TURN_ALU5 GENERATE
-    LAYER L_ALU5 ;
-        DIRECTION vertical ;
-
-    LAYER L_ALU5 ;
-        DIRECTION horizontal ;
-END TURN_ALU5
-
-
-VIARULE TURN_ALU6 GENERATE
-    LAYER L_ALU6 ;
-        DIRECTION vertical ;
-
-    LAYER L_ALU6 ;
-        DIRECTION horizontal ;
-END TURN_ALU6
-
-
-#VIARULE VIA1_HV
-#    LAYER L_ALU1 ;
-#        DIRECTION VERTICAL ;
-#        OVERHANG 0.50 ;
-#        METALOVERHANG 0.50 ;
-#
-#    LAYER L_ALU2 ;
-#        DIRECTION HORIZONTAL ;
-#        OVERHANG 0.50 ;
-#        METALOVERHANG 0.50 ;
-#
-#    VIA CONT_VIA ;
-#END VIA1_HV
-#
-#
-#VIARULE VIA2_VH
-#    LAYER L_ALU2 ;
-#        DIRECTION HORIZONTAL ;
-#        OVERHANG 0.50 ;
-#        METALOVERHANG 0.50 ;
-#
-#    LAYER L_ALU3 ;
-#        DIRECTION VERTICAL ;
-#        OVERHANG 0.50 ;
-#        METALOVERHANG 0.50 ;
-#
-#    VIA CONT_VIA2 ;
-#END VIA2_VH
-#
-#
-#VIARULE VIA3_VH
-#    LAYER L_ALU3 ;
-#        DIRECTION HORIZONTAL ;
-#        OVERHANG 0.50 ;
-#        METALOVERHANG 0.50 ;
-#
-#    LAYER L_ALU4 ;
-#        DIRECTION VERTICAL ;
-#        OVERHANG 0.50 ;
-#        METALOVERHANG 0.50 ;
-#
-#    VIA CONT_VIA3 ;
-#END VIA3_VH
-
-
-VIARULE genVIA1_HV GENERATE
-    LAYER L_ALU1 ;
-        DIRECTION VERTICAL ;
-        OVERHANG 0.50 ;
-        METALOVERHANG 0.50 ;
-
-    LAYER L_ALU2 ;
-        DIRECTION HORIZONTAL ;
-        OVERHANG 0.50 ;
-        METALOVERHANG 0.50 ;
-
-    LAYER L_VIA1 ;
-        RECT -0.50 -0.50 0.50 0.50 ;
-        SPACING 3.00 BY 3.00 ;
-END genVIA1_HV
-
-
-VIARULE genVIA1_VH GENERATE
-    LAYER L_ALU1 ;
-        DIRECTION HORIZONTAL ;
-        OVERHANG 0.50 ;
-        METALOVERHANG 0.50 ;
-
-    LAYER L_ALU2 ;
-        DIRECTION VERTICAL ;
-        OVERHANG 0.50 ;
-        METALOVERHANG 0.50 ;
-
-    LAYER L_VIA1 ;
-        RECT -0.50 -0.50 0.50 0.50 ;
-        SPACING 3.00 BY 3.00 ;
-END genVIA1_VH
-
-
-VIARULE genVIA2_VH GENERATE
-    LAYER L_ALU2 ;
-        DIRECTION HORIZONTAL ;
-        OVERHANG 0.50 ;
-        METALOVERHANG 0.50 ;
-
-    LAYER L_ALU3 ;
-        DIRECTION VERTICAL ;
-        OVERHANG 0.50 ;
-        METALOVERHANG 0.50 ;
-
-    LAYER L_VIA2 ;
-        RECT -0.50 -0.50 0.50 0.50 ;
-        SPACING 3.00 BY 3.00 ;
-END genVIA2_VH
-
-
-VIARULE genVIA2_HV GENERATE
-    LAYER L_ALU2 ;
-        DIRECTION VERTICAL ;
-        OVERHANG 0.50 ;
-        METALOVERHANG 0.50 ;
-
-    LAYER L_ALU3 ;
-        DIRECTION HORIZONTAL ;
-        OVERHANG 0.50 ;
-        METALOVERHANG 0.50 ;
-
-    LAYER L_VIA2 ;
-        RECT -0.50 -0.50 0.50 0.50 ;
-        SPACING 3.00 BY 3.00 ;
-END genVIA2_HV
-
-
-VIARULE genVIA3_VH GENERATE
-    LAYER L_ALU3 ;
-        DIRECTION HORIZONTAL ;
-        OVERHANG 0.50 ;
-        METALOVERHANG 0.50 ;
-
-    LAYER L_ALU4 ;
-        DIRECTION VERTICAL ;
-        OVERHANG 0.50 ;
-        METALOVERHANG 0.50 ;
-
-    LAYER L_VIA3 ;
-        RECT -0.50 -0.50 0.50 0.50 ;
-        SPACING 3.00 BY 3.00 ;
-END genVIA3_VH
-
-
-VIARULE genVIA3_HV GENERATE
-    LAYER L_ALU3 ;
-        DIRECTION VERTICAL ;
-        OVERHANG 0.50 ;
-        METALOVERHANG 0.50 ;
-
-    LAYER L_ALU4 ;
-        DIRECTION HORIZONTAL ;
-        OVERHANG 0.50 ;
-        METALOVERHANG 0.50 ;
-
-    LAYER L_VIA3 ;
-        RECT -0.50 -0.50 0.50 0.50 ;
-        SPACING 3.00 BY 3.00 ;
-END genVIA3_HV
-
-
-SPACING
-    SAMENET L_CONT L_CONT 3.00 ;
-    SAMENET L_VIA1 L_VIA1 3.00 ;
-    SAMENET L_VIA2 L_VIA2 3.00 ;
-    SAMENET L_CONT L_VIA1 3.00 STACK ;
-    SAMENET L_VIA1 L_VIA2 3.00 STACK ;
-    SAMENET L_VIA2 L_VIA3 3.00 STACK ;
-    SAMENET L_VIA3 L_VIA4 3.00 STACK ;
-    SAMENET L_VIA4 L_VIA5 3.00 STACK ;
-    SAMENET L_POLY L_POLY 3.00 ;
-    SAMENET L_ALU1 L_ALU1 3.00 STACK ;
-    SAMENET L_ALU2 L_ALU2 3.00 STACK ;
-    SAMENET L_ALU3 L_ALU3 3.00 STACK ;
-    SAMENET L_ALU4 L_ALU4 3.00 STACK ;
-    SAMENET L_ALU5 L_ALU5 3.00 STACK ;
-    SAMENET L_ALU6 L_ALU6 3.00 ;
-END SPACING
-
-
-SITE core
-    SYMMETRY y  ;
-    CLASS core  ;
-    SIZE 5.00 BY 50.00 ;
-END core
-
-
-SITE pad
-    SYMMETRY y  ;
-    CLASS pad  ;
-    SIZE 1.00 BY 500.00 ;
-END pad
-
-
-SITE corner
-    SYMMETRY y r90  ;
-    CLASS pad  ;
-    SIZE 500.00 BY 500.00 ;
-END corner
-
-
-END LIBRARY
diff --git a/alliance/share/etc/cmos_12.rds b/alliance/share/etc/cmos_12.rds
deleted file mode 100644
index 65aa2737..00000000
--- a/alliance/share/etc/cmos_12.rds
+++ /dev/null
@@ -1,907 +0,0 @@
-#=====================================================================
-#
-#                         ALLIANCE VLSI CAD                  
-#            (R)eal (D)ata (S)tructure parameter file
-#         (c) copyright 1992 Laboratory UPMC/MASI/CAO-VLSI   
-#                        all rights reserved                 
-#                   e-mail : cao-vlsi@masi.ibp.fr            
-#
-#                   file       : cmos_9.rds
-#                   version    : 10
-#                   last modif : Nov 4, 1999
-#
-##-------------------------------------------------------------------
-# Symbolic to micron on a 'one lambda equals one micron' basis
-##-------------------------------------------------------------------
-# Refer to the documentation for more precise information.
-#=====================================================================
-# 01/11/09 ALU5/6 pitch 10
-#
-# 99/11/3 ALU5/6 rules
-# . theses rules are preliminary rules, we hope that they wil change
-#   in future. For now, ALU5/6 are dedicated to supplies an clock.
-# 
-# 99/3/22 new symbolics rules
-# . ALU1 width remains 1, ALU2/3/4 is 2
-# . ALU1/2/3/4 distance (edge to edge) is now 3 for all
-# . GATE to GATE distance is 3 but POLY wire to POLY wire remains 2
-# . All via stacking are allowed
-#
-# 98/12/1 drc rules were updated
-# distance VIA to POLY or gate is one rather 2
-# VIA2 and ALU3 appeared
-# . ALU3 width is 3
-# . ALU2/VIA2/ALU3 is resp. 3/1/3
-# . ALU3 edge distance is 2
-# . stacked VIA/VIA2 is allowed
-# . if they are not stacked they must distant of 2
-# . CONT/VIA2 is free
-# note
-# . stacked CONT/VIA is always not allowed
-# NWELL is automatically drawn with the DIFN and NTIE layers
-#=====================================================================
-
-##-------------------------------------------------------------------
-# PHYSICAL_GRID :
-##-------------------------------------------------------------------
-
-DEFINE  PHYSICAL_GRID  .5
-
-##-------------------------------------------------------------------
-# LAMBDA : 
-##-------------------------------------------------------------------
-
-DEFINE  LAMBDA         1
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_SEGMENT :
-#
-# MBK      RDS layer 1                 RDS layer 2         
-# name     name TRANS DLR DWR OFFSET   name TRANS DLR DWR OFFSET  ...
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_SEGMENT
-
-  PWELL    RDS_PWELL  VW  0.0  0.0  0.0  EXT
-  NWELL    RDS_NWELL  VW  0.0  0.0  0.0  ALL
-  NDIF     RDS_NDIF   VW  0.5  0.0  0.0  ALL
-  PDIF     RDS_PDIF   VW  0.5  0.0  0.0  ALL \
-           RDS_NWELL  VW  1.0  1.0  0.0  ALL
-  NTIE     RDS_NTIE   VW  0.5  0.0  0.0  ALL \
-           RDS_NWELL  VW  1.0  1.0  0.0  ALL
-  PTIE     RDS_PTIE   VW  0.5  0.0  0.0  ALL
-  NTRANS   RDS_POLY   VW  0.0  0.0  0.0  ALL \
-           RDS_NDIF  LCW -1.5  2.0  0.0  EXT \
-           RDS_NDIF  RCW -1.5  2.0  0.0  EXT \
-           RDS_NDIF   VW -1.5  4.0  0.0  DRC \
-           RDS_ACTIV  VW -1.5  5.0  0.0  ALL \
-	   RDS_PWELL  VW -1.5  0.0  0.0  EXT
-  PTRANS   RDS_POLY   VW  0.0  0.0  0.0  ALL \
-           RDS_PDIF  LCW -1.5  2.0  0.0  EXT \
-           RDS_PDIF  RCW -1.5  2.0  0.0  EXT \
-           RDS_PDIF   VW -1.5  4.0  0.0  DRC \
-           RDS_ACTIV  VW -1.5  5.0  0.0  ALL \
-           RDS_NWELL  VW -1.0  5.0  0.0  ALL 
-  POLY     RDS_POLY   VW  0.5  0.0  0.0  ALL
-  POLY2    RDS_POLY2  VW  0.5  0.0  0.0  ALL
-  ALU1     RDS_ALU1   VW  0.5  0.0  0.0  ALL
-  ALU2     RDS_ALU2   VW  1.0  0.0  0.0  ALL
-  ALU3     RDS_ALU3   VW  1.0  0.0  0.0  ALL
-  ALU4     RDS_ALU4   VW  1.0  0.0  0.0  ALL
-  ALU5     RDS_ALU5   VW  1.0  0.0  0.0  ALL 
-  ALU6     RDS_ALU6   VW  1.0  0.0  0.0  ALL 
-  CALU1    RDS_ALU1   VW  1.0  0.0  0.0  ALL
-  CALU2    RDS_ALU2   VW  1.0  0.0  0.0  ALL
-  CALU3    RDS_ALU3   VW  1.0  0.0  0.0  ALL
-  CALU4    RDS_ALU4   VW  1.0  0.0  0.0  ALL
-  CALU5    RDS_ALU5   VW  1.0  0.0  0.0  ALL 
-  CALU6    RDS_ALU6   VW  1.0  0.0  0.0  ALL 
-  TPOLY    RDS_TPOLY  VW  0.5  0.0  0.0  ALL
-  TALU1    RDS_TALU1  VW  0.5  0.0  0.0  ALL
-  TALU2    RDS_TALU2  VW  1.0  0.0  0.0  ALL
-  TALU3    RDS_TALU3  VW  1.0  0.0  0.0  ALL
-  TALU4    RDS_TALU4  VW  1.0  0.0  0.0  ALL
-  TALU5    RDS_TALU5  VW  1.0  0.0  0.0  ALL
-  TALU6    RDS_TALU6  VW  1.0  0.0  0.0  ALL
-
-END
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_CONNECTOR :
-#
-# MBK      RDS layer 
-# name     name     DER DWR 
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_CONNECTOR
-
-  POLY    RDS_POLY  .5  0  
-  POLY2   RDS_POLY2 .5  0  
-  ALU1    RDS_ALU1  .5  0  
-  ALU2    RDS_ALU2 1.0  0  
-  ALU3    RDS_ALU3 1.0  0  
-  ALU4    RDS_ALU4 1.0  0  
-  ALU5    RDS_ALU5 1.0  0  
-  ALU6    RDS_ALU6 1.0  0  
-
-END
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_REFERENCE :
-#
-# MBK ref    RDS layer 
-# name       name       width
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_REFERENCE
-
-  REF_REF    RDS_REF    1
-  REF_CON    RDS_VALU1  2  RDS_TVIA1 1  RDS_TALU2  2
-
-END
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_VIA1 :
-#
-# MBK via      RDS layer 1  RDS  layer 2  RDS  layer 3  RDS layer 4      
-# name         name  width  name   width  name   width  name  width  
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_VIA
-
-  CONT_BODY_P  RDS_ALU1 2 ALL  RDS_CONT 1 ALL  RDS_PTIE 3 ALL  
-  CONT_BODY_N  RDS_ALU1 2 ALL  RDS_CONT 1 ALL  RDS_NTIE 3 ALL  RDS_NWELL 4 ALL
-  CONT_DIF_N   RDS_ALU1 2 ALL  RDS_CONT 1 ALL  RDS_NDIF 3 ALL
-  CONT_DIF_P   RDS_ALU1 2 ALL  RDS_CONT 1 ALL  RDS_PDIF 3 ALL  RDS_NWELL 4 ALL
-  CONT_POLY    RDS_ALU1 2 ALL  RDS_CONT 1 ALL  RDS_POLY 3 ALL
-  CONT_POLY2   RDS_ALU1 2 ALL  RDS_CONT 1 ALL  RDS_POLY2 3 ALL
-  CONT_VIA     RDS_ALU1 2 ALL  RDS_VIA1 1 ALL  RDS_ALU2 2 ALL
-  CONT_VIA2    RDS_ALU2 2 ALL  RDS_VIA2 1 ALL  RDS_ALU3 2 ALL
-  CONT_VIA3    RDS_ALU3 2 ALL  RDS_VIA3 1 ALL  RDS_ALU4 2 ALL
-  CONT_VIA4    RDS_ALU4 2 ALL  RDS_VIA4 1 ALL  RDS_ALU5 2 ALL
-  CONT_VIA5    RDS_ALU5 2 ALL  RDS_VIA5 1 ALL  RDS_ALU6 2 ALL
-  C_X_N        RDS_POLY 1 ALL  RDS_NDIF 5 ALL  RDS_ACTIV 6 ALL
-  C_X_P        RDS_POLY 1 ALL  RDS_PDIF 5 ALL  RDS_NWELL 6 ALL  RDS_ACTIV 6 ALL
-
-END
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_BIGVIA_HOLE :
-#
-# MBK via      RDS Hole        
-# name         name  side step mode
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_BIGVIA_HOLE
-
-CONT_VIA   RDS_VIA1 1 4 ALL
-CONT_VIA2  RDS_VIA2 1 4 ALL
-CONT_VIA3  RDS_VIA3 1 4 ALL
-CONT_VIA5  RDS_VIA3 1 9 ALL
-CONT_VIA6  RDS_VIA3 1 9 ALL
-
-END
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_BIGVIA_METAL :
-#
-# MBK via      RDS layer 1                      ...
-# name         name  delta-width overlap mode
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_BIGVIA_METAL
-
-CONT_VIA  RDS_ALU1 0.0 0.5 ALL RDS_ALU2 0.0 0.5 ALL
-CONT_VIA2 RDS_ALU2 0.0 0.5 ALL RDS_ALU3 0.0 0.5 ALL
-CONT_VIA3 RDS_ALU3 0.0 0.5 ALL RDS_ALU4 0.0 0.5 ALL
-CONT_VIA4 RDS_ALU4 0.0 0.5 ALL RDS_ALU5 0.0 0.5 ALL
-CONT_VIA5 RDS_ALU5 0.0 0.5 ALL RDS_ALU6 0.0 0.5 ALL
-
-END 
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_TURNVIA :
-#
-# MBK via      RDS layer 1                      ...
-# name         name  DWR MODE
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_TURNVIA
-
-CONT_TURN1 RDS_ALU1 0 ALL
-CONT_TURN2 RDS_ALU2 0 ALL
-CONT_TURN3 RDS_ALU3 0 ALL
-CONT_TURN4 RDS_ALU4 0 ALL
-CONT_TURN5 RDS_ALU5 0 ALL
-CONT_TURN6 RDS_ALU6 0 ALL
-
-END
-
-
-##-------------------------------------------------------------------
-# TABLE LYNX_GRAPH :
-#
-# RDS layer   Rds layer 1   Rds layer 2    ...
-# name        name          name           ...
-##-------------------------------------------------------------------
-
-TABLE LYNX_GRAPH
-
-##---------------------------
-#
-# Modifie par L.Jacomme (Pb Bulk/Alim avec Lynx)
-# 23.11.99
-#
-# RDS_NWELL  RDS_NTIE   RDS_NWELL
-# RDS_PWELL  RDS_PTIE   RDS_PWELL
-# RDS_NDIF  RDS_CONT RDS_NDIF
-# RDS_PDIF  RDS_CONT RDS_PDIF
-# RDS_NTIE  RDS_CONT RDS_NTIE RDS_NWELL
-# RDS_PTIE  RDS_CONT RDS_PTIE RDS_PWELL
-
-  RDS_NDIF  RDS_CONT RDS_NDIF
-  RDS_PDIF  RDS_CONT RDS_PDIF
-  RDS_NTIE  RDS_CONT RDS_NTIE
-  RDS_PTIE  RDS_CONT RDS_PTIE
-
-  RDS_POLY  RDS_CONT RDS_POLY 
-  RDS_POLY2  RDS_CONT RDS_POLY2 
-  RDS_CONT  RDS_PDIF RDS_NDIF RDS_POLY RDS_PTIE  RDS_NTIE RDS_ALU1 RDS_CONT
-  RDS_ALU1  RDS_CONT RDS_VIA1 RDS_ALU1 RDS_VALU1 RDS_ALU1
-  RDS_VALU1 RDS_CONT RDS_VIA1 RDS_ALU1 RDS_VALU1
-  RDS_VIA1  RDS_ALU1 RDS_ALU2 RDS_VIA1
-  RDS_VIA2  RDS_ALU2 RDS_ALU3 RDS_VIA2
-  RDS_VIA3  RDS_ALU3 RDS_ALU4 RDS_VIA3
-  RDS_VIA4  RDS_ALU4 RDS_ALU5 RDS_VIA4
-  RDS_VIA5  RDS_ALU5 RDS_ALU6 RDS_VIA5
-  RDS_ALU2  RDS_VIA1 RDS_VIA2 RDS_ALU2 
-  RDS_ALU3  RDS_VIA2 RDS_VIA3 RDS_ALU3
-  RDS_ALU4  RDS_VIA3 RDS_VIA4 RDS_ALU4 
-  RDS_ALU5  RDS_VIA4 RDS_VIA5 RDS_ALU5 
-  RDS_ALU6  RDS_VIA5          RDS_ALU6 
-
-END
-
-##-------------------------------------------------------------------
-# TABLE LYNX_CAPA : 
-#
-# RDS layer   Surface capacitance  Perimetric capacitance
-# name        piF / Micron^2       piF / Micron 
-##-------------------------------------------------------------------
-
-TABLE LYNX_CAPA
-
-  RDS_POLY    1.00e-04    1.00e-04
-  RDS_POLY2   1.00e-04    1.00e-04
-  RDS_ALU1    0.50e-04    0.90e-04
-  RDS_ALU2    0.25e-04    0.95e-04
-  RDS_ALU3    0.25e-04    0.95e-04
-  RDS_ALU4    0.25e-04    0.95e-04
-  RDS_ALU5    0.25e-04    0.95e-04
-  RDS_ALU6    0.25e-04    0.95e-04
-
-END
-
-##-------------------------------------------------------------------
-# TABLE LYNX_RESISTOR :
-#
-# RDS layer   Surface resistor
-# name        Ohm / Micron^2 
-##-------------------------------------------------------------------
-
-TABLE LYNX_RESISTOR
-
-  RDS_POLY    50.0
-  RDS_POLY2   50.0
-  RDS_ALU1     0.1
-  RDS_ALU2     0.05
-  RDS_ALU3     0.05
-  RDS_ALU4     0.05
-  RDS_ALU5     0.05
-  RDS_ALU6     0.05
-
-END
-
-##-------------------------------------------------------------------
-# TABLE LYNX_TRANSISTOR : 
-#
-# MBK layer  Transistor Type  MBK via
-# name       name             name
-##-------------------------------------------------------------------
-
-TABLE LYNX_TRANSISTOR
-
-  NTRANS  NTRANS  C_X_N   RDS_POLY   RDS_NDIF  RDS_NDIF  RDS_PWELL
-  PTRANS  PTRANS  C_X_P   RDS_POLY   RDS_PDIF  RDS_PDIF  RDS_NWELL
-
-END
-
-##-------------------------------------------------------------------
-# TABLE LYNX_DIFFUSION :
-#
-# RDS layer  RDS layer
-# name       name    
-##-------------------------------------------------------------------
-
-TABLE LYNX_DIFFUSION
-END
-
-##-------------------------------------------------------------------
-# TABLE LYNX_BULK_IMPLICIT :
-#
-# RDS layer  Bulk type
-# name       EXPLICIT/IMPLICIT
-##-------------------------------------------------------------------
-
-TABLE LYNX_BULK_IMPLICIT
-
-##---------------------------
-#
-# Modifie par L.Jacomme (Pb Bulk/Alim avec Lynx)
-# 23.11.99
-#
-# NWELL  EXPLICIT
-# PWELL  IMPLICIT
-
-END
-
-
-
-##-------------------------------------------------------------------
-# TABLE S2R_OVERSIZE_DENOTCH :
-##-------------------------------------------------------------------
-
-TABLE S2R_OVERSIZE_DENOTCH 
-END
-
-##-------------------------------------------------------------------
-# TABLE S2R_BLOC_RING_WIDTH :
-##-------------------------------------------------------------------
-
-TABLE S2R_BLOC_RING_WIDTH
-END
-
-##-------------------------------------------------------------------
-# TABLE S2R_MINIMUM_LAYER_WIDTH :
-##-------------------------------------------------------------------
-
-TABLE S2R_MINIMUM_LAYER_WIDTH 
-
-  RDS_NWELL   4
-  RDS_PDIF    2
-  RDS_NTIE    2
-  RDS_PTIE    2
-  RDS_POLY    1
-  RDS_POLY2   1
-  RDS_TPOLY   1
-  RDS_CONT    1
-  RDS_ALU1    1
-  RDS_TALU1   1
-  RDS_VIA1    1
-  RDS_ALU2    2
-  RDS_TALU2   2
-  RDS_VIA2    1
-  RDS_ALU3    2
-  RDS_TALU3   2
-  RDS_VIA3    1
-  RDS_ALU4    2
-  RDS_TALU4   2
-  RDS_VIA4    1
-  RDS_ALU5    2
-  RDS_TALU5   2
-  RDS_VIA5    1
-  RDS_ALU6    2
-  RDS_TALU6   2
-
-END
-
-##-------------------------------------------------------------------
-# TABLE CIF_LAYER :
-##-------------------------------------------------------------------
-
-TABLE CIF_LAYER
-
-  RDS_NWELL    LNWELL
-  RDS_NDIF     LNDIF
-  RDS_PDIF     LPDIF
-  RDS_NTIE     LNTIE
-  RDS_PTIE     LPTIE
-  RDS_POLY     LPOLY
-  RDS_POLY2    LPOLY2
-  RDS_TPOLY    LTPOLY
-  RDS_CONT     LCONT
-  RDS_ALU1     LALU1
-  RDS_VALU1    LVALU1
-  RDS_TALU1    LTALU1
-  RDS_VIA1     LVIA
-  RDS_TVIA1    LTVIA1
-  RDS_ALU2     LALU2
-  RDS_TALU2    LTALU2
-  RDS_VIA2     LVIA2
-  RDS_ALU3     LALU3
-  RDS_TALU3    LTALU3
-  RDS_VIA3     LVIA3
-  RDS_ALU4     LALU4
-  RDS_TALU4    LTALU4
-  RDS_VIA4     LVIA4
-  RDS_ALU5     LALU5
-  RDS_TALU5    LTALU5
-  RDS_VIA5     LVIA5
-  RDS_ALU6     LALU6
-  RDS_TALU6    LTALU6
-  RDS_REF      LREF
-
-END
-
-##-------------------------------------------------------------------
-# TABLE GDS_LAYER :
-##-------------------------------------------------------------------
-
-TABLE GDS_LAYER
-
-  RDS_NWELL    1
-  RDS_NDIF     3
-  RDS_PDIF     4
-  RDS_NTIE     5
-  RDS_PTIE     6
-  RDS_POLY     7
-  RDS_POLY2    8
-  RDS_TPOLY    9
-  RDS_CONT    10
-  RDS_ALU1    11
-  RDS_VALU1   12
-  RDS_TALU1   13
-  RDS_VIA1    14
-  RDS_TVIA1   15
-  RDS_ALU2    16
-  RDS_TALU2   17
-  RDS_VIA2    18
-  RDS_ALU3    19
-  RDS_TALU3   20
-  RDS_VIA3    21
-  RDS_ALU4    22
-  RDS_TALU4   23
-  RDS_VIA4    25
-  RDS_ALU5    26
-  RDS_TALU5   27
-  RDS_VIA5    28
-  RDS_ALU6    29
-  RDS_TALU6   30
-  RDS_REF     24
-
-END
-
-##-------------------------------------------------------------------
-# TABLE S2R_POST_TREAT :
-##-------------------------------------------------------------------
-
-TABLE S2R_POST_TREAT
-
-END
-DRC_RULES
-
-layer RDS_NWELL 4.;
-layer RDS_NTIE 2.;
-layer RDS_PTIE 2.;
-layer RDS_NDIF 2.;
-layer RDS_PDIF 2.;
-layer RDS_ACTIV 2.;
-layer RDS_CONT 1.;
-layer RDS_VIA1 1.;
-layer RDS_VIA2 1.;
-layer RDS_VIA3 1.;
-layer RDS_VIA4 1.;
-layer RDS_VIA5 1.;
-layer RDS_POLY 1.;
-layer RDS_POLY2 1.;
-layer RDS_ALU1 1.;
-layer RDS_ALU2 2.;
-layer RDS_ALU3 2.;
-layer RDS_ALU4 2.;
-layer RDS_ALU5 2.;
-layer RDS_ALU6 2.;
-layer RDS_USER0 1.;
-layer RDS_USER1 1.;
-layer RDS_USER2 1.;
-
-regles
-
-# Note : ``min'' is different from ``>=''. 
-# min is applied on polygons and >= is applied on rectangles.
-# There is the same difference between max and <=.
-# >= is faster than min, but min must be used where it is
-# required to consider polygons, for example distance of
-# two objects in the same layer 
-#
-# There is no rule to check NTIE and PDIF are included in NWELL
-# since this is necessarily true
-#----------------------------------------------------------- 
-
-# Check the NWELL shapes
-#-----------------------
-caracterise RDS_NWELL (
-  regle 1 : largeur >= 4. ;
-  regle 2 : longueur_inter min 4. ;
-  regle 3 : notch >= 12. ;
-);
-relation RDS_NWELL , RDS_NWELL (
-  regle 4 : distance axiale min 12. ;
-);
-
-# Check RDS_PTIE is really excluded outside NWELL
-#------------------------------------------------
-relation RDS_PTIE , RDS_NWELL (
-  regle 5 : distance axiale >= 7.5;
-  regle 6 : enveloppe longueur_inter < 0. ;
-  regle 7 : marge longueur_inter < 0. ;
-  regle 8 : croix longueur_inter < 0. ;
-  regle 9 : intersection longueur_inter < 0. ;
-  regle 10 : extension longueur_inter < 0. ;
-  regle 11 : inclusion longueur_inter < 0. ;
-);
-
-# Check RDS_NDIF is really excluded outside NWELL
-#------------------------------------------------
-relation RDS_NDIF , RDS_NWELL (
-  regle 12 : distance axiale >= 7.5;
-  regle 13 : enveloppe longueur_inter < 0. ;
-  regle 14 : marge longueur_inter < 0. ;
-  regle 15 : croix longueur_inter < 0. ;
-  regle 16 : intersection longueur_inter < 0. ;
-  regle 17 : extension longueur_inter < 0. ;
-  regle 18 : inclusion longueur_inter < 0. ;
-);
-
-# Check the RDS_PDIF shapes
-#--------------------------
-caracterise RDS_PDIF (
-  regle 19 : largeur >= 2. ;
-  regle 20 : longueur_inter min 2. ;
-  regle 21 : notch >= 3. ;
-);
-relation RDS_PDIF , RDS_PDIF (
-  regle 22 : distance axiale min 3. ;
-);
-
-# Check the RDS_NDIF shapes
-#--------------------------
-caracterise RDS_NDIF (
-  regle 23 : largeur >= 2. ;
-  regle 24 : longueur_inter min 2. ;
-  regle 25 : notch >= 3. ;
-);
-relation RDS_NDIF , RDS_NDIF (
-  regle 26 : distance axiale min 3. ;
-);
-
-# Check the RDS_PTIE shapes
-#--------------------------
-caracterise RDS_PTIE (
-  regle 27 : largeur >= 2. ;
-  regle 28 : longueur_inter min 2. ;
-  regle 29 : notch >= 3. ;
-);
-relation RDS_PTIE , RDS_PTIE (
-  regle 30 : distance axiale min 3. ;
-);
-
-# Check the RDS_NTIE shapes
-#--------------------------
-caracterise RDS_NTIE (
-  regle 31 : largeur >= 2. ;
-  regle 32 : longueur_inter min 2. ;
-  regle 33 : notch >= 3. ;
-);
-relation RDS_NTIE , RDS_NTIE (
-  regle 34 : distance axiale min 3. ;
-);
-
-define RDS_PDIF , RDS_PTIE union -> ANY_P_DIF;
-define RDS_NDIF , RDS_NTIE union -> ANY_N_DIF;
-
-# Check the ANY_N_DIF ANY_P_DIFF exclusion
-#--------------------------------------
-relation ANY_N_DIF , ANY_P_DIF (
-  regle 35 : distance axiale >= 3. ;
-  regle 36 : enveloppe longueur_inter < 0. ;
-  regle 37 : marge longueur_inter < 0. ;
-  regle 38 : croix longueur_inter < 0. ;
-  regle 39 : intersection longueur_inter < 0. ;
-  regle 40 : extension longueur_inter < 0. ;
-  regle 41 : inclusion longueur_inter < 0. ;
-);
-
-undefine ANY_P_DIF;
-undefine ANY_N_DIF;
-
-define RDS_NDIF , RDS_PDIF union -> NP_DIF;
-
-# Check RDS_POLY related to NP_DIF
-#---------------------------------
-relation RDS_POLY , NP_DIF (
-  regle 42 : distance axiale >= 1. ;
-  regle 43 : intersection longueur_inter < 0. ;
-);
-
-define NP_DIF , RDS_POLY intersection -> CHANNEL;
-
-# Check the RDS_POLY shapes
-#--------------------------
-caracterise RDS_POLY (
-  regle 44 : largeur >= 1. ;
-  regle 45 : longueur_inter min 1. ;
-  regle 46 : notch >= 2. ;
-);
-relation RDS_POLY , RDS_POLY (
-  regle 47 : distance axiale min 2.;
-);
-
-define NP_DIF , RDS_CONT intersection -> CONT_DIFF;
-# Check the CHANNEL shapes
-#--------------------------
-caracterise CHANNEL (
-  regle 48 : notch >= 3. ;
-);
-relation CHANNEL , CHANNEL (
-  regle 49 : distance axiale min 3.;
-);
-
-undefine CHANNEL;
-
-# Check RDS_POLY is distant from ACTIV ZONE of TRANSISTOR
-#--------------------------------------------------------
-relation RDS_POLY , RDS_ACTIV (
-  regle 79 : distance axiale >= 1. ;
-);
-
-relation RDS_POLY , CONT_DIFF (
-  regle 50 : distance axiale >= 2. ;
-);
-
-undefine CONT_DIFF;
-undefine NP_DIF;
-
-
-# Check RDS_ALU1 shapes
-#----------------------
-caracterise RDS_ALU1 (
-  regle 51 : largeur >= 1. ;
-  regle 52 : longueur_inter min 1. ;
-  regle 53 : notch >= 3. ;
-);
-relation RDS_ALU1 , RDS_ALU1 (
-  regle 54 : distance axiale min 3. ;
-);
-
-# Check RDS_ALU2 shapes
-#----------------------
-caracterise RDS_ALU2 (
-  regle 55 : largeur >= 2. ;
-  regle 56 : longueur_inter min 2. ;
-  regle 57 : notch >= 3. ;
-);
-relation RDS_ALU2 , RDS_ALU2 (
-  regle 58 : distance axiale min 3. ;
-);
-
-# Check RDS_ALU3 shapes
-#----------------------
-caracterise RDS_ALU3 (
-  regle 59 : largeur >= 2. ;
-  regle 60 : longueur_inter min 2. ;
-  regle 61 : notch >= 3. ;
-);
-relation RDS_ALU3 , RDS_ALU3 (
-  regle 62 : distance axiale min 3. ;
-);
-
-# Check RDS_ALU4 shapes
-#----------------------
-caracterise RDS_ALU4 (
-  regle 63 : largeur >= 2. ;
-  regle 64 : longueur_inter min 2. ;
-  regle 65 : notch >= 3. ;
-);
-relation RDS_ALU4 , RDS_ALU4 (
-  regle 66 : distance axiale min 3. ;
-);
-
-# Check RDS_ALU5 shapes
-#----------------------
-caracterise RDS_ALU5 (
-  regle 80 : largeur >= 2. ;
-  regle 81 : longueur_inter min 2. ;
-  regle 82 : notch >= 8. ;
-);
-relation RDS_ALU5 , RDS_ALU5 (
-  regle 83 : distance axiale min 8. ;
-);
-
-# Check RDS_ALU6 shapes
-#----------------------
-caracterise RDS_ALU6 (
-  regle 84 : largeur >= 2. ;
-  regle 85 : longueur_inter min 2. ;
-  regle 86 : notch >= 8. ;
-);
-relation RDS_ALU6 , RDS_ALU6 (
-  regle 87 : distance axiale min 8. ;
-);
-
-# Check ANY_VIA layers, stacking are free
-#----------------------------------------
-relation RDS_CONT , RDS_CONT (
-  regle 67 : distance axiale >= 3. ;
-);
-relation RDS_VIA , RDS_VIA (
-  regle 68 : distance axiale >= 4. ;
-);
-relation RDS_VIA2 , RDS_VIA2 (
-  regle 69 : distance axiale >= 4. ;
-);
-relation RDS_VIA3 , RDS_VIA3 (
-  regle 70 : distance axiale >= 4. ;
-);
-relation RDS_VIA4 , RDS_VIA4 (
-  regle 88 : distance axiale >= 9. ;
-);
-relation RDS_VIA5 , RDS_VIA5 (
-  regle 89 : distance axiale >= 9. ;
-);
-caracterise RDS_CONT (
-  regle 71 : largeur >= 1. ;
-  regle 72 : longueur <= 1. ;
-);
-caracterise RDS_VIA (
-  regle 73 : largeur >= 1. ;
-  regle 74 : longueur <= 1. ;
-);
-caracterise RDS_VIA2 (
-  regle 75 : largeur >= 1. ;
-  regle 76 : longueur <= 1. ;
-);
-caracterise RDS_VIA3 (
-  regle 77 : largeur >= 1. ;
-  regle 78 : longueur <= 1. ;
-);
-caracterise RDS_VIA4 (
-  regle 90 : largeur >= 1. ;
-  regle 91 : longueur <= 1. ;
-);
-caracterise RDS_VIA5 (
-  regle 92 : largeur >= 1. ;
-  regle 93 : longueur <= 1. ;
-);
-
-# Check the POLY2 shapes
-#-----------------------
-caracterise RDS_POLY2 (
-  regle 94 : largeur >= 1. ;
-  regle 95 : longueur_inter min 1. ;
-  regle 96 : notch >= 5. ;
-);
-relation RDS_POLY2 , RDS_POLY2 (
-  regle 97 : distance axiale min 5. ;
-);
-
-# Check RDS_POLY2 is really included inside RDS_POLY1
-#----------------------------------------------------
-relation RDS_POLY , RDS_POLY2 (
-  regle 98 : distance axiale < 0.;
-  regle 99 : enveloppe inferieure min 5. ;
-  regle 100 : marge longueur_inter < 0. ;
-  regle 101 : croix longueur_inter < 0. ;
-  regle 102 : intersection longueur_inter < 0. ;
-  regle 103 : extension longueur_inter < 0. ;
-  regle 104 : inclusion longueur_inter < 0. ;
-);
-
-
-fin regles
-DRC_COMMENT
-1 (RDS_NWELL) minimum width 4. 
-2 (RDS_NWELL) minimum width 4. 
-3 (RDS_NWELL) Manhatan distance min 12. 
-4 (RDS_NWELL,RDS_NWELL) Manhatan distance min 12. 
-5 (RDS_PTIE,RDS_NWELL) Manhatan distance min 7.5
-6 (RDS_PTIE,RDS_NWELL) must never been in contact
-7 (RDS_PTIE,RDS_NWELL) must never been in contact
-8 (RDS_PTIE,RDS_NWELL) must never been in contact
-9 (RDS_PTIE,RDS_NWELL) must never been in contact
-10 (RDS_PTIE,RDS_NWELL) must never been in contact
-11 (RDS_PTIE,RDS_NWELL) must never been in contact
-12 (RDS_NDIF,RDS_NWELL) Manhatan distance min 7.5
-13 (RDS_NDIF,RDS_NWELL) must never been in contact
-14 (RDS_NDIF,RDS_NWELL) must never been in contact
-15 (RDS_NDIF,RDS_NWELL) must never been in contact
-16 (RDS_NDIF,RDS_NWELL) must never been in contact
-17 (RDS_NDIF,RDS_NWELL) must never been in contact
-18 (RDS_NDIF,RDS_NWELL) must never been in contact
-19 (RDS_PDIF) minimum width 2. 
-20 (RDS_PDIF) minimum width 2. 
-21 (RDS_PDIF) Manhatan distance min 3. 
-22 (RDS_PDIF,RDS_PDIF) Manhatan distance min 3. 
-23 (RDS_NDIF) minimum width 2. 
-24 (RDS_NDIF) minimum width 2. 
-25 (RDS_NDIF) Manhatan distance min 3. 
-26 (RDS_NDIF,RDS_NDIF) Manhatan distance min 3. 
-27 (RDS_PTIE) minimum width 2. 
-28 (RDS_PTIE) minimum width 2. 
-29 (RDS_PTIE) Manhatan distance min 3. 
-30 (RDS_PTIE,RDS_PTIE) Manhatan distance min 3. 
-31 (RDS_NTIE) minimum width 2. 
-32 (RDS_NTIE) minimum width 2. 
-33 (RDS_NTIE) Manhatan distance min 3. 
-34 (RDS_NTIE,RDS_NTIE) Manhatan distance min 3. 
-35 (ANY_N_DIF,ANY_P_DIF) Manhatan distance min 3. 
-36 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-37 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-38 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-39 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-40 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-41 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-42 (RDS_POLY,ANY_N_DIF) Manhatan distance min 1. 
-43 (RDS_POLY,NP_DIF) bad intersection
-44 (RDS_POLY) minimum width 1. 
-45 (RDS_POLY) minimum width 1. 
-46 (RDS_POLY) Manhatan distance min 2. 
-47 (RDS_POLY,RDS_POLY) Manhatan distance min 2.
-48 (CHANNEL) Manhatan distance min 3. 
-49 (CHANNEL,CHANNEL) Manhatan distance min 3.
-50 (RDS_POLY,CONT_DIFF) Manhatan distance min 2. 
-51 (RDS_ALU1) minimum width 1. 
-52 (RDS_ALU1) minimum width 1. 
-53 (RDS_ALU1) Manhatan distance min 3.
-54 (RDS_ALU1,RDS_ALU1) Manhatan distance min 3.
-55 (RDS_ALU2) minimum width 2. 
-56 (RDS_ALU2) minimum width 2. 
-57 (RDS_ALU2) Manhatan distance min 3. 
-58 (RDS_ALU2,RDS_ALU2) Manhatan distance min 3. 
-59 (RDS_ALU3) minimum width 2. 
-60 (RDS_ALU3) minimum width 2. 
-61 (RDS_ALU3) Manhatan distance min 3. 
-62 (RDS_ALU3,RDS_ALU3) Manhatan distance min 3. 
-63 (RDS_ALU4) minimum width 2. 
-64 (RDS_ALU4) minimum width 2. 
-65 (RDS_ALU4) Manhatan distance min 3. 
-66 (RDS_ALU4,RDS_ALU4) Manhatan distance min 3. 
-67 (RDS_CONT,RDS_CONT) Manhatan distance min 3. 
-68 (RDS_VIA,RDS_VIA) Manhatan distance min 4. 
-69 (RDS_VIA2,RDS_VIA2) Manhatan distance min 4. 
-70 (RDS_VIA3,RDS_VIA3) Manhatan distance min 4. 
-71 (RDS_CONT) minimum width 1. 
-72 (RDS_CONT) maximum length 1. 
-73 (RDS_VIA) minimum width 1. 
-74 (RDS_VIA) maximum length 1. 
-75 (RDS_VIA2) minimum width 1. 
-76 (RDS_VIA2) maximum length 1. 
-77 (RDS_VIA3) minimum width 1. 
-78 (RDS_VIA3) maximum length 1. 
-79 (RDS_POLY,RDS_ACTIV) Manhatan distance min 1. 
-80 (RDS_ALU5) minimum width 2. 
-81 (RDS_ALU5) minimum width 2. 
-82 (RDS_ALU5) Manhatan distance min 8. 
-83 (RDS_ALU5,RDS_ALU5) Manhatan distance min 8. 
-84 (RDS_ALU6) minimum width 2. 
-85 (RDS_ALU6) minimum width 2. 
-86 (RDS_ALU6) Manhatan distance min 8. 
-87 (RDS_ALU6,RDS_ALU6) Manhatan distance min 8. 
-88 (RDS_VIA4,RDS_VIA4) Manhatan distance min 9. 
-89 (RDS_VIA5,RDS_VIA5) Manhatan distance min 9. 
-90 (RDS_VIA4) minimum width 1. 
-91 (RDS_VIA4) maximum length 1. 
-92 (RDS_VIA5) minimum width 1. 
-93 (RDS_VIA5) maximum length 1. 
-94 (RDS_POLY2) minimum width 1. 
-95 (RDS_POLY2) minimum width 1. 
-96 (RDS_POLY2) Manhatan distance min 5. 
-97 (RDS_POLY2,POLY2) Manhatan distance min 5. 
-98 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. 
-99 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. 
-100 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. 
-101 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. 
-102 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. 
-103 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. 
-104 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. 
-END_DRC_COMMENT
-END_DRC_RULES
diff --git a/alliance/share/etc/cmos_7.dreal b/alliance/share/etc/cmos_7.dreal
deleted file mode 100644
index ca8a1f51..00000000
--- a/alliance/share/etc/cmos_7.dreal
+++ /dev/null
@@ -1,120 +0,0 @@
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Title      :      Parameters File for Dreal                 |
-# |                                                             |
-# | Technology :              Cmos V7                           |
-# |                                                             |
-# | Date       :             02/08/95                           |
-# |                                                             |
-# \------------------------------------------------------------*/
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                   Lower Grid Step in pixel                  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE DREAL_LOWER_GRID_STEP 10
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |               Lower Figure Text Step in pixel               |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE DREAL_LOWER_FIGURE_STEP 0.1
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |              Lower Instance Text Step in pixel              |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE DREAL_LOWER_INSTANCE_STEP 0.1
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |             Lower Connector Text Step in pixel              |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE DREAL_LOWER_CONNECTOR_STEP 0.5
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |               Lower Segment Text Step in pixel              |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE DREAL_LOWER_SEGMENT_STEP 0.7
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |              Lower Reference Text Step in pixel             |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE DREAL_LOWER_REFERENCE_STEP 1.0
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                 Dreal Cursor Color Name                     |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE DREAL_CURSOR_COLOR_NAME  Gray
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                 Dreal Cursor Size in pixel                  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE DREAL_CURSOR_SIZE 10
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# | View Layer Panel Button Label, Foreground, Background Color |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE DREAL_RDS_LAYER_NAME
-
-  RDS_NWELL    Nwell   tan               Black
-  RDS_PWELL    Pwell   light_yellow      Black
-  RDS_NIMP     Nimp    forest_green      Black
-  RDS_PIMP     Pimp    goldenrod         Black
-  RDS_ACTIV    Activ   brown             Black
-  RDS_NDIF     Ndif    lawn_green        Black
-  RDS_PDIF     Pdif    yellow            Black
-  RDS_NTIE     Ntie    spring_green      Black
-  RDS_PTIE     Ptie    light_goldenrod   Black
-  RDS_POLY     Poly    red               Black
-  RDS_VPOLY    VPoly   coral             Black
-  RDS_GATE     Gate    orange            Black
-  RDS_TPOLY    Tpoly   hot_pink          Black
-  RDS_CONT     Cont    dark_violet       Black
-  RDS_TCONT    TCont   orchid            Black
-  RDS_ALU1     Alu1    royal_blue        Black
-  RDS_VALU1    VAlu1   sky_blue          Black
-  RDS_TALU1    Talu1   royal_blue        Black
-  RDS_VIA1     Via1    deep_sky_blue     Black
-  RDS_TVIA1    TVia1   dodger_blue       Black
-  RDS_ALU2     Alu2    cyan              Black
-  RDS_TALU2    Talu2   turquoise         Black
-  RDS_VIA2     Via2    deep_pink         Black
-  RDS_ALU3     Alu3    light_pink        Black
-  RDS_TALU3    Talu3   light_pink        Black
-  RDS_VIA3     Via3    sea_green         Black
-  RDS_ALU4     Alu4    green             Black
-  RDS_TALU4    Talu4   green             Black
-  RDS_VIA4     Via4    gold              Black
-  RDS_ALU5     Alu5    yellow            Black
-  RDS_TALU5    Talu5   yellow            Black
-  RDS_VIA5     Via5    violet_red        Black
-  RDS_ALU6     Alu6    violet            Black
-  RDS_TALU6    Talu6   violet            Black
-  RDS_CPAS     Cpas    gray              Black
-  RDS_REF      Ref     coral             Black
-  RDS_ABOX     Abox    pink              Black
-  
-END
diff --git a/alliance/share/etc/cmos_7.genview b/alliance/share/etc/cmos_7.genview
deleted file mode 100644
index 57356fb6..00000000
--- a/alliance/share/etc/cmos_7.genview
+++ /dev/null
@@ -1,170 +0,0 @@
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Title      :      Parameters File for Genview               |
-# |                                                             |
-# | Technology :               Cmos                             |
-# |                                                             |
-# | Date       :             17.08.95                           |
-# |                                                             |
-# \------------------------------------------------------------*/
-# /*------------------------------------------------------------\
-# |                                                             |
-# |               Genview Peek Bound in lambda                  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GENVIEW_PEEK_BOUND 7
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                       Segment name                          |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GENVIEW_SEGMENT_NAME
-
-  NWELL    Nwell  
-  PWELL    Pwell 
-  NDIF     Ndif 
-  PDIF     Pdif 
-  NTIE     Ntie
-  PTIE     Ptie
-  NTRANS   Ntrans
-  PTRANS   Ptrans
-  POLY     Poly
-  ALU1     Alu1
-  ALU2     Alu2
-  ALU3     Alu3
-  TPOLY    Tpoly
-  TALU1    Talu1
-  TALU2    Talu2
-  TALU3    Talu3
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                     Connector Name                          |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GENVIEW_CONNECTOR_NAME
-
-  POLY     Poly
-  ALU1     Alu1
-  ALU2     Alu2
-  ALU3     Alu3
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                      Reference Name                         |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GENVIEW_REFERENCE_NAME
-
-  REF_REF  Ref_Ref
-  REF_CON  Ref_Con
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                          Via Name                           |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GENVIEW_VIA_NAME
-
-  CONT_DIF_N   Cont_DifN
-  CONT_DIF_P   Cont_DifP
-  CONT_BODY_N  Cont_BodyN
-  CONT_BODY_P  Cont_BodyP
-  CONT_POLY    Cont_Poly
-  CONT_VIA     Cont_Via 
-  CONT_VIA2    Cont_Via2
-  C_X_N        Cont_CxN
-  C_X_P        Cont_CxP
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                    Connector Orient Name                    |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GENVIEW_ORIENT_NAME 
-
-  NORTH  North
-  SOUTH  South
-  EAST   East 
-  WEST   West
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                          Symmetry Name                      |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GENVIEW_SYMMETRY_NAME
-
-  NOSYM No_Sym
-  SYM_X Sym_X
-  SYM_Y Sym_Y
-  SYMXY Sym_XY
-  ROT_P Rot_P
-  ROT_M Rot_M
-  SY_RP Sym_RP
-  SY_RM Sym_RM
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                   Rds Layer Name and Color                  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GENVIEW_RDS_LAYER_NAME
-
-  RDS_NWELL    Nwell   tan              
-  RDS_PWELL    Pwell   light_yellow     
-  RDS_NIMP     Nimp    forest_green     
-  RDS_PIMP     Pimp    goldenrod        
-  RDS_ACTIV    Activ   brown            
-  RDS_NDIF     Ndif    lawn_green       
-  RDS_PDIF     Pdif    yellow           
-  RDS_NTIE     Ntie    spring_green     
-  RDS_PTIE     Ptie    light_goldenrod  
-  RDS_POLY     Poly    red              
-  RDS_VPOLY    VPoly   coral            
-  RDS_GATE     Gate    orange           
-  RDS_TPOLY    Tpoly   light_pink       
-  RDS_CONT     Cont    dark_violet      
-  RDS_TCONT    TCont   orchid           
-  RDS_ALU1     Alu1    royal_blue       
-  RDS_VALU1    VAlu1   sky_blue         
-  RDS_TALU1    Talu1   light_steel_blue 
-  RDS_VIA1     Via1    deep_sky_blue    
-  RDS_TVIA1    TVia1   dodger_blue      
-  RDS_ALU2     Alu2    Cyan             
-  RDS_VALU2    VAlu2   turquoise        
-  RDS_TALU2    Talu2   light_cyan       
-  RDS_VIA2     Via2    chocolate        
-  RDS_TVIA2    TVia2   sandy_brown      
-  RDS_ALU3     Alu3    peach_puff       
-  RDS_VALU3    VAlu3   dark_salmon      
-  RDS_TALU3    Talu3   bisque           
-  RDS_CPAS     Cpas    gray             
-  RDS_REF      Ref     coral            
-  RDS_USER0    User0   White
-  RDS_USER1    User1   Gray
-  RDS_USER2    User2   Gray
-  RDS_ABOX     Abox    pink             
-
-END
diff --git a/alliance/share/etc/cmos_7.graal b/alliance/share/etc/cmos_7.graal
deleted file mode 100644
index e99efef8..00000000
--- a/alliance/share/etc/cmos_7.graal
+++ /dev/null
@@ -1,293 +0,0 @@
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Title      :      Parameters File for Graal                 |
-# |                                                             |
-# | Technology :              Cmos V7                           |
-# |                                                             |
-# | Date       :             27/06/95                           |
-# |                                                             |
-# \------------------------------------------------------------*/
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                 Graal Peek Bound in lambda                  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_PEEK_BOUND 7
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |               Lower Grid Step in pixel by lambda            |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_LOWER_GRID_STEP 10
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |          Lower Figure Text Step in pixel by lambda          |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_LOWER_FIGURE_STEP 1
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |         Lower Instance Text Step in pixel by lambda         |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_LOWER_INSTANCE_STEP 1
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |        Lower Connector Text Step in pixel by lambda         |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_LOWER_CONNECTOR_STEP 5
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |          Lower Segment Text Step in pixel by lambda         |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_LOWER_SEGMENT_STEP 7
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |         Lower Reference Text Step in pixel by lambda        |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_LOWER_REFERENCE_STEP 10
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                 Graal Cursor Color Name                     |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_CURSOR_COLOR_NAME  Gray
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                 Graal Cursor Size in pixel                  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_CURSOR_SIZE 10 
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |  Segment Panel Button Label, Foreground , Background Color  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_SEGMENT_NAME
-
-  NWELL    Nwell  tan              Black
-  PWELL    Pwell  light_yellow     Black
-  NDIF     Ndif   lawn_green       Black
-  PDIF     Pdif   yellow           Black
-  NTIE     Ntie   spring_green     Black
-  PTIE     Ptie   light_goldenrod  Black
-  POLY     Poly   red              Black
-  ALU1     Alu1   royal_blue       Black
-  ALU2     Alu2   Cyan             Black
-  ALU3     Alu3   light_pink       Black
-  ALU4     Alu4   green            Black
-  ALU5     Alu5   yellow           Black
-  ALU6     Alu6   violet           Black
-  TPOLY    Tpoly  hot_pink         Black
-  TALU1    Talu1  royal_blue       Black
-  TALU2    Talu2  turquoise        Black
-  TALU3    Talu3  light_pink       Black
-  TALU4    Talu4  green            Black
-  TALU5    Talu5  yellow           Black
-  TALU6    Talu6  violet           Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Transistor Panel Button Label, Foreground, Background Color |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_TRANSISTOR_NAME
-
-  NTRANS   Ntrans lawn_green       Black
-  PTRANS   Ptrans yellow           Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Connector Panel Button Label, Foreground , Background Color |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_CONNECTOR_NAME
-
-  POLY     Poly   red              Black
-  ALU1     Alu1   royal_blue       Black
-  ALU2     Alu2   Cyan             Black
-  ALU3     Alu3   light_pink       Black
-  ALU4     Alu4   green            Black
-  ALU5     Alu5   yellow           Black
-  ALU6     Alu6   violet           Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |       Minimun Length and Width for a symbolic Segment       |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_SEGMENT_VALUE
-
-  NWELL    4   4
-  PWELL    4   4
-  NDIF     2   2
-  PDIF     2   2
-  NTIE     2   2
-  PTIE     2   2
-  NTRANS   1   4
-  PTRANS   1   4
-  POLY     1   1
-  ALU1     1   1
-  ALU2     2   2
-  ALU3     2   2
-  ALU4     2   2
-  ALU5     4   4
-  ALU6     4   4
-  TPOLY    1   1
-  TALU1    1   1
-  TALU2    2   2
-  TALU3    2   2
-  TALU4    2   2
-  TALU5    2   2
-  TALU6    2   2
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Reference Panel Button Label, Foreground, Background Color  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_REFERENCE_NAME
-
-  REF_REF  Ref_Ref red  Black
-  REF_CON  Ref_Con Cyan Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |     Via Panel Button Label, Foreground , Background Color   |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_VIA_NAME
-
-  CONT_DIF_N   Cont_NDif   lawn_green       Black
-  CONT_DIF_P   Cont_PDif   yellow           Black
-  CONT_BODY_N  Cont_NTie   spring_green     Black
-  CONT_BODY_P  Cont_PTie   light_goldenrod  Black
-  CONT_POLY    Cont_Poly   red              Black
-  CONT_VIA     Via_1-2     cyan             Black
-  CONT_VIA2    Via_2-3     light_pink       Black
-  CONT_VIA3    Via_3-4     green            Black
-  CONT_VIA4    Via_4-5     yellow           Black
-  CONT_VIA5    Via_5-6     violet           Black
-  C_X_N        Cont_CxN    orange           Black
-  C_X_P        Cont_CxP    orange           Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |   Orient Panel Button Label, Foreground , Background Color  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_ORIENT_NAME 
-
-  NORTH  North   lawn_green  Black
-  SOUTH  South   yellow      Black
-  EAST   East    tan         Black
-  WEST   West    red         Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Symmetry Panel Button Label, Foreground , Background Color  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_SYMMETRY_NAME
-
-  NOSYM No_Sym  LightBlue         Black
-  SYM_X Sym_X   turquoise         Black
-  SYM_Y Sym_Y   cyan              Black
-  SYMXY Sym_XY  LightCyan         Black
-  ROT_P Rot_P   MediumAquamarine  Black
-  ROT_M Rot_M   aquamarine        Black
-  SY_RP Sym_RP  green             Black
-  SY_RM Sym_RM  MediumSpringGreen Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# | View Layer Panel Button Label, Foreground, Background Color |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_RDS_LAYER_NAME
-
-  RDS_NWELL    Nwell   tan               Black
-  RDS_PWELL    Pwell   light_yellow      Black
-  RDS_NIMP     Nimp    forest_green      Black
-  RDS_PIMP     Pimp    goldenrod         Black
-  RDS_ACTIV    Activ   brown             Black
-  RDS_NDIF     Ndif    lawn_green        Black
-  RDS_PDIF     Pdif    yellow            Black
-  RDS_NTIE     Ntie    spring_green      Black
-  RDS_PTIE     Ptie    light_goldenrod   Black
-  RDS_POLY     Poly    red               Black
-  RDS_VPOLY    VPoly   coral             Black
-  RDS_GATE     Gate    orange            Black
-  RDS_TPOLY    Tpoly   hot_pink          Black
-  RDS_CONT     Cont    dark_violet       Black
-  RDS_TCONT    TCont   orchid            Black
-  RDS_ALU1     Alu1    royal_blue        Black
-  RDS_VALU1    VAlu1   sky_blue          Black
-  RDS_TALU1    Talu1   royal_blue        Black
-  RDS_VIA1     Via1    deep_sky_blue     Black
-  RDS_TVIA1    TVia1   dodger_blue       Black
-  RDS_ALU2     Alu2    cyan              Black
-  RDS_TALU2    Talu2   turquoise         Black
-  RDS_VIA2     Via2    deep_pink         Black
-  RDS_ALU3     Alu3    light_pink        Black
-  RDS_TALU3    Talu3   light_pink        Black
-  RDS_VIA3     Via3    sea_green         Black
-  RDS_ALU4     Alu4    green             Black
-  RDS_TALU4    Talu4   green             Black
-  RDS_VIA4     Via4    gold              Black
-  RDS_ALU5     Alu5    yellow            Black
-  RDS_TALU5    Talu5   yellow            Black
-  RDS_VIA5     Via5    violet_red        Black
-  RDS_ALU6     Alu6    violet            Black
-  RDS_TALU6    Talu6   violet            Black
-  RDS_CPAS     Cpas    gray              Black
-  RDS_REF      Ref     coral             Black
-  RDS_ABOX     Abox    pink              Black
-
-END
diff --git a/alliance/share/etc/cmos_7.rds b/alliance/share/etc/cmos_7.rds
deleted file mode 100644
index 4ff08ad4..00000000
--- a/alliance/share/etc/cmos_7.rds
+++ /dev/null
@@ -1,768 +0,0 @@
-#=====================================================================
-#
-#                         ALLIANCE VLSI CAD                  
-#            (R)eal (D)ata (S)tructure parameter file
-#         (c) copyright 1992 Laboratory UPMC/MASI/CAO-VLSI   
-#                        all rights reserved                 
-#                   e-mail : cao-vlsi@masi.ibp.fr            
-#
-#                   file       : cmos_7.rds
-#                   version    : 10
-#                   last modif : Nov 4, 1999
-#
-##-------------------------------------------------------------------
-# Symbolic to micron on a 'one lambda equals one micron' basis
-##-------------------------------------------------------------------
-# Refer to the documentation for more precise information.
-#=====================================================================
-# 99/11/4 old rules 
-# . for ALU1, ALU2, GATE
-# . however stacked are allowed
-# 
-# 99/11/3 ALU5/6 rules
-# . theses rules are preliminary rules, we hope that they wil change
-#   in future. For now, ALU5/6 are dedicated to supplies an clock.
-# 
-# 99/3/22 new symbolics rules
-# . ALU1 width remains 1, ALU2/3/4 is 2
-# . ALU1/2/3/4 distance (edge to edge) is now 3 for all
-# . GATE to GATE distance is 3 but POLY wire to POLY wire remains 2
-# . All via stacking are allowed
-#
-# 98/12/1 drc rules were updated
-# distance VIA to POLY or gate is one rather 2
-# VIA2 and ALU3 appeared
-# . ALU3 width is 3
-# . ALU2/VIA2/ALU3 is resp. 3/1/3
-# . ALU3 edge distance is 2
-# . stacked VIA/VIA2 is allowed
-# . if they are not stacked they must distant of 2
-# . CONT/VIA2 is free
-# note
-# . stacked CONT/VIA is always not allowed
-# NWELL is automatically drawn with the DIFN and NTIE layers
-#=====================================================================
-
-##-------------------------------------------------------------------
-# PHYSICAL_GRID :
-##-------------------------------------------------------------------
-
-DEFINE  PHYSICAL_GRID  .5
-
-##-------------------------------------------------------------------
-# LAMBDA : 
-##-------------------------------------------------------------------
-
-DEFINE  LAMBDA         1
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_SEGMENT :
-#
-# MBK      RDS layer 1                 RDS layer 2         
-# name     name TRANS DLR DWR OFFSET   name TRANS DLR DWR OFFSET  ...
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_SEGMENT
-
-  NWELL    RDS_NWELL  VW  0.0  0.0  0.0  ALL
-  NDIF     RDS_NDIF   VW  0.5  0.0  0.0  ALL
-  PDIF     RDS_PDIF   VW  0.5  0.0  0.0  ALL \
-           RDS_NWELL  VW  1.0  1.0  0.0  ALL
-  NTIE     RDS_NTIE   VW  0.5  0.0  0.0  ALL \
-           RDS_NWELL  VW  1.0  1.0  0.0  ALL
-  PTIE     RDS_PTIE   VW  0.5  0.0  0.0  ALL
-  NTRANS   RDS_POLY   VW  0.0  0.0  0.0  ALL \
-           RDS_NDIF  LCW -1.5  2.0  0.0  EXT \
-           RDS_NDIF  RCW -1.5  2.0  0.0  EXT \
-           RDS_NDIF   VW -1.5  4.0  0.0  DRC  
-  PTRANS   RDS_POLY   VW  0.0  0.0  0.0  ALL \
-           RDS_PDIF  LCW -1.5  2.0  0.0  EXT \
-           RDS_PDIF  RCW -1.5  2.0  0.0  EXT \
-           RDS_PDIF   VW -1.5  4.0  0.0  DRC \
-           RDS_NWELL  VW -1.0  5.0  0.0  ALL 
-  POLY     RDS_POLY   VW  0.5  0.0  0.0  ALL
-  ALU1     RDS_ALU1   VW  0.5  0.0  0.0  ALL
-  ALU2     RDS_ALU2   VW  1.0  0.0  0.0  ALL
-  ALU3     RDS_ALU3   VW  1.0  0.0  0.0  ALL
-  ALU4     RDS_ALU4   VW  1.0  0.0  0.0  ALL
-  ALU5     RDS_ALU5   VW  1.0  0.0  0.0  ALL
-  ALU6     RDS_ALU6   VW  1.0  0.0  0.0  ALL 
-  TPOLY    RDS_TPOLY  VW  0.5  0.0  0.0  ALL
-  TALU1    RDS_TALU1  VW  0.5  0.0  0.0  ALL
-  TALU2    RDS_TALU2  VW  1.0  0.0  0.0  ALL
-  TALU3    RDS_TALU3  VW  1.0  0.0  0.0  ALL
-  TALU4    RDS_TALU4  VW  1.0  0.0  0.0  ALL
-  TALU5    RDS_TALU5  VW  1.0  0.0  0.0  ALL
-  TALU6    RDS_TALU6  VW  1.0  0.0  0.0  ALL
-
-END
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_CONNECTOR :
-#
-# MBK      RDS layer 
-# name     name     DER DWR 
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_CONNECTOR
-
-  POLY    RDS_POLY  .5  0  
-  ALU1    RDS_ALU1  .5  0  
-  ALU2    RDS_ALU2 1.0  0  
-  ALU3    RDS_ALU3 1.0  0  
-  ALU4    RDS_ALU4 1.0  0  
-  ALU5    RDS_ALU4 1.0  0  
-  ALU6    RDS_ALU4 1.0  0  
-
-END
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_REFERENCE :
-#
-# MBK ref    RDS layer 
-# name       name       width
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_REFERENCE
-
-  REF_REF    RDS_REF    1
-  REF_CON    RDS_VALU1  2  RDS_TVIA1 1  RDS_TALU2  2
-
-END
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_VIA1 :
-#
-# MBK via      RDS layer 1  RDS  layer 2  RDS  layer 3  RDS layer 4      
-# name         name  width  name   width  name   width  name  width  
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_VIA
-
-  CONT_BODY_P  RDS_ALU1 2 ALL  RDS_CONT 1 ALL  RDS_PTIE 3 ALL  
-  CONT_BODY_N  RDS_ALU1 2 ALL  RDS_CONT 1 ALL  RDS_NTIE 3 ALL  RDS_NWELL 4 ALL
-  CONT_DIF_N   RDS_ALU1 2 ALL  RDS_CONT 1 ALL  RDS_NDIF 3 ALL
-  CONT_DIF_P   RDS_ALU1 2 ALL  RDS_CONT 1 ALL  RDS_PDIF 3 ALL  RDS_NWELL 4 ALL
-  CONT_POLY    RDS_ALU1 2 ALL  RDS_CONT 1 ALL  RDS_POLY 3 ALL
-  CONT_VIA     RDS_ALU1 2 ALL  RDS_VIA1 1 ALL  RDS_ALU2 3 ALL
-  CONT_VIA2    RDS_ALU2 3 ALL  RDS_VIA2 1 ALL  RDS_ALU3 2 ALL
-  CONT_VIA3    RDS_ALU3 2 ALL  RDS_VIA3 1 ALL  RDS_ALU4 2 ALL
-  CONT_VIA4    RDS_ALU4 2 ALL  RDS_VIA4 1 ALL  RDS_ALU5 2 ALL
-  CONT_VIA5    RDS_ALU5 2 ALL  RDS_VIA5 1 ALL  RDS_ALU6 2 ALL
-  C_X_N        RDS_POLY 1 ALL  RDS_NDIF 5 ALL
-  C_X_P        RDS_POLY 1 ALL  RDS_PDIF 5 ALL  RDS_NWELL 6 ALL
-
-END
-
-##-------------------------------------------------------------------
-# TABLE LYNX_GRAPH :
-#
-# RDS layer   Rds layer 1   Rds layer 2    ...
-# name        name          name           ...
-##-------------------------------------------------------------------
-
-TABLE LYNX_GRAPH
-
-  RDS_NDIF  RDS_CONT RDS_NDIF
-  RDS_PDIF  RDS_CONT RDS_PDIF
-  RDS_NTIE  RDS_CONT RDS_NTIE
-  RDS_PTIE  RDS_CONT RDS_PTIE
-  RDS_POLY  RDS_CONT RDS_POLY 
-  RDS_CONT  RDS_PDIF RDS_NDIF RDS_POLY RDS_PTIE  RDS_NTIE RDS_ALU1 RDS_CONT
-  RDS_ALU1  RDS_CONT RDS_VIA1 RDS_ALU1 RDS_VALU1 RDS_ALU1
-  RDS_VALU1 RDS_CONT RDS_VIA1 RDS_ALU1 RDS_VALU1
-  RDS_VIA1  RDS_ALU1 RDS_ALU2 RDS_VIA1
-  RDS_VIA2  RDS_ALU2 RDS_ALU3 RDS_VIA2
-  RDS_VIA3  RDS_ALU3 RDS_ALU4 RDS_VIA3
-  RDS_VIA4  RDS_ALU4 RDS_ALU5 RDS_VIA4
-  RDS_VIA5  RDS_ALU5 RDS_ALU6 RDS_VIA5
-  RDS_ALU2  RDS_VIA1 RDS_VIA2 RDS_ALU2 
-  RDS_ALU3  RDS_VIA2 RDS_VIA3 RDS_ALU3
-  RDS_ALU4  RDS_VIA3 RDS_VIA4 RDS_ALU4 
-  RDS_ALU5  RDS_VIA4 RDS_VIA5 RDS_ALU5 
-  RDS_ALU6  RDS_VIA5          RDS_ALU6 
-
-END
-
-##-------------------------------------------------------------------
-# TABLE LYNX_CAPA : 
-#
-# RDS layer   Surface capacitance  Perimetric capacitance
-# name        piF / Micron^2       piF / Micron 
-##-------------------------------------------------------------------
-
-TABLE LYNX_CAPA
-
-  RDS_POLY    1.00e-04    1.00e-04
-  RDS_ALU1    0.50e-04    0.90e-04
-  RDS_ALU2    0.25e-04    0.95e-04
-  RDS_ALU3    0.25e-04    0.95e-04
-  RDS_ALU4    0.25e-04    0.95e-04
-  RDS_ALU5    0.25e-04    0.95e-04
-  RDS_ALU6    0.25e-04    0.95e-04
-
-END
-
-##-------------------------------------------------------------------
-# TABLE LYNX_RESISTOR :
-#
-# RDS layer   Surface resistor
-# name        Ohm / Micron^2 
-##-------------------------------------------------------------------
-
-TABLE LYNX_RESISTOR
-
-  RDS_POLY    50.0
-  RDS_ALU1     0.1
-  RDS_ALU2     0.05
-  RDS_ALU3     0.05
-  RDS_ALU4     0.05
-  RDS_ALU5     0.05
-  RDS_ALU6     0.05
-
-END
-
-##-------------------------------------------------------------------
-# TABLE LYNX_TRANSISTOR : 
-#
-# MBK layer  Transistor Type  MBK via
-# name       name             name
-##-------------------------------------------------------------------
-
-TABLE LYNX_TRANSISTOR
-
-  NTRANS  NTRANS  C_X_N   RDS_POLY   RDS_NDIF  RDS_NDIF
-  PTRANS  PTRANS  C_X_P   RDS_POLY   RDS_PDIF  RDS_PDIF
-
-END
-
-##-------------------------------------------------------------------
-# TABLE LYNX_DIFFUSION :
-#
-# RDS layer  RDS layer
-# name       name    
-##-------------------------------------------------------------------
-
-TABLE LYNX_DIFFUSION
-END
-
-##-------------------------------------------------------------------
-# TABLE S2R_OVERSIZE_DENOTCH :
-##-------------------------------------------------------------------
-
-TABLE S2R_OVERSIZE_DENOTCH 
-END
-
-##-------------------------------------------------------------------
-# TABLE S2R_BLOC_RING_WIDTH :
-##-------------------------------------------------------------------
-
-TABLE S2R_BLOC_RING_WIDTH
-END
-
-##-------------------------------------------------------------------
-# TABLE S2R_MINIMUM_LAYER_WIDTH :
-##-------------------------------------------------------------------
-
-TABLE S2R_MINIMUM_LAYER_WIDTH 
-
-  RDS_NWELL   4
-  RDS_PDIF    2
-  RDS_NTIE    2
-  RDS_PTIE    2
-  RDS_POLY    1
-  RDS_TPOLY   1
-  RDS_CONT    1
-  RDS_ALU1    1
-  RDS_TALU1   1
-  RDS_VIA1    1
-  RDS_ALU2    2
-  RDS_TALU2   2
-  RDS_VIA2    1
-  RDS_ALU3    2
-  RDS_TALU3   2
-  RDS_VIA3    1
-  RDS_ALU4    2
-  RDS_TALU4   2
-  RDS_VIA4    1
-  RDS_ALU5    4
-  RDS_TALU5   4
-  RDS_VIA5    1
-  RDS_ALU6    4
-  RDS_TALU6   4
-
-END
-
-##-------------------------------------------------------------------
-# TABLE CIF_LAYER :
-##-------------------------------------------------------------------
-
-TABLE CIF_LAYER
-
-  RDS_NWELL    LNWELL
-  RDS_NDIF     LNDIF
-  RDS_PDIF     LPDIF
-  RDS_NTIE     LNTIE
-  RDS_PTIE     LPTIE
-  RDS_POLY     LPOLY
-  RDS_TPOLY    LTPOLY
-  RDS_CONT     LCONT
-  RDS_ALU1     LALU1
-  RDS_VALU1    LVALU1
-  RDS_TALU1    LTALU1
-  RDS_VIA1     LVIA
-  RDS_TVIA1    LTVIA1
-  RDS_ALU2     LALU2
-  RDS_TALU2    LTALU2
-  RDS_VIA2     LVIA2
-  RDS_ALU3     LALU3
-  RDS_TALU3    LTALU3
-  RDS_VIA3     LVIA3
-  RDS_ALU4     LALU4
-  RDS_TALU4    LTALU4
-  RDS_VIA4     LVIA4
-  RDS_ALU5     LALU5
-  RDS_TALU5    LTALU5
-  RDS_VIA5     LVIA5
-  RDS_ALU6     LALU6
-  RDS_TALU6    LTALU6
-  RDS_REF      LREF
-
-END
-
-##-------------------------------------------------------------------
-# TABLE GDS_LAYER :
-##-------------------------------------------------------------------
-
-TABLE GDS_LAYER
-
-  RDS_NWELL    1
-  RDS_NDIF     3
-  RDS_PDIF     4
-  RDS_NTIE     5
-  RDS_PTIE     6
-  RDS_POLY     7
-  RDS_TPOLY    9
-  RDS_CONT    10
-  RDS_ALU1    11
-  RDS_VALU1   12
-  RDS_TALU1   13
-  RDS_VIA1    14
-  RDS_TVIA1   15
-  RDS_ALU2    16
-  RDS_TALU2   17
-  RDS_VIA2    18
-  RDS_ALU3    19
-  RDS_TALU3   20
-  RDS_VIA3    21
-  RDS_ALU4    22
-  RDS_TALU4   23
-  RDS_VIA4    25
-  RDS_ALU5    26
-  RDS_TALU5   27
-  RDS_VIA5    28
-  RDS_ALU6    29
-  RDS_TALU6   30
-  RDS_REF     24
-
-END
-
-##-------------------------------------------------------------------
-# TABLE S2R_POST_TREAT :
-##-------------------------------------------------------------------
-
-TABLE S2R_POST_TREAT
-
-END
-DRC_RULES
-
-layer RDS_NWELL 4.;
-layer RDS_NTIE 2.;
-layer RDS_PTIE 2.;
-layer RDS_NDIF 2.;
-layer RDS_PDIF 2.;
-layer RDS_CONT 1.;
-layer RDS_VIA1 1.;
-layer RDS_VIA2 1.;
-layer RDS_VIA3 1.;
-layer RDS_VIA4 1.;
-layer RDS_VIA5 1.;
-layer RDS_POLY 1.;
-layer RDS_ALU1 1.;
-layer RDS_ALU2 2.;
-layer RDS_ALU3 2.;
-layer RDS_ALU4 2.;
-layer RDS_ALU5 2.;
-layer RDS_ALU6 2.;
-layer RDS_USER0 1.;
-layer RDS_USER1 1.;
-layer RDS_USER2 1.;
-
-regles
-
-# Note : ``min'' is different from ``>=''. 
-# min is applied on polygons and >= is applied on rectangles.
-# There is the same difference between max and <=.
-# >= is faster than min, but min must be used where it is
-# required to consider polygons, for example distance of
-# two objects in the same layer 
-#
-# There is no rule to check NTIE and PDIF are included in NWELL
-# since this is necessarily true
-#----------------------------------------------------------- 
-
-# Check the NWELL shapes
-#-----------------------
-caracterise RDS_NWELL (
-  regle 1 : largeur >= 4. ;
-  regle 2 : longueur_inter min 4. ;
-  regle 3 : notch >= 12. ;
-);
-relation RDS_NWELL , RDS_NWELL (
-  regle 4 : distance axiale min 12. ;
-);
-
-# Check RDS_PTIE is really excluded outside NWELL
-#------------------------------------------------
-relation RDS_PTIE , RDS_NWELL (
-  regle 5 : distance axiale >= 7.5;
-  regle 6 : enveloppe longueur_inter < 0. ;
-  regle 7 : marge longueur_inter < 0. ;
-  regle 8 : croix longueur_inter < 0. ;
-  regle 9 : intersection longueur_inter < 0. ;
-  regle 10 : extension longueur_inter < 0. ;
-  regle 11 : inclusion longueur_inter < 0. ;
-);
-
-# Check RDS_NDIF is really excluded outside NWELL
-#------------------------------------------------
-relation RDS_NDIF , RDS_NWELL (
-  regle 12 : distance axiale >= 7.5;
-  regle 13 : enveloppe longueur_inter < 0. ;
-  regle 14 : marge longueur_inter < 0. ;
-  regle 15 : croix longueur_inter < 0. ;
-  regle 16 : intersection longueur_inter < 0. ;
-  regle 17 : extension longueur_inter < 0. ;
-  regle 18 : inclusion longueur_inter < 0. ;
-);
-
-# Check the RDS_PDIF shapes
-#--------------------------
-caracterise RDS_PDIF (
-  regle 19 : largeur >= 2. ;
-  regle 20 : longueur_inter min 2. ;
-  regle 21 : notch >= 2. ;
-);
-relation RDS_PDIF , RDS_PDIF (
-  regle 22 : distance axiale min 3. ;
-);
-
-# Check the RDS_NDIF shapes
-#--------------------------
-caracterise RDS_NDIF (
-  regle 23 : largeur >= 2. ;
-  regle 24 : longueur_inter min 2. ;
-  regle 25 : notch >= 2. ;
-);
-relation RDS_NDIF , RDS_NDIF (
-  regle 26 : distance axiale min 3. ;
-);
-
-# Check the RDS_PTIE shapes
-#--------------------------
-caracterise RDS_PTIE (
-  regle 27 : largeur >= 2. ;
-  regle 28 : longueur_inter min 2. ;
-  regle 29 : notch >= 2. ;
-);
-relation RDS_PTIE , RDS_PTIE (
-  regle 30 : distance axiale min 3. ;
-);
-
-# Check the RDS_NTIE shapes
-#--------------------------
-caracterise RDS_NTIE (
-  regle 31 : largeur >= 2. ;
-  regle 32 : longueur_inter min 2. ;
-  regle 33 : notch >= 2. ;
-);
-relation RDS_NTIE , RDS_NTIE (
-  regle 34 : distance axiale min 3. ;
-);
-
-define RDS_PDIF , RDS_PTIE union -> ANY_P_DIF;
-define RDS_NDIF , RDS_NTIE union -> ANY_N_DIF;
-
-# Check the ANY_N_DIF ANY_P_DIFF exclusion
-#--------------------------------------
-relation ANY_N_DIF , ANY_P_DIF (
-  regle 35 : distance axiale >= 3. ;
-  regle 36 : enveloppe longueur_inter < 0. ;
-  regle 37 : marge longueur_inter < 0. ;
-  regle 38 : croix longueur_inter < 0. ;
-  regle 39 : intersection longueur_inter < 0. ;
-  regle 40 : extension longueur_inter < 0. ;
-  regle 41 : inclusion longueur_inter < 0. ;
-);
-
-# Check RDS_POLY is distant from ANY_DIF
-#---------------------------------------
-relation RDS_POLY , ANY_P_DIF (
-  regle 42 : distance axiale >= 1. ;
-);
-relation RDS_POLY , ANY_N_DIF (
-  regle 43 : distance axiale >= 1. ;
-);
-
-undefine ANY_P_DIF;
-undefine ANY_N_DIF;
-
-define RDS_NDIF , RDS_PDIF union -> NP_DIF;
-define NP_DIF , RDS_POLY intersection -> CHANNEL;
-
-# Check the RDS_POLY shapes
-#--------------------------
-caracterise RDS_POLY (
-  regle 44 : largeur >= 1. ;
-  regle 45 : longueur_inter min 1. ;
-  regle 46 : notch >= 2. ;
-);
-relation RDS_POLY , RDS_POLY (
-  regle 47 : distance axiale min 2.;
-);
-
-# Check the CHANNEL shapes
-#--------------------------
-caracterise CHANNEL (
-  regle 48 : notch >= 2. ;
-);
-relation CHANNEL , CHANNEL (
-  regle 49 : distance axiale min 2.;
-);
-
-
-# Check the RDS_POLY distance
-#----------------------------
-relation RDS_POLY , RDS_POLY (
-  regle 50 : distance axiale min 2.;
-);
-
-undefine CHANNEL;
-
-define NP_DIF , RDS_CONT intersection -> CONT_DIFF;
-relation RDS_POLY , CONT_DIFF (
-  regle 79 : distance axiale >= 2. ;
-);
-
-undefine CONT_DIFF;
-undefine NP_DIF;
-
-
-# Check RDS_ALU1 shapes
-#----------------------
-caracterise RDS_ALU1 (
-  regle 51 : largeur >= 1. ;
-  regle 52 : longueur_inter min 1. ;
-  regle 53 : notch >= 2.5 ;
-);
-relation RDS_ALU1 , RDS_ALU1 (
-  regle 54 : distance axiale min 2.5 ;
-);
-
-# Check RDS_ALU2 shapes
-#----------------------
-caracterise RDS_ALU2 (
-  regle 55 : largeur >= 2. ;
-  regle 56 : longueur_inter min 2. ;
-  regle 57 : notch >= 2. ;
-);
-relation RDS_ALU2 , RDS_ALU2 (
-  regle 58 : distance axiale min 2. ;
-);
-
-# Check RDS_ALU3 shapes
-#----------------------
-caracterise RDS_ALU3 (
-  regle 59 : largeur >= 2. ;
-  regle 60 : longueur_inter min 2. ;
-  regle 61 : notch >= 3. ;
-);
-relation RDS_ALU3 , RDS_ALU3 (
-  regle 62 : distance axiale min 3. ;
-);
-
-# Check RDS_ALU4 shapes
-#----------------------
-caracterise RDS_ALU4 (
-  regle 63 : largeur >= 2. ;
-  regle 64 : longueur_inter min 2. ;
-  regle 65 : notch >= 3. ;
-);
-relation RDS_ALU4 , RDS_ALU4 (
-  regle 66 : distance axiale min 3. ;
-);
-
-# Check RDS_ALU5 shapes
-#----------------------
-caracterise RDS_ALU5 (
-  regle 80 : largeur >= 2. ;
-  regle 81 : longueur_inter min 2. ;
-  regle 82 : notch >= 12. ;
-);
-relation RDS_ALU5 , RDS_ALU5 (
-  regle 83 : distance axiale min 12. ;
-);
-
-# Check RDS_ALU6 shapes
-#----------------------
-caracterise RDS_ALU6 (
-  regle 84 : largeur >= 2. ;
-  regle 85 : longueur_inter min 2. ;
-  regle 86 : notch >= 12. ;
-);
-relation RDS_ALU6 , RDS_ALU6 (
-  regle 87 : distance axiale min 12. ;
-);
-
-# Check ANY_VIA layers, stacking are free
-#----------------------------------------
-relation RDS_CONT , RDS_CONT (
-  regle 67 : distance axiale >= 3. ;
-);
-relation RDS_VIA , RDS_VIA (
-  regle 68 : distance axiale >= 3. ;
-);
-relation RDS_VIA2 , RDS_VIA2 (
-  regle 69 : distance axiale >= 3. ;
-);
-relation RDS_VIA3 , RDS_VIA3 (
-  regle 70 : distance axiale >= 3. ;
-);
-relation RDS_VIA4 , RDS_VIA4 (
-  regle 88 : distance axiale >= 5. ;
-);
-relation RDS_VIA5 , RDS_VIA5 (
-  regle 89 : distance axiale >= 5. ;
-);
-caracterise RDS_CONT (
-  regle 71 : largeur >= 1. ;
-  regle 72 : longueur <= 1. ;
-);
-caracterise RDS_VIA (
-  regle 73 : largeur >= 1. ;
-  regle 74 : longueur <= 1. ;
-);
-caracterise RDS_VIA2 (
-  regle 75 : largeur >= 1. ;
-  regle 76 : longueur <= 1. ;
-);
-caracterise RDS_VIA3 (
-  regle 77 : largeur >= 1. ;
-  regle 78 : longueur <= 1. ;
-);
-caracterise RDS_VIA4 (
-  regle 90 : largeur >= 1. ;
-  regle 91 : longueur <= 1. ;
-);
-caracterise RDS_VIA5 (
-  regle 92 : largeur >= 1. ;
-  regle 93 : longueur <= 1. ;
-);
-
-fin regles
-DRC_COMMENT
-1 (RDS_NWELL) minimum width 4. 
-2 (RDS_NWELL) minimum width 4. 
-3 (RDS_NWELL) Manhatan distance min 12. 
-4 (RDS_NWELL,RDS_NWELL) Manhatan distance min 12. 
-5 (RDS_PTIE,RDS_NWELL) Manhatan distance min 7.5
-6 (RDS_PTIE,RDS_NWELL) must never been in contact
-7 (RDS_PTIE,RDS_NWELL) must never been in contact
-8 (RDS_PTIE,RDS_NWELL) must never been in contact
-9 (RDS_PTIE,RDS_NWELL) must never been in contact
-10 (RDS_PTIE,RDS_NWELL) must never been in contact
-11 (RDS_PTIE,RDS_NWELL) must never been in contact
-12 (RDS_NDIF,RDS_NWELL) Manhatan distance min 7.5
-13 (RDS_NDIF,RDS_NWELL) must never been in contact
-14 (RDS_NDIF,RDS_NWELL) must never been in contact
-15 (RDS_NDIF,RDS_NWELL) must never been in contact
-16 (RDS_NDIF,RDS_NWELL) must never been in contact
-17 (RDS_NDIF,RDS_NWELL) must never been in contact
-18 (RDS_NDIF,RDS_NWELL) must never been in contact
-19 (RDS_PDIF) minimum width 2. 
-20 (RDS_PDIF) minimum width 2. 
-21 (RDS_PDIF) Manhatan distance min 2. 
-22 (RDS_PDIF,RDS_PDIF) Manhatan distance min 3. 
-23 (RDS_NDIF) minimum width 2. 
-24 (RDS_NDIF) minimum width 2. 
-25 (RDS_NDIF) Manhatan distance min 2. 
-26 (RDS_NDIF,RDS_NDIF) Manhatan distance min 3. 
-27 (RDS_PTIE) minimum width 2. 
-28 (RDS_PTIE) minimum width 2. 
-29 (RDS_PTIE) Manhatan distance min 2. 
-30 (RDS_PTIE,RDS_PTIE) Manhatan distance min 3. 
-31 (RDS_NTIE) minimum width 2. 
-32 (RDS_NTIE) minimum width 2. 
-33 (RDS_NTIE) Manhatan distance min 2. 
-34 (RDS_NTIE,RDS_NTIE) Manhatan distance min 3. 
-35 (ANY_N_DIF,ANY_P_DIF) Manhatan distance min 3. 
-36 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-37 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-38 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-39 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-40 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-41 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-42 (RDS_POLY,ANY_N_DIF) Manhatan distance min 1. 
-43 (RDS_POLY,ANY_P_DIF) Manhatan distance min 1. 
-44 (RDS_POLY) minimum width 1. 
-45 (RDS_POLY) minimum width 1. 
-46 (RDS_POLY) Manhatan distance min 2. 
-47 (RDS_POLY,RDS_POLY) Manhatan distance min 2.
-48 (CHANNEL) Manhatan distance min 2. 
-49 (CHANNEL,CHANNEL) Manhatan distance min 2.
-50 (RDS_POLY,RDS_POLY) Manhatan distance min 2.
-51 (RDS_ALU1) minimum width 1. 
-52 (RDS_ALU1) minimum width 1. 
-53 (RDS_ALU1) Manhatan distance min 2.5
-54 (RDS_ALU1,RDS_ALU1) Manhatan distance min 2.5
-55 (RDS_ALU2) minimum width 2. 
-56 (RDS_ALU2) minimum width 2. 
-57 (RDS_ALU2) Manhatan distance min 2. 
-58 (RDS_ALU2,RDS_ALU2) Manhatan distance min 2. 
-59 (RDS_ALU3) minimum width 2. 
-60 (RDS_ALU3) minimum width 2. 
-61 (RDS_ALU3) Manhatan distance min 3. 
-62 (RDS_ALU3,RDS_ALU3) Manhatan distance min 3. 
-63 (RDS_ALU4) minimum width 2. 
-64 (RDS_ALU4) minimum width 2. 
-65 (RDS_ALU4) Manhatan distance min 3. 
-66 (RDS_ALU4,RDS_ALU4) Manhatan distance min 3. 
-67 (RDS_CONT,RDS_CONT) Manhatan distance min 3. 
-68 (RDS_VIA,RDS_VIA) Manhatan distance min 3. 
-69 (RDS_VIA2,RDS_VIA2) Manhatan distance min 3. 
-70 (RDS_VIA3,RDS_VIA3) Manhatan distance min 3. 
-71 (RDS_CONT) minimum width 1. 
-72 (RDS_CONT) maximum length 1. 
-73 (RDS_VIA) minimum width 1. 
-74 (RDS_VIA) maximum length 1. 
-75 (RDS_VIA2) minimum width 1. 
-76 (RDS_VIA2) maximum length 1. 
-77 (RDS_VIA3) minimum width 1. 
-78 (RDS_VIA3) maximum length 1. 
-79 (RDS_POLY,CONT_DIFF) Manhatan distance min 2. 
-80 (RDS_ALU5) minimum width 2. 
-81 (RDS_ALU5) minimum width 2. 
-82 (RDS_ALU5) Manhatan distance min 12. 
-83 (RDS_ALU5,RDS_ALU5) Manhatan distance min 12. 
-84 (RDS_ALU6) minimum width 2. 
-85 (RDS_ALU6) minimum width 2. 
-86 (RDS_ALU6) Manhatan distance min 12. 
-87 (RDS_ALU6,RDS_ALU6) Manhatan distance min 12. 
-88 (RDS_VIA4,RDS_VIA4) Manhatan distance min 5. 
-89 (RDS_VIA5,RDS_VIA5) Manhatan distance min 5. 
-90 (RDS_VIA4) minimum width 1. 
-91 (RDS_VIA4) maximum length 1. 
-92 (RDS_VIA5) minimum width 1. 
-93 (RDS_VIA5) maximum length 1. 
-END_DRC_COMMENT
-END_DRC_RULES
diff --git a/alliance/share/etc/cmos_7.rds.1999.09.30 b/alliance/share/etc/cmos_7.rds.1999.09.30
deleted file mode 100644
index e1b33260..00000000
--- a/alliance/share/etc/cmos_7.rds.1999.09.30
+++ /dev/null
@@ -1,865 +0,0 @@
-# $Id: cmos_7.rds.1999.09.30,v 1.1 1999/10/12 11:22:27 franck Exp $
-#=====================================================================
-#
-#                          ALLIANCE VLSI CAD                  
-#             (R)eal (D)ata (S)tructure parameter file
-#          (c) copyright 1992 Laboratory UPMC/MASI/CAO-VLSI   
-#                         all rights reserved                 
-#                    e-mail : cao-vlsi@masi.ibp.fr            
-#
-#                    file       : cmos_7.rds
-#                    version    : 7
-#                    last modif : July 02, 1995
-#
-#---------------------------------------------------------------------
-# Symbolic to micron on a 'one lambda equals one micron' basis
-#---------------------------------------------------------------------
-#   Refer to the documentation for more precise information.
-#=====================================================================
-
-#---------------------------------------------------------------------
-# PHYSICAL_GRID :
-#---------------------------------------------------------------------
-
-DEFINE  PHYSICAL_GRID  .5
-
-#---------------------------------------------------------------------
-# LAMBDA : 
-#---------------------------------------------------------------------
-
-DEFINE  LAMBDA         1
-
-#---------------------------------------------------------------------
-# TABLE MBK_TO_RDS_SEGMENT :
-#
-# MBK      RDS layer 1                 RDS layer 2         
-# name     name TRANS DLR DWR OFFSET   name TRANS DLR DWR OFFSET  ...
-#---------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_SEGMENT
-
-  NWELL    RDS_NWELL  VW  0.0  0.0  0.0  ALL
-  NDIF     RDS_NDIF   VW  0.5  0.0  0.0  ALL
-  PDIF     RDS_PDIF   VW  0.5  0.0  0.0  ALL \
-           RDS_NWELL  VW  1.0  1.0  0.0  ALL
-  NTIE     RDS_NTIE   VW  0.5  0.0  0.0  ALL
-  PTIE     RDS_PTIE   VW  0.5  0.0  0.0  ALL \
-           RDS_NWELL  VW  1.0  1.0  0.0  ALL
-  NTRANS   RDS_GATE   VW  0.0  0.0  0.0  ALL \
-           RDS_NDIF  LCW -1.5  2.0  0.0  EXT \
-           RDS_NDIF  RCW -1.5  2.0  0.0  EXT \
-           RDS_NDIF   VW -1.5  4.0  0.0  DRC  
-  PTRANS   RDS_GATE   VW  0.0  0.0  0.0  ALL \
-           RDS_PDIF  LCW -1.5  2.0  0.0  EXT \
-           RDS_PDIF  RCW -1.5  2.0  0.0  EXT \
-           RDS_PDIF   VW -1.5  4.0  0.0  DRC \
-		   RDS_NWELL  VW -1.0  5.0  0.0  ALL
-  POLY     RDS_POLY   VW  0.5  0.0  0.0  ALL
-  ALU1     RDS_ALU1   VW  0.5  0.0  0.0  ALL
-  ALU2     RDS_ALU2   VW  1.0  0.0  0.0  ALL
-  ALU3     RDS_ALU3   VW  1.0  0.0  0.0  ALL
-  TPOLY    RDS_TPOLY  VW  0.5  0.0  0.0  ALL
-  TALU1    RDS_TALU1  VW  0.5  0.0  0.0  ALL
-  TALU2    RDS_TALU2  VW  1.0  0.0  0.0  ALL
-  TALU3    RDS_TALU3  VW  1.0  0.0  0.0  ALL
-
-END
-
-#---------------------------------------------------------------------
-# TABLE MBK_TO_RDS_CONNECTOR :
-#
-# MBK      RDS layer 
-# name     name     DER DWR 
-#---------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_CONNECTOR
-
-  POLY    RDS_POLY  .5  0  
-  ALU1    RDS_ALU1  .5  0  
-  ALU2    RDS_ALU2   1  0  
-  ALU3    RDS_ALU3   1  0  
-
-END
-
-#---------------------------------------------------------------------
-# TABLE MBK_TO_RDS_REFERENCE :
-#
-# MBK ref    RDS layer 
-# name       name       width
-#---------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_REFERENCE
-
-  REF_REF    RDS_REF    1
-  REF_CON    RDS_VALU1  2  RDS_TVIA1 1  RDS_TALU2  3
-
-END
-
-#---------------------------------------------------------------------
-# TABLE MBK_TO_RDS_VIA :
-#
-# MBK via      RDS layer 1  RDS  layer 2  RDS  layer 3  RDS layer 4      
-# name         name  width  name   width  name   width  name  width  
-#---------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_VIA
-
-  CONT_BODY_P  RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_PTIE 3 ALL
-  CONT_BODY_N  RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_NTIE 3 ALL RDS_NWELL 4 ALL
-  CONT_DIF_N   RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_NDIF 3 ALL
-  CONT_DIF_P   RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_PDIF 3 ALL RDS_NWELL 4 ALL
-  CONT_POLY    RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_POLY 3 ALL
-  CONT_VIA     RDS_ALU1 2 ALL RDS_VIA1 1 ALL RDS_ALU2 3 ALL
-  CONT_VIA2    RDS_ALU2 3 ALL RDS_VIA2 1 ALL RDS_ALU3 3 ALL
-  C_X_N        RDS_GATE 1 ALL RDS_NDIF 5 ALL
-  C_X_P        RDS_GATE 1 ALL RDS_PDIF 5 ALL RDS_NWELL 6 ALL
-
-END
-
-#---------------------------------------------------------------------
-# TABLE LYNX_GRAPH :
-#
-# RDS layer   Rds layer 1   Rds layer 2    ...
-# name        name          name           ...
-#---------------------------------------------------------------------
- 
-TABLE LYNX_GRAPH
- 
-  RDS_NDIF   RDS_CONT RDS_NDIF
-  RDS_PDIF   RDS_CONT RDS_PDIF
-  RDS_NTIE   RDS_CONT RDS_NTIE
-  RDS_PTIE   RDS_CONT RDS_PTIE
-  RDS_POLY   RDS_CONT RDS_GATE RDS_POLY
-  RDS_GATE   RDS_POLY RDS_GATE
-  RDS_CONT   RDS_PDIF RDS_NDIF RDS_POLY RDS_PTIE RDS_NTIE RDS_ALU1 RDS_CONT
-  RDS_ALU1   RDS_CONT RDS_VIA1 RDS_ALU1 RDS_VALU1
-  RDS_VALU1  RDS_CONT RDS_VIA1 RDS_ALU1 RDS_VALU1
-  RDS_VIA1   RDS_ALU1 RDS_ALU2 RDS_VIA1
-  RDS_ALU2   RDS_VIA1 RDS_VIA2 RDS_ALU2
-  RDS_VIA2   RDS_ALU2 RDS_ALU3 RDS_VIA2
-  RDS_ALU3   RDS_VIA2 RDS_ALU3
-
-END
-
-#---------------------------------------------------------------------
-# TABLE LYNX_CAPA : 
-#
-# RDS layer   Surface capacitance  Perimetric capacitance
-# name        piF / Micron^2       piF / Micron 
-#---------------------------------------------------------------------
- 
-
-TABLE LYNX_CAPA
-
-  RDS_POLY    1.00e-04    1.00e-04
-  RDS_ALU1    0.50e-04    0.90e-04
-  RDS_ALU2    0.25e-04    0.95e-04
-  RDS_ALU3    0.25e-04    0.95e-04
-  
-END
-
-#---------------------------------------------------------------------
-# TABLE LYNX_RESISTOR :
-#
-# RDS layer   Surface resistor
-# name        Ohm / Micron^2 
-#---------------------------------------------------------------------
-
-TABLE LYNX_RESISTOR
-
-  RDS_POLY    50.0
-  RDS_ALU1     0.1
-  RDS_ALU2     0.05
-  RDS_ALU2     0.05
- 
-END
-
-#---------------------------------------------------------------------
-# TABLE LYNX_TRANSISTOR : 
-#
-# MBK layer  Transistor Type  MBK via
-# name       name             name
-#---------------------------------------------------------------------
- 
-TABLE LYNX_TRANSISTOR
-
-  NTRANS  NTRANS  C_X_N   RDS_GATE   RDS_NDIF  RDS_NDIF
-  PTRANS  PTRANS  C_X_P   RDS_GATE   RDS_PDIF  RDS_PDIF
-
-END
-
-#---------------------------------------------------------------------
-# TABLE LYNX_DIFFUSION :
-#
-# RDS layer  RDS layer
-# name       name    
-#---------------------------------------------------------------------
-
-TABLE LYNX_DIFFUSION
-END
-
-#---------------------------------------------------------------------
-# TABLE CIF_LAYER :
-#---------------------------------------------------------------------
-
-TABLE CIF_LAYER
-
-  RDS_NWELL    LNWELL
-  RDS_NDIF     LNDIF
-  RDS_PDIF     LPDIF
-  RDS_NTIE     LNTIE
-  RDS_PTIE     LPTIE
-  RDS_POLY     LPOLY
-  RDS_GATE     LGATE
-  RDS_TPOLY    LTPOLY
-  RDS_CONT     LCONT
-  RDS_ALU1     LALU1
-  RDS_VALU1    LVALU1
-  RDS_TALU1    LTALU1
-  RDS_VIA1     LVIA1
-  RDS_TVIA1    LTVIA1
-  RDS_ALU2     LALU2
-  RDS_TALU2    LTALU2
-  RDS_VIA2     LVIA2
-  RDS_ALU3     LALU3
-  RDS_TALU3    LTALU3
-  RDS_REF      LREF
-
-END
- 
-#---------------------------------------------------------------------
-# TABLE GDS_LAYER :
-#---------------------------------------------------------------------
-
-TABLE GDS_LAYER
-
-  RDS_NWELL    1
-  RDS_NDIF     3
-  RDS_PDIF     4
-  RDS_NTIE     5
-  RDS_PTIE     6
-  RDS_POLY     7
-  RDS_GATE     8
-  RDS_TPOLY    9
-  RDS_CONT    10
-  RDS_ALU1    11
-  RDS_VALU1   12
-  RDS_TALU1   13
-  RDS_VIA1    14
-  RDS_TVIA1   15
-  RDS_ALU2    16
-  RDS_TALU2   17
-  RDS_VIA2    18
-  RDS_ALU3    19
-  RDS_TALU3   20
-  RDS_REF     21
-
-END
-
-#---------------------------------------------------------------------
-# TABLE S2R_OVERSIZE_DENOTCH :
-#---------------------------------------------------------------------
-
-TABLE S2R_OVERSIZE_DENOTCH 
-
-END
-
-#---------------------------------------------------------------------
-# TABLE S2R_BLOC_RING_WIDTH :
-#---------------------------------------------------------------------
-
-TABLE S2R_BLOC_RING_WIDTH
-
-END
-
-#---------------------------------------------------------------------
-# TABLE S2R_MINIMUM_LAYER_WIDTH :
-#---------------------------------------------------------------------
-
-TABLE S2R_MINIMUM_LAYER_WIDTH 
-
-  RDS_NWELL   4
-  RDS_PDIF    2
-  RDS_NTIE    2
-  RDS_PTIE    2
-  RDS_POLY    1
-  RDS_GATE    1
-  RDS_TPOLY   1
-  RDS_CONT    1
-  RDS_ALU1    1
-  RDS_TALU1   1
-  RDS_VIA1    1
-  RDS_ALU2    2
-  RDS_TALU2   2
-  RDS_VIA2    1
-  RDS_ALU3    3
-  RDS_TALU3   3
-
-END
-
-#---------------------------------------------------------------------
-# TABLE S2R_POST_TREAT :
-#---------------------------------------------------------------------
-
-TABLE S2R_POST_TREAT
-
-END
-DRC_RULES
-
-layer RDS_NWELL 4.;
-layer RDS_NTIE  2.;
-layer RDS_PTIE  2.;
-layer RDS_NDIF  2.;
-layer RDS_PDIF  2.;
-layer RDS_VIA   1.;
-layer RDS_GATE  1.;
-layer RDS_POLY  1.;
-layer RDS_ALU1  1.;
-layer RDS_ALU2  2.;
-layer RDS_ALU3  3.;
-layer RDS_CONT  1.;
-
-regles
-
-caracterise RDS_NWELL(
-   regle 100: largeur  >= 4. ;
-   regle 101: longueur_inter  min 4. ;
-   regle 102: notch    >= 4. ;
-);
-
-relation RDS_NWELL , RDS_NTIE (
-  regle  103 : enveloppe    largeur_min     min    0.5;
-  regle  104 : marge        longueur_inter  max    0. ;
-  regle  105 : croix        longueur_inter  max    0. ;
-  regle  106 : intersection longueur_inter  max    0. ;
-  regle  107 : extension    longueur_inter  max    0. ;
-  regle  108 : inclusion    longueur_inter  max    0. ;
-);
-
-define RDS_NTIE , RDS_NWELL exclusion -> NWEL_NTIE; 
-
-caracterise NWEL_NTIE (
-   regle  109 : longueur     <    0. ;
-);
-
-undefine NWEL_NTIE;
-
-relation RDS_NWELL , RDS_PDIF (
-   regle  110 : enveloppe    largeur_min     min    0.5;
-   regle  111 : marge        longueur_inter  max    0. ;
-   regle  112 : croix        longueur_inter  max    0. ;
-   regle  113 : intersection longueur_inter  max    0. ;
-   regle  114 : extension    longueur_inter  max    0. ;
-   regle  115 : inclusion    longueur_inter  max    0. ;
-);
-
-define RDS_PDIF , RDS_NWELL exclusion -> NWEL_PDIF;
-
-caracterise NWEL_PDIF (
-   regle  117 : longueur     <    0. ;
-);
-
-undefine NWEL_PDIF;
-
-
-relation RDS_NWELL , RDS_NWELL (
-   regle  118 : distance     axiale         min  12. ;
-);
- 
-caracterise RDS_NTIE (
-   regle 119: largeur  >= 2. ;
-   regle 120: notch    >= 2. ;
-);
-
-relation RDS_NTIE , RDS_NTIE (
-   regle  121 : distance     axiale         min   3. ;
-);
-
-caracterise RDS_PTIE (
-   regle 122: largeur  >= 2. ;
-   regle 123: longueur_inter  min 2. ;
-   regle 124: notch    >= 2. ;
-);
-
-relation RDS_PTIE , RDS_NWELL (
-   regle  125 : distance     axiale         >=   7.5;
-   regle  126 : enveloppe    longueur_inter  <    0. ;
-   regle  127 : marge        longueur_inter  <    0. ;
-   regle  128 : croix        longueur_inter  <    0. ;
-   regle  129 : intersection longueur_inter  <    0. ;
-   regle  130 : extension    longueur_inter  <    0. ;
-   regle  131 : inclusion    longueur_inter  <    0. ;
-);
-
-relation RDS_PTIE , RDS_NTIE (
-   regle  132 : distance     axiale         >=   8. ;
-   regle  133 : enveloppe    longueur_inter  <    0. ;
-   regle  134 : marge        longueur_inter  <    0. ;
-   regle  135 : croix        longueur_inter  <    0. ;
-   regle  136 : intersection longueur_inter  <    0. ;
-   regle  137 : extension    longueur_inter  <    0. ;
-   regle  138 : inclusion    longueur_inter  <    0. ;
-);
-
-relation RDS_PTIE , RDS_PTIE (
-   regle  139 : distance     axiale         >=   3. ;
-);
-
-caracterise RDS_NDIF (
-   regle 140: largeur  >= 2. ;
-   regle 141: longueur_inter  min 2. ;
-   regle 142: notch    >= 3. ;
-);
-
-relation RDS_NDIF , RDS_NWELL (
-   regle  143 : distance     axiale         >=   7.5;
-   regle  144 : enveloppe    longueur_inter  <    0. ;
-   regle  145 : marge        longueur_inter  <    0. ;
-   regle  146 : croix        longueur_inter  <    0. ;
-   regle  147 : intersection longueur_inter  <    0. ;
-   regle  148 : extension    longueur_inter  <    0. ;
-   regle  149 : inclusion    longueur_inter  <    0. ;
-);
-
-relation RDS_NDIF , RDS_NTIE (
-   regle  150 : distance     axiale         >=   8. ;
-   regle  151 : enveloppe    longueur_inter  <    0. ;
-   regle  152 : marge        longueur_inter  <    0. ;
-   regle  153 : croix        longueur_inter  <    0. ;
-   regle  154 : intersection longueur_inter  <    0. ;
-   regle  155 : extension    longueur_inter  <    0. ;
-   regle  156 : inclusion    longueur_inter  <    0. ;
-);
-
-relation RDS_NDIF , RDS_PTIE (
-   regle  157 : distance     axiale         >=   3. ;
-   regle  158 : enveloppe    longueur_inter  <    0. ;
-   regle  159 : marge        longueur_inter  <    0. ;
-   regle  160 : croix        longueur_inter  <    0. ;
-   regle  161 : intersection longueur_inter  <    0. ;
-   regle  162 : extension    longueur_inter  <    0. ;
-   regle  163 : inclusion    longueur_inter  <    0. ;
-);
-
-relation RDS_NDIF , RDS_NDIF (
-   regle  164 : distance     axiale         min   3. ;
-);
-
-caracterise RDS_PDIF (
-   regle 165: largeur  >= 2. ;
-   regle 166: longueur_inter  min 2. ;
-   regle 167: notch    >= 2. ;
-);
-
-relation RDS_PDIF , RDS_NTIE (
-   regle  168 : distance     axiale         >=   3. ;
-   regle  169 : enveloppe    longueur_inter  <    0. ;
-   regle  170 : marge        longueur_inter  <    0. ;
-   regle  171 : croix        longueur_inter  <    0. ;
-   regle  172 : intersection longueur_inter  <    0. ;
-   regle  173 : extension    longueur_inter  <    0. ;
-   regle  174 : inclusion    longueur_inter  <    0. ;
-);
-
-relation RDS_PDIF , RDS_PTIE (
-   regle  175 : distance     axiale         >=   8. ;
-   regle  176 : enveloppe    longueur_inter  <    0. ;
-   regle  177 : marge        longueur_inter  <    0. ;
-   regle  178 : croix        longueur_inter  <    0. ;
-   regle  179 : intersection longueur_inter  <    0. ;
-   regle  180 : extension    longueur_inter  <    0. ;
-   regle  181 : inclusion    longueur_inter  <    0. ;
-);
-
-relation RDS_PDIF , RDS_NDIF (
-   regle  182 : distance     axiale         >=   8. ;
-   regle  183 : enveloppe    longueur_inter  <    0. ;
-   regle  184 : marge        longueur_inter  <    0. ;
-   regle  185 : croix        longueur_inter  <    0. ;
-   regle  186 : intersection longueur_inter  <    0. ;
-   regle  187 : extension    longueur_inter  <    0. ;
-   regle  188 : inclusion    longueur_inter  <    0. ;
-);
-
-relation RDS_PDIF , RDS_PDIF (
-   regle  189 : distance     axiale         min   3. ;
-);
-
-
-relation RDS_GATE , RDS_NTIE (
-   regle  190 : distance     axiale         >=   1. ;
-   regle  191 : enveloppe    longueur_inter  <    0. ;
-   regle  192 : marge        longueur_inter  <    0. ;
-   regle  193 : croix        longueur_inter  <    0. ;
-   regle  194 : intersection longueur_inter  <    0. ;
-   regle  195 : extension    longueur_inter  <    0. ;
-   regle  196 : inclusion    longueur_inter  <    0. ;
-);
-
-relation RDS_GATE , RDS_PTIE (
-   regle  197 : distance     axiale         >=   1. ;
-   regle  198 : enveloppe    longueur_inter  <    0. ;
-   regle  199 : marge        longueur_inter  <    0. ;
-   regle  200 : croix        longueur_inter  <    0. ;
-   regle  201 : intersection longueur_inter  <    0. ;
-   regle  202 : extension    longueur_inter  <    0. ;
-   regle  203 : inclusion    longueur_inter  <    0. ;
-);
-
-relation RDS_GATE , RDS_NDIF (
-   regle  204 : distance     axiale         min   1. ;
-);
-
-relation RDS_GATE , RDS_PDIF (
-   regle  205 : distance     axiale         min   1. ;
-);
-
-relation RDS_POLY , RDS_NTIE (
-   regle  206 : distance     axiale         >=   1. ;
-   regle  207 : enveloppe    longueur_inter  <    0. ;
-   regle  208 : marge        longueur_inter  <    0. ;
-   regle  209 : croix        longueur_inter  <    0. ;
-   regle  210 : intersection longueur_inter  <    0. ;
-   regle  211 : extension    longueur_inter  <    0. ;
-   regle  212 : inclusion    longueur_inter  <    0. ;
-);
-
-relation RDS_POLY , RDS_PTIE (
-   regle  213 : distance     axiale         >=   1. ;
-   regle  214 : enveloppe    longueur_inter  <    0. ;
-   regle  215 : marge        longueur_inter  <    0. ;
-   regle  216 : croix        longueur_inter  <    0. ;
-   regle  217 : intersection longueur_inter  <    0. ;
-   regle  218 : extension    longueur_inter  <    0. ;
-   regle  219 : inclusion    longueur_inter  <    0. ;
-);
-
-relation RDS_POLY , RDS_NDIF (
-   regle  220 : distance     axiale         >=   1. ;
-   regle  221 : enveloppe    longueur_inter  <    0. ;
-   regle  222 : marge        longueur_inter  <    0. ;
-   regle  223 : croix        longueur_inter  <    0. ;
-   regle  224 : intersection longueur_inter  <    0. ;
-   regle  225 : extension    longueur_inter  <    0. ;
-   regle  226 : inclusion    longueur_inter  <    0. ;
-);
-
-relation RDS_POLY , RDS_PDIF (
-   regle  227 : distance     axiale         >=   1. ;
-   regle  228 : enveloppe    longueur_inter  <    0. ;
-   regle  229 : marge        longueur_inter  <    0. ;
-   regle  230 : croix        longueur_inter  <    0. ;
-   regle  231 : intersection longueur_inter  <    0. ;
-   regle  232 : extension    longueur_inter  <    0. ;
-   regle  233 : inclusion    longueur_inter  <    0. ;
-);
-
-caracterise RDS_POLY (
-   regle 234: largeur  >= 1. ;
-   regle 235: longueur_inter  min 1. ;
-#   regle 236: notch    >= 1. ;
-#   Modif Patrick le 11/03/94 
-   regle 236: notch    >= 2. ;
-);
-
-define RDS_POLY , RDS_GATE union -> POLY_GATE;
-
-relation POLY_GATE , POLY_GATE (
-   regle 237 : distance      axiale         min   2. ;
-);
-
-relation POLY_GATE , RDS_CONT (
-   regle 248 : distance      axiale         min   1.5;
-);
-#pour renumeroter il faut aussi modifier le fichier des commentaires et le man
- 
-undefine POLY_GATE;
-
-caracterise RDS_ALU1 (
-   regle 238: largeur  >= 1. ;
-   regle 239: longueur_inter  min 1. ;
-   regle 240: notch    >= 2.5 ;
-);
-
-relation RDS_ALU1 , RDS_ALU1 (
-   regle  241 : distance     axiale         min   2.5;
-);
-
-caracterise RDS_ALU2 (
-   regle 242: largeur  >= 2. ;
-   regle 243: longueur_inter  min 2. ;
-   regle 244: notch    >= 2. ;
-);
-
-relation RDS_ALU2 , RDS_ALU2 (
-   regle  245 : distance     axiale         min   2. ;
-);
-
-caracterise RDS_CONT (
-   regle 246 : largeur  >= 1. ;
-   regle 247 : longueur <= 1. ;
-);
-
-relation RDS_CONT , RDS_GATE (
-  
-   regle  249 : enveloppe    longueur_inter  <    0. ;
-   regle  250 : marge        longueur_inter  <    0. ;
-   regle  251 : croix        longueur_inter  <    0. ;
-   regle  252 : intersection longueur_inter  <    0. ;
-   regle  253 : extension    longueur_inter  <    0. ;
-   regle  254 : inclusion    longueur_inter  <    0. ;
-);
-
-relation RDS_CONT , RDS_CONT (
-   regle  255 : distance     axiale          >=  3. ;
-);
-
-caracterise RDS_VIA (
-   regle 261 : largeur  >= 1. ;
-   regle 262 : longueur <= 1. ;
-);
-
-#relation RDS_VIA , RDS_GATE (
-#   regle  263 : distance     axiale          >=  2. ;
-#   regle  264 : enveloppe    longueur_inter  <    0. ;
-#   regle  265 : marge        longueur_inter  <    0. ;
-#   regle  266 : croix        longueur_inter  <    0. ;
-#   regle  267 : intersection longueur_inter  <    0. ;
-#   regle  268 : extension    longueur_inter  <    0. ;
-#   regle  269 : inclusion    longueur_inter  <    0. ;
-#);
-
-#relation RDS_VIA , RDS_POLY (
-#   regle  270 : distance     axiale          >=  1. ; # SPECIAL MS2D /MS2U
-#   regle  271 : enveloppe    longueur_inter  >   1. ; # SPECIAL MS2D /MS2U
-#   regle  272 : marge        longueur_inter  <    0. ;
-#   regle  273 : croix        longueur_inter  <    0. ;
-#   regle  274 : intersection longueur_inter  <    0. ;
-#   regle  275 : extension    longueur_inter  <    0. ;
-#   regle  276 : inclusion    longueur_inter  <    0. ;
-#);
-
-relation RDS_VIA , RDS_CONT (
-   regle  277 : distance     axiale          >=  2. ;
-   regle  278 : enveloppe    longueur_inter  <    0. ;
-   regle  279 : marge        longueur_inter  <    0. ;
-   regle  280 : croix        longueur_inter  <    0. ;
-   regle  281 : intersection longueur_inter  <    0. ;
-   regle  282 : extension    longueur_inter  <    0. ;
-   regle  283 : inclusion    longueur_inter  <    0. ;
-);
-
-relation RDS_VIA , RDS_VIA (
-   regle  284 : distance     axiale          >=  3. ;
-);
-
-caracterise RDS_ALU3 (
-   regle 285: largeur  >= 3. ;
-   regle 286: longueur_inter  min 3. ;
-   regle 287: notch    >= 2. ;
-);
-
-relation RDS_ALU3 , RDS_ALU3 (
-   regle  288 : distance     axiale         min   2. ;
-);
-
-relation RDS_VIA2 , RDS_VIA2 (
-   regle  289 : distance     axiale          >=   3. ;
-);
-
-caracterise RDS_VIA2 (
-   regle 290 : largeur  >= 1. ;
-   regle 291 : longueur <= 1. ;
-);
-
-fin regles
-
-END_DRC_RULES
-DRC_COMMENT
-100 the minimum width for a segment of NWELL is 4
-101 the minimum width for a segment of NWELL is 4
-102 the minimum notch for a segment of NWELL is 4
-103 the minimun NWELL width around NTIE is 0.5
-104 the NTIE must not exceed the boundaries of NWELL
-105 the NTIE must not exceed the boundaries of NWELL
-106 the NTIE must not exceed the boundaries of NWELL
-107 the NTIE must not exceed the boundaries of NWELL
-108 the inclusion of NWELL in NTIE is forbiden
-109 contact between NTIE and NWELL is forbidden.
-110 the minimun NWELL width around PDIFF is 0.5
-111 the PDIFF must not exceed the boundaries of NWELL
-112 the PDIFF must not exceed the boundaries of NWELL
-113 the PDIFF must not exceed the boundaries of NWELL
-114 the PDIFF must not exceed the boundaries of NWELL
-115 the inclusion of NWELL in PDIFF is forbiden
-117 contact between PDIF and NWELL is forbidden.
-118 the minimum distance between NWELL and NWELL is 12
-119 the minimum width for a segment of NTIE is 2
-120 the minimum notch for a segment of NTIE is 2
-121 the minimum distance between NTIE and NTIE is 3
-122 the minimum width for a segment of PTIE is 2
-123 the minimum width for a segment of PTIE is 2
-124 the minimum notch for a segment of PTIE is 2
-125 the minimum distance between PTIE and NWELL is 7.5
-126 contact between PTIE and NWELL is forbidden.
-127 contact between PTIE and NWELL is forbidden.
-128 contact between PTIE and NWELL is forbidden.
-129 contact between PTIE and NWELL is forbidden.
-130 contact between PTIE and NWELL is forbidden.
-131 contact between PTIE and NWELL is forbidden.
-132 the minimum distance between PTIE and NTIE is 8
-133 contact between PTIE and NTIE is forbidden.
-134 contact between PTIE and NTIE is forbidden.
-135 contact between PTIE and NTIE is forbidden.
-136 contact between PTIE and NTIE is forbidden.
-137 contact between PTIE and NTIE is forbidden.
-138 contact between PTIE and NTIE is forbidden.
-139 the minimum distance between PTIE and PTIE is 3
-140 the minimum width for a segment of NDIF is 2
-141 the minimum width for a segment of NDIF is 2
-142 the minimum notch for a segment of NDIF is 2
-143 the minimum distance between NDIF and NWELL is 7.5
-144 contact between NDIF and NWELL is forbidden.
-145 contact between NDIF and NWELL is forbidden.
-146 contact between NDIF and NWELL is forbidden.
-147 contact between NDIF and NWELL is forbidden.
-148 contact between NDIF and NWELL is forbidden.
-149 contact between NDIF and NWELL is forbidden.
-150 the minimum distance between NDIF and NTIE is 8
-151 contact between NDIF and NTIE is forbidden.
-152 contact between NDIF and NTIE is forbidden.
-153 contact between NDIF and NTIE is forbidden.
-154 contact between NDIF and NTIE is forbidden.
-155 contact between NDIF and NTIE is forbidden.
-156 contact between NDIF and NTIE is forbidden.
-157 the minimum distance between NDIF and PTIE is 3
-158 contact between NDIF and PTIE is forbidden.
-159 contact between NDIF and PTIE is forbidden.
-160 contact between NDIF and PTIE is forbidden.
-161 contact between NDIF and PTIE is forbidden.
-162 contact between NDIF and PTIE is forbidden.
-163 contact between NDIF and PTIE is forbidden.
-164 contact between NDIF and NDIF is forbidden.
-165 the minimum width for a segment of PDIF is 2
-166 the minimum width for a segment of PDIF is 2
-167 the minimum notch for a segment of PDIF is 2
-168 the minimum distance between PDIF and NTIE is 3
-169 contact between PDIF and NTIE is forbidden.
-170 contact between PDIF and NTIE is forbidden.
-171 contact between PDIF and NTIE is forbidden.
-172 contact between PDIF and NTIE is forbidden.
-173 contact between PDIF and NTIE is forbidden.
-174 contact between PDIF and NTIE is forbidden.
-175 the minimum distance between PDIF and PTIE is 8
-176 contact between PDIF and PTIE is forbidden.
-177 contact between PDIF and PTIE is forbidden.
-178 contact between PDIF and PTIE is forbidden.
-179 contact between PDIF and PTIE is forbidden.
-180 contact between PDIF and PTIE is forbidden.
-181 contact between PDIF and PTIE is forbidden.
-182 the minimum distance between PDIF and NDIF is 8
-183 contact between PDIF and NDIF is forbidden.
-184 contact between PDIF and NDIF is forbidden.
-185 contact between PDIF and NDIF is forbidden.
-186 contact between PDIF and NDIF is forbidden.
-187 contact between PDIF and NDIF is forbidden.
-188 contact between PDIF and NDIF is forbidden.
-189 the minimum distance between PDIF and PDIF is 3
-190 the minimum distance between GATE and NTIE is 1
-191 contact between GATE and NTIE is forbidden.
-192 contact between GATE and NTIE is forbidden.
-193 contact between GATE and NTIE is forbidden.
-194 contact between GATE and NTIE is forbidden.
-195 contact between GATE and NTIE is forbidden.
-196 contact between GATE and NTIE is forbidden.
-197 the minimum distance between GATE and PTIE is 1
-198 contact between GATE and PTIE is forbidden.
-199 contact between GATE and PTIE is forbidden.
-200 contact between GATE and PTIE is forbidden.
-201 contact between GATE and PTIE is forbidden.
-202 contact between GATE and PTIE is forbidden.
-203 contact between GATE and PTIE is forbidden.
-204 the minimum distance between GATE and NDIF is 1
-205 the minimum distance between GATE and PDIF is 1
-206 the minimum distance between POLY and NTIE is 1
-207 contact between POLY and NTIE is forbidden.
-208 contact between POLY and NTIE is forbidden.
-209 contact between POLY and NTIE is forbidden.
-210 contact between POLY and NTIE is forbidden.
-211 contact between POLY and NTIE is forbidden.
-212 contact between POLY and NTIE is forbidden.
-213 the minimum distance between POLY and PTIE is 1
-214 contact between POLY and PTIE is forbidden.
-215 contact between POLY and PTIE is forbidden.
-216 contact between POLY and PTIE is forbidden.
-217 contact between POLY and PTIE is forbidden.
-218 contact between POLY and PTIE is forbidden.
-219 contact between POLY and PTIE is forbidden.
-220 the minimum distance between POLY and NDIF is 1
-221 contact between POLY and NDIF is forbidden.
-222 contact between POLY and NDIF is forbidden.
-223 contact between POLY and NDIF is forbidden.
-224 contact between POLY and NDIF is forbidden.
-225 contact between POLY and NDIF is forbidden.
-226 contact between POLY and NDIF is forbidden.
-227 the minimum distance between POLY and PDIF is 1
-228 contact between POLY and PDIF is forbidden.
-229 contact between POLY and PDIF is forbidden.
-230 contact between POLY and PDIF is forbidden.
-231 contact between POLY and PDIF is forbidden.
-232 contact between POLY and PDIF is forbidden.
-233 contact between POLY and PDIF is forbidden.
-234 the minimum width for a segment of POLY is 1
-235 the minimum width for a segment of POLY is 1
-236 the minimum notch for a segment of POLY is 2
-237 the minimum distance between GATE and GATE or POLY and GATE or POLY and POLY is 2
-238 the minimum width for a segment of ALU1 is 1 
-239 the minimum width for a segment of ALU1 is 1 
-240 the minimum notch for a segment of ALU1 is 2.5 
-241 the minimum distance between ALU1 and ALU1 is 2.5
-242 the minimum width for a segment of ALU2 is 2
-243 the minimum width for a segment of ALU2 is 2
-244 the minimum notch for a segment of ALU2 is 2
-245 the minimum distance between ALU2 and ALU2 is 2
-246 the width of a CONT must be equal to 1
-247 the width of a CONT must be equal to 1
-248 the minimum distance between CONT and GATE or POLY 1.5
-249 contact between CONT and GATE is forbidden.
-250 contact between CONT and GATE is forbidden.
-251 contact between CONT and GATE is forbidden.
-252 contact between CONT and GATE is forbidden.
-253 contact between CONT and GATE is forbidden.
-254 contact between CONT and GATE is forbidden.
-255 the minimum distance between CONT and CONT is 3
-261 the width of a VIA must be equal to 1
-262 the width of a VIA must be equal to 1
-263 the minimum distance between VIA and GATE is 2
-264 contact between VIA and GATE is forbidden.
-265 contact between VIA and GATE is forbidden.
-266 contact between VIA and GATE is forbidden.
-267 contact between VIA and GATE is forbidden.
-268 contact between VIA and GATE is forbidden.
-269 contact between VIA and GATE is forbidden.
-270 the minimum distance between VIA and POLY is 2
-271 contact between VIA and POLY is forbidden.
-272 contact between VIA and POLY is forbidden.
-273 contact between VIA and POLY is forbidden.
-274 contact between VIA and POLY is forbidden.
-275 contact between VIA and POLY is forbidden.
-276 contact between VIA and POLY is forbidden.
-277 the minimum distance between VIA and CONT is 2
-278 contact between VIA and CONT is forbidden.
-279 contact between VIA and CONT is forbidden.
-280 contact between VIA and CONT is forbidden.
-281 contact between VIA and CONT is forbidden.
-282 contact between VIA and CONT is forbidden.
-283 contact between VIA and CONT is forbidden.
-284 the minimum distance between VIA and VIA is 3
-285 the minimum width for a segment of ALU3 is 3
-286 the minimum width for a segment of ALU3 is 3
-287 the minimum notch for a segment of ALU3 is 2
-288 the minimum distance between ALU3 and ALU3 is 2
-289 the minimum distance between VIA2 and VIA2 is 3
-290 the width of a VIA2 must be equal to 1
-291 the width of a VIA2 must be equal to 1
-END_DRC_COMMENT
diff --git a/alliance/share/etc/cmos_8.graal b/alliance/share/etc/cmos_8.graal
deleted file mode 100644
index f1fa2c97..00000000
--- a/alliance/share/etc/cmos_8.graal
+++ /dev/null
@@ -1,305 +0,0 @@
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Title      :      Parameters File for Graal                 |
-# |                                                             |
-# | Technology :              Cmos V7                           |
-# |                                                             |
-# | Date       :             27/06/95                           |
-# |                                                             |
-# \------------------------------------------------------------*/
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                 Graal Peek Bound in lambda                  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_PEEK_BOUND 7
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |               Lower Grid Step in pixel by lambda            |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_LOWER_GRID_STEP 10
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |          Lower Figure Text Step in pixel by lambda          |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_LOWER_FIGURE_STEP 1
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |         Lower Instance Text Step in pixel by lambda         |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_LOWER_INSTANCE_STEP 1
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |        Lower Connector Text Step in pixel by lambda         |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_LOWER_CONNECTOR_STEP 5
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |          Lower Segment Text Step in pixel by lambda         |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_LOWER_SEGMENT_STEP 7
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |         Lower Reference Text Step in pixel by lambda        |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_LOWER_REFERENCE_STEP 10
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                 Graal Cursor Color Name                     |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_CURSOR_COLOR_NAME  Gray
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                 Graal Cursor Size in pixel                  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_CURSOR_SIZE 10 
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |  Segment Panel Button Label, Foreground , Background Color  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_SEGMENT_NAME
-
-  NWELL    Nwell  tan              Black
-  PWELL    Pwell  light_yellow     Black
-  NDIF     Ndif   lawn_green       Black
-  PDIF     Pdif   yellow           Black
-  NTIE     Ntie   spring_green     Black
-  PTIE     Ptie   light_goldenrod  Black
-  POLY     Poly   red              Black
-  ALU1     Alu1   royal_blue       Black
-  ALU2     Alu2   Cyan             Black
-  ALU3     Alu3   light_pink       Black
-  ALU4     Alu4   green            Black
-  ALU5     Alu5   yellow           Black
-  ALU6     Alu6   violet           Black
-  TPOLY    Tpoly  hot_pink         Black
-  TALU1    Talu1  royal_blue       Black
-  TALU2    Talu2  turquoise        Black
-  TALU3    Talu3  light_pink       Black
-  TALU4    Talu4  green            Black
-  TALU5    Talu5  yellow           Black
-  TALU6    Talu6  violet           Black
-  CALU1    CAlu1  royal_blue       Black
-  CALU2    CAlu2  Cyan             Black
-  CALU3    CAlu3  light_pink       Black
-  CALU4    CAlu4  green            Black
-  CALU5    CAlu5  yellow           Black
-  CALU6    CAlu6  violet           Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Transistor Panel Button Label, Foreground, Background Color |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_TRANSISTOR_NAME
-
-  NTRANS   Ntrans lawn_green       Black
-  PTRANS   Ptrans yellow           Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Connector Panel Button Label, Foreground , Background Color |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_CONNECTOR_NAME
-
-  POLY     Poly   red              Black
-  ALU1     Alu1   royal_blue       Black
-  ALU2     Alu2   Cyan             Black
-  ALU3     Alu3   light_pink       Black
-  ALU4     Alu4   green            Black
-  ALU5     Alu5   yellow           Black
-  ALU6     Alu6   violet           Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |       Minimun Length and Width for a symbolic Segment       |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_SEGMENT_VALUE
-
-  NWELL    4   4
-  PWELL    4   4
-  NDIF     2   2
-  PDIF     2   2
-  NTIE     2   2
-  PTIE     2   2
-  NTRANS   1   4
-  PTRANS   1   4
-  POLY     1   1
-  ALU1     1   1
-  ALU2     2   2
-  ALU3     2   2
-  ALU4     2   2
-  ALU5     4   4
-  ALU6     4   4
-  TPOLY    1   1
-  TALU1    1   1
-  TALU2    2   2
-  TALU3    2   2
-  TALU4    2   2
-  TALU5    2   2
-  TALU6    2   2
-  CALU1    1   1
-  CALU2    2   2
-  CALU3    2   2
-  CALU4    2   2
-  CALU5    4   4
-  CALU6    4   4
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Reference Panel Button Label, Foreground, Background Color  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_REFERENCE_NAME
-
-  REF_REF  Ref_Ref red  Black
-  REF_CON  Ref_Con Cyan Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |     Via Panel Button Label, Foreground , Background Color   |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_VIA_NAME
-
-  CONT_DIF_N   Cont_NDif   lawn_green       Black
-  CONT_DIF_P   Cont_PDif   yellow           Black
-  CONT_BODY_N  Cont_NTie   spring_green     Black
-  CONT_BODY_P  Cont_PTie   light_goldenrod  Black
-  CONT_POLY    Cont_Poly   red              Black
-  CONT_VIA     Via_1-2     cyan             Black
-  CONT_VIA2    Via_2-3     light_pink       Black
-  CONT_VIA3    Via_3-4     green            Black
-  CONT_VIA4    Via_4-5     yellow           Black
-  CONT_VIA5    Via_5-6     violet           Black
-  C_X_N        Cont_CxN    orange           Black
-  C_X_P        Cont_CxP    orange           Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |   Orient Panel Button Label, Foreground , Background Color  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_ORIENT_NAME 
-
-  NORTH  North   lawn_green  Black
-  SOUTH  South   yellow      Black
-  EAST   East    tan         Black
-  WEST   West    red         Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Symmetry Panel Button Label, Foreground , Background Color  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_SYMMETRY_NAME
-
-  NOSYM No_Sym  LightBlue         Black
-  SYM_X Sym_X   turquoise         Black
-  SYM_Y Sym_Y   cyan              Black
-  SYMXY Sym_XY  LightCyan         Black
-  ROT_P Rot_P   MediumAquamarine  Black
-  ROT_M Rot_M   aquamarine        Black
-  SY_RP Sym_RP  green             Black
-  SY_RM Sym_RM  MediumSpringGreen Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# | View Layer Panel Button Label, Foreground, Background Color |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_RDS_LAYER_NAME
-
-  RDS_NWELL    Nwell   tan               Black
-  RDS_PWELL    Pwell   light_yellow      Black
-  RDS_NIMP     Nimp    forest_green      Black
-  RDS_PIMP     Pimp    goldenrod         Black
-  RDS_ACTIV    Activ   brown             Black
-  RDS_NDIF     Ndif    lawn_green        Black
-  RDS_PDIF     Pdif    yellow            Black
-  RDS_NTIE     Ntie    spring_green      Black
-  RDS_PTIE     Ptie    light_goldenrod   Black
-  RDS_POLY     Poly    red               Black
-  RDS_VPOLY    VPoly   coral             Black
-  RDS_GATE     Gate    orange            Black
-  RDS_TPOLY    Tpoly   hot_pink          Black
-  RDS_CONT     Cont    dark_violet       Black
-  RDS_TCONT    TCont   orchid            Black
-  RDS_ALU1     Alu1    royal_blue        Black
-  RDS_VALU1    VAlu1   sky_blue          Black
-  RDS_TALU1    Talu1   royal_blue        Black
-  RDS_VIA1     Via1    deep_sky_blue     Black
-  RDS_TVIA1    TVia1   dodger_blue       Black
-  RDS_ALU2     Alu2    cyan              Black
-  RDS_TALU2    Talu2   turquoise         Black
-  RDS_VIA2     Via2    deep_pink         Black
-  RDS_ALU3     Alu3    light_pink        Black
-  RDS_TALU3    Talu3   light_pink        Black
-  RDS_VIA3     Via3    sea_green         Black
-  RDS_ALU4     Alu4    green             Black
-  RDS_TALU4    Talu4   green             Black
-  RDS_VIA4     Via4    gold              Black
-  RDS_ALU5     Alu5    yellow            Black
-  RDS_TALU5    Talu5   yellow            Black
-  RDS_VIA5     Via5    violet_red        Black
-  RDS_ALU6     Alu6    violet            Black
-  RDS_TALU6    Talu6   violet            Black
-  RDS_CPAS     Cpas    gray              Black
-  RDS_REF      Ref     coral             Black
-  RDS_ABOX     Abox    pink              Black
-
-END
diff --git a/alliance/share/etc/cmos_8.rds b/alliance/share/etc/cmos_8.rds
deleted file mode 100644
index dd3113e2..00000000
--- a/alliance/share/etc/cmos_8.rds
+++ /dev/null
@@ -1,802 +0,0 @@
-#=====================================================================
-#
-#                         ALLIANCE VLSI CAD                  
-#            (R)eal (D)ata (S)tructure parameter file
-#         (c) copyright 1992 Laboratory UPMC/MASI/CAO-VLSI   
-#                        all rights reserved                 
-#                   e-mail : cao-vlsi@masi.ibp.fr            
-#
-#                   file       : cmos_7.rds
-#                   version    : 10
-#                   last modif : Nov 4, 1999
-#
-##-------------------------------------------------------------------
-# Symbolic to micron on a 'one lambda equals one micron' basis
-##-------------------------------------------------------------------
-# Refer to the documentation for more precise information.
-#=====================================================================
-# 99/11/4 old rules 
-# . for ALU1, ALU2, GATE
-# . however stacked are allowed
-# 
-# 99/11/3 ALU5/6 rules
-# . theses rules are preliminary rules, we hope that they wil change
-#   in future. For now, ALU5/6 are dedicated to supplies an clock.
-# 
-# 99/3/22 new symbolics rules
-# . ALU1 width remains 1, ALU2/3/4 is 2
-# . ALU1/2/3/4 distance (edge to edge) is now 3 for all
-# . GATE to GATE distance is 3 but POLY wire to POLY wire remains 2
-# . All via stacking are allowed
-#
-# 98/12/1 drc rules were updated
-# distance VIA to POLY or gate is one rather 2
-# VIA2 and ALU3 appeared
-# . ALU3 width is 3
-# . ALU2/VIA2/ALU3 is resp. 3/1/3
-# . ALU3 edge distance is 2
-# . stacked VIA/VIA2 is allowed
-# . if they are not stacked they must distant of 2
-# . CONT/VIA2 is free
-# note
-# . stacked CONT/VIA is always not allowed
-# NWELL is automatically drawn with the DIFN and NTIE layers
-#=====================================================================
-
-##-------------------------------------------------------------------
-# PHYSICAL_GRID :
-##-------------------------------------------------------------------
-
-DEFINE  PHYSICAL_GRID  .5
-
-##-------------------------------------------------------------------
-# LAMBDA : 
-##-------------------------------------------------------------------
-
-DEFINE  LAMBDA         1
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_SEGMENT :
-#
-# MBK      RDS layer 1                 RDS layer 2         
-# name     name TRANS DLR DWR OFFSET   name TRANS DLR DWR OFFSET  ...
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_SEGMENT
-
-  PWELL    RDS_PWELL  VW  0.0  0.0  0.0  EXT
-  NWELL    RDS_NWELL  VW  0.0  0.0  0.0  ALL
-  NDIF     RDS_NDIF   VW  0.5  0.0  0.0  ALL
-  PDIF     RDS_PDIF   VW  0.5  0.0  0.0  ALL \
-           RDS_NWELL  VW  1.0  1.0  0.0  ALL
-  NTIE     RDS_NTIE   VW  0.5  0.0  0.0  ALL \
-           RDS_NWELL  VW  1.0  1.0  0.0  ALL
-  PTIE     RDS_PTIE   VW  0.5  0.0  0.0  ALL
-  NTRANS   RDS_POLY   VW  0.0  0.0  0.0  ALL \
-           RDS_NDIF  LCW -1.5  2.0  0.0  EXT \
-           RDS_NDIF  RCW -1.5  2.0  0.0  EXT \
-           RDS_NDIF   VW -1.5  4.0  0.0  DRC \
-           RDS_PWELL  VW -1.5  0.0  0.0  EXT
-  PTRANS   RDS_POLY   VW  0.0  0.0  0.0  ALL \
-           RDS_PDIF  LCW -1.5  2.0  0.0  EXT \
-           RDS_PDIF  RCW -1.5  2.0  0.0  EXT \
-           RDS_PDIF   VW -1.5  4.0  0.0  DRC \
-           RDS_NWELL  VW -1.0  5.0  0.0  ALL 
-  POLY     RDS_POLY   VW  0.5  0.0  0.0  ALL
-  ALU1     RDS_ALU1   VW  0.5  0.0  0.0  ALL
-  ALU2     RDS_ALU2   VW  1.0  0.0  0.0  ALL
-  ALU3     RDS_ALU3   VW  1.0  0.0  0.0  ALL
-  ALU4     RDS_ALU4   VW  1.0  0.0  0.0  ALL
-  ALU5     RDS_ALU5   VW  1.0  0.0  0.0  ALL
-  ALU6     RDS_ALU6   VW  1.0  0.0  0.0  ALL 
-  TPOLY    RDS_TPOLY  VW  0.5  0.0  0.0  ALL
-  TALU1    RDS_TALU1  VW  0.5  0.0  0.0  ALL
-  TALU2    RDS_TALU2  VW  1.0  0.0  0.0  ALL
-  TALU3    RDS_TALU3  VW  1.0  0.0  0.0  ALL
-  TALU4    RDS_TALU4  VW  1.0  0.0  0.0  ALL
-  TALU5    RDS_TALU5  VW  1.0  0.0  0.0  ALL
-  TALU6    RDS_TALU6  VW  1.0  0.0  0.0  ALL
-
-END
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_CONNECTOR :
-#
-# MBK      RDS layer 
-# name     name     DER DWR 
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_CONNECTOR
-
-  POLY    RDS_POLY  .5  0  
-  ALU1    RDS_ALU1  .5  0  
-  ALU2    RDS_ALU2 1.0  0  
-  ALU3    RDS_ALU3 1.0  0  
-  ALU4    RDS_ALU4 1.0  0  
-  ALU5    RDS_ALU4 1.0  0  
-  ALU6    RDS_ALU4 1.0  0  
-
-END
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_REFERENCE :
-#
-# MBK ref    RDS layer 
-# name       name       width
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_REFERENCE
-
-  REF_REF    RDS_REF    1
-  REF_CON    RDS_VALU1  2  RDS_TVIA1 1  RDS_TALU2  2
-
-END
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_VIA1 :
-#
-# MBK via      RDS layer 1  RDS  layer 2  RDS  layer 3  RDS layer 4      
-# name         name  width  name   width  name   width  name  width  
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_VIA
-
-  CONT_BODY_P  RDS_ALU1 2 ALL  RDS_CONT 1 ALL  RDS_PTIE 3 ALL  
-  CONT_BODY_N  RDS_ALU1 2 ALL  RDS_CONT 1 ALL  RDS_NTIE 3 ALL  RDS_NWELL 4 ALL
-  CONT_DIF_N   RDS_ALU1 2 ALL  RDS_CONT 1 ALL  RDS_NDIF 3 ALL
-  CONT_DIF_P   RDS_ALU1 2 ALL  RDS_CONT 1 ALL  RDS_PDIF 3 ALL  RDS_NWELL 4 ALL
-  CONT_POLY    RDS_ALU1 2 ALL  RDS_CONT 1 ALL  RDS_POLY 3 ALL
-  CONT_VIA     RDS_ALU1 2 ALL  RDS_VIA1 1 ALL  RDS_ALU2 3 ALL
-  CONT_VIA2    RDS_ALU2 3 ALL  RDS_VIA2 1 ALL  RDS_ALU3 2 ALL
-  CONT_VIA3    RDS_ALU3 2 ALL  RDS_VIA3 1 ALL  RDS_ALU4 2 ALL
-  CONT_VIA4    RDS_ALU4 2 ALL  RDS_VIA4 1 ALL  RDS_ALU5 2 ALL
-  CONT_VIA5    RDS_ALU5 2 ALL  RDS_VIA5 1 ALL  RDS_ALU6 2 ALL
-  C_X_N        RDS_POLY 1 ALL  RDS_NDIF 5 ALL
-  C_X_P        RDS_POLY 1 ALL  RDS_PDIF 5 ALL  RDS_NWELL 6 ALL
-
-END
-
-##-------------------------------------------------------------------
-# TABLE LYNX_GRAPH :
-#
-# RDS layer   Rds layer 1   Rds layer 2    ...
-# name        name          name           ...
-##-------------------------------------------------------------------
-
-TABLE LYNX_GRAPH
-
-##---------------------------
-#
-# Modifie par L.Jacomme (Pb Bulk/Alim avec Lynx)
-# 23.11.99
-#
-# RDS_NWELL  RDS_NTIE   RDS_NWELL
-# RDS_PWELL  RDS_PTIE   RDS_PWELL
-# RDS_NDIF  RDS_CONT RDS_NDIF
-# RDS_PDIF  RDS_CONT RDS_PDIF
-# RDS_NTIE  RDS_CONT RDS_NTIE   RDS_NWELL
-# RDS_PTIE  RDS_CONT RDS_PTIE   RDS_PWELL
-
-  RDS_NDIF  RDS_CONT RDS_NDIF
-  RDS_PDIF  RDS_CONT RDS_PDIF
-  RDS_NTIE  RDS_CONT RDS_NTIE
-  RDS_PTIE  RDS_CONT RDS_PTIE
-
-  RDS_POLY  RDS_CONT RDS_POLY 
-  RDS_CONT  RDS_PDIF RDS_NDIF RDS_POLY RDS_PTIE  RDS_NTIE RDS_ALU1 RDS_CONT
-  RDS_ALU1  RDS_CONT RDS_VIA1 RDS_ALU1 RDS_VALU1 RDS_ALU1
-  RDS_VALU1 RDS_CONT RDS_VIA1 RDS_ALU1 RDS_VALU1
-  RDS_VIA1  RDS_ALU1 RDS_ALU2 RDS_VIA1
-  RDS_VIA2  RDS_ALU2 RDS_ALU3 RDS_VIA2
-  RDS_VIA3  RDS_ALU3 RDS_ALU4 RDS_VIA3
-  RDS_VIA4  RDS_ALU4 RDS_ALU5 RDS_VIA4
-  RDS_VIA5  RDS_ALU5 RDS_ALU6 RDS_VIA5
-  RDS_ALU2  RDS_VIA1 RDS_VIA2 RDS_ALU2 
-  RDS_ALU3  RDS_VIA2 RDS_VIA3 RDS_ALU3
-  RDS_ALU4  RDS_VIA3 RDS_VIA4 RDS_ALU4 
-  RDS_ALU5  RDS_VIA4 RDS_VIA5 RDS_ALU5 
-  RDS_ALU6  RDS_VIA5          RDS_ALU6 
-
-END
-
-##-------------------------------------------------------------------
-# TABLE LYNX_CAPA : 
-#
-# RDS layer   Surface capacitance  Perimetric capacitance
-# name        piF / Micron^2       piF / Micron 
-##-------------------------------------------------------------------
-
-TABLE LYNX_CAPA
-
-  RDS_POLY    1.00e-04    1.00e-04
-  RDS_ALU1    0.50e-04    0.90e-04
-  RDS_ALU2    0.25e-04    0.95e-04
-  RDS_ALU3    0.25e-04    0.95e-04
-  RDS_ALU4    0.25e-04    0.95e-04
-  RDS_ALU5    0.25e-04    0.95e-04
-  RDS_ALU6    0.25e-04    0.95e-04
-
-END
-
-##-------------------------------------------------------------------
-# TABLE LYNX_RESISTOR :
-#
-# RDS layer   Surface resistor
-# name        Ohm / Micron^2 
-##-------------------------------------------------------------------
-
-TABLE LYNX_RESISTOR
-
-  RDS_POLY    50.0
-  RDS_ALU1     0.1
-  RDS_ALU2     0.05
-  RDS_ALU3     0.05
-  RDS_ALU4     0.05
-  RDS_ALU5     0.05
-  RDS_ALU6     0.05
-
-END
-
-##-------------------------------------------------------------------
-# TABLE LYNX_TRANSISTOR : 
-#
-# MBK layer  Transistor Type  MBK via
-# name       name             name
-##-------------------------------------------------------------------
-
-TABLE LYNX_TRANSISTOR
-
-  NTRANS  NTRANS  C_X_N   RDS_POLY   RDS_NDIF  RDS_NDIF   RDS_PWELL
-  PTRANS  PTRANS  C_X_P   RDS_POLY   RDS_PDIF  RDS_PDIF   RDS_NWELL
-
-END
-
-##-------------------------------------------------------------------
-# TABLE LYNX_DIFFUSION :
-#
-# RDS layer  RDS layer
-# name       name    
-##-------------------------------------------------------------------
-
-TABLE LYNX_DIFFUSION
-END
-
-##-------------------------------------------------------------------
-# TABLE LYNX_BULK_IMPLICIT :
-#
-# RDS layer  Bulk type
-# name       EXPLICIT/IMPLICIT
-##-------------------------------------------------------------------
-
-TABLE LYNX_BULK_IMPLICIT
-
-##---------------------------
-#
-# Modifie par L.Jacomme (Pb Bulk/Alim avec Lynx)
-# 23.11.99
-#
-# NWELL  EXPLICIT
-# PWELL  IMPLICIT
-
-END
-
-##-------------------------------------------------------------------
-# TABLE S2R_OVERSIZE_DENOTCH :
-##-------------------------------------------------------------------
-
-TABLE S2R_OVERSIZE_DENOTCH 
-END
-
-##-------------------------------------------------------------------
-# TABLE S2R_BLOC_RING_WIDTH :
-##-------------------------------------------------------------------
-
-TABLE S2R_BLOC_RING_WIDTH
-END
-
-##-------------------------------------------------------------------
-# TABLE S2R_MINIMUM_LAYER_WIDTH :
-##-------------------------------------------------------------------
-
-TABLE S2R_MINIMUM_LAYER_WIDTH 
-
-  RDS_NWELL   4
-  RDS_PDIF    2
-  RDS_NTIE    2
-  RDS_PTIE    2
-  RDS_POLY    1
-  RDS_TPOLY   1
-  RDS_CONT    1
-  RDS_ALU1    1
-  RDS_TALU1   1
-  RDS_VIA1    1
-  RDS_ALU2    2
-  RDS_TALU2   2
-  RDS_VIA2    1
-  RDS_ALU3    2
-  RDS_TALU3   2
-  RDS_VIA3    1
-  RDS_ALU4    2
-  RDS_TALU4   2
-  RDS_VIA4    1
-  RDS_ALU5    4
-  RDS_TALU5   4
-  RDS_VIA5    1
-  RDS_ALU6    4
-  RDS_TALU6   4
-
-END
-
-##-------------------------------------------------------------------
-# TABLE CIF_LAYER :
-##-------------------------------------------------------------------
-
-TABLE CIF_LAYER
-
-  RDS_NWELL    LNWELL
-  RDS_NDIF     LNDIF
-  RDS_PDIF     LPDIF
-  RDS_NTIE     LNTIE
-  RDS_PTIE     LPTIE
-  RDS_POLY     LPOLY
-  RDS_TPOLY    LTPOLY
-  RDS_CONT     LCONT
-  RDS_ALU1     LALU1
-  RDS_VALU1    LVALU1
-  RDS_TALU1    LTALU1
-  RDS_VIA1     LVIA
-  RDS_TVIA1    LTVIA1
-  RDS_ALU2     LALU2
-  RDS_TALU2    LTALU2
-  RDS_VIA2     LVIA2
-  RDS_ALU3     LALU3
-  RDS_TALU3    LTALU3
-  RDS_VIA3     LVIA3
-  RDS_ALU4     LALU4
-  RDS_TALU4    LTALU4
-  RDS_VIA4     LVIA4
-  RDS_ALU5     LALU5
-  RDS_TALU5    LTALU5
-  RDS_VIA5     LVIA5
-  RDS_ALU6     LALU6
-  RDS_TALU6    LTALU6
-  RDS_REF      LREF
-
-END
-
-##-------------------------------------------------------------------
-# TABLE GDS_LAYER :
-##-------------------------------------------------------------------
-
-TABLE GDS_LAYER
-
-  RDS_NWELL    1
-  RDS_NDIF     3
-  RDS_PDIF     4
-  RDS_NTIE     5
-  RDS_PTIE     6
-  RDS_POLY     7
-  RDS_TPOLY    9
-  RDS_CONT    10
-  RDS_ALU1    11
-  RDS_VALU1   12
-  RDS_TALU1   13
-  RDS_VIA1    14
-  RDS_TVIA1   15
-  RDS_ALU2    16
-  RDS_TALU2   17
-  RDS_VIA2    18
-  RDS_ALU3    19
-  RDS_TALU3   20
-  RDS_VIA3    21
-  RDS_ALU4    22
-  RDS_TALU4   23
-  RDS_VIA4    25
-  RDS_ALU5    26
-  RDS_TALU5   27
-  RDS_VIA5    28
-  RDS_ALU6    29
-  RDS_TALU6   30
-  RDS_REF     24
-
-END
-
-##-------------------------------------------------------------------
-# TABLE S2R_POST_TREAT :
-##-------------------------------------------------------------------
-
-TABLE S2R_POST_TREAT
-
-END
-DRC_RULES
-
-layer RDS_NWELL 4.;
-layer RDS_NTIE 2.;
-layer RDS_PTIE 2.;
-layer RDS_NDIF 2.;
-layer RDS_PDIF 2.;
-layer RDS_CONT 1.;
-layer RDS_VIA1 1.;
-layer RDS_VIA2 1.;
-layer RDS_VIA3 1.;
-layer RDS_VIA4 1.;
-layer RDS_VIA5 1.;
-layer RDS_POLY 1.;
-layer RDS_ALU1 1.;
-layer RDS_ALU2 2.;
-layer RDS_ALU3 2.;
-layer RDS_ALU4 2.;
-layer RDS_ALU5 2.;
-layer RDS_ALU6 2.;
-layer RDS_USER0 1.;
-layer RDS_USER1 1.;
-layer RDS_USER2 1.;
-
-regles
-
-# Note : ``min'' is different from ``>=''. 
-# min is applied on polygons and >= is applied on rectangles.
-# There is the same difference between max and <=.
-# >= is faster than min, but min must be used where it is
-# required to consider polygons, for example distance of
-# two objects in the same layer 
-#
-# There is no rule to check NTIE and PDIF are included in NWELL
-# since this is necessarily true
-#----------------------------------------------------------- 
-
-# Check the NWELL shapes
-#-----------------------
-caracterise RDS_NWELL (
-  regle 1 : largeur >= 4. ;
-  regle 2 : longueur_inter min 4. ;
-  regle 3 : notch >= 12. ;
-);
-relation RDS_NWELL , RDS_NWELL (
-  regle 4 : distance axiale min 12. ;
-);
-
-# Check RDS_PTIE is really excluded outside NWELL
-#------------------------------------------------
-relation RDS_PTIE , RDS_NWELL (
-  regle 5 : distance axiale >= 7.5;
-  regle 6 : enveloppe longueur_inter < 0. ;
-  regle 7 : marge longueur_inter < 0. ;
-  regle 8 : croix longueur_inter < 0. ;
-  regle 9 : intersection longueur_inter < 0. ;
-  regle 10 : extension longueur_inter < 0. ;
-  regle 11 : inclusion longueur_inter < 0. ;
-);
-
-# Check RDS_NDIF is really excluded outside NWELL
-#------------------------------------------------
-relation RDS_NDIF , RDS_NWELL (
-  regle 12 : distance axiale >= 7.5;
-  regle 13 : enveloppe longueur_inter < 0. ;
-  regle 14 : marge longueur_inter < 0. ;
-  regle 15 : croix longueur_inter < 0. ;
-  regle 16 : intersection longueur_inter < 0. ;
-  regle 17 : extension longueur_inter < 0. ;
-  regle 18 : inclusion longueur_inter < 0. ;
-);
-
-# Check the RDS_PDIF shapes
-#--------------------------
-caracterise RDS_PDIF (
-  regle 19 : largeur >= 2. ;
-  regle 20 : longueur_inter min 2. ;
-  regle 21 : notch >= 2. ;
-);
-relation RDS_PDIF , RDS_PDIF (
-  regle 22 : distance axiale min 3. ;
-);
-
-# Check the RDS_NDIF shapes
-#--------------------------
-caracterise RDS_NDIF (
-  regle 23 : largeur >= 2. ;
-  regle 24 : longueur_inter min 2. ;
-  regle 25 : notch >= 2. ;
-);
-relation RDS_NDIF , RDS_NDIF (
-  regle 26 : distance axiale min 3. ;
-);
-
-# Check the RDS_PTIE shapes
-#--------------------------
-caracterise RDS_PTIE (
-  regle 27 : largeur >= 2. ;
-  regle 28 : longueur_inter min 2. ;
-  regle 29 : notch >= 2. ;
-);
-relation RDS_PTIE , RDS_PTIE (
-  regle 30 : distance axiale min 3. ;
-);
-
-# Check the RDS_NTIE shapes
-#--------------------------
-caracterise RDS_NTIE (
-  regle 31 : largeur >= 2. ;
-  regle 32 : longueur_inter min 2. ;
-  regle 33 : notch >= 2. ;
-);
-relation RDS_NTIE , RDS_NTIE (
-  regle 34 : distance axiale min 3. ;
-);
-
-define RDS_PDIF , RDS_PTIE union -> ANY_P_DIF;
-define RDS_NDIF , RDS_NTIE union -> ANY_N_DIF;
-
-# Check the ANY_N_DIF ANY_P_DIFF exclusion
-#--------------------------------------
-relation ANY_N_DIF , ANY_P_DIF (
-  regle 35 : distance axiale >= 3. ;
-  regle 36 : enveloppe longueur_inter < 0. ;
-  regle 37 : marge longueur_inter < 0. ;
-  regle 38 : croix longueur_inter < 0. ;
-  regle 39 : intersection longueur_inter < 0. ;
-  regle 40 : extension longueur_inter < 0. ;
-  regle 41 : inclusion longueur_inter < 0. ;
-);
-
-# Check RDS_POLY is distant from ANY_DIF
-#---------------------------------------
-relation RDS_POLY , ANY_P_DIF (
-  regle 42 : distance axiale >= 1. ;
-);
-relation RDS_POLY , ANY_N_DIF (
-  regle 43 : distance axiale >= 1. ;
-);
-
-undefine ANY_P_DIF;
-undefine ANY_N_DIF;
-
-define RDS_NDIF , RDS_PDIF union -> NP_DIF;
-define NP_DIF , RDS_POLY intersection -> CHANNEL;
-
-# Check the RDS_POLY shapes
-#--------------------------
-caracterise RDS_POLY (
-  regle 44 : largeur >= 1. ;
-  regle 45 : longueur_inter min 1. ;
-  regle 46 : notch >= 2. ;
-);
-relation RDS_POLY , RDS_POLY (
-  regle 47 : distance axiale min 2.;
-);
-
-# Check the CHANNEL shapes
-#--------------------------
-caracterise CHANNEL (
-  regle 48 : notch >= 2. ;
-);
-relation CHANNEL , CHANNEL (
-  regle 49 : distance axiale min 2.;
-);
-
-
-# Check the RDS_POLY distance
-#----------------------------
-relation RDS_POLY , RDS_POLY (
-  regle 50 : distance axiale min 2.;
-);
-
-undefine CHANNEL;
-
-define NP_DIF , RDS_CONT intersection -> CONT_DIFF;
-relation RDS_POLY , CONT_DIFF (
-  regle 79 : distance axiale >= 2. ;
-);
-
-undefine CONT_DIFF;
-undefine NP_DIF;
-
-
-# Check RDS_ALU1 shapes
-#----------------------
-caracterise RDS_ALU1 (
-  regle 51 : largeur >= 1. ;
-  regle 52 : longueur_inter min 1. ;
-  regle 53 : notch >= 2.5 ;
-);
-relation RDS_ALU1 , RDS_ALU1 (
-  regle 54 : distance axiale min 2.5 ;
-);
-
-# Check RDS_ALU2 shapes
-#----------------------
-caracterise RDS_ALU2 (
-  regle 55 : largeur >= 2. ;
-  regle 56 : longueur_inter min 2. ;
-  regle 57 : notch >= 2. ;
-);
-relation RDS_ALU2 , RDS_ALU2 (
-  regle 58 : distance axiale min 2. ;
-);
-
-# Check RDS_ALU3 shapes
-#----------------------
-caracterise RDS_ALU3 (
-  regle 59 : largeur >= 2. ;
-  regle 60 : longueur_inter min 2. ;
-  regle 61 : notch >= 3. ;
-);
-relation RDS_ALU3 , RDS_ALU3 (
-  regle 62 : distance axiale min 3. ;
-);
-
-# Check RDS_ALU4 shapes
-#----------------------
-caracterise RDS_ALU4 (
-  regle 63 : largeur >= 2. ;
-  regle 64 : longueur_inter min 2. ;
-  regle 65 : notch >= 3. ;
-);
-relation RDS_ALU4 , RDS_ALU4 (
-  regle 66 : distance axiale min 3. ;
-);
-
-# Check RDS_ALU5 shapes
-#----------------------
-caracterise RDS_ALU5 (
-  regle 80 : largeur >= 2. ;
-  regle 81 : longueur_inter min 2. ;
-  regle 82 : notch >= 12. ;
-);
-relation RDS_ALU5 , RDS_ALU5 (
-  regle 83 : distance axiale min 12. ;
-);
-
-# Check RDS_ALU6 shapes
-#----------------------
-caracterise RDS_ALU6 (
-  regle 84 : largeur >= 2. ;
-  regle 85 : longueur_inter min 2. ;
-  regle 86 : notch >= 12. ;
-);
-relation RDS_ALU6 , RDS_ALU6 (
-  regle 87 : distance axiale min 12. ;
-);
-
-# Check ANY_VIA layers, stacking are free
-#----------------------------------------
-relation RDS_CONT , RDS_CONT (
-  regle 67 : distance axiale >= 3. ;
-);
-relation RDS_VIA , RDS_VIA (
-  regle 68 : distance axiale >= 3. ;
-);
-relation RDS_VIA2 , RDS_VIA2 (
-  regle 69 : distance axiale >= 3. ;
-);
-relation RDS_VIA3 , RDS_VIA3 (
-  regle 70 : distance axiale >= 3. ;
-);
-relation RDS_VIA4 , RDS_VIA4 (
-  regle 88 : distance axiale >= 5. ;
-);
-relation RDS_VIA5 , RDS_VIA5 (
-  regle 89 : distance axiale >= 5. ;
-);
-caracterise RDS_CONT (
-  regle 71 : largeur >= 1. ;
-  regle 72 : longueur <= 1. ;
-);
-caracterise RDS_VIA (
-  regle 73 : largeur >= 1. ;
-  regle 74 : longueur <= 1. ;
-);
-caracterise RDS_VIA2 (
-  regle 75 : largeur >= 1. ;
-  regle 76 : longueur <= 1. ;
-);
-caracterise RDS_VIA3 (
-  regle 77 : largeur >= 1. ;
-  regle 78 : longueur <= 1. ;
-);
-caracterise RDS_VIA4 (
-  regle 90 : largeur >= 1. ;
-  regle 91 : longueur <= 1. ;
-);
-caracterise RDS_VIA5 (
-  regle 92 : largeur >= 1. ;
-  regle 93 : longueur <= 1. ;
-);
-
-fin regles
-DRC_COMMENT
-1 (RDS_NWELL) minimum width 4. 
-2 (RDS_NWELL) minimum width 4. 
-3 (RDS_NWELL) Manhatan distance min 12. 
-4 (RDS_NWELL,RDS_NWELL) Manhatan distance min 12. 
-5 (RDS_PTIE,RDS_NWELL) Manhatan distance min 7.5
-6 (RDS_PTIE,RDS_NWELL) must never been in contact
-7 (RDS_PTIE,RDS_NWELL) must never been in contact
-8 (RDS_PTIE,RDS_NWELL) must never been in contact
-9 (RDS_PTIE,RDS_NWELL) must never been in contact
-10 (RDS_PTIE,RDS_NWELL) must never been in contact
-11 (RDS_PTIE,RDS_NWELL) must never been in contact
-12 (RDS_NDIF,RDS_NWELL) Manhatan distance min 7.5
-13 (RDS_NDIF,RDS_NWELL) must never been in contact
-14 (RDS_NDIF,RDS_NWELL) must never been in contact
-15 (RDS_NDIF,RDS_NWELL) must never been in contact
-16 (RDS_NDIF,RDS_NWELL) must never been in contact
-17 (RDS_NDIF,RDS_NWELL) must never been in contact
-18 (RDS_NDIF,RDS_NWELL) must never been in contact
-19 (RDS_PDIF) minimum width 2. 
-20 (RDS_PDIF) minimum width 2. 
-21 (RDS_PDIF) Manhatan distance min 2. 
-22 (RDS_PDIF,RDS_PDIF) Manhatan distance min 3. 
-23 (RDS_NDIF) minimum width 2. 
-24 (RDS_NDIF) minimum width 2. 
-25 (RDS_NDIF) Manhatan distance min 2. 
-26 (RDS_NDIF,RDS_NDIF) Manhatan distance min 3. 
-27 (RDS_PTIE) minimum width 2. 
-28 (RDS_PTIE) minimum width 2. 
-29 (RDS_PTIE) Manhatan distance min 2. 
-30 (RDS_PTIE,RDS_PTIE) Manhatan distance min 3. 
-31 (RDS_NTIE) minimum width 2. 
-32 (RDS_NTIE) minimum width 2. 
-33 (RDS_NTIE) Manhatan distance min 2. 
-34 (RDS_NTIE,RDS_NTIE) Manhatan distance min 3. 
-35 (ANY_N_DIF,ANY_P_DIF) Manhatan distance min 3. 
-36 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-37 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-38 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-39 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-40 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-41 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-42 (RDS_POLY,ANY_N_DIF) Manhatan distance min 1. 
-43 (RDS_POLY,ANY_P_DIF) Manhatan distance min 1. 
-44 (RDS_POLY) minimum width 1. 
-45 (RDS_POLY) minimum width 1. 
-46 (RDS_POLY) Manhatan distance min 2. 
-47 (RDS_POLY,RDS_POLY) Manhatan distance min 2.
-48 (CHANNEL) Manhatan distance min 2. 
-49 (CHANNEL,CHANNEL) Manhatan distance min 2.
-50 (RDS_POLY,RDS_POLY) Manhatan distance min 2.
-51 (RDS_ALU1) minimum width 1. 
-52 (RDS_ALU1) minimum width 1. 
-53 (RDS_ALU1) Manhatan distance min 2.5
-54 (RDS_ALU1,RDS_ALU1) Manhatan distance min 2.5
-55 (RDS_ALU2) minimum width 2. 
-56 (RDS_ALU2) minimum width 2. 
-57 (RDS_ALU2) Manhatan distance min 2. 
-58 (RDS_ALU2,RDS_ALU2) Manhatan distance min 2. 
-59 (RDS_ALU3) minimum width 2. 
-60 (RDS_ALU3) minimum width 2. 
-61 (RDS_ALU3) Manhatan distance min 3. 
-62 (RDS_ALU3,RDS_ALU3) Manhatan distance min 3. 
-63 (RDS_ALU4) minimum width 2. 
-64 (RDS_ALU4) minimum width 2. 
-65 (RDS_ALU4) Manhatan distance min 3. 
-66 (RDS_ALU4,RDS_ALU4) Manhatan distance min 3. 
-67 (RDS_CONT,RDS_CONT) Manhatan distance min 3. 
-68 (RDS_VIA,RDS_VIA) Manhatan distance min 3. 
-69 (RDS_VIA2,RDS_VIA2) Manhatan distance min 3. 
-70 (RDS_VIA3,RDS_VIA3) Manhatan distance min 3. 
-71 (RDS_CONT) minimum width 1. 
-72 (RDS_CONT) maximum length 1. 
-73 (RDS_VIA) minimum width 1. 
-74 (RDS_VIA) maximum length 1. 
-75 (RDS_VIA2) minimum width 1. 
-76 (RDS_VIA2) maximum length 1. 
-77 (RDS_VIA3) minimum width 1. 
-78 (RDS_VIA3) maximum length 1. 
-79 (RDS_POLY,CONT_DIFF) Manhatan distance min 2. 
-80 (RDS_ALU5) minimum width 2. 
-81 (RDS_ALU5) minimum width 2. 
-82 (RDS_ALU5) Manhatan distance min 12. 
-83 (RDS_ALU5,RDS_ALU5) Manhatan distance min 12. 
-84 (RDS_ALU6) minimum width 2. 
-85 (RDS_ALU6) minimum width 2. 
-86 (RDS_ALU6) Manhatan distance min 12. 
-87 (RDS_ALU6,RDS_ALU6) Manhatan distance min 12. 
-88 (RDS_VIA4,RDS_VIA4) Manhatan distance min 5. 
-89 (RDS_VIA5,RDS_VIA5) Manhatan distance min 5. 
-90 (RDS_VIA4) minimum width 1. 
-91 (RDS_VIA4) maximum length 1. 
-92 (RDS_VIA5) minimum width 1. 
-93 (RDS_VIA5) maximum length 1. 
-END_DRC_COMMENT
-END_DRC_RULES
diff --git a/alliance/share/etc/cmos_9.graal b/alliance/share/etc/cmos_9.graal
deleted file mode 100644
index b8800bf7..00000000
--- a/alliance/share/etc/cmos_9.graal
+++ /dev/null
@@ -1,293 +0,0 @@
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Title      :      Parameters File for Graal                 |
-# |                                                             |
-# | Technology :              Cmos V9                           |
-# |                                                             |
-# | Date       :             4/11/99                            |
-# |                                                             |
-# \------------------------------------------------------------*/
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                 Graal Peek Bound in lambda                  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_PEEK_BOUND 7
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |               Lower Grid Step in pixel by lambda            |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_LOWER_GRID_STEP 10
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |          Lower Figure Text Step in pixel by lambda          |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_LOWER_FIGURE_STEP 1
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |         Lower Instance Text Step in pixel by lambda         |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_LOWER_INSTANCE_STEP 1
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |        Lower Connector Text Step in pixel by lambda         |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_LOWER_CONNECTOR_STEP 5
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |          Lower Segment Text Step in pixel by lambda         |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_LOWER_SEGMENT_STEP 7
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |         Lower Reference Text Step in pixel by lambda        |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_LOWER_REFERENCE_STEP 10
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                 Graal Cursor Color Name                     |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_CURSOR_COLOR_NAME  Gray
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                 Graal Cursor Size in pixel                  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE GRAAL_CURSOR_SIZE 10 
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |  Segment Panel Button Label, Foreground , Background Color  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_SEGMENT_NAME
-
-  NWELL    Nwell  tan              Black
-  PWELL    Pwell  light_yellow     Black
-  NDIF     Ndif   lawn_green       Black
-  PDIF     Pdif   yellow           Black
-  NTIE     Ntie   spring_green     Black
-  PTIE     Ptie   light_goldenrod  Black
-  POLY     Poly   red              Black
-  ALU1     Alu1   royal_blue       Black
-  ALU2     Alu2   Cyan             Black
-  ALU3     Alu3   light_pink       Black
-  ALU4     Alu4   green            Black
-  ALU5     Alu5   yellow           Black
-  ALU6     Alu6   violet           Black
-  TPOLY    Tpoly  hot_pink         Black
-  TALU1    Talu1  royal_blue       Black
-  TALU2    Talu2  turquoise        Black
-  TALU3    Talu3  light_pink       Black
-  TALU4    Talu4  green            Black
-  TALU5    Talu5  yellow           Black
-  TALU6    Talu6  violet           Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Transistor Panel Button Label, Foreground, Background Color |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_TRANSISTOR_NAME
-
-  NTRANS   Ntrans lawn_green       Black
-  PTRANS   Ptrans yellow           Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Connector Panel Button Label, Foreground , Background Color |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_CONNECTOR_NAME
-
-  POLY     Poly   red              Black
-  ALU1     Alu1   royal_blue       Black
-  ALU2     Alu2   Cyan             Black
-  ALU3     Alu3   light_pink       Black
-  ALU4     Alu4   green            Black
-  ALU5     Alu5   yellow           Black
-  ALU6     Alu6   violet           Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |       Minimun Length and Width for a symbolic Segment       |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_SEGMENT_VALUE
-
-  NWELL    4   4
-  PWELL    4   4
-  NDIF     2   2
-  PDIF     2   2
-  NTIE     2   2
-  PTIE     2   2
-  NTRANS   1   4
-  PTRANS   1   4
-  POLY     1   1
-  ALU1     1   1
-  ALU2     2   2
-  ALU3     2   2
-  ALU4     2   2
-  ALU5     4   4
-  ALU6     4   4
-  TPOLY    1   1
-  TALU1    1   1
-  TALU2    2   2
-  TALU3    2   2
-  TALU4    2   2
-  TALU5    2   2
-  TALU6    2   2
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Reference Panel Button Label, Foreground, Background Color  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_REFERENCE_NAME
-
-  REF_REF  Ref_Ref red  Black
-  REF_CON  Ref_Con Cyan Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |     Via Panel Button Label, Foreground , Background Color   |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_VIA_NAME
-
-  CONT_DIF_N   Cont_NDif   lawn_green       Black
-  CONT_DIF_P   Cont_PDif   yellow           Black
-  CONT_BODY_N  Cont_NTie   spring_green     Black
-  CONT_BODY_P  Cont_PTie   light_goldenrod  Black
-  CONT_POLY    Cont_Poly   red              Black
-  CONT_VIA     Via_1-2     cyan             Black
-  CONT_VIA2    Via_2-3     light_pink       Black
-  CONT_VIA3    Via_3-4     green            Black
-  CONT_VIA4    Via_4-5     yellow           Black
-  CONT_VIA5    Via_5-6     violet           Black
-  C_X_N        Cont_CxN    orange           Black
-  C_X_P        Cont_CxP    orange           Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |   Orient Panel Button Label, Foreground , Background Color  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_ORIENT_NAME 
-
-  NORTH  North   lawn_green  Black
-  SOUTH  South   yellow      Black
-  EAST   East    tan         Black
-  WEST   West    red         Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Symmetry Panel Button Label, Foreground , Background Color  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_SYMMETRY_NAME
-
-  NOSYM No_Sym  LightBlue         Black
-  SYM_X Sym_X   turquoise         Black
-  SYM_Y Sym_Y   cyan              Black
-  SYMXY Sym_XY  LightCyan         Black
-  ROT_P Rot_P   MediumAquamarine  Black
-  ROT_M Rot_M   aquamarine        Black
-  SY_RP Sym_RP  green             Black
-  SY_RM Sym_RM  MediumSpringGreen Black
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# | View Layer Panel Button Label, Foreground, Background Color |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE GRAAL_RDS_LAYER_NAME
-
-  RDS_NWELL    Nwell   tan               Black
-  RDS_PWELL    Pwell   light_yellow      Black
-  RDS_NIMP     Nimp    forest_green      Black
-  RDS_PIMP     Pimp    goldenrod         Black
-  RDS_ACTIV    Activ   brown             Black
-  RDS_NDIF     Ndif    lawn_green        Black
-  RDS_PDIF     Pdif    yellow            Black
-  RDS_NTIE     Ntie    spring_green      Black
-  RDS_PTIE     Ptie    light_goldenrod   Black
-  RDS_POLY     Poly    red               Black
-  RDS_VPOLY    VPoly   coral             Black
-  RDS_GATE     Gate    orange            Black
-  RDS_TPOLY    Tpoly   hot_pink          Black
-  RDS_CONT     Cont    dark_violet       Black
-  RDS_TCONT    TCont   orchid            Black
-  RDS_ALU1     Alu1    royal_blue        Black
-  RDS_VALU1    VAlu1   sky_blue          Black
-  RDS_TALU1    Talu1   royal_blue        Black
-  RDS_VIA1     Via1    deep_sky_blue     Black
-  RDS_TVIA1    TVia1   dodger_blue       Black
-  RDS_ALU2     Alu2    cyan              Black
-  RDS_TALU2    Talu2   turquoise         Black
-  RDS_VIA2     Via2    deep_pink         Black
-  RDS_ALU3     Alu3    light_pink        Black
-  RDS_TALU3    Talu3   light_pink        Black
-  RDS_VIA3     Via3    sea_green         Black
-  RDS_ALU4     Alu4    green             Black
-  RDS_TALU4    Talu4   green             Black
-  RDS_VIA4     Via4    gold              Black
-  RDS_ALU5     Alu5    yellow            Black
-  RDS_TALU5    Talu5   yellow            Black
-  RDS_VIA5     Via5    violet_red        Black
-  RDS_ALU6     Alu6    violet            Black
-  RDS_TALU6    Talu6   violet            Black
-  RDS_CPAS     Cpas    gray              Black
-  RDS_REF      Ref     coral             Black
-  RDS_ABOX     Abox    pink              Black
-
-END
diff --git a/alliance/share/etc/cmos_9.rds b/alliance/share/etc/cmos_9.rds
deleted file mode 100644
index cbe91e22..00000000
--- a/alliance/share/etc/cmos_9.rds
+++ /dev/null
@@ -1,763 +0,0 @@
-#=====================================================================
-#
-#                         ALLIANCE VLSI CAD                  
-#            (R)eal (D)ata (S)tructure parameter file
-#         (c) copyright 1992 Laboratory UPMC/MASI/CAO-VLSI   
-#                        all rights reserved                 
-#                   e-mail : cao-vlsi@masi.ibp.fr            
-#
-#                   file       : cmos_9.rds
-#                   version    : 10
-#                   last modif : Nov 4, 1999
-#
-##-------------------------------------------------------------------
-# Symbolic to micron on a 'one lambda equals one micron' basis
-##-------------------------------------------------------------------
-# Refer to the documentation for more precise information.
-#=====================================================================
-# 99/11/3 ALU5/6 rules
-# . theses rules are preliminary rules, we hope that they wil change
-#   in future. For now, ALU5/6 are dedicated to supplies an clock.
-# 
-# 99/3/22 new symbolics rules
-# . ALU1 width remains 1, ALU2/3/4 is 2
-# . ALU1/2/3/4 distance (edge to edge) is now 3 for all
-# . GATE to GATE distance is 3 but POLY wire to POLY wire remains 2
-# . All via stacking are allowed
-#
-# 98/12/1 drc rules were updated
-# distance VIA to POLY or gate is one rather 2
-# VIA2 and ALU3 appeared
-# . ALU3 width is 3
-# . ALU2/VIA2/ALU3 is resp. 3/1/3
-# . ALU3 edge distance is 2
-# . stacked VIA/VIA2 is allowed
-# . if they are not stacked they must distant of 2
-# . CONT/VIA2 is free
-# note
-# . stacked CONT/VIA is always not allowed
-# NWELL is automatically drawn with the DIFN and NTIE layers
-#=====================================================================
-
-##-------------------------------------------------------------------
-# PHYSICAL_GRID :
-##-------------------------------------------------------------------
-
-DEFINE  PHYSICAL_GRID  .5
-
-##-------------------------------------------------------------------
-# LAMBDA : 
-##-------------------------------------------------------------------
-
-DEFINE  LAMBDA         1
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_SEGMENT :
-#
-# MBK      RDS layer 1                 RDS layer 2         
-# name     name TRANS DLR DWR OFFSET   name TRANS DLR DWR OFFSET  ...
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_SEGMENT
-
-  NWELL    RDS_NWELL  VW  0.0  0.0  0.0  ALL
-  NDIF     RDS_NDIF   VW  0.5  0.0  0.0  ALL
-  PDIF     RDS_PDIF   VW  0.5  0.0  0.0  ALL \
-           RDS_NWELL  VW  1.0  1.0  0.0  ALL
-  NTIE     RDS_NTIE   VW  0.5  0.0  0.0  ALL \
-           RDS_NWELL  VW  1.0  1.0  0.0  ALL
-  PTIE     RDS_PTIE   VW  0.5  0.0  0.0  ALL
-  NTRANS   RDS_POLY   VW  0.0  0.0  0.0  ALL \
-           RDS_NDIF  LCW -1.5  2.0  0.0  EXT \
-           RDS_NDIF  RCW -1.5  2.0  0.0  EXT \
-           RDS_NDIF   VW -1.5  4.0  0.0  DRC  
-  PTRANS   RDS_POLY   VW  0.0  0.0  0.0  ALL \
-           RDS_PDIF  LCW -1.5  2.0  0.0  EXT \
-           RDS_PDIF  RCW -1.5  2.0  0.0  EXT \
-           RDS_PDIF   VW -1.5  4.0  0.0  DRC \
-           RDS_NWELL  VW -1.0  5.0  0.0  ALL 
-  POLY     RDS_POLY   VW  0.5  0.0  0.0  ALL
-  ALU1     RDS_ALU1   VW  0.5  0.0  0.0  ALL
-  ALU2     RDS_ALU2   VW  1.0  0.0  0.0  ALL
-  ALU3     RDS_ALU3   VW  1.0  0.0  0.0  ALL
-  ALU4     RDS_ALU4   VW  1.0  0.0  0.0  ALL
-  ALU5     RDS_ALU5   VW  1.0  0.0  0.0  ALL 
-  ALU6     RDS_ALU6   VW  1.0  0.0  0.0  ALL 
-  TPOLY    RDS_TPOLY  VW  0.5  0.0  0.0  ALL
-  TALU1    RDS_TALU1  VW  0.5  0.0  0.0  ALL
-  TALU2    RDS_TALU2  VW  1.0  0.0  0.0  ALL
-  TALU3    RDS_TALU3  VW  1.0  0.0  0.0  ALL
-  TALU4    RDS_TALU4  VW  1.0  0.0  0.0  ALL
-  TALU5    RDS_TALU5  VW  1.0  0.0  0.0  ALL
-  TALU6    RDS_TALU6  VW  1.0  0.0  0.0  ALL
-
-END
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_CONNECTOR :
-#
-# MBK      RDS layer 
-# name     name     DER DWR 
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_CONNECTOR
-
-  POLY    RDS_POLY  .5  0  
-  ALU1    RDS_ALU1  .5  0  
-  ALU2    RDS_ALU2 1.0  0  
-  ALU3    RDS_ALU3 1.0  0  
-  ALU4    RDS_ALU4 1.0  0  
-  ALU5    RDS_ALU4 1.0  0  
-  ALU6    RDS_ALU4 1.0  0  
-
-END
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_REFERENCE :
-#
-# MBK ref    RDS layer 
-# name       name       width
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_REFERENCE
-
-  REF_REF    RDS_REF    1
-  REF_CON    RDS_VALU1  2  RDS_TVIA1 1  RDS_TALU2  2
-
-END
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_VIA1 :
-#
-# MBK via      RDS layer 1  RDS  layer 2  RDS  layer 3  RDS layer 4      
-# name         name  width  name   width  name   width  name  width  
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_VIA
-
-  CONT_BODY_P  RDS_ALU1 2 ALL  RDS_CONT 1 ALL  RDS_PTIE 3 ALL  
-  CONT_BODY_N  RDS_ALU1 2 ALL  RDS_CONT 1 ALL  RDS_NTIE 3 ALL  RDS_NWELL 4 ALL
-  CONT_DIF_N   RDS_ALU1 2 ALL  RDS_CONT 1 ALL  RDS_NDIF 3 ALL
-  CONT_DIF_P   RDS_ALU1 2 ALL  RDS_CONT 1 ALL  RDS_PDIF 3 ALL  RDS_NWELL 4 ALL
-  CONT_POLY    RDS_ALU1 2 ALL  RDS_CONT 1 ALL  RDS_POLY 3 ALL
-  CONT_VIA     RDS_ALU1 2 ALL  RDS_VIA1 1 ALL  RDS_ALU2 2 ALL
-  CONT_VIA2    RDS_ALU2 2 ALL  RDS_VIA2 1 ALL  RDS_ALU3 2 ALL
-  CONT_VIA3    RDS_ALU3 2 ALL  RDS_VIA3 1 ALL  RDS_ALU4 2 ALL
-  CONT_VIA4    RDS_ALU4 2 ALL  RDS_VIA4 1 ALL  RDS_ALU5 2 ALL
-  CONT_VIA5    RDS_ALU5 2 ALL  RDS_VIA5 1 ALL  RDS_ALU6 2 ALL
-  C_X_N        RDS_POLY 1 ALL  RDS_NDIF 5 ALL
-  C_X_P        RDS_POLY 1 ALL  RDS_PDIF 5 ALL  RDS_NWELL 6 ALL
-
-END
-
-##-------------------------------------------------------------------
-# TABLE LYNX_GRAPH :
-#
-# RDS layer   Rds layer 1   Rds layer 2    ...
-# name        name          name           ...
-##-------------------------------------------------------------------
-
-TABLE LYNX_GRAPH
-
-  RDS_NDIF  RDS_CONT RDS_NDIF
-  RDS_PDIF  RDS_CONT RDS_PDIF
-  RDS_NTIE  RDS_CONT RDS_NTIE
-  RDS_PTIE  RDS_CONT RDS_PTIE
-  RDS_POLY  RDS_CONT RDS_POLY 
-  RDS_CONT  RDS_PDIF RDS_NDIF RDS_POLY RDS_PTIE  RDS_NTIE RDS_ALU1 RDS_CONT
-  RDS_ALU1  RDS_CONT RDS_VIA1 RDS_ALU1 RDS_VALU1 RDS_ALU1
-  RDS_VALU1 RDS_CONT RDS_VIA1 RDS_ALU1 RDS_VALU1
-  RDS_VIA1  RDS_ALU1 RDS_ALU2 RDS_VIA1
-  RDS_VIA2  RDS_ALU2 RDS_ALU3 RDS_VIA2
-  RDS_VIA3  RDS_ALU3 RDS_ALU4 RDS_VIA3
-  RDS_VIA4  RDS_ALU4 RDS_ALU5 RDS_VIA4
-  RDS_VIA5  RDS_ALU5 RDS_ALU6 RDS_VIA5
-  RDS_ALU2  RDS_VIA1 RDS_VIA2 RDS_ALU2 
-  RDS_ALU3  RDS_VIA2 RDS_VIA3 RDS_ALU3
-  RDS_ALU4  RDS_VIA3 RDS_VIA4 RDS_ALU4 
-  RDS_ALU5  RDS_VIA4 RDS_VIA5 RDS_ALU5 
-  RDS_ALU6  RDS_VIA5          RDS_ALU6 
-
-END
-
-##-------------------------------------------------------------------
-# TABLE LYNX_CAPA : 
-#
-# RDS layer   Surface capacitance  Perimetric capacitance
-# name        piF / Micron^2       piF / Micron 
-##-------------------------------------------------------------------
-
-TABLE LYNX_CAPA
-
-  RDS_POLY    1.00e-04    1.00e-04
-  RDS_ALU1    0.50e-04    0.90e-04
-  RDS_ALU2    0.25e-04    0.95e-04
-  RDS_ALU3    0.25e-04    0.95e-04
-  RDS_ALU4    0.25e-04    0.95e-04
-  RDS_ALU5    0.25e-04    0.95e-04
-  RDS_ALU6    0.25e-04    0.95e-04
-
-END
-
-##-------------------------------------------------------------------
-# TABLE LYNX_RESISTOR :
-#
-# RDS layer   Surface resistor
-# name        Ohm / Micron^2 
-##-------------------------------------------------------------------
-
-TABLE LYNX_RESISTOR
-
-  RDS_POLY    50.0
-  RDS_ALU1     0.1
-  RDS_ALU2     0.05
-  RDS_ALU3     0.05
-  RDS_ALU4     0.05
-  RDS_ALU5     0.05
-  RDS_ALU6     0.05
-
-END
-
-##-------------------------------------------------------------------
-# TABLE LYNX_TRANSISTOR : 
-#
-# MBK layer  Transistor Type  MBK via
-# name       name             name
-##-------------------------------------------------------------------
-
-TABLE LYNX_TRANSISTOR
-
-  NTRANS  NTRANS  C_X_N   RDS_POLY   RDS_NDIF  RDS_NDIF
-  PTRANS  PTRANS  C_X_P   RDS_POLY   RDS_PDIF  RDS_PDIF
-
-END
-
-##-------------------------------------------------------------------
-# TABLE LYNX_DIFFUSION :
-#
-# RDS layer  RDS layer
-# name       name    
-##-------------------------------------------------------------------
-
-TABLE LYNX_DIFFUSION
-END
-
-##-------------------------------------------------------------------
-# TABLE S2R_OVERSIZE_DENOTCH :
-##-------------------------------------------------------------------
-
-TABLE S2R_OVERSIZE_DENOTCH 
-END
-
-##-------------------------------------------------------------------
-# TABLE S2R_BLOC_RING_WIDTH :
-##-------------------------------------------------------------------
-
-TABLE S2R_BLOC_RING_WIDTH
-END
-
-##-------------------------------------------------------------------
-# TABLE S2R_MINIMUM_LAYER_WIDTH :
-##-------------------------------------------------------------------
-
-TABLE S2R_MINIMUM_LAYER_WIDTH 
-
-  RDS_NWELL   4
-  RDS_PDIF    2
-  RDS_NTIE    2
-  RDS_PTIE    2
-  RDS_POLY    1
-  RDS_TPOLY   1
-  RDS_CONT    1
-  RDS_ALU1    1
-  RDS_TALU1   1
-  RDS_VIA1    1
-  RDS_ALU2    2
-  RDS_TALU2   2
-  RDS_VIA2    1
-  RDS_ALU3    2
-  RDS_TALU3   2
-  RDS_VIA3    1
-  RDS_ALU4    2
-  RDS_TALU4   2
-  RDS_VIA4    1
-  RDS_ALU5    2
-  RDS_TALU5   2
-  RDS_VIA5    1
-  RDS_ALU6    2
-  RDS_TALU6   2
-
-END
-
-##-------------------------------------------------------------------
-# TABLE CIF_LAYER :
-##-------------------------------------------------------------------
-
-TABLE CIF_LAYER
-
-  RDS_NWELL    LNWELL
-  RDS_NDIF     LNDIF
-  RDS_PDIF     LPDIF
-  RDS_NTIE     LNTIE
-  RDS_PTIE     LPTIE
-  RDS_POLY     LPOLY
-  RDS_TPOLY    LTPOLY
-  RDS_CONT     LCONT
-  RDS_ALU1     LALU1
-  RDS_VALU1    LVALU1
-  RDS_TALU1    LTALU1
-  RDS_VIA1     LVIA
-  RDS_TVIA1    LTVIA1
-  RDS_ALU2     LALU2
-  RDS_TALU2    LTALU2
-  RDS_VIA2     LVIA2
-  RDS_ALU3     LALU3
-  RDS_TALU3    LTALU3
-  RDS_VIA3     LVIA3
-  RDS_ALU4     LALU4
-  RDS_TALU4    LTALU4
-  RDS_VIA4     LVIA4
-  RDS_ALU5     LALU5
-  RDS_TALU5    LTALU5
-  RDS_VIA5     LVIA5
-  RDS_ALU6     LALU6
-  RDS_TALU6    LTALU6
-  RDS_REF      LREF
-
-END
-
-##-------------------------------------------------------------------
-# TABLE GDS_LAYER :
-##-------------------------------------------------------------------
-
-TABLE GDS_LAYER
-
-  RDS_NWELL    1
-  RDS_NDIF     3
-  RDS_PDIF     4
-  RDS_NTIE     5
-  RDS_PTIE     6
-  RDS_POLY     7
-  RDS_TPOLY    9
-  RDS_CONT    10
-  RDS_ALU1    11
-  RDS_VALU1   12
-  RDS_TALU1   13
-  RDS_VIA1    14
-  RDS_TVIA1   15
-  RDS_ALU2    16
-  RDS_TALU2   17
-  RDS_VIA2    18
-  RDS_ALU3    19
-  RDS_TALU3   20
-  RDS_VIA3    21
-  RDS_ALU4    22
-  RDS_TALU4   23
-  RDS_VIA4    25
-  RDS_ALU5    26
-  RDS_TALU5   27
-  RDS_VIA5    28
-  RDS_ALU6    29
-  RDS_TALU6   30
-  RDS_REF     24
-
-END
-
-##-------------------------------------------------------------------
-# TABLE S2R_POST_TREAT :
-##-------------------------------------------------------------------
-
-TABLE S2R_POST_TREAT
-
-END
-DRC_RULES
-
-layer RDS_NWELL 4.;
-layer RDS_NTIE 2.;
-layer RDS_PTIE 2.;
-layer RDS_NDIF 2.;
-layer RDS_PDIF 2.;
-layer RDS_CONT 1.;
-layer RDS_VIA1 1.;
-layer RDS_VIA2 1.;
-layer RDS_VIA3 1.;
-layer RDS_VIA4 1.;
-layer RDS_VIA5 1.;
-layer RDS_POLY 1.;
-layer RDS_ALU1 1.;
-layer RDS_ALU2 2.;
-layer RDS_ALU3 2.;
-layer RDS_ALU4 2.;
-layer RDS_ALU5 2.;
-layer RDS_ALU6 2.;
-layer RDS_USER0 1.;
-layer RDS_USER1 1.;
-layer RDS_USER2 1.;
-
-regles
-
-# Note : ``min'' is different from ``>=''. 
-# min is applied on polygons and >= is applied on rectangles.
-# There is the same difference between max and <=.
-# >= is faster than min, but min must be used where it is
-# required to consider polygons, for example distance of
-# two objects in the same layer 
-#
-# There is no rule to check NTIE and PDIF are included in NWELL
-# since this is necessarily true
-#----------------------------------------------------------- 
-
-# Check the NWELL shapes
-#-----------------------
-caracterise RDS_NWELL (
-  regle 1 : largeur >= 4. ;
-  regle 2 : longueur_inter min 4. ;
-  regle 3 : notch >= 12. ;
-);
-relation RDS_NWELL , RDS_NWELL (
-  regle 4 : distance axiale min 12. ;
-);
-
-# Check RDS_PTIE is really excluded outside NWELL
-#------------------------------------------------
-relation RDS_PTIE , RDS_NWELL (
-  regle 5 : distance axiale >= 7.5;
-  regle 6 : enveloppe longueur_inter < 0. ;
-  regle 7 : marge longueur_inter < 0. ;
-  regle 8 : croix longueur_inter < 0. ;
-  regle 9 : intersection longueur_inter < 0. ;
-  regle 10 : extension longueur_inter < 0. ;
-  regle 11 : inclusion longueur_inter < 0. ;
-);
-
-# Check RDS_NDIF is really excluded outside NWELL
-#------------------------------------------------
-relation RDS_NDIF , RDS_NWELL (
-  regle 12 : distance axiale >= 7.5;
-  regle 13 : enveloppe longueur_inter < 0. ;
-  regle 14 : marge longueur_inter < 0. ;
-  regle 15 : croix longueur_inter < 0. ;
-  regle 16 : intersection longueur_inter < 0. ;
-  regle 17 : extension longueur_inter < 0. ;
-  regle 18 : inclusion longueur_inter < 0. ;
-);
-
-# Check the RDS_PDIF shapes
-#--------------------------
-caracterise RDS_PDIF (
-  regle 19 : largeur >= 2. ;
-  regle 20 : longueur_inter min 2. ;
-  regle 21 : notch >= 2. ;
-);
-relation RDS_PDIF , RDS_PDIF (
-  regle 22 : distance axiale min 3. ;
-);
-
-# Check the RDS_NDIF shapes
-#--------------------------
-caracterise RDS_NDIF (
-  regle 23 : largeur >= 2. ;
-  regle 24 : longueur_inter min 2. ;
-  regle 25 : notch >= 2. ;
-);
-relation RDS_NDIF , RDS_NDIF (
-  regle 26 : distance axiale min 3. ;
-);
-
-# Check the RDS_PTIE shapes
-#--------------------------
-caracterise RDS_PTIE (
-  regle 27 : largeur >= 2. ;
-  regle 28 : longueur_inter min 2. ;
-  regle 29 : notch >= 2. ;
-);
-relation RDS_PTIE , RDS_PTIE (
-  regle 30 : distance axiale min 3. ;
-);
-
-# Check the RDS_NTIE shapes
-#--------------------------
-caracterise RDS_NTIE (
-  regle 31 : largeur >= 2. ;
-  regle 32 : longueur_inter min 2. ;
-  regle 33 : notch >= 2. ;
-);
-relation RDS_NTIE , RDS_NTIE (
-  regle 34 : distance axiale min 3. ;
-);
-
-define RDS_PDIF , RDS_PTIE union -> ANY_P_DIF;
-define RDS_NDIF , RDS_NTIE union -> ANY_N_DIF;
-
-# Check the ANY_N_DIF ANY_P_DIFF exclusion
-#--------------------------------------
-relation ANY_N_DIF , ANY_P_DIF (
-  regle 35 : distance axiale >= 3. ;
-  regle 36 : enveloppe longueur_inter < 0. ;
-  regle 37 : marge longueur_inter < 0. ;
-  regle 38 : croix longueur_inter < 0. ;
-  regle 39 : intersection longueur_inter < 0. ;
-  regle 40 : extension longueur_inter < 0. ;
-  regle 41 : inclusion longueur_inter < 0. ;
-);
-
-# Check RDS_POLY is distant from ANY_DIF
-#---------------------------------------
-relation RDS_POLY , ANY_P_DIF (
-  regle 42 : distance axiale >= 1. ;
-);
-relation RDS_POLY , ANY_N_DIF (
-  regle 43 : distance axiale >= 1. ;
-);
-
-undefine ANY_P_DIF;
-undefine ANY_N_DIF;
-
-define RDS_NDIF , RDS_PDIF union -> NP_DIF;
-define NP_DIF , RDS_POLY intersection -> CHANNEL;
-
-# Check the RDS_POLY shapes
-#--------------------------
-caracterise RDS_POLY (
-  regle 44 : largeur >= 1. ;
-  regle 45 : longueur_inter min 1. ;
-  regle 46 : notch >= 2. ;
-);
-relation RDS_POLY , RDS_POLY (
-  regle 47 : distance axiale min 2.;
-);
-
-# Check the CHANNEL shapes
-#--------------------------
-caracterise CHANNEL (
-  regle 48 : notch >= 3. ;
-);
-relation CHANNEL , CHANNEL (
-  regle 49 : distance axiale min 3.;
-);
-
-# Check the RDS_POLY distance
-#----------------------------
-relation RDS_POLY , RDS_POLY (
-  regle 50 : distance axiale min 2.;
-);
-
-undefine CHANNEL;
-
-define NP_DIF , RDS_CONT intersection -> CONT_DIFF;
-relation RDS_POLY , CONT_DIFF (
-  regle 79 : distance axiale >= 2. ;
-);
-
-undefine CONT_DIFF;
-undefine NP_DIF;
-
-
-# Check RDS_ALU1 shapes
-#----------------------
-caracterise RDS_ALU1 (
-  regle 51 : largeur >= 1. ;
-  regle 52 : longueur_inter min 1. ;
-  regle 53 : notch >= 3. ;
-);
-relation RDS_ALU1 , RDS_ALU1 (
-  regle 54 : distance axiale min 3. ;
-);
-
-# Check RDS_ALU2 shapes
-#----------------------
-caracterise RDS_ALU2 (
-  regle 55 : largeur >= 2. ;
-  regle 56 : longueur_inter min 2. ;
-  regle 57 : notch >= 3. ;
-);
-relation RDS_ALU2 , RDS_ALU2 (
-  regle 58 : distance axiale min 3. ;
-);
-
-# Check RDS_ALU3 shapes
-#----------------------
-caracterise RDS_ALU3 (
-  regle 59 : largeur >= 2. ;
-  regle 60 : longueur_inter min 2. ;
-  regle 61 : notch >= 3. ;
-);
-relation RDS_ALU3 , RDS_ALU3 (
-  regle 62 : distance axiale min 3. ;
-);
-
-# Check RDS_ALU4 shapes
-#----------------------
-caracterise RDS_ALU4 (
-  regle 63 : largeur >= 2. ;
-  regle 64 : longueur_inter min 2. ;
-  regle 65 : notch >= 3. ;
-);
-relation RDS_ALU4 , RDS_ALU4 (
-  regle 66 : distance axiale min 3. ;
-);
-
-# Check RDS_ALU5 shapes
-#----------------------
-caracterise RDS_ALU5 (
-  regle 80 : largeur >= 2. ;
-  regle 81 : longueur_inter min 2. ;
-  regle 82 : notch >= 8. ;
-);
-relation RDS_ALU5 , RDS_ALU5 (
-  regle 83 : distance axiale min 8. ;
-);
-
-# Check RDS_ALU6 shapes
-#----------------------
-caracterise RDS_ALU6 (
-  regle 84 : largeur >= 2. ;
-  regle 85 : longueur_inter min 2. ;
-  regle 86 : notch >= 12. ;
-);
-relation RDS_ALU6 , RDS_ALU6 (
-  regle 87 : distance axiale min 12. ;
-);
-
-# Check ANY_VIA layers, stacking are free
-#----------------------------------------
-relation RDS_CONT , RDS_CONT (
-  regle 67 : distance axiale >= 3. ;
-);
-relation RDS_VIA , RDS_VIA (
-  regle 68 : distance axiale >= 4. ;
-);
-relation RDS_VIA2 , RDS_VIA2 (
-  regle 69 : distance axiale >= 4. ;
-);
-relation RDS_VIA3 , RDS_VIA3 (
-  regle 70 : distance axiale >= 4. ;
-);
-relation RDS_VIA4 , RDS_VIA4 (
-  regle 88 : distance axiale >= 5. ;
-);
-relation RDS_VIA5 , RDS_VIA5 (
-  regle 89 : distance axiale >= 5. ;
-);
-caracterise RDS_CONT (
-  regle 71 : largeur >= 1. ;
-  regle 72 : longueur <= 1. ;
-);
-caracterise RDS_VIA (
-  regle 73 : largeur >= 1. ;
-  regle 74 : longueur <= 1. ;
-);
-caracterise RDS_VIA2 (
-  regle 75 : largeur >= 1. ;
-  regle 76 : longueur <= 1. ;
-);
-caracterise RDS_VIA3 (
-  regle 77 : largeur >= 1. ;
-  regle 78 : longueur <= 1. ;
-);
-caracterise RDS_VIA4 (
-  regle 90 : largeur >= 1. ;
-  regle 91 : longueur <= 1. ;
-);
-caracterise RDS_VIA5 (
-  regle 92 : largeur >= 1. ;
-  regle 93 : longueur <= 1. ;
-);
-
-fin regles
-DRC_COMMENT
-1 (RDS_NWELL) minimum width 4. 
-2 (RDS_NWELL) minimum width 4. 
-3 (RDS_NWELL) Manhatan distance min 12. 
-4 (RDS_NWELL,RDS_NWELL) Manhatan distance min 12. 
-5 (RDS_PTIE,RDS_NWELL) Manhatan distance min 7.5
-6 (RDS_PTIE,RDS_NWELL) must never been in contact
-7 (RDS_PTIE,RDS_NWELL) must never been in contact
-8 (RDS_PTIE,RDS_NWELL) must never been in contact
-9 (RDS_PTIE,RDS_NWELL) must never been in contact
-10 (RDS_PTIE,RDS_NWELL) must never been in contact
-11 (RDS_PTIE,RDS_NWELL) must never been in contact
-12 (RDS_NDIF,RDS_NWELL) Manhatan distance min 7.5
-13 (RDS_NDIF,RDS_NWELL) must never been in contact
-14 (RDS_NDIF,RDS_NWELL) must never been in contact
-15 (RDS_NDIF,RDS_NWELL) must never been in contact
-16 (RDS_NDIF,RDS_NWELL) must never been in contact
-17 (RDS_NDIF,RDS_NWELL) must never been in contact
-18 (RDS_NDIF,RDS_NWELL) must never been in contact
-19 (RDS_PDIF) minimum width 2. 
-20 (RDS_PDIF) minimum width 2. 
-21 (RDS_PDIF) Manhatan distance min 2. 
-22 (RDS_PDIF,RDS_PDIF) Manhatan distance min 3. 
-23 (RDS_NDIF) minimum width 2. 
-24 (RDS_NDIF) minimum width 2. 
-25 (RDS_NDIF) Manhatan distance min 2. 
-26 (RDS_NDIF,RDS_NDIF) Manhatan distance min 3. 
-27 (RDS_PTIE) minimum width 2. 
-28 (RDS_PTIE) minimum width 2. 
-29 (RDS_PTIE) Manhatan distance min 2. 
-30 (RDS_PTIE,RDS_PTIE) Manhatan distance min 3. 
-31 (RDS_NTIE) minimum width 2. 
-32 (RDS_NTIE) minimum width 2. 
-33 (RDS_NTIE) Manhatan distance min 2. 
-34 (RDS_NTIE,RDS_NTIE) Manhatan distance min 3. 
-35 (ANY_N_DIF,ANY_P_DIF) Manhatan distance min 3. 
-36 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-37 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-38 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-39 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-40 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-41 (ANY_N_DIF,ANY_P_DIF) must never been in contact
-42 (RDS_POLY,ANY_N_DIF) Manhatan distance min 1. 
-43 (RDS_POLY,ANY_P_DIF) Manhatan distance min 1. 
-44 (RDS_POLY) minimum width 1. 
-45 (RDS_POLY) minimum width 1. 
-46 (RDS_POLY) Manhatan distance min 2. 
-47 (RDS_POLY,RDS_POLY) Manhatan distance min 2.
-48 (CHANNEL) Manhatan distance min 3. 
-49 (CHANNEL,CHANNEL) Manhatan distance min 3.
-50 (RDS_POLY,RDS_POLY) Manhatan distance min 2.
-51 (RDS_ALU1) minimum width 1. 
-52 (RDS_ALU1) minimum width 1. 
-53 (RDS_ALU1) Manhatan distance min 3.
-54 (RDS_ALU1,RDS_ALU1) Manhatan distance min 3.
-55 (RDS_ALU2) minimum width 2. 
-56 (RDS_ALU2) minimum width 2. 
-57 (RDS_ALU2) Manhatan distance min 3. 
-58 (RDS_ALU2,RDS_ALU2) Manhatan distance min 3. 
-59 (RDS_ALU3) minimum width 2. 
-60 (RDS_ALU3) minimum width 2. 
-61 (RDS_ALU3) Manhatan distance min 3. 
-62 (RDS_ALU3,RDS_ALU3) Manhatan distance min 3. 
-63 (RDS_ALU4) minimum width 2. 
-64 (RDS_ALU4) minimum width 2. 
-65 (RDS_ALU4) Manhatan distance min 3. 
-66 (RDS_ALU4,RDS_ALU4) Manhatan distance min 3. 
-67 (RDS_CONT,RDS_CONT) Manhatan distance min 3. 
-68 (RDS_VIA,RDS_VIA) Manhatan distance min 4. 
-69 (RDS_VIA2,RDS_VIA2) Manhatan distance min 4. 
-70 (RDS_VIA3,RDS_VIA3) Manhatan distance min 4. 
-71 (RDS_CONT) minimum width 1. 
-72 (RDS_CONT) maximum length 1. 
-73 (RDS_VIA) minimum width 1. 
-74 (RDS_VIA) maximum length 1. 
-75 (RDS_VIA2) minimum width 1. 
-76 (RDS_VIA2) maximum length 1. 
-77 (RDS_VIA3) minimum width 1. 
-78 (RDS_VIA3) maximum length 1. 
-79 (RDS_POLY,CONT_DIFF) Manhatan distance min 2. 
-80 (RDS_ALU5) minimum width 2. 
-81 (RDS_ALU5) minimum width 2. 
-82 (RDS_ALU5) Manhatan distance min 8. 
-83 (RDS_ALU5,RDS_ALU5) Manhatan distance min 8. 
-84 (RDS_ALU6) minimum width 2. 
-85 (RDS_ALU6) minimum width 2. 
-86 (RDS_ALU6) Manhatan distance min 12. 
-87 (RDS_ALU6,RDS_ALU6) Manhatan distance min 12. 
-88 (RDS_VIA4,RDS_VIA4) Manhatan distance min 5. 
-89 (RDS_VIA5,RDS_VIA5) Manhatan distance min 5. 
-90 (RDS_VIA4) minimum width 1. 
-91 (RDS_VIA4) maximum length 1. 
-92 (RDS_VIA5) minimum width 1. 
-93 (RDS_VIA5) maximum length 1. 
-END_DRC_COMMENT
-END_DRC_RULES
diff --git a/alliance/share/etc/configure b/alliance/share/etc/configure
deleted file mode 100755
index 2335fb11..00000000
--- a/alliance/share/etc/configure
+++ /dev/null
@@ -1,4526 +0,0 @@
-#! /bin/sh
-
-# From configure.in Revision: 1.28 
-# Guess values for system-dependent variables and create Makefiles.
-# Generated automatically using autoconf version 2.13 
-# Copyright (C) 1992, 93, 94, 95, 96 Free Software Foundation, Inc.
-#
-# This configure script is free software; the Free Software Foundation
-# gives unlimited permission to copy, distribute and modify it.
-
-# Defaults:
-ac_help=
-ac_default_prefix=/usr/local
-# Any additions from configure.in:
-ac_default_prefix=/usr/local/alliance
-ac_help="$ac_help
-  --with-x                use the X Window System"
-
-# Initialize some variables set by options.
-# The variables have the same names as the options, with
-# dashes changed to underlines.
-build=NONE
-cache_file=./config.cache
-exec_prefix=NONE
-host=NONE
-no_create=
-nonopt=NONE
-no_recursion=
-prefix=NONE
-program_prefix=NONE
-program_suffix=NONE
-program_transform_name=s,x,x,
-silent=
-site=
-srcdir=
-target=NONE
-verbose=
-x_includes=NONE
-x_libraries=NONE
-bindir='${exec_prefix}/bin'
-sbindir='${exec_prefix}/sbin'
-libexecdir='${exec_prefix}/libexec'
-datadir='${prefix}/share'
-sysconfdir='${prefix}/etc'
-sharedstatedir='${prefix}/com'
-localstatedir='${prefix}/var'
-libdir='${exec_prefix}/lib'
-includedir='${prefix}/include'
-oldincludedir='/usr/include'
-infodir='${prefix}/info'
-mandir='${prefix}/man'
-
-# Initialize some other variables.
-subdirs=
-MFLAGS= MAKEFLAGS=
-SHELL=${CONFIG_SHELL-/bin/sh}
-# Maximum number of lines to put in a shell here document.
-ac_max_here_lines=12
-
-ac_prev=
-for ac_option
-do
-
-  # If the previous option needs an argument, assign it.
-  if test -n "$ac_prev"; then
-    eval "$ac_prev=\$ac_option"
-    ac_prev=
-    continue
-  fi
-
-  case "$ac_option" in
-  -*=*) ac_optarg=`echo "$ac_option" | sed 's/[-_a-zA-Z0-9]*=//'` ;;
-  *) ac_optarg= ;;
-  esac
-
-  # Accept the important Cygnus configure options, so we can diagnose typos.
-
-  case "$ac_option" in
-
-  -bindir | --bindir | --bindi | --bind | --bin | --bi)
-    ac_prev=bindir ;;
-  -bindir=* | --bindir=* | --bindi=* | --bind=* | --bin=* | --bi=*)
-    bindir="$ac_optarg" ;;
-
-  -build | --build | --buil | --bui | --bu)
-    ac_prev=build ;;
-  -build=* | --build=* | --buil=* | --bui=* | --bu=*)
-    build="$ac_optarg" ;;
-
-  -cache-file | --cache-file | --cache-fil | --cache-fi \
-  | --cache-f | --cache- | --cache | --cach | --cac | --ca | --c)
-    ac_prev=cache_file ;;
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-
-
-
-
-
-# Helps this script to run in bad configured env...
-
-PATH=/local/beny1/arnaud/bin:$PATH
-
-#PATH=$PATH:/bin:/usr/bin:/usr/local/bin:/labo/TeX/teTeX/bin:/labo/X11R6/bin:/labo/X11r5/bin:/labo/bin:/labo/gnu/bin:/sbin:/user/local/bin:/usr/X11/bin:/usr/X11R6/bin:/usr/andrew/bin:/usr/bin/X11:/usr/bin/games:/usr/bin:/usr/ccs/bin:/usr/dt/bin:/usr/etc:/usr/games:/usr/lib/teTeX/bin:/usr/local/bin:/usr/local/games:/usr/openwin/bin:/usr/sbin:/usr/ucb/bin:/usr/ucb:/usr/xpg4/bin
-
-#LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/usr/lib:/usr/local/lib:/labo/gnu/lib:/labo/X11R6/lib:/usr/lib/X11:/labo/X11r5/lib:/usr/X11R6.3/lib
-
-    
-# Which platform for Alliance CAD
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-echo "configure:543: checking for platform" >&5
-
-# WARNING : if changing this remember to do it on the 3 config files :
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-
-ALLIANCE_OS=Unknown
- 
-case `uname` in
-
-  Linux*) case `uname -r` in
-           1.*) ALLIANCE_OS=Linux_aout ;;
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-             *) ALLIANCE_OS=Linux  ;;
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-
-  SunOS*) case `uname -r` in
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-             *) ALLIANCE_OS=SunOS ;;
-          esac ;;
-
-  FreeBSD*)     ALLIANCE_OS=FreeBSD ;;
-
-  NetBSD*)      ALLIANCE_OS=NetBSD ;;
-
-  HP-UX*)       ALLIANCE_OS=HPUX ;;
-
-  OSF1*)        ALLIANCE_OS=OSF ;;
-
-  CYGWIN*)      ALLIANCE_OS=Cygwin ;;
-
-  *)            ALLIANCE_OS=Unknown ;;
-
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-
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-
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-
-
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-EOF
-# GNU make sometimes prints "make[1]: Entering...", which would confuse us.
-eval `${MAKE-make} -f conftestmake 2>/dev/null | grep temp=`
-if test -n "$ac_maketemp"; then
-  eval ac_cv_prog_make_${ac_make}_set=yes
-else
-  eval ac_cv_prog_make_${ac_make}_set=no
-fi
-rm -f conftestmake
-fi
-if eval "test \"`echo '$ac_cv_prog_make_'${ac_make}_set`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-  SET_MAKE=
-else
-  echo "$ac_t""no" 1>&6
-  SET_MAKE="MAKE=${MAKE-make}"
-fi
-
-
-if test "$program_suffix" = NONE ; then
-  if test "$ALLIANCE_OS" = Cygwin ; then
-      PROGRAM_SUFFIX=".exe"
-  else    
-      PROGRAM_SUFFIX=""
-  fi
-else    
-    PROGRAM_SUFFIX="$program_suffix"
-fi
-
-
-
-
-################################################################## Binaries
-echo "checking %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% Binaries" 1>&6
-echo "configure:626: checking %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% Binaries" >&5
-
-# AC_CANONICAL_SYSTEM
-
-# Set default value for CC and CFLAGS
-# -DALLIANCE_DISTRIB
-
-if test -z "$CFLAGS" ; then
-  CFLAGS="-O -D$ALLIANCE_OS"
-fi
-
-# Extract the first word of "gcc", so it can be a program name with args.
-set dummy gcc; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:640: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  if test -n "$CC"; then
-  ac_cv_prog_CC="$CC" # Let the user override the test.
-else
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_prog_CC="gcc"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-fi
-fi
-CC="$ac_cv_prog_CC"
-if test -n "$CC"; then
-  echo "$ac_t""$CC" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-if test -z "$CC"; then
-  # Extract the first word of "cc", so it can be a program name with args.
-set dummy cc; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:670: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  if test -n "$CC"; then
-  ac_cv_prog_CC="$CC" # Let the user override the test.
-else
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_prog_rejected=no
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      if test "$ac_dir/$ac_word" = "/usr/ucb/cc"; then
-        ac_prog_rejected=yes
-	continue
-      fi
-      ac_cv_prog_CC="cc"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-if test $ac_prog_rejected = yes; then
-  # We found a bogon in the path, so make sure we never use it.
-  set dummy $ac_cv_prog_CC
-  shift
-  if test $# -gt 0; then
-    # We chose a different compiler from the bogus one.
-    # However, it has the same basename, so the bogon will be chosen
-    # first if we set CC to just the basename; use the full file name.
-    shift
-    set dummy "$ac_dir/$ac_word" "$@"
-    shift
-    ac_cv_prog_CC="$@"
-  fi
-fi
-fi
-fi
-CC="$ac_cv_prog_CC"
-if test -n "$CC"; then
-  echo "$ac_t""$CC" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-  if test -z "$CC"; then
-    case "`uname -s`" in
-    *win32* | *WIN32*)
-      # Extract the first word of "cl", so it can be a program name with args.
-set dummy cl; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:721: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  if test -n "$CC"; then
-  ac_cv_prog_CC="$CC" # Let the user override the test.
-else
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_prog_CC="cl"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-fi
-fi
-CC="$ac_cv_prog_CC"
-if test -n "$CC"; then
-  echo "$ac_t""$CC" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
- ;;
-    esac
-  fi
-  test -z "$CC" && { echo "configure: error: no acceptable cc found in \$PATH" 1>&2; exit 1; }
-fi
-
-echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6
-echo "configure:753: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5
-
-ac_ext=c
-# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
-ac_cpp='$CPP $CPPFLAGS'
-ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5'
-ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5'
-cross_compiling=$ac_cv_prog_cc_cross
-
-cat > conftest.$ac_ext << EOF
-
-#line 764 "configure"
-#include "confdefs.h"
-
-main(){return(0);}
-EOF
-if { (eval echo configure:769: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  ac_cv_prog_cc_works=yes
-  # If we can't run a trivial program, we are probably using a cross compiler.
-  if (./conftest; exit) 2>/dev/null; then
-    ac_cv_prog_cc_cross=no
-  else
-    ac_cv_prog_cc_cross=yes
-  fi
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  ac_cv_prog_cc_works=no
-fi
-rm -fr conftest*
-ac_ext=c
-# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
-ac_cpp='$CPP $CPPFLAGS'
-ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5'
-ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5'
-cross_compiling=$ac_cv_prog_cc_cross
-
-echo "$ac_t""$ac_cv_prog_cc_works" 1>&6
-if test $ac_cv_prog_cc_works = no; then
-  { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; }
-fi
-echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6
-echo "configure:795: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5
-echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6
-cross_compiling=$ac_cv_prog_cc_cross
-
-echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6
-echo "configure:800: checking whether we are using GNU C" >&5
-if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.c <<EOF
-#ifdef __GNUC__
-  yes;
-#endif
-EOF
-if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:809: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then
-  ac_cv_prog_gcc=yes
-else
-  ac_cv_prog_gcc=no
-fi
-fi
-
-echo "$ac_t""$ac_cv_prog_gcc" 1>&6
-
-if test $ac_cv_prog_gcc = yes; then
-  GCC=yes
-else
-  GCC=
-fi
-
-ac_test_CFLAGS="${CFLAGS+set}"
-ac_save_CFLAGS="$CFLAGS"
-CFLAGS=
-echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6
-echo "configure:828: checking whether ${CC-cc} accepts -g" >&5
-if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  echo 'void f(){}' > conftest.c
-if test -z "`${CC-cc} -g -c conftest.c 2>&1`"; then
-  ac_cv_prog_cc_g=yes
-else
-  ac_cv_prog_cc_g=no
-fi
-rm -f conftest*
-
-fi
-
-echo "$ac_t""$ac_cv_prog_cc_g" 1>&6
-if test "$ac_test_CFLAGS" = set; then
-  CFLAGS="$ac_save_CFLAGS"
-elif test $ac_cv_prog_cc_g = yes; then
-  if test "$GCC" = yes; then
-    CFLAGS="-g -O2"
-  else
-    CFLAGS="-g"
-  fi
-else
-  if test "$GCC" = yes; then
-    CFLAGS="-O2"
-  else
-    CFLAGS=
-  fi
-fi
-
-
-# Extract the first word of "$CC", so it can be a program name with args.
-set dummy $CC; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:863: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_FULL_CC'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$FULL_CC" in
-  /*)
-  ac_cv_path_FULL_CC="$FULL_CC" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_FULL_CC="$FULL_CC" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_FULL_CC="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-FULL_CC="$ac_cv_path_FULL_CC"
-if test -n "$FULL_CC"; then
-  echo "$ac_t""$FULL_CC" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-
-
-echo $ac_n "checking how to run the C preprocessor""... $ac_c" 1>&6
-echo "configure:898: checking how to run the C preprocessor" >&5
-# On Suns, sometimes $CPP names a directory.
-if test -n "$CPP" && test -d "$CPP"; then
-  CPP=
-fi
-if test -z "$CPP"; then
-if eval "test \"`echo '$''{'ac_cv_prog_CPP'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-    # This must be in double quotes, not single quotes, because CPP may get
-  # substituted into the Makefile and "${CC-cc}" will confuse make.
-  CPP="${CC-cc} -E"
-  # On the NeXT, cc -E runs the code through the compiler's parser,
-  # not just through cpp.
-  cat > conftest.$ac_ext <<EOF
-#line 913 "configure"
-#include "confdefs.h"
-#include <assert.h>
-Syntax Error
-EOF
-ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:919: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
-ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
-if test -z "$ac_err"; then
-  :
-else
-  echo "$ac_err" >&5
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  CPP="${CC-cc} -E -traditional-cpp"
-  cat > conftest.$ac_ext <<EOF
-#line 930 "configure"
-#include "confdefs.h"
-#include <assert.h>
-Syntax Error
-EOF
-ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:936: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
-ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
-if test -z "$ac_err"; then
-  :
-else
-  echo "$ac_err" >&5
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  CPP="${CC-cc} -nologo -E"
-  cat > conftest.$ac_ext <<EOF
-#line 947 "configure"
-#include "confdefs.h"
-#include <assert.h>
-Syntax Error
-EOF
-ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:953: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
-ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
-if test -z "$ac_err"; then
-  :
-else
-  echo "$ac_err" >&5
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  CPP=/lib/cpp
-fi
-rm -f conftest*
-fi
-rm -f conftest*
-fi
-rm -f conftest*
-  ac_cv_prog_CPP="$CPP"
-fi
-  CPP="$ac_cv_prog_CPP"
-else
-  ac_cv_prog_CPP="$CPP"
-fi
-echo "$ac_t""$CPP" 1>&6
-
-
-if test "$GCC" = yes ; then
-    CFLAGS="-O2 -Wall -D$ALLIANCE_OS"
-fi
-
-
-# Set default value for MAKE
-# Extract the first word of "gmake", so it can be a program name with args.
-set dummy gmake; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:987: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_GMAKE'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$GMAKE" in
-  /*)
-  ac_cv_path_GMAKE="$GMAKE" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_GMAKE="$GMAKE" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_GMAKE="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-GMAKE="$ac_cv_path_GMAKE"
-if test -n "$GMAKE"; then
-  echo "$ac_t""$GMAKE" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-# Extract the first word of "make", so it can be a program name with args.
-set dummy make; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1022: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_MAKE'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$MAKE" in
-  /*)
-  ac_cv_path_MAKE="$MAKE" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_MAKE="$MAKE" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_MAKE="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-MAKE="$ac_cv_path_MAKE"
-if test -n "$MAKE"; then
-  echo "$ac_t""$MAKE" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-if test -n "$GMAKE" ; then
-    MAKE=$GMAKE
-fi
-
-ARFLAGS=
-
-
-# Looking for particular programs
-# Lex & Yacc
-# Do not use AC_PROG_YACC because our yacc grammar
-# is not compatible with bison...
-# AC_PATH_PROG(YACC, yacc)
-
-for ac_prog in 'bison -y' byacc
-do
-# Extract the first word of "$ac_prog", so it can be a program name with args.
-set dummy $ac_prog; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1072: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_prog_YACC'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  if test -n "$YACC"; then
-  ac_cv_prog_YACC="$YACC" # Let the user override the test.
-else
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_prog_YACC="$ac_prog"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-fi
-fi
-YACC="$ac_cv_prog_YACC"
-if test -n "$YACC"; then
-  echo "$ac_t""$YACC" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-test -n "$YACC" && break
-done
-test -n "$YACC" || YACC="yacc"
-
-# Extract the first word of "flex", so it can be a program name with args.
-set dummy flex; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1105: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_prog_LEX'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  if test -n "$LEX"; then
-  ac_cv_prog_LEX="$LEX" # Let the user override the test.
-else
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_prog_LEX="flex"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  test -z "$ac_cv_prog_LEX" && ac_cv_prog_LEX="lex"
-fi
-fi
-LEX="$ac_cv_prog_LEX"
-if test -n "$LEX"; then
-  echo "$ac_t""$LEX" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-if test -z "$LEXLIB"
-then
-  case "$LEX" in
-  flex*) ac_lib=fl ;;
-  *) ac_lib=l ;;
-  esac
-  echo $ac_n "checking for yywrap in -l$ac_lib""... $ac_c" 1>&6
-echo "configure:1139: checking for yywrap in -l$ac_lib" >&5
-ac_lib_var=`echo $ac_lib'_'yywrap | sed 'y%./+-%__p_%'`
-if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  ac_save_LIBS="$LIBS"
-LIBS="-l$ac_lib  $LIBS"
-cat > conftest.$ac_ext <<EOF
-#line 1147 "configure"
-#include "confdefs.h"
-/* Override any gcc2 internal prototype to avoid an error.  */
-/* We use char because int might match the return type of a gcc2
-    builtin and then its argument prototype would still apply.  */
-char yywrap();
-
-int main() {
-yywrap()
-; return 0; }
-EOF
-if { (eval echo configure:1158: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  eval "ac_cv_lib_$ac_lib_var=yes"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_lib_$ac_lib_var=no"
-fi
-rm -f conftest*
-LIBS="$ac_save_LIBS"
-
-fi
-if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-  LEXLIB="-l$ac_lib"
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-fi
-
-echo $ac_n "checking lex output file root""... $ac_c" 1>&6
-echo "configure:1181: checking lex output file root" >&5
-if eval "test \"`echo '$''{'ac_cv_prog_lex_root'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  # The minimal lex program is just a single line: %%.  But some broken lexes
-# (Solaris, I think it was) want two %% lines, so accommodate them.
-echo '%%
-%%' | $LEX
-if test -f lex.yy.c; then
-  ac_cv_prog_lex_root=lex.yy
-elif test -f lexyy.c; then
-  ac_cv_prog_lex_root=lexyy
-else
-  { echo "configure: error: cannot find output from $LEX; giving up" 1>&2; exit 1; }
-fi
-fi
-
-echo "$ac_t""$ac_cv_prog_lex_root" 1>&6
-LEX_OUTPUT_ROOT=$ac_cv_prog_lex_root
-
-echo $ac_n "checking whether yytext is a pointer""... $ac_c" 1>&6
-echo "configure:1202: checking whether yytext is a pointer" >&5
-if eval "test \"`echo '$''{'ac_cv_prog_lex_yytext_pointer'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  # POSIX says lex can declare yytext either as a pointer or an array; the
-# default is implementation-dependent. Figure out which it is, since
-# not all implementations provide the %pointer and %array declarations.
-ac_cv_prog_lex_yytext_pointer=no
-echo 'extern char *yytext;' >>$LEX_OUTPUT_ROOT.c
-ac_save_LIBS="$LIBS"
-LIBS="$LIBS $LEXLIB"
-cat > conftest.$ac_ext <<EOF
-#line 1214 "configure"
-#include "confdefs.h"
-`cat $LEX_OUTPUT_ROOT.c`
-int main() {
-
-; return 0; }
-EOF
-if { (eval echo configure:1221: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  ac_cv_prog_lex_yytext_pointer=yes
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-fi
-rm -f conftest*
-LIBS="$ac_save_LIBS"
-rm -f "${LEX_OUTPUT_ROOT}.c"
-
-fi
-
-echo "$ac_t""$ac_cv_prog_lex_yytext_pointer" 1>&6
-if test $ac_cv_prog_lex_yytext_pointer = yes; then
-  cat >> confdefs.h <<\EOF
-#define YYTEXT_POINTER 1
-EOF
-
-fi
-
-
-YACCFLAGS=`echo $YACC | awk '{for (i=2 ; i<=NF ; i++) printf("%s ", $i);printf ("\n"); }'`
-
-
-LEXFLAGS=`echo $LEX  | awk '{for (i=2 ; i<=NF ; i++) printf("%s ", $i);printf ("\n"); }'`
-
-
-# Extract the first word of "`echo $LEX | awk '{print $1}'`", so it can be a program name with args.
-set dummy `echo $LEX | awk '{print $1}'`; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1252: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_FULL_LEX'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$FULL_LEX" in
-  /*)
-  ac_cv_path_FULL_LEX="$FULL_LEX" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_FULL_LEX="$FULL_LEX" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_FULL_LEX="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-FULL_LEX="$ac_cv_path_FULL_LEX"
-if test -n "$FULL_LEX"; then
-  echo "$ac_t""$FULL_LEX" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-
-
-# Extract the first word of "`echo $YACC | awk '{print $1}'`", so it can be a program name with args.
-set dummy `echo $YACC | awk '{print $1}'`; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1289: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_FULL_YACC'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$FULL_YACC" in
-  /*)
-  ac_cv_path_FULL_YACC="$FULL_YACC" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_FULL_YACC="$FULL_YACC" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_FULL_YACC="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-FULL_YACC="$ac_cv_path_FULL_YACC"
-if test -n "$FULL_YACC"; then
-  echo "$ac_t""$FULL_YACC" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-
-
-# gcc-cpp has the wonderful -MM option to produce nicer dependencies
-test "$GCC" = yes && CPP_MM=M; 
-
-echo $ac_n "checking whether ln -s works""... $ac_c" 1>&6
-echo "configure:1327: checking whether ln -s works" >&5
-if eval "test \"`echo '$''{'ac_cv_prog_LN_S'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  rm -f conftestdata
-if ln -s X conftestdata 2>/dev/null
-then
-  rm -f conftestdata
-  ac_cv_prog_LN_S="ln -s"
-else
-  ac_cv_prog_LN_S=ln
-fi
-fi
-LN_S="$ac_cv_prog_LN_S"
-if test "$ac_cv_prog_LN_S" = "ln -s"; then
-  echo "$ac_t""yes" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-
-# Looking for ordinary programs
-
-# Extract the first word of "ar", so it can be a program name with args.
-set dummy ar; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1353: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_AR'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$AR" in
-  /*)
-  ac_cv_path_AR="$AR" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_AR="$AR" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_AR="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-AR="$ac_cv_path_AR"
-if test -n "$AR"; then
-  echo "$ac_t""$AR" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-
-ARFLAGS=rv 
-
-
-# Extract the first word of "autoconf", so it can be a program name with args.
-set dummy autoconf; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1392: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_AUTOCONF'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$AUTOCONF" in
-  /*)
-  ac_cv_path_AUTOCONF="$AUTOCONF" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_AUTOCONF="$AUTOCONF" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_AUTOCONF="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-AUTOCONF="$ac_cv_path_AUTOCONF"
-if test -n "$AUTOCONF"; then
-  echo "$ac_t""$AUTOCONF" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-# Extract the first word of "autoheader", so it can be a program name with args.
-set dummy autoheader; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1427: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_AUTOHEADER'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$AUTOHEADER" in
-  /*)
-  ac_cv_path_AUTOHEADER="$AUTOHEADER" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_AUTOHEADER="$AUTOHEADER" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_AUTOHEADER="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-AUTOHEADER="$ac_cv_path_AUTOHEADER"
-if test -n "$AUTOHEADER"; then
-  echo "$ac_t""$AUTOHEADER" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-# Extract the first word of "automake", so it can be a program name with args.
-set dummy automake; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1462: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_AUTOMAKE'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$AUTOMAKE" in
-  /*)
-  ac_cv_path_AUTOMAKE="$AUTOMAKE" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_AUTOMAKE="$AUTOMAKE" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_AUTOMAKE="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-AUTOMAKE="$ac_cv_path_AUTOMAKE"
-if test -n "$AUTOMAKE"; then
-  echo "$ac_t""$AUTOMAKE" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-
-# Extract the first word of "gawk", so it can be a program name with args.
-set dummy gawk; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1498: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_GAWK'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$GAWK" in
-  /*)
-  ac_cv_path_GAWK="$GAWK" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_GAWK="$GAWK" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_GAWK="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-GAWK="$ac_cv_path_GAWK"
-if test -n "$GAWK"; then
-  echo "$ac_t""$GAWK" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-# Extract the first word of "awk", so it can be a program name with args.
-set dummy awk; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1533: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_AWK'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$AWK" in
-  /*)
-  ac_cv_path_AWK="$AWK" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_AWK="$AWK" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_AWK="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-AWK="$ac_cv_path_AWK"
-if test -n "$AWK"; then
-  echo "$ac_t""$AWK" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-if test -n "$GAWK" ; then
-    AWK=$GAWK
-fi
-
-# Extract the first word of "chmod", so it can be a program name with args.
-set dummy chmod; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1572: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_CHMOD'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$CHMOD" in
-  /*)
-  ac_cv_path_CHMOD="$CHMOD" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_CHMOD="$CHMOD" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_CHMOD="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-CHMOD="$ac_cv_path_CHMOD"
-if test -n "$CHMOD"; then
-  echo "$ac_t""$CHMOD" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-# Extract the first word of "cp", so it can be a program name with args.
-set dummy cp; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1607: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_CP'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$CP" in
-  /*)
-  ac_cv_path_CP="$CP" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_CP="$CP" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_CP="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-CP="$ac_cv_path_CP"
-if test -n "$CP"; then
-  echo "$ac_t""$CP" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-# Extract the first word of "cat", so it can be a program name with args.
-set dummy cat; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1642: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_CAT'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$CAT" in
-  /*)
-  ac_cv_path_CAT="$CAT" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_CAT="$CAT" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_CAT="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-CAT="$ac_cv_path_CAT"
-if test -n "$CAT"; then
-  echo "$ac_t""$CAT" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-# Extract the first word of "csh", so it can be a program name with args.
-set dummy csh; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1677: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_CSH'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$CSH" in
-  /*)
-  ac_cv_path_CSH="$CSH" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_CSH="$CSH" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_CSH="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-CSH="$ac_cv_path_CSH"
-if test -n "$CSH"; then
-  echo "$ac_t""$CSH" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-# Extract the first word of "cut", so it can be a program name with args.
-set dummy cut; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1712: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_CUT'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$CUT" in
-  /*)
-  ac_cv_path_CUT="$CUT" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_CUT="$CUT" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_CUT="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-CUT="$ac_cv_path_CUT"
-if test -n "$CUT"; then
-  echo "$ac_t""$CUT" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-# Extract the first word of "echo", so it can be a program name with args.
-set dummy echo; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1747: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_ECHO'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$ECHO" in
-  /*)
-  ac_cv_path_ECHO="$ECHO" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_ECHO="$ECHO" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_ECHO="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-ECHO="$ac_cv_path_ECHO"
-if test -n "$ECHO"; then
-  echo "$ac_t""$ECHO" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-# Extract the first word of "false", so it can be a program name with args.
-set dummy false; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1782: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_FALSE'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$FALSE" in
-  /*)
-  ac_cv_path_FALSE="$FALSE" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_FALSE="$FALSE" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_FALSE="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-FALSE="$ac_cv_path_FALSE"
-if test -n "$FALSE"; then
-  echo "$ac_t""$FALSE" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-# Extract the first word of "find", so it can be a program name with args.
-set dummy find; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1817: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_FIND'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$FIND" in
-  /*)
-  ac_cv_path_FIND="$FIND" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_FIND="$FIND" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_FIND="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-FIND="$ac_cv_path_FIND"
-if test -n "$FIND"; then
-  echo "$ac_t""$FIND" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-# Extract the first word of "grep", so it can be a program name with args.
-set dummy grep; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1852: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_GREP'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$GREP" in
-  /*)
-  ac_cv_path_GREP="$GREP" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_GREP="$GREP" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_GREP="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-GREP="$ac_cv_path_GREP"
-if test -n "$GREP"; then
-  echo "$ac_t""$GREP" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-# Extract the first word of "hostname", so it can be a program name with args.
-set dummy hostname; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1887: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_HOSTNAME'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$HOSTNAME" in
-  /*)
-  ac_cv_path_HOSTNAME="$HOSTNAME" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_HOSTNAME="$HOSTNAME" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_HOSTNAME="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-HOSTNAME="$ac_cv_path_HOSTNAME"
-if test -n "$HOSTNAME"; then
-  echo "$ac_t""$HOSTNAME" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-# Extract the first word of "ld", so it can be a program name with args.
-set dummy ld; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1922: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_LD'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$LD" in
-  /*)
-  ac_cv_path_LD="$LD" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_LD="$LD" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_LD="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-LD="$ac_cv_path_LD"
-if test -n "$LD"; then
-  echo "$ac_t""$LD" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-# Extract the first word of "lndir", so it can be a program name with args.
-set dummy lndir; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1957: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_LNDIR'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$LNDIR" in
-  /*)
-  ac_cv_path_LNDIR="$LNDIR" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_LNDIR="$LNDIR" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_LNDIR="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-LNDIR="$ac_cv_path_LNDIR"
-if test -n "$LNDIR"; then
-  echo "$ac_t""$LNDIR" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-# Extract the first word of "ls", so it can be a program name with args.
-set dummy ls; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1992: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_LS'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$LS" in
-  /*)
-  ac_cv_path_LS="$LS" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_LS="$LS" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_LS="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-LS="$ac_cv_path_LS"
-if test -n "$LS"; then
-  echo "$ac_t""$LS" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-# Extract the first word of "mkdir", so it can be a program name with args.
-set dummy mkdir; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2027: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_MKDIR'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$MKDIR" in
-  /*)
-  ac_cv_path_MKDIR="$MKDIR" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_MKDIR="$MKDIR" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_MKDIR="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-MKDIR="$ac_cv_path_MKDIR"
-if test -n "$MKDIR"; then
-  echo "$ac_t""$MKDIR" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-# Extract the first word of "mv", so it can be a program name with args.
-set dummy mv; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2062: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_MV'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$MV" in
-  /*)
-  ac_cv_path_MV="$MV" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_MV="$MV" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_MV="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-MV="$ac_cv_path_MV"
-if test -n "$MV"; then
-  echo "$ac_t""$MV" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-# Extract the first word of "perl", so it can be a program name with args.
-set dummy perl; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2097: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_PERL'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$PERL" in
-  /*)
-  ac_cv_path_PERL="$PERL" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_PERL="$PERL" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_PERL="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-PERL="$ac_cv_path_PERL"
-if test -n "$PERL"; then
-  echo "$ac_t""$PERL" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-# Extract the first word of "pwd", so it can be a program name with args.
-set dummy pwd; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2132: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_PWDBIN'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$PWDBIN" in
-  /*)
-  ac_cv_path_PWDBIN="$PWDBIN" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_PWDBIN="$PWDBIN" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_PWDBIN="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-PWDBIN="$ac_cv_path_PWDBIN"
-if test -n "$PWDBIN"; then
-  echo "$ac_t""$PWDBIN" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-# Extract the first word of "ranlib", so it can be a program name with args.
-set dummy ranlib; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2167: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_RANLIB'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$RANLIB" in
-  /*)
-  ac_cv_path_RANLIB="$RANLIB" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_RANLIB="$RANLIB" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_RANLIB="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-RANLIB="$ac_cv_path_RANLIB"
-if test -n "$RANLIB"; then
-  echo "$ac_t""$RANLIB" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-# Extract the first word of "rm", so it can be a program name with args.
-set dummy rm; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2202: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_RM'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$RM" in
-  /*)
-  ac_cv_path_RM="$RM" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_RM="$RM" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_RM="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-RM="$ac_cv_path_RM"
-if test -n "$RM"; then
-  echo "$ac_t""$RM" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-# Extract the first word of "sed", so it can be a program name with args.
-set dummy sed; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2237: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_SED'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$SED" in
-  /*)
-  ac_cv_path_SED="$SED" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_SED="$SED" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_SED="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-SED="$ac_cv_path_SED"
-if test -n "$SED"; then
-  echo "$ac_t""$SED" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-
-# Extract the first word of "sh", so it can be a program name with args.
-set dummy sh; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2273: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_SH'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$SH" in
-  /*)
-  ac_cv_path_SH="$SH" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_SH="$SH" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_SH="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-SH="$ac_cv_path_SH"
-if test -n "$SH"; then
-  echo "$ac_t""$SH" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-if test "$SH" != sh ; then
-    SHELL=$SH
-else
-    SHELL=/bin/sh
-fi
-
-
-# Extract the first word of "strip", so it can be a program name with args.
-set dummy strip; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2315: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_STRIP'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$STRIP" in
-  /*)
-  ac_cv_path_STRIP="$STRIP" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_STRIP="$STRIP" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_STRIP="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-STRIP="$ac_cv_path_STRIP"
-if test -n "$STRIP"; then
-  echo "$ac_t""$STRIP" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-# Extract the first word of "test", so it can be a program name with args.
-set dummy test; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2350: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_TEST'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$TEST" in
-  /*)
-  ac_cv_path_TEST="$TEST" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_TEST="$TEST" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_TEST="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-TEST="$ac_cv_path_TEST"
-if test -n "$TEST"; then
-  echo "$ac_t""$TEST" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-# Extract the first word of "touch", so it can be a program name with args.
-set dummy touch; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2385: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_TOUCH'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$TOUCH" in
-  /*)
-  ac_cv_path_TOUCH="$TOUCH" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_TOUCH="$TOUCH" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_TOUCH="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-TOUCH="$ac_cv_path_TOUCH"
-if test -n "$TOUCH"; then
-  echo "$ac_t""$TOUCH" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-# Extract the first word of "tr", so it can be a program name with args.
-set dummy tr; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2420: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_TR'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$TR" in
-  /*)
-  ac_cv_path_TR="$TR" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_TR="$TR" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_TR="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-TR="$ac_cv_path_TR"
-if test -n "$TR"; then
-  echo "$ac_t""$TR" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-# Extract the first word of "true", so it can be a program name with args.
-set dummy true; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2455: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_TRUE'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$TRUE" in
-  /*)
-  ac_cv_path_TRUE="$TRUE" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_TRUE="$TRUE" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_TRUE="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-TRUE="$ac_cv_path_TRUE"
-if test -n "$TRUE"; then
-  echo "$ac_t""$TRUE" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-# Extract the first word of "wc", so it can be a program name with args.
-set dummy wc; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2490: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_WC'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$WC" in
-  /*)
-  ac_cv_path_WC="$WC" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_WC="$WC" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do 
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_WC="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
-fi
-WC="$ac_cv_path_WC"
-if test -n "$WC"; then
-  echo "$ac_t""$WC" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-
-
-# SKIPTEST
-# if false; then
-    
-# Check that all the utilities are present
-
-# All but makeinfo, automake, autoconf, autoheader, zsh
-if $TEST -z "$AR" \
-   -o -z "$AWK" \
-   -o -z "$CAT" \
-   -o -z "$CHMOD" \
-   -o -z "$CP" \
-   -o -z "$CUT" \
-   -o -z "$ECHO" \
-   -o -z "$FALSE" \
-   -o -z "$FIND" \
-   -o -z "$GREP" \
-   -o -z "$HOSTNAME" \
-   -o -z "$LD" \
-   -o -z "$LS" \
-   -o -z "$MKDIR" \
-   -o -z "$MV" \
-   -o -z "$PERL" \
-   -o -z "$PWDBIN" \
-   -o -z "$RM" \
-   -o -z "$SED" \
-   -o -z "$STRIP" \
-   -o -z "$TEST" \
-   -o -z "$TOUCH" \
-   -o -z "$TR" \
-   -o -z "$TRUE" \
-   -o -z "$WC" 
-then
-  echo "configure: warning: please install the above utilities that are not present" 1>&2
-fi
-
-if test "$ALLIANCE_OS" = Cygwin ; then
-    STRIP="echo"
-fi
-
-
-################################################################## Libraries...
-echo "checking %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%  Headers and Libraries..." 1>&6
-echo "configure:2566: checking %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%  Headers and Libraries..." >&5
-# Check that Xpm is installed
-# ($TRUE is used to avoid inclusion of -lXpm in LIBS)
-#AC_CHECK_LIB(Xpm, XpmReadFileToImage, $TRUE,
-#  AC_MSG_ERROR([please install Xpm]))
-
-# Check that xforms is installed
-#AC_CHECK_LIB(xforms, fl_init_font, $TRUE,
-#  AC_MSG_ERROR([please install xforms]))
-
-
-if test "$ALLIANCE_OS" = Solaris ; then
-    x_includes=/usr/openwin/include
-    x_libraries=/usr/openwin/lib
-fi
-
-# If we find X, set shell vars x_includes and x_libraries to the
-# paths, otherwise set no_x=yes.
-# Uses ac_ vars as temps to allow command line to override cache and checks.
-# --without-x overrides everything else, but does not touch the cache.
-echo $ac_n "checking for X""... $ac_c" 1>&6
-echo "configure:2587: checking for X" >&5
-
-# Check whether --with-x or --without-x was given.
-if test "${with_x+set}" = set; then
-  withval="$with_x"
-  :
-fi
-
-# $have_x is `yes', `no', `disabled', or empty when we do not yet know.
-if test "x$with_x" = xno; then
-  # The user explicitly disabled X.
-  have_x=disabled
-else
-  if test "x$x_includes" != xNONE && test "x$x_libraries" != xNONE; then
-    # Both variables are already set.
-    have_x=yes
-  else
-if eval "test \"`echo '$''{'ac_cv_have_x'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  # One or both of the vars are not set, and there is no cached value.
-ac_x_includes=NO ac_x_libraries=NO
-rm -fr conftestdir
-if mkdir conftestdir; then
-  cd conftestdir
-  # Make sure to not put "make" in the Imakefile rules, since we grep it out.
-  cat > Imakefile <<'EOF'
-acfindx:
-	@echo 'ac_im_incroot="${INCROOT}"; ac_im_usrlibdir="${USRLIBDIR}"; ac_im_libdir="${LIBDIR}"'
-EOF
-  if (xmkmf) >/dev/null 2>/dev/null && test -f Makefile; then
-    # GNU make sometimes prints "make[1]: Entering...", which would confuse us.
-    eval `${MAKE-make} acfindx 2>/dev/null | grep -v make`
-    # Open Windows xmkmf reportedly sets LIBDIR instead of USRLIBDIR.
-    for ac_extension in a so sl; do
-      if test ! -f $ac_im_usrlibdir/libX11.$ac_extension &&
-        test -f $ac_im_libdir/libX11.$ac_extension; then
-        ac_im_usrlibdir=$ac_im_libdir; break
-      fi
-    done
-    # Screen out bogus values from the imake configuration.  They are
-    # bogus both because they are the default anyway, and because
-    # using them would break gcc on systems where it needs fixed includes.
-    case "$ac_im_incroot" in
-	/usr/include) ;;
-	*) test -f "$ac_im_incroot/X11/Xos.h" && ac_x_includes="$ac_im_incroot" ;;
-    esac
-    case "$ac_im_usrlibdir" in
-	/usr/lib | /lib) ;;
-	*) test -d "$ac_im_usrlibdir" && ac_x_libraries="$ac_im_usrlibdir" ;;
-    esac
-  fi
-  cd ..
-  rm -fr conftestdir
-fi
-
-if test "$ac_x_includes" = NO; then
-  # Guess where to find include files, by looking for this one X11 .h file.
-  test -z "$x_direct_test_include" && x_direct_test_include=X11/Intrinsic.h
-
-  # First, try using that file with no special directory specified.
-cat > conftest.$ac_ext <<EOF
-#line 2649 "configure"
-#include "confdefs.h"
-#include <$x_direct_test_include>
-EOF
-ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:2654: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
-ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
-if test -z "$ac_err"; then
-  rm -rf conftest*
-  # We can compile using X headers with no special include directory.
-ac_x_includes=
-else
-  echo "$ac_err" >&5
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  # Look for the header file in a standard set of common directories.
-# Check X11 before X11Rn because it is often a symlink to the current release.
-  for ac_dir in               \
-    /usr/X11/include          \
-    /usr/X11R6/include        \
-    /usr/X11R5/include        \
-    /usr/X11R4/include        \
-                              \
-    /usr/include/X11          \
-    /usr/include/X11R6        \
-    /usr/include/X11R5        \
-    /usr/include/X11R4        \
-                              \
-    /usr/local/X11/include    \
-    /usr/local/X11R6/include  \
-    /usr/local/X11R5/include  \
-    /usr/local/X11R4/include  \
-                              \
-    /usr/local/include/X11    \
-    /usr/local/include/X11R6  \
-    /usr/local/include/X11R5  \
-    /usr/local/include/X11R4  \
-                              \
-    /usr/X386/include         \
-    /usr/x386/include         \
-    /usr/XFree86/include/X11  \
-                              \
-    /usr/include              \
-    /usr/local/include        \
-    /usr/unsupported/include  \
-    /usr/athena/include       \
-    /usr/local/x11r5/include  \
-    /usr/lpp/Xamples/include  \
-                              \
-    /usr/openwin/include      \
-    /usr/openwin/share/include \
-    ; \
-  do
-    if test -r "$ac_dir/$x_direct_test_include"; then
-      ac_x_includes=$ac_dir
-      break
-    fi
-  done
-fi
-rm -f conftest*
-fi # $ac_x_includes = NO
-
-if test "$ac_x_libraries" = NO; then
-  # Check for the libraries.
-
-  test -z "$x_direct_test_library" && x_direct_test_library=Xt
-  test -z "$x_direct_test_function" && x_direct_test_function=XtMalloc
-
-  # See if we find them without any special options.
-  # Don't add to $LIBS permanently.
-  ac_save_LIBS="$LIBS"
-  LIBS="-l$x_direct_test_library $LIBS"
-cat > conftest.$ac_ext <<EOF
-#line 2723 "configure"
-#include "confdefs.h"
-
-int main() {
-${x_direct_test_function}()
-; return 0; }
-EOF
-if { (eval echo configure:2730: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  LIBS="$ac_save_LIBS"
-# We can link X programs with no special library path.
-ac_x_libraries=
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  LIBS="$ac_save_LIBS"
-# First see if replacing the include by lib works.
-# Check X11 before X11Rn because it is often a symlink to the current release.
-for ac_dir in `echo "$ac_x_includes" | sed s/include/lib/` \
-    /usr/X11/lib          \
-    /usr/X11R6/lib        \
-    /usr/X11R5/lib        \
-    /usr/X11R4/lib        \
-                          \
-    /usr/lib/X11          \
-    /usr/lib/X11R6        \
-    /usr/lib/X11R5        \
-    /usr/lib/X11R4        \
-                          \
-    /usr/local/X11/lib    \
-    /usr/local/X11R6/lib  \
-    /usr/local/X11R5/lib  \
-    /usr/local/X11R4/lib  \
-                          \
-    /usr/local/lib/X11    \
-    /usr/local/lib/X11R6  \
-    /usr/local/lib/X11R5  \
-    /usr/local/lib/X11R4  \
-                          \
-    /usr/X386/lib         \
-    /usr/x386/lib         \
-    /usr/XFree86/lib/X11  \
-                          \
-    /usr/lib              \
-    /usr/local/lib        \
-    /usr/unsupported/lib  \
-    /usr/athena/lib       \
-    /usr/local/x11r5/lib  \
-    /usr/lpp/Xamples/lib  \
-    /lib/usr/lib/X11	  \
-                          \
-    /usr/openwin/lib      \
-    /usr/openwin/share/lib \
-    ; \
-do
-  for ac_extension in a so sl; do
-    if test -r $ac_dir/lib${x_direct_test_library}.$ac_extension; then
-      ac_x_libraries=$ac_dir
-      break 2
-    fi
-  done
-done
-fi
-rm -f conftest*
-fi # $ac_x_libraries = NO
-
-if test "$ac_x_includes" = NO || test "$ac_x_libraries" = NO; then
-  # Didn't find X anywhere.  Cache the known absence of X.
-  ac_cv_have_x="have_x=no"
-else
-  # Record where we found X for the cache.
-  ac_cv_have_x="have_x=yes \
-	        ac_x_includes=$ac_x_includes ac_x_libraries=$ac_x_libraries"
-fi
-fi
-  fi
-  eval "$ac_cv_have_x"
-fi # $with_x != no
-
-if test "$have_x" != yes; then
-  echo "$ac_t""$have_x" 1>&6
-  no_x=yes
-else
-  # If each of the values was on the command line, it overrides each guess.
-  test "x$x_includes" = xNONE && x_includes=$ac_x_includes
-  test "x$x_libraries" = xNONE && x_libraries=$ac_x_libraries
-  # Update the cache value to reflect the command line values.
-  ac_cv_have_x="have_x=yes \
-		ac_x_includes=$x_includes ac_x_libraries=$x_libraries"
-  echo "$ac_t""libraries $x_libraries, headers $x_includes" 1>&6
-fi
-
-if test "$no_x" = yes; then
-  # Not all programs may use this symbol, but it does not hurt to define it.
-  cat >> confdefs.h <<\EOF
-#define X_DISPLAY_MISSING 1
-EOF
-
-  X_CFLAGS= X_PRE_LIBS= X_LIBS= X_EXTRA_LIBS=
-else
-  if test -n "$x_includes"; then
-    X_CFLAGS="$X_CFLAGS -I$x_includes"
-  fi
-
-  # It would also be nice to do this for all -L options, not just this one.
-  if test -n "$x_libraries"; then
-    X_LIBS="$X_LIBS -L$x_libraries"
-    # For Solaris; some versions of Sun CC require a space after -R and
-    # others require no space.  Words are not sufficient . . . .
-    case "`(uname -sr) 2>/dev/null`" in
-    "SunOS 5"*)
-      echo $ac_n "checking whether -R must be followed by a space""... $ac_c" 1>&6
-echo "configure:2836: checking whether -R must be followed by a space" >&5
-      ac_xsave_LIBS="$LIBS"; LIBS="$LIBS -R$x_libraries"
-      cat > conftest.$ac_ext <<EOF
-#line 2839 "configure"
-#include "confdefs.h"
-
-int main() {
-
-; return 0; }
-EOF
-if { (eval echo configure:2846: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  ac_R_nospace=yes
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  ac_R_nospace=no
-fi
-rm -f conftest*
-      if test $ac_R_nospace = yes; then
-	echo "$ac_t""no" 1>&6
-	X_LIBS="$X_LIBS -R$x_libraries"
-      else
-	LIBS="$ac_xsave_LIBS -R $x_libraries"
-	cat > conftest.$ac_ext <<EOF
-#line 2862 "configure"
-#include "confdefs.h"
-
-int main() {
-
-; return 0; }
-EOF
-if { (eval echo configure:2869: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  ac_R_space=yes
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  ac_R_space=no
-fi
-rm -f conftest*
-	if test $ac_R_space = yes; then
-	  echo "$ac_t""yes" 1>&6
-	  X_LIBS="$X_LIBS -R $x_libraries"
-	else
-	  echo "$ac_t""neither works" 1>&6
-	fi
-      fi
-      LIBS="$ac_xsave_LIBS"
-    esac
-  fi
-
-  # Check for system-dependent libraries X programs must link with.
-  # Do this before checking for the system-independent R6 libraries
-  # (-lICE), since we may need -lsocket or whatever for X linking.
-
-  if test "$ISC" = yes; then
-    X_EXTRA_LIBS="$X_EXTRA_LIBS -lnsl_s -linet"
-  else
-    # Martyn.Johnson@cl.cam.ac.uk says this is needed for Ultrix, if the X
-    # libraries were built with DECnet support.  And karl@cs.umb.edu says
-    # the Alpha needs dnet_stub (dnet does not exist).
-    echo $ac_n "checking for dnet_ntoa in -ldnet""... $ac_c" 1>&6
-echo "configure:2901: checking for dnet_ntoa in -ldnet" >&5
-ac_lib_var=`echo dnet'_'dnet_ntoa | sed 'y%./+-%__p_%'`
-if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  ac_save_LIBS="$LIBS"
-LIBS="-ldnet  $LIBS"
-cat > conftest.$ac_ext <<EOF
-#line 2909 "configure"
-#include "confdefs.h"
-/* Override any gcc2 internal prototype to avoid an error.  */
-/* We use char because int might match the return type of a gcc2
-    builtin and then its argument prototype would still apply.  */
-char dnet_ntoa();
-
-int main() {
-dnet_ntoa()
-; return 0; }
-EOF
-if { (eval echo configure:2920: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  eval "ac_cv_lib_$ac_lib_var=yes"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_lib_$ac_lib_var=no"
-fi
-rm -f conftest*
-LIBS="$ac_save_LIBS"
-
-fi
-if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-  X_EXTRA_LIBS="$X_EXTRA_LIBS -ldnet"
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-    if test $ac_cv_lib_dnet_dnet_ntoa = no; then
-      echo $ac_n "checking for dnet_ntoa in -ldnet_stub""... $ac_c" 1>&6
-echo "configure:2942: checking for dnet_ntoa in -ldnet_stub" >&5
-ac_lib_var=`echo dnet_stub'_'dnet_ntoa | sed 'y%./+-%__p_%'`
-if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  ac_save_LIBS="$LIBS"
-LIBS="-ldnet_stub  $LIBS"
-cat > conftest.$ac_ext <<EOF
-#line 2950 "configure"
-#include "confdefs.h"
-/* Override any gcc2 internal prototype to avoid an error.  */
-/* We use char because int might match the return type of a gcc2
-    builtin and then its argument prototype would still apply.  */
-char dnet_ntoa();
-
-int main() {
-dnet_ntoa()
-; return 0; }
-EOF
-if { (eval echo configure:2961: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  eval "ac_cv_lib_$ac_lib_var=yes"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_lib_$ac_lib_var=no"
-fi
-rm -f conftest*
-LIBS="$ac_save_LIBS"
-
-fi
-if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-  X_EXTRA_LIBS="$X_EXTRA_LIBS -ldnet_stub"
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-    fi
-
-    # msh@cis.ufl.edu says -lnsl (and -lsocket) are needed for his 386/AT,
-    # to get the SysV transport functions.
-    # chad@anasazi.com says the Pyramis MIS-ES running DC/OSx (SVR4)
-    # needs -lnsl.
-    # The nsl library prevents programs from opening the X display
-    # on Irix 5.2, according to dickey@clark.net.
-    echo $ac_n "checking for gethostbyname""... $ac_c" 1>&6
-echo "configure:2990: checking for gethostbyname" >&5
-if eval "test \"`echo '$''{'ac_cv_func_gethostbyname'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 2995 "configure"
-#include "confdefs.h"
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char gethostbyname(); below.  */
-#include <assert.h>
-/* Override any gcc2 internal prototype to avoid an error.  */
-/* We use char because int might match the return type of a gcc2
-    builtin and then its argument prototype would still apply.  */
-char gethostbyname();
-
-int main() {
-
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_gethostbyname) || defined (__stub___gethostbyname)
-choke me
-#else
-gethostbyname();
-#endif
-
-; return 0; }
-EOF
-if { (eval echo configure:3018: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  eval "ac_cv_func_gethostbyname=yes"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_func_gethostbyname=no"
-fi
-rm -f conftest*
-fi
-
-if eval "test \"`echo '$ac_cv_func_'gethostbyname`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-  :
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-    if test $ac_cv_func_gethostbyname = no; then
-      echo $ac_n "checking for gethostbyname in -lnsl""... $ac_c" 1>&6
-echo "configure:3039: checking for gethostbyname in -lnsl" >&5
-ac_lib_var=`echo nsl'_'gethostbyname | sed 'y%./+-%__p_%'`
-if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  ac_save_LIBS="$LIBS"
-LIBS="-lnsl  $LIBS"
-cat > conftest.$ac_ext <<EOF
-#line 3047 "configure"
-#include "confdefs.h"
-/* Override any gcc2 internal prototype to avoid an error.  */
-/* We use char because int might match the return type of a gcc2
-    builtin and then its argument prototype would still apply.  */
-char gethostbyname();
-
-int main() {
-gethostbyname()
-; return 0; }
-EOF
-if { (eval echo configure:3058: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  eval "ac_cv_lib_$ac_lib_var=yes"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_lib_$ac_lib_var=no"
-fi
-rm -f conftest*
-LIBS="$ac_save_LIBS"
-
-fi
-if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-  X_EXTRA_LIBS="$X_EXTRA_LIBS -lnsl"
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-    fi
-
-    # lieder@skyler.mavd.honeywell.com says without -lsocket,
-    # socket/setsockopt and other routines are undefined under SCO ODT
-    # 2.0.  But -lsocket is broken on IRIX 5.2 (and is not necessary
-    # on later versions), says simon@lia.di.epfl.ch: it contains
-    # gethostby* variants that don't use the nameserver (or something).
-    # -lsocket must be given before -lnsl if both are needed.
-    # We assume that if connect needs -lnsl, so does gethostbyname.
-    echo $ac_n "checking for connect""... $ac_c" 1>&6
-echo "configure:3088: checking for connect" >&5
-if eval "test \"`echo '$''{'ac_cv_func_connect'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 3093 "configure"
-#include "confdefs.h"
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char connect(); below.  */
-#include <assert.h>
-/* Override any gcc2 internal prototype to avoid an error.  */
-/* We use char because int might match the return type of a gcc2
-    builtin and then its argument prototype would still apply.  */
-char connect();
-
-int main() {
-
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_connect) || defined (__stub___connect)
-choke me
-#else
-connect();
-#endif
-
-; return 0; }
-EOF
-if { (eval echo configure:3116: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  eval "ac_cv_func_connect=yes"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_func_connect=no"
-fi
-rm -f conftest*
-fi
-
-if eval "test \"`echo '$ac_cv_func_'connect`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-  :
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-    if test $ac_cv_func_connect = no; then
-      echo $ac_n "checking for connect in -lsocket""... $ac_c" 1>&6
-echo "configure:3137: checking for connect in -lsocket" >&5
-ac_lib_var=`echo socket'_'connect | sed 'y%./+-%__p_%'`
-if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  ac_save_LIBS="$LIBS"
-LIBS="-lsocket $X_EXTRA_LIBS $LIBS"
-cat > conftest.$ac_ext <<EOF
-#line 3145 "configure"
-#include "confdefs.h"
-/* Override any gcc2 internal prototype to avoid an error.  */
-/* We use char because int might match the return type of a gcc2
-    builtin and then its argument prototype would still apply.  */
-char connect();
-
-int main() {
-connect()
-; return 0; }
-EOF
-if { (eval echo configure:3156: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  eval "ac_cv_lib_$ac_lib_var=yes"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_lib_$ac_lib_var=no"
-fi
-rm -f conftest*
-LIBS="$ac_save_LIBS"
-
-fi
-if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-  X_EXTRA_LIBS="-lsocket $X_EXTRA_LIBS"
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-    fi
-
-    # gomez@mi.uni-erlangen.de says -lposix is necessary on A/UX.
-    echo $ac_n "checking for remove""... $ac_c" 1>&6
-echo "configure:3180: checking for remove" >&5
-if eval "test \"`echo '$''{'ac_cv_func_remove'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 3185 "configure"
-#include "confdefs.h"
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char remove(); below.  */
-#include <assert.h>
-/* Override any gcc2 internal prototype to avoid an error.  */
-/* We use char because int might match the return type of a gcc2
-    builtin and then its argument prototype would still apply.  */
-char remove();
-
-int main() {
-
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_remove) || defined (__stub___remove)
-choke me
-#else
-remove();
-#endif
-
-; return 0; }
-EOF
-if { (eval echo configure:3208: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  eval "ac_cv_func_remove=yes"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_func_remove=no"
-fi
-rm -f conftest*
-fi
-
-if eval "test \"`echo '$ac_cv_func_'remove`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-  :
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-    if test $ac_cv_func_remove = no; then
-      echo $ac_n "checking for remove in -lposix""... $ac_c" 1>&6
-echo "configure:3229: checking for remove in -lposix" >&5
-ac_lib_var=`echo posix'_'remove | sed 'y%./+-%__p_%'`
-if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  ac_save_LIBS="$LIBS"
-LIBS="-lposix  $LIBS"
-cat > conftest.$ac_ext <<EOF
-#line 3237 "configure"
-#include "confdefs.h"
-/* Override any gcc2 internal prototype to avoid an error.  */
-/* We use char because int might match the return type of a gcc2
-    builtin and then its argument prototype would still apply.  */
-char remove();
-
-int main() {
-remove()
-; return 0; }
-EOF
-if { (eval echo configure:3248: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  eval "ac_cv_lib_$ac_lib_var=yes"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_lib_$ac_lib_var=no"
-fi
-rm -f conftest*
-LIBS="$ac_save_LIBS"
-
-fi
-if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-  X_EXTRA_LIBS="$X_EXTRA_LIBS -lposix"
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-    fi
-
-    # BSDI BSD/OS 2.1 needs -lipc for XOpenDisplay.
-    echo $ac_n "checking for shmat""... $ac_c" 1>&6
-echo "configure:3272: checking for shmat" >&5
-if eval "test \"`echo '$''{'ac_cv_func_shmat'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 3277 "configure"
-#include "confdefs.h"
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char shmat(); below.  */
-#include <assert.h>
-/* Override any gcc2 internal prototype to avoid an error.  */
-/* We use char because int might match the return type of a gcc2
-    builtin and then its argument prototype would still apply.  */
-char shmat();
-
-int main() {
-
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_shmat) || defined (__stub___shmat)
-choke me
-#else
-shmat();
-#endif
-
-; return 0; }
-EOF
-if { (eval echo configure:3300: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  eval "ac_cv_func_shmat=yes"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_func_shmat=no"
-fi
-rm -f conftest*
-fi
-
-if eval "test \"`echo '$ac_cv_func_'shmat`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-  :
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-    if test $ac_cv_func_shmat = no; then
-      echo $ac_n "checking for shmat in -lipc""... $ac_c" 1>&6
-echo "configure:3321: checking for shmat in -lipc" >&5
-ac_lib_var=`echo ipc'_'shmat | sed 'y%./+-%__p_%'`
-if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  ac_save_LIBS="$LIBS"
-LIBS="-lipc  $LIBS"
-cat > conftest.$ac_ext <<EOF
-#line 3329 "configure"
-#include "confdefs.h"
-/* Override any gcc2 internal prototype to avoid an error.  */
-/* We use char because int might match the return type of a gcc2
-    builtin and then its argument prototype would still apply.  */
-char shmat();
-
-int main() {
-shmat()
-; return 0; }
-EOF
-if { (eval echo configure:3340: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  eval "ac_cv_lib_$ac_lib_var=yes"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_lib_$ac_lib_var=no"
-fi
-rm -f conftest*
-LIBS="$ac_save_LIBS"
-
-fi
-if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-  X_EXTRA_LIBS="$X_EXTRA_LIBS -lipc"
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-    fi
-  fi
-
-  # Check for libraries that X11R6 Xt/Xaw programs need.
-  ac_save_LDFLAGS="$LDFLAGS"
-  test -n "$x_libraries" && LDFLAGS="$LDFLAGS -L$x_libraries"
-  # SM needs ICE to (dynamically) link under SunOS 4.x (so we have to
-  # check for ICE first), but we must link in the order -lSM -lICE or
-  # we get undefined symbols.  So assume we have SM if we have ICE.
-  # These have to be linked with before -lX11, unlike the other
-  # libraries we check for below, so use a different variable.
-  #  --interran@uluru.Stanford.EDU, kb@cs.umb.edu.
-  echo $ac_n "checking for IceConnectionNumber in -lICE""... $ac_c" 1>&6
-echo "configure:3373: checking for IceConnectionNumber in -lICE" >&5
-ac_lib_var=`echo ICE'_'IceConnectionNumber | sed 'y%./+-%__p_%'`
-if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  ac_save_LIBS="$LIBS"
-LIBS="-lICE $X_EXTRA_LIBS $LIBS"
-cat > conftest.$ac_ext <<EOF
-#line 3381 "configure"
-#include "confdefs.h"
-/* Override any gcc2 internal prototype to avoid an error.  */
-/* We use char because int might match the return type of a gcc2
-    builtin and then its argument prototype would still apply.  */
-char IceConnectionNumber();
-
-int main() {
-IceConnectionNumber()
-; return 0; }
-EOF
-if { (eval echo configure:3392: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  eval "ac_cv_lib_$ac_lib_var=yes"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_lib_$ac_lib_var=no"
-fi
-rm -f conftest*
-LIBS="$ac_save_LIBS"
-
-fi
-if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-  X_PRE_LIBS="$X_PRE_LIBS -lSM -lICE"
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-  LDFLAGS="$ac_save_LDFLAGS"
-
-fi
-
-
-#dnl Check for Motif include files location.
-#dnl The LAST one found is used, this makes the highest version to be used,
-#dnl e.g. when Motif1.2 and Motif2.0 are both present.
-
-SKIP_MOTIF=
-if test -z "$SKIP_MOTIF"; then
-  gui_includes="`echo $x_includes|sed 's%/^/^/*$%%'` /local/Motif*/include /local/include/Motif* /usr/local/Motif*/include /usr/local/include/Motif* /usr/include/Motif* /usr/Motif*/include /usr/local/include /usr/local/X11*/include /usr/include /usr/X11*/include /usr/include/X11* /usr/dt/include $MOTIFHOME/include $GUI_INC_LOC"
-  echo $ac_n "checking for location of Motif GUI includes""... $ac_c" 1>&6
-echo "configure:3425: checking for location of Motif GUI includes" >&5
-  GUI_INC_LOC=
-  for try in $gui_includes; do
-    if test -f "$try/Xm/Xm.h"; then
-      GUI_INC_LOC=$try
-    fi
-  done
-  if test -n "$GUI_INC_LOC"; then
-    echo "$ac_t""$GUI_INC_LOC" 1>&6
-    test "$GUI_INC_LOC" = /usr/include && GUI_INC_LOC=.
-  else
-    echo "$ac_t""<not found>" 1>&6
-    SKIP_MOTIF=YES
-  fi
-fi
-
-#dnl Check for Motif library files location.
-#dnl The LAST one found is used, this makes the highest version to be used,
-#dnl e.g. when Motif1.2 and Motif2.0 are both present.
-
-if test -z "$SKIP_MOTIF"; then
-  gui_libs="`echo $x_libraries|sed 's%/^/^/*$%%'` `echo "$GUI_INC_LOC" | sed 's/include/lib/'` /local/Motif*/lib /local/lib/Motif* /usr/local/Motif*/lib /usr/local/lib/Motif* /usr/Motif*/lib /usr/lib/Motif* /usr/local/lib /usr/local/X11*/lib /usr/lib /usr/X11*/lib /usr/lib/X11* /usr/dt/lib $MOTIFHOME/lib $GUI_LIB_LOC"
-  echo $ac_n "checking for location of Motif GUI libs""... $ac_c" 1>&6
-echo "configure:3448: checking for location of Motif GUI libs" >&5
-  GUI_LIB_LOC=
-  for try in $gui_libs; do
-    if test -f "$try/libXm.a" -o -f "$try/libXm.so" -o -f "$try/libXm.sl"; then
-      GUI_LIB_LOC=$try
-      if test "`(uname) 2>/dev/null`" = SunOS &&
-            uname -r | grep '^5' >/dev/null; then
-        GUI_LIB_LOC="$GUI_LIB_LOC -R $try"
-      fi
-    fi
-  done
-  if test -n "$GUI_LIB_LOC"; then
-    echo "$ac_t""$GUI_LIB_LOC" 1>&6
-  else
-    echo "$ac_t""<not found>" 1>&6
-    SKIP_MOTIF=YES
-  fi
-fi
-
-MOTIF_INC_LOC="-I$GUI_INC_LOC"
-MOTIF_LIB_LOC="-L$GUI_LIB_LOC -lXm"
-
-# Try static link on Linux
-# TODO: faire pareil pour Xpm, voir gvim???
-# ERRORLinux !!!! ca marche pas Xm a besoin de -lXp (pb xfsm)
-
-    if test -f "$GUI_LIB_LOC/libXm.a"; then
-      if test "$ALLIANCE_OS" = ERRORLinux; then
-          MOTIF_LIB_LOC="$GUI_LIB_LOC/libXm.a"
-      fi
-    fi
-
-
-
-
-# Under Cygwin I had problems with the order of libs...
-if test "$ALLIANCE_OS" = Cygwin ; then
-    X_PRE_LIBS="-lXt $X_PRE_LIBS"
-fi
-
-# Check if a small X app compiles
-
-OLD_LIBS=$LIBS
-OLD_CFLAGS=$CFLAGS
-LIBS="$OLD_LIBS $X_LIBS $X_EXTRA_LIBS $X_PRE_LIBS -lXt -lX11"
-CFLAGS="$OLD_CFLAGS $X_CFLAGS"
-echo $ac_n "checking if you can link X11 app""... $ac_c" 1>&6
-echo "configure:3495: checking if you can link X11 app" >&5
-cat > conftest.$ac_ext <<EOF
-#line 3497 "configure"
-#include "confdefs.h"
-#include <stdio.h>
-#include <X11/Xlib.h>
-int main() {
- XOpenDisplay (":0");
-; return 0; }
-EOF
-if { (eval echo configure:3505: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  echo "$ac_t""yes" 1>&6
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  echo "$ac_t""ERROR: BAD X11 environment" 1>&6
-
-fi
-rm -f conftest*
-LIBS=$OLD_LIBS
-CFLAGS=$OLD_CFLAGS
-    
-# Check if the motif lib needs other libs to link ok
-
-OLD_LIBS=$LIBS
-OLD_CFLAGS=$CFLAGS
-LIBS="$OLD_LIBS -L$GUI_LIB_LOC -lXm $X_LIBS $X_EXTRA_LIBS $X_PRE_LIBS -lXt -lX11"
-CFLAGS="$OLD_CFLAGS $X_CFLAGS -I$GUI_INC_LOC"
-
-echo "checking if you can link Motif/LessTif app" 1>&6
-echo "configure:3527: checking if you can link Motif/LessTif app" >&5
-echo $ac_n "checking        without additional libs""... $ac_c" 1>&6
-echo "configure:3529: checking        without additional libs" >&5
-cat > conftest.$ac_ext <<EOF
-#line 3531 "configure"
-#include "confdefs.h"
-# include <Xm/Xm.h>
-# include <Xm/FileSB.h>
-# include <Xm/MessageB.h>
-# include <Xm/SelectioB.h>
-# include <Xm/SeparatoG.h>
-int main() {
- XtAppContext app;
-  Widget toplevel;
-  XmString xm_string;
-  Arg args[1];
-  toplevel = XtVaAppInitialize(&app, "Demos", 0, 0, 0, 0, 0, 0);
-  xm_string = XmStringCreateSimple("Vive Alliance");
-  XtSetArg(args[0], XmNmessageString, xm_string);
-  XmStringFree(xm_string);
-  XtAppMainLoop( app );
-; return 0; }
-EOF
-if { (eval echo configure:3550: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  echo "$ac_t""yes" 1>&6
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  echo "$ac_t""no" 1>&6
-
-# try with Xintl
-echo $ac_n "checking        with Xintl""... $ac_c" 1>&6
-echo "configure:3561: checking        with Xintl" >&5
-LIBS="$OLD_LIBS -L$GUI_LIB_LOC -lXm $X_LIBS $X_EXTRA_LIBS $X_PRE_LIBS -lXintl -lXt -lX11"
-CFLAGS="$OLD_CFLAGS $X_CFLAGS -I$GUI_INC_LOC"
-
-cat > conftest.$ac_ext <<EOF
-#line 3566 "configure"
-#include "confdefs.h"
-# include <Xm/Xm.h>
-# include <Xm/FileSB.h>
-# include <Xm/MessageB.h>
-# include <Xm/SelectioB.h>
-# include <Xm/SeparatoG.h>
-int main() {
- XtAppContext app;
-  Widget toplevel;
-  XmString xm_string;
-  Arg args[1];
-  toplevel = XtVaAppInitialize(&app, "Demos", 0, 0, 0, 0, 0, 0);
-  xm_string = XmStringCreateSimple("Vive Alliance");
-  XtSetArg(args[0], XmNmessageString, xm_string);
-  XmStringFree(xm_string);
-  XtAppMainLoop( app );
-; return 0; }
-EOF
-if { (eval echo configure:3585: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  echo "$ac_t""yes" 1>&6; X_PRE_LIBS="$X_PRE_LIBS -lXintl"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  echo "$ac_t""no" 1>&6
-
-# try with Xp
-echo $ac_n "checking        with Xext and Xp""... $ac_c" 1>&6
-echo "configure:3596: checking        with Xext and Xp" >&5
-LIBS="$OLD_LIBS -L$GUI_LIB_LOC -lXm $X_LIBS $X_EXTRA_LIBS $X_PRE_LIBS -lXext -lXp -lXt -lX11"
-CFLAGS="$OLD_CFLAGS $X_CFLAGS -I$GUI_INC_LOC"
-
-cat > conftest.$ac_ext <<EOF
-#line 3601 "configure"
-#include "confdefs.h"
-# include <Xm/Xm.h>
-# include <Xm/FileSB.h>
-# include <Xm/MessageB.h>
-# include <Xm/SelectioB.h>
-# include <Xm/SeparatoG.h>
-int main() {
- XtAppContext app;
-  Widget toplevel;
-  XmString xm_string;
-  Arg args[1];
-  toplevel = XtVaAppInitialize(&app, "Demos", 0, 0, 0, 0, 0, 0);
-  xm_string = XmStringCreateSimple("Vive Alliance");
-  XtSetArg(args[0], XmNmessageString, xm_string);
-  XmStringFree(xm_string);
-  XtAppMainLoop( app );
-; return 0; }
-EOF
-if { (eval echo configure:3620: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  echo "$ac_t""yes" 1>&6; X_PRE_LIBS="$X_PRE_LIBS -lXext -lXp"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  echo "$ac_t""ERROR: BAD Motif/LessTif environment" 1>&6
-
-fi
-rm -f conftest*
-fi
-rm -f conftest*
-fi
-rm -f conftest*
-
-LIBS=$OLD_LIBS
-CFLAGS=$OLD_CFLAGS
-
-
-
-XPM_CFLAGS_LOC=""
-XPM_LIBS_LOC="-lXpm"
-
-OLD_LIBS=$LIBS
-OLD_CFLAGS=$CFLAGS
-LIBS="$OLD_LIBS $XPM_LIBS_LOC $X_LIBS $X_EXTRA_LIBS $X_PRE_LIBS -lXt -lX11"
-CFLAGS="$OLD_CFLAGS $X_CFLAGS $XPM_CFLAGS_LOC"
-echo $ac_n "checking for libXpm""... $ac_c" 1>&6
-echo "configure:3649: checking for libXpm" >&5
-cat > conftest.$ac_ext <<EOF
-#line 3651 "configure"
-#include "confdefs.h"
-#include <stdio.h>
-#include <stdlib.h>
-#include <X11/xpm.h>
-int main() {
- XpmWriteFileFromPixmap( NULL, NULL, NULL, NULL, NULL );
-; return 0; }
-EOF
-if { (eval echo configure:3660: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  echo "$ac_t""yes" 1>&6; AUTO_HAS="$AUTO_HAS -DAUTO_HAS_XPM"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  echo "$ac_t""no" 1>&6;XPM_CFLAGS_LOC="" ; XPM_LIBS_LOC=""
-
-fi
-rm -f conftest*
-LIBS=$OLD_LIBS
-CFLAGS=$OLD_CFLAGS
-
-
-
-
-# Check where usefull GNU libs are installed (readline)
-#AC_CHECK_LIB(readline, main, $TRUE,
-#AC_MSG_WARN(Cannot find readline library), -ltermcap )
-
-
-# Check for readline include
-
-SKIP_GNU=
-if test -z "$SKIP_GNU"; then
-  gnu_includes="`echo $LD_LIBRARY_PATH | sed 's/:/ /g' | sed 's/lib/include/g'` /usr/local/include /usr/include $GNUHOME/include $GNU_INC_LOC"
-  echo $ac_n "checking for location of GNU readline include""... $ac_c" 1>&6
-echo "configure:3688: checking for location of GNU readline include" >&5
-  GNU_INC_LOC=
-#    echo $gnu_includes
-  for try in $gnu_includes; do
-    if test -f "$try/readline/readline.h"; then
-      GNU_INC_LOC=$try
-    fi
-  done
-  if test -n "$GNU_INC_LOC"; then
-    echo "$ac_t""$GNU_INC_LOC" 1>&6
-    test "$GNU_INC_LOC" = /usr/include && GNU_INC_LOC=.
-  else
-    echo "$ac_t""not found." 1>&6
-    SKIP_GNU=YES
-  fi
-fi
-
-# Check for readline library
-
-if test -z "$SKIP_GNU"; then
-  gnu_libs="`echo $LD_LIBRARY_PATH | sed 's/:/ /g'` `echo "$GNU_INC_LOC" | sed 's/include/lib/'` /usr/local/lib /usr/lib $GNUHOME/lib $GNU_LIB_LOC"
-  echo $ac_n "checking for location of GNU libs""... $ac_c" 1>&6
-echo "configure:3710: checking for location of GNU libs" >&5
-  GNU_LIB_LOC=
-#    echo $gnu_libs
-  for try in $gnu_libs; do
-    if test -f "$try/libreadline.a" ; then
-      GNU_LIB_LOC=$try
-    fi
-  done
-  if test -n "$GNU_LIB_LOC"; then
-    echo "$ac_t""$GNU_LIB_LOC" 1>&6
-  else
-    echo "$ac_t""not found. Please install readline and add lib to your LD_LIBRARY_PATH " 1>&6
-    SKIP_GNU=YES
-  fi
-fi
-
-
-
-
-
-################################################################### Headers...
-echo $ac_n "checking for ANSI C header files""... $ac_c" 1>&6
-echo "configure:3732: checking for ANSI C header files" >&5
-if eval "test \"`echo '$''{'ac_cv_header_stdc'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 3737 "configure"
-#include "confdefs.h"
-#include <stdlib.h>
-#include <stdarg.h>
-#include <string.h>
-#include <float.h>
-EOF
-ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:3745: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
-ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
-if test -z "$ac_err"; then
-  rm -rf conftest*
-  ac_cv_header_stdc=yes
-else
-  echo "$ac_err" >&5
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  ac_cv_header_stdc=no
-fi
-rm -f conftest*
-
-if test $ac_cv_header_stdc = yes; then
-  # SunOS 4.x string.h does not declare mem*, contrary to ANSI.
-cat > conftest.$ac_ext <<EOF
-#line 3762 "configure"
-#include "confdefs.h"
-#include <string.h>
-EOF
-if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
-  egrep "memchr" >/dev/null 2>&1; then
-  :
-else
-  rm -rf conftest*
-  ac_cv_header_stdc=no
-fi
-rm -f conftest*
-
-fi
-
-if test $ac_cv_header_stdc = yes; then
-  # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI.
-cat > conftest.$ac_ext <<EOF
-#line 3780 "configure"
-#include "confdefs.h"
-#include <stdlib.h>
-EOF
-if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
-  egrep "free" >/dev/null 2>&1; then
-  :
-else
-  rm -rf conftest*
-  ac_cv_header_stdc=no
-fi
-rm -f conftest*
-
-fi
-
-if test $ac_cv_header_stdc = yes; then
-  # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi.
-if test "$cross_compiling" = yes; then
-  :
-else
-  cat > conftest.$ac_ext <<EOF
-#line 3801 "configure"
-#include "confdefs.h"
-#include <ctype.h>
-#define ISLOWER(c) ('a' <= (c) && (c) <= 'z')
-#define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c))
-#define XOR(e, f) (((e) && !(f)) || (!(e) && (f)))
-int main () { int i; for (i = 0; i < 256; i++)
-if (XOR (islower (i), ISLOWER (i)) || toupper (i) != TOUPPER (i)) exit(2);
-exit (0); }
-
-EOF
-if { (eval echo configure:3812: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
-then
-  :
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -fr conftest*
-  ac_cv_header_stdc=no
-fi
-rm -fr conftest*
-fi
-
-fi
-fi
-
-echo "$ac_t""$ac_cv_header_stdc" 1>&6
-if test $ac_cv_header_stdc = yes; then
-  cat >> confdefs.h <<\EOF
-#define STDC_HEADERS 1
-EOF
-
-fi
-
-
-#AC_CHECK_SIZEOF(int)
-
-#AC_CHECK_SIZEOF(void *)
-
-#AC_MSG_RESULT([kernel name : "$KERNEL_FILE"])
-
-################################################################### OS specific...
-
-vfork=vfork
-echo $ac_n "checking for pid_t""... $ac_c" 1>&6
-echo "configure:3846: checking for pid_t" >&5
-if eval "test \"`echo '$''{'ac_cv_type_pid_t'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 3851 "configure"
-#include "confdefs.h"
-#include <sys/types.h>
-#if STDC_HEADERS
-#include <stdlib.h>
-#include <stddef.h>
-#endif
-EOF
-if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
-  egrep "(^|[^a-zA-Z_0-9])pid_t[^a-zA-Z_0-9]" >/dev/null 2>&1; then
-  rm -rf conftest*
-  ac_cv_type_pid_t=yes
-else
-  rm -rf conftest*
-  ac_cv_type_pid_t=no
-fi
-rm -f conftest*
-
-fi
-echo "$ac_t""$ac_cv_type_pid_t" 1>&6
-if test $ac_cv_type_pid_t = no; then
-  cat >> confdefs.h <<\EOF
-#define pid_t int
-EOF
-
-fi
-
-ac_safe=`echo "vfork.h" | sed 'y%./+-%__p_%'`
-echo $ac_n "checking for vfork.h""... $ac_c" 1>&6
-echo "configure:3880: checking for vfork.h" >&5
-if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 3885 "configure"
-#include "confdefs.h"
-#include <vfork.h>
-EOF
-ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:3890: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
-ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
-if test -z "$ac_err"; then
-  rm -rf conftest*
-  eval "ac_cv_header_$ac_safe=yes"
-else
-  echo "$ac_err" >&5
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_header_$ac_safe=no"
-fi
-rm -f conftest*
-fi
-if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-  cat >> confdefs.h <<\EOF
-#define HAVE_VFORK_H 1
-EOF
-
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-echo $ac_n "checking for working vfork""... $ac_c" 1>&6
-echo "configure:3915: checking for working vfork" >&5
-if eval "test \"`echo '$''{'ac_cv_func_vfork_works'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  if test "$cross_compiling" = yes; then
-  echo $ac_n "checking for vfork""... $ac_c" 1>&6
-echo "configure:3921: checking for vfork" >&5
-if eval "test \"`echo '$''{'ac_cv_func_vfork'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 3926 "configure"
-#include "confdefs.h"
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char vfork(); below.  */
-#include <assert.h>
-/* Override any gcc2 internal prototype to avoid an error.  */
-/* We use char because int might match the return type of a gcc2
-    builtin and then its argument prototype would still apply.  */
-char vfork();
-
-int main() {
-
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_vfork) || defined (__stub___vfork)
-choke me
-#else
-vfork();
-#endif
-
-; return 0; }
-EOF
-if { (eval echo configure:3949: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  eval "ac_cv_func_vfork=yes"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_func_vfork=no"
-fi
-rm -f conftest*
-fi
-
-if eval "test \"`echo '$ac_cv_func_'vfork`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-  :
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-ac_cv_func_vfork_works=$ac_cv_func_vfork
-else
-  cat > conftest.$ac_ext <<EOF
-#line 3971 "configure"
-#include "confdefs.h"
-/* Thanks to Paul Eggert for this test.  */
-#include <stdio.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-#ifdef HAVE_UNISTD_H
-#include <unistd.h>
-#endif
-#ifdef HAVE_VFORK_H
-#include <vfork.h>
-#endif
-/* On some sparc systems, changes by the child to local and incoming
-   argument registers are propagated back to the parent.
-   The compiler is told about this with #include <vfork.h>,
-   but some compilers (e.g. gcc -O) don't grok <vfork.h>.
-   Test for this by using a static variable whose address
-   is put into a register that is clobbered by the vfork.  */
-static
-#ifdef __cplusplus
-sparc_address_test (int arg)
-#else
-sparc_address_test (arg) int arg;
-#endif
-{
-  static pid_t child;
-  if (!child) {
-    child = vfork ();
-    if (child < 0) {
-      perror ("vfork");
-      _exit(2);
-    }
-    if (!child) {
-      arg = getpid();
-      write(-1, "", 0);
-      _exit (arg);
-    }
-  }
-}
-main() {
-  pid_t parent = getpid ();
-  pid_t child;
-
-  sparc_address_test ();
-
-  child = vfork ();
-
-  if (child == 0) {
-    /* Here is another test for sparc vfork register problems.
-       This test uses lots of local variables, at least
-       as many local variables as main has allocated so far
-       including compiler temporaries.  4 locals are enough for
-       gcc 1.40.3 on a Solaris 4.1.3 sparc, but we use 8 to be safe.
-       A buggy compiler should reuse the register of parent
-       for one of the local variables, since it will think that
-       parent can't possibly be used any more in this routine.
-       Assigning to the local variable will thus munge parent
-       in the parent process.  */
-    pid_t
-      p = getpid(), p1 = getpid(), p2 = getpid(), p3 = getpid(),
-      p4 = getpid(), p5 = getpid(), p6 = getpid(), p7 = getpid();
-    /* Convince the compiler that p..p7 are live; otherwise, it might
-       use the same hardware register for all 8 local variables.  */
-    if (p != p1 || p != p2 || p != p3 || p != p4
-	|| p != p5 || p != p6 || p != p7)
-      _exit(1);
-
-    /* On some systems (e.g. IRIX 3.3),
-       vfork doesn't separate parent from child file descriptors.
-       If the child closes a descriptor before it execs or exits,
-       this munges the parent's descriptor as well.
-       Test for this by closing stdout in the child.  */
-    _exit(close(fileno(stdout)) != 0);
-  } else {
-    int status;
-    struct stat st;
-
-    while (wait(&status) != child)
-      ;
-    exit(
-	 /* Was there some problem with vforking?  */
-	 child < 0
-
-	 /* Did the child fail?  (This shouldn't happen.)  */
-	 || status
-
-	 /* Did the vfork/compiler bug occur?  */
-	 || parent != getpid()
-
-	 /* Did the file descriptor bug occur?  */
-	 || fstat(fileno(stdout), &st) != 0
-	 );
-  }
-}
-EOF
-if { (eval echo configure:4066: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
-then
-  ac_cv_func_vfork_works=yes
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -fr conftest*
-  ac_cv_func_vfork_works=no
-fi
-rm -fr conftest*
-fi
-
-fi
-
-echo "$ac_t""$ac_cv_func_vfork_works" 1>&6
-if test $ac_cv_func_vfork_works = no; then
-  cat >> confdefs.h <<\EOF
-#define vfork fork
-EOF
-
-fi
- 
-echo $ac_n "checking AUTO_HAS_VFORK""... $ac_c" 1>&6
-echo "configure:4089: checking AUTO_HAS_VFORK" >&5
-if test $vfork = fork; then
-echo "$ac_t""no" 1>&6
-else
-echo "$ac_t""yes" 1>&6
-AUTO_HAS="$AUTO_HAS -DAUTO_HAS_VFORK"
-fi
-
-echo $ac_n "checking AUTO_HAS_SA_RESTART""... $ac_c" 1>&6
-echo "configure:4098: checking AUTO_HAS_SA_RESTART" >&5
-cat > conftest.$ac_ext <<EOF
-#line 4100 "configure"
-#include "confdefs.h"
-#include <stdio.h>
-#include <stdlib.h>
-#include <signal.h>
-int main() {
-struct sigaction sgct;
-sgct.sa_flags    = SA_RESTART;
-sigaction( SIGCHLD, &sgct , NULL );
-; return 0; }
-EOF
-if { (eval echo configure:4111: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  echo "$ac_t""yes" 1>&6; AUTO_HAS="$AUTO_HAS -DAUTO_HAS_SA_RESTART"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  echo "$ac_t""no" 1>&6
-fi
-rm -f conftest*
-
-echo $ac_n "checking AUTO_HAS_DRAND48""... $ac_c" 1>&6
-echo "configure:4123: checking AUTO_HAS_DRAND48" >&5
-cat > conftest.$ac_ext <<EOF
-#line 4125 "configure"
-#include "confdefs.h"
-#include <stdio.h>
-#include <stdlib.h>
-int main() {
-  double     Proba;
-   Proba    = drand48();
-; return 0; }
-EOF
-if { (eval echo configure:4134: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  echo "$ac_t""yes" 1>&6; AUTO_HAS="$AUTO_HAS -DAUTO_HAS_DRAND48"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  echo "$ac_t""no" 1>&6
-fi
-rm -f conftest*
-
-echo $ac_n "checking AUTO_HAS_VALUES_H""... $ac_c" 1>&6
-echo "configure:4146: checking AUTO_HAS_VALUES_H" >&5
-cat > conftest.$ac_ext <<EOF
-#line 4148 "configure"
-#include "confdefs.h"
-#include <stdio.h>
-#include <stdlib.h>
-#include <values.h>
-int main() {
-  float     Proba;
-   Proba   = MAXFLOAT;
-; return 0; }
-EOF
-if { (eval echo configure:4158: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  echo "$ac_t""yes" 1>&6; AUTO_HAS="$AUTO_HAS -DAUTO_HAS_VALUES_H"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  echo "$ac_t""no" 1>&6
-fi
-rm -f conftest*
-
-
-
-#fi # SKIPTEST
-    
-################################################################### Alliance ALLIANCE_TOP
-echo $ac_n "checking where the Alliance package was installed""... $ac_c" 1>&6
-echo "configure:4175: checking where the Alliance package was installed" >&5
-# Avoid problems with soft links and builtin pwd...
-ALLIANCE_TOP=`$PWDBIN | sed 's§share/etc$§archi§'`
-ALLIANCE_TOP=`echo $ALLIANCE_TOP | sed 's§archi/Cygwin/etc$§archi§'`
-
-export ALLIANCE_TOP
-echo "$ac_t""""" 1>&6
-
-
-DATE=`date`
-
-
-HOST=`uname -a`
-
-
-# create output files
-
-trap '' 1 2 15
-cat > confcache <<\EOF
-# This file is a shell script that caches the results of configure
-# tests run on this system so they can be shared between configure
-# scripts and configure runs.  It is not useful on other systems.
-# If it contains results you don't want to keep, you may remove or edit it.
-#
-# By default, configure uses ./config.cache as the cache file,
-# creating it if it does not exist already.  You can give configure
-# the --cache-file=FILE option to use a different cache file; that is
-# what configure does when it calls configure scripts in
-# subdirectories, so they share the cache.
-# Giving --cache-file=/dev/null disables caching, for debugging configure.
-# config.status only pays attention to the cache file if you give it the
-# --recheck option to rerun configure.
-#
-EOF
-# The following way of writing the cache mishandles newlines in values,
-# but we know of no workaround that is simple, portable, and efficient.
-# So, don't put newlines in cache variables' values.
-# Ultrix sh set writes to stderr and can't be redirected directly,
-# and sets the high bit in the cache file unless we assign to the vars.
-(set) 2>&1 |
-  case `(ac_space=' '; set | grep ac_space) 2>&1` in
-  *ac_space=\ *)
-    # `set' does not quote correctly, so add quotes (double-quote substitution
-    # turns \\\\ into \\, and sed turns \\ into \).
-    sed -n \
-      -e "s/'/'\\\\''/g" \
-      -e "s/^\\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\\)=\\(.*\\)/\\1=\${\\1='\\2'}/p"
-    ;;
-  *)
-    # `set' quotes correctly as required by POSIX, so do not add quotes.
-    sed -n -e 's/^\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\)=\(.*\)/\1=${\1=\2}/p'
-    ;;
-  esac >> confcache
-if cmp -s $cache_file confcache; then
-  :
-else
-  if test -w $cache_file; then
-    echo "updating cache $cache_file"
-    cat confcache > $cache_file
-  else
-    echo "not updating unwritable cache $cache_file"
-  fi
-fi
-rm -f confcache
-
-trap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15
-
-test "x$prefix" = xNONE && prefix=$ac_default_prefix
-# Let make expand exec_prefix.
-test "x$exec_prefix" = xNONE && exec_prefix='${prefix}'
-
-# Any assignment to VPATH causes Sun make to only execute
-# the first set of double-colon rules, so remove it if not needed.
-# If there is a colon in the path, we need to keep it.
-if test "x$srcdir" = x.; then
-  ac_vpsub='/^[ 	]*VPATH[ 	]*=[^:]*$/d'
-fi
-
-trap 'rm -f $CONFIG_STATUS conftest*; exit 1' 1 2 15
-
-# Transform confdefs.h into DEFS.
-# Protect against shell expansion while executing Makefile rules.
-# Protect against Makefile macro expansion.
-cat > conftest.defs <<\EOF
-s%#define \([A-Za-z_][A-Za-z0-9_]*\) *\(.*\)%-D\1=\2%g
-s%[ 	`~#$^&*(){}\\|;'"<>?]%\\&%g
-s%\[%\\&%g
-s%\]%\\&%g
-s%\$%$$%g
-EOF
-DEFS=`sed -f conftest.defs confdefs.h | tr '\012' ' '`
-rm -f conftest.defs
-
-
-# Without the "./", some shells look in PATH for config.status.
-: ${CONFIG_STATUS=./config.status}
-
-echo creating $CONFIG_STATUS
-rm -f $CONFIG_STATUS
-cat > $CONFIG_STATUS <<EOF
-#! /bin/sh
-# Generated automatically by configure.
-# Run this file to recreate the current configuration.
-# This directory was configured as follows,
-# on host `(hostname || uname -n) 2>/dev/null | sed 1q`:
-#
-# $0 $ac_configure_args
-#
-# Compiler output produced by configure, useful for debugging
-# configure, is in ./config.log if it exists.
-
-ac_cs_usage="Usage: $CONFIG_STATUS [--recheck] [--version] [--help]"
-for ac_option
-do
-  case "\$ac_option" in
-  -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r)
-    echo "running \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion"
-    exec \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion ;;
-  -version | --version | --versio | --versi | --vers | --ver | --ve | --v)
-    echo "$CONFIG_STATUS generated by autoconf version 2.13"
-    exit 0 ;;
-  -help | --help | --hel | --he | --h)
-    echo "\$ac_cs_usage"; exit 0 ;;
-  *) echo "\$ac_cs_usage"; exit 1 ;;
-  esac
-done
-
-ac_given_srcdir=$srcdir
-
-trap 'rm -fr `echo "alliance_os.mk alc_env.sh alc_env.csh alc_env.bat" | sed "s/:[^ ]*//g"` conftest*; exit 1' 1 2 15
-EOF
-cat >> $CONFIG_STATUS <<EOF
-
-# Protect against being on the right side of a sed subst in config.status.
-sed 's/%@/@@/; s/@%/@@/; s/%g\$/@g/; /@g\$/s/[\\\\&%]/\\\\&/g;
- s/@@/%@/; s/@@/@%/; s/@g\$/%g/' > conftest.subs <<\\CEOF
-$ac_vpsub
-$extrasub
-s%@SHELL@%$SHELL%g
-s%@CFLAGS@%$CFLAGS%g
-s%@CPPFLAGS@%$CPPFLAGS%g
-s%@CXXFLAGS@%$CXXFLAGS%g
-s%@FFLAGS@%$FFLAGS%g
-s%@DEFS@%$DEFS%g
-s%@LDFLAGS@%$LDFLAGS%g
-s%@LIBS@%$LIBS%g
-s%@exec_prefix@%$exec_prefix%g
-s%@prefix@%$prefix%g
-s%@program_transform_name@%$program_transform_name%g
-s%@bindir@%$bindir%g
-s%@sbindir@%$sbindir%g
-s%@libexecdir@%$libexecdir%g
-s%@datadir@%$datadir%g
-s%@sysconfdir@%$sysconfdir%g
-s%@sharedstatedir@%$sharedstatedir%g
-s%@localstatedir@%$localstatedir%g
-s%@libdir@%$libdir%g
-s%@includedir@%$includedir%g
-s%@oldincludedir@%$oldincludedir%g
-s%@infodir@%$infodir%g
-s%@mandir@%$mandir%g
-s%@ALLIANCE_OS@%$ALLIANCE_OS%g
-s%@SET_MAKE@%$SET_MAKE%g
-s%@PROGRAM_SUFFIX@%$PROGRAM_SUFFIX%g
-s%@CC@%$CC%g
-s%@FULL_CC@%$FULL_CC%g
-s%@CPP@%$CPP%g
-s%@GMAKE@%$GMAKE%g
-s%@MAKE@%$MAKE%g
-s%@MAKEFLAGS@%$MAKEFLAGS%g
-s%@YACC@%$YACC%g
-s%@LEX@%$LEX%g
-s%@LEXLIB@%$LEXLIB%g
-s%@LEX_OUTPUT_ROOT@%$LEX_OUTPUT_ROOT%g
-s%@YACCFLAGS@%$YACCFLAGS%g
-s%@LEXFLAGS@%$LEXFLAGS%g
-s%@FULL_LEX@%$FULL_LEX%g
-s%@FULL_YACC@%$FULL_YACC%g
-s%@CPP_MM@%$CPP_MM%g
-s%@LN_S@%$LN_S%g
-s%@AR@%$AR%g
-s%@ARFLAGS@%$ARFLAGS%g
-s%@AUTOCONF@%$AUTOCONF%g
-s%@AUTOHEADER@%$AUTOHEADER%g
-s%@AUTOMAKE@%$AUTOMAKE%g
-s%@GAWK@%$GAWK%g
-s%@AWK@%$AWK%g
-s%@CHMOD@%$CHMOD%g
-s%@CP@%$CP%g
-s%@CAT@%$CAT%g
-s%@CSH@%$CSH%g
-s%@CUT@%$CUT%g
-s%@ECHO@%$ECHO%g
-s%@FALSE@%$FALSE%g
-s%@FIND@%$FIND%g
-s%@GREP@%$GREP%g
-s%@HOSTNAME@%$HOSTNAME%g
-s%@LD@%$LD%g
-s%@LNDIR@%$LNDIR%g
-s%@LS@%$LS%g
-s%@MKDIR@%$MKDIR%g
-s%@MV@%$MV%g
-s%@PERL@%$PERL%g
-s%@PWDBIN@%$PWDBIN%g
-s%@RANLIB@%$RANLIB%g
-s%@RM@%$RM%g
-s%@SED@%$SED%g
-s%@SH@%$SH%g
-s%@STRIP@%$STRIP%g
-s%@TEST@%$TEST%g
-s%@TOUCH@%$TOUCH%g
-s%@TR@%$TR%g
-s%@TRUE@%$TRUE%g
-s%@WC@%$WC%g
-s%@X_CFLAGS@%$X_CFLAGS%g
-s%@X_PRE_LIBS@%$X_PRE_LIBS%g
-s%@X_LIBS@%$X_LIBS%g
-s%@X_EXTRA_LIBS@%$X_EXTRA_LIBS%g
-s%@MOTIF_INC_LOC@%$MOTIF_INC_LOC%g
-s%@MOTIF_LIB_LOC@%$MOTIF_LIB_LOC%g
-s%@XPM_LIBS_LOC@%$XPM_LIBS_LOC%g
-s%@XPM_CFLAGS_LOC@%$XPM_CFLAGS_LOC%g
-s%@GNU_INC_LOC@%$GNU_INC_LOC%g
-s%@GNU_LIB_LOC@%$GNU_LIB_LOC%g
-s%@AUTO_HAS@%$AUTO_HAS%g
-s%@ALLIANCE_TOP@%$ALLIANCE_TOP%g
-s%@DATE@%$DATE%g
-s%@HOST@%$HOST%g
-
-CEOF
-EOF
-
-cat >> $CONFIG_STATUS <<\EOF
-
-# Split the substitutions into bite-sized pieces for seds with
-# small command number limits, like on Digital OSF/1 and HP-UX.
-ac_max_sed_cmds=90 # Maximum number of lines to put in a sed script.
-ac_file=1 # Number of current file.
-ac_beg=1 # First line for current file.
-ac_end=$ac_max_sed_cmds # Line after last line for current file.
-ac_more_lines=:
-ac_sed_cmds=""
-while $ac_more_lines; do
-  if test $ac_beg -gt 1; then
-    sed "1,${ac_beg}d; ${ac_end}q" conftest.subs > conftest.s$ac_file
-  else
-    sed "${ac_end}q" conftest.subs > conftest.s$ac_file
-  fi
-  if test ! -s conftest.s$ac_file; then
-    ac_more_lines=false
-    rm -f conftest.s$ac_file
-  else
-    if test -z "$ac_sed_cmds"; then
-      ac_sed_cmds="sed -f conftest.s$ac_file"
-    else
-      ac_sed_cmds="$ac_sed_cmds | sed -f conftest.s$ac_file"
-    fi
-    ac_file=`expr $ac_file + 1`
-    ac_beg=$ac_end
-    ac_end=`expr $ac_end + $ac_max_sed_cmds`
-  fi
-done
-if test -z "$ac_sed_cmds"; then
-  ac_sed_cmds=cat
-fi
-EOF
-
-cat >> $CONFIG_STATUS <<EOF
-
-CONFIG_FILES=\${CONFIG_FILES-"alliance_os.mk alc_env.sh alc_env.csh alc_env.bat"}
-EOF
-cat >> $CONFIG_STATUS <<\EOF
-for ac_file in .. $CONFIG_FILES; do if test "x$ac_file" != x..; then
-  # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in".
-  case "$ac_file" in
-  *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'`
-       ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;;
-  *) ac_file_in="${ac_file}.in" ;;
-  esac
-
-  # Adjust a relative srcdir, top_srcdir, and INSTALL for subdirectories.
-
-  # Remove last slash and all that follows it.  Not all systems have dirname.
-  ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'`
-  if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then
-    # The file is in a subdirectory.
-    test ! -d "$ac_dir" && mkdir "$ac_dir"
-    ac_dir_suffix="/`echo $ac_dir|sed 's%^\./%%'`"
-    # A "../" for each directory in $ac_dir_suffix.
-    ac_dots=`echo $ac_dir_suffix|sed 's%/[^/]*%../%g'`
-  else
-    ac_dir_suffix= ac_dots=
-  fi
-
-  case "$ac_given_srcdir" in
-  .)  srcdir=.
-      if test -z "$ac_dots"; then top_srcdir=.
-      else top_srcdir=`echo $ac_dots|sed 's%/$%%'`; fi ;;
-  /*) srcdir="$ac_given_srcdir$ac_dir_suffix"; top_srcdir="$ac_given_srcdir" ;;
-  *) # Relative path.
-    srcdir="$ac_dots$ac_given_srcdir$ac_dir_suffix"
-    top_srcdir="$ac_dots$ac_given_srcdir" ;;
-  esac
-
-
-  echo creating "$ac_file"
-  rm -f "$ac_file"
-  configure_input="Generated automatically from `echo $ac_file_in|sed 's%.*/%%'` by configure."
-  case "$ac_file" in
-  *Makefile*) ac_comsub="1i\\
-# $configure_input" ;;
-  *) ac_comsub= ;;
-  esac
-
-  ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"`
-  sed -e "$ac_comsub
-s%@configure_input@%$configure_input%g
-s%@srcdir@%$srcdir%g
-s%@top_srcdir@%$top_srcdir%g
-" $ac_file_inputs | (eval "$ac_sed_cmds") > $ac_file
-fi; done
-rm -f conftest.s*
-
-EOF
-cat >> $CONFIG_STATUS <<EOF
-
-EOF
-cat >> $CONFIG_STATUS <<\EOF
-
-exit 0
-EOF
-chmod +x $CONFIG_STATUS
-rm -fr confdefs* $ac_clean_files
-test "$no_create" = yes || ${CONFIG_SHELL-/bin/sh} $CONFIG_STATUS || exit 1
-
-
-mv alliance_os.mk $ALLIANCE_OS.mk
-chmod +x alc_env.sh alc_env.csh alc_env.bat
-
-# remove  config cache
-rm -f config.cache
-
-#cat config.status | grep '^s%' | sed -e 's/^s%@//' -e 's/@%/ /' -e 's/%g$//' | sort | gawk '{printf("%-30s",$1) ; for (i=2 ; i<=NF ; i++) printf("%s ", $i); printf ("\n");}'
-
-cat << EOF
-Done...
-Alliance is installed on $ALLIANCE_TOP/$ALLIANCE_OS
-OS definitions are in $ALLIANCE_OS.mk
-You'll need to 'source alc_env.csh'
-or '. alc_env.sh' whether you use csh or sh"
-EOF
-
-# end of configure
diff --git a/alliance/share/etc/configure.in b/alliance/share/etc/configure.in
deleted file mode 100644
index 4a37efac..00000000
--- a/alliance/share/etc/configure.in
+++ /dev/null
@@ -1,583 +0,0 @@
-#             ,,,
-#            (o o)
-####=====oOO--(_)--OOO=========================================####
-# 
-# Filename: configure.in
-# Copyright (C) 1997, 2000 Czo <Olivier.Sirol@lip6.fr>
-# License: GPL (http://www.gnu.org/copyleft/gpl.html)
-# Started: Feb 1997
-# Last Change: Monday 25 February 2002, 15:06
-# Edit Time: 5:34:52
-# Description: Alliance CAD system configure.in 
-#
-# $Id: configure.in,v 1.29 2002/02/25 14:08:45 czo Exp $
-#
-
-AC_REVISION($Revision: 1.29 $)dnl
-
-AC_INIT(configure.in)
-
-AC_PREFIX_DEFAULT(/usr/local/alliance)
-
-# Helps this script to run in bad configured env...
-
-PATH=/local/beny1/arnaud/bin:$PATH
-
-#PATH=$PATH:/bin:/usr/bin:/usr/local/bin:/labo/TeX/teTeX/bin:/labo/X11R6/bin:/labo/X11r5/bin:/labo/bin:/labo/gnu/bin:/sbin:/user/local/bin:/usr/X11/bin:/usr/X11R6/bin:/usr/andrew/bin:/usr/bin/X11:/usr/bin/games:/usr/bin:/usr/ccs/bin:/usr/dt/bin:/usr/etc:/usr/games:/usr/lib/teTeX/bin:/usr/local/bin:/usr/local/games:/usr/openwin/bin:/usr/sbin:/usr/ucb/bin:/usr/ucb:/usr/xpg4/bin
-
-#LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/usr/lib:/usr/local/lib:/labo/gnu/lib:/labo/X11R6/lib:/usr/lib/X11:/labo/X11r5/lib:/usr/X11R6.3/lib
-
-    
-# Which platform for Alliance CAD
-AC_MSG_CHECKING(for platform)
-
-# WARNING : if changing this remember to do it on the 3 config files :
-# configure.in alc_env.sh.in and alc_env.csh.in
-
-ALLIANCE_OS=Unknown
- 
-case `uname` in
-
-  Linux*) case `uname -r` in
-           1.*) ALLIANCE_OS=Linux_aout ;;
-          2.0*) ALLIANCE_OS=Linux_elf  ;;            
-             *) ALLIANCE_OS=Linux  ;;
-          esac ;;
-
-  SunOS*) case `uname -r` in
-            5*) ALLIANCE_OS=Solaris ;;
-             *) ALLIANCE_OS=SunOS ;;
-          esac ;;
-
-  FreeBSD*)     ALLIANCE_OS=FreeBSD ;;
-
-  NetBSD*)      ALLIANCE_OS=NetBSD ;;
-
-  HP-UX*)       ALLIANCE_OS=HPUX ;;
-
-  OSF1*)        ALLIANCE_OS=OSF ;;
-
-  CYGWIN*)      ALLIANCE_OS=Cygwin ;;
-
-  *)            ALLIANCE_OS=Unknown ;;
-
-esac
-
-export ALLIANCE_OS
-# echo $ALLIANCE_OS
-
-AC_MSG_RESULT(Configuring Alliance VLSI CAD System on platform : $ALLIANCE_OS)
-AC_SUBST(ALLIANCE_OS)
-
-AC_PROG_MAKE_SET
-
-if test "$program_suffix" = NONE ; then
-  if test "$ALLIANCE_OS" = Cygwin ; then
-      PROGRAM_SUFFIX=".exe"
-  else    
-      PROGRAM_SUFFIX=""
-  fi
-else    
-    PROGRAM_SUFFIX="$program_suffix"
-fi
-
-AC_SUBST(PROGRAM_SUFFIX)
-
-
-################################################################## Binaries
-AC_CHECKING(%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% Binaries)
-
-# AC_CANONICAL_SYSTEM
-
-# Set default value for CC and CFLAGS
-# -DALLIANCE_DISTRIB
-
-if test -z "$CFLAGS" ; then
-  CFLAGS="-O -D$ALLIANCE_OS"
-fi
-
-AC_PROG_CC
-
-AC_PATH_PROG(FULL_CC,       $CC)
-AC_SUBST(FULL_CC)
-
-AC_PROG_CPP
-
-if test "$GCC" = yes ; then
-    CFLAGS="-O2 -Wall -D$ALLIANCE_OS"
-fi
-
-
-# Set default value for MAKE
-AC_PATH_PROG(GMAKE,      gmake)
-AC_PATH_PROG(MAKE,       make)
-if test -n "$GMAKE" ; then
-    MAKE=$GMAKE
-fi
-
-ARFLAGS=
-AC_SUBST(MAKEFLAGS)
-
-# Looking for particular programs
-# Lex & Yacc
-# Do not use AC_PROG_YACC because our yacc grammar
-# is not compatible with bison...
-# AC_PATH_PROG(YACC, yacc)
-
-AC_PROG_YACC
-AC_PROG_LEX
-AC_DECL_YYTEXT
-
-YACCFLAGS=`echo $YACC | awk '{for (i=2 ; i<=NF ; i++) printf("%s ", $i);printf ("\n"); }'`
-AC_SUBST(YACCFLAGS)
-
-LEXFLAGS=`echo $LEX  | awk '{for (i=2 ; i<=NF ; i++) printf("%s ", $i);printf ("\n"); }'`
-AC_SUBST(LEXFLAGS)
-
-AC_PATH_PROG(FULL_LEX,   `echo $LEX | awk '{print $1}'`)
-AC_SUBST(FULL_LEX)
-
-AC_PATH_PROG(FULL_YACC,  `echo $YACC | awk '{print $1}'`)
-AC_SUBST(FULL_YACC)
-
-# gcc-cpp has the wonderful -MM option to produce nicer dependencies
-test "$GCC" = yes && CPP_MM=M; AC_SUBST(CPP_MM)
-
-AC_PROG_LN_S
-
-# Looking for ordinary programs
-
-AC_PATH_PROG(AR,         ar)
-
-ARFLAGS=rv 
-AC_SUBST(ARFLAGS)
-
-AC_PATH_PROG(AUTOCONF,   autoconf)
-AC_PATH_PROG(AUTOHEADER, autoheader)
-AC_PATH_PROG(AUTOMAKE,   automake)
-
-AC_PATH_PROG(GAWK,       gawk)
-AC_PATH_PROG(AWK,        awk)
-if test -n "$GAWK" ; then
-    AWK=$GAWK
-fi
-
-AC_PATH_PROG(CHMOD,      chmod)
-AC_PATH_PROG(CP,         cp)
-AC_PATH_PROG(CAT,        cat)
-AC_PATH_PROG(CSH,        csh)
-AC_PATH_PROG(CUT,        cut)
-AC_PATH_PROG(ECHO,       echo)
-AC_PATH_PROG(FALSE,      false)
-AC_PATH_PROG(FIND,       find)
-AC_PATH_PROG(GREP,       grep)
-AC_PATH_PROG(HOSTNAME,   hostname)
-AC_PATH_PROG(LD,         ld)
-AC_PATH_PROG(LNDIR,      lndir)
-AC_PATH_PROG(LS,         ls)
-AC_PATH_PROG(MKDIR,      mkdir)
-AC_PATH_PROG(MV,         mv)
-AC_PATH_PROG(PERL,       perl)
-AC_PATH_PROG(PWDBIN,     pwd)
-AC_PATH_PROG(RANLIB,     ranlib)
-AC_PATH_PROG(RM,         rm)
-AC_PATH_PROG(SED,        sed)
-
-AC_PATH_PROG(SH,      sh)
-if test "$SH" != sh ; then
-    SHELL=$SH
-else
-    SHELL=/bin/sh
-fi
-AC_SUBST(SHELL)
-
-AC_PATH_PROG(STRIP,      strip)
-AC_PATH_PROG(TEST,       test)
-AC_PATH_PROG(TOUCH,      touch)
-AC_PATH_PROG(TR,         tr)
-AC_PATH_PROG(TRUE,       true)
-AC_PATH_PROG(WC,         wc)
-
-
-# SKIPTEST
-# if false; then
-    
-# Check that all the utilities are present
-
-# All but makeinfo, automake, autoconf, autoheader, zsh
-if $TEST -z "$AR" \
-   -o -z "$AWK" \
-   -o -z "$CAT" \
-   -o -z "$CHMOD" \
-   -o -z "$CP" \
-   -o -z "$CUT" \
-   -o -z "$ECHO" \
-   -o -z "$FALSE" \
-   -o -z "$FIND" \
-   -o -z "$GREP" \
-   -o -z "$HOSTNAME" \
-   -o -z "$LD" \
-   -o -z "$LS" \
-   -o -z "$MKDIR" \
-   -o -z "$MV" \
-   -o -z "$PERL" \
-   -o -z "$PWDBIN" \
-   -o -z "$RM" \
-   -o -z "$SED" \
-   -o -z "$STRIP" \
-   -o -z "$TEST" \
-   -o -z "$TOUCH" \
-   -o -z "$TR" \
-   -o -z "$TRUE" \
-   -o -z "$WC" 
-then
-  AC_MSG_WARN([please install the above utilities that are not present])
-fi
-
-if test "$ALLIANCE_OS" = Cygwin ; then
-    STRIP="echo"
-fi
-
-
-################################################################## Libraries...
-AC_CHECKING(%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%  Headers and Libraries...)
-# Check that Xpm is installed
-# ($TRUE is used to avoid inclusion of -lXpm in LIBS)
-#AC_CHECK_LIB(Xpm, XpmReadFileToImage, $TRUE,
-#  AC_MSG_ERROR([please install Xpm]))
-
-# Check that xforms is installed
-#AC_CHECK_LIB(xforms, fl_init_font, $TRUE,
-#  AC_MSG_ERROR([please install xforms]))
-
-
-if test "$ALLIANCE_OS" = Solaris ; then
-    x_includes=/usr/openwin/include
-    x_libraries=/usr/openwin/lib
-fi
-
-AC_PATH_XTRA
-
-#dnl Check for Motif include files location.
-#dnl The LAST one found is used, this makes the highest version to be used,
-#dnl e.g. when Motif1.2 and Motif2.0 are both present.
-
-SKIP_MOTIF=
-if test -z "$SKIP_MOTIF"; then
-  gui_includes="`echo $x_includes|sed 's%/[^/][^/]*$%%'` /local/Motif*/include /local/include/Motif* /usr/local/Motif*/include /usr/local/include/Motif* /usr/include/Motif* /usr/Motif*/include /usr/local/include /usr/local/X11*/include /usr/include /usr/X11*/include /usr/include/X11* /usr/dt/include $MOTIFHOME/include $GUI_INC_LOC"
-  AC_MSG_CHECKING(for location of Motif GUI includes)
-  GUI_INC_LOC=
-  for try in $gui_includes; do
-    if test -f "$try/Xm/Xm.h"; then
-      GUI_INC_LOC=$try
-    fi
-  done
-  if test -n "$GUI_INC_LOC"; then
-    AC_MSG_RESULT($GUI_INC_LOC)
-    test "$GUI_INC_LOC" = /usr/include && GUI_INC_LOC=.
-  else
-    AC_MSG_RESULT(<not found>)
-    SKIP_MOTIF=YES
-  fi
-fi
-
-#dnl Check for Motif library files location.
-#dnl The LAST one found is used, this makes the highest version to be used,
-#dnl e.g. when Motif1.2 and Motif2.0 are both present.
-
-if test -z "$SKIP_MOTIF"; then
-  gui_libs="`echo $x_libraries|sed 's%/[^/][^/]*$%%'` `echo "$GUI_INC_LOC" | sed 's/include/lib/'` /local/Motif*/lib /local/lib/Motif* /usr/local/Motif*/lib /usr/local/lib/Motif* /usr/Motif*/lib /usr/lib/Motif* /usr/local/lib /usr/local/X11*/lib /usr/lib /usr/X11*/lib /usr/lib/X11* /usr/dt/lib $MOTIFHOME/lib $GUI_LIB_LOC"
-  AC_MSG_CHECKING(for location of Motif GUI libs)
-  GUI_LIB_LOC=
-  for try in $gui_libs; do
-    if test -f "$try/libXm.a" -o -f "$try/libXm.so" -o -f "$try/libXm.sl"; then
-      GUI_LIB_LOC=$try
-      if test "`(uname) 2>/dev/null`" = SunOS &&
-            uname -r | grep '^5' >/dev/null; then
-        GUI_LIB_LOC="$GUI_LIB_LOC -R $try"
-      fi
-    fi
-  done
-  if test -n "$GUI_LIB_LOC"; then
-    AC_MSG_RESULT($GUI_LIB_LOC)
-  else
-    AC_MSG_RESULT(<not found>)
-    SKIP_MOTIF=YES
-  fi
-fi
-
-MOTIF_INC_LOC="-I$GUI_INC_LOC"
-MOTIF_LIB_LOC="-L$GUI_LIB_LOC -lXm"
-
-# Try static link on Linux
-# TODO: faire pareil pour Xpm, voir gvim???
-# ERRORLinux !!!! ca marche pas Xm a besoin de -lXp (pb xfsm)
-
-    if test -f "$GUI_LIB_LOC/libXm.a"; then
-      if test "$ALLIANCE_OS" = ERRORLinux; then
-          MOTIF_LIB_LOC="$GUI_LIB_LOC/libXm.a"
-      fi
-    fi
-
-AC_SUBST(MOTIF_INC_LOC)
-AC_SUBST(MOTIF_LIB_LOC)
-
-# Under Cygwin I had problems with the order of libs...
-if test "$ALLIANCE_OS" = Cygwin ; then
-    X_PRE_LIBS="-lXt $X_PRE_LIBS"
-fi
-
-# Check if a small X app compiles
-
-OLD_LIBS=$LIBS
-OLD_CFLAGS=$CFLAGS
-LIBS="$OLD_LIBS $X_LIBS $X_EXTRA_LIBS $X_PRE_LIBS -lXt -lX11"
-CFLAGS="$OLD_CFLAGS $X_CFLAGS"
-AC_MSG_CHECKING(if you can link X11 app)
-AC_TRY_LINK([#include <stdio.h>
-#include <X11/Xlib.h>],
-[ XOpenDisplay (":0");],
-AC_MSG_RESULT(yes),
-AC_MSG_RESULT(ERROR: BAD X11 environment)
-)
-LIBS=$OLD_LIBS
-CFLAGS=$OLD_CFLAGS
-    
-# Check if the motif lib needs other libs to link ok
-
-OLD_LIBS=$LIBS
-OLD_CFLAGS=$CFLAGS
-LIBS="$OLD_LIBS -L$GUI_LIB_LOC -lXm $X_LIBS $X_EXTRA_LIBS $X_PRE_LIBS -lXt -lX11"
-CFLAGS="$OLD_CFLAGS $X_CFLAGS -I$GUI_INC_LOC"
-
-AC_CHECKING([if you can link Motif/LessTif app])
-AC_MSG_CHECKING([       without additional libs])
-AC_TRY_LINK([# include <Xm/Xm.h>
-# include <Xm/FileSB.h>
-# include <Xm/MessageB.h>
-# include <Xm/SelectioB.h>
-# include <Xm/SeparatoG.h>],
-[ XtAppContext app;
-  Widget toplevel;
-  XmString xm_string;
-  Arg args[1];
-  toplevel = XtVaAppInitialize(&app, "Demos", 0, 0, 0, 0, 0, 0);
-  xm_string = XmStringCreateSimple("Vive Alliance");
-  XtSetArg(args[0], XmNmessageString, xm_string);
-  XmStringFree(xm_string);
-  XtAppMainLoop( app );],
-AC_MSG_RESULT(yes),
-AC_MSG_RESULT(no)
-
-# try with Xintl
-AC_MSG_CHECKING([       with Xintl])
-LIBS="$OLD_LIBS -L$GUI_LIB_LOC -lXm $X_LIBS $X_EXTRA_LIBS $X_PRE_LIBS -lXintl -lXt -lX11"
-CFLAGS="$OLD_CFLAGS $X_CFLAGS -I$GUI_INC_LOC"
-[
-AC_TRY_LINK([# include <Xm/Xm.h>
-# include <Xm/FileSB.h>
-# include <Xm/MessageB.h>
-# include <Xm/SelectioB.h>
-# include <Xm/SeparatoG.h>],
-[ XtAppContext app;
-  Widget toplevel;
-  XmString xm_string;
-  Arg args[1];
-  toplevel = XtVaAppInitialize(&app, "Demos", 0, 0, 0, 0, 0, 0);
-  xm_string = XmStringCreateSimple("Vive Alliance");
-  XtSetArg(args[0], XmNmessageString, xm_string);
-  XmStringFree(xm_string);
-  XtAppMainLoop( app );],
-AC_MSG_RESULT(yes); X_PRE_LIBS="$X_PRE_LIBS -lXintl",
-AC_MSG_RESULT(no)
-
-# try with Xp
-AC_MSG_CHECKING([       with Xext and Xp])
-LIBS="$OLD_LIBS -L$GUI_LIB_LOC -lXm $X_LIBS $X_EXTRA_LIBS $X_PRE_LIBS -lXext -lXp -lXt -lX11"
-CFLAGS="$OLD_CFLAGS $X_CFLAGS -I$GUI_INC_LOC"
-[
-AC_TRY_LINK([# include <Xm/Xm.h>
-# include <Xm/FileSB.h>
-# include <Xm/MessageB.h>
-# include <Xm/SelectioB.h>
-# include <Xm/SeparatoG.h>],
-[ XtAppContext app;
-  Widget toplevel;
-  XmString xm_string;
-  Arg args[1];
-  toplevel = XtVaAppInitialize(&app, "Demos", 0, 0, 0, 0, 0, 0);
-  xm_string = XmStringCreateSimple("Vive Alliance");
-  XtSetArg(args[0], XmNmessageString, xm_string);
-  XmStringFree(xm_string);
-  XtAppMainLoop( app );],
-AC_MSG_RESULT(yes); X_PRE_LIBS="$X_PRE_LIBS -lXext -lXp",
-AC_MSG_RESULT(ERROR: BAD Motif/LessTif environment)
-)])])
-
-LIBS=$OLD_LIBS
-CFLAGS=$OLD_CFLAGS
-
-
-dnl ##### Check for libXpm.
-
-XPM_CFLAGS_LOC=""
-XPM_LIBS_LOC="-lXpm"
-
-OLD_LIBS=$LIBS
-OLD_CFLAGS=$CFLAGS
-LIBS="$OLD_LIBS $XPM_LIBS_LOC $X_LIBS $X_EXTRA_LIBS $X_PRE_LIBS -lXt -lX11"
-CFLAGS="$OLD_CFLAGS $X_CFLAGS $XPM_CFLAGS_LOC"
-AC_MSG_CHECKING(for libXpm)
-AC_TRY_LINK([#include <stdio.h>
-#include <stdlib.h>
-#include <X11/xpm.h>],
-[ XpmWriteFileFromPixmap( NULL, NULL, NULL, NULL, NULL );],
-AC_MSG_RESULT(yes); AUTO_HAS="$AUTO_HAS -DAUTO_HAS_XPM",
-AC_MSG_RESULT(no);XPM_CFLAGS_LOC="" ; XPM_LIBS_LOC=""
-)
-LIBS=$OLD_LIBS
-CFLAGS=$OLD_CFLAGS
-
-AC_SUBST(XPM_LIBS_LOC)
-AC_SUBST(XPM_CFLAGS_LOC)
-
-# Check where usefull GNU libs are installed (readline)
-#AC_CHECK_LIB(readline, main, $TRUE,
-#AC_MSG_WARN(Cannot find readline library), -ltermcap )
-
-
-# Check for readline include
-
-SKIP_GNU=
-if test -z "$SKIP_GNU"; then
-  gnu_includes="`echo $LD_LIBRARY_PATH | sed 's/:/ /g' | sed 's/lib/include/g'` /usr/local/include /usr/include $GNUHOME/include $GNU_INC_LOC"
-  AC_MSG_CHECKING(for location of GNU readline include)
-  GNU_INC_LOC=
-#    echo $gnu_includes
-  for try in $gnu_includes; do
-    if test -f "$try/readline/readline.h"; then
-      GNU_INC_LOC=$try
-    fi
-  done
-  if test -n "$GNU_INC_LOC"; then
-    AC_MSG_RESULT($GNU_INC_LOC)
-    test "$GNU_INC_LOC" = /usr/include && GNU_INC_LOC=.
-  else
-    AC_MSG_RESULT(not found.)
-    SKIP_GNU=YES
-  fi
-fi
-
-# Check for readline library
-
-if test -z "$SKIP_GNU"; then
-  gnu_libs="`echo $LD_LIBRARY_PATH | sed 's/:/ /g'` `echo "$GNU_INC_LOC" | sed 's/include/lib/'` /usr/local/lib /usr/lib $GNUHOME/lib $GNU_LIB_LOC"
-  AC_MSG_CHECKING(for location of GNU libs)
-  GNU_LIB_LOC=
-#    echo $gnu_libs
-  for try in $gnu_libs; do
-    if test -f "$try/libreadline.a" ; then
-      GNU_LIB_LOC=$try
-    fi
-  done
-  if test -n "$GNU_LIB_LOC"; then
-    AC_MSG_RESULT($GNU_LIB_LOC)
-  else
-    AC_MSG_RESULT(not found. Please install readline and add lib to your LD_LIBRARY_PATH )
-    SKIP_GNU=YES
-  fi
-fi
-
-AC_SUBST(GNU_INC_LOC)
-AC_SUBST(GNU_LIB_LOC)
-
-
-################################################################### Headers...
-AC_STDC_HEADERS
-
-#AC_CHECK_SIZEOF(int)
-
-#AC_CHECK_SIZEOF(void *)
-
-#AC_MSG_RESULT([kernel name : "$KERNEL_FILE"])
-
-################################################################### OS specific...
-
-vfork=vfork
-AC_FUNC_VFORK 
-AC_MSG_CHECKING(AUTO_HAS_VFORK)
-if test $vfork = fork; then
-AC_MSG_RESULT(no)
-else
-AC_MSG_RESULT(yes)
-AUTO_HAS="$AUTO_HAS -DAUTO_HAS_VFORK"
-fi
-
-AC_MSG_CHECKING(AUTO_HAS_SA_RESTART)
-AC_TRY_LINK([#include <stdio.h>
-#include <stdlib.h>
-#include <signal.h>],
-[struct sigaction sgct;
-sgct.sa_flags    = SA_RESTART;
-sigaction( SIGCHLD, &sgct , NULL );],
-AC_MSG_RESULT(yes); AUTO_HAS="$AUTO_HAS -DAUTO_HAS_SA_RESTART",
-AC_MSG_RESULT(no))
-
-AC_MSG_CHECKING(AUTO_HAS_DRAND48)
-AC_TRY_LINK([#include <stdio.h>
-#include <stdlib.h>],
-[  double     Proba;
-   Proba    = drand48();],
-AC_MSG_RESULT(yes); AUTO_HAS="$AUTO_HAS -DAUTO_HAS_DRAND48",
-AC_MSG_RESULT(no))
-
-AC_MSG_CHECKING(AUTO_HAS_VALUES_H)
-AC_TRY_LINK([#include <stdio.h>
-#include <stdlib.h>
-#include <values.h>],
-[  float     Proba;
-   Proba   = MAXFLOAT;],
-AC_MSG_RESULT(yes); AUTO_HAS="$AUTO_HAS -DAUTO_HAS_VALUES_H",
-AC_MSG_RESULT(no))
-
-AC_SUBST(AUTO_HAS)
-
-#fi # SKIPTEST
-    
-################################################################### Alliance ALLIANCE_TOP
-AC_MSG_CHECKING(where the Alliance package was installed)
-# Avoid problems with soft links and builtin pwd...
-ALLIANCE_TOP=`$PWDBIN | sed 's§share/etc$§archi§'`
-ALLIANCE_TOP=`echo $ALLIANCE_TOP | sed 's§archi/Cygwin/etc$§archi§'`
-
-export ALLIANCE_TOP
-AC_MSG_RESULT("")
-AC_SUBST(ALLIANCE_TOP)
-
-DATE=`date`
-AC_SUBST(DATE)
-
-HOST=`uname -a`
-AC_SUBST(HOST)
-
-# create output files
-
-AC_OUTPUT(alliance_os.mk alc_env.sh alc_env.csh alc_env.bat)
-
-mv alliance_os.mk $ALLIANCE_OS.mk
-chmod +x alc_env.sh alc_env.csh alc_env.bat
-
-# remove  config cache
-rm -f config.cache
-
-#cat config.status | grep '^s%' | sed -e 's/^s%@//' -e 's/@%/ /' -e 's/%g$//' | sort | gawk '{printf("%-30s",$1) ; for (i=2 ; i<=NF ; i++) printf("%s ", $i); printf ("\n");}'
-
-cat << EOF
-Done...
-Alliance is installed on $ALLIANCE_TOP/$ALLIANCE_OS
-OS definitions are in $ALLIANCE_OS.mk
-You'll need to 'source alc_env.csh'
-or '. alc_env.sh' whether you use csh or sh"
-EOF
-
-# end of configure
diff --git a/alliance/share/etc/cvsrmlist.txt b/alliance/share/etc/cvsrmlist.txt
deleted file mode 100644
index c57f469a..00000000
--- a/alliance/share/etc/cvsrmlist.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-a virer !!!!!
-mais cmos_12.dreal
-n'existe pas
-
-cmos_10.rds
-cmos_11.genview
-cmos_11.graal
-cmos_11.rds
-cmos_7.dreal
-cmos_7.genview
-cmos_7.graal
-cmos_7.rds
-cmos_7.rds.1999.09.30
-cmos_8.graal
-cmos_8.rds
-cmos_9.graal
-cmos_9.rds
-prol05.elp
-prol05.rds
-prol10_11.rds
-prol10_7.rds
-prol10_8.rds
-prol10.elp
-ecpd07.elp
-ecpd10.elp
-ecpd12.elp
-hcmos05.elp
-
diff --git a/alliance/share/etc/ecpd07.elp b/alliance/share/etc/ecpd07.elp
deleted file mode 100644
index e69de29b..00000000
diff --git a/alliance/share/etc/ecpd10.elp b/alliance/share/etc/ecpd10.elp
deleted file mode 100644
index e69de29b..00000000
diff --git a/alliance/share/etc/ecpd12.elp b/alliance/share/etc/ecpd12.elp
deleted file mode 100644
index e69de29b..00000000
diff --git a/alliance/share/etc/hcmos05.elp b/alliance/share/etc/hcmos05.elp
deleted file mode 100644
index e69de29b..00000000
diff --git a/alliance/share/etc/libraries.mk b/alliance/share/etc/libraries.mk
deleted file mode 100644
index c24b5bd9..00000000
--- a/alliance/share/etc/libraries.mk
+++ /dev/null
@@ -1,437 +0,0 @@
-# ###---------------------------------------------------------###
-# file          : libraries.mk                                  #
-# description   : Alliance Shared Libraries and Include Files   #
-# ###---------------------------------------------------------###
-
-# $Id: libraries.mk,v 1.36 2002/02/26 13:42:50 czo Exp $
-
-# The variables $ALLIANCE_TOP and $ALLIANCE_OS are set by
-# alc_env.[c]sh script
-
-# ###---------------------------------------------------------###
-#    Common settings                                            #
-# ###---------------------------------------------------------###
-
-ALLIANCE_VERSION = '"4.9.4"'
-ALLIANCE_BIN     = $(ALLIANCE_TOP)/bin
-ALLIANCE_LIB     = $(ALLIANCE_TOP)/lib
-ALLIANCE_INCLUDE = $(ALLIANCE_TOP)/include
-ALLIANCE_CELLS   = $(ALLIANCE_TOP)/cells
-ALLIANCE_ETC     = $(ALLIANCE_TOP)/etc
-
-# distrib path is now set by make command line
-# when building alliance distrib (./build)
-#ALLIANCE_INSTALL_DIR     = $(ALLIANCE_TOP)
-# develloppers path
-ALLIANCE_INSTALL_DIR     = $(HOME)/labo/$(ALLIANCE_OS)
-
-TARGET_BIN       = $(ALLIANCE_INSTALL_DIR)/bin
-TARGET_LIB       = $(ALLIANCE_INSTALL_DIR)/lib
-TARGET_INCLUDE   = $(ALLIANCE_INSTALL_DIR)/include
-
-# ###---------------------------------------------------------###
-#    general purpose utilities                                  #
-# ###---------------------------------------------------------###
-
-MUT_L      =  -lMut325
-MUT_LIB    = libMut325.a
-MUT_H      =    mut325.h
-
-# ###---------------------------------------------------------###
-#    functions related to cone net-list representation :        #
-#                                                               #
-#      - cns : cone net_list                                    #
-#      - yag : cone extractor form transistor net-list          #
-# ###---------------------------------------------------------###
-
-CNS_L      =  -lCns211
-CNS_LIB    = libCns211.a
-CNS_H      =    cns211.h
-
-YAG_L      =  -lYag350
-YAG_LIB    = libYag350.a
-YAG_H      =    yag350.h
-
-# ###---------------------------------------------------------###
-#    functions related to net-list representation :             #
-#                                                               #
-#      - rcn : data structures for resistor representation      #
-#      - mlo : basic data structures                            #
-#                                                               #
-#      - mal : parser & driver for Al format                    #
-#      - mcl : parser & driver for COMPASS net-lists            #
-#      - mel : parser & driver for EDIF                         #
-#      - mgl :          driver for VERILOG net-lists            #
-#      - mhl :          driver for GHDL net-list                #
-#      - msl : parser & driver for SPICE                        #
-#      - mvl : parser & driver for VHDL net-lists               #
-#                                                               #
-#      - mlu : user level functions                             #
-# ###---------------------------------------------------------###
-
-
-RCN_L      =  -lRcn200
-RCN_LIB    = libRcn200.a
-RCN_H      =    rcn200.h
-
-MLO_L      =  -lMlo502
-MLO_LIB    = libMlo502.a
-MLO_H      =    mlo502.h
-
-MAL_L      =  -lMal603
-MAL_LIB    = libMal603.a
-
-MCL_L      =  -lMcl413
-MCL_LIB    = libMcl413.a
-
-MEL_L      =  -lMel407
-MEL_LIB    = libMel407.a
-
-MHL_L      =  -lMhl403
-MHL_LIB    = libMhl403.a
-
-MGL_L      =  -lMgl100
-MGL_LIB    = libMgl100.a
-
-MSL_L      =  -lMsl700
-MSL_LIB    = libMsl700.a
-MSL_H      =    msl700.h
-
-MVL_L      =  -lMvl409
-MVL_LIB    = libMvl409.a
-
-MLU_L      =  -lMlu502
-MLU_LIB    = libMlu502.a
-MLU_H      =    mlu502.h
-
-# ###---------------------------------------------------------###
-#    functions related to symbolic layout representation :      #
-#                                                               #
-#      - mph : basic data structures                            #
-#                                                               #
-#      - map : parser & driver for AP format                    #
-#      - mcp : parser & driver for COMPASS Compose layout       #
-#      - mmg : parser & driver for MODGEN                       #
-#                                                               #
-#      - mpu : user level functions                             #
-# ###---------------------------------------------------------###
-
-MPH_L      =  -lMph413
-MPH_LIB    = libMph413.a
-MPH_H      =    mph413.h
-
-MAP_L      =  -lMap408
-MAP_LIB    = libMap408.a
-MCP_L      =  -lMcp409
-MCP_LIB    = libMcp409.a
-MMG_L      =  -lMmg403
-MMG_LIB    = libMmg403.a
-
-MPU_L      =  -lMpu408
-MPU_LIB    = libMpu408.a
-MPU_H      =    mpu408.h
-
-# ###---------------------------------------------------------###
-#    user level functions for GENLIB                            #
-# ###---------------------------------------------------------###
-
-MGN_L      =  -lMgn330
-MGN_LIB    = libMgn330.a
-MGN_H      =    mgn330.h
-
-# ###---------------------------------------------------------###
-#    functions related to expression representation :           #
-#                                                               #
-#      - aut : utilites                                         #
-#      - abl : lisp-like trees                                  #
-#      - bdd : binary decision diagram                          #
-#      - gef : factorized expression representation             # 
-# ###---------------------------------------------------------###
-
-AUT_L      =  -lAut103
-AUT_LIB    = libAut103.a
-AUT_H      =    aut103.h
-
-ABL_L      =  -lAbl103
-ABL_LIB    = libAbl103.a
-ABL_H      =    abl103.h
-
-BDD_L      =  -lBdd105
-BDD_LIB    = libBdd105.a
-BDD_H      =    bdd105.h
-
-# attention il s'agit de la lib luc
-# ne pas utiliser avec aut abl bdd : utiliser log102...
-
-LOG_L      =  -llog201
-LOG_LIB    = liblog201.a
-LOG_H      =    log201.h
-
-# ###---------------------------------------------------------###
-#    functions related to another behavioural representation :  #
-#                                                               #
-#      - abe : basic data structures                            #
-#      - abt : high level functions                             #
-#      - abv : parser & driver for Data-Flow VHDL and user      #
-#              level functions                                  #
-# ###---------------------------------------------------------###
-
-ABE_L      =  -lAbe201
-ABE_LIB    = libAbe201.a
-ABE_H      =    abe201.h
-ABT_L      =  -lAbt201
-ABT_LIB    = libAbt201.a
-ABT_H      =    abt201.h
-ABV_L      =  -lAbv201
-ABV_LIB    = libAbv201.a
-ABV_H      =    abv201.h
-
-# ###---------------------------------------------------------###
-#    functions related to simulation scheduler :                #
-#                                                               #
-#      - sch : simulation scheduler                             #
-# ###---------------------------------------------------------###
-
-SCH_L      =  -lSch110
-SCH_LIB    = libSch110.a
-SCH_H      =    sch110.h
-
-# ###---------------------------------------------------------###
-#    functions related to schematic :                           #
-#                                                               #
-#      - scl : Schematic Library                                #
-# ###---------------------------------------------------------###
-
-SCL_L      =  -lScl105
-SCL_LIB    = libScl105.a
-SCL_H      =    scl105.h
-
-# ###---------------------------------------------------------###
-#    functions related to behavioural representation :          #
-#                                                               #
-#      - beh : basic data structures                            #
-#      - cst : chain-like set treatment                         #
-#      - bhl : high level functions                             #
-#      - bvl : parser & driver for Data-Flow VHDL and user      #
-#              level functions                                  #
-# ###---------------------------------------------------------###
-
-BEH_L      =  -lBeh111
-BEH_LIB    = libBeh111.a
-BEH_H      =    beh111.h
-CST_L      =  -lCst100
-CST_LIB    = libCst100.a
-CST_H      =    cst100.h
-BHL_L      =  -lBhl111
-BHL_LIB    = libBhl111.a
-BHL_H      =    bhl111.h
-BVL_L      =  -lBvl114
-BVL_LIB    = libBvl114.a
-BVL_H      =    bvl114.h
-
-# ###---------------------------------------------------------###
-#    functions related to finite state machine representation : #
-#                                                               #
-#       - fsm : basic data structures                           #
-#       - fbh : intermediate data structures                    #
-#                                                               #
-#       - fvh : VHDL parser                                     #
-#       - fks : KISS parser                                     #
-# ###---------------------------------------------------------###
-
-FSM_L      =  -lFsm104
-FSM_LIB    = libFsm104.a
-FSM_H      =    fsm104.h
-
-FVH_L      =  -lFvh104
-FVH_LIB    = libFvh104.a
-FVH_H      =    fvh104.h
-FKS_L      =  -lFks104
-FKS_LIB    = libFks104.a
-FKS_H      =    fks104.h
-
-FTL_L      =  -lFtl104
-FTL_LIB    = libFtl104.a
-FTL_H      =    ftl104.h
-
-# ###---------------------------------------------------------###
-#    functions related to simulation patterns representation :  #
-#                                                               #
-#      - pat : basic data structures                            #
-#      - phl : high level functions                             #
-#      - ppt : parser & driver for PAT format and user level    #
-#              functions                                        #
-#      - pgn : user level functions for GENPAT                  #
-# ###---------------------------------------------------------###
-
-PAT_L      =  -lPat109
-PAT_LIB    = libPat109.a
-PAT_H      =    pat109.h
-PHL_L      =  -lPhl109
-PHL_LIB    = libPhl109.a
-PHL_H      =    phl109.h
-PPT_L      =  -lPpt109
-PPT_LIB    = libPpt109.a
-PPT_H      =    ppt109.h
-PGN_L      =  -lPgn103
-PGN_LIB    = libPgn103.a
-PGN_H      =    Pgn102.h
-
-# ###---------------------------------------------------------###
-#    functions related to physical (micron) layout :            #
-#                                                               #
-#      - rds : basic data structures                            #
-#      - rut : user level functions                             #
-#                                                               #
-#      - rdf : parser & driver for CIF format                   #
-#      - rgs : parser & driver for GDSII format                 #
-#      - rfm : physical layout from symbolic layout             #
-#      - rpr : parser for technology file                       #
-#      - rwi : windowing functions                              #
-#                                                               #
-#      - rtl : user level functions                             #
-# ###---------------------------------------------------------###
-
-RDS_L      =  -lRds210
-RDS_LIB    = libRds210.a
-RDS_H      =    rds210.h
-
-RUT_L      =  -lRut209
-RUT_LIB    = libRut209.a
-RUT_H      =    rut209.h
-
-RCF_L      =  -lRcf112
-RCF_LIB    = libRcf112.a
-RFM_L      =  -lRfm212
-RFM_LIB    = libRfm212.a
-RFM_H      =    rfm212.h
-RGS_L      =  -lRgs113
-RGS_LIB    = libRgs113.a
-RPR_L      =  -lRpr214
-RPR_LIB    = libRpr214.a
-RPR_H      =    rpr214.h
-RWI_L      =  -lRwi110
-RWI_LIB    = libRwi110.a
-RWI_H      =    rwi110.h
-
-RTL_L      =  -lRtl111
-RTL_LIB    = libRtl111.a
-RTL_H      =    rtl111.h
-
-# ###---------------------------------------------------------###
-#    functions related to icon representation :                 #
-#                                                               #
-#      - icn : basic data structures                            #
-#                                                               #
-#      - ica : parser & driver for Alliance icon format         #
-#      - icc : parser & driver for Compass  icon format         #
-#                                                               #
-#      - icu : user level functions                             #
-# ###---------------------------------------------------------###
-
-ICN_L      =  -lIcn201
-ICN_LIB    = libIcn201.a
-ICN_H      =    icn201.h
-
-IAC_H      =    iac201.h
-
-ICA_L      =  -lIca201
-ICA_LIB    = libIca201.a
-ICC_L      =  -lIcc201
-ICC_LIB    = libIcc201.a
-
-ICU_L      =  -lIcu201
-ICU_LIB    = libIcu201.a
-ICU_H      =    icu201.h
-
-# ###---------------------------------------------------------###
-#    functions related to portable blocks generators :          #
-#                                                               #
-#      - gbs : barrel shifter                                   #
-#      - gga : fast adder                                       #
-#      - ggr : rom                                              #
-#      - grf : register file                                    #
-#      - gam : array pipelined multiplier                       #
-#      - gfp : data path simple operators                       #
-# ###---------------------------------------------------------###
-
-GBS_L      =  -lGbs201
-GBS_LIB    = libGbs201.a
-GBS_H      =    gbs201.h
-
-GGA_L      =  -lGga301
-GGA_LIB    = libGga301.a
-GGA_H      =    gga301.h
-
-GGR_L      =  -lGgr001
-GGR_LIB    = libGgr001.a
-GGR_H      =    ggr001.h
-
-GRF_L      =  -lGrf605
-GRF_LIB    = libGrf605.a
-GRF_H      =    grf605.h
-
-GAM_L      =  -lGam000
-GAM_LIB    = libGam000.a
-GAM_H      =    gam000.h
-
-GFP_L      =  -lGfp116
-GFP_LIB    = libGfp116.a
-GFP_H      =    gfp116.h
-
-# ###---------------------------------------------------------###
-#    place & route functions                                    #
-# ###---------------------------------------------------------###
-
-APR_L      =  -lApr103
-APR_LIB    = libApr103.a
-APR_H      =    apr103.h
-
-# ###---------------------------------------------------------###
-#    design rule checker functions                              #
-# ###---------------------------------------------------------###
-
-VRD_L      =  -lVrd304
-VRD_LIB    = libVrd304.a
-VRD_H      =    vrd304.h
-
-# ###---------------------------------------------------------###
-#    user level functions for FPGEN				#
-# ###---------------------------------------------------------###
-
-FGN_L      =  -lFgn116
-FGN_LIB    = libFgn116.a
-FGN_H        = Fgn115.h
-
-
-# ###---------------------------------------------------------###
-#    Timing Analysis                                            #
-#                                                               #
-#      - ttv : basic timing data structures                     #
-#                                                               #
-#      - inf : information file parser                          #
-#      - elp : electrical parameters' file parser               #
-#      - tas : static delay analysis functions                  #
-# ###---------------------------------------------------------###
-
-TTV_L      =  -lTtv110
-TTV_LIB    = libTtv110.a
-TTV_H      =    ttv110.h
-
-INF_L      =  -lInf112
-INF_LIB    = libInf112.a
-INF_H      =    inf112.h
-
-ELP_L      =  -lElp105
-ELP_LIB    = libElp105.a
-ELP_H      =    elp105.h
-
-TAS_L      =  -lTas542
-TAS_LIB    = libTas542.a
-TAS_H      =    tas542.h
-
-FCL_L      =  -lFcl110
-FCL_LIB    = libFcl110.a
-FCL_H      =    fcl110.h
-
-# end of libraries.mk
diff --git a/alliance/share/etc/multiconf b/alliance/share/etc/multiconf
deleted file mode 100755
index c2eb9d1c..00000000
--- a/alliance/share/etc/multiconf
+++ /dev/null
@@ -1,37 +0,0 @@
-#! /bin/sh
-#
-# Author      : Olivier.Sirol@lip6.fr
-# Date        : dec 1998
-# Description : 
-#
-# (C) Czo 1998,99
-# This code is released under GPL
-# $Id: multiconf,v 1.2 2001/05/18 14:37:16 czo Exp $
-#
-
-
-# I made this script to build alliance on multiple architectures
-# Modify it to suit you site
-
-# TODO : change this to a makefile...
-
-#set +x
-#set -x
-
-TMPFILE=/tmp/albuild.$$
-
-ALLIANCEDIR=`pwd`
-
-for WKS in beny bip
-
-do
-echo "Configuring $WKS..."
-ssh -n $WKS "cd $ALLIANCEDIR; ./configure"  2>&1 | tee $TMPFILE
-grep "^or .*whether you use csh or sh" $TMPFILE
-if [ $? -ne 0 ] ; then echo "Error, $WKS, exiting" ; exit 4 ; fi
-rm $TMPFILE
-done
-
-echo "done..."
-echo "###########   O K pour tout le monde   #############"
-
diff --git a/alliance/share/etc/prol035.elp b/alliance/share/etc/prol035.elp
deleted file mode 100644
index 92ddb79c..00000000
--- a/alliance/share/etc/prol035.elp
+++ /dev/null
@@ -1,56 +0,0 @@
-#TAS PARAMETER FILE
-
-Technologie : prol035 Version : 1.0
-
-#Reference Simulator
-ESIM  = eldo
-MODEL = MOS
-LEVEL = 59
-
-#shrink parameters (micron)
-DLN = 0.026
-DLP = -0.038
-DWN = -0.20
-DWP = -0.13
-
-#transistor characteristics
-#NMOS
-VTN = 0.6
-BN  = 1.4
-AN  = 0.00010
-RNT = 10400
-
-#PMOS
-VTP = 0.58
-BP  = 0.56
-AP  = 2.0e-05
-RPT = 29000
-
-#general parameters
-VDDmax = 2.7
-VTHR   = 1.35
-VSSdeg = 0.77
-VDDdeg = 2
-TEMP   = 85
-
-#dynamic capacitance: grid capacitance (in pF/u and pF/u2)
-CGSN = 0.0032
-CGSP = 0.0032
-CGPN = 0.00016
-CGPP = 0.00014
-
-#dynamic capacitance: drain capacitance (in pF/u and pF/u2)
-CDSN = 0.00083
-CDSP = 0.00036
-CDPN = 0.00026
-CDPP = 0.00036
-CDWN = 0.00018
-CDWP = 0.00022
-
-#dynamic capacitance: source capacitance (in pF/u and pF/u2)
-CSSN = 0.00083
-CSSP = 0.00036
-CSPN = 0.00026
-CSPP = 0.00036
-CSWN = 0.00018
-CSWP = 0.00022
diff --git a/alliance/share/etc/prol035.rds b/alliance/share/etc/prol035.rds
deleted file mode 100644
index ba788615..00000000
--- a/alliance/share/etc/prol035.rds
+++ /dev/null
@@ -1,324 +0,0 @@
-DEFINE PHYSICAL_GRID    0.025
-
-DEFINE LAMBDA           0.300
-
-TABLE MBK_TO_RDS_SEGMENT
-
-  NWELL  RDS_NWELL VW   0.950   1.900    0.000  ALL
-  PWELL  RDS_PWELL VW   0.950   1.900    0.000  ALL
-  NDIF   RDS_NDIF  VW   0.100  -0.100    0.000  EXT\
-         RDS_ACTIV VW   0.100  -0.100    0.000  DRC\
-         RDS_NIMP  VW   0.400   0.500    0.000  DRC\
-         RDS_PWELL VW   1.200   2.100    0.000  DRC  
-  PDIF   RDS_PDIF  VW   0.100  -0.100    0.000  EXT\
-         RDS_ACTIV VW   0.100  -0.100    0.000  DRC\
-         RDS_PIMP  VW   0.400   0.500    0.000  DRC\
-         RDS_NWELL VW   1.200   2.100    0.000  DRC  
-  NTIE   RDS_NTIE  VW   0.100  -0.100    0.000  EXT\
-         RDS_ACTIV VW   0.100  -0.100    0.000  DRC\
-         RDS_NIMP  VW   0.400   0.500    0.000  EXT\
-         RDS_NWELL VW   1.200   2.100    0.000  DRC  
-  PTIE   RDS_PTIE  VW   0.100  -0.100    0.000  EXT\
-         RDS_ACTIV VW   0.100  -0.100    0.000  DRC\
-         RDS_PIMP  VW   0.400   0.500    0.000  DRC\
-         RDS_PWELL VW   1.200   2.100    0.000  DRC  
-  NTRANS RDS_GATE  VW   0.000   0.050    0.000  EXT\
-         RDS_NDIF LCW  -0.500   0.750    0.025  EXT\
-         RDS_NDIF RCW  -0.500   0.750    0.025  EXT\
-         RDS_POLY  VW   0.000   0.050    0.000  DRC\
-         RDS_ACTIV VW  -0.500   1.350    0.000  DRC\
-         RDS_NIMP  VW  -0.200   1.950    0.000  DRC\
-         RDS_PWELL VW   0.600   3.550    0.000  ALL
-  PTRANS RDS_GATE  VW   0.000   0.050    0.000  EXT\
-         RDS_PDIF LCW  -0.500   0.750    0.025  EXT\
-         RDS_PDIF RCW  -0.500   0.750    0.025  EXT\
-         RDS_POLY  VW   0.000   0.050    0.000  DRC\
-         RDS_ACTIV VW  -0.500   1.350    0.000  DRC\
-         RDS_PIMP  VW  -0.200   1.950    0.000  DRC\
-         RDS_NWELL VW   0.600   3.550    0.000  ALL
-  POLY   RDS_POLY  VW   0.175   0.050    0.000  ALL
-  ALU1   RDS_ALU1  VW   0.300   0.300    0.000  ALL
-  ALU2   RDS_ALU2  VW   0.350   0.100    0.000  ALL
-  ALU3   RDS_ALU3  VW   0.450   0.000    0.000  ALL
-  ALU4   RDS_ALU4  VW   0.450   0.000    0.000  ALL
-  CALU1  RDS_ALU1  VW   0.300   0.300    0.000  ALL
-  CALU2  RDS_ALU2  VW   0.350   0.100    0.000  ALL
-  CALU3  RDS_ALU3  VW   0.450   0.000    0.000  ALL
-  CALU4  RDS_ALU4  VW   0.450   0.000    0.000  ALL
-END
-TABLE MBK_TO_RDS_CONNECTOR
-  POLY   RDS_POLY    0.175   0.050
-  ALU1   RDS_ALU1    0.300   0.300
-  ALU2   RDS_ALU2    0.350   0.100
-  ALU3   RDS_ALU3    0.450   0.000
-  ALU4   RDS_ALU4    0.450   0.000
-END
-TABLE MBK_TO_RDS_REFERENCE
-  REF_REF  RDS_REF   0.600
-  REF_CON  RDS_REF   0.600
-END
-TABLE MBK_TO_RDS_VIA
-  CONT_BODY_N              \
-    RDS_ALU1      0.900  ALL\
-    RDS_CONT      0.400  ALL\
-    RDS_ACTIV     0.800  DRC\
-    RDS_NIMP      1.400  DRC\
-    RDS_NWELL     3.000  DRC\
-    RDS_NTIE      0.800  EXT  
-  CONT_BODY_P              \
-    RDS_ALU1      0.900  ALL\
-    RDS_CONT      0.400  ALL\
-    RDS_ACTIV     0.800  DRC\
-    RDS_PIMP      1.400  DRC\
-    RDS_PWELL     3.000  DRC\
-    RDS_PTIE      0.800  EXT  
-  CONT_DIF_N               \
-    RDS_ALU1      0.900  ALL\
-    RDS_CONT      0.400  ALL\
-    RDS_ACTIV     0.800  DRC\
-    RDS_NIMP      1.400  DRC\
-    RDS_PWELL     3.000  DRC\
-    RDS_NDIF      0.800  EXT  
-  CONT_DIF_P               \
-    RDS_ALU1      0.900  ALL\
-    RDS_CONT      0.400  ALL\
-    RDS_ACTIV     0.800  DRC\
-    RDS_PIMP      1.400  DRC\
-    RDS_NWELL     3.000  DRC\
-    RDS_PDIF      0.800  EXT  
-  CONT_POLY                \
-    RDS_ALU1      0.900  ALL\
-    RDS_CONT      0.400  ALL\
-    RDS_POLY      0.950  ALL  
-  CONT_VIA                 \
-    RDS_ALU1      0.900  ALL\
-    RDS_VIA1      0.400  ALL\
-    RDS_ALU2      1.000  ALL  
-  CONT_VIA2                \
-    RDS_ALU2      1.000  ALL\
-    RDS_VIA2      0.400  ALL\
-    RDS_ALU3      0.900  ALL  
-  CONT_VIA3                \
-    RDS_ALU3      0.900  ALL\
-    RDS_VIA3      0.400  ALL\
-    RDS_ALU4      0.900  ALL  
-  C_X_N                    \
-    RDS_POLY      0.350  DRC\
-    RDS_ACTIV     1.650  DRC\
-    RDS_NIMP      2.250  DRC\
-    RDS_PWELL     3.850  DRC\
-    RDS_GATE      0.350  EXT\
-    RDS_NDIF      1.650  EXT  
-  C_X_P                    \
-    RDS_POLY      0.350  DRC\
-    RDS_ACTIV     1.650  DRC\
-    RDS_PIMP      2.250  DRC\
-    RDS_NWELL     3.850  DRC\
-    RDS_GATE      0.350  EXT\
-    RDS_PDIF      1.650  EXT  
-END
-TABLE CIF_LAYER 
-  RDS_NWELL    NWEL
-  RDS_POLY     POLY
-  RDS_CONT     CONTACT
-  RDS_ALU1     METAL1
-  RDS_TALU1    ?
-  RDS_VIA1     VIA1
-  RDS_ALU2     METAL2
-  RDS_TALU2    ?
-  RDS_ACTIV    ACTIVE
-  RDS_NIMP     NPLUS
-  RDS_PIMP     PPLUS
-  RDS_CPAS     PAD
-  RDS_ALU3     METAL3
-  RDS_VIA2     VIA2
-  RDS_ALU4     METAL4
-  RDS_VIA3     VIA3
-END
-TABLE GDS_LAYER
-  RDS_NWELL    1
-  RDS_POLY     13
-  RDS_CONT     19
-  RDS_ALU1     23
-  RDS_VIA1     25
-  RDS_ALU2     27
-  RDS_ACTIV    2
-  RDS_NIMP     16
-  RDS_PIMP     17
-  RDS_CPAS     31
-  RDS_ALU3     34
-  RDS_VIA2     32
-  RDS_ALU4     36
-  RDS_VIA3     35
-END
-TABLE S2R_OVERSIZE_DENOTCH
-  RDS_NWELL     0.700
-  RDS_PWELL     0.000
-  RDS_POLY      0.250
-  RDS_ALU1     -0.025
-  RDS_ALU2     -0.025
-  RDS_ACTIV     0.325
-  RDS_NIMP      0.250
-  RDS_PIMP      0.250
-  RDS_ALU3     -0.025
-  RDS_ALU4     -0.025
-END
-TABLE S2R_BLOC_RING_WIDTH
-  RDS_NWELL     1.400
-  RDS_PWELL     0.000
-  RDS_POLY      0.550
-  RDS_ALU1      0.000
-  RDS_ALU2      0.000
-  RDS_ACTIV     0.700
-  RDS_NIMP      0.500
-  RDS_PIMP      0.500
-  RDS_ALU3      0.000
-  RDS_ALU4      0.000
-END
-TABLE S2R_MINIMUM_LAYER_WIDTH 
-  RDS_NWELL     1.700
-  RDS_PWELL     1.700
-  RDS_POLY      0.350
-  RDS_ALU1      0.600
-  RDS_ALU2      0.700
-  RDS_ACTIV     0.500
-  RDS_NIMP      0.500
-  RDS_PIMP      0.500
-  RDS_ALU3      0.900
-  RDS_ALU3      0.900
-END
-TABLE S2R_POST_TREAT
-  RDS_NWELL        TREAT NULL     
-  RDS_PWELL        TREAT NULL     
-  RDS_POLY         TREAT NULL     
-  RDS_CONT       NOTREAT NULL     
-  RDS_ALU1         TREAT NULL     
-  RDS_VIA1       NOTREAT NULL     
-  RDS_ALU2         TREAT NULL     
-  RDS_ACTIV        TREAT NULL     
-  RDS_NIMP         TREAT RDS_PIMP 
-  RDS_PIMP         TREAT RDS_NIMP 
-  RDS_ABOX       NOTREAT NULL     
-  RDS_VIA2       NOTREAT NULL     
-  RDS_ALU3         TREAT NULL     
-  RDS_VIA3       NOTREAT NULL     
-  RDS_ALU4         TREAT NULL     
-END
-TABLE LYNX_TRANSISTOR
-NTRANS  NTRANS  C_X_N RDS_GATE RDS_NDIF RDS_NDIF RDS_PWELL
-PTRANS  PTRANS  C_X_P RDS_GATE RDS_PDIF RDS_PDIF RDS_NWELL
-END
-TABLE LYNX_DIFFUSION
-END
-TABLE LYNX_RESISTOR
-  RDS_POLY          6
-  RDS_ALU1      0.087
-  RDS_ALU2      0.066
-  RDS_ALU3      0.066
-  RDS_ALU3      0.066
-  RDS_ALU4      0.066
-  RDS_CONT         12
-  RDS_VIA1          4
-  RDS_VIA2          4
-  RDS_VIA3          4
-END
-TABLE LYNX_GRAPH
-
-##---------------------------
-#
-# Modifie par L.Jacomme (Pb Bulk/Alim avec Lynx)
-# 23.11.99
-#
-# RDS_NWELL  RDS_NTIE   RDS_NWELL
-# RDS_PWELL  RDS_PTIE   RDS_PWELL
-# RDS_NTIE  RDS_CONT RDS_NTIE   RDS_NWELL
-# RDS_PTIE  RDS_CONT RDS_PTIE   RDS_PWELL
-# RDS_NDIF   RDS_CONT   RDS_NDIF
-# RDS_PDIF   RDS_CONT   RDS_PDIF
-
-  RDS_NDIF  RDS_CONT RDS_NDIF
-  RDS_PDIF  RDS_CONT RDS_PDIF
-  RDS_NTIE  RDS_CONT RDS_NTIE
-  RDS_PTIE  RDS_CONT RDS_PTIE
-
-  RDS_POLY   RDS_CONT   RDS_GATE   RDS_POLY
-  RDS_GATE   RDS_POLY   RDS_GATE
-  RDS_CONT  RDS_PDIF RDS_NDIF RDS_POLY RDS_PTIE  RDS_NTIE RDS_ALU1 RDS_CONT
-  RDS_ALU1   RDS_CONT   RDS_VIA1   RDS_ALU1  RDS_REF
-  RDS_REF    RDS_CONT   RDS_VIA1   RDS_ALU1  RDS_REF
-  RDS_VIA1   RDS_ALU1   RDS_ALU2   RDS_VIA1
-  RDS_ALU2   RDS_VIA1   RDS_VIA2   RDS_ALU2
-  RDS_VIA2   RDS_ALU2   RDS_ALU3   RDS_VIA2
-  RDS_ALU3   RDS_VIA2   RDS_ALU3   RDS_VIA3
-  RDS_VIA3   RDS_ALU3   RDS_ALU4   RDS_VIA3
-  RDS_ALU4   RDS_VIA3   RDS_ALU4
-END
-TABLE LYNX_CAPA
-  RDS_POLY     0.000101  9.8e-05
-  RDS_ALU1     2.65e-05  8.6e-05
-  RDS_ALU2     1.3e-05  7.6e-05
-  RDS_ALU3     8.4e-06  6.8e-05
-  RDS_ALU4     6.2e-06  6.34e-05
-END
-##-------------------------------------------------------------------
-# TABLE LYNX_BULK_IMPLICIT :
-#
-# RDS layer  Bulk type
-# name       EXPLICIT/IMPLICIT
-##-------------------------------------------------------------------
-
-TABLE LYNX_BULK_IMPLICIT
-
-##---------------------------
-#
-# Modifie par L.Jacomme (Pb Bulk/Alim avec Lynx)
-# 23.11.99
-#
-# NWELL  EXPLICIT
-# PWELL  IMPLICIT
-
-END
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_BIGVIA_HOLE :
-#
-# MBK via      RDS Hole        
-# name         name  side step mode
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_BIGVIA_HOLE
-
-CONT_VIA   RDS_VIA1 .4 1.1 ALL
-CONT_VIA2  RDS_VIA2 .4 1.1 ALL
-
-END
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_BIGVIA_METAL :
-#
-# MBK via      RDS layer 1                      ...
-# name         name  delta-width overlap mode
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_BIGVIA_METAL
-
-CONT_VIA   RDS_ALU1 .3 .0 ALL RDS_ALU2 .1 .0 ALL
-CONT_VIA2  RDS_ALU2 .1 .0 ALL RDS_ALU3 .0 .0 ALL
-
-END 
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_TURNVIA :
-#
-# MBK via      RDS layer 1                      ...
-# name         name  delta-width overlap mode
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_TURNVIA
-
-CONT_TURN1 RDS_ALU1 .3 ALL
-CONT_TURN2 RDS_ALU2 .1 ALL
-CONT_TURN3 RDS_ALU3 .0 ALL
-
-END
-
diff --git a/alliance/share/etc/prol05.elp b/alliance/share/etc/prol05.elp
deleted file mode 100644
index d3c5e234..00000000
--- a/alliance/share/etc/prol05.elp
+++ /dev/null
@@ -1,58 +0,0 @@
-#Fichier de parametrisation de TAS, HCMOS05, LEVEL 3, ST-SPICE
-#Les parametres sont calcules en tenant compte des shrinks
-#Par DIOURY karim, le 15/06/1995
-
-Technologie : prol05 Version : 2.0
-
-#Reference Simulator
-ESIM  = ST-SPICE
-MODEL = MOS
-LEVEL = 3.0
-
-#shrink parameters (micron)
-DLN = 0.058
-DLP = 0.015
-DWN = -0.068
-DWP = -0.008
-
-#transistor characteristics
-#NMOS
-VTN = 0.709
-BN  = 1.2177
-AN  = 7.63e-5
-RNT = 13764.0
-
-#PMOS
-VTP = 0.676
-BP  = 0.3302
-AP  = 1.65e-05
-RPT = 34740.0
-
-#general parameters
-VDDmax = 3.0
-VTHR   = 1.5
-VSSdeg = 0.952
-VDDdeg = 2.05
-TEMP   = 70.0
-
-#dynamic capacitance: grid capacitance (in pF/u and pF/u2)
-CGSN = 2704.0e-6
-CGSP = 2704.0e-6
-CGPN = 430.0e-6
-CGPP = 380.0e-6
-
-#dynamic capacitance: drain capacitance (in pF/u and pF/u2)
-CDSN = 840.0e-6
-CDSP = 915.0e-6
-CDPN = 270.0e-6
-CDPP = 220.0e-6
-CDWN = 430.0e-6
-CDWP = 380.0e-6
-
-#dynamic capacitance: source capacitance (in pF/u and pF/u2)
-CSSN = 840.0e-6
-CSSP = 915.0e-6
-CSPN = 270.0e-6
-CSPP = 220.0e-6
-CSWN = 430.0e-6
-CSWP = 380.0e-6
diff --git a/alliance/share/etc/prol05.rds b/alliance/share/etc/prol05.rds
deleted file mode 100644
index c3978ae9..00000000
--- a/alliance/share/etc/prol05.rds
+++ /dev/null
@@ -1,278 +0,0 @@
-# $Id: prol05.rds,v 1.4 2000/09/14 10:28:40 syf Exp $
-
-DEFINE PHYSICAL_GRID    0.050
-
-DEFINE LAMBDA           0.500
-
-TABLE MBK_TO_RDS_SEGMENT
-
-  NWELL  RDS_NWELL VW   1.550   3.300    0.000  ALL
-  PWELL  RDS_PWELL VW   1.550   3.300    0.000  ALL
-  NDIF   RDS_NDIF  VW   0.350   0.000    0.000  EXT\
-         RDS_ACTIV VW   0.350   0.000    0.000  DRC\
-         RDS_NIMP  VW   0.850   1.000    0.000  DRC\
-         RDS_PWELL VW   2.150   3.600    0.000  DRC  
-  PDIF   RDS_PDIF  VW   0.350   0.000    0.000  EXT\
-         RDS_ACTIV VW   0.350   0.000    0.000  DRC\
-         RDS_PIMP  VW   0.850   1.000    0.000  DRC\
-         RDS_NWELL VW   2.150   3.600    0.000  DRC  
-  NTIE   RDS_NTIE  VW   0.350   0.000    0.000  EXT\
-         RDS_ACTIV VW   0.350   0.000    0.000  DRC\
-         RDS_NIMP  VW   0.850   1.000    0.000  DRC\
-         RDS_NWELL VW   2.150   3.600    0.000  DRC  
-  PTIE   RDS_PTIE  VW   0.350   0.000    0.000  EXT\
-         RDS_ACTIV VW   0.350   0.000    0.000  DRC\
-         RDS_PIMP  VW   0.850   1.000    0.000  DRC\
-         RDS_PWELL VW   2.150   3.600    0.000  DRC  
-  NTRANS RDS_POLY  VW   0.000   0.000    0.000  EXT\
-         RDS_NDIF LCW  -0.650   1.000    0.000  EXT\
-         RDS_NDIF RCW  -0.650   1.000    0.000  EXT\
-         RDS_POLY  VW   0.000   0.000    0.000  DRC\
-         RDS_ACTIV VW  -0.650   2.000    0.000  DRC\
-         RDS_NIMP  VW  -0.150   3.000    0.000  DRC\
-         RDS_PWELL VW   1.150   5.600    0.000  ALL
-  PTRANS RDS_POLY  VW   0.000   0.000    0.000  EXT\
-         RDS_PDIF LCW  -0.650   1.000    0.000  EXT\
-         RDS_PDIF RCW  -0.650   1.000    0.000  EXT\
-         RDS_POLY  VW   0.000   0.000    0.000  DRC\
-         RDS_ACTIV VW  -0.650   2.000    0.000  DRC\
-         RDS_PIMP  VW  -0.150   3.000    0.000  DRC\
-         RDS_NWELL VW   1.150   5.600    0.000  ALL
-  POLY   RDS_POLY  VW   0.250   0.000    0.000  ALL
-  ALU1   RDS_ALU1  VW   0.400   0.300    0.000  ALL
-  ALU2   RDS_ALU2  VW   0.500   0.000    0.000  ALL
-  ALU3   RDS_ALU3  VW   0.650  -0.200    0.000  ALL
-  CALU1   RDS_ALU1  VW   0.400   0.300    0.000  ALL
-  CALU2   RDS_ALU2  VW   0.500   0.000    0.000  ALL
-  CALU3   RDS_ALU3  VW   0.650  -0.200    0.000  ALL
-END
-TABLE MBK_TO_RDS_CONNECTOR
-  POLY   RDS_POLY    0.250   0.000
-  ALU1   RDS_ALU1    0.400   0.300
-  ALU2   RDS_ALU2    0.500   0.000
-  ALU3   RDS_ALU3    0.650  -0.200
-END
-TABLE MBK_TO_RDS_REFERENCE
-  REF_REF  RDS_REF   0.800
-  REF_CON  RDS_REF   0.800
-END
-TABLE MBK_TO_RDS_VIA
-  CONT_BODY_N              \
-    RDS_ALU1      1.300  ALL\
-    RDS_CONT      0.600  ALL\
-    RDS_ACTIV     1.500  DRC\
-    RDS_NIMP      2.500  DRC\
-    RDS_NWELL     5.100  DRC\
-    RDS_NTIE      1.500  EXT  
-  CONT_BODY_P              \
-    RDS_ALU1      1.300  ALL\
-    RDS_CONT      0.600  ALL\
-    RDS_ACTIV     1.500  DRC\
-    RDS_PIMP      2.500  DRC\
-    RDS_PWELL     5.100  DRC\
-    RDS_PTIE      1.500  EXT  
-  CONT_DIF_N               \
-    RDS_ALU1      1.300  ALL\
-    RDS_CONT      0.600  ALL\
-    RDS_ACTIV     1.500  DRC\
-    RDS_NIMP      2.500  DRC\
-    RDS_PWELL     5.100  DRC\
-    RDS_NDIF      1.500  EXT  
-  CONT_DIF_P               \
-    RDS_ALU1      1.300  ALL\
-    RDS_CONT      0.600  ALL\
-    RDS_ACTIV     1.500  DRC\
-    RDS_PIMP      2.500  DRC\
-    RDS_NWELL     5.100  DRC\
-    RDS_PDIF      1.500  EXT  
-  CONT_POLY                \
-    RDS_ALU1      1.300  ALL\
-    RDS_CONT      0.600  ALL\
-    RDS_POLY      1.500  ALL  
-  CONT_VIA                 \
-    RDS_ALU1      1.300  ALL\
-    RDS_VIA1      0.600  ALL\
-    RDS_ALU2      1.500  ALL  
-  CONT_VIA2                \
-    RDS_ALU2      1.500  ALL\
-    RDS_VIA2      0.700  ALL\
-    RDS_ALU3      1.500  ALL  
-  C_X_N                    \
-    RDS_POLY      0.500  DRC\
-    RDS_ACTIV     2.500  DRC\
-    RDS_NIMP      3.500  DRC\
-    RDS_PWELL     6.100  DRC\
-    RDS_POLY      0.500  EXT\
-    RDS_NDIF      2.500  EXT  
-  C_X_P                    \
-    RDS_POLY      0.500  DRC\
-    RDS_ACTIV     2.500  DRC\
-    RDS_PIMP      3.500  DRC\
-    RDS_NWELL     6.100  DRC\
-    RDS_POLY      0.500  EXT\
-    RDS_PDIF      2.500  EXT  
-END
-TABLE CIF_LAYER 
-  RDS_NWELL    NWELL
-  RDS_PWELL    PWELL
-  RDS_POLY     POLYSILICON
-  RDS_CONT     CONTACTS
-  RDS_ALU1     METAL1
-  RDS_VIA1     VIA1
-  RDS_ALU2     METAL2
-  RDS_ACTIV    ACTIVEAREA
-  RDS_PIMP     PIMPLANT
-  RDS_NIMP     NIMPLANT
-  RDS_CPAS     NITRIDE
-  RDS_ALU3     METAL3
-  RDS_VIA2     VIA2
-END
-
-TABLE GDS_LAYER
-  RDS_NWELL    1
-  RDS_POLY     13
-  RDS_CONT     19
-  RDS_ALU1     23
-  RDS_VIA1     25
-  RDS_ALU2     27
-  RDS_ACTIV    2
-  RDS_PIMP     17
-  RDS_CPAS     31
-  RDS_ALU3     34
-  RDS_VIA2     32
-END
-TABLE S2R_OVERSIZE_DENOTCH
-  RDS_NWELL     1.500
-  RDS_PWELL     1.500
-  RDS_POLY      0.350
-  RDS_ALU1      0.350
-  RDS_ALU2      0.400
-  RDS_ACTIV     0.500
-  RDS_NIMP      0.400
-  RDS_PIMP      0.400
-  RDS_ALU3      0.550
-END
-TABLE S2R_BLOC_RING_WIDTH
-  RDS_NWELL     3.000
-  RDS_PWELL     3.000
-  RDS_POLY      0.800
-  RDS_ALU1      0.800
-  RDS_ALU2      0.900
-  RDS_ACTIV     1.100
-  RDS_NIMP      0.800
-  RDS_PIMP      0.800
-  RDS_ALU3      1.200
-END
-TABLE S2R_MINIMUM_LAYER_WIDTH 
-  RDS_NWELL     2.400
-  RDS_PWELL     2.400
-  RDS_POLY      0.500
-  RDS_ALU1      0.800
-  RDS_ALU2      1.000
-  RDS_ACTIV     0.800
-  RDS_NIMP      0.800
-  RDS_PIMP      0.800
-  RDS_ALU3      1.300
-END
-TABLE S2R_POST_TREAT
-  RDS_NWELL        TREAT NULL     
-  RDS_PWELL      NOTREAT NULL     
-  RDS_POLY         TREAT NULL     
-  RDS_CONT       NOTREAT NULL     
-  RDS_ALU1         TREAT NULL     
-  RDS_VIA1       NOTREAT NULL     
-  RDS_ALU2         TREAT NULL     
-  RDS_ACTIV        TREAT NULL     
-  RDS_NIMP         TREAT RDS_PIMP 
-  RDS_PIMP         TREAT RDS_NIMP 
-  RDS_ABOX       NOTREAT NULL     
-  RDS_VIA2       NOTREAT NULL     
-  RDS_ALU3         TREAT NULL     
-END
-TABLE LYNX_TRANSISTOR
-NTRANS  NTRANS  C_X_N RDS_POLY RDS_NDIF RDS_ACTIV RDS_PWELL
-PTRANS  PTRANS  C_X_P RDS_POLY RDS_PDIF RDS_ACTIV RDS_NWELL
-END
-
-##-------------------------------------------------------------------
-# TABLE LYNX_BULK_IMPLICIT :
-#
-# RDS layer  Bulk type
-# name       EXPLICIT/IMPLICIT
-##-------------------------------------------------------------------
-
-TABLE LYNX_BULK_IMPLICIT
-  NWELL  EXPLICIT
-  PWELL  IMPLICIT
-END
-
-TABLE LYNX_GRAPH
-  RDS_NWELL RDS_NTIE RDS_NWELL
-  RDS_PWELL RDS_PTIE RDS_PWELL
-  RDS_NTIE  RDS_CONT RDS_NTIE   RDS_NWELL
-  RDS_PTIE  RDS_CONT RDS_PTIE   RDS_PWELL
-  RDS_NDIF  RDS_CONT RDS_NDIF
-  RDS_PDIF  RDS_CONT RDS_PDIF
-  RDS_POLY  RDS_CONT RDS_POLY
-  RDS_CONT  RDS_PDIF RDS_NDIF RDS_POLY RDS_PTIE RDS_NTIE RDS_ALU1 RDS_CONT
-  RDS_ALU1  RDS_CONT RDS_VIA1 RDS_ALU1 RDS_REF
-  RDS_REF   RDS_CONT RDS_VIA1 RDS_ALU1 RDS_REF
-  RDS_VIA1  RDS_ALU1 RDS_ALU2 RDS_VIA1
-  RDS_ALU2  RDS_VIA1 RDS_VIA2 RDS_ALU2
-  RDS_VIA2  RDS_ALU2 RDS_ALU3 RDS_VIA2
-  RDS_ALU3  RDS_VIA2 RDS_ALU3
-END
-TABLE LYNX_CAPA
-  RDS_POLY     8.3e-05 10.0e-05
-  RDS_ALU1     3.2e-05  9.2e-05
-  RDS_ALU2     2.2e-05  8.4e-05
-  RDS_ALU3     1.6e-05  8.4e-05 
-END
-TABLE LYNX_RESISTOR
-END
-TABLE LYNX_DIFFUSION
-  RDS_PDIF  RDS_ACTIV 1 RDS_PIMP 1 RDS_NWELL 1
-  RDS_PTIE  RDS_ACTIV 1 RDS_PIMP 1 RDS_PWELL 1
-  RDS_NDIF  RDS_ACTIV 1 RDS_NIMP 1 RDS_PWELL 1
-  RDS_NTIE  RDS_ACTIV 1 RDS_NIMP 1 RDS_NWELL 1
-END
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_BIGVIA_HOLE :
-#
-# MBK via      RDS Hole        
-# name         name  side step mode
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_BIGVIA_HOLE
-
-# CONT_VIA  RDS_VIA1 1 2 ALL
-
-END
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_BIGVIA_METAL :
-#
-# MBK via      RDS layer 1                      ...
-# name         name  delta-width overlap mode
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_BIGVIA_METAL
-
-# CONT_VIA  RDS_ALU1 3 4 ALL RDS_ALU2 4 5 ALL
-
-END 
-
-##-------------------------------------------------------------------
-# TABLE MBK_TO_RDS_TURNVIA :
-#
-# MBK via      RDS layer 1                      ...
-# name         name  delta-width overlap mode
-##-------------------------------------------------------------------
-
-TABLE MBK_TO_RDS_TURNVIA
-
-# CONT_TURN1 
-
-END
-
-
diff --git a/alliance/share/etc/prol10.elp b/alliance/share/etc/prol10.elp
deleted file mode 100644
index e205d65e..00000000
--- a/alliance/share/etc/prol10.elp
+++ /dev/null
@@ -1,58 +0,0 @@
-#Fichier de parametrisation de TAS, PROL10, LEVEL 2, HSPICE
-#Les parametres sont calcules en tenant compte des shrinks
-#Par DIOURY karim, le 15/06/1995
-
-Technologie : prol10 Version : 2.0
-
-#Reference Simulator
-ESIM  = HSPICE
-MODEL = MOS
-LEVEL = 2.0
-
-#shrink parameters (micron)
-DLN = 0.0
-DLP = 0.0
-DWN = 0.0
-DWP = 0.0
-
-#transistor characteristics
-#NMOS
-VTN = 0.8
-BN  = 0.7
-AN  = 4.8e-05
-RNT = 11000.0
-
-#PMOS
-VTP = 1.2
-BP  = 0.25
-AP  = 1.7e-05
-RPT = 26000.0
-
-#general parameters
-VDDmax = 4.50
-VTHR   = 2.250
-VSSdeg = 1.6
-VDDdeg = 3.5
-TEMP   = 70.0
-
-#dynamic capacitance: grid capacitance (in pF/u and pF/u2)
-CGSN = 1500.0e-6
-CGSP = 1500.0e-6
-CGPN =  200.0e-6
-CGPP =  200.0e-6
-
-#dynamic capacitance: drain capacitance (in pF/u and pF/u2)
-CDSN = 400.0e-6
-CDSP = 600.0e-6
-CDPN = 500.0e-6
-CDPP = 800.0e-6
-CDWN = 200.0e-6
-CDWP = 200.0e-6
-
-#dynamic capacitance: source capacitance (in pF/u and pF/u2)
-CSSN = 400.0e-6
-CSSP = 600.0e-6
-CSPN = 500.0e-6
-CSPP = 800.0e-6
-CSWN = 200.0e-6
-CSWP = 200.0e-6
diff --git a/alliance/share/etc/prol10_11.rds b/alliance/share/etc/prol10_11.rds
deleted file mode 100644
index 100ae169..00000000
--- a/alliance/share/etc/prol10_11.rds
+++ /dev/null
@@ -1,211 +0,0 @@
-DEFINE PHYSICAL_GRID    0.050
-
-DEFINE LAMBDA           1.000
-
-TABLE MBK_TO_RDS_SEGMENT
-
-  NWELL  RDS_NWELL VW   0.500   1.000    0.000  ALL
-  NDIF   RDS_NDIF  VW   0.500   0.000    0.000  EXT\
-         RDS_ACTIV VW   0.500   0.000    0.000  DRC\
-         RDS_NIMP  VW   0.900   0.800    0.000  DRC
-  PDIF   RDS_PDIF  VW   0.500   0.000    0.000  EXT\
-         RDS_ACTIV VW   0.500   0.000    0.000  DRC\
-         RDS_PIMP  VW   0.900   0.800    0.000  DRC\
-         RDS_NWELL VW   1.500   2.000    0.000  DRC  
-  NTIE   RDS_NTIE  VW   0.500   0.000    0.000  EXT\
-         RDS_ACTIV VW   0.500   0.000    0.000  DRC\
-         RDS_NIMP  VW   0.900   0.800    0.000  DRC\
-         RDS_NWELL VW   0.900   0.800    0.000  DRC  
-  PTIE   RDS_PTIE  VW   0.500   0.000    0.000  EXT\
-         RDS_ACTIV VW   0.500   0.000    0.000  DRC\
-         RDS_PIMP  VW   0.900   0.800    0.000  DRC
-  NTRANS RDS_POLY  VW   0.000   0.000    0.000  EXT\
-         RDS_NDIF LCW  -1.500   2.000    0.000  EXT\
-         RDS_NDIF RCW  -1.500   2.000    0.000  EXT\
-         RDS_POLY  VW   0.000   0.000    0.000  DRC\
-         RDS_ACTIV VW  -1.500   4.000    0.000  DRC\
-         RDS_NIMP  VW  -1.100   4.800    0.000  DRC
-  PTRANS RDS_POLY  VW   0.000   0.000    0.000  EXT\
-         RDS_PDIF LCW  -1.500   2.000    0.000  EXT\
-         RDS_PDIF RCW  -1.500   2.000    0.000  EXT\
-         RDS_POLY  VW   0.000   0.000    0.000  DRC\
-         RDS_ACTIV VW  -1.500   4.000    0.000  DRC\
-         RDS_PIMP  VW  -1.100   4.800    0.000  DRC\
-         RDS_NWELL VW  -0.500   6.000    0.000  DRC
-  POLY   RDS_POLY  VW   0.500   0.000    0.000  ALL
-  ALU1   RDS_ALU1  VW   0.750   0.500    0.000  ALL
-  ALU2   RDS_ALU2  VW   0.750  -0.500    0.000  ALL
-END
-TABLE MBK_TO_RDS_CONNECTOR
-  POLY   RDS_POLY    0.500   0.000
-  ALU1   RDS_ALU1    0.750   0.500
-  ALU2   RDS_ALU2    0.750  -0.500
-END
-TABLE MBK_TO_RDS_REFERENCE
-  REF_REF  RDS_REF   1.500
-  REF_CON  RDS_REF   1.500
-END
-TABLE MBK_TO_RDS_BIGVIA_HOLE
-END
-TABLE MBK_TO_RDS_BIGVIA_METAL
-END 
-TABLE MBK_TO_RDS_TURNVIA
-END
-
-
-TABLE MBK_TO_RDS_VIA
-  CONT_BODY_N              \
-    RDS_ALU1      2.500  ALL\
-    RDS_CONT      1.500  ALL\
-    RDS_ACTIV     2.500  DRC\
-    RDS_NIMP      3.300  DRC\
-    RDS_NWELL     3.300  DRC\
-    RDS_NTIE      2.500  EXT  
-  CONT_BODY_P              \
-    RDS_ALU1      2.500  ALL\
-    RDS_CONT      1.500  ALL\
-    RDS_ACTIV     2.500  DRC\
-    RDS_PIMP      3.300  DRC\
-    RDS_PTIE      2.500  EXT  
-  CONT_DIF_N               \
-    RDS_ALU1      2.500  ALL\
-    RDS_CONT      1.500  ALL\
-    RDS_ACTIV     2.500  DRC\
-    RDS_NIMP      3.300  DRC\
-    RDS_NDIF      2.500  EXT  
-  CONT_DIF_P               \
-    RDS_ALU1      2.500  ALL\
-    RDS_CONT      1.500  ALL\
-    RDS_ACTIV     2.500  DRC\
-    RDS_PIMP      3.300  DRC\
-    RDS_NWELL     4.500  DRC\
-    RDS_PDIF      2.500  EXT  
-  CONT_POLY                \
-    RDS_ALU1      2.500  ALL\
-    RDS_CONT      1.500  ALL\
-    RDS_POLY      2.500  ALL  
-  CONT_VIA                 \
-    RDS_ALU1      2.500  ALL\
-    RDS_VIA1      1.500  ALL\
-    RDS_ALU2      2.500  ALL  
-  C_X_N                    \
-    RDS_POLY      1.000  DRC\
-    RDS_ACTIV     5.000  DRC\
-    RDS_NIMP      5.800  DRC\
-    RDS_POLY      1.000  EXT\
-    RDS_NDIF      5.000  EXT  
-  C_X_P                    \
-    RDS_POLY      1.000  DRC\
-    RDS_ACTIV     5.000  DRC\
-    RDS_PIMP      5.800  DRC\
-    RDS_NWELL     7.000  DRC\
-    RDS_POLY      1.000  EXT\
-    RDS_PDIF      5.000  EXT  
-END
-TABLE CIF_LAYER 
-  RDS_NWELL    CNW
-  RDS_POLY     CP
-  RDS_CONT     CC
-  RDS_ALU1     CM
-  RDS_TALU1    AM1
-  RDS_VIA1     CC2
-  RDS_ALU2     CM2
-  RDS_TALU2    AM2
-  RDS_ACTIV    AR
-  RDS_NIMP     CND
-  RDS_PIMP     CPD
-  RDS_NDIF     CNDI
-  RDS_PDIF     CPDI
-  RDS_NTIE     CNTI
-  RDS_PTIE     CPTI
-  RDS_CPAS     CG
-  RDS_REF      LREF
-END
-TABLE GDS_LAYER
-  RDS_NWELL    1
-  RDS_POLY     11
-  RDS_CONT     16
-  RDS_ALU1     17
-  RDS_VIA1     18
-  RDS_ALU2     19
-  RDS_ACTIV    2
-  RDS_NIMP     12
-  RDS_PIMP     14
-  RDS_CPAS     20
-END
-TABLE S2R_OVERSIZE_DENOTCH
-  RDS_NWELL     4.000
-  RDS_POLY      0.950
-  RDS_ALU1      0.950
-  RDS_ALU2      0.950
-  RDS_ACTIV     1.000
-  RDS_NIMP      0.250
-  RDS_PIMP      0.250
-END
-TABLE S2R_BLOC_RING_WIDTH
-  RDS_NWELL     8.000
-  RDS_POLY      2.000
-  RDS_ALU1      2.000
-  RDS_ALU2      2.000
-  RDS_ACTIV     2.100
-  RDS_NIMP      0.500
-  RDS_PIMP      0.500
-END
-TABLE S2R_MINIMUM_LAYER_WIDTH 
-  RDS_NWELL     4.000
-  RDS_POLY      1.000
-  RDS_ALU1      1.500
-  RDS_ALU2      1.500
-  RDS_ACTIV     2.000
-  RDS_NIMP      2.000
-  RDS_PIMP      2.000
-END
-TABLE S2R_POST_TREAT
-  RDS_NWELL        TREAT NULL     
-  RDS_POLY         TREAT NULL     
-  RDS_CONT       NOTREAT NULL     
-  RDS_ALU1         TREAT NULL     
-  RDS_VIA1       NOTREAT NULL     
-  RDS_ALU2         TREAT NULL     
-  RDS_ACTIV        TREAT NULL     
-  RDS_NIMP         TREAT RDS_PIMP 
-  RDS_PIMP         TREAT RDS_NIMP 
-  RDS_ABOX       NOTREAT NULL     
-END
-
-TABLE LYNX_DIFFUSION
-  RDS_NDIF RDS_ACTIV 1 RDS_NIMP 1 RDS_NWELL 0
-  RDS_PDIF RDS_ACTIV 1 RDS_PIMP 1 RDS_NWELL 1
-  RDS_NTIE RDS_ACTIV 1 RDS_NIMP 1 RDS_NWELL 1
-  RDS_PTIE RDS_ACTIV 1 RDS_PIMP 1 RDS_NWELL 0
-END
-
-TABLE LYNX_TRANSISTOR
-  NTRANS  NTRANS C_X_N RDS_POLY RDS_NDIF RDS_ACTIV RDS_PWELL
-  PTRANS  PTRANS C_X_P RDS_POLY RDS_PDIF RDS_ACTIV RDS_NWELL
-END
-
-TABLE LYNX_BULK_IMPLICIT
-END 
-
-TABLE LYNX_GRAPH
-  RDS_NDIF   RDS_CONT   RDS_NDIF
-  RDS_PDIF   RDS_CONT   RDS_PDIF
-  RDS_NTIE   RDS_CONT   RDS_NTIE
-  RDS_PTIE   RDS_CONT   RDS_PTIE
-  RDS_POLY   RDS_CONT   RDS_POLY
-  RDS_CONT   RDS_PDIF   RDS_NDIF   RDS_POLY  RDS_PTIE   RDS_NTIE   RDS_ALU1  RDS_CONT
-  RDS_ALU1   RDS_CONT   RDS_VIA1   RDS_ALU1  RDS_REF
-  RDS_REF    RDS_CONT   RDS_VIA1   RDS_ALU1  RDS_REF
-  RDS_VIA1   RDS_ALU1   RDS_ALU2   RDS_VIA1
-  RDS_ALU2   RDS_VIA1   RDS_VIA2   RDS_ALU2
-  RDS_VIA2   RDS_ALU2   RDS_ALU3   RDS_VIA2
-  RDS_ALU3   RDS_VIA2   RDS_ALU3
-END
-TABLE LYNX_CAPA
-  RDS_POLY      7e-05   6e-05
-  RDS_ALU1      3e-05   5e-05
-  RDS_ALU2      2e-05   6e-05
-END
-TABLE LYNX_RESISTOR
-END
diff --git a/alliance/share/etc/prol10_7.rds b/alliance/share/etc/prol10_7.rds
deleted file mode 100644
index 4be27cea..00000000
--- a/alliance/share/etc/prol10_7.rds
+++ /dev/null
@@ -1,200 +0,0 @@
-DEFINE PHYSICAL_GRID    0.050
-
-DEFINE LAMBDA           1.000
-
-TABLE MBK_TO_RDS_SEGMENT
-
-  NWELL  RDS_NWELL VW   0.500   1.000    0.000  ALL
-  NDIF   RDS_NDIF  VW   0.500   0.000    0.000  EXT\
-         RDS_ACTIV VW   0.500   0.000    0.000  DRC\
-         RDS_NIMP  VW   0.900   0.800    0.000  DRC
-  PDIF   RDS_PDIF  VW   0.500   0.000    0.000  EXT\
-         RDS_ACTIV VW   0.500   0.000    0.000  DRC\
-         RDS_PIMP  VW   0.900   0.800    0.000  DRC\
-         RDS_NWELL VW   1.500   2.000    0.000  DRC  
-  NTIE   RDS_NTIE  VW   0.500   0.000    0.000  EXT\
-         RDS_ACTIV VW   0.500   0.000    0.000  DRC\
-         RDS_NIMP  VW   0.900   0.800    0.000  DRC\
-         RDS_NWELL VW   0.900   0.800    0.000  DRC  
-  PTIE   RDS_PTIE  VW   0.500   0.000    0.000  EXT\
-         RDS_ACTIV VW   0.500   0.000    0.000  DRC\
-         RDS_PIMP  VW   0.900   0.800    0.000  DRC
-  NTRANS RDS_POLY  VW   0.000   0.000    0.000  EXT\
-         RDS_NDIF LCW  -1.500   2.000    0.000  EXT\
-         RDS_NDIF RCW  -1.500   2.000    0.000  EXT\
-         RDS_POLY  VW   0.000   0.000    0.000  DRC\
-         RDS_ACTIV VW  -1.500   4.000    0.000  DRC\
-         RDS_NIMP  VW  -1.100   4.800    0.000  DRC
-  PTRANS RDS_POLY  VW   0.000   0.000    0.000  EXT\
-         RDS_PDIF LCW  -1.500   2.000    0.000  EXT\
-         RDS_PDIF RCW  -1.500   2.000    0.000  EXT\
-         RDS_POLY  VW   0.000   0.000    0.000  DRC\
-         RDS_ACTIV VW  -1.500   4.000    0.000  DRC\
-         RDS_PIMP  VW  -1.100   4.800    0.000  DRC\
-         RDS_NWELL VW  -0.500   6.000    0.000  DRC
-  POLY   RDS_POLY  VW   0.500   0.000    0.000  ALL
-  ALU1   RDS_ALU1  VW   0.750   0.500    0.000  ALL
-  ALU2   RDS_ALU2  VW   0.750  -0.500    0.000  ALL
-END
-TABLE MBK_TO_RDS_CONNECTOR
-  POLY   RDS_POLY    0.500   0.000
-  ALU1   RDS_ALU1    0.750   0.500
-  ALU2   RDS_ALU2    0.750  -0.500
-END
-TABLE MBK_TO_RDS_REFERENCE
-  REF_REF  RDS_REF   1.500
-  REF_CON  RDS_REF   1.500
-END
-TABLE MBK_TO_RDS_VIA
-  CONT_BODY_N              \
-    RDS_ALU1      2.500  ALL\
-    RDS_CONT      1.500  ALL\
-    RDS_ACTIV     2.500  DRC\
-    RDS_NIMP      3.300  DRC\
-    RDS_NWELL     3.300  DRC\
-    RDS_NTIE      2.500  EXT  
-  CONT_BODY_P              \
-    RDS_ALU1      2.500  ALL\
-    RDS_CONT      1.500  ALL\
-    RDS_ACTIV     2.500  DRC\
-    RDS_PIMP      3.300  DRC\
-    RDS_PTIE      2.500  EXT  
-  CONT_DIF_N               \
-    RDS_ALU1      2.500  ALL\
-    RDS_CONT      1.500  ALL\
-    RDS_ACTIV     2.500  DRC\
-    RDS_NIMP      3.300  DRC\
-    RDS_NDIF      2.500  EXT  
-  CONT_DIF_P               \
-    RDS_ALU1      2.500  ALL\
-    RDS_CONT      1.500  ALL\
-    RDS_ACTIV     2.500  DRC\
-    RDS_PIMP      3.300  DRC\
-    RDS_NWELL     4.500  DRC\
-    RDS_PDIF      2.500  EXT  
-  CONT_POLY                \
-    RDS_ALU1      2.500  ALL\
-    RDS_CONT      1.500  ALL\
-    RDS_POLY      2.500  ALL  
-  CONT_VIA                 \
-    RDS_ALU1      2.500  ALL\
-    RDS_VIA1      1.500  ALL\
-    RDS_ALU2      2.500  ALL  
-  C_X_N                    \
-    RDS_POLY      1.000  DRC\
-    RDS_ACTIV     5.000  DRC\
-    RDS_NIMP      5.800  DRC\
-    RDS_POLY      1.000  EXT\
-    RDS_NDIF      5.000  EXT  
-  C_X_P                    \
-    RDS_POLY      1.000  DRC\
-    RDS_ACTIV     5.000  DRC\
-    RDS_PIMP      5.800  DRC\
-    RDS_NWELL     7.000  DRC\
-    RDS_POLY      1.000  EXT\
-    RDS_PDIF      5.000  EXT  
-END
-TABLE CIF_LAYER 
-  RDS_NWELL    CNW
-  RDS_POLY     CP
-  RDS_CONT     CC
-  RDS_ALU1     CM
-  RDS_TALU1    AM1
-  RDS_VIA1     CC2
-  RDS_ALU2     CM2
-  RDS_TALU2    AM2
-  RDS_ACTIV    AR
-  RDS_NIMP     CND
-  RDS_PIMP     CPD
-  RDS_NDIF     CNDI
-  RDS_PDIF     CPDI
-  RDS_NTIE     CNTI
-  RDS_PTIE     CPTI
-  RDS_CPAS     CG
-  RDS_REF      LREF
-END
-TABLE GDS_LAYER
-  RDS_NWELL    1
-  RDS_POLY     11
-  RDS_CONT     16
-  RDS_ALU1     17
-  RDS_VIA1     18
-  RDS_ALU2     19
-  RDS_ACTIV    2
-  RDS_NIMP     12
-  RDS_PIMP     14
-  RDS_CPAS     20
-END
-TABLE S2R_OVERSIZE_DENOTCH
-  RDS_NWELL     4.000
-  RDS_POLY      0.950
-  RDS_ALU1      0.950
-  RDS_ALU2      0.950
-  RDS_ACTIV     1.000
-  RDS_NIMP      0.250
-  RDS_PIMP      0.250
-END
-TABLE S2R_BLOC_RING_WIDTH
-  RDS_NWELL     8.000
-  RDS_POLY      2.000
-  RDS_ALU1      2.000
-  RDS_ALU2      2.000
-  RDS_ACTIV     2.100
-  RDS_NIMP      0.500
-  RDS_PIMP      0.500
-END
-TABLE S2R_MINIMUM_LAYER_WIDTH 
-  RDS_NWELL     4.000
-  RDS_POLY      1.000
-  RDS_ALU1      1.500
-  RDS_ALU2      1.500
-  RDS_ACTIV     2.000
-  RDS_NIMP      2.000
-  RDS_PIMP      2.000
-END
-TABLE S2R_POST_TREAT
-  RDS_NWELL        TREAT NULL     
-  RDS_POLY         TREAT NULL     
-  RDS_CONT       NOTREAT NULL     
-  RDS_ALU1         TREAT NULL     
-  RDS_VIA1       NOTREAT NULL     
-  RDS_ALU2         TREAT NULL     
-  RDS_ACTIV        TREAT NULL     
-  RDS_NIMP         TREAT RDS_PIMP 
-  RDS_PIMP         TREAT RDS_NIMP 
-  RDS_ABOX       NOTREAT NULL     
-END
-
-TABLE LYNX_DIFFUSION
-  RDS_NDIF RDS_ACTIV 1 RDS_NIMP 1 RDS_NWELL 0
-  RDS_PDIF RDS_ACTIV 1 RDS_PIMP 1 RDS_NWELL 1
-  RDS_NTIE RDS_ACTIV 1 RDS_NIMP 1 RDS_NWELL 1
-  RDS_PTIE RDS_ACTIV 1 RDS_PIMP 1 RDS_NWELL 0
-END
-
-TABLE LYNX_TRANSISTOR
-  NTRANS  NTRANS C_X_N RDS_POLY RDS_NDIF RDS_ACTIV
-  PTRANS  PTRANS C_X_P RDS_POLY RDS_PDIF RDS_ACTIV
-END
-
-TABLE LYNX_GRAPH
-  RDS_NDIF   RDS_CONT   RDS_NDIF
-  RDS_PDIF   RDS_CONT   RDS_PDIF
-  RDS_NTIE   RDS_CONT   RDS_NTIE
-  RDS_PTIE   RDS_CONT   RDS_PTIE
-  RDS_POLY   RDS_CONT   RDS_POLY
-  RDS_CONT   RDS_PDIF   RDS_NDIF   RDS_POLY  RDS_PTIE   RDS_NTIE   RDS_ALU1  RDS_CONT
-  RDS_ALU1   RDS_CONT   RDS_VIA1   RDS_ALU1  RDS_REF
-  RDS_REF    RDS_CONT   RDS_VIA1   RDS_ALU1  RDS_REF
-  RDS_VIA1   RDS_ALU1   RDS_ALU2   RDS_VIA1
-  RDS_ALU2   RDS_VIA1   RDS_VIA2   RDS_ALU2
-  RDS_VIA2   RDS_ALU2   RDS_ALU3   RDS_VIA2
-  RDS_ALU3   RDS_VIA2   RDS_ALU3
-END
-TABLE LYNX_CAPA
-  RDS_POLY      7e-05   6e-05
-  RDS_ALU1      3e-05   5e-05
-  RDS_ALU2      2e-05   6e-05
-END
-TABLE LYNX_RESISTOR
-END
diff --git a/alliance/share/etc/prol10_8.rds b/alliance/share/etc/prol10_8.rds
deleted file mode 100644
index 1ac238fe..00000000
--- a/alliance/share/etc/prol10_8.rds
+++ /dev/null
@@ -1,203 +0,0 @@
-DEFINE PHYSICAL_GRID    0.050
-
-DEFINE LAMBDA           1.000
-
-TABLE MBK_TO_RDS_SEGMENT
-
-  NWELL  RDS_NWELL VW   0.500   1.000    0.000  ALL
-  NDIF   RDS_NDIF  VW   0.500   0.000    0.000  EXT\
-         RDS_ACTIV VW   0.500   0.000    0.000  DRC\
-         RDS_NIMP  VW   0.900   0.800    0.000  DRC
-  PDIF   RDS_PDIF  VW   0.500   0.000    0.000  EXT\
-         RDS_ACTIV VW   0.500   0.000    0.000  DRC\
-         RDS_PIMP  VW   0.900   0.800    0.000  DRC\
-         RDS_NWELL VW   1.500   2.000    0.000  DRC  
-  NTIE   RDS_NTIE  VW   0.500   0.000    0.000  EXT\
-         RDS_ACTIV VW   0.500   0.000    0.000  DRC\
-         RDS_NIMP  VW   0.900   0.800    0.000  DRC\
-         RDS_NWELL VW   0.900   0.800    0.000  DRC  
-  PTIE   RDS_PTIE  VW   0.500   0.000    0.000  EXT\
-         RDS_ACTIV VW   0.500   0.000    0.000  DRC\
-         RDS_PIMP  VW   0.900   0.800    0.000  DRC
-  NTRANS RDS_POLY  VW   0.000   0.000    0.000  EXT\
-         RDS_NDIF LCW  -1.500   2.000    0.000  EXT\
-         RDS_NDIF RCW  -1.500   2.000    0.000  EXT\
-         RDS_POLY  VW   0.000   0.000    0.000  DRC\
-         RDS_ACTIV VW  -1.500   4.000    0.000  DRC\
-         RDS_NIMP  VW  -1.100   4.800    0.000  DRC
-  PTRANS RDS_POLY  VW   0.000   0.000    0.000  EXT\
-         RDS_PDIF LCW  -1.500   2.000    0.000  EXT\
-         RDS_PDIF RCW  -1.500   2.000    0.000  EXT\
-         RDS_POLY  VW   0.000   0.000    0.000  DRC\
-         RDS_ACTIV VW  -1.500   4.000    0.000  DRC\
-         RDS_PIMP  VW  -1.100   4.800    0.000  DRC\
-         RDS_NWELL VW  -0.500   6.000    0.000  DRC
-  POLY   RDS_POLY  VW   0.500   0.000    0.000  ALL
-  ALU1   RDS_ALU1  VW   0.750   0.500    0.000  ALL
-  ALU2   RDS_ALU2  VW   0.750  -0.500    0.000  ALL
-END
-TABLE MBK_TO_RDS_CONNECTOR
-  POLY   RDS_POLY    0.500   0.000
-  ALU1   RDS_ALU1    0.750   0.500
-  ALU2   RDS_ALU2    0.750  -0.500
-END
-TABLE MBK_TO_RDS_REFERENCE
-  REF_REF  RDS_REF   1.500
-  REF_CON  RDS_REF   1.500
-END
-TABLE MBK_TO_RDS_VIA
-  CONT_BODY_N              \
-    RDS_ALU1      2.500  ALL\
-    RDS_CONT      1.500  ALL\
-    RDS_ACTIV     2.500  DRC\
-    RDS_NIMP      3.300  DRC\
-    RDS_NWELL     3.300  DRC\
-    RDS_NTIE      2.500  EXT  
-  CONT_BODY_P              \
-    RDS_ALU1      2.500  ALL\
-    RDS_CONT      1.500  ALL\
-    RDS_ACTIV     2.500  DRC\
-    RDS_PIMP      3.300  DRC\
-    RDS_PTIE      2.500  EXT  
-  CONT_DIF_N               \
-    RDS_ALU1      2.500  ALL\
-    RDS_CONT      1.500  ALL\
-    RDS_ACTIV     2.500  DRC\
-    RDS_NIMP      3.300  DRC\
-    RDS_NDIF      2.500  EXT  
-  CONT_DIF_P               \
-    RDS_ALU1      2.500  ALL\
-    RDS_CONT      1.500  ALL\
-    RDS_ACTIV     2.500  DRC\
-    RDS_PIMP      3.300  DRC\
-    RDS_NWELL     4.500  DRC\
-    RDS_PDIF      2.500  EXT  
-  CONT_POLY                \
-    RDS_ALU1      2.500  ALL\
-    RDS_CONT      1.500  ALL\
-    RDS_POLY      2.500  ALL  
-  CONT_VIA                 \
-    RDS_ALU1      2.500  ALL\
-    RDS_VIA1      1.500  ALL\
-    RDS_ALU2      2.500  ALL  
-  C_X_N                    \
-    RDS_POLY      1.000  DRC\
-    RDS_ACTIV     5.000  DRC\
-    RDS_NIMP      5.800  DRC\
-    RDS_POLY      1.000  EXT\
-    RDS_NDIF      5.000  EXT  
-  C_X_P                    \
-    RDS_POLY      1.000  DRC\
-    RDS_ACTIV     5.000  DRC\
-    RDS_PIMP      5.800  DRC\
-    RDS_NWELL     7.000  DRC\
-    RDS_POLY      1.000  EXT\
-    RDS_PDIF      5.000  EXT  
-END
-TABLE CIF_LAYER 
-  RDS_NWELL    CNW
-  RDS_POLY     CP
-  RDS_CONT     CC
-  RDS_ALU1     CM
-  RDS_TALU1    AM1
-  RDS_VIA1     CC2
-  RDS_ALU2     CM2
-  RDS_TALU2    AM2
-  RDS_ACTIV    AR
-  RDS_NIMP     CND
-  RDS_PIMP     CPD
-  RDS_NDIF     CNDI
-  RDS_PDIF     CPDI
-  RDS_NTIE     CNTI
-  RDS_PTIE     CPTI
-  RDS_CPAS     CG
-  RDS_REF      LREF
-END
-TABLE GDS_LAYER
-  RDS_NWELL    1
-  RDS_POLY     11
-  RDS_CONT     16
-  RDS_ALU1     17
-  RDS_VIA1     18
-  RDS_ALU2     19
-  RDS_ACTIV    2
-  RDS_NIMP     12
-  RDS_PIMP     14
-  RDS_CPAS     20
-END
-TABLE S2R_OVERSIZE_DENOTCH
-  RDS_NWELL     4.000
-  RDS_POLY      0.950
-  RDS_ALU1      0.950
-  RDS_ALU2      0.950
-  RDS_ACTIV     1.000
-  RDS_NIMP      0.250
-  RDS_PIMP      0.250
-END
-TABLE S2R_BLOC_RING_WIDTH
-  RDS_NWELL     8.000
-  RDS_POLY      2.000
-  RDS_ALU1      2.000
-  RDS_ALU2      2.000
-  RDS_ACTIV     2.100
-  RDS_NIMP      0.500
-  RDS_PIMP      0.500
-END
-TABLE S2R_MINIMUM_LAYER_WIDTH 
-  RDS_NWELL     4.000
-  RDS_POLY      1.000
-  RDS_ALU1      1.500
-  RDS_ALU2      1.500
-  RDS_ACTIV     2.000
-  RDS_NIMP      2.000
-  RDS_PIMP      2.000
-END
-TABLE S2R_POST_TREAT
-  RDS_NWELL        TREAT NULL     
-  RDS_POLY         TREAT NULL     
-  RDS_CONT       NOTREAT NULL     
-  RDS_ALU1         TREAT NULL     
-  RDS_VIA1       NOTREAT NULL     
-  RDS_ALU2         TREAT NULL     
-  RDS_ACTIV        TREAT NULL     
-  RDS_NIMP         TREAT RDS_PIMP 
-  RDS_PIMP         TREAT RDS_NIMP 
-  RDS_ABOX       NOTREAT NULL     
-END
-
-TABLE LYNX_DIFFUSION
-  RDS_NDIF RDS_ACTIV 1 RDS_NIMP 1 RDS_NWELL 0
-  RDS_PDIF RDS_ACTIV 1 RDS_PIMP 1 RDS_NWELL 1
-  RDS_NTIE RDS_ACTIV 1 RDS_NIMP 1 RDS_NWELL 1
-  RDS_PTIE RDS_ACTIV 1 RDS_PIMP 1 RDS_NWELL 0
-END
-
-TABLE LYNX_TRANSISTOR
-  NTRANS  NTRANS C_X_N RDS_POLY RDS_NDIF RDS_ACTIV RDS_PWELL
-  PTRANS  PTRANS C_X_P RDS_POLY RDS_PDIF RDS_ACTIV RDS_NWELL
-END
-
-TABLE LYNX_BULK_IMPLICIT
-END 
-
-TABLE LYNX_GRAPH
-  RDS_NDIF   RDS_CONT   RDS_NDIF
-  RDS_PDIF   RDS_CONT   RDS_PDIF
-  RDS_NTIE   RDS_CONT   RDS_NTIE
-  RDS_PTIE   RDS_CONT   RDS_PTIE
-  RDS_POLY   RDS_CONT   RDS_POLY
-  RDS_CONT   RDS_PDIF   RDS_NDIF   RDS_POLY  RDS_PTIE   RDS_NTIE   RDS_ALU1  RDS_CONT
-  RDS_ALU1   RDS_CONT   RDS_VIA1   RDS_ALU1  RDS_REF
-  RDS_REF    RDS_CONT   RDS_VIA1   RDS_ALU1  RDS_REF
-  RDS_VIA1   RDS_ALU1   RDS_ALU2   RDS_VIA1
-  RDS_ALU2   RDS_VIA1   RDS_VIA2   RDS_ALU2
-  RDS_VIA2   RDS_ALU2   RDS_ALU3   RDS_VIA2
-  RDS_ALU3   RDS_VIA2   RDS_ALU3
-END
-TABLE LYNX_CAPA
-  RDS_POLY      7e-05   6e-05
-  RDS_ALU1      3e-05   5e-05
-  RDS_ALU2      2e-05   6e-05
-END
-TABLE LYNX_RESISTOR
-END
diff --git a/alliance/share/etc/se_defaults.mac b/alliance/share/etc/se_defaults.mac
deleted file mode 100644
index c56cb3c5..00000000
--- a/alliance/share/etc/se_defaults.mac
+++ /dev/null
@@ -1,33 +0,0 @@
-#
-# $Id: se_defaults.mac,v 1.4 2000/12/21 10:45:19 czo Exp $
-#
-# /------------------------------------------------------------------\
-# |                                                                  |
-# |        A l l i a n c e   C A D   S y s t e m                     |
-# |  S i l i c o n   E n s e m b l e / A l l i a n c e               |
-# |                                                                  |
-# |  Author    :                      Jean-Paul CHAPUT               |
-# |  E-mail    :         alliance-support@asim.lip6.fr               |
-# | ================================================================ |
-# |  SE script :         "se_defaults.mac"                           |
-# | **************************************************************** |
-# |  U p d a t e s                                                   |
-# |                                                                  |
-# \------------------------------------------------------------------/
-#
-
-
- SET VARIABLE draw.swire.at               ON ;
- SET VARIABLE userlevel                   EXPERT ;
- SET VARIABLE Plan.RGrid.M1Offset         0 ;
- SET VARIABLE Plan.RGrid.M2Offset         0 ;
- SET VARIABLE Plan.RGrid.M3Offset         0 ;
- SET VARIABLE Plan.RGrid.M4Offset         0 ;
- SET VARIABLE Plan.Lowerleft.Origin       TRUE ;
- SET VARIABLE QPlace.Fix.Placed.Cell      TRUE ;
- SET VARIABLE Qplace.Place.Pin.Preferred.Layer 
-                "(left L_ALU2)(right L_ALU2)(top L_ALU3)(bottom L_ALU3)" ;
- SET VARIABLE GRoute.AutoGGrid            TRUE ;
- SET VARIABLE GRoute.Check.Unmarked.Pgnet FALSE ;
- SET VARIABLE FRoute.AutoSearchAndRepair  TRUE ;
-
diff --git a/alliance/share/etc/spimodel.cfg b/alliance/share/etc/spimodel.cfg
deleted file mode 100644
index 8b53f6f7..00000000
--- a/alliance/share/etc/spimodel.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-# MBK_SPI_MODEL 
-# configure the transistor models of spi parser/driver
-#
-
-TN N 
-TP P
-
diff --git a/alliance/share/etc/sxlib.scapin b/alliance/share/etc/sxlib.scapin
deleted file mode 100644
index ff9a8586..00000000
--- a/alliance/share/etc/sxlib.scapin
+++ /dev/null
@@ -1,67 +0,0 @@
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Tool    :              Parameter File for Scan Tool         |
-# |                                                             |
-# | File    :                    sxlib.scan                     |
-# |                                                             |
-# | Authors :                  Jacomme Ludovic                  |
-# |                            Kazi Tani Ilhem                  |
-# |                                                             |
-# | Date    :                    29.06.2000                     |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-BEGIN_MUX
-
-MUX_MODEL        mx2_x2
-MUX_SEL          cmd
-MUX_INPUT_SEL    i1
-MUX_INPUT_NSEL   i0
-MUX_VDD          vdd
-MUX_VSS          vss
-MUX_OUTPUT       q
-
-END_MUX
-
-
-BEGIN_REG
-
-REG_MODEL        sff1_x4
-REG_CLK          ck
-REG_INPUT        i
-REG_VDD          vdd
-REG_VSS          vss
-REG_OUTPUT       q
-REG_MUX          mx2_x2
-REG_REG_MUX      sff2_x4
-
-END_REG 
-               
-
-BEGIN_REG_MUX
-
-REG_MUX_MODEL        sff2_x4
-REG_MUX_SEL          cmd
-REG_MUX_INPUT_SEL    i1
-REG_MUX_INPUT_NSEL   i0
-REG_MUX_CLK          ck
-REG_MUX_VDD          vdd
-REG_MUX_VSS          vss
-REG_MUX_OUTPUT       q
-REG_MUX_MUX          mx2_x2
-REG_MUX_REG          sff1_x4
- 
-END_REG_MUX   
-
-
-BEGIN_BUF
-
-BUF_MODEL            buf_x2
-BUF_INPUT            i
-BUF_VDD              vdd
-BUF_VSS              vss
-BUF_OUTPUT           q
-
-END_BUF   
-
-
diff --git a/alliance/share/etc/xfsm.par b/alliance/share/etc/xfsm.par
deleted file mode 100644
index 0e043a6c..00000000
--- a/alliance/share/etc/xfsm.par
+++ /dev/null
@@ -1,64 +0,0 @@
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Title      :       Parameters File for Xfsm                 |
-# |                                                             |
-# | Date       :             01.01.95                           |
-# |                                                             |
-# \------------------------------------------------------------*/
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                           Unit                              |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE XFSM_UNIT  64
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |               Lower Grid Step in pixel by unit              |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE XFSM_LOWER_GRID_STEP 50
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                        Xfsm Color                           |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE XFSM_CURSOR_COLOR_NAME      Gray
-DEFINE XFSM_BACKGROUND_COLOR_NAME  Black
-DEFINE XFSM_FOREGROUND_COLOR_NAME  White
-DEFINE XFSM_ACCEPT_COLOR_NAME      magenta
-DEFINE XFSM_CONNECT_COLOR_NAME     White
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                  Xfsm Cursor Size in pixel                  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE XFSM_CURSOR_SIZE 10 
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                     Xfsm Layer Color                        |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE XFSM_LAYER_NAME
-
-  0   Arc             Cyan              Black
-  1   Reset           red               Black
-  2   Initial         yellow            Black
-  3   Layer_3         pink              Black
-  4   Layer_4         lawn_green        Black
-  5   Layer_5         red               Black
-  6   Layer_6         yellow            Black
-  7   Layer_7         white             Black
-  8   Layer_8         pink              Black
-  9   Layer_9         red               Black
-
-
-END 
diff --git a/alliance/share/etc/xpat.par b/alliance/share/etc/xpat.par
deleted file mode 100644
index 1ab59ec5..00000000
--- a/alliance/share/etc/xpat.par
+++ /dev/null
@@ -1,65 +0,0 @@
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Title      :       Parameters File for Xpat                 |
-# |                                                             |
-# | Author     :           Jacomme Ludovic                      |
-# |                                                             |
-# | Date       :             28.05.96                           |
-# |                                                             |
-# \------------------------------------------------------------*/
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                           Unit                              |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE XPAT_UNIT  2
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |               Lower Grid Step in pixel by unit              |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE XPAT_LOWER_GRID_STEP 25
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                        Xpat Color                           |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE XPAT_CURSOR_COLOR_NAME      Gray
-DEFINE XPAT_BACKGROUND_COLOR_NAME  Black
-DEFINE XPAT_FOREGROUND_COLOR_NAME  White
-DEFINE XPAT_ACCEPT_COLOR_NAME      magenta
-DEFINE XPAT_CONNECT_COLOR_NAME     White
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                  Xpat Cursor Size in pixel                  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE XPAT_CURSOR_SIZE 10 
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                     Xpat Layer Color                        |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE XPAT_LAYER_NAME
-
-  0   Zero            DeepSkyBlue       Black
-  1   One             red               Black
-  2   Down            Cyan              Black
-  3   Up              pink              Black
-  4   Dont_care       orchid            Black
-  5   Vector          MediumSlateBlue   Black
-  6   Unused          gray             Black
-  7   Unused          gray             Black
-  8   Unused          gray             Black
-  9   Unused          gray             Black
-
-END 
diff --git a/alliance/share/etc/xsch.par b/alliance/share/etc/xsch.par
deleted file mode 100644
index 81dae574..00000000
--- a/alliance/share/etc/xsch.par
+++ /dev/null
@@ -1,457 +0,0 @@
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Title      :       Parameters File for Xsch                 |
-# |                                                             |
-# | Author     :           Ludovic Jacomme                      |
-# |                                                             |
-# | Date       :             03.29.2000                         |
-# |                                                             |
-# \------------------------------------------------------------*/
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                           Unit                              |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE XSCH_UNIT  64
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |               Lower Grid Step in pixel by unit              |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE XSCH_LOWER_GRID_STEP 50
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                        Xsch Color                           |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE XSCH_CURSOR_COLOR_NAME      Black
-DEFINE XSCH_BACKGROUND_COLOR_NAME  Black
-DEFINE XSCH_FOREGROUND_COLOR_NAME  White
-DEFINE XSCH_ACCEPT_COLOR_NAME      magenta
-DEFINE XSCH_CONNECT_COLOR_NAME     magenta 
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                  Xsch Cursor Size in pixel                  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE XSCH_CURSOR_SIZE 10 
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                     Xsch Layer Color                        |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE XSCH_LAYER_NAME
-
-  0   Gates           cyan              Black      0070ff
-  1   Inputs          red               Black      ff0000
-  2   Outputs         light_blue        Black      00ff00
-  3   Signals         pink              Black      0000ff
-  4   Debug           spring_green      Black      00a000
-  5   Layer_0         #0000ff           Black      0000ff           
-  6   Layer_1         #0020ff           Black      0020ff           
-  7   Layer_2         #0040ff           Black      0040ff           
-  8   Layer_3         #0060ff           Black      0060ff           
-  9   Layer_4         #0080ff           Black      0080ff           
- 10   Layer_5         #00a0ff           Black      00a0ff           
- 11   Layer_6         #00c0ff           Black      00c0ff           
- 12   Layer_7         #00e0ff           Black      00e0ff           
- 13   Layer_8         #00ffff           Black      00ffff           
- 14   Layer_9         #00ffe0           Black      00ffe0           
- 15   Layer_10        #00ffc0           Black      00ffc0           
- 16   Layer_11        #00ffa0           Black      00ffa0           
- 17   Layer_12        #00ff80           Black      00ff80           
- 18   Layer_13        #00ff60           Black      00ff60           
- 19   Layer_14        #00ff40           Black      00ff40           
- 20   Layer_15        #00ff20           Black      00ff20           
- 21   Layer_16        #00ff00           Black      00ff00           
- 22   Layer_17        #20ff00           Black      20ff00           
- 23   Layer_18        #40ff00           Black      40ff00           
- 24   Layer_19        #60ff00           Black      60ff00           
- 25   Layer_20        #80ff00           Black      80ff00           
- 26   Layer_21        #a0ff00           Black      a0ff00           
- 27   Layer_22        #c0ff00           Black      c0ff00           
- 28   Layer_23        #e0ff00           Black      e0ff00           
- 29   Layer_24        #ffff00           Black      ffff00           
- 30   Layer_25        #ffe000           Black      ffe000           
- 31   Layer_26        #ffc000           Black      ffc000           
- 32   Layer_27        #ffa000           Black      ffa000           
- 33   Layer_28        #ff8000           Black      ff8000           
- 34   Layer_29        #ff6000           Black      ff6000           
- 35   Layer_30        #ff4000           Black      ff4000           
- 36   Layer_31        #ff2000           Black      ff2000           
- 37   Layer_32        #ff0000           Black      ff0000           
-
-END 
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                     Xsch Icon Cell Buffer                   |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE XSCH_ICON_CELL_BUFFER
-
-# model  inputs output not_in not_out
-
-# SXLIB
-
-  buf_x2 i  q 0 0
-  buf_x4 i  q 0 0
-  buf_x8 i  q 0 0
-
-  inv_x1 i nq 0 1
-  inv_x2 i nq 0 1
-  inv_x4 i nq 0 1
-  inv_x8 i nq 0 1
-
-# SCLIB
-
-  b1_y     i  t 0 0
-  d1_y     i  t 0 0
-  p1_y     i  t 0 0
-
-  n1_y     i  f 0 1
-  np1_y    i  f 0 1
-  ndrv_y   i  f 0 1
-  ndrvp_y  i  f 0 1
-
-# DP_SXLIB
-
-  dp_rom2_buf i nix 0 1
-
-# RFLIB
-
-   rf_out_buf_2 nck xcks 0 1
-   rf_out_buf_4 nck xcks 0 1
-   rf_dec_nbuf  i   nq   0 1
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                     Xsch Icon Cell And                      |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE XSCH_ICON_CELL_AND
-
-# model  inputs output number_in not_in not_out
-
-# SXLIB
-
-  a2_x2   i0,i1         q  2 0 0
-  a2_x4   i0,i1         q  2 0 0
-  a3_x2   i0,i1,i2      q  3 0 0
-  a3_x4   i0,i1,i2      q  3 0 0
-  a4_x2   i0,i1,i2,i3   q  4 0 0
-  a4_x4   i0,i1,i2,i3   q  4 0 0
-
-  na2_x1   i0,i1        nq  2 0 1
-  na2_x4   i0,i1        nq  2 0 1
-  na3_x1   i0,i1,i2     nq  3 0 1
-  na3_x4   i0,i1,i2     nq  3 0 1
-  na4_x1   i0,i1,i2,i3  nq  4 0 1
-  na4_x4   i0,i1,i2,i3  nq  4 0 1
-
-  an12_x1  i0,i1         q  2 2 0
-  an12_x4  i0,i1         q  2 2 0
-
-# SCLIB
-
-  a2_y     i0,i1         t 2 0 0
-  a2p_y    i0,i1         t 2 0 0
-  a3_y     i0,i1,i2      t 3 0 0
-  a3p_y    i0,i1,i2      t 3 0 0
-  a4_y     i0,i1,i2,i3   t 4 0 0
-  a4p_y    i0,i1,i2,i3   t 4 0 0
-
-  na2_y    i0,i1         f 2 0 1
-  na2p_y   i0,i1         f 2 0 1
-  na3_y    i0,i1,i2      f 3 0 1
-  na3p_y   i0,i1,i2      f 3 0 1
-  na4_y    i0,i1,i2,i3   f 4 0 1
-  na4p_y   i0,i1,i2,i3   f 4 0 1
-
-# RFLIB
-
-  rf_dec_nand2 i0,i1       nq 2 0 1
-  rf_dec_nand3 i0,i1,i2    nq 3 0 1
-  rf_dec_nand4 i0,i1,i2,i3 nq 4 0 1
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                     Xsch Icon Cell Or                       |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE XSCH_ICON_CELL_OR 
-
-# model  inputs output number_in not_in not_out
-
-# SXLIB
-
-  o2_x2   i0,i1         q  2 0 0
-  o2_x4   i0,i1         q  2 0 0
-  o3_x2   i0,i1,i2      q  3 0 0
-  o3_x4   i0,i1,i2      q  3 0 0
-  o4_x2   i0,i1,i2,i3   q  4 0 0
-  o4_x4   i0,i1,i2,i3   q  4 0 0
-
-  no2_x1   i0,i1        nq  2 0 1
-  no2_x4   i0,i1        nq  2 0 1
-  no3_x1   i0,i1,i2     nq  3 0 1
-  no3_x4   i0,i1,i2     nq  3 0 1
-  no4_x1   i0,i1,i2,i3  nq  4 0 1
-  no4_x4   i0,i1,i2,i3  nq  4 0 1
-
-  on12_x1  i0,i1         q  2 2 0
-  on12_x4  i0,i1         q  2 2 0
-
-# SCLIB
-
-  o2_y     i0,i1         t 2 0 0
-  op2_y    i0,i1         t 2 0 0
-  o3_y     i0,i1,i2      t 3 0 0
-  op3_y    i0,i1,i2      t 3 0 0
-
-  no2_y    i0,i1         f 2 0 1
-  nop2_y   i0,i1         f 2 0 1
-  no3_y    i0,i1,i2      f 3 0 1
-  nop3_y   i0,i1,i2      f 3 0 1
-
-# RFLIB
-
-  rf_dec_nor3 i0,i1,i2        nq    3 0 1
-  rf_fifo_inc ckm,nreset,nval inc   3 1 0
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                     Xsch Icon Cell Xor                      |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE XSCH_ICON_CELL_XOR 
-
-# model  inputs output number_in not_in not_out
-
-# SXLIB
-
-  xr2_x1    i0,i1         q  2 0 0
-  xr2_x4    i0,i1         q  2 0 0
-
-  nxr2_x1   i0,i1        nq  2 0 1
-  nxr2_x4   i0,i1        nq  2 0 1
-
-# SCLIB
-
-  xr2_y     i0,i1         t  2 0 0
-  nxr2_y    i0,i1         f  2 0 1
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                     Xsch Icon Cell Tristate                 |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE XSCH_ICON_CELL_TRISTATE 
-
-# model  inputs output not_in not_out
-
-# SXLIB
-
-  nts_x1    cmd,i        nq  0 1
-  nts_x2    cmd,i        nq  0 1
-
-  ts_x4     cmd,i         q  0 0
-  ts_x8     cmd,i         q  0 0
-
-# SCLIB
-
-  ts_y      v,i           t  0 0
-  tsp_y     v,i           t  0 0
-
-  tsn_y     v,i           f  0 1
-  
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                     Xsch Icon Cell Register                 |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE XSCH_ICON_CELL_REGISTER 
-
-# model  inputs output number_in not_in clock_in not_out edge
-
-# SXLIB
-
-  sff1_x4   i,ck                      q 2 0 1  0  1
-  sff2_x4   cmd,i0,i1,ck              q 4 0 1  0  1
-  sff3_x4   cmd0,cmd1,i0,i1,i2,ck     q 6 0 1  0  1
-
-# SCLIB
-
-  ms_y      i,l                       t 2 0 1  0  2
-  msdp2_y   di,ck                     t 2 0 1  0  2
-  msdp4_y   di,ck                     t 2 0 1  0  2
-
-  ms2dp2_y  di,si,se,ck               t 4 0 1  0  2
-  ms2dp4_y  di,si,se,ck               t 4 0 1  0  2
-
-# RFLIB
-
-  rf_out_mem rbus,xcks          dataout 2 0 1 0 0
-  
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                     Xsch Icon Cell One                      |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE XSCH_ICON_CELL_CONSTANT 
-
-# model  outputs number_out value
-
-# SXLIB
-  one_x0    q  1 1
-  zero_x0  nq  1 0
-
-# SCLIB
-  one_y     t  1 1
-  zero_y    f  1 0
-  
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                     Xsch Icon Cell Or_And                   |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE XSCH_ICON_CELL_ORAND 
-
-# model      inputs  output number_in  not_in not_out
-
-# SXLIB
-
-  ao22_x2    i0,i1,i2     q  3          0     0
-  ao22_x4    i0,i1,i2     q  3          0     0
-  ao2o22_x2  i0,i1,i2,i3  q  4          0     0
-  ao2o22_x4  i0,i1,i2,i3  q  4          0     0
-                          
-  nao22_x1   i0,i1,i2    nq  3          0     1
-  nao22_x4   i0,i1,i2    nq  3          0     1
-  nao2o22_x1 i0,i1,i2,i3 nq  4          0     1
-  nao2o22_x4 i0,i1,i2,i3 nq  4          0     1
-
-# SCLIB
-
-  mx2_y      i0,l0,i1,l1              t  4   0   0
-  mx2p_y     i0,l0,i1,l1              t  4   0   0
-  mx3_y      i0,l0,i1,l1,i2,l2        t  6   0   0
-  mx4_y      i0,l0,i1,l1,i2,l2,i3,l3  t  8   0   0
-  nmx2_y     j0,i0,j1,i1              t  4   0   1
-  nao3_y     i0,i1,i2                 f  3   0   1
-
-# RFLIB
-
-  rf_dec_nao3 i0,i1,i2               nq  3   0   1
-  
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                     Xsch Icon Cell And_Or                   |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE XSCH_ICON_CELL_ANDOR
-
-# model      inputs  output number_in  not_in   not_out
-
-# SXLIB
-
-  noa22_x1         i0,i1,i2                 nq  3  0 1
-  noa22_x4         i0,i1,i2                 nq  3  0 1
-  noa2a22_x1       i0,i1,i2,i3              nq  4  0 1
-  noa2a22_x4       i0,i1,i2,i3              nq  4  0 1
-  noa2a2a23_x1     i0,i1,i2,i3,i4,i5        nq  6  0 1
-  noa2a2a23_x4     i0,i1,i2,i3,i4,i5        nq  6  0 1
-  noa2a2a2a24_x1   i0,i1,i2,i3,i4,i5,i6,i7  nq  8  0 1
-  noa2a2a2a24_x4   i0,i1,i2,i3,i4,i5,i6,i7  nq  8  0 1
-
-  oa22_x2          i0,i1,i2                  q  3  0 0
-  oa22_x4          i0,i1,i2                  q  3  0 0
-  oa2a22_x2        i0,i1,i2,i3               q  4  0 0
-  oa2a22_x4        i0,i1,i2,i3               q  4  0 0
-  oa2a2a23_x2      i0,i1,i2,i3,i4,i5         q  6  0 0
-  oa2a2a23_x4      i0,i1,i2,i3,i4,i5         q  6  0 0
-  oa2a2a2a24_x2    i0,i1,i2,i3,i4,i5,i6,i7   q  8  0 0
-  oa2a2a2a24_x4    i0,i1,i2,i3,i4,i5,i6,i7   q  8  0 0
-
-
-# SCLIB
-
-   noa3_y          i0,i1,i2                  f  3  0 1
-   annup_y         i1,i2,i3,i4               f  4  0 1
-
-# RFLIB
-
-   rf_fifo_orand4  a0,b0,a1,b1           rippleout   4  0 0
-   rf_fifo_orand5  a0,b0,a1,b1,ripplein  rippleout   5  0 0
-
-END
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                     Xsch Icon Cell Mux                      |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE XSCH_ICON_CELL_MUX 
-
-# model  inputs               output number_sel number_in not_in not_out
-                              
-# SXLIB                       
-                              
-  mx2_x2 cmd,i0,i1            q      1          2         0      0
-  mx2_x4 cmd,i0,i1            q      1          2         0      0
-                              
-  mx3_x2 cmd0,cmd1,i0,i1,i2   q      2          3         0      0
-  mx3_x4 cmd0,cmd1,i0,i1,i2   q      2          3         0      0
-
-  nmx2_x1 cmd,i0,i1          nq      1          2         0      1
-  nmx2_x4 cmd,i0,i1          nq      1          2         0      1
-                             
-  nmx3_x1 cmd0,cmd1,i0,i1,i2 nq      2          3         0      1
-  nmx3_x4 cmd0,cmd1,i0,i1,i2 nq      2          3         0      1
-
-# DP_SXLIB
-
-  dp_mux_x2  sel0,sel1,i0,i1  q      2          2         0      0
-  dp_mux_x4  sel0,sel1,i0,i1  q      2          2         0      0
-  dp_nmux_x1 sel0,sel1,i0,i1 nq      2          2         0      1
-
-# RFLIB
-
-  rf_inmux_mem sel0,sel1,datain0,datain1 dinx 2 2         0      0
-
-END
diff --git a/alliance/share/etc/xvpn.par b/alliance/share/etc/xvpn.par
deleted file mode 100644
index 31b8403a..00000000
--- a/alliance/share/etc/xvpn.par
+++ /dev/null
@@ -1,63 +0,0 @@
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Title      :       Parameters File for Xvpn                 |
-# |                                                             |
-# | Date       :             01.01.95                           |
-# |                                                             |
-# \------------------------------------------------------------*/
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                           Unit                              |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE XVPN_UNIT  32
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |               Lower Grid Step in pixel by unit              |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE XVPN_LOWER_GRID_STEP 50
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                  Xvpn Cursor Color Name                     |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE XVPN_CURSOR_COLOR_NAME      Black
-DEFINE XVPN_BACKGROUND_COLOR_NAME  Black
-DEFINE XVPN_FOREGROUND_COLOR_NAME  White
-DEFINE XVPN_ACCEPT_COLOR_NAME      magenta
-DEFINE XVPN_CONNECT_COLOR_NAME     pink
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                  Xvpn Cursor Size in pixel                  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-DEFINE XVPN_CURSOR_SIZE 10 
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                     Xvpn Layer Color                        |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TABLE XVPN_LAYER_NAME
-
-  0   Process         Cyan              Black
-  1   Function        sky_blue          Black
-  2   Wait            pink              Black
-  3   Assign          lawn_green        Black
-  4   Guard           red               Black
-  5   Asg-Guard       yellow            Black
-  6   Token           magenta           Black
-  7   Unused_7        gray              Black
-  8   Unused_8        gray              Black
-  9   Unused_9        gray              Black
-
-END 
diff --git a/alliance/share/man/README.man b/alliance/share/man/README.man
deleted file mode 100644
index a40e5e00..00000000
--- a/alliance/share/man/README.man
+++ /dev/null
@@ -1 +0,0 @@
-Some man pages might be obsolete
diff --git a/alliance/share/man/makewhatis b/alliance/share/man/makewhatis
deleted file mode 100755
index b7d0886d..00000000
--- a/alliance/share/man/makewhatis
+++ /dev/null
@@ -1,334 +0,0 @@
-#!/bin/sh
-# makewhatis: create the whatis database
-# Created: Sun Jun 14 10:49:37 1992
-# Revised: Sat Jan  8 14:12:37 1994 by faith@cs.unc.edu
-# Revised: Sat Mar 23 17:56:18 1996 by micheal@actrix.gen.nz
-# Copyright 1992, 1993, 1994 Rickard E. Faith (faith@cs.unc.edu)
-# May be freely distributed and modified as long as copyright is retained.
-#
-# Wed Dec 23 13:27:50 1992: Rik Faith (faith@cs.unc.edu) applied changes
-# based on Mitchum DSouza (mitchum.dsouza@mrc-apu.cam.ac.uk) cat patches.
-# Also, cleaned up code and make it work with NET-2 doc pages.
-#
-# makewhatis-1.4: aeb 940802, 941007, 950417
-# Fixed so that the -c option works correctly for the cat pages
-# on my machine. Fix for -u by Nan Zou (nan@ksu.ksu.edu).
-# Many minor changes.
-# The -s option is undocumented, and may well disappear again.
-#
-# Sat Mar 23 1996: Michael Hamilton (michael@actrix.gen.nz).
-# I changed the script to invoke gawk only once for each directory tree.
-# This speeds things up considerably (from 30 minutes down to 1.5 minutes
-# on my 486DX66).
-# 960401 - aeb: slight adaptation to work correctly with cat pages.
-# 960510 - added fixes by brennan@raven.ca.boeing.com, author of mawk.
-# 971012 - replaced "test -z" - it doesnt work on SunOS 4.1.3_U1.
-# 980710 - be more careful with TMPFILE
-#
-# Note for Slackware users: "makewhatis -v -w -c" will work.
-
-PATH=/usr/bin:/bin
-
-DEFMANPATH=/usr/man
-DEFCATPATH=/usr/man/preformat:/usr/man
-
-# AWK=/usr/bin/gawk
-AWK=/bin/gawk
-
-# Find a place for our temporary files. If security is not a concern, use
-#	TMPFILE=/tmp/whatis$$; TMPFILEDIR=none
-# Of course makewhatis should only have the required permissions
-# (for reading and writing directories like /usr/man).
-# We try here to be careful (and avoid preconstructed symlinks)
-# in case makewhatis is run as root, by creating a subdirectory of /tmp.
-# If that fails we use $HOME.
-# The code below uses  test -O  which doesnt work on all systems.
-TMPFILE=$HOME/whatis$$
-TMPFILEDIR=/tmp/whatis$$
-if [ ! -d $TMPFILEDIR ]; then
-	mkdir $TMPFILEDIR
-	chmod 0700 $TMPFILEDIR
-	if [ -O $TMPFILEDIR ]; then
-		TMPFILE=$TMPFILEDIR/w
-	fi
-fi
-
-topath=manpath
-
-defmanpath=$DEFMANPATH
-defcatpath=
-
-sections="1 2 3 4 5 6 7 8 9 n l"
-
-for name in $*
-do
-if [ -n "$setsections" ]; then
-	setsections=
-	sections=$name
-	continue
-fi
-case $name in
-    -c) topath=catpath
-	defmanpath=
-	defcatpath=$DEFCATPATH
-        continue;;
-    -s) setsections=1
-        continue;;
-    -u) findarg="-ctime 0"
-        update=1
-        continue;;
-    -v) verbose=1
-	continue;;
-    -w) manpath=`man --path`
-	continue;;
-    -*) echo "Usage: makewhatis [-u] [-v] [-w] [manpath] [-c [catpath]]"
-	echo "       This will build the whatis database for the man pages"
-	echo "       found in manpath and the cat pages found in catpath."
-        echo "       -u: update database with new pages"
-	echo "       -v: verbose"
-	echo "       -w: use manpath obtained from \`man --path\`"
-        echo "       [manpath]: man directories (default: $DEFMANPATH)"
-	echo "       [catpath]: cat directories (default: the first existing"
-	echo "           directory in $DEFCATPATH)"
-        exit;;
-     *) if [ -d $name ]
-        then
-            eval $topath="\$$topath":$name
-        else
-            echo "No such directory $name"
-            exit
-        fi;;
-esac
-done
-
-manpath=`echo ${manpath-$defmanpath} | tr : ' '`
-if [ x"$catpath" = x ]; then
-   for d in `echo $defcatpath | tr : ' '`
-   do
-      if [ -d $d ]; then catpath=$d; break; fi
-   done
-fi
-catpath=`echo ${catpath} | tr : ' '`
-
-# first truncate all the whatis files that will be created new,
-# then only update - we might visit the same directory twice
-if [ x$update = x ]; then
-   for pages in man cat
-   do
-      eval path="\$$pages"path
-      for mandir in $path
-      do
-         cp /dev/null $mandir/whatis
-      done
-   done
-fi
-
-for pages in man cat
-do
-   export pages
-   eval path="\$$pages"path
-   for mandir in $path
-   do
-     if [ x$verbose != x ]; then
-        echo "about to enter $mandir" > /dev/tty
-     fi
-     if [ -s ${mandir}/whatis -a $pages = man ]; then
-        if [ x$verbose != x ]; then
-           echo skipping $mandir - we did it already > /dev/tty
-        fi
-     else      
-       here=`pwd`
-       cd $mandir
-       for i in $sections
-       do
-         if [ -d ${pages}$i ]
-         then
-            cd ${pages}$i
-            section=$i
-            export section verbose
-	    find . -name '*' $findarg -print | $AWK '
-
-	    function readline() {
-	      if (use_zcat) {
-		result = (pipe_cmd | getline);
-		if (result < 0) {
-		  print "Pipe error: " pipe_cmd " " ERRNO > "/dev/stderr";
-		}
-	      } else {
-		result = (getline < filename);
-		if (result < 0) {
-		  print "Read file error: " filename " " ERRNO > "/dev/stderr";
-		}
-	      }
-	      return result;
-	    }
-	    
-	    function closeline() {
-	      if (use_zcat) {
-		return close(pipe_cmd);
-	      } else {
-		return close(filename);
-	      }
-	    }
-	    
-	    function do_one() {
-	      after = 0; insh = 0; thisjoin = 1; charct = 0;
-
-	      if (verbose) {
-		print "adding " filename > "/dev/tty"
-	      }
-	      
-	      use_zcat = (filename ~ /\.Z$/ || filename ~ /\.z$/ ||
-			  filename ~ /\.gz$/);
-	      match(filename, "/[^/]+$");
-	      progname = substr(filename, RSTART + 1, RLENGTH - 1);
-	      if (match(progname, "\\." section "[A-Za-z]+")) {
-		actual_section = substr(progname, RSTART + 1, RLENGTH - 1);
-	      } else {
-		actual_section = section;
-	      }
-	      sub(/\..*/, "", progname);
-	      if (use_zcat) {
-		pipe_cmd = "zcat " filename;
-	      }
-	    
-	      while (readline() > 0) {
-		gsub(/.\b/, "");
-		if (($1 ~ /^\.[Ss][Hh]/ &&
-		  ($2 ~ /[Nn][Aa][Mm][Ee]/ ||
-		   $2 ~ /^JMÉNO/ || $2 ~ /^NAVN/ ||
-		   $2 ~ /^BEZEICHNUNG/ || $2 ~ /^NOMBRE/ ||
-		   $2 ~ /^NIMI/ || $2 ~ /^NOM/ || $2 ~ /^IME/ ||
-		   $2 ~ /^NOME/ || $2 ~ /^NAAM/)) ||
-		  (pages == "cat" && $1 ~ /^NAME/)) {
-		    if (!insh)
-		      insh = 1;
-		    else {
-		      printf "\n";
-		      closeline();
-                      return;
-		    }
-		} else if (insh) {
-		  if ($1 ~ /^\.[Ss][HhYS]/ ||
-		    (pages == "cat" &&
-		    ($1 ~ /^S[yYeE]/ || $1 ~ /^DESCRIPTION/ ||
-		    $1 ~ /^COMMAND/ || $1 ~ /^OVERVIEW/ ||
-		    $1 ~ /^STRUCTURES/ || $1 ~ /^INTRODUCTION/))) {
-		      # end insh for Synopsis, Syntax, but also for
-		      # DESCRIPTION (e.g., XFree86.1x),
-		      # COMMAND (e.g., xspread.1)
-		      # OVERVIEW (e.g., TclCommandWriting.3)
-		      # STRUCTURES (e.g., XEvent.3x)
-		      # INTRODUCTION (e.g., TclX.n)
-		      printf "\n";
-		      closeline();
-                      return; 
-		  } else { # derived from Tom Christiansen perl script
-		      if (!after && $0 ~ progname"-") {  # Fix old cat pages
-			  sub(progname"-", progname" - ");
-		      }
-		      gsub(/	/, " ");        # Translate tabs to spaces
-		      gsub(/  +/, " ");         # Collapse spaces
-		      gsub(/ *, */, ", ");      # Fix comma spacings
-		      sub(/^ /, "");            # Kill initial spaces
-		      sub(/ $/, "");            # Kill trailing spaces
-		      sub(/__+/, "_");          # Collapse underscores
-		      if ($0 ~ /[^ ]-$/) {
-			sub(/-$/, "");          # Handle Hyphenations
-			nextjoin = 1;
-		      } else
-			nextjoin = 0;
-			sub(/^.[IB] /, "");       # Kill bold and italics
-			sub(/^.Nm /, "");         # Kill bold
-			sub(/^.Tn /, "");         # Kill normal
-			sub(/^.Li /, "");         # Kill .Li
-			sub(/^.Dq /, "");         # Kill .Dq
-			sub(/^.Nd */, "- ");      # Convert .Nd to dash
-			gsub(/\\f[PRIB0123]/, "");   # Kill font changes
-			gsub(/\\s[-+0-9]*/, "");     # Kill size changes
-			gsub(/\\&/, "");             # Kill \&
-			gsub(/\\\((ru|ul)/, "_");    # Translate
-			gsub(/\\\((mi|hy|em)/, "-"); # Translate
-			gsub(/\\\*\(../, "");        # Kill troff strings
-			sub(/^\.\\\".*/, "");        # Kill comments
-			gsub(/\\/, "");              # Kill all backslashes
-			if ($1 ~ /^\.../ || $1 == "") {
-			  if (after && !needmore) {
-			    printf "\n";
-			    thisjoin = 1;
-			    charct = 0;
-			    after = 0;
-			  }
-			} else {
-			  if ($0 ~ /^- /) {
-			    sub("- ", " - ");
-			  } else if (!thisjoin && $0 !~ /^- /) {
-			    printf " ";
-			    charct += 1;
-			  }
-			  thisjoin = nextjoin;
-			  if ($0 !~ / - / && $0 !~ / -$/ && $0 !~ /^- /) {
-			    printf "%s", $0;
-			    charct += length();
-			    needmore = 0;
-			  } else {
-			    after = 1
-			    if ($0 ~ / - /) {
-			      where = match( $0 , / - /);
-			    } else if ($0 ~ / -$/) {
-			      where = match( $0, / -$/);
-			    } else {
-			      where = 1;
-			    }
-			    if ((width = 20-charct) < 0) width=0
-			    printf "%-*s", width, sprintf( "%s (%s)",
-			    substr( $0, 1, where-1 ), actual_section );
-			    printf "%s", substr( $0, where )
-			    if ($0 ~ /- *$/) {
-			      needmore = 1;
-			    } else {
-			      needmore = 0;
-			    }
-			  }
-			}
-		      }
-		   }
-		}
-	      closeline();
-	    }
-
-            {			# Main action - process each filename read in.
-	      filename = $0;
-	      do_one();
-	    }
-	    ' pages=$pages section=$section verbose=$verbose
-            cd ..
-         fi
-       done > $TMPFILE
-
-       cd $here
-
-       # kludge for Slackware's /usr/man/preformat
-       if [ $mandir = /usr/man/preformat ]
-       then
-         mandir1=/usr/man
-       else
-         mandir1=$mandir
-       fi
-
-       if [ -f ${mandir1}/whatis ]
-       then
-         cat ${mandir1}/whatis >> $TMPFILE
-       fi
-       sed '/^$/d' < $TMPFILE | sort | uniq > ${mandir1}/whatis
-
-       chmod 644 ${mandir1}/whatis
-       rm $TMPFILE
-     fi
-   done
-done
-
-# remove the dir if we created it
-if [ $TMPFILE = $TMPFILEDIR/w ]; then
-	rmdir $TMPFILEDIR
-fi
diff --git a/alliance/share/man/man1/MBK_CATAL_NAME.1 b/alliance/share/man/man1/MBK_CATAL_NAME.1
deleted file mode 100644
index f8aa25aa..00000000
--- a/alliance/share/man/man1/MBK_CATAL_NAME.1
+++ /dev/null
@@ -1,54 +0,0 @@
-.\"   $Id: MBK_CATAL_NAME.1,v 1.2 2000/10/17 15:35:12 czo Exp $
-.\" @(#)MBK_CATAL_NAME.8 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-MBK_CATAL_NAME
-.XE \}
-.TH MBK_CATAL_NAME 1 "October 1, 1997" "ASIM/LIP6" "MBK ENVIRONMENT VARIABLES"
-.SH NAME
-MBK_CATAL_NAME \- define the mbk catalog file
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-c-shell running
-setenv MBK_CATAL_NAME file
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH DESCRIPTION
-\fBMBK_CATAL_NAME\fP sets the name of the catalog file, that contains
-information about the cells of a design. The catalog file syntax is a cellname, 
-plus a flag. The cellname may appear many times with a different flag.
-.TP
-Three flags are available:
-  C : tells the flatten functions to stop a this level.
-.br
-  G : informs the user that this is a phantom cell.
-.br
-  F : says that this is a feed through.
-.br
-The seaching mecanism first look in \fBMBK_WORK_LIB\fP(1), and then
-in \fBMBK_CATA_LIB\fP(1). So it is recommended to have a catalog file in
-the \fBMBK_WORK_LIB\fP(1).
-.br
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-	setenv MBK_CATAL_NAME catalog
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR genlib (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/MBK_CATA_LIB.1 b/alliance/share/man/man1/MBK_CATA_LIB.1
deleted file mode 100644
index 2a14b69f..00000000
--- a/alliance/share/man/man1/MBK_CATA_LIB.1
+++ /dev/null
@@ -1,63 +0,0 @@
-.\"   $Id: MBK_CATA_LIB.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
-.\" @(#)MBK_CATA_LIB.8 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-MBK_CATA_LIB
-.XE \}
-.TH MBK_CATA_LIB 1 "October 1, 1997" "ASIM/LIP6" "MBK ENVIRONMENT VARIABLES"
-.SH NAME
-MBK_CATA_LIB \- define the mbk catalog directory
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-c-shell running
-setenv MBK_CATA_LIB path1:path2:path3:...:...:pathn
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH DESCRIPTION
-\fBMBK_CATA_LIB\fP sets the directories that are to be searched thru for
-reading. When instanciating a cell for example, the first cell that is found
-with the given name is loaded in memory.
-.br
-The seaching mecanism first look in
-\fBMBK_WORK_LIB\fP(1), and then, in path1 thru pathn, in the order defined by the
-user when typing the setenv command.
-This directories are considered to be, from a mbk point of view, read only.
-.br
-The pathi arguments must be actually accessible pathes on your host machine.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"mbk_fopen : can't open file 'unix_path/file.xx' thru directories : path1, ..., pathn"
-.ft R
-.RS
-This occurs when either the unix path is irrelevent, or when the file doesn't
-exist. This can also be a unix right problem if the file is not accessible for
-reading, but this is seldom.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-	setenv MBK_CATA_LIB ~fred/crechan/uom:/labo/sclib
-.ft R
-.fi
-.SH DIAGNOSTICS
-Only the first path may be given with a '~', since the shell extents it only
-when seen first.
-.SH SEE ALSO
-.BR mbk (1),
-.BR genlib (1),
-.BR MBK_WORK_LIB (1).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/MBK_FILTER_SFX.1 b/alliance/share/man/man1/MBK_FILTER_SFX.1
deleted file mode 100644
index bdd6c19e..00000000
--- a/alliance/share/man/man1/MBK_FILTER_SFX.1
+++ /dev/null
@@ -1,33 +0,0 @@
-.\"   $Id: MBK_FILTER_SFX.1,v 1.2 2000/11/20 12:43:37 gregoire Exp $
-
-.TH MBK_FILTER_SFX 1 "October 1, 1999" "ASIM/LIP6" "MBK ENVIRONMENT VARIABLES"
-
-.SH NAME
-MBK_FILTER_SFX \- define the input\/output filter suffixe.
-
-.so man1/alc_origin.1
-
-.SH DESCRIPTION
-\fBMBK_FILTER_SFX\fP tells to Alliance the extention set by compression tools.
-This variable must be set in order to activate filters. Note the leading points
-of extention must be set if necessary.
-
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-For compressed files with gzip :
-	setenv MBK_FILTER_SFX ".gz"
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR MBK_IN_FILTER (1),
-.BR MBK_OUT_FILTER (1),
-.BR mbkenv (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/MBK_IN_FILTER.1 b/alliance/share/man/man1/MBK_IN_FILTER.1
deleted file mode 100644
index 7c435725..00000000
--- a/alliance/share/man/man1/MBK_IN_FILTER.1
+++ /dev/null
@@ -1,39 +0,0 @@
-.\"   $Id: MBK_IN_FILTER.1,v 1.2 2000/11/20 12:43:37 gregoire Exp $
-
-.TH MBK_IN_FILTER 1 "October 1, 1999" "ASIM/LIP6" "MBK ENVIRONMENT VARIABLES"
-
-.SH NAME
-MBK_IN_FILTER \- define the input filter
-
-.so man1/alc_origin.1
-
-.SH DESCRIPTION
-\fBMBK_IN_FILTER\fP set the input filter for reading compressed Alliance files.
-Filter is typically a string containing filename and options. This filter
-must read compressed data flow on it standard input and write non compressed
-data flow on it standard output. Files are taken in the first directory where
-they are found according to the environment variable \fbMBK_CATA_LIB\fb. If a
-file compressed version and a file non compressed version exist booth in the
-same directory, the non compressed is opended, and a warning message is
-supllyed. To activate filters, variable \fbMBK_FILTER_SFX\fb must be set.
-
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-Opening compressed files with gzip :
-	setenv MBK_IN_FILTER "/asim/gnu/bin/gunzip -c"
-	setenv MBK_FILTER_SFX ".gz"
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR MBK_FILTER_SFX (1),
-.BR MBK_OUT_FILTER (1),
-.BR mbkenv (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/MBK_IN_LO.1 b/alliance/share/man/man1/MBK_IN_LO.1
deleted file mode 100644
index 0fcd45ba..00000000
--- a/alliance/share/man/man1/MBK_IN_LO.1
+++ /dev/null
@@ -1,64 +0,0 @@
-.\"   $Id: MBK_IN_LO.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
-.\" @(#)MBK_IN_LO.8 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-MBK_IN_LO
-.XE \}
-.TH MBK_IN_LO 1 "October 1, 1997" "ASIM/LIP6" "MBK ENVIRONMENT VARIABLES"
-.SH NAME
-MBK_IN_LO \- define the logical input format of mbk and genlib
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-c-shell running
-setenv MBK_IN_LO format
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH DESCRIPTION
-\fBMBK_IN_LO\fP sets the logical input format of the mbk database. The database
-will be filled with informations found in the given format file.
-.TP
-valid formats are :
-\- \fBal\fP, \fBalx\fP, that are alliance logical formats
-.br
-\- \fBedi\fP, that is edif standart netlist format
-.br
-\- \fBhns\fP, \fBfns\fP, \fBfne\fP, \fBfdn\fP, \fBhdn\fP, that are vti logical
-formats
-.br
-\- \fBspi\fP, that's spice netlist
-.br
-\- \fBvst\fP, that structural vhdl description
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"MBK_IN_LO : 'xxx' unknown format"
-.ft R
-.RS
-The argument given to the setenv is not a legal logical input format for mbk.
-You must changed it before any other action.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-	setenv MBK_IN_LO al
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR genlib (1),
-.BR MBK_OUT_LO (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/MBK_IN_PH.1 b/alliance/share/man/man1/MBK_IN_PH.1
deleted file mode 100644
index 0bd8f66b..00000000
--- a/alliance/share/man/man1/MBK_IN_PH.1
+++ /dev/null
@@ -1,58 +0,0 @@
-.\"   $Id: MBK_IN_PH.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
-.\" @(#)MBK_IN_PH.8 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-MBK_IN_PH
-.XE \}
-.TH MBK_IN_PH 1 "October 1, 1997" "ASIM/LIP6" "MBK ENVIRONMENT VARIABLES"
-.SH NAME
-MBK_IN_PH \- define the physical input format of mbk and genlib
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-c-shell running
-setenv MBK_IN_PH format
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH DESCRIPTION
-\fBMBK_IN_PH\fP sets the physical input format of the mbk data structure.
-The data structure will be filled with informations found in the given format
-file.
-.TP
-valid formats are :
-\- \fBap\fP, alliance physical format
-.br
-\- \fBcp\fP, vti physical format
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"MBK_IN_PH : 'xxx' unknown format"
-.ft R
-.RS
-The argument given to the setenv is not a legal physical input format for mbk.
-You must changed it before any other action.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-	setenv MBK_IN_PH al
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR genlib (1),
-.BR MBK_OUT_PH (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/MBK_OUT_FILTER.1 b/alliance/share/man/man1/MBK_OUT_FILTER.1
deleted file mode 100644
index a40751c8..00000000
--- a/alliance/share/man/man1/MBK_OUT_FILTER.1
+++ /dev/null
@@ -1,39 +0,0 @@
-.\"   $Id: MBK_OUT_FILTER.1,v 1.2 2000/11/20 12:43:37 gregoire Exp $
-
-.TH MBK_OUT_FILTER 1 "October 1, 1999" "ASIM/LIP6" "MBK ENVIRONMENT VARIABLES"
-
-.SH NAME
-MBK_OUT_FILTER \- define the input filter
-
-.so man1/alc_origin.1
-
-.SH DESCRIPTION
-\fBMBK_OUT_FILTER\fP sets the output filter for writting compressed Alliance
-files. Filter is typically a string containing filename and options. This filter
-must read non compressed data flow on it standard input and write compressed
-data flow on it standard output. If a non compressed version of a file exist in
-the same target directory the designer want the save a file's compressed
-version, to ensure that file will be read later and not the non compressed one,
-the non compressed file is DELETED.  To activate filters, variable
-MBK_FILTER_SFX must be set.
-
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-Writing compressed files with gzip :
-	setenv MBK_OUT_FILTER "/asim/gnu/bin/gzip -c"
-	setenv MBK_FILTER_SFX ".gz"
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR MBK_FILTER_SFX (1),
-.BR MBK_IN_FILTER (1),
-.BR mbkenv (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/MBK_OUT_LO.1 b/alliance/share/man/man1/MBK_OUT_LO.1
deleted file mode 100644
index e49823de..00000000
--- a/alliance/share/man/man1/MBK_OUT_LO.1
+++ /dev/null
@@ -1,70 +0,0 @@
-.\"   $Id: MBK_OUT_LO.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
-.\" @(#)MBK_OUT_LO.8 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-MBK_OUT_LO
-.XE \}
-.TH MBK_OUT_LO 1 "October 1, 1997" "ASIM/LIP6" "MBK ENVIRONMENT VARIABLES"
-.SH NAME
-MBK_OUT_LO \- define the logical output format of mbk and genlib
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-c-shell running
-setenv MBK_OUT_LO format
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIparam\fP
-pwet
-.SH DESCRIPTION
-\fBMBK_OUT_LO\fP sets the logical output format of the mbk data structure.
-The files resulting of the work on mbk will have the given format. 
-.TP
-valid formats are :
-\- \fBal\fP, \fBalx\fP, that are alliance logical formats
-.br
-\- \fBcct\fP, that is genrad hilo netlist format
-.br
-\- \fBedi\fP, that is edif standart netlist format
-.br
-\- \fBhns\fP, \fBfns\fP, \fBfne\fP, \fBfdn\fP, \fBhdn\fP, that are vti logical
-formats
-.br
-\- \fBspi\fP, that's spice netlist
-.br
-\- \fBvst\fP, that is structural vhdl description
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"MBK_OUT_LO : 'xxx' unknown format"
-.ft R
-.RS
-The argument given to the setenv is not a legal logical output format for mbk.
-You must changed it before any other action.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-	setenv MBK_OUT_LO al
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR genlib (1),
-.BR MBK_IN_LO (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/MBK_OUT_PH.1 b/alliance/share/man/man1/MBK_OUT_PH.1
deleted file mode 100644
index bc408844..00000000
--- a/alliance/share/man/man1/MBK_OUT_PH.1
+++ /dev/null
@@ -1,57 +0,0 @@
-.\"   $Id: MBK_OUT_PH.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
-.\" @(#)MBK_OUT_PH.8 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-MBK_OUT_PH
-.XE \}
-.TH MBK_OUT_PH 1 "October 1, 1997" "ASIM/LIP6" "MBK ENVIRONMENT VARIABLES"
-.SH NAME
-MBK_OUT_PH \- define the physical output format of mbk and genlib
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-c-shell running
-setenv MBK_OUT_PH format
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH DESCRIPTION
-\fBMBK_OUT_PH\fP sets the physical output format of the mbk data structure.
-The files resulting of the work on mbk will have the given format. 
-.TP
-valid formats are :
-\- \fBap\fP, for alliance physical output
-.br
-\- \fBcp\fP, in order to obtain a vti physical file
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"MBK_OUT_PH : 'xxx' unknown format"
-.ft R
-.RS
-The argument given to the setenv is not a legal physical output format for mbk.
-You must changed it before any other action.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-	setenv MBK_OUT_PH al
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR genlib (1),
-.BR MBK_IN_PH (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/MBK_SEPAR.1 b/alliance/share/man/man1/MBK_SEPAR.1
deleted file mode 100644
index 6f949b05..00000000
--- a/alliance/share/man/man1/MBK_SEPAR.1
+++ /dev/null
@@ -1,43 +0,0 @@
-.\"   $Id: MBK_SEPAR.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
-.\" @(#)MBK_SEPAR.8 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-MBK_SEPAR
-.XE \}
-.TH MBK_SEPAR 1 "October 1, 1997" "ASIM/LIP6" "MBK ENVIRONMENT VARIABLES"
-.SH NAME
-MBK_SEPAR \- define the separator character for hierarchy
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-c-shell running
-setenv MBK_SEPAR character
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH DESCRIPTION
-\fBMBK_SEPAR\fP sets the character that is to be used while concatening
-names, during a flatten, for example.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-	setenv MBK_SEPAR /
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR genlib (1),
-.BR concatname (3),
-.BR nameindex (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/MBK_TRACE_GETENV.1 b/alliance/share/man/man1/MBK_TRACE_GETENV.1
deleted file mode 100644
index 2e2ca013..00000000
--- a/alliance/share/man/man1/MBK_TRACE_GETENV.1
+++ /dev/null
@@ -1,30 +0,0 @@
-.\" Alliance man
-.\" Author: Czo <Olivier.Sirol@lip6.fr>
-.\" $Id: MBK_TRACE_GETENV.1,v 1.1 2001/11/02 14:51:10 czo Exp $
-.TH MBK_TRACE_GETENV 1 "$Date: 2001/11/02 14:51:10 $" "ASIM/LIP6" "MBK ENVIRONMENT VARIABLES"
-.SH NAME
-\fBMBK_TRACE_GETENV\fP \- defines getenv() debug output
-
-.so man1/alc_origin.1
-
-.SH SYNOPSIS
-.TP
-.TP
-Bourne Shell : \fBMBK_TRACE_GETENV\fR=\fIyes\fR; export MBK_TRACE_GETENV
-.TP
-C-shell : sentenv \f4MBK_TRACE_GETENV\fR \fIyes\fR
-
-.SH DESCRIPTION
-If \fBMBK_TRACE_GETENV\fR is set to "yes", all alliance tools will print debug info to stdout each time a  getenv() syscall is done.
-
-.SH OUTPUT EXAMPLE
-.RS
-\f4--- mbk --- mbkgetenv VH_PATSFX : pat\fR
-
-.SH SEE ALSO
-.PP
-.BR mbk(1)
-.BR mbkgetenv(3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/MBK_VDD.1 b/alliance/share/man/man1/MBK_VDD.1
deleted file mode 100644
index 0e44b0d3..00000000
--- a/alliance/share/man/man1/MBK_VDD.1
+++ /dev/null
@@ -1,46 +0,0 @@
-.\"   $Id: MBK_VDD.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
-.\" @(#)MBK_VDD.8 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-MBK_VDD
-.XE \}
-.TH MBK_VDD 1 "October 1, 1997" "ASIM/LIP6" "MBK ENVIRONMENT VARIABLES"
-.SH NAME
-MBK_VDD \- define the high level power name pattern
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-c-shell running
-setenv MBK_VDD powername
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH DESCRIPTION
-\fBMBK_VDD\fP sets the pattern to be matched in a name to indicate a power
-supply for the tools based upon \fBmbk\fP.
-Its default value is \fBvdd\fP.
-Therefore all names of the form `*\fBvdd\fP*' indicates a power supply.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-	setenv MBK_VDD vcc
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR genlib (1),
-.BR isvdd (3),
-.BR isvss (3),
-.BR MBK_VSS (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/MBK_VSS.1 b/alliance/share/man/man1/MBK_VSS.1
deleted file mode 100644
index 899f990f..00000000
--- a/alliance/share/man/man1/MBK_VSS.1
+++ /dev/null
@@ -1,46 +0,0 @@
-.\"   $Id: MBK_VSS.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
-.\" @(#)MBK_VSS.8 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-MBK_VSS
-.XE \}
-.TH MBK_VSS 1 "October 1, 1997" "ASIM/LIP6" "MBK ENVIRONMENT VARIABLES"
-.SH NAME
-MBK_VSS \- define the ground power name pattern
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-c-shell running
-setenv MBK_VSS groundname
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH DESCRIPTION
-\fBMBK_VSS\fP sets the pattern to be matched in a name to indicate a
-ground node for the tools based upon
-Its default value is \fBvss\fP.
-Therefore all names of the form `*\fBvss\fP*' in indicates a ground node.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-	setenv MBK_VSS gnd
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR genlib (1),
-.BR isvss (3),
-.BR isvdd (3),
-.BR MBK_VDD (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/MBK_WORK_LIB.1 b/alliance/share/man/man1/MBK_WORK_LIB.1
deleted file mode 100644
index 0098a534..00000000
--- a/alliance/share/man/man1/MBK_WORK_LIB.1
+++ /dev/null
@@ -1,60 +0,0 @@
-.\"   $Id: MBK_WORK_LIB.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
-.\" @(#)MBK_WORK_LIB.8 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-MBK_WORK_LIB
-.XE \}
-.TH MBK_WORK_LIB 1 "October 1, 1997" "ASIM/LIP6" "MBK ENVIRONMENT VARIABLES"
-.SH NAME
-MBK_WORK_LIB \- define the mbk working directory
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-c-shell running
-setenv MBK_WORK_LIB unix path
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH DESCRIPTION
-\fBMBK_WORK_LIB\fP sets the directory where are saved the results of an
-invocation of mbk or genlib. This directory is considered to be, from an
-mbk point of view, read and write.
-.br
-Also, when a file is searched for
-reading, the first directory to be looked at is the \fBMBK_WORK_LIB\fP, and then
-the one defined in \fBMBK_CATA_LIB\fP(1).
-.br
-The unix path argument must be a actually accessible path on your host machine.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"mbk_fopen : can't open file 'unix_path/file.xx'"
-.ft R
-.RS
-This occurs when either the unix path is irrelevent, or when the file doesn't
-exist if it is open for reading, or when you don't have the right on the file
-or directory while trying to write it.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-	setenv MBK_WORK_LIB ~fred/crechan/uom
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR genlib (1),
-.BR MBK_CATA_LIB (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/RDS_IN.1 b/alliance/share/man/man1/RDS_IN.1
deleted file mode 100644
index 1501d4e0..00000000
--- a/alliance/share/man/man1/RDS_IN.1
+++ /dev/null
@@ -1,90 +0,0 @@
-.\"   $Id: RDS_IN.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
-.\" @(#)RDS_IN.1 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.TH RDS_IN 1 "October 1, 1997" "ASIM/LIP6" "RDS ENVIRONEMENT VARIABLES"
-.SH NAME
-\fBRDS_IN\fP \- define the real layout input file format of rds
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-c-shell running
-setenv RDS_IN format
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH DESCRIPTION
-\fBRDS_IN\fP sets the physical real input file format of the rds data structure.
-The data structure will be filled with informations found in the given format
-files.
-.TP
-valid formats are :
-.RS
-\- \fBcif\fP, caltech intermediate file format
-.RS
-Some cif standard extensions are known :
-.TP
-\fB9\fP \fIname\fP;
-defines the name associated to the Define Symbol construct.
-.TP
-\fB4A\fP \fIx0 y0 x1 y1\fP;
-describes the abutment box of a model. see \fBmbk\fP(1) for more on
-abutment box.
-\fIx0, y0, x1, y1\fP are respectively the lower left corner, and the upper
-right corner of the abutment box.
-.TP
-\fB4I\fP \fIinstancename\fP;
-assigns a name to a Call Symbol.
-.TP
-\fB4X\fP \fIconnectorname width x y\fP;
-defines the pin called \fIconnectorname\fP, at \fIx,y\fP location,
-with the given \fIwidth\fP.
-This doesn't define a rectangle.
-.TP
-\fB4N\fP \fInodename x y\fP;
-gives a name to every object from the current layer that include the given
-point.
-.RS
-None of those extensions are generating layout, so a tool that skips cif extension will still have a correct and complete layout.
-.RE
-.br
-\- \fBgds\fP, calma format
-.RS
-The gds known is a subset without text, or specific extensions for connectors.
-.RE
-.RE
-.PP
-The licit objects are square polygones, with angle multiple of 90
-.ie t \(de.
-.el degrees.
-Circles, triangle, and other exotic objects, are strictly forbidden.
-You shall ensure that your real pads follow these rules before parsing them.
-.br
-The variable default value is ``gds''.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"RDS_IN : 'xxx' unknown format"
-.ft R
-.RS
-The argument given to the setenv is not a legal layout input format for rds.
-You must changed it before any other action.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-	setenv RDS_IN gds
-.ft R
-.fi
-.SH SEE ALSO
-.BR s2r (1),
-.BR RDS_OUT (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/RDS_OUT.1 b/alliance/share/man/man1/RDS_OUT.1
deleted file mode 100644
index 459db5b2..00000000
--- a/alliance/share/man/man1/RDS_OUT.1
+++ /dev/null
@@ -1,56 +0,0 @@
-.\"   $Id: RDS_OUT.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
-.\" @(#)RDS_OUT.1 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.TH RDS_OUT 1 "October 1, 1997" "ASIM/LIP6" "RDS ENVIRONEMENT VARIABLES"
-.SH NAME
-\fBRDS_OUT\fP \- define the real layout output format of rds
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-c-shell running
-setenv RDS_OUT format
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH DESCRIPTION
-\fBRDS_OUT\fP sets the physical real output format of the rds data structure.
-The data structure will be written in files of the given format.
-.TP
-valid formats are :
-\- \fBcif\fP, caltech intermediat format
-.br
-\- \fBgds\fP, calma format
-.PP
-The output file contains only rectangles, boxes for cif, and five vertices
-polygones for gds.
-.br
-The variable default value is ``gds''.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"RDS_OUT : 'xxx' unknown format"
-.ft R
-.RS
-The argument given to the setenv is not a legal layout output format for rds.
-You must changed it before any other action.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-	setenv RDS_OUT gds
-.ft R
-.fi
-.SH SEE ALSO
-.BR s2r (1),
-.BR RDS_IN (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/RDS_TECHNO_NAME.1 b/alliance/share/man/man1/RDS_TECHNO_NAME.1
deleted file mode 100644
index 7b1ba240..00000000
--- a/alliance/share/man/man1/RDS_TECHNO_NAME.1
+++ /dev/null
@@ -1,39 +0,0 @@
-.\"   $Id: RDS_TECHNO_NAME.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
-.\" @(#)RDS_TECHNO_NAME.1 2.11 92/09/16; Labo Cao-vlsi; Author : Frederic Petrot
-.TH RDS_TECHNO_NAME 1 "October 1, 1997" "ASIM/LIP6" "RDS ENVIRONEMENT VARIABLES"
-.SH NAME
-\fBRDS_TECHNO_NAME\fP \- define the rds technology file
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-c-shell running
-setenv RDS_TECHNO_NAME file
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH DESCRIPTION
-\fBRDS_TECHNO_NAME\fP sets the name of the technology file that indicates
-how to translate from symbolic layout to real process layout.
-This file is to be edited by a technologist in order to parametrize the
-\fBs2r\fP(1) tool for proper operation.
-.br
-It default value is \fBALLIANCE_ETC/prol15.rds\fP.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-	setenv RDS_TECHNO_NAME /alliance/etc/PROL15.rds
-	setenv RDS_TECHNO_NAME idps.rds
-.ft R
-.fi
-.SH SEE ALSO
-.BR s2r (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/abl.1 b/alliance/share/man/man1/abl.1
deleted file mode 100644
index 4e88adcb..00000000
--- a/alliance/share/man/man1/abl.1
+++ /dev/null
@@ -1,235 +0,0 @@
-.\"   $Id: abl.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
-.\" @(#)log.l 0.0 92/08/01 UPMC; Author: Luc Burgun 
-.pl -.4
-.TH ABL 1 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-.SH NAME
-\fBabl\fP \- Prefixed representation for boolean functions
-.so man1/alc_origin.1
-.SH DESCRIPTION
-\fIlibablmmm.a\fP is a library that enables to represent a boolean function in a LISP-like form. An ABL is a prefixed internal representation for a boolean function having standard operators as OR,NOR,NAND,XOR,NOT and AND. An ABL is only made up of doublets. A doublet is composed of two fields wich are accessible by the functionnal \fI#define\fP \fICAR\fP and \fICDR\fP. A doublet is implemented with a MBK \fIchain_list\fP. 
-.br
-\fIExpression\fP is the generic term for a boolean function represented by an ABL. An expression can be an atomic expression or an operator expression. The function \fBf = a\fP is represented by an atomic expression whereas \fBf = (or a b)\fP is represented by an operator expression. An atomic expression is made up of a single doublet having the \fINEXT\fP pointer equal to NULL and \fIDATA\fP pointer equal to the identifier pointer. A constant atomic expression is an atomic expression having the string  "'0'" or "'1'" as identifier.
-.br
-An operator expression is more complicated than an atomic expression. It's a list of items, the first item is the head operator of the expression and the following items are the arguments of the expression. It's possible to go trough the arguments by calling the functionnal \fI#define\fP \fICDR\fP. Then each argument is accessible by the functionnal \fI#define\fP \fICAR\fP. An argument can be recursively an atomic or an operator expression. The arity of an operator expression is the number of arguments of the first level. 
-.br
-.br
-Functions are divided into two groups, the low level functions are written with \fI#define\fP and are used to manage the ABL internal form, the high level functions are used to manage the boolean expressions. All functions are defined in the file "prefbib.c" (\fI#define\fP in "logmmm.h").
-.TP
-\fIFunctionnal #define\fP
-.TP 20
-\fBATOM\fP
-\- checks the kind of an expression (atomic or operator expression). 
-.TP 20
-\fBCAR\fP
-\- returns the \fIDATA\fP pointer of a doublet.
-.TP 20
-\fBCADR\fP
-\- returns the \fIDATA\fP pointer of the \fINEXT\fP pointer of a doublet.
-.TP 20
-\fBCDR\fP
-\- returns the \fINEXT\fP pointer of a doublet.
-.TP 20
-\fBOPER\fP
-\- returns the operator number of an operator expression.
-.TP 20
-\fBVALUE_ATOM\fP
-\- returns the associated \fIchar *\fP of an atomic expression.
-.br
-.TP
-\fIFunctions and procedures\fP
-.TP 20
-\fBaddHExpr\fP
-\- adds a new arguments at the head of an operator expression. 
-.TP 20
-\fBaddQExpr\fP
-\- adds a new arguments at the queue of an operator expression. 
-.TP 20
-\fBanyExpr\fP
-\- returns the value of a logical OR applied on the results of the application of a function on the arguments of an operator expression.
-.TP 20
-\fBchangeOperExpr\fP
-\- changes the operator of the head of an expression.
-.TP 20
-\fBcharToOper\fP
-\- converts an operator string into an operator number.
-.TP 20
-\fBcopyExpr\fP
-\- copies an expression. 
-.TP 20
-\fBcreateAtom\fP
-\- creates an atomic expression. 
-.TP 20
-\fBcreateBinExpr\fP
-\- creates a binary operator expression with an eventual merging of the operator. 
-.TP 20
-\fBcreateExpr\fP
-\- creates the head of an operator expression. 
-.TP 20
-\fBdeleteNumExpr\fP
-\- removes the i-th argument in an operator expression. 
-.TP 20
-\fBdevXor2Expr\fP
-\- converts XOR 2 to OR-AND.
-.TP 20
-\fBdevXorExpr\fP
-\- removes XOR in an expression. 
-.TP 20
-\fBdisplayExpr\fP
-\- displays an expression in a prefixed notation. 
-.TP 20
-\fBdisplayInfExpr\fP
-\- displays an expression in infixed notation. 
-.TP 20
-\fBequalExpr\fP
-\- checks that two expressions are strictly equal. 
-.TP 20
-\fBequalVarExpr\fP
-\- checks that two expressions are syntactically equal. 
-.TP 20
-\fBeveryExpr\fP
-\- returns the value of a logical AND applied on the results of the application of a function on the arguments of an operator expression.
-.TP 20
-\fBexprToChar\fP
-\- converts an expression into a string.
-.TP 20
-\fBcharToExpr\fP
-\- converts a string into an expression.
-.TP 20
-\fBflatArityExpr\fP
-\- flattens the operators of an expression. 
-.TP 20
-\fBflatPolarityExpr\fP
-\- translates the inverters of an expression to the level of atomic expressions. 
-.TP 20
-\fBfreeExpr\fP
-\- frees an expression. 
-.TP 20
-\fBidentExpr\fP
-\- gives an identifier from an operator expression. 
-.TP 20
-\fBlengthExpr\fP
-\- returns the number of arguments in an expression. 
-.TP 20
-\fBmapCarExpr\fP
-\- creates a new expression by applying a function to all arguments of an operator expression. 
-.TP 20
-\fBmapExpr\fP
-\- applies a procedure to all the arguments of an operator expression. 
-.TP 20
-\fBmaxExpr\fP
-\- returns the highest argument of an operator expression. 
-.TP 20
-\fBminExpr\fP
-\- returns the lowest argument of an operator expression. 
-.TP 20
-\fBnormExpr\fP
-\- normalizes an expression. 
-.TP 20
-\fBnotExpr\fP
-\- complements an expression and eventually does a simplification. 
-.TP 20
-\fBnumberAtomExpr\fP
-\- returns the number of atoms in an expression.
-.TP 20
-\fBnumberOccExpr\fP
-\- returns the number of time an atom appears in an expression. 
-.TP 20
-\fBnumberOperBinExpr\fP
-\- returns the number of equivalent binary operators in an expression.
-.TP 20
-\fBoperToChar\fP
-\- converts an operator number into an operator string. 
-.TP 20
-\fBprofExpr\fP
-\- returns the depth of an expression. 
-.TP 20
-\fBprofAOExpr\fP
-\- returns the depth of an expression without taking the inverters into account. 
-.TP 20
-\fBsearchExpr\fP
-\- searches for a specific atom in an expression. 
-.TP 20
-\fBsearchNumExpr\fP
-\- fetches the i-th argument in an operator expression. 
-.TP 20
-\fBsearchOperExpr\fP
-\- searches for an operator in an expression. 
-.TP 20
-\fBsimplif10Expr\fP
-\- makes simplifications on an expression including constant atomic expressions.  
-.TP 20
-\fBsimplifNotExpr\fP
-\- makes simplifications on an expression including inverters.  
-.TP 20
-\fBsortExpr\fP
-\- sorts an expression. 
-.TP 20
-\fBsubstExpr\fP
-\- copies an expression by substituting a given atom by an expression. 
-.TP 20
-\fBsubstPhyExpr\fP
-\- substitutes an atomic expression by an expression within an expression. 
-.TP 20
-\fBsupportChain_listExpr\fP
-\- returns the support of an expression in a \fIchain_list\fP. 
-.TP 20
-\fBsupportPtype_listExpr\fP
-\- returns the support of an expression in a \fIptype_list\fP. 
-.TP 20
-\fBwPMExpr\fP
-\- returns 1 if the pattern matching is possible between two expressions.
-
-.br
-.SH SEE ALSO
-.BR log (1),
-.BR mbk (1),
-.BR addHExpr (3),
-.BR addQExpr (3),
-.BR anyExpr (3),
-.BR changeOperExpr (3),
-.BR charToExpr (3),
-.BR charToOper (3),
-.BR copyExpr (3),
-.BR createAtom (3),
-.BR createBinExpr (3),
-.BR createExpr (3),
-.BR deleteNumExpr (3),
-.BR devXor2Expr (3),
-.BR devXorExpr (3),
-.BR displayExpr (3),
-.BR displayInfExpr (3),
-.BR equalExpr (3),
-.BR equalVarExpr (3),
-.BR everyExpr (3),
-.BR exprToChar (3),
-.BR flatArityExpr (3),
-.BR flatPolarityExpr (3),
-.BR freeExpr (3),
-.BR identExpr (3),
-.BR lengthExpr (3),
-.BR mapCarExpr (3),
-.BR mapExpr (3),
-.BR maxExpr (3),
-.BR minExpr (3),
-.BR notExpr (3),
-.BR normExpr (3),
-.BR numberAtomExpr (3),
-.BR numberOccExpr (3),
-.BR numberOperBinExpr (3),
-.BR operToChar (3),
-.BR profExpr (3),
-.BR profAOExpr (3),
-.BR searchExpr (3),
-.BR searchNumExpr (3),
-.BR searchOperExpr (3),
-.BR simplif10Expr (3),
-.BR simplifNotExpr (3),
-.BR sortExpr (3),
-.BR substExpr (3),
-.BR substPhyExpr (3),
-.BR supportChain_listExpr (3),
-.BR supportPtype_listExpr (3).
-.BR PMExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/abl101.1 b/alliance/share/man/man1/abl101.1
deleted file mode 100644
index d648691c..00000000
--- a/alliance/share/man/man1/abl101.1
+++ /dev/null
@@ -1,310 +0,0 @@
-.\"   $Id: abl101.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
-.\" @(#)abl.1 1.01 96/02/07 UPMC; Author : Jacomme Ludovic
-.TH ABL101 1 "October 1, 1997" "ASIM/LIP6" "ALLIANCE ABL LIBRARY"
-.SH NAME
-abl \- Prefixed representation for boolean functions
-.so man1/alc_origin.1
-.SH DESCRIPTION
-\fBabl\fP is a library that enables to represent a boolean
-function in a LISP-like form. An \fIABL\fP is a prefixed representation
-for a boolean function having standard operators as ABL_NOT, ABL_AND, ABL_OR,
-ABL_XOR, ABL_NAND, ABL_NOR, ABL_NXOR and CTL operators as ABL_AF, ABL_AG, ABL_AX,
-ABL_AU, ABL_EF, ABL_EG, ABL_EX and ABL_EU.
-An ABL is only made up of doublets. A doublet is composed of two fields 
-wich are accessible by \fIABL_CAR\fP and \fIABL_CDR\fP macro-functions.
-A doublet is implemented with a \fImbk\fP \fIchain_list\fP.
-"Expression" is the generic term for a boolean function represented by an ABL.
-An expression can be an atomic expression or an operator expression.
-The function \fBf = a\fP is represented by an atomic expression whereas
-\fBf = (or a b)\fP is represented by an operator expression.
-An atomic expression is made up of a single doublet having 
-the \fINEXT\fP pointer equal to NULL
-and \fIDATA\fP pointer equal to the identifier pointer.
-A constant atomic expression is an atomic expression having the 
-string "'0'", "'1'" or "'d'" as identifier.
-An operator expression is more complicated than an atomic expression.
-It's a list of items, the first item is the head operator of the expression and
-the following items are the arguments of the expression.
-It's possible to go trough the arguments by calling \fIABL_CDR\fP.
-Then each argument is accessible by \fIABL_CAR\fP.
-An argument can be recursively an atomic or an operator expression.
-The arity of an operator expression is the number of arguments of the first level.
-
-.TP
-Macro-functions :
-.TP 20
-.br
-\fBABL_CDR( E )\fP
-\- gives the \fINEXT\fP field of a \fIchain_list\fP.
-.TP
-\fBABL_CAR( E )\fP
-\- gives the \fIDATA\fP field of a \fIchain_list\fP.
-.TP
-\fBABL_CADR( E )\fP
-\- gives the \fINEXT->DATA\fP field.
-.TP
-\fBABL_CDDR( E )\fP
-\- gives the \fINEXT->NEXT\fP field.
-.TP
-\fBABL_ATOM( E )\fP
-\- True if the expression is atomic.
-.TP
-\fBABL_ATOM_VALUE( E )\fP
-\- Value of an atom in an expression.
-.TP
-\fBABL_OPER( E )\fP
-\- Operator number in an expression.
-
-.TP
-Functions :
-.TP 20
-.br
-\fBaddablqexpr\fP
-\- appends an expression to another one.
-.TP
-\fBaddablhexpr\fP
-\- adds an expression in the head of another one.
-.TP
-\fBcreateablatom\fP
-\- creates an atomic expression.
-.TP
-\fBcreateabloper\fP
-\- creates a the head of an operator expression. 
-.TP
-\fBcreateablbinexpr\fP
-\- creates a binary expression.
-.TP
-\fBcreateablnotexpr\fP
-\- complements an expression.
-.TP
-\fBcreateablxorbinexpr\fP
-\- creates an 'xor' or 'xnor' operator expression.
-.TP
-\fBcreateablunaryexpr\fP
-\- creates an unary expression.
-.TP
-\fBdelablexpr\fP
-\- deletes an expression.
-.TP
-\fBdelablexprnum\fP
-\- deletes a specified operand.
-.TP
-\fBdevdupablxorexpr\fP
-\- duplicates and develops 'xor', 'nxor'.
-.TP
-\fBdevablxorexpr\fP
-\- develops 'xor', 'xnor'.
-.TP
-\fBdupablexpr\fP
-\- duplicates an expression.
-.TP
-\fBflatablexpr\fP
-\- merges the operators of an expression.
-.TP
-\fBfreeablexpr\fP
-\- deletes an expression.
-.TP
-\fBgetablopername\fP
-\- gives the name of an operator number.
-.TP
-\fBgetabloperuppername\fP
-\- gives the upper name of an operator number.
-.TP
-\fBgetabloperpolar\fP
-\- gives the polarity of an operator.
-.TP
-\fBgetablopernot\fP
-\- gives the complement of an operator.
-.TP
-\fBgetabloperbyname\fP
-\- gives the operator number using a name.
-.TP
-\fBgetablatomone\fP
-\- gives the name "'1'"
-.TP
-\fBgetablatomzero\fP
-\- gives the name "'0'"
-.TP
-\fBgetablatomdc\fP
-\- gives the name "'d'"
-.TP
-\fBgetablexprdepth\fP
-\- returns the depth of an expression.
-.TP
-\fBgetablexprlength\fP
-\- returns the length of an expression.
-.TP
-\fBgetablexprnumatom\fP
-\- returns the number of atom in an expression.
-.TP
-\fBgetablexprnumbinoper\fP
-\- returns the number of binary operator.
-.TP
-\fBgetablexprsupport\fP
-\- gives the support of an expression.
-.TP
-\fBgetablexprnumocc\fP
-\- gives the number of occurent of a name.
-.TP
-\fBgetablexprmax\fP
-\- applies a maximum cost function.
-.TP
-\fBgetablexprmin\fP
-\- applies a minimum cost function.
-.TP
-\fBgetablexprnum\fP
-\- returns a specified operand.
-.TP
-\fBinitablatomname\fP
-\- initialize atom static name.
-.TP
-\fBinitablopername\fP
-\- initialize operator static name.
-.TP
-\fBinitabloperbinary\fP
-\- sets the binary operator mode on.
-.TP
-\fBinitablname\fP
-\- initialize all the static names.
-.TP
-\fBisablunaryoper\fP
-\- tests if an operator is unary.
-.TP
-\fBisablbinaryoper\fP
-\- tests if an operator is binary.
-.TP
-\fBisabloperinexpr\fP
-\- tests if an oper appears in an expression.
-.TP
-\fBisablnameinexpr\fP
-\- tests if a name appears in an expression.
-.TP
-\fBisablequalexpr\fP
-\- tests if two expressions are equals.
-.TP
-\fBisablsimilarexpr\fP
-\- tests if two expressions are similars.
-.TP
-\fBmapablexpr\fP
-\- applies a function to the operand's expression.
-.TP
-\fBmapabloperexpr\fP
-\- applies a function to the operand's expression.
-.TP
-\fBmapablanyexpr\fP
-\- applies a function to the operand's expression.
-.TP
-\fBmapableveryexpr\fP
-\- applies a function to the operand's expression.
-.TP
-\fBpolardupablexpr\fP
-\- moves and duplicates inverters to the atomic level.
-.TP
-\fBpolarablexpr\fP
-\- moves inverters to the atomic level.
-.TP
-\fBsimpdupablexpr\fP
-\- duplicates and simplifies an expression.
-.TP
-\fBsimpablexpr\fP
-\- simplifies an expression.
-.TP
-\fBstrablexpr\fP
-\- parses a prefixed string an creates expression.
-.TP
-\fBsubstablexpr\fP
-\- substitutes an expression in another one.
-.TP
-\fBsubstdupablexpr\fP
-\- duplicates and substitutes an expression in another one.
-.TP
-\fBunflatablexpr\fP
-\- unflats the operators of an expression.
-.TP
-\fBvhdlablname\fP
-\- returns a compatible VHDL name.
-.TP
-\fBvhdlablvector\fP
-\- gives the index and the name of a vector.
-.TP
-\fBviewablexprfile\fP
-\- displays an expression in a file.
-.TP
-\fBviewablexpr\fP
-\- displays an expression.
-.TP
-\fBviewablexprstr\fP
-\- displays an expression in a string.
-
-.TP 0
-libAbl101.a :
-
-\fBaddablqexpr\fP,
-\fBaddablhexpr\fP,
-\fBcreateablatom\fP,
-\fBcreateabloper\fP,
-\fBcreateablbinexpr\fP,
-\fBcreateablnotexpr\fP,
-\fBcreateablxorbinexpr\fP,
-\fBcreateablunaryexpr\fP,
-\fBnormablctlexpr\fP,
-\fBsimpablctlexpr\fP,
-\fBdelablexpr\fP,
-\fBdelablexprnum\fP,
-\fBdevdupablxorexpr\fP,
-\fBdevablxorexpr\fP,
-\fBdupablexpr\fP,
-\fBflatablexpr\fP,
-\fBfreeablexpr\fP,
-\fBgetablopername\fP,
-\fBgetabloperuppername\fP,
-\fBgetabloperpolar\fP,
-\fBgetablopernot\fP,
-\fBgetabloperbyname\fP,
-\fBgetablatomone\fP,
-\fBgetablatomzero\fP,
-\fBgetablatomdc\fP,
-\fBgetablexprdepth\fP,
-\fBgetablexprlength\fP,
-\fBgetablexprnumatom\fP,
-\fBgetablexprnumbinoper\fP,
-\fBgetablexprsupport\fP,
-\fBgetablexprnumocc\fP,
-\fBgetablexprmax\fP,
-\fBgetablexprmin\fP,
-\fBgetablexprnum\fP,
-\fBinitablatomname\fP,
-\fBinitablopername\fP,
-\fBinitabloperbinary\fP,
-\fBinitablname\fP,
-\fBisablunaryoper\fP,
-\fBisablbinaryoper\fP,
-\fBisabloperinexpr\fP,
-\fBisablnameinexpr\fP,
-\fBisablequalexpr\fP,
-\fBisablsimilarexpr\fP,
-\fBmapablexpr\fP,
-\fBmapabloperexpr\fP,
-\fBmapablanyexpr\fP,
-\fBmapableveryexpr\fP,
-\fBpolardupablexpr\fP,
-\fBpolarablexpr\fP,
-\fBsimpdupexpr\fP,
-\fBsimpdupablexpr\fP,
-\fBsimpablexpr\fP,
-\fBstrablexpr\fP,
-\fBsubstablexpr\fP,
-\fBsubstdupablexpr\fP,
-\fBunflatablexpr\fP,
-\fBvhdlablname\fP,
-\fBvhdlablvector\fP,
-\fBviewablexprfile\fP,
-\fBviewablexpr\fP,
-\fBviewablexprstr\fP.
-
-.SH SEE ALSO
-.BR \fBmbk\fP(1),
-.BR \fBaut\fP(1).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/alc_bug_report.1 b/alliance/share/man/man1/alc_bug_report.1
deleted file mode 100644
index e87aefdf..00000000
--- a/alliance/share/man/man1/alc_bug_report.1
+++ /dev/null
@@ -1,18 +0,0 @@
-.\" $Id: alc_bug_report.1,v 1.2 1999/09/22 13:53:19 czo Exp $
-.\" 
-.\" Generic footer for alliance man pages
-.\" 
-
-.SH BUG REPORT
-
-This tool is under development at the
-.B ASIM/LIP6/UPMC
-laboratory, cao-vlsi research team.
-.br
-We need your feedbak to improve documentation and tools.
-.br
-If you find bugs, please fill-in the form at
-.br
-.I http://www\-asim.lip6.fr/alliance/support/bug\-report/ 
-.br
-Thanks for doing this.
diff --git a/alliance/share/man/man1/alc_contents.mac b/alliance/share/man/man1/alc_contents.mac
deleted file mode 100644
index 82df59c1..00000000
--- a/alliance/share/man/man1/alc_contents.mac
+++ /dev/null
@@ -1,275 +0,0 @@
-.\" $Id: alc_contents.mac,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" 
-.\" ****************************
-.\" ******** module toc ********
-.\" ****************************
-.\" Table of contents generation.
-.de XS
-.da toc*div
-.ev h
-.par@reset
-.fi
-.ie \\n[.$] .XA "\\$1"
-.el .XA
-..
-.de @div-end!toc*div
-.XE
-..
-.de XA
-.ie '\\n(.z'toc*div' \{\
-.	if d toc*num .toc*end-entry
-.	ie \\n[.$] \{\
-.		ie '\\$1'no' .ds toc*num
-.		el .ds toc*num "\\$1
-.	\}
-.	el .ds toc*num \\n[PN]
-.	in (n;0\\$2)
-.\}
-.el .@error XA without XS
-..
-.de XE
-.ie '\\n(.z'toc*div' \{\
-.	if d toc*num .toc*end-entry
-.	ev
-.	di
-.\}
-.el .@error XS without XE
-..
-.de toc*end-entry
-\\a\\t\\*[toc*num]
-.br
-.rm toc*num
-..
-.de PX
-.nf
-.lc .
-.ta (u;\\n[.l]-\\n[.i]-\w'000') (u;\\n[.l]-\\n[.i])R
-.sp 2
-.toc*div
-.par@reset
-..
-.\" Table of contents generation.
-.de XS0
-.da toc0*div
-.ev h
-.par@reset
-.fi
-.ie \\n[.$] .XA0 "\\$1"
-.el .XA0
-..
-.de @div-end!toc0*div
-.XE0
-..
-.de XA0
-.ie '\\n(.z'toc0*div' \{\
-.	if d toc0*num .toc0*end-entry
-.	ie \\n[.$] \{\
-.		ie '\\$1'no' .ds toc0*num
-.		el .ds toc0*num "\\$1
-.	\}
-.	el .ds toc0*num \\n[PN]
-.	in (n;0\\$2)
-.\}
-.el .@error XA0 without XS0
-..
-.de XE0
-.ie '\\n(.z'toc0*div' \{\
-.	if d toc0*num .toc0*end-entry
-.	ev
-.	di
-.\}
-.el .@error XS0 without XE0
-..
-.de toc0*end-entry
-\\a\\t\\*[toc0*num]
-.br
-.rm toc0*num
-..
-.de PX0
-.nf
-.lc .
-.ta (u;\\n[.l]-\\n[.i]-\w'000') (u;\\n[.l]-\\n[.i])R
-.sp 2
-.toc0*div
-.par@reset
-..
-.\" Table of contents generation.
-.de XS1
-.da toc1*div
-.ev h
-.par@reset
-.fi
-.ie \\n[.$] .XA1 "\\$1"
-.el .XA1
-..
-.de @div-end!toc1*div
-.XE1
-..
-.de XA1
-.ie '\\n(.z'toc1*div' \{\
-.	if d toc1*num .toc1*end-entry
-.	ie \\n[.$] \{\
-.		ie '\\$1'no' .ds toc1*num
-.		el .ds toc1*num "\\$1
-.	\}
-.	el .ds toc1*num \\n[PN]
-.	in (n;0\\$2)
-.\}
-.el .@error XA1 without XS1
-..
-.de XE1
-.ie '\\n(.z'toc1*div' \{\
-.	if d toc1*num .toc1*end-entry
-.	ev
-.	di
-.\}
-.el .@error XS1 without XE1
-..
-.de toc1*end-entry
-\\a\\t\\*[toc1*num]
-.br
-.rm toc1*num
-..
-.de PX1
-.nf
-.lc .
-.ta (u;\\n[.l]-\\n[.i]-\w'000') (u;\\n[.l]-\\n[.i])R
-.sp 2
-.toc1*div
-.par@reset
-..
-.\" Table of contents generation.
-.de XS2
-.da toc2*div
-.ev h
-.par@reset
-.fi
-.ie \\n[.$] .XA2 "\\$1"
-.el .XA2
-..
-.de @div-end!toc2*div
-.XE2
-..
-.de XA2
-.ie '\\n(.z'toc2*div' \{\
-.	if d toc2*num .toc2*end-entry
-.	ie \\n[.$] \{\
-.		ie '\\$1'no' .ds toc2*num
-.		el .ds toc2*num "\\$1
-.	\}
-.	el .ds toc2*num \\n[PN]
-.	in (n;0\\$2)
-.\}
-.el .@error XA2 without XS2
-..
-.de XE2
-.ie '\\n(.z'toc2*div' \{\
-.	if d toc2*num .toc2*end-entry
-.	ev
-.	di
-.\}
-.el .@error XS2 without XE2
-..
-.de toc2*end-entry
-\\a\\t\\*[toc2*num]
-.br
-.rm toc2*num
-..
-.de PX2
-.nf
-.lc .
-.ta (u;\\n[.l]-\\n[.i]-\w'000') (u;\\n[.l]-\\n[.i])R
-.sp 2
-.toc2*div
-.par@reset
-..
-.\" Table of contents generation.
-.de XS3
-.da toc3*div
-.ev h
-.par@reset
-.fi
-.ie \\n[.$] .XA3 "\\$1"
-.el .XA3
-..
-.de @div-end!toc3*div
-.XE3
-..
-.de XA3
-.ie '\\n(.z'toc3*div' \{\
-.	if d toc3*num .toc3*end-entry
-.	ie \\n[.$] \{\
-.		ie '\\$1'no' .ds toc3*num
-.		el .ds toc3*num "\\$1
-.	\}
-.	el .ds toc3*num \\n[PN]
-.	in (n;0\\$2)
-.\}
-.el .@error XA3 without XS3
-..
-.de XE3
-.ie '\\n(.z'toc3*div' \{\
-.	if d toc3*num .toc3*end-entry
-.	ev
-.	di
-.\}
-.el .@error XS3 without XE3
-..
-.de toc3*end-entry
-\\a\\t\\*[toc3*num]
-.br
-.rm toc3*num
-..
-.de PX3
-.nf
-.lc .
-.ta (u;\\n[.l]-\\n[.i]-\w'000') (u;\\n[.l]-\\n[.i])R
-.sp 2
-.toc3*div
-.par@reset
-..
-.\" Table of contents generation.
-.de XS4
-.da toc4*div
-.ev h
-.par@reset
-.fi
-.ie \\n[.$] .XA4 "\\$1"
-.el .XA4
-..
-.de @div-end!toc4*div
-.XE4
-..
-.de XA4
-.ie '\\n(.z'toc4*div' \{\
-.	if d toc4*num .toc4*end-entry
-.	ie \\n[.$] \{\
-.		ie '\\$1'no' .ds toc4*num
-.		el .ds toc4*num "\\$1
-.	\}
-.	el .ds toc4*num \\n[PN]
-.	in (n;0\\$2)
-.\}
-.el .@error XA4 without XS4
-..
-.de XE4
-.ie '\\n(.z'toc4*div' \{\
-.	if d toc4*num .toc4*end-entry
-.	ev
-.	di
-.\}
-.el .@error XS4 without XE4
-..
-.de toc4*end-entry
-\\a\\t\\*[toc4*num]
-.br
-.rm toc4*num
-..
-.de PX4
-.nf
-.lc .
-.ta (u;\\n[.l]-\\n[.i]-\w'000') (u;\\n[.l]-\\n[.i])R
-.sp 2
-.toc4*div
-.par@reset
-..
diff --git a/alliance/share/man/man1/alc_origin.1 b/alliance/share/man/man1/alc_origin.1
deleted file mode 100644
index 937d5124..00000000
--- a/alliance/share/man/man1/alc_origin.1
+++ /dev/null
@@ -1,34 +0,0 @@
-.\" $Id: alc_origin.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
-.\" 
-.\" Generic header for alliance man pages
-.\" 
- 
-.SH ORIGIN
-This software belongs to the
-.I ALLIANCE
-CAD system from the
-CAO-VLSI team at 
-.B ASIM/LIP6/UPMC
-laboratory. 
-.br
-.ce
-LIP6/ASIM
-.br
-.ce
-University P. et M. Curie
-.br
-.ce
-4, place Jussieu 
-.br
-.ce
-75252 PARIS Cedex 05
-.br
-.ce
-FRANCE
-.br
-Fax : {33/0} 1.44.27.62.86
-.br
-E-mail support : 
-.I alliance\-support@asim.lip6.fr
-
-
diff --git a/alliance/share/man/man1/alcbanner.1 b/alliance/share/man/man1/alcbanner.1
deleted file mode 100644
index 90a09895..00000000
--- a/alliance/share/man/man1/alcbanner.1
+++ /dev/null
@@ -1,78 +0,0 @@
-
-.TH ALCBANNER 1 "October 1, 1997" "ASIM/LIP6" "ALLIANCE USER COMMANDS"
-
-.SH NAME
-\fBalcbanner\fP \- Display a standardized banner for Alliance tools
-
-.so man1/alc_origin.1
-
-
-.SH SYNOPSIS
-.TP
-\f4alcbanner\fR \fItool toolversion purpose copyrightdates\fR
-
-.SH DESCRIPTION
-\f4alcbanner\fR display on \f4stdout\fP a standardized banner for the Alliance
-tools.
-This is a compiled version of the \f4alliancebanner\fR(2) function.
-
-
-.SH EXAMPLE
-.RS
-\f4alcbanner GenPat 3.1 "Procedural GENeration of test PATterns" 1991\fR
-
-.RE
-will display :
-.ft 4
-.nf
-
-
-             @@@@ @                        @@@@@@@                      
-           @@    @@                          @@   @@               @    
-          @@      @                          @@    @@             @@    
-         @@             @@@@@   @@@ @@@      @@    @@   @@@@      @@    
-         @@            @     @   @@@   @     @@   @@   @@   @   @@@@@@@@
-         @@     @@@@@ @@     @@  @@    @@    @@@@@     @@   @@    @@    
-         @@     @ @@  @@@@@@@@@  @@    @@    @@          @@@@@    @@    
-         @@    @  @@  @@         @@    @@    @@        @@   @@    @@    
-          @@      @@  @@      @  @@    @@    @@       @@    @@    @@    
-           @@    @@    @@    @@  @@    @@    @@       @@   @@@    @@   @
-             @@@@        @@@@   @@@@  @@@@ @@@@@@      @@@@  @@    @@@@ 
-
-                     Procedural GENeration of test PATterns
-
-                  Alliance CAD System 3.2b,          genpat 3.1
-                  Copyright (c) 1991-1997,       ASIM/LIP6/UPMC
-                  E-mail support: alliance-support@asim.lip6.fr
-
-
-.fi
-.ft R
-
-.SH SEE ALSO
-.PP
-.BR mbk(1)
-.BR alliancebanner (3).
-
-
-.SH DIAGNOSTICS
-
-The output is centered for a 80 columns screen, so it can be used on most
-display easilly, and not found at execution time.
-
-\f4alliancebanner: Error: Resulting size bigger than 80 columns not allowed\fR
-.RS
-The \fItool\fR argument must be such that its resulting size isn't wider that
-80 culumns.
-This means, since the character set is proportional, that the longest name
-to be output is about 8 characters long.
-.RE
-\f4alliancebanner: Error: Character out of [0-9A-Za-z] range\fR
-.RS
-The \fItool\fR parameter has a non allowed character in it.
-For simplicity purposes, only numbers and letters are accepted.
-.RE
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/algue.1 b/alliance/share/man/man1/algue.1
deleted file mode 100644
index 770b61b0..00000000
--- a/alliance/share/man/man1/algue.1
+++ /dev/null
@@ -1,18 +0,0 @@
-.\" $Id: algue.1,v 1.1 1999/10/12 15:42:23 czo Exp $
-
-.TH algue 1 "$Date: 1999/10/12 15:42:23 $" "ASIM/LIP6" "ALLIANCE  Reference Manual"
-
-.SH NAME
-algue \- ALliance Graphic User Environement
-
-.so man1/alc_origin.1
-
-.SH DESCRIPTION
-Algue is a graphical environnement that let you lauch every
-Alliance tool in press button way.
-
-.SH SEE ALSO
-.BR alliance(1).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/ali.1 b/alliance/share/man/man1/ali.1
deleted file mode 100644
index d2d16ec1..00000000
--- a/alliance/share/man/man1/ali.1
+++ /dev/null
@@ -1,51 +0,0 @@
-.\" $Id: ali.1,v 1.4 2000/08/25 12:01:41 syf Exp $
-
-.TH ali 1 "$Date: 2000/08/25 12:01:41 $" "ASIM/LIP6" "ALLIANCE  Reference Manual"
-
-.SH NAME
-ali \- ALliance Information
-
-.so man1/alc_origin.1
-
-.SH DESCRIPTION
-ali is a small script used to display Alliance environnemnt variables 
-
-.SH EXAMPLE
-
-Alliance settings :
-
-ALLIANCE_OS          = Linux_elf
-ALLIANCE_OS      = Linux_elf
-ALLIANCE_TOP              = /users/cao/czo/cvstree/alliance/archi/Linux_elf
-ALLIANCE_TOP     = /users/cao/czo/cvstree/alliance/archi/Linux_elf
-ALLIANCE_VERSION = '"3.5.9"'
-
-DREAL_TECHNO_NAME=/users/cao/czo/cvstree/alliance/archi/Linux_elf/etc/cmos_7.dreal
-ELP_TECHNO_NAME=/users/cao/czo/cvstree/alliance/archi/Linux_elf/etc/prol10.elp
-GRAAL_TECHNO_NAME=/users/cao/czo/cvstree/alliance/archi/Linux_elf/etc/cmos_7.graal
-MBK_C4_LIB=./cellsC4
-MBK_CATAL_NAME=CATAL
-MBK_CATA_LIB=.:/users/cao/czo/cvstree/alliance/archi/Linux_elf/cells/sxlib:/users/cao/cz
-o/cvstree/alliance/archi/Linux_elf/cells/padlib
-MBK_IN_LO=vst
-MBK_IN_PH=ap
-MBK_OUT_LO=vst
-MBK_OUT_PH=ap
-MBK_SCALE_X=10
-MBK_TARGET_LIB=/users/cao/czo/cvstree/alliance/archi/Linux_elf/cells/sxlib
-MBK_VDD=vdd
-MBK_VSS=vss
-MBK_WORK_LIB=.
-RDS_TECHNO_NAME=/users/cao/czo/cvstree/alliance/archi/Linux_elf/etc/cmos_7.rds
-VH_BEHSFX=vbe
-VH_DLYSFX=dly
-VH_MAXERR=10
-VH_PATSFX=pat
-XFSM_PARAM_NAME=/users/cao/czo/cvstree/alliance/archi/Linux_elf/etc/xfsm.par
-XPAT_PARAM_NAME=/users/cao/czo/cvstree/alliance/archi/Linux_elf/etc/xpat.par
-
-.SH SEE ALSO
-.BR alliance(1).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/amg.1 b/alliance/share/man/man1/amg.1
deleted file mode 100644
index 89383c0a..00000000
--- a/alliance/share/man/man1/amg.1
+++ /dev/null
@@ -1,165 +0,0 @@
-.\"   $Id: amg.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
-.\" @(#)LABO.1 0.0 91/04/02 UPMC;AUTHOR:Philippe ROYANNEZ
-.TH AMG 1 "October 1, 1997" "ASIM/LIP6" "ALLIANCE USER COMMANDS"
-.SH NAME
-AMG \- Array Multiplior Generator
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B amg
-.I <size1>
-.I <size2>
-.B [ -t0 -t1 -n=<integer> ]
-.B [ -virtual -msb0 ]
-.B [ -layout -vhdl -datasheet -icon -patterns]
-.B [ -o <BlockName> ]
-.SH DESCRIPTION
-	amg provides several different views of a booth multiplier with or without pipeline.
-The multiplier generated respects a bit-slice topologie and can be inserted in a data path.
-.LP
-The Interface is the following
-
-.br
-.ul
-unpipelined multiplier:
-.br
-
-ENTITY \fIamg\fP IS
-.TP
-PORT	(
-\fIa\fP: IN	BIT_VECTOR (\fIM-1\fP DOWNTO 0);
-.br
-\fIb\fP: IN	BIT_VECTOR (\fIN-1\fP DOWNTO 0);
-.br
-\fIp\fP: OUT	BIT_VECTOR (\fI(N+M-1)\fP DOWNTO 0);
-.br
-\fIVdd\fP: IN BIT;
-.br
-\fIVss\fP: IN BIT
-.br
-);
-.br
-END \fIamg\fP;
-.br
-
-.TP
-.ul
-pipelined multiplier:
-.TP
-ENTITY \fIamg\fP IS
-.TP
-PORT	(
-\fIa\fP:	IN	BIT_VECTOR (\fIM-1\fP DOWNTO 0),
-.br
-\fIb\fP:	IN	BIT_VECTOR (\fIN-1\fP DOWNTO 0),
-.br
-\fIp\fP:	OUT	BIT_VECTOR (\fI(N+M-1)\fP DOWNTO 0),
-.br
-\fIck\fP:	IN 	BIT,
-.br
-\fIsd\fP:	IN 	BIT,
-.br
-\fIst\fP:	IN 	BIT,
-.br
-.br
-\fIscin\fP:	IN	BIT,
-.br
-\fIscout\fP:	OUT	BIT
-.br
-\fIVdd\fP: IN BIT;
-.br
-\fIVss\fP: IN BIT
-);
-.br
-END \fIamg\fP;
-
-.br
-.SH OPTIONS
-.TP 12
-.IB size1:
-is the first operand size. The range is from 6 to 64.It's an even number.
-.TP 12
-.IB size2:
-is the second operand size. The range is from 6 to 64. It's an even number.
-.TP 12
-.IB -msb0
-Default is index 0 for the least significant bit. When \fB-msb0\fP is present
-the the most significant bit is indexed with 0.
-.TP 12
-.IB -virtual
-Default blocks contain fixed terminals. Virtual terminals can be obtained
-using this option. This way,
-.BR dpr (1) router should optimized the resultant routed data-path.
-.TP 12
-.IB -layout:
-provides the layout view of the multiplier.
-.TP 12
-.IB -vhdl:
-gives a behavioural vhdl description of the multiplier
-.TP 12
-.IB -datasheet:
-provides technical informations about the multiplier like size value or propagation delays .
-.TP 12
-.IB -icon:
-provides an icon representing the generated multiplier
-.TP 12
-.IB -patterns:
-provides a set of test vectors in .pat format which is the format used by asimut
-.TP 12
-.IB -t0,-t1,-n:
-These parameters specifie the pipelined configuration
-.TP 12
-The global topologie is the following
-
-____________________________________________________
-.br
-		|				|	
-	DNC			MUX+CSA			CLA
-		|				|	
-____________________________________________________
-
-.br
-As it can be seen on the figure, the multiplier can be
-divided into three parts:
-.br
--> The input part is the DNC part. 
-.br
--> The central part is a succession of "mux column" and "csa column".
-.br
--> The output part is the final adder of the multiplication.
-.br
-
-t0: This parameter indicates if a "master-slave column" must be placed after the first part.
-.br
-* t0 -> after 
-.br
-* default -> none 
-.br
-
-t1: This parameter indicates if a "master-slave column" must be placed before the CLA.
-.br
-* t1 -> before
-.br
-* default -> none
-.br
-
-n: This parameter indicates the number of "master-slave columns" in the central part
-.br
-.TP 12
-.BI -o	BlockName:
-specifies the name of the generated multiplier.
-(default name is m<size1>x<size2> )
-.SH EXAMPLES
-.IP
-amg 32 32 -t0 -t1 -n=3 -layout -datasheet -vhdl  -o mult32
-.br
-
-Produces the layout, the datasheet, and the vhdl view of a 32 X 32 size multiplier with pipeline.
-.SH SEE ALSO
-.BR MBK_CATA_LIB (1) ,
-.BR MBK_WORK_LIB (1) ,
-.BR MBK_OUT_PH (1) ,
-.BR MBK_OUT_LO (1) ,
-.BR MBK_IN_PH (1) ,
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/asimut.1 b/alliance/share/man/man1/asimut.1
deleted file mode 100644
index 03f698f5..00000000
--- a/alliance/share/man/man1/asimut.1
+++ /dev/null
@@ -1,200 +0,0 @@
-.\"   $Id: asimut.1,v 1.3 1999/10/05 09:48:32 simcity Exp $
-.\" @(#)asimut.1 1.92  Nov 30 1995 UPMC; Pirouz BAZARGAN SABET
-.TH ASIMUT 1 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-
-.SH NAME
-.PP
-\fBasimut\fP \- A simulation tool for hardware descriptions
-
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.PP
-asimut \fI[options] [root_file] [pattern_file] [result_file]\fP
-
-.SH DESCRIPTION
-.PP
-\fBasimut\fP is a logical simulation tool for hardware descriptions. It
-compiles and loads a complete hardware description written in VHDL (Very
-high speed integrated circuits Hardware Description Language). The hardware
-description may be structural (a hierarchy of instances) or behavioural.
-Only a subset of VHDL is supported. Descriptions that do not
-match this subset cause a syntax error during compilation. See \fBvhdl(5)\fP
-for detailed information about the supported subset of VHDL.
-
-.PP
-Once a hardware description is loaded, \fBasimut\fP looks for a simulation
-pattern description file. This file is to be written in \fBpat\fP format.
-The file is compiled, loaded and linked with the hardware description. Then,
-the simulation is started. When patterns are processed, a result file in
-\fBpat\fP format is produced.
-
-.PP
-If a save action has been requested in the pattern description file (see
-\fBpat (5)\fP), \fBasimut\fP creates also a save file representing the state
-of the description at the end of the simulation of the last pattern. The save
-file is named \fIroot_file\fP.sav, where \fIroot_file\fP is the name of the
-description.
-
-.PP
-The save file can be used in a later simulation sequence to initialize the
-state of the (same) hardware description before the simulation begins.
-Using this mechanism, a large sequence of patterns can be breaked onto
-several small sequences, each one initializing the hardware description with
-the save file resulted from the previous sequence.
-
-.PP
-\fBasimut\fP reads several parameters from the environment variables :
-
-.TP 20
-\fIMBK_CATA_LIB\fP
-list of directories containing description and pattern files (using $PATH
-syntax). The default path is the current directory (see mbk(1)).
-.TP 20
-\fIMBK_WORK_LIB\fP
-specifies the current working directory. The working directory idicates the
-place where all output files are written.
-.TP 20
-\fIMBK_CATAL_NAME\fP
-Indicates the file where the behavioral description files are listed. This
-file is used to leaf cells of a structural description.(see mbk(1))
-.TP 20
-\fIMBK_IN_LO\fP
-file extension for structural entity. (see mbk(1))
-.TP 20
-\fIVH_BEHSFX\fP
-list of file extensions for behavioural entities (using $PATH syntax). The
-default file extension is \fBvbe\fP.
-.TP 20
-\fIVH_PATSFX\fP
-list of file extensions for pattern description entities (using $PATH syntax).
-The default file extension is \fBpat\fP.
-.TP 20
-\fIVH_DLYSFX\fP
-list of file extensions for delays description entities (using $PATH syntax).
-The default file extension is \fBdly\fP.
-.TP 20
-\fIVH_MAXERR\fP
-maximum number of errors allowed during simulation phase. If the number of
-errors occured during simulation reaches VH_MAXERR, \fBasimut\fP stops
-the simulation at the end of processing the current pattern. Patterns following
-the current pattern remain unprocessed and are reproduced in the result file.
-The default value of \fIVH_MAXERR\fP is 10.
-
-.PP
-\fIroot_file\fP is the name of the description.
-
-.PP
-By default \fBasimut\fP looks for a structural description. It uses the
-\fIMBK_IN_LO\fP environment variables to identify both the format and the
-extension of structural description files. To load structural VHDL files
-\fIMBK_IN_LO\fP must be set to \fBvst\fP.
-
-.PP
-To load a pure behavioural description \fB\-b\fP option must be specified. In
-such a case \fBasimut\fP loads a data flow VHDL description file. The
-\fIVH_BEHSFX\fP environment variable gives the extensions to be used.
-
-.PP
-\fIpattern_file\fP is the entity name of the pattern description. The file
-containing this entity must be named \fIpattern_file.ext\fP , where \fIext\fP
-is one of the extension specified in \fIVH_PATSFX\fP.
-
-.PP
-\fIresult_file\fP is the result file produced by \fBasimut\fP. The result file
-is a pattern description file with the extension specified by \fIVH_PATSFX\fP.
-
-.SH OPTIONS
-.TP 20
-\fI\-b\fP
-consider the \fIroot_file\fP description as a behavioural description
-.TP 20
-\fI\-backdelay [min, max, typ] delay_file\fP
-use file \fIdelay_file.ext\fP for delays backannotation, where \fIext\fP
-is one of the extension specified in \fIVH_DLYSFX\fP.
-.TP 20
-\fI\-bdd\fP
-use BDDs (Binary Decision Diagram) to represent expressions. Using this option
-makes the simulation be two times faster but increases memory requirement
-.TP 20
-\fI\-c\fP
-run only the compilation stage
-.TP 20
-\fI\-core core_file\fP
-at the first error encountered, dump the state of the circuit in both an
-ascii file (suffixed .cor) and a binary save file (suffixed .sav) which can
-be used as initialization file in a further session. If the \fI\-nores\fP
-option is specified a pattern file is also produced.
-.TP 20
-\fI\-dbg[sbpldc]\fP
-call the debugger (developper usage)
-.TP 20
-\fI\-defaultdelay (\-dd)\fP
-only null delays (no after clause in the VHDL file) are changed if
-backannotated delays or fixed delays are specified.
-.TP 20
-\fI\-fixeddelay value (\-fd value)\fP
-all delays of the description are fixed to \fIvalue\fP.
-.TP 20
-\fI\-h\fP
-display this help file
-.TP 20
-\fI\-i value\fP
-initialize all signals of the description with \fIvalue\fP. \fIValue\fP can
-be 0 or 1
-.TP 20
-\fI\-i save_file\fP
-read a save file and use it to initialize the state of the description before
-processing the first pattern (the file name cannot be 1 nor 0)
-.TP 20
-\fI\-inspect instance_name\fP
-produce a pattern file corresponding to the interface of the instance
-identified by \fIinstance-name\fP
-.TP 20
-\fI\-l n\fP
-print at most \fIn\fP characters for pattern labels. The default value for
-\fIn\fP is 15.
-.TP 20
-\fI\-nores\fP
-do not generate result file
-.TP 20
-\fI\-p n\fP
-load at most \fIn\fP patterns from input pattern file each time. Using this
-feature reduces memory allocation when a great number of patterns are to be
-simulated. In addition after the \fIn\fP patterns have been processed, the
-simulation result is printed in the result pattern file. The default value
-for \fIn\fP is 0 which makes the whole pattern
-file be loaded.
-.TP 20
-\fI\-t\fP
-trace signals when making BDDs (developper usage).
-.TP 20
-\fI\-transport\fP
-use transport delay model (default is inertial).
-.TP 20
-\fI\-zerodelay (\-zd)\fP
-all the delays of the VHDL description are supposed to be null delays.
-
-.SH EXAMPLE
-.PP
-asimut \-b \-i init_add adder_32 adder_patterns res_add
-.PP
-simulates a behavioural description held in the file named 'adder_32.vbe
-using the pattern file `adder_patterns.pat'. The simulation results is
-written into 'res_add.pat' and the description is initialized with the
-values contained in 'init_add.sav'.
-
-.SH DIAGNOSTICS
-.PP
-Register initializations in the pattern file allows changing the value of
-a register into a known value. However, using this feature to initialize a
-register before executing the first pattern is not recommended. Registers
-value (defined by the initialization statement) may be overwritten since
-description has not a coherent state before the first pattern.
-
-.SH SEE ALSO
-.PP
-vhdl(5), pat(5), genpat(1), mbk(1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/aut101.1 b/alliance/share/man/man1/aut101.1
deleted file mode 100644
index 35003672..00000000
--- a/alliance/share/man/man1/aut101.1
+++ /dev/null
@@ -1,143 +0,0 @@
-.\"   $Id: aut101.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
-.\" @(#)aut.1 1.01 96/02/07 UPMC; Author : Jacomme Ludovic
-.TH AUT101 1 "October 1, 1997" "ASIM/LIP6" "ALLIANCE AUT LIBRARY"
-.SH NAME
-aut \- Memory allocation, and hash tables management
-.so man1/alc_origin.1
-.SH DESCRIPTION
-\fBaut\fP is a set of utilities functions and types that may be useful.
-.TP
-Types :
-.TP 20
-.br
-\fBauthelem\fP
-\- Hash table element type.
-.TP
-\fBauthtable\fP
-\- Hash table type.
-.TP
-\fBauth2elem\fP
-\- Hash table element type.
-.TP
-\fBauth2table\fP
-\- Hash table type.
-
-.TP
-Functions :
-.TP 20
-.br
-\fBautallocblock\fP
-\- memory allocator
-.TP
-\fBautallocheap\fP
-\- heap memory allocator
-.TP
-\fBautresizeblock\fP
-\- resizes a memory block
-.TP
-\fBautfreeblock\fP
-\- releases a memory block
-.TP
-\fBautfreeheap\fP
-\- releases an heap memory block.
-.TP
-\fBautexit\fP
-\- encapsulates exit function.
-.TP
-\fBcreateauthtable\fP
-\- creates a simple hash table.
-.TP
-\fBdestroyauthtable\fP
-\- destroys a simple hash table.
-.TP
-\fBresetauthtable\fP
-\- resets a simple hash table.
-.TP
-\fBaddauthelem\fP
-\- adds an element in the hash table.
-.TP
-\fBdelauthelem\fP
-\- deletes an element in the hash table.
-.TP
-\fBsearchauthelem\fP
-\- searches an element in the hash table.
-.TP
-\fBviewauthelem\fP
-\- displays an hash table element.
-.TP
-\fBviewauthtable\fP
-\- displays an hash table.
-.TP
-\fBcreateauth2table\fP
-\- creates an hash table with two keys.
-.TP
-\fBdestroyauth2table\fP
-\- destroys an hash table with two keys.
-.TP
-\fBresetauth2table\fP
-\- resets an hash table with two keys.
-.TP
-\fBaddauth2elem\fP
-\- adds an element in the hash table.
-.TP
-\fBdelauth2elem\fP
-\- deletes an element in the hash table.
-.TP
-\fBsearchauth2elem\fP
-\- searches an element in the hash table.
-.TP
-\fBviewauth2elem\fP
-\- displays an hash table element.
-.TP
-\fBviewauth2table\fP
-\- displays an hash table with two keys.
-.TP
-\fBsortautcompare\fP
-\- default heap sort comparison function.
-.TP
-\fBsortautarray\fP
-\- heap sort.
-
-.TP 0
-libAut101.a :
-
-\fBautallocblock\fP,
-\fBautallocblock\fP,
-\fBautresizeblock\fP,
-\fBautfreeblock\fP,
-\fBautfreeheap\fP,
-\fBautexit\fP,
-\fBsetauthfunc\fP,
-\fBgetauthsize\fP,
-\fBgetauthkey\fP,
-\fBgetauthindex\fP,
-\fBcheckauthkey\fP,
-\fBcreateauthtable\fP,
-\fBdestroyauthtable\fP,
-\fBresetauthtable\fP,
-\fBstretchauthtable\fP,
-\fBaddauthelem\fP,
-\fBdelauthelem\fP,
-\fBsearchauthelem\fP,
-\fBviewauthelem\fP,
-\fBviewauthtable\fP,
-\fBsetauth2func\fP,
-\fBgetauth2size\fP,
-\fBgetauth2key\fP,
-\fBgetauth2index\fP,
-\fBcheckauth2key\fP,
-\fBcreateauth2table\fP,
-\fBdestroyauth2table\fP,
-\fBresetauth2table\fP,
-\fBstretchauth2table\fP,
-\fBaddauth2elem\fP,
-\fBdelauth2elem\fP,
-\fBsearchauth2elem\fP,
-\fBviewauth2elem\fP,
-\fBviewauth2table\fP,
-\fBsortautcompare\fP,
-\fBsortautarray\fP,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/bbr.1 b/alliance/share/man/man1/bbr.1
deleted file mode 100644
index 5a97cb8a..00000000
--- a/alliance/share/man/man1/bbr.1
+++ /dev/null
@@ -1,216 +0,0 @@
-.\"   $Id: bbr.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
-.\" @(#)Labo.l 0.0 90/22/08 UPMC; Author: Frederic Petrot
-.\" make a choice for Bold font thru the entire doc
-.ie t \{\
-.fp 4 C \}
-.el \{\
-.fp 4 B \}
-.TH BBR 1 "October 1, 1997" "ASIM/LIP6" "ALLIANCE USER COMMANDS"
-.SH NAME
-bbr \- A pitchless channel router for preplaced two blocks floorplan
-.SH SYNOPSIS
-.TP
-\f4bbr\fR \fIplanet\fR [ \f4-v\fR ] [ \f4-o \fIfilename\fR ] [ \fIsupply width\fR ]
-.so man1/alc_origin.1
-.SH DESCRIPTION
-The goal of \f4bbr\fR is to interconnect two, and only two, macro-blocks
-through a routing channel.
-.TP 20
-Input files
-Its first argument, \fIplanet\fR, is the name of two views of a figure.
-.br
-The layout one, with the constraint that only two instances must be placed,
-and that they must abut in such a way that \f4bbr\fR can deduce the channel.
-And the structural one, that describes the interconnections to be made.
-Consistency checks are done to ensure routability of the nets.
-.PP
-The nets are of two types for \f4bbr\fR, the \fIsimple nets\fR, that are
-routed in minimum width with the symbolic channel router, see \f4scr\fR(1), and
-the \fIspecial nets\fR, like \fIpower\fR, \fIground\fR and \fIclock\fR, that
-are handled specifically by bbr.
-.TP 20
-Simple nets
-\f4bbr\fR looks for the validity of a net, checking that either all the
-connectors linked to the net are accessible in the channel, or that there is
-a single connector not to be routed in the channel.
-.TP
-Special nets
-When a supplies is demanded, either one or two wires are drawn parallel to the
-channel, depending on the location of the connectors on the blocks.
-Supplies are \fInot\fR connected together by the router.
-\f4bbr\fR will not be confused with \fIspecial nets\fR having the same name
-but not beeing connected together.
-This will lead to an explicit unexpected renaming of some physical external
-connectors.
-.LP
-Physical connectors can be present in the placement file, in order to specify
-some constraints to the router.
-Two positions are legal :
-.TP 20
-Right on the channel coordinate
-If a connector is placed where the two block abut, then it will be used as
-routing point on the given side of the channel.
-It is legal to put several connectors at the same coordinate, since the channel
-width is zero when starting.
-The router will choose a track for each of them, so there is no warranty on the
-relative order of connectors on the orthogonal faces of the channel.
-.TP 20
-On the parallel external sides of the block
-If a feed through is detected in the instance under the connector, the
-router will use the track to reach the channel.
-.LP
-The external connectors appearing in the netlist file but not in the placement
-file are physically created on a randomly choosen face of the channel. 
-.LP
-The physical connectors to appear in the interface of the block are the one
-declared in the netlist.
-Other instance connectors will not be copied up.
-.SH CONSTRAINTS
-As \f4bbr\fR is only a channer router, not a floorplan one, the design must
-ensure routability.
-.PP
-Both the instances must have single \fIpower\fP and \fIground\fP signals.
-These signals should be available in the channel, as \fBbbr\fR must
-tie them to realize the input netlist.
-.PP
-All instance connectors not in the channel should appear as connectors of the
-top level figure.
-Otherwise \fBbbr\fR will complain that it can't route them together.
-.SH OPTIONS
-.TP 20
-\f4-v\fR
-produces a verbose output, giving the time needed for each step of the routing
-process.
-Some statistics on the number of vias and the wire length are also displayed.
-.TP
-\f4-o \fIfilename\fR
-renames the output file name to \fIfilename\fR.
-By default, the name of the input placement file is used, suffixed by \f4_f\fR.
-.TP
-\fIsupply width\fR
-indicates the signals to be considered as supplies.
-These signals are not going to be routed by the channel router, but will
-be drawn straigth through the channel, with wires of \fIwidth\fR lambda wide.
-Any number of power supplies and crucial clock may be specified that way.
-.SH EXAMPLES
-.RS
-\f4bbr bank+rom -v vddb 12 vddr 12 vssb 10 vddr 12\fR
-.RE
-will create a \f4bank+rom_f.cp\fR file in the current directory, displaying the
-routing phases, and adding four supplies, two on the bank side, two on the rom
-side.
-.SH OUTPUT FILE
-.TP 20
-\fIname.xx\fP
-Where name is \fIplanet\fP or \f4filename\fP if \f4-o\fP is specified, and
-\fIxx\fP the file format chosen with the \f4MBK_OUT_PH\fP(1) environment
-variable.
-.SH ENVIRONMENT VARIABLES
-\f4bbr\fR relies on the proper setting of the following enviroment variables :
-.TP 20
-\f4MBK_CATA_LIB\fR(1)
-gives the path to the cell libraries.
-Since \f4bbr\fR doesn't dive deep into the blocks, only the instances'
-models must be on the search path.
-.TP
-\f4MBK_WORK_LIB\fR(1)
-furnishes the path to the working directory.
-.TP
-\f4MBK_IN_PH\fR(1)
-indicates the input layout file format.
-.TP
-\f4MBK_OUT_PH\fR(1)
-indicates the output layout file format.
-.TP
-\f4MBK_IN_LO\fR(1)
-indicates the input structural file format.
-.SH SEE ALSO
-.BR mbk(1),
-.BR scr(1),
-.BR MBK_CATA_LIB(1),
-.BR MBK_WORK_LIB(1),
-.BR MBK_IN_PH(1),
-.BR MBK_OUT_PH(1),
-.BR MBK_IN_LO(1).
-
-.SH DIAGNOSTICS
-\f4no physical instance\fR
-.br
-\f4only one physical instance placed\fR
-.br
-\f4more than two physical instance placed\fR
-.RS
-There must be two and only two instances in the logical and placement file
-in order for \f4bbr\fR to work.
-.RE
- 
-\f4unexpected logical instance 'name'\fR
-\f4instance 'x' has physical model 'y' and logical model 'z'\fR
-.RS
-The name of the logical and physical instances does not match, so the two views
-are inconsistent.
-.RE
- 
-\f4the channel cannot be found from the placement\fR
-.RS
-The instance placement is not so that \f4bbr\fP can deduce the channel
-direction and coordinates.
-It's probably either a misuse of \f4bbr\fR or a designer error.
-.RE
- 
-\f4cannot route connectors 'a' and 'b' together\fR
-.RS
-The two connectors are logically connected, but do not belong to the
-channel, so it's not possible to connect them.
-\f4bbr\fP is \fInot\fP a floorplan router.
-These connector placement issues must be known before using \f4bbr\fR.
-.RE
- 
-\f4unable to change layer on edges of channel for connector '%s'\fR
-.RS
-A hand placed connector is wanted with a given layer in contradiction with
-the prefered routing layer.
-.RE
- 
-\f4connector '%s' changed to minimum width\fR
-.RS
-A hand placed connector is wanted with a given with, but \f4bbr\fR can
-handle only minimun width wires, but for supplies.
-.RE
- 
-\f4connector '%s' different from channel y, %d != %d, thus ignored\fR
-.br
-\f4connector '%s' different from channel x, %d != %d, thus ignored\fR
-.RS
-A hand placed connector is not on the initial channel coordinate.
-.RE
- 
-\f4connector '%s' is not on EAST or WEST face of the figure, thus ignored\fR
-.br
-\f4connector '%s' is not on SOUTH or NORTH face of the figure, thus ignored\fR
-.RS
-A hand placed connector is not on an expected face for the router.
-.RE
- 
-\f4no logical external connector equivalent to phisical '%s'\fR
-.RS
-A hand placed physical connector has no logical equivalent, thus leading
-to an inconsistence between the two views.
-.RE
- 
-\f4connector '%s' on a feed through of a different layer\fR
-.RS
-A hand placed physical connector has a layer conflicting with the feed
-through it's placed on.
-.RE
- 
-\f4not enough empty tracks for correct supplies connections\fR
-.RS
-In certain cases where the channel is dense and many supplies are wanted,
-the router may no be able to connected all the supplies together, because
-of a lack of track.
-There ain't nothing much to do.
-.RE
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/bdd.1 b/alliance/share/man/man1/bdd.1
deleted file mode 100644
index ec5a5fb8..00000000
--- a/alliance/share/man/man1/bdd.1
+++ /dev/null
@@ -1,176 +0,0 @@
-.\"   $Id: bdd.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
-.\" @(#)log.l 0.0 92/08/01 UPMC; Author: Luc Burgun 
-.pl -.4
-.TH BDD 1 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-.SH NAME
-\fBbdd\fP \- Ordered binary decision diagrams representation
-.so man1/alc_origin.1
-.SH DESCRIPTION
-\fIlibbdd.a\fP is a library that allows the representation of a boolean function by a binary decision diagram (BDD). A BDD is a canonical graphic representation for a boolean function. This canonical form enables to test for equivalence or satisfiability.
-All the functions produce a reduced graph. The number of nodes is limited to 500.000 nodes corresponding to 10 Mb in memory.
-.br
-Functions are divided into two groups, the zero level functions (suffixed by \fIBdd\fP) are used to manage BDDs at a low level. A unique \fIIndex\fP must be associated to a identifier signal and the BDDs have to be create by calling the \fBapplyBdd()\fP function. The first level functions (suffixed by \fICct\fP) manage a multi-BDD associated to a combinatory part of a logical circuit. This description can be considered like a set of boolean equations : 
-.br
-Output0 = F0(Input0, ... ,Inputn), ... ,Outputm = Fm(Input0, ... ,Inputn). 
-.br
-Each function F0, .. , Fn is represented by a BDD in wich each \fIinput\fP is associated to an \fIindex\fP.
-.TP
-\fILow level functions and procedures\fP
-.TP 20
-\fBaddListBdd\fP
-\- adds a BDD to a chained list of BDDs.
-.TP 20
-\fBapplyBdd\fP
-\- applies an operator to a list of BDDs.
-.TP 20
-\fBapplyBinBdd\fP
-\- applies an operator to two BDDs. 
-.TP 20
-\fBcomposeBdd\fP
-\- substitutes an index by a BDD in another BDD.  
-.TP 20
-\fBconstraintBdd\fP
-\- restricts a BDD to another BDD. 
-.TP 20
-\fBcreateNodeTermBdd\fP
-\- creates a terminal node of primary input.
-.TP 20
-\fBdestroyBdd\fP
-\- removes the BDDs system. 
-.TP 20
-\fBdisplayBdd\fP
-\- displays a BDD. 
-.TP 20
-\fBgcNodeBdd\fP
-\- does a garbage collection. 
-.TP 20
-\fBinitializeBdd\fP
-\- initializes the BDDs system. 
-.TP 20
-\fBmarkAllBdd\fP
-\- marks all the nodes of the BDDs system. 
-.TP 20
-\fBmarkBdd\fP
-\- marks all the nodes of a BDD. 
-.TP 20
-\fBnotBdd\fP
-\- complements a BDD.  
-.TP 20
-\fBnumberNodeAllBdd\fP
-\- counts the number of nodes used in the BDDs system. 
-.TP 20
-\fBnumberNodeBdd\fP
-\- counts the number of nodes used in a BDD. 
-.TP 20
-\fBresetBdd\fP
-\- resets the BDDs system. 
-.TP 20
-\fBsimplifDcOneBdd\fP
-\- simplifies a BDD with don't cares on its on-set part. 
-.TP 20
-\fBsimplifDcZeroBdd\fP
-\- simplifies a BDD with don't cares on its off-set part. 
-.TP 20
-\fBsupportChain_listBdd\fP
-\- returns a chained list of nodes that are used in a given BDD.
-.TP 20
-\fBupVarBdd\fP
-\- brings up an index in a BDD. 
-.TP
-\fIHigh level functions and procedures\fP
-.TP 20
-\fBablToBddCct\fP
-\- converts an ABL into a BDD within a circuit. 
-.TP 20
-\fBaddInputCct\fP
-\- adds an input to a circuit. 
-.TP 20
-\fBaddOutputCct\fP
-\- adds an output to a circuit. 
-.TP 20
-\fBbddToAblcct\fP
-\- converts a BDD into an ABL. 
-.TP 20
-\fBcomposeCct\fP
-\- composes all outputs within a circuit with a BDD. 
-.TP 20
-\fBcountNodeCct\fP
-\- counts the number of nodes used within a circuit. 
-.TP 20
-\fBconstraintCct\fP
-\- restricts all outputs with a BDD constraint within a circuit.
-.TP 20
-\fBcpOrderCct\fP
-\- copies the association order of the inputs with the indexes in another circuit. 
-.TP 20
-\fBdestroyCctfP
-\- removes a circuit. 
-.TP 20
-\fBdisplayCct\fP
-\- displays a circuit.
-.TP 20
-\fBgcNodeCct\fP
-\- does a garbarge collection. 
-.TP 20
-\fBinitializeCct\fP
-\- creates a circuit. 
-.TP 20
-\fBproofCct\fP
-\- checks the equivalence of two circuits.
-.TP 20
-\fBsearchInputCct\fP
-\- searches for the index number associated to an input.
-.TP 20
-\fBsearchOutputCct\fP
-\- searches for the BDD associated to an output. 
-.TP 20
-\fBresetCct\fP
-\- resets a circuit. 
-.TP 20
-\fBupVarCct\fP
-\- brings up the index of a primary input within a circuit.
-
-.br
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR addListBdd (3),
-.BR applyBdd (3),
-.BR applyBinBdd (3),
-.BR composeBdd (3),
-.BR constraintBdd (3),
-.BR createNodeTermBdd (3),
-.BR destroyBdd (3),
-.BR displayBdd (3),
-.BR gcNodeBdd (3),
-.BR initializeBdd (3),
-.BR markBdd (3),
-.BR markAllBdd (3),
-.BR notBdd (3),
-.BR numberNodeAllBdd (3),
-.BR numberNodeBdd (3),
-.BR resetBdd (3),
-.BR simplifDcOneBdd (3),
-.BR simplifDcZeroBdd (3),
-.BR supportChain_listBdd (3),
-.BR upVarBdd (3),
-.BR ablToBddCct (3),
-.BR addInputCct (3),
-.BR addOutputCct (3).
-.BR bddToAblCct (3).
-.BR composeCct (3),
-.BR constraintCct (3),
-.BR cpOrderCct (3),
-.BR destroyCct (3),
-.BR displayCct (3),
-.BR gcNodeCct (3),
-.BR initializeCct (3),
-.BR numberNodeCct (3),
-.BR proofCct (3),
-.BR resetCct (3),
-.BR searchInputCct (3),
-.BR searchOutputCct (3),
-.BR upVarCct (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/bdd101.1 b/alliance/share/man/man1/bdd101.1
deleted file mode 100644
index ceaa4c70..00000000
--- a/alliance/share/man/man1/bdd101.1
+++ /dev/null
@@ -1,479 +0,0 @@
-.\"   $Id: bdd101.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
-.\" @(#)bdd.1 1.01 96/02/07 UPMC; Author : Jacomme Ludovic
-.TH BDD101 1 "October 1, 1997" "ASIM/LIP6" "ALLIANCE BDD LIBRARY"
-.SH NAME
-bdd \-  Mutli Reduced Ordered Binary Decision Diagrams
-.so man1/alc_origin.1
-.SH DESCRIPTION
-\fBbdd\fP is a library that enables to represent a boolean expression
-as a Multi Reduced Ordered Binary Decision Diagrams.
-.TP 20
-.br
-\fBviewbddallocinfo\fP
-\- displays memory informations.
-.TP
-\fBapplybddnodenot\fP
-\- complements a \fBbdd\fP.
-.TP
-\fBapplybddnodeterm\fP
-\- applies an operator on two \fBbdd\fP nodes.
-.TP
-\fBapplybddnode\fP
-\- applies an operator on two \fBbdd\fP nodes.
-.TP
-\fBapplybddnodeite\fP
-\- computes the IF-THEN-ELSE  logical operation.
-.TP
-\fBapplybddnodelist\fP
-\- applies an opertor to a \fBbdd\fP nodes list.
-.TP
-\fBaddbddassoc\fP
-\- creates a new association variables.
-.TP
-\fBaddbddnodeassoc\fP
-\- adds a \fBbdd\fP node in a variable association.
-.TP
-\fBdelbddassoc\fP
-\- deletes a variable association.
-.TP
-\fBdelbddnodeassoc\fP
-\- deletes a \fBbdd\fP node in a variable association.
-.TP
-\fBdestroybddassoc\fP
-\- frees all the variable associations.
-.TP
-\fBviewbddassoc\fP
-\- displays variable associations.
-.TP
-\fBcheckbddvar\fP
-\- checks the coherence of a variable.
-.TP
-\fBcheckbddindex\fP
-\- checks the coherence of a \fBbdd\fP index.
-.TP
-\fBcheckbddoper\fP
-\- ckecks the coherence of an operator.
-.TP
-\fBcheckbddassoc\fP
-\- checks a variable association.
-.TP
-\fBcheckbddmaxnode\fP
-\- checks if the max node reached.
-.TP
-\fBcreatebddcircuit\fP
-\- creates a \fBbdd\fP circuit.
-.TP
-\fBresetbddcircuit\fP
-\- resets a \fBbdd\fP circuit.
-.TP
-\fBdestroybddcircuit\fP
-\- frees a \fBbdd\fP circuit.
-.TP
-\fBsearchbddcircuitin\fP
-\- searches a specified input in a circuit.
-.TP
-\fBaddbddcircuitin\fP
-\- adds a new input in a circuit.
-.TP
-\fBaddbddcircuitaux\fP
-\- adds an auxialiary variable in a circuit.
-.TP
-\fBsearchbddcircuitout\fP
-\- searches a specified output in a circuit.
-.TP
-\fBaddbddcircuitout\fP
-\- adds a new output in a circuit.
-.TP
-\fBdelbddcircuitout\fP
-\- deletes a specified output in a circuit.
-.TP
-\fBaddbddcircuitabl\fP
-\- converts an \fBabl\fP to a \fBbdd\fP node.
-.TP
-\fBconvertbddcircuitabl\fP
-\- converts a \fBbdd\fP node to an \fBabl\fP.
-.TP
-\fBconvertbddcircuitsumabl\fP
-\- converts a \fBbdd\fP node to an \fBabl\fP.
-.TP
-\fBviewbddcircuit\fP
-\- displays a \fBbdd\fP circuit.
-.TP
-\fBcofactorbddnode\fP
-\- computes the generalized cofactor.
-.TP
-\fBrestrictbddnode\fP
-\- substitutes a variable by zero or one.
-.TP
-\fBcomposebddnode\fP
-\- substitutes a variable by a \fBbdd\fP node.
-.TP
-\fBconvertbddindexabl\fP
-\- converts a \fBbdd\fP index to an atomic \fBabl\fP.
-.TP
-\fBconvertbddmuxabl\fP
-\- converts a \fBbdd\fP node to a multiplexor.
-.TP
-\fBconvertbddnodeabl\fP
-\- converts a \fBbdd\fP node to an \fBabl\fP.
-.TP
-\fBconvertbddnodesumabl\fP
-\- converts a \fBbdd\fP node to an \fBabl\fP.
-.TP
-\fBexistbddnodeassocon\fP
-\-  computes an existantial quantification.
-.TP
-\fBexistbddnodeassocoff\fP
-\- computes an existantial quantification.
-.TP
-\fBgarbagebddsystem\fP
-\- forces a \fBbdd\fP garbage collection.
-.TP
-\fBimplybddnode\fP
-\- computes a \fBbdd\fP that implies a conjonction.
-.TP
-\fBintersectbddnode\fP
-\- tests for an intersection.
-.TP
-\fBmarkbddnode\fP
-\- marks a \fBbdd\fP node.
-.TP
-\fBunmarkbddnode\fP
-\- clears a marked \fBbdd\fP node.
-.TP
-\fBgetbddnodenum\fP
-\- gets the number of nodes in a \fBbdd\fP.
-.TP
-\fBgetbddnodesize\fP
-\- gets the number of nodes in a \fBbdd\fP.
-.TP
-\fBaddbddnode\fP
-\- adds a new \fBbdd\fP node.
-.TP
-\fBaddbddnodelist\fP
-\- adds a node in a \fIchain_list\fP.
-.TP
-\fBdelbddnode\fP
-\- deletes a \fBbdd\fP node.
-.TP
-\fBdelbddnodelist\fP
-\- deletes a list of \fBbdd\fP nodes.
-.TP
-\fBviewbddnode\fP
-\- displays a \fBbdd\fP node.
-.TP
-\fBincbddrefext\fP
-\- increments the number of external reference.
-.TP
-\fBincbddrefint\fP
-\- increments the number of internal reference.
-.TP
-\fBdecbddrefext\fP
-\- decrements the number of external reference.
-.TP
-\fBdecbddrefint\fP
-\- decrements the number of internal reference.
-.TP
-\fBsetbddrefext\fP
-\- sets a node visible from outside.
-.TP
-\fBunsetbddrefext\fP
-\- sets a node invisible from outside.
-.TP
-\fBclearbddsystemrefint\fP
-\- clears all the internal references.
-.TP
-\fBclearbddsystemrefext\fP
-\- clears all the external references.
-.TP
-\fBclearbddsystemref\fP
-\- clears all the references.
-.TP
-\fBrelprodbddnodeassoc\fP
-\- computes a relation product.
-.TP
-\fBreorderbddsystemsimple\fP
-\- reorders the \fBbdd\fP nodes.
-.TP
-\fBreorderbddsystemwindow\fP
-\- reorders the \fBbdd\fP nodes.
-.TP
-\fBreorderbddsystemtop\fP
-\- reorders the \fBbdd\fP nodes.
-.TP
-\fBreorderbddsystemdynamic\fP
-\- sets the dynamic reorder parameters.
-.TP
-\fBsatisfybddnode\fP
-\- finds a satisfying path for a \fBbdd\fP.
-.TP
-\fBsimpbddnodedcon\fP
-\- simplifies a \fBbdd\fP with don't cares on its on-set.
-.TP
-\fBsimpbddnodedcoff\fP
-\- simplifies a \fBbdd\fP with don't cares on its off-set
-.TP
-\fBsubstbddnodeassoc\fP
-\- substitutes variables with \fBbdd\fP nodes.
-.TP
-\fBgetbddnodesupport\fP
-\- gives the support of a \fBbdd\fP node.
-.TP
-\fBisbddvarinsupport\fP
-\- checks if a variable appears in a \fBbdd\fP node.
-.TP
-\fBcreatebddsystem\fP
-\- creates a \fBbdd\fP system.
-.TP
-\fBresetbddsystem\fP
-\- resets a \fBbdd\fP system.
-.TP
-\fBdestroybddsystem\fP
-\- frees a \fBbdd\fP system.
-.TP
-\fBviewbddsystem\fP
-\- displays a \fBbdd\fP system.
-.TP
-\fBviewbddsysteminfo\fP
-\- displays statisticals informations.
-.TP
-\fBtestbddcircuit\fP
-\- debbugs a \fBbdd\fP circuit.
-.TP
-\fBaddbddvar\fP
-\- creates a new variable.
-.TP
-\fBaddbddvarlast\fP
-\- creates a new variable.
-.TP
-\fBaddbddvarfirst\fP
-\- creates a new variable.
-.TP
-\fBaddbddvarbefore\fP
-\- creates a new variable.
-.TP
-\fBaddbddvarafter\fP
-\- creates a new variable.
-.TP
-\fBsweepbddvar\fP
-\- sweeps all the unused nodes for a variable.
-.TP
-\fBswapbddvar\fP
-\- swaps two contigous variables.
-.TP
-\fBgetbddvarbyindex\fP
-\- converts \fBbdd\fP index to a variable number.
-.TP
-\fBgetbddvarindex\fP
-\- converts a variable number in a \fBbdd\fP index.
-.TP
-\fBgetbddvarnode\fP
-\- gives the \fBbdd\fP node of a variable.
-.TP
-\fBgetbddvarnodebyindex\fP
-\- gives the \fBbdd\fP node of a variable.
-.TP
-\fBaddbddvarauxsingle\fP
-\- creates an auxiliary variable. 
-.TP
-\fBaddbddvarauxglobal\fP
-\- creates an auxiliary variable. 
-
-.TP 0
-libBdd101.a :
-
-\fBallocbdduserfunc\fP,
-\fBallocbddheath\fP,
-\fBallocbddhnode\fP,
-\fBallocbddhoper\fP,
-\fBallocbddhnodetable\fP,
-\fBallocbddhopertable\fP,
-\fBallocbddblock\fP,
-\fBallocbddnodeblock\fP,
-\fBallocbddvartree\fP,
-\fBallocbddvarchild\fP,
-\fBallocbddvarnode\fP,
-\fBallocbddindexnode\fP,
-\fBallocbddvar\fP,
-\fBallocbddindex\fP,
-\fBallocbddassoc\fP,
-\fBallocbddassocnode\fP,
-\fBallocbddnamein\fP,
-\fBallocbddindexin\fP,
-\fBallocbddsystem\fP,
-\fBallocbddcircuit\fP,
-\fBviewbddallocinfo\fP,
-\fBapplybddnodenot\fP,
-\fBapplybddnodeterm\fP,
-\fBapplybddnode\fP,
-\fBapplybddnodeite\fP,
-\fBapplybddnodelist\fP,
-\fBaddbddassoc\fP,
-\fBaddbddnodeassoc\fP,
-\fBdelbddassoc\fP,
-\fBdelbddnodeassoc\fP,
-\fBdestroybddassoc\fP,
-\fBviewbddassoc\fP,
-\fBaddbddblock\fP,
-\fBcreatebddblock\fP,
-\fBresetbddblock\fP,
-\fBdestroybddblock\fP,
-\fBviewbddblock\fP,
-\fBcheckbddvar\fP,
-\fBcheckbddindex\fP,
-\fBcheckbddoper\fP,
-\fBcheckbddassoc\fP,
-\fBcheckbddmaxnode\fP,
-\fBcreatebddcircuit\fP,
-\fBresetbddcircuit\fP,
-\fBdestroybddcircuit\fP,
-\fBsearchbddcircuitin\fP,
-\fBaddbddcircuitin\fP,
-\fBaddbddcircuitaux\fP,
-\fBsearchbddcircuitout\fP,
-\fBaddbddcircuitout\fP,
-\fBdelbddcircuitout\fP,
-\fBaddbddcircuitabl\fP,
-\fBconvertbddcircuitabl\fP,
-\fBconvertbddcircuitsumabl\fP,
-\fBviewbddcircuit\fP,
-\fBcofactorbddnode\fP,
-\fBrestrictbddnode\fP,
-\fBcomposebddnode\fP,
-\fBconvertbddindexabl\fP,
-\fBconvertbddmuxabl\fP,
-\fBconvertbddnodeabl\fP,
-\fBconvertbddnodesumabl\fP,
-\fBexistbddnodeassocon\fP,
-\fBexistbddnodeassocoff\fP,
-\fBfreebdduserfunc\fP,
-\fBfreebddheath\fP,
-\fBfreebddhnode\fP,
-\fBfreebddhoper\fP,
-\fBfreebddhnodetable\fP,
-\fBfreebddhopertable\fP,
-\fBfreebddblock\fP,
-\fBfreebddnodeblock\fP,
-\fBfreebddvartree\fP,
-\fBfreebddvarchild\fP,
-\fBfreebddvarnode\fP,
-\fBfreebddindexnode\fP,
-\fBfreebddvar\fP,
-\fBfreebddindex\fP,
-\fBfreebddassoc\fP,
-\fBfreebddassocnode\fP,
-\fBfreebddnamein\fP,
-\fBfreebddindexin\fP,
-\fBfreebddsystem\fP,
-\fBfreebddcircuit\fP,
-\fBgarbagebddsystem\fP,
-\fBgetbddheathvar\fP,
-\fBgetbddheath\fP,
-\fBdelbddheath\fP,
-\fBsetbddhnodefunc\fP,
-\fBgetbddhnodesize\fP,
-\fBgetbddhnodekey\fP,
-\fBgetbddhnodeindex\fP,
-\fBcheckbddhnode\fP,
-\fBcreatebddhnodetable\fP,
-\fBdestroybddhnodetable\fP,
-\fBresetbddhnodetable\fP,
-\fBresizebddhnodetable\fP,
-\fBstretchbddhnodetable\fP,
-\fBaddbddhnode\fP,
-\fBdelbddhnode\fP,
-\fBviewbddhnode\fP,
-\fBviewbddhnodetable\fP,
-\fBviewbddindexnode\fP,
-\fBviewbddvarnode\fP,
-\fBsetbddhoperfunc\fP,
-\fBgetbddhopersize\fP,
-\fBgetbddhoperkey\fP,
-\fBcreatebddhopertable\fP,
-\fBdestroybddhopertable\fP,
-\fBresetbddhopertable\fP,
-\fBaddbddhoper\fP,
-\fBsearchbddhoper\fP,
-\fBviewbddhoper\fP,
-\fBviewbddhopertable\fP,
-\fBimplybddnode\fP,
-\fBintersectbddnode\fP,
-\fBmarkbddnode\fP,
-\fBunmarkbddnode\fP,
-\fBgetbddnodenum\fP,
-\fBgetbddnodesize\fP,
-\fBaddbddnode\fP,
-\fBaddbddnodelist\fP,
-\fBdelbddnode\fP,
-\fBdelbddnodelist\fP,
-\fBviewbddnode\fP,
-\fBincbddrefext\fP,
-\fBincbddrefint\fP,
-\fBdecbddrefext\fP,
-\fBdecbddrefint\fP,
-\fBsetbddrefext\fP,
-\fBunsetbddrefext\fP,
-\fBclearbddsystemrefint\fP,
-\fBclearbddsystemrefext\fP,
-\fBclearbddsystemref\fP,
-\fBrelprodbddnodeassoc\fP,
-\fBreorderbddvartreewindow2\fP,
-\fBreorderbddvartreewindow3\fP,
-\fBreorderbddsystemsimple\fP,
-\fBreorderbddsystemwindow\fP,
-\fBreorderbddsystemtop\fP,
-\fBreorderbddsystemdynamic\fP,
-\fBresizebddvarchild\fP,
-\fBresizebddvarnode\fP,
-\fBresizebddvar\fP,
-\fBresizebddindexnode\fP,
-\fBresizebddindex\fP,
-\fBresizebddassocnode\fP,
-\fBresizebddnamein\fP,
-\fBresizebddindexin\fP,
-\fBsatisfybddnode\fP,
-\fBsimpbddnodedcon\fP,
-\fBsimpbddnodedcoff\fP,
-\fBsubstbddnodeassoc\fP,
-\fBgetbddnodesupport\fP,
-\fBisbddvarinsupport\fP,
-\fBcreatebddsystem\fP,
-\fBresetbddsystem\fP,
-\fBdestroybddsystem\fP,
-\fBviewbddsystem\fP,
-\fBviewbddsysteminfo\fP,
-\fBtestbddcircuit\fP,
-\fBaddbdduserfunc\fP,
-\fBdelbdduserfunc\fP,
-\fBexecbdduserfunc\fP,
-\fBdestroybdduserfunc\fP,
-\fBnewbddvar\fP,
-\fBaddbddvar\fP,
-\fBaddbddvarlast\fP,
-\fBaddbddvarfirst\fP,
-\fBaddbddvarbefore\fP,
-\fBaddbddvarafter\fP,
-\fBsweepbddvar\fP,
-\fBswapbddvar\fP,
-\fBgetbddvarbyindex\fP,
-\fBgetbddvarindex\fP,
-\fBgetbddvarnode\fP,
-\fBgetbddvarnodebyindex\fP,
-\fBaddbddvarauxsingle\fP,
-\fBaddbddvarauxglobal\fP,
-\fBsearchbddvartree\fP,
-\fBdeltabddvartree\fP,
-\fBshiftbddvartree\fP,
-\fBaddbddvartree\fP,
-\fBswapbddvartree\fP,
-\fBcreatebddvartree\fP,
-\fBresetbddvartree\fP,
-\fBdestroybddvartree\fP,
-\fBviewbddvartree\fP.
-
-.SH SEE ALSO
-.BR \fBaut\fP(1), \fBabl\fP(1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/bgd.1 b/alliance/share/man/man1/bgd.1
deleted file mode 100644
index 928e971d..00000000
--- a/alliance/share/man/man1/bgd.1
+++ /dev/null
@@ -1,216 +0,0 @@
-.\"   $Id: bgd.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
-.\" @(#)Labo.l 0.0 92/07/03 UPMC; Author: Laurent WINCKEL
-.TH BGD 1 "October 1, 1997" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
-.SH NAME
-bgd \- register file generator
-.SH SYNOPSIS
-.B bgd
-.br
-.B bgd
-.B -h
-.br
-.B bgd
-.B -deco
-.I crunch_name
-.br
-.B bgd
-.I bits words busses
-.br
-.B [ li ] 
-.B [ lo ] 
-.B [ id ] 
-.B [ lp ] 
-.B [ wel|weh ] 
-.B [ dsh|ish ] 
-.B [ hc ]
-.br
-.B ro|rs|ds|ba
-.br
-.B [ name=\fIname_prefix\fP ]
-.br
-.B layout|outline|vhdl|data|netlist
-.br
-.B [ layout ]
-.B [ outline ]
-.B [ vhdl ]
-.B [ data ]
-.B [ netlist ]
-.so man1/alc_origin.1
-.SH AVAILABILITY
-This command is available with
-.B MBK/GENLIB
-software installation option.
-.SH DESCRIPTION
-The first form is a on line help.
-.br
-
-The second is a long on line help.
-.br
-
-In the third form, 
-.B bgd
-decrunch prefix name who have been generated by himself.
-.br
-
-In the last form,
-.B bgd
-generates differents views of a register file and offers a very large range of possible parameters.
-The generator respect the CAO-VLSI definition of a data-path. The slice is fixed at 60
-lambdas, allows multi-acces connectors, could be used with the data-path router
-.BR dpr (1).
-.LP
-The generator needs a library cells to well compute.
-The MBK_CATA_LIB environment variable should contain the path to the library,
-.IR /labo/cells/bgd .
-.SH PARAMETERS AND OPTIONS
-.TP
-.B -h
-Help (long form).
-.TP
-.B -deco \fIcrunch_name\fP
-Name decrunch function.
-.br
-\fIcrunch_name\fP : XXYYYYY.
-      XX    : prefix of Bank Generator bloks name.
-      YYYYY : 5 charaters for parameters incoding.
-.TP
-.I bits
-Word size. The range is from 2 to 64, the value must be even.
-.TP
-.I words
-Number of registers. The range is from 2 to 256, the value must be even.
-.TP
-.I busses
-Number of read busses : 1 or 2. Generated register file has one write address bus and one or two read address busses.
-.TP
-.B li
-Adds an input latch
-.TP
-.B lo
-Adds output latches. One latch for each output bus.
-.TP
-.B id
-Inverts data polarity between input bus and output busses.
-.TP
-.B lp
-Reduces consumption but increases read time. This option is only available for register file which have more than 16 registers.
-.TP
-.B wel
-Adds a write enable signal. The signal is actif low.
-.TP
-.B weh
-Adds a write enable signal. The signal is actif high.
-.TP
-.B dsh
-Adds a bypass to each output bus. Data polarity between bypass inputs and outputs is preserved.
-.TP
-.B ish
-Adds a bypass to each output bus. Data polarity between bypass inputs and outputs is inverted.
-.TP
-.B ro
-Generates a block without address decoders, with an optimized width.
-.TP
-.B rs
-Generates a block without address decoders, that could be abuted with a decoders block.
-.TP
-.B ds
-Generates a block that contains only the address decoders.
-This block has the same size and the same connectors interface as the block generated with the \fIrs\fP option.
-.TP
-.B ba
-Generates a complete register file with address decoders.
-.TP
-.B name=\fIname_prefix\fP
-\fIname_prefix\fP indicate the user name prefix for all files generated.
-If no name is given, the default files prefix is : XXYYYYY
-Where XX is "ro" | "rs" | "ds" | "ba" and
-YYYYY is an encode of the parameter values ensuring an unique name.
-.TP
-.B layout
-To obtain a layout view.
-The different formats are given by
-.BR mbk (1)
-documentation.
-.TP
-.B outline
-To obtain a outline view.
-.TP
-.B vhdl
-To obtain a VHDL data-flow behavioural description view.
-.TP
-.B data
-To obtain a data sheet.
-.TP
-.B netlist
-To obtain a netlist view. This view contains only the logical block interface.
-The different formats are given by
-.BR mbk (1)
-documentation.
-.SH EXAMPLES
-.TP
-.B bgd "\fI 24 16 2\fB rs name=\fImy_reg\fB outline"
-Produces the outline view of 16 registers of 24 bits with 2 read busses. The generated file name is "\fImy_reg.edif\fP".
-.TP
-.B bgd "\fI 16 32 1\fB wel ba name=\fItest\fB layout vhdl"
-Produces the layout and vhdl views of a 32 registers of 16 bits complete register file with 1 read bus and a write enable input active at low level. The prefix name of all generated files is "\fItest\fP".
-.SH SIGNAL NAMES
-.LP
-Each signal name is predefined and could not be modified by the user.
-Index 0 is the most significant bit and N represent the number of bits.
-M represent the size of address busses, this size depend on number of registers.
-Signal names are :
-.TP
-ad_w[0]-ad_w[M-1]
-Write address
-.TP
-we
-Write enable signal
-.TP
-ad_r_a[0]-ad_r_a[M-1]
-First read address
-.TP
-ad_r_b[0]-ad_r_b[M-1]
-Second read address
-.TP
-c_s_a
-First bypass control signal
-.TP
-c_s_b
-Second bypass control signal
-.TP
-ck_m
-Master clock signal
-.TP
-ck_s
-Slave clock signal
-.TP
-in_a[0]-in_a[N-1]
-Data input
-.TP
-i_s_a[0]-i_s_a[N-1]
-First bypass data input
-.TP
-i_s_b[0]-i_s_b[N-1]
-Second bypass data input
-.TP
-out_a[0]-out_a[N-1]
-Fisrt data output
-.TP
-out_b[0]-out_b[N-1]
-Second data output
-.TP
-vdd, vss
-Power supplies
-.LP
-.SH TOPOLOGY
-.TP
-The complete register file dimension are approximately :
-width = words * 34 lambdas.
-.br
-height = (bits + 3 * busses + 6) * 60 lambdas.
-.SH SEE ALSO
-.BR mbk (1),
-.BR dpr (1),
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/boog.1 b/alliance/share/man/man1/boog.1
deleted file mode 100644
index 183bb495..00000000
--- a/alliance/share/man/man1/boog.1
+++ /dev/null
@@ -1,171 +0,0 @@
-.\" 
-.\" This file is part of the Alliance CAD System
-.\" Copyright (C) Laboratoire LIP6 - Département ASIM
-.\" Universite Pierre et Marie Curie
-.\" 
-.\" Home page          : http://www-asim.lip6.fr/alliance/
-.\" E-mail support     : mailto:alliance-support@asim.lip6.fr
-.\" 
-.\" This progam is  free software; you can redistribute it  and/or modify it
-.\" under the  terms of the GNU  General Public License as  published by the
-.\" Free Software Foundation;  either version 2 of the License,  or (at your
-.\" option) any later version.
-.\" 
-.\" Alliance VLSI  CAD System  is distributed  in the hope  that it  will be
-.\" useful, but WITHOUT  ANY WARRANTY; without even the  implied warranty of
-.\" MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
-.\" Public License for more details.
-.\" 
-.\" You should have received a copy  of the GNU General Public License along
-.\" with the GNU C Library; see the  file COPYING. If not, write to the Free
-.\" Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-.\" 
-.\" 
-.\" Tool    : Man pages
-.\" Date    : 1991,92,2000
-.\" Author  : Luc Burgun, Pascale Allegre, Nathalie Dictus
-.\" Modified by Czo <Olivier.Sirol@lip6.fr> 1996,97
-.\" Modified by francois Donnet 2000
-.\" 
-.\" 
-.\" 
-.\" 
-.\" 
-.pl -.4
-.TH BOOG 1 "Jun 29 2000"  "ASIM/LIP6" "CAO\-VLSI Reference Manual"
-.SH NAME
-.TP
-BooG \- Binding and Optimizing On Gates.
-
-
-.so man1/alc_origin.1
-
-.SH SYNOPSIS
-.TP
-\f4boog\fP  [-hmxold] \fIinput_file\fP \fIoutput_file\fP  [\fIlax_file\fP]
-.br
-
-.SH DESCRIPTION
-.br
-\f4boog\fP is a mapper of a behavioural description onto a predefined standard cell library as SXLIB.
-It is the second step of the logic synthesis: it builds a gate network using a standard cell library. 
-.br
-
-.br
-\f4  Input file description\fP
-.br
-The logic level behavioural description (.vbe file) uses the same VHDL subset as the logic simulator \f4asimut\fP, the FSM synthesizer \f4syf\fP, the functional abstractor \f4yagle\fP and the formal prover \f4proof\fP (for further information about the subset of VHDL, see the "vbe" manual). 
-.br
-Some constraints due to hardware mapping exist. These attributes are only supported by technology mapping onto a standard cell library as \f4sxlib\fP.
-.br
-For the register signal description, only one condition statement must appear. STABLE must be strictely used as a negativ motion and joined to clock setup value. Setup can be on high or low value, but it would be worthy to choose it accordingly with hardware register cell.
-.br
-\fI# Example\fP
-        label: BLOCK (NOT ck 'STABLE and ck='1')
-        BEGIN
-            reg <= GUARDED expr;
-        END BLOCK;
-        
-You can also put a write enable condition to your register:
-        label: BLOCK (NOT ck 'STABLE and ck='1' and wen='1')
-        BEGIN
-            reg <= GUARDED expr;
-        END BLOCK;
-.fi
-.ti 7
-
-A special feature has been introduced in the VHDL subset in order to allow the don't care description for external outputs and internal registers : A bit signal can take the 'd' value. 
-This value is interpreted as a '0' by the logic simulator \f4asimut\fP. 
-Don't Cares are automatically generated by \f4syf\fP in the resulting '.vbe' file.
-
-
-.br
-\f4  Output file description\fP
-.br
-A pure standard cell netlist is produced by \f4boog\fP. This file is destinated for /fBloon/fP alliance utility to improve RC delays.
-Any equipotential keeps its name from connector to connector. In trouble case, buffers are inserted to respect this VHDL constraint.
-
-.br
-\f4  lax Parameter file description\fP
-.br
-The lax file is common with other logic synthesis tools and is used
-for driving the synthesis process. 
-See \f4lax\fP(5) manual for more detail.
-
-.br
-\f4lax\fP uses a lot of parameters to guide every step of the synthesis process.
-Some parameters are globally used (for example, \fIoptimization level\fP whereas others are specifically used (\f4load capacitance\fP for the netlist optimization only).
-Here is the default lax file (see the user's manual for further information about the syntax of the '.lax' file):
-.br
-
-.br
-   Optimization mode = 2 (50% area - 50% delay)
-.br
-   Input impedance = 0
-.br
-   Output capacitance = 0
-.br
-   Delayed input = none
-.br
-   Auxiliary signal saved = none
-.br
-
-
-.br
-\f4  Mapping with a standard cell library\fP
-.br
-Every cell appearing in the directory defined by the environment variable MBK_TARGET_LIB may be used by \f4boog\fP since they are described as a '.vbe' file. There are some restrictions about the type of the cell used. Every cell has to have only one output. 
-The cell must be characterized. The timing and area informations required by \f4boog\fP are specified in the "generic" clause of the ".vbe" file.
-.br
-
-.SH OPTION
-.TP 10
-\f4\-h\fP
-Help mode. Displays possible uses of \f4boog\fP.
-.TP 10
-\f4\-m optim_mode\fP
-Optimization mode. Can be defined in lax file, it's only a shortcut to define it on command line. This mode number has an array defined between \fI0\fP and \fI4\fP. It indicates the way of optimization the user wants. If \fI0\fP is chosen, the circuit area will be improved. On the other hand, \fI4\fP will improve circuit delays. \fI2\fP is a medium value for optimization.
-.TP 10
-\f4\-x xsch_mode\fP
-Generate a '.xsc' file. It is a color map for each signals contained in \fIoutput_file\fP network. This file is used by \f4xsch\fP to view the netlist. By choosing level 0 or 1 for xsch_mode, you can color respectively the critical path or all signals with delay graduation.
-.TP 10
-\f4\-o output_file\fP
-Just another way to show explicitely the \f4VST\fP output file name.
-.TP 10
-\f4\-l lax_file\fP
-Just another way to show explicitely the \f4LAX\fP parameter file name.
-.TP 10
-\f4\-d debug_file\fP
-Generates a \f4VBE\f debug file. It comes from internal result algorithm. Users aren't concerned.
-.br
-
-.SH ENVIRONMENT VARIABLES
-.br
-The following environment variables have to be set before using \f4boog\fP :
-.HP
-.ti 7
-\fIMBK_CATA_LIB\fP gives the auxiliary paths of the directories of input files (behavioural description). 
-.HP
-.ti 7
-\fIMBK_TARGET_LIB\fP gives the path (single) of the directory of the selected standard cell library. 
-.HP
-.ti 7
-\fIMBK_OUT_LO\fP gives the output format of the structural description.
-
-
-.SH EXAMPLE
-.br
-You can call \f4boog\fP as follows :
-.br
-.br
-	boog alu alu
-
-
-
-.SH SEE ALSO
-.br
-boog(1), boom(1), loon(1), lax(1), vbe(1), scmap(1), bop(1), glop(1), c4map(1), xlmap(1), proof(1), yagle(1), asimut(1), vhdl(5), scr(1), sclib(1), sxlib(1).
-.br
-
-
-.so man1/alc_bug_report.1
diff --git a/alliance/share/man/man1/boom.1 b/alliance/share/man/man1/boom.1
deleted file mode 100644
index 7da53396..00000000
--- a/alliance/share/man/man1/boom.1
+++ /dev/null
@@ -1,108 +0,0 @@
-.\"   $Id: boom.1,v 1.4 2001/11/17 14:02:00 syf Exp $
-.\" @(#)Labo.l 2.2 95/09/24 UPMC; Author: Jacomme L.
-.pl -.4
-.TH BOOM 1 "August 25, 2000" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
-.SH NAME
-.TP
-BOOM \- BOOlean Minimization
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.TP
-\f4boom [\-VTOAP] [\-l num] [\-d num] [\-i num] [\-a num] [\-sjbgpwtmorn]
-        filename [outname]
-.br
-.SH DESCRIPTION
-.br
-\fBBOOM\fP is used for the first step of the synthesis process.
-It optimizes a behavioural description using a Reduced Ordered Binary
-Decision Diagram representation of logic functions.
-The file \fBfilename\fP is the input behavioural description and must
-be written in vbe(5) format.
-The resulting behavioural optimized description is saved with the name
-\fBoutname\fP or \fBinput_name\fP_o in vbe(5) format.
-
-.SH ENVIRONMENT VARIABLES
-.br
-.TP 10
-\f4MBK_WORK_LIB\fR(1)
-indicates the path to the read/write directory for the session.
-.br
-
-.SH OPTIONS
-.TP 10
-\f4\-V\fP
-Verbose mode on.
-Each step of the optimization is displayed on the standard output.
-.TP 10
-\f4\-T\fP
-Trace mode on.
-Some debug informations are displayed on the standard output.
-.TP 10
-\f4\-O\fP
-Reverses initial Bdd variables order.
-.TP 10
-\f4\-A\fP
-\fBBOOM\fP performs a local optimization and keeps the architecture of the initial description by saving most of the intermediate signals.
-This mode is well-suited for big or regular circuits such as multipliers, adders.
-By default \fBBOOM\fP performs a global optimization and removes most of the intermediate
-signals so that the outputs are expressed in terms of the inputs or the internal registers.
-This mode is well-suited for random circuits such as FSMs. 
-.TP 10
-\f4\-P\fP
-Uses a parameter file \fBinput_name\fP.boom describing
-optimization directives and constraints.
-(see below for the exact syntax)
-
-.nf
-# Example of .boom file
-
-#
-# The list of auxiliary signals that have to be kept
-# during optimization.
-# Generally carry signals, ram address signals etc ...
-# 
-BEGIN_KEEP
-
-carry[3:0]
-ram_address[3:0]
-
-END
-
-#
-# The list of auxiliary signals which assigned
-# expression won't be modified.
-# Generally it's ram output signals.
-# 
-BEGIN_DONT_TOUCH
-ram_out[7:0]
-END
-.fi
-
-.TP 10
-\f4\-l num\fP
-Specifies the optimization level [0\-3]
-(default is 0, low level).
-.TP 10
-\f4\-d num\fP
-Specifies the delay optimization percent
-(default is 0% delay, 100% surface).
-.TP 10
-\f4\-i num\fP
-Specifies the number of iterations for the choosen optimization algorithm
-(for experts only).
-.TP 10
-\f4\-a num\fP
-Specifies the amplitude during bdd reordering (for experts only).
-.TP 10
-\f4\-sjbgpwtmorn\fP
-Specifies which algorithm has to be used for the boolean optimization.
-
-.SH SEE ALSO
-.BR boom (5),
-.BR vbe (5),
-.BR asimut (1),
-.BR boog (1),
-.BR MBK_WORK_LIB (1).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/bop.1 b/alliance/share/man/man1/bop.1
deleted file mode 100644
index 21ce8525..00000000
--- a/alliance/share/man/man1/bop.1
+++ /dev/null
@@ -1,138 +0,0 @@
-.\"   $Id: bop.1,v 1.2 2001/04/04 13:19:57 francois Exp $
-.\" 
-.\" 
-.\"   $Id: bop.1,v 1.2 2001/04/04 13:19:57 francois Exp $
-.\" 
-.\" 
-.pl -.4
-.TH BOP 1 "October 1, 1997" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
-.SH NAME
-.TP
-bop    
-\- boolean optimization of a logic level behavioural description (VHDL data flow)
-
-.so man1/alc_origin.1
-
-.SH SYNOPSIS
-.TP
-\fBbop\fP [\fI-o|-l\fP]  \fIdata_flow_file\fP \fIoutput_file\fP  [\fIparameter_file\fP]
-.br
-
-.SH DESCRIPTION
-.br
-
-.br
-\fB  Input description\fP
-.br
-
-.br
-You should rather use the newest version of \fBboom\fP.
-The logic level behavioural description (.vbe file) uses the same VHDL subset as the logic simulator \fBasimut\fP, the FSM synthesizer \fBsyf\fP, the functional abstractor \fByagle\fP and the formal prover \fBproof\fP (for further information about the subset of VHDL, see the "vbe" manual). 
-.br
-A special feature has been introduced in the VHDL subset in order to allow the don't care description for external outputs and internal registers : A bit signal can take the 'd' value. 
-This value is interpreted as a '0' by the logic simulator \fBasimut\fP. 
-Don't Cares are automatically generated by \fBsyf\fP in the resulting '.vbe' file.
-.br
-For the register signal, only one signal can appear in a guarded expression since the STABLE attribute is used. This attribute is only supported by technology mapping onto a standard cell library as \fBsclib\fP. 
-.br
-\fBbop\fP is used for the first step of the synthesis process.
-It optimizes the behavioural description using a Reduced Ordered Binary Decision Diagram representation of logic functions. Two kinds of optimization are performed : local or global. 
-A Local optimization keeps the architecture of the initial description by saving most of the intermediate signals. This mode is well-suited for regular circuits such as multipliers, adders.
-A Global optimization removes most of the intermediate signals so that the outputs are expressed in terms of the inputs or the internal registers. This mode is
-well-suited for random circuits such as FSMs. 
-
-
-.br
-\fB  Parameter file '.lax'\fP
-.br
-The parameter file is common with other logic synthesis tools and is used
-for driving the synthesis process. 
-See \fBlax\fP(5) manual for more detail.
-
-.br
-\fBlax\fP uses a lot of parameters to guide every step of the synthesis process.
-Some parameters are globally used (for example, \fIoptimization level\fP whereas others are specifically used (\fBload capacitance\fP for the netlist optimization only).
-Here is the default parameter file (see the user's manual for further information about the syntax of the '.lax' file):
-.br
-
-.br
-   Optimization mode = 2 (50% area - 50% delay)
-.br
-   Optimization level = 2 
-.br
-   Delayed input = 0
-.br
-   Early output = 0
-.br
-   Auxiliary signal saved = 0
-.br
-   Number of serial transistors = 4 in N and P area
-.br
-
-
-
-.SH ENVIRONMENT VARIABLES
-.br
-The following environment variables have to be set before using \fBbop\fP :
-.HP
-.ti 7
-\fIMBK_WORK_LIB\fP gives the path of the directory of both input and output files (behavioural, structural and parameters description).
-.HP
-.ti 7
-\fIMBK_CATA_LIB\fP gives the auxiliary paths of the directories of input files (behavioural description). 
-.HP
-.ti 7
-\fIMBK_TARGET_LIB\fP gives the path (single) of the directory of the selected standard cell library. 
-.HP
-.ti 7
-\fIMBK_C4_LIB\fP gives the path (single) of the directory for the three views of each cell generated by C4.
-.HP
-.ti 7
-\fIMBK_IN_LO\fP gives the format of models instantiated in the structural description.
-.HP
-.ti 7
-\fIMBK_OUT_LO\fP gives the output format of the structural description.
-.HP
-.ti 7
-\fIMBK_OUT_PH\fP gives the output format for the layout of the cells generated by C4.
-
-
-
-
-
-.SH OPTIONS
-.br
-Only one option can be given at the same time.
-.HP
-.ti 7
-\-o optimizes globally a behavioural description.
-.HP
-.ti 7
-\-l optimizes locally a behavioural description.
-
-
-.SH EXAMPLE
-.br
-You can call \fBbop\fP as follows :
-.br
-.br
-	bop -o alu4 area
-	bop -o alu4 area paramfile
-
-
-.SH SEE ALSO
-.br
-scmap(1), c4map(1), xlmap(1), proof(1), yagle(1), asimut(1), vhdl(5), scr(1), sclib(1), boom(1), boog(1), loon(1), scapin(1), sxlib(1).
-.br
-
-
-.SH DIAGNOSTICS
-.br
-"VHDL : Error - bad usage of the 'stable' attribut"
-.br
-The stable attribut must be used with only one signal in a guarded expression
-.br
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/bsg.1 b/alliance/share/man/man1/bsg.1
deleted file mode 100644
index 9223b277..00000000
--- a/alliance/share/man/man1/bsg.1
+++ /dev/null
@@ -1,192 +0,0 @@
-.\"   $Id: bsg.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
-.\" @(#)Labo.l 2.01 95/03/02 UPMC; Author: laurent WINCKEL
-.TH BSG 1 "October 1, 1997" "ASIM/LIP6" "ALLIANCE USER COMMANDS"
-.SH NAME
-bsg \-  Barrel Shifter Generator
-.SH SYNOPSYS
-.B bsg 
-.I bits
-.B [ -virtual ] [ -msb0 ]
-.br
-.B [ -layout ] [ -icon ] [ -vhdl ] [ -patterns ] [ -datasheet ]
-.br
-.B [ -physical_box ] [ -logical_box ]
-.br
-.B [ -o name_prefix ]
-.so man1/alc_origin.1
-.SH DESCRIPTION
-.B bsg
-is a fast barrel shifter generator for bit-sliced data-paths.
-The slice is fixed to 60 lambdas, allows virtual terminals, and could be
-used with the data-path compiler
-.BR fitpath (1).
-It has the capability of doing logical and arithmetical shifts and
-rotations.
-.BR fitpath (1).
-.LP
-The generator needs a leaf cell library to work well.
-The \fBMBK_CATA_LIB\fP(1) environment variable should contain the path to
-the generator library, \fIbslib\fP.
-.SH OPTIONS
-.TP 20
-.I bits
-data size in bits of the barrel shifter to be 
-generated. Must be in range 3-64.
-This argument is mandatory.
-.B -virtual
-Generates a barrel shifter with virtual connectors, as opposed to the default
-that generates steady terminals, to be used by the data-path compiler
-\fPfitpath\fP(1).
-.TP
-.B -msb0
-Index 0 of vectorized busses will be used for the most significant bit, else index 0 will be used for the less significant bit of busses.
-.TP
-.B -layout
-To obtain a layout view.
-The different formats are given by
-.BR mbk (1)
-documentation.
-.TP
-.B -icon
-To obtain a icon view.
-.TP
-.B -vhdl
-To obtain a VHDL data-flow behavioral description view.
-.TP
-.B -patterns
-To obtain a patterns file.
-.TP
-.B -datasheet
-To obtain a data sheet.
-.TP
-.B -physical_box
-To obtain a physical outline view. Cannot be used with the -layout option.
-The different formats are given by
-.BR mbk (1)
-documentation.
-.TP
-.B -logical_box
-To obtain a netlist view. This view contains only the logical block interface.
-The different formats are given by
-.BR mbk (1)
-documentation.
-.TP
-.B -o \fIblockname\fP
-\fIblockname\fP indicate the user name prefix for all files generated.
-If no name is given, a default name will be composed by the generator.
-For each set of parameters and options, the default name will be different.
-.LP
-Each signal name is predefined and can not be modified by the user.
-.I bits
-represent the number of bits.
-Signal names are:
-.TP 20
-.B in_s[0..\fIbits\fP-1]
-Shift number.
-.TP
-.B in_d[0..\fIbits\fP-1]
-Data input.
-.TP 
-.B out_d[0..\fIbits\fP-1]
-Data output.
-.TP
-.B left
-When set to logical 
-.BR 1 ,
-Makes a shift to the left. When set to ground, makes a shift to the right.
-.TP
-.B rot
-When set to logical
-.BR 1 ,
-makes a rotation which direction depends on the value of the 
-.B left 
-signal.
-.TP
-.B ext
-When set to logical 
-.B 1
-whenever
-.B left 
-is set to logical 
-.B 0
-(right shift) and 
-.B rot
-to logical 
-.B 0
-(no rotation), makes an arithmetical shift to the right (lefting 
-.BI in_d[ \fIbits\fP-1]
-in the most significant bits).
-.PP
-.ta 5n 10n 15n 20n
-\fBrot\fP	\fBleft\fP	\fBext\fP	       \fBaction\fP
- 0	 0	 0	logical right shift
- 0	 0	 1	arithmetical right shift
- 0	 1	 0	logical left shift
- 0	 1	 1	arithmetical left shift
- 1	 0	 0	right rotation
- 1	 0	 1	?
- 1	 1	 0	left rotation
- 1	 1	 1	?
-.PP
-See the 
-.B Barrel Shifter Cell Library documentation 
-for more details about the shifter structure and connectors.
-.PP
-.SH OUTPUT FILES
-.TP 20
-.IB \|name\| .xx
-The layout  and netlist views. The suffix 
-depends on the 
-.B MBK_OUT_PH 
-and 
-.B MBK_OUT_LO 
-environment variables. (see below).
-.TP
-.IB \|name\| .icn
-The shifter icon view.
-.TP
-.IB \|name\| .vbe
-The 
-.B VHDL
-behavioral view of the shifter.
-.TP
-.IB \|name\| .pat
-The patterns set.
-.SH ENVIRONMENT VARIABLES
-.TP 20
-.B MBK_CATA_LIB
-contains the directory path of the barrel shifter
-leaf cells library. This library is already in 
-.IR /labo/cells/bsg
-and if not, depends upon the system administrator installation.
-.TP
-.B MBK_WORK_LIB
-contains the directory path of the working
-directory. Usually set to
-.BR . .
-.TP
-.B MBK_IN_PH
-contains the format of the barrel shifter cell
-library.
-.TP
-.B MBK_OUT_PH
-contains the desired format of the layout output.
-.TP
-.B MBK_OUT_LO
-contains the desired format of the netlist output.
-.SH SEE ALSO
-.BR MBK_CATA_LIB (1),
-.BR MBK_WORK_LIB (1),
-.BR MBK_IN_PH (1),
-.BR MBK_OUT_PH (1),
-.BR MBK_OUT_LO (1),
-.BR mbk (1),
-.BR genlib (1),
-.BR vhdl (1),
-.BR fitpath (1),
-.BR rfg (1),
-.BR grog (1),
-.BR rsa (1).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/buseg.1 b/alliance/share/man/man1/buseg.1
deleted file mode 100644
index 3c6cc015..00000000
--- a/alliance/share/man/man1/buseg.1
+++ /dev/null
@@ -1,182 +0,0 @@
-.\"   $Id: buseg.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
-.TH BUSEG 1 "October 1, 1997" "ASIM/LIP6" "FITPATH Dedicated Generators"
-.so man1/alc_origin.1
-.SH NAME
-\fBbuseg\fP - Tristate generator for \fBFITPATH\fP data-path compiler.
-.SH SYNOPSYS
-.ft B
-.nf
-.ta 7n
-buseg	<\fIdpwidth\fB> <\fIopwidth\fB> <\fIlsb_slice\fB> 
-	[-msb0] <-vhdl|-netlist|-icon> [-o \fIModelName\fB]
-.fi
-.ft R
-.SH OPTIONS
-.ta  11n
-.in +11n
-.ti -11n
-\fIdpwidth\fP	An integer giving the data-path full bus wide.
-
-.ti -11n
-\fIopwidth\fP	An integer giving the operator bus wide.
-
-.ti -11n
-\fIlsb_slice\fP	An integer giving the operator bottom slice,
-i.e. the slice where the LSB will be set.
-
-.ti -11n
-\fBmsb0\fP
-.in -6n
-.ti +6n
-If this switch is present, the virtual connector with index
-of \fBn\fP is on the slice numberred \fIWidth\fP\fB-1-n\fP.
-That is to say :
-.br
-.ta +2n
--	Connectors indexed \fPzero\fP are on the slice \fIWidth\fP\fB-1\fP.
-.br
--	Connectors indexed \fIWidth\fP\fB-1\fP are on the slice \fBzero\fP.
-.br
-.ti +6n
-Otherwise, the virtual connector with index of \fBn\fP is on the slice
-numberred \fBn\fP. That give :
-.br
-.ta +2n
--	Connectors indexed \fPzero\fP are on the slice \fBzero\fP.
-.br
--	Connectors indexed \fIWidth\fP\fB-1\fP are on the slice
-\fIWidth\fP\fB-1\fP.
-.br
-.ti +6n
-So if we assume that the MSB is in all case associated with the
-\fBslice\fP numberred \fIWidth\fP\fB-1\fP, when \fPmsb0\fP is set the
-connector of the MSB have an index of \fPzero\fP, and an index of
-\fIWidth\fP\fB-1\fP otherwise.
-.br
-.ti +6n
-Notice that the leaf cell indexation is not affected by the
-\fBmsb0\fP switch.
-.br
-.in +6n
-.ta  11n
-
-.ti -11n
-\fBnetlist\fP	Generates the netlist view of the tristate operator.
-.br
-
-.ti -11n
-\fBicon\fP	Generates the icon view of the tristate operator.
-.br
-
-.ti -11n
-\fIModelName\fP	Give the name of the model. If it is not specified
-the generator creates it automatically (based on the parametrization).
-.in -11n
-.SH DESCRIPTION
-.ta 4n +10nR +2n +2n
-	\fBBuseg\fP generate the netlist view and/or the icon view of the
-tristate operator. In order to build the netlist view the generator
-use the following cells of \fBfplib\fP librarie :
-.br
-	-	nt1_fp	:	Effective tristate leaf cell.
-.br
-	-	bnt1_dp	:	Dedicated buffer cell.
-.br
-	All informations needed to perform the physical placement of leaf
-cells with \fBdpp(1)\fP are sets. In other words, the instance names
-are indexed according to the three parameters \fIdpwidth\fP, \fIopwidth\fP
-and \fIlsb_slice\fP.
-
-\fBTerminals\fP
-.br
-
-.ta  10n
-.in +10n
-.ti -10n
-\fBsel\fP	Select the state of the output :
-.br
-.ta +2n +10n +2n
--	low	:	output in high impedance.
-.br
--	high	:	output drived by the input.
-.br
-This is a fixed terminal available on the north side of the
-abutment box.
-.br
-.ta 10n
-
-.ti -10n
-\fBi0[\fP\fIopwidth\fP\fB+\fP\fIlsb_slice\fP\fB-1:\fP\fIlsb_slice\fP\fB]\fP
-.br
-.ti -10n
-\fBi0[\fP\fIdpwidth\fP\fB-\fP\fIopwidth\fP\fB-\fP\fIlsb_slice\fP\fB:\fP\fIdpwidth\fP\fB-\fP\fIlsb_slice\fP\fB-1]\fP
-.br
-Input bus, virtual terminal (without and with the \fB-msb0\fP option).
-.br
-.bp
-.ti -10n
-\fBo[\fP\fIopwidth\fP\fB+\fP\fIlsb_slice\fP\fB-1:\fP\fIlsb_slice\fP\fB]\fP
-.br
-.ti -10n
-\fBo[\fP\fIdpwidth\fP\fB-\fP\fIopwidth\fP\fB-\fP\fIlsb_slice\fP\fB:\fP\fIdpwidth\fP\fB-\fP\fIlsb_slice\fP\fB-1]\fP
-.br
-Ouput bus, virtual terminal (without and with the \fB-msb0\fP option).
-.br
-
-.ti -10n
-\fBvdd, vss\fP	Power supplies.
-.in -10n
-.SH EXAMPLES
-.ft CR
-buseg 32 32 0 -netlist -o my_tris
-.ft R
-.in +4n
-Generates the netlist of a 32 bits tristate, named \fImy_tris\fP, with
-leaf cell indexed from slice 0 (LSB) to slice 31 (MSB).
-
-.in -4n
-.ft CR
-buseg 32 16 16 -netlist
-.ft R
-.in +4n
-Generate the netlist of a 16 bits tristate, named \fIbuse32x16x16l_cl\fP,
-with leaf cell indexed from slice 16 (LSB) to slice 31 (MSB).
-.in -4n
-.SH OUTPUT FILES
-.ta  20n
-.in +20n
-.ti -20n
-\fIModelName\fP\fB.vbe\fP	VHDL behevioral view.
-.br
-
-.ti -20n
-\fIModelName\fP\fB.xx\fP	Netlist view. The ouput format \fB"xx"\fP
-depend on the \fBMBK_OUT_LO\fP environment variable.
-.br
-
-.ti -20n
-\fIModelName\fP\fB.icn\fP	The icon view.
-.in -20n
-.SH ENVIRONMENT VARIABLES
-.ta +20n
-.in +20n
-.ti -20n
-\fPMBK_CATA_LIB\fP	Contain the list of directories path holding the
-leaf cells libraries. In this case it have to include the path to
-\fBfplib\fP : \fB/labo/cells/fplib\fP.
-.br
-
-.ti -20n
-\fPMBK_IN_LO\fP	Contain the format of the logical description of the
-library leaf cells.
-.br
-
-.ti -20n
-\fBMBK_OUT_LO\fP	Contain the ouput format of the generated netlist.
-.in -20n
-.SH SEE ALSO
-.ft B
-DP_BUSE(3), fpgen(3), fplib(3), mbk(3)
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/c4map.1 b/alliance/share/man/man1/c4map.1
deleted file mode 100644
index 0519100d..00000000
--- a/alliance/share/man/man1/c4map.1
+++ /dev/null
@@ -1,137 +0,0 @@
-.\"   $Id: c4map.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
-.\" 
-.\" 
-.\"   $Id: c4map.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
-.\" 
-.\" 
-.pl -.4
-.TH C4MAP 1 "October 1, 1997" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
-.SH NAME
-.TP
-c4map   
-\- mapping of a behavioural description with the CMOS Complex Cell Compiler : C4.
-
-.so man1/alc_origin.1
-
-.SH SYNOPSIS
-.TP
-\fBc4map\fP  \fIdata_flow_file\fP \fIoutput_file\fP  [\fIparameter_file\fP]
-.br
-
-.SH DESCRIPTION
-.br
-
-.br
-\fB  Input description\fP
-.br
-
-.br
-The logic level behavioural description (.vbe file) uses the same VHDL subset as the logic simulator \fBasimut\fP, the FSM synthesizer \fBsyf\fP, the functional abstractor \fByagle\fP and the formal prover \fBproof\fP (for further information about the subset of VHDL, see the "vbe" manual). 
-.br
-A special feature has been introduced in the VHDL subset in order to allow the don't care description for external outputs and internal registers : A bit signal can take the 'd' value. 
-This value is interpreted as a '0' by the logic simulator \fBasimut\fP. 
-Don't Cares are automatically generated by \fBsyf\fP in the resulting '.vbe' file.
-.br
-For the register signal, only one signal can appear in a guarded expression since the STABLE attribute is used. This attribute is only supported by technology mapping onto a standard cell library as \fBsclib\fP. 
-.br
-\fBc4map\fP is the second step of the logic synthesis : it builds a gate network 
-invoking a CMOS complex cell compiler called C4
-.br
-
-.br
-\fB  Mapping with C4\fP
-.br
-
-.br
-There is no predefined cell library. A decomposition phase is performed on the behavioural description such that each of the logic function are feasible by the C4 compiler. The C4 compiler then generates dynamically the cells througouht the following views :  layout , transistor network and behavioural including data-sheet informations.
-The generated cells have the same height and topology as the SCLIB cells. So the synthesized block is still routable using SCR (or any standard cell router).
-C4 generates dual CMOS gates. The maximum number of serial transistors N (resp. P) is a parameter. The name of the cells generated by C4 is computed according to the expression representing its associated logic function. The operator (o for OR, a for AND) is written in a prefixed notation while the arity (inputs number of the operator) is written in a postfixed notation. A "n" is added for the negative cells.
-.br
-.br
-\fBExample\fP :    F = not ((a and b) or c);     name = noa22
-.br
-.br
-Each cell generated by C4 is dynamically characterized with a RC model and the electrical informations are added to the behavioural description. A technology parameter file is used during this process.
-.br
-
-.br
-\fB  Parameter file '.lax'\fP
-.br
-The parameter file is common with other logic synthesis tools and is used
-for driving the synthesis process. 
-See \fBlax\fP(5) manual for more detail.
-
-.br
-\fBlax\fP uses a lot of parameters to guide every step of the synthesis process.
-Some parameters are globally used (for example, \fIoptimization level\fP whereas others are specifically used (\fBload capacitance\fP for the netlist optimization only).
-Here is the default parameter file (see the user's manual for further information about the syntax of the '.lax' file):
-.br
-
-.br
-   Optimization mode = 2 (50% area - 50% delay)
-.br
-   Optimization level = 2 
-.br
-   Delayed input = 0
-.br
-   Early output = 0
-.br
-   Auxiliary signal saved = 0
-.br
-   Number of serial transistors = 4 in N and P area
-.br
-
-
-
-.SH ENVIRONMENT VARIABLES
-.br
-The following environment variables have to be set before using \fBc4map\fP :
-.HP
-.ti 7
-\fIMBK_WORK_LIB\fP gives the path of the directory of both input and output files (behavioural, structural and parameters description).
-.HP
-.ti 7
-\fIMBK_CATA_LIB\fP gives the auxiliary paths of the directories of input files (behavioural description). 
-.HP
-.ti 7
-\fIMBK_TARGET_LIB\fP gives the path (single) of the directory of the selected standard cell library. 
-.HP
-.ti 7
-\fIMBK_C4_LIB\fP gives the path (single) of the directory for the three views of each cell generated by C4.
-.HP
-.ti 7
-\fIMBK_IN_LO\fP gives the format of models instantiated in the structural description.
-.HP
-.ti 7
-\fIMBK_OUT_LO\fP gives the output format of the structural description.
-.HP
-.ti 7
-\fIMBK_OUT_PH\fP gives the output format for the layout of the cells generated by C4.
-
-
-
-.SH EXAMPLE
-.br
-You can call \fBc4map\fP as follows :
-.br
-.br
-	c4map alu4 alu4c4
-
-
-.SH SEE ALSO
-.br
-scmap(1), c4map(1), xlmap(1), proof(1), yagle(1), asimut(1), vhdl(5), scr(1), sclib(1).
-.br
-
-
-
-.SH DIAGNOSTICS
-.br
-"VHDL : Error - bad usage of the 'stable' attribut"
-.br
-The stable attribut must be used with only one signal in a guarded expression
-.br
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/dlx_asm.1 b/alliance/share/man/man1/dlx_asm.1
deleted file mode 100644
index b4f22c1d..00000000
--- a/alliance/share/man/man1/dlx_asm.1
+++ /dev/null
@@ -1,538 +0,0 @@
-.\"   $Id: dlx_asm.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
-.\" @(#)dlx_asm.5 v0.4 Oct 20 1995 UPMC ; Pirouz BAZARGAN SABET
-.TH DLX_ASM 1 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBDLX_ASM\fP \- assembly language for DLX processor
-
-.SH SYNOPSIS
-.PP
-
-dlx_asm \fI[<options>] <assembly_file> <text_vhdl_file> <data_vhdl_file>\fP
-
-.SH DESCRIPTION
-.PP
-The DLX assembler, \fBdlx_asm\fP, takes assembly language programs, as
-specified bellow and produces a rom (read only memory) using a VHDL syntax.
-
-.PP
-The specified assembly language can be used undifferently for both micro-
-programmed and pipeline version of DLX.
-
-.PP
-For the pipeline version option \fI\-p\fP must be specified.
-
-.pp
-In the assembly language file, two segments can be specified: the text segment
-contains instructions, the data segment contains initialized data and arraies.
-The assembler generates two separate VHDL files corresponding to the text and
-the data segments.
-
-.PP
-The size of the result rom for the text segment can be specified using the
-\fI-textsize bt\fP option, where \fIbt\fP is the maximum number bytes in the
-text segment. By default, \fBdlx_asm\fP produces a rom of 64 instructions
-(256 bytes).
-
-.PP
-The size of the result rom for the data segment can be specified using the
-\fI-datasize bd\fP option, where \fIbd\fP is the maximum number bytes in the
-data segment. By default, \fBdlx_asm\fP produces a rom of 64 bytes.
-
-.PP
-Using the \fI-s\fP option makes the assembler produce a symbol table. Each
-label in the assembly file is associated with an address either in the text
-or the data segment. The label and its corresponding address is written into
-the file specified just after the \fI-s\fP option.
-
-.SH THE FORMAT
-.PP
-An assembly program is a set of statements. Each statement must be followed
-by a \fInewline\fP. An statement is of the form:
-
-.RS
-.PP
-\fB<label> <opcode> <operands>\fP
-.RE
-
-.PP
-\fIlabel\fP is a string used to tag a specific statement or a portion of
-the program. For all opcods (except .equ) a \fIlabel\fP must be followed
-by a ':' (colon) character. The \fIlabel\fP and the \fIopcod\fP may be
-separated by one or several \fInewline(s)\fP. 
-
-.PP
-\fIopcode\fP is a string representing either an effective instruction or
-an assembly directive.
-
-.PP
-An effective instruction is either an instruction, from the DLX's instruction
-set, or a macro\-instruction. The assembler expands a macro\-instruction
-into a set of DLX instructions.
-
-.PP
-\fIoperands\fP is a list of arguments. Depending on the \fIopcode\fP, an
-assembly statement needs from 0 to 3 arguments. Arguments must be separated
-by , (comma).
-
-.PP
-A comment begins with a ';' (semicolon) character and extends until the end
-of the line.
-
-.SH EFFECTIVE INSTRUCTIONS
-.PP
-Here follows the instruction set of the DLX architecture and the syntax of
-each instruction in the assembly file.
-
-.TP 20
-\fBadd\fP Rd, Rs, Rt
-add register to register (signed arithmetic). An overflow exception may be
-generated:
-.br
-\fIRd <- Rs + Rt\fP
-.TP 20
-\fBaddu\fP Rd, Rs, Rt
-(pipeline architecture) add register to register (unsigned arithmetic). An
-overflow exception may be generated:
-.br
-\fIRd <- Rs + Rt\fP
-.TP 20
-\fBsub\fP Rd, Rs, Rt
-subtract register from register (signed arithmetic). An overflow exception
-may be generated:
-.br
-\fIRd <- Rs - Rt\fP
-.TP 20
-\fBsubu\fP Rd, Rs, Rt
-(pipeline architecture) subtract register from register (unsigned arithmetic).
-An overflow exception may be generated:
-.br
-\fIRd <- Rs - Rt\fP
-.TP 20
-\fBand\fP Rd, Rs, Rt
-perform logical bitwise and between two registers:
-.br
-\fIRd <- Rs and Rt\fP
-.TP 20
-\fBor\fP Rd, Rs, Rt
-perform logical bitwise or between two registers:
-.br
-\fIRd <- Rs or Rt\fP
-.TP 20
-\fBxor\fP Rd, Rs, Rt
-perform logical bitwise exclusive or between two registers:
-.br
-\fIRd <- Rs xor Rt\fP
-.TP 20
-\fBaddi\fP Rd, Rs, I
-add immediate to register (signed arithmetic - 16 bits signed immediate
-extended to 32 bits). An overflow exception may be generated:
-.br
-\fIRd <- Rs + I\fP
-.TP 20
-\fBaddui\fP Rd, Rs, I
-(pipeline architecture) add immediate to register (unsigned arithmetic - 16
-bits unsigned immediate extended to 32 bits). An overflow exception may be
-generated:
-.br
-\fIRd <- Rs + I\fP
-.TP 20
-\fBsubi\fP Rd, Rs, I
-subtract immediate from register (signed arithmetic - 16 bits signed immediate
-extended to 32 bits). An overflow exception may be generated:
-.br
-\fIRd <- Rs - I\fP
-.TP 20
-\fBsubui\fP Rd, Rs, I
-(pipeline architecture) subtract immediate from register (unsigned arithmetic
-- 16 bits unsigned immediate extended to 32 bits). An overflow exception may
-be generated:
-.br
-\fIRd <- Rs - I\fP
-.TP 20
-\fBandi\fP Rd, Rs, I
-perform logical bitwise and between immediate and register (16 bits unsigned
-immediate extended to 32 bits):
-.br
-\fIRd <- Rs and I\fP
-.TP 20
-\fBori\fP Rd, Rs, I
-perform logical bitwise or between immediate and register (16 bits unsigned
-immediate extended to 32 bits):
-.br
-\fIRd <- Rs or I\fP
-.TP 20
-\fBxori\fP Rd, Rs, I
-perform logical bitwise exclusive or between immediate and register (16 bits
-unsigned immediate extended to 32 bits):
-.br
-\fIRd <- Rs xor \fP
-.TP 20
-\fBsll\fP Rd, Rs, Rt
-shift left register (only the 5 lsb of Rt are significant):
-.br
-\fIRd <- Rs << Rt\fP
-.TP 20
-\fBsrl\fP Rd, Rs, Rt
-shift right register (logic - only the 5 lsb of Rt are significant):
-.br
-\fIRd <- Rs << Rt\fP
-.TP 20
-\fBsra\fP Rd, Rs, Rt
-shift right register (arithmetic - only the 5 lsb of Rt are significant):
-.br
-\fIRd <- Rs << Rt\fP
-.TP 20
-\fBslli\fP Rd, Rs, I
-shift left register (5 bits unsigned immediate):
-.br
-\fIRd <- Rs << I\fP
-.TP 20
-\fBsrli\fP Rd, Rs, I
-shift right register (logic - 5 bits unsigned immediate):
-.br
-\fIRd <- Rs << I\fP
-.TP 20
-\fBsrai\fP Rd, Rs, I
-shift right register (arithmetic - 5 bits unsigned immediate):
-.br
-\fIRd <- Rs << I\fP
-.TP 20
-\fBlhi\fP Rd, I
-load high order bits of register (16 bits immediate completed with 16 zeros at
-last significant bits):
-.br
-\fIRd <- I\fP
-.TP 20
-\fBseq\fP Rd, Rs, Rt
-set register if equal zero:
-.br
-\fIRd <- 1 if (Rs = Rt) else 0\fP
-.TP 20
-\fBsne\fP Rd, Rs, Rt
-set register if non equal zero:
-.br
-\fIRd <- 1 if (Rs != Rt) else 0\fP
-.TP 20
-\fBsge\fP Rd, Rs, Rt
-set register if greater than or equal zero:
-.br
-\fIRd <- 1 if (Rs >= Rt) else 0\fP
-.TP 20
-\fBsgeu\fP Rd, Rs, Rt
-(pipeline architecture) set register if greater than or equal zero (unsigned):
-.br
-\fIRd <- 1 if (Rs >= Rt) else 0\fP
-.TP 20
-\fBsle\fP Rd, Rs, Rt
-set register if less than or equal zero:
-.br
-\fIRd <- 1 if (Rs <= Rt) else 0\fP
-.TP 20
-\fBsleu\fP Rd, Rs, Rt
-(pipeline architecture) set register if less than or equal zero (unsigned):
-.br
-\fIRd <- 1 if (Rs <= Rt) else 0\fP
-.TP 20
-\fBsgt\fP Rd, Rs, Rt
-set register if greater than:
-.br
-\fIRd <- 1 if (Rs > Rt) else 0\fP
-.TP 20
-\fBsgtu\fP Rd, Rs, Rt
-(pipeline architecture) set register if greater than (unsigned):
-.br
-\fIRd <- 1 if (Rs > Rt) else 0\fP
-.TP 20
-\fBslt\fP Rd, Rs, Rt
-set register if less than:
-.br
-\fIRd <- 1 if (Rs < Rt) else 0\fP
-.TP 20
-\fBsltu\fP Rd, Rs, Rt
-(pipeline architecture) set register if less than (unsigned):
-.br
-\fIRd <- 1 if (Rs < Rt) else 0\fP
-.TP 20
-\fBseqi\fP Rd, Rs, I
-set register if equal zero (16 bits signed immediate extended to 32 bits):
-.br
-\fIRd <- 1 if (Rs = I) else 0\fP
-.TP 20
-\fBsnei\fP Rd, Rs, I
-set register if not equal zero (16 bits signed immediate extended to 32 bits):
-.br
-\fIRd <- 1 if (Rs != I) else 0\fP
-.TP 20
-\fBsgei\fP Rd, Rs, I
-set register if greater than or equal zero (16 bits signed immediate extended
-to 32 bits):
-.br
-\fIRd <- 1 if (Rs >= I) else 0\fP
-.TP 20
-\fBsgeui\fP Rd, Rs, I
-(pipeline architecture) set register if greater than or equal zero (unsigned
-- 16 bits unsigned immediate extended to 32 bits):
-.br
-\fIRd <- 1 if (Rs >= I) else 0\fP
-.TP 20
-\fBslei\fP Rd, Rs, I
-set register if less than or equal zero (16 bits signed immediate extended to
-32 bits):
-.br
-\fIRd <- 1 if (Rs <= I) else 0\fP
-.TP 20
-\fBsleui\fP Rd, Rs, I
-(pipeline architecture) set register if less than or equal zero (unsigned -
-16 bits unsigned immediate extended to 32 bits):
-.br
-\fIRd <- 1 if (Rs <= I) else 0\fP
-.TP 20
-\fBsgti\fP Rd, Rs, I
-set register if greater than (16 bits signed immediate extended to 32 bits):
-.br
-\fIRd <- 1 if (Rs > I) else 0\fP
-.TP 20
-\fBsgtui\fP Rd, Rs, I
-(pipeline architecture) set register if greater than (unsigned - 16 bits
-unsigned immediate extended to 32 bits):
-.br
-\fIRd <- 1 if (Rs > I) else 0\fP
-.TP 20
-\fBslti\fP Rd, Rs, I
-set register if less than (16 bits signed immediate extended to 32 bits):
-.br
-\fIRd <- 1 if (Rs < I) else 0\fP
-.TP 20
-\fBsltui\fP Rd, Rs, I
-(pipeline architecture) set register if less than (unsigned - 16 bits
-unsigned immediate extended to 32 bits):
-.br
-\fIRd <- 1 if (Rs < I) else 0\fP
-.TP 20
-\fBsw\fP I(Rs), Rt
-store register (word) into external storage (16 bits signed immediate extended
-to 32 bits). The memory address must be aligned:
-.br
-\fIStorage (Rs + I) <- Rt\fP
-.TP 20
-\fBsh\fP I(Rs), Rt
-(pipeline architecture) store half-word (2 last significant bytes) of register
-into external storage (16 bits signed immediate extended to 32 bits). The
-memory address must be aligned:
-.br
-\fIStorage (Rs + I) <- Rt\fP
-.TP 20
-\fBsb\fP I(Rs), Rt
-store the last significant byte of register into external storage (16 bits
-signed immediate extended to 32 bits):
-.br
-\fIStorage (Rs + I) <- Rt\fP
-.TP 20
-\fBlw\fP Rd, I(Rs)
-load a word from external storage into register (16 bits signed immediate
-extended to 32 bits). The memory address must be aligned:
-.br
-\fIRd <- Storage (Rs + I)\fP
-.TP 20
-\fBlh\fP Rd, I(Rs)
-(pipeline architecture) load a signed half-word (2 bytes) from external
-storage into register (16 bits signed immediate extended to 32 bits - the
-signed half-word read from external storage is extended to 32 bits). The
-memory address must be aligned:
-.br
-\fIRd <- Storage (Rs + I)\fP
-.TP 20
-\fBlhu\fP Rd, I(Rs)
-(pipeline architecture) load an unsigned half-word (2 bytes) from external
-storage into register (16 bits signed immediate extended to 32 bits
-- the unsigned half-word read from external storage is extended to 32 bits).
-The memory address must be aligned:
-.br
-\fIRd <- Storage (Rs + I)\fP
-.TP 20
-\fBlb\fP Rd, I(Rs)
-(pipeline architecture) load a signed single byte from external storage into
-register (16 bits signed immediate extended to 32 bits - the signed byte
-read from external storage is extended to 32 bits):
-.br
-\fIRd <- Storage (Rs + I)\fP
-.TP 20
-\fBlbu\fP Rd, I(Rs)
-load an unsigned single byte from external storage into register (16 bits
-signed immediate extended to 32 bits - the unsigned byte read from external
-storage is extended to 32 bits):
-.br
-\fIRd <- Storage (Rs + I)\fP
-.TP 20
-\fBjr\fP Rs
-jump register:
-.br
-\fIPC <- Rs\fP
-.TP 20
-\fBjalr\fP Rs
-jump and link register:
-.br
-\fIPC <- Rs\fP
-.br
-\fIR31 <- PC + 4\fP
-.TP 20
-\fBmovs2i\fP Rd, S
-move special register (S may be IAR, SR or TVR) into integer register
-(privileged instruction):
-.br
-\fIRd <- S\fP
-.TP 20
-\fBmovi2s\fP S, Rs
-move integer register into special register (S may be IAR, SR or TVR)
-(privileged instruction):
-.br
-\fIS <- Rs\fP
-.TP 20
-\fBbeqz\fP Rs, label
-branch if equal zero
-.br
-\fIPC <- label if (Rs = 0)\fP
-.TP 20
-\fBbnez\fP Rs, label
-branch if not equal zero:
-.br
-\fIPC <- label if (Rs != 0)\fP
-.TP 20
-\fBj\fP label
-jump:
-.br
-\fIPC <- label\fP
-.TP 20
-\fBjal\fP label
-jump and link:
-.br
-\fIPC <- label\fP
-.br
-\fIR31 <- PC + 4\fP
-.TP 20
-\fBrfe\fP
-return from interrupt (privileged instruction)
-.TP 20
-\fBtrap\fP I
-software interrupt (the 16 bits unsigned immediate represents the trap
-number)
-
-.PP
-Macro\-instructions are the followings:
-
-.TP 20
-\fBnop\fP
-no operation
-.TP 20
-\fBloadi\fP Rd, I
-load immediate into register (32 bits immediate):
-.br
-\fIRd <- I\fP
-
-.SH ASSEMBLY DIRECTIVES
-.PP
-In addition to the instruction set several assembly directives can be used
-either to enhance the readability or specify memory allocation or segment
-partition.
-
-.TP 20
-\fB \.equ\fP I
-assign the value of an immediate to a \fIlabel\fP.
-.TP 20
-\fB \.org\fP address
-set the address (of the first statement) in the text or data segment to the
-location defined by the \fIaddress\fP (32 bits).
-.TP 20
-\fB \.start\fP label
-marks the first statement of the program to be executed.
-.TP 20
-\fB \.end\fP
-marks the end of the program.
-.TP 20
-\fB \.space\fP I
-make a reservation of \fII\fP bytes in the current segment.
-.TP 20
-\fB \.skip\fP I
-skip \fII\fP bytes in the current segment (the current address is incremented
-by \fII\fP).
-.TP 20
-\fB \.word\fP I
-make a reservation of one word (4 bytes) in the current segment and initialize
-the word to the value specified by \fII\fP.
-.TP 20
-\fB \.byte\fP I
-make a reservation of one byte in the current segment and initialize the
-byte to the value specified by \fII\fP.
-.TP 20
-\fB \.align\fP I
-align the address. Depending on \fII\fP (which values may be 2 or 4), the
-address is aligned on 2 or 4 bytes.
-.TP 20
-\fB \.data\fP address
-indicates that the following section of the assembly file must be placed
-in the data segment. If an \fIaddress\fP is specified, the generated code
-is placed at the location specified by \fIaddress\fP.
-.TP 20
-\fB \.text\fP address
-indicates that the following section of the assembly file must be placed
-in the text segment. If an \fIaddress\fP is specified, the generated code
-is placed at the location specified by \fIaddress\fP.
-
-.SH NOTES
-.PP
-Immediate values can be expressed using decimal, binary, octal or hexadecimal
-representations:
-.RS
-.TP 10
--235
-decimal value
-.TP 10
-0b01011
-binary value
-.TP 10
-0o376
-octal value
-.TP 10
-0x0f72
-hexadecimal value
-.RE
-
-.PP
-A static expression can be used instead of an immediate. There is no
-priority between operators, and the parenthesis must be used to avoid
-confusion. The following operations are allowed inside expressions:
-
-.RS
-.TP 10
-\fB\+\fP
-arithmetic addition
-.TP 10
-\fB\-\fP
-arithmetic subtraction
-.TP 10
-\fB*\fP
-arithmetic multiplication
-.TP 10
-\fP\>\>\fP
-shift arithmetic right
-.TP 10
-\fP\<\<\fP
-shift logical left
-.RE
-
-.SH EXAMPLE
-.PP
-dlx_asm \-p -textsize 32000 prog text data
-.br
-dlx_asm \-p \-datasize 65000 \-s symb_file prog text data
-
-.SH SEE ALSO
-.PP
-vhdl(5), vbe(5), asimut(1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/dpp.1 b/alliance/share/man/man1/dpp.1
deleted file mode 100644
index 4e1d25d5..00000000
--- a/alliance/share/man/man1/dpp.1
+++ /dev/null
@@ -1,248 +0,0 @@
-.\"   $Id: dpp.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
-.\" @(#)Labo.l 0.0 93/03/06 UPMC; Author: Lotfi BEN AMMAR
-.pl -.4
-.TH DPP 1 "October 1, 1997" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
-.SH NAME
-.TP
-dpp
- - DataPath Placement tool
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.TP
-\fBdpp\fP <\fIsource\fP> [\fBMSB\fP] [\fB-o1/-o2\fP]
-.br
-.SH DESCRIPTION
-\fBdpp\fP is an automatic placement tool for bit-sliced datapath. It can be
-used with the specialized router dpr.
-.br
-
-\fB1/ The Bit-slice Topology\fP
-.br
-A datapath is considered as a set of operators handling bus-structured data.
-It is made by abutting operators (or columns) horizontally.
-In fully regular multi-bit architectures, all operators are N-bit height,
-N corresponds to the number of bits. So, a bit-sliced datapath structure
-is similar to a two-dimensional array where lines and columns correspond
-respectively to bit-slices and operators. Data busses are distributed
-horizontally
-in metal2 over the cells, while control lines run vertically in metal1.
-Power and ground supplies
-are horizontal in metal2, they delimit slices and are shared by two adjacent
-bit-slices. Least Significant Bit (L.S.B) is at the bottom, while Most
-Significant Bit (M.S.B) is at the top. At the top of the datapath, two slices
-are dedicated to the control line buffers. So for a 32 bit datapath the compiled
-layout is 34 slices.
-
-\fB2/ Datapath components\fP
-.br
-Two types of components may be used in a datapath:
-.br
-
-- One-bit functional cells called bit-cells. Such components are available in a
-specialized datapath cell library called DPLIB.
-.br
-
-- Multi-bit optimized blocks provided by a set of parameterized datapath block
-generators.
-.br
-
-The parameterized datapath block generators may be used for complex operators
-such as fast adders, barrel shifters and register files. To
-construct regular multi-bit operators such as multiplexers, logic units and
-buffers or to implement irregular operators such as comparators and flag
-generators, DPLIB cells must be used.
-
-\fB3/ User Interface\fP
-.br
-The placement tool needs as an input the datapath net-list.
-It must be given in the "source" file. This file
-must be available in the directory defined by the environment variable
-\fBMBK_WORK_LIB\fP. The result file provided by the
-placement tool contains the physical description of the datapath. It is saved,
-with the same name as the source file, in the directory defined by the
-environment variable
-\fBMBK_WORK_LIB\fP. Several logical and physical description formats are
-supported by this tool. The input netlist format of both the datapath
-and its components is defined by the environment variable \fBMBK_IN_LO\fP.
-the input layout format of each datapath leaf-cell is defined by the
-environment variable \fBMBK_IN_PH\fP.
-While the output layout format is defined by the environment variable
-\fBMBK_OUT_PH\fP.
-.br
-
-The input net-list must be structured in one or two hierarchical levels:
-.br
-- First hierarchical level defines the datapath operators (or columns). At
-this level, columns are either multi-bit optimized blocks or structured.
-These operators are abutted horizontally by the placement tool.
-.br
-- The possible second hierarchical level contains one-bit cells that belong
-to DPLIB to form
-the structured operators. In that case cells are stacked vertically in the
-same column.
-.br
-
-At the moment, \fBdpp\fP needs a catalog file whose name is defined by the
-environment variable \fBMBK_CATAL_NAME\fP, the default name is CATAL.
-This file must contain the model names of the optimized blocks. These blocks
-must be generated before invoking the placement tool. It tells the placement
-tool which elements must be considered as leaf-cells in addition to DPLIB cells.
-For more details about the catalog file use "man catal".
-Files describing the logical view and the physical view of each leaf-cell
-must be available in one of the directories defined by the environment
-variable \fBMBK_CATA_LIB\fP.
-.br
-
-Placement is performed in two independent steps: a constructive step that
-builds the different columns and a second step that abuts columns horizontally
-and optimizes (if specified) the column ordering. During the first step, the
-vertical bit-cell placemennt is based on the optional information given by
-the user through the instance name. The integer just after the last
-underscore '_' in the instance name is supposed to be the slice index
-in which the cell must be placed. For example an instance named "toto_0" will
-be placed in the slice number 0. When the cell is two or more slice height,
-the index corresponds to the lower slice. For example in a 32 bit datapath,
-buffers (two slice height) must be named "tata_32".
-.br
-
-While constructing columns, vertical abutability is checked to ensure the
-control line continuity. Warning messages may appear during this placement
-step.
-.br
-
-Datapath external terminals are automatically created and placed by this
-tool. We define two types of terminals: data terminals and control terminals.
-A data terminal is placed on the west or east abutment box side, in its
-corresponding slice. While a control terminal is placed on the north or/and
-south abutment box side(s), in its column.
-.br
-
-.SH OPTIONS
-.TP
-\MSB:
-This option is necessary to tell the placement tool that the index 0
-corresponds to the MSB. So, in a 32 bit datapath plus two slice buffers,
-the LSB cells must be indexed by 33 while the buffers must be indexed by 1.
-By default the index 0 corresponds to the LSB.
-.TP
-\-o1:
-This option tells the placement tool to optimize the column ordering.
-The algorithm that will be used for this task is the first one: for a given
-permutation cycle, the exchange of two columns that gives the best solution
-is realized. If this option is not given, the resulting column ordering
-corresponds to the order of the operators found in the input netlist. This feature
-may be used to dictate a given column ordering.
-.TP
-\-o2:
-This option tells the placement tool to optimize the column ordering.
-The algorithm that will be used for this task is the second one: each time
-that a permutation of two columns gives a better solution, columns are exchanged,
-and so on. If this option is not given, the resulting column ordering
-corresponds to the order of the operators found in the input netlist. This feature
-may be used to dictate a given column ordering.
-.br
-
-.SH ERROR MESSAGES
-.br
-
-.BR 1/ 
-\fI<figname> is not in the CATAL, must be a second hierarchical level!\fP
-.br
-This message appears when a figure is instanciated in the first hierarchical
-level and is neither a leaf-cell (in the CATAL) nor structured (a second
-hierarchical level).
-
-.BR 2/ 
-\fI<figname> is not in the CATAL!\fP
-.br
-This message appears when a figure is instanciated in the second hierarchical
-level and is not in the CATAL file.
-
-.BR 3/ 
-\fIPhysical terminal <conname> with no logical corresponding in <figname>!\fP
-.br
-This message appears when a physical terminal has no corresponding logical
-terminal for a given leaf-cell. Logical and physical terminals must have the
-same name in both logical and physical descriptions.
-
-.BR 4/ 
-\fIVirtual terminal <conname> in <figname> is not valid!\fP
-.br
-This message appears when a virtual terminal does not respect the naming
-convention which is "conname_tracknumber" (for example "titi_0") or when
-it is not covered by an allow-metal2 wire.
-
-.BR 5/ 
-\fIAllow-metal2 wire in <figname> not valid!\fP
-.br
-This message appears when an allow-metal2 wire is fully or partially out of
-the abutment box of the figure.
-.br
-
-.BR 6/ 
-\fIThe index must be an integer in <insname>!\fP
-.br
-This message appears when the index, just after the underscore, in the instance
-name is not an integer.
-.br
-
-.BR 6/ 
-\fISpace [i,j] is already full!\fP
-.br
-This message appears when two different instances in the same column have the
-same index or when instance indexes are not correctly given (especially if
-there is two or more slice height instances in the coolumn).
-.br
-
-.SH EXAMPLES
-To use \fBdpp\fP, some environment variables must be set :
-.br
-If the VHDL format for netlist and the MODGEN format for layout are used,
-the user must have the following environment:
-.br
-.BR 	MBK_CATA_LIB 
-=/labo/cells/dpr:/labo/cells/rsa/:/labo/cells/bgd:/labo/cells/bsg
-.br
-.BR 	MBK_IN_LO 
-=vst
-.br
-.BR 	MBK_IN_PH 
-=mg
-.br
-.BR 	MBK_OUT_PH 
-=mg
-.br
-.BR 	MBK_CATAL_NAME 
-=CATAL
-.br
-.BR 	MBK_WORK_LIB 
-=. 
-.br
-The command line to be executed for placing the datapath called "alu4" without
-any option is the following:
-.br
-
-\fBdpp\fP alu4
-.br
-
-This command generates the physical initial placement of the alu4. In that case
-the indexes 0 and 3 correspond respectively to the MSB and the LSB.
-.br
-
-.SH SEE ALSO
-.BR MBK_IN_LO (1),
-.BR MBK_IN_PH (1),
-.BR MBK_OUT_PH (1),
-.BR MBK_CATA_LIB (1),
-.BR MBK_WORK_LIB (1),
-.BR MBK_CATAL_NAME (1),
-.BR dplib (1),
-.BR catal(5),
-.BR dpr(1),
-.BR rsa(1),
-.BR bgd(1),
-.BR bsg(1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/dpr.1 b/alliance/share/man/man1/dpr.1
deleted file mode 100644
index 7903cdae..00000000
--- a/alliance/share/man/man1/dpr.1
+++ /dev/null
@@ -1,411 +0,0 @@
-.\"   $Id: dpr.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
-.\" @(#)Labo.l 0.0 95/10/04 UPMC; Author: BEAURIN Olivier
-.pl -.4
-.TH DPR 1 "October 1, 1997" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
-.SH NAME
-DPR \- Placer-Router for Datapath Compiler
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.ft B
-dpr [-v|V] [-p] [-s name1 s:t[,s1:t1]] [-r name2] [-w nb] [-i nb] [-c nb] \fIsource\fP
-.ft R
-.SH DESCRIPTION
-DPR is a specialized placement and routing tool for bit-sliced datapaths.
-It is recommended to be used with the dedicated datapath description language,
-FPGEN.
-.br
-
-\fB1/ The Bit-slice Topology\fP
-.br
-
-A datapath is considered as a set of operators handling bus-structured data.
-The physical structure is made by abutting operators (or columns) horizontally.
-In fully regular multi-bit architectures, all operators are N-bit height,
-N corresponds to the number of bits. So, a bit-sliced datapath structure
-is similar to a two-dimensional array where lines and columns correspond
-respectively to bit-slices and operators. Data busses are distributed
-horizontally
-in metal2 over the cells, while control lines run vertically in metal1.
-To perform inter-slice connections, such as shifts and propagations, vertical
-routing channels are automatically created between operators.
-Power and ground supplies
-are horizontal in metal2, they delimit slices and are shared by two adjacent
-bit-slices. Vertical power and ground wires in metal1 are possible between
-operators when specified by the user.
-At the top of the datapath, two slices
-are dedicated to the control line buffers.
-For example, if a 32 bit datapath is specified, the compiled
-layout is 34 slice height.
-
-\fB2/ Datapath components\fP
-.br
-
-Two types of components may be used in a datapath:
-.br
-
-- Multi-bit optimized blocks, that can be provided by parameterized
-datapath block generators. Some complex operators such as fast adders (RSA),
-barrel shifters (BSG), pipelined multipliers (AMG) and register files (RFG)
-are considered by DPR as leaf-cells.
-.br
-
-- One-bit functional cells called bit-cells. Such components are available in a
-specialized datapath cell library called DPLIB. Functions are similar to those
-found in a classical standard-cell. This type of components may be used to
-synthesize irregular blocks (or heterogeneous operators).
-
-\fB3/ User Interface\fP
-.br
-
-All the hierarchical constraints that we describe in this
-section may be ignored if the input net-list
-is synthesized by using the FPGEN language.
-.br
-DPR can be used to perform placement or routing separately, or both placement
-and routing sequentially.
-
-The place and route tool needs, as input, the datapath net-list, that must be
-given in the "source" file. It also needs
-the structural and physical views of each
-leaf-cell.
-After the placement step, we obtain a result file containing
-the positions of the corresponding physical instances and terminals.
-.br
-
-At present, the input datapath net-list must be structured in one or two
-hierarchical levels, considering optimized blocks, DPLIB cells and FPLIB
-cells as terminal leaf-cells:
-.br
-- The first hierarchical level defines the datapath operators (or columns).
-.br
-- The possible second hierarchical level describes the structured operators.
-It contains one-bit cells that belong to DPLIB library (heterogeneous operators)
-or FPLIB library (regular operators). In that case leaf-cells are stacked
-vertically in the same column during the placement step.
-.br
-
-Placement is performed in two independent steps: a constructive step that
-builds the different columns and a second step that abuts columns horizontally.
-During the first step, the
-vertical bit-cell placemennt is based on the optional information given by
-the user through the instance name. The integer just after the last
-underscore '_' in the instance name is supposed to be the slice index
-in which the cell must be placed. For example an instance named "name_0" will
-be placed in the slice number 0, namely, the LSB slice.
-If a given cell is more than one slice height, the index must
-correspond to the lower slice. For example, in a 32 bit datapath,
-buffers (two slice height) must be named "name_32".
-While constructing columns, vertical abutability is checked to ensure the
-possible control line continuity. Warning messages may appear during this
-placement step. During the second step columns are abutted horizontally.
-The column ordering may be automatically optimized in the routing step.
-.br
-
-Datapath external terminals are automatically created and placed by DPR.
-We define two types of terminals: data terminals and control terminals.
-A data terminal is placed on the west or east abutment box side, in its
-corresponding slice. A control terminal is placed on the north or/and
-south abutment box side(s), in its column. A data terminal can be forced
-on the north or south abutment box side by using the .dpr file.
-.br
-
-The routing step gives a symbolic layout file that contains the final
-physical description of the datapath components and the routing wires.
-Vertical power
-(VDD) and ground (VSS) wires in metal1 are automatically inserted
-if requested in the .dpr file.
-.br
-
-.SH ENVIRONMENT
-.br
-
-DPR supports several structural and physical formats for
-inputs and outputs. The input net-list format of the datapath and its
-components is defined by the environment variable \fBMBK_IN_LO\fP. The input
-and output physical format(s) of the datapath and its leaf-cells are defined
-respectively by the environment variables \fBMBK_IN_PH\fP and \fBMBK_OUT_PH\fP.
-Files describing the logical view and the physical view of each leaf-cell
-must be available in one of the directories defined by the environment
-variable \fBMBK_CATA_LIB\fP.
-.br
-At the moment, DPR needs a catalog file which name is defined by the
-environment variable \fBMBK_CATAL_NAME\fP. This file describes
-which components must be considered as leaf-cells in addition
-to the DPLIB and FPLIB cells. For example, the catalog file must contain the
-model names of the optimized blocks used in the datapath description.
-Such blocks must be generated before invoking the placement and routing tool.
-.br
-
-.SH TERMINAL PLACEMENT FILE
-.br
-The \fB<source>.dpr\fR optional file allow the designer to place
-precisely the data-path external DATA terminals. Notice that CTRL
-terminals are sets to fixed positions on north side of the data-path and
-cannot be moved.
-.ft CR
-.br
-	Here is a short example :
-.br
-.ft CR
-.nf
-
-#
-# Terminal Placement.
-#        :  Terminal Name   :  Side :  Slice  :  Track 
-# =====================================================
-DP_LOCON         cout         NORTH   DEFAULT   DEFAULT
-DP_LOCON    pin_input[4]       EAST      3      DEFAULT
-DP_LOCON    bus_input[15:0]    EAST   DEFAULT   DEFAULT
-DP_LOCON   bus_output[15:0]    WEST     15:0       1
-#
-#
-# Informations For Glue Logic Placer.
-#          Model Name   : Iterations : Height : CPC
-# ==================================================
-DP_GLUE  glue_model_us       5000         8      2
-#
-#
-# Informations For Placer
-# =======================
-DP_KEEP  user1_us  user2_us
-#
-#
-# Global Power Refreshment.
-#        : Number : Width
-# ========================
-DP_POWER     3        60
-#
-# Power Refreshement associated to specific columns.
-#        : Column Name : Side : Width
-# ====================================
-DP_POWER      nand2      EAST     70
-#
-#
-# Resize Abutment-Box.
-#        :  DXAB1 : DXAB2
-# =======================
-DP_DEFAB     -10     +10
-
-.fi
-.ft R
-The \fBDP_LOCON\fP instruction : DP_LOCON ConName Side Slice Track
-.br
-
-.ta +11n +2n
-.in +13n
-.ti -13n
-ConName	:	Terminal name, a vectorized notation can be used.
-.br
-
-.ti -13n
-Side	:	The side of the data-path on which the terminal must be set.
-The legal values are :
-.br
-.in +11m
-.ti -11m
-.ta +2m +8m +1m
--	\fBDEFAULT\fP	:	The terminal will be set on East or West side.
-.br
-.ti -11m
--	\fBEAST\fP	:	East side.
-.br
-.ti -11m
--	\fBWEST\fP	:	West side.
-.br
-.ti -11m
--	\fBNORTH\fP	:	North side.
-.br
-.ti -11m
--	\fBSOUTH\fP	:	South side.
-.br
-.in -11m
-When set to the \fBNORTH\fP or \fBSOUTH\fP side, the fields Slice and
-Track are not meaningful and must be sets to \fBDEFAULT\fP. There is
-no means to sets more precisely a terminal to the north or south side.
-
-.in -13n
-.ta +11n +2n
-.in +13n
-.ti -13n
-Slice	:	Slice where the terminal will appear, a vectorized notation
-can be used. In this case the wide of this vector must be the same as the
-ConName vector.
-.br
-
-.ti -13n
-Track	:	The track where the terminal will be set, inside his slice.
-When a vector is used for the ConName, the track is the same for each
-bit of the vector.
-.br
-
-.ti -13n
-The \fBDP_GLUE\fP instruction : DP_GLUE ModelName Iterations Height CPC
-.br
-
-.ta +11n +2n
-.ti -13n
-ModelName	:	Glue logic model name (must be suffixed by \fB_us\fP,
-see \fBfpgen(1)\fP).
-.br
-
-.ti -13n
-Iterations	:	Number of iterations for the placement algorithm.
-.br
-
-.ti -13n
-Height	:	Number of slices allowed to do the placement.
-.br
-
-.ti -13n
-CPC	:	Number of cell per columns.
-.br
-
-.ti -13n
-The \fBDP_KEEP\fP instruction : DP_KEEP ModelName1 ModelName2 ...
-.br
-
-.ta +11n +2n
-.ti -13n
-ModelNameN	:	Tells the placer to keep any previously generated
-placement for model ModelNameN. This useful for big glue logic blocks
-for which placement can take much time.
-.br
-
-.ti -13n
-The \fBDP_POWER\fP instruction : two forms are possibles :
-.br
-DP_POWER ColName Side Width
-.br
-DP_POWER Number Width
-.br
-
-.ti -13n
-ColName	:	The name of the column where the vertical power
-refreshement will be set.
-.br
-
-.ti -13n
-Side	:	The side of the column on which set the power refreshment.
-.br
-
-.ti -13n
-Width	:	The wide of the power refresment.
-.br
-
-.ti -13n
-Number	:	The number of power refreshment. They are splitted across
-the data-path as periodicaly as possible.
-.br
-
-.ti -13n
-The \fBDP_DEFAB\fP instruction : DP_DEFAB DXAB1 DXAB2
-.br
-
-.ti -13n
-DXAB1	:	Number of lambdas added to the top of the abutment-box.
-.br
-
-.ti -13n
-DXAB2	:	Number of lambdas added to the bottom of the
-abutment-box.
-.br
-
-Only one instruction DP_DEFAB is allowed in a .dpr file. If
-DP_DEFAB is not found, then \fBDXAB1\fP is set to -10 and
-\fBDXAB2\fP to +10, in order for the generated data-path to be routed
-by a floorplan router or \fBbbr(1)\fP.
-
-.ft R
-
-.SH OPTIONS
-.TP
-\-p :
-This option activates the placement step.
-.TP
-\-r :
-This option activates the routing step.
-In that case the name of the routed
-datapath must be given explicitly after the -r parameter.
-.TP
-\-o :
-This option optimizes the column ordering.
-It can be used only if the routing step is activated.
-.TP
-\-s :
-This option activate the streching step. The datapath
-will be t tracks strech in slice s. The name after the -s
-option indicate the final placement and strech layout name and the
-new netlist name.
-.TP
-\-w :
-This option indicate the datapath width when DPR can't
-calculate it.
-.TP
-\-i :
-This option set the default iteration number for the
-simulated annealing placement algorithm.
-.TP
-\-c :
-This option set the default number of cells puts in one column
-in the glue logic placement step.
-.TP
-\-v :
-This option set the verbose mode on.
-.TP
-\-V :
-This option set the verbose mode max.
-
-.SH EXAMPLES
-To use DPR, some environment variables must be set :
-.br
-If the VHDL format for netlist (.vst) and the ALLIANCE format for layout
-(.ap) are used for the "alu4" example,
-the user must have the following environment:
-.br
-.BR 	MBK_CATA_LIB 
-=/labo/cells/fitpath/fplib:/labo/cells/rsa
-.br
-.BR 	MBK_IN_LO 
-= vst
-.br
-.BR 	MBK_IN_PH 
-= ap
-.br
-.BR 	MBK_OUT_PH 
-= ap
-.br
-.BR 	MBK_CATAL_NAME 
-= CATAL
-.br
-.BR 	MBK_WORK_LIB 
-= . 
-.br
-The command line to be executed in order to place and route the datapath
-example called "alu4" without any option is the following:
-.br
-
-dpr -p -r alu4r alu4
-.br
-
-This command generates the datapath layout and saves it in the file alu4r.
-.br
-
-.SH SEE ALSO
-.BR MBK_IN_LO (1),
-.BR MBK_IN_PH (1),
-.BR MBK_OUT_PH (1),
-.BR MBK_CATA_LIB (1),
-.BR MBK_WORK_LIB (1),
-.BR MBK_CATAL_NAME (1),
-.BR catal (5),
-.BR fpgen (1),
-.BR fplib (1),
-.BR dplib (1),
-.BR rsa (1),
-.BR rfg (1),
-.BR bsg (1).
-.BR amg (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/dreal.1 b/alliance/share/man/man1/dreal.1
deleted file mode 100644
index 9b39c4bb..00000000
--- a/alliance/share/man/man1/dreal.1
+++ /dev/null
@@ -1,77 +0,0 @@
-.\"   $Id: dreal.1,v 1.2 1999/11/05 14:23:29 syf Exp $
-.\" @(#)dreal 1.07 94/10/10 UPMC/ASIM/LIP6/CAO-VLSI "
-.TH DREAL 1 "October 1, 1997" "ASIM/LIP6" "ALLIANCE Reference Manual"
-.SH NAME
-dreal \- Graphic real layout viewer
-.SH SYNOPSIS
-.B dreal 
-[\-l file_name]
-[\-xor]
-[\-debug]
-[\-install]
-[\-force]
-.br
-.so man1/alc_origin.1
-.SH DESCRIPTION
-.B Dreal
-is a hierarchical real layout viewer. All functionnalities can be
-accessed through different menus.
-.B Dreal
-works under Motif and X11r5.
-When entering 
-.B Dreal,
-the main window appears and shows 4 different
-menus on the top bar.These menus can be entered by simply clicking on the
-mouse left button. Here is the description of these menus.
-
-.TP 10
-.B File
-\f4Open\fP : load an existing cell.
-.br
-\f4Quit\fP : quit dreal.
-
-.TP 10   
-.B View
-\f4Zoom\fP : perform zoom in, zoom out, center, fit, refresh on figure.
-.br
-\f4Layer\fP : select types of layers displayed.
-.br
-\f4Map\fP : show cursor position in the entire figure.
-.br
-\f4Arrows\fP : show arrows for moving at the grid step.
-.br
-\f4Grid\fP : Set the X,Y step of the grid if displayed.
-
-.TP 10
-.B Tools
-\f4Flatten\fP : flatten the current figure.
-.br
-\f4Message\fP : display the last error messages.
-
-.TP 10
-.B Setup
-Save or load a user defined configuration of default displayed menus.
-
-.SH ENVIRONMENT VARIABLES
-.TP
-.B MBK_CATA_LIB
-indicates the path to the read only libraries to be used. 
-.TP
-.B MBK_WORK_LIB
-indicates the path to the read directory for the session.
-.TP
-.B RDS_IN
-indicates the file format to be used for the cell.
-.TP
-.B DREAL_TECHNO_NAME (optionnal)
-indicates the path to the techno name file used by Dreal.
-.TP
-.B RDS_TECHNO_NAME (optionnal)
-indicates the path to the RDS configuration file used by Dreal.
-
-.SH SEE ALSO
-mbk(1), MBK_CATA_LIB(8), RDS_IN(1), RDS_TECHNO_NAME(1)
-
-.so man1/alc_bug_report.1
-
-
diff --git a/alliance/share/man/man1/druc.1 b/alliance/share/man/man1/druc.1
deleted file mode 100644
index 82109424..00000000
--- a/alliance/share/man/man1/druc.1
+++ /dev/null
@@ -1,519 +0,0 @@
-.\"   $Id: druc.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
-.\" @(#)Labo.l 1.2 93/12/08 UPMC; Author: Patrick RENNAUD
-.pl -.4
-.TH DRUC 1 "October 1, 1997" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
-.SH NAME
-DRuC   - Design Rule Checker
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.TP
-\fBdruc\fP \<\fIroot_name\fP\>
-.br
-.br
-.br
-.br
-.SH DESCRIPTION
-.br
-\fBDRuC\fP is a general parametrized VLSI design rule checker. 
-.br
-This tool replace the \fBVERSATIL\fP tool that is not anymore supported.
-.br
-This manual presents the layout rules for tle \fBALLIANCE\fP symbolic layout approach.
-The rules are described in a technology file defined by the environment variable \fB RDS_TECHNO_NAME\fP (see bellow).
-.br
-The root cell and all the instanciated cells (except the intanciated libraries cells) must be in the current directory.
-.br
-The default mode of \fBDRuC\fP is (currently) full flat: 
-it first flatten all the hierarchy in order to obtain a flat, rectangle level description.
-.br
-.fi
-.ft R
-.bp
-\fBO: LAYER NAME.\fP
-.br
-
-
-
-This section explicits the layer name used in the following rules.
-.br
-.br
-.nf
-.ie t \{\
-.ft CR \}
-.el \{\
-.ft B\}
--  NWELL	: N well
-.br
--  NTIE 	: N well polarisation
-.br
--  PTIE 	: P substrat polarisation
-.br
--  NDIF 	: N diffusion
-.br
--  PDIF 	: P diffusion
-.br
--  GATE 	: transistor gate
-.br
--  POLY 	: polysilicon wire
-.br
--  ALU1 	: first level of metal
-.br
--  ALU2 	: second level of metal
-.br
--  CONT 	: contact between ALU1 and POLY or DIFF
-.br
--  VIA  	: contact between ALU1 and ALU2
-.br
-.fi
-.ft R
-.bp
-\fBI: LAYER WIDTH.\fP
-.br
-
-
-
-
-This class of rules deals with the width limits of a layer.
-and the conditions for equipotentiality between 
-two overlapping or abutting segments.
-.br
-.br
-.nf
-.ie t \{\
-.ft CR \}
-.el \{\
-.ft B\}
-
-rule  1 : 
-	the minimum width for a segment of NWELL is 4
-	corresponding error codes are : 100 101
-.br
-rule 2 :
-	the minimum width for a segment of NTIE  is 2
-	corresponding error code is : 119
-.br
-rule 3 :
-	the minimum width for a segment of PTIE  is 2
-	corresponding error codes are : 122 123
-.br
-rule 4 :
-	the minimum width for a segment of NDIF  is 2
-	corresponding error codes are : 140 141
-.br
-rule 5 :
-	the minimum width for a segment of PDIF  is 2
-	corresponding error codes are : 165 166
-.br
-rule 6 :
-	the minimum width for a segment of GATE  is 1
-	corresponding error codes are : 234 235
-.br
-rule 7 :
-	the minimum width for a segment of POLY  is 1
-	corresponding error codes are : 234 235
-.br
-rule 8 :
-	the minimum width for a segment of ALU1  is 1 
-	corresponding error codes are : 238 239
-.br
-rule 9 :
-	the minimum width for a segment of ALU2  is 2
-	corresponding error codes are : 242 243
-.br
-rule 10 :
-	the width of a CONT must be equal to 1
-	corresponding error codes are : 246 247
-.br
-rule 11 :
-	the width of a VIA must be equal to 1
-	corresponding error codes are : 261 262
-.br
-.fi
-.ft R
-.bp
-\fBII: FORBIDDEN OVERLAP\fP
-.br
-
-
-
-
-This class of rules specifies the forbidden overlaps between two layers. (The distance between them must be strictly positive)
-.br
-.br
-.nf
-.ie t \{\
-.ft CR \}
-.el \{\
-.ft B\}
-.br
-rule 12 :
-	contact between PTIE and NWELL is forbidden.
-	corresponding error codes are : 126 127 128 129 130 131
-.br
-rule 13 :
-	contact between PTIE and NTIE  is forbidden.
-	corresponding error codes are : 133 134 135 136 137 138
-.br
-rule 14 :
-	contact between NDIF and NWELL is forbidden.
-	corresponding error codes are : 144 145 146 147 148 149
-.br
-rule 15 :
-	contact between NDIF and NTIE  is forbidden.
-	corresponding error codes are : 151 152 153 154 155 156
-.br
-rule 16 :
-	contact between NDIF and PTIE  is forbidden.
-	corresponding error codes are : 158 159 160 161 162 163
-.br
-rule 17 :
-	contact between PDIF and NTIE  is forbidden.
-	corresponding error codes are : 169 170 171 172 173 174
-.br
-rule 18 :
-	contact between PDIF and PTIE  is forbidden.
-	corresponding error codes are : 176 177 178 179 180 181
-.br
-rule 19 :
-	contact between PDIF and NDIF  is forbidden.
-	corresponding error codes are : 183 184 185 186 187 188
-.br
-rule 20 :
-	contact between GATE and NTIE  is forbidden.
-	corresponding error codes are : 191 192 193 194 195 196
-.br
-rule 21 :
-	contact between GATE and PTIE  is forbidden.
-	corresponding error codes are : 198 199 200 201 202 203
-.br
-rule 22 :
-	contact between POLY and NTIE  is forbidden.
-	corresponding error codes are : 207 208 209 210 211 212
-.br
-rule 23 :
-	contact between POLY and PTIE  is forbidden.
-	corresponding error codes are : 214 215 216 217 218 219
-.br
-rule 24 :
-	contact between POLY and NDIF  is forbidden.
-	corresponding error codes are : 221 222 223 224 225 226
-.br
-rule 25 :
-	contact between POLY and PDIF  is forbidden.
-	corresponding error codes are : 228 229 230 231 232 233
-.bp
-.br
-rule 26 :
-	contact between CONT and GATE or POLY is forbidden.
-	corresponding error codes are : 249 250 251 252 253
-.br
-rule 27 :
-	contact between VIA and GATE   is forbidden.
-	corresponding error codes are : 264 265 266 267 268 269
-.br
-rule 28 :
-	contact between VIA and POLY   is forbidden.
-	corresponding error codes are : 271 272 273 274 275 276
-.br
-rule 29 :
-	contact between VIA and CONT   is forbidden.
-	corresponding error codes are : 278 279 280 281 282 283
-.br
-rule 30 :
-	contact between NTIE and NWELL is forbidden.
-	corresponding error code is : 109
-.br
-rule 31 :
-	contact between PDIF and NWELL is forbidden.
-	corresponding error code is : 117
-.br
-.fi
-.ft R
-.bp
-\fBIII: LAYER NOTCH.\fP
-.br
-
-
-
-
-This class of rules deals with the notch limits of a layer.
-.br
-.br
-.nf
-.ie t \{\
-.ft CR \}
-.el \{\
-.ft B\}
-.br
-rule 32 : 
-	the minimum notch for a segment of NWELL is 4
-	corresponding error code is : 102
-.br
-rule 33 :
-	the minimum notch for a segment of NTIE  is 2
-	corresponding error code is : 120
-.br
-rule 34 :
-	the minimum notch for a segment of PTIE  is 2
-	corresponding error code is : 124
-.br
-rule 35 :
-	the minimum notch for a segment of NDIF  is 2
-	corresponding error code is : 142
-.br
-rule 36 :
-	the minimum notch for a segment of PDIF  is 2
-	corresponding error code is : 167
-.br
-rule 37 :
-	the minimum notch for a segment of POLY  is 1
-	corresponding error code is : 236
-.br
-rule 38 :
-	the minimum notch for a segment of ALU1  is 2.5 
-	corresponding error code is : 240
-.br
-rule 39 :
-	the minimum notch for a segment of ALU2  is 2
-	corresponding error code is : 244
-.br
-.fi
-.ft R
-.bp
-\fBIV: MINIMUM SPACING\fP
-.br
-
-
-
-
-This class of rules specifies the minimum edge-to-edge distance allowed between
-two layers.
-.br
-.nf
-.ie t \{\
-.ft CR \}
-.el \{\
-.ft B\}
-rule 40 : 
-	the minimum distance between NWELL and NWELL is 12
-	corresponding error code is : 118
-.br
-rule 42 :
-	the minimum distance between NTIE  and NTIE  is 3
-	corresponding error code is : 121
-.br
-rule 43 : 
-	the minimum distance between PTIE  and NWELL is 7.5
-	corresponding error code is : 125
-.br
-rule 44 : 
-	the minimum distance between PTIE  and NTIE  is 8
-	corresponding error code is : 132
-.br
-rule 45 : 
-	the minimum distance between PTIE  and PTIE  is 3
-	corresponding error code is : 139
-.br
-rule 46 : 
-	the minimum distance between NDIF  and NWELL is 7.5
-	corresponding error code is : 143
-.br
-rule 47 :
-	the minimum distance between NDIF  and NTIE  is 8
-	corresponding error code is : 150
-.br
-rule 48 : 
-	the minimum distance between NDIF  and PTIE  is 3
-	corresponding error code is : 157
-.br
-rule 49 : 
-	the minimum distance between NDIF  and NDIF  is 3
-	corresponding error code is : 164
-.br
-rule 51 : 
-	the minimum distance between PDIF  and NTIE  is 3
-	corresponding error code is : 168
-.br
-rule 52 : 
-	the minimum distance between PDIF  and PTIE  is 8
-	corresponding error code is : 175
-.br
-rule 53 : 
-	the minimum distance between PDIF  and NDIF  is 8
-	corresponding error code is : 182
-.br
-rule 54 : 
-	the minimum distance between PDIF  and PDIF  is 3
-	corresponding error code is : 189
-.br
-rule 55 : 
-	the minimum distance between GATE  and NTIE  is 1
-	corresponding error code is : 190
-.br
-rule 56 : 
-	the minimum distance between GATE  and PTIE  is 1
-	corresponding error code is : 197
-.br
-rule 57 : 
-	the minimum distance between GATE  and NDIF  is 1
-	corresponding error code is : 204
-.br
-rule 58 : 
-	the minimum distance between GATE  and PDIF  is 1
-	corresponding error code is : 205
-.br
-rule 59 : 
-	the minimum distance between GATE  and GATE  is 2
-	corresponding error code is : 237
-.br
-rule 60 : 
-	the minimum distance between POLY  and NTIE  is 1
-	corresponding error code is : 206
-.br
-rule 61 : 
-	the minimum distance between POLY  and PTIE  is 1
-	corresponding error code is : 213
-.br
-rule 62 : 
-	the minimum distance between POLY  and NDIF  is 1
-	corresponding error code is : 220
-.br
-rule 63 : 
-	the minimum distance between POLY  and PDIF  is 1
-	corresponding error code is : 227
-.br
-rule 64 : 
-	the minimum distance between POLY  and GATE  is 2
-	corresponding error code is : 237
-.br
-rule 65 : 
-	the minimum distance between POLY  and POLY  is 2
-	corresponding error code is : 237
-.br
-rule 66 : 
-	the minimum distance between ALU1  and ALU1  is 2.5
-	corresponding error code is : 241
-.br
-rule 67 : 
-	the minimum distance between ALU2  and ALU2  is 2
-	corresponding error code is : 245
-.br
-rule 68 : 
-	the minimum distance between CONT  and CONT  is 3
-	corresponding error code is : 254
-.br
-.br
-rule 69 : 
-	the minimum distance between  VIA  and GATE  is 2
-	corresponding error code is : 263
-.br
-rule 70 : 
-	the minimum distance between  VIA  and POLY  is 2
-	corresponding error code is : 270
-.br
-rule 71 : 
-	the minimum distance between  VIA  and CONT  is 2
-	corresponding error code is : 277
-.br
-rule 72 : 
-	the minimum distance between  VIA  and VIA   is 3
-	corresponding error code is : 284
-.br
-rule 73 : 
-        the minimum distance between CONT and GATE or POLY is 1.5
-	corresponding error code is : 248
-.br
-.fi
-.ft R
-.bp
-	\fBV: TOTAL INCLUSION.\fP
-.br
-
-
-
-
-The last class of rules deals with the inclusion of a layer in another one.
-.br
-
-.br
-.nf
-.ie t \{\
-.ft CR \}
-.el \{\
-.ft B\}
-rule 74 : 
-	NTIE must be included in NWELL with a minimun margin of 0.5
-	corresponding error code is : 103
-.br
-rule 75 : 
-	PDIF must be included in NWELL with a minimun margin of 0.5
-	corresponding error code is : 110
-.br
-
-.br
-.fi
-.ft R
-.SH OPTIONS
-.br
-
-
-No optons are currently avalable.
-.br
-
-
-
-.SH FILES
-.br
-
-
-If design errors are found, \fBDRuC\fP produces the list of them in two files :
-
-.br
-.IP
-- \<\fIroot_name.drc\fP\>: 
-.br
-This ascii file contains the list of DRC violations.
-
-.br
-- \<\fIroot_name.iii\fP\>:
-.br
-This \fBgds\fP ro \fBcif\fp file contains only rectangles detected in violation.
-.br
-( suffix iii is defined with the environment )
-.br
-
-\fIRDS_OUT_PH\fP is default setted to gds.
-.br
-
-
-
-.SH ENVIRONMENT VARIABLES
-.br
-
-
-\fBDRuC\fP uses several environment variables:
-.ti 8
-- MBK_IN_PH       - defines the layout input format.
-.br
-.ti 8
-- RDS_OUT_PH       - defines the layout output format.
-.br
-.ti 8
-- RDS_TECHNO_NAME - defines the technology file.
-.br
-.ti 8
-- MBK_CATA_LIB - defines the catalog directory.
-.HP
-See the corresponding manual pages for further informations.
-
-
-
-.SH EXAMPLE
-	druc register
-.br
-
-
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/emulbs.1 b/alliance/share/man/man1/emulbs.1
deleted file mode 100644
index c16442ec..00000000
--- a/alliance/share/man/man1/emulbs.1
+++ /dev/null
@@ -1,118 +0,0 @@
-.\" @(#)PCBS.1 3.1 April 2001 UPMC; Author: DONNET Francois
-.TH EMULBS 1 "February 2002" "Release 3.1" "CAO\-VLSI Reference Manual"
-.SH NAME
-.PP
-\fIPcBs\fP, Emulated Boundary-Scan Tester Platform.
-
-.so man1/alc_origin.1
-
-.SH SYNOPSIS
-.PP
-   \f4emulbs\fP   [ -hvc ]  [ \-l <\fInumber\fP> ]  [ -b <\fInumber\fP> ] [ <\fIsource.PAT\fP> ]
-                [ -e <\fIconnections_file\fP> [ -s <\fIbs.PAT\fP> ] ]
-                [ \-\-pci <\fIres.PAT\fP> | \-\-parallel <\fIres.PAT\fP> ]
-        
-
-.SH DESCRIPTION
-.PP
-\f4emulbs\fP is a tool addressing a Boundary Scan card connected to the PC Printer
-parallel interface or to the pci bus interface. This tool is able to :
-.PP
-\- Automatically check the Boundary\-scan device for Instruction register length, Bypass register length and Boundary\-scan register length, 
-.PP
-\- Execute Boundary\-scan patterns directly to the device,
-.PP
-\- Translate functionnal patterns to Boundary\-scan patterns using an ASCII description of the device Boundary\-scan architecture for the specific emulbs31 card.
-.PP
-
-
-To use this tool, you don't need to have a particular knowledge of Boundary-scan architecture.
-The lpscan driver should be installed if you want to use the parallel port.
-
-.PP
-If it cannot communicate with the device, \f4emulbs\fP will output an error message 
-like :
-.PP
-.nf
-Cannot check INSTRUCTION Register (longer than xxxx bits ???)
-Check the card connection
-.fi
-
-
-
-.SH DEFINITION
-.PP
-We call "\f4Boundary\-scan patterns\fP" patterns written for a device with Boundary\-scan architecture using only the Test Acess Port interface (i.e TDI, TDO, TMS, TCK and eventually TRST).
-.br
-We call "\f4Functionnal patterns\fP" patterns written for a device with Boundary\-
-scan architecture, but using the fonctionnal interface  of the device or for a chip branched with the specific EMULBS31 card which emulated the boundary-scan device(--emulbs option).
-
-.SH OPTION
-
-.TP 10
-\f4\-h,\-\-help\fP
-Help mode. Displays possible uses of \f4emulbs\fP.
-
-.TP 10
-\f4\-v,\-\-verbose\fP
-Verbose mode. Dump executed patterns as \f4asimut\fP.
-
-.TP 10
-\f4\-c,\-\-check\fP
-Check the boundary scan device by sending some patterns. It's able to guess the kind of boundary-scan card is in use (instruction length, bypass length, boundary-scan length).
-
-.TP 10
-\f4\-l,\-\-load\fP <number>
-Do not load all patterns in memory but do it by sequences of <number> patterns.
-Boundary-scan patterns are well known to be huge. It's a way to save memory.
-
-.TP 10
-\f4\-b,\-\-burst\fP <number>
-When you are using a pci bus, you can choose the size in words of your dma burst.
-It's a nonsense to use this option with a parallel port.
-
-.TP 10
-\f4\-e,\-\-emulbs\fP <connections_file>
-<connections_file> describes the device connections between the tested chip and the test card. Functional patterns in <source.PAT> will be serialized in boundary-scan patterns.
-  
-.TP 10
-\f4\-s,\-\-save\fP <connections_file>
-Save the produced boundary-scan patterns in the file <bs.PAT>.
-This option should be used with \f4\-e,\-\-emulbs\fP.
-
-.TP 10
-\f4\--pci\fP <res.PAT>
-To select the pci port where the test card is connected.
-Results of testing <source.PAT> will be saved in the file <res.PAT>.
-
-.TP 10
-\f4\--parallel\fP <res.PAT>
-To select the parallel port where the test card is connected.
-Results of testing <source.PAT> will be saved in the file <res.PAT>.
-
-
-.SH EMULBS CONNECTIONS FILE
-
-.nf
---example for emulbs connexions file 
---left-hand is for EMULBS connector
---right-hand is for CHIP connector 
-                                   
-0    <=in     ck  ;
-185  <=out    y   ;
-56   <=in     i(0);
-76   <=in     i(1);
-80   <=inout  sh  ;
-.fi
-
-.SH SEE ALSO
-.PP
-pat(5), asimut(1)
-
-.so man1/alc_bug_report.1
-
-
-
-
-
-
diff --git a/alliance/share/man/man1/flatbeh.1 b/alliance/share/man/man1/flatbeh.1
deleted file mode 100644
index 49d9d4fe..00000000
--- a/alliance/share/man/man1/flatbeh.1
+++ /dev/null
@@ -1,61 +0,0 @@
-.\" @(#)flatbeh.1 1.0  29 january 1993 UPMC; VUONG Huu Nghia
-.TH FLATBEH 1 "29 january 1993" "Release 1.0" "ALLIANCE USER COMMANDS"
-
-.SH NAME
-.PP
-\fBflatbeh\fP \- Synthetize a behavioral description from a structural description
-
-.SH SYNOPSIS
-.PP
-flatbeh \fIroot_structural_file\fP  [ \fIoutput_file\fP ]
-
-.SH ORIGIN
-This software belongs to the
-.B ALLIANCE
-CAD system from the
-.br
-CAO-VLSI team at MASI laboratory, University P. et M. Curie
-.br
-4, place Jussieu ; 75252 PARIS Cedex 05 ; FRANCE
-.br
-Fax: (33-1) 44.27.62.86 ; E-mail: cao-vlsi@masi.ibp.fr
-
-.SH DESCRIPTION
-.PP
-\fBflatbeh\fP synthetize a VHDL behavioral data-flow description from a
-structural description. It flattens the structural description (it can be
-a hierarchy of macro block) until the cells which have a behavioral
-description. Then it raise all the equations and create a behavioral
-description of the root file.
-
-.SH PARAMETERS
-.PP
-\fBroot_structural_file\fP is the filename of the root of the structural
-description file.
-
-\fBoutput_file\fP is the destination filename for behavioural description.
-
-.SH ENVIRONMENT VARIABLES
-.TP 20
-\fIMBK_CATA_LIB\fP
-list of directories containing descriptions. 
-The default path is the current directory (see mbk(1)).
-.TP 20
-\fIMBK_CATAL_NAME\fP
-Indicates the file where the behavioral description files are given. This serves
-to flatbeh to stop the flatten of the structural root circuit.(see mbk(1))
-.TP 20
-\fIMBK_IN_LO\fP
-file extension for structural entity. (see mbk(1))
-
-.SH EXAMPLE
-.PP
-flatbeh adder_32 
-
-.SH SEE ALSO
-.PP
-vhdl(5), mbk(1).
-
-.SH BUGS
-.PP
-Please e-mail to \fIcao-vlsi@masi.ibp.fr\fP for bug report and suggestions.
diff --git a/alliance/share/man/man1/fmi.1 b/alliance/share/man/man1/fmi.1
deleted file mode 100644
index df7670fd..00000000
--- a/alliance/share/man/man1/fmi.1
+++ /dev/null
@@ -1,49 +0,0 @@
-.TH FSP 1 "October 1, 1997" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
-.SH NAME
-.TP
-fmi    
-\- FSM state miminization
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.TP
-\fBfmi\fP [\fI-V\fP] \fIinput_file\fP  \fIoutput_file\fP
-.br
-.SH DESCRIPTION
-.br
-Made to run on FSM descriptions, \fBfmi\fP supports the same subset of VHDL as syf 
-(for further informations about this subset see SYF(1) and FSM(5)).
-\fBfmi\fP uses a Reduced Ordered Binary Decision Diagrams representation and 
-identifies equivalent states.
-After this step, it drives a new FSM where all equivalent states are replaced
-by a single state.
-.br
-As a restriction \fBfmi\fP doesn't handle don't cares (as this much more
-difficult).
-
-.SH ENVIRONMENT VARIABLES
-.br
-.HP
-.ti 7
-\fIMBK_WORK_LIB\fP gives the path of the FSM description.
-The default value is the current directory.
-.br
-.HP
-.ti 7
-\fIMBK_CATA_LIB\fP gives some auxiliary pathes for the FSM descriptions.
-The default value is the current directory.
-.SH OPTIONS
-.ti 7
-\-V
-Sets verbose mode on. Each step of the minimization is displayed on the
-standard output.
-.br
-.SH EXAMPLE
-.br
-	fmi digi digi_min
-
-.SH SEE ALSO
-.br
- \fBsyf\fP (1), \fBfsp\fP (1), \fBfsm\fP (5), \fBxfsm\fP (1).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/fpgen.1 b/alliance/share/man/man1/fpgen.1
deleted file mode 100644
index a77892e1..00000000
--- a/alliance/share/man/man1/fpgen.1
+++ /dev/null
@@ -1,269 +0,0 @@
-.\"   $Id: fpgen.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
-.TH FPGEN 1 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBfpgen\fP - Procedural language for Data-Path synthesis based upon C.
-.SH SYNOPSIS
-.ft  B
-fpgen [--no-exec] [--keep-exec] [-v] <\fISourceFile\fP> [-e <\fIArgs\fP>]
-.ft  R
-.SH DESCRIPTION
-.ta 4n
-	\fBfpgen\fP is a set of \fBC\fP functions dedicated to \fIdata-path\fP
-synthesis. It provide a large set of vectorized operators, in the
-following, the \fBC\fP functions which generates such \fIdata-path\fP
-components are called \fIMacro-functions\fP. \fBfpgen\fP create a
-hierarchical \fINetList\fP that can be given to the \fIdata-path\fP place
-and route tool \fBdpr(1)\fP.
-.br
-.SH MISCELLANEOUS FUNCTIONS
-.ta  19n
-.in +19n
-.ti -19n
-\fBDP_DEFLOFIG()\fR	Open a new logical figure and set \fBdata-path\fR
-context to its default configuration.
-.ti -19n
-\fBDP_SAVLOFIG()\fR	Close and save on disk the current logical figure.
-.ti -19n
-\fBDP_TRACE()\fP	Enable/disable trace mode.
-.ti -19n
-\fBDP_LOCON()\fR	Define a connector.
-.ti -19n
-\fBDP_IMPORT()\fP	Instanciate a data-path compatible component.
-.in -19n
-.SH MACRO-FUNCTIONS
-.ta 4n 
-	The behavior of all the \fBmacro-functions\fP can be described by
-the four following steps :
-
-.ta +6n
-\fBI)\fP	Reading arguments and performing some checks.
-.br
-
-\fBII)\fP	Looking for a previously generated model with the same
-set of parameters as actually required, in an internal table.
-If the model has already been generated, jump to step \fBIV)\fP.
-.br
-
-\fBIII)\fP	At this point, the model is created by a call
-to the generator associated to this \fBmacro-function\fP. Then the
-new model is stored in the internal table.
-.br
-	Notice that the model name is not accessible by the
-designer. The \fBmacro-function\fP encode the parameters and the
-context in order to build this name.
-.br
-
-\fBIV)\fP	A new instance of the model is added to the current
-working figure.
-.br
-	As in \fBGENLIB(1)\fP each of the signals given
-as arguments are connected to an instance connector. The 
-connectors are implicitly matched from the order of the signal
-on the list. The supply connectors are automatically added
-by the \fBmacro-function\fP, thus they have not to appear in the
-call.
-.br
-
-	In all the macro-function descriptions, it is shown that
-connectors have two different types. The \fIData\fR (noted \fBDATA\fP) and the
-\fIControl\fR (noted \fBCTRL\fP) types. 
-.br
-.ta  2n +9n +2n
-.in +13n
-.ti -13n
--	\fBDATA\fP	:	Corresponds to a virtual connector used in horizontal
-connections in \fIfplib\fP cells to interconnect \fBdata\fR signals.
-.ti -13n
--	\fBCTRL\fP	:	Corresponds to a North or South connector generally used to
-introduce vertical \fBcontrol\fR signals in \fIfplib\fP cells.
-.ta 4n
-.in -13n
-
-All the \fBC\fP macro-function calls have the followings common arguments :
-.br
-.ta   2n +9n +2n
-.in +13n
-.ti -13n
--	\fIInstName\fP	:	Name of the new instance in the operator.
-.br
-.ti -13n
--	\fIWidth\fP	:	Width of the operator bus, in bits.
-.br
-.ti -13n
--	\fISlice\fP	:	Bottom slice of the operator(i.e. the slice where the LSB will be set).
-.br
-	All view of the \fBMacro-Function\fP are stored in the directory given
-by the \fBFPGEN_LIB\fP environement variable. The associated \fBCATAL\fP
-file is automatically updated
-.SS MODEL NAMES
-.ta +4n +8m
-	\fBfpgen\fP generate itself the operator model names and give them
-special meanings. So, designers must avoid to use same names. The
-reserved names are listed below (using regular expression syntax) :
-.br
-
-		\fB[a-z0-9]*_[0-9x]*[lm]_cl\fP
-.br
-		\fB[a-z0-9]*_[0-9x]*[lm]_bk\fP
-.br
-
-	At the opposite, when the designer wants to create a custom operator,
-with \fBGenLib\fP or logical synthetizer \fBscmap(1)\fP he must gave to
-his operator model name the suffix \fB"_us"\fP.
-.SS AVALAIBLE MACRO-FUNCTIONS
-.ta +21n
-.in +21n
-.ti -21n
-Booleans:
-.ti -21n 
-\fBDP_INV()\fR	Inverter.
-.ti -21n 
-\fBDP_BUFF()\fR	Buffer.
-.ti -21n 
-\fBDP_AND2()\fR	Logical \fBand\fR, two inputs.
-.ti -21n 
-\fBDP_NAND2()\fR	Logical \fBand\fR, two inputs, complemented output.
-.ti -21n 
-\fBDP_AND3()\fR	Logical \fBand\fR, three inputs.
-.ti -21n 
-\fBDP_NAND3()\fR	Logical \fBand\fR, three inputs, complemented output.
-.ti -21n 
-\fBDP_OR2()\fR	Logical \fBor\fR, two inputs.
-.ti -21n 
-\fBDP_NOR2()\fR	Logical \fBor\fR, two inputs, complemented output.
-.ti -21n 
-\fBDP_OR3()\fR	Logical \fBor\fR, three inputs.
-.ti -21n 
-\fBDP_NOR3()\fR	Logical \fBor\fR, three inputs, complemented output.
-.ti -21n 
-\fBDP_XOR2()\fR	Logical \fBexclusive or\fR, two inputs.
-.ti -21n 
-\fBDP_XNOR2()\fR	Logical \fBexclusive or\fR, two inputs, complemented output.
-
-.ti -21n
-Masks :
-.ti -21n
-\fBDP_NAND2MASK()\fR	Logical \fBand\fR mask, complemented output.
-.ti -21n
-\fBDP_NOR2MASK()\fR	Logical \fBor\fR mask, complemented output.
-.ti -21n
-\fBDP_XNOR2MASK()\fR	Logical \fBexclusive or\fR mask, complemented output.
-
-.ti -21n
-Multiplexers :
-.ti -21n 
-\fBDP_NMUX2CS()\fR	Multiplexer, 2 inputs, complemented output.
-.ti -21n 
-\fBDP_MUX2CS()\fR	Multiplexer, 2 inputs.
-.ti -21n 
-\fBDP_MUX3Cs()\fR	Multiplexer, 3 inputs.
-.ti -21n 
-\fBDP_MUX4Cs()\fR	Multiplexer, 4 inputs.
-.ti -21n 
-\fBDP_MUX5Cs()\fR	Multiplexer, 5 inputs.
-.\".ti -21n 
-.ti -21n
-\fBDP_NBUSE()\fR	Tristate, complemented output.
-.ti -21n
-\fBDP_BUSE()\fR	Tristate.
-
-.ti -21n
-Arithmetic:
-.ti -21n
-\fBDP_ADD2F\fR	fast adder, two operands.
-.ti -21n
-\fBDP_ADSB2F()\fR	Controlable adder substractor, 2 operands (need \fBrsa\fP
-dedicated leaf cell library).
-.ti -21n
-\fBDP_SHIFT()\fR	Barrel shifter (need \fBbsg\fP dedicated leaf cells
-library).
-.ti -21n
-\fBDP_MULT()\fR	Unpipelined array multiplier (need \fBamg\fP
-dedicated leaf cell library).
-.ti -21n
-\fBDP_MULTP()\fR	Pipelined array multiplier (need \fBamg\fP
-dedicated leaf cell library).
-
-.ti -21n
-Miscellaneous:
-.ti -21n
-\fBDP_NUL()\fR	Zero detect.
-.ti -21n
-\fBDP_CONST()\fR	Constant generator.
-
-.bp
-.ti -21n
-Registers:
-.ti -21n
-\fBDP_PDFF()\fR	D flip-flop with write enable.
-.ti -21n
-\fBDP_PDFFR()\fR	D flip-flop with write enable and reset.
-.ti -21n
-\fBDP_PDFFT()\fR	D flip-flop with write enable and scan.
-.ti -21n
-\fBDP_PDFFRT()\fR	D flip-flop with write enable, scan and reset.
-.ti -21n
-\fBDP_RGF1CC()\fR	D Register file, one read bus.
-.ti -21n
-\fBDP_RGF1C0()\fR	D Register file, one read bus, \fBR0 <= 0\fP.
-.ti -21n
-\fBDP_RGF2CC()\fR	D Register file, two read bus.
-.ti -21n
-\fBDP_RGF2C0()\fR	D Register file, two read bus, \fBR0 <= 0\fP.
-.br
-(need \fBrfg\fP dedicated leaf cells
-library).
-.SH OPTIONS
-.in +12n
-.ta +12n
-.ti -12n
-\fB-v\fP	Verbose mode. \fBfpgen\fP will show one message per processing
-step.
-
-.ti -12n
-\fB--keep-exec\fP	Do not erase the executable after run.
-
-.ti -12n
-\fB--no-exec\fP	Skip the execution step.
-
-.ti -12n
-\fISourceFile\fP	Name of the file containing the \fBfpgen\fP specific
-\fBC\fP source progam.
-
-.ti -12n
-\fB-e <\fIArgs\fB>\fR	All arguments following \fB-e\fP are passed to the executable.
-.in -12n
-.SH ENVIRONMENT VARIABLES
-.ta +20n
-.in +20n
-.ti -20n
-\fBMBK_CATA_LIB\fP	Contain the list of directories path holding the
-leaf cells libraries. All \fImacro-funcions\fP uses the \fBfplib(5)\fP
-library, and a few others need additionnal one.
-.br
-.ti -20n
-\fBFPGEN_LIB\fP	The path were \fBFpGen\fP will store all the generated
-models, and their associated \fBCATAL\fP. If not set \fBMBK_WORK_LIB\fP
-will be used. Notice that this library path must also be part of the
-\fBMBK_CATA_LIB\fP list.
-.br
-.SH SEE ALSO
-.ft B
-genlib(1)
-,
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/fpmap.1 b/alliance/share/man/man1/fpmap.1
deleted file mode 100644
index f6b47c02..00000000
--- a/alliance/share/man/man1/fpmap.1
+++ /dev/null
@@ -1,86 +0,0 @@
-.\"   $Id: fpmap.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
-.pl -.4
-.TH FPMAP 1 "October 1, 1997" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
-.SH NAME
-.TP
-fpmap
-\- fpga mapper of a logic level behavioural description (VHDL data flow)
-
-.so man1/alc_origin.1
-
-.SH SYNOPSIS
-.TP
-\fBfpmap\fP \fI-Tarchi\fP [\fIoptions\fP]  \fIdata_flow_file\fP \fIoutput_file\fP  [\fIparameter_file\fP]
-.br
-
-.SH DESCRIPTION
-.br
-
-.br
-\fB  Input description\fP
-.br
-
-.br
-The logic level behavioural description (.vbe file) uses the same VHDL subset as the logic simulator \fBasimut\fP, the FSM synthesizer \fBsyf\fP, the functional abstractor \fByagle\fP and the formal prover \fBproof\fP (for further information about the subset of VHDL, see the "vbe" manual). 
-.br
-A special feature has been introduced in the VHDL subset in order to allow the don't care description for external outputs and internal registers : A bit signal can take the 'd' value. 
-This value is interpreted as a '0' by the logic simulator \fBasimut\fP. 
-Don't Cares are automatically generated by \fBsyf\fP in the resulting '.vbe' file.
-.br
-For the register signal, only one signal can appear in a guarded expression. Since most of the fpga devices have a separate \fBwrite enable\fP input on their registers, it can be used in the description using a \fBwhen .. else\fP statement (reg <= input when write_enable else reg;). 
-.br
-
-.br
-\fB  Parameter file '.lax'\fP
-.br
-The parameter file is common with other logic synthesis tools and is used
-for driving the synthesis process. 
-See \fBlax\fP(5) manual for more detail.
-
-.SH ENVIRONMENT VARIABLES
-.br
-The following environment variables have to be set before using \fBfpmap\fP :
-.HP
-.ti 7
-\fIMBK_WORK_LIB\fP gives the path of the directory of both input and output files (behavioural, structural and parameters description).
-.HP
-.ti 7
-\fIMBK_OUT_LO\fP gives the output format of the structural description.
-
-.SH OPTIONS
-.br
-.HP
-.ti 7
-\-O[0-5] defines the level of optimization. O0 means no optimisation at all, O5 is the highest degree of optimization. If the level of optimization is set both in the \fB.lax\fP parameter file and on the command line, the latter is keeped.
-.HP
-.ti 7
-\-M[0-5] defines the area/delay trade-off. M0 optimize only for area, while M5 optimize only for delay. If the area/delay trade-offis set both in the \fB.lax\fP parameter file and on the command line, the latter is keeped.
-.HP
-.ti 7
-\-f flatten the description before the optimization. All auxiliary signals are erased unless they are in the list of saved auxiliary in the \fB.lax\fP parameter file.
-.HP
-.ti 7
-\-a run the abl ordonnancer before building the bdd. Most of the time this option give a better solution, and is not very time consuming.
-.HP
-.ti 7
-\-i (Xilinx 4000 only) generate iobs in the generated \fB.xnf\fP netlist.
-.HP
-.ti 7
-\-n (Xilinx 4000 only) do not generate iobs in the generated \fB.xnf\fP netlist.
-
-
-.SH EXAMPLE
-.br
-You can call \fBfpmap\fP as follows :
-.br
-.br
-	fpmap -TX4000 -afn sequncer
-
-.SH SEE ALSO
-.br
-proof(1), yagle(1), asimut(1), vhdl(5).
-.br
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/fsm.1 b/alliance/share/man/man1/fsm.1
deleted file mode 100644
index 1a8c143b..00000000
--- a/alliance/share/man/man1/fsm.1
+++ /dev/null
@@ -1,50 +0,0 @@
-.\"   $Id: fsm.1,v 1.1 2000/05/05 11:21:51 syf Exp $
-.\" @(#)fsm.1 1.01 96/02/07 UPMC; Fsmhor : Jacomme Ludovic
-.TH FSM101 1 "October 1, 1997" "ASIM/LIP6" "ALLIANCE FSM LIBRARY"
-.SH NAME
-fsm \- Finite State Machine representation. 
-.so man1/alc_origin.1
-.SH DESCRIPTION
-\fBfsm\fP is a library that enables to represent finite state machine.
-
-.TP
-Types :
-.TP 20
-.br
-\fBfsmin_list\fP
-\- inputs of a FSM.
-.TP
-\fBfsmout_list\fP
-\- outputs of a FSM.
-.TP
-\fBfsmport_list\fP
-\- ports of a FSM.
-.TP
-\fBfsmlocout_list\fP
-\- state output assign.
-.TP
-\fBfsmtrans_list\fP
-\- transition of a FSM.
-.TP
-\fBfsmstate_list\fP
-\- state of a FSM.
-.TP
-\fBfsmstack_list\fP
-\- stack of a FSM.
-.TP
-\fBfsmfig_list\fP
-\- FSM figure.
-
-.TP
-Functions :
-.TP 20
-.br
-
-...
-
-.TP 0
-libFsm101.a :
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/fsp.1 b/alliance/share/man/man1/fsp.1
deleted file mode 100644
index f7dcf93a..00000000
--- a/alliance/share/man/man1/fsp.1
+++ /dev/null
@@ -1,47 +0,0 @@
-.TH FSP 1 "October 1, 1997" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
-.SH NAME
-.TP
-fsp    
-\- Formal proof between two FSM descriptions
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.TP
-\fBfsp\fP [\fI-V\fP] \fIformat1\fP \fIformat2\fP \fIfile1\fP  \fIfile2\fP
-.br
-.SH DESCRIPTION
-.br
-Made to run on FSM descriptions, \fBfsp\fP supports the same subset of VHDL as syf 
-(for further informations about this subset see SYF(1) and FSM(5)).
-\fBfsp\fP uses a Reduced Ordered Binary Decision Diagrams representation and 
-computes the product of the two FSM descriptions.
-After this step, it explores the resulting FSM product and proves formally the equivalence
-between the two initial FSM descriptions. 
-Those two descriptions must have the same interface (VHDL entity).
-
-.SH ENVIRONMENT VARIABLES
-.br
-.HP
-.ti 7
-\fIMBK_WORK_LIB\fP gives the path for the FSM descriptions.
-The default value is the current directory.
-.br
-.HP
-.ti 7
-\fIMBK_CATA_LIB\fP gives some auxiliary pathes for the FSM descriptions.
-The default value is the current directory.
-.SH OPTIONS
-.ti 7
-\-V
-Sets verbose mode on. Each step of the formal proof is displayed on the
-standard output.
-.br
-.SH EXAMPLE
-.br
-	fsp fsm fsm digi digi2
-
-.SH SEE ALSO
-.br
- \fBsyf\fP (1), \fBfmi\fP (1), \fBfsm\fP (5), \fBxfsm\fP (1).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/genbs.1 b/alliance/share/man/man1/genbs.1
deleted file mode 100644
index fd97186c..00000000
--- a/alliance/share/man/man1/genbs.1
+++ /dev/null
@@ -1,405 +0,0 @@
-.\"   $Id: genbs.1,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)Labo.l 1.0 96/01/02 UPMC; Author: Olivier FLORENT
-.pl -.4
-.TH GENBS 1 "October 1, 1997" "ASIM/LIP6" "ALLIANCE USER COMMANDS"
-.SH NAME
-.TP
-genbs - A IEEE 1149.1 Boundary\-Scan Architecture Generator
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.TP
-\fBgenbs\fP \fI<expert options>\fP \fI<user options>\fP \fI<chip_name>\fP \fI<core_name>\fP
-.br
-.SH DESCRIPTION
-\fBgenbs\fP is an automatic Boundary\-Scan Architecture generator,
-according to IEEE 1149.1-1990 standard, also known as JTAG. It looks
-for a chip hierarchical description (\fI<chip_name>\fP) containing
-pads and a core called \fI<core_name>\fP, and generates a new
-hierarchical chip description containing the core, the pads and all
-the Boundary\-Scan circuitry.  \fI<expert options>\fP describes the
-target pads and defines the mode of generation (structural or
-behavioural blocks).  \fI<user options>\fP defines Boundary\-Scan
-specific options. If no \fI<user options>\fP are provided, a minimal
-but fully compliant Boundary\-Scan Architecture is generated.
-
-.SH INPUT FILES
-.TP 10
-\fI<chip_name>.vst\fP 
-The hierarchical netlist describing the chip.
-It must only contain pads and a core netlist.  
-File format (here \fI.vst\fP) can be changed using MBK\_IN\_LO 
-environment variable.
-
-.TP 10
-\fI<core_name>.vst\fP 
-The hierarchical netlist describing the core.
-File format (here \fI.vst\fP) can be changed using MBK\_IN\_LO
-environment variable.
-
-.TP 10
-\fI<chip_name>.rin\fP
-A file describing the pad order in the pad
-ring. This is the same file as used by the pad router
-\fIring\fP.  See \fIring(1)\fP for more info on this file format.
-This file is used by \fBgenbs\fP to know how to chain the pads in the
-boundary\-scan register.
-
-.SH EXPERT OPTIONS
-Theses options describes the pad library and the mode of generation.
-Usually theses options are defined once for every pad library and are
-provided by the program maintainer.
-
-.TP 10
-\fI-padin <name> <in> <out> <inv>\fP 
-This option describes an input
-pad model called \fI<name>\fP. Its input connector is called
-\fI<in>\fP, its output connector is called \fI<out>\fP. If
-\fI<inv>\fP is '0' then there is an inversion beetween \fI<in>\fP and
-\fI<out>\fP.  For example :
-.br
-	    -padin pi_sp pad t 1
-.br
-describes a non inverting input pad model called \fIpi_sp\fP.
-
-.TP 10
-\fI-padout <name> <in> <out> <inv>\fP 
-This option describes an output
-pad model called \fI<name>\fP. Its input connector is called
-\fI<in>\fP, its output connector is called \fI<out>\fP. If
-\fI<inv>\fP is '0' then there is an inversion beetween \fI<in>\fP and
-\fI<out>\fP.  For example :
-.br
-	    -padout po_sp t pad 1
-.br
-describes a non inverting output pad model called \fIpo_sp\fP.
-
-.TP 10
-\fI-padtri <name> <in> <out> <inv> <enable> <pol>\fP 
-This option
-describes an output tristate pad model called \fI<name>\fP. Its input
-connector is called \fI<in>\fP, its output connector is called
-\fI<out>\fP. If \fI<inv>\fP is '0' then there is an inversion
-beetween \fI<in>\fP and \fI<out>\fP. Its output enable connector is
-called \fI<enable>\fP. If this output enable connector is active low,
-then \fI<pol>\fP must be '0', else '1'. For example :
-.br
-	    -padtri pot_sp i pad 1 b 1
-.br
-describes a non inverting output tristate pad model called
-\fIpot_sp\fP with its output enable connector \fIb\fP active high.
-
-.TP 10
-\fI-padbidir\fP \fI<name>\fP \fI<dtin>\fP \fI<dtout>\fP \fI<invi>\fP \fI<out>\fP
-\fI<invo>\fP \fI<enable>\fP \fI<pol>\fP
-
-This option describes an output bidirectionnal pad model
-called \fI<name>\fP. Its internal input data connector is called
-\fI<dtin>\fP, its internal output data connector is called
-\fI<dtout>\fP, and its external bidirectionnal output connector is
-called \fI<out>\fP. If \fI<invi>\fP is '0' then there is an inversion
-beetween the internal data connector \fI<dtin>\fP and the external
-bidirectionnal output connector \fI<out>\fP.  If \fI<invo>\fP is '0'
-then there is an inversion beetween the internal data connector
-\fI<dtout>\fP and the external bidirectionnal output connector
-\fI<out>\fP.  Its output enable connector is called \fI<enable>\fP.
-If this output enable connector is active low then \fI<pol>\fP must
-be '0', else '1'. For example :
-.br
-	    -padbidir piot_sp i t 1 pad 1 b 1
-.br
-describes a non inverting output bidirectionnal pad model called
-\fIpiot_sp\fP with its output enable connector \fIb\fP active high.
-
-.TP 10
-\fB-pad\fP | \fB-core\fP
-With \fI-pad\fP option, boundary-scan cells
-are generated in the core of the chip. This is used for \fBPAD
-LIMITED\fP chips. With \fI-core\fP option, boundary-scan cells are
-located in the pad. This is used for \fBCORE LIMITED\fP chips. If
-this option is active the pad library must be specific to
-Boundary-scan Architecture.  \fI-core\fP option is not currently
-implemented.
-
-.TP 10
-\fB-sclib\fP 
-If this option is active, the generated blocks are
-automatically mapped on SCLIB, The ALLIANCE CAD SYSTEM standard cell
-library. See \fBsclib(1)\fP for more info on this standard cell
-library. By default, the generated blocks are described using a VHDL
-Behavioural description. See \fBvhdl(5)\fP for more info on ALLIANCE
-CAD SYSTEM VHDL subset.
-
-.SH USER OPTIONS
-Theses options are used to add specific parameters to the generated
-boundary-scan architecture and to rename output files. If no \fI<user
-options>\fP are provided, a minimal full compliant IEEE 1149.1 chip
-is generated including a 2 bits instruction register, a
-boundary\-scan register, and a bypass register, and with the three
-mandatory instruction \fBEXTEST\fP, \fBBYPASS\fP and \fBSAMPLE\fP, as
-specified by the standard.
-
-.TP 10
-\fI-bypass <inst>\fP 
-Specify the binary code \fI<inst>\fP of the
-mandatory instruction \fBBYPASS\fP. Standard requires that
-\fBBYPASS\fP binary instruction code must be all '1'.
-
-.TP 10
-\fI-extest    <inst>\fP 
-Specify the binary code \fI<inst>\fP of the
-mandatory instruction \fBEXTEST\fP. Standard requires that
-\fBEXTEST\fP binary instruction code must be all '0'.
-
-.TP 10
-\fI-sample    <inst>\fP 
-Specify the binary code \fI<inst>\fP of the
-mandatory instruction \fBSAMPLE\fP.
-
-.TP 10
-\fI-intest    <inst>\fP 
-Specify the binary code \fI<inst>\fP of the
-optional instruction \fBINTEST\fP.
-
-.TP 10
-\fI-idcode    <inst> <code>\fP 
-Specify the binary code \fI<inst>\fP
-of the optional instruction \fBIDCODE\fP, and specify the 32 bit
-hexadecimal Identification code \fI<code>\fP.
-
-.TP 10
-\fI-usercode  <inst> <code>\fP
-Specify the binary code \fI<inst>\fP
-of the optional instruction \fBUSERCODE\fP, and specify the 32 bit
-hexadecimal User Identification code \fI<code>\fP.
-
-.TP 10
-\fI-hiz       <inst>\fP 
-Specify the binary code \fI<inst>\fP of the
-optional instruction \fBHIZ\fP. This option is not yet implemented.
-
-.TP 10
-\fI-clamp     <inst>\fP 
-Specify the binary code \fI<inst>\fP of the
-optional instruction \fBCLAMP\fP. This option is not yet
-implemented.
-
-.TP 10
-\fI-runbist   <inst>\fP 
-Specify the binary code \fI<inst>\fP of the
-optional instruction \fBRUNBIST\fP. This option is not yet
-implemented.
-
-.TP 10
-\fI-nock\fP 
-This options tells \fBgenbs\fP to not include the clock
-connector in the boundary-scan register. This is mandatory when using
-a special clock tree distribution.
-
-.TP 10
-\fI-trst\fP
-This options tells \fBgenbs\fP to include the optional reset pin \fBTRST\fP
-in the boundary-scan circuitry.
-
-.TP 10
-\fI-prefix <prefix>\fP
-Prefixs all the output files with
-\fI<prefix>\fP. Default prefix is \fIbs_\fP
-
-.TP 10
-\fI-out <out_chip_name>\fP
-The new chip will be called \fI<out_chip_name>\fP instead of
-\fIbs_<chip_name>\fP
-
-.TP 10
-\fI-overwrite\fP 
-Force writing of files even if they already exist on
-disk.
-
-.TP 10
-\fI-catal <output_catal_name>\fP
-Specify the name of the output catal
-when VHDL behavioural files are generated. The default name is
-\fIbs_CATAL\fP.
-
-.TP 10
-\fI-scanpath  <inst>\fP 
-Specify the binary code \fI<inst>\fP of the
-private instruction \fBSCANPATH\fP. This instruction allows a single
-scan-path to be connected between \fITDI\fP and \fITDO\fP. This is a
-private instruction and may not be fully compliant with the standard.
-This option requires \fI-scin\fP, \fI-scout\fP, \fI-test\fP,
-\fI-ckscan\fP and \fI-splength\fP options to be supplied.
-
-.TP 10
-\fI-scin   <pin_name> \fP 
-Specify the name \fI<pin_name>\fP of the
-chip scan-path input connector. This pin will be replaced by the
-\fITDI\fP input in the new chip.
-
-.TP 10
-\fI-scout  <pin_name> \fP 
-Specify the name \fI<pin_name>\fP of the
-chip scan-path output connector. This pin will be replaced by the
-\fITDO\fP output in the new chip.
-
-.TP 10
-\fI-test   <pin_name> <pol> \fP 
-Specify the name \fI<pin_name>\fP of
-the chip scan-path test-mode connector. This pin will be replaced by
-the \fITMS\fP input in the new chip. If the scan-path test-mode
-connector is active high, \fI<pol>\fP must be '1', else '0'.
-
-.TP 10
-\fI-ckscan <pin_name> <pol>\fP 
-Specify the name \fI<pin_name>\fP of
-the chip scan-path clock connector. If this clock is a rising edge
-clock, then \fI<pol>\fP must be '1'. If this clock is a falling edge
-clock, then \fI<pol>\fP must be '0'.
-
-.TP 10
-\fI-splength <n> \fP
-Specify the scan-path length in bits. This will
-be used to generate verification patterns for the private instruction
-\fBSCANPATH\fP. (see OUTPUT FILES section).
-
-.SH OUTPUT FILES
-
-\fBgenbs\fP produces several files : basic boundary-scan blocks
-description, new netlists, patterns and info files.
-
-1/ Output basic boundary-scan blocks description
-
-The basics boundary-scan blocks can be obtained in two ways : with
-\fB-sclib\fP option, you will obtain structural files mapped on
-\fBsclib\fP standard cell library (currently \fBsclib version
-5.2\fP. Output netlist file format will be determinated by
-\fBMBK\_OUT\_LO\fP environment variable. With no \fB-sclib\fP option,
-you will obtain VHDL behavioural files.
-All the file names are prefixed with the default prefix (see \fB-prefix\fP
-option). The basics boundary-scan blocks generated are :
-
-.TP 10
-\fBbs_in\fP
-One bit input Boundary-scan cell
-
-.TP 10
-\fBbs_out\fP
-One bit output Boundary-scan cell
-
-.TP 10
-\fBbs_trim\fP
-One bit tristate master Boundary-scan cell. A master tristate Boundary-scan cell
-contains 2 outputs : one for data and one for output enable.
-
-.TP 10
-\fBbs_tris\fP
-One bit tristate slave Boundary-scan cell. A slave tristate Boundary-scan cell
-contains only one output data. Output enable is provided by a master 
-Boundary-scan cell.
-
-.TP 10
-\fBbs_bidm\fP
-One bit bidir master Boundary-scan cell. A master bidir Boundary-scan cell
-contains 3 outputs : one for data-in, one for data-out and one for
-output enable.
-
-.TP 10
-\fBbs_bids\fP
-One bit bidir slave Boundary-scan cell. A slave bidir Boundary-scan cell
-contains only 2 outputs : one for data-in and one for data-out.
-Output enable is provided by a master Boundary-scan cell.
-
-.TP 10 
-\fBbs_tap\fP
-Tap Controller state machine
-
-.TP 10 
-\fBbs_idec\fP
-Instruction decoder
-
-.TP 10 
-\fBbs_bypass\fP
-One bit bypass register
-
-.TP 10 
-\fBbs_rinst\fP
-Instruction register. Instruction register length depends on the number of 
-instruction implemented.
-
-.TP 10
-\fBbs_muxd\fP
-Data register mux. It is a (n ==> 1) mux fed by the (n) data registers.
-
-.TP 10 
-\fBbs_muxtdo\fP
-TDO output mux. Is is a (2 ==> 1) mux fed by the instruction register and
-the output of the Data register mux.
-
-.TP 10
-\fBbs_idcd\fP and \fBbs_usercd\fP
-32 bits Identification and User code register. They are generated only if
-\fB-usercode\fP and \fB-idcode\fP options are choosen.
-
-.PP
-2/ Output netlists.
-.br
-Three netlists are always generated :
-
-.TP 10
-\fIbs_bsreg.vst\fI
-The boundary-scan register.
-
-.TP 10
-\fIbs_<core_name>\fP
-The new core netlist. This is a hierarchical netlist containing the
-original core and all the boundary-scan circuitry.
-
-.TP 10
-\fIbs_<chip_name>\fP
-The new chip netlists. This is a hierarchical netlists containing 
-the new core and the pads. The new chip name can be changed using the
-\fB-out\fP option. 4 new connectors are added to the chip interface :
-\fBTMS, TCK, TDI and TDO\fP (and \fBTRST\fP if \fI-trst\fP option is
-choosen).
-
-
-.PP
-3/ Miscellaneous files
-.br
-Pattern and info files are also generated :
-
-.TP 10
-\fIbs_<chip_name>_pat.c\fP
-This is a genpat file (see \fBgenpat(1)\fP) containing high-level functions
-to write boundary-scan patterns for the new chip.
-
-.TP 10
-\fIbs_<chip_name>.info\fP
-This is a text file containing info about the new chip : the instruction
-implemented and their codes, the name of the new blocks, informations
-about the chip interface and the boundary-scan register description.
-
-.SH EXAMPLES
-
-Let assume that \fI<expert_options>\fP have been provided by the tool
-maintainer.
-.br
-
-> genbs amd heart
-.br
-
-will generate a minimal full compliant boundary-scan chip named \fBbs_amd\fP
-with the three mandatory instruction \fBEXTEST\fP,\fBBYPASS\fP and \fBSAMPLE\fP.
-
-.SH SEE ALSO
-MBK_IN_LO(8) 
-MBK_OUT_LO(8) 
-vbe(5) 
-vhdl(5) 
-genpat(1) 
-sclib(5).
-
-
-.so man1/alc_bug_report.1
-
-
diff --git a/alliance/share/man/man1/genlib.1 b/alliance/share/man/man1/genlib.1
deleted file mode 100644
index 99c7e66b..00000000
--- a/alliance/share/man/man1/genlib.1
+++ /dev/null
@@ -1,231 +0,0 @@
-.\"   $Id: genlib.1,v 1.2 2000/09/28 16:27:58 francois Exp $
-.\" @(#)Labo.l 0.0 90/22/08 UPMC; Author: Frederic Petrot
-.TH GENLIB 1 "October 1, 1997" "ASIM/LIP6" "ALLIANCE USER COMMANDS"
-.SH NAME
-genlib \- Procedural design language based upon C, along with its
-compiler 
-.so man1/alc_origin.1
-.SH DESCRIPTION
-\fBgenlib\fP is a set of \fIC\fP functions dedicated to procedural generation
-purposes.
-From a user point of view, \fBgenlib\fP is a circuit's description language
-that allows standard \fIC\fP programming flow control, variable use, and 
-specialized functions in order to handle vlsi objects.
-.br
-Based upon the \fIAlliance\fP \fBmbk\fP data structures, the \fBgenlib\fP
-language gives the user the ability to describe both netlist and
-layout views, thus allowing both standard cell and full custom approachs.
-.br
-.TP 20
-Netlist capture :
-\- it is a hierachical structural description of
-a circuit in terms of connectors (I/Os), signals (nets), and instances.
-.br
-The function calls used to handle the netlist view are
-.RS
-	GENLIB_DEF_LOFIG(3)
-.br
-	GENLIB_SAVE_LOFIG(3)
-.br
-	GENLIB_LOINS(3)
-.br
-	GENLIB_LOCON(3)
-.br
-	GENLIB_LOSIG(3)
-.br
-	GENLIB_FLATTEN_LOFIG(3)
-.br
-Some facilities, in order to create vectors are also available :
-.br
-	GENLIB_BUS(3)
-.br
-	GENLIB_ELM(3)
-.RE
-.TP 20
-Standard cell placement
-The following functions allows to define a placement file for a standard cell
-design.
-This file can be used by the standard cell router \fBscr\fP(1).
-.RS
-	GENLIB_DEF_PHSC(3)
-.br
-	GENLIB_SAVE_PHSC(3)
-.br
-	GENLIB_SC_PLACE(3)
-.br
-	GENLIB_SC_RIGHT(3)
-.br
-	GENLIB_SC_TOP(3)
-.br
-	GENLIB_SC_LEFT(3)
-.br
-	GENLIB_SC_BOTTOM(3)
-.br
-.RE
-.TP 20
-Full custom symbolic layout
-Those functions are dedicated to optimized full custom procedural layout.
-In order to provide some process independance, \fIAlliance\fP uses a
-symbolic layout approach (fixed grid without compaction.)
-.br
-The symbolic objects are segments (wires), vias (contacts), connectors (I/Os),
-references and instances.
-For more informations, see \fBphseg\fP(1), \fBphvia\fP(1), \fBphcon\fP(1),
-\fBphref\fP(1), \fBphins\fP(1), and \fBalc\fP(1).
-.br
-	GENLIB_DEF_PHFIG(3)
-.br
-	GENLIB_SAVE_PHFIG(3)
-.br
-	GENLIB_DEF_AB(3)
-.br
-	GENLIB_DEF_PHINS(3)
-.br
-	GENLIB_PHCON(3)
-.br
-	GENLIB_COPY_UP_CON(3)
-.br
-	GENLIB_COPY_UP_CON_FACE(3)
-.br
-	GENLIB_COPY_UP_ALL_CON(3)
-.br
-	GENLIB_PHSEG(3)
-.br
-	GENLIB_COPY_UP_SEG(3)
-.br
-	GENLIB_THRU_H(3)
-.br
-	GENLIB_THRU_V(3)
-.br
-	GENLIB_THRU_CON_H(3)
-.br
-	GENLIB_THRU_CON_V(3)
-.br
-	GENLIB_WIRE1(3)
-.br
-	GENLIB_WIRE2(3)
-.br
-	GENLIB_WIRE3(3)
-.br
-	GENLIB_PHVIA(3)
-.br
-	GENLIB_PLACE(3)
-.br
-	GENLIB_PLACE_RIGHT(3)
-.br
-	GENLIB_PLACE_TOP(3)
-.br
-	GENLIB_PLACE_LEFT(3)
-.br
-	GENLIB_PLACE_BOTTOM(3)
-.br
-	GENLIB_PLACE_ON(3)
-.br
-	GENLIB_PHREF(3)
-.br
-	GENLIB_COPY_UP_REF(3)
-.br
-	GENLIB_COPY_UP_ALL_REF(3)
-.br
-	GENLIB_PLACE_VIA_REF(3)
-.br
-	GENLIB_PLACE_CON_REF(3)
-.br
-	GENLIB_PLACE_SEG_REF(3)
-.br
-	GENLIB_FLATTEN_PHFIG(3)
-.br
-	GENLIB_GET_REF_X(3)
-.br
-	GENLIB_GET_REF_Y(3)
-.br
-	GENLIB_GET_CON_X(3)
-.br
-	GENLIB_GET_CON_Y(3)
-.br
-	GENLIB_HEIGHT(3)
-.br
-	GENLIB_WIDTH(3)
-.RE
-.LP
-In order to have information about each of these functions, use the online
-documentation with \fBman\fP(1), as in ``man function-name''.
-.br
-.LP
-It is strongly recommended to read some books
-on C programming, in order to take full advantage of the C flow control
-possibilities, as it may greatly reduce the size of a \fBgenlib\fP source code.
-.SH ENVIRONMENT VARIABLES
-.TP 20
-the variables are :
-.ta 25n
-\fIname\fP	\fIdefault value\fP
-.br
-MBK_IN_LO(1)	al
-.br
-MBK_OUT_LO(1)	al
-.br
-MBK_IN_PH(1)	ap
-.br
-MBK_OUT_PH(1)	ap
-.br
-MBK_CATA_LIB(1)	.
-.br
-MBK_WORK_LIB(1)	.
-.br
-MBK_CATAL_NAME(1)	CATAL
-.LP
-see the corresponding manual pages for further informations.
-.br
-In order to compile and execute a genlib file, one has to call \fBgenlib\fP
-with one argument, that is the \fBgenlib\fP source file.
-The source file must have a .c extension, but the extension should not be
-mentionned on the command line.
-.PP
-The names used in genlib, as arguments to genlib functions, should be
-alphanumerical, including the underscore.
-They also are not case sensitive, so \fBVDD\fP is equivalent to \fBvdd\fP.
-Vectorized connectors or signal can be declareds using the \fB[n:m]\fP
-construct.
-.SH OPTIONS
-Two options can alter the behavior of \fBgenlib\fP : 
-.TP 20
--v
-displays everything that is to be done during the compilation and
-execution process: verbose mode.
-.TP
--k
-keeps the executable along with the compilation Makefile after completion.
-.SH EXAMPLES
-\fBgenlib\fP -v amd2901
-.br
-Compiles and runs a \fBgenlib\fP source file called amd2901.c
-.SH SEE ALSO
-.BR dpgen (1),
-.BR mbk (1),
-.BR alc (1),
-.BR scr (1),
-.BR bgd (1),
-.BR bsg (1),
-.BR grog (1),
-.BR rsa (1).
-
-.SH DIAGNOSTICS
-.RS
-\fBCompilation aborted\fP
-.RE
-This indicates either a \fIC\fP syntaxic error, most likely, or a
-misinstallation of the \fBmbk\fP package of the \fIAlliance\fP CAD system,
-if the error is \fBcannot find file genlib.h\fB.
-.RS
-\fBLink aborted\fP
-.RE
-This indicates a
-misinstallation of the \fBmbk\fP package of the \fIAlliance\fP CAD system,
-see your system administrator for details.
-.PP
-Many errors may occur while executing the source file, so refer to the proper
-genlib function manual for more.
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/genpat.1 b/alliance/share/man/man1/genpat.1
deleted file mode 100644
index ff942f98..00000000
--- a/alliance/share/man/man1/genpat.1
+++ /dev/null
@@ -1,186 +0,0 @@
-.\"   $Id: genpat.1,v 1.3 1999/10/25 08:03:08 simcity Exp $
-.\" @(#)genpat 2.0 Sep 07 1993 UPMC; Author: PITON D.
-.TH GENPAT 1 "October 1, 1997" "ASIM/LIP6" "ALLIANCE USER COMMANDS"
-
-.SH NAME
-.PP
-\fBgenpat\fP, A procedural pattern file generator
-
-.SH SYNOPSIS
-.PP
-\fBgenpat [-v] [-k] [file]\fP
-.br
-
-.so man1/alc_origin.1
-
-.SH DESCRIPTION
-.PP
-\fBGenpat\fP is a set of C fonctions that allows a procedural description of
-input pattern file for the logic simulator \fBASIMUT\fP. The Unix \fBgenpat\fP
-command accepts a C file as input and produces a pattern description file as
-output. The extension ".c" is not to be given. The file generated by
-\fBgenpat\fP is in pat format, so IT IS STRONGLY RECOMMENDED TO SEE pat(5)
-BEFORE THIS MANUAL.
-
-.SH OPTIONS
-.PP
-.TP 15
-\fI\-v\fP
-verbose mode
-.TP 15
-\fI\-k\fP
-keeps the executable along with the compilation Makefile after completion
-
-.SH GENPAT FILE FORMAT
-.PP
-From a user point of view, \fBgenpat\fP is a pattern description language
-using all standard C facilities (include, define, variables, loop, ...).
-Fonctions provided by \fBgenpat\fP are to be used in a given order. Using
-them in a different order won't crash the system, but will result in
-execution errors. Here follows the description of the input file.
-
-.PP
-A \fBpat\fP format file can be divided in two parts : declaration and
-description part.
-
-.PP
-The declaration part is the list of inputs, outputs, internal signals and
-registers. Inputs are to be forced to a certain value and all the others are
-to be observed during simulation.
-
-.PP
-The description part is a series of patterns, where each pattern defines the
-value of inputs and outputs at a given date. This date represents the absolute
-time for the simulator.
-
-.PP
-Similarly, a \fBgenpat\fP file can be divided in two parts : declaration and
-description part. Functions related to the declaration must be called before
-any function related to the description part.
-
-.PP
-.TP 10
-\fIdeclaration part\fP
-The first thing you should do in this part is to give the output file's name
-(see DEF_GENPAT(3)). You can also set the time unit (see SETTUNIT(3)).
-Then, this part allows you to declare the inputs, the outputs, and internal
-observing points (see DECLAR(3)). It is also possible to create virtual
-arraies (see ARRAY(3)).
-.TP 10
-\fIdescription part\fP
-After all signals are declared, you can begin to define input values which
-are to be applied to the inputs of the circuit at given simulation time.
-You can also define output values which are to be compare with the values
-produced during the simulation. (see AFFECT(3)).
-Genpat describes the stimulus by event : only signal transitions are described.
-Genpat manage the simulation time according to the time unit specified using
-SETTUNIT in the declaration part.
-This part also allows you to give instructions to the simulation tool to save
-the state of the circuit at the end of the simulation. (see SAVE(3)). Last
-thing you should do in this part is to generate the output file (see
-SAV_GENPAT(3)).  
-
-.SH FUNCTIONS
-.PP
-.TP 15
-\fIDEF_GENPAT()\fP 
-defines the output file's name.
-.TP 15
-\fISETTUNIT()\fP 
-defines the time unit (default is ps : pico-seconde).
-.TP 15   
-\fISAV_GENPAT()\fP
-make the output file be generated
-.TP 15
-\fIDECLAR()\fP
-declares inputs, outputs, and the internal observing points.
-.TP 15
-\fIARRAY()\fP
-allows signals of the same type to be groupped in an "virtual array" in
-order to ease their manipulation 
-.TP 15
-\fIINIT()\fP
-changes the values of registers between two patterns.
-.TP 15
-\fIAFFECT()\fP
-assigns a value to a signal, at a given simulation time (in ps). This value
-is kept on the signal until a new value is assigned to the signal.
-.TP 15
-\fISAVE()\fP
-informs the simulation tool to save the state of the circuit at the end of
-simulation
-.TP 15
-\fILABEL()\fP
-gives a label to the current pattern.
-.TP 15
-\fIGETCPAT()\fP
-return the date of the current pattern (in ps).
-
-.SH EXAMPLES
-.PP
- 
-.nf
-#include <stdio.h>
-#include "genpat.h"
-
-char *inttostr(entier)
-int entier;
-  {
-  char *str;
-  str = (char *) mbkalloc (32 * sizeof (char));
-  sprintf (str, "%d",entier);
-  return(str);
-  }
- 
- main () 
- {
- int i;
- int j;
- int vect_date; /* this date is an absolute date, in ps */
- 
- DEF_GENPAT("vecteurs");
-
- SETTUNIT ("ns");
- 
- /* interface */
- DECLAR ("a", ":2", "X", IN, "0  to 3", "");
- DECLAR ("b", ":2", "X", IN, "0  to 3", "");
- DECLAR ("sel", ":2", "B", IN, "", "");
- DECLAR ("ck", ":2", "B", IN, "", "");
- DECLAR ("s", ":2", "X", OUT, "0 to 3", "S");
- 
- LABEL ("additionneur");
- AFFECT ("0", "ck", "0b0");
- AFFECT ("0", "sel", "0b0");
- 
- for (i=0; i<16; i++)
-     for (j=0; j<16; j++) 
-     {
-         vect_date = i*16 + j;
-         AFFECT (inttostr(vect_date), "a", inttostr(i));
-         AFFECT (inttostr(vect_date), "b", inttostr(j));
-     }
- 
- vect_date = vect_date + 1;
- AFFECT (inttostr(vect_date), "a", "0b0");
- AFFECT (inttostr(vect_date), "b", "0b0");
- AFFECT (inttostr(vect_date), "sel", "0b0");
- AFFECT (inttostr(vect_date), "ck" , "0b0");
- 
- SAV_GENPAT ();
- }
-.fi
- 
-.SH ENVIRONMENT VARIABLES
-.PP
-\fBGenpat\fP reads the environment variable VH_PATSFX to give the result
-file an extension.
-
-.SH SEE ALSO
-.PP
-AFFECT(3), ARRAY(3), DECLAR(3), DEF_GENPAT(3), GETCPAT(3), INIT(3), LABEL(3),
-SAVE(3), SAV_GENPAT(3), SETTUNIT(3), pat(5), asimut(1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/genscan.1 b/alliance/share/man/man1/genscan.1
deleted file mode 100644
index 2b09351a..00000000
--- a/alliance/share/man/man1/genscan.1
+++ /dev/null
@@ -1,177 +0,0 @@
-.\"   $Id: genscan.1,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)Labo.l 0.0 92/09/24 UPMC; Author: amar GUETTAF
-.pl -.4
-.TH GENSCAN 1 "October 1, 1997" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
-.SH NAME
-.TP
-genscan - scan path generator
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.TP
-\fBgenscan\fP \fIsource\fP \fItarget\fP [\fIoptions\fP] 
-.br
-.SH DESCRIPTION
-\fBgenscan\fP is an automatic scan architecture generator for gate level netlists. The input netlist must be a sequential one with no scan-path or a complete and unique scan-path.\fBgenscan\fP can add a full or a partial scan-path.
-.br
-
-\fB1/ input netlist\fP
-.br
-The \fIsource\fP file describes the input net-list.
-.br
-\fBgenscan\fP supports sequential D flip-flop based net-lists. For this release the input netlist must be a gate level netlist. The netlist format can be : structural VHDL, EDIF, or ALLIANCE internal format according to the environment variable \fBMBK_IN_LO\fP.
-.br
-
-\fB2/ output netlist\fP
-.br
-The generated file containing the netlist with scan_path will have the name \fItarget\fP. The output format is defined by the environment variable \fBMBK_OUT_LO\fP.
-.br
-The scan-path architecture generation can be used in two ways. The first method consists of changing all the D flip-flop instances of the netlist with scannable ones to build a scan-path . The second one, consist on changing the order of an existant scan-path . 
-.br
-Some new signals may be added to the circuit interface. For sequential circuits with no scan-path we have three new signals, a \fIscan input\fP, a \fIscan output\fP, and  a \fItest\fP signal. The \fItest\fP is used to select the scan-path mode or the functional mode. For sequential circuits with already existing scan-path or already declared scan signals no signals are added.    
-.br
-A full or a partial scan-path can be added to a sequential netlist , the optiona \fI-s ScanOrder\fP file gives the way in which memory cells will be ordered in the scan-path. The order of the scan_path can be specified using the register identifiers (instance name), if the registers names are indexed using the underscore character and a number ( for example : \fIregister_12\fP ), the order is the growing way of the registers index. The scan-path default order is the random one. 
-.br
-.SH OPTIONS 
-.TP 20
-\fI\-n\fP
-use the declared \fIscan_out\fP as the output of the scan chain. This option is useful if the output of the last DFF of the scan chain is a primary output. 
-.TP 20
-\fI\-s ScanOrderFile\fP
-A user scan-path order can be specified using the \fIScanOrderFile\fP file. This file gives the memory cells instances names and the order in wich they will appear in the scan-path. If this file is not specified a full scan-path is added to the netlist with a register index based order or a random order. The \fIScanOrderFile\fP is a text file in which each line contains one memory cell instance name. The first instance ( top of the file) will be connected to scan input signal and the last instance (bottom of the file) will be connected to scan out signal.
-
-
-.SH ENVIRONMENT
-\f4genscan\fR relies on the proper setting of the following environment variables.
-The first set of environment variables sets the \fBMBK\fP environment. The second set gives the names of special signals if they exist or if they must be added on the interface.The last set of environment variables give the names of D flip-flop and scannable D flip-flop models.
-
-.TP 20
-\f4MBK_CATA_LIB\fR(1)
-gives the path to the cell libraries. 
-.TP 20
-\f4MBK_WORK_LIB\fR(1)
-furnishes the path to the working directory.
-.TP 20
-\f4MBK_IN_LO\fR(1)
-indicates the input structural file format.
-.TP 20
-\f4MBK_OUT_LO\fR(1)
-indicates the output structural file format.
-
-.TP 20
-\f4SCIN\fR
-scan input connector of the netlist.
-.TP 20
-\f4SCOUT\fR
-scan output connector  of the netlist.
-.TP 20
-\f4TEST\fR
-test and functional mode selection connector.This variable is defined by the signals name. 
-.TP 20
-\f4CLOCK\fR
-netlist clock input.
-.TP 20
-\f4DFF\fR
-D flip-flop model name and its interface organization( \fIModelName\fP : \fIDataIn\fP : \fIClock\fP : \fIDataOut\fP).
-.TP 20
-\f4SCAN_DFF\fR
-scannable D flip-flop model name and its interface organization( \fIModelName\fP : \fIDataIn\fP : \fIScanIn\fP : \fIScanEnable\fP : \fIClock\fP : \fIDataOut\fP). The test signal is connected to the ScanEnable input. 
-
-.SH EXAMPLES
-To use \fBgenscan\fP, some environment variables must be set :
-.br
-If the ALLIANCE format is used, the user must have the following environment:
-.br
-.BR 	MBK_CATA_LIB 
-=/labo/cells/sclib
-.br
-.BR 	MBK_IN_LO 
-=vst
-.br
-.BR 	MBK_OUT_LO 
-=vst
-.br
-.BR 	MBK_WORK_LIB 
-=. 
-.br
-.BR 	MBK_VDD 
-=vdd 
-.br
-.BR 	MBK_VSS 
-=vss 
-.br
-According to the netlist we have for example the following environement variables:
-.br
-.BR SCIN 
-=scin
-.br
-.BR 	SCOUT 
-=scout
-.br
-.BR 	TEST 
-=test 
-.br
-.BR 	CLOCK 
-=clk 
-.br
-.br 
-For using sclib library we have:
-.br
-.BR 	DFF 
-=ms_y:i:l:t 
-.br
-.BR 	SCAN_DFF 
-=ms2_y:di:si:se:l:t 
-.br
-The command line to be executed for adding a scan-path architecture  with a default order to the circuit called, for example, "automate" is:
-.br
-.TP
-\fBgenscan\fP automate automate_scan 
-.br
-The input netlist will be the file \fIautomate.vst\fP
-.br
-The resulting file will be \fIautomate_scan.vst\fP
-.br
-.TP
-\fBgenscan\fP ctrl ctrl_scan -s order 
-.br
-This command allows to add a scan path to the circuit called \fIctrl\fP with the order defined by the input file \fIorder\fP , the result netlist is ctrl_scan.The content of the file \fIorder\fP is:
-.br
-.br 
-       state_0
-.br
-       state_2
-.br
-       state_1
-.br
-       state_3
-.br
-.br
-The memory cell \fIstate_0\fP will be the first cell in the scan-path and the cell \fIsatate_3\fP is the last one.
-.br
-.SH SEE ALSO
-.BR mbkenv (3).
-
-
-.SH DIAGNOSTICS
-.br
-.BR 1/ 
-\fIModel ... not found !!\fP
-.br
-The model defined by an environment variable doesn't exist in the library.
-.br
-
-.BR 2/ 
-\fIConnector names discrepency on model ...\fP
-.br
-When the connectors names of a defined model ( defined by the environment variable) are different from those of the model  in the library.
-.br
-
-.BR 3/ 
-\fICan't extract scan-path\fP
-.br
-There is no active path between scan input and scan output signals.
-.br
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/genview.1 b/alliance/share/man/man1/genview.1
deleted file mode 100644
index 2f2ab15f..00000000
--- a/alliance/share/man/man1/genview.1
+++ /dev/null
@@ -1,294 +0,0 @@
-.\"   $Id: genview.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
-.\" @(#)genview.l 0.0 90/22/08 UPMC; Author: Frederic Petrot
-.\" make a choice for Bold font thru the entire doc
-.ie t \{\
-.fp 4 C \}
-.el \{\
-.fp 4 B \}
-.TH GENVIEW 1 "October 1, 1997" "ASIM/LIP6" "ALLIANCE USER COMMANDS"
-.SH NAME
-genview \- genlib graphical source level debugger
-.SH SYNOPSYS
-\f4genview [ \-s \fIsource_file\f4 ] [ \-l \fIlayout_file\f4 ]
-.RS 8n
-[ \-ge \fI<height>x<width>[{+}x{+}y]\f4 ]
-.br
-[ \-gt \fI<height>x<width>[{+}x{+}y]\f4 ]
-.br
-[ \-gv \fI<height>x<width>[{+}x{+}y]\f4 ]\fR
-.RE
-.so man1/alc_origin.1
-.SH DESCRIPTION
-\f4Genview\fP is a graphical source level debugger for the \fIcao-vlsi\fP
-procedural generation language \f4genlib\fR.
-\f4Genview\fR stands for procedural \f4Gen\fPerator \f4View\fPer,
-because its primary
-use is to help debug parametrable layout generator programs.
-Since \f4genlib\fP is a superset of the \f4C\fP language, de facto
-\f4genview\fP is a \f4C\fP debugger that contains a specific dictionary for
-\f4genlib\fP's functions.
-.br
-\f4Genview\fP works under X11r4, and is made of, at least, three distinct
-windows, each of them having a given behaviour:
-.TP 10
-Edit Window
-This window allows the user to edit a source file under a \f4vi\fR-like editor.
-It is \fInot\fR \f4vi\fR, so only the basical and most used functions have
-been implemented.
-.br
-No meta-characters can be used, things like `\f4c$\fR' or `\f4cw\fR', or
-`\f4.\fR' are not available.
-But this is not so much of a restriction, since they are far less used than
-`\f4i\fR', `\f4a\fR' or `\f4o\fR'.
-.br
-The menu of the Edit window is, let's say, the main menu of the application.
-It contains three separate items, each of them made up of some buttons.
-They could be called System, Interpret and trace.
-.RS 5
-
-System:
-.TP 10
-`load'
-enables to load a \f4C\fP source file from disk.
-The complete path to the file is expected, either absolu or relative, but
-no meta-characters may be used.
-.TP 10
-`save'
-enables to save an edited file to the disk.
-The constrains are the same as for loading.
-.TP 10
-`shell'
-runs either a shell command if given as parameter, or runs an
-\fIxterm\fP if no arguments are given in the dialog box.
-.TP 10
-`exit'
-kills genview.
-The state of the source files is not check before exiting, so make sure you
-are up to date.
-.RE
-.RS 5
-
-Interpret:
-.TP 10
-`compile'
-just calls the compiler for syntax checks.
-Currently, this button is desactivated.
-No actions are performed if clicked.
-.TP 10
-`run'
-calls the compiler, if the file has not yet been compiled,
-then the interpreter, and executes all the file, if
-no break points are present.
-If a break point is encountered, then an other click on run go to the next
-break point or the end of file.
-.TP 10
-`step'
-calls the compiler, if the file has not yet been compiled, and
-goes to the \fImain\fP position in the code.
-Then further clicks on `step' will execute the source file statement by
-statement, entering inside local function calls.
-.TP 10
-`next'
-is like `step', but executes call all at once.
-.TP 10
-`start'
-goes back to \fImain\fP if clicked while interpreting.
-.TP 10
-`params'
-is used to set the \fImain\fP arguments, for parametrable generators.
-This function bugs today, so please avoid using it.
-.RE
-.RS 5
-
-Trace:
-.TP 10
-`set/unset bp'
-is a flip-flop that either sets or unsets, depending of the
-previous state of the line, a break point on a given line.
-The line is choosen by the cursor position in the `Edit window'.
-Take care not to put a break point on a `\f4{\fR' or `\f4}\fR', or
-something like that,
-since it will not be taken into account at execution time.
-Choose a \f4C\fP control statement, or a function call.
-.TP 10
-`clear all bps'
-clears all previously sets break points.
-.TP 10
-`set trace'
-tells the interpreter to print out in the `Trace window' the
-value of the given variable.
-To name a variable, give, if it is a global one, it name as argument.
-If it is a local one, just concatenate the function name with the variable
-name, separeted by a semi-colon.
-This function is not entirely bug free.
-Do not use it with the argument of the \fImain\fP, because this is most
-likely to fail.
-.TP 10
-`unset trace'
-tells the interpreter no to trace anymore a given variable.
-.RE
-.TP 10
-Trace Window
-The Trace window is an output window in the which are redirected all
-system and \f4genlib\fP errors, and also user messages given through
-\fIprintf\fP since it represent both \fIstderr\fP and \fPstdout\fP.
-.br
-It is much simpler than the other windows, and possesses four buttons, that
-allow to scroll through it:
-.RS 5
-.TP 10
-`line up'
-scrolls up one line at a time.
-.TP 10
-`line down'
-scrolls down one line at a time.
-.TP 10
-`page up'
-for one page up.
-.TP 10
-`page down'
-for one page down.
-.RE
-.TP 10
-View Window
-The View window is an output window that contains the drawing of the layout
-beeing textualy described in genlib.
-It may also be used to simply load a symbolic layout cell, for looking at it
-only.
-This is not a symbolic layout editor.
-It contains many buttons needed to modify circuit coordinates and scale.
-.RS 5
-.TP 10
-`in'
-allows to change the scale.
-Push down the leftmost button of the mouse, and move it.
-It defines a one pixel box that represents the new window to be displayed.
-As soon as the button is released, the windows changes.
-.TP 10
-`out'
-comes back to the window defined by the previous `in'.
-.TP 10
-`fit'
-center the circuit, with appropriate scale, so it occupies the whole window.
-.TP 10
-`zoom'
-enlarges the scale, center of the window beeing left unchanged.
-The `scale factor' can be defined by clicking into and moving the rectangle of
-the right hand side icon of `zoom'.
-.TP 10
-`mooz'
-reduces the scale, center of the window beeing left unchanged.
-The `scale factor' can be defined by clicking into and moving the rectangle of
-the right hand side icon of `zoom'.
-.TP 10
-`lock'
-explicits the entire window to transistor level.
-Please do no use this function on an entire big circuit, because it is very
-time and memory consuming, and does not give any informations but artistic ones.
-.TP 10
-`peek'
-explicits the user defined window to transistor level.
-Push down the leftmost button of the mouse, and move it.
-It defines a one pixel box that represents the new window to be displayed.
-As soon as the button is released, the windows changes.
-.TP 10
-`pan'
-move the window in both `x' and `y' direction over the circuit.
-Push down the leftmost button of the mouse, and move it.
-A line is drawn, and as soon as the button is released, the windows changes.
-The begining point of the line beeing placed at the end point after the
-operation.
-If this is not really clear, just try it!
-.TP 10
-`refresh'
-redraws the entire screen.
-.TP 10
-`inspect'
-gives a textual output of the screen contents in a window opened for it.
-This window has scrolling buttons, so see `Trace window' for the motions.
-.TP 10
-`^ > v <'
-move the screen over the circuit.
-.TP 10
-`setup'
-opens a window that allows to choose users preferences.
-Moreless self explanatory.
-.TP 10
-`load'
-loads a layout cell directly from disk.
-.TP 10
-`map'
-draws the overall abutment box of the circuit.
-Clicking in it will move the circuit to the given point.
-.TP 10
-`x y'
-indicate current circuit absolute coordinates.
-Clicking in this button will allow the user to set them to a desired value.
-.TP 10
-`dx dy'
-indicate relatives coordinates regarding the most recent mouse click.
-.RE
-
-As most graphical tool, using it will be much easier than using this
-documentation, so just try it.
-.SH OPTIONS
-.TP 10
-\f4\-s\fP \fIsourcefile\fP
-tells genview to load a source file in its `Edit window' when starting.
-the source file may be any 32-127 ascii file.
-The file is to be given with its extension and path if needed.
-But only file sufixed by `.c' are to be interpreted.
-.TP 10
-\f4\-l\fP \fIlayoutfile\fP
-tells genview to load a layout file in its `View window' when starting.
-The file name is given without extension.
-.TP 10
-\f4\-ge\fP \fI<height>x<width>[{+}x{+}y]\fP
-opens the `Edit window' at \fIx\fP and \fIy\fP coordinates with the given
-\fIheight\fP and \fIwidth\fP.
-This is for customisation, but it is recommanded to use \fIas it is\fP because
-it is what esxperience has shown to be more practical.
-.TP 10
-\f4\-gt\fP \fI<height>x<width>[{+}x{+}y]\fP
-opens the `Trace window' at \fIx\fP and \fIy\fP coordinates with the given
-\fIheight\fP and \fIwidth\fP.
-.TP 10
-\f4\-gv\fP \fI<height>x<width>[{+}x{+}y]\fP
-opens the `View window' at \fIx\fP and \fIy\fP coordinates with the given
-\fIheight\fP and \fIwidth\fP.
-.SH EXAMPLE
-genview -s rsa.c -l gapg0_b
-.SH ENVIRONMENT VARIABLES
-.TP
-\f4MBK_CATA_LIB\fR(1)
-indicates the path to the read only libraries to be used under \f4genview\fR.
-.TP
-\f4MBK_WORK_LIB\fR(1)
-indicates the path to the read/write directory for the session.
-.TP
-\f4MBK_IN_PH\fR(1)
-indicates the file format to be used for the leaf cells.
-.TP
-\f4MBK_OUT_PH\fR(1)
-indicates the file format to be used for the generated blocks.
-
-.SH SEE ALSO
-.BR mbk (1).
-.BR genlib (1).
-
-.SH DIAGNOSTICS
-In order to work, \f4genview\fP must have read/write access on a directory
-called `/usr/tmp'.
-It will else fail at any compilation or inspect attempt.
-.br
-\f4Genview\fP does not allows rotations in placed instances.
-This is because it has been written for full custom generator debug, and such
-geometrical operations are not used in this context.
-This is the only known incompatibility with \f4genlib\fP.
-.br
-The use of \fImain\fP arguments is not entirely debugged, and may lead to
-a software exception.
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/glop.1 b/alliance/share/man/man1/glop.1
deleted file mode 100644
index ace0716f..00000000
--- a/alliance/share/man/man1/glop.1
+++ /dev/null
@@ -1,92 +0,0 @@
-.\"   $Id: glop.1,v 1.2 2001/04/04 13:19:58 francois Exp $
-.\" 
-.\" 
-.\"   $Id: glop.1,v 1.2 2001/04/04 13:19:58 francois Exp $
-.\" 
-.\" 
-.pl -.4
-.TH GLOP 1 "October 1, 1997" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
-.SH NAME
-.TP
-glop   
-\- Fanout optimizer, global optimizer and timing analyzer of a gate netlist 
-
-.so man1/alc_origin.1
-
-.SH SYNOPSIS
-.TP
-\fBglop\fP [\fI-f | -g | -t | -i\fP]  \fInetlist_file\fP \fInetlist_output\fP \fI[file_of_parameters]\fP
-.br
-
-.SH DESCRIPTION
-.br
-You should rather use the newest version of \fBloon\fP.
-\fBglop\fP is a CAD tool that permits to remove fanout problems within a gates netlist and to optimize the delay. The netlist can be hierarchical and is flattened if necessary. \fBglop\fP run in  batch mode and a parameter file can be used (see man \fBlax\fP) to parametrize optimization by adding informations on outputs (fanin), inputs (fanout, delay) and by setting general parameters such as fanout factor.
-\fBglop\fP permits to compute delays of gates in the netlist and gives the critical path in the netlist. The global optimization of \fBglop\fP performs gate repowering and buffer inserting to decrease the critical path delay.
-
-.br
-.SH OPTIONS
-.br
-One option may be given at the same time.
-.HP
-.ti 7
-\fI-f\fP performs a fanout optimization : This checks the fanout of every gates, regardless of the critical path, and insert buffer or a more powerfull gate if necessary.
-.HP
-.ti 7
-\fI-g\fP performs a timing optimization : This checks the fanout of every gates and insert buffer or a more powerfull gate only if the critical path is not altered.
-.HP
-.ti 7
-\fI-i\fP gives fanout informations about the netlist 
-.HP
-.ti 7
-\fI-t\fP gives timing informations about the netlist 
-
-
-.SH EXAMPLES
-.br
-You can call \fBglop\fP as follows :
-.br
-	glop -f add8 add8opt
-.br
-	glop -g alu4 alu4buff myparam
-.br
-
-.SH ENVIRONMENT VARIABLES
-.br
-.HP
-.ti 7
-\fIMBK_WORK_LIB\fP gives the path for the input and output netlist files or parameter file.
-.HP
-.ti 7
-\fIMBK_CATA_LIB\fP gives the auxiliary path for the input netlist file or paths for the cell libraries. 
-.HP
-.ti 7
-\fIMBK_IN_LO\fP gives the format for input structural description. 
-.HP
-.ti 7
-\fIMBK_OUT_LO\fP gives the format for output structural description. 
-.HP
-.ti 7
-\fIMBK_VDD\fP & \fIMBK_VSS\fP permits to define the alimentation names.
-
-
-.SH SEE ALSO
-.br
-loon(1), boom(1), boog(1), genlib(1), scmap(1), sclib(1), sxlib(1), scr(1).
-.br
-
-.SH DIAGNOSTICS
-.PP
-.br
-Special optimisation can be done running \fBglop\fP twice :
-.br
-	1: glop -g alu4 alu4g myparam
-.br
-	2: glop -f alu4g alu4buff myparam
-.br
-Then the second time \fBglop\fP is run (whith -f) it doesn't optimizes the gates added by
-the first pass and uses a FANOUT_FACTOR/4 for the internal gates.
-This is used to optimize the critcal path AND the interface cells.
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/graal.1 b/alliance/share/man/man1/graal.1
deleted file mode 100644
index d1037c27..00000000
--- a/alliance/share/man/man1/graal.1
+++ /dev/null
@@ -1,153 +0,0 @@
-.\"   $Id: graal.1,v 1.3 1999/11/22 15:29:55 syf Exp $
-.\" @(#)graal 1.07 94/10/10 UPMC/ASIM/LIP6/CAO-VLSI "
-.TH GRAAL 1 "October 1, 1997" "ASIM/LIP6" "ALLIANCE Reference Manual"
-.SH NAME
-graal \- symbolic layout editor
-.SH SYNOPSIS
-.B graal
-[\-l file_name]
-[\-scale n]
-[\-debug]
-[\-xor]
-[\-install]
-      [\-force]
-.br
-.so man1/alc_origin.1
-.SH DESCRIPTION
-.B Graal
-is a hierarchical symbolic layout editor. All functionnalities can be
-accessed through different menus.
-Among them exists a design rule checker performing verifications inside a
-user defined window.
-.B Graal
-works under Motif and X11r6.
-When entering 
-.B Graal,
-the main window appears and shows 7 different
-menus on the top bar.These menus can be entered by simply clicking on the
-mouse left button. Here is the description of these menus.
-
-.TP 10
-.B File
-\f4New\fP : clean the entire window and save the current cell.
-.br
-\f4Open\fP : load an already existing cell.
-.br
-\f4Save\fP : save the current cell.
-.br
-\f4Save as\fP : rename and save the current cell.
-.br
-\f4Quit\fP : quit graal.
-
-.TP 10
-.B Edit
-\f4Undo\fP : undo the previous action.
-.br
-\f4Copy\fP : copy a selected object.
-.br
-\f4Move\fP : move a selected object.
-.br
-\f4Delete\fP : delete a selected object.
-.br
-\f4Stretch\fP : strech a selected object (transistor or segment length).
-.br
-\f4Modify\fP : modify the caracteristics of an object (name, width,
-etc...).
-.br
-\f4Identify\fP : identify a selected object.
-.br
-\f4Search\fP : search an object according to its type.
-
-.TP 10
-.B Window
-This menu allows user to perform the same actions than the previous menu
-Edit, not on an object but on a group of objects belonging to a defined
-window.The two opposite corner of the window are set by clicking on the mouse 
-left button.
-
-.TP 10
-.B Create
-\f4Instance\fP : add a new instance in the current cell.
-.br
-\f4Abutmentbox\fP : define the abutment box of the current cell.
-.br
-\f4Segment\fP : add segments.
-.br
-\f4Via\fP : add vias or contacts.
-.br
-\f4Connector\fP : add connectors.
-.br
-\f4Transistor\fP : add transistors.
-.br
-\f4Reference\fP : add references.
-
-.TP 10   
-.B View
-\f4Zoom\fP : perform zoom in, zoom out, center, fit, refresh on figure.
-.br
-\f4Layer\fP : select types of layers displayed.
-.br
-\f4Map\fP : show cursor position in the entire figure.
-.br
-\f4Arrows\fP : show arrows for moving at the grid step.
-.br
-\f4Grid\fP : Set the X,Y step of the grid if displayed.
-
-.TP 10
-.B Tools
-\f4Equi\fP : highlight all objects electrically connected to a given object.
-.br
-\f4Flat\fP : virtual hierarchy flattening of an instance
-(display all visible objects inside a given instance). 
-.br
-\f4UnFlat\fP : undo the virtual flattening of an instance
-(done before with the Flat command)
-.br
-\f4Peek\fP : virtual hierarchy flattening 
-(display all visible objects inside a given window). 
-.br
-\f4UnPeek\fP : undo the virtual flattening of a window
-(done before with the Peek command)
-.br
-\f4Druc\fP : call the design rule checker in a given window.
-.br
-\f4RealFlat\fP : real hierarchy flattening of instances included in a window
-(this command can not be undone, and should be used very carefully)
-.br
-\f4Hierarchy\fP : navigate into the current figure hierarchy
-.br
-\f4Load Error\fP : load a real layout file and superpose it to the current figure.
-.br
-\f4Message\fP : display the last error messages
-
-
-.TP 10
-.B Setup
-Save or load a user defined configuration of default displayed menus.
-
-.SH ENVIRONMENT VARIABLES
-.TP
-.B MBK_CATA_LIB
-indicates the path to the read only libraries to be used. 
-.TP
-.B MBK_WORK_LIB
-indicates the path to the read/write directory for the session.
-.TP
-.B MBK_IN_PH
-indicates the file format to be used for the leaf cells.
-.TP
-.B MBK_OUT_PH
-indicates the file format to be used for the generated figures.
-.TP
-.B GRAAL_TECHNO_NAME (optionnal)
-indicates the path to the techno name file used by Graal.
-.TP
-.B RDS_TECHNO_NAME (optionnal)
-indicates the path to the RDS configuration file used by Graal.
-
-.SH SEE ALSO
-mbk(1), MBK_CATA_LIB(1), MBK_IN_PH(1), MBK_OUT_PH(1), RDS_TECHNO_NAME(1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/grog.1 b/alliance/share/man/man1/grog.1
deleted file mode 100644
index b40cb57f..00000000
--- a/alliance/share/man/man1/grog.1
+++ /dev/null
@@ -1,262 +0,0 @@
-.\"   $Id: grog.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
-.\" @(#)grog.1 0.0 90/22/08 UPMC; Author: Frederic Petrot
-.\" choose font for the entire document, when in groff
-.ie t \{\
-.fp 4 C \}
-.el \{\
-.fp 4 B \}
-.TH GROG 1 "October 1, 1997" "ASIM/LIP6" "ALLIANCE USER COMMANDS"
-.SH NAME
-grog \- a generic \fIROM\fR generator
-.SH SYNOPSIS
-\f4grog \fIbits words codefile \f4[ -tr ] [ -hz ] [ -r ] [-msb0]
-[ -o \fIblockname\f4 ] [ -layout ] [ -vhdl ] [ -icon ] [ -logicalbox ]
-[ -physicalbox ] [ -datasheet ]\fR
-.so man1/alc_origin.1
-.SH DESCRIPTION
-\f4grog\fR is high speed portable \fIROM\fR generator.
-The \fIROM\fP is contact coded, this means than all non used transistors are
-left with an unconnected drain.
-This is not an error, but some verification tools may be mixed up.
-.\" \f4grog\fR generates different views of a read only memory,
-.\" ranging from layout to datasheet.
-.br
-The \fIROM\fR binary contents is defined in the \f4codefile\fR.
-This file is a dataflow VHDL description file with \f4vbe\fR extension. 
-In this file, the text after the first \f4WITH/SELECT/WHEN\fR construct is
-considered as the \fIROM\fR contents.
-The constant and concatenation operators are allowed in this description.
-.br
-A little example is given below :
-.br
-.nf
-.ie t \fC
-.el \f4
-constant rot    : bit_vector(2 downto 0) := B"101" ;
-constant pet    : bit_vector(2 downto 0) := B"110" ;
-constant more   : bit_vector(3 downto 0) := B"0100" ;
-constant some   : bit_vector(3 downto 0) := B"0001" ;
-constant more   : bit_vector(3 downto 0) := B"0100" ;
-constant ones   : bit_vector(3 downto 0) := B"1111" ;
-constant fred   : bit_vector(7 downto 0) := B"01110111" ;
-constant other  : bit_vector(7 downto 0) := B"10000110" ;
-constant stuff  : bit_vector(7 downto 0) := B"01110101" ;
-constant eric   : bit_vector(7 downto 0) := B"10101110" ;
-
-WITH address(5 DOWNTO 0) SELECT
-     output(0 TO 15) <= some & more & stuff WHEN B"000000",
-                        some & other & ones WHEN B"1" & X"F",
-                        fred & eric         WHEN pet & rot,
-                        X"FFFF"             WHEN OTHERS;
-.fi
-.br
-.ft R
-Both the address and the output assigments have to contain the vector
-ordering explicitly.
-The least significant bit of the address vector has index \f40\fR.
-
-In order to be able to generate any view, the path to \f4grog\fR leaf cells
-library, \fIgrol\fR, must be set correctly.
-The usual path is \f4/labo/cells/grog\fR, and has to be put in the
-environment through the use of the \f4MBK_CATA_LIB\fR(1) shell variable.
-Notice that the leaf cells of the \fIROM\fR follows a given naming convention,
-to avoid name collisions when generating the final tape.
-So, all leaf cells names are prefixed with \f4gr\fR and suffixed with
-\f4_c\fR.
-.LP
-The \fIROM\fR interface is described here for behavior description.
-.br
-.nf
-.ie t \fC
-.el \f4
- ENTITY grog IS
-   PORT( adr  : IN BIT_VECTOR(\fIn\fP DOWNTO 0);
-         ck   : IN BIT_VECTOR(\fIk\fP DOWNTO 0);
-         f    : OUT BIT_VECTOR(\fIm\fP DOWNTO 0);
-         vdd  : IN BIT;
-         vss  : IN BIT );
- END grog;
-.ft R
-.fi
-.LP
-When the number of words is larger than \f4512\fR, the \f4ck\fR connector
-is vectorized.
-In that case, all clock connectors are not internally shorted and must
-be externally connected to the same signal.
-.SH OPTIONS
-.ie t \fC
-.el \f4
-.TP 20
-bits
-.ft R
-specifies the number of bits per words.
-The legal values range from \f41\fR to \f464\fP inclusive.
-.ie t \fC
-.el \f4
-.TP 20
-words
-.ft R
-specifies the number of words in the rom.
-The legal values are \f464, 128, 256, \fIn\fP \(** 512\fR,
-where \fIn\fP ranges from \f41\fP to \f48\fP inclusive.
-.ie t \fC
-.el \f4
-.TP 20
-codefile
-.ft R
-gives the name of the file to be used for programming the \fIROM\fP.
-The file is expected to have a \f4.vbe\fP extension.
-.ie t \fC
-.el \f4
-.TP 20
--tr
-.ft R
-indicates that a minimum width metal 1 through route is to be placed each
-every vertical bit slice in the \fIROM\fP matrix.
-This through route does not have connectors associated to it, it is just
-a path to be used by floorplan router if needed.
-.ie t \fC
-.el \f4
-.TP 20
--hz
-.ft R
-indicates that the output buffer is a three-state buffer and not a simple
-direct buffer.
-This means that a connector for the three-state control signal
-called \f4oe\fP, is created.
-.br
-The output is in high impedance when \f4oe\fP is low.
-.ie t \fC
-.el \f4
-.TP 20
--r
-.ft R
-when chosen, this option reverses the topological order of the ouputs.
-By default, \f4f[0]\fP is on the left hand side of the circuit, the 
-decoder being at the right hand side.
-Using \f4r\fP indicates that \f4f[0]\fP will be placed on the right
-hand side.
-.ie t \fC
-.el \f4
-.TP 20
--msb0
-.ft R
-indicates that the most significant bit of the addresses, \f4adr\fR lines, is
-called \f4adr(0)\fP in the \fIvhdl\fR coding file, thus changing its meaning
-and the \fIROM\fP binary contents.
-.ie t \fC
-.el \f4
-.TP 20
--n \fIblockname\fR
-forces the resulting files to have the name \fIname\fP.
-If not specified, the generator will create a unique name, for a given
-set of parameters excluding the coding file.
-.ie t \fC
-.el \f4
-.TP 20
--layout
-.ft R
-if stated, will generate the \fIROM\fP layout.
-.ie t \fC
-.el \f4
-.TP 20
--vhdl
-.ft R
-will output the \f4vhdl\fP description of the coded \fIROM\fP.
-A pattern file, for cosimulation purpose, is also created.
-.TP 20
-\f4-icon\fR
-will generate the icon view of the block.
-.ie t \fC
-.el \f4
-.TP 20
--logicalbox
-.ft R
-will generate an interface of the circuit, in terms of connectors, for use
-with a router.
-No internal description in terms of gate netlist is generated.
-.ie t \fC
-.el \f4
-.TP 20
--physicalbox
-.ft R
-generates only a layout outline of the \fIROM\fP.
-This is of little interest, since the internal layout is not top secret.
-.ie t \fC
-.el \f4
-.TP 20
--datasheet
-.ft R
-outputs some informations in readable form about the \fIROM\fP, like size,
-and also an estimation of the propagation delays.
-.SH EXAMPLES
-.RS
-.ie t \fC
-.el \f4
-grog 5 1024 romcode -hz -r -logicalbox -physicalbox
-.ft R
-.RE
-.br
-This generate a \fIROM\fP of 1024 words of 5 bits each, with an high impedance 
-output, and \fIlsb\fP first.
-.br
-The generated views give only the interface of the block.
-.RS
-.ie t \fC
-.el \f4
-grog 28 64 dlxm_ctl layout netlist vhdl 1.0 datasheet
-.ft R
-.RE
-.br
-This generate a \fIROM\fP of 64 words of 28 bits each, using the \fIdlxm_ctl.vbe\fP
-file as coding file, and outputs a layout, a netlist, and a datasheet with
-delay estimations for a 1.0 \fIp\fPF load on \f4f\fP output lines.
-.SH OUTPUT FILES
-.TP 20
-\fIname\fP.\f4xx\fP
-Layout and netlist views.
-For these views, the suffixes depend on the
-\f4MBK_OUT_LO\fP(1) and \f4MBK_OUT_PH\fP(1) environment variables.
-The \fIname\fP is either the one specified by the user, or an internally
-generated one prefixed by \f4r\fIwords\f4x\fIbits\fR.
-.TP
-\fIname\fP.\f4vbe\fP
-\fIvhdl\fP behavior.
-.TP
-\fIname\fP.\f4pat\fP
-Set of patterns for validation.
-.TP
-\fIname\fP.\f4dts\fP
-Datasheet.
-.SH ENVIRONMENT VARIABLES
-.TP 20
-\f4MBK_CATA_LIB\fR
-contains the directory path of the \fIROM\fR generator leaf cell library,
-\fIrolib\fR.
-This library is by default in \f4/labo/cells/grog\fR, and if not,
-depends upon the system administrator installation.
-.TP
-\f4MBK_WORK_LIB\fR
-contains the directory path of the working directory, usually set to
-\f4.\fR (dot).
-.TP
-\f4MBK_IN_PH\fR
-contains the format of the \fIROM\fR generator leaf cell library.
-.TP
-\f4MBK_OUT_PH\fR
-contains the expected format of the generated layout. 
-.TP
-\f4MBK_OUT_LO\fR
-contains the expected format of the netlist output.
-.TP
-\f4ICON_OUT\fR
-contains the expected format of the icon output.
-.SH SEE ALSO
-.BR mbk (1),
-.BR genlib (1),
-.BR rfg (1),
-.BR bsg (1),
-.BR rsa (1).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/k2f.1 b/alliance/share/man/man1/k2f.1
deleted file mode 100644
index d33aca60..00000000
--- a/alliance/share/man/man1/k2f.1
+++ /dev/null
@@ -1,28 +0,0 @@
-.TH PAT2DWL 1 "October 1, 1997" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
-.SH NAME
-.PP
-\fIk2f\fP, FSM translator ALLIANCE format from/to Berkeley format
-
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.PP
-\fBk2f\fP 
-.I In_format
-.I Out_format
-.I Input_name
-[
-.I Output_name
-]
-
-.SH DESCRIPTION
-.PP
-\fBk2f\fP is a FSM translator from ALLIANCE format (\fI".fsm"\fP)
-to Berkeley format (\fI".kiss2"\fP).
-
-.SH SEE ALSO
-.PP
-fsm(5)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/l2p.1 b/alliance/share/man/man1/l2p.1
deleted file mode 100644
index 2775d7c9..00000000
--- a/alliance/share/man/man1/l2p.1
+++ /dev/null
@@ -1,255 +0,0 @@
-.\"   $Id: l2p.1,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)l2p.l 1.03 94/Jan/30 UPMC; Author: Gilles-Eric DESCAMPS
-.pl -.4
-.TH L2P 1 "October 1, 1997" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
-.SH NAME
-.TP
-l2p
-\- Creates a PostScript file from a symbolic layout file,or from
-a physical layout file.
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.TP
-\fBl2p\fP
-[\fB-color\fP] 
-[\fB-drawingsize=<w>x<h>\fP]
-[\fB-fA3\fP] [\fB-fLETTER\fP]
-[\fB-fLEGAL\fP]
-[\fB-givebwdict\fP] [\fB-givecolordict\fP]
-[\fB-help\fP]
-[\fB-noheader\fP] 
-[\fB-papersize=<x>x<y>x<w>x<h>\fP] [\fB-pages=<x>x<y>\fP] [\fB-tsize=<s>\fP]
-[\fB-nrname\fP] [\fB-ncname\fP] [\fB-nrfname\fP] [\fB-niname\fP]
-[\fB-nsname\fP] [\fB-mfeed\fP]
-[\fB-real\fP] [\fB-resol=<x>\fP] [\fB-rflattencatal\fP] [\fB-rflattentrans\fP]
-[\fB-rotate\fP] [\fB-scale=<f.f>\fP] [\fB-usedict=<f>\fP] \fIcellname\fP
-.br
-.SH DESCRIPTION
-Two main kind of cells can be used as inputs for l2p :
-.br
-First, you can use l2p to print symbolic layout cells. File formats
-can be .ap or .cp . This is given by an environment variable
-.B MBK_IN_PH
-that gives the appropriate symbolic layout file format.
-.br
-Second, you can use l2p to print real layout cells whose file formats
-can be .cif or .gds .
-This is given by an environment variable
-.B RDS_IN
-that gives the appropriate real layout file format.
-.br
-The path to the input file is set up by two environment variables:
-\fBMBK_WORK_LIB\fP(3) and if not found 
-\fBMBK_CATA_LIB\fP(3).
-The output of \fIl2p\fP is a \fBPostScript\fP file 
-in the current directory. The drawing size and the paper size
-can be specified by the user. So, you can split your drawing
-in as many pages as wanted. The resulting file can be then
-used on any adequat \fBPostcript\fP printer.
-.br
-l2p will generate in the current directory, either a single file called
-\fI<cellname>.ps\fP, either several files suffixed by \fI-<x>x<y>.ps\fP,
-depending on wether you've asked for a monopage plot or for a drawing
-that will be splitted on several pages. 
-If you do something like
-\fIl2p -pages=2x1 cell\fP, it will generate two files called
-\fIcell-1x1.ps\fP, and \fIcell-2x1.ps\fP.
-.SH OPTIONS
-With no options, l2p generate a 'standard file', with all options off.
-This is ok for leaf cells, but not for large circuits.
-.TP
-\-color
-generates a color PostScript file for use with color interpreters.
-The default value gives a black and white \fBPostCript\fP file.
-.TP
-\-drawingsize=<width>x<height>
-specifies the drawing area in centh of inch.
-By default, wide = 725 and height = 1068 for french A4 paper. If
-the drawing size is bigger than the paper area, then the
-drawing will be splitted on several pages.
-.TP
-\-fA3
-The drawing is done on A3 format paper.
-.TP
-\-fLETTER
-The drawing is done on LETTER format paper.
-.TP
-\-fLEGAL
-The drawing is done on LEGAL format paper. 
-.TP
-\-givebwdict
-give the Black & White internal PostScript dictionnary.
-See below.
-.TP
-\-givecolordict
-This option must be unique on the  command  line.  When
-used  as  in  'l2p  -givebwdict', l2p then gives on the
-standard output its Black & White  internal  Postscript
-dictionnary.  A PostScript dictionnary is a set of mac-
-ros that will be used  during  interpretation  of  your
-PostScript file.  The macros in the internal PostScript
-dictionnaries of l2p allows you to control which  layer
-to  output,  how  to  plot  rectangles, and specify the
-colors of the rectangles. You get the standard diction-
-nary  by  a  line  of  the  form  'l2p -givecolordict >
-dict.ps'. You can then edit it, in order to reuse it 
-with l2p, see the '-usedict' option below.
-.TP
-\-help
-gives you this man page that explains how to use l2p.
-.TP
-\-noheader
-prevents the border and various info, as the cellname and the position
-of the page in the drawing, from being printed.
-.TP
-\-papersize=<x_low_left>x<y_low_left>x<width>x<height>
-specifies the paper area in centh of inch. By default, 50x50x726x1069
-for a4 paper.
-.TP
-\-pages=<number_of_x_pages>x<number_of_y_pages>
-specifies the drawing area in pages. It can be useful, instead of having
-to calculate the size in cenths of inch of the drawing, to give it in
-numbers of pages. It takes care of the resizing of the paper and whether
-there is a header.
-.TP
-\-tsize=<s>
-.br
-Available sizes:6,8,10,12,14.The default value is 8.
-.TP
-\-nrname
-.br
-No name at all will be displayed.
-.TP
-\-ncname
-The external connector's names won't be displayed.
-.TP
-\-nrfname
-The references's names won't be displayed.
-.TP
-\-niname
-The instances's names won't be displayed.
-.TP
-\-nsname
-The segments's names won't be displayed.
-.TP
-\-mfeed
-Manualfeed:if set,informs the printer that it will be fed by the
-user himself,for each printing .
-.TP
-\-real
-uses real file (cif, gds). By default, uses 
-symbolic layout file (ap, cp).
-.TP
-\-resol=<x>
-is the resolution of the file in dots per inch (dpi). This value has been
-introducted to limitate the size of the generated PostScript files. Each
-rectangle whose width and height are smaller than the resolution will not
-be printed. The default value is 72dpi. It should only be changed in one
-specifical case : when you want to produce a plot
-of several meter large. Usually, you must provide
-a PostScript file sized for A4 paper with
-a much better resolution
-than 72dpi. You can then increase that value to up to 1000dpi, but be
-aware that the size of the file will probably be bigger than a 44Mb SyQuest
-cartridge that is used in PAO for exchanging data files.
-.TP
-\-rflattencatal
-flattens the cell to the catalog level. see catal(5) for more details
-on the use of the catalog file. Be careful, this option requires a lot of memory...
-.TP
-\-rflattentrans
-flattens the cell to the transistor level before printing. Be careful, this option
-requires a lot more memory...
-.TP
-\-rotate
-rotate the cell from 90 degree. This is useful if you have a wide cell, and you
-want to have it printed in landscape mode.
-.TP
-\-scale=<f.f>
-forces the cell to be printed with a certain scale (a floating-point number).
-This is very useful, when you are printing a whole library of cells,
-and you want all cells to be printed to the same scale.
-.br
-You can find at which scale a cell was printed by looking at the beginning of
-the file : 'head n1_y-1x1.ps' will show you a PostScript comment beginning
-by '%SCALE=3.78435' for example.
-.TP
-\-usedict=<filename>
-The output Postcript file contains a Postcript dictionnary of macros.
-.br
-There are two standard dictionnaries used by l2p for black and white or color prints.
-This allows you to use a PostScript dictionnary different from the two
-internally encoded into l2p. By modifying one of the standard l2p 
-dictionnary, you can choose which layer to output, how to fill the
-rectangles (empty, hashed, filled), which color to choose, ... and
-lots of other possibilities. The rest of the generated postscript file
-is mainly orders of drawing rectangles. PostScript is a reverse polish
-notation langage, that is easy to read for simple programs.
-.br
-If you use this functionnality, and think that your dictionnaries are
-worth it, please mail them to alliance\-support@asim.lip6.fr, in order to submit
-them for inclusion in future version of l2p (Thanks).
-
-.SH ENVIRONMENT VARIABLES:
-.TP
-for symbolic file(s) :
-.nf
-\fBsetenv MBK_IN_PH ap
-setenv MBK_WORK_LIB .
-setenv MBK_CATA_LIB /labo/cells/scr
-setenv MBK_CATAL_NAME CATAL
-setenv RDS_TECHNO_NAME cmos_1.rds\fP
-.fi
-.TP
-for real file(s) :
-.nf
-\fBsetenv RDS_IN cif
-setenv MBK_CATAL_NAME CATAL_ROUT
-setenv RDS_TECHNO_NAME prol12_1.rds\fP
-.fi
-
-.SH EXAMPLES:
-.TP
-\fIl2p -color n1_y\fP
-will create a colored \fBn1_y.ps\fP file in the current directory :
-the 'standard' way.
-.TP
-\fIl2p -real cell\fP
-will create a \fBcell.ps\fP file in the current directory from cell.cif
-or cell.gds, depending on the RDS_IN environment variable.
-.TP
-\fIl2p -pages=3x2 na2_y\fP
-size of the created drawing:3 horizontal pages,2 vertical ones;
-.TP
-
-.SH SEE ALSO
-.BR mbk(1),
-.BR rds(1),
-.BR MBK_IN_PH(3),
-.BR MBK_CATA_LIB(3),
-.BR MBK_WORK_LIB(3),
-.BR MBK_CATAL_NAME(3),
-.BR RDS_TECHNO_NAME(3),
-.BR pageview(1),
-.BR gs(1),
-.BR ghostview(1),
-.BR lpr(1).
-
-.SH DIAGNOSTICS
-.br
-You will not be able to generate more than approximativly 30 pages at the same
-time (because of the FOPEN_MAX of your environment). In this case, see the
-option that is not implemented yet.
-.br
-The generated \fBPostScript\fP is Level 1 for black& white plots.
-When you use color, it generates Level 1 with color extensions.
-It may not run with strict Level 1 interpreters, although it runs here with
-our Apple Personnal LaserWriter, Sun Sparcprinters, and Canon CLC-300-PS.
-It follows the Adobe Document Structuring Conventions 1, and as there
-is a fake bitmap image inside each generated files, you can re-use them in your
-word-processors, or publishing software, because the PostScript is EPSF-1.2
-compliant.
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/librds.1 b/alliance/share/man/man1/librds.1
deleted file mode 100644
index 0d863345..00000000
--- a/alliance/share/man/man1/librds.1
+++ /dev/null
@@ -1,767 +0,0 @@
-.\"   $Id: librds.1,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)librds.1 0.0 93/18/08 UPMC
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-librds
-.XE
-.XS0 \n%
-.ti 0.2i
-librds
-.XE0 \}
-.TH LIBRDS 1 "October 1, 1997" "ASIM/LIP6" "RDS LIBRARY VERSION 202"
-.SH NAME
-librds \- rds library description
-.SH DESCRIPTION
-.IP
-.IP I)
-DATA STRUCTURES USED
-.RS
-.IP A)
-rdsrec_list structure
-.PP
-The rdsrec_list structure is used to describe a rectangle which belongs to a symbolic figure.
-.PP
-The following C structure supports the description of a rectangle :
-.PP
-.RS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.ta 3n 20n 30n
-typedef struct rdsrec_list
-     {
-        struct  rdsrec_list     \(**NEXT;
-        long                     X;
-        long                     Y;
-        long                     DX;
-        long                     DY;
-        long                     FLAGS;
-        char                    \(**NAME;
-        void                    \(**USER;
-     } rdsrec_list;
-.ft R
-.fi
-.RE
-.PP
-Description of the structure's fields :
-.TP
-\fINEXT\fP :
-Pointer to the next rectangle whitch belongs to the list of rectangles.
-.TP
-\fIX,Y\fP :
-Coordinates of one of the extremities of the rectangle.
-.TP
-\fIDX,DY\fP :
-Width and lenght of the rectangle ; fixes the position of the second extremity of the rectangle.
-.TP
-\fIFLAGS\fP :
-32 bits flag; contains informations about the rectangle.
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-31..........................17.16..............................0
-|X|X|X|X|X|X|X|X|X|X|X|X|X|X|X|X|X|X|X|X|X|X|X|X|X|X|X|X|X|X|X|X| 
-|-----------------------------|-|-|-----|-------|---------------|
-    reserved for user          ^ ^ type   object      Layer
-			       | |
-			       | figure/instance     
-			       |
-			       one/many window(s)
-.ft R
-.fi
-.TP
-\fI\- first 8 bits (0 to 7)\fP
-reserved to code the layer, constants used to code the layer can take the values as follows (defined in rdsnnn.h) :
-RDS_NWELL, RDS_PWELL, RDS_ACTIV, RDS_NIMP,    
-RDS_PIMP, RDS_NDIF, RDS_PDIF, RDS_NTIE,    
-RDS_PTIE, RDS_POLY, RDS_GATE, RDS_TPOLY,   
-RDS_CONT, RDS_ALU1, RDS_TALU1, RDS_VIA1,    
-RDS_ALU2, RDS_TALU2, RDS_VIA2, RDS_ALU3,    
-RDS_TALU3, RDS_VIA3, RDS_ALU4, RDS_VIA4,    
-RDS_CPAS, RDS_PPOL, RDS_REF, RDS_USER0,   
-RDS_USER1, RDS_USER2, RDS_ABOX    
-.TP
-\fI\- 4 next bits\fP
-MBK object which belongs the rectangle, constants used to code the object can take the values as follows (defined in rfmnnn.h) :
-MBK_CONNECTOR,  MBK_SEGMENT,   MBK_REFERENCE,
-MBK_VIA,        MBK_INSTANCE,  MBK_FIGURE
-.TP
-\fI\- 3 next bits\fP
-complementary information about connectors and references objects, constants used to code these bits can take the values as follows (defined in rfmnnn.h) :
-.PP
-RDS_CON_EXTER, RDS_CON_INTER : external/internal connector ;
-.br
-RDS_REF_REF, RDS_REF_CON : reference type.
-.TP
-\fI\- next bit
-Determine if the rectangle belongs to a figure or an instance. The constant used to code this bit can take the value as follows (defined in rfmnnn.h) :
-.IP
-RDS_FIG_REC
-.TP
-\fI\- next bit
-Determine if the rectangle belongs to one or many windows. The constant used to code this bit can take the value as follows (defined in rwinnn.h) :
-.IP
-RDS_ONE_WINDOW
-.PP
-\- \fIthe 15 bits\fP remaining are free and can be used by the user.
-.TP
-\fINAME\fP :
-rectangle's name 
-.TP
-\fIUSER\fP :
-not used in RDS library. It's used in RFM library and RWI library.If the user wants to use both libraries, he has to save (in an added structure to the rdsrec_list structure, for example) the USER field after calling the functions of one of the two libraries. In RFM library, the field USER is used to chain rectangles belonging to a same object. In RWI library, the field USER is used know the windows which contains the rectangle.
-.IP B)
-rdsins_list structure
-.PP
-The rdsins_list structure is used to describe an instance which belongs to a symbolic figure.
-.PP
-The following C structure supports the description of an instance :
-.PP
-.RS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.ta 3n 20n 30n
-typedef struct rdsins_list
-     {
-        struct rdsins_list \(**NEXT;
-        char               \(**FIGNAME;
-        char               \(**INSNAME;
-        long                X;
-        long                Y;
-        char                TRANSF;
-        unsigned int        SIZE;
-        struct rdsrec_list \(**LAYERTAB[ RDS_MAX_LAYER ];
-        struct rdsrec_list \(**COURONNE[ RDS_MAX_LAYER ];
-        void               \(**USER;
-     } rdsins_list;
-.ft R
-.fi
-.RE
-.PP
-Description of the structure's fields :
-.TP
-\fINEXT\fP :
-Pointer to the next instance whitch belongs to the list of instances.
-.TP 
-\fIFIGNAME\fP :
-Model's name of the instance.
-.TP
-\fIINSNAME\fP :
-Instance name in the figure of higher hierarchical level.
-.TP
-\fIX,Y\fP :
-Position of the lower left corner of instance after geometrical transformation.
-.TP
-\fITRANSF\fP :
-Geometrical transformation applied to the instance before placing.
-.PP
-The field TRANSF can take these values :
-.RS
-.TP 20
-\fIRDS_NOSYM\fP 
-no symmetry.
-.TP
-\fIRDS_ROT_P\fP 
-90 degrees rotation counter clockwise.
-.TP
-\fIRDS_SYMXY \fP
-Symmetry with regard to a horizontal and vertical axis.
-.TP
-\fIRDS_ROT_M\fP 
-90 degrees rotation clockwise.
-.TP
-\fIRDS_SYM_X\fP 
-Symmetry with regard to a vertical axis.
-.TP
-\fIRDS_SY_RM\fP 
-Symmetry with regard to a vertical axis and 90 degrees clockwise.
-.TP
-\fIRDS_SYM_Y\fP 
-Symmetry with regard to a horizontal axis.
-.TP
-\fIRDS_SY_RP\fP 
-Symmetry with regard to a horizontal axis and 90 degrees rotation counter clockwise.
-.RE
-.TP
-\fISIZE\fP : 
-Size of the user structure which can be added to a rdsrec_list structure.
-.TP
-\fILAYERTAB [RDS_MAX_LAYER]\fP :
-Table of layers which contains rectangle's list associated to each layer. 
-.TP
-\fICOURONNE [RDS_MAX_LAYER]\fP :
-Specific field used by some tools. Table of layers which contains rectangle's list associated to each layer. These rectangles compose the instance's perimeter. 
-.IP C) 
-rdsfig_list structure
-.PP
-The rdsfig_list structure is used to describe a hierarchical level of a symbolic figure.
-.PP
-The following C structure supports the description of a figure :
-.PP
-.RS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.ta 3n 20n 30n
-typedef struct rdsfig_list
-     {
-        struct rdsfig_list   \(**NEXT;
-        char                 \(**NAME;
-        struct rdsrec_list   \(**LAYERTAB[ RDS_MAX_LAYER ];
-        struct rdsins_list   \(**INSTANCE;
-        char                  MODE;
-        unsigned int          SIZE;
-        char                  FLAGTAB[ RDS_MAX_LAYER ];
-        struct rdsrec_list   \(**BBOXTAB[ RDS_MAX_LAYER ];
-        void                 \(**USER;
-     } rdsfig_list;
-.ft R
-.fi
-.RE
-.PP
-Description of the structure's fields :
-.TP
-\fINEXT\fP :
-Pointer to the next figure of figure's list.
-.TP
-\fINAME\fP :  
-Name of the figure : it identifies the figure so it must be unique and identical to the filename which describes the figure on disk.
-.TP
-\fILAYERTAB [RDS_MAX_LAYER]\fP : 
-Table of layers which contains rectangle's list associated to each layer. 
-.TP
-\fIINSTANCE\fP : 
-Pointer to the head of the list of instances of the figure.
-.TP
-\fIMODE\fP :   
-Caracter indicating the status of the figure in memory. 
-.PP
-This field can take three values : 
-.RS
-.TP
-\fI\'A\'\fP 
-All the cell is loaded in ram (The figure, its rectangles and its instances empty).
-.TP
-\fI\'P\'\fP 
-Only information concerning the model interface is present, that means : connectors, the abutment box and through routes of the figure.
-.TP
-\fI\'V\'\fP
-Visualization mode : all is loaded in RAM : The figure, its rectangles, its instances and the rectangles of its instances. 
-.RE
-.TP
-\fISIZE\fP :   
-Size of the user structure which can be added to a rdsrec_list structure.
-.TP
-\fIFLAGTAB[RDS_MAX_LAYER]\fP :  
-This is a table of flags associated to each layer. This table is free for the user.
-.TP
-\fIBBOXTAB[RDS_MAX_LAYER]\fP : 
-This table is used to contain the bounding box of a circuit by layer (It is used by the s2r tool).
-.TP
-\fIUSER\fP :  
-Pointer free for the user.
-.RE
-.IP II)  
-Description of global variables and constants of the library
-.RS
-.IP A) 
-Constants of the library
-.TP
-\fIRDS_MAX_TRANSF\fP  
-Maximum number of possible geometrical transformations applied to an instance (defines the size of the table RDS_TRANSF_NAME[]).
-.TP
-\fIRDS_MAX_LAYER\fP   
-Maximum number of layers defined in RDS library (defines the size of the table RDS_LAYER_NAME).
-.TP
-\fIRDS_ALLOC_BLOCK\fP 
-Used in rdsalloc function to set a BLOCK allocation. 
-.TP        
-\fIRDS_ALLOC_HEAP\fP  
-Used in rdsalloc function to set a HEAP allocation.
-.TP
-\fITransformation constants\fP
-RDS_NOSYM, RDS_ROT_P, RDS_SYMXY, RDS_ROT_M, RDS_SYM_X, RDS_SY_RM, RDS_SYM_Y, RDS_SY_RP :
-.IP
-define the transformation to apply to an instance (see rdsins_list structure).
-.TP
-\fILayer constants\fP
-RDS_NWELL, RDS_PWELL, RDS_NDIF, RDS_PDIF, RDS_NTIE, RDS_PTIE, RDS_POLY, RDS_GATE, RDS_TPOLY, RDS_CONT, RDS_ALU1, RDS_TALU1, RDS_VIA1, RDS_ALU2, RDS_TALU2, RDS_VIA2, RDS_ALU3, RDS_TALU3, RDS_ACTIV, RDS_NIMP, RDS_PIMP, RDS_REF, RDS_USER0, RDS_USER1, RDS_USER2, RDS_ABOX :
-.TP
-\fIMBK_CONNECTOR\fP
-Represents object type of the field \'FLAGS\' of the rdsrec_list structure which is a MBK connector.
-.TP
-\fIMBK_SEGMENT\fP
-Represents object type of the field \'FLAGS\' of the rdsrec_list structure which is a MBK segment.
-.TP
-\fIMBK_REFERENCE\fP
-Represents object type of the field \'FLAGS\' of the rdsrec_list structure which is a MBK reference.
-.TP
-\fIMBK_VIA\fP
-Represents object type of the field \'FLAGS\' of the rdsrec_list structure which is a MBK contact.
-.TP
-\fIMBK_INSTANCE\fP
-Represents object type of the field \'FLAGS\' of the rdsrec_list structure which is a MBK instance.
-.TP
-\fIMBK_FIGURE\fP
-Represents object type of the field \'FLAGS\' of the rdsrec_list structure which is a MBK figure.
-.TP
-\fIMBK_TYPE\fP
-Mask of the field \'FLAGS\' of the rdsrec_list structure which permits to get object type.(see librds).
-.TP
-\fIRDS_FIG_REC\fP
-Represents the bit of the field \'FLAGS\' of the rdsrec_list structure that means if the rectangle belongs to a figure or to an instance.
-.TP
-\fIRDS_CON_EXTER\fP
-Represents the type of the MBK connector of the field \'FLAGS\' of the rdsrec_list structure (external connector).
-.TP
-\fIRDS_CON_INTER\fP
-Represents the type of the MBK connector of the field \'FLAGS\' of the rdsrec_list structure (internal connector).
-.TP 
-\fIRDS_REF_REF\fP
-Represents the type of the MBK reference of the field \'FLAGS\' of the rdsrec_list structure (ref_ref reference).
-.TP
-\fIRDS_REF_CON\fP
-Represents the type of the MBK reference of the field \'FLAGS\' of the rdsrec_list structure (ref_con reference).
-.TP
-\fIRDS_EXTRACT_TYPE\fP
-Mask of the field \'FLAGS\' of the rdsrec_list structure which permits to get additionnal object type (for a reference or a connector).
-.IP
-Constants associated to the possible layers.
-.IP B) 
-Global variables
-.PP
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.ta 3n 20n 30n
-\fIrdsfig_list \(**HEAD_RDSFIG;\fP
-.ft R
-.fi
-.PP
-HEAD_RDSFIG is a pointer to the head of the list of figures in memory.
-.PP
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.ta 3n 20n 30n
-\fIchar RDS_LAYER_NAME [ RDS_MAX_LAYER ] [ 12 ]\fP =
-       {
-         "RDS_NWELL  ",
-         "RDS_PWELL  ",
-         "RDS_ACTIV  ",
-         "RDS_NINP   ",
-         "RDS_PINP   ",
-         "RDS_NDIF   ",
-         "RDS_PDIF   ",
-         "RDS_NTIE   ",
-         "RDS_PTIE   ",
-         "RDS_POLY   ",
-         "RDS_GATE   ",
-         "RDS_TPOLY  ",
-         "RDS_CONT   ",
-         "RDS_ALU1   ",
-         "RDS_TALU1  ",
-         "RDS_VIA1   ",
-         "RDS_ALU2   ",
-         "RDS_TALU2  ",
-         "RDS_VIA2   ",
-         "RDS_ALU3   ",
-         "RDS_TALU3  ",
-         "RDS_VIA3   ",
-         "RDS_ALU4   ",
-         "RDS_VIA4   ",
-         "RDS_CPAS   ",
-         "RDS_PPOL   ",
-         "RDS_REF    ",
-         "RDS_USER0  ",
-         "RDS_USER1  ",
-         "RDS_USER2  ",
-         "RDS_ABOX   "
-       };
-.ft R
-.fi
-.PP
-The \fBRDS_LAYER_NAME\fP table contains names of possible layers of a rectangle. May be used when debugging a programme.
-.PP
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.ta 3n 20n 30n
-\fIchar RDS_TRANSF_NAME [ RDS_MAX_TRANSF ][ 8 ]\fP =
-       {
-         "NOSYM",
-         "ROT_P",
-         "SYMXY",
-         "ROT_M",
-         "SYM_X",
-         "SY_RM",
-         "SYM_Y",
-         "SY_RP"
-       };
-.ft R
-.fi
-.PP
-The \fBRDS_TRANSF_NAME\fP table contains names of possible transformations of an instance. May be used when debugging a programme.
-.RE
-.IP III) 
-Description of the macros
-.PP
-\-  char GetRdsLayer( Rectangle )
-.br
-    rdsrec_list \(**Rectangle;
-.RS
-.PP
-\fBGetRdsLayer\fP function gets the layer associated to the rectangle by testing the field FLAGS of the rdsrec_list structure.The returned value corresponds to the following layers :
-.RE
-.PP
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.ta 3n 20n 30n
-.RS
-0   -> RDS_NWELL   
-1   -> RDS_PWELL   
-2   -> RDS_ACTIV   
-3   -> RDS_NIMP    
-4   -> RDS_PIMP    
-5   -> RDS_NDIF    
-6   -> RDS_PDIF    
-7   -> RDS_NTIE    
-8   -> RDS_PTIE    
-9   -> RDS_POLY    
-10  -> RDS_GATE    
-11  -> RDS_TPOLY   
-12  -> RDS_CONT    
-13  -> RDS_ALU1    
-14  -> RDS_TALU1   
-15  -> RDS_VIA1    
-16  -> RDS_ALU2    
-17  -> RDS_TALU2   
-18  -> RDS_VIA2    
-19  -> RDS_ALU3    
-20  -> RDS_TALU3   
-21  -> RDS_VIA3    
-22  -> RDS_ALU4    
-23  -> RDS_VIA4    
-24  -> RDS_CPAS    
-25  -> RDS_PPOL    
-26  -> RDS_REF     
-27  -> RDS_USER0   
-28  -> RDS_USER1   
-29  -> RDS_USER2   
-30  -> RDS_ABOX    
-.RE
-.ft R
-.fi
-.PP
-Where the names "RDS_XXXXX" are some constants defined in the file "rdsnnn.h".
-.PP
-\-  void SetRdsLayer( Rectangle, Layer )
-.br
-    rdsrec_list \(**Rectangle;
-.br
-    char         Layer;
-.RS
-.PP
-The \fBSetRdsLayer\fP function sets in the FLAGS field of rdsrec_list structure the layer associated to the rectangle.
-.RE
-.PP
-Macros for testing rectangle type :
-.PP
-\-  char IsRdsConnector( Rectangle )
-.br
-    rdsrec_list \(**Rectangle;
-.RS
-.PP
-Tests if the rectangle is a MBK connector :
-.br
-If true, then value 1 is returned else value 0 is returned.
-.RE
-.PP
-\-  char IsRdsConExter( Rectangle )
-.br
-    rdsrec_list \(**Rectangle;
-.RS
-.PP
-Tests if the rectangle is an external MBK connector :
-.br
-If true, then value 1 is returned else value 0 is returned.
-.RE
-.PP
-\-  char IsRdsConInter( Rectangle )
-.br
-    rdsrec_list \(**Rectangle;
-.RS
-.PP
-Tests if the rectangle is an internal MBK connector :
-.br
-If true, then value 1 is returned else value 0 is returned.
-.RE
-.PP
-\-  char IsRdsSegment( Rectangle )
-.br
-    rdsrec_list \(**Rectangle;
-.RS
-.PP
-Tests if the rectangle is a MBK segment :
-.br
-If true, then value 1 is returned else value 0 is returned.
-.RE
-.PP
-\-  char IsRdsReference( Rectangle )
-.br
-    rdsrec_list \(**Rectangle;
-.RS
-.PP
-Tests if the rectangle is a MBK reference :
-.br
-If true, then value 1 is returned else value 0 is returned.
-.RE
-.PP
-\-  char IsRdsRefRef( Rectangle )
-.br
-    rdsrec_list \(**Rectangle;
-.RS
-.PP
-Tests if the rectangle is a Ref_Ref MBK reference :
-.br
-If true, then value 1 is returned else value 0 is returned.
-.RE
-.PP
-\-  char IsRdsRefCon( Rectangle )
-.br
-    rdsrec_list \(**Rectangle;
-.RS
-.PP
-Tests if the rectangle is a Ref_Con MBK reference :
-.br
-If true, then value 1 is returned else value 0 is returned.
-.RE
-.PP
-\-  char IsRdsVia( Rectangle )
-.br
-    rdsrec_list \(**Rectangle;
-.RS
-.PP
-Tests if the rectangle is a MBK contact :
-.br
-If true, then value 1 is returned else value 0 is returned.
-.RE
-.PP
-\-  char IsRdsInstance( Rectangle )
-.br
-    rdsrec_list \(**Rectangle;
-.RS
-.PP
-Tests if the rectangle is an MBK instance :
-.br
-If true, then value 1 is returned else value 0 is returned.
-.RE
-.PP
-\-  char IsRdsFigure( Rectangle )
-.br
-    rdsrec_list \(**Rectangle;
-.RS
-.PP
-Tests if the rectangle is a MBK figure :
-.br
-If true, then value 1 is returned else value 0 is returned.
-.RE
-.PP
-\-  char IsRdsFigRec( Rectangle )
-.br
-    rdsrec_list \(**Rectangle;
-.RS
-.PP
-Tests if the rectangle belongs to  a MBK figure :
-.br
-If true, then value 1 is returned else value 0 is returned (it belongs to an instance).
-.RE
-.PP
-Macros for setting rectangle type :
-.PP
-.PP
-\-  void SetRdsConnector( Rectangle )
-.br
-    rdsrec_list \(**Rectangle;
-.RS
-.PP
-Sets rectangle type as a \fBconnector\fP.
-.RE
-.PP
-\-  void SetRdsConExter( Rectangle )
-.br
-    rdsrec_list \(**Rectangle;
-.RS
-.PP
-Sets connector type as \fBexternal\fP connector. Uses the RDS_CON_EXTER constant in the field \'FLAGS\' of rdsrec_list structure.
-.RE
-.PP
-\-  void SetRdsConInter( Rectangle )
-.br
-    rdsrec_list \(**Rectangle;
-.RS
-.PP
-Sets connector type as \fBinternal\fP connector. Uses the RDS_CON_INTER constant in the field \'FLAGS\' of rdsrec_list structure.
-.RE
-.PP
-\-  void SetRdsSegment( Rectangle )
-.br
-    rdsrec_list \(**Rectangle;
-.RS
-.PP
-Sets rectangle type as a segment.
-.RE
-.PP
--  void SetRdsReference( Rectangle )
-.br
-    rdsrec_list \(**Rectangle;
-.RS
-.PP
-Sets rectangle type as a reference.
-.RE
-.PP
-\-  void SetRdsRefRef( Rectangle )
-.br
-    rdsrec_list \(**Rectangle;
-.RS
-.PP
-Sets reference type as \fBREF_REF\fP reference. Uses the RDS_REF_REF constant in the field \'FLAGS\' of rdsrec_list structure.
-.RE
-.PP
-\-  void SetRdsRefCon( Rectangle )
-.br
-    rdsrec_list \(**Rectangle;
-.RS
-.PP
-Sets reference type as \fBREF_CON\fP reference. Uses the RDS_REF_CON constant in the field \'FLAGS\' of rdsrec_list structure.
-.RE
-.PP
-\-  void SetRdsVia( Rectangle )
-.br
-    rdsrec_list \(**Rectangle;
-.RS
-.PP
-Sets the rectangle type as a contact.
-.RE
-.PP
-\-  SetRdsInstance( Rectangle )
-.br
-    rdsrec_list \(**Rectangle;
-.RS
-.PP
-Sets the rectangle type as an instance.
-.RE
-.PP
-\-  SetRdsFigure( Rectangle )
-.br
-    rdsrec_list \(**Rectangle;
-.RS
-.PP
-Sets the rectangle type as a figure.
-.RE
-.PP
-\-  SetRdsFigRec( Rectangle )
-.br
-    rdsrec_list \(**Rectangle;
-.RS
-.PP
-Sets the rectangle type as belonging to a figure.
-.RE
-.PP
-\-  ClearRdsFigRec( Rectangle )
-.br
-    rdsrec_list \(**Rectangle;
-.RS
-.PP
-Sets the rectangle type as not belonging to a figure.It can be used to mean that the rectangle belongs to an instance.
-.RE
-.IP VI) 
-Functions of LibRds library
-.TP
-\fIrdsalloc\fP     
-memory allocation
-.TP
-\fIrdsfree\fP      
-memory freeing 
-.TP
-\fIallocrdsfig\fP  
-allocates memory for a figure
-.TP
-\fIallocrdsins\fP  
-allocates memory for an instance
-.TP  
-\fIallocrdsrec\fP  
-allocates memory for a rectangle
-.TP
-\fIfreerdsfig\fP   
-frees memory of a figure
-.TP
-\fIfreerdsins\fP   
-frees memory of an instance
-.TP
-\fIfreerdsrec\fP   
-frees memory of a rectangle
-.TP
-\fIaddrdsfig\fP    
-adds a figure to the head of figures's list
-.TP
-\fIaddrdsins\fP    
-adds an instance to the head of instances's list of a figure 
-.TP
-\fIaddrdsinsrec\fP 
-adds a rectangle in an instance
-.TP
-\fIaddrdsfigrec\fP 
-adds a rectangle in a figure
-.TP
-\fIdelrdsfig\fP    
-deletes a figure and the objects contained in it
-.TP
-\fIdelrdsins\fP    
-deletes an instance and the objects contained in it
-.TP
-\fIdelrdsinsrec\fP 
-deletes a rectangle in an instance
-.TP
-\fIdelrdsfigrec\fP 
-deletes a rectangle in a figure
-.TP
-\fIviewrdsrec\fP   
-displays caracteristics of a rectangle
-.TP
-\fIviewrdsins\fP   
-displays caracteristics of an instance
-.TP
-\fIviewrdsfig\fP   
-displays caracteristics of a figure
-.RE
-.SH SEE ALSO
-.BR librfm,
-.BR librpr,
-.BR librut,
-.BR librtl,
-.BR librwi
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/librfm.1 b/alliance/share/man/man1/librfm.1
deleted file mode 100644
index 5acc92e8..00000000
--- a/alliance/share/man/man1/librfm.1
+++ /dev/null
@@ -1,105 +0,0 @@
-.\"   $Id: librfm.1,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)librfm.1 0.0 93/18/08 UPMC
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-librfm
-.XE
-.XS0 \n%
-.ti 0.2i
-librfm
-.XE0 \}
-.TH LIBRFM 1 "October 1, 1997" "ASIM/LIP6" "RDS LIBRARY VERSION 202"
-.SH NAME
-librfm \- rfm library description
-.SH DESCRIPTION
-.IP I)
-Description of the macros
-.PP
-\-  long RfmRoundLow(X)
-.br
-    long X;
-.RS
-.PP
-Permits to get the lower grid step of the value \'X\' in parameter.
-.RE
-.PP
-\-  long RfmRoundHigh(X)
-.br
-    long X;
-.RS
-.PP
-Permits to get the higher grid step of the value \'X\' in parameter.
-.RE
-.IP II)
-Functions of Rfm library
-.TP
-\fIsegmbkrds\fP
-Converts a MBK segment to RDS segment.
-.TP
-\fIviambkrds\fP
-Converts a MBK contact to RDS contact.
-.TP
-\fIrefmbkrds\fP
-Converts a MBK reference to RDS reference.
-.TP
-\fIconmbkrds\fP
-Converts a MBK connector to RDS connector.
-.TP
-\fIaboxmbkrds\fP
-Converts a MBK abutment box to RDS abutment box.
-.TP
-\fIinsconmbkrds\fP
-Converts all MBK connectors of an MBK instance to RDS connectors of RDS instance corresponding.
-.TP
-\fIinsrefmbkrds\fP
-Converts all MBK references of an MBK instance to RDS references of RDS instance corresponding.
-.TP
-\fIinssegmbkrds\fP
-Converts all MBK segments of an MBK instance to RDS segments of RDS instance corresponding.
-.TP
-\fIinsmbkrds\fP
-Converts an MBK instance to RDS instance.
-.TP
-\fIfigmbkrds\fP
-Converts a MBK figure to RDS figure.
-.TP
-\fImodelmbkrds\fP
-Gets list of models contained in a figure
-.TP
-\fIviewrfmrec\fP
-Displays caracteristics of an object using a rectangle of this object.
-.TP
-\fIviewrfmseg\fP
-Displays caracteristics of a segment to MBK and RDS format.
-.TP
-\fIviewrfmvia\fP
-Displays caracteristics of a contact to MBK and RDS format.
-.TP
-\fIviewrfmref\fP
-Displays caracteristics of a reference to MBK and RDS format.
-.TP
-\fIviewrfmcon\fP
-Displays caracteristics of a connector to MBK and RDS format.
-.TP
-\fIviewrfmins\fP
-Displays caracteristics of an instance to MBK and RDS format.
-.TP
-\fIviewrfmfig\fP
-Displays caracteristics of a figure to MBK and RDS format.
-.TP
-\fIroundrdsrec\fP
-adjusts a rectangle to lambda grid step.
-.ft R
-.fi
-.SH SEE ALSO
-.BR librds,
-.BR librpr,
-.BR librtl,
-.BR librut,
-.BR librwi
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/librpr.1 b/alliance/share/man/man1/librpr.1
deleted file mode 100644
index e847f913..00000000
--- a/alliance/share/man/man1/librpr.1
+++ /dev/null
@@ -1,130 +0,0 @@
-.\"   $Id: librpr.1,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)librpr.1 0.0 93/18/08 UPMC
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-librpr
-.XE
-.XS0 \n%
-.ti 0.2i
-librpr
-.XE0 \}
-.TH LIBRPR 1 "October 1, 1997" "ASIM/LIP6" "RPR LIBRARY VERSION 203"
-.SH NAME
-librpr \- rpr library description
-.SH DESCRIPTION
-.IP
-.IP I)
-Description of global variables and constants of the library
-.RS
-.IP A)
-Constants
-.TP
-\fBRDS_SEGMENT_EMPTY\fP :
-This value is returned by the \fIGET_SEGMENT_LAYER\fP macro to mean the end of the layer list returned.
-.TP
-\fBRDS_VIA_EMPTY\fP :
-This value is returned by the \fIGET_VIA_LAYER\fP macro to mean the end of the layer list returned.
-.PP
-.IP B)
-Global variables
-.PP
-long   \fBRDS_PHYSICAL_GRID\fP;
-.PP
-Some technolgies demand the layout to respect a physical grid. It means that all coordinates have to be a multiple of the physical grid value.
-.PP
-long   \fBRDS_LAMBDA\fP;
-.PP
-The RDS_LAMBDA value is the unity of base in which are described RDS objects (rectangles, instances, figures). This value permits to be technology independant. One Lambda units corresponds to a value explained in micro-meter.
-.PP
-long   \fBRDS_LAMBDA2\fP;
-.PP
-The RDS_LAMBDA2 is a surface unit which represents the RDS_LAMBDA value squared.
-.RE
-.IP II)
-Description of the macros
-.PP
-\- char GET_SEGMENT_LAYER( Layer, Index )
-.br
-    char Layer;
-.br
-    char Index;
-.RS
-.PP
-The \fBGET_SEGMENT_LAYER\fP macro gets all the RDS layers which compose a MBK segment. The returned value is a RDS layer or the \fBRDS_SEGMENT_EMPTY\fP value if there is no layer anymore.
-.PP
-\fIExample\fP :
-.PP
-Layer = POLY; /\(** MBK segment \(**/
-.br
-Index = 0;
-.br
-while ( LayerRds != RDS_SEGMENT_EMPTY )
-.br
- {
-.br
-   LayerRds  = GET_SEGMENT_LAYER( Layer, Index );
-.br
-
-.br
-   /\(** Treatment ... \(**/
-.br
-
-.br
-   Index = Index + 1;
-.br
- }
-.PP
-.RE
-\- char GET_VIA_LAYER( Layer, Index )
-.br
-    char Layer;
-.br
-    char Index;
-.RS
-.PP
-The \fBGET_VIA_LAYER\fP macro gets all the RDS layers which compose a MBK contact. The returned value is a RDS layer or the \fBRDS_VIA_EMPTY\fP value if there is no layer anymore.
-.PP
-\fIExample\fP :
-.PP
-Layer = CONT_VIA; /\(** MBK contact \(**/
-.br
-Index = 0;
-.br
-while ( LayerRds != RDS_VIA_EMPTY )
-.br
- {
-.br
-   LayerRds  = GET_VIA_LAYER( Layer, Index );
-.br
-
-.br
-   /\(** Treatment ... \(**/
-.br
-
-.br
-   Index = Index + 1;
-.br
- }
-.RE
-.IP III)
-Function of the libRpr library
-.TP
-\fBloadrdsparam\fP
-This function loads parameters contained in a file with extention ".rds" which is the translation file from symbolic to real. Some of these files are contained in the path "/labo/etc".See them for more information.
-.TP
-\fBviewrdsparam\fP
-This function displays all the tables in memory filled with the loadrdsparam function.
-.SH SEE ALSO
-.BR librds,
-.BR librfm,
-.BR librut,
-.BR librtl,
-.BR librwi,
-.BR phvia,
-.BR phseg
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/librtl.1 b/alliance/share/man/man1/librtl.1
deleted file mode 100644
index a1b18c48..00000000
--- a/alliance/share/man/man1/librtl.1
+++ /dev/null
@@ -1,60 +0,0 @@
-.\"   $Id: librtl.1,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)librtl.1 0.0 93/18/08 UPMC
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-librtl
-.XE
-.XS0 \n%
-.ti 0.2i
-librtl
-.XE0 \}
-.TH LIBRTL 1 "October 1, 1997" "ASIM/LIP6" "RTL LIBRARY VERSION 102"
-.SH NAME
-librtl \- rtl library description
-.SH DESCRIPTION
-.IP I)
-Description of global variables of the library
-.RS
-.TP
-\fIRDS_IN\fP
-File input format used by the RDS parser. Two formats are possible : cif and gds.
-.TP
-\fIRDS_OUT\fP
-File output format generated by the RDS driver. Two formats are possible : cif and gds.
-.TP
-\fIRDS_TECHNO_NAME\fP
-Environment variable which contains acces path to the technology file with extension ".rds". This file contains definition and caracteristics of the layers used by RDS structure.
-.RE
-.IP II)                     
-The LibRtl functions
-.RS
-.TP
-\fIrdsenv\fP
-set user preferences
-.TP
-\fIloadrdsfig\fP
-Loads a figure from disk
-.TP
-\fIsaverdsfig\fP
-Save a figure in memory to disk.
-.TP
-\fIgetrdsfig\fP
-gets a pointer to a figure.
-.RE
-.ft R
-.fi
-.SH SEE ALSO
-.BR librds,
-.BR librpr,
-.BR librfm,
-.BR librut,
-.BR librwi,
-.BR RDS_IN,
-.BR RDS_OUT,
-.BR RDS_TECHNO_NAME
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/librut.1 b/alliance/share/man/man1/librut.1
deleted file mode 100644
index d3a627d3..00000000
--- a/alliance/share/man/man1/librut.1
+++ /dev/null
@@ -1,71 +0,0 @@
-.\"   $Id: librut.1,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)librut.1 0.0 93/18/08 UPMC
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-libut
-.XE
-.XS0 \n%
-.ti 0.2i
-libut
-.XE0 \}
-.TH LIBRUT 1 "October 1, 1997" "ASIM/LIP6" "RUT LIBRARY"
-.SH NAME
-librut \- rut library description
-.SH DESCRIPTION
-.IP I)
-DATA STRUCTURES USED
-.PP
-.RS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.ta 3n 20n 30n
- typedef struct coord_t
-  {
-    long X;
-    long Y;
-  } coord_t;
-.ft R
-.fi
-.RE
-.PP
-The structure \fIcoord_t\fP is a data structure used to have a couple of coordinates.
-.IP II)
-Description of the macros
-.PP
-\-  char CheckPhysicalGridAligned(c)
-.br
-    long  c;
-.RS
-.PP
-Tests if the integer \'c\' is a multiple of the grid step.
-.br
-If true, then value \fB0\fP is returned else value \fB1\fP is returned.
-.RE
-.IP III)
-Functions of LibRut library
-.TP
-\fIsearchrdsfig\fP
-Searchs a figure by its name in the figure's list in memory
-.TP
-\fIgetrdsmodellist\fP
-Gets models's list of instances of a figure.
-.TP
-\fIapplyrdssym\fP
-applies a transformation to a rectangle from a model.
-.ft R
-.fi
-.SH SEE ALSO
-.BR librds,
-.BR librfm,
-.BR librpr,
-.BR librtl,
-.BR librwi
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/librwi.1 b/alliance/share/man/man1/librwi.1
deleted file mode 100644
index 2a5127a9..00000000
--- a/alliance/share/man/man1/librwi.1
+++ /dev/null
@@ -1,239 +0,0 @@
-.\"   $Id: librwi.1,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)librwi.1 0.0 93/18/08 UPMC
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-librwi
-.XE
-.XS0 \n%
-.ti 0.2i
-librwi
-.XE0 \}
-.TH LIBRWI 1 "October 1, 1997" "ASIM/LIP6" "RWI LIBRARY VERSION 103"
-.SH NAME
-librwi \- rwi library description
-.SH DESCRIPTION
-.IP
-.IP I)
-DATA STRUCTURES USED
-.RS
-.IP A)
-The rdswinrec_list structure
-.PP
-The rdswinrec_list structure is used to create list of rectangles's tables. Each table contains a maximum of RWI_MAX_REC pointers to rdsrec_list structure.
-.PP
-.RS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.ta 3n 20n 30n
-typedef struct rdswinrec_list
-  {
-    struct rdswinrec_list \(**NEXT;
-    rdsrec_list           \(**RECTAB[ RWI_MAX_REC ];
-  } rdswinrec_list;
-.ft R
-.fi
-.RE
-.PP
-Description of the structure's fields :
-.TP
-\fINEXT\fP
-Pointer to the next table of tables's list.
-.TP
-\fIRECTAB\fP
-Table of rectangles.
-.IP B)
-The rdswin_list structure
-.PP
-The rdswin_list permits to create a window which contains the rectangles. This structure is used to make the windowing of the rds structure. Windowing permits fastly acces to rectangles of the data base.
-.PP
-.RS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.ta 3n 20n 30n
-typedef struct rdswin_list
-  {
-    struct rdswinrec_list \(**LAYERTAB[ RWI_MAX_LAYER ];
-  } rdswin_list;
-.ft R
-.fi
-.RE
-.PP
-Description of the structure's fields :
-.TP
-\fILAYERTAB\fP
-It's a table of pointers on rectangles's tables. Each entry of the table corresponds to a determinated RDS layer. The size of the table is defined by the constant RWI_MAX_LAYER which is the number of possible layers. 
-.IP C)
-The rdsrecwin_list structure
-.PP
-The rdsrecwin_list structure permits for a rectangle to know the windows which it belongs. In the rdsrec_list structure, there is no field destinated to point to this structure. Some functions of the Rwi library use the field \'USER\' but it may be also used by functions of the Rfm library. So, the user has to save the \'USER\' field by creating an additionnal structure to the rdsrec_list structure to put the new pointer (during this operation, the field \'USER\' must be saved in a temporary variable). 
-.PP
-.RS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.ta 3n 20n 30n
-typedef struct rdsrecwin_list
-  {
-    struct rdsrecwin_list \(**NEXT;
-    struct rdswin_list    \(**WINDOW;
-  } rdsrecwin_list;
-.ft R
-.fi
-.RE
-.PP
-Description of the structure's fields :
-.TP
-\fINEXT\fP
-Pointer to the next item whitch belongs to the list of rdsrecwin_list structure.
-.TP
-\fIWINDOW\fP
-Pointer to the window at which belongs the rectangle.
-.IP D)
-The rdswindow structure
-.PP
-The rdswindow structure permits to set a windowing to the rds data structure.
-.PP
-.RS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.ta 3n 20n 30n
-typedef struct rdswindow
-  {
-    long          XMIN;
-    long          YMIN;
-    long          XMAX;
-    long          YMAX;
-    long          MASK;
-    long          DX;
-    long          DY;
-    long          SIDE;
-    long          SIZE;
-    rdswin_list  \(**WINTAB;
-  } rdswindow;
-.ft R
-.fi
-.RE
-.PP
-Description of the structure's fields :
-.TP
-\fIXMIN\fP
-Position in lambda of the lower left corner of the windowing table to the X axis. 
-.TP
-\fIYMIN\fP
-Position in lambda of the lower left corner of the windowing table to the Y axis.
-.TP
-\fIXMAX\fP
-Position in lambda of the upper right corner of the windowing table to the X axis.
-.TP
-\fIYMAX\fP
-Position in lambda of the upper right corner of the windowing table to the Y axis.
-.TP
-\fIMASK\fP
-Number of rectangles in the windowing.
-.TP
-\fIDX\fP
-Width of the table in number of windows.
-.TP
-\fIDY\fP
-Height of the table in number of windows.
-.TP
-\fISIDE\fP
-size of the side of a window (which is a square) in lambda.
-.TP
-\fISIZE\fP
-Number of windows contained in the table.
-.TP
-\fIWINTAB\fP
-Pointer to the table of windows.
-.RE
-.IP II)
-Description of constants of the library
-.TP
-\fIRWI_MAX_REC\fP
-Maximum number of rectangles contained in a table used in the rdswinrec_list structure.
-.TP
-\fIRWI_MAX_LAYER\fP
-Number of possible layers. 
-.TP
-\fIRDS_ONE_WINDOW\fP
-This constant is used to determinate if a rectangle belongs to one or many windows.
-.IP III)
-Description of the macros
-.PP
-\- char IsRdsOneWindow( Rectangle )
-.br
-   rdsrec_list \(**Rectangle;  
-.RS
-.PP
-Tests if the rectangle belongs to a window :
-.br
-If true, then value 1 is returned else value 0 is returned (the rectangle belongs to many windows).
-.RE
-.PP
-\- void SetRdsOneWindow( Rectangle )
-.br
-   rdsrec_list \(**Rectangle;
-.RS
-.PP
-Sets the field \'FLAGS\' of the rectangle to mean that the rectangle belongs to one window.
-.RE
-.PP
-\- void ClearRdsOneWindow( Rectangle )
-.br
-rdsrec_list \(**Rectangle;
-.RS
-.PP
-Sets the field \'FLAGS\' of the rectangle to mean that the rectangle belongs to many windows.
-.RE
-.IP IV)
-Function of the libRwi library
-.TP
-\fIallocrdswinrec\fP
-allocates a structure used to create a list of tables of rectangles.
-.TP
-\fIallocrdsrecwin\fP
-allocates a structure used to know windows which contain a rectangle.
-.TP
-\fIallocrdswin\fP
-allocates table of windows
-.TP
-\fIallocrdswindow\fP
-allocates a window structure
-.TP
-\fIaddrdsrecwindow\fP
-adds a rectangle in the windowing of rds structure. 
-.TP
-\fIdelrdsrecwindow\fP
-deletes a rectangle from the windowing of rds structure.
-.TP
-\fIbuildrdswindow\fP
-builds windowing of a figure
-.TP
-\fIdestroyrdswindow\fP
-destroys windowing of a figure
-.TP
-\fIviewrdswindow\fP
-Displays caracteristics of all the windowing
-.SH SEE ALSO
-.BR librds,
-.BR librfm,
-.BR librpr,
-.BR librut,
-.BR librtl
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/log.1 b/alliance/share/man/man1/log.1
deleted file mode 100644
index 6ac23da9..00000000
--- a/alliance/share/man/man1/log.1
+++ /dev/null
@@ -1,38 +0,0 @@
-.\"   $Id: log.1,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)log.l 0.0 92/08/01 UPMC; Author: Luc Burgun
-.pl -.4
-.TH LOG 1 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-.SH NAME
-\fBlog\fP \- logical representations for boolean functions and utilities.
-.so man1/alc_origin.1
-.SH DESCRIPTION
-\fBlog\fP is a set of structures and functions that permits to manipulate several representations of boolean functions. Several programs and libraries of the \fIcao-vlsi cad tools\fP rest on the \fIlog\fP package. Three different kind of functions are available for:
-.TP 20
-Hash table management
-.TP 20
-Prefixed representation for boolean functions
-.TP 20
-Ordered binary decision diagrams representation
-.SH EXAMPLE
-Let's suppose that actual mbk version is 'nnn'.
-In order to use log, \fIlibMutnnn.a\fP library must be called. 
-.br
-\fImakefile\fP:
-.br
-HEADER = -I/labo/include 
-.br
-LIB = -L/labo/lib -lMutnnn -ltshmmm -lablmmm -lbddmmm
-.br
-Each library can be called separatly. The "logmmm.h" header file must be inserted in the files that use the functions or the structures defined in a library.  
-.br
-.SH SEE ALSO
-.BR mbk (1),
-.BR beh (1),
-.SH AUTHOR
-L. BURGUN salle 30 T. 55-65 Universite P&M Curie - 4 pl. Jussieu - FRANCE
-.br
-.SH THANKS
-Thanks to P. REMY, F. PETROT, P. ALLEGRE and N. DICTUS.
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/loon.1 b/alliance/share/man/man1/loon.1
deleted file mode 100644
index e23954f4..00000000
--- a/alliance/share/man/man1/loon.1
+++ /dev/null
@@ -1,131 +0,0 @@
-.\" 
-.\" This file is part of the Alliance CAD System
-.\" Copyright (C) Laboratoire LIP6 - Département ASIM
-.\" Universite Pierre et Marie Curie
-.\" 
-.\" Home page          : http://www-asim.lip6.fr/alliance/
-.\" E-mail support     : mailto:alliance-support@asim.lip6.fr
-.\" 
-.\" This progam is  free software; you can redistribute it  and/or modify it
-.\" under the  terms of the GNU  General Public License as  published by the
-.\" Free Software Foundation;  either version 2 of the License,  or (at your
-.\" option) any later version.
-.\" 
-.\" Alliance VLSI  CAD System  is distributed  in the hope  that it  will be
-.\" useful, but WITHOUT  ANY WARRANTY; without even the  implied warranty of
-.\" MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
-.\" Public License for more details.
-.\" 
-.\" You should have received a copy  of the GNU General Public License along
-.\" with the GNU C Library; see the  file COPYING. If not, write to the Free
-.\" Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-.\" 
-.\" 
-.\" Tool    : Man pages
-.\" Date    : 1991,92,2000
-.\" Author  : Luc Burgun, Pascale Allegre, Nathalie Dictus
-.\" Modified by Czo <Olivier.Sirol@lip6.fr> 1996,97
-.\" Modified by francois Donnet 2000
-.\" 
-.\" 
-.\" 
-.\" 
-.\" 
-.pl -.4
-.TH LOON 1 "Sept 01 2000"  "ASIM/LIP6" "CAO\-VLSI Reference Manual"
-.SH NAME
-.TP
-LooN \- Light optimizing on Nets.
-
-
-.so man1/alc_origin.1
-
-.SH SYNOPSIS
-.TP
-\f4loon\fP  [-hmxlo] \fIinput_file\fP \fIoutput_file\fP  [\fIlax_file\fP]
-.br
-
-.SH DESCRIPTION
-.br
-\f4loon\fP is a CAD tool that permits to remove fanout problems within a gates netlist and to optimize the delay. The netlist can be hierarchical and is flattened if necessary. \f4loon\fP run in batch mode and a parameter file can be used (see man \f4lax\fP) to parametrize optimization by adding informations on outputs (fanin), inputs (fanout, delay) and by setting general parameters such as optimization level.
-\f4loon\fP permits to compute delays of gates in the netlist and gives the critical path in the netlist. The global optimization of \f4loon\fP performs gate repowering to decrease the critical path delay. No buffers are inserted at this state of development of \f4loon\fP.
-.br
-
-
-.br
-\f4  lax Parameter file description\fP
-.br
-The lax file is common with other logic synthesis tools and is used
-for driving the synthesis process. 
-See \f4lax\fP(5) manual for more detail.
-
-.br
-\f4lax\fP uses a lot of parameters to guide every step of the synthesis process.
-Some parameters are globally used (for example, \fIoptimization level\fP whereas others are specifically used (\f4load capacitance\fP for the netlist optimization only).
-Here is the default lax file (see the user's manual for further information about the syntax of the '.lax' file):
-.br
-
-.br
-   Optimization mode = 2 (50% area - 50% delay)
-.br
-   Input impedance = 0
-.br
-   Output capacitance = 0
-.br
-   Delayed input = none
-.br
-   Auxiliary signal saved = none
-.br
-
-
-.SH OPTION
-.TP 10
-\f4\-h\fP
-Help mode. Displays possible uses of \f4loon\fP.
-.TP 10
-\f4\-o input_file\fP
-Overwrites the source file if no \fIoutput_file\fP is given. This can be usefull if you don't want several netlist files.
-.TP 10
-\f4\-m optim_mode\fP
-Optimization mode. Can be defined in lax file, it's only a shortcut to define it on command line. This mode number has an array defined between \fI0\fP and \fI4\fP. It indicates the way of optimization the user wants. If \fI0\fP is chosen, the circuit area will be improved. On the other hand, \fI4\fP will improve circuit delays. \fI2\fP is a medium value for optimization.
-.TP 10
-\f4\-x xsch_mode\fP
-Generate a '.xsc' file. It is a color map for each signals contained in \fIoutput_file\fP network. This file is used by \f4xsch\fP to view the netlist. By choosing level 0 or 1 for xsch_mode, you can color respectively the critical path or all signals with delay graduation.
-.TP 10
-\f4\-l lax_file\fP
-Just another way to show explicitely the \f4LAX\fP parameter file name.
-.br
-
-.SH ENVIRONMENT VARIABLES
-.br
-The following environment variables have to be set before using \f4loon\fP :
-.HP
-.ti 7
-\fIMBK_CATA_LIB\fP gives the auxiliary paths of the directories of input files (behavioural description). 
-.HP
-.ti 7
-\fIMBK_TARGET_LIB\fP gives the path (single) of the directory of the selected standard cell library. 
-.HP
-.ti 7
-\fIMBK_IN_LO\fP gives the input format of the structural description.
-.HP
-.ti 7
-\fIMBK_OUT_LO\fP gives the output format of the structural description.
-
-
-.SH EXAMPLE
-.br
-You can call \f4loon\fP as follows :
-.br
-.br
-	loon alu alu_loon
-
-
-
-.SH SEE ALSO
-.br
-loon(1), boog(1), boom(1), lax(1), vbe(1), scmap(1), bop(1), glop(1), c4map(1), xlmap(1), proof(1), yagle(1), asimut(1), vhdl(5), scr(1), sclib(1), sxlib(1).
-.br
-
-
-.so man1/alc_bug_report.1
diff --git a/alliance/share/man/man1/lvx.1 b/alliance/share/man/man1/lvx.1
deleted file mode 100644
index 3e97f134..00000000
--- a/alliance/share/man/man1/lvx.1
+++ /dev/null
@@ -1,188 +0,0 @@
-.\"   $Id: lvx.1,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)lvx.l 0.0 92/11/27 UPMC; Author: Francois Nacabal
-.TH LVX 1 "October 1, 1997" "ASIM/LIP6" "ALLIANCE USER COMMANDS"
-.SH NAME
-lvx \- Logical Versus eXtracted net-list comparator 
-.SH SYNOPSIS
-.TP
-\fBlvx \fIformat1 format2 filename1 filename2 \fB[ -a ] [ -o ] [ -f ]\fR
-.br
-.so man1/alc_origin.1
-.SH DESCRIPTION
-.B lvx
-compares two gate-level or block level net-list. The goal is to compare
-a specification net-list (logical net-list), the input to a place and route tool,
-with the physical net-list (extracted net-list) obtained by the
-.BR lynx (1)
-extractor.
-.br
-The net-list 1 is considered as the logical net-list and net-list 2 as the
-extracted net-list.
-.br
-.br
-.B lvx
-is an one-level hierarchical tool:
-.IP
-The two net-list are flattened, if the \fB-f\fP option is present, to the cells
-contained in the catalog file. The path to the catalog file is indicated in the
-.BR MBK_CATA_LIB (1)
-variable for the cell library, and in the
-.BR MBK_WORK_LIB (1)
-variable with the name
-.BR MBK_CATAL_NAME (1)
-for user blocks (
-.BR catal (5)
-) that are not to be flattened.
-.IP
-For both net-list, the instances are considered as black-boxes.
-.IP
-The two net-list must have the same external connectors names.
-.IP
-The two net-list must have the same instances names.
-.IP
-The two net-list must have the same signals names for unconnected signals.
-.IP
-The two net-list cannot directly contain transistors.
-.LP
-Comparison is performed in three steps:
-.IP
-Compare terminals.
-.IP
-Compare instances.
-.IP
-Compare connections.
-.IP
-Compare unconnected signals.
-.LP
-If an error occurs during first or second step, a message is
-immediately displayed and the third step will not start:
-.B lvx
-cannot compare connections (signals) if terminals
-or instances are not equivalent.
-.br
-The
-.B -o
-option allows to order connectors if the steps described before have been
-reached successfully.
-.I Extracted_netlist
-is then saved on disk. The file get the name
-.I filename2
-suffixed by the value of
-.BR MBK_OUT_LO (1)
-variable.
-.br
-Routers add automatically empty feed-through cells.
-These cells must not be taken into account in the comparison.
-A cell that have the
-.I F
-attribute in the catalog file (
-.B catal (5)
-) is considered as feed-through cell, and are deleted, in memory, from the
-net-list where it appears.
-.SH OPTIONS
-.TP
-.B "-a"
-Some routers generate layout with several physical connectors for power and
-ground (
-.I VDD
-or
-.I VSS
-).
-If those connectors are not internally connected, they will have different
-indexed names (
-.I VDD1
-,
-.I VDD2
-etc...) in the extracted net-list.
-It is possible to perform reduction on those power and ground connectors before
-comparison, using the -a option.
-After reduction, each instance contains only one
-.I VDD
-connector and one
-.I VSS
-connector, as the main figure.
-.TP
-.B "-o"
-In this case,
-.B lvx
-produces a modified net-list (saved with the name
-.I filename2
-), which is a copy of net-list 2 with ordered connectors.
-Terminals and instance connectors are relisted in the order of the models
-in net-list 1. The saved net-list is done with the
-.BR MBK_OUT_LO (1)
-format, so user has to set this variable before running
-.B lvx
-\&.
-If he does not, default value is used, and net-list 1 could be lost if
-filename are identical and input format same as output format.
-.br
-If -a option is used, then the saved net-list is the reduced net-list with only
-one
-.I VDD
-and one
-.I VSS
-\&.
-.TP
-.B "-f"
-The two net-lists are flattened to the leaf cells contained in the catalog
-file. Usually the extracted net-list is a flatten net-list, while the logical
-one can be a hierarchical net-list.
-.SH EXAMPLES
-With
-.I logical_netlist
-named amd2901.vst and the corresponding
-.I extracted_netlist
-as amd2901.al containing multiple power connectors, the command line is :
-.br
-.IP
-.B lvx
-vst al amd2901 amd2901 -a
-.br
-.LP
-.SH OUTPUT FILES
-.TP 20
-\fIfilename2\fP.\f4xx\fP
-Netlist view saved when the \fB-o\fP option is present. The suffixe depend on
-the \f4MBK_OUT_LO\fP(1) environment variable.
-.SH ENVIRONMENT VARIABLES
-.TP 20
-\f4MBK_CATA_LIB\fR
-contains the directories where the cell librtaries are.
-\f4MBK_WORK_LIB\fR
-contains the directory path of the working directory, usually set to
-\f4.\fR (dot).
-.TP
-\f4MBK_OUT_LO\fR
-contains the expected format of the netlist output.
-.TP
-\f4MBK_CATAL_NAME\fR
-contains the name of the user cell catalog.
-.SH SEE ALSO
-.BR lynx (1),
-.BR MBK_OUT_LO (1),
-.BR MBK_WORK_LIB (1),
-.BR MBK_CATA_LIB (1),
-.BR MBK_CATAL_NAME (1),
-.BR catal (5)
-\&.
-.SH DIAGNOSTICS
-The string "_logic" is appended to the net-list 1 and the string "_extract", is
-appended to the net-list 2.
-.LP
-Two kinds of error message can occur:
-.IP
-A fatal error causes the program to exit.
-It happens when one of the net-lists is not correct,
-.B lvx
-cannot construct internal structure for compare.
-.IP
-A compare error occurs when the figures are not identical.
-It happens when basic objects (instances, connectors) do not exist in both
-net-list, or when connections (signals) do not connect same terminals or
-instances in the two net-lists.
-.LP
-Exit code 0 is returned for identical net-lists.
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/lynx.1 b/alliance/share/man/man1/lynx.1
deleted file mode 100644
index 0abfac8b..00000000
--- a/alliance/share/man/man1/lynx.1
+++ /dev/null
@@ -1,167 +0,0 @@
-.\"   $Id: lynx.1,v 1.3 1999/07/22 15:05:35 outil Exp $
-.\" @(#)lynx 1.09 94/10/10 UPMC/ASIM/LIP6/CAO-VLSI " Ludovic Jacomme, Frederic Petrot
-.TH LYNX 1 "October 1, 1997" "ASIM/LIP6" "ALLIANCE USER COMMANDS"
-.SH NAME
-lynx \- Hierarchical netlist extractor
-.SH SYNOPSIS
-.B lynx
-[
-.I \-v
-]
-[
-.I \-c
-]
-[
-.I \-f
-]
-[
-.I \-t
-]
-[
-.I \-ar
-]
-[
-.I \-ac
-]
-.I input_name
-[
-.I output_name
-]
-.br
-.so man1/alc_origin.1
-.SH DESCRIPTION
-\fBLynx\fP is a hierarchical layout extractor.
-It builds a netlist of interconnections from a symbolic layout view.
-The \fIinput\fP argument is the name of the symbolic layout cell to
-be extracted, using as input format the one selected by the
-\fBMBK_IN_PH\fP(1) environment variable.
-If \fIoutput\fP is present, the resulting netlist will be given this name.
-If no \fIoutput\fP is given, then \fIinput\fP will also be the generated
-netlist name.
-The output format is specified by the \fBMBK_OUT_LO\fP(1) environment variable.
-.br
-As most of the Alliance cad tools, \fBlynx\fP uses \fBmbk\fP(1) environment
-variables.
-.BR MBK_CATA_LIB (1),
-.BR MBK_WORK_LIB (1),
-.BR MBK_IN_PH (1),
-.BR MBK_OUT_LO (1),
-.BR RDS_TECHNO_NAME (1).
-.PP
-\fBLynx\fP computes capacitances attached to the signals if 
-the -ac option is set. At the moment,
-the value of these capacitances is computed for a typical one micron
-technology, and cannot be changed by the user through a technology file.
-The extracted netlist can be simulated for performance evaluation.
-.br
-The typical capacitances are given below in 10e-18 farad / lamda^2 :
-.TP 20
-POLY
-100
-.TP 20
-ALU1
-50
-.TP 20
-ALU2
-25
-.SH OPTIONS
-\fBLynx\fP checks the two basic \fBALLIANCE\fP rules regarding connector names:
-.br
-.RS
-If two physical connectors are connected to the same net, they must have
-the same name. 
-.br
-If two physical connectors have the same name, they must be internally
-connected to the same net.
-.RE
-.br
-As a result only one logical connector will appear in the netlist.
-A fatal error occurs if one of those two rules is violated ( even for power
-and ground connectors )
-
-When no options are specified, the current hierarchical level is extracted.
-The resulting netlist is the list of interconnections of the current
-layout hierarchy level.
-Three options are available to change \fBlynx\fP behaviour :
-.TP
-\-t
-Notifies a transistor level extraction, the symbolic layout cell is flattened to
-transistor layout before extraction.
-.TP
-\-f
-The symbolic layout cell is flattened to the catalog level before extraction.
-Use "man catal" for detail on  the  catalog file.
-If the catalog is empty, or doesn't exist, the netlist is an interconection of
-transistors, if  it isn't, the netlist is an interconection of gates or blocks
-whose names are defined in the catalog.
-.TP
-\-v
-Verbose mode on.
-Each step of the extraction is displayed on the standard  output,
-along  with some statistics.
-.TP
-\-c
-Generates a \fBcore\fP file representing the conflictuel net, when 
-\fBlynx\fP detects two external connectors with different names on
-the same signal, or when it finds two external connectors having 
-the same name but not internally connected to the same net, or when 
-it cannot correctly extract an L shaped transistor.
-.TP
-\-ac
-Extract capacitance to ground on losig.
-.TP
-\-ar
-Extract interconnect resistance and capacitance to ground. Value of
-resistance foreach layer can be changed in the RDS file.
-.SH EXAMPLES
-.ie t  \{\
-.ft CR \}
-.el \fB
-prompt> lynx -v amd2901
-.ft R
-.RS
-Gives a logical netlist of the chip amd2901, for one hierarchical
-level, using verbose mode.
-This would be typically used to verify the work of the \fBring\fP(1)
-router, in conjunction with \fBlvx\fP on the specificated netlist and
-the extracted one.
-.RE
-.ie t  \{\
-.ft CR \}
-.el \fB
-.nf
-prompt> cat $MBK_WORK_LIB/$MBK_CATAL_NAME
-a2_y
-a2p_y
- .
- .
-prompt> lynx -f amd2901
-.fi
-.ft R
-.RS
-Gives a logical netlist of the chip amd2901, after a flatten operation stopping
-on the cells specified in the catalog ( the standard cell library in our case ).
-.RE
-.ie t  \{\
-.ft CR \}
-.el \fB
-.nf
-prompt> lynx -t amd2901
-.fi
-.ft R
-.RS
-Gives a logical netlist of the amd2901 chip at the transistor level.
-This is useful with \fByagle\fP(1), to retrieve logical equations from
-a layout.
-.RE
-.SH SEE ALSO
-.BR al (1),
-.BR MBK_CATA_LIB (1),
-.BR MBK_WORK_LIB (1),
-.BR MBK_CATAL_NAME (1),
-.BR MBK_IN_PH (1),
-.BR catal (5),
-.BR RDS_TECHNO_NAME (1).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/mbk.1 b/alliance/share/man/man1/mbk.1
deleted file mode 100644
index 24845647..00000000
--- a/alliance/share/man/man1/mbk.1
+++ /dev/null
@@ -1,667 +0,0 @@
-.\"   $Id: mbk.1,v 1.2 2000/11/20 12:43:38 gregoire Exp $
-.\" @(#)mbk.l 0.0 90/22/08 UPMC; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-\fBPresentation of generic \fIlayout\fP and \fInetlist\fP data structures\fR
-.XE \}
-.TH MBK 1 "October 1, 1997" "ASIM/LIP6" "ALLIANCE MBK LIBRARIES"
-.SH NAME
-mbk \- generic layout and netlist data structures
-.so man1/alc_origin.1
-.SH DESCRIPTION
-mbk is a generic data structure supporting vlsi concepts. It covers
-two distinct areas of representation of a circuit :
-.TP
-the \fInetlist\fP view :
-This is a structural representation of circuits, in terms of logical gates and
-interconnections between gates.
-.TP
-the \fIsymbolic layout\fP view :
-This is a drawing matter, and describes the objects from a geometrical 
-and topological point of view.
-.LP
-The goal of mbk is to have a single data structure, with fixed meaning well
-defined on each objects. So any tools that needs to work on netlist or
-symbolic layout views can be build upon it.
-.LP
-For each object, a set of functions is defined in order to add, delete and get
-it. Some other functions are higher level, but very useful, so they are also
-given in the standard libraries.
-.TP
-The \fInetlist\fP view manipulates :
-.RS
-.TP 20
-\-figures :
-Models of cells.
-.TP
-\-instances :
-Needed to build up a hierarchy.
-.TP
-\-connectors :
-Terminals used to describe interconnections.
-.TP
-\-signals :
-Interconnecting nets between the connectors.
-.TP
-\-transistors :
-Terminal elements of a netlist.
-.TP
-\-capacitances :
-Define the load of a signal.
-.RE
-.TP
-The \fIlayout\fP view uses :
-.RS
-.TP 20
-\-figures :
-Models of cells.
-.TP
-\-instances :
-Needed to build up a hierarchy.
-.TP
-\-connectors :
-Terminals that should match the ones given in the netlist view.
-.TP
-\-vias :
-Realise the contact between two separate layout levels.
-.TP
-\-references :
-Allow to name a point in order to use it later on.
-.TP
-\-segments :
-Basical wires.
-.RE
-.LP
-Each of these elements does possess access functions.
-.TP
-\fInetlist\fP view :
-.RS
-.TP 10
-\-figures :
-.RS
-.TP 20
-\fBaddlofig\fP
-\- create a new structural cell model
-.TP
-\fBaddlomodel\fP
-\- create a temporary logical model and add it to a list
-.TP
-\fBflattenlofig\fP
-\- flatten an instance in a logical figure
-.TP
-\fBfreelomodel\fP
-\- free a \fBlofig_list\fP for temporary models
-.TP
-\fBgetlofig\fP
-\- give back a pointer to a \fIlofig\fP
-.TP
-\fBgetlomodel\fP
-\- retrieve a model from a \fBlofig_list\fP
-.TP
-\fBloadlofig\fP
-\- load a new logical cell model from disk
-.TP
-\fBrflattenlofig\fP
-\- recursivly flatten a figure
-.TP
-\fBsavelofig\fP
-\- save a logical figure on disk
-.TP
-\fBviewlo\fP
-\- scan all \fBlofig_list\fPs and display their elements
-.TP
-\fBviewlofig\fP
-\- display elements of a \fBlofig_list\fP
-.RE
-.TP
-\-instances :
-.RS
-.TP 20
-\fBaddloins\fP
-\- create a logical instance
-.TP
-\fBdelloins\fP
-\- delete a logical instance
-.TP
-\fBgetloins\fP
-\- retrieve a logical instance
-.TP
-\fBviewloins\fP
-\- display elements of a \fBloins_list\fP
-.RE
-.TP
-\-connectors :
-.RS
-.TP 20
-\fBaddlocon\fP
-\- create a logical connector
-.TP
-\fBdellocon\fP
-\- delete a logical connector
-.TP
-\fBgetlocon\fP
-\- retrieve a logical connector
-.TP
-\fBsortlocon\fP
-\- sort a set of logical connectors by name
-.TP
-\fBcheckloconorder\fP
-\- check a list of connector towards mbk consistency rules
-.TP
-\fBviewlofigcon\fP
-\- display elements of a \fBlocon_list\fP attached to a figure
-.TP
-\fBviewloinscon\fP
-\- display elements of a \fBlocon_list\fP attached to an instance
-.RE
-.TP
-\-signals :
-.RS
-.TP 20
-\fBaddlosig\fP
-\- create a logical signal
-.TP
-\fBdellosig\fP
-\- delete a logical signal
-.TP
-\fBgetlosig\fP
-\- retrieve a logical signal
-.TP
-\fBgivelosig\fP
-\- give a logical signal
-.TP
-\fBgetsigname\fP
-\- choose a signal name in alias list
-.TP
-\fBsortlosig\fP
-\- sort a list of signals by name
-.TP
-\fBlofigchain\fP
-\- creates a netlist in terms of connectors on signals
-.TP
-\fBviewlosig\fP
-\- display elements of a \fBlosig_list\fP
-.RE
-.TP
-\-transistors :
-.RS
-.TP 20
-\fBaddlotrs\fP
-\- create a logical transistor
-.TP
-\fBdellotrs\fP
-\- delete a logical transistor
-.TP
-\fBviewlotrs\fP
-\- display elements of a \fBlotrs_list\fP
-.RE
-.TP
-\-capacitances :
-.RS
-.TP 20
-\fBaddcapa\fP
-\- add a capacitance to a signal
-.RE
-.RE
-.TP
-\fIlayout\fP view :
-.RS
-.TP 10
-\-figures :
-.RS
-.TP 20
-\fBaddphfig\fP
-\- create a new physical cell model
-.TP
-\fBdelphfig\fP
-\- delete and free a physical figure
-.TP
-\fBflattenphfig\fP
-\- flatten an instance in a figure
-.TP
-\fBgetphfig\fP
-\- give back a pointer to a \fIphfig\fP
-.TP
-\fBloadphfig\fP
-\- load a new physical cell model from disk
-.TP
-\fBrflattenphfig\fP
-\- recursivly flatten a figure
-.TP
-\fBsavephfig\fP
-\- save a physical figure on disk
-.TP
-\fBxyflat\fP
-\- compute hierarchical coordinates
-.TP
-\fBviewph\fP
-\- display all the \fBphfig_list\fPs and their elements
-.TP
-\fBviewphfig\fP
-\- display elements of a \fBphfig_list\fP
-.RE
-.TP
-\-instances :
-.RS
-.TP 20
-\fBaddphins\fP
-\- create a physical instance
-.TP
-\fBdelphins\fP
-\- delete a physical instance
-.TP
-\fBgetphins\fP
-\- retrieve a physical instance
-.TP
-\fBgetphins\fP
-\- retrieve a physical instance
-.TP
-\fBviewphins\fP
-\- display elements of a \fBphins_list\fP
-.RE
-.TP
-\-connectors :
-.RS
-.TP 20
-\fBaddphcon\fP
-\- create a physical connector
-.TP
-\fBdelphcon\fP
-\- delete a physical connector
-.TP
-\fBgetphcon\fP
-\- retrieve a physical connector
-.TP
-\fBinstanceface\fP
-\- give the face of a connector in a placed instance
-.TP
-\fBviewphcon\fP
-\- display elements of a \fBphcon_list\fP
-.RE
-.TP
-\-vias :
-.RS
-.TP 20
-\fBaddphvia\fP
-\- create a physical via
-.TP 20
-\fBbigvia\fP
-\- create a bunch of vias
-.TP
-\fBdelphvia\fP
-\- delete a physical via
-.TP
-\fBviewphvia\fP
-\- display elements of a \fBphvia_list\fP
-.RE
-.TP
-\-references :
-.RS
-.TP 20
-\fBaddphref\fP
-\- create a physical reference
-.TP
-\fBdelphref\fP
-\- delete a physical reference
-.TP
-\fBgetphref\fP
-\- retrieve a physical reference
-.TP
-\fBviewphref\fP
-\- display elements of a \fBphref_list\fP
-.RE
-.TP
-\-segments :
-.RS
-.TP 20
-\fBaddphseg\fP
-\- create a physical segment
-.TP
-\fBdelphseg\fP
-\- delete a physical segment
-.TP
-\fBviewphseg\fP
-\- display elements of a \fBphseg_list\fP
-.RE
-.RE
-\fBmbk\fP also has a set of utilities functions that does not deal with
-netlist nor layout, but that may be useful when working on these views.
-.TP
-helpful functions on :
-.RS
-.TP 10
-\-chain list :
-.RS
-.TP 20
-\fBaddchain\fP
-\- create a chain element, much like lisp cons
-.TP
-\fBdelchain\fP
-\- delete an element of a chain
-.TP
-\fBfreechain\fP
-\- delete an entire chain
-.RE
-.TP 10
-\-typed list :
-.RS
-.TP 20
-\fBaddptype\fP
-\- create a typed pointer list element
-.TP
-\fBdelptype\fP
-\- delete an element of a typed list
-.TP
-\fBfreeptype\fP
-\- delete an entire typed list
-.RE
-.TP 10
-\-numerical list :
-.RS
-.TP 20
-\fBaddnum\fP
-\- create a numerical list element
-.TP
-\fBdelnum\fP
-\- delete an element of a typed list
-.TP
-\fBfreenum\fP
-\- delete an entire typed list
-.RE
-.TP 10
-\- hash tables :
-.RS
-.TP 20
-\fBaddht\fP
-\- create an hash table
-.TP
-\fBdelht\fP
-\- delete an hash table
-.TP
-\fBviewht\fP
-\- dumps an hash table
-.TP 20
-\fBaddhtitem\fP
-\- add an item in an hash table
-.TP
-\fBdelhtitem\fP
-\- delete an item in an hash table
-.TP
-\fBgethtitem\fP
-\- retrieve an item in an hash table
-.TP
-\fBsethtitem\fP
-\- test and set an item in an hash table
-.RE
-.TP 10
-\-strings :
-.RS
-.TP 20
-\fBnamealloc\fP
-\- fill a dictionnary that ensures that equivalence with strcmp implies
-an equality of pointers
-.TP
-\fBupstr\fP
-\- uppercase a string
-.TP
-\fBdownstr\fP
-\- lowercase a string
-.TP
-\fBinstr\fP
-\- search a string into a string
-.TP
-\fBnaturalstrcmp\fP
-\- compare strings regarding aphabetical and numerical values.
-.RE
-.TP 10
-\-files :
-.RS
-.TP 20
-\fBmbkfopen\fP
-\- open a file regarding mbk environment
-.TP
-\fBmbkunlink\fP
-\- erase a file regarding mbk environement
-.TP
-\fBfilepath\fP
-\- give the absolute name of a file being used in mbk
-.RE
-.TP 10
-\-memory :
-.RS
-.TP 20
-\fBmbkalloc\fP
-\- allocate memory, like \fBmalloc\fP(3V)
-.TP
-\fBmbkrealloc\fP
-\- reallocate memory, like \fBrealloc\fP(3V)
-.TP
-\fBmbkfree\fP
-\- free memory, like \fBfree\fP(3V)
-.TP
-\fBmbkps\fP
-\- display informations on utilized memory and time spend on a process
-.RE
-.TP 10
-\-child process :
-.RS
-.TP 20
-\fBmbkwaitpid\fP
-\- wait for a particular child process
-.TP
-\fBmbksetautoackchld\fP
-\- tells Alliance library to automatically handle the terminaison a particular
-process
-.RE
-.RE
-.sp
-.LP
-In order to use mbk, concepts on library use are needed. And since this
-library is under development, the code is subject to change.
-.br
-To enable work, a static version is always present for the user on disk.
-Libraries and header files are suffixed by a number, and the programmer can
-choose to work with earlier versions than the actual one.
-But it is recommended
-to adapt its software to the libraries as soon as possible to see possible
-problems before old libraries destruction.
-.LP
-A \fImakefile\fP is necessary for all mbk applications.
-This is required because any soft must be easily recompilable, and knowing
-the needed libraries for an mbk based program is not an easy matter.
-It can't be achieved an other way, so do use \fImakefile\fP.
-.LP
-The file format parsers and drivers are not integrated into mbk, and each of
-them is a specific library. So if a parser or driver changes it is not needed
-to recompile mbk, because function prototypes are well define.
-Only a relink of the application is needed.
-.LP
-In terms of software organisation, mbk is splitted in five libraries for the
-basic functions, three header files for structure and variable declarations,
-and as many parsers drivers as needed, now a days two for physical view, and
-six for structural one.
-.br
-It is to be noticed that library version numbers are not the same for each
-of them, since they may evolve differently.
-For ease sake, version number will nevertheless always be represented by
-three numbers : \fInnn\fP, for current version.
-.LP
-Here follows the list of the libraries and their contents.
-It is the dual representation of what was given previously for each function.
-.TP 20
-libMphnnn.a :
-\fBaddphfig\fP,
-\fBdefab\fP,
-\fBdelphfig\fP,
-\fBxyflat\fP,
-\fBviewph\fP,
-\fBviewphfig\fP,
-\fBaddphcon\fP,
-\fBdelphcon\fP,
-\fBgetphcon\fP,
-\fBviewphcon\fP,
-\fBaddphins\fP,
-\fBgetphins\fP,
-\fBdelphins\fP,
-\fBviewphins\fP,
-\fBaddphseg\fP,
-\fBdelphseg\fP,
-\fBviewphseg\fP,
-\fBaddphvia\fP,
-\fBdelphvia\fP,
-\fBviewphvia\fP,
-\fBaddphref\fP,
-\fBdelphref\fP,
-\fBgetphref\fP,
-\fBviewphref\fP.
-.TP 20
-libMpunnn.a :
-\fBgetphfig\fP,
-\fBloadphfig\fP,
-\fBsavephfig\fP,
-\fBflattenphfig\fP,
-\fBrflattenphfig\fP,
-\fBbigvia\fP,
-\fBinstanceface\fP,
-\fBmphdebug\fP.
-.TP 20
-libMlonnn.a :
-\fBaddlofig\fP,
-\fBaddlomodel\fP,
-\fBfreelomodel\fP,
-\fBgetlomodel\fP,
-\fBviewlo\fP,
-\fBviewlofig\fP,
-\fBaddlocon\fP,
-\fBdellocon\fP,
-\fBgetlocon\fP,
-\fBviewlofigcon\fP,
-\fBviewloinscon\fP,
-\fBaddloins\fP,
-\fBdelloins\fP,
-\fBgetloins\fP,
-\fBviewloins\fP,
-\fBaddcapa\fP,
-\fBaddlosig\fP,
-\fBdellosig\fP,
-\fBgetlosig\fP,
-\fBgetsigname\fP,
-\fBlofigchain\fP,
-\fBviewlosig\fP,
-\fBaddlotrs\fP,
-\fBdellotrs\fP,
-\fBviewlotrs\fP.
-.TP 20
-libMlunnn.a :
-\fBgetlofig\fP,
-\fBloadlofig\fP,
-\fBsavelofig\fP,
-\fBflattenlofig\fP,
-\fBrflattenlofig\fP,
-\fBsortlosig\fP,
-\fBgivelosig\fP,
-\fBsortlocon\fP,
-\fBcheckloconorder\fP,
-\fBmlodebug\fP.
-.TP 20
-libMutnnn.a :
-\fBmbkenv\fP,
-\fBnamealloc\fP,
-\fBnameindex\fP,
-\fBconcatname\fP,
-\fBdownstr\fP,
-\fBupstr\fP,
-\fBinstr\fP,
-\fBnaturalstrcmp\fP,
-\fBincatalog\fP,
-\fBincatalogfeed\fP,
-\fBincataloggds\fP,
-\fBincatalogdelete\fP,
-\fBmbkalloc\fP,
-\fBmbkrealloc\fP,
-\fBmbkfree\fP,
-\fBmbkfopen\fP,
-\fBmbkunlink\fP,
-\fBfilepath\fP,
-\fBmbkps\fP,
-\fBaddchain\fP,
-\fBappend\fP,
-\fBdelchain\fP,
-\fBfreechain\fP,
-\fBreverse\fP,
-\fBaddptype\fP,
-\fBdelptype\fP,
-\fBfreeptype\fP,
-\fBgetptype\fP,
-\fBnum\fP,
-\fBaddnum\fP,
-\fBdelnum\fP,
-\fBfreenum\fP,
-\fBaddht\fP,
-\fBdelht\fP,
-\fBviewht\fP,
-\fBaddhtitem\fP,
-\fBdelhtitem\fP,
-\fBgethtitem\fP,
-\fBsethtitem\fP,
-\fBmbkwaitpid\fP,
-\fBmbksetautoackchld\fP.
-.LP
-The libraries are organized in such a way that no cycle can appear through
-calls.
-It means that if a given library, let's say One, has a function that performs
-a call to a function in an other library, Two, then none of the functions of
-Two do call functions that belong to One.
-.br
-When linking, the order of the libraries matters, and should be given from
-the upper level one, to the basical one. See the examples for needed order.
-.SH REMARKS
-In order for the tools using mbk to work properly, some consistency rules are
-to be ensured.
-Most of these rules are explained in the \fBman\fP(1) page of each data
-structure, but some are more general, and should be mentioned.
-.TP 20
-Netlist layout consistency
-The most import rules are :
-.RS
-Two physical connectors internally linked must have the same name.
-This name is the logical name.
-.br
-A logical connector may only be connected on a single signal, and two
-external logical connectors may not be on the same signal.
-.RE
-.TP 20
-Name identifiers
-The names are \fInot\fP case sensitive.
-The names must begin with a letter followed by a letter, a number or an
-underscore.
-Two underscores cant be contiguous, and the name cannot be ended with an
-underscore.
-.SH EXAMPLE
-Let's suppose that actual mbk version is 'nnn'.
-In order to use physical view, one needs something like that in its
-\fImakefile\fP :
-.RS
-.ft B
-.ad l
-HEADER = -I/labo/include -DMPH_H='"mphnnn.h"' -DMUT_H='"mutnnn.h"'
-LIB = -L/labo/lib -lMphnnn -lMpunnn -lMcpnnn -lMapnnn -lMutnnn
-.ad n
-.ft R
-.RE
-For logical view, the \fImakefile\fP should look like that :
-.RS
-.ft B
-.ad l
-HEADER = -I/labo/include -DMLO_H='"mlonnn.h"' -DMUT_H='"mutnnn.h"'
-LIB = -L/labo/lib -lMlonnn -lMlunnn -lMclnnn -lMalnnn -lMvlnnn -lMelnnn -lMslnnn -Mhlnnn -lMutnnn
-.ad n
-.ft R
-.RE
-If needed to work on both, just concatenate both \fBHEADER\fP and both \fBLIB\fP.
-.SH SEE ALSO
-.BR genlib (1).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/mbk2ps.1 b/alliance/share/man/man1/mbk2ps.1
deleted file mode 100644
index cba631cc..00000000
--- a/alliance/share/man/man1/mbk2ps.1
+++ /dev/null
@@ -1,200 +0,0 @@
-.\"   $Id: mbk2ps.1,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)Labo.l 0.0 90/22/08 UPMC; Author: Frederic Petrot
-.pl -.4
-.TH MBK2PS 1 "October 1, 1997" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
-.SH NAME
-.TP
-mbk2ps
-\- Creates a PostScript file from a symbolic layout cell
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.TP
-\fBmbk2ps\fP \fIcellname\fP
-.br
-[\fB-b\fP] [\fB-c\fP] [\fB-cn\fP] [\fB-fl\fP] [\fB-m\fP] [\fB-i\fP]
-[\fB-in\fP] [\fB-p\fP] [\fB-r\fP] [\fB-rn\fP] [\fB-rot\fP] [\fB-s\fP] 
-[\fB-si\fP] [\fB-sn\fP] [\fB-v\fP] [\fB-mn\fP]
-.br
-[\fB-f\fP \fIX0,Y0,X1,Y1\fP] [\fB-l\fP \fIlayernumber=patternnumber\fP]
-[\fB-sc\fP \fIscale\fP] [\fB-fs\fP \fIfontsize\fP]
-.br
-.SH DESCRIPTION
-The need for a clean output on paper of designs is an important issue in
-every day designer's life, and also in a more long term sight, to archive
-and give information about old design, or to build a complete documentation,
-for a standard cell library for example.
-.br
-In order to be as device independant and powerfull as possible, the choosen
-output file format is \fBPostScript\fP, since many today's device,
-laser printers, plotters, graphical terminals, etc, support it.
-.br
-The input file format is given by an environment variable
-.B MBK_IN_PH
-that gives the appropriate symbolic layout file format.
-The possible values are 
-.I cp, ap.
-See mbk(1) for details.
-.br
-The path to the input file is set up by two environment variables
-\fBMBK_WORK_LIB\fP(3) and if not found in the directory then the directory 
-pointed by \fBMBK_CATA_LIB\fP(3) is then searched through.
-The output of \fImbk2ps\fP is a \fBPostScript\fP file with the name 
-\fBcellname.ps\fP in the current directory. The resulting file can be then
-used on any adequat device.
-.br
-At invocation time, the first argument must be the \fIcellname\fP.
-The options can be given in any order beside this restriction.
-.SH OPTIONS
-With no options, mbk2ps generate a "standard file", with all options off.
-This is ok for leaf cells output, but not for hierarchical circuit.
-.TP
-\-b
-inhibits the drawing of the abutment box.
-.TP
-\-c 
-inhibits the drawing of the connectors.
-.TP
-\-cn 
-inhibits the drawing of the connectors names.
-.TP
-\-i 
-inhibits the drawing of the instances.
-.TP
-\-in 
-inhibits the drawing of the instances names.
-.TP
-\-r 
-inhibits the drawing of the references.
-.TP
-\-rn 
-inhibits the drawing of the references names.
-.TP
-\-s 
-inhibits the drawing of the segments.
-.TP
-\-sn 
-inhibits the drawing of the segments names.
-.TP
-\-v 
-inhibits the drawing of the vias.
-.TP
-\-mn 
-if the \-in option is not active, this option writes the name of the instance's
-model, not the instance one.
-It implies that either the \fIinstance\fP name is written, or its \fImodel\fP
-name, but not both of them at once.
-.TP
-\-f \fIX0,Y0,X1,Y1\fB
-gives the frame coordinates, in dot units, on the page.
-You may give any number, but no check will be performed to ensure it fits on
-a particular paper size, since many devices can be used for plotting.
-The default values are {(20, 40), (570, 820)}, and are meant to
-be used with A4 paper.
-.TP
-\-fl 
-flattens the cell to the catalog level. Recommended mainly for
-routed circuits that have more than one hierarchical level.
-.TP
-\-fs fontsize
-uses the \fIfontsize\fP argument as the new size for the font
-used to print objects names. If \fIfontsize\fP is not specified,
-then the value twelve is used by default. If \fIfontsize\fP is smaller
-than four, then four is used.
-.TP
-\-l \fIlayernumber=patternnumber\fP
-affects a pattern, given by it's number in the \fBpatternfont.ps\fP
-file, to a layer, given by it's number in the \fBmbk.h\fP file.
-The patterns by default are the one recommanded, so if you're not a genius
-in \fBPostScript\fP, avoid this option.
-.TP
-\-m 
-do not merge rectangles of a same layer in a polygon. This options is
-automatically turned on when circuits have instances, since the algorithm
-is quit time consuming, and not useful then.
-.TP
-\-p 
-do not fill the polygons and rectangles with a pattern.
-This option is more than strongly recommended when translating big circuits.
-The gained time factor is approximatly 35! Do not use it for leaf cells, or
-you won't understand them.
-.TP
-\-rot 
-rotates the figure from plus 90 degrees before output. Notice that this
-rotation is perfomed in memory, not in the generated \fBPostScript\fP file.
-.TP
-\-sc scale
-uses the \fIscale\fP argument as the new scale factor for
-printing. If \fIscale\fP is not specified, then the scale will be choosen
-to best fit the page.
-.TP
-\-si 
-executes silently. If not specified, a banner appears on the screen,
-and some internals informations are displayed at the end of the
-process, giving the actual scale, frame, name, etc.
-.TP
-patternsheet
-.br
-if \fBcellname\fP is "pattersheet", without quotes, then \fImbk2ps\fP
-generates a demonstration file, called \fBpatternsheet.ps\fP
-that draws a segment in each layer with its name and pattern, and
-also each contact with its name. This can be done once in order to
-have a reference for all the future uses of this tool.
-.SH EXAMPLES
-.TP
-You should first have a correct execution environment :
-.nf
-\fBsetenv MBK_IN_PH cp
-setenv MBK_WORK_LIB ~fred/mbk/mbk2ps
-setenv MBK_CATA_LIB /labo/cells/scr\fP
-.fi
-.TP
-\fImbk2ps n1_y\fP
-will create a \fBn1_y.ps\fP file in the current directory the "standard" way.
-.TP
-\fImbk2ps na2_y -sc 1.1\fP
-will create a \fBna2_y.ps\fP file in the current
-directory with a scale of 1.1 (in arbitrary unit!). Don't get afraid,
-\fImbk2ps\fP gives back a value for each plot. This option is useful when
-you want to plot many cells with the same scale, as in a
-library document.
-.TP
-\fImbk2ps bigcell -rot -fl -m -p -in -sn -fs 4\fP
-will create a \fBbigcell.ps\fP
-file in the current directory with a 90 degrees rotation, a flatten to the
-catalog, no patterns, nor segments names, nor instance names, and without
-merging the layers, with a font size of 4, that is the minimun allowed value.
-Tipically, this is what you would do for a routed
-circuit.
-.TP
-\fImbk2ps z2l_y -f 20,40,820,1160\fP
-will create a \fBz2l_y.ps\fP file in the current directory with a frame
-choosen to fit on an A3 paper. Just find the printer now!
-.SH SEE ALSO
-.BR mbk(1),
-.BR MBK_IN_PH(3),
-.BR MBK_CATA_LIB(3),
-.BR MBK_WORK_LIB(3),
-.BR MBK_CATAL_NAME(3),
-.BR pageview(1),
-.BR lpr(1).
-
-
-.SH DIAGNOSTICS
-.br
-Merging algorithm, that makes a polygone from a bunch of crossing rectangles
-fails if a loop exists.
-Do use the \fI-m\fP options in order to avoid it.
-.br
-The generated \fBPostScript\fP is version 2.0. It may not run with 1.0
-interpreters, due to the use of new structure conventions.
-.br
-The pattern filling algorithm is written in \fBPostScript\fP, and when
-interpreted, may take a lot of time on big circuits. Even a printer
-timeout error can occur on machine having to few Kbytes of ram. This is
-\fBnot\fP a \fImbk2ps\fP generated \fBPostScript\fP error,
-but a misuse of it.
-If such a problem occurs, just use the \fI\-p\fP option.
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/mbkcif.1 b/alliance/share/man/man1/mbkcif.1
deleted file mode 100644
index d9d4b0c9..00000000
--- a/alliance/share/man/man1/mbkcif.1
+++ /dev/null
@@ -1,54 +0,0 @@
-.\"   $Id: mbkcif.1,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)mbkcif  3.0 91/11/11 UPMC/ASIM/LIP6/CAO-VLSI "  
-.TH MBKCIF 1 "October 1, 1997" "ASIM/LIP6" "ALLIANCE Reference Manual"
-.SH NAME
-mbkcif \- mbk cif translater 
-.SH SYNOPSIS
-.B mbkcif
-.I target techno hier_mode input [output]
-.TP
-.I target    
-{ vti | versatil | cmp } 
-defines the layer type name, for vti (CAD software) or versatil DRC or cmp (
-.TP
-.I techno        
-{ idps | ecpd15 }
-
-defines the technology name, idps means that there isn't segment fitting.
-That must be used to versatil (Design Rules Checker).
-.TP
-.I hier_mode
-{F | H}
-
-.TP
-.I input     
-
-file name to translate
-.TP
-.I [output]     
-
-output file name, input file name is used when output missing.
-.br
-.SH AVAILABILITY
-This tool owns to Alliance CAD 
-.I UPMC/ASIM/LIP6/CAO-VLSI.
-It uses environement
-.B MBK/GENLIB
-.SH DESCRIPTION
-.SH EXAMPLES
-mbkcif cmp ecpd15 F amd2901
-.SH OPTIONS
-this tools use MBK variables defined in Unix environnemnent as :
-.TP
-.B MBK_CATA_LIB
-which defines the directories list containing cell librairies.
-.TP
-.B MBK_WORK_LIB
-which defines working directory.
-.TP
-except out data format, which is cif.
-.SH SEE ALSO
-mbk(1)
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/ocp.1 b/alliance/share/man/man1/ocp.1
deleted file mode 100644
index 9e5a8318..00000000
--- a/alliance/share/man/man1/ocp.1
+++ /dev/null
@@ -1,95 +0,0 @@
-.\"   $Id: ocp.1,v 1.5 2002/02/26 13:41:45 xtof Exp $
-.\" @(#)Labo.l 0.0 92/09/24 UPMC; Author: Christophe ALEXANDRE
-.pl -.4
-.TH OCP 1 "September 27, 2001" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
-.SH NAME
-.TP
-ocp
- - Standard Cell Placer
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.TP
-\fBocp\fP 
-[\fBoptions\fP] [\fInetlist\fP] [\fIfilename\fP]
-.br
-
-.SH DESCRIPTION
-\fBocp\fP is an automatic place tool for standard-cells.
-.br
-
-\fBinput net-list\fP
-.br
-The \fInetlist\fP file describes the input net-list.
-.br
-\fBocp\fP supports a hierarchical net-list. In this case the net-list is flattened by the placer according to the catalog file. The net-list format can be : structural VHDL, EDIF, or ALLIANCE internal format according to the environment variable \fBMBK_IN_LO\fP.
-.br
-
-\fBoutput layout\fP
-.br
-The file containing the placed block will have the name \fIfilename\fP. The output format is defined by the environment variable \fBMBK_OUT_PH\fP.
-.br
-
-.SH OPTIONS
-.br
-\fBOptional cells placement file\fP
-.br
-\fB-partial <NAME>\fP
-.br
-A user defined placement can be specified, thanks to a placement file.
-.br
-The optional placement file must be given by the user. It must have an extension that denotes the format defined by the environment variable \fBMBK_IN_PH\fP.
-.br
-
-\fBOptional connectors placement\fP
-.br
-The placement of connectors can be also specified.
-.br
-There are three ways to place connectors in a physical view :
-.br
-.br
-\fB-c\fP option will automatically place the connectors randomly. The auto placement will set connectors on each side of the abutment box.
-.br
-\fB-ring\fP option will automatically place the connectors randomly but only on the north and south side. This option is temporary and is provided for the ring pad placement tool.
-.br
-\fB-ioc <NAME>\fP option will place connectors as specified by the <NAME>.ioc given file.
-.br
-
-\fBMargin\fP
-.br
-It is possible to force the free area of the physical view.
-.br
-The \fB-margin <MARGIN>\fP option allow to set The amount of free area added in percentage of the cells area.
-.br
-The resulting area will be equal to CELL_AREA * (1 + <MARGIN>).
-.br
-By default, the margin value is 0.2 (20%)
-.br
-
-\fBNumber of rows\fP
-.br
-\fB-rows <NR>\fP option forces the design to be placed in <NR> rows.
-.br
-The abutment box's width is automatically generated.
-.br
-This option won't be used if a defined placement file is given.
-.br
-
-\fBVerbose mode\fP
-.br
-\fB-v\fP set the verbose mode on
-.br
-
-\fBGnuplot\fP
-.br
-\fB-gnuplot\fP option allow to generate automatically gnuplot files, for editing statistics
-.br
-.SH ENVIRONMENT VARIABLES
-.PP
-\fBocp\fP uses the environment variables MBK_VDD and MBK_VSS to know
-the name of the power signals vdd and vss.
-.br
-
-.SH SEE ALSO
-.PP
-ocr(1), MBK_IN_LO(1), MBK_IN_PH(1), MBK_OUT_PH(1), MBK_VDD(1), MBK_VSS(1)
-.so man1/alc_bug_report.1
diff --git a/alliance/share/man/man1/ocr.1 b/alliance/share/man/man1/ocr.1
deleted file mode 100644
index 401bd83b..00000000
--- a/alliance/share/man/man1/ocr.1
+++ /dev/null
@@ -1,68 +0,0 @@
-.\"   $Id: ocr.1,v 1.3 2002/01/14 15:48:53 hcl Exp $
-.\" @(#)Labo.l 0.0 92/09/24 UPMC; Author: Hugo CLEMENT
-.pl -.4
-.TH OCR 1 "January 11, 2002" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
-.SH NAME
-.TP
-ocr
- - An over-the-cell router
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.TP
-\fBocr\fP 
-[\fBoptions\fP] -L <\fIlogical_view\fP> -P <\fIplaced_view\fP> -O <\fIrouted_view\fP>
-.br
-
-.SH DESCRIPTION
-\fBocr\fP is an automatic router tool for standard-cells.
-.br
-
-\fBinput net-list\fP
-.br
-The \fIlogical_view\fP and \fIplaced_view\fP files describe the input net-list.
-.br
-\fBocr\fP supports a hierarchical net-list. In this case the net-list is flattened by the router according to the catalog file. The file format of the input files is set respectively by the environment variable \fBMBK_IN_LO\fP and \fBMBK_IN_PH\fP.
-.br
-
-\fBoutput layout\fP
-.br
-The file containing the routed block will have the name \fIrouted_view\fP. The output format is defined by the environment variable \fBMBK_OUT_PH\fP.
-.br
-
-.SH OPTIONS
-.br
-
-\fBNumber of layers\fP
-.br
-\fB-l [0-9]+\fP
-.br
-This paramaters sets how many layers the router is allowed to use. The maximun is 5 (ie up to, and including, ALU6). The default is the minimum : 2, ie use only ALU2 and ALU3.
-
-.br
-
-\fBIterations\fP
-.br
-\fB-i [0-9]+\fP
-.br
-Tells the router to stop its main loop when it reaches N iterations. The default is to loop till core dump.
-.br
-
-\fBVerbose mode\fP
-.br
-\fB-v\fP set the verbose mode on
-.br
-\fB-vv\fP produces a lot of output
-.br
-\fB-d\fP for debugging purpose
-.br
-
-.SH ENVIRONMENT VARIABLES
-.PP
-\fBocr\fP uses the environment variables MBK_VDD and MBK_VSS to know
-the name of the power signals vdd and vss.
-.br
-
-.SH SEE ALSO
-.PP
-ocp(1), MBK_IN_LO(1), MBK_IN_PH(1), MBK_OUT_PH(1), MBK_VDD(1), MBK_VSS(1)
-.so man1/alc_bug_report.1
diff --git a/alliance/share/man/man1/pat2dwl.1 b/alliance/share/man/man1/pat2dwl.1
deleted file mode 100644
index e60f626d..00000000
--- a/alliance/share/man/man1/pat2dwl.1
+++ /dev/null
@@ -1,26 +0,0 @@
-.\"   $Id: pat2dwl.1,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)PAT2DWL.1 1.0 Oct 05 1994 UPMC; Author: FLORENT O.
-.TH PAT2DWL 1 "October 1, 1997" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
-.SH NAME
-.PP
-\fIpat2dwl\fP, pattern translator from ALLIANCE CAD SYSTEM to HILO CAD SYSTEM
-
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.PP
-\fBpat2dwl\fP [\-nc] <\fIpat\fP> [<\fIdwl\fP>]
-
-.SH DESCRIPTION
-.PP
-\fBpat2dwl\fP is a pattern translator from ALLIANCE format (\fI".pat"\fP)
-to HILO format (\fI".dwl"\fP). With the \fI"\-nc"\fP option, only affectations
-are translated (i.e '0' and '1'), but not the comparisons ('+','-' and '*'). 
-This is useful for using HILO fault simulator, \fIHIFAULT\fP.
-
-.SH SEE ALSO
-.PP
-pat(5)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/patest.1 b/alliance/share/man/man1/patest.1
deleted file mode 100644
index 14da3564..00000000
--- a/alliance/share/man/man1/patest.1
+++ /dev/null
@@ -1,122 +0,0 @@
-.\"   $Id: patest.1,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)PATEST 3.0a March 01 1995 UPMC; Author: FLORENT O.
-.TH PATEST 1 "October 1, 1997" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
-.SH NAME
-.PP
-\fIpatest\fP, a pattern translator for test.
-
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.PP
-\fBpatest\fP \-tomsa <\fIpatfile\fP> [\-t <\fItplfile\fP>] [\-m <\fImsafile\fP>]
-.PP
-\fBpatest\fP \-topat <\fImsafile\fP> [\-f <\fIpatfile\fP>] [\-p <\fIpatfile\fP>]
-
-.SH DESCRIPTION
-.PP
-\fBpatest\fP translates patterns from ALLIANCE CAD SYSTEM world to LV500 world and vice-versa.
-
-.PP
-The \fBLV500\fP is an electronic tester for digital circuit from \fBTecktronix\fP\*R. 
-It can handle up to 256 channels with a maximum resolution of 0.5 ns.
-
-\fB1) From ALLIANCE CAD SYSTEM to LV500\fP
-.PP
-\fBpatest\fP \-tomsa <\fIpatfile\fP> [\-t <\fItplfile\fP>] [\-m <\fImsafile\fP>]
-
-.TP 20
-\fI\-tomsa <patfile>\fP
-This is the pattern file to be traduced. This file is in PAT format.
-As you cannot check the values of internal signals and internal registers 
-in a manufactured chip, \fBsignal\fP and \fBregister\fP constructs are not allowed.
-See \fBpat(5)\fP for more information on PAT format.
-.TP 20
-\fI\-t <tplfile>\fP
-This is a file written in TPL format. It describes timing characteristics and
-wiring information of the chip. See \fBtpl(5)\fP for more information on TPL format.
-if \fBtplfile\fP is not provided, \fBpatest\fP will look for a file called "\fB<patfile>.tpl\fP"
-.TP 20
-\fI\-m <msafile>\fP
-This is the name of the MSA file that \fBpatest\fP produce. if not provided, \fBpatest\fP
-will write a file called "\fB<patfile>.msa\fP"
-
-.PP
-\fB2) From LV500 to ALLIANCE CAD SYSTEM \fP
-.PP
-\fBpatest\fP \-topat <\fImsafile\fP> [\-f <\fIpatfile\fP>] [\-p <\fIpatfile\fP>]
-
-.TP 20
-\fI\-topat <msafile>\fP
-This is the MSA file to traduced. It usually results from the execution of a
-MSA file produces by \fBpatest\fP on the LV500 tester.
-
-.TP 20
-\fI\-f <patfile>\fP
-This is the name of the \fBold\fP PAT file (The PAT file wich has produced the MSA
-file used on the tester). if not provided, \fBpatest\fP will look for a file called 
-"\fB<msafile>.pat\fP"
-
-.TP 20
-\fI\-p <patfile>\fP
-This is the name of the \fBnew\fP PAT file to produce as the result of the
-execution of the old PAT file on the LV500 tester. if not provided, \fBpatest\fP
-will write a file called "\fB<msafile>.pat\fP"
-
-.SH EXAMPLE
-.PP
-
-A typical session of test is:
-
-.TP 10
-\fI(1) Produce a msa file\fP
-\fBcaracvect.msa\fP is produced from the pattern file \fBcaracvect.pat\fP 
-and the TPL file \fBcarac.tpl\fP: 
-.br
-> patest -tomsa caracvect -t carac
-.br
-The PAT file \fBcaracvect.pat\fP is usually verified before sending it 
-to the tester using the VHDL simulator \fBasimut\fP.
-
-.TP 10
-\fI(3) Send the msa file to the tester\fP
-The MSA file \fBcaracvect.msa\fP is sent to the tester using FTP 
-or the \fBlv500\fP batch:
-.br
-> lv500 -s caracvect.msa
-.br 
-See \fBlv500(1)\fP for more information on the \fBlv500\fP batch.
-
-.TP 10
-\fI(3) Execute the msa file on the tester\fP
-The MSA file is compiled an executed on the tester. The result is
-decompiled in a MSA file (\fBrescarac.msa\fP for example). See
-the Textronix Manual for informations on the LV500 tester.
-
-.TP 10
-\fI(4) Get the msa result file from the tester\fP
-The MSA result file \fBrescarac.msa\fP is retrieved from the tester using FTP or
-the \fBlv500\fP batch:
-.br
-> lv500 -s rescarac.msa
-.br 
-See \fBlv500(1)\fP for more information on the \fBlv500\fP batch.
-
-.TP 10
-\fI(5) Convert the msa result file to pat format\fP
-The PAT file \fBrescarac.pat\fP is produced using the MSA file
-\fBrescarac.msa\fP but also the old file \fBcaracvect.pat\fP.
-.br
-> patest -topat rescarac -f caracvect 
-
-
-.SH FILES
-When an error occurs during translation, \fBpatest\fP produce an error file
-named \fB<patfile>.log\fP or \fB<msafile>.log\fP
-
-.SH SEE ALSO
-.PP
-tpl(5), pat(5), asimut(1), lv500(1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/pcbs.1 b/alliance/share/man/man1/pcbs.1
deleted file mode 100644
index 8dc03279..00000000
--- a/alliance/share/man/man1/pcbs.1
+++ /dev/null
@@ -1,127 +0,0 @@
-.\" @(#)PCBS.1 2.0 April 1998 UPMC; Author: DONNET F.
-.TH PCBS 1 "April 1998" "Release 2.0" "CAO\-VLSI Reference Manual"
-.SH NAME
-.PP
-\fIpcbs\fP, PC/Boundary-Scan Tester Platform.
-
-.so man1/alc_origin.1
-
-.SH SYNOPSIS
-.PP
-\fBpcbs\fP \-\-check [-b <\fIBSDL\fP> | -e <\fIemul\fP> <\fIpga\fP>]
-.PP
-\fBpcbs\fP \-\-execute <\fIsource.PAT\fP> [<\fIdestination.PAT\fP>]
-.PP
-\fBpcbs\fP \-\-bsdl <\fIBSDL\fP> <\fIsource.PAT\fP> <\fIdestination.PAT\fP>
-.PP
-\fBpcbs\fP \-\-emulbs <\fIemul\fP> <\fIpga\fP> <\fIsource.PAT\fP> <\fIdestination.PAT\fP>
-
-
-.SH DESCRIPTION
-.PP
-\fBpcbs\fP is a tool addressing a Boundary Scan card connected to the PC Printer
-parallel interface. This tool is able to :
-.PP
-\- Automatically check the Boundary\-scan device for Instruction register length, Bypass register length and Boundary\-scan register length, 
-.PP
-\- Execute Boundary\-scan patterns directly to the device,
-.PP
-\- Translate functionnal patterns to Boundary\-scan patterns using a BSDL description of the device Boundary\-scan architecture,
-.PP
-\- Translate functionnal patterns to Boundary\-scan patterns using an ASCII description of the device Boundary\-scan architecture for the specific emulbs31 card,
-.PP
-
-
-To use this tool, you must have a strong knowledge of Boundary-scan architecture 
-and eventually Boundary\-scan Description Language.
-
-.SH DEFINITION
-.PP
-We call "\fBBoundary\-scan patterns\fP" patterns written for a device with Boundary\-scan architecture using only the Test Acess Port interface (i.e TDI, TDO, TMS, TCK and eventually TRST).
-.br
-We call "\fBFunctionnal patterns\fP" patterns written for a device with Boundary\-
-scan architecture(case of --bsdl option), but using the fonctionnal interface  of the device or for a chip branched with the specific EMULBS31 card which emulated the boundary-scan device(--emulbs option).
-
-.SH CHECK MODE
-.PP
-\fBpcbs\fP \-\-check [-b <\fIBSDL\fP> | -e <\fIemul\fP> <\fIpga\fP>]
-
-\fBpcbs\fP will send special patterns to the Boundary\-scan device to find by itself
-the Instruction register length, the Bypass register length and the 
-Boundary\-scan register length. If a <\fIbsdl\fP> file is provided, it will compare
-the found values against the <\fIbsdl\fP> or <\fIemul\fP> + <\fIpga\fP> ones.
-See BSDL MODE or EMULBS MODE for more informations about these files.
-.PP
-If it cannot communicate with the device, \fBpcbs\fP will output an error message 
-like :
-.PP
-.nf
-Cannot check INSTRUCTION Register (longer than xxxx bits ???)
-Check the card connection
-.fi
-
-.SH EXECUTION MODE
-.PP
-\fBpcbs\fP \-\-execute [\-vp] <\fIsource.PAT\fP> [ [\-fs] <\fIdestination.PAT\fP>]
-
-\fBpcbs\fP will send the "\fBBoundary\-scan patterns\fP" <\fIsource.PAT\fP> to the device.
-The EXECUTION MODE can be used with the BSDL MODE or EMULBS MODE to translate the
-functionnal patterns and send them directly to the device.\n
-.br
-If <\fIdestination.PAT\fP> is specified, it will save the results with format boundary(\-s) or functionnal(\-f).
-
-\-v or \-\-verbose mode display all behaves and warnings. It is very verbose, so use it only for debugging your patterns.\n
-.br
-\-p or \-\-pattern followed by a number is to indicate the number of patterns to be loaded in memory in one sequence. It's an evidence you must decrease this number if you have problem of memory and swapping(\-p=50 for example). you should also raise it if you are free of (\-p all for example).
-
-.SH BSDL MODE
-.PP
-\fBpcbs\fP \-\-bsdl [\-vp] <\fIBSDL\fP> <\fIsource.PAT\fP> <\fIdestination.PAT\fP>
-
-\fBpcbs\fP will translate "\fBFunctionnal patterns\fP" <\fIsource.PAT\fP> to 
-"\fBBoundary\-scan patterns\fP" <\fIdestination.PAT\fP> (see DEFINITIONS) using a
-Boundary-Scan Description Language file <\fIBSDL\fP>.
-.br
-\-v or \-\-verbose mode display all behaves and warnings. It is very verbose, so use it only for debugging your patterns.
-.br
-\-p or \-\-pattern followed by a number is to indicate the number of patterns to be loaded in memory in one sequence. It's an evidence you must decrease this number if you have problem of memory and swapping(\-p=50 for example). you should also raise it if you are free of (\-p all for example).
-
-.SH EMULBS MODE
-.PP
-\fBpcbs\fP \-\-emulbs [-vp] <\fIemul\fP> <\fIpga\fP> <\fIsource.PAT\fP> <\fIdestination.PAT\fP>
-
-\fBpcbs\fP will translate "\fBFunctionnal patterns\fP" <\fIsource.PAT\fP> to 
-"\fBBoundary\-scan patterns\fP" <\fIdestination.PAT\fP> (see DEFINITIONS) using
-ASCII description files. Users have to give connexions between the PGA block and the emulbs31 card and also between the PGA and the chip.
-\fBpcbs\fP runs faster if your connexions are only on some emulbs31 because of bypass.
-.br
-\-v or \-\-verbose mode display all behaves and warnings. It is very verbose, so use it only for debugging your patterns.
-.br
-\-p or \-\-pattern followed by a number is to indicate the number of patterns to be loaded in memory in one sequence. It's an evidence you must decrease this number if you have problem of memory and swapping(\-p=50 for example). you should also raise it if you are free of (\-p all for example).
-.nf
-
---example for emul connexions file | --example for chip connexions file
---left-hand is for EMULBS connector| --left-hand is for PGA connector
---right-hand is for PGA connector  | --right-hand is for CHIP connector
-                                   |
-pcbs emul_connexions V2.0;         | pcbs pga_connexions version 2.0;
-0    <=a:1 ;                       | a:1 <=in     ck  ;
-185  <=r:16;                       | r:16<=out    y   ;
-56   <=d:5 ;                       | d:4 <=in     i(0);
-76   <=d:4 ;                       | d:5 <=in     i[1];
-80   <=g:2 ;                       | g:2 <=inout  sh  ;
-Vdd  <=e:6 ;                       | e:6 <=in   d_Vdd ;
-d_Vss<=a:2 ;                       | a:2 <=in   d_Vss ;
-.fi
-
-.SH SEE ALSO
-.PP
-pat(5), asimut(1), bsdl(5)
-
-.so man1/alc_bug_report.1
-
-
-
-
-
-
diff --git a/alliance/share/man/man1/proof.1 b/alliance/share/man/man1/proof.1
deleted file mode 100644
index 49164da0..00000000
--- a/alliance/share/man/man1/proof.1
+++ /dev/null
@@ -1,57 +0,0 @@
-.\"   $Id: proof.1,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)Labo.l 1.2 91/11/01 UPMC; Author: BURGUN L.
-.pl -.4
-.TH PROOF 1 "October 1, 1997" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
-.SH NAME
-.TP
-proof    
-\- Formal proof between two behavioural descriptions
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.TP
-\fBproof\fP [\fI-a\fP] [\fI-d\fP]  \fIfile1\fP  \fIfile2\fP
-.br
-.SH DESCRIPTION
-.br
-Made to run on a data-flow description, \fBproof\fP supports the same subset of VHDL as asimut and bop and scmap (for further informations about this subset, please call the VHDL manual). \fBproof\fP uses a Reduced Ordered Binary Decision Diagrams representation that permits the designer to prove easily the functionnal equivalence between two behavioral descriptions. 
-\fBproof\fP is generally used in order to compare a behavioural specification with an extracted behaviour obtained by \fByagle\fP.
-.br
-In default mode, a collapsing phase is done on the description by removing all the auxiliary signals (the BDD of the outputs, the registers and the buses are described from the inputs or the registers). The two descriptions must contain the same ressources (signals register with the same name). 
-It is possible to use the \fI.inf\fP file in \fByagle\fP to rename the registers in the extracted behavioural description (see man \fByagle\fP). The datas and the commands (the guarded expressions) must match separatly. The buses corresponding to completely specified logical functions are represented by a logical multiplexor in both descriptions.
-The two descriptions must have the same interface (VHDL entity), if they do not, the formal \fBproof\fP is stopped.
-.br 
-\fBproof\fP only uses two system environment variables related to the work directory. 
-.br
-.SH ENVIRONMENT VARIABLES
-.br
-.HP
-.ti 7
-\fIMBK_WORK_LIB\fP gives the path for the behavioral descriptions. The default value is the current directory.
-.br
-.HP
-.ti 7
-\fIMBK_CATA_LIB\fP gives some auxiliary pathes for the behavioral descriptions. The default value is the current directory.
-.SH OPTIONS
-.br
-Options may be given in any order before the filenames.
-.HP
-.ti 7
-\-a
-This option asks \fBproof\fP to keep the common auxiliary signals. \fBproof\fP keeps all intermediate signals that have the same name in both descriptions (A common signal is considered as an input and an output of each description). This option can be useful for descriptions containing large equations. It may be used when \fBproof\fP has failed or if you want to debug in step by step mode the two different descriptions.
-.HP
-.ti 7
-\-d
-The program displays errors when the behavioral descriptions are different. Equations are displayed when it's possible.
-.br
-.SH EXAMPLE
-.br
-	proof -a -d adder1 adder2
-
-.SH SEE ALSO
-.br
- \fBbop\fP (1), \fBglop\fP (1), \fBscmap\fP (1), \fBc4map\fP (1),
-\fBasimut\fP(1), \fBvhdl\fP(5), \fByagle\fP(1), \fBvbe\fP(5).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/rage.1 b/alliance/share/man/man1/rage.1
deleted file mode 100644
index 1625913b..00000000
--- a/alliance/share/man/man1/rage.1
+++ /dev/null
@@ -1,199 +0,0 @@
-.\"   $Id: rage.1,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)Labo.1 0.0 91/04/02 UPMC; Author: Abdelhafid BOUARAOUA
-.TH RAGE 1 "October 1, 1997" "ASIM/LIP6" "ALLIANCE USER COMMANDS"
-.SH NAME
-rage \- Random Acess Memory(RAM) Generator
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B rage
-.I bits
-.I words
-.B [ -n | -m | -w ] 
-.B [ -u ] [ -t\fIn\fP ]
-.B [ -ckup / -ckdown ]
-.B [ -layout ]    
-.B [ -physicalbox ] [ -vhdl ]
-.B [ -datasheet ]       
-.B [ -icon ] [ -o \fBblockname\fP ]
-.SH DESCRIPTION
-.B rage
-generates several different views of a Random Acess Memory.
-The ram generated is always constitued of two ram-cells blocks between which is placed a decoder cell.
-.LP
-The interfaces of the ram are given below(there is two versions of the interface because input and output data can be bidirectionnal or separated):
-.br
-.ul
-bidirectionnal data:
-.br
-ENTITY \fIrage\fP IS
-.TP
-PORT(\fIadr\fP: IN BIT_VECTOR(0 TO \fIn\fP);
-\fIdata\fP: INOUT BIT_VECTOR(0 TO \fIw\fP);
-.br
-\fIck\fP: IN BIT;
-.br
-\fIwrite\fP: IN BIT;
-.br
-\fIen\fP: IN BIT;
-.br
-\fIvdd\fP: IN BIT;
-.br
-\fIvss\fP: IN BIT);
-.LP
-END \fIrage\fP;
-.br
-
-.ul
-unidirectionnal data:
-.br
-ENTITY \fIrage\fP IS
-.TP
-PORT(\fIadr\fP: IN BIT_VECTOR(0 TO \fIn\fP);
-\fIdin\fP: IN BIT_VECTOR(0 TO \fIw\fP);
-.br
-\fIdout\fP: OUT BIT_VECTOR(0 TO \fIw\fP);
-.br
-\fIck\fP: IN BIT;
-.br
-\fIwrite\fP: IN BIT;
-.br
-\fIen\fP: IN BIT;
-.br
-\fIvdd\fP: IN BIT;
-.br
-\fIvss\fP: IN BIT);
-.LP
-END \fIrage\fP;
-.br
-.LP
-.B
-Write is active high and 
-.B en
-is active high. When 
-.BR ck
-is high for -ckup option RAMs or ck is low for -ckdown option RAMS the RAM is in precharge state, otherwise it is evaluation (read or write mode). The en signal suspends the normal functionment of the RAM by disabling it when it is '0'. In this case the RAM remains in precharge mode. It is
-authorised to change only at the precharge state of the clock.
-.SH OPTIONS
-.TP 12
-.IB bits
-is the number of bits per word. The range is from 2 to 128, and this number must be even.
-.TP 12
-.IB words
-indicates the size of the ram. The possible values are 128, 256, 512, 1024, 2048 and 4096 words.
-.TP 12
-.B -n|-m|-w
-specifies the aspect/ratio of the generated block. In fact, this generator is designed on the base of:
-.IP
-- 3 line decoders: 6 --> 64, 7 --> 128, 8 --> 256
-.br
-- 4 column decoders(multiplexers): 2 --> 1, 4 -->1, 8 --> 1, 16 --> 1
-.br
-Then, we obtain the following table, corresponding to all the possibilities of our generator:
-.br
-      -------------------------
-.br
-      |          mux          |
-.br
-      |-----------------------|
-.br
-      |  1  |  2  |  3  |  4  |
-.br
- -----|-----------------------|
-.br
- | 6  | 128 | 256 | 512 | 1024|
-.br
- |----|-----------------------|
-.br
- | 7  | 256 | 512 | 1024| 2048|
-.br
- |----|-----------------------|
-.br
- | 8  | 512 | 1024| 2048| 4096|
-.br
- ------------------------------
-.br
-for example: in this configuration we will have three versions of the 1K-word ram.
-.br
-- the first is a 256x4: which is narrow
-.br
-- the second is a 128x8: which is medium
-.br
-- the third is a 64x16: which is wide
-.br
-So, the -n,-m and -w parameters correspond to the different ways of implementation of the ram size regarding to that we want the narrow, the medium or the wide version.
-.br
-.ul
-Note:
-However, there is some cases where the choose is limited and can be not possible(extremity sizes, for ex.)
-.TP 12
-.B -u
-specifies that the input and output data buses must be separated (unidirectionnal)
-.TP 12
-.B -t\fIn\fP
-allows the insertion of one or two allow-ALU2 across the ram (one or two with each bit). \fIn\fP=1 or 2.
-.TP 12
-.B -ckup or -ckdown
-These two options indicate respectively that the generated RAM behaves like a rising edge (ckup) or falling edge (ckdown) flip-flop. -ckdown is the default option.
-.TP 12
-.B -layout
-generates the layout view of the ram
-.TP 12
-.B -vhdl
-gives a vhdl description of the ram
-.TP 12
-.B -physicalbox
-generates only a physicalbox layout of the ram with physical connectors.
-.TP 12
-.B -datasheet
-provides technical and design informations about the ram like size values, function chronograms and propagation delays.
-.TP 12
-.BI -o \|blockname\|
-specifies the name of the generated ram (default name is ram<\fIbits\fP>_<\fIword\fP>)
-.TP 12
-.BI icon
-Provides a VTI schematic compatible icon representing the generated RAM with connectors.
-.SH SPECIAL DIRECTIVES
-All the cells within any generated RAM have been tested and are correct except for one cell
-which is the memory cell which introduces a design rule violation due to its proper design.
-The cell "dtram_c" has an apparent design rule violation. To perform a well DRC on the whole
-generated RAM one have to copy a 'light' version of this cell called "dtram2_c" in the current
-work directory and change its name to "dtram_c" so that the DRC program will take this one
-first.
-.br
-For most tested target technologies, the translation of this cell from symbolic to real 
-gives a good result. In some cases, one have to patch the cell. However, to avoid any problem
-one can follow a process of generation. This process is in fact the default process.
-The cell "dtram_c" must be translated to the target technology before translating all the RAM.
-This cell has a 'G' option into the CATAL file instead of 'C' option. That means that this cell
-must not be translated because the real layout view already exist. So it have to be integrated
-into the global figure (i.e. generated RAM).
-Perform the following operations:
-.IP
-.B s2r dtram_c
-.br
-.B <patch the cell>
-.br
-.B <make a real DRC
-.B on the cell>
-.br
-.B s2r <ram>
-.br
-.LP
-The appropriate RDS_TECHNO_NAME, RDS_IN, RDS_OUT environment variables setting is
-explained in S2R(3).
-For more informations about the tools used to perform this operation, please see S2R(3).
-.SH EXAMPLES
-.IP
-.B rage 64 1024 -m -u -layout
-.B -vhdl -datasheet -o memo
-.LP
-produces the layout and vhdl views of a 1K size ram of 64-bits word , medium aspect/ratio and separated data buses named "memo" and provides informations about its function, timing and layout charachteristics.
-.SH SEE ALSO
-.BR MBK_CATA_LIB (1) ,
-.BR MBK_WORK_LIB (1) ,
-.BR MBK_OUT_PH (1) ,
-.BR MBK_OUT_LO (1) ,
-.BR MBK_IN_PH (1) ,
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/rds.1 b/alliance/share/man/man1/rds.1
deleted file mode 100644
index e7f7c08d..00000000
--- a/alliance/share/man/man1/rds.1
+++ /dev/null
@@ -1,88 +0,0 @@
-.\"   $Id: rds.1,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)rds.1 0.0 93/18/08 UPMC
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-rds
-.XE
-.XS0 \n%
-.ti 0.2i
-rds
-.XE0 \}
-.TH RDS 1 "October 1, 1997" "ASIM/LIP6" "RDS PACKAGE VERSION 103"
-.SH NAME
-rds \- rds package
-.SH DESCRIPTION
-.IP I)
-\fBPresentation of the RDS data structure\fP
-.RS
-.PP
-     Rds is a Rectangle data structure which contains a minimun of information in order to permit to the user to configurate it according to his needs (optimisation of use of the structure). Somme technological parameters of the structure can be configurated by using a technology file (cmos/asga).
-.PP
-     The RDS data structure permits a real representation of objects used because they are described in the forme of rectangles (a chip is a rectangle bag). So, RDS data structure is used by all the tools which need a real rectangle view of a chip (ex: lynx, s2r, graal, druc).
-.RE
-.IP II)
-\fBConcepts used\fP
-.RS
-.PP
-     A figure or an instance structure have a table of layers. Each entry of the table is a pointer to a rectangles's list associated to the corresponding layer.
-.PP
-     The RDS data structure use a high number of rectangles. For optimizing memory acces time when getting a rectangle in memory, memory allocation for a rectangle is done by heap : At the first allocation of a rectangle, a memory for a high number of rectangles is allocated. It permits to minimize fragmentation.
-.PP
-     If the user wants to add other fields to a rectangle structure, he can do it. In that case, a structure defined by the user is added to the rectangle structure (the all rectangle structure is an object of two structures). Functions of RDS library take this particularity into account. 
-.PP	
-     A complementary data structure permits to cut the chip in windows. A window (the size can be modified by the user) knows all the rectangles of the chip contained in it. Moreover, each rectangle can know all windows in which it's contained. This structure is useful to get quickly an object in the chip.
-.PP
-     The rds structure is technology dependant, so it uses a technological file.
-.RE
-.IP III)
-\fBDescription of the structure\fP
-
-The RDS structure is composed of figures, instances and rectangles. The basic structure contains a minimum of information so the user has to add additionnal structure if he wants.
-.RS
-.TP
-\fIA figure\fP
-A figure represents a symbolic view of a chip. It contains rectangles and instances. A figure has a name (it must be unique) which represents it on the disk, a list of instances and a list of rectangles by layer.
-.TP
-\fIAn Instance\fP
-An instance represents a figure described in a higher hierarchical level. An instance has a model name (the figure which describes it) and an instance name (the name of the instance in the current figure: two different instances of a figure must have different names). An instance can subject symmetries and rotations. 
-.TP
-\fIA rectangle\fP
-It is the basic item which permits to constitute objects of a figure. The user can add a structure defined by him to complete the rectangle structure.
-.RE
-.IP IV)
-\fBDescription of the libraries which constitute the RDS package\fP
-.RS
-.TP
-\fIThe Rds library\fP :
-This library contains the description of the RDS structure (figure, instance, rectangle), allocation and free functions of objects, adding functions of objects in a list of objects.
-.TP
-\fIThe Rfm library\fP :
-Contains conversion functions from MBK to RDS objects, visualization functions of objects (MBK and RDS).
-.TP
-\fIThe Rpr library\fP :
-Contains the parser of the technological file of the RDS structure.
-.TP  
-\fIThe Rut library\fP :
-Contains utility functions like searching a figure by its name, creating a list of models of instances contained in a figure.
-.TP
-\fIThe Rtl librairie\fP :
-This library contains environment variables of the RDS structure, function of loading and saving of a figure in the "cif" or "gds" format.
-.TP
-\fIThe Rwi Library\fP :
-It contains all the functions of the windowing of a chip like adding/deleting a window, adding a rectangle in a window, visualization of objects of a window.
-.SH SEE ALSO
-.BR librds,
-.BR librfm,
-.BR librpr,
-.BR librtl,
-.BR librut,
-.BR librwi,
-.BR RDS_IN,
-.BR RDS_OUT,
-.BR RDS_TECHNO_NAME
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/rfg.1 b/alliance/share/man/man1/rfg.1
deleted file mode 100644
index 9bcaea40..00000000
--- a/alliance/share/man/man1/rfg.1
+++ /dev/null
@@ -1,287 +0,0 @@
-.\"   $Id: rfg.1,v 1.3 1999/10/13 15:28:57 franck Exp $
-.\" @(#)Labo.l 6.05 99/10/12 UPMC; Author: Laurent WINCKEL
-.TH RFG 1 "October 1, 1997" "ASIM/LIP6" "ALLIANCE USER COMMANDS"
-.SH NAME
-rfg \- register file generator - version 6.05
-.SH SYNOPSIS
-.B rfg
-.br
-
-.B rfg
-.B -h
-.br
-
-.B rfg
-.I bits words busses ro|rs|ds|ba
-.br
-.B [ -ffd ] 
-.B [ -ffu ] 
-.B [ -id ] 
-.B [ -lp ] 
-.B [ -wel|-weh ] 
-.B [ -stuck ]
-.br
-.B [ -virtual ]
-.B [ -msb0 ]
-.br
-.B [ -layout ]
-.B [ -icon ]
-.B [ -vhdl ]
-.B [ -patterns ]
-.B [ -datasheet ]
-.br
-.B [ -physical_box ]
-.B [ -logical_box ]
-.br
-.B [ -o \fIblockname\fP ]
-.so man1/alc_origin.1
-.SH DESCRIPTION
-The first form is a short on line help.
-.br
-
-The second is a long on line help.
-.br
-
-In the last form, \fBrfg\fP is a register file generator for bit-sliced
-data-paths.
-It generates differents views of a register file and offers a very large range
-of possible parameters.
-The generator respect the CAO-VLSI definition of a data-path.
-The slice is fixed to 60
-lambdas, allows virtual terminals and could be used with the data-path
-compiler
-.BR fitpath (1).
-.LP
-The generator needs a leaf cell library to work well.
-The \fBMBK_CATA_LIB\fP(1) environment variable should contain the path to
-the generator library, \fIrflib\fP.
-.SH OPTIONS
-.TP 25
-.B -h
-long form help.
-.TP
-.I bits
-Word size. The range is from 2 to 64, the value must be even.
-.TP
-.I words
-Number of registers. The range is from 2 to 256, the value must be even.
-.TP
-.I busses
-Number of read busses : 1 or 2. Generated register file has one write address bus and one or two read address busses.
-.TP
-.B ro
-Generates a block without address decoders, with an optimized width.
-.TP
-.B rs
-Generates a block without address decoders, that could be abutted with a decoders block.
-.TP
-.B ds
-Generates a block that contains only the address decoders.
-This block has the same size and the same connectors interface as the block generated with the \fIrs\fP option.
-.TP
-.B ba
-Generates a complete register file with address decoders.
-.TP
-.B -ffd
-Adds output latches then the generated register file work like a falling edge triggered flip-flop rather than a level sensitive latch.
-.TP
-.B -ffu
-Adds output latches then the generated register file work like a rizing edge triggered flip-flop rather than a level sensitive latch.
-.TP
-.B -id
-Inverts data polarity between input bus and output busses.
-.TP
-.B -lp
-Reduces consumption but increases read time. This option is only available for register file which have more than 16 registers.
-.TP
-.B -wel
-Adds a write enable signal. The signal is active low.
-.TP
-.B -weh
-Adds a write enable signal. The signal is active high.
-.TP
-.B -stuck
-The register at address 0 will be stuck to a value of 0.
-.TP
-.B -virtual
-Generates a register file with virtual connectors, as opposed to the default
-that generates steady terminals, to be used by the data-path compiler
-\fPfitpath\fP(1).
-.TP
-.B -msb0
-Index 0 of vectorized busses will be used for the most significant bit, else index 0 will be used for the less significant bit of busses.
-.TP
-.B -layout
-To obtain a layout view.
-The different formats are given by
-.BR mbk (1)
-documentation.
-.TP
-.B -icon
-To obtain a icon view.
-.TP
-.B -vhdl
-To obtain a VHDL data-flow behavioral description view.
-.TP
-.B -patterns
-To obtain a patterns file.
-.TP
-.B -datasheet
-To obtain a data sheet.
-.TP
-.B -physical_box
-To obtain a physical outline view. Cannot be used with the -layout option.
-.TP
-.B -logical_box
-To obtain a netlist view. This view contains only the logical block interface.
-The different formats are given by
-.BR mbk (1)
-documentation.
-.TP
-.B -o \fIblockname\fP
-\fIblockname\fP indicate the user name prefix for all files generated.
-If no name is given, a default name will be composed by the generator.
-For each set of parameters and options, the default name will be different.
-.LP
-Each terminal name is predefined and cannot not be modified by the user.
-Index 0 could be the less significant bit or the most significant following the msb option.
-\fIN\fP represent the number of bits of registers.
-\fIM\fP represent the size of address busses, this size depend on number of registers.
-Terminal names are :
-.TP 25
-\fBad_w[0]-ad_w[\fIM\fP-1]\fP
-Write address
-.TP
-\fBwe\fP
-Write enable signal
-.TP
-\fBad_r_a[0]-ad_r_a[\fIM\fP-1]\fP
-First read address
-.TP
-\fBad_r_b[0]-ad_r_b[\fIM\fP-1]\fP
-Second read address
-.TP
-\fBck_m\fP
-Clock signal
-.TP
-\fBin_a[0]-in_a[\fIN\fP-1]\fP
-Data input
-.TP
-\fBout_a[0]-out_a[\fIN\fP-1]\fP
-First data output
-.TP
-\fBout_b[0]-out_b[\fIN\fP-1]\fP
-Second data output
-.TP
-\fBvdd, vss\fP
-Power supplies
-.LP
-The complete register file dimension are approximately :
-.RS
-width = words * 34 lambdas.
-.br
-height = (bits + 3 * busses + 6) * 60 lambdas.
-.RE
-.SH TIMINGS
-.LP
-The data sheet contains information on register file timings. 
-These informations are only available for complete register file (ba option).
-.br
-Common timings for all register file :
-.TP 10
-\fBtc1\fP
-Minimun width for clock high level.
-.TP
-\fBtc0\fP
-Minimun width for clock low level.
-.TP
-\fBtaws\fP
-Minimum set up time for write address bus before clock rising front.
-.TP
-\fBtawh\fP
-Minimum hold time for write address bus after clock falling front.
-.TP
-\fBtdts\fP
-Minimum set up time for data input bus before clock falling front.
-.TP
-\fBtdth\fP
-Minimum hold time for data input bus after clock falling front.
-.TP
-Additionnal timings for level sensitive latch register file :
-.TP
-\fBtrda\fP
-Maximun read access time from read address bus stabilization to data output (when write address is not equal to read address or when clock is at low level).
-.TP
-\fBtpd\fP
-Maximum propagation delay from data in bus stabilization to data ouput bus (when write address is equal to read address and clock is at high level).
-.TP
-Additionnal timings for edge triggered flip-flop register file :
-.TP
-\fBtars\fP
-Minimum set up time for read address bus before clock falling front.
-.TP
-\fBtarh\fP
-Minimum hold time for read address bus before clock rising front.
-.TP
-\fBtoe\fP
-Maximun read access time from clock falling front to data output.
-.SH EXAMPLES
-.TP
-rfg 24 16 2 rs -o my_reg -physical_box
-Produces the outline view of 16 registers of 24 bits with 2 read busses. The generated file name is "\fImy_reg.xx\fP".
-.TP
-rfg 16 32 1 ba -wel -o test -layout -vhdl
-Produces the layout and vhdl views of a 32 registers of 16 bits complete register file with 1 read bus and a write enable input active at low level. The prefix name of all generated files is "\fItest\fP".
-.SH OUTPUT FILES
-.TP 25
-\fIname\fP.\fBxx\fP
-Layout, physical_box and logical_box views.
-For these views, the suffixes depend on the
-\fBMBK_OUT_PH\fP(1) and \fBMBK_OUT_LO\fP(1) environment variables.
-The \fIname\fP is either the user name entered under the \fB-o\fP
-option, or an internally generated name, as explained under the \fIOPTIONS\fP
-section.
-.TP
-\fIname\fP.\fBicn\fP
-Icon view.
-.TP
-\fIname\fP.\fBvbe\fP
-\fIvhdl\fP behavior.
-.TP
-\fIname\fP.\fBpat\fP
-Set of patterns for validation.
-.SH ENVIRONMENT VARIABLES
-.TP 25
-\fBMBK_CATA_LIB\fP
-contains the directory path of the register file generator leaf cell library.
-This library is by default in \fB"/labo/cells/rfg"\fP, and if not,
-depends upon the system administrator installation.
-.TP
-\fBMBK_WORK_LIB\fP
-contains the directory path of the working directory, usually set to
-\fB"."\fP.
-.TP
-\fBMBK_IN_PH\fP
-contains the format of the register file generator leaf cell library.
-.TP
-\fBMBK_OUT_PH\fP
-contains the expected format of the generated layout.
-.TP
-\fBMBK_OUT_LO\fP
-contains the expected format of the netlist output.
-.SH SEE ALSO
-.BR MBK_CATA_LIB (1),
-.BR MBK_WORK_LIB (1),
-.BR MBK_IN_PH (1),
-.BR MBK_OUT_PH (1),
-.BR MBK_OUT_LO (1),
-.BR mbk (1),
-.BR genlib (1),
-.BR vhdl (1),
-.BR fitpath (1),
-.BR bsg (1),
-.BR grog (1),
-.BR rsa (1).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/ring.1 b/alliance/share/man/man1/ring.1
deleted file mode 100644
index 9226357b..00000000
--- a/alliance/share/man/man1/ring.1
+++ /dev/null
@@ -1,347 +0,0 @@
-.\"   $Id: ring.1,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)Labo.l 0.0 90/22/08 UPMC;
-.TH RING 1 "October 1, 1997" "ASIM/LIP6" "ALLIANCE USER COMMANDS"
-.SH NAME
-RING \- PAD RING router
-.SH SYNOPSIS
-RING \fIsource\fP \fIresult\fP \fB[ stat ]\fP
-.so man1/alc_origin.1
-.SH DESCRIPTION
-.IR source
-defines two input files:
-.RS
-\-\- the file describing the input netlist (MBK_IN_LO(1) format).
-.br
-.RS
-example: source.al
-.br
-.LP
-.RE
-\-\- the parameter file: source.rin
-.br
-This file consists in 5 sections: 4 for the pad placement on circuit
-sides, one to define the power sypply width (in lambda units).
-.LP
-.br
-.TP 10
-example:
-.RS
-.IR east
-() # none pad at east side.
-.br
-.IR north
-(
-.br
-p_pck p_i0 p_i1
-.br
-p_i3)
-.br
-.IR south
-(p_vssb p_vddb p_i2)
-.br
-.IR width
-(vss 50 vdd 80)
-.br
-.RE
-.LP
-Separators (spaces, tabulations and new line) are allowed between instance names.
-.LP
-.br
-\-\- east(), north(), south(), west() define the relative pad order.
-They use the pad instance names.
-.LP
-.br
-For the north() and south() sections, the instance name declaration
-are from the 
-.IR left
-(first pad) to the
-.IR right
-(last pad).
-.LP
-.br
-For the east() and west() sections, the instance name declaration
-are from the 
-.IR bottom
-(first pad) to the
-.IR top
-(last pad).
-.LP
-.br
-Any section may be missing. It means so the revalive side has no pad, 
-however at least one side must has one pad.
-.LP
-.br
-\-\- the width() section is optional and describes the
-power (vdd), and ground (vss) track width.
-.LP
-.br
-.RE
-.IR \fIresult\fP 
-defines the output filename.
-.LP
-.br
-.RS
-This file contains the layout of the routed circuit (MBK_OUT_PH(1) format).
-.br
-.RS
-example: result.ap
-.LP
-.RE
-.br
-RING uses a pad library whose path directory is defined with the 
-MBK_CATA_LIB(1) environment variable.
-It also uses a catalog filename which is defined with the MBK_CATAL_NAME(1)
-environment variable.
-.br
-The catalog must contain all the pad model names used in the
-circuit. The core model-name must not be present in the catalog.
-.br
-.LP
-Part of catalog file:
-.RS
-.br
-a2_y  C
-.br
-high_y  C
-.br
-pck_sp C
-.br
-piot_sp  C
-.br
-pvssick_sp  C
-.br
-\.\.\.\.
-.br
-pvdde_sp C
-.br
-pvddi_sp C
-.br
-.LP
-.RE
-.br
-.RE
-.IR [stat]
-(optional parameter) defines another output file:
-.br
-.LP
-.RS
-.br
-\-\- the statistic file: result.stat
-.br
-.LP
-It contains data about length (lambdas) and area (lambdas * lambdas) in ALU1 and ALU2, for each
-equipotential. It describes how many vias were placed.
-.br
-.LP
-.RS
-example: *** STATISTIC FILE < result.stat > ***
-.br
-.LP
-.RE
-Equipotential list :
-.br
-.LP
-.nf
-.if t \{\
-.ft CR \}
-index|   name   |lgth A1|lgth A2|area A1|area A2| nb vias
-.br
-_________________________________________________________
-.br
- 60  |      vss | 9034  | 4408  | 614288| 454024| 1128
-.br
-_________________________________________________________
-.br
- 59  |      vdd | 7494  | 3968  | 574248| 408704| 1128
-.br
-_________________________________________________________
-.br
- 54  | b2_coeur | 2253  | 1899  |   2253|   3798|    4
-_________________________________________________________
-.br
-Total length alu1  :        18781 (lambdas)
-.br
-Total length alu2  :        10275 (lambdas)
-.br
-Total area alu1    :      1190789 (lambdas * lambdas)
-.br
-Total area alu2    :       866526 (lambdas * lambdas)
-.br
-Total of vias      :         2260
-.br
-.ft R
-.fi
-.LP
-.RE
-.br
-.LP
-.SH ENVIRONMENT VARIABLES
-.LP
-.br
-\fBMBK_IN_LO(1)\fP defines the input file format for the netlist.
-.br
-\fBMBK_IN_PH(1)\fP defines the input file format for the layout.
-.br
-\fBMBK_OUT_PH(1)\fP defines the output file format for the layout.
-.br
-\fBMBK_CATAL_NAME(1)\fP defines the catalog filename.
-.br
-\fBMBK_CATA_LIB(1)\fP defines the library pad cells directory.
-.br
-\fBMBK_WORK_LIB(1)\fP defines the work directory.
-.br
-.LP
-.SH USAGE
-.LP
-.br
-RING performs the physical routing between core of
-circuit and pad ring. 
-RING is not a floor plan router and allows only one core.
-.LP
-.br
-A core is designed, for example, with the standard
-cells router SCR, which places the input and output connectors on 
-the abutment box. The physical core connectors must be
-separated by more than one pitch in any metal (in ALU1 or ALU2).
-.LP
-.br
-Netlist and layout views relative to the same figure must have
-the same name. For example, the netlist core name and the routed core name.	
-.LP
-.br
-RING performs an automatic placement of the pad ring
-and core. It is not necessary to place pads, but only
-to describe their relative position on each side, in the parameter file
-(source.rin).
-.LP
-.br
-Distance between the first track and any instance (pad or core) is the pitch
-so 5 lambdas.
-.FF 
-.br
-.SH EXAMPLE
-.LP
-.br
-Let chip.al be the circuit netlist and core.ap the routed core.
-80 lambdas for supply track width and the pad placement are described as follows.
-.LP
-.RE
-.br
-.br
-.TP 10
-.IR chip.rin:
-.LP
-.RS
-# This is a comment: 1 comment per line
-.br
-north(p_a1 p_a2 p_a3 p_a4)
-.br
-south(
-.br
-p_i1 #another comment: the rest of the line
-.br
-p_i2
-.br
-p_i3
-.br
-p_i4)
-.br
-east(p_b4 p_b3 p_b2 p_b1)
-.br
-west(p_f1 p_f2 p_f3 p_f4)
-.br
-width(
-.br
-vdd 80
-.br
-vss 80
-.br
-)
-.br
-.TP 10
-We want a ring of pads as follow:
-.LP
-.br
-.RS
-.nf
-.if t \{\
-.ft CR \}
-+-------------------------------------------------+
-.br
-|            |p_a1|p_a2|p_a3|p_a4|                |
-.br
-|----+---------------------------------------+----|
-.br
-|p_f4|                                       |p_b1|
-.br
-|----|            +-------+                  |----|
-.br
-|p_f3|            |       |                  |p_b2|
-.br
-|----|            | CORE  |                  |----|
-.br
-|p_f2|            |       |                  |p_b3|
-.br
-|----|            +-------+                  |----|
-.br
-|p_f1|                                       |p_b4|
-.br
-|----+---------------------------------------+----|
-.br
-|            |p_i1|p_i2|p_i3|p_i4|                |
-.br
-+-------------------------------------------------+
-.ft R
-.fi
-.LP
-.RE
-.br
-.br
-In order to obtain the routed circuit (chipr.ap):
-.LP
-.br
->
-.IR ring
-.IR chip
-.IR chipr
-.LP
-.br
-.SH "SEE ALSO"
-genlib(1)
-lvx(1)
-scr(1)
-druc(1)
-
-
-.SH DIAGNOSTICS
-Physical core must have at least one physical connector by side,
-otherwise it can't place pads correctly, and maybe dump a core file.
-.LP
-.br
-Whenever lots of core connectors (bus) are placed close ones from each others, 
-RING may have problems to connect pad connectors placed just in front of them.
-In such a case, it is recommended to not have pad connectors at that place and 
-thus to place an instance pad without connector (as pvdde_sp)
-or to cut the bus into several parts to let space between connectors.
-.LP
-.br
-When core connectors are to close from corners, RING sometimes connects those
-one to supply rings, to solve this bug, move core connectors or change pad 
-placement. In any case, use \fBdruc(1)\fP or \fBlvx(1)\fP to detect problem.
-.br
-.LP
-Supply vdd and vss pads (resp. pvddi_sp and pvssi_sp) 
-must be placed as close as possible of the core side middle
-(i.e. not in the corners). 
-Otherwise, RING cannot link supply pad connector to ring supplies and
-exits with a error message.
-.br
-.LP
-Supply tracks from pads and core are connected at the supply ring.
-There is sometimes few problems when core and pad tracks are opposite.
-Move pads usually corrects problem.
-.br
-.LP
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/rsa.1 b/alliance/share/man/man1/rsa.1
deleted file mode 100644
index e010d09a..00000000
--- a/alliance/share/man/man1/rsa.1
+++ /dev/null
@@ -1,227 +0,0 @@
-.\"   $Id: rsa.1,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)Labo.l 0.0 91/04/02 UPMC; Author: Luis LUCAS
-.TH RSA 1 "October 1, 1997" "ASIM/LIP6" "ALLIANCE USER COMMANDS"
-.SH NAME
-rsa \- Recurrence Solver Adder generator
-.SH SYNOPSIS
-.B rsa
-.I bits
-.B [ -cin ] [ -cout ] [ -overn ] [ -not ]
-.B [ -csa ] [ -sub ] [ -addsub ]
-.B [ -over ] [ -deci ] [ -stretch ] [ -stretch2 ]
-.B [ -msb0 ] [ -virtual ]
-.B [ -layout ] [ -icon ] [ -vhdl ] [ -patterns ] [ -datasheet ]
-.B [ -physicalbox ] [ -logicalbox ] [ -perf ]
-.B [ -o \fIblockname\fB ]\fP
-.so man1/alc_origin.1
-.SH DESCRIPTION
-.B rsa
-is a fast adder generator for bit-sliced data-paths.
-The slice is fixed to 60 lambdas, allows virtual terminals, and could be
-used with the data-path compiler
-.BR fitpath (1).
-The algorithm used is a binary carry-look-ahead adder (Recurrence Solver Adder)
-to offer the highest performance.
-The technology employed is CMOS 5V nwell process.
-.LP
-Each signal name is predefined and can not be modified by the user.
-Each signal name suffixed by
-.I _n
-indicates that the polarity signal is complemented.
-Index 0 is the most significant bit when \fB-msb0\fP is specified and
-.I bits
-represent the number of bits.
-Signal names are :
-.TP 20
-a[0]-a[\fIbits\fP-1]
-First input operand
-.TP
-b[0]-b[\fIbits\fP-1]
-Second input operand
-.TP
-c[0]-c[\fIbits\fP-1]
-Third input operand if option \fBcsa\fP is selected.
-.TP
-cin
-Carry in
-.TP
-cout
-Last carry output
-.TP
-coc
-Overflow when three operands
-.TP
-co[0]-co[\fIbits\fP-1]
-Intermediates carries
-.TP
-s[0]-s[\fIbits\fP-1]
-Sum result
-.TP
-sub
-When is equal to 5V, it is a subtractor, otherwhise an adder.
-.TP
-vdd[],vss[]
-Power supplies
-.LP
-The width of the block is given by :
-.TP
-width = 73 + (27*(Log2(\fIbits\fP)+1)) + 67(if \fBcsa\fP) + 16(if \fBcout\fP) lambdas
-.TP
-height = \fIbits\fP*60 lambdas
-.LP
-The generator needs a library cells to well compute.
-The \fBMBK_CATA_LIB\fP(1) environment variable should contain the path to the
-library \fIgalib\fP.
-.SH OPTIONS
-.TP
-.IB bits
-The range is from 3 to 128 bits.
-.TP
-.B -cin
-The generated adder will contain a carry input connector on the North side in
-Metal1 layer.
-.TP
-.B -cout
-The generated adder will contain all the intermediates carry, accessible in
-Metal2 Layer, with the multi-access possibilities.
-.TP
-.B -overn
-The generated adder will contain the previous carry output \fBover\fP in Metal1
-layer on the North side.
-This signal could be used to calculate an overflow flag = over^cout.
-.TP
-.B -not
-The output sum will be complemented but still keep the connector name
-.BR s .
-.TP
-.B -csa
-The generated adder will be an adder with 3 operands, and one overflow connector
-on the North side in Metal1 layer.
-.TP
-.B -sub
-The adder generated is, in fact, a subtractor, and performs always a-b. If the
-option \fB-cin\fP is present, then the block calculates a+not(b)+cin .
-.TP
-.B -addsub
-The block obtained is a adder/subtractor. If the input terminal is set to 5V
-then it is a subtractor. If the option \fB-cin\fP is present, then the block
-performs a+xor(b,sub)+cin.
-.TP
-.B -over -deci -stretch -stretch2
-Bull Options.
-.TP
-.B -msb0
-Default is index 0 for the least significant bit. When \fB-msb0\fP is present
-the the most significant bit is indexed with 0.
-.TP
-.B -virtual
-Default blocks contain fixed terminals. Virtual terminals can be obtained
-using this option. This way,
-.BR dpr (1) router should optimized the resultant routed data-path.
-.TP
-.B -layout
-The generated view asked is a layout view. The different formats are given by
-.BR mbk (1)
-documentation, using
-.BR MBK_OUT_PH (1)
-environment variable.
-.TP
-.B -icon
-Icon view for schematic capture. The possible output formats are specified
-setting the ICON_OUT (1) environement variable.
-.TP 
-.B -vhdl
-The generated view asked is a data-flow behavioural view. The description of
-the VHDL used is gived by
-.BR vhdl (5).
-.TP
-.B -patterns
-Some test vectors are proposed to validate the generated block. The format used
-is the
-.BR pat (5)
-one accepted by the VHDL simulator
-.BR asimut (1).
-.TP
-.B -datasheet
-Principals process dependent informations are proposed to estimate the adder
-performances. It is the default view if none is specified.
-.TP
-.B -physicalbox
-The generated view asked is a interface view. The different formats are given by
-.BR mbk (1)
-documentation, using
-.BR MBK_OUT_PH (1)
-environment variable.
-.TP
-.B -logicalbox
-The generated view asked is an interface netlist view.
-The different formats are given by
-.BR mbk (1)
-documentation, using
-.BR MBK_OUT_LO (1)
-environment variable.
-.TP
-.B -perf
-Programmer Option
-.TP
-.BI -o \|blockname\|
-The generated adder name will be \fIblockname\fP.
-.SH EXAMPLES
-.IP
-.B rsa 32 -cin -cout -layout -vhdl
-.LP
-Produce the layout and vhdl view of a two operands adder with carry in
-and final intermediates carries with the default name:
-.TP
-.B rsa32daaa.cp
-.TP
-.B rsa32daaa.vbe
-.LP
-.SH OUTPUT FILES
-.TP 20
-.IB \|name\| .xx
-The layout  and netlist views. The suffix
-depends on the
-.BR MBK_OUT_LO (1)
-and 
-.BR MBK_OUT_PH (1)
-environment variables.
-\fIname\fB is \fIblockname\fP or, by default, prefixed by \fIrsa\fB.
-.TP 
-.IB \|name\| .vbe
-The \fBVHDL\fP behavioral view of the shifter.
-.SH ENVIRONMENT VARIABLES
-.TP 20
-.B MBK_CATA_LIB
-contains the directory path of the recurrence solver adder leaf cells library.
-This library is, by default, in \fI/labo/cells/rsa\fP, and if not, depends upon
-the system administrator installation.
-.TP
-.B MBK_WORK_LIB
-contains the directory path of the working
-directory. Usually set to \fB.\fP .
-.TP
-.B MBK_IN_PH
-contains the format of the recurrence solver adder leaf cells library.
-.TP
-.B MBK_OUT_PH
-contains the desired format of the layout output.
-.TP
-.B MBK_OUT_LO
-contains the desired format of the netlist output.
-.SH SEE ALSO
-.BR MBK_CATA_LIB (1),
-.BR MBK_WORK_LIB (1),
-.BR MBK_OUT_PH (1),
-.BR MBK_OUT_LO (1),
-.BR MBK_IN_PH (1),
-.BR vhdl (5),
-.BR pat (5),
-.BR fitpath (1),
-.BR rfg (1),
-.BR bsg (1),
-.BR grog (1),
-.BR genlib (1)
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/s2r.1 b/alliance/share/man/man1/s2r.1
deleted file mode 100644
index 245395d6..00000000
--- a/alliance/share/man/man1/s2r.1
+++ /dev/null
@@ -1,174 +0,0 @@
-.\"   $Id: s2r.1,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)Labo.l 0.0 90/21/08 UPMC; Author: Fr'ed'eric P'etrot & Franck Wajsburt
-.TH S2R 1 "October 1, 1997" "ASIM/LIP6" "ALLIANCE USER COMMANDS"
-.SH NAME
-.TP
-s2r
-\- Process mapping from symbolic layout to physical layout
-.SH SYNOPSIS
-.TP
-\fBs2r\fP [\fB-sc1rv\fP] \fIsource\fP [\fIresult\fP]
-.so man1/alc_origin.1
-.SH DESCRIPTION
-The goal of \fBs2r\fP is to perform the translation from the symbolic layout
-to physical layout for the foundry.
-\fBs2r\fP uses a technolgy file whose name is defined by the environnement 
-variable RDS_TECHNO_NAME.
-.br
-Some cells, like I/O pads, are specific to a given foundry.
-In the symbolic methodology, these cells are phantom cells.
-It means that only their abutment box and and connectors are present.
-\fBs2r\fP wil substitute physical cells to the symbolic phamtom cells.
-Beware, this implies that the manufacturer cells must be modified by hand to
-ensure the abutment box is a symbolic grid step multiple, and that the
-real connectors are centered on symbolic grid.
-.br
-In order for the replacement to work well, the physicals cells must have
-the abutment box lower left corner at coordinate (0,0)
-The name of cells to be replaced are written in the catalog file with the
-G attribute, see \fBcatal\fP(5) for details on that file.
-See also \fBring\fP(1) for more on pads.
-Ouput can be generated in either cif or gds formats, to fit the manufacturer
-requirements.
-.br
-.LP
-Mainly two kinds of users are concerned with \fBs2r\fP :
-.TP 21
-experts
-they should be able to parametrize the technology file for a new process
-technology file is described in \fBtechno(5)\fP.
-.TP
-designers
-they are not directly concerned with the target process, but need to be able to
-compute real capacitances for simulation.
-.PP
-The \fIsource\fP argument is the name of the symbolic layout file to be
-translated.
-The optional \fIresult\fP argument indicates the name to be given to the real
-layout output.
-This name is also the name of the top level model of the layout hierarchy.
-If \fIresult\fP name is omitted, then \fIsource\fP name is used.
-.PP
-Six environment variables must be set for proper usage of \fBs2r\fP,
-all of them having default values, thus ensuring the possibility of using it
-``as it is''.
-.TP 21
-MBK_IN_PH
-The input format for symbolic layout is given by this environment variable.
-The possible values are \fI cp, ap\fP. Default is \fIcp\fP.
-See \fBMBK_IN_PH\fP(1) for details.
-.TP
-MBK_CATA_LIB
-Sets the directories that are to be searched thru for reading files. 
-The seaching mecanism first look in MBK_WORK_LIB(1) 
-MBK_WORK_LIB
-defines the path where the generated file is saved.
-Make sure the write permissions are set up correctly, otherwise no save
-will occur.
-.TP
-MBK_CATAL_NAME
-This indicates the name of the catalog file used for pad substitution.
-For the appropriate syntax of this file, see \fBcatal\fP(5). 
-.TP
-RDS_IN
-Defines the format to be used as input for cell substitution.
-The available ones are \fIcif\fP and \fIgds\fP (default one).
-The cells to be parsed must not containt 45
-.ie t \(de
-.el degrees
-wires. If an unknown layer is encountered, the entire cell will be skipped.
-.TP
-RDS_OUT
-Gives the format of the output file.
-This may be either \fIcif\fP or \fIgds\fP (default is \fIgds\fP).
-.TP
-RDS_TECHNO_NAME
-This points to the technology file to be used for symbolic to real translation.
-This file is in general shared between all the designers.
-it is the full path name to the file location, with the extension.
-.SH OPTIONS
-Without option, \fBs2r\fP should produce a layout that fits for the foundry.
-Nevertheless, its behaviour can be modified when invoked with the
-following options:
-.TP 21
-\-s
-Suppress the denotching phase. \fBs2r\fP performs gap filling, denotching
-in order to avoid DRC errors. This operation is time consuming.
-It is mandatory for the foundry but not really useful for capacitance 
-evaluation.
-.TP
-\-c 
-Deletes connectors and node names at all hierarchy level.
-Theses objects link the physical view and the logical view of a chip.
-If simulation is to be done after physical mapping, connectors must appear,
-so that the extractors and simulators can use them.
-This must \fInot\fP be used when preparing a final layout for the foundry.
-.br
-For the factory, the top level connectors are forbidden, since they do not
-represent any physical reality.
-.TP
-\-1
-Creates the top level cell with the instances as black boxes.
-This may be useful for hierarchical extractors, since the file size may be
-greatly reduced.
-.TP
-\-r
-does not replace black boxes.
-Cells flagged with the \fBG\fP attribute in the \fBcatal\fP(5) file will not
-be replaced by their equivalent layout loaded from disk.
-.TP
-\-v
-verbose mode on.
-
-
-.SH EXAMPLES
-.RS
-You should first have a correct execution environment :
-.br
-It is recommanded to put it in the ``.cshrc'' file if in c shell, as in the
-example below.
-.RE
-.br
-.ie t \{\
-.ft CR \}
-.el \fB
-.ta 30n
-.nf
-       setenv MBK_IN_PH	ap
-       setenv MBK_WORK_LIB      ~fred/mbk/layout
-       setenv MBK_CATA_LIB      ~franck/s2r:/alliance/cells
-       setenv MBK_CATAL_NAME    catalog
-       setenv RDS_TECHNO_NAME   /labo/etc/prol15.rds
-       setenv RDS_IN            gds
-       setenv RDS_OUT           gds
-       s2r -c na2_y
-.fi
-.ft R
-.RS
-This invocation will produce the cell \fBna2_y\fP from the standard cell
-library in real layout, without connectors, scotches if needed, in gds format.
-.RE
-.SH SEE ALSO
-.BR mbk (1),
-.BR ring(1),
-.BR MBK_IN_PH (1),
-.BR MBK_CATA_LIB (1),
-.BR MBK_WORK_LIB (1),
-.BR MBK_CATAL_NAME (1),
-.BR RDS_IN (1),
-.BR RDS_OUT (1),
-.BR RDS_TECHNO_NAME (1),
-.BR techno(5),
-.BR catal(5).
-
-.SH DIAGNOSTICS
-.br
-The actual version of the gds parser and driver doesn't translate neither
-connectors, nor node names.
-If an extraction on s2r output is needed, cif format will create the
-connectors using cif extension \fB4X\fP, and the node names with \fB4N\fP.
-
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/scapin.1 b/alliance/share/man/man1/scapin.1
deleted file mode 100644
index d3975066..00000000
--- a/alliance/share/man/man1/scapin.1
+++ /dev/null
@@ -1,156 +0,0 @@
-.pl -.4
-.TH SCAPIN 1 "Juin 29, 2000" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
-.SH NAME
-.TP
-scapin - Scan path insertion
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.TP
-\f4scapin [\-VRB] [\-P file] Input_name Path_name Output_name
-.br
-.SH DESCRIPTION
-\fBSCAPIN\fP is an automatic scan path generator for gate level netlists.
-\fBSCAPIN\fP inserts a scan path in the netlist \fBInput_name\fP and drives 
-a new netlist \fBOutput_name\fP.
-This scan path contains all registers specified in the file \fBPath_name\fP.path
-(see below for the exact syntax).
-\fBSCAPIN\fP adds also 3 new connectors in the netlist: scan_in, scan_out and
-scan_test in order to control the scan path.
-Eventually \fBSCAPIN\fP adds an output buffer before the output connector
-scan_out (option -B).
-.br
-
-.SH ENVIRONMENT VARIABLES
-.br
-.TP 10
-\f4MBK_WORK_LIB\fR(1)
-indicates the path to the read/write directory for the session.
-.br
-.TP 10
-\f4MBK_IN_LO\fR(1)
-indicates the input netlist file format.
-.br
-.TP 10
-\f4MBK_OUT_LO\fR(1)
-indicates the output netlist file format.
-.br
-.TP 10
-\f4SCAPIN_PARAM_NAME\fR
-indicates the location of a parameter file (with extention .scapin) containing
-the properties (ports name, models name etc ...) of all cells needed for the
-scan path insertion.  (see below for the exact syntax)
-.br
-
-.SH OPTIONS
-.TP 10
-\f4\-V\fP
-Sets verbose mode on.
-Each step is displayed on the standard output.
-.TP 10
-\f4\-R\fP
-All registers of the scan path are replaced by an equivalent scannable register cell
-(called reg-mux).  (With the default option a simple multiplexor is added just
-before all registers of the scan path).
-.TP 10
-\f4\-B\fP
-Adds an output buffer before the output connector scan_out.
-.TP 10
-\f4\-P file\fP
-Specifies a parameter file (with extention .scapin) containing the properties of
-all cells needed for the scan path insertion.
-(see below for the exact syntax)
-
-.nf
-# Example of .scapin file
-
-BEGIN_MUX
-
-MUX_MODEL        mx2_x2
-MUX_SEL          cmd
-MUX_INPUT_SEL    i1
-MUX_INPUT_NSEL   i0
-MUX_VDD          vdd
-MUX_VSS          vss
-MUX_OUTPUT       q
-
-END_MUX
-
-
-BEGIN_REG
-
-REG_MODEL        sff1_x4
-REG_CLK          ck
-REG_INPUT        i
-REG_VDD          vdd
-REG_VSS          vss
-REG_OUTPUT       q
-REG_MUX          mx2_x2
-REG_REG_MUX      sff2_x4
-
-END_REG 
-               
-
-BEGIN_REG_MUX
-
-REG_MUX_MODEL        sff2_x4
-REG_MUX_SEL          cmd
-REG_MUX_INPUT_SEL    i1
-REG_MUX_INPUT_NSEL   i0
-REG_MUX_CLK          ck
-REG_MUX_VDD          vdd
-REG_MUX_VSS          vss
-REG_MUX_OUTPUT       q
-REG_MUX_MUX          mx2_x2
-REG_MUX_REG          sff1_x4
- 
-END_REG_MUX   
-
-
-BEGIN_BUF
-
-BUF_MODEL            buf_x2
-BUF_INPUT            i
-BUF_VDD              vdd
-BUF_VSS              vss
-BUF_OUTPUT           q
-
-END_BUF   
-.fi
-
-
-.TP 10
-\f4\Path_name\fP
-Specifies a parameter file (with extention .path) containing an ordered list of
-all instances (registers) of the scan path.
-It contains also the name of the 3 connectors scan_in, scan_out and scan_test.
-(see below for the exact syntax)
-
-.nf
-# Example of .path file
-
-BEGIN_PATH_REG
-
-cs_0
-cs_1
-cs_2
-
-END_PATH_REG
-
-BEGIN_CONNECTOR
-
-SCAN_IN      scin
-SCAN_OUT     scout
-SCAN_TEST    test
-
-END_CONNECTOR
-
-.fi
-.ti 7
-
-.SH SEE ALSO
-.BR MBK_IN_LO (1).
-.BR MBK_OUT_LO (1).
-.BR MBK_WORK_LIB (1).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/scmap.1 b/alliance/share/man/man1/scmap.1
deleted file mode 100644
index 09faa9bd..00000000
--- a/alliance/share/man/man1/scmap.1
+++ /dev/null
@@ -1,131 +0,0 @@
-.\"   $Id: scmap.1,v 1.2 2001/04/04 13:19:58 francois Exp $
-.\" 
-.\" 
-.\"   $Id: scmap.1,v 1.2 2001/04/04 13:19:58 francois Exp $
-.\" 
-.\" 
-.pl -.4
-.TH SCMAP 1 "October 1, 1997" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
-.SH NAME
-.TP
-scmap
-\- mapping of a behavioural description onto a standard cell library.
-
-
-.so man1/alc_origin.1
-
-.SH SYNOPSIS
-.TP
-\fBscmap\fP  \fIdata_flow_file\fP \fIoutput_file\fP  [\fIparameter_file\fP]
-.br
-
-.SH DESCRIPTION
-.br
-
-.br
-\fB  Input description\fP
-.br
-
-.br
-You should rather use the newest version of \fBboog\fP.
-The logic level behavioural description (.vbe file) uses the same VHDL subset as the logic simulator \fBasimut\fP, the FSM synthesizer \fBsyf\fP, the functional abstractor \fByagle\fP and the formal prover \fBproof\fP (for further information about the subset of VHDL, see the "vbe" manual). 
-.br
-A special feature has been introduced in the VHDL subset in order to allow the don't care description for external outputs and internal registers : A bit signal can take the 'd' value. 
-This value is interpreted as a '0' by the logic simulator \fBasimut\fP. 
-Don't Cares are automatically generated by \fBsyf\fP in the resulting '.vbe' file.
-.br
-For the register signal, only one signal can appear in a guarded expression since the STABLE attribute is used. This attribute is only supported by technology mapping onto a standard cell library as \fBsclib\fP. 
-
-\fBscmap\fP is the second step of the logic synthesis : it builds a gate network using
- a predefined standard cell library as SCLIB. 
-.br
-
-.br
-\fB  Mapping with a standard cell library\fP
-.br
-
-.br
-Every cell appearing in the directory defined by the environment variable MBK_TARGET_LIB may be used by \fBscmap\fP since they are described as a '.vbe' file. There are some restrictions about the type of the cell used. Every cell has to have only one output. For the combinational cells, two levels maximum (AND-OR or OR-AND) are required for the logical function.
-The cell must be characterized. The timing and area informations required by \fBscmap\fP are specified in the "generic" clause of the ".vbe" file.
-.br
-
-.br
-\fB  Parameter file '.lax'\fP
-.br
-The parameter file is common with other logic synthesis tools and is used
-for driving the synthesis process. 
-See \fBlax\fP(5) manual for more detail.
-
-.br
-\fBlax\fP uses a lot of parameters to guide every step of the synthesis process.
-Some parameters are globally used (for example, \fIoptimization level\fP whereas others are specifically used (\fBload capacitance\fP for the netlist optimization only).
-Here is the default parameter file (see the user's manual for further information about the syntax of the '.lax' file):
-.br
-
-.br
-   Optimization mode = 2 (50% area - 50% delay)
-.br
-   Optimization level = 2 
-.br
-   Delayed input = 0
-.br
-   Early output = 0
-.br
-   Auxiliary signal saved = 0
-.br
-   Number of serial transistors = 4 in N and P area
-.br
-
-
-
-.SH ENVIRONMENT VARIABLES
-.br
-The following environment variables have to be set before using \fBscmap\fP :
-.HP
-.ti 7
-\fIMBK_WORK_LIB\fP gives the path of the directory of both input and output files (behavioural, structural and parameters description).
-.HP
-.ti 7
-\fIMBK_CATA_LIB\fP gives the auxiliary paths of the directories of input files (behavioural description). 
-.HP
-.ti 7
-\fIMBK_TARGET_LIB\fP gives the path (single) of the directory of the selected standard cell library. 
-.HP
-.ti 7
-\fIMBK_C4_LIB\fP gives the path (single) of the directory for the three views of each cell generated by C4.
-.HP
-.ti 7
-\fIMBK_IN_LO\fP gives the format of models instantiated in the structural description.
-.HP
-.ti 7
-\fIMBK_OUT_LO\fP gives the output format of the structural description.
-.HP
-.ti 7
-\fIMBK_OUT_PH\fP gives the output format for the layout of the cells generated by C4.
-
-
-.SH EXAMPLE
-.br
-You can call \fBscmap\fP as follows :
-.br
-.br
-	scmap alu4 alu4c4
-
-
-
-.SH SEE ALSO
-.br
-scmap(1), lax(1), c4map(1), xlmap(1), proof(1), yagle(1), asimut(1), vhdl(5), scr(1), sclib(1), boog(1), boom(1), loon(1), scapin(1), sxlib(1).
-.br
-
-
-.SH DIAGNOSTICS
-.br
-"VHDL : Error - bad usage of the 'stable' attribut"
-.br
-The stable attribut must be used with only one signal in a guarded expression
-.br
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/scr.1 b/alliance/share/man/man1/scr.1
deleted file mode 100644
index 50b452bf..00000000
--- a/alliance/share/man/man1/scr.1
+++ /dev/null
@@ -1,352 +0,0 @@
-.\"   $Id: scr.1,v 1.2 2000/08/30 08:14:06 syf Exp $
-.\" @(#)Labo.l 0.0 92/09/24 UPMC; Author: El housseine REJOUAN
-.pl -.4
-.TH SCR 1 "October 1, 1997" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
-.SH NAME
-.TP
-scr
- - Standard Cell Router
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.TP
-\fBscr\fP 
-[\fB-p\fP] [\fB-r\fP] [\fB-c \fIChannelName\fP] [\fB-i \fIIterationNumber \fP] [\fB-l \fIRowNumber\fP] [\fB-a \fISupplyNumber\fP] [-sclib]
-.br
-[\fB-o \fIOutputFileName\fP] \fIsource\fP 
-.br
-.SH DESCRIPTION
-\fBscr\fP is an automatic place and route tool for standard-cells.
-.br
-
-\fB1/ standard cells\fP
-.br
-\fBscr\fP uses a catalog file whose name is defined by the environment variable \fBMBK_CATAL_NAME\fP. This file must contain the standard cells names.
-.br
-The cells must have the same height, but they can have different width (multiple of the pitch).
-.br
-Power and ground connectors defined by the environment variable \fBMBK_VDD\fP and \fBMBK_VSS\fP must be
- in metal1 on the WEST and EAST sides of the abutment-box of the cells.
-.br
-Other connectors must be in metal2  only on the NORTH and SOUTH sides of the abutment-box of the cells.
-They must be pitched.
-.br
-If two connectors of the cell have the same name, the router will consider them electrically connected inside the cell. \fBscr\fP uses this feature to go through the cell.
-.br
-One or several attributes can be associated with each cell. The attributes that concern the router are:
-.br
-\fBC\fR : for Catalog, associated to the leaf cells that will not be flattened. 
-.br
-\fBF\fR : for Feed-through, associated to the cells which are used as feed-through, a feed-through may do not appear in the logical net-list. 
-.br
-For more details on the catalog file see catal(5).
-.br
-The files describing the physical and the logical view for each cell must be located in one of the directories defined by the environment variable \fBMBK_CATA_LIB\fP.
-
-\fB2/ input net-list\fP
-.br
-The \fIsource\fP file describes the input net-list.
-.br
-\fBscr\fP supports a hierarchical net-list. In this case the net-list is flattened by the router according to the catalog file. The net-list format can be : structural VHDL, EDIF, or ALLIANCE internal format according to the environment variable \fBMBK_IN_LO\fP.
-.br
-
-\fB3/ output layout\fP
-.br
-The file containing the routed block will have the name \fIsource\fP if the -o option is not used, otherwise the \fIOutputFileName\fP is used. The output format is defined by the environment variable \fBMBK_OUT_PH\fP.
-.br
-The router uses two layers for routing: metal1 for the horizontal wires, and metal2 for the vertical wi
-res.
-.br
-The first metal1 horizontal wires are six LAMBDAs from the NORTH and SOUTH abutment-box sides of the cells.
- The horizontal PITCH between metal1 wires is equal to five LAMBDAs.
-A six LAMBDAs margin is ensured between the extreme horizontal wires of the circuit and its NORTH and S
-OUTH abutment-box sides.
-.br
-The first metal2 vertical wires are three LAMBDAs from the WEST and EAST abutment-box sides of routed circu
-it. The vertical PITCH between metal2 wires is equal to six LAMBDAs.
-.br
-There are two possibilities for the output layout:
-.br
-If the -c option is used, the routing channels and cell rows are instanciated as intermediate hierarchical blocks.(their names are prefixed by \fIChannelName\fP). Otherwise the instances of the routed figure are the input net-list leaf cells.
-.br
-The names for power and ground sources are given by the environment variables MBK_VDD and MBK_VSS. The
-default values are vdd and vss.
-.br
-All power and ground are internally connected by two vertical metal2 wires (one for VDD, one for VSS).
-It is possible to increase the number of vertical power and ground wires with the -a option.
-.br
-
-\fB4/ Optional cells placement file\fP
-.br
-A user defined placement can be specified, thanks to a placement file.
-.br
-The optional placement file must have the same name as the input net-list with a extension that denotes the format defined by the environment variable \fBMBK_IN_PH\fP.
-.br
-The circuit to be routed must be composed of horizontal rows. The height of each row is the height of the standard-cells. The cells must not overlap.
-.br
-This placement can also be hierarchical. In this case the hierarchy must be the same as the input net-list.  Each logical instance must correspond to one and only one physical instance, and each physical instance must correspond to one and only one logical instance.
-.br
-This constraint does not apply to the physical cells with F attribute into the catalog file. 
-.br
-
-\fB5/ Optional connectors and feed-through placement file\fP
-.br
-The placement of connectors can be also specified : which connector on which side, and the relative order of connectors on one side.
-.br 
-The same logical connector can be placed on several sides.
-.br
-This information is contained in a file that has the same name as the input net-list file, with the \fB".scr"\fP extension.
-.br
-In this \fIsource\fP\fB.scr\fP file, all lines begining whith a \fB"#"\fP (sharp) are comments.
-.br
-To define the position of the connectors four instructions can be  used :
-.IP
-\fB PLACE_PHCON_NORTH \fR \fIname order\fP \fB;\fR
-.br
-\fB PLACE_PHCON_SOUTH \fR \fIname order\fP \fB;\fR
-.br
-\fB PLACE_PHCON_WEST \fR \fIname order\fP \fB;\fR
-.br
-\fB PLACE_PHCON_EAST \fR \fIname order\fP \fB;\fR
-.LP
-where \fI"name"\fP is the logical connector name and \fI"order"\fP is the index.
-.br
-If the relative placement on a given side is undefined the \fI"order"\fP parameter takes the value \fB"-1"\fP.
-.br
-In \fB WEST \fR and \fB EAST \fR sides, the \fI order \fP parameter of connectors on these sides can not be defined by the user (so the \fI order \fP parameter on these sides takes the value "-1").
-.br
-A vectorized syntax is usable for buses.
-.br
-\fBscr\fR can be place vertical and horizontal feed-through in the routed circuit (this can be used by the floor-plan router to route over the block).
-.br
-Two instructions are usable :
-.br
-.IP
-\fB HOR_FEED_THROUGH\fR \fIn\fP \fB;\fR
-.br
-\fB VER_FEED_THROUGH\fR \fIm\fP \fB;\fR
-.LP
-where \fIn\fP and \fIm\fP are the number of feed-through.
-.br
-The horizontal feed-throughs are placed in the middle channel of the routed circuit.
-.br 
-The vertical feed-throughs are placed regulary over the entire width of the routed circuit according to the number of vertical power and ground wires. If a null number is given for -a option, the vertical feed-throughs are placed in the middle of the routed circuit.
-.br
-This is an example :
-.IP
-\fB PLACE_PHCON_NORTH\fR in3 4\fB;\fR
-.br
-\fB PLACE_PHCON_NORTH\fR in2 1\fB;\fR
-.br
-\fB PLACE_PHCON_NORTH\fR in1 2\fB;\fR
-.br
-\fB PLACE_PHCON_SOUTH\fR in0 4\fB;\fR
-.br
-\fB PLACE_PHCON_SOUTH\fR in5 0\fB;\fR
-.br
-\fB PLACE_PHCON_WEST\fR in7 -1\fB;\fR
-.br
-\fB PLACE_PHCON_EAST\fR in6 -1\fB;\fR
-.LP
-The result of this set of instructions, is a circuit having on it's \fI"NORTH"\fP side
-four connectors whose names are the following order (i.e. from left to right : in2, in1 and in3), on it's \fI"SOUTH"\fP side two connectors whose names are the following order (i.e. from left to right : in5 and in0).
-.br
-If the position of a connector on a given side is not crucial the "order" parameter may be set to "-1".
-.br
-for examples :
-.IP
-\fB PLACE_PHCON_NORTH\fR in3 -1\fB;\fR
-.LP
-The syntax has the same structure as before but the parameters "name" and "order" are written as vectors.
-.br
-for examples :
-.br
-The following sets of instruction give the same result.
-.IP
- Non vectorized structure :
-\fB PLACE_PHCON_NORTH\fR in[3] 4\fB;\fR
-.br
-\fB PLACE_PHCON_NORTH\fR in[2] 3\fB;\fR
-.br
-\fB PLACE_PHCON_NORTH\fR in[1] 2\fB;\fR
-.br
-\fB PLACE_PHCON_NORTH\fR in[0] 1\fB;\fR
-.br
-\fB PLACE_PHCON_WEST\fR in[5] -1\fB;\fR
-.br
-\fB PLACE_PHCON_WEST\fR in[6] -1\fB;\fR
-.IP
- Vectorized  structure :
-\fB PLACE_PHCON_NORTH\fR in[0:3] 1:4\fB;\fR
-.br
-\fB PLACE_PHCON_WEST\fR in[0:3] -1\fB;\fR
-.LP
-To vectorized buses, the characters \fB"()"\fR can be used instead \f4"[]"\fR.
-.br
-.SH OPTIONS
-.TP 20
-\-o \fIOutputFileName\fP 
-renames the output file name to OutputFileName. By default, the name of the input net-list file is used.
-.TP 20
-\-p 
-This option invokes the automatic placement process. 
-.TP 20
-\-r 
-This option invokes the automatic routing process.
-.br
-So \fBscr\fP must be used with at least one of -p or -r options:
-.br
--p	automatic place, no route.
-.br
--r	automatic route, no place.
-.br
--p -r	automatic place and route.
-.TP 20
-\-c \fIChannelName\fP 
-If this option is used ,the rows and channels will be instanciated as intermediate hierarchical levels.
-.br
-Otherwise the result will be flattened to the standard cells.
-.TP 20
-\-i \fIIterationNumber\fP 
-This option is used to improve the quality of the placement, and consequently of the routing. The default value is the number of cells.
-.TP 20
-\-l \fIRowNumber\fP 
-This option allows the designer to set the number of rows.
-The default value is computed to provide a square result.
-.TP 20
-\-a \fISupplyNumber\fP 
-This option allows the designer to set the number of vertical power and ground wires. The default value is one.
-.TP 20
-\-sclib
-This option must be used for sclib netlist (for upward compatibility).
-.br
-
-.SH ENVIRONMENT
-\f4scr\fR relies on the proper setting of the following environment variables :
-.TP 20
-\f4MBK_CATA_LIB\fR(1)
-gives the path to the cell libraries. 
-.TP 20
-\f4MBK_WORK_LIB\fR(1)
-furnishes the path to the working directory.
-.TP 20
-\f4MBK_IN_PH\fR(1)
-indicates the input layout format.
-.TP 20
-\f4MBK_OUT_PH\fR(1)
-indicates the output layout format.
-.TP 20
-\f4MBK_IN_LO\fR(1)
-indicates the input structural file format.
-.TP 20
-\f4MBK_VDD\fR(1)
-sets the name of power supply. "vdd" is the default. Every external port of the circuit whose name contain this string will be considered as a power supply.
-.TP 20
-\f4MBK_VSS\fR(1)
-sets the name of ground. "vss" is the default. Every external port of the circuit whose name contain this string will be considered as a ground.
-
-.SH EXAMPLES
-To use \fBscr\fP, some environment variables must be set :
-.br
-If the ALLIANCE format is used, the user must have the following environment:
-.br
-.BR 	MBK_CATA_LIB 
-=/labo/cells/sclib/prol10
-.br
-.BR 	MBK_IN_LO 
-=vst
-.br
-.BR 	MBK_IN_PH 
-=ap
-.br
-.BR 	MBK_OUT_PH 
-=ap
-.br
-.BR 	MBK_CATAL_NAME 
-=CATAL
-.br
-.BR 	MBK_WORK_LIB 
-=. 
-.br
-.BR 	MBK_VDD 
-=vdd 
-.br
-.BR 	MBK_VSS 
-=vss 
-.br
-The command line to be executed for routing the circuit called, for example, "core" with all options is:
-.br
-.TP
-\fBscr\fP -p -r -i 500 -l 6 -c chan -a 2 -o core_r core 
-.br
-The input net-list will be the file core.vst
-.br
-The resulting file will be core_r.ap
-.br
-The number of iterations is equal to 500
-.br
-The number of rows is equal to 6
-.br
-The result will be hierarchical
-.br
-Two power and ground wires are placed in the routed circuit.
-.br
-.TP
-\fBscr\fP -r -p -a 3 -o alur  alu 
-.br
-This command makes a placement and routing on the circuit "alu" with 3 vertical power and ground wires.
-.br
-The resulting file will be alur.ap
-.br
-.TP
-\fBscr\fP -r -p -a 0 alu 
-.bR
-If a null number is given for the -a option as in this example,there will be no vertical power and ground wires and all the external power and ground connectors will have different names.
-.br
-The resulting file will be alu.ap
-.br
-.SH SEE ALSO
-.BR mbkenv (3),
-.BR bbr (1),
-.BR sclib (1),
-.BR ring (1),
-.BR genlib(1),
-.BR catal(5),
-
-
-
-.SH DIAGNOSTICS
-.br
-.BR 1/
-\fISegment and via lists must be NULL!!\fP
-.br
-This message can appear if:
-.br
--The user tries to route a figure already routed.
-.br
--The catalog file is not accessible, or it is incomplete and the router has flattened a cell not included in the catalog.
-.br
-
-.BR 2/ 
-\fILogic "INS_NAME" does not exist in the physical view!!\fP
-.br
-Logic instance in the net-list is not declared in the placement.
-.br
-
-.BR 3/ 
-\fIPhysical "INS_NAME" does not exist in the logical view!!\fP
-.br
-Physical instance in the placement file is not declared in the net-list.
-.br
-
-.BR 4/ 
-\fIPhysical connector "CON_NAME" does not exist in the logical view!!\fP
-.br
-The physical internal connector called "CON_NAME" is not declared in the net-list.
-
-.BR 5/ 
-\fIImpossible configuration : the number of connectors to be placed on south/north side is greater than the existing number of pitchs.\fP
-.br
-In this case, the user may user lower number of rows to overcome this placement problem.
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/syf.1 b/alliance/share/man/man1/syf.1
deleted file mode 100644
index 2ab690dd..00000000
--- a/alliance/share/man/man1/syf.1
+++ /dev/null
@@ -1,119 +0,0 @@
-.\"   $Id: syf.1,v 1.3 2000/09/06 09:24:19 francois Exp $
-.\" @(#)Labo.l 2.2 95/09/24 UPMC; Author: Jacomme L.
-.pl -.4
-.TH SYF 1 "October 1, 1997" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
-.SH NAME
-.TP
-SYF \- Finite State Machine synthesizer.
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.TP
-\f4syf \-a|j|m|u|o|r [\-CDEOPRSTV] input_name [output_name]
-.br
-.SH DESCRIPTION
-.br
-\fBsyf\fp is a Finite State Machine synthesizer.
-\fBsyf\fp allows a fast generation of VHDL Data Flow description (see \fBvbe\fP(5))
-from a VHDL Finite State Machine description (see \fBfsm\fP(5)).
-The input FSM specification can use an internal STACK.
-Both MOORE and MEALEY FSMs can be synthesized, with output registers if desired.
-For a MOORE FSM, a timing\-optimized implementation that emulates a ROM with microsequencer
-is possible.
-A scan-path for the state registers can also be implemented.
-.br
-
-.SH ENVIRONMENT VARIABLES
-.br
-.TP 10
-\f4MBK_WORK_LIB\fR(1)
-indicates the path to the read/write directory for the session.
-.br
-
-.SH OPTIONS
-.TP 10
-\f4\-a\fP
-Uses "Asp" as encoding algorithm.
-.TP 10
-\f4\-j\fP
-Uses "Jedi" as encoding algorithm.
-.TP 10
-\f4\-m\fP
-Uses "Mustang" as encoding algorithm.
-.TP 10
-\f4\-u\fP
-Uses an encoding given by user through <input_name>.enc file.
-In this file, a line started by a # character is a comment.
-A valid line contains one state name followed by its hexadecimal code.
-.TP 10
-\f4\-o\fP
-Uses the one hot encoding algorithm.
-.TP 10
-\f4\-r\fP
-Uses distinct random numbers for state encoding.
-.TP 10
-\f4\-C\fP
-Checks the transition's consistency.
-.TP 10
-\f4\-D\fP
-With this option \fBsyf\fP doesn't optimize unused, i.e Don't Care, codes.
-.TP 10
-\f4\-E\fP
-Saves the encoding result in the <output_name>.enc.
-This file has the same syntax as <input_name>.enc file which is used by \-u option.
-.TP 10
-\f4\-O\fP
-With this option \fBsyf\fp places registers on the outputs.
-.TP 10
-\f4\-P\fP
-Implements a scan-path for the state registers, stack registers and possibly output registers. Scan-path mechanism is directely included in states decoder. Users should use \fBscapin\fP(5) for a correct insertion of a scan-path in a netlist.
-Please check \fBfsm\fP(5) for information about scan-path descriptions.
-.TP 10
-\f4\-R\fP
-This option is only available for MOORE FSM. With this option, \fBsyf\fP emulate
-s a ROM with micro\-sequencer implementation : there is no combinatorial logic between
-the state registers and the FSM outputs.
-This can be mandatory for external timing constraints.
-See \fBfsm\fP(5) and \fBgrog\fP(1) for more on ROM descriptions.
-.TP 10
-\f4\-S\fP
-With this option \fBsyf\fp doesn't take into account the cost of the transitions to compute
-an encoding.
-.TP 10
-\f4\-V\fP
-Verbose mode on.
-Each step of the FSM synthesis is displayed on the standard output, along with some statistics.
-.ti 7
-.SH EXAMPLE
-.br
-Environment variables:
-.br
-.ti 7
-setenv MBK_WORK_LIB /alliance/tutorials/dlxm
-.br
-.ti 7
-
-\fBsyf\fP is called as follow (the dlx_ctrl.fsm is already created in /alliance/tutorials/dlxm) :
-
-.ti 7
-\fBsyf\fP -sE dlx_ctrl
-
-Two files will be generated, a states encoding file dlx_ctrls.enc and a VHDL data flow file /alliance/tutorials/dlxm/dlx_ctrls.vbe
-.SH SEE ALSO
-.BR fsm (5),
-.BR vbe (5),
-.BR vhdl (5),
-.BR boom (1),
-.BR boog (1),
-.BR loon (1),
-.BR scapin (1),
-.BR bop (1),
-.BR glop (1),
-.BR scmap (1),
-.BR c4map (1),
-.BR asimut (1),
-.BR proof (1),
-.BR MBK_WORK_LIB (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/vasy.1 b/alliance/share/man/man1/vasy.1
deleted file mode 100644
index 30770bd3..00000000
--- a/alliance/share/man/man1/vasy.1
+++ /dev/null
@@ -1,114 +0,0 @@
-.\"   $Id: vasy.1,v 1.8 2000/04/12 13:28:32 syf Exp $
-.\" @(#)Labo.l 2.2 95/09/24 UPMC; Author: Jacomme L.
-.pl -.4
-.TH VASY 1 "November 26, 1999" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
-.SH NAME
-.TP
-VASY \- VHDL Analyzer for Synthesis
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.TP
-\f4vasy [\-VpavsoipSHL] [\-C num] [\-E num] [\-I format] [\-P file] filename [outname]
-.br
-.SH DESCRIPTION
-.br
-\fBVASY\fp is a hierarchical VHDL Analyzer for Synthesis.
-\fBVASY\fp performs a semantic analysis of a VHDL RTL description 
-\fBfilename\fP, with a VHDL subset much more extended than the Alliance one
-(see vasy(5) for more details), and identifies with precision all the 
-memorizing elements and tristate buffers.
-.br
-During its analysis, \fBVASY\fp expands generic parameters, executes generic map
-and generate statements, and also unrolls static FOR loops.
-.br
-At the end, \fBVASY\fp drives an equivalent description
-\fBoutname\fP (in Verilog or VHDL format) accepted by most of
-synthesis tools.
-.br
-
-.SH ENVIRONMENT VARIABLES
-.br
-.TP 10
-\f4MBK_WORK_LIB\fR(1)
-indicates the path to the read/write directory for the session.
-.br
-
-.SH OPTIONS
-.TP 10
-\f4\-V\fP
-Verbose mode on.
-Each step of the analysis is displayed on the standard output.
-.TP 10
-\f4\-v\fP
-Drives an equivalent description in \fBVerilog\fP format.
-.TP 10
-\f4\-a\fP
-Drives an equivalent description in Alliance VHDL format \fBvbe\fP(5) and/or
-\fBvst\fP(5).
-We can note that with this option, all arithmetic operators are expanded in an
-equivalent set of boolean expressions, because these operators don't belong to
-the Alliance VHDL subset.
-.TP 10
-\f4\-s\fP
-Drives an equivalent VHDL description (with the extention \fB.vhd\fP)
-accepted by most of industrial synthesis tools.
-.TP 10
-\f4\-S\fP
-Uses Std_logic instead of Bit (taken into account only with option -s).
-.TP 10
-\f4\-i\fP
-Drives initial signal values (taken into account only with option -s).
-.TP 10
-\f4\-I format\fP
-Specifies the VHDL input format such as Alliance VHDL format \fBvbe\fP(5),
-\fBvst\fP(5) or industrial VHDL format \fBvhd\fP or \fBvhdl\fP.
-.TP 10
-\f4\-H\fP
-In a structural description, all model of instances are recursively analyzed.
-(By default \fBVASY\fp analyzes only models with generic parameters)
-The leaves cells are defined by a file called CATAL (see catal(5) for details).
-.TP 10
-\f4\-o\fP
-Authorizes to overwrite existing files.
-.TP 10
-\f4\-p\fP
-Adds power supply connectors (vdd and vss). Usefull option to enter in Alliance.
-.TP 10
-\f4\-C num\fP
-When the size of the adder is greater or equal to \fBnum\fP a Carry Look Ahead
-adder is generated, instead of a Ripple Carry adder.
-(taken into account only with option -a).
-.TP 10
-\f4\-E num\fP
-Comparators are expanded in an equivalent set of boolean expressions, when their
-size is greater than \fBnum\fP 
-(taken into account only with option -a).
-.TP 10
-\f4\-L\fP
-A file .lax (see lax(5) for details) is generated. This file contains the list of 
-all signals that must be kept during the synthesis step, using \fBbop\fP (see
-bop(1) for details). (taken into account only with option -a).
-.TP 10
-\f4\-P file\fP
-Specifies a file containing a list of logical and physical package name:
-.nf
-# Example
-work.constants.all  : pkg_constants
-work.components.all : pkg_components
-.fi
-.ti 7
-
-.SH SEE ALSO
-.BR vasy (5),
-.BR vbe (5),
-.BR vhdl (5),
-.BR catal (5).
-.BR lax (5).
-.BR asimut (1),
-.BR bop (1),
-.BR MBK_WORK_LIB (1).
-.BR MBK_CATA_LIB (1).
-.BR MBK_CATAL_NAME (1).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/xmbk.1 b/alliance/share/man/man1/xmbk.1
deleted file mode 100644
index 21afd392..00000000
--- a/alliance/share/man/man1/xmbk.1
+++ /dev/null
@@ -1,112 +0,0 @@
-.\"                ,,,
-.\"               (o o)
-.\"  ####=====oOO--(_)--OOO=========================================####
-.\"  ##                                                               ##
-.\"  ##   This file is part of FPT : A Formal Proof Toolkit           ##
-.\"  ##   (C) 1996, MASI, CAO-VLSI Team                               ##
-.\"  ##                                                               ##
-.\"  ##   File            :  magic.1 (manual file)                    ##
-.\"  ##   Author          :  Olivier SIROL                            ##
-.\"  ##   Date            :  Sep 1996                                 ##
-.\"  ##                                                               ##
-.\"  ##   E-mail support  :  cao-vlsi@masi.ibp.fr                     ##
-.\"  ##                                                               ##
-.\"  ####===========================================================####
-.\" 
-.\" 
-.\"   $Id: xmbk.1,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" 
-.\" 
-
-.TH XMBK 1 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-.SH NAME
-.I xmbk
-\-  A simple way to set alliance environnement variables
-
-.so man1/alc_origin.1
-
-.SH SYNOPSIS
-
-.TP
-\fBxmbk\fP [\fI-h\fP] [\fI-u\fP] [\fI-c\fP]
-.br
-
-.SH DESCRIPTION
-.I Xmbk
-is a graphical interactive tool that let you set some environment variables 
-used by Alliance CAD tools whitin the shell session it has been executed.
-.I Xmbk
-lets you also save this environnement in a script file for later use.
-.sp
-This program is self explanatory : baloon help will appear when leaving the
-cursor on an environnement variable name.
-.sp
-.I Xmbk
-prints shell commands for setting these environment variables.
-For this output to take effect, \fIxmbk\fP must either be evaluated
-as part of the command line (usually done with a shell alias or function) or
-else redirected to a file which can then be read in.  From the C shell (usually
-known as \fI/bin/csh\fP), the following alias could be defined in the 
-user's \fI.cshrc\fP (Don't forget the '\\' before the word xmbk to avoid alias loop.) :
-
-.sp
-.nf
-        %  alias xmbk 'eval \fC`\fP\\xmbk\fC -c\fP`'
-.fi
-.sp
-When he wants to change its Alliance Environment, the user would type:
-.sp
-.nf
-        %  xmbk
-.fi
-.sp
-Users of versions of the Bourne shell (usually known as \fI/bin/sh\fP) that 
-don't have command
-functions will need to send the output to a temporary file and the read it back
-in with the ``.'' command ('eval' should work whith bash the same way as csh) :
-.sp
-.nf
-        $  xmbk > /tmp/out
-        $  .\0/tmp/out
-.fi
-.SH OPTIONS
-The following options may be used with \fIxmbk\fP:
-.TP 8
-.B \-u
-This option indicates that Bourne shell commands should be generated.
-.TP 8
-.B \-c
-This option indicates that C shell commands should be generated.
-
-
-.SH FILES
-.TP 15
-~/.profile
-user's alias for the command.
-.TP 15
-~/.cshrc
-user's alias for the command.
-
-
-
-.SH SEE ALSO
-.br
-\fBcsh\fP(1),
-\fBtcsh\fP(1),
-\fBsh\fP(1),
-\fBbash\fP(1),
-\fBMBK_IN_LO\fP(1),
-\fBMBK_IN_PH\fP(1),
-\fBMBK_OUT_LO\fP(1),
-\fBMBK_OUT_PH\fP(1),
-\fBMBK_CATA_LIB\fP(1),
-\fBMBK_CATAL_NAME\fP(1),
-\fBMBK_TARGET_LIB\fP(1),
-\fBMBK_WORK_LIB\fP(1),
-\fBMBK_VDD\fP(1),
-\fBMBK_VSS\fP(1),
-\fBELP_TECHNO_NAME\fP(1),
-\fBRDS_TECHNO_NAME\fP(1)
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/xpat.1 b/alliance/share/man/man1/xpat.1
deleted file mode 100644
index da44a8bd..00000000
--- a/alliance/share/man/man1/xpat.1
+++ /dev/null
@@ -1,91 +0,0 @@
-.TH XPAT 1 "September 1, 2000" "ASIM/LIP6" "ALLIANCE Reference Manual"
-.SH NAME
-xpat \- graphic pattern viewer
-.SH SYNOPSIS
-.B xpat
-[\-l file_name]
-[\-xor]
-[\-install]
-[\-force]
-.br
-.so man1/alc_origin.1
-.SH DESCRIPTION
-.B Xpat
-is a pattern viewer. All functionnalities can be
-accessed through different menus.
-.B Xpat
-works under Motif and X11r6.
-When entering 
-.B Xpat,
-the main window appears and shows 5 different
-menus on the top bar. These menus can be entered by simply clicking on the
-mouse left button. Here is the description of these menus.
-
-.TP 10
-.B File
-\f4Open\fP : load an existing pattern file (see pat(5)).
-.br
-\f4Quit\fP : quit xpat.
-
-.TP 10
-.B Edit
-\f4Identify\fP : identify a selected pattern.
-.br
-\f4Connected\fP : highlight a selected pattern.
-.br
-\f4Search\fP : search a pattern.
-
-.TP 10   
-.B View
-\f4Zoom\fP : perform zoom in, zoom out, center, fit, refresh on figure.
-.br
-\f4Layer\fP : select types of layers displayed.
-.br
-\f4Map\fP : show cursor position in the entire figure.
-.br
-\f4Arrows\fP : show arrows for moving at the grid step.
-.br
-\f4Grid\fP : Set the X,Y step of the grid if displayed.
-
-.TP 10
-.B Tools
-\f4Message\fP : display the last error messages
-
-.TP 10
-.B Setup
-Save or load a user defined configuration of default displayed menus.
-
-.SH SPECIAL KEYS
-.TP
-+/-
-Increase or decrease the time scale.
-
-.SH OPTIONS
-.TP
-\-l file_name
-Load the pattern file file_name (without extention .pat)
-.TP
-\-xor 
-Two graphic cursor methods can be used, invert or xor.
-.TP
-\-force
-this option force all graphical objects to be displayed. 
-.TP
-\-install
-Switch to a private color map.
-
-.SH ENVIRONMENT VARIABLES
-.TP
-.B MBK_WORK_LIB
-indicates the path to the read directory for the session.
-.TP
-.B XPAT_PARAM_NAME (optionnal)
-indicates the path to the parameter file used by Xpat.
-.TP
-
-.SH SEE ALSO
-mbk(1), MBK_WORK_LIB(1), PAT(5), asimut(1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man1/xsch.1 b/alliance/share/man/man1/xsch.1
deleted file mode 100644
index d355519c..00000000
--- a/alliance/share/man/man1/xsch.1
+++ /dev/null
@@ -1,135 +0,0 @@
-.TH XSCH 1 "September 1, 2000" "ASIM/LIP6" "ALLIANCE Reference Manual"
-.SH NAME
-xsch \- graphical schematic viewer
-.SH SYNOPSIS
-.B xsch
-[\-l file_name]
-[\-xor]
-[\-install]
-[\-force]
-[\-I input_format]
-[\-slide file_name ...]
-.br
-.so man1/alc_origin.1
-.SH DESCRIPTION
-.B Xsch
-is a graphical schematic viewer. All functionnalities can be
-accessed through different menus.
-.B Xsch
-works under Motif and X11r6.
-When entering 
-.B Xsch,
-the main window appears and shows 5 different
-menus on the top bar. These menus can be entered by simply clicking on the
-mouse left button. Here is the description of these menus.
-
-.TP 10
-.B File
-\f4Open\fP : load an existing file. Note that a file with the same name
-and the extention .xsc can be used to attach special
-colors and comments to all displayed objects (see below for details).
-.fi
-.br
-\f4Quit\fP : quit xsch.
-
-.TP 10
-.B Edit
-\f4Identify\fP : identify a selected object.
-.br
-\f4Connected\fP : highlight a selected object.
-.br
-\f4Search\fP : search an object by its name.
-
-.TP 10   
-.B View
-\f4Zoom\fP : perform zoom in, zoom out, center, fit, refresh on figure.
-.br
-\f4Layer\fP : select types of layers displayed.
-.br
-\f4Map\fP : show cursor position in the entire figure.
-.br
-\f4Arrows\fP : show arrows for moving at the grid step.
-.br
-\f4Grid\fP : Set the X,Y step of the grid if displayed.
-
-.TP 10
-.B Tools
-\f4Hierarchy\fP : enable user to browse into the design hierarchy.
-.br
-\f4Message\fP : display the last error messages
-
-.TP 10
-.B Setup
-Save or load a user defined configuration of default displayed menus.
-
-.SH SPECIAL KEYS
-.TP
-+/-
-Next or previous file in slide mode.
-
-.SH OPTIONS
-.TP
-\-l file_name
-Load the file file_name (with or without extention)
-.TP
-\-xor 
-Two graphic cursor methods can be used, invert or xor.
-.TP
-\-force
-this option force all graphical objects to be displayed. 
-.TP
-\-install
-Switch to a private color map.
-.TP
-\-I input_format
-Specifies the input format (vst(5), al(5), vbe(5))
-.TP
-\-slide file_name ...
-Enables slide mode, all specifies files will be displayed one by one
-using keys +/- in the graphic window.
-
-.SH XSC FILE FORMAT
-.nf
-# Example of .xsc file
-#
-# To attach a particular color and comment to a box :
-# B:box_name:color:comment
-# color is an integer from 0 to 32, or -1 for no_color
-# comment is a string
-B:my_box:0:this box should be blue
-B:another_box:-1:this won't change the box color
-#
-# To attach a particular color and comment to a net :
-# N:net_name:color:comment
-N:my_net:15:this net should be green
-#
-# To attach a particular color and comment to a connector :
-# C:connector_name:color:comment
-C:my_con:32:this connector should be red
-#
-# To attach a particular color and comment to a path :
-# P:from_name:net_name:to_name:color:comment
-P:my_con:my_net:my_box:15:this path should be green
-
-
-.SH ENVIRONMENT VARIABLES
-.TP
-.B MBK_CATA_LIB
-indicates the path to the read only libraries to be used. 
-.TP
-.B MBK_WORK_LIB
-indicates the path to the read directory for the session.
-.TP
-.B MBK_IN_LO
-indicates the file format to be used.
-.TP
-.B XSCH_PARAM_NAME (optionnal)
-indicates the path to the parameter file used by Xsch.
-.TP
-
-.SH SEE ALSO
-mbk(1), MBK_CATA_LIB(1), MBK_WORK_LIB(1), PAT(5), asimut(1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/ACTION.3 b/alliance/share/man/man3/ACTION.3
deleted file mode 100644
index 8307bda7..00000000
--- a/alliance/share/man/man3/ACTION.3
+++ /dev/null
@@ -1,39 +0,0 @@
-.\"   $Id: ACTION.3,v 1.2 2001/04/25 08:31:47 czo Exp $
-.\" @(#)ACTION.2 2.20 Sep 09 1993 UPMC ; VUONG H.N. 
-.TH ACTION 3 "October 1, 1997" "ASIM/LIP6" "GENPAT functions"
-
-.SH NAME
-.PP
-\fBACTION\fP \- GENPAT Package
-
-.SH SYNOPSYS
-.PP
-.nf
-ACTION("instruction");
-.fi
-
-.so man1/alc_origin.1
-.SH PARAMETERS
-.PP
-.TP 10
-\fIinstruction\fP
-The action asked.
-There is only one instruction available : S, to save the current state of the circuit at the end of the simulation.
-
-.SH DESCRIPTION
-.PP
-To give instructions to the simulator.
-
-.SH EXAMPLES
-.PP
-.nf
-ACTION("S");
-.fi
-
-.SH SEE ALSO
-.PP
-genpat(1), pat(5)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/AFFECT.3 b/alliance/share/man/man3/AFFECT.3
deleted file mode 100644
index 744ab236..00000000
--- a/alliance/share/man/man3/AFFECT.3
+++ /dev/null
@@ -1,83 +0,0 @@
-.\"   $Id: AFFECT.3,v 1.3 1999/10/25 08:03:12 simcity Exp $
-.\" @(#)AFFECT.3 2.30 Sep 08 1993 UPMC ; VUONG H.N. & PITON D.
-.TH AFFECT 3 "October 1, 1997" "ASIM/LIP6" "GENPAT functions"
-
-.SH NAME
-.PP
-\fBAFFECT\fP, GENPAT Package
-
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.PP
-.nf
-AFFECT ("pattern_date", "ident", "value");
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIpattern_date\fP
-: pattern date which may be either : integer (absolute date) or + integer
-(relative date, the date of the current pattern (last modified using INIT
-or AFFECT) is the reference). All dates are supposed to be expressed in 
-the same time unit which may be set only once using SETTUNIT.
-.TP 10
-\fIident\fP
-Either the name of a bused signal or a scalar. Vectors must be referenced with
-their names only, or bit per bit. For example, if b(3 downto 0) exists, you
-can affect "b", "b(3)" or "b 3". 
-.TP 10
-\fIvalue\fP
-The value associated with the signal which may be either a based number
-(ex. binary: 0b011 ,hexa:  0x3F, octal: 0o56) or a decimal number. Unknown
-value (value where a '*' appears), can be used when dealing with an output,
-a signal, a register or an input/output when this last one is to be tested. 
-Star ('*') can appears everywhere in a BASED number, but the result will be a
-"full star" value. (For example, "0B0*10" and "0B***" would give the same
-result.) AFFECT is doing automatically the transformation of the value into
-a "forced" value or a "tested" value except for the bidirectional connectors
-affectation. When and bidirectional is to be tested, a '?' character must be
-added before the value (example : "?0x45f*" instead of "0x45f*").
-
-.SH DESCRIPTION
-.PP
-"Affect" a value to a signal. This value will be apllied to the signal, at
-the specified simulation date, until the end of the simulation or until a new
-value is affected to the signal. Beware : Inputs have to be affected at the
-begining of the simulation (first pattern at 0 ps). By default, signals
-(except Inputs) are affected with a "full star" value at the first pattern.
-
-.PP
-This fonction also set the current pattern.
-
-.SH EXAMPLES
-.PP
-.nf
-SETTUNIT("ps");
-AFFECT ("5", "b", "0B1");
-result :            b
-<      5 ps> :.....1...;
-.fi
-
-.PP
-At simulation date 0 ps the signal b(3 downto 0) receives the value "0001".
-This value will be kept until the end of the simulation if no more affectation
-is made.
-
-.nf
-SETTUNIT("ns");
-AFFECT ("0", "b", "0B0");
-AFFECT ("2", "b", "0B1");
-result :            b
-<      0 ns> :.....0...;
-<      2 ns> :.....1...;
-.fi
-
-
-.SH SEE ALSO
-.PP
-genpat(1), pat(5)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/ARRAY.3 b/alliance/share/man/man3/ARRAY.3
deleted file mode 100644
index ec1038ea..00000000
--- a/alliance/share/man/man3/ARRAY.3
+++ /dev/null
@@ -1,101 +0,0 @@
-.\"   $Id: ARRAY.3,v 1.2 1999/10/25 08:03:13 simcity Exp $
-.\" @(#)ARRAY.3 2.30  UPMC ; VUONG H.N. & PITON D.
-.TH ARRAY 3 "October 1, 1997" "ASIM/LIP6" "GENPAT functions"
-
-.SH NAME
-.PP
-\fBARRAY\fP, GENPAT Package
-
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.PP
-.nf
-ARRAY ("ident", "ident", ..., ":nb_space", "format", type, option, "ident_group", 0);
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIident\fP
-Name, followed with a number if part of a bused signal, of a connector, a
-signal or a register. All idents must be of the same type. The name and the
-number must be separated by a blank or the number must be parenthesized.
-.TP 10
-\fInb_space\fP
-Specify the number of blank space between each group of value. 0,1,2,3,4,5,6,
-7,8,9 or nothing.
-.TP 10
-\fIformat\fP
-Specify the format that will be used to represent the value associated to
-the connectors. X for Hexadecimal, O for Octal and B for Binary.
-.TP 10
-\fItype\fP
-Specify the type of the aggregate. REGISTER for Register, SIGNAL for Signal,
-OUT for Output, IN for Input, INOUT for Input/Output. REGISTER, SIGNAL, OUT,
-IN, INOUT are constants (defines) provided by genpat.
-.TP 10
-\fIoption\fP
-Specify options of the connectors. "S" for a spied connector, empty ("")
-for a normal connector.
-.TP 10
-\fIident_group\fP
-Specify the array's name, the first ident is associated with the MSB of the
-array.
-
-.SH DESCRIPTION
-.PP
-Create a virtual vector with signals of the same type and format. The signals
-may be either Inputs, Outputs, Inputs/Outputs, Registers or Internal Signals.
-A vector to be aggregate is to be declared bit per bit (it will appear as a
-vector in the output file). Outputs, Signals and Registers can be redeclared
-in a virtual vector. Inputs and Inputs/Outputs CANNOT be redeclared.
-
-.SH EXAMPLES
-.PP
-.nf
-ARRAY ("cout", "s 9", "s 8", "s 7", ":2", "B", OUT, "S", "Y", 0);
-
-format : Binary.
-type   : Output connector.
-option : spied connector.
-
-each group is separated of the others with 2 blank spaces.
-result :   out Y ( cout, s (9 downto 7) ) B spy ;;;
-
-ARRAY ("regt", "reg 9", ":2", "B", REGISTER, "", "Y", 0);
-
-format : Binary.
-type   : Register.
-option : none.
-
-each group is separated of the others with 2 blank spaces.
-result :   register   Y ( regt, reg (9 downto 9) ) B;;;
-.fi
-
-.SH WARNING
-.PP
-The ARRAY function from the 4.0 release have a new parameter (option).
-
-.SH SEE ALSO
-.PP
-DECLAR(3), genpat(1), pat(5)
-
-.SH DIAGNOSTICS
-.PP
-You are dealing with a variable number of parameters fonction. If you forget
-one or more parameter, you will have one of the following results :
-
-.RS
-Nothing bad happen, but your result file is erroneous.
-.br
-You are asked for more parameter.
-.br
-You crash the program and produce a Segmentation Fault.
-.RE
-
-.PP
-In all cases, check your C file for missing parameter.
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/BUS.3 b/alliance/share/man/man3/BUS.3
deleted file mode 100644
index 24c8b9c6..00000000
--- a/alliance/share/man/man3/BUS.3
+++ /dev/null
@@ -1,81 +0,0 @@
-.\"   $Id: BUS.3,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)BUS.3 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-BUS
-.XE \}
-.TH BUS 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-BUS \- Creates a bus name for netlist
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-char \(**BUS(busname, from, to);
-char \(**busname;
-long from, to;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIbusname\fP
-Common signal name for a bus
-.TP
-\fIfrom\fP
-Starting index of the set of signal, \fIfrom\fP included
-.TP
-\fIto\fP
-Ending index of the set of signal, \fIto\fP included
-.SH DESCRIPTION
-\fIBUS\fP Creates a set of names, based upon a common name, valid for the
-genlib netlist
-functions that manipulate the signal, and/or connector, concept.
-They are:
-.RS
-\fBLOINS\fP(3)
-.br
-\fBLOCON\fP(3)
-.RE
-The \fIfrom, to\fP arguments give the boundaries of the bus to be created,
-both of them beeing included in the set. The function allows increasing or
-decreasing order busses, as one could expect.
-.br
-This function has a constant equivalent, it means that if the \fIfrom, to\fP
-values are known at compilation time, one should better use,
-for readability purposes, the "[n:m]" construct.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-int b = 0;
-int e = 12;
-	/\(** Create a figure to work on  \(**/
-	DEF_LOFIG("mycell");
-	/\(** define interface  \(**/
-	LOCON(BUS("i", b, e), INPUT, BUS("sig", b, e);
-	LOCON("o[2:0]", OUTPUT, "sigout[4:6]");
-	/\(** Place an instance \(**/
-	LOINS("model","instance", BUS("sig", e/2), "sigout[6]", EOL);
-	/\(** Save all that on disk \(**/
-	SAVE_LOFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR ELM (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/COPY_UP_ALL_CON.3 b/alliance/share/man/man3/COPY_UP_ALL_CON.3
deleted file mode 100644
index 83259436..00000000
--- a/alliance/share/man/man3/COPY_UP_ALL_CON.3
+++ /dev/null
@@ -1,122 +0,0 @@
-.\"   $Id: COPY_UP_ALL_CON.3,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)COPY_UP_ALL_CON.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-COPY_UP_ALL_CON
-.XE \}
-.TH COPY_UP_ALL_CON 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-COPY_UP_ALL_CON \- copy all physical connectors of an instance face in the
-current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void COPY_UP_ALL_CON(face, insname, concatenate)
-char face, concatenate;
-char \(**insname;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIface\fP
-Face of the instance
-.TP
-\fIinsname\fP
-Name of the instance the connector belongs to
-.TP
-\fIconcatenate\fP
-Indicates wheter or not to concatenate instance connectors names with instance
-name
-.SH DESCRIPTION
-\fBCOPY_UP_ALL_CON\fP copies all instance connectors of the face \fIface\fP of
-the placed instance called \fIinsname\fP into the current layout.
-The \fIconcatenate\fP argument may take two values:
-.TP 20
-\fBYES\fP
-then the resulting name of a connector in the current figure is the
-concatenation of the \fIinsname\fP and the \fIconname\fP.
-It warranties the unicity of name at the figure level, and is to be used
-most of the time.
-.TP
-\fBNO\fP
-implies a direct copy of the connector name.
-The user must take care of the unicity of connector name by itself.
-.br
-Two behaviour are expected, depending on each of the instance connectors
-location regarding the \fIabutment box\fP of the current figure.
-.TP 20
-Connector on the \fIabutment box\fP
-The figure connector is place right over the instance connector. The single
-connector is duplicated.
-.TP
-Connector inside the \fIabutment box\fP
-The instance connector face is computed in the figure, and then, the connector
-is duplicated \fIon\fP the given face, at the right coordinates for this face.
-Then a wire is drawn between the instance connector and the figure connector in
-the connector layer.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"COPY_UP_ALL_CON impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a connector inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"*** genlib error *** COPY_UP_ALL_CON impossible : connector \fIconname\fP face
-\fIface\fP of instance \fIinsname\fP, \fIcurrent\fP figure doesn't exist"
-.ft R
-.RS
-No connector matches both the \fIconname\fP and the \fIface\fP arguments.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("cell");
-	.
-	.
-	PLACE_LEFT("gaer0_f", "insN", SYMXY);
-	.
-	.
-	DEF_AB(0L, 0L, 0L, 0L);
-	/\(** Copy all connectors \(**/
-	COPY_UP_ALL_CON(NORTH, "insN", YES);
-	/\(** Save that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHFIG (3),
-.BR SAVE_PHFIG (3),
-.BR COPY_UP_CON (3),
-.BR COPY_UP_CON_FACE (3),
-.BR PHCON (3),
-.BR THRU_CON_H (3),
-.BR THRU_CON_V (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/COPY_UP_ALL_REF.3 b/alliance/share/man/man3/COPY_UP_ALL_REF.3
deleted file mode 100644
index bc051d49..00000000
--- a/alliance/share/man/man3/COPY_UP_ALL_REF.3
+++ /dev/null
@@ -1,127 +0,0 @@
-.\"   $Id: COPY_UP_ALL_REF.3,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)COPY_UP_ALL_REF.3 2.11 01/92; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-COPY_UP_ALL_REF
-.XE \}
-.TH COPY_UP_ALL_REF 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-COPY_UP_ALL_REF \- copy a several physical reference from an instance
-in the current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void COPY_UP_ALL_REF(reftype, insname, concatenate)
-char \(**reftype, \(**insname;
-char concatenate;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIreftype\fP
-Type of the references to be duplicated
-.TP
-\fIinsname\fP
-Name of the instance in the which the references is to be searched for
-.TP
-\fIconcatenate\fP
-Indicates whether or not to concatenate the instance name to the references
-names when copying
-.SH DESCRIPTION
-\fBCOPY_UP_ALL_REF\fP duplicates all the references of type \fIreftype\fP
-of the instance called \fIinsname\fP into the current layout cell.
-The main purpose of this function is to copy a set references in the upper
-hierarchical level, so it can be used as \fIvirtual\fP connector, for
-the data-path router.
-See \fBdpr\fP(1) for details.
-.br
-The \fIreftype\fP argument can take two values:
-.TP 20
-\fB"ref_con"\fP
-for virtual connectors
-.TP
-\fB"ref_ref"\fP
-for any other references
-.LP
-See the \fIleaf cells design for generators\fP document for details on
-reference types and usage.
-.br
-The \fIconcatenate\fP argument can take two values:
-.TP 20
-A\fBYES\fP
-indicates that the name of the copied references is concatenated to the
-instance name.
-.TP
-\fBNO\fP
-implies a direct duplication of the reference name
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"COPY_UP_ALL_REF impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a reference inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphins : instance \fIinsname\fP does not exist"
-.ft R
-.RS
-The instance called \fIinsname\fP does not currently belong to the figure.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"COPY_UP_ALL_REF impossible : references of type \fIreftype\fP do not exist"
-.ft R
-.RS
-No reference of type \fIreftype\fP exist in the model of the instance
-\fIinsname\fP.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("cell");
-	PLACE("z2l_y", "r1", NOSYM, 23L, 54L);
-	/\(** Put a reference \(**/
-	COPY_UP_ALL_REF("ref_con", "r1", NO);
-	/\(** Save that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR dpr (1),
-.BR genlib (1),
-.BR DEF_PHFIG (3),
-.BR SAVE_PHFIG (3),
-.BR PHREF (3),
-.BR COPY_UP_ALL_REF (3),
-.BR PLACE_CON_REF (3),
-.BR PLACE_SEG_REF (3),
-.BR PLACE_VIA_REF (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/COPY_UP_CON.3 b/alliance/share/man/man3/COPY_UP_CON.3
deleted file mode 100644
index 43eaed74..00000000
--- a/alliance/share/man/man3/COPY_UP_CON.3
+++ /dev/null
@@ -1,119 +0,0 @@
-.\"   $Id: COPY_UP_CON.3,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)COPY_UP_CON.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-COPY_UP_CON
-.XE \}
-.TH COPY_UP_CON 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-COPY_UP_CON \- copy a physical connector from an instance in the
-current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void COPY_UP_CON(index, conname, insname, newname)
-long index;
-char \(**insname;
-char \(**conname;
-char \(**newname;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIindex\fP
-Connector index in the instance
-.TP
-\fIconname\fP
-Name of the connector in the instance model
-.TP
-\fIinsname\fP
-Name of the instance the connector belongs to
-.TP
-\fInewname\fP
-Name to be given to the connector in the current figure
-.SH DESCRIPTION
-\fBCOPY_UP_CON\fP copies a instance connector into the current layout figure,
-and gives to the new connector the name \fInewname\fP. The instance connector
-is identified by its name, \fIconname\fP, and index, \fIindex\fP.
-.br
-Two behaviour are expected, depending on the instance connector location
-regarding the \fIabutment box\fP of the current figure.
-.TP 20
-Connector on the \fIabutment box\fP
-The figure connector is place right over the instance connector. The single
-connector is duplicated.
-.TP
-Connector inside the \fIabutment box\fP
-The instance connector face is computed in the figure, and then, the connector
-is duplicated \fIon\fP the given face, at the right coordinates for this face.
-Then a wire is drawn between the instance connector and the figure connector in
-the connector layer.
-.LP
-If \fInewname\fP is \fBNULL\fP, then not connector is copied up, on the segment
-is drawn to the side of the \fIabutment\fP box.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"COPY_UP_CON impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a connector inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"*** genlib error *** COPY_UP_CON impossible : connector \fIconname\fP index
-\fIindex\fP of instance \fIinsname\fP, \fIcurrent\fP figure doesn't exist"
-.ft R
-.RS
-The given connector does not exist in the current figure.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("cell");
-	.
-	.
-	PLACE_LEFT("gaer0_f", "insN", SYMXY);
-	.
-	.
-	DEF_AB(0L, 0L, 0L, 0L);
-	/\(** Put a connector \(**/
-	COPY_UP_CON("i0", 1, "insN", "inz0");
-	/\(** Save that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHFIG (3),
-.BR SAVE_PHFIG (3),
-.BR COPY_UP_ALL_CON (3),
-.BR COPY_UP_CON_FACE (3),
-.BR PHCON (3),
-.BR THRU_CON_H (3),
-.BR THRU_CON_V (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/COPY_UP_CON_FACE.3 b/alliance/share/man/man3/COPY_UP_CON_FACE.3
deleted file mode 100644
index 3f8921cb..00000000
--- a/alliance/share/man/man3/COPY_UP_CON_FACE.3
+++ /dev/null
@@ -1,119 +0,0 @@
-.\"   $Id: COPY_UP_CON_FACE.3,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)COPY_UP_CON_FACE.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-COPY_UP_CON_FACE
-.XE \}
-.TH COPY_UP_CON_FACE 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-COPY_UP_CON_FACE \- copy a physical connector from an instance in the
-current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void COPY_UP_CON_FACE(face, conname, insname, newname)
-long index;
-char \(**insname;
-char \(**conname;
-char \(**newname;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIface\fP
-Connector face in the instance
-.TP
-\fIconname\fP
-Name of the connector in the instance model
-.TP
-\fIinsname\fP
-Name of the instance the connector belongs to
-.TP
-\fInewname\fP
-Name to be given to the connector in the current figure
-.SH DESCRIPTION
-\fBCOPY_UP_CON_FACE\fP copies a instance connector into the current layout
-figure, and gives to the new connector the name \fInewname\fP.
-The \fIface\fP and \fIconname\fP arguments are not suffiscient for non
-ambiguiously identify a single connector.
-So, if more than one connector matches these arguments, the behaviour described
-below is applied on all of them.
-.br
-Two behaviour are expected, depending on the instance connector location
-regarding the \fIabutment box\fP of the current figure.
-.TP 20
-Connector on the \fIabutment box\fP
-The figure connector is place right over the instance connector. The single
-connector is duplicated.
-.TP
-Connector inside the \fIabutment box\fP
-The instance connector face is computed in the figure, and then, the connector
-is duplicated \fIon\fP the given face, at the right coordinates for this face.
-Then a wire is drawn between the instance connector and the figure connector in
-the connector layer.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"COPY_UP_CON_FACE impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a connector inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"*** genlib error *** COPY_UP_CON_FACE impossible : connector \fIconname\fP face
-\fIface\fP of instance \fIinsname\fP, \fIcurrent\fP figure doesn't exist"
-.ft R
-.RS
-No connector matches both the \fIconname\fP and the \fIface\fP arguments.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("cell");
-	.
-	.
-	PLACE_LEFT("gaer0_f", "insN", SYMXY);
-	.
-	.
-	DEF_AB(0L, 0L, 0L, 0L);
-	/\(** Put a connector \(**/
-	COPY_UP_CON_FACE("i0", 1, "insN", "inz0");
-	/\(** Save that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHFIG (3),
-.BR SAVE_PHFIG (3),
-.BR COPY_UP_ALL_CON (3),
-.BR COPY_UP_CON (3),
-.BR PHCON (3),
-.BR THRU_CON_H (3),
-.BR THRU_CON_V (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/COPY_UP_REF.3 b/alliance/share/man/man3/COPY_UP_REF.3
deleted file mode 100644
index 92c5a701..00000000
--- a/alliance/share/man/man3/COPY_UP_REF.3
+++ /dev/null
@@ -1,110 +0,0 @@
-.\"   $Id: COPY_UP_REF.3,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)COPY_UP_REF.3 2.11 01/92; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-COPY_UP_REF
-.XE \}
-.TH COPY_UP_REF 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-COPY_UP_REF \- copy a physical reference from an instance in the current
-figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void COPY_UP_REF(refname, insname, newname)
-char \(**refname, \(**insname, \(**newname;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIrefname\fP
-Name of the reference in the instance
-.TP
-\fIinsname\fP
-Name of the instance in the which the reference is to be searched for
-.TP
-\fInewname\fP
-Name to be given to the reference in the current figure
-.SH DESCRIPTION
-\fBCOPY_UP_REF\fP adds a reference in the current layout cell.
-All the reference's attributes are copied from the first found reference
-called \fIrefname\fP in the instance \fIinsname\fP.
-The designer should avoid to give to several refences the same name if
-he plans to use this function.
-The new reference is given the name \fInewname\fP.
-The main purpose of this function is to copy a reference in the upper
-hierarchical level, so it can be used as \fIvirtual\fP connector, for
-the data-path router.
-See \fBdpr\fP(1) for details.
-layout.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"COPY_UP_REF impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a reference inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphins : instance \fIinsname\fP does not exist"
-.ft R
-.RS
-The instance called \fIinsname\fP does not currently belong to the figure.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"COPY_UP_REF impossible : reference \fIrefname\fP does not exist"
-.ft R
-.RS
-The reference \fIrefname\fP does not exist in the model of the instance
-\fIinsname\fP.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("cell");
-	PLACE("z2l_y", "r1", NOSYM, 23L, 54L);
-	/\(** Put a reference \(**/
-	COPY_UP_REF("mux0_s", "r1", "out_s");
-	/\(** Save that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR dpr (1),
-.BR genlib (1),
-.BR DEF_PHFIG (3),
-.BR SAVE_PHFIG (3),
-.BR PHREF (3),
-.BR COPY_UP_ALL_REF (3),
-.BR PLACE_CON_REF (3),
-.BR PLACE_SEG_REF (3),
-.BR PLACE_VIA_REF (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/COPY_UP_SEG.3 b/alliance/share/man/man3/COPY_UP_SEG.3
deleted file mode 100644
index c065be92..00000000
--- a/alliance/share/man/man3/COPY_UP_SEG.3
+++ /dev/null
@@ -1,107 +0,0 @@
-.\"   $Id: COPY_UP_SEG.3,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)COPY_UP_SEG.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-COPY_UP_SEG
-.XE \}
-.TH COPY_UP_SEG 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-COPY_UP_SEG \- copy a physical segment from an instance in the current
-figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void COPY_UP_SEG(oldname, insname, newname)
-char \(**oldname, \(**insname, \(**newname;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIoldname\fP
-Name of the segment in the instance
-.TP
-\fIinsname\fP
-Name of the instance in the which the segment is to be searched for
-.TP
-\fInewname\fP
-Name to be given to the segment in the current figure
-.SH DESCRIPTION
-\fBCOPY_UP_SEG\fP adds a segment in the current layout cell.
-All the segment's attributes are copied from the first found segment called
-\fIoldname\fP in the instance \fIinsname\fP.
-The new segment is given the name \fInewname\fP. The main purpose of this
-function is to rename a segment, so it can be used later, when extracting a
-layout.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"COPY_UP_SEG impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a segment inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphins : instance \fIinsname\fP does not exist"
-.ft R
-.RS
-The instance called \fIinsname\fP does not currently belong to the figure.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"COPY_UP_SEG impossible : segment \fIsegname\fP does not exist"
-.ft R
-.RS
-The segment \fIsegname\fP does not exist in the model of the instance
-\fIinsname\fP.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("cell");
-	PLACE("z2l_y", "r1", NOSYM, 23L, 54L);
-	/\(** Put a segment \(**/
-	COPY_UP_SEG("mux0_s", "r1", "out_s");
-	/\(** Save that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHFIG (3),
-.BR SAVE_PHFIG (3),
-.BR PHSEG (3),
-.BR THRU_H (3),
-.BR THRU_CON_H (3),
-.BR THRU_V (3),
-.BR THRU_CON_V (3),
-.BR WIRE1 (3),
-.BR WIRE2 (3),
-.BR WIRE3 (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DECLAR.3 b/alliance/share/man/man3/DECLAR.3
deleted file mode 100644
index 5f33357c..00000000
--- a/alliance/share/man/man3/DECLAR.3
+++ /dev/null
@@ -1,124 +0,0 @@
-.\"   $Id: DECLAR.3,v 1.2 1999/10/25 08:03:14 simcity Exp $
-.\" @(#)DECLAR.3 2.30 UPMC ; VUONG H.N. & PITON D.
-.TH DECLAR 3 "October 1, 1997" "ASIM/LIP6" "GENPAT functions"
-
-.SH NAME
-.PP
-\fBDECLAR\fP, GENPAT Package
-
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.PP
-.nf
-DECLAR("ident",":nb_space","format",mode,size,option);
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIident\fP
-External connector, internal observing points or register's name. For the
-hierarchical descriptions, the path-name of the internal observing points
-or registers must be specified by the syntax : instance1.instance11.name . 
-.TP 10
-\fInb_space\fP
-Specify the number of blank space between each group of value associated to
-the connectors, signals or registers in the output file. 0,1,2,3,4,5,6,7,8,9
-or nothing.
-.TP 10
-\fIformat\fP
-Specify the format that will be used to represent the value associated to the
-connectors, signals or registers. X for Hexadecimal, O for Octal and B for
-Binary.
-.TP 10
-\fImode\fP
-Specify the type of the connectors. IN for Input, OUT for Output, INOUT for
-Input/Output, SIGNAL for internal observing point, REGISTER for register. IN,
-OUT, INOUT, SIGNAL, REGISTER are constants (defines) provided by genpat.
-.TP 10
-\fIsize\fP
-Specify the size of the bused connectors : empty ("") for the scalar
-connectors, "nb1" for the numbered connectors, "nb1 TO nb2" or "(nb1 TO nb2)"
-(nb1 < nb2), "nb1 DOWNTO nb2" or "(nb1 DOWNTO nb2)" (nb2 < nb1) for the
-vectors. Where nb1 and nb2 are integer.
-.TP 10
-\fIoption\fP
-Specify options of the connector. "S" for a spied connector, empty ("")
-for a normal connector.
-
-.SH DESCRIPTION
-.PP
-Describes a set of connectors, signals or registers of the same format, size
-and mode.
-
-.SH EXAMPLE
-.PP
-.nf
-DECLAR("a", ":2", "X", OUT, "3 DOWNTO 0", "S");
-
-describes : a 3, a 2, a 1, a 0
-format    : Hexadecimal.
-mode      : Output.
-option    : Spied connector.
-
-the group is separated of the others with 2 blank spaces.
-result : 
-	out a(3 downto 0) X spy ;;;
-
-DECLAR ("toto", ":", "O", INOUT, "7 TO 11", "");
-
-describes : toto 7, toto 8, toto 9, toto 10, toto 11.
-format    : Octal.
-mode      : Input/Output.
-option    : none.
-
-the group is separated of the following with 0 blank space.
-result :
-	inout toto(7 to 11) O ;
-
-DECLAR ("ck", ":2", "B", IN, "", "");
-
-describes : ck.
-format    : Binary.
-mode      : Input.
-option    : none.
-
-the port is separated of the following with 2 blank spaces.
-result :
-	in ck ;;;
-
-DECLAR ("accu.f", ":", "B", SIGNAL, "", "S");
-
-describes : accu.f .
-format    : Binary.
-mode      : Signal.
-option    : Spied connector.
-
-the signal is separated of the following with 0 blank space.
-result : 
-	signal accu.f spy ;
-
-DECLAR ("accu.reg", ":1", "B", REGISTER, "(3)", "");
-
-describes : accu.reg .
-format    : Binary.
-mode      : Register.
-option    : none.
-
-the signal is separated of the following with 1 blank space.
-result :
-	register accu.reg(3) ;;;;
-
-.fi
-
-.SH WARNING
-.PP
-The DECLAR function from the 4.0 release have a new parameter (option).
-
-.SH SEE ALSO
-.PP
-ARRAY(3), genpat(1), pat(5)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DEF_AB.3 b/alliance/share/man/man3/DEF_AB.3
deleted file mode 100644
index 1b97004a..00000000
--- a/alliance/share/man/man3/DEF_AB.3
+++ /dev/null
@@ -1,84 +0,0 @@
-.\"   $Id: DEF_AB.3,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)DEF_AB.3 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-DEF_AB
-.XE \}
-.TH DEF_AB 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-DEF_AB \- define a new \fIabutment box\fP to the current layout cell
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void DEF_AB(dx1, dy1, dx2, dy2);
-long dx1, dy1, dx2, dy2;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIdx1, dy1\fP
-Values to be added to the lower left corner of the previous \fIabutment box\fP
-.TP
-\fIdx2, dy2\fP
-Values to be added to the upper right corner of the previous \fIabutment box\fP
-.SH DESCRIPTION
-\fBDEF_AB\fP give a new \fIabutment box\fP to the current physical cell.
-The coordinates of
-the \fIabutment box\fP are the coordinates of the envelop of the \fIabutment boxes\fP of
-each instance plus the delta values given as argument. The \fI(dx1, dy1)\fP
-values are added to the (x1, y1) coordinates of the bottom left corner of the
-\fI"standard abutment box"\fP (the envelop), and the \fI(dx2, dy2)\fP
-are added to the top right ones.
-You have to call this function before saving, otherwise the figure will not
-have an \fIabutment box\fP. Since it's regarding the \fIabutment box\fP
-of its model that an instance is placed, any futher use of this figure
-will be incorrect if \fBDEF_AB\fP isn't called, or properly defined.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"DEF_AB impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to give it a size.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("cell");
-	/\(** Place an instance \(**/
-	PLACE("model","i1", NOSYM,0L,0L);
-	PLACE("model","i2", NOSYM,120L,40L);
-	DEF_PHINS("i1");
-	PLACE_TOP("model2", "i3", NOSYM);
-	/\(** define the new abutment box as the standard envelop \(**/
-	DEF_AB(0, 0, 0, 0);
-	/\(** Save all that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR SAVE_PHFIG (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DEF_GENPAT.3 b/alliance/share/man/man3/DEF_GENPAT.3
deleted file mode 100644
index 52fd9ca4..00000000
--- a/alliance/share/man/man3/DEF_GENPAT.3
+++ /dev/null
@@ -1,39 +0,0 @@
-.\"   $Id: DEF_GENPAT.3,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)DEF_GENPAT.3 2.30  UPMC ; VUONG H.N.
-.TH DEF_GENPAT 3 "October 1, 1997" "ASIM/LIP6" "GENPAT functions"
-
-.SH NAME
-.PP
-\fBDEF_GENPAT\fP, GENPAT Package
-
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.PP
-.nf
-DEF_GENPAT ("ident");
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIident\fP
-Output file's name without extension.
-
-.SH DESCRIPTION
-.PP
-Gives the output file's name.
-
-.SH EXAMPLE
-.PP
-.nf
-DEF_GENPAT ("my_file");
-Declares the output file's name as my_file.<VH_PATSFX>, usually my_file.pat.
-.fi
-
-.SH SEE ALSO
-.PP
-SAV_GENPAT(3), genpat(1), pat(5)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DEF_LOFIG.3 b/alliance/share/man/man3/DEF_LOFIG.3
deleted file mode 100644
index fb5a9574..00000000
--- a/alliance/share/man/man3/DEF_LOFIG.3
+++ /dev/null
@@ -1,62 +0,0 @@
-.\"   $Id: DEF_LOFIG.3,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)DEF_LOFIG.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-DEF_LOFIG
-.XE \}
-.TH DEF_LOFIG 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-DEF_LOFIG \- open a netlist model as current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void DEF_LOFIG(cellname)
-char \(**cellname;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIcellname\fP
-Name of the cell which all futher calls to genlib logical functions will work on 
-.SH DESCRIPTION
-\fBDEF_LOFIG\fP defines the current working structural figure by it's name, 
-the \fIcellname\fP argument. It can be use anywhere in the \fBgenlib\fP 
-program, but must appear at least once at the top of it, since it also 
-initalize the user's preferences through environment variables.
-.br
-If the figure called cellname doesn't exists in memory, it is created. 
-If it already exists in memory, it makes it the current working figure. 
-\fBDEF_LOFIG\fP doesn't look on disk for the figure \fIcellname\fP, 
-so be careful not to overwrite an existing file while saving later on.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_LOFIG("cell");
-	/\(** Place an instance \(**/
-	LOINS("model","instance", "sig1", "sig2", "sig3", "vdd", "vss", EOL);
-	/\(** Save all that on disk \(**/
-	SAVE_LOFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR SAVE_LOFIG (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DEF_PHFIG.3 b/alliance/share/man/man3/DEF_PHFIG.3
deleted file mode 100644
index eccd15fc..00000000
--- a/alliance/share/man/man3/DEF_PHFIG.3
+++ /dev/null
@@ -1,62 +0,0 @@
-.\"   $Id: DEF_PHFIG.3,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)DEF_PHFIG.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-DEF_PHFIG
-.XE \}
-.TH DEF_PHFIG 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-DEF_PHFIG \- open a layout model as current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void DEF_PHFIG(cellname)
-char \(**cellname;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIcellname\fP
-Name of the cell which all futher calls to genlib physical functions will work on
-.SH DESCRIPTION
-\fBDEF_PHFIG\fP defines the current physical working figure by it's name, 
-the \fIcellname\fP argument. It can be use anywhere in the \fBgenlib\fP 
-program, but must appear at least once at the top of it, since it also 
-initalize the user's preferences through environment variables.
-.br
-If the figure called cellname doesn't exists in memory, it is created. 
-If it already exists in memory, it makes it the current working figure. 
-\fBDEF_PHFIG\fP doesn't look on disk for the figure \fIcellname\fP, 
-so be careful not to overwrite an existing file while saving later on.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("mycell");
-	/\(** Place an instance \(**/
-	PLACE("mymodel","firstinstance", NOSYM,0L,0L);
-	/\(** Save all that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHSC (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DEF_PHINS.3 b/alliance/share/man/man3/DEF_PHINS.3
deleted file mode 100644
index 04e719c3..00000000
--- a/alliance/share/man/man3/DEF_PHINS.3
+++ /dev/null
@@ -1,94 +0,0 @@
-.\"   $Id: DEF_PHINS.3,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)DEF_PHINS.3 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-DEF_PHINS
-.XE \}
-.TH DEF_PHINS 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-DEF_PHINS \- define a new reference instance
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void DEF_PHINS(instancename);
-char \(**instancename;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIinstancename\fP
-Defines the instance called \fIinstancename\fP as the new "reference instance" 
-.SH DESCRIPTION
-\fBDEF_PHINS\fP define the new "reference instance", used as starting point
-in the relative placement functions of genlib. It's regarding the \fBabutment
-box\fP of the instance \fIinstancename\fP that the next instance is going to be
-placed, if using the appropriate functions. Notice that the more recently
-placed instance becomes automaticaly the "reference instance", if 
-\fBDEF_PHINS\fP isn't called.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"DEF_PHINS impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to refer to an instance inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"instance instancename doesn't exist in current figure"
-.ft R
-.RS
-The instance \fIinstancename\fP hasn't currently been placed in the figure,
-so it's impossible do to any placement from it. 
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("cell");
-	/\(** Place an instance \(**/
-	PLACE("model","i1", NOSYM,0L,0L);
-	PLACE("model","i2", NOSYM,120L,40L);
-	DEF_PHINS("i1");
-	PLACE_TOP("model2", "i3", NOSYM);
-	DEF_AB(0, 0, 0, 0);
-	/\(** Save all that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR PLACE (3),
-.BR PLACE_TOP (3),
-.BR PLACE_RIGHT (3),
-.BR PLACE_LEFT (3),
-.BR PLACE_BOTTOM (3),
-.BR SC_PLACE (3),
-.BR SC_TOP (3),
-.BR SC_RIGHT (3),
-.BR SC_LEFT (3),
-.BR SC_BOTTOM (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DEF_PHSC.3 b/alliance/share/man/man3/DEF_PHSC.3
deleted file mode 100644
index 146e9e8e..00000000
--- a/alliance/share/man/man3/DEF_PHSC.3
+++ /dev/null
@@ -1,78 +0,0 @@
-.\"   $Id: DEF_PHSC.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.\" @(#)DEF_PHSC.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-DEF_PHSC
-.XE \}
-.TH DEF_PHSC 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-DEF_PHSC \- load a netlist and open a layout model as current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void DEF_PHSC(cellname)
-char \(**cellname;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIcellname\fP
-Name of the netlist figure to be looked for in memory or on disk, for
-futher physical placement.
-.SH DESCRIPTION
-\fBDEF_PHSC\fP defines the current working figure by it's name, 
-the \fIcellname\fP argument, for layout and netlist operations.
-It can be use anywhere in the \fBgenlib\fP 
-program, but must appear at least once at the top of it, since it also 
-initalize the user's preferences through environment variables.
-.br
-\fBDEF_PHSC\fP looks for the netlist figure \fIcellname\fP in memory, and if
-not found, on disk. If it fails, an error occurs and the process terminates.
-.br
-The main issue of this function is to allow the netlist and physical
-descriptions of a circuit in two separate files,
-for standard cell approach. So there is
-no need to recreate the netlist view each time the placement changes.
-.br
-If the physical figure called \fIcellname\fP doesn't exists in memory,
-it is created. 
-If it already exists in memory, it makes it the current working figure. 
-\fBDEF_PHSC\fP doesn't look on disk for the figure \fIcellname\fP, 
-so be careful not to overwrite an existing file while saving later on.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHSC("mycell");
-	/\(** Place an instance \(**/
-	SC_PLACE("instance", NOSYM,0L,0L);
-	/\(** Save all that on disk \(**/
-	SAVE_PHSC();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR SAVE_PHSC (3),
-.BR SC_PLACE (3),
-.BR SC_TOP (3),
-.BR SC_BOTTOM (3),
-.BR SC_LEFT (3),
-.BR SC_RIGHT (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_ADD2F.3 b/alliance/share/man/man3/DP_ADD2F.3
deleted file mode 100644
index 4c189d9f..00000000
--- a/alliance/share/man/man3/DP_ADD2F.3
+++ /dev/null
@@ -1,65 +0,0 @@
-.\"   $Id: DP_ADD2F.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_ADD2F 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_ADD2F\fP - Adder-Substractor
-.LP
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-void  DP_ADD2F( 
-    char *InstName,  /*           Instance name           */
-
-    char *BusI0   ,  /* IN     First Operand         DATA */
-    char *BusI1   ,  /* IN    Second Operand         DATA */
-    char *SigCout ,  /* OUT    Carry output N        CTRL */
-    char *SigOvr  ,  /* OUT    Carry output N-1      CTRL */
-    char *BusO    ,  /* OUT   Direct Result output   DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.LP
-.ta 4m +4n +2n +14n +2n
-	\fBDP_ADD2F\fP creates a fast adder and then instanciates it
-with the name \fIInstName\fP. The adder bit-size is the full wide
-of the current data-path, set by the previous call to the function
-\fBDP_DEFLOFIG\fP.
-.br
-	The environment variable \fBMBK_CATA_LIB\fP have to contain an additionnal
-library path when using this macro-function, see \fBfpgen(1)\fP for more
-details.
-.br
-.SH CHARACTERISTICS
-.ta +15n +2n +2n
-Operator wide	:	Depends on the data-path wide.
-.SH EXAMPLE
-.ft CR
-.nf
-DP_ADD2F("add2f_instance0", "input_i0[31:0]", 
-                            "input_i1[31:0]", 
-                              "pin_cout"    ,
-                              "pin_ovr"     ,
-                            "output_o[31:0]", EOL);
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-rsa(1)
-,
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_ADSB2.3 b/alliance/share/man/man3/DP_ADSB2.3
deleted file mode 100644
index d9b7d548..00000000
--- a/alliance/share/man/man3/DP_ADSB2.3
+++ /dev/null
@@ -1,66 +0,0 @@
-.\"   $Id: DP_ADSB2.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_ADSB2 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_ADSB2\fP - adder-substractor
-.LP
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-void  DP_ADSB2( 
-    char *InstName,  /*          Instance name           */
-
-    char *BusI0,     /* IN       First Operand      DATA */
-    char *BusI1,     /* IN       Second Operand     DATA */
-    char *SigOp,     /* IN            Codop         CTRL */ 
-    char *SigCout,   /* OUT         Carry out(n)    CTRL */
-    char *SigCovr ,  /* OUT   Previous carry(n-1)   CTRL */
-    char *BusO, EOL);/* OUT       Result output     DATA */
-.fi
-.ft R
-.SH ARGUMENTS
-.ta  7mC 12m
-.in +12m
-.ti -12m
-\fISigOp\fP	\fBCTRL\fR	This one bit signal indicates the operation
-(addition or substraction).
-.ta +2n +10n +2n
-.br
-	- low	 :   addition.
-.br
-	- high	 :   substraction.
-.br
-.ta  7mC 12m
-
-.SH DESCRIPTION
-.LP
-.ta 4m +4n +15nR +2n +2n
-	\fBDP_ADSB2\fP creates an adder-substracter that has a wide of \fIWidth\fP
-bits and then instanciates it with the name \fIInstName\fP. The maximal
-authorized value for \fIWidth\fP is the full width of the current 
-data-path, set by the previous call to the function \fBDP_DEFLOFIG\fP.
-In the layout the leaf cells are placed on the slices numbered from
-\fISlice\fP to \fISlice\fB+\fIWidth\fB-1\fR (the bottom slice is 0).
-.br
-.SH EXAMPLE
-.ft CR
-.nf
-
-    DP_ADSB2( "adsb20", 32, 
-                         0, 
-                        "input0[3:0]", 
-                        "input1[3:0]", 
-                            "op"     ,
-                            "c31"     ,
-                            "c30"     ,
-                        "output[3:0]", EOL);
-	
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-fpgen(3), adsb2g(3), fplib(3), mbk(1)
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_ADSB2F.3 b/alliance/share/man/man3/DP_ADSB2F.3
deleted file mode 100644
index fe5d5f1b..00000000
--- a/alliance/share/man/man3/DP_ADSB2F.3
+++ /dev/null
@@ -1,75 +0,0 @@
-.\"   $Id: DP_ADSB2F.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_ADSB2F 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_ADSB2F\fP - Adder-Substractor
-.LP
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-void  DP_ADSB2F( 
-    char *InstName,  /*           Instance name           */
-
-    char *BusI0   ,  /* IN     First Operand         DATA */
-    char *BusI1   ,  /* IN    Second Operand         DATA */
-    char *SigCout ,  /* OUT    Carry output N        CTRL */
-    char *SigOvr  ,  /* OUT    Carry output N-1      CTRL */
-    char *BusO    ,  /* OUT   Direct Result output   DATA */
-    char *SigOp   ,  /* IN           Operation       CTRL */ 
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.LP
-.ta 4m +4n +2n +14n +2n
-	\fBDP_ADSB2F\fP creates a fast adder substractor and then instanciates it
-with the name \fIInstName\fP. The adder substractor bit-size is the full wide
-of the current data-path, set by the previous call to the function
-\fBDP_DEFLOFIG\fP.
-.br
-	The one bit signal \fISigOp\fP select which arithmetical operation to
-perform :
-.br
-		-	\fISigOp\fP equal "\fB0\fP"	:	Addition.
-.br
-		-	\fISigOp\fP equal "\fB1\fP"	:	Substraction.
-.br
-.br
-	The environment variable \fBMBK_CATA_LIB\fP have to contain an additionnal
-library path when using this macro-function, see \fBfpgen(1)\fP for more
-details.
-.br
-.SH CHARACTERISTICS
-.ta +15n +2n +2n
-Operator wide	:	Depends on the data-path wide.
-.SH EXAMPLE
-.ft CR
-.nf
-DP_ADSB2F("adsb2f_instance0", "input_i0[31:0]", 
-                              "input_i1[31:0]", 
-                                "pin_cout"    ,
-                                "pin_ovr"     ,
-                              "output_o[31:0]",
-                                "pin_op"      , EOL);
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-rsa(1)
-,
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_AND2.3 b/alliance/share/man/man3/DP_AND2.3
deleted file mode 100644
index 4f14937e..00000000
--- a/alliance/share/man/man3/DP_AND2.3
+++ /dev/null
@@ -1,63 +0,0 @@
-.\"   $Id: DP_AND2.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_AND2 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_AND2\fP - Logical and 2.
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_AND2( 	
-    char *InstName,  /*              Instance name              */
-    long  Width   ,  /*             Number of bits              */
-    long  Slice   ,  /*        Index of the bottom slice        */
-
-    long  Drive   ,  /*           Fanout : among 1 or 2         */
-    char *BusI0   ,  /*  IN          First Operand         DATA */
-    char *BusI1   ,  /*  IN         Second Operand         DATA */
-    char *BusO    ,  /* OUT         Direct Result output   DATA */
-    char *BusNO   ,  /* OUT   Complemented Result output   DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m +4n +10nR +2n +2n
-	\fBDP_AND2\fP creates a logical and 2 of \fIWidth\fP
-bits and then instanciates it with the name \fIInstName\fP. The maximal
-authorized value for \fIWidth\fP is the full width of the current 
-data-path, set by the previous call to the function \fBDP_DEFLOFIG\fP.
-In the layout the leaf cells are placed on the slices numbered from
-\fISlice\fP to \fISlice\fB+\fIWidth\fB-1\fR (the bottom slice of the
-whole data-path is numbered zero).
-.br
-.SH CHARACTERISTICS
-.ta +15n +2n +2n
-Operator wide	:	\fB24 lambdas\fP.
-.SH EXAMPLE
-.ft CR
-.nf
-DP_AND2("and2_instance0", 32, 
-                           0, 1, "input_i0[31:0]", 
-                                 "input_i1[31:0]", 
-                                 "output_o[31:0]",
-                                "output_no[31:0]", EOL);
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_AND3.3 b/alliance/share/man/man3/DP_AND3.3
deleted file mode 100644
index 08e4bbb7..00000000
--- a/alliance/share/man/man3/DP_AND3.3
+++ /dev/null
@@ -1,65 +0,0 @@
-.\"   $Id: DP_AND3.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_AND3 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_AND3\fP - logical and 3
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_AND3( 	
-    char *InstName,  /*              Instance name              */
-    long  Width   ,  /*             Number of bits              */
-    long  Slice   ,  /*        Index of the bottom slice        */
-
-    long  Drive   ,  /*           Fanout : among 1 or 2         */
-    char *BusI0   ,  /*  IN          First Operand         DATA */
-    char *BusI1   ,  /*  IN         Second Operand         DATA */
-    char *BusI2   ,  /*  IN          Third Operand         DATA */
-    char *BusO    ,  /* OUT         Direct Result output   DATA */
-    char *BusNO   ,  /* OUT   Complemented Result output   DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m +4n +10nR +2n +2n
-	\fBDP_AND3\fP creates a logical and 3 of \fIWidth\fP
-bits and then instanciates it with the name \fIInstName\fP. The maximal
-authorized value for \fIWidth\fP is the full width of the current 
-data-path, set by the previous call to the function \fBDP_DEFLOFIG\fP.
-In the layout the leaf cells are placed on the slices numbered from
-\fISlice\fP to \fISlice\fB+\fIWidth\fB-1\fR (the bottom slice of the
-whole data-path is numbered zero).
-.br
-.SH CHARACTERISTICS
-.ta +15n +2n +2n
-Operator wide	:	\fB30 lambdas\fP.
-.SH EXAMPLE
-.ft CR
-.nf
-DP_AND3("and3_instance0", 32, 
-                           0, 1, "input_i0[31:0]", 
-                                 "input_i1[31:0]", 
-                                 "input_i2[31:0]", 
-                                 "output_o[31:0]", 
-                                "output_no[31:0]", EOL);
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_BUFF.3 b/alliance/share/man/man3/DP_BUFF.3
deleted file mode 100644
index b69958c0..00000000
--- a/alliance/share/man/man3/DP_BUFF.3
+++ /dev/null
@@ -1,63 +0,0 @@
-.\"   $Id: DP_BUFF.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_BUFF 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_BUFF\fP - inverter
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_BUFF( 	
-    char *InstName,  /*         Instance name         */
-    long  Width   ,  /*        Number of slices       */
-    long  Slice   ,  /*   Index of the bottom slice   */
-
-    long  Drive   ,  /*  Fanout : among 1, 2 or 3     */
-    char *BusI0   ,  /* IN     Input Operand     DATA */
-    char *BusO    ,  /* OUT    Result output     DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m +4n +10nR +2n +2n
-	\fBDP_BUFF\fP creates a buffer of \fIWidth\fP
-bits and then instanciates it with the name \fIInstName\fP. The maximal
-authorized value for \fIWidth\fP is the full width of the current 
-data-path, set by the previous call to the function \fBDP_DEFLOFIG\fP.
-In the layout the leaf cells are placed on the slices numbered from
-\fISlice\fP to \fISlice\fB+\fIWidth\fB-1\fR (the bottom slice is 0).
-.br
-.SH CHARACTERISTICS
-.nf
-.ta 15n +2n +9n +2n +4n +2n
-Operator wide	:	drive = 1	-->	\fB18 lambdas\fP.
-		drive = 2	-->	\fB24 lambdas\fP.
-		drive = 3	-->	\fB36 lambdas\fP.
-.fi
-.SH EXAMPLE
-.ft CR
-.nf
-
-    DP_BUFF( "inv_instance0", 32, 
-                               0, 1, "input_i0[3:0]", 
-                                     "output_o[3:0]", EOL);
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_BUSE.3 b/alliance/share/man/man3/DP_BUSE.3
deleted file mode 100644
index 6c8e73a5..00000000
--- a/alliance/share/man/man3/DP_BUSE.3
+++ /dev/null
@@ -1,67 +0,0 @@
-.\"   $Id: DP_BUSE.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_BUSE 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_BUSE\fP - Tristate with direct output.
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_BUSE( 	
-    char *InstName,  /*         Instance name          */
-    long  Width   ,  /*        Number of bits          */
-    long  Slice   ,  /*   Index of the bottom slice    */
-
-    char *SigEn   ,  /*  IN          Enable       CTRL */
-    char *BusI0   ,  /*  IN    Input Operand      DATA */
-    char *BusO    ,  /* OUT   Direct Bus Output   DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m +4n +2n +14n +2n
-	\fBDP_BUSE\fP create a tristate where the one bit signal \fISigEn\fP select
-the output state :
-.br
-		-	\fISigEn\fP equal "\fB0\fP"	:	\fIBusO\fP <= \fIhigh impedance\fP.
-.br
-		-	\fISigEn\fP equal "\fB1\fP"	:	\fIBusO\fP <= \fIBusI0\fP.
-.br
-	\fBDP_BUSE\fP build an operator of \fIWidth\fP
-bits and then instanciates it with the name \fIInstName\fP. The maximal
-authorized value for \fIWidth\fP is the full width of the current 
-data-path, set by the previous call to the function \fBDP_DEFLOFIG\fP.
-In the layout the leaf cells are placed on the slices numbered from
-\fISlice\fP to \fISlice\fB+\fIWidth\fB-1\fR (the bottom slice of the
-whole data-path is numbered zero).
-.br
-.SH CHARACTERISTICS
-.ta +15n +2n +2n
-Operator wide	:	\fB48 lambdas\fP.
-.SH EXAMPLE
-.ft CR
-.nf
-DP_BUSE("buse_instance0", 32, 
-                           0, "pin_state"      ,
-                               "input_i0[31:0]", 
-                               "output_o[31:0]", EOL);
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_CONST.3 b/alliance/share/man/man3/DP_CONST.3
deleted file mode 100644
index 4a61eb92..00000000
--- a/alliance/share/man/man3/DP_CONST.3
+++ /dev/null
@@ -1,58 +0,0 @@
-.\"   $Id: DP_CONST.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_CONST 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_CONST\fP - Constant Generator
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_CONST( 	
-    char *InstName,  /*            Instance name            */
-    long  Width   ,  /*           Number of bits            */
-    long  Slice   ,  /*     Index of the bottom slice.      */
-
-    char *ValConst,  /*              Constant value         */
-    char *BusO    ,  /* OUT   Direct constant output   DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m +4n +10nR +2n +2n
-	\fBDP_CONST\fP creates a constant generator that have a wide of \fIWidth\fP
-bits and then instanciates it with the name \fIInstName\fP. The maximal
-authorized value for \fIWidth\fP is the full wide of the current 
-data-path, set by the previous call to the function \fBDP_DEFLOFIG\fP.
-In the layout the leaf cells are placed on the slices numbered from
-\fISlice\fP to \fISlice\fB+\fIWidth\fB-1\fR (the bottom slice of the whole
-data-path is numbered zero).
-.br
-.SH CHARACTERISTICS
-.ta +15n +2n +2n
-Operator wide	:	\fB12 lambdas\fP.
-.SH EXAMPLE
-.ft CR
-.nf
-DP_CONST("const_instance0", 32 , 
-                             0 ,   
-                       "0xFA50", "output_o[31:0]", EOL);
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_DEFLOFIG.3 b/alliance/share/man/man3/DP_DEFLOFIG.3
deleted file mode 100644
index 62147961..00000000
--- a/alliance/share/man/man3/DP_DEFLOFIG.3
+++ /dev/null
@@ -1,88 +0,0 @@
-.\"   $Id: DP_DEFLOFIG.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_DEFLOFIG 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_DEFLOFIG\fP - Open a new Data-Path figure/model.
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_DEFLOFIG( 
-    char *aFigName ,  /* Figure/model name                 */
-    long  aMaxWidth,  /* Maximal operator bus wide         */
-    long  aMSB0    ); /* Select the type of bus indexation */
-.fi
-.ft R
-.SH ARGUMENTS
-.in +8m
-.ta +8m
-.ti -8m
-\fIaFiglName\fP	Give the data-path model name.
-
-.ti -8m
-\fIaMaxWidth\fP	Set the maximal width of the operators bus. This is also
-the width used when a \fImacro-function\fP is called width the argument
-\fBDEFAULT_WIDTH\fP as the \fIWidth\fP parameter.
-
-.ti -8m
-\fIaMSB0\fP	Tells how the buses will be indexed. Two values are allowed :
-.br
-.ta +20nR +1n +2n
--	\fBLSB_INDEX_ZERO\fP	:	The least significant bit have the index of
-\fIzero\fP.
-.br
-			(so bus are noted \fB[\fIMaxWidth\fB-1:0]\fR)
-.br
--	\fBMSB_INDEX_ZERO\fP	:	The most significant bit have the index of
-\fIzero\fP.
-.br
-			(so bus are noted \fB[0:\fIMaxWidth\fB-1]\fR)
-.br
-Notice that, in the layout, the \fBLSB\fP is always on the \fIslice\fP
-numdered \fIzero\fP.
-
-.SH DESCRIPTION
-.ta  4n
-	\fBDP_DEFLOFIG\fP define the current working data-path. The call to this
-function must be done before to use any other \fBfpgen\fP macro-function.
-It doesn't look on the disk for the figure \fIModelName\fP, so be careful
-to not overwrite an existing file while saving later on.
-.ta 4m +4n
-.SH EXAMPLE
-.ft CR
-.nf
-#include  <genlib.h>
-#include  <fpgen.h>
- 
- 
-main()
-{
-    /* Create a new data-path figure names "my_sweet_data_path". */
-    DP_DEFLOFIG("my_sweet_data_path", 32, LSB_INDEX_ZERO);
-
-    /* Data-path netlist description, using macro-functions. */
-
-    /* Save the model on disk. */
-    DP_SAVLOFIG();
-}
-.fi
-.ft R
-.bp
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_IMPORT.3 b/alliance/share/man/man3/DP_IMPORT.3
deleted file mode 100644
index 80582f98..00000000
--- a/alliance/share/man/man3/DP_IMPORT.3
+++ /dev/null
@@ -1,73 +0,0 @@
-.\"   $Id: DP_IMPORT.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_IMPORT 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_IMPORT\fP - Add a new data-path component inside the current data-path.
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_IMPORT( 
-    char *ModelName,  /* Figure/model name.                */
-    char  *InstName,  /* Instance name.                    */
-    char  *SigList ,  /* List of signals names.            */
-                 EOL);
-.fi
-.ft R
-.SH ARGUMENTS
-.in +8m
-.ta +8m
-.ti -8m
-\fIModelName\fP	The data-path object model name.
-
-.ti -8m
-\fIInstName\fP	Name to be given to the new instance.
-
-.ti -8m
-\fISigList\fP	List of signals to be linked to the connectors of the
-instance. Notice that power supply signals "\fI*vdd*\fP" and "\fI*vss*\fP"
-must be ommited in the above list. They are detected in the model connector
-list and automatically inserted at the right place in the signal list.
-.in -8m
-.br
-.SH DESCRIPTION
-.ta  4n
-	The \fBDP_IMPORT\fP function allow the designer to include in the
-current data-path various customized components. At this time, only three
-type are recognized. The two first are \fIheterogeneous operators\fP and
-\fIsub data-paths\fP, they consist in netlists that must respect the rules
-given for the place and route tool \fBdpr\fP. In the preceeding cases \fBDP_IMPORT\fP
-checks for the netlist validity. For more informations about the data-path 
-netlist constraints, see \fBdpr\fP. The last case is \fIcustom blocs\fP,
-such blocs are detected when a layout associated with the model is found on the
-disk. For these the \fBDP_IMPORT\fP function run blindly,
-assuming that the layout is correct regarding the \fBbit-slice\fP requirements.
-.SH EXAMPLE
-.ft CR
-.nf
-#include <genlib.h>
-#include  <fpgen.h>
- 
-DP_IMPORT("custom_model", "custom_instance0", "input_i0[31:0]",
-                                              "input_i1[31:0]",
-                                              "output_o[31:0]", EOL);
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_INV.3 b/alliance/share/man/man3/DP_INV.3
deleted file mode 100644
index 4f09b8b7..00000000
--- a/alliance/share/man/man3/DP_INV.3
+++ /dev/null
@@ -1,64 +0,0 @@
-.\"   $Id: DP_INV.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_INV 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_INV\fP - inverter
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_INV( 	
-    char *InstName,  /*         Instance name         */
-    long  Width   ,  /*        Number of slices       */
-    long  Slice   ,  /*   Index of the bottom slice   */
-
-    long  Drive   ,  /*  Fanout : among 1, 2, 3 or 4  */
-    char *BusI0   ,  /* IN     Input Operand     DATA */
-    char *BusO    ,  /* OUT    Result output     DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m +4n +10nR +2n +2n
-	\fBDP_INV\fP creates a inverter of \fIWidth\fP
-bits and then instanciates it with the name \fIInstName\fP. The maximal
-authorized value for \fIWidth\fP is the full width of the current 
-data-path, set by the previous call to the function \fBDP_DEFLOFIG\fP.
-In the layout the leaf cells are placed on the slices numbered from
-\fISlice\fP to \fISlice\fB+\fIWidth\fB-1\fR (the bottom slice is 0).
-.br
-.SH CHARACTERISTICS
-.nf
-.ta 15n +2n +9n +2n +4n +2n
-Operator wide	:	drive = 1	-->	\fB12 lambdas\fP.
-		drive = 2	-->	\fB12 lambdas\fP.
-		drive = 3	-->	\fB18 lambdas\fP.
-		drive = 4	-->	\fB48 lambdas\fP.
-.fi
-.SH EXAMPLE
-.ft CR
-.nf
-
-    DP_INV( "inv_instance0", 32, 
-                              0, 1, "input_i0[3:0]", 
-                                    "output_o[3:0]", EOL);
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_LOCON.3 b/alliance/share/man/man3/DP_LOCON.3
deleted file mode 100644
index a5b398e3..00000000
--- a/alliance/share/man/man3/DP_LOCON.3
+++ /dev/null
@@ -1,106 +0,0 @@
-.\"   $Id: DP_LOCON.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_LOCON 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_LOCON\fP -  Logical connector
-.SH SYNOPSYS
-.ft CR
-.nf
-#include <genlib.h>
-#include <fpgen.h>
-
-void DP_LOCON(
-     char *aCon,  /*       Connector name       */
-     char  aDir,  /* Direction of the connector */
-     char *aSig); /*    Internal signal name    */
-.ft R
-.fi
-.SH ARGUMENTS
-.in +14n
-.ta +14n
-.ti -14n
-\fIaCon\fP	Name of the connector to be created in the current figure.
-.br
-
-.ti -14n
-\fIaDir\fP	Indicates the connector behavior regarding signal propagation.
-The available values are listed below, they are the same as in the
-\fBgenlib(1)\fP description language :
-.br
-.ta +12nR +1n +2n
--	\fBIN\fP	:	Input.
-.br
--	\fBOUT\fP	:	Output.
-.br
--	\fBINOUT\fP	:	Input/output.
-.br
--	\fBUNKNOW\fP	:	If one doesn't know what it is.
-.br
--	\fBTRISTATE\fP	:	High impedance output.
-.br
--	\fBTRANSV\fP	:	Transceiver, that means \fBTRISTATE\fP input plus
-output.
-.br
-
-.ta +14n
-.ti -14n
-\fIaSig\fP	Name of the internal signal with which the connector is
-linked. For better understanding this name could by the same as given for
-\fIaCon\fP.
-.br
-
-.ta +14n
-.in -14n
-.SH DESCRIPTION
-.ta +4n
-	\fBDP_LOCON\fP add a logical connector \fIaCon\fP to the interface of
-the actual working figure. This connector is logicaly linked to the signal
-\fIaSig\fP.
-.br
-	All the \fBDP_LOCON\fP function calls must immediatly follow the
-\fBDP_DEFLOFIG\fP function call.
-.bp
-.SH EXAMPLE
-.ft CR
-.nf
-#include  <genlib.h>
-#include  <fpgen.h>
- 
- 
-main()
-{
-    /* Create a new data-path figure names "my_sweet_data_path". */
-    DP_DEFLOFIG("my_sweet_data_path", 32, LSB_INDEX_ZERO);
-
-    /* Data-path connectors declaration. */
-    DP_LOCON("pin_ctrl1"      , IN   , "pin_ctrl1"      );
-    DP_LOCON("bus_data1[31:0]", IN   , "bus_data1[31:0]");
-    DP_LOCON("pin_data2[31]"  ,   OUT, "pin_data2[31]"  );
-
-    DP_LOCON(BUS("bus_data3",31,0), IN   ,BUS("bus_data2",31,0));
-	DP_LOCON(ELM("pin_data4",31  )    OUT,ELM("pin_data4",31  ));
-
-    /* Data-path netlist description, using macro-functions. */
-
-    /* Save the model on disk. */
-    DP_SAVLOFIG();
-}
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_MULT.3 b/alliance/share/man/man3/DP_MULT.3
deleted file mode 100644
index c8266018..00000000
--- a/alliance/share/man/man3/DP_MULT.3
+++ /dev/null
@@ -1,66 +0,0 @@
-.\"   $Id: DP_MULT.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_MULT 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_MULT\fP - Unpipelined array multiplier.
-.LP
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-void  DP_MULT( 
-    char *InstName,  /*            Instance name             */
-    long  MWide   ,  /*        Wide of the B operand         */
-
-    char *BusA    ,  /* IN    First Operand (  N wide)  DATA */
-    char *BusB    ,  /* IN   Second Operand (M   wide)  DATA */
-    char *SigP    ,  /* OUT         Product (M+N wide)  DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.LP
-.ta 4m +4n +2n +14n +2n
-	\fBDP_MULT\fP creates an unpipelined array multiplier and then
-instanciates it with the name \fIInstName\fP. The multiplier bit-size is
-the full wide of the current data-path, set by the previous call to
-the function \fBDP_DEFLOFIG\fP. As a consequence the wide of the \fBA\fP
-input bus is always the full data-path wide, and the wide of the \fBB\fP
-input bus is given by the \fPMWide\fP structural parameter. The wide of
-the result \fBP\fP is \fBN+M\fP.
-.br
-	The environment variable \fBMBK_CATA_LIB\fP have to contain an additionnal
-library path when using this macro-function, see \fBfpgen(1)\fP for more
-details.
-.br
-.SH CHARACTERISTICS
-.ta +15n +2n +2n
-Operator wide	:	Depends on the data-path wide.
-.SH EXAMPLE
-.ft CR
-.nf
-DP_MULT("mult_instance0", 16
-                          "input_a[31:0]", 
-                          "input_b[15:0]", 
-                         "output_p[47:0]", EOL);
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-amg(1)
-,
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_MULTP.3 b/alliance/share/man/man3/DP_MULTP.3
deleted file mode 100644
index c709c1a9..00000000
--- a/alliance/share/man/man3/DP_MULTP.3
+++ /dev/null
@@ -1,83 +0,0 @@
-.\"   $Id: DP_MULTP.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_MULTP 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_MULTP\fP - Unpipelined array multiplier.
-.LP
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-void  DP_MULTP( 
-    char *InstName,  /*            Instance name             */
-    long  MWide   ,  /*        Wide of the B operand         */
-    long  T0      ,  /*         register after  DNC          */
-    long  T1      ,  /*         register before CLA          */
-    long  N       ,  /*       registers in the MUX+CSA       */
-
-    char *BusA    ,  /* IN    First Operand (  N wide)  DATA */
-    char *BusB    ,  /* IN   Second Operand (M   wide)  DATA */
-    char *SigCK   ,  /* IN            Clock             CTRL */
-    char *SigSD   ,  /* IN        Fonc Mode Enable      CTRL */
-    char *SigST   ,  /* IN        Test Mode Enable      CTRL */
-    char *SigScin ,  /* IN       Scan Input             CTRL */
-    char *SigScout,  /* OUT      Scan Output            CTRL */
-    char *SigP    ,  /* OUT         Product (M+N wide)  DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.LP
-.ta 4m +4n +2n +14n +2n
-	\fBDP_MULTP\fP creates an unpipelined array multiplier and then
-instanciates it with the name \fIInstName\fP. The MULTPiplier bit-size is
-the full wide of the current data-path, set by the previous call to
-the function \fBDP_DEFLOFIG\fP. As a consequence the wide of the \fBA\fP
-input bus is always the full data-path wide, and the wide of the \fBB\fP
-input bus is given by the \fPMWide\fP structural parameter. The wide of
-the result \fBP\fP is \fBN+M\fP.
-.br
-	For more informations about the various pipeline stages sets by
-\fBT0\fP, \fBT1\fP and \fBN\fP structural parameters, please refer to
-\fBamg(1)\fP.
-.br
-	The environment variable \fBMBK_CATA_LIB\fP have to contain an additionnal
-library path when using this macro-function, see \fBfpgen(1)\fP for more
-details.
-.br
-.SH CHARACTERISTICS
-.ta +15n +2n +2n
-Operator wide	:	Depends on the data-path wide.
-.SH EXAMPLE
-.ft CR
-.nf
-DP_MULTP("mult_instance0", 16
-                           "input_a[31:0]", 
-                           "input_b[15:0]", 
-                                "ck",
-                                "sd",
-                                "st",
-                             "scin" ,
-                             "scout",
-                           "output_p[47:0]", EOL);
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-amg(1)
-,
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_MUX2CS.3 b/alliance/share/man/man3/DP_MUX2CS.3
deleted file mode 100644
index 7a8684c2..00000000
--- a/alliance/share/man/man3/DP_MUX2CS.3
+++ /dev/null
@@ -1,70 +0,0 @@
-.\"   $Id: DP_MUX2CS.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_MUX2CS 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_MUX2CS\fP - 2 input multiplexer.
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_MUX2CS( 	
-    char *InstName,  /*           Instance name           */
-    long  Width   ,  /*          Number of bits           */
-    long  Slice   ,  /*     Index of the bottom slice     */
-
-    char *SigSel  ,  /*  IN    Input Select          CTRL */
-    char *BusI1   ,  /*  IN   Second Input           DATA */
-    char *BusI0   ,  /*  IN    First Input           DATA */
-    char *BusO    ,  /* OUT   Direct Result Output   DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m +4n +2n +14n +2n
-	\fBDP_MUX2CS\fP creates a 2 input multiplexer. It is build using a
-\fIpseudo-CMOS\fP architecture. The signal \fISigSel\fP select which input
-is connected to the  output :
-.br
-		-	\fISigSel\fP equal "\fB0\fP"	:	\fIBusO\fP <= \fIBusI0\fP.
-.br
-		-	\fISigSel\fP equal "\fB1\fP"	:	\fIBusO\fP <= \fIBusI1\fP.
-.br
-	\fBDP_MUX2CS\fP build an operator of \fIWidth\fP
-bits and then instanciates it with the name \fIInstName\fP. The maximal
-authorized value for \fIWidth\fP is the full width of the current 
-data-path, set by the previous call to the function \fBDP_DEFLOFIG\fP.
-In the layout the leaf cells are placed on the slices numbered from
-\fISlice\fP to \fISlice\fB+\fIWidth\fB-1\fR (the bottom slice of the
-whole data-path is numbered zero).
-.br
-.SH CHARACTERISTICS
-.ta +15n +2n +2n
-Operator wide	:	\fB33 lambdas\fP.
-.SH EXAMPLE
-.ft CR
-.nf
-DP_MUX2CS("mux2cs_instance0", 32, 
-                               0,  "pin_sel"      ,
-                                  "input_i1[31:0]", 
-                                  "input_i0[31:0]", 
-                                  "output_o[31:0]", EOL);
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_MUX3CD.3 b/alliance/share/man/man3/DP_MUX3CD.3
deleted file mode 100644
index 18b4369f..00000000
--- a/alliance/share/man/man3/DP_MUX3CD.3
+++ /dev/null
@@ -1,69 +0,0 @@
-.\"   $Id: DP_MUX3CD.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_MUX3CD 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_MUX3CD\fP - 3 input multiplexer.
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_MUX3CD( 	
-    char *InstName,  /*           Instance name           */
-    long  Width   ,  /*          Number of bits           */
-    long  Slice   ,  /*     Index of the bottom slice     */
-
-    char *BusSel  ,  /*  IN    Input Select          CTRL */
-    char *BusI0   ,  /*  IN    First Input           DATA */
-    char *BusI1   ,  /*  IN   Second Input           DATA */
-    char *BusI1   ,  /*  IN    Third Input           DATA */
-    char *BusO    ,  /* OUT   Direct Result Output   DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m +4n +2n +15n +2n
-	\fBDP_MUX3CD\fP creates a 3 input multiplexer. It is build using a
-\fIdual-CMOS\fP architecture. The signal \fIBusSel\fP select which input is
-connected to the  output :
-.nf
-		-	\fIBusSel\fP equal "\fB00\fP"	:	\fIBusO\fP <= \fIBusI0\fP.
-		-	\fIBusSel\fP equal "\fB01\fP"	:	\fIBusO\fP <= \fIBusI1\fP.
-		-	\fIBusSel\fP equal "\fB10\fP"	:	\fIBusO\fP <= \fIBusI2\fP.
-.fi
-	\fBDP_MUX3CD\fP build an operator of \fIWidth\fP
-bits and then instanciates it with the name \fIInstName\fP. The maximal
-authorized value for \fIWidth\fP is the full width of the current 
-data-path, set by the previous call to the function \fBDP_DEFLOFIG\fP.
-In the layout the leaf cells are placed on the slices numbered from
-\fISlice\fP to \fISlice\fB+\fIWidth\fB-1\fR (the bottom slice of the
-whole data-path is numbered zero).
-.br
-.SH EXAMPLE
-.ft CR
-.nf
-DP_MUX3CD("mux3cd_instance0", 32, 
-                               0,  "bus_sel[1:0]" ,
-                                  "input_i0[31:0]", 
-                                  "input_i1[31:0]", 
-                                  "input_i1[31:0]", 
-                                  "output_o[31:0]", EOL);
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_MUX3CS.3 b/alliance/share/man/man3/DP_MUX3CS.3
deleted file mode 100644
index b705db13..00000000
--- a/alliance/share/man/man3/DP_MUX3CS.3
+++ /dev/null
@@ -1,72 +0,0 @@
-.\"   $Id: DP_MUX3CS.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_MUX3CS 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_MUX3CS\fP - 3 input multiplexer.
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_MUX3CS( 	
-    char *InstName,  /*           Instance name           */
-    long  Width   ,  /*          Number of bits           */
-    long  Slice   ,  /*     Index of the bottom slice     */
-
-    char *BusSel  ,  /*  IN    Input Select          CTRL */
-    char *BusI2   ,  /*  IN    Third Input           DATA */
-    char *BusI1   ,  /*  IN   Second Input           DATA */
-    char *BusI0   ,  /*  IN    First Input           DATA */
-    char *BusO    ,  /* OUT   Direct Result Output   DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m +4n +2n +15n +2n
-	\fBDP_MUX3CS\fP creates a 3 input multiplexer. It is build using a
-\fIdual-CMOS\fP architecture. The signal \fIBusSel\fP select which input is
-connected to the  output :
-.nf
-		-	\fIBusSel\fP equal "\fB00\fP"	:	\fIBusO\fP <= \fIBusI0\fP.
-		-	\fIBusSel\fP equal "\fB01\fP"	:	\fIBusO\fP <= \fIBusI1\fP.
-		-	\fIBusSel\fP equal "\fB10\fP"	:	\fIBusO\fP <= \fIBusI2\fP.
-.fi
-	\fBDP_MUX3CS\fP build an operator of \fIWidth\fP
-bits and then instanciates it with the name \fIInstName\fP. The maximal
-authorized value for \fIWidth\fP is the full width of the current 
-data-path, set by the previous call to the function \fBDP_DEFLOFIG\fP.
-In the layout the leaf cells are placed on the slices numbered from
-\fISlice\fP to \fISlice\fB+\fIWidth\fB-1\fR (the bottom slice of the
-whole data-path is numbered zero).
-.br
-.SH CHARACTERISTICS
-.ta +15n +2n +2n
-Operator wide	:	\fB49 lambdas\fP.
-.SH EXAMPLE
-.ft CR
-.nf
-DP_MUX3CS("mux3cs_instance0", 32, 
-                               0,  "bus_sel[1:0]" ,
-                                  "input_i2[31:0]", 
-                                  "input_i1[31:0]", 
-                                  "input_i0[31:0]", 
-                                  "output_o[31:0]", EOL);
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_MUX4CS.3 b/alliance/share/man/man3/DP_MUX4CS.3
deleted file mode 100644
index 2b5eeeaf..00000000
--- a/alliance/share/man/man3/DP_MUX4CS.3
+++ /dev/null
@@ -1,76 +0,0 @@
-.\"   $Id: DP_MUX4CS.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_MUX4CS 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_MUX4CS\fP - 4 input multiplexer.
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_MUX4CS( 	
-    char *InstName,  /*           Instance name           */
-    long  Width   ,  /*          Number of bits           */
-    long  Slice   ,  /*     Index of the bottom slice     */
-
-    char *BusSel  ,  /*  IN    Input Select          CTRL */
-    char *BusI3   ,  /*  IN    Third Input           DATA */
-    char *BusI2   ,  /*  IN    Third Input           DATA */
-    char *BusI1   ,  /*  IN   Second Input           DATA */
-    char *BusI0   ,  /*  IN    First Input           DATA */
-    char *BusO    ,  /* OUT   Direct Result Output   DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m +4n +2n +15n +2n
-	\fBDP_MUX4CS\fP creates a 4 input multiplexer. It is build using a
-\fIdual-CMOS\fP architecture. The signal \fIBusSel\fP select which input is
-connected to the  output :
-.nf
-		-	\fIBusSel\fP equal "\fB00\fP"	:	\fIBusO\fP <= \fIBusI0\fP.
-		-	\fIBusSel\fP equal "\fB01\fP"	:	\fIBusO\fP <= \fIBusI1\fP.
-		-	\fIBusSel\fP equal "\fB10\fP"	:	\fIBusO\fP <= \fIBusI2\fP.
-		-	\fIBusSel\fP equal "\fB11\fP"	:	\fIBusO\fP <= \fIBusI3\fP.
-.fi
-	\fBDP_MUX3CS\fP build an operator of \fIWidth\fP
-bits and then instanciates it with the name \fIInstName\fP. The maximal
-authorized value for \fIWidth\fP is the full width of the current 
-data-path, set by the previous call to the function \fBDP_DEFLOFIG\fP.
-In the layout the leaf cells are placed on the slices numbered from
-\fISlice\fP to \fISlice\fB+\fIWidth\fB-1\fR (the bottom slice of the
-whole data-path is numbered zero).
-.br
-.SH CHARACTERISTICS
-.ta +15n +2n +2n
-Operator wide	:	\fB60 lambdas\fP.
-.SH EXAMPLE
-.ft CR
-.nf
-DP_MUX4CS("mux4cs_instance0", 32, 
-                               0,  "bus_sel[1:0]" ,
-                                  "input_i3[31:0]", 
-                                  "input_i2[31:0]", 
-                                  "input_i1[31:0]", 
-                                  "input_i0[31:0]", 
-                                  "output_o[31:0]", EOL);
-.fi
-.ft R
-.bp
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_MUX5CS.3 b/alliance/share/man/man3/DP_MUX5CS.3
deleted file mode 100644
index 91bf21fd..00000000
--- a/alliance/share/man/man3/DP_MUX5CS.3
+++ /dev/null
@@ -1,79 +0,0 @@
-.\"   $Id: DP_MUX5CS.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_MUX5CS 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_MUX5CS\fP - 5 input multiplexer.
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_MUX5CS( 	
-    char *InstName,  /*           Instance name           */
-    long  Width   ,  /*          Number of bits           */
-    long  Slice   ,  /*     Index of the bottom slice     */
-
-    char *BusSel  ,  /*  IN    Input Select          CTRL */
-    char *BusI4   ,  /*  IN    Third Input           DATA */
-    char *BusI3   ,  /*  IN    Third Input           DATA */
-    char *BusI2   ,  /*  IN    Third Input           DATA */
-    char *BusI1   ,  /*  IN   Second Input           DATA */
-    char *BusI0   ,  /*  IN    First Input           DATA */
-    char *BusO    ,  /* OUT   Direct Result Output   DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m +4n +2n +15n +2n
-	\fBDP_MUX5CS\fP creates a 5 input multiplexer. It is build using a
-\fIdual-CMOS\fP architecture. The signal \fIBusSel\fP select which input is
-connected to the  output :
-.nf
-		-	\fIBusSel\fP equal "\fB000\fP"	:	\fIBusO\fP <= \fIBusI0\fP.
-		-	\fIBusSel\fP equal "\fB001\fP"	:	\fIBusO\fP <= \fIBusI1\fP.
-		-	\fIBusSel\fP equal "\fB010\fP"	:	\fIBusO\fP <= \fIBusI2\fP.
-		-	\fIBusSel\fP equal "\fB011\fP"	:	\fIBusO\fP <= \fIBusI3\fP.
-		-	\fIBusSel\fP equal "\fB100\fP"	:	\fIBusO\fP <= \fIBusI4\fP.
-.fi
-	\fBDP_MUX3CS\fP build an operator of \fIWidth\fP
-bits and then instanciates it with the name \fIInstName\fP. The maximal
-authorized value for \fIWidth\fP is the full width of the current 
-data-path, set by the previous call to the function \fBDP_DEFLOFIG\fP.
-In the layout the leaf cells are placed on the slices numbered from
-\fISlice\fP to \fISlice\fB+\fIWidth\fB-1\fR (the bottom slice of the
-whole data-path is numbered zero).
-.br
-.SH CHARACTERISTICS
-.ta +15n +2n +2n
-Operator wide	:	\fB86 lambdas\fP.
-.SH EXAMPLE
-.ft CR
-.nf
-DP_MUX5CS("mux5cs_instance0", 32, 
-                               0,  "bus_sel[2:0]" ,
-                                  "input_i4[31:0]", 
-                                  "input_i3[31:0]", 
-                                  "input_i2[31:0]", 
-                                  "input_i1[31:0]", 
-                                  "input_i0[31:0]", 
-                                  "output_o[31:0]", EOL);
-.fi
-.ft R
-.bp
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_NAND2.3 b/alliance/share/man/man3/DP_NAND2.3
deleted file mode 100644
index 69613272..00000000
--- a/alliance/share/man/man3/DP_NAND2.3
+++ /dev/null
@@ -1,61 +0,0 @@
-.\"   $Id: DP_NAND2.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_NAND2 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_NAND2\fP - logical not and 2
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_NAND2( 	
-    char *InstName,  /*           Instance name           */
-    long  Width   ,  /*          Number of bits           */
-    long  Slice   ,  /*     Index of the bottom slice     */
-
-    long  Drive   ,  /*     Fanout : among 1 or 2         */
-    char *BusI0   ,  /*  IN    First Operand         DATA */
-    char *BusI1   ,  /*  IN   Second Operand         DATA */
-    char *BusO    ,  /* OUT   Direct Result output   DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m +4n +10nR +2n +2n
-	\fBDP_NAND2\fP creates a logical not and 2 of \fIWidth\fP
-bits and then instanciates it with the name \fIInstName\fP. The maximal
-authorized value for \fIWidth\fP is the full width of the current 
-data-path, set by the previous call to the function \fBDP_DEFLOFIG\fP.
-In the layout the leaf cells are placed on the slices numbered from
-\fISlice\fP to \fISlice\fB+\fIWidth\fB-1\fR (the bottom slice of the
-whole data-path is numbered zero).
-.br
-.SH CHARACTERISTICS
-.ta +15n +2n +2n
-Operator wide	:	\fB18 lambdas\fP.
-.SH EXAMPLE
-.ft CR
-.nf
-DP_NAND2("nand2_instance0", 32, 
-                             0, 1, "input_i0[31:0]", 
-                                   "input_i1[31:0]", 
-                                   "output_o[31:0]", EOL);
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_NAND2MASK.3 b/alliance/share/man/man3/DP_NAND2MASK.3
deleted file mode 100644
index 8fc579d2..00000000
--- a/alliance/share/man/man3/DP_NAND2MASK.3
+++ /dev/null
@@ -1,68 +0,0 @@
-.\"   $Id: DP_NAND2MASK.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_NAND2MASK 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_NAND2MASK\fP - Logical not and 2 controllable mask.
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_NAND2MASK( 	
-    char *InstName,  /*           Instance name           */
-    long  Width   ,  /*          Number of bits           */
-    long  Slice   ,  /*     Index of the bottom slice     */
-
-    char    *Mask ,  /*         Mask Value                */
-    char *SigMask ,  /*  IN     Mask Activation      CTRL */
-    char *BusI0   ,  /*  IN    First Operand         DATA */
-    char *BusO    ,  /* OUT   Direct Result output   DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m +4n +10nR +2n +2n
-	\fBDP_NAND2MASK\fP creates a programmable mask which can inhibits
-the data input with a constant provided by the user. The mask is active
-when the control signal command \fISigMask\fP is "\fB1\fP", otherwise
-the input data is propagated to the output through an inverter-like
-scheme.
-.br
-	This function have a width of \fIWidth\fP
-bits and is instanciated with the name \fIInstName\fP. The maximal
-authorized value for \fIWidth\fP is the full width of the current 
-data-path, set by the previous call to the function \fBDP_DEFLOFIG\fP.
-In the layout the leaf cells are placed on the slices numbered from
-\fISlice\fP to \fISlice\fB+\fIWidth\fB-1\fR (the bottom slice of the
-whole data-path is numbered zero).
-.br
-.SH CHARACTERISTICS
-.ta +15n +2n +2n
-Operator wide	:	\fB21 lambdas\fP.
-.SH EXAMPLE
-.ft CR
-.nf
-DP_NAND2MASK("nand2mask_instance0", 32, 
-                                     0,
-                              "0x000F",  "pin_msk"      ,
-                                        "input_i0[31:0]", 
-                                        "output_o[31:0]", EOL);
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_NAND3.3 b/alliance/share/man/man3/DP_NAND3.3
deleted file mode 100644
index 54de5c34..00000000
--- a/alliance/share/man/man3/DP_NAND3.3
+++ /dev/null
@@ -1,63 +0,0 @@
-.\"   $Id: DP_NAND3.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_NAND3 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_NAND3\fP - logical not and 3
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_NAND3( 	
-    char *InstName,  /*           Instance name           */
-    long  Width   ,  /*          Number of bits           */
-    long  Slice   ,  /*     Index of the bottom slice     */
-
-    long  Drive   ,  /*     Fanout : among 1 or 2         */
-    char *BusI0   ,  /*  IN    First Operand         DATA */
-    char *BusI1   ,  /*  IN   Second Operand         DATA */
-    char *BusI2   ,  /*  IN    Third Operand         DATA */
-    char *BusO    ,  /* OUT   Direct Result output   DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m +4n +10nR +2n +2n
-	\fBDP_NAND3\fP creates a logical not and 3 of \fIWidth\fP
-bits and then instanciates it with the name \fIInstName\fP. The maximal
-authorized value for \fIWidth\fP is the full width of the current 
-data-path, set by the previous call to the function \fBDP_DEFLOFIG\fP.
-In the layout the leaf cells are placed on the slices numbered from
-\fISlice\fP to \fISlice\fB+\fIWidth\fB-1\fR (the bottom slice of the
-whole data-path is numbered zero).
-.br
-.SH CHARACTERISTICS
-.ta +15n +2n +2n
-Operator wide	:	\fB24 lambdas\fP.
-.SH EXAMPLE
-.ft CR
-.nf
-DP_NAND3("nand3_instance0", 32, 
-                             0, 1, "input_i0[31:0]", 
-                                   "input_i1[31:0]", 
-                                   "input_i2[31:0]", 
-                                   "output_o[31:0]", EOL);
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_NBUSE.3 b/alliance/share/man/man3/DP_NBUSE.3
deleted file mode 100644
index efa95469..00000000
--- a/alliance/share/man/man3/DP_NBUSE.3
+++ /dev/null
@@ -1,67 +0,0 @@
-.\"   $Id: DP_NBUSE.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_NBUSE 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_NBUSE\fP - Tristate with complemented output.
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_NBUSE( 	
-    char *InstName,  /*         Instance name          */
-    long  Width   ,  /*        Number of bits          */
-    long  Slice   ,  /*   Index of the bottom slice    */
-
-    char *SigEn   ,  /*  IN          Enable       CTRL */
-    char *BusI0   ,  /*  IN    Input Operand      DATA */
-    char *BusO    ,  /* OUT   Direct Bus Output   DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m +4n +2n +14n +2n
-	\fBDP_NBUSE\fP create a tristate where the one bit signal \fISigEn\fP select
-the output state :
-.br
-		-	\fISigEn\fP equal "\fB0\fP"	:	\fIBusO\fP <= \fIhigh impedance\fP.
-.br
-		-	\fISigEn\fP equal "\fB1\fP"	:	\fIBusO\fP <= not \fIBusI0\fP.
-.br
-	\fBDP_NBUSE\fP build an operator of \fIWidth\fP
-bits and then instanciates it with the name \fIInstName\fP. The maximal
-authorized value for \fIWidth\fP is the full width of the current 
-data-path, set by the previous call to the function \fBDP_DEFLOFIG\fP.
-In the layout the leaf cells are placed on the slices numbered from
-\fISlice\fP to \fISlice\fB+\fIWidth\fB-1\fR (the bottom slice of the
-whole data-path is numbered zero).
-.br
-.SH CHARACTERISTICS
-.ta +15n +2n +2n
-Operator wide	:	\fB24 lambdas\fP.
-.SH EXAMPLE
-.ft CR
-.nf
-DP_NBUSE("nbuse_instance0", 32, 
-                             0, "pin_state"      ,
-                                 "input_i0[31:0]", 
-                                 "output_o[31:0]", EOL);
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_NMUX2CS.3 b/alliance/share/man/man3/DP_NMUX2CS.3
deleted file mode 100644
index c188273a..00000000
--- a/alliance/share/man/man3/DP_NMUX2CS.3
+++ /dev/null
@@ -1,70 +0,0 @@
-.\"   $Id: DP_NMUX2CS.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_NMUX2CS 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_NMUX2CS\fP - 2 input multiplexer, with complemented output.
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_NMUX2CS( 	
-    char *InstName,  /*           Instance name           */
-    long  Width   ,  /*          Number of bits           */
-    long  Slice   ,  /*     Index of the bottom slice     */
-
-    char *SigSel  ,  /*  IN    Input Select          CTRL */
-    char *BusI1   ,  /*  IN   Second Input           DATA */
-    char *BusI0   ,  /*  IN    First Input           DATA */
-    char *BusO    ,  /* OUT   Direct Result output   DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m +4n +2n +14n +2n
-	\fBDP_NMUX2CS\fP creates a 2 input multiplexer. It is build using a
-\fIpseudo-CMOS\fP architecture. The signal \fISigSel\fP select which input
-is connected to the  output :
-.br
-		-	\fISigSel\fP equal "\fB0\fP"	:	\fIBusO\fP <= not \fIBusI0\fP.
-.br
-		-	\fISigSel\fP equal "\fB1\fP"	:	\fIBusO\fP <= not \fIBusI1\fP.
-.br
-	\fBDP_MUX2CS\fP build an operator of \fIWidth\fP
-bits and then instanciates it with the name \fIInstName\fP. The maximal
-authorized value for \fIWidth\fP is the full width of the current 
-data-path, set by the previous call to the function \fBDP_DEFLOFIG\fP.
-In the layout the leaf cells are placed on the slices numbered from
-\fISlice\fP to \fISlice\fB+\fIWidth\fB-1\fR (the bottom slice of the
-whole data-path is numbered zero).
-.br
-.SH CHARACTERISTICS
-.ta +15n +2n +2n
-Operator wide	:	\fB24 lambdas\fP.
-.SH EXAMPLE
-.ft CR
-.nf
-DP_NMUX2CS("nmux2cs_instance0", 32, 
-                                 0,  "pin_sel"      ,
-                                    "input_i1[31:0]", 
-                                    "input_i0[31:0]", 
-                                    "output_o[31:0]", EOL);
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_NOR2.3 b/alliance/share/man/man3/DP_NOR2.3
deleted file mode 100644
index 2344d2ba..00000000
--- a/alliance/share/man/man3/DP_NOR2.3
+++ /dev/null
@@ -1,64 +0,0 @@
-.\"   $Id: DP_NOR2.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_NOR2 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_NOR2\fP - logical not or 2
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_NOR2( 	
-    char *InstName,  /*           Instance name           */
-    long  Width   ,  /*          Number of bits           */
-    long  Slice   ,  /*     Index of the bottom slice     */
-
-    long  Drive   ,  /*     Fanout : among 1 or 2         */
-    char *BusI0   ,  /*  IN    First Operand         DATA */
-    char *BusI1   ,  /*  IN   Second Operand         DATA */
-    char *BusO    ,  /* OUT   Direct Result output   DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m +4n +10nR +2n +2n
-	\fBDP_NOR2\fP creates a logical not or 2 of \fIWidth\fP
-bits and then instanciates it with the name \fIInstName\fP. The maximal
-authorized value for \fIWidth\fP is the full width of the current 
-data-path, set by the previous call to the function \fBDP_DEFLOFIG\fP.
-In the layout the leaf cells are placed on the slices numbered from
-\fISlice\fP to \fISlice\fB+\fIWidth\fB-1\fR (the bottom slice of the
-whole data-path is numbered zero).
-.br
-.SH CHARACTERISTICS
-.nf
-.ta 15n +2n +9n +2n +4n +2n
-Operator wide	:	drive = 1	-->	\fB18 lambdas\fP.
-		drive = 2	-->	\fB36 lambdas\fP.
-.fi
-.SH EXAMPLE
-.ft CR
-.nf
-DP_NOR2("nor2_instance0", 32, 
-                           0, 1, "input_i0[31:0]", 
-                                 "input_i1[31:0]", 
-                                 "output_o[31:0]", EOL);
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_NOR2MASK.3 b/alliance/share/man/man3/DP_NOR2MASK.3
deleted file mode 100644
index a1c0c7b6..00000000
--- a/alliance/share/man/man3/DP_NOR2MASK.3
+++ /dev/null
@@ -1,68 +0,0 @@
-.\"   $Id: DP_NOR2MASK.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_NOR2MASK 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_NOR2MASK\fP - Logical not or 2 controllable mask.
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_NOR2MASK( 	
-    char *InstName,  /*           Instance name           */
-    long  Width   ,  /*          Number of bits           */
-    long  Slice   ,  /*     Index of the bottom slice     */
-
-    char    *Mask ,  /*         Mask Value                */
-    char *SigMask ,  /*  IN     Mask Activation      CTRL */
-    char *BusI0   ,  /*  IN    First Operand         DATA */
-    char *BusO    ,  /* OUT   Direct Result output   DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m +4n +10nR +2n +2n
-	\fBDP_NOR2MASK\fP creates a programmable mask which can inhibits
-the data input with a constant provided by the user. The mask is active
-when the control signal command \fISigMask\fP is "\fB1\fP", otherwise
-the input data is propagated to the output through an inverter-like
-scheme.
-.br
-	This function have a width of \fIWidth\fP
-bits and is instanciated with the name \fIInstName\fP. The maximal
-authorized value for \fIWidth\fP is the full width of the current 
-data-path, set by the previous call to the function \fBDP_DEFLOFIG\fP.
-In the layout the leaf cells are placed on the slices numbered from
-\fISlice\fP to \fISlice\fB+\fIWidth\fB-1\fR (the bottom slice of the
-whole data-path is numbered zero).
-.br
-.SH CHARACTERISTICS
-.ta +15n +2n +2n
-Operator wide	:	\fB21 lambdas\fP.
-.SH EXAMPLE
-.ft CR
-.nf
-DP_NOR2MASK("nor2mask_instance0", 32, 
-                                   0,
-                            "0xFFF0", "pin_msk"      ,
-                                     "input_i0[31:0]", 
-                                     "output_o[31:0]", EOL);
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_NOR3.3 b/alliance/share/man/man3/DP_NOR3.3
deleted file mode 100644
index 13250223..00000000
--- a/alliance/share/man/man3/DP_NOR3.3
+++ /dev/null
@@ -1,66 +0,0 @@
-.\"   $Id: DP_NOR3.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_NOR3 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_NOR3\fP - logical not or 3
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_NOR3( 	
-    char *InstName,  /*           Instance name           */
-    long  Width   ,  /*          Number of bits           */
-    long  Slice   ,  /*     Index of the bottom slice     */
-
-    long  Drive   ,  /*     Fanout : among 1 or 2         */
-    char *BusI0   ,  /*  IN    First Operand         DATA */
-    char *BusI1   ,  /*  IN   Second Operand         DATA */
-    char *BusI2   ,  /*  IN    Third Operand         DATA */
-    char *BusO    ,  /* OUT   Direct Result output   DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m +4n +10nR +2n +2n
-	\fBDP_NOR3\fP creates a logical not or 3 of \fIWidth\fP
-bits and then instanciates it with the name \fIInstName\fP. The maximal
-authorized value for \fIWidth\fP is the full width of the current 
-data-path, set by the previous call to the function \fBDP_DEFLOFIG\fP.
-In the layout the leaf cells are placed on the slices numbered from
-\fISlice\fP to \fISlice\fB+\fIWidth\fB-1\fR (the bottom slice of the
-whole data-path is numbered zero).
-.br
-.SH CHARACTERISTICS
-.nf
-.ta 15n +2n +9n +2n +4n +2n
-Operator wide	:	drive = 1	-->	\fB24 lambdas\fP.
-		drive = 2	-->	\fB42 lambdas\fP.
-.fi
-.SH EXAMPLE
-.ft CR
-.nf
-DP_NOR3("nor3_instance0", 32, 
-                           0, 1, "input_i0[31:0]", 
-                                 "input_i1[31:0]", 
-                                 "input_i2[31:0]", 
-                                 "output_o[31:0]", EOL);
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_NUL.3 b/alliance/share/man/man3/DP_NUL.3
deleted file mode 100644
index 361804f9..00000000
--- a/alliance/share/man/man3/DP_NUL.3
+++ /dev/null
@@ -1,62 +0,0 @@
-.\"   $Id: DP_NUL.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_NUL 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_NUL\fP - Zero Detect 
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_NUL( 	
-    char *InstName,  /*         Instance name         */
-    long  Width   ,  /*        Number of bits         */
-    long  Slice   ,  /*   Index of the bottom slice   */
-
-    char *BusI0   ,  /*  IN     Operand input    DATA */
-    char *SigNul  ,  /* OUT   Zero flag output   DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m
-	\fBDP_NUL\fP creates a zero detect operator of \fIWidth\fP
-bits and then instanciates it with the name \fIInstName\fP. The maximal
-authorized value for \fIWidth\fP is the full width of the current 
-data-path, set by the previous call to the function \fBDP_DEFLOFIG\fP.
-In the layout the leaf cells are placed on the slices numbered from
-\fISlice\fP to \fISlice\fB+\fIWidth\fB-1\fR (the bottom slice of the
-whole data-path is numbered zero).
-.br
-.SH CHARACTERISTICS
-.nf
-.ta 15n +2n +16n +2n +4n +2n
-Operator wide	:	drive 4 to 8	-->	\fB24 lambdas\fP.
-		drive 9 to 16	-->	\fB29 lambdas\fP.
-		drive 17 to 32	-->	\fB32 lambdas\fP.
-.fi
-.SH EXAMPLE
-.ft CR
-.nf
-DP_NUL("nul_instance0", 32, 
-                         0, "input_i0[3:0]", 
-                           "output_null"   , EOL);
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_OR2.3 b/alliance/share/man/man3/DP_OR2.3
deleted file mode 100644
index 425629fc..00000000
--- a/alliance/share/man/man3/DP_OR2.3
+++ /dev/null
@@ -1,63 +0,0 @@
-.\"   $Id: DP_OR2.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_OR2 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_OR2\fP - logical or 2
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_OR2( 	
-    char *InstName,  /*              Instance name              */
-    long  Width   ,  /*             Number of bits              */
-    long  Slice   ,  /*        Index of the bottom slice        */
-
-    long  Drive   ,  /*           Fanout : among 1 or 2         */
-    char *BusI0   ,  /*  IN          First Operand         DATA */
-    char *BusI1   ,  /*  IN         Second Operand         DATA */
-    char *BusO    ,  /* OUT         Direct Result output   DATA */
-    char *BusNO   ,  /* OUT   Complemented Result output   DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m +4n +10nR +2n +2n
-	\fBDP_OR2\fP creates a logical or 2 of \fIWidth\fP
-bits and then instanciates it with the name \fIInstName\fP. The maximal
-authorized value for \fIWidth\fP is the full width of the current 
-data-path, set by the previous call to the function \fBDP_DEFLOFIG\fP.
-In the layout the leaf cells are placed on the slices numbered from
-\fISlice\fP to \fISlice\fB+\fIWidth\fB-1\fR (the bottom slice of the
-whole data-path is numbered zero).
-.br
-.SH CHARACTERISTICS
-.ta +15n +2n +2n
-Operator wide	:	\fB24 lambdas\fP.
-.SH EXAMPLE
-.ft CR
-.nf
-DP_OR2("or2_instance0", 32, 
-                         0, 1, "input_i0[31:0]", 
-                               "input_i1[31:0]", 
-                              "output_no[31:0]",
-                               "output_o[31:0]", EOL);
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_OR3.3 b/alliance/share/man/man3/DP_OR3.3
deleted file mode 100644
index 6d5b1afd..00000000
--- a/alliance/share/man/man3/DP_OR3.3
+++ /dev/null
@@ -1,65 +0,0 @@
-.\"   $Id: DP_OR3.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_OR3 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_OR3\fP - logical or 3
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_OR3( 	
-    char *InstName,  /*              Instance name              */
-    long  Width   ,  /*             Number of bits              */
-    long  Slice   ,  /*        Index of the bottom slice        */
-
-    long  Drive   ,  /*           Fanout : among 1 or 2         */
-    char *BusI0   ,  /*  IN          First Operand         DATA */
-    char *BusI1   ,  /*  IN         Second Operand         DATA */
-    char *BusI2   ,  /*  IN          Third Operand         DATA */
-    char *BusNO   ,  /* OUT   Complemented Result output   DATA */
-    char *BusO    ,  /* OUT         Direct Result output   DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m +4n +10nR +2n +2n
-	\fBDP_OR3\fP creates a logical or 3 of \fIWidth\fP
-bits and then instanciates it with the name \fIInstName\fP. The maximal
-authorized value for \fIWidth\fP is the full width of the current 
-data-path, set by the previous call to the function \fBDP_DEFLOFIG\fP.
-In the layout the leaf cells are placed on the slices numbered from
-\fISlice\fP to \fISlice\fB+\fIWidth\fB-1\fR (the bottom slice of the
-whole data-path is numbered zero).
-.br
-.SH CHARACTERISTICS
-.ta +15n +2n +2n
-Operator wide	:	\fB30 lambdas\fP.
-.SH EXAMPLE
-.ft CR
-.nf
-DP_OR3("or3_instance0", 32, 
-                         0, 1, "input_i0[31:0]", 
-                               "input_i1[31:0]", 
-                               "input_i2[31:0]", 
-                              "output_no[31:0]",
-                               "output_o[31:0]", EOL);
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_PDFF.3 b/alliance/share/man/man3/DP_PDFF.3
deleted file mode 100644
index 75a9c283..00000000
--- a/alliance/share/man/man3/DP_PDFF.3
+++ /dev/null
@@ -1,64 +0,0 @@
-.\"   $Id: DP_PDFF.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_PDFF 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_PDFF\fP - D Flip-Flop with write enable.
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_PDFF( 	
-    char *InstName,  /*          Instance name           */
-    long  Width   ,  /*          Number of bits          */
-    long  Slice   ,  /*    Index of the bottom slice     */
-
-    char *SigWen  ,  /*  IN         Write Enable    CTRL */
-    char *SigCK   ,  /*  IN         Clock           CTRL */
-    char *BusD    ,  /*  IN          Data Input     DATA */
-    char *BusQ    ,  /* OUT        Direct Output    DATA */
-    char *BusNQ   ,  /* OUT  Complemented Output    DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m
-	\fBDP_PDFF\fP creates a D Flip-Flop with a write enable  of \fIWidth\fP
-bits wide and then instanciates it with the name \fIInstName\fP. The maximal
-authorized value for \fIWidth\fP is the full width of the current 
-data-path, set by the previous call to the function \fBDP_DEFLOFIG\fP.
-In the layout the leaf cells are placed on the slices numbered from
-\fISlice\fP to \fISlice\fB+\fIWidth\fB-1\fR (the bottom slice of the
-whole data-path is numbered zero).
-.br
-.SH CHARACTERISTICS
-.ta +15n +2n +2n
-Operator wide	:	\fB71 lambdas\fP.
-.SH EXAMPLE
-.ft CR
-.nf
-DP_PDFF("pdff_instance0", 32, 
-                           0, "pin_wen"        ,
-                              "pin_clock"      ,
-                                "d_input[31:0]", 
-                               "q_output[31:0]",
-                              "nq_output[31:0]", EOL);
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_PDFFQ.3 b/alliance/share/man/man3/DP_PDFFQ.3
deleted file mode 100644
index 37304453..00000000
--- a/alliance/share/man/man3/DP_PDFFQ.3
+++ /dev/null
@@ -1,59 +0,0 @@
-.\"   $Id: DP_PDFFQ.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_PDFFQ 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_PDFFQ\fP - D Flip-Flop with write enable.
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_PDFFQ( 	
-    char *InstName,  /*          Instance name           */
-    long  Width   ,  /*          Number of bits          */
-    long  Slice   ,  /*    Index of the bottom slice     */
-
-    char *SigWen  ,  /*  IN         Write Enable    CTRL */
-    char *SigCK   ,  /*  IN         Clock           CTRL */
-    char *BusD    ,  /*  IN          Data Input     DATA */
-    char *BusQ    ,  /* OUT        Direct Output    DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m
-	\fBDP_PDFFQ\fP creates a D Flip-Flop with a write enable  of \fIWidth\fP
-bits wide and then instanciates it with the name \fIInstName\fP. The maximal
-authorized value for \fIWidth\fP is the full width of the current 
-data-path, set by the previous call to the function \fBDP_DEFLOFIG\fP.
-In the layout the leaf cells are placed on the slices numbered from
-\fISlice\fP to \fISlice\fB+\fIWidth\fB-1\fR (the bottom slice of the
-whole data-path is numbered zero).
-.br
-.SH EXAMPLE
-.ft CR
-.nf
-DP_PDFFQ("pdff_instance0", 32, 
-                           0, "pin_wen"        ,
-                              "pin_clock"      ,
-                                "d_input[31:0]", 
-                               "q_output[31:0]", EOL);
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_PDFFR.3 b/alliance/share/man/man3/DP_PDFFR.3
deleted file mode 100644
index 9b0895af..00000000
--- a/alliance/share/man/man3/DP_PDFFR.3
+++ /dev/null
@@ -1,67 +0,0 @@
-.\"   $Id: DP_PDFFR.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_PDFFR 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_PDFFR\fP - D Flip-Flop with write enable and reset.
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_PDFFR( 	
-    char *InstName,  /*          Instance name           */
-    long  Width   ,  /*          Number of bits          */
-    long  Slice   ,  /*    Index of the bottom slice     */
-
-    char *SigReset,  /*  IN         Reset           CTRL */
-    char *SigWen  ,  /*  IN         Write Enable    CTRL */
-    char *SigCK   ,  /*  IN         Clock           CTRL */
-    char *BusD    ,  /*  IN          Data Input     DATA */
-    char *BusQ    ,  /* OUT        Direct Output    DATA */
-    char *BusNQ   ,  /* OUT  Complemented Output    DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m
-	\fBDP_PDFFR\fP creates a D Flip-Flop with write enable and reset 
-of \fIWidth\fP
-bits wide and then instanciates it with the name \fIInstName\fP. The maximal
-authorized value for \fIWidth\fP is the full width of the current 
-data-path, set by the previous call to the function \fBDP_DEFLOFIG\fP.
-In the layout the leaf cells are placed on the slices numbered from
-\fISlice\fP to \fISlice\fB+\fIWidth\fB-1\fR (the bottom slice of the
-whole data-path is numbered zero).
-.br
-.SH CHARACTERISTICS
-.ta +15n +2n +2n
-Operator wide	:	\fB76 lambdas\fP.
-.SH EXAMPLE
-.ft CR
-.nf
-DP_PDFFR("pdffr_instance0", 32, 
-                             0, "pin_reset"      ,
-                                "pin_wen"        ,
-                                "pin_clock"      ,
-                                  "d_input[31:0]", 
-                                 "q_output[31:0]",
-                                "nq_output[31:0]", EOL);
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_PDFFRT.3 b/alliance/share/man/man3/DP_PDFFRT.3
deleted file mode 100644
index 4941aefb..00000000
--- a/alliance/share/man/man3/DP_PDFFRT.3
+++ /dev/null
@@ -1,76 +0,0 @@
-.\"   $Id: DP_PDFFRT.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_PDFFRT 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_PDFFRT\fP - D Flip-Flop with scan-path, write enable and reset.
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_PDFFRT( 	
-    char *InstName,  /*          Instance name           */
-    long  Width   ,  /*          Number of bits          */
-    long  Slice   ,  /*    Index of the bottom slice     */
-
-    char *SigScin ,  /*  IN     Scan-Path Input     CTRL */
-    char *SigTest ,  /*  IN     Scan-Path Enable    CTRL */
-    char *SigReset,  /*  IN         Reset           CTRL */
-    char *SigWen  ,  /*  IN         Write Enable    CTRL */
-    char *SigCK   ,  /*  IN         Clock           CTRL */
-    char *BusD    ,  /*  IN          Data Input     DATA */
-    char *BusQ    ,  /* OUT        Direct Output    DATA */
-    char *BusNQ   ,  /* OUT  Complemented Output    DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m +4n +10nR +2n +2n
-	\fBDP_PDFFRT\fP creates a D Flip-Flop with a scan-path support a
-write enable and a reset.
-The scan-path is active wen the input signal \fISigTest\fP
-is set to "\fB1\fP". Notice that the write enable take effect only in normal
-mode.
-.br
-	\fBDP_PDFFRT\fP build an operator of \fIWidth\fP bits wide and then
-instanciates it with the name \fIInstName\fP. The maximal
-authorized value for \fIWidth\fP is the full width of the current 
-data-path, set by the previous call to the function \fBDP_DEFLOFIG\fP.
-In the layout the leaf cells are placed on the slices numbered from
-\fISlice\fP to \fISlice\fB+\fIWidth\fB-1\fR (the bottom slice of the
-whole data-path is numbered zero).
-.br
-.SH CHARACTERISTICS
-.ta +15n +2n +2n
-Operator wide	:	\fB98 lambdas\fP.
-.SH EXAMPLE
-.ft CR
-.nf
-DP_PDFFRT("pdffrt_instance", 32, 
-                             0, "pin_scin"       ,
-                                "pin_test"       ,
-                                "pin_reset"      ,
-                                "pin_wen"        ,
-                                "pin_clock"      ,
-                                  "d_input[31:0]", 
-                                 "q_output[31:0]",
-                                "nq_output[31:0]", EOL);
-.fi
-.ft R
-.bp
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_PDFFT.3 b/alliance/share/man/man3/DP_PDFFT.3
deleted file mode 100644
index 26f370b4..00000000
--- a/alliance/share/man/man3/DP_PDFFT.3
+++ /dev/null
@@ -1,74 +0,0 @@
-.\"   $Id: DP_PDFFT.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_PDFFT 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_PDFFT\fP - D Flip-Flop with scan-path and write enable.
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_PDFFT( 	
-    char *InstName,  /*          Instance name           */
-    long  Width   ,  /*          Number of bits          */
-    long  Slice   ,  /*    Index of the bottom slice     */
-
-    char *SigScin ,  /*  IN     Scan-Path Input     CTRL */
-    char *SigTest ,  /*  IN     Scan-Path Enable    CTRL */
-    char *SigWen  ,  /*  IN         Write Enable    CTRL */
-    char *SigCK   ,  /*  IN         Clock           CTRL */
-    char *BusD    ,  /*  IN          Data Input     DATA */
-    char *BusQ    ,  /* OUT        Direct Output    DATA */
-    char *BusNQ   ,  /* OUT  Complemented Output    DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m +4n +10nR +2n +2n
-	\fBDP_PDFFT\fP creates a D Flip-Flop with a scan-path support and a
-write enable. The scan-path is active wen the input signal \fISigTest\fP
-is set to "\fB1\fP". Notice that the write enable take effect only in normal
-mode.
-.br
-	\fBDP_PDFFT\fP build an operator of \fIWidth\fP bits wide and then
-instanciates it with the name \fIInstName\fP. The maximal
-authorized value for \fIWidth\fP is the full width of the current 
-data-path, set by the previous call to the function \fBDP_DEFLOFIG\fP.
-In the layout the leaf cells are placed on the slices numbered from
-\fISlice\fP to \fISlice\fB+\fIWidth\fB-1\fR (the bottom slice of the
-whole data-path is numbered zero).
-.br
-.SH CHARACTERISTICS
-.ta +15n +2n +2n
-Operator wide	:	\fB82 lambdas\fP.
-.SH EXAMPLE
-.ft CR
-.nf
-DP_PDFFT("pdfft_instance", 32, 
-                            0, "pin_scin"       ,
-                               "pin_test"       ,
-                               "pin_wen"        ,
-                               "pin_clock"      ,
-                                 "d_input[31:0]", 
-                                "q_output[31:0]",
-                               "nq_output[31:0]", EOL);
-.fi
-.ft R
-.bp
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_PDFFTQ.3 b/alliance/share/man/man3/DP_PDFFTQ.3
deleted file mode 100644
index c425792e..00000000
--- a/alliance/share/man/man3/DP_PDFFTQ.3
+++ /dev/null
@@ -1,68 +0,0 @@
-.\"   $Id: DP_PDFFTQ.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_PDFFTQ 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_PDFFTQ\fP - D Flip-Flop with scan-path and write enable.
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_PDFFTQ( 	
-    char *InstName,  /*          Instance name           */
-    long  Width   ,  /*          Number of bits          */
-    long  Slice   ,  /*    Index of the bottom slice     */
-
-    char *SigScin ,  /*  IN     Scan-Path Input     CTRL */
-    char *SigTest ,  /*  IN     Scan-Path Enable    CTRL */
-    char *SigWen  ,  /*  IN         Write Enable    CTRL */
-    char *SigCK   ,  /*  IN         Clock           CTRL */
-    char *BusD    ,  /*  IN          Data Input     DATA */
-    char *BusQ    ,  /* OUT        Direct Output    DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m +4n +10nR +2n +2n
-	\fBDP_PDFFTQ\fP creates a D Flip-Flop with a scan-path support and a
-write enable. The scan-path is active wen the input signal \fISigTest\fP
-is set to "\fB1\fP". Notice that the write enable take effect only in normal
-mode.
-.br
-	\fBDP_PDFFTQ\fP build an operator of \fIWidth\fP bits wide and then
-instanciates it with the name \fIInstName\fP. The maximal
-authorized value for \fIWidth\fP is the full width of the current 
-data-path, set by the previous call to the function \fBDP_DEFLOFIG\fP.
-In the layout the leaf cells are placed on the slices numbered from
-\fISlice\fP to \fISlice\fB+\fIWidth\fB-1\fR (the bottom slice of the
-whole data-path is numbered zero).
-.br
-.SH EXAMPLE
-.ft CR
-.nf
-DP_PDFFTQ("pdfft_instance", 32, 
-                            0, "pin_scin"       ,
-                               "pin_test"       ,
-                               "pin_wen"        ,
-                               "pin_clock"      ,
-                                 "d_input[31:0]", 
-                                "q_output[31:0]", EOL);
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_RFG1C0.3 b/alliance/share/man/man3/DP_RFG1C0.3
deleted file mode 100644
index 50b22d78..00000000
--- a/alliance/share/man/man3/DP_RFG1C0.3
+++ /dev/null
@@ -1,69 +0,0 @@
-.\"   $Id: DP_RFG1C0.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_RFG1C0 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_RFG1C0\fP - Register File
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_RFG1C0( 
-    char *InstName,  /*            Instance name             */
-    long  RegNB   ,  /*         Number of Registers          */
-
-    char *SigAr   ,  /*  IN          Read data adress   CTRL */
-    char *SigWe   ,  /*  IN         Write enable        CTRL */
-    char *SigAw   ,  /*  IN         Write data adress   CTRL */
-    char *BusI    ,  /*  IN         Write data input    DATA */
-    char *BusO    ,  /* OUT   Direct read data output   DATA */
-    char *SigCk   ,  /*  IN              Clock input    DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m
-	\fBDP_RFG1C0\fP creates a one-read and one-write register file of
-\fIRegNB\fP registers and then instanciates it with the name \fIInstName\fP.
-The register bit-size is the full wide of the current data-path, set by the 
-previous call to the function \fBDP_DEFLOFIG\fP. The first register R0 is
-hardwired to the constant zero.
-.br
-	The environment variable \fBMBK_CATA_LIB\fP have to contain an additionnal
-library path when using this macro-function, see \fBfpgen(1)\fP for more
-details.
-.br
-.SH CHARACTERISTICS
-.ta +15n +2n +2n
-Operator wide	:	Depends on the data-path wide and \fBRegNB\fP.
-.SH EXAMPLE
-.ft CR
-.nf
-DP_RFG1C0("rfg0_instance0", 8, "read_adress[2:0]" ,
-                                "pin_wen"         ,
-                              "write_adress[2:0]" ,
-                                "data_input[31:0]", 
-                               "data_output[31:0]",
-                                "pin_ck"          , EOL);
-	
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-rfg(1)
-,
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_RFG1CC.3 b/alliance/share/man/man3/DP_RFG1CC.3
deleted file mode 100644
index 40422cab..00000000
--- a/alliance/share/man/man3/DP_RFG1CC.3
+++ /dev/null
@@ -1,69 +0,0 @@
-.\"   $Id: DP_RFG1CC.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_RFG1CC 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_RFG1CC\fP - Register File
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_RFG1CC( 
-    char *InstName,  /*            Instance name             */
-    long  RegNB   ,  /*         Number of Registers          */
-
-    char *SigAr   ,  /*  IN          Read data adress   CTRL */
-    char *SigWe   ,  /*  IN         Write enable        CTRL */
-    char *SigAw   ,  /*  IN         Write data adress   CTRL */
-    char *BusI    ,  /*  IN         Write data input    DATA */
-    char *BusO    ,  /* OUT   Direct read data output   DATA */
-    char *SigCk   ,  /*  IN              Clock input    DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m
-	\fBDP_RFG1CC\fP creates a one-read and one-write register file of
-\fIRegNB\fP registers and then instanciates it with the name \fIInstName\fP.
-The register bit-size is the full wide of the current data-path, set by the 
-previous call to the function \fBDP_DEFLOFIG\fP. The first register R0 is
-a normal register.
-.br
-	The environment variable \fBMBK_CATA_LIB\fP have to contain an additionnal
-library path when using this macro-function, see \fBfpgen(1)\fP for more
-details.
-.br
-.SH CHARACTERISTICS
-.ta +15n +2n +2n
-Operator wide	:	Depends on the data-path wide and \fBRegNB\fP.
-.SH EXAMPLE
-.ft CR
-.nf
-DP_RFG1CC("rfg0_instance0", 8, "read_adress[2:0]" ,
-                                "pin_wen"         ,
-                              "write_adress[2:0]" ,
-                                "data_input[31:0]", 
-                               "data_output[31:0]",
-                                "pin_ck"          , EOL);
-	
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-rfg(1)
-,
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_RFG2C0.3 b/alliance/share/man/man3/DP_RFG2C0.3
deleted file mode 100644
index f1d7c268..00000000
--- a/alliance/share/man/man3/DP_RFG2C0.3
+++ /dev/null
@@ -1,73 +0,0 @@
-.\"   $Id: DP_RFG2C0.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_RFG2C0 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_RFG2C0\fP - Register File
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_RFG2C0( 
-    char *InstName,  /*            Instance name             */
-    long  RegNB   ,  /*         Number of Registers          */
-
-    char *SigAr0  ,  /*  IN    First read data adress   CTRL */
-    char *SigAr1  ,  /*  IN   Second read data adress   CTRL */
-    char *SigWe   ,  /*  IN         Write enable        CTRL */
-    char *SigAw   ,  /*  IN         Write data adress   CTRL */
-    char *BusI    ,  /*  IN         Write data input    DATA */
-    char *BusO0   ,  /* OUT    First read data output   DATA */
-    char *BusO1   ,  /* OUT   Second read data output   DATA */
-    char *SigCk   ,  /*  IN              Clock input    DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m
-	\fBDP_RFG2C0\fP creates a two-read and one-write register file of
-\fIRegNB\fP registers and then instanciates it with the name \fIInstName\fP.
-The register bit-size is the full wide of the current data-path, set by the 
-previous call to the function \fBDP_DEFLOFIG\fP. The first register R0 is
-hardwired to the constant zero.
-.br
-	The environment variable \fBMBK_CATA_LIB\fP have to contain an additionnal
-library path when using this macro-function, see \fBfpgen(1)\fP for more
-details.
-.br
-.SH CHARACTERISTICS
-.ta +15n +2n +2n
-Operator wide	:	Depends on the data-path wide and \fBRegNB\fP.
-.SH EXAMPLE
-.ft CR
-.nf
-DP_RFG2C0("rfg0_instance0", 8, "read_adress0[2:0]" ,
-                               "read_adress1[2:0]" ,
-                                 "pin_wen"         ,
-                               "write_adress[2:0]" ,
-                                 "data_input[31:0]", 
-                               "data_output0[31:0]",
-                               "data_output1[31:0]",
-                                 "pin_ck"          , EOL);
-	
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-rfg(1)
-,
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_RFG2CC.3 b/alliance/share/man/man3/DP_RFG2CC.3
deleted file mode 100644
index e515ab18..00000000
--- a/alliance/share/man/man3/DP_RFG2CC.3
+++ /dev/null
@@ -1,73 +0,0 @@
-.\"   $Id: DP_RFG2CC.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_RFG2CC 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_RFG2CC\fP - Register File
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_RFG2CC( 
-    char *InstName,  /*            Instance name             */
-    long  RegNB   ,  /*         Number of Registers          */
-
-    char *SigAr0  ,  /*  IN    First read data adress   CTRL */
-    char *SigAr1  ,  /*  IN   Second read data adress   CTRL */
-    char *SigWe   ,  /*  IN         Write enable        CTRL */
-    char *SigAw   ,  /*  IN         Write data adress   CTRL */
-    char *BusI    ,  /*  IN         Write data input    DATA */
-    char *BusO0   ,  /* OUT    First read data output   DATA */
-    char *BusO1   ,  /* OUT   Second read data output   DATA */
-    char *SigCk   ,  /*  IN              Clock input    DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m
-	\fBDP_RFG2CC\fP creates a two-read and one-write register file of
-\fIRegNB\fP registers and then instanciates it with the name \fIInstName\fP.
-The register bit-size is the full wide of the current data-path, set by the 
-previous call to the function \fBDP_DEFLOFIG\fP. The first register R0 is
-a regular register.
-.br
-	The environment variable \fBMBK_CATA_LIB\fP have to contain an additionnal
-library path when using this macro-function, see \fBfpgen(1)\fP for more
-details.
-.br
-.SH CHARACTERISTICS
-.ta +15n +2n +2n
-Operator wide	:	Depends on the data-path wide and \fBRegNB\fP.
-.SH EXAMPLE
-.ft CR
-.nf
-DP_RFG2CC("rfg0_instance0", 8, "read_adress0[2:0]" ,
-                               "read_adress1[2:0]" ,
-                                 "pin_wen"         ,
-                               "write_adress[2:0]" ,
-                                 "data_input[31:0]", 
-                               "data_output0[31:0]",
-                               "data_output1[31:0]",
-                                 "pin_ck"          , EOL);
-	
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-rfg(1)
-,
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_SAVLOFIG.3 b/alliance/share/man/man3/DP_SAVLOFIG.3
deleted file mode 100644
index c478fe62..00000000
--- a/alliance/share/man/man3/DP_SAVLOFIG.3
+++ /dev/null
@@ -1,56 +0,0 @@
-.\"   $Id: DP_SAVLOFIG.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_SAVLOFIG 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_SAVLOFIG\fP - Save Data-Path figure/model.
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_SAVLOFIG()
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m +4n +10nR +2n +2n
-\fBDP_SAVLOFIG\fP saves the current working figure previously defined by
-a \fBDP_DEFLOFIG\fP call. \fBDP_SAVLOFIG\fP uses the \fBmbk(1)\fP environment
-variables to choose the file format and the path to the file.
-\fBDP_SAVLOFIG\fP doesn't look on disk for the figure \fIModelName\fP, so be
-careful not to overwrite an existing file while saving.
-.SH EXAMPLE
-.ft CR
-.nf
-#include <genlib.h>
-#include  <fpgen.h>
- 
- 
-main()
-{
-    /* Create a new data-path figure names "my_sweet_data_path". */
-    DP_DEFLOFIG("my_sweet_data_path", 32, LSB_INDEX_ZERO, TERMINAL);
-
-    /* Data-path netlist description, using macro-functions. */
-
-    /* Save the model on disk. */
-    DP_SAVLOFIG();
-}
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_SHIFT.3 b/alliance/share/man/man3/DP_SHIFT.3
deleted file mode 100644
index 572abdd0..00000000
--- a/alliance/share/man/man3/DP_SHIFT.3
+++ /dev/null
@@ -1,73 +0,0 @@
-.\"   $Id: DP_SHIFT.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_SHIFT 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_SHIFT\fP - Barrel Shifter
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_SHIFT( 
-    char *InstName,  /*             Instance name            */
-
-    char *BusI0   ,  /*  IN              Shift number   DATA */
-    char *BusSh   ,  /*  IN              Shift mode     CTRL */
-    char *BusI1   ,  /*  IN   Operand to shift input    DATA */
-    char *BusO    ,  /* OUT      Direct result output   DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m +4n +2n +12nR +2n +2n
-	\fBDP_SHIFT\fP creates a barrel shifter 
-and then instanciates it with the name \fIInstName\fP. The shifter bit-size
-is the full wide of the current data-path, set by the previous call to the
-function \fBDP_DEFLOFIG\fP.
-	The three bit wide bus signal \fIBusSh\fP select which shift operation
-to perform :
-.br
-		-	\fIBusSh[0]\fP	(ext)	:	When high the sign of the shifted
-operand is extended.
-.br
-		-	\fIBusSh[1]\fP	(rot)	:	When high the shift perform a rotate
-operation, no rotate othewise.
-.br
-		-	\fIBusSh[2]\fP	(left)	:	When high the direction of the shift
-is left, else it is rigth.
-	The environment variable \fBMBK_CATA_LIB\fP have to contain an additionnal
-library path when using this macro-function, see \fBfpgen(1)\fP for more
-details.
-.br
-.SH CHARACTERISTICS
-.ta +15n +2n +2n
-Operator wide	:	Depends on the data-path wide.
-.SH EXAMPLE
-.ft CR
-.nf
-DP_SHIFT("shift_instance0", "shift_value[4:0]" ,
-                             "shift_mode[2:0]" ,
-                             "shift_oper[31:0]", 
-                           "shift_output[31:0]", EOL);
-	
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-bsg(1)
-,
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_TRACE.3 b/alliance/share/man/man3/DP_TRACE.3
deleted file mode 100644
index c5501851..00000000
--- a/alliance/share/man/man3/DP_TRACE.3
+++ /dev/null
@@ -1,89 +0,0 @@
-.\"   $Id: DP_TRACE.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_TRACE 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_TRACE\fP - Eanble/disable trace mode.
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_TRACE(
-    long  aMode );   /*            Mode value.            */
-.fi
-.ft R
-.SH ARGUMENTS
-.in +8m
-.ta +8m
-.ti -8m
-\fIaMode\fP	Set the trace mode, two values are allowed :
-.br
-.ta +20nR +1n +2n
--	\fBTRACE_ON\fP	:	Enable trace mode.
-.br
-.br
--	\fBTRACE_OFF\fP	:	Disable trace mode.
-.br
-.SH DESCRIPTION
-.ta 4m +4n +10nR +2n +2n
-	\fBDP_TRACE\fP allow the designer to see on the standart output the
-execution of his \fBfpgen(1)\fP program. With \fBDP_TRACE\fP you can see
-the order of the function calls, which arguments are given to these
-functions and how instances are internally wired in the netlist.
-With \fBDP_TRACE\fP programs can be partially or completly traced.
-.br
-	A \fBDP_TRACE\fP call can take place at any location in a C source file,
-even before the first \fPDP_DEFLOFIG(3)\fP.
-.br
-.bp
-.SH EXAMPLE
-.ft CR
-.nf
-#include  <genlib.h>
-#include  <fpgen.h>
- 
- 
-main()
-{
-  /* Create a new data-path figure named "my_sweet_data_path". */
-  DP_DEFLOFIG( "my_sweet_data_path", 32, LSB_INDEX_ZERO );
-
-  /* Data-path netlist description, using macro-functions.
-   * The following fpgen functions are not traced.
-   */
-  /* ... */
-
-  /* Trace mode enabled, fpgen functions called after this point
-   * will be traced.
-   */
-  DP_TRACE( TRACE_ON );
-
-  /* ... */
-
-  /* Trace mode desabled. */
-  DP_TRACE( TRACE_OFF );
-
-  /* ... */
-
-  /* Save the model on disk. */
-  DP_SAVLOFIG();
-}
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_XNOR2.3 b/alliance/share/man/man3/DP_XNOR2.3
deleted file mode 100644
index f005dd93..00000000
--- a/alliance/share/man/man3/DP_XNOR2.3
+++ /dev/null
@@ -1,60 +0,0 @@
-.\"   $Id: DP_XNOR2.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_XNOR2 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_XNOR2\fP - logical not exclusive or 2
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_XNOR2( 	
-    char *InstName,  /*           Instance name           */
-    long  Width   ,  /*          Number of bits           */
-    long  Slice   ,  /*     Index of the bottom slice     */
-
-    char *BusI0   ,  /*  IN    First Operand         DATA */
-    char *BusI1   ,  /*  IN   Second Operand         DATA */
-    char *BusO    ,  /* OUT   Direct Result output   DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m +4n +10nR +2n +2n
-	\fBDP_XNOR2\fP creates a logical not exclusive or 2 of \fIWidth\fP
-bits and then instanciates it with the name \fIInstName\fP. The maximal
-authorized value for \fIWidth\fP is the full width of the current 
-data-path, set by the previous call to the function \fBDP_DEFLOFIG\fP.
-In the layout the leaf cells are placed on the slices numbered from
-\fISlice\fP to \fISlice\fB+\fIWidth\fB-1\fR (the bottom slice of the
-whole data-path is numbered zero).
-.br
-.SH CHARACTERISTICS
-.ta +15n +2n +2n
-Operator wide	:	\fB46 lambdas\fP.
-.SH EXAMPLE
-.ft CR
-.nf
-DP_XNOR2("xnor2_instance0", 32, 
-                             0, "input_i0[31:0]", 
-                                "input_i1[31:0]", 
-                                "output_o[31:0]", EOL);
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_XNOR2MASK.3 b/alliance/share/man/man3/DP_XNOR2MASK.3
deleted file mode 100644
index d14ccc3b..00000000
--- a/alliance/share/man/man3/DP_XNOR2MASK.3
+++ /dev/null
@@ -1,68 +0,0 @@
-.\"   $Id: DP_XNOR2MASK.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_XNOR2MASK 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_XNOR2MASK\fP - Logical not exclusive or 2 controllable mask.
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_XNOR2MASK( 	
-    char *InstName,  /*           Instance name           */
-    long  Width   ,  /*          Number of bits           */
-    long  Slice   ,  /*     Index of the bottom slice     */
-
-    char    *Mask ,  /*         Mask Value                */
-    char *SigMask ,  /*  IN     Mask Activation      CTRL */
-    char *BusI0   ,  /*  IN    First Operand         DATA */
-    char *BusO    ,  /* OUT   Direct Result output   DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m +4n +10nR +2n +2n
-	\fBDP_XNOR2MASK\fP creates a programmable mask which can inhibits
-the data input with a constant provided by the user. The mask is active
-when the control signal command \fISigMask\fP is "\fB1\fP", otherwise
-the input data is propagated to the output through an inverter-like
-scheme.
-.br
-	This function have a width of \fIWidth\fP
-bits and is instanciated with the name \fIInstName\fP. The maximal
-authorized value for \fIWidth\fP is the full width of the current 
-data-path, set by the previous call to the function \fBDP_DEFLOFIG\fP.
-In the layout the leaf cells are placed on the slices numbered from
-\fISlice\fP to \fISlice\fB+\fIWidth\fB-1\fR (the bottom slice of the
-whole data-path is numbered zero).
-.br
-.SH CHARACTERISTICS
-.ta +15n +2n +2n
-Operator wide	:	\fB45 lambdas\fP.
-.SH EXAMPLE
-.ft CR
-.nf
-DP_XNOR2MASK("xnor2mask_instance0", 32, 
-                                     0,
-                              "0xFFF0", "pin_msk"       ,
-                                        "input_i0[31:0]", 
-                                        "output_o[31:0]", EOL);
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/DP_XOR2.3 b/alliance/share/man/man3/DP_XOR2.3
deleted file mode 100644
index 3626536a..00000000
--- a/alliance/share/man/man3/DP_XOR2.3
+++ /dev/null
@@ -1,60 +0,0 @@
-.\"   $Id: DP_XOR2.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.TH DP_XOR2 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_XOR2\fP - logical exclusive or 2
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_XOR2( 	
-    char *InstName,  /*           Instance name           */
-    long  Width   ,  /*          Number of bits           */
-    long  Slice   ,  /*     Index of the bottom slice     */
-
-    char *BusI0   ,  /*  IN    First Operand         DATA */
-    char *BusI1   ,  /*  IN   Second Operand         DATA */
-    char *BusO    ,  /* OUT   Direct Result output   DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m +4n +10nR +2n +2n
-	\fBDP_XOR2\fP creates a logical exclusive or 2 of \fIWidth\fP
-bits and then instanciates it with the name \fIInstName\fP. The maximal
-authorized value for \fIWidth\fP is the full width of the current 
-data-path, set by the previous call to the function \fBDP_DEFLOFIG\fP.
-In the layout the leaf cells are placed on the slices numbered from
-\fISlice\fP to \fISlice\fB+\fIWidth\fB-1\fR (the bottom slice of the
-whole data-path is numbered zero).
-.br
-.SH CHARACTERISTICS
-.ta +15n +2n +2n
-Operator wide	:	\fB46 lambdas\fP.
-.SH EXAMPLE
-.ft CR
-.nf
-DP_XOR2("xor2_instance0", 32, 
-                           0, "input_i0[31:0]", 
-                              "input_i1[31:0]", 
-                              "output_o[31:0]", EOL);
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/ELM.3 b/alliance/share/man/man3/ELM.3
deleted file mode 100644
index 14d93a39..00000000
--- a/alliance/share/man/man3/ELM.3
+++ /dev/null
@@ -1,75 +0,0 @@
-.\"   $Id: ELM.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.\" @(#)ELM.3 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-ELM
-.XE \}
-.TH ELM 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-ELM \- Creates a single element bus name for netlist
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-char \(**ELM(busname, index);
-char \(**busname;
-long index;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIbusname\fP
-Common signal name for a bus
-.TP 20
-\fIindex\fP
-Index of the demanded signal belonging to the bus
-.SH DESCRIPTION
-\fIELM\fP Creates a single element bus names valid for the genlib netlist
-functions that manipulate the signal, and/or connector, concept.
-They are:
-.RS
-\fBLOINS\fP(3)
-.br
-\fBLOCON\fP(3)
-.RE
-The \fIindex\fP argument gives the index of the name to be created.
-.br
-This function has a constant equivalent, it means that if the \fIindex\fP
-value is known at compilation time, one should better use,
-for readability purposes, the "[n]" construct.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-int b = 0;
-int e = 12;
-	/\(** Create a figure to work on  \(**/
-	DEF_LOFIG("mycell");
-	/\(** define interface  \(**/
-	LOCON(BUS("i", b, e), INPUT, BUS("sig", b, e);
-	LOCON("o[2:0]", OUTPUT, "sigout[4:6]");
-	/\(** Place an instance \(**/
-	LOINS("model","instance", ELM("sig", e/2), "sigout[6]", EOL);
-	/\(** Save all that on disk \(**/
-	SAVE_LOFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR BUS (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/FLATTEN_ALL_LOINS.3 b/alliance/share/man/man3/FLATTEN_ALL_LOINS.3
deleted file mode 100644
index 33d230fb..00000000
--- a/alliance/share/man/man3/FLATTEN_ALL_LOINS.3
+++ /dev/null
@@ -1,76 +0,0 @@
-.\"   $Id: FLATTEN_ALL_LOINS.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.\" @(#)FLATTEN_ALL_LOINS.3 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-FLATTEN_ALL_LOINS
-.XE \}
-.TH FLATTEN_ALL_LOINS 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-FLATTEN_ALL_LOINS \- flatten all instances in the current netlist figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void FLATTEN_ALL_LOINS(concat)
-char concat;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETER
-.TP 20
-\fIconcat\fP
-Indicate whether or not to concatenate instance name to instance' objects name
-.SH DESCRIPTION
-\fBFLATTEN_ALL_LOINS\fP inserts the contents of all the instances of the
-current figure in the current figure.
-All these instances are destroyed during the process, and therefore cannot be
-refered to later in the netlist description.
-.br
-The \fIconcat\fP parameter may take two values:
-.TP
-\fBYES\fP
-to concatenate object name with instance names.
-.TP
-\fBNO\fP 
-to copy object names.
-.LP
-In most case, the \fIconcat\fP value must be \fBYES\fP, in order to warranty
-the unicity of names in the figure.
-It may otherwise fail, because the function would try to add in the current
-figure some object with an already existing name.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_LOFIG("mycell");
-	.
-	.
-	.
-	/\(** Place an instance \(**/
-	LOINS("model","instance", "sig1", "sig2", EOL);
-	/\(** flatten all figure instance \(**/
-	FLATTEN_ALL_LOINS(YES);
-	/\(** Save all that on disk \(**/
-	SAVE_LOFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR LOINS (3)
-.BR FLATTEN_LOFIG (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/FLATTEN_ALL_PHINS.3 b/alliance/share/man/man3/FLATTEN_ALL_PHINS.3
deleted file mode 100644
index 421388c9..00000000
--- a/alliance/share/man/man3/FLATTEN_ALL_PHINS.3
+++ /dev/null
@@ -1,93 +0,0 @@
-.\"   $Id: FLATTEN_ALL_PHINS.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.\" @(#)FLATTEN_ALL_PHINS.3 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-FLATTEN_ALL_PHINS
-.XE \}
-.TH FLATTEN_ALL_PHINS 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-FLATTEN_ALL_PHINS \- flatten all instances in the current layout figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void FLATTEN_ALL_PHINS(concat, catal)
-char concat, catal;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETER
-.TP 20
-\fIconcat\fP
-Indicate whether or not to concatenate instance name to instance' objects name
-.TP 20
-\fIconcat\fP
-Indicate whether or not to look in the catalog file before flattening a cell
-.SH DESCRIPTION
-\fBFLATTEN_ALL_PHINS\fP inserts the contents of all the instances of the
-current figure in the current figure.
-All these instances are destroyed during the process, and therefore cannot be
-refered to later in the layout description.
-.br
-The \fIconcat\fP parameter may take two values:
-.TP
-\fBYES\fP
-to concatenate object name with instance names.
-.TP
-\fBNO\fP 
-to copy object names.
-.LP
-In most case, the \fIconcat\fP value must be \fBYES\fP, in order to warranty
-the unicity of names in the figure.
-It may otherwise fail, because the function would try to add in the current
-figure some object with an already existing name.
-.br
-The \fIcatal\fP parameter may also take two values:
-.TP
-\fBYES\fP
-to check the catalog file to see if the model of an instance is in it.
-If the model belong to the catalog, then it is \fInot\fR flattened.
-.TP
-\fBNO\fP 
-in this case, no checks are done, and every instance is flattened.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("mycell");
-	.
-	.
-	.
-	/\(** Place an instance \(**/
-	PHINS("model","instance", "sig1", "sig2", EOL);
-	/\(** flatten all figure instance \(**/
-	FLATTEN_ALL_PHINS(YES, YES);
-	/\(** Save all that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR PLACE (3),
-.BR PLACE_LEFT (3),
-.BR PLACE_RIGHT (3),
-.BR PLACE_TOP (3),
-.BR PLACE_BOTTOM (3),
-.BR PLACE_ON (3),
-.BR FLATTEN_PHFIG (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/FLATTEN_LOFIG.3 b/alliance/share/man/man3/FLATTEN_LOFIG.3
deleted file mode 100644
index 617dd4ed..00000000
--- a/alliance/share/man/man3/FLATTEN_LOFIG.3
+++ /dev/null
@@ -1,78 +0,0 @@
-.\"   $Id: FLATTEN_LOFIG.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.\" @(#)FLATTEN_LOFIG.3 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-FLATTEN_LOFIG
-.XE \}
-.TH FLATTEN_LOFIG 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-FLATTEN_LOFIG \- flatten an instance in the current netlist figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void FLATTEN_LOFIG(insname,concat)
-char \(**insname;
-char concat;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIinsname\fP
-Name of the instance to be flattened
-.TP
-\fIconcat\fP
-Indicate whether or not to concatenate instance name to instance' objects name
-.SH DESCRIPTION
-\fBFLATTEN_LOFIG\fP inserts the contents of an instance, but its connectors,
-in the current figure, and then destroys the instance.
-.br
-The \fIconcat\fP parameter may take two values:
-.TP
-\fBYES\fP
-to concatenate object name with instance names.
-.TP
-\fBNO\fP 
-to copy object names.
-.LP
-In most case, the \fIconcat\fP value must be \fBYES\fP, in order to warranty
-the unicity of names in the figure.
-It may otherwise fail, because the function would try to add in the current
-figure some object with an already existing name.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_LOFIG("mycell");
-	.
-	.
-	.
-	/\(** Place an instance \(**/
-	LOINS("model","instance", "sig1", "sig2", EOL);
-	/\(** flatten an instance \(**/
-	FLATTEN_LOFIG("instance", YES);
-	/\(** Save all that on disk \(**/
-	SAVE_LOFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR UNFLATTEN_LOFIG (3).
-.BR LOINS (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/FLATTEN_PHFIG.3 b/alliance/share/man/man3/FLATTEN_PHFIG.3
deleted file mode 100644
index 8d84a2a0..00000000
--- a/alliance/share/man/man3/FLATTEN_PHFIG.3
+++ /dev/null
@@ -1,77 +0,0 @@
-.\"   $Id: FLATTEN_PHFIG.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.\" @(#)FLATTEN_PHFIG.3 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-FLATTEN_PHFIG
-.XE \}
-.TH FLATTEN_PHFIG 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-FLATTEN_PHFIG \- flatten an instance in the current layout figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void FLATTEN_PHFIG(insname,concat)
-char \(**insname;
-char concat;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIinsname\fP
-Name of the instance to be flattened
-.TP
-\fIconcat\fP
-Indicate whether or not to concatenate instance name to instance' objects name
-.SH DESCRIPTION
-\fBFLATTEN_PHFIG\fP inserts the contents of an instance, but its connectors,
-in the current figure, and then destroys the instance.
-.br
-The \fIconcat\fP parameter may take two values:
-.TP 20
-\fBYES\fP
-to concatenate object name with instance names.
-.TP
-\fBNO\fP 
-to copy object names.
-.LP
-In most case, the \fIconcat\fP value must be \fBYES\fP, in order to warranty
-the unicity of names in the figure.
-It may otherwise fail, because the function would try to add in the current
-figure some object with an already existing name.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("mycell");
-	.
-	.
-	.
-	/\(** Place an instance \(**/
-	PLACE("model","instance", SYM_X, 0, 0);
-	/\(** flatten an instance \(**/
-	FLATTEN_PHFIG("instance", YES);
-	/\(** Save all that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR LOINS (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_BUS.3 b/alliance/share/man/man3/GENLIB_BUS.3
deleted file mode 100644
index dea3ca85..00000000
--- a/alliance/share/man/man3/GENLIB_BUS.3
+++ /dev/null
@@ -1,81 +0,0 @@
-.\"   $Id: GENLIB_BUS.3,v 1.3 2000/11/06 12:08:42 francois Exp $
-.\" @(#)GENLIB_BUS.3 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_BUS
-.XE \}
-.TH GENLIB_BUS.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_BUS \- Creates a bus name for netlist
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-char \(**GENLIB_BUS(busname, from, to);
-char \(**busname;
-long from, to;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIbusname\fP
-Common signal name for a bus
-.TP
-\fIfrom\fP
-Starting index of the set of signal, \fIfrom\fP included
-.TP
-\fIto\fP
-Ending index of the set of signal, \fIto\fP included
-.SH DESCRIPTION
-\fIGENLIB_BUS\fP Creates a set of names, based upon a common name, valid for the
-genlib netlist
-functions that manipulate the signal, and/or connector, concept.
-They are:
-.RS
-\fBLOINS\fP(3)
-.br
-\fBLOCON\fP(3)
-.RE
-The \fIfrom, to\fP arguments give the boundaries of the bus to be created,
-both of them beeing included in the set. The function allows increasing or
-decreasing order busses, as one could expect.
-.br
-This function has a constant equivalent, it means that if the \fIfrom, to\fP
-values are known at compilation time, one should better use,
-for readability purposes, the "[n:m]" construct.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-int b = 0;
-int e = 12;
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_LOFIG("mycell");
-	/\(** define interface  \(**/
-	GENLIB_LOCON(GENLIB_BUS("i", b, e), INPUT, GENLIB_BUS("sig", b, e);
-	GENLIB_LOCON("o[2:0]", OUTPUT, "sigout[4:6]");
-	/\(** Place an instance \(**/
-	GENLIB_LOINS("model","instance", GENLIB_BUS("sig", e/2), "sigout[6]", EOL);
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_LOFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_ELM (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_COPY_UP_ALL_CON.3 b/alliance/share/man/man3/GENLIB_COPY_UP_ALL_CON.3
deleted file mode 100644
index f8b08452..00000000
--- a/alliance/share/man/man3/GENLIB_COPY_UP_ALL_CON.3
+++ /dev/null
@@ -1,122 +0,0 @@
-.\"   $Id: GENLIB_COPY_UP_ALL_CON.3,v 1.2 2000/09/28 15:25:48 fred Exp $
-.\" @(#)GENLIB_COPY_UP_ALL_CON.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_COPY_UP_ALL_CON
-.XE \}
-.TH GENLIB_COPY_UP_ALL_CON.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_COPY_UP_ALL_CON \- copy all physical connectors of an instance face in the
-current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_COPY_UP_ALL_CON(face, insname, concatenate)
-char face, concatenate;
-char \(**insname;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIface\fP
-Face of the instance
-.TP
-\fIinsname\fP
-Name of the instance the connector belongs to
-.TP
-\fIconcatenate\fP
-Indicates wheter or not to concatenate instance connectors names with instance
-name
-.SH DESCRIPTION
-\fBCOPY_UP_ALL_CON\fP copies all instance connectors of the face \fIface\fP of
-the placed instance called \fIinsname\fP into the current layout.
-The \fIconcatenate\fP argument may take two values:
-.TP 20
-\fBYES\fP
-then the resulting name of a connector in the current figure is the
-concatenation of the \fIinsname\fP and the \fIconname\fP.
-It warranties the unicity of name at the figure level, and is to be used
-most of the time.
-.TP
-\fBNO\fP
-implies a direct copy of the connector name.
-The user must take care of the unicity of connector name by itself.
-.br
-Two behaviour are expected, depending on each of the instance connectors
-location regarding the \fIabutment box\fP of the current figure.
-.TP 20
-Connector on the \fIabutment box\fP
-The figure connector is place right over the instance connector. The single
-connector is duplicated.
-.TP
-Connector inside the \fIabutment box\fP
-The instance connector face is computed in the figure, and then, the connector
-is duplicated \fIon\fP the given face, at the right coordinates for this face.
-Then a wire is drawn between the instance connector and the figure connector in
-the connector layer.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_COPY_UP_ALL_CON impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a connector inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"*** genlib error *** GENLIB_COPY_UP_ALL_CON impossible : connector \fIconname\fP face
-\fIface\fP of instance \fIinsname\fP, \fIcurrent\fP figure doesn't exist"
-.ft R
-.RS
-No connector matches both the \fIconname\fP and the \fIface\fP arguments.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("cell");
-	.
-	.
-	GENLIB_PLACE_LEFT("gaer0_f", "insN", SYMXY);
-	.
-	.
-	GENLIB_DEF_AB(0L, 0L, 0L, 0L);
-	/\(** Copy all connectors \(**/
-	GENLIB_COPY_UP_ALL_CON(NORTH, "insN", YES);
-	/\(** Save that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHFIG (3),
-.BR GENLIB_SAVE_PHFIG (3),
-.BR GENLIB_COPY_UP_CON (3),
-.BR GENLIB_COPY_UP_CON_FACE (3),
-.BR GENLIB_PHCON (3),
-.BR GENLIB_THRU_CON_H (3),
-.BR GENLIB_THRU_CON_V (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_COPY_UP_ALL_REF.3 b/alliance/share/man/man3/GENLIB_COPY_UP_ALL_REF.3
deleted file mode 100644
index 0c927cea..00000000
--- a/alliance/share/man/man3/GENLIB_COPY_UP_ALL_REF.3
+++ /dev/null
@@ -1,127 +0,0 @@
-.\"   $Id: GENLIB_COPY_UP_ALL_REF.3,v 1.2 2000/09/28 15:25:48 fred Exp $
-.\" @(#)GENLIB_COPY_UP_ALL_REF.3 2.11 01/92; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_COPY_UP_ALL_REF
-.XE \}
-.TH GENLIB_COPY_UP_ALL_REF.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_COPY_UP_ALL_REF \- copy a several physical reference from an instance
-in the current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_COPY_UP_ALL_REF(reftype, insname, concatenate)
-char \(**reftype, \(**insname;
-char concatenate;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIreftype\fP
-Type of the references to be duplicated
-.TP
-\fIinsname\fP
-Name of the instance in the which the references is to be searched for
-.TP
-\fIconcatenate\fP
-Indicates whether or not to concatenate the instance name to the references
-names when copying
-.SH DESCRIPTION
-\fBCOPY_UP_ALL_REF\fP duplicates all the references of type \fIreftype\fP
-of the instance called \fIinsname\fP into the current layout cell.
-The main purpose of this function is to copy a set references in the upper
-hierarchical level, so it can be used as \fIvirtual\fP connector, for
-the data-path router.
-See \fBdpr\fP(1) for details.
-.br
-The \fIreftype\fP argument can take two values:
-.TP 20
-\fB"ref_con"\fP
-for virtual connectors
-.TP
-\fB"ref_ref"\fP
-for any other references
-.LP
-See the \fIleaf cells design for generators\fP document for details on
-reference types and usage.
-.br
-The \fIconcatenate\fP argument can take two values:
-.TP 20
-A\fBYES\fP
-indicates that the name of the copied references is concatenated to the
-instance name.
-.TP
-\fBNO\fP
-implies a direct duplication of the reference name
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_COPY_UP_ALL_REF impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a reference inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphins : instance \fIinsname\fP does not exist"
-.ft R
-.RS
-The instance called \fIinsname\fP does not currently belong to the figure.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_COPY_UP_ALL_REF impossible : references of type \fIreftype\fP do not exist"
-.ft R
-.RS
-No reference of type \fIreftype\fP exist in the model of the instance
-\fIinsname\fP.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("cell");
-	GENLIB_PLACE("z2l_y", "r1", NOSYM, 23L, 54L);
-	/\(** Put a reference \(**/
-	GENLIB_COPY_UP_ALL_REF("ref_con", "r1", NO);
-	/\(** Save that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR dpr (1),
-.BR genlib (1),
-.BR GENLIB_DEF_PHFIG (3),
-.BR GENLIB_SAVE_PHFIG (3),
-.BR GENLIB_PHREF (3),
-.BR GENLIB_COPY_UP_ALL_REF (3),
-.BR GENLIB_PLACE_CON_REF (3),
-.BR GENLIB_PLACE_SEG_REF (3),
-.BR GENLIB_PLACE_VIA_REF (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_COPY_UP_CON.3 b/alliance/share/man/man3/GENLIB_COPY_UP_CON.3
deleted file mode 100644
index cab27bc6..00000000
--- a/alliance/share/man/man3/GENLIB_COPY_UP_CON.3
+++ /dev/null
@@ -1,119 +0,0 @@
-.\"   $Id: GENLIB_COPY_UP_CON.3,v 1.2 2000/09/28 15:25:48 fred Exp $
-.\" @(#)GENLIB_COPY_UP_CON.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_COPY_UP_CON
-.XE \}
-.TH GENLIB_COPY_UP_CON.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_COPY_UP_CON \- copy a physical connector from an instance in the
-current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_COPY_UP_CON(index, conname, insname, newname)
-long index;
-char \(**insname;
-char \(**conname;
-char \(**newname;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIindex\fP
-Connector index in the instance
-.TP
-\fIconname\fP
-Name of the connector in the instance model
-.TP
-\fIinsname\fP
-Name of the instance the connector belongs to
-.TP
-\fInewname\fP
-Name to be given to the connector in the current figure
-.SH DESCRIPTION
-\fBCOPY_UP_CON\fP copies a instance connector into the current layout figure,
-and gives to the new connector the name \fInewname\fP. The instance connector
-is identified by its name, \fIconname\fP, and index, \fIindex\fP.
-.br
-Two behaviour are expected, depending on the instance connector location
-regarding the \fIabutment box\fP of the current figure.
-.TP 20
-Connector on the \fIabutment box\fP
-The figure connector is place right over the instance connector. The single
-connector is duplicated.
-.TP
-Connector inside the \fIabutment box\fP
-The instance connector face is computed in the figure, and then, the connector
-is duplicated \fIon\fP the given face, at the right coordinates for this face.
-Then a wire is drawn between the instance connector and the figure connector in
-the connector layer.
-.LP
-If \fInewname\fP is \fBNULL\fP, then not connector is copied up, on the segment
-is drawn to the side of the \fIabutment\fP box.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_COPY_UP_CON impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a connector inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"*** genlib error *** GENLIB_COPY_UP_CON impossible : connector \fIconname\fP index
-\fIindex\fP of instance \fIinsname\fP, \fIcurrent\fP figure doesn't exist"
-.ft R
-.RS
-The given connector does not exist in the current figure.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("cell");
-	.
-	.
-	GENLIB_PLACE_LEFT("gaer0_f", "insN", SYMXY);
-	.
-	.
-	GENLIB_DEF_AB(0L, 0L, 0L, 0L);
-	/\(** Put a connector \(**/
-	GENLIB_COPY_UP_CON("i0", 1, "insN", "inz0");
-	/\(** Save that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHFIG (3),
-.BR GENLIB_SAVE_PHFIG (3),
-.BR GENLIB_COPY_UP_ALL_CON (3),
-.BR GENLIB_COPY_UP_CON_FACE (3),
-.BR GENLIB_PHCON (3),
-.BR GENLIB_THRU_CON_H (3),
-.BR GENLIB_THRU_CON_V (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_COPY_UP_CON_FACE.3 b/alliance/share/man/man3/GENLIB_COPY_UP_CON_FACE.3
deleted file mode 100644
index a01edad5..00000000
--- a/alliance/share/man/man3/GENLIB_COPY_UP_CON_FACE.3
+++ /dev/null
@@ -1,119 +0,0 @@
-.\"   $Id: GENLIB_COPY_UP_CON_FACE.3,v 1.2 2000/09/28 15:25:48 fred Exp $
-.\" @(#)GENLIB_COPY_UP_CON_FACE.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_COPY_UP_CON_FACE
-.XE \}
-.TH GENLIB_COPY_UP_CON_FACE.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_COPY_UP_CON_FACE \- copy a physical connector from an instance in the
-current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_COPY_UP_CON_FACE(face, conname, insname, newname)
-long index;
-char \(**insname;
-char \(**conname;
-char \(**newname;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIface\fP
-Connector face in the instance
-.TP
-\fIconname\fP
-Name of the connector in the instance model
-.TP
-\fIinsname\fP
-Name of the instance the connector belongs to
-.TP
-\fInewname\fP
-Name to be given to the connector in the current figure
-.SH DESCRIPTION
-\fBCOPY_UP_CON_FACE\fP copies a instance connector into the current layout
-figure, and gives to the new connector the name \fInewname\fP.
-The \fIface\fP and \fIconname\fP arguments are not suffiscient for non
-ambiguiously identify a single connector.
-So, if more than one connector matches these arguments, the behaviour described
-below is applied on all of them.
-.br
-Two behaviour are expected, depending on the instance connector location
-regarding the \fIabutment box\fP of the current figure.
-.TP 20
-Connector on the \fIabutment box\fP
-The figure connector is place right over the instance connector. The single
-connector is duplicated.
-.TP
-Connector inside the \fIabutment box\fP
-The instance connector face is computed in the figure, and then, the connector
-is duplicated \fIon\fP the given face, at the right coordinates for this face.
-Then a wire is drawn between the instance connector and the figure connector in
-the connector layer.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_COPY_UP_CON_FACE impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a connector inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"*** genlib error *** GENLIB_COPY_UP_CON_FACE impossible : connector \fIconname\fP face
-\fIface\fP of instance \fIinsname\fP, \fIcurrent\fP figure doesn't exist"
-.ft R
-.RS
-No connector matches both the \fIconname\fP and the \fIface\fP arguments.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("cell");
-	.
-	.
-	GENLIB_PLACE_LEFT("gaer0_f", "insN", SYMXY);
-	.
-	.
-	GENLIB_DEF_AB(0L, 0L, 0L, 0L);
-	/\(** Put a connector \(**/
-	GENLIB_COPY_UP_CON_FACE("i0", 1, "insN", "inz0");
-	/\(** Save that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHFIG (3),
-.BR GENLIB_SAVE_PHFIG (3),
-.BR GENLIB_COPY_UP_ALL_CON (3),
-.BR GENLIB_COPY_UP_CON (3),
-.BR GENLIB_PHCON (3),
-.BR GENLIB_THRU_CON_H (3),
-.BR GENLIB_THRU_CON_V (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_COPY_UP_REF.3 b/alliance/share/man/man3/GENLIB_COPY_UP_REF.3
deleted file mode 100644
index 4c8f7208..00000000
--- a/alliance/share/man/man3/GENLIB_COPY_UP_REF.3
+++ /dev/null
@@ -1,110 +0,0 @@
-.\"   $Id: GENLIB_COPY_UP_REF.3,v 1.2 2000/09/28 15:25:48 fred Exp $
-.\" @(#)GENLIB_COPY_UP_REF.3 2.11 01/92; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_COPY_UP_REF
-.XE \}
-.TH GENLIB_COPY_UP_REF.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_COPY_UP_REF \- copy a physical reference from an instance in the current
-figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_COPY_UP_REF(refname, insname, newname)
-char \(**refname, \(**insname, \(**newname;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIrefname\fP
-Name of the reference in the instance
-.TP
-\fIinsname\fP
-Name of the instance in the which the reference is to be searched for
-.TP
-\fInewname\fP
-Name to be given to the reference in the current figure
-.SH DESCRIPTION
-\fBCOPY_UP_REF\fP adds a reference in the current layout cell.
-All the reference's attributes are copied from the first found reference
-called \fIrefname\fP in the instance \fIinsname\fP.
-The designer should avoid to give to several refences the same name if
-he plans to use this function.
-The new reference is given the name \fInewname\fP.
-The main purpose of this function is to copy a reference in the upper
-hierarchical level, so it can be used as \fIvirtual\fP connector, for
-the data-path router.
-See \fBdpr\fP(1) for details.
-layout.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_COPY_UP_REF impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a reference inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphins : instance \fIinsname\fP does not exist"
-.ft R
-.RS
-The instance called \fIinsname\fP does not currently belong to the figure.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_COPY_UP_REF impossible : reference \fIrefname\fP does not exist"
-.ft R
-.RS
-The reference \fIrefname\fP does not exist in the model of the instance
-\fIinsname\fP.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("cell");
-	GENLIB_PLACE("z2l_y", "r1", NOSYM, 23L, 54L);
-	/\(** Put a reference \(**/
-	GENLIB_COPY_UP_REF("mux0_s", "r1", "out_s");
-	/\(** Save that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR dpr (1),
-.BR genlib (1),
-.BR GENLIB_DEF_PHFIG (3),
-.BR GENLIB_SAVE_PHFIG (3),
-.BR GENLIB_PHREF (3),
-.BR GENLIB_COPY_UP_ALL_REF (3),
-.BR GENLIB_PLACE_CON_REF (3),
-.BR GENLIB_PLACE_SEG_REF (3),
-.BR GENLIB_PLACE_VIA_REF (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_COPY_UP_SEG.3 b/alliance/share/man/man3/GENLIB_COPY_UP_SEG.3
deleted file mode 100644
index 5e4fb5bd..00000000
--- a/alliance/share/man/man3/GENLIB_COPY_UP_SEG.3
+++ /dev/null
@@ -1,107 +0,0 @@
-.\"   $Id: GENLIB_COPY_UP_SEG.3,v 1.2 2000/09/28 15:25:48 fred Exp $
-.\" @(#)GENLIB_COPY_UP_SEG.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_COPY_UP_SEG
-.XE \}
-.TH GENLIB_COPY_UP_SEG.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_COPY_UP_SEG \- copy a physical segment from an instance in the current
-figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_COPY_UP_SEG(oldname, insname, newname)
-char \(**oldname, \(**insname, \(**newname;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIoldname\fP
-Name of the segment in the instance
-.TP
-\fIinsname\fP
-Name of the instance in the which the segment is to be searched for
-.TP
-\fInewname\fP
-Name to be given to the segment in the current figure
-.SH DESCRIPTION
-\fBCOPY_UP_SEG\fP adds a segment in the current layout cell.
-All the segment's attributes are copied from the first found segment called
-\fIoldname\fP in the instance \fIinsname\fP.
-The new segment is given the name \fInewname\fP. The main purpose of this
-function is to rename a segment, so it can be used later, when extracting a
-layout.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_COPY_UP_SEG impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a segment inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphins : instance \fIinsname\fP does not exist"
-.ft R
-.RS
-The instance called \fIinsname\fP does not currently belong to the figure.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_COPY_UP_SEG impossible : segment \fIsegname\fP does not exist"
-.ft R
-.RS
-The segment \fIsegname\fP does not exist in the model of the instance
-\fIinsname\fP.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("cell");
-	GENLIB_PLACE("z2l_y", "r1", NOSYM, 23L, 54L);
-	/\(** Put a segment \(**/
-	GENLIB_COPY_UP_SEG("mux0_s", "r1", "out_s");
-	/\(** Save that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHFIG (3),
-.BR GENLIB_SAVE_PHFIG (3),
-.BR GENLIB_PHSEG (3),
-.BR GENLIB_THRU_H (3),
-.BR GENLIB_THRU_CON_H (3),
-.BR GENLIB_THRU_V (3),
-.BR GENLIB_THRU_CON_V (3),
-.BR GENLIB_WIRE1 (3),
-.BR GENLIB_WIRE2 (3),
-.BR GENLIB_WIRE3 (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_DEF_AB.3 b/alliance/share/man/man3/GENLIB_DEF_AB.3
deleted file mode 100644
index a5b46819..00000000
--- a/alliance/share/man/man3/GENLIB_DEF_AB.3
+++ /dev/null
@@ -1,84 +0,0 @@
-.\"   $Id: GENLIB_DEF_AB.3,v 1.2 2000/09/28 15:25:48 fred Exp $
-.\" @(#)GENLIB_DEF_AB.3 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_DEF_AB
-.XE \}
-.TH GENLIB_DEF_AB.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_DEF_AB \- define a new \fIabutment box\fP to the current layout cell
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_DEF_AB(dx1, dy1, dx2, dy2);
-long dx1, dy1, dx2, dy2;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIdx1, dy1\fP
-Values to be added to the lower left corner of the previous \fIabutment box\fP
-.TP
-\fIdx2, dy2\fP
-Values to be added to the upper right corner of the previous \fIabutment box\fP
-.SH DESCRIPTION
-\fBDEF_AB\fP give a new \fIabutment box\fP to the current physical cell.
-The coordinates of
-the \fIabutment box\fP are the coordinates of the envelop of the \fIabutment boxes\fP of
-each instance plus the delta values given as argument. The \fI(dx1, dy1)\fP
-values are added to the (x1, y1) coordinates of the bottom left corner of the
-\fI"standard abutment box"\fP (the envelop), and the \fI(dx2, dy2)\fP
-are added to the top right ones.
-You have to call this function before saving, otherwise the figure will not
-have an \fIabutment box\fP. Since it's regarding the \fIabutment box\fP
-of its model that an instance is placed, any futher use of this figure
-will be incorrect if \fBDEF_AB\fP isn't called, or properly defined.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_DEF_AB impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to give it a size.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("cell");
-	/\(** Place an instance \(**/
-	GENLIB_PLACE("model","i1", NOSYM,0L,0L);
-	GENLIB_PLACE("model","i2", NOSYM,120L,40L);
-	GENLIB_DEF_PHINS("i1");
-	GENLIB_PLACE_TOP("model2", "i3", NOSYM);
-	/\(** define the new abutment box as the standard envelop \(**/
-	GENLIB_DEF_AB(0, 0, 0, 0);
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_SAVE_PHFIG (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_DEF_LOFIG.3 b/alliance/share/man/man3/GENLIB_DEF_LOFIG.3
deleted file mode 100644
index 50fc97a1..00000000
--- a/alliance/share/man/man3/GENLIB_DEF_LOFIG.3
+++ /dev/null
@@ -1,62 +0,0 @@
-.\"   $Id: GENLIB_DEF_LOFIG.3,v 1.2 2000/09/28 15:25:49 fred Exp $
-.\" @(#)GENLIB_DEF_LOFIG.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_DEF_LOFIG
-.XE \}
-.TH GENLIB_DEF_LOFIG.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_DEF_LOFIG \- open a netlist model as current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_DEF_LOFIG(cellname)
-char \(**cellname;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIcellname\fP
-Name of the cell which all futher calls to genlib logical functions will work on 
-.SH DESCRIPTION
-\fBDEF_LOFIG\fP defines the current working structural figure by it's name, 
-the \fIcellname\fP argument. It can be use anywhere in the \fBgenlib\fP 
-program, but must appear at least once at the top of it, since it also 
-initalize the user's preferences through environment variables.
-.br
-If the figure called cellname doesn't exists in memory, it is created. 
-If it already exists in memory, it makes it the current working figure. 
-\fBDEF_LOFIG\fP doesn't look on disk for the figure \fIcellname\fP, 
-so be careful not to overwrite an existing file while saving later on.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_LOFIG("cell");
-	/\(** Place an instance \(**/
-	GENLIB_LOINS("model","instance", "sig1", "sig2", "sig3", "vdd", "vss", EOL);
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_LOFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_SAVE_LOFIG (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_DEF_PHFIG.3 b/alliance/share/man/man3/GENLIB_DEF_PHFIG.3
deleted file mode 100644
index d562813a..00000000
--- a/alliance/share/man/man3/GENLIB_DEF_PHFIG.3
+++ /dev/null
@@ -1,62 +0,0 @@
-.\"   $Id: GENLIB_DEF_PHFIG.3,v 1.2 2000/09/28 15:25:49 fred Exp $
-.\" @(#)GENLIB_DEF_PHFIG.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_DEF_PHFIG
-.XE \}
-.TH GENLIB_DEF_PHFIG.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_DEF_PHFIG \- open a layout model as current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_DEF_PHFIG(cellname)
-char \(**cellname;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIcellname\fP
-Name of the cell which all futher calls to genlib physical functions will work on
-.SH DESCRIPTION
-\fBDEF_PHFIG\fP defines the current physical working figure by it's name, 
-the \fIcellname\fP argument. It can be use anywhere in the \fBgenlib\fP 
-program, but must appear at least once at the top of it, since it also 
-initalize the user's preferences through environment variables.
-.br
-If the figure called cellname doesn't exists in memory, it is created. 
-If it already exists in memory, it makes it the current working figure. 
-\fBDEF_PHFIG\fP doesn't look on disk for the figure \fIcellname\fP, 
-so be careful not to overwrite an existing file while saving later on.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("mycell");
-	/\(** Place an instance \(**/
-	GENLIB_PLACE("mymodel","firstinstance", NOSYM,0L,0L);
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHSC (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_DEF_PHINS.3 b/alliance/share/man/man3/GENLIB_DEF_PHINS.3
deleted file mode 100644
index 6fce0171..00000000
--- a/alliance/share/man/man3/GENLIB_DEF_PHINS.3
+++ /dev/null
@@ -1,94 +0,0 @@
-.\"   $Id: GENLIB_DEF_PHINS.3,v 1.2 2000/09/28 15:25:49 fred Exp $
-.\" @(#)GENLIB_DEF_PHINS.3 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_DEF_PHINS
-.XE \}
-.TH GENLIB_DEF_PHINS.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_DEF_PHINS \- define a new reference instance
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_DEF_PHINS(instancename);
-char \(**instancename;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIinstancename\fP
-Defines the instance called \fIinstancename\fP as the new "reference instance" 
-.SH DESCRIPTION
-\fBDEF_PHINS\fP define the new "reference instance", used as starting point
-in the relative placement functions of genlib. It's regarding the \fBabutment
-box\fP of the instance \fIinstancename\fP that the next instance is going to be
-placed, if using the appropriate functions. Notice that the more recently
-placed instance becomes automaticaly the "reference instance", if 
-\fBDEF_PHINS\fP isn't called.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_DEF_PHINS impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to refer to an instance inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"instance instancename doesn't exist in current figure"
-.ft R
-.RS
-The instance \fIinstancename\fP hasn't currently been placed in the figure,
-so it's impossible do to any placement from it. 
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("cell");
-	/\(** Place an instance \(**/
-	GENLIB_PLACE("model","i1", NOSYM,0L,0L);
-	GENLIB_PLACE("model","i2", NOSYM,120L,40L);
-	GENLIB_DEF_PHINS("i1");
-	GENLIB_PLACE_TOP("model2", "i3", NOSYM);
-	GENLIB_DEF_AB(0, 0, 0, 0);
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_PLACE (3),
-.BR GENLIB_PLACE_TOP (3),
-.BR GENLIB_PLACE_RIGHT (3),
-.BR GENLIB_PLACE_LEFT (3),
-.BR GENLIB_PLACE_BOTTOM (3),
-.BR GENLIB_SC_PLACE (3),
-.BR GENLIB_SC_TOP (3),
-.BR GENLIB_SC_RIGHT (3),
-.BR GENLIB_SC_LEFT (3),
-.BR GENLIB_SC_BOTTOM (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_DEF_PHSC.3 b/alliance/share/man/man3/GENLIB_DEF_PHSC.3
deleted file mode 100644
index fdc681ad..00000000
--- a/alliance/share/man/man3/GENLIB_DEF_PHSC.3
+++ /dev/null
@@ -1,78 +0,0 @@
-.\"   $Id: GENLIB_DEF_PHSC.3,v 1.2 2000/09/28 15:25:49 fred Exp $
-.\" @(#)GENLIB_DEF_PHSC.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_DEF_PHSC
-.XE \}
-.TH GENLIB_DEF_PHSC.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_DEF_PHSC \- load a netlist and open a layout model as current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_DEF_PHSC(cellname)
-char \(**cellname;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIcellname\fP
-Name of the netlist figure to be looked for in memory or on disk, for
-futher physical placement.
-.SH DESCRIPTION
-\fBDEF_PHSC\fP defines the current working figure by it's name, 
-the \fIcellname\fP argument, for layout and netlist operations.
-It can be use anywhere in the \fBgenlib\fP 
-program, but must appear at least once at the top of it, since it also 
-initalize the user's preferences through environment variables.
-.br
-\fBDEF_PHSC\fP looks for the netlist figure \fIcellname\fP in memory, and if
-not found, on disk. If it fails, an error occurs and the process terminates.
-.br
-The main issue of this function is to allow the netlist and physical
-descriptions of a circuit in two separate files,
-for standard cell approach. So there is
-no need to recreate the netlist view each time the placement changes.
-.br
-If the physical figure called \fIcellname\fP doesn't exists in memory,
-it is created. 
-If it already exists in memory, it makes it the current working figure. 
-\fBDEF_PHSC\fP doesn't look on disk for the figure \fIcellname\fP, 
-so be careful not to overwrite an existing file while saving later on.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHSC("mycell");
-	/\(** Place an instance \(**/
-	GENLIB_SC_PLACE("instance", NOSYM,0L,0L);
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_PHSC();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_SAVE_PHSC (3),
-.BR GENLIB_SC_PLACE (3),
-.BR GENLIB_SC_TOP (3),
-.BR GENLIB_SC_BOTTOM (3),
-.BR GENLIB_SC_LEFT (3),
-.BR GENLIB_SC_RIGHT (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_ELM.3 b/alliance/share/man/man3/GENLIB_ELM.3
deleted file mode 100644
index d5d0709c..00000000
--- a/alliance/share/man/man3/GENLIB_ELM.3
+++ /dev/null
@@ -1,75 +0,0 @@
-.\"   $Id: GENLIB_ELM.3,v 1.2 2000/09/28 15:25:49 fred Exp $
-.\" @(#)GENLIB_ELM.3 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_ELM
-.XE \}
-.TH GENLIB_ELM.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_ELM \- Creates a single element bus name for netlist
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-char \(**GENLIB_ELM(busname, index);
-char \(**busname;
-long index;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIbusname\fP
-Common signal name for a bus
-.TP 20
-\fIindex\fP
-Index of the demanded signal belonging to the bus
-.SH DESCRIPTION
-\fIELM\fP Creates a single element bus names valid for the genlib netlist
-functions that manipulate the signal, and/or connector, concept.
-They are:
-.RS
-\fBLOINS\fP(3)
-.br
-\fBLOCON\fP(3)
-.RE
-The \fIindex\fP argument gives the index of the name to be created.
-.br
-This function has a constant equivalent, it means that if the \fIindex\fP
-value is known at compilation time, one should better use,
-for readability purposes, the "[n]" construct.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-int b = 0;
-int e = 12;
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_LOFIG("mycell");
-	/\(** define interface  \(**/
-	GENLIB_LOCON(GENLIB_BUS("i", b, e), INPUT, BUS("sig", b, e);
-	GENLIB_LOCON("o[2:0]", OUTPUT, "sigout[4:6]");
-	/\(** Place an instance \(**/
-	GENLIB_LOINS("model","instance", GENLIB_ELM("sig", e/2), "sigout[6]", EOL);
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_LOFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_BUS (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_FLATTEN_ALL_LOINS.3 b/alliance/share/man/man3/GENLIB_FLATTEN_ALL_LOINS.3
deleted file mode 100644
index 1465f4fe..00000000
--- a/alliance/share/man/man3/GENLIB_FLATTEN_ALL_LOINS.3
+++ /dev/null
@@ -1,76 +0,0 @@
-.\"   $Id: GENLIB_FLATTEN_ALL_LOINS.3,v 1.2 2000/09/28 15:25:49 fred Exp $
-.\" @(#)GENLIB_FLATTEN_ALL_LOINS.3 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_FLATTEN_ALL_LOINS
-.XE \}
-.TH GENLIB_FLATTEN_ALL_LOINS.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_FLATTEN_ALL_LOINS \- flatten all instances in the current netlist figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_FLATTEN_ALL_LOINS(concat)
-char concat;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETER
-.TP 20
-\fIconcat\fP
-Indicate whether or not to concatenate instance name to instance' objects name
-.SH DESCRIPTION
-\fBFLATTEN_ALL_LOINS\fP inserts the contents of all the instances of the
-current figure in the current figure.
-All these instances are destroyed during the process, and therefore cannot be
-refered to later in the netlist description.
-.br
-The \fIconcat\fP parameter may take two values:
-.TP
-\fBYES\fP
-to concatenate object name with instance names.
-.TP
-\fBNO\fP 
-to copy object names.
-.LP
-In most case, the \fIconcat\fP value must be \fBYES\fP, in order to warranty
-the unicity of names in the figure.
-It may otherwise fail, because the function would try to add in the current
-figure some object with an already existing name.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_LOFIG("mycell");
-	.
-	.
-	.
-	/\(** Place an instance \(**/
-	GENLIB_LOINS("model","instance", "sig1", "sig2", EOL);
-	/\(** flatten all figure instance \(**/
-	GENLIB_FLATTEN_ALL_LOINS(YES);
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_LOFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_LOINS (3)
-.BR GENLIB_FLATTEN_LOFIG (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_FLATTEN_ALL_PHINS.3 b/alliance/share/man/man3/GENLIB_FLATTEN_ALL_PHINS.3
deleted file mode 100644
index bb7e46fd..00000000
--- a/alliance/share/man/man3/GENLIB_FLATTEN_ALL_PHINS.3
+++ /dev/null
@@ -1,93 +0,0 @@
-.\"   $Id: GENLIB_FLATTEN_ALL_PHINS.3,v 1.2 2000/09/28 15:25:49 fred Exp $
-.\" @(#)GENLIB_FLATTEN_ALL_PHINS.3 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_FLATTEN_ALL_PHINS
-.XE \}
-.TH GENLIB_FLATTEN_ALL_PHINS.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_FLATTEN_ALL_PHINS \- flatten all instances in the current layout figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_FLATTEN_ALL_PHINS(concat, catal)
-char concat, catal;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETER
-.TP 20
-\fIconcat\fP
-Indicate whether or not to concatenate instance name to instance' objects name
-.TP 20
-\fIconcat\fP
-Indicate whether or not to look in the catalog file before flattening a cell
-.SH DESCRIPTION
-\fBFLATTEN_ALL_PHINS\fP inserts the contents of all the instances of the
-current figure in the current figure.
-All these instances are destroyed during the process, and therefore cannot be
-refered to later in the layout description.
-.br
-The \fIconcat\fP parameter may take two values:
-.TP
-\fBYES\fP
-to concatenate object name with instance names.
-.TP
-\fBNO\fP 
-to copy object names.
-.LP
-In most case, the \fIconcat\fP value must be \fBYES\fP, in order to warranty
-the unicity of names in the figure.
-It may otherwise fail, because the function would try to add in the current
-figure some object with an already existing name.
-.br
-The \fIcatal\fP parameter may also take two values:
-.TP
-\fBYES\fP
-to check the catalog file to see if the model of an instance is in it.
-If the model belong to the catalog, then it is \fInot\fR flattened.
-.TP
-\fBNO\fP 
-in this case, no checks are done, and every instance is flattened.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("mycell");
-	.
-	.
-	.
-	/\(** Place an instance \(**/
-	PHINS("model","instance", "sig1", "sig2", EOL);
-	/\(** flatten all figure instance \(**/
-	GENLIB_FLATTEN_ALL_PHINS(YES, YES);
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_PLACE (3),
-.BR GENLIB_PLACE_LEFT (3),
-.BR GENLIB_PLACE_RIGHT (3),
-.BR GENLIB_PLACE_TOP (3),
-.BR GENLIB_PLACE_BOTTOM (3),
-.BR GENLIB_PLACE_ON (3),
-.BR GENLIB_FLATTEN_PHFIG (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_FLATTEN_LOFIG.3 b/alliance/share/man/man3/GENLIB_FLATTEN_LOFIG.3
deleted file mode 100644
index 0e887995..00000000
--- a/alliance/share/man/man3/GENLIB_FLATTEN_LOFIG.3
+++ /dev/null
@@ -1,78 +0,0 @@
-.\"   $Id: GENLIB_FLATTEN_LOFIG.3,v 1.2 2000/09/28 15:25:50 fred Exp $
-.\" @(#)GENLIB_FLATTEN_LOFIG.3 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_FLATTEN_LOFIG
-.XE \}
-.TH GENLIB_FLATTEN_LOFIG.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_FLATTEN_LOFIG \- flatten an instance in the current netlist figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_FLATTEN_LOFIG(insname,concat)
-char \(**insname;
-char concat;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIinsname\fP
-Name of the instance to be flattened
-.TP
-\fIconcat\fP
-Indicate whether or not to concatenate instance name to instance' objects name
-.SH DESCRIPTION
-\fBFLATTEN_LOFIG\fP inserts the contents of an instance, but its connectors,
-in the current figure, and then destroys the instance.
-.br
-The \fIconcat\fP parameter may take two values:
-.TP
-\fBYES\fP
-to concatenate object name with instance names.
-.TP
-\fBNO\fP 
-to copy object names.
-.LP
-In most case, the \fIconcat\fP value must be \fBYES\fP, in order to warranty
-the unicity of names in the figure.
-It may otherwise fail, because the function would try to add in the current
-figure some object with an already existing name.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_LOFIG("mycell");
-	.
-	.
-	.
-	/\(** Place an instance \(**/
-	GENLIB_LOINS("model","instance", "sig1", "sig2", EOL);
-	/\(** flatten an instance \(**/
-	GENLIB_FLATTEN_LOFIG("instance", YES);
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_LOFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_UNFLATTEN_LOFIG (3).
-.BR GENLIB_LOINS (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_FLATTEN_PHFIG.3 b/alliance/share/man/man3/GENLIB_FLATTEN_PHFIG.3
deleted file mode 100644
index 4fbd9446..00000000
--- a/alliance/share/man/man3/GENLIB_FLATTEN_PHFIG.3
+++ /dev/null
@@ -1,77 +0,0 @@
-.\"   $Id: GENLIB_FLATTEN_PHFIG.3,v 1.2 2000/09/28 15:25:50 fred Exp $
-.\" @(#)GENLIB_FLATTEN_PHFIG.3 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_FLATTEN_PHFIG
-.XE \}
-.TH GENLIB_FLATTEN_PHFIG.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_FLATTEN_PHFIG \- flatten an instance in the current layout figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_FLATTEN_PHFIG(insname,concat)
-char \(**insname;
-char concat;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIinsname\fP
-Name of the instance to be flattened
-.TP
-\fIconcat\fP
-Indicate whether or not to concatenate instance name to instance' objects name
-.SH DESCRIPTION
-\fBFLATTEN_PHFIG\fP inserts the contents of an instance, but its connectors,
-in the current figure, and then destroys the instance.
-.br
-The \fIconcat\fP parameter may take two values:
-.TP 20
-\fBYES\fP
-to concatenate object name with instance names.
-.TP
-\fBNO\fP 
-to copy object names.
-.LP
-In most case, the \fIconcat\fP value must be \fBYES\fP, in order to warranty
-the unicity of names in the figure.
-It may otherwise fail, because the function would try to add in the current
-figure some object with an already existing name.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("mycell");
-	.
-	.
-	.
-	/\(** Place an instance \(**/
-	GENLIB_PLACE("model","instance", SYM_X, 0, 0);
-	/\(** flatten an instance \(**/
-	GENLIB_FLATTEN_PHFIG("instance", YES);
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_LOINS (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_GET_CON_X.3 b/alliance/share/man/man3/GENLIB_GET_CON_X.3
deleted file mode 100644
index ec453f2a..00000000
--- a/alliance/share/man/man3/GENLIB_GET_CON_X.3
+++ /dev/null
@@ -1,110 +0,0 @@
-.\"   $Id: GENLIB_GET_CON_X.3,v 1.2 2000/09/28 15:25:50 fred Exp $
-.\" @(#)GENLIB_GET_CON_X.3 2.11 01/92; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_GET_CON_X
-.XE \}
-.TH GENLIB_GET_CON_X.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_GET_CON_X \- retrieve the x coordinate of an instance connector
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-long GENLIB_GET_CON_X(insname, conname, index)
-char \(**insname, \(**conname;
-long index;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIinsname\fP
-Name of the instance in the which the connector is to be searched for
-.TP
-\fIconname\fP
-Name of the connector
-.TP
-\fIindex\fP
-Connector index
-.SH DESCRIPTION
-\fBGET_CON_X\fP looks for 
-the connector, \fIconname\fP, in the instance called \fIinsname\fP.
-Then it computes its absolute coordinates in the figure, and gives back the
-x coordinate.
-.SH RETURN VALUE
-The function returns a long int beeing the x position of the connector
-in the current figure
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_GET_CON_X impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a connector inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphins : instance called \fIinsname\fP does not exist"
-.ft R
-.RS
-No instance called \fIinsname\fP exists in the current figure.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphcon : connectors \fIconname\fP, index \fIindex\fP does not exist"
-.ft R
-.RS
-No connector called \fIconname\fP exists in the model of the instance
-\fIinsname\fP.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-long x, y;
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("cell");
-	GENLIB_PLACE("gaci0_b", "r1", NOSYM, 23L, 54L);
-	/\(** Get a connector \(**/
-	x = GENLIB_GET_CON_X("r1", "a", 1);
-	.
-	.
-	GENLIB_PHVIA(x, y, CONT_VIA);
-	/\(** Save that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHFIG (3),
-.BR GENLIB_SAVE_PHFIG (3),
-.BR GENLIB_PHCON (3),
-.BR GENLIB_PHSEG (3),
-.BR GENLIB_COPY_UP_CON (3),
-.BR GENLIB_COPY_UP_ALL_CON (3),
-.BR GENLIB_GET_CON_Y (3),
-.BR GENLIB_GET_REF_X (3),
-.BR GENLIB_GET_REF_Y (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_GET_CON_Y.3 b/alliance/share/man/man3/GENLIB_GET_CON_Y.3
deleted file mode 100644
index e13921c9..00000000
--- a/alliance/share/man/man3/GENLIB_GET_CON_Y.3
+++ /dev/null
@@ -1,110 +0,0 @@
-.\"   $Id: GENLIB_GET_CON_Y.3,v 1.2 2000/09/28 15:25:50 fred Exp $
-.\" @(#)GENLIB_GET_CON_Y.3 2.11 01/92; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_GET_CON_Y
-.XE \}
-.TH GENLIB_GET_CON_Y.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_GET_CON_Y \- retrieve the x coordinate of an instance connector
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-long GENLIB_GET_CON_Y(insname, conname, index)
-char \(**insname, \(**conname;
-long index;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIinsname\fP
-Name of the instance in the which the connector is to be searched for
-.TP
-\fIconname\fP
-Name of the connector
-.TP
-\fIindex\fP
-Connector index
-.SH DESCRIPTION
-\fBGET_CON_Y\fP looks for 
-the connector, \fIconname\fP, in the instance called \fIinsname\fP.
-Then it computes its absolute coordinates in the figure, and gives back the
-y coordinate.
-.SH RETURN VALUE
-The function returns a long int beeing the y position of the connector
-in the current figure
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_GET_CON_Y impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a connector inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphins : instance called \fIinsname\fP does not exist"
-.ft R
-.RS
-No instance called \fIinsname\fP exists in the current figure.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphcon : connectors \fIconname\fP, index \fIindex\fP does not exist"
-.ft R
-.RS
-No connector called \fIconname\fP exists in the model of the instance
-\fIinsname\fP.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-long x, y;
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("cell");
-	GENLIB_PLACE("gaci0_b", "r1", NOSYM, 23L, 54L);
-	/\(** Get a connector \(**/
-	y = GENLIB_GET_CON_Y("r1", "a", 1);
-	.
-	.
-	GENLIB_PHVIA(x, y, CONT_VIA);
-	/\(** Save that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHFIG (3),
-.BR GENLIB_SAVE_PHFIG (3),
-.BR GENLIB_PHCON (3),
-.BR GENLIB_PHSEG (3),
-.BR GENLIB_COPY_UP_CON (3),
-.BR GENLIB_COPY_UP_ALL_CON (3),
-.BR GENLIB_GET_CON_X (3),
-.BR GENLIB_GET_REF_X (3),
-.BR GENLIB_GET_REF_Y (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_GET_INS_X.3 b/alliance/share/man/man3/GENLIB_GET_INS_X.3
deleted file mode 100644
index 2c2be1ce..00000000
--- a/alliance/share/man/man3/GENLIB_GET_INS_X.3
+++ /dev/null
@@ -1,94 +0,0 @@
-.\"   $Id: GENLIB_GET_INS_X.3,v 1.2 2000/09/28 15:25:50 fred Exp $
-.\" @(#)GENLIB_GET_INS_X.3 2.11 01/92; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_GET_INS_X
-.XE \}
-.TH GENLIB_GET_INS_X.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_GET_INS_X \- retrieve the x coordinate of an instance
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-long GENLIB_GET_INS_X(insname)
-char \(**insname;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETER
-.TP 20
-\fIinsname\fP
-Name of the instance which x coordinate is to be given back
-.SH DESCRIPTION
-\fBGET_INS_X\fP looks for 
-the instance called \fIinsname\fP in the current figure.
-Then it computes its absolute coordinates in the figure, and gives back its
-x coordinate.
-.SH RETURN VALUE
-The function returns a long int beeing the x position of the instance
-in the current figure
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_GET_INS_X impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a connector inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphins : instance called \fIinsname\fP does not exist"
-.ft R
-.RS
-No instance called \fIinsname\fP exists in the current figure.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-long x, y;
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("cell");
-	GENLIB_PLACE("gaci0_b", "r1", NOSYM, 23L, 54L);
-	GENLIB_PLACE_TOP("gaci0_b", "r2", SYM_X);
-	GENLIB_PLACE_RIGHT("gaci0_b", "r3", SYM_Y);
-	/\(** Get a connector \(**/
-	x = GENLIB_GET_INS_X("r3");
-	y = GENLIB_GET_INS_Y("r3");
-	.
-	.
-	/\(** Save that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHFIG (3),
-.BR GENLIB_SAVE_PHFIG (3),
-.BR PHINS (3),
-.BR GENLIB_GET_INS_Y (3),
-.BR GENLIB_GET_CON_X (3),
-.BR GENLIB_GET_CON_Y (3).
-.BR GENLIB_GET_REF_X (3),
-.BR GENLIB_GET_REF_Y (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_GET_INS_Y.3 b/alliance/share/man/man3/GENLIB_GET_INS_Y.3
deleted file mode 100644
index 82e8d0ff..00000000
--- a/alliance/share/man/man3/GENLIB_GET_INS_Y.3
+++ /dev/null
@@ -1,94 +0,0 @@
-.\"   $Id: GENLIB_GET_INS_Y.3,v 1.2 2000/09/28 15:25:50 fred Exp $
-.\" @(#)GENLIB_GET_INS_Y.3 2.11 01/92; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_GET_INS_Y
-.XE \}
-.TH GENLIB_GET_INS_Y.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_GET_INS_Y \- retrieve the y coordinate of an instance
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-long GENLIB_GET_INS_Y(insname)
-char \(**insname;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETER
-.TP 20
-\fIinsname\fP
-Name of the instance which y coordinate is to be given back
-.SH DESCRIPTION
-\fBGET_INS_Y\fP looks for 
-the instance called \fIinsname\fP in the current figure.
-Then it computes its absolute coordinates in the figure, and gives back its
-y coordinate.
-.SH RETURN VALUE
-The function returns a long int beeing the y position of the instance
-in the current figure
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_GET_INS_Y impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a connector inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphins : instance called \fIinsname\fP does not exist"
-.ft R
-.RS
-No instance called \fIinsname\fP exists in the current figure.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-long x, y;
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("cell");
-	GENLIB_PLACE("gaci0_b", "r1", NOSYM, 23L, 54L);
-	GENLIB_PLACE_TOP("gaci0_b", "r2", SYM_Y);
-	GENLIB_PLACE_RIGHT("gaci0_b", "r3", SYM_Y);
-	/\(** Get a connector \(**/
-	x = GENLIB_GET_INS_X("r3");
-	y = GENLIB_GET_INS_Y("r3");
-	.
-	.
-	/\(** Save that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHFIG (3),
-.BR GENLIB_SAVE_PHFIG (3),
-.BR PHINS (3),
-.BR GENLIB_GET_INS_X (3),
-.BR GENLIB_GET_CON_X (3),
-.BR GENLIB_GET_CON_Y (3).
-.BR GENLIB_GET_REF_X (3),
-.BR GENLIB_GET_REF_Y (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_GET_REF_X.3 b/alliance/share/man/man3/GENLIB_GET_REF_X.3
deleted file mode 100644
index a56e7f3a..00000000
--- a/alliance/share/man/man3/GENLIB_GET_REF_X.3
+++ /dev/null
@@ -1,130 +0,0 @@
-.\"   $Id: GENLIB_GET_REF_X.3,v 1.2 2000/09/28 15:25:50 fred Exp $
-.\" @(#)GENLIB_GET_REF_X.3 2.11 01/92; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_GET_REF_X
-.XE \}
-.TH GENLIB_GET_REF_X.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_GET_REF_X \- retrieve the x coordinate of an instance reference
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-long GENLIB_GET_REF_X(insname, refname)
-char \(**insname, \(**refname;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIinsname\fP
-Name of the instance in the which the reference is to be searched for
-.TP
-\fIrefname\fP
-Name of the reference
-SH DESCRIPTION
-\fBGET_REF_X\fP looks for 
-the reference, \fIrefname\fP, in the instance called \fIinsname\fP.
-.SH RETURN VALUE
-The function returns a long int beeing the x position of the reference
-in the current figure
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_GET_REF_X impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a reference inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_GET_REF_X impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a reference inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_GET_REF_X impossible : no abutment box"
-.ft R
-.RS
-The current figure does not have an \fIabutment box\fI. Use \fIDEF_AB\fP(3)
-before this function.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal GENLIB_GET_REF_X : orientation is XX"
-.ft R
-.RS
-The \fIface\fP parameter does not have a legal value, but \fIXX\fP.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphins : instance called \fIinsname\fP does not exist"
-.ft R
-.RS
-No instance called \fIinsname\fP exists in the current figure
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphref : references called \fIrefname\fP does not exist"
-.ft R
-.RS
-No reference called \fIrefname\fP exists in the model of the instance
-\fIinsname\fP.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("cell");
-	GENLIB_PLACE("gaci0_b", "r1", NOSYM, 23L, 54L);
-	/\(** Put a reference \(**/
-	GENLIB_GET_REF_X("r1", "a_0", ALU2, 2, NORTH);
-	/\(** Save that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHFIG (3),
-.BR GENLIB_SAVE_PHFIG (3),
-.BR GENLIB_PHREF (3),
-.BR GENLIB_PHSEG (3),
-.BR GENLIB_COPY_UP_REF (3),
-.BR GENLIB_COPY_UP_ALL_REF (3),
-.BR GENLIB_GET_REF_X (3),
-.BR GENLIB_GET_REF_X (3),
-.BR GENLIB_GET_REF_X (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_GET_REF_Y.3 b/alliance/share/man/man3/GENLIB_GET_REF_Y.3
deleted file mode 100644
index d9149ceb..00000000
--- a/alliance/share/man/man3/GENLIB_GET_REF_Y.3
+++ /dev/null
@@ -1,106 +0,0 @@
-.\"   $Id: GENLIB_GET_REF_Y.3,v 1.2 2000/09/28 15:25:50 fred Exp $
-.\" @(#)GENLIB_GET_REF_Y.3 2.11 01/92; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_GET_REF_Y
-.XE \}
-.TH GENLIB_GET_REF_Y.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_GET_REF_Y \- retrieve the y coordinate of an instance reference
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-long GENLIB_GET_REF_Y(insname, refname)
-char \(**insname, \(**refname;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIinsname\fP
-Name of the instance in the which the reference is to be searched for
-.TP
-\fIrefname\fP
-Name of the reference
-.SH DESCRIPTION
-\fBGET_REF_Y\fP looks for 
-the reference, \fIrefname\fP, in the instance called \fIinsname\fP.
-Then it computes its absolute coordinates in the figure, and gives back the
-y coordinate.
-.SH RETURN VALUE
-The function returns a long int beeing the y position of the reference
-in the current figure
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_GET_REF_Y impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a reference inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphins : instance called \fIinsname\fP does not exist"
-.ft R
-.RS
-No instance called \fIinsname\fP exists in the current figure.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphref : references called \fIrefname\fP does not exist"
-.ft R
-.RS
-No reference called \fIrefname\fP exists in the model of the instance
-\fIinsname\fP.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-long x, y;
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("cell");
-	GENLIB_PLACE("gaci0_b", "r1", NOSYM, 23L, 54L);
-	/\(** Get a reference \(**/
-	y = GENLIB_GET_REF_Y("r1", "a_0");
-	.
-	.
-	GENLIB_PHVIA(x, y, CONT_VIA);
-	/\(** Save that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHFIG (3),
-.BR GENLIB_SAVE_PHFIG (3),
-.BR GENLIB_PHREF (3),
-.BR GENLIB_PHSEG (3),
-.BR GENLIB_COPY_UP_REF (3),
-.BR GENLIB_COPY_UP_ALL_REF (3),
-.BR GENLIB_GET_CON_X (3),
-.BR GENLIB_GET_CON_Y (3),
-.BR GENLIB_GET_REF_X (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_HEIGHT.3 b/alliance/share/man/man3/GENLIB_HEIGHT.3
deleted file mode 100644
index 528f099c..00000000
--- a/alliance/share/man/man3/GENLIB_HEIGHT.3
+++ /dev/null
@@ -1,59 +0,0 @@
-.\"   $Id: GENLIB_HEIGHT.3,v 1.2 2000/09/28 15:25:51 fred Exp $
-.\" @(#)GENLIB_HEIGHT.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_HEIGHT
-.XE \}
-.TH GENLIB_HEIGHT.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_HEIGHT \- compute the height of a model
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-long GENLIB_HEIGHT(cellname)
-char \(**cellname;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIcellname\fP
-Name of the cell which height is needed
-.SH DESCRIPTION
-\fBHEIGHT\fP looks for the figure called \fIcellname\fP on memory, and then on
-disk. When found, the figure \fIabutment box\fP height is calculated, and
-returned.
-.SH RETURN VALUE
-\fIHEIGHT\fP returns a long int beeing the cell \fIabutment box\fP height.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-long cellHeight;
-main()
-{
-	cellHeight = GENLIB_HEIGHT("mycell");
-	GENLIB_DEF_PHFIG("grumf_z");
-	GENLIB_PLACE("na2_y","ins1", NOSYM, 3 * cellHeight, 0L);
-	/\(** Save all that on disk \(**/
-	GENLIB_DEF_AB(0L, 0L, 0L, 0L);
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_WIDTH (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_LOAD_LOFIG.3 b/alliance/share/man/man3/GENLIB_LOAD_LOFIG.3
deleted file mode 100644
index bc6c9311..00000000
--- a/alliance/share/man/man3/GENLIB_LOAD_LOFIG.3
+++ /dev/null
@@ -1,59 +0,0 @@
-.\"   $Id: GENLIB_LOAD_LOFIG.3,v 1.2 2000/09/28 15:25:51 fred Exp $
-.\" @(#)GENLIB_LOAD_LOFIG.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_LOAD_LOFIG
-.XE \}
-.TH GENLIB_LOAD_LOFIG.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_LOAD_LOFIG \- loads a netlist form disk and opens it as current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_LOAD_LOFIG(cellname)
-char \(**cellname;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIcellname\fP
-Name of the cell which all futher calls to genlib logical functions will
-work on 
-.SH DESCRIPTION
-\fBLOAD_LOFIG\fP loads a netlist from disk and defines it as current working
-structural figure. 
-This overrides the working figure initialized by \fBDEF_LOFIG\fP(3), if any.
-So the next call to \fBSAVE_LOFIG\fP will save the cell called \fIcellname\fP.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Loads the figure to work on  \(**/
-	GENLIB_LOAD_LOFIG("cell");
-	/\(** Add an instance in cell \(**/
-	GENLIB_LOINS("model","instance", "sig1", "sig2", "sig3", "vdd", "vss", EOL);
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_LOFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_LOFIG (3).
-.BR GENLIB_SAVE_LOFIG (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_LOAD_PHFIG.3 b/alliance/share/man/man3/GENLIB_LOAD_PHFIG.3
deleted file mode 100644
index b7bda28d..00000000
--- a/alliance/share/man/man3/GENLIB_LOAD_PHFIG.3
+++ /dev/null
@@ -1,59 +0,0 @@
-.\"   $Id: GENLIB_LOAD_PHFIG.3,v 1.2 2000/09/28 15:25:51 fred Exp $
-.\" @(#)GENLIB_LOAD_PHFIG.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_LOAD_PHFIG
-.XE \}
-.TH GENLIB_LOAD_PHFIG.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-\fBPHAD_PHFIG\fP \- loads a layout form disk and opens it as current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_LOAD_PHFIG(cellname)
-char \(**cellname;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIcellname\fP
-Name of the cell which all futher calls to genlib layout functions will
-work on 
-.SH DESCRIPTION
-\fBPHAD_PHFIG\fP loads a physical view from disk and defines it as current
-working layout figure. 
-This overrides the working figure initialized by \fBDEF_PHFIG\fP(3), if any.
-So the next call to \fBSAVE_PHFIG\fP will save the cell called \fIcellname\fP.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Loads the figure to work on  \(**/
-	GENLIB_LOAD_PHFIG("cell");
-	/\(** Add an instance in cell \(**/
-	GENLIB_PLACE("model","instance", NOSYM, 200, 600);
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHFIG (3).
-.BR GENLIB_SAVE_PHFIG (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_LOCON.3 b/alliance/share/man/man3/GENLIB_LOCON.3
deleted file mode 100644
index 2fd1b620..00000000
--- a/alliance/share/man/man3/GENLIB_LOCON.3
+++ /dev/null
@@ -1,146 +0,0 @@
-.\"   $Id: GENLIB_LOCON.3,v 1.3 2000/11/06 12:08:43 francois Exp $
-.\" @(#)GENLIB_LOCON.3 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_LOCON
-.XE \}
-.TH GENLIB_LOCON.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_LOCON \- adds a logical connector to the current netlist figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_LOCON(connector, direction, signal);
-char \(**connector, \(**signal;
-char direction;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIconnector\fP
-Name of the connector to be created in the current figure
-.TP
-\fIdirection\fP
-Indicates the connector behaviour regarding signals propagation
-.TP
-\fIsignal\fP
-Name of the signal on which the connector is linked
-.SH DESCRIPTION
-\fBLOCON\fP add a logical connector to the interface of the actual
-working figure. This connector is logicaly linked to the signal \fIsignal\fP.
-The \fIdirection\fP attribut may take the following values:
-.TP
-\fBIN\fP
-as input.
-.TP
-\fBOUT\fP 
-as output.
-.TP
-\fBINOUT\fP 
-as input/output, like supplies or clock for example.
-.TP
-\fBUNKNOWN\fP 
-if one doesn't know what it is.
-.TP
-\fBTRISTATE\fP 
-as high impedance output.
-.TP
-\fBTRANSV\fP 
-as transciever. That means \fBTRISTATE\fP input plus output.
-.SH ERROR
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_LOCON impossible : missing GENLIB_DEF_LOFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_LOFIG\fP. So it isn't
-possible to add anything. you must call \fBDEF_LOFIG\fP before any other
-netlist call.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_LOCON : Bad signal or connector bus name"
-.ft R
-.RS
-A signal or connector, described under a bus form, has an illegal syntax.
-.RE
-.TP
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_LOCON : All LOCON should be defined befor any GENLIB_LOINS"
-.ft R
-.RS
-A connector is added after instances. This is a methodological error.
-Only move your \fBLOCON\fP before the first \fBLOINS\fP in your code.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_LOCON : different number of signals and connectors"
-.ft R
-.RS
-A bussed form of signal and connector has been used, but the width of
-the busses are not equal. This is an obvious error, check it.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Illegal addlocon. Connector connector already exist in figure figname"
-.ft R
-.RS
-A connector name must be unique in a given figure at a given hierachy level.
-.RE
-.SH DIAGNOSTICS
-Due to the \fBvti\fP file format, the direction of connectors is lost if
-one uses it as starting point of a netlist desciption. All the connectors
-have then the \fBUNKNOWN\fP direction.
-.br
-Alliance and edif file format know only about \fBIN\fP, \fBOUT\fP, and
-\fBUNKNOWN\fP.
-Only vhdl format fully supports the whole thing.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_LOFIG("mycell");
-	/\(** define interface  \(**/
-	GENLIB_LOCON("i", INPUT, "sig1");
-	GENLIB_LOCON("o", OUTPUT, "sig2");
-	/\(** Place an instance \(**/
-	GENLIB_LOINS("model","instance", "sig1", "sig2", EOL);
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_LOFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_BUS (3),
-.BR GENLIB_ELM (3),
-.BR GENLIB_LOSIG (3),
-.BR GENLIB_LOINS (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_LOINS.3 b/alliance/share/man/man3/GENLIB_LOINS.3
deleted file mode 100644
index 29c1cd51..00000000
--- a/alliance/share/man/man3/GENLIB_LOINS.3
+++ /dev/null
@@ -1,152 +0,0 @@
-.\"   $Id: GENLIB_LOINS.3,v 1.2 2000/09/28 15:25:51 fred Exp $
-.\" @(#)GENLIB_LOINS.3 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_LOINS
-.XE \}
-.TH GENLIB_LOINS.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_LOINS \- add a logical instance to the current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_LOINS(model, instance, sig1, sig2, ..., sign, EOL);
-char \(**model, \(**instance;
-char \(**sig1, \(**sig2, ..., \(**sign;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fImodel\fP
-Name of the model to be logically instanciated
-.TP
-\fIinstance\fP
-Name to be given to the new instance
-.TP
-\fIsig1, sig2, ..., sign\fP
-List of signals to be linked to the implicit connector list of the instance
-.SH DESCRIPTION
-\fBLOINS\fP add a logical instance in the actual working figure.
-\fBLOINS\fP uses environment variables to
-choose the file format and the path to the file.
-.br
-\fBMBK_IN_LO\fP set up the input file format, the valid ones beeing :
-.RS
-.br
-\fBhns
-.br
-fne
-.br
-al
-.br
-alx\fP
-.RE
-\fBMBK_WORK_LIB\fP set up the output file path. Any valid unix path is
-ok.
-\fBLOINS\fP look in memory and then, if not found, on disk for the
-figure \fImodelname\fP. This is due to the need to ensure consistency
-between the model and its ascociated instances.
-.br
-The instance is added with the name \fIinstance\fP, and each of the
-signals are connected to an instance connector. The connectors are 
-implicitly matched from the order of the signal on the list.
-This order is the one given
-in the netlist file, \fBhns\fP or \fBal\fP, or in the \fIsclib\fP
-documentation, for standard cell circuits.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_LOINS impossible : missing GENLIB_DEF_LOFIG"
-.ft R
-.br
-.RS
-No figure has been yet specified by a call to \fBDEF_LOFIG\fP. So it isn't
-possible to add anything. you must call \fBDEF_LOFIG\fP before any other
-netlist call.
-.RE
-.br
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_LOINS : Bad signal bus name"
-.ft R
-.br
-.RS
-A signal, described under a bus form, has an illegal syntax.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Illegal addloins. Instance insname already exist in figure figname"
-.ft R
-.br
-.RS
-An instance name must be unique in a given figure at a given hierachy level.
-.RE
-.br
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Illegal addloins. Instance model is the figure figname itself"
-.ft R
-.br
-.RS
-A figure cannot be included in itself. Be careful, the check is only
-made at current hierarchy level.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.br
-"Illegal addloins. Connector number discrepancy between
-figure modelname and instance insname in figure figname"
-.ft R
-.br
-.RS
-The number of connector in the model is not equal to the number of signals
-describing the connectivity during the \fBLOINS\fP call.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_LOFIG("mycell");
-	/\(** define interface  \(**/
-	GENLIB_LOCON("i", INPUT, "sig1");
-	GENLIB_LOCON("o", OUTPUT, "sig2");
-	/\(** Place an instance \(**/
-	GENLIB_LOINS("model","instance", "sig1", "sig2", EOL);
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_LOFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_LOFIG (3),
-.BR MBK_IN_LO (1),
-.BR MBK_CATA_LIB (1),
-.BR MBK_WORK_LIB (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_LOINSE.3 b/alliance/share/man/man3/GENLIB_LOINSE.3
deleted file mode 100644
index f6019b70..00000000
--- a/alliance/share/man/man3/GENLIB_LOINSE.3
+++ /dev/null
@@ -1,159 +0,0 @@
-.\"   $Id: GENLIB_LOINSE.3,v 1.2 2000/09/28 15:25:51 fred Exp $
-.\" @(#)GENLIB_LOINSE.3 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_LOINSE
-.XE \}
-.TH GENLIB_LOINSE.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_LOINSE \- add a logical instance to the current figure, with explicit connections
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_LOINSE(model, instance, couple1, couple2, ..., couplen, EOL);
-char \(**model, \(**instance;
-char \(**couple1, \(**couple2, ..., \(**couplen;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fImodel\fP
-Name of the model to be logically instanciated
-.TP
-\fIinstance\fP
-Name to be given to the new instance
-.TP
-\fIcouple1, couple2, ..., couplen\fP
-Explicit list of connections between connectors and signals.
-.SH DESCRIPTION
-\fBLOINSE\fP add a logical instance in the actual working figure.
-\fBLOINSE\fP uses environment variables to
-choose the file format and the path to the file.
-.br
-\fBMBK_IN_LO\fP set up the input file format, the valid ones beeing :
-.RS
-.br
-\fBhns
-.br
-fne
-.br
-al
-.br
-alx\fP
-.RE
-\fBMBK_WORK_LIB\fP set up the output file path. Any valid unix path is
-ok.
-\fBLOINSE\fP look in memory and then, if not found, on disk for the
-figure \fImodelname\fP. This is due to the need to ensure consistency
-between the model and its ascociated instances.
-.br
-The instance is added with the name \fIinstance\fP, and each of the
-signals are connected to an instance connector.
-The connector signal link is explicit, and described in the \fBcouple\fRs
-arguments.
-The \fBcouple\fRs arguments are supposed to have the form:
-.nf
-\fBconector => signal\fP
-.br
-or
-\fBconector[a:b] => signal[n:m]\fP
-where \fIa - b\fP equals, in absolute value, \fIn - m\fR.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_LOINSE impossible : missing GENLIB_DEF_LOFIG"
-.ft R
-.br
-.RS
-No figure has been yet specified by a call to \fBDEF_LOFIG\fP. So it isn't
-possible to add anything. you must call \fBDEF_LOFIG\fP before any other
-netlist call.
-.RE
-.br
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_LOINSE : Bad signal bus name"
-.ft R
-.br
-.RS
-A signal, described under a bus form, has an illegal syntax.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Illegal addloins. Instance insname already exist in figure figname"
-.ft R
-.br
-.RS
-An instance name must be unique in a given figure at a given hierachy level.
-.RE
-.br
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Illegal addloins. Instance model is the figure figname itself"
-.ft R
-.br
-.RS
-A figure cannot be included in itself. Be careful, the check is only
-made at current hierarchy level.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.br
-"Illegal addloins. Connector number discrepancy between
-figure modelname and instance insname in figure figname"
-.ft R
-.br
-.RS
-The number of connector in the model is not equal to the number of signals
-describing the connectivity during the \fBLOINSE\fP call.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_LOFIG("mycell");
-	/\(** define interface  \(**/
-	GENLIB_LOCON("i", INPUT, "sig1");
-	GENLIB_LOCON("o", OUTPUT, "sig2");
-	/\(** Place an instance \(**/
-	GENLIB_LOINSE("model","instance", "con1 => sig1", "con2 => sig2", 0L);
-	GENLIB_LOINSE("stuff","shirt", "i[31:0] => out[32:63]", "j[2] => sig2", 0L);
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_LOFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_LOFIG (3),
-.BR GENLIB_LOINS (3),
-.BR MBK_IN_LO (1),
-.BR MBK_CATA_LIB (1),
-.BR MBK_WORK_LIB (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_LOSIG.3 b/alliance/share/man/man3/GENLIB_LOSIG.3
deleted file mode 100644
index 977062fa..00000000
--- a/alliance/share/man/man3/GENLIB_LOSIG.3
+++ /dev/null
@@ -1,79 +0,0 @@
-.\"   $Id: GENLIB_LOSIG.3,v 1.2 2000/09/28 15:25:51 fred Exp $
-.\" @(#)GENLIB_LOSIG.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_LOSIG
-.XE \}
-.TH GENLIB_LOSIG.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_LOSIG \- declare an internal logical signal, or a vector of internal
-logical signals
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_LOSIG(name)
-char \(**name;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIname\fP
-Name of a signal to be declared
-.SH DESCRIPTION
-\fBLOSIG\fP creates the internal signal, or the set of internal signals
-coresponding to a vector description, represented by \fIname\fP.
-See \fBBUS(3)\fP and \fBELM(3)\fP for more details on vectors.
-.br
-The need for declaring signal is mostly felt when one wants to create a
-consistent vector declaration, for file formats that do not allow partial or
-multiple declarations, like \fIvhdl\fP.
-This way, a user can create a vector and access its member the way he wants,
-but still having an internal consistent form.
-.TP 20
-Warning
-If a signal is declared with \fBLOSIG\fP, but not used, the resulting file
-will have an internal node floating.
-This is not an error from a genlib point of view, so the user must be aware
-of it.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_LOFIG("cell");
-	/\(** Define interface \(**
-	GENLIB_LOCON(...
-	/\(** declare buses \(**/
-	GENLIB_LOSIG("grum[23:0]");
-	GENLIB_LOSIG("iconection[0:7]");
-	/\(** Place an instance \(**/
-	GENLIB_LOINS("no2_y" ,"no3" ,"grum[12]" ,"a9_s" ,"new_no3_s" ,"vdd" ,"vss" ,0);
-	GENLIB_LOINS("no2_y" ,"no4" ,"a12_s" ,"grum[6]" ,"no4_s" ,"vdd" ,"vss" ,0);
-	GENLIB_LOINS("a2_y" ,"a22" ,"no3_s" ,"grum[15]" ,"a22_s" ,"vdd" ,"vss" ,0);
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_LOFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_LOINS (3),
-.BR GENLIB_LOCON (3),
-.BR GENLIB_BUS (3),
-.BR GENLIB_ELM (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_LOSIGMERGE.3 b/alliance/share/man/man3/GENLIB_LOSIGMERGE.3
deleted file mode 100644
index c6be4091..00000000
--- a/alliance/share/man/man3/GENLIB_LOSIGMERGE.3
+++ /dev/null
@@ -1,95 +0,0 @@
-.\"   $Id: GENLIB_LOSIGMERGE.3,v 1.2 2000/09/28 15:25:51 fred Exp $
-.\" @(#)GENLIB_LOSIGMERGE.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_LOSIGMERGE
-.XE \}
-.TH GENLIB_LOSIGMERGE.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_LOSIGMERGE \- merge two logical signals
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_LOSIGMERGE(signal1, signal2)
-char \(**signal1, \(**signal2;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIsignal1\fP
-Name of a signal to be merged
-.TP 20
-\fIsignal2\fP
-Name of a signal to be merged
-.SH DESCRIPTION
-\fBLOSIGMERGE\fP merges the two signals, \fIsignal1\fP and \fIsignal2\fP.
-This function can be used anywhere in the \fBgenlib\fP program, but its
-resultings actions must be known by the user.
-.TP 10
-1)
-If \fIsignal1\fP and \fIsignal2\fP have not been used yet, then the
-corresponding signal can be later accessed through any of these aliases.
-.TP 10
-2)
-If one of \fIsignal1\fP or \fIsignal2\fP has not been used yet, then all
-further reference to the not defined name will be made on the same signal than
-the defined signal.
-.TP 10
-3)
-If both signals exist, then they are merged, and both can be used for reference
-to the same signal later on.
-.LP
-Since most of the file formats do not allow multiple name for a
-single signal, the choice is made to keep for disk usage the name that appears
-in the cell interface, if any.
-Otherwise, the choice is randomly made by \fBLOSIGMERGE\fP.
-.TP 10
-Warning
-This function allows the user to internally connect two external connectors.
-This is \fInot\fP a valid disk representation for netlist generated by
-\fBgenlib\fP.
-The \fBSAVE_LOFIG\fP function will exit if encountering such a situation.
-.br
-In order to avoid it, either take care not to link such signals, or build
-all your hierarchy in memory, make sure your block does not have such signals,
-and call \fPFLATTEN_LOFIG\fP(3) just before saving.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_LOFIG("cell");
-	/\(** Define interface \(**
-	GENLIB_LOCON(...
-	/\(** Place an instance \(**/
-	GENLIB_LOINS("no2_y" ,"no3" ,"a8_s" ,"a9_s" ,"new_no3_s" ,"vdd" ,"vss" ,0);
-	GENLIB_LOINS("no2_y" ,"no4" ,"a12_s" ,"a15_s" ,"no4_s" ,"vdd" ,"vss" ,0);
-	GENLIB_LOINS("a2_y" ,"a22" ,"no3_s" ,"no4_s" ,"a22_s" ,"vdd" ,"vss" ,0);
-	GENLIB_LOSIGMERGE("new_no3_s", "no3_s");
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_LOFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_LOINS (3),
-.BR GENLIB_LOCON (3),
-.BR GENLIB_FLATTEN_LOFIG (3),
-.BR GENLIB_SAVE_PHFIG (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_LOTRS.3 b/alliance/share/man/man3/GENLIB_LOTRS.3
deleted file mode 100644
index f477f0d0..00000000
--- a/alliance/share/man/man3/GENLIB_LOTRS.3
+++ /dev/null
@@ -1,92 +0,0 @@
-.\"   $Id: GENLIB_LOTRS.3,v 1.2 2000/09/28 15:25:52 fred Exp $
-.\" @(#)GENLIB_LOTRS.3 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_LOTRS
-.XE \}
-.TH GENLIB_LOTRS.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_LOTRS \- adds a logical transistor to the current netlist figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_LOTRS(type,width,length,grid,source,drain)
-char type;
-long width, length;
-char \(**grid, \(**source, \(**drain;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fItype\fP
-Type of the transistor to be created in the current figure
-.TP
-\fIwidth, length\fP
-Size of the transistor
-.TP
-\fIgrid, source, drain\fP
-Name of the signals on which the given transitor connector are to be linked
-.SH DESCRIPTION
-\fBLOTRS\fP add a logical transistor to the current
-working figure. This transitor has each of its pin logicaly linked to the signal
-adequat signal given as parameter.
-The \fItype\fP attribut may take the following values:
-.TP
-\fBTRANSN\fP
-for a N type mos transistor.
-.TP
-\fBTRANSP\fP 
-for a P type mos transistor.
-.SH ERROR
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_LOTRS impossible : missing GENLIB_DEF_LOFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_LOFIG\fP. So it isn't
-possible to add anything. you must call \fBDEF_LOFIG\fP before any other
-netlist call.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on, an inverter  \(**/
-	GENLIB_DEF_LOFIG("n1");
-	/\(** define interface  \(**/
-	GENLIB_LOCON("i", IN, "input");
-	GENLIB_LOCON("f", OUT, "output");
-	GENLIB_LOCON("vdd", IN, "vdd");
-	GENLIB_LOCON("vss", IN, "vss");
-	/\(** Place transistors \(**/
-	GENLIB_LOTRS(TRANSP, 5, 4, "input", "vdd", "output");
-	GENLIB_LOTRS(TRANSN, 2, 4, "input", "vss", "output");
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_LOFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_BUS (3),
-.BR GENLIB_ELM (3),
-.BR GENLIB_LOINS (3),
-.BR GENLIB_LOCON (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_OUTLINE.3 b/alliance/share/man/man3/GENLIB_OUTLINE.3
deleted file mode 100644
index 964fcbf8..00000000
--- a/alliance/share/man/man3/GENLIB_OUTLINE.3
+++ /dev/null
@@ -1,56 +0,0 @@
-.\"   $Id: GENLIB_OUTLINE.3,v 1.2 2000/09/28 15:25:52 fred Exp $
-.\" @(#)GENLIB_OUTLINE.3 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_OUTLINE
-.XE \}
-.TH GENLIB_OUTLINE.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_OUTLINE \- build an outline from the current layout cell
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_OUTLINE();
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH DESCRIPTION
-\fBOUTLINE\fP build a black box from a layout.
-After a call to \fBOUTLINE\fP, the figure has only its abutment box,
-its connectors, references and feed through.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("cell");
-	/\(** Place an instance \(**/
-	GENLIB_PLACE("model","i1", NOSYM,0L,0L);
-	GENLIB_PLACE("model","i2", NOSYM,120L,40L);
-	GENLIB_DEF_PHINS("i1");
-	GENLIB_PLACE_TOP("model2", "i3", NOSYM);
-	/\(** define the new abutment box as the standard envelop \(**/
-	GENLIB_DEF_AB(0, 0, 0, 0);
-	GENLIB_OUTLINE();
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_PHCON.3 b/alliance/share/man/man3/GENLIB_PHCON.3
deleted file mode 100644
index 093a5efd..00000000
--- a/alliance/share/man/man3/GENLIB_PHCON.3
+++ /dev/null
@@ -1,174 +0,0 @@
-.\"   $Id: GENLIB_PHCON.3,v 1.2 2000/09/28 15:25:52 fred Exp $
-.\" @(#)GENLIB_PHCON.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_PHCON
-.XE \}
-.TH GENLIB_PHCON.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_PHCON \- place a physical connector in the current figure at absolute coordinates
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_PHCON(layer, width, name, orient, x, y)
-char layer;
-long width;
-char \(**name, orient;
-long x, y;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIlayer\fP
-Layout layer of the connector
-.TP
-\fIwidth\fP
-Width of the connector
-.TP
-\fIname\fP
-Name to be given to the connector
-.TP
-\fIorient\fP
-Face of the cell on witch the connector belongs
-.TP
-\fIx, y\fP
-Absolute coordinates of the connector
-.SH DESCRIPTION
-\fBPHCON\fP adds a connector in the current layout cell, at the specified
-coordinates, with the given attributs.
-The \fIlayer\fP argument can take the following legal values:
-.RS
-.TP
-\fBNWELL\fP 
-.TP
-\fBPWELL\fP 
-.TP
-\fBNTIE\fP 
-.TP
-\fBPTIE\fP 
-.TP
-\fBNDIF\fP 
-.TP
-\fBPDIF\fP 
-.TP
-\fBNTRANS\fP 
-.TP
-\fBPTRANS\fP 
-.TP
-\fBPOLY\fP 
-.TP
-\fBALU1\fP 
-.TP
-\fBALU2\fP 
-.TP
-\fBALU3\fP 
-.TP
-\fBTPOLY\fP 
-.TP
-\fBTALU1\fP 
-.TP
-\fBTALU2\fP 
-.TP
-\fBTALU3\fP 
-.RE
-.LP
-The name argument is not enough of an information to non ambigiously identify
-a connector.
-In order to be able to do so, an \fIindex\fP is computed for each connector
-that has an already existing name, following a topological order.
-Each time a connector is created, the \fIindex\fP is updated, regarding the
-name of the connector.
-Since someone writting a tiler needs to know exactly what connector to access,
-the indexation algorithm must be known by the user.
-.TP 20
-Connectors with a unique name:
-Such connectors have the index \fB0\fP
-.TP 20
-Connectors with a name apearing many times:
-The indexes are computed from left to right, and then from bottom to top,
-starting at \fB0\fP. 
-If two connectors are on the same location, with the same name, then the
-\fIlayer\fP decides which one is has the greater number, from lower level,
-\fBNWELL\fP to upper level, \fBALU3\fP.
-.LP
-The \fIorient\fP paramater may take the following values:
-.TP 20
-\fBNORTH\fP
-for a connector placed on the top of the cell.
-.TP
-\fBSOUTH\fP
-for a connector placed on the bottom of the cell.
-.TP
-\fBEAST\fP
-for a connector placed on the right side of the cell.
-.TP
-\fBWEST\fP
-for a connector placed on the left side of the cell.
-.TP
-Remark:
-Connectors placed on corners of leaf cells are given the \fBEAST\fP orientation
-if on top/right or bottom/right corner, and \fBWEST\fP if top/left or
-bottom/left.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_PHCON impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a connector inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal addphcon : orientation is XX in \fIname\fP"
-.ft R
-.RS
-The \fIorient\fP parameter does not have a legal value, but \fIXX\fP.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("cell");
-	.
-	.
-	.
-	GENLIB_DEF_AB(0L, 0L, 0L, 0L);
-	/\(** Put a connector \(**/
-	GENLIB_PHCON(ALU1, 1, "cin", SOUTH, 12L, 0L);
-	/\(** Save that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHFIG (3),
-.BR GENLIB_SAVE_PHFIG (3),
-.BR GENLIB_COPY_UP_ALL_CON (3),
-.BR GENLIB_COPY_UP_CON (3),
-.BR GENLIB_COPY_UP_CON_FACE (3),
-.BR GENLIB_THRU_CON_H (3),
-.BR GENLIB_THRU_CON_V (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_PHREF.3 b/alliance/share/man/man3/GENLIB_PHREF.3
deleted file mode 100644
index ac764378..00000000
--- a/alliance/share/man/man3/GENLIB_PHREF.3
+++ /dev/null
@@ -1,96 +0,0 @@
-.\"   $Id: GENLIB_PHREF.3,v 1.2 2000/09/28 15:25:52 fred Exp $
-.\" @(#)GENLIB_PHREF.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_PHREF
-.XE \}
-.TH GENLIB_PHREF.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_PHREF \- place a physical reference in the current figure at absolute
-coordinates
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_PHREF(type, name, x, y)
-char \(**type, \(**name;
-long x, y;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fItype\fP
-Type of the reference to be added
-.TP
-\fIname\fP
-Name of the reference
-.TP
-\fIx, y\fP
-Absolute coordinates of the reference
-.SH DESCRIPTION
-\fBPHREF\fP adds a reference in the current layout cell, at the specified
-coordinates.
-A reference is an object that allows to symbolicaly name a point for
-futur use by the designer.
-They have been mainly used in the past to \fIprogram\fP decoders, in order
-to obtain many cells from a unique cell.
-.LP
-The \fItype\fP argument may take the two following legal values:
-.TP 20
-\fBref_con\fP 
-for virtual connectors, see \fBdpr\fP(1) for details.
-.TP
-\fBref_ref\fP 
-for any other need from the designer.
-.LP
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_PHREF impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a reference inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("cell");
-	.
-	/\(** Put a reference \(**/
-	GENLIB_PHREF("ref_con", "in_a[0]", 102L, 10L);
-	.
-	.
-	GENLIB_DEF_AB(0L, 0L, 0L, 0L);
-	/\(** Save that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHFIG (3),
-.BR GENLIB_SAVE_PHFIG (3),
-.BR GENLIB_PLACE_CON_REF (3),
-.BR GENLIB_PLACE_SEG_REF (3),
-.BR GENLIB_PLACE_VIA_REF (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_PHSEG.3 b/alliance/share/man/man3/GENLIB_PHSEG.3
deleted file mode 100644
index 7dae97d8..00000000
--- a/alliance/share/man/man3/GENLIB_PHSEG.3
+++ /dev/null
@@ -1,137 +0,0 @@
-.\"   $Id: GENLIB_PHSEG.3,v 1.2 2000/09/28 15:25:52 fred Exp $
-.\" @(#)GENLIB_PHSEG.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_PHSEG
-.XE \}
-.TH GENLIB_PHSEG.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_PHSEG \- place a physical segment in the current figure at absolute coordinates
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_PHSEG(layer, width, name, x1, y1, x2, y2)
-char layer;
-long width;
-char \(**name;
-long x1, y1, x2, y2;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIlayer\fP
-Layout layer of the segment
-.TP
-\fIwidth\fP
-Width of the segment
-.TP
-\fIname\fP
-Name to be given to the segment
-.TP
-\fIx1, y1, x2, y2\fP
-Coordinates of the segment's end points in the current figure
-.SH DESCRIPTION
-\fBPHSEG\fP adds a segment in the current layout cell, at the specified
-coordinates, with the given attributs.
-The \fIlayer\fP argument can take the following legal values :
-.RS
-.TP
-\fBNWELL\fP 
-.TP
-\fBPWELL\fP 
-.TP
-\fBNTIE\fP 
-.TP
-\fBPTIE\fP 
-.TP
-\fBNDIF\fP 
-.TP
-\fBPDIF\fP 
-.TP
-\fBNTRANS\fP 
-.TP
-\fBPTRANS\fP 
-.TP
-\fBPOLY\fP 
-.TP
-\fBALU1\fP 
-.TP
-\fBALU2\fP 
-.TP
-\fBALU3\fP 
-.TP
-\fBTPOLY\fP 
-.TP
-\fBTALU1\fP 
-.TP
-\fBTALU2\fP 
-.TP
-\fBTALU3\fP 
-.RE
-.LP
-The name argument needs not to be specified, since one usually doesn't need to
-give a segment a name. To do so, just type "" as name.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_PHSEG impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place an instance inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal addphseg : x1, y1, x2, y2"
-.ft R
-.RS
-A symbolic segment must be either vertical or horizontal, so either
-\fIx1 = x2\fP, or \fIy1 = y2\fP.
-.RE
-.br
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("cell");
-	/\(** Put a segment \(**/
-	GENLIB_PHSEG(ALU1, 1, "", 0L, 0L, 12L, 0L);
-	/\(** Save that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHFIG (3),
-.BR GENLIB_SAVE_PHFIG (3),
-.BR GENLIB_COPY_UP_SEG (3),
-.BR GENLIB_THRU_H (3),
-.BR GENLIB_THRU_CON_H (3),
-.BR GENLIB_THRU_V (3),
-.BR GENLIB_THRU_CON_V (3),
-.BR GENLIB_WIRE1 (3),
-.BR GENLIB_WIRE2 (3),
-.BR GENLIB_WIRE3 (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_PHVIA.3 b/alliance/share/man/man3/GENLIB_PHVIA.3
deleted file mode 100644
index 943ded0e..00000000
--- a/alliance/share/man/man3/GENLIB_PHVIA.3
+++ /dev/null
@@ -1,114 +0,0 @@
-.\"   $Id: GENLIB_PHVIA.3,v 1.2 2000/09/28 15:25:52 fred Exp $
-.\" @(#)GENLIB_PHVIA.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_PHVIA
-.XE \}
-.TH GENLIB_PHVIA.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_PHVIA \- place a physical via in the current figure at absolute coordinates
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_PHVIA(type, x, y)
-char type;
-long x, y;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fItype\fP
-Type of the contact to be made
-.TP
-\fIx, y\fP
-Absolute coordinates of the via
-.SH DESCRIPTION
-\fBPHVIA\fP adds a via in the current layout cell, at the specified
-coordinates.
-The \fItype\fP argument may take the following legal values:
-.TP 20
-\fBCONT_POLY\fP 
-links \fBPOLY\fP and \fBALU1\fP
-.TP
-\fBCONT_DIF_N\fP 
-links \fBNDIF\fP and \fBALU1\fP
-.TP
-\fBCONT_DIF_P\fP 
-links \fBPDIF\fP and \fBALU1\fP
-.TP
-\fBCONT_BODY_N\fP 
-links \fBNTIE\fP and \fBALU1\fP
-.TP
-\fBCONT_BODY_P\fP 
-links \fBPTIE\fP and \fBALU1\fP
-.TP
-\fBCONT_VIA\fP 
-links \fBALU1\fP and \fBALU2\fP
-.TP
-\fBCONT_VIA2\fP 
-links \fBALU2\fP and \fBALU3\fP
-.TP
-\fBC_X_N\fP 
-corner for L-shaped (and S-shaped) N transistor
-.TP
-\fBC_X_P\fP 
-corner for L-shaped (and S-shaped) P transistor
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_PHVIA impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a via inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal addphvia : type is XX  at \fIx, y\fP"
-.ft R
-.RS
-The \fItype\fP parameter does not have a legal value, but \fIXX\fP.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("cell");
-	.
-	/\(** Put a via \(**/
-	GENLIB_PHVIA(CONT_VIA, 12L, 10L);
-	.
-	.
-	GENLIB_DEF_AB(0L, 0L, 0L, 0L);
-	/\(** Save that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHFIG (3),
-.BR GENLIB_SAVE_PHFIG (3),
-.BR GENLIB_PLACE_VIA_REF (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_PLACE.3 b/alliance/share/man/man3/GENLIB_PLACE.3
deleted file mode 100644
index b0899d0b..00000000
--- a/alliance/share/man/man3/GENLIB_PLACE.3
+++ /dev/null
@@ -1,137 +0,0 @@
-.\"   $Id: GENLIB_PLACE.3,v 1.2 2000/09/28 15:25:52 fred Exp $
-.\" @(#)GENLIB_PLACE.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_PLACE
-.XE \}
-.TH GENLIB_PLACE.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_PLACE \- place a physical instance in the current figure at absolute coordinates
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_PLACE(modelname, insname, symetry, x, y)
-char \(**modelname, \(**insname;
-char symetry;
-long x,y;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fImodelname\fP
-Name of the layout figure to be instanciated
-.TP
-\fIinsname\fP
-Name to be given to the instance on the model
-.TP
-\fIsymetry\fP
-Geometrical operation to be performed on the instance before beeing placed
-.TP
-\fIx, y\fP
-Coordinates of the lower left corner of the abutment box on the instance in
-the current figure
-.SH DESCRIPTION
-\fBPLACE\fP add an instance in the current layout cell. The bottom left corner
-of the instance of the model \fImodelname\fP is placed, after beeing
-symetrized and/or rotated, at \fI(x, y)\fP coordinates. 
-The placed instance becomes the new "reference instance", used in
-the relative placement functions.
-.br
-The \fIinsname\fP is the name given to the instance and must be unique at
-a given hierarchy level.
-.br
-The \fIsymetry\fP argument can take eight legal values :
-.TP 20
-\fBNOSYM\fP 
-no geometrical operation is performed
-.TP
-\fBSYM_Y\fP 
-Y becomes -Y, that means toward X axe symetry
-.TP
-\fBSYM_X\fP 
-X becomes -X, that means toward Y axe symetry
-.TP
-\fBSYMXY\fP 
-X becomes -X, Y becomes -Y
-.TP
-\fBROT_P\fP 
-a positive 90 degrees rotation take place
-.TP
-\fBROT_M\fP 
-a negative 90 degrees rotation take place
-.TP
-\fBSY_RP\fP 
-Y becomes -Y, and then a positive 90 degrees rotation take place
-.TP
-\fBSY_RM\fP 
-Y becomes -Y, and then a negative 90 degrees rotation take place
-.PP
-The model of the figure to be placed must be available, on disk or in memory.
-The path to the library is specified in the \fBMBK_CATA_LIB\fP (1) and
-\fBMBK_WORK_LIB\fP (1) environment
-variables, and its format is given by the \fBMBK_IN_PH\fP (1) environment
-variable.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_PLACE impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place an instance inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal addphins : transformation is x in insname"
-.ft R
-.RS
-The \fIsymetry\fP parameter is not one of the define given, but has the
-integer value \fBx\fP.
-.RE
-.br
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("cell");
-	/\(** Place two instances \(**/
-	GENLIB_PLACE("gapg0_b","ins1", NOSYM, 0L, 0L);
-	GENLIB_PLACE("gapg8_b","ins2", SYM_X, 80L, 100L);
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHFIG (3),
-.BR GENLIB_SAVE_PHFIG (3),
-.BR GENLIB_PLACE_TOP (3),
-.BR GENLIB_PLACE_BOTTOM (3),
-.BR GENLIB_PLACE_LEFT (3),
-.BR GENLIB_PLACE_RIGHT (3),
-.BR MBK_CATA_LIB (1),
-.BR MBK_WORK_LIB (1),
-.BR MBK_IN_PH (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_PLACE_BOTTOM.3 b/alliance/share/man/man3/GENLIB_PLACE_BOTTOM.3
deleted file mode 100644
index 6d033a13..00000000
--- a/alliance/share/man/man3/GENLIB_PLACE_BOTTOM.3
+++ /dev/null
@@ -1,146 +0,0 @@
-.\"   $Id: GENLIB_PLACE_BOTTOM.3,v 1.2 2000/09/28 15:25:52 fred Exp $
-.\" @(#)GENLIB_PLACE_BOTTOM.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_PLACE_BOTTOM
-.XE \}
-.TH GENLIB_PLACE_BOTTOM.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_PLACE_BOTTOM \- place a physical instance in the current figure under
-the "reference instance"
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_PLACE_BOTTOM(modelname, insname, symetry)
-char \(**modelname, \(**insname;
-char symetry;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fImodelname\fP
-Name of the layout figure to be instanciated
-.TP
-\fIinsname\fP
-Name to be given to the instance on the model
-.TP
-\fIsymetry\fP
-Geometrical operation to be performed on the instance before beeing placed
-.SH DESCRIPTION
-\fBPLACE_BOTTOM\fP add a instance of model \fImodelname\fP
-in the current layout cell.
-The bottom left corner
-of the abutment box of the instance is placed, after beeing symetrized
-and/or rotated,
-toward the bottom left corner of the abutment box of the
-"reference instance". The newly
-placed instance becomes the "reference instance".
-.br
-The \fIinsname\fP is the name given to the instance and must be unique at
-a given hierarchy level.
-.br
-The \fIsymetry\fP argument can take eight legal values :
-.TP 20
-\fBNOSYM\fP
-no geometrical operation is performed
-.TP
-\fBSYM_Y\fP 
-Y becomes -Y, that means toward X axe symetry
-.TP
-\fBSYM_X\fP 
-X becomes -X, that means toward Y axe symetry
-.TP
-\fBSYMXY\fP 
-X becomes -X, Y becomes -Y
-.TP
-\fBROT_P\fP 
-a positive 90 degrees rotation take place
-.TP
-\fBROT_M\fP 
-a negative 90 degrees rotation take place
-.TP
-\fBSY_RP\fP 
-Y becomes -Y, and then a positive 90 degrees rotation take place
-.TP
-\fBSY_RM\fP 
-Y becomes -Y, and then a negative 90 degrees rotation take place
-.PP
-The model of the figure to be placed must be available, on disk or in memory.
-The path to the library is specified in the \fBMBK_CATA_LIB\fP (1) and
-\fBMBK_WORK_LIB\fP (1) environment
-variables, and its format is given by the \fBMBK_IN_PH\fP (1) environment
-variable.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_PLACE_BOTTOM impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place an instance inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_PLACE_BOTTOM impossible : No previous instance"
-.ft R
-.RS
-There are no instances placed in the current layout cell, so it's
-impossible to know where to place from. Use a \fBPLACE\fP call before.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal addphins : transformation is x in insname"
-.ft R
-.RS
-The \fIsymetry\fP parameter is not one of the define given, but has the
-integer value \fBx\fP.
-.RE
-.br
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHSC("cell");
-	/\(** Place two instances \(**/
-	PLACE_PLACE("grbos", "ins1", SYMXY, -3L, 0L);
-	GENLIB_PLACE_BOTTOM("gln", "ins2", NOSYM);
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_PHSC();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHFIG (3),
-.BR GENLIB_SAVE_PHFIG (3),
-.BR GENLIB_PLACE (3),
-.BR GENLIB_PLACE_TOP (3),
-.BR GENLIB_PLACE_RIGHT (3),
-.BR GENLIB_PLACE_LEFT (3),
-.BR MBK_CATA_LIB (1),
-.BR MBK_WORK_LIB (1),
-.BR MBK_IN_PH (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_PLACE_CON_REF.3 b/alliance/share/man/man3/GENLIB_PLACE_CON_REF.3
deleted file mode 100644
index b1efe1ec..00000000
--- a/alliance/share/man/man3/GENLIB_PLACE_CON_REF.3
+++ /dev/null
@@ -1,173 +0,0 @@
-.\"   $Id: GENLIB_PLACE_CON_REF.3,v 1.2 2000/09/28 15:25:53 fred Exp $
-.\" @(#)GENLIB_PLACE_CON_REF.3 2.11 01/92; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_PLACE_CON_REF
-.XE \}
-.TH GENLIB_PLACE_CON_REF.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_PLACE_CON_REF \- put a connector on top of a reference belonging an
-instance in the current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_PLACE_CON_REF(insname, refname, conname, layer, width, face)
-char  \(**insname, \(**refname, \(**conname;
-char layer, face;
-long width;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIinsname\fP
-Name of the instance in the which the reference is to be searched for
-.TP
-\fIrefname\fP
-Name of the reference to be used for the connector placement
-.TP
-\fIconname\fP
-Name of the connector to be placed
-.TP
-\fIlayer\fP
-Physical layer of the connector
-.TP
-\fIwidth\fP
-Width of the connector
-.TP
-\fIface\fP
-Face of the figure on which the connector is to be placed
-.SH DESCRIPTION
-\fBPLACE_CON_REF\fP places a connector called \fIconname\fP ragarding the
-position of the reference, \fIrefname\fP, in the instance called \fIinsname\fP.
-The connector coordinates are computed from the reference coordinates and
-the face given as argument.
-.br
-Two behaviours are expected, regarding the reference coordinates:
-.TP 20
-the reference is on the given face of the \fIabutment box\fP
-a connector called \fIconname\fP is added on top of the reference, with
-the given \fIlayer\fP and \fIwidth\fP.
-.TP
-the reference is anywhere else
-a connector called \fIconname\fP is added on the given face, \fIface\fP, of the
-\fIabutment box\fP, at the y coordinates of the reference if the \fIface\fP
-is \fBEAST\fP or \fBWEST\fP, or x one if the \fIface\fP is \fBNORTH\fP or
-\fBSOUTH\fP. Then a segment is drawn between the reference and the connector.
-All drawn objects are given \fIlayer\fP and \fIwidth\fP as caracteristics.
-.br
-The \fIface\fP argument is meant in the placed instance, and can take any of
-the following values:
-.TP 20
-\fBNORTH\fP
-for a connector placed on the top of the cell.
-.TP
-\fBSOUTH\fP
-for a connector placed on the bottom of the cell.
-.TP
-\fBEAST\fP
-for a connector placed on the right side of the cell.
-.TP
-\fBWEST\fP
-for a connector placed on the left side of the cell.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_PLACE_CON_REF impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a reference inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_PLACE_CON_REF impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a reference inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_PLACE_CON_REF impossible : no abutment box"
-.ft R
-.RS
-The current figure does not have an \fIabutment box\fI. Use \fIDEF_AB\fP(3)
-before this function.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal GENLIB_PLACE_CON_REF : orientation is XX"
-.ft R
-.RS
-The \fIface\fP parameter does not have a legal value, but \fIXX\fP.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphins : instance called \fIinsname\fP does not exist"
-.ft R
-.RS
-No instance called \fIinsname\fP exists in the current figure
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphref : references called \fIrefname\fP does not exist"
-.ft R
-.RS
-No reference called \fIrefname\fP exists in the model of the instance
-\fIinsname\fP.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("cell");
-	GENLIB_PLACE("gaci0_b", "r1", NOSYM, 23L, 54L);
-	/\(** Put a reference \(**/
-	GENLIB_PLACE_CON_REF("r1", "a_0", ALU2, 2, NORTH);
-	/\(** Save that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHFIG (3),
-.BR GENLIB_SAVE_PHFIG (3),
-.BR GENLIB_PHREF (3),
-.BR GENLIB_PHCON (3),
-.BR GENLIB_COPY_UP_REF (3),
-.BR GENLIB_COPY_UP_ALL_REF (3),
-.BR GENLIB_PLACE_CON_REF (3),
-.BR GENLIB_PLACE_SEG_REF (3),
-.BR GENLIB_PLACE_CON_REF (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_PLACE_LEFT.3 b/alliance/share/man/man3/GENLIB_PLACE_LEFT.3
deleted file mode 100644
index a58f3282..00000000
--- a/alliance/share/man/man3/GENLIB_PLACE_LEFT.3
+++ /dev/null
@@ -1,146 +0,0 @@
-.\"   $Id: GENLIB_PLACE_LEFT.3,v 1.2 2000/09/28 15:25:53 fred Exp $
-.\" @(#)GENLIB_PLACE_LEFT.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_PLACE_LEFT
-.XE \}
-.TH GENLIB_PLACE_LEFT.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_PLACE_LEFT \- place a physical instance in the current figure at the left of the
-"reference instance"
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_PLACE_LEFT(modelname, insname, symetry)
-char \(**modelname, \(**insname;
-char symetry;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fImodelname\fP
-Name of the layout figure to be instanciated
-.TP
-\fIinsname\fP
-Name to be given to the instance on the model
-.TP
-\fIsymetry\fP
-Geometrical operation to be performed on the instance before beeing placed
-.SH DESCRIPTION
-\fBPLACE_LEFT\fP add an instance of model \fImodelname\fP
-in the current layout cell.
-The bottom right corner
-of the abutment box of the instance is placed, after beeing symetrized
-and/or rotated,
-toward the bottom left corner of the abutment box of the
-"reference instance". The newly
-placed instance becomes the "reference instance".
-.br
-The \fIinsname\fP is the name given to the instance and must be unique at
-a given hierarchy level.
-.br
-The \fIsymetry\fP argument can take eight legal values :
-.TP 20
-\fBNOSYM\fP
-no geometrical operation is performed
-.TP
-\fBSYM_Y\fP
-Y becomes -Y, that means toward X axe symetry
-.TP
-\fBSYM_X\fP
-X becomes -X, that means toward Y axe symetry
-.TP
-\fBSYMXY\fP
-X becomes -X, Y becomes -Y
-.TP
-\fBROT_P\fP
-a positive 90 degrees rotation take place
-.TP
-\fBROT_M\fP
-a negative 90 degrees rotation take place
-.TP
-\fBSY_RP\fP
-Y becomes -Y, and then a positive 90 degrees rotation take place
-.TP
-\fBSY_RM\fP
-Y becomes -Y, and then a negative 90 degrees rotation take place
-.PP
-The model of the figure to be placed must be available, on disk or in memory.
-The path to the library is specified in the \fBMBK_CATA_LIB\fP (1) and
-\fBMBK_WORK_LIB\fP (1) environment
-variables, and its format is given by the \fBMBK_IN_PH\fP (1) environment
-variable.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_PLACE_LEFT impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place an instance inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_PLACE_LEFT impossible : No previous instance"
-.ft R
-.RS
-There are no instances placed in the current layout cell, so it's
-impossible to know where to place from. Use a \fBPLACE\fP call before.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal addphins : transformation is x in insname"
-.ft R
-.RS
-The \fIsymetry\fP parameter is not one of the define given, but has the
-integer value \fBx\fP.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("cell");
-	/\(** Place two instances \(**/
-	GENLIB_PLACE("grbdo_3","ins1", NOSYM, 0L, 0L);
-	/\(** negative placement values are allowed \(**/
-	GENLIB_PLACE_LEFT("grxwh_k","ins2", SYMXY);
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHFIG (3),
-.BR GENLIB_SAVE_PHFIG (3),
-.BR GENLIB_PLACE (3),
-.BR GENLIB_PLACE_TOP (3),
-.BR GENLIB_PLACE_BOTTOM (3),
-.BR GENLIB_PLACE_RIGHT (3),
-.BR MBK_CATA_LIB (1),
-.BR MBK_WORK_LIB (1),
-.BR MBK_IN_PH (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_PLACE_ON.3 b/alliance/share/man/man3/GENLIB_PLACE_ON.3
deleted file mode 100644
index 7a5ba57a..00000000
--- a/alliance/share/man/man3/GENLIB_PLACE_ON.3
+++ /dev/null
@@ -1,152 +0,0 @@
-.\"   $Id: GENLIB_PLACE_ON.3,v 1.2 2000/09/28 15:25:53 fred Exp $
-.\" @(#)GENLIB_PLACE_ON.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_PLACE_ON
-.XE \}
-.TH GENLIB_PLACE_ON.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_PLACE_ON \- place a physical instance in the current figure matching
-connectors
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_PLACE_ON(figname,ins1,con1,index1,symetry,ins2,con2,index2)
-char \(**figname, \(**ins1, \(**con1, \(**ins2, \(**con2;
-char symetry;
-long index1, index2;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIfigname\fP
-Name of the layout figure to be instanciated
-.TP
-\fIins1\fP
-Name to be given to the instance in the model
-.TP
-\fIcon1\fP
-Name of the connector of the instance to be used for placement
-.TP
-\fIindex1\fP
-Index of the connector, or reference, \fIcon1\fP of the model to be used
-for placement
-.TP
-\fIsymetry\fP
-Geometrical operation to be performed on the instance before beeing placed
-.TP
-\fIins2\fP
-Name of the instance to be used for relative placement
-.TP
-\fIcon2\fP
-Name of the connector of the instance \fIins2\fP on which the placement will
-take place
-.TP
-\fIindex2\fP
-Index of the connector \fIcon2\fP of the instance to be used for relative
-placement
-.SH DESCRIPTION
-\fBPLACE_ON\fP add an instance in the current layout cell. The bottom left corner
-of the instance of the model \fImodelname\fP is placed, after beeing
-symetrized and/or rotated, at \fI(x, y)\fP coordinates. 
-The placed instance becomes the new "reference instance", used in
-the relative placement functions.
-.br
-The \fIinsname\fP is the name given to the instance and must be unique at
-a given hierarchy level.
-.br
-The \fIsymetry\fP argument can take eight legal values :
-.TP 20
-\fBNOSYM\fP 
-no geometrical operation is performed
-.TP
-\fBSYM_Y\fP 
-Y becomes -Y, that means toward X axe symetry
-.TP
-\fBSYM_X\fP 
-X becomes -X, that means toward Y axe symetry
-.TP
-\fBSYMXY\fP 
-X becomes -X, Y becomes -Y
-.TP
-\fBROT_P\fP 
-a positive 90 degrees rotation take place
-.TP
-\fBROT_M\fP 
-a negative 90 degrees rotation take place
-.TP
-\fBSY_RP\fP 
-Y becomes -Y, and then a positive 90 degrees rotation take place
-.TP
-\fBSY_RM\fP 
-Y becomes -Y, and then a negative 90 degrees rotation take place
-.PP
-The model of the figure to be placed must be available, on disk or in memory.
-The path to the library is specified in the \fBMBK_CATA_LIB\fP (1) and
-\fBMBK_WORK_LIB\fP (1) environment
-variables, and its format is given by the \fBMBK_IN_PH\fP (1) environment
-variable.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_PLACE_ON impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place an instance inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal addphins : transformation is x in insname"
-.ft R
-.RS
-The \fIsymetry\fP parameter is not one of the define given, but has the
-integer value \fBx\fP.
-.RE
-.br
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("cell");
-	/\(** Place two instances \(**/
-	GENLIB_PLACE_ON("gapg0_b","ins1", NOSYM, 0L, 0L);
-	GENLIB_PLACE_ON("gapg8_b","ins2", SYM_X, 80L, 100L);
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHFIG (3),
-.BR GENLIB_SAVE_PHFIG (3),
-.BR GENLIB_PLACE_TOP (3),
-.BR GENLIB_PLACE_BOTTOM (3),
-.BR GENLIB_PLACE_LEFT (3),
-.BR GENLIB_PLACE_RIGHT (3),
-.BR MBK_CATA_LIB (1),
-.BR MBK_WORK_LIB (1),
-.BR MBK_IN_PH (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_PLACE_RIGHT.3 b/alliance/share/man/man3/GENLIB_PLACE_RIGHT.3
deleted file mode 100644
index 7824009e..00000000
--- a/alliance/share/man/man3/GENLIB_PLACE_RIGHT.3
+++ /dev/null
@@ -1,145 +0,0 @@
-.\"   $Id: GENLIB_PLACE_RIGHT.3,v 1.2 2000/09/28 15:25:53 fred Exp $
-.\" @(#)GENLIB_PLACE_RIGHT.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_PLACE_RIGHT
-.XE \}
-.TH GENLIB_PLACE_RIGHT.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_PLACE_RIGHT \- place a physical instance in the current figure at
-the right of the "reference instance"
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_PLACE_RIGHT(modelname, insname, symetry)
-char \(**modelname, \(**insname;
-char symetry;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fImodelname\fP
-Name of the layout figure to be instanciated
-.TP
-\fIinsname\fP
-Name to be given to the instance on the model
-.TP
-\fIsymetry\fP
-Geometrical operation to be performed on the instance before beeing placed
-.SH DESCRIPTION
-\fBPLACE_RIGHT\fP add an instance of model \fImodelname\fP
-in the current layout cell.
-The bottom left corner
-of the abutment box of the instance is placed, after beeing symetrized
-and/or rotated,
-toward the bottom right corner of the abutment box of the
-"reference instance". The newly
-placed instance becomes the "reference instance".
-.br
-The \fIinsname\fP is the name given to the instance and must be unique at
-a given hierarchy level.
-.br
-The \fIsymetry\fP argument can take eight legal values :
-.TP 20
-\fBNOSYM\fP
-no geometrical operation is performed
-.TP
-\fBSYM_Y\fP
-Y becomes -Y, that means toward X axe symetry
-.TP
-\fBSYM_X\fP
-X becomes -X, that means toward Y axe symetry
-.TP
-\fBSYMXY\fP
-X becomes -X, Y becomes -Y
-.TP
-\fBROT_P\fP
-a positive 90 degrees rotation take place
-.TP
-\fBROT_M\fP
-a negative 90 degrees rotation take place
-.TP
-\fBSY_RP\fP
-Y becomes -Y, and then a positive 90 degrees rotation take place
-.TP
-\fBSY_RM\fP
-Y becomes -Y, and then a negative 90 degrees rotation take place
-.PP
-The model of the figure to be placed must be available, on disk or in memory.
-The path to the library is specified in the \fBMBK_CATA_LIB\fP (1) and
-\fBMBK_WORK_LIB\fP (1) environment
-variables, and its format is given by the \fBMBK_IN_PH\fP (1) environment
-variable.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_PLACE_RIGHT impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place an instance inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_PLACE_RIGHT impossible : No previous instance"
-.ft R
-.RS
-There are no instances placed in the current layout cell, so it's
-impossible to know where to place from. Use a \fBPLACE\fP call before.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal addphins : transformation is x in insname"
-.ft R
-.RS
-The \fIsymetry\fP parameter is not one of the define given, but has the
-integer value \fBx\fP.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("cell");
-	/\(** Place two instances \(**/
-	GENLIB_PLACE("rsa16","ins1", ROT_P, -5L, 5L);
-	GENLIB_PLACE_RIGHT("gnr32x16", "ins2", SYM_X);
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHFIG (3),
-.BR GENLIB_SAVE_PHFIG (3),
-.BR GENLIB_PLACE (3),
-.BR GENLIB_PLACE_TOP (3),
-.BR GENLIB_PLACE_BOTTOM (3),
-.BR GENLIB_PLACE_LEFT (3),
-.BR MBK_CATA_LIB (1),
-.BR MBK_WORK_LIB (1),
-.BR MBK_IN_PH (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_PLACE_SEG_REF.3 b/alliance/share/man/man3/GENLIB_PLACE_SEG_REF.3
deleted file mode 100644
index 46257848..00000000
--- a/alliance/share/man/man3/GENLIB_PLACE_SEG_REF.3
+++ /dev/null
@@ -1,175 +0,0 @@
-.\"   $Id: GENLIB_PLACE_SEG_REF.3,v 1.2 2000/09/28 15:25:53 fred Exp $
-.\" @(#)GENLIB_PLACE_SEG_REF.3 2.11 01/92; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_PLACE_SEG_REF
-.XE \}
-.TH GENLIB_PLACE_SEG_REF.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_PLACE_SEG_REF \- put a segment on a reference belonging an
-instance in the current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_PLACE_SEG_REF(insname, refname, layer, width, face)
-char  \(**insname, \(**refname;
-char layer, face;
-long width;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIinsname\fP
-Name of the instance in the which the reference is to be searched for
-.TP
-\fIrefname\fP
-Name of the reference to be used for the segment placement
-.TP
-\fIlayer\fP
-Physical layer of the segment
-.TP
-\fIwidth\fP
-Width of the segment
-.TP
-\fIface\fP
-Face of the figure on which the segment is to be placed
-.SH DESCRIPTION
-\fBPLACE_SEG_REF\fP places a segment regarding the position
-of the reference, \fIrefname\fP, in the instance called \fIinsname\fP.
-The segment coordinates are computed from the reference coordinates and
-the face given as argument.
-.br
-Two behaviours are expected, regarding the reference coordinates:
-.TP 20
-the reference is on the given face of the \fIabutment box\fP
-the segment is not added, since it would have zero as length
-.TP
-the reference is anywhere else
-A segment is drawn between the reference and the \fIabutment box\fP,  and is
-given \fIlayer\fP and \fIwidth\fP as attributs.
-One of its endpoint is given by the reference coordinates, the other one
-comes from the \fIface\fP.
-The \fIface\fP argument is meant in the placed instance, and can take any of
-the following values:
-.TP 20
-\fBNORTH\fP
-the other endpoint has, for absissa, the x coordinate of the top of the
-\fIabutment box\fP of the cell, and for ordinate, the y coordinate of
-the reference.
-.TP
-\fBSOUTH\fP
-the other endpoint has, for absissa, the x coordinate of the bottom of the
-\fIabutment box\fP of the cell, and for ordinate, the y coordinate of
-the reference.
-.TP
-\fBEAST\fP
-the other endpoint has, for absissa, the x coordinate of the reference and
-for ordinate, the y coordinate of the right of the \fIabutment box\fP of the
-cell.
-.TP
-\fBWEST\fP
-the other endpoint has, for absissa, the x coordinate of the reference and
-for ordinate, the y coordinate of the left of the \fIabutment box\fP of the
-cell.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_PLACE_SEG_REF impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a reference inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_PLACE_SEG_REF impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a reference inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_PLACE_SEG_REF impossible : no abutment box"
-.ft R
-.RS
-The current figure does not have an \fIabutment box\fI. Use \fIDEF_AB\fP(3)
-before this function.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal GENLIB_PLACE_SEG_REF : orientation is XX"
-.ft R
-.RS
-The \fIface\fP parameter does not have a legal value, but \fIXX\fP.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphins : instance called \fIinsname\fP does not exist"
-.ft R
-.RS
-No instance called \fIinsname\fP exists in the current figure
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphref : references called \fIrefname\fP does not exist"
-.ft R
-.RS
-No reference called \fIrefname\fP exists in the model of the instance
-\fIinsname\fP.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("cell");
-	GENLIB_PLACE("gaci0_b", "r1", NOSYM, 23L, 54L);
-	/\(** Put a reference \(**/
-	GENLIB_PLACE_SEG_REF("r1", "a_0", ALU2, 2, NORTH);
-	/\(** Save that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHFIG (3),
-.BR GENLIB_SAVE_PHFIG (3),
-.BR GENLIB_PHREF (3),
-.BR GENLIB_PHSEG (3),
-.BR GENLIB_COPY_UP_REF (3),
-.BR GENLIB_COPY_UP_ALL_REF (3),
-.BR GENLIB_PLACE_SEG_REF (3),
-.BR GENLIB_PLACE_SEG_REF (3),
-.BR GENLIB_PLACE_SEG_REF (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_PLACE_TOP.3 b/alliance/share/man/man3/GENLIB_PLACE_TOP.3
deleted file mode 100644
index 22ff8149..00000000
--- a/alliance/share/man/man3/GENLIB_PLACE_TOP.3
+++ /dev/null
@@ -1,146 +0,0 @@
-.\"   $Id: GENLIB_PLACE_TOP.3,v 1.2 2000/09/28 15:25:53 fred Exp $
-.\" @(#)GENLIB_PLACE_TOP.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_PLACE_TOP
-.XE \}
-.TH GENLIB_PLACE_TOP.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_PLACE_TOP \- place a physical instance in the current figure on the top of the
-"reference instance"
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_PLACE_TOP(modelname, insname, symetry)
-char \(**modelname, \(**insname;
-char symetry;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fImodelname\fP
-Name of the layout figure to be instanciated
-.TP
-\fIinsname\fP
-Name to be given to the instance on the model
-.TP
-\fIsymetry\fP
-Geometrical operation to be performed on the instance before beeing placed
-.SH DESCRIPTION
-\fBPLACE_TOP\fP add an instance of model \fImodelname\fP
-in the current layout cell.
-The bottom left corner
-of the abutment box of the instance is placed, after beeing symetrized
-and/or rotated,
-toward the top left corner of the abutment box of the
-"reference instance". The newly
-placed instance becomes the "reference instance".
-.br
-The \fIinsname\fP is the name given to the instance and must be unique at
-a given hierarchy level.
-.br
-The \fIsymetry\fP argument can take eight legal values :
-.TP 20
-\fBNOSYM\fP
-no geometrical operation is performed
-.TP
-\fBSYM_Y\fP 
-Y becomes -Y, that means toward X axe symetry
-.TP
-\fBSYM_X\fP 
-X becomes -X, that means toward Y axe symetry
-.TP
-\fBSYMXY\fP 
-X becomes -X, Y becomes -Y
-.TP
-\fBROT_P\fP 
-a positive 90 degrees rotation take place
-.TP
-\fBROT_M\fP 
-a negative 90 degrees rotation take place
-.TP
-\fBSY_RP\fP 
-Y becomes -Y, and then a positive 90 degrees rotation take place
-.TP
-\fBSY_RM\fP
-becomes -Y, and then a negative 90 degrees rotation take place
-.PP
-The model of the figure to be placed must be available, on disk or in memory.
-The path to the library is specified in the \fBMBK_CATA_LIB\fP (1) and
-\fBMBK_WORK_LIB\fP (1) environment
-variables, and its format is given by the \fBMBK_IN_PH\fP (1) environment
-variable.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_PLACE_TOP impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place an instance inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_PLACE_TOP impossible : No previous instance"
-.ft R
-.RS
-There are no instances placed in the current layout cell, so it's
-impossible to know where to place from. Use a \fBPLACE\fP call before.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal addphins : transformation is x in insname"
-.ft R
-.RS
-The \fIsymetry\fP parameter is not one of the define given, but has the
-integer value \fBx\fP.
-.RE
-.br
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("cell");
-	/\(** Place two instances \(**/
-	GENLIB_PLACE("dgl", "ins1", ROT_P, 0L, 0L);
-	GENLIB_PLACE_TOP("idv", "ins2", SY_RP);
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHFIG (3),
-.BR GENLIB_SAVE_PHFIG (3),
-.BR GENLIB_PLACE (3),
-.BR GENLIB_PLACE_RIGHT (3),
-.BR GENLIB_PLACE_BOTTOM (3),
-.BR GENLIB_PLACE_LEFT (3),
-.BR MBK_CATA_LIB (1),
-.BR MBK_WORK_LIB (1),
-.BR MBK_IN_PH (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_PLACE_VIA_REF.3 b/alliance/share/man/man3/GENLIB_PLACE_VIA_REF.3
deleted file mode 100644
index d9520868..00000000
--- a/alliance/share/man/man3/GENLIB_PLACE_VIA_REF.3
+++ /dev/null
@@ -1,130 +0,0 @@
-.\"   $Id: GENLIB_PLACE_VIA_REF.3,v 1.2 2000/09/28 15:25:53 fred Exp $
-.\" @(#)GENLIB_PLACE_VIA_REF.3 2.11 01/92; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_PLACE_VIA_REF
-.XE \}
-.TH GENLIB_PLACE_VIA_REF.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_PLACE_VIA_REF \- put a via on top of a reference belonging to an instance
-in the current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_PLACE_VIA_REF(insname, refname, viatype)
-char  \(**insname, \(**refname;
-char viatype;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIinsname\fP
-Name of the instance in the which the reference is to be searched for
-.TP
-\fIrefname\fP
-Name of the reference to be used as target point
-.TP
-\fIviatype\fP
-Type of via to be placed
-.SH DESCRIPTION
-\fBPLACE_VIA_REF\fP places a via of type \fIviatype\fP on top of the specified
-reference, \fIrefname\fP, in the instance called \fIinsname\fP.
-This function may be used to generate many cells from a single one, in order
-to "program" decoders for example, or in conjuction with \fBPLACE_SEG_REF\fP(3)
-or \fBPLACE_CON_REF\fP(3) to translate virtual connectors into fixed ones.
-.br
-The \fIviatype\fP argument may take the following legal values:
-.TP 20
-\fBCONT_POLY\fP 
-links \fBPOLY\fP and \fBALU1\fP
-.TP
-\fBCONT_DIF_N\fP 
-links \fBNDIF\fP and \fBALU1\fP
-.TP
-\fBCONT_DIF_P\fP 
-links \fBPDIF\fP and \fBALU1\fP
-.TP
-\fBCONT_BODY_N\fP 
-links \fBNTIE\fP and \fBALU1\fP
-.TP
-\fBCONT_BODY_P\fP 
-links \fBPTIE\fP and \fBALU1\fP
-.TP
-\fBCONT_VIA\fP 
-links \fBALU1\fP and \fBALU2\fP
-.TP
-\fBCONT_VIA2\fP 
-links \fBALU2\fP and \fBALU3\fP
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_PLACE_VIA_REF impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a reference inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphins : instance \fIinsname\fP does not exist"
-.ft R
-.RS
-The instance called \fIinsname\fP does not currently belong to the figure.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphref : references called \fIrefname\fP does not exist"
-.ft R
-.RS
-No reference called \fIrefname\fP exists in the model of the instance
-\fIinsname\fP.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("cell");
-	GENLIB_PLACE("gaci0_b", "r1", NOSYM, 23L, 54L);
-	/\(** Put a reference \(**/
-	GENLIB_PLACE_VIA_REF("a_0", "r1", CONT_VIA);
-	/\(** Save that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR dpr (1),
-.BR genlib (1),
-.BR GENLIB_DEF_PHFIG (3),
-.BR GENLIB_SAVE_PHFIG (3),
-.BR GENLIB_PHREF (3),
-.BR GENLIB_PHVIA (3),
-.BR GENLIB_COPY_UP_REF (3),
-.BR GENLIB_COPY_UP_ALL_REF (3),
-.BR GENLIB_PLACE_CON_REF (3),
-.BR GENLIB_PLACE_SEG_REF (3),
-.BR GENLIB_PLACE_VIA_REF (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_REVERSE_PHCON.3 b/alliance/share/man/man3/GENLIB_REVERSE_PHCON.3
deleted file mode 100644
index 9f623ee8..00000000
--- a/alliance/share/man/man3/GENLIB_REVERSE_PHCON.3
+++ /dev/null
@@ -1,71 +0,0 @@
-.\"   $Id: GENLIB_REVERSE_PHCON.3,v 1.2 2000/09/28 15:25:54 fred Exp $
-.\" @(#)GENLIB_REVERSE_PHCON.3 2.11 93/09/03 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_REVERSE_PHCON
-.XE \}
-.TH GENLIB_REVERSE_PHCON.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_REVERSE_PHCON \- reverse the order of physical connectors on a bus.
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_REVERSE_PHCON(basename)
-char \(**basename;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIbasename\fP
-Radical of the vector to be reversed.
-.SH DESCRIPTION
-\fBREVERSE_PHCON\fP will change the indexes of the vector called
-\fIbasename\fP, making the greatest values the smallest and so on.
-Both hard connectors, created by \fBPHCON\fR(3) like functions and
-virtual ones, done with \fBPHREF\fR(3), will be taken into account for
-the reverse operation.
-This function is mainly useful to implement the \fBmsb0\fR options of
-the \fBAlliance\fR CAD system module generators, as the whole design can
-be done with the designer choosen bit ordering, and modified on user
-demand only before saving.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	GENLIB_DEF_PHFIG("rom");
-	/\(** Create a figure to work on  \(**/
-	.
-	.
-	.
-	/\(** Reverse the bit ordering if needed \(**/
-	if (msb0)
-		GENLIB_REVERSE_PHCON("adr");
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_PHCON (3),
-.BR GENLIB_PHREF (3),
-.BR GENLIB_COPY_UP_CON (3),
-.BR GENLIB_COPY_UP_ALL_CON (3),
-.BR GENLIB_COPY_UP_CON_FACE (3),
-.BR GENLIB_COPY_UP_REF (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_SAVE_LOFIG.3 b/alliance/share/man/man3/GENLIB_SAVE_LOFIG.3
deleted file mode 100644
index 3f64326c..00000000
--- a/alliance/share/man/man3/GENLIB_SAVE_LOFIG.3
+++ /dev/null
@@ -1,92 +0,0 @@
-.\"   $Id: GENLIB_SAVE_LOFIG.3,v 1.2 2000/09/28 15:25:54 fred Exp $
-.\" @(#)SAVE_LOFIOG.3 2.11 01/92; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_SAVE_LOFIG
-.XE \}
-.TH GENLIB_SAVE_LOFIG.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_SAVE_LOFIG \- save a netlist on disk
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_SAVE_LOFIG();
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH DESCRIPTION
-\fBSAVE_LOFIG\fP saves the current working figure previously definded by
-a \fBDEF_LOFIG\fP call. \fBSAVE_LOFIG\fP uses environment variables to
-choose the file format and the path to the file.
-\fBMBK_OUT_LO\fP set up the output file format, the valid ones beeing :
-.RS
-\fBhns
-.br
-fne
-.br
-al
-.br
-alx\fP
-.RE
-you could for example do :
-.br
-.RS
-\fBsetenv MBK_OUT_LO al\fP
-.RE
-\fBMBK_WORK_LIB\fP set up the output file path. Any valid unix path is
-ok.
-.br
-for example :
-.RS
-\fBsetenv MBK_WORK_LIB ~fred/booth/genlib\fP
-.RE
-\fBSAVE_LOFIG\fP doesn't look on disk for the figure \fIcellname\fP, 
-so be careful not to overwrite an existing file while saving.
-.SH ERROR
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_SAVE_LOFIG impossible : missing GENLIB_DEF_LOFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_LOFIG\fP. So it isn't
-possible to save anything. you must call \fBDEF_LOFIG\fP before any other
-netlist call.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_LOFIG("mycell");
-	/\(** define interface  \(**/
-	GENLIB_LOCON("i", INPUT, "sig1");
-	GENLIB_LOCON("o", OUTPUT, "sig2");
-	/\(** Place an instance \(**/
-	GENLIB_LOINS("model","instance", "sig1", "sig2", EOL);
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_LOFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_LOFIG.3),
-.BR MBK_OUT_LO (1),
-.BR MBK_WORK_LIB (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_SAVE_PHFIG.3 b/alliance/share/man/man3/GENLIB_SAVE_PHFIG.3
deleted file mode 100644
index d64a5ec8..00000000
--- a/alliance/share/man/man3/GENLIB_SAVE_PHFIG.3
+++ /dev/null
@@ -1,85 +0,0 @@
-.\"   $Id: GENLIB_SAVE_PHFIG.3,v 1.2 2000/09/28 15:25:54 fred Exp $
-.\" @(#)GENLIB_SAVE_PHFIG.3 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_SAVE_PHFIG
-.XE \}
-.TH GENLIB_SAVE_PHFIG.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_SAVE_PHFIG \- save a layout on disk
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_SAVE_PHFIG();
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH DESCRIPTION
-\fBSAVE_PHFIG\fP saves the current working figure previously definded by
-a \fBDEF_PHFIG\fP call. \fBSAVE_PHFIG\fP uses environment variables to
-choose the file format and the path to the file.
-.br
-\fBMBK_OUT_PH\fP set up the output file format, the valid ones beeing :
-.RS
-\fBcp
-.br
-ap\fP
-.RE
-you could for example do :
-.RS
-\fBsetenv MBK_OUT_PH ap\fP
-.RE
-\fBMBK_WORK_LIB\fP set up the output file path. Any valid unix path is
-ok.
-.br
-for example :
-.RS
-	\fBsetenv MBK_WORK_LIB ~fred/booth/genlib\fP
-.RE
-\fBSAVE_PHFIG\fP doesn't look on disk for the figure \fIcellname\fP, 
-so be careful not to overwrite an existing file while saving.
-.SH ERROR
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_SAVE_PHFIG impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to save anything. you must call \fBDEF_PHFIG\fP before any other
-layout action.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("mycell");
-	/\(** Place an instance \(**/
-	GENLIB_PLACE("mymodel","firstinstance", NOSYM,0L,0L);
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_SAVE_PHSC (3),
-.BR MBK_OUT_PH (1),
-.BR MBK_WORK_LIB (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_SAVE_PHSC.3 b/alliance/share/man/man3/GENLIB_SAVE_PHSC.3
deleted file mode 100644
index 932f55c0..00000000
--- a/alliance/share/man/man3/GENLIB_SAVE_PHSC.3
+++ /dev/null
@@ -1,72 +0,0 @@
-.\"   $Id: GENLIB_SAVE_PHSC.3,v 1.2 2000/09/28 15:25:54 fred Exp $
-.\" @(#)GENLIB_SAVE_PHSC.3 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_SAVE_PHSC
-.XE \}
-.TH GENLIB_SAVE_PHSC.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_SAVE_PHSC \- save a layout on disk
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_SAVE_PHSC();
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH DESCRIPTION
-\fBSAVE_PHSC\fP saves the current working figure previously definded by
-a \fBDEF_PHFIG\fP or \fBDEF_PHSC\fP call, and performs a
-\fBDEF_AB(0L, 0L, 0L, 0L)\fP just before saving the figure, in order to give
-it the appropriate size for standard cell blocks.
-\fBSAVE_PHSC\fP uses environment variables to choose the file format and 
-the path to the file.
-.br
-No check is made to see if a file with the same name already exists on disk, so
-be careful not to overwrite some precious data.
-.SH ERROR
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_SAVE_PHSC impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP or
-\fBDEF_PHSC\fB. So it isn't
-possible to save anything. you must call \fBDEF_PHFIG\fP before any other
-layout action.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a physical figure to work on \(**/
-	GENLIB_DEF_PHSC("cell");
-	/\(** Place an instance \(**/
-	GENLIB_SC_PLACE("finst", NOSYM,0L,0L);
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_PHSC();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHSC (3),
-.BR MBK_OUT_PH (1),
-.BR MBK_WORK_LIB (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_SC_BOTTOM.3 b/alliance/share/man/man3/GENLIB_SC_BOTTOM.3
deleted file mode 100644
index 520fdbe2..00000000
--- a/alliance/share/man/man3/GENLIB_SC_BOTTOM.3
+++ /dev/null
@@ -1,148 +0,0 @@
-.\"   $Id: GENLIB_SC_BOTTOM.3,v 1.2 2000/09/28 15:25:54 fred Exp $
-.\" @(#)GENLIB_SC_BOTTOM.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_SC_BOTTOM
-.XE \}
-.TH GENLIB_SC_BOTTOM.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_SC_BOTTOM \- place an instance in the current figure at the right of the
-"reference instance"
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_SC_BOTTOM(insname, symetry)
-char \(**insname;
-char symetry;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIinsname\fP
-Name to be given to the instance on the model
-.TP
-\fIsymetry\fP
-Geometrical operation to be performed on the instance before beeing placed
-.SH DESCRIPTION
-\fBSC_BOTTOM\fP add an instance in the current cell. The bottom left corner
-of the abutment box of the instance is placed, after beeing symetrized
-and/or rotated,
-toward the bottom left corner of the abutment box of the
-"reference instance". The newly
-placed instance becomes the "reference instance".
-The placement takes place only if the netlist is up to day,
-because the model of the instance is seeked there, in order to ensure
-consistency.
-.LP
-The \fIsymetry\fP argument can take eight legal values :
-.TP 20
-\fBNOSYM\fP
-no geometrical operation is performed
-.TP
-\fBSYM_Y\fP
-Y becomes -Y, that means toward X axe symetry
-.TP
-\fBSYM_X\fP
-X becomes -X, that means toward Y axe symetry
-.TP
-\fBSYMXY\fP
-X becomes -X, Y becomes -Y
-.TP
-\fBROT_P\fP
-a positive 90 degrees rotation take place
-.TP
-\fBROT_M\fP
-a negative 90 degrees rotation take place
-.TP
-\fBSY_RP\fP
-Y becomes -Y, and then a positive 90 degrees rotation take place
-.TP
-\fBSY_RM\fP
-Y becomes -Y, and then a negative 90 degrees rotation take place
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_SC_BOTTOM impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place an instance inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_SC_BOTTOM impossible : missing GENLIB_DEF_LOFIG"
-.ft R
-.RS
-The current netlist figure is not define, so \fBSC_BOTTOM\fP doesn't know
-where to pick up the model. A \fBDEF_LOFIG\fP or a \fBDEF_PHSC\fP
-is to be performed to avoid this error.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_SC_BOTTOM impossible : no logical instance insname"
-.ft R
-.RS
-The instance \fIinsname\fP does not exist in the netlist representation
-of the cell. It may lead us to believe that there is a consistency
-problem between the two representation of this cell.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal addphins : transformation is x in insname"
-.ft R
-.RS
-The \fIsymetry\fP parameter is not one of the define given, but has the
-integer value \fBx\fP.
-.RE
-.br
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHSC("cell");
-	/\(** Place two instances \(**/
-	GENLIB_SC_PLACE("ins1", NOSYM, 0L, 0L);
-	GENLIB_SC_BOTTOM("ins2", SYMXY);
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_PHSC();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHSC (3),
-.BR GENLIB_SAVE_PHSC (3),
-.BR GENLIB_SC_PLACE (3),
-.BR GENLIB_SC_TOP (3),
-.BR GENLIB_SC_RIGHT (3),
-.BR GENLIB_SC_LEFT (3),
-.BR GENLIB_DEF_PHINS (3),
-.BR GENLIB_FLATTEN_PHFIG (3),
-.BR GENLIB_FLATTEN_ALL_PHINS (3),
-.BR GENLIB_LOINS (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_SC_LEFT.3 b/alliance/share/man/man3/GENLIB_SC_LEFT.3
deleted file mode 100644
index f08dd9e0..00000000
--- a/alliance/share/man/man3/GENLIB_SC_LEFT.3
+++ /dev/null
@@ -1,149 +0,0 @@
-.\"   $Id: GENLIB_SC_LEFT.3,v 1.2 2000/09/28 15:25:54 fred Exp $
-.\" @(#)GENLIB_SC_LEFT.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_SC_LEFT
-.XE \}
-.TH GENLIB_SC_LEFT.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_SC_LEFT \- place an instance in the current figure at the right of the
-"reference instance"
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_SC_LEFT(insname, symetry)
-char \(**insname;
-char symetry;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIinsname\fP
-Name to be given to the instance on the model
-.TP
-\fIsymetry\fP
-Geometrical operation to be performed on the instance before beeing placed
-.SH DESCRIPTION
-\fBSC_LEFT\fP add an instance in the current cell. The bottom right corner
-of the abutment box of the instance is placed, after beeing symetrized
-and/or rotated,
-toward the bottom left corner of the abutment box of the
-"reference instance". The newly
-placed instance becomes the "reference instance".
-The placement takes place only if the netlist is up to day,
-because the model of the instance is seeked there, in order to ensure
-consistency.
-.LP
-The \fIsymetry\fP argument can take eight legal values :
-.TP 20
-\fBNOSYM\fP 
-no geometrical operation is performed
-.TP
-\fBSYM_Y\fP 
-Y becomes -Y, that means toward X axe symetry
-.TP
-\fBSYM_X\fP 
-X becomes -X, that means toward Y axe symetry
-.TP
-\fBSYMXY\fP 
-X becomes -X, Y becomes -Y
-.TP
-\fBROT_P\fP 
-a positive 90 degrees rotation take place
-.TP
-\fBROT_M\fP 
-a negative 90 degrees rotation take place
-.TP
-\fBSY_RP\fP 
-Y becomes -Y, and then a positive 90 degrees rotation take place
-.TP
-\fBSY_RM\fP 
-Y becomes -Y, and then a negative 90 degrees rotation take place
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_SC_LEFT impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place an instance inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_SC_LEFT impossible : missing GENLIB_DEF_LOFIG"
-.ft R
-.RS
-The current netlist figure is not define, so \fISC_LEFT\fP doesn't know
-where to pick up the model. A \fIDEF_LOFIG\fP or a \fIDEF_PHSC\fP
-is to be performed to avoid this error.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_SC_LEFT impossible : no logical instance insname"
-.ft R
-.RS
-The instance \fIinsname\fP does not exist in the netlist representation
-of the cell. It may lead us to believe that there is a consistency
-problem between the two representation of this cell.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal addphins : transformation is x in insname"
-.ft R
-.RS
-The \fIsymetry\fP parameter is not one of the define given, but has the
-integer value \fBx\fP.
-.RE
-.br
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHSC("cell");
-	/\(** Place two instances \(**/
-	GENLIB_SC_PLACE("ins1", NOSYM, 0L, 0L);
-	/\(** negative placement values are allowed \(**/
-	GENLIB_SC_LEFT("ins2", SYM_Y);
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_PHSC();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib(1),
-.BR GENLIB_DEF_PHSC.3),
-.BR GENLIB_SAVE_PHSC.3),
-.BR GENLIB_SC_PLACE.3),
-.BR GENLIB_SC_TOP.3),
-.BR GENLIB_SC_BOTTOM.3),
-.BR GENLIB_SC_RIGHT.3),
-.BR GENLIB_DEF_PHINS (3),
-.BR GENLIB_FLATTEN_PHFIG (3),
-.BR GENLIB_FLATTEN_ALL_PHINS (3),
-.BR GENLIB_LOINS.3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_SC_PLACE.3 b/alliance/share/man/man3/GENLIB_SC_PLACE.3
deleted file mode 100644
index a06342ae..00000000
--- a/alliance/share/man/man3/GENLIB_SC_PLACE.3
+++ /dev/null
@@ -1,150 +0,0 @@
-.\"   $Id: GENLIB_SC_PLACE.3,v 1.2 2000/09/28 15:25:54 fred Exp $
-.\" @(#)GENLIB_SC_PLACE.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_SC_PLACE
-.XE \}
-.TH GENLIB_SC_PLACE.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_SC_PLACE \- place an instance in the current figure at absolute coordinates
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_SC_PLACE(insname, symetry, x, y)
-char \(**insname;
-char symetry;
-long x,y;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIinsname\fP
-Name to be given to the instance on the model
-.TP
-\fIsymetry\fP
-Geometrical operation to be performed on the instance before beeing placed
-.TP
-\fIx, y\fP
-Coordinates of the lower left corner of the abutment box of the model in
-the current figure
-.SH DESCRIPTION
-\fISC_PLACE\fP add an instance in the current cell. The bottom left corner
-of the instance is placed, after beeing symetrized and/or rotated,
-at \fI(x, y)\fP
-coordinates. The placement takes place only if the netlist is up to day,
-because the model of the instance is seeked there, in order to ensure
-consistency.
-The placed instance becomes the new "reference instance", used in
-the relative placement functions.
-.br
-The \fIsymetry\fP argument can take eight legal values :
-.TP 20
-\fBNOSYM\fP
-no geometrical operation is performed
-.TP
-\fBSYM_Y\fP
-Y becomes -Y, that means toward X axe symetry
-.TP
-\fBSYM_X\fP
-X becomes -X, that means toward Y axe symetry
-.TP
-\fBSYMXY\fP
-X becomes -X, Y becomes -Y
-.TP
-\fBROT_P\fP
-a positive 90 degrees rotation take place
-.TP
-\fBROT_M\fP
-a negative 90 degrees rotation take place
-.TP
-\fBSY_RP\fP
-Y becomes -Y, and then a positive 90 degrees rotation take place
-.TP
-\fBSY_RM\fP
-Y becomes -Y, and then a negative 90 degrees rotation take place
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_SC_PLACE impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place an instance inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_SC_PLACE impossible : missing GENLIB_DEF_LOFIG"
-.ft R
-.RS
-The current netlist figure is not define, so \fBSC_PLACE\fP doesn't know
-where to pick up the model. A \fBDEF_LOFIG\fP or a \fBDEF_PHSC\fP
-is to be performed to avoid this error.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_SC_PLACE impossible : no logical instance insname"
-.ft R
-.RS
-The instance \fIinsname\fP does not exist in the netlist representation
-of the cell. It may lead us to believe that there is a consistency
-problem between the two representation of this cell.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal addphins : transformation is x in insname"
-.ft R
-.RS
-The \fIsymetry\fP parameter is not one of the define given, but has the
-integer value \fBx\fP.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHSC("cell");
-	/\(** Place two instances \(**/
-	GENLIB_SC_PLACE("ins1", NOSYM, 0L, 0L);
-	GENLIB_SC_PLACE("ins2", NOSYM, 80L, 100L);
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_PHSC();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHSC (3),
-.BR GENLIB_SAVE_PHSC (3),
-.BR GENLIB_SC_TOP (3),
-.BR GENLIB_SC_BOTTOM (3),
-.BR GENLIB_SC_LEFT (3),
-.BR GENLIB_SC_RIGHT (3),
-.BR GENLIB_DEF_PHINS (3),
-.BR GENLIB_FLATTEN_PHFIG (3),
-.BR GENLIB_FLATTEN_ALL_PHINS (3),
-.BR GENLIB_LOINS (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_SC_RIGHT.3 b/alliance/share/man/man3/GENLIB_SC_RIGHT.3
deleted file mode 100644
index d3385995..00000000
--- a/alliance/share/man/man3/GENLIB_SC_RIGHT.3
+++ /dev/null
@@ -1,147 +0,0 @@
-.\"   $Id: GENLIB_SC_RIGHT.3,v 1.2 2000/09/28 15:25:54 fred Exp $
-.\" @(#)GENLIB_SC_RIGHT.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_SC_RIGHT
-.XE \}
-.TH GENLIB_SC_RIGHT.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_SC_RIGHT \- place an instance in the current figure at the right of the
-"reference instance"
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_SC_RIGHT(insname, symetry)
-char \(**insname;
-char symetry;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIinsname\fP
-Name to be given to the instance on the model
-.TP
-\fIsymetry\fP
-Geometrical operation to be performed on the instance before beeing placed
-.SH DESCRIPTION
-\fBSC_RIGHT\fP add an instance in the current cell. The bottom left corner
-of the abutment box of the instance is placed, after beeing symetrized
-and/or rotated,
-toward the bottom right corner of the abutment box of the
-"reference instance". The newly
-placed instance becomes the "reference instance".
-The placement takes place only if the netlist is up to day,
-because the model of the instance is seeked there, in order to ensure
-consistency.
-.LP
-The \fIsymetry\fP argument can take eight legal values :
-.TP 20
-\fBNOSYM\fP 
-no geometrical operation is performed
-.TP
-\fBSYM_Y\fP 
-Y becomes -Y, that means toward X axe symetry
-.TP
-\fBSYM_X\fP 
-X becomes -X, that means toward Y axe symetry
-.TP
-\fBSYMXY\fP 
-X becomes -X, Y becomes -Y
-.TP
-\fBROT_P\fP 
-a positive 90 degrees rotation take place
-.TP
-\fBROT_M\fP 
-a negative 90 degrees rotation take place
-.TP
-\fBSY_RP\fP 
-Y becomes -Y, and then a positive 90 degrees rotation take place
-.TP
-\fBSY_RM\fP 
-Y becomes -Y, and then a negative 90 degrees rotation take place
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_SC_RIGHT impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place an instance inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_SC_RIGHT impossible : missing GENLIB_DEF_LOFIG"
-.ft R
-.RS
-The current netlist figure is not define, so \fBSC_RIGHT\fP doesn't know
-where to pick up the model. A \fBDEF_LOFIG\fP or a \fBDEF_PHSC\fP
-is to be performed to avoid this error.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_SC_RIGHT impossible : no logical instance insname"
-.ft R
-.RS
-The instance \fIinsname\fP does not exist in the netlist representation
-of the cell. It may lead us to believe that there is a consistency
-problem between the two representation of this cell.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal addphins : transformation is x in insname"
-.ft R
-.RS
-The \fIsymetry\fP parameter is not one of the define given, but has the
-integer value \fBx\fP.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHSC("cell");
-	/\(** Place two instances \(**/
-	GENLIB_SC_PLACE("ins1", NOSYM, 0L, 0L);
-	GENLIB_SC_RIGHT("ins2", SYM_X);
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_PHSC();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib(1),
-.BR GENLIB_DEF_PHSC.3),
-.BR GENLIB_SAVE_PHSC.3),
-.BR GENLIB_SC_PLACE.3),
-.BR GENLIB_SC_TOP.3),
-.BR GENLIB_SC_BOTTOM.3),
-.BR GENLIB_SC_LEFT.3),
-.BR GENLIB_DEF_PHINS (3),
-.BR GENLIB_FLATTEN_PHFIG (3),
-.BR GENLIB_FLATTEN_ALL_PHINS (3),
-.BR GENLIB_LOINS.3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_SC_TOP.3 b/alliance/share/man/man3/GENLIB_SC_TOP.3
deleted file mode 100644
index 22c2ed48..00000000
--- a/alliance/share/man/man3/GENLIB_SC_TOP.3
+++ /dev/null
@@ -1,148 +0,0 @@
-.\"   $Id: GENLIB_SC_TOP.3,v 1.2 2000/09/28 15:25:55 fred Exp $
-.\" @(#)GENLIB_SC_TOP.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_SC_TOP
-.XE \}
-.TH GENLIB_SC_TOP.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_SC_TOP \- place an instance in the current figure at the right of the
-"reference instance"
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_SC_TOP(insname, symetry)
-char \(**insname;
-char symetry;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIinsname\fP
-Name to be given to the instance on the model
-.TP
-\fIsymetry\fP
-Geometrical operation to be performed on the instance before beeing placed
-.SH DESCRIPTION
-\fBSC_TOP\fP add an instance in the current cell. The bottom left corner
-of the abutment box of the instance is placed, after beeing symetrized
-and/or rotated,
-toward the top left corner of the abutment box of the
-"reference instance". The newly
-placed instance becomes the "reference instance".
-The placement takes place only if the netlist is up to day,
-because the model of the instance is seeked there, in order to ensure
-consistency.
-.LP
-The \fIsymetry\fP argument can take eight legal values :
-.TP 20
-\fBNOSYM\fP
-no geometrical operation is performed
-.TP
-\fBSYM_Y\fP
-Y becomes -Y, that means toward X axe symetry
-.TP
-\fBSYM_X\fP
-X becomes -X, that means toward Y axe symetry
-.TP
-\fBSYMXY\fP
-X becomes -X, Y becomes -Y
-.TP
-\fBROT_P\fP
-a positive 90 degrees rotation take place
-.TP
-\fBROT_M\fP
-a negative 90 degrees rotation take place
-.TP
-\fBSY_RP\fP
-Y becomes -Y, and then a positive 90 degrees rotation take place
-.TP
-\fBSY_RM\fP
-Y becomes -Y, and then a negative 90 degrees rotation take place
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_SC_TOP impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place an instance inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_SC_TOP impossible : missing GENLIB_DEF_LOFIG"
-.ft R
-.RS
-The current netlist figure is not define, so \fBSC_TOP\fP doesn't know
-where to pick up the model. A \fBDEF_LOFIG\fP or a \fBDEF_PHSC\fP
-is to be performed to avoid this error.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_SC_TOP impossible : no logical instance insname"
-.ft R
-.RS
-The instance \fIinsname\fP does not exist in the netlist representation
-of the cell. It may lead us to believe that there is a consistency
-problem between the two representation of this cell.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal addphins : transformation is x in insname"
-.ft R
-.RS
-The \fIsymetry\fP parameter is not one of the define given, but has the
-integer value \fBx\fP.
-.RE
-.br
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHSC("cell");
-	/\(** Place two instances \(**/
-	GENLIB_SC_PLACE("ins1", NOSYM, 0L, 0L);
-	GENLIB_SC_TOP("ins2", SYM_X);
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_PHSC();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHSC (3),
-.BR GENLIB_SAVE_PHSC (3),
-.BR GENLIB_SC_PLACE (3),
-.BR GENLIB_SC_RIGHT (3),
-.BR GENLIB_SC_BOTTOM (3),
-.BR GENLIB_SC_LEFT (3),
-.BR GENLIB_DEF_PHINS (3),
-.BR GENLIB_FLATTEN_PHFIG (3),
-.BR GENLIB_FLATTEN_ALL_PHINS (3),
-.BR GENLIB_LOINS (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_THRU_CON_H.3 b/alliance/share/man/man3/GENLIB_THRU_CON_H.3
deleted file mode 100644
index 0018b48f..00000000
--- a/alliance/share/man/man3/GENLIB_THRU_CON_H.3
+++ /dev/null
@@ -1,141 +0,0 @@
-.\"   $Id: GENLIB_THRU_CON_H.3,v 1.2 2000/09/28 15:25:55 fred Exp $
-.\" @(#)GENLIB_THRU_CON_H.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_THRU_CON_H
-.XE \}
-.TH GENLIB_THRU_CON_H.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_THRU_CON_H \- draw an horizontal wire from side to side of the
-\fIabutment box\fP of the current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_THRU_CON_H(layer, width, name, y)
-char layer;
-long width;
-char \(**name;
-long y;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIlayer\fP
-Layout layer of the wire and connectors
-.TP
-\fIwidth\fP
-Width of the wire and connectors
-.TP
-\fIname\fP
-Name of the connectors
-.TP
-\fIy\fP
-Absolute y coordinate of the wire and connectors
-.SH DESCRIPTION
-\fBTHRU_CON_H\fP adds an horizontal segment in the current layout cell.
-Two connectors are created on the \fBWEST\fP and \fPEQST\fP sides of the
-\fIabutment box\fP, at the \fIy\fP coordinates, and given the name \fIname\fP.
-The segment is drawn thru the figure, from the \fBWEST\fP connector to the
-\fBEAST\fP one.
-.br
-This function is mostly used to put \fIthrough routes\fP on a figure, and
-therefore, the \fBT\fP prefixed layer names are the most likely to be used
-here.
-.br
-The \fIlayer\fP argument can take the following legal values:
-.RS
-.TP
-\fBNWELL\fP 
-.TP
-\fBPWELL\fP 
-.TP
-\fBNTIE\fP 
-.TP
-\fBPTIE\fP 
-.TP
-\fBNDIF\fP 
-.TP
-\fBPDIF\fP 
-.TP
-\fBNTRANS\fP 
-.TP
-\fBPTRANS\fP 
-.TP
-\fBPOLY\fP 
-.TP
-\fBALU1\fP 
-.TP
-\fBALU2\fP 
-.TP
-\fBALU3\fP 
-.TP
-\fBTPOLY\fP 
-.TP
-\fBTALU1\fP 
-.TP
-\fBTALU2\fP 
-.TP
-\fBTALU3\fP 
-.RE
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_THRU_CON_H impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a connector inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_THRU_CON_H impossible : no or illegal abutment box"
-.ft R
-.RS
-The current figure has either no abutment box defined yet, or has a heigth
-of zero. \fBDEF_AB\fP is to be called.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("cell");
-	.
-	.
-	.
-	GENLIB_DEF_AB(0L, 0L, 0L, 0L);
-	/\(** Put a wire through the figure \(**/
-	GENLIB_THRU_CON_H(TALU2, 1, "pwet", 32L);
-	/\(** Save that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHFIG (3),
-.BR GENLIB_SAVE_PHFIG (3),
-.BR GENLIB_THRU_H (3),
-.BR GENLIB_THRU_V (3),
-.BR GENLIB_THRU_CON_V (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_THRU_CON_V.3 b/alliance/share/man/man3/GENLIB_THRU_CON_V.3
deleted file mode 100644
index 5799f2d3..00000000
--- a/alliance/share/man/man3/GENLIB_THRU_CON_V.3
+++ /dev/null
@@ -1,144 +0,0 @@
-.\"   $Id: GENLIB_THRU_CON_V.3,v 1.2 2000/09/28 15:25:55 fred Exp $
-.\" @(#)GENLIB_THRU_CON_V.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_THRU_CON_V
-.XE \}
-.TH GENLIB_THRU_CON_V.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_THRU_CON_V \- draw a vertical wire with connectors from side to side
-of the \fIabutment box\fP of the current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_THRU_CON_V(layer, width, name, x)
-char layer;
-long width;
-char \(**name;
-long x;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIlayer\fP
-Layout layer of the wire and connectors
-.TP
-\fIwidth\fP
-Width of the wire and connectors
-.TP
-\fIname\fP
-Name of the connectors
-.TP
-\fIx\fP
-Absolute x coordinate of the wire and connectors
-.SH DESCRIPTION
-\fBTHRU_CON_V\fP adds a vertical segment and two connectors in the current
-layout cell.
-The \fIx\fP coordinates gives the wire and connectors horizontal position,
-vertical ones beeing extracted from the figure \fIabutment box\fP.
-Two connectors are created on the \fBNORTH\fP and \fPSOUTH\fP sides of the
-\fIabutment box\fP, at the \fIx\fP coordinates, and given the name \fIname\fP.
-The segment is drawn thru the figure, from the \fBNORTH\fP connector to the
-\fBSOUTH\fP one.
-.br
-This function is mostly used to put \fIthrough routes\fP on a figure, and
-therefore, the \fBT\fP prefixed layer names are the most likely to be used
-here.
-.br
-The \fIlayer\fP argument can take the following legal values:
-.RS
-.TP
-\fBNWELL\fP 
-.TP
-\fBPWELL\fP 
-.TP
-\fBNTIE\fP 
-.TP
-\fBPTIE\fP 
-.TP
-\fBNDIF\fP 
-.TP
-\fBPDIF\fP 
-.TP
-\fBNTRANS\fP 
-.TP
-\fBPTRANS\fP 
-.TP
-\fBPOLY\fP 
-.TP
-\fBALU1\fP 
-.TP
-\fBALU2\fP 
-.TP
-\fBALU3\fP 
-.TP
-\fBTPOLY\fP 
-.TP
-\fBTALU1\fP 
-.TP
-\fBTALU2\fP 
-.TP
-\fBTALU3\fP 
-.RE
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_THRU_CON_V impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a connector inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_THRU_CON_V impossible : no or illegal abutment box"
-.ft R
-.RS
-The current figure has either no abutment box defined yet, or has an heigth
-of zero. \fBDEF_AB\fP is to be called.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("cell");
-	.
-	.
-	.
-	GENLIB_DEF_AB(0L, 0L, 0L, 0L);
-	/\(** Put a wire through the figure \(**/
-	GENLIB_THRU_CON_V(TALU2, 1, "grumf", 12L);
-	/\(** Save that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHFIG (3),
-.BR GENLIB_SAVE_PHFIG (3),
-.BR GENLIB_THRU_H (3),
-.BR GENLIB_THRU_V (3),
-.BR GENLIB_THRU_CON_V (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_THRU_H.3 b/alliance/share/man/man3/GENLIB_THRU_H.3
deleted file mode 100644
index 18d80600..00000000
--- a/alliance/share/man/man3/GENLIB_THRU_H.3
+++ /dev/null
@@ -1,137 +0,0 @@
-.\"   $Id: GENLIB_THRU_H.3,v 1.2 2000/09/28 15:25:55 fred Exp $
-.\" @(#)GENLIB_THRU_H.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_THRU_H
-.XE \}
-.TH GENLIB_THRU_H.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-\fBTHRU_H\fP \- draw an horizontal wire from side to side of the
-\fIabutment box\fP of the current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_THRU_H(layer, width, y)
-char layer;
-long width;
-long y;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIlayer\fP
-Layout layer of the wire
-.TP
-\fIwidth\fP
-Width of the wire
-.TP
-\fIy\fP
-Absolute y coordinate of the wire
-.SH DESCRIPTION
-\fBTHRU_H\fP adds an horizontal segment in the current layout cell.
-The \fIy\fP coordinates gives the wire its vertical position, horizontal ones
-beeing extracted from the figure \fIabutment box\fP.
-The segment is drawn thru the figure, from one side of the \fIabutment box\fP
-to the other side.
-.br
-This function is mostly used to put \fIthrough routes\fP on a figure, and
-therefore, the \fBT\fP prefixed layer names are the most likely to be used
-here.
-.br
-The \fIlayer\fP argument can take the following legal values:
-.RS
-.TP 
-\fBNWELL\fP 
-.TP
-\fBPWELL\fP 
-.TP
-\fBNTIE\fP 
-.TP
-\fBPTIE\fP 
-.TP
-\fBNDIF\fP 
-.TP
-\fBPDIF\fP 
-.TP
-\fBNTRANS\fP 
-.TP
-\fBPTRANS\fP 
-.TP
-\fBPOLY\fP 
-.TP
-\fBALU1\fP 
-.TP
-\fBALU2\fP 
-.TP
-\fBALU3\fP 
-.TP
-\fBTPOLY\fP 
-.TP
-\fBTALU1\fP 
-.TP
-\fBTALU2\fP 
-.TP
-\fBTALU3\fP 
-.RE
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_THRU_H impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a connector inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_THRU_H impossible : no or illegal abutment box"
-.ft R
-.RS
-The current figure has either no abutment box defined yet, or has a width
-of zero. \fBDEF_AB\fP is to be called.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("cell");
-	.
-	.
-	.
-	GENLIB_DEF_AB(0L, 0L, 0L, 0L);
-	/\(** Put a wire through the figure \(**/
-	GENLIB_THRU_H(TALU2, 1, 32L);
-	/\(** Save that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHFIG (3),
-.BR GENLIB_SAVE_PHFIG (3),
-.BR GENLIB_THRU_V (3),
-.BR GENLIB_THRU_CON_H (3),
-.BR GENLIB_THRU_CON_V (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_THRU_V.3 b/alliance/share/man/man3/GENLIB_THRU_V.3
deleted file mode 100644
index a0ef5f7a..00000000
--- a/alliance/share/man/man3/GENLIB_THRU_V.3
+++ /dev/null
@@ -1,137 +0,0 @@
-.\"   $Id: GENLIB_THRU_V.3,v 1.2 2000/09/28 15:25:55 fred Exp $
-.\" @(#)GENLIB_THRU_V.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_THRU_V
-.XE \}
-.TH GENLIB_THRU_V.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_THRU_V \- draw a vertical wire from side to side of the
-\fIabutment box\fP of the current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_THRU_V(layer, width, x)
-char layer;
-long width;
-long x;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIlayer\fP
-Layout layer of the wire
-.TP
-\fIwidth\fP
-Width of the wire
-.TP
-\fIx\fP
-Absolute x coordinate of the wire
-.SH DESCRIPTION
-\fBTHRU_V\fP adds a vertical segment in the current layout cell.
-The \fIx\fP coordinates gives the wire its horizontal position, vertical ones
-beeing extracted from the figure \fIabutment box\fP.
-The segment is drawn thru the figure, from one side of the \fIabutment box\fP
-to the other side.
-.br
-This function is mostly used to put \fIthrough routes\fP on a figure, and
-therefore, the \fBT\fP prefixed layer names are the most likely to be used
-here.
-.br
-The \fIlayer\fP argument can take the following legal values:
-.RS
-.TP
-\fBNWELL\fP 
-.TP
-\fBPWELL\fP 
-.TP
-\fBNTIE\fP 
-.TP
-\fBPTIE\fP 
-.TP
-\fBNDIF\fP 
-.TP
-\fBPDIF\fP 
-.TP
-\fBNTRANS\fP 
-.TP
-\fBPTRANS\fP 
-.TP
-\fBPOLY\fP 
-.TP
-\fBALU1\fP 
-.TP
-\fBALU2\fP 
-.TP
-\fBALU3\fP 
-.TP
-\fBTPOLY\fP 
-.TP
-\fBTALU1\fP 
-.TP
-\fBTALU2\fP 
-.TP
-\fBTALU3\fP 
-.RE
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_THRU_V impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a connector inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_THRU_V impossible : no or illegal abutment box"
-.ft R
-.RS
-The current figure has either no abutment box defined yet, or has a width
-of zero. \fBDEF_AB\fP is to be called.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("cell");
-	.
-	.
-	.
-	GENLIB_DEF_AB(0L, 0L, 0L, 0L);
-	/\(** Put a wire through the figure \(**/
-	GENLIB_THRU_V(TALU2, 1, 32L);
-	/\(** Save that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHFIG (3),
-.BR GENLIB_SAVE_PHFIG (3),
-.BR GENLIB_THRU_H (3),
-.BR GENLIB_THRU_CON_H (3),
-.BR GENLIB_THRU_CON_V (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_UNFLATTEN_LOFIG.3 b/alliance/share/man/man3/GENLIB_UNFLATTEN_LOFIG.3
deleted file mode 100644
index ee9f0eb1..00000000
--- a/alliance/share/man/man3/GENLIB_UNFLATTEN_LOFIG.3
+++ /dev/null
@@ -1,72 +0,0 @@
-.\"   $Id: GENLIB_UNFLATTEN_LOFIG.3,v 1.2 2000/09/28 15:25:55 fred Exp $
-.\" @(#)GENLIB_UNFLATTEN_LOFIG.3 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_UNFLATTEN_LOFIG
-.XE \}
-.TH GENLIB_UNFLATTEN_LOFIG.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-\fBUNFLATTEN_LOFIG\fP \- creates a hierarchy level from instances in the current logical figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_UNFLATTEN_LOFIG(figurename, instancename, list_of_instances, 0)
-char \(**figurename;
-char \(**instancename;
-char \(**list_of_instances;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIfigurename\fP
-Name of the figure of the new hierarchy to be created
-.TP
-\fIinstancename\fP
-Name to be given at the instanciation of \fIfigurename\fP into the current
-structual figure
-.TP
-\fIlist_of_instances\fP
-List of strings representing the instances to be inserted into the new figure
-.SH DESCRIPTION
-\fBUNFLATTEN_LOFIG\fP creates a new level of hierarchy, whose model name will
-be \fIfigurename\fP, and instanciate it under the name \fIinstancename\fP in
-the current figure.
-The instances whose name belong to the \fIlist_of_instances\fP parameters are
-added in the new figure, and destroyed from the current figure.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_LOFIG("mycell");
-	.
-	.
-	.
-	/\(** Place an instance \(**/
-	GENLIB_LOINS("model","instance", "sig1", "sig2", EOL);
-	/\(** flatten an instance \(**/
-	GENLIB_UNFLATTEN_LOFIG("newfig", "newins", "instance", ..., 0);
-	/\(** Save all that on disk \(**/
-	GENLIB_SAVE_LOFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_FLATTEN_LOFIG (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_WIDTH.3 b/alliance/share/man/man3/GENLIB_WIDTH.3
deleted file mode 100644
index 1f68499a..00000000
--- a/alliance/share/man/man3/GENLIB_WIDTH.3
+++ /dev/null
@@ -1,62 +0,0 @@
-.\"   $Id: GENLIB_WIDTH.3,v 1.2 2000/09/28 15:25:55 fred Exp $
-.\" @(#)GENLIB_WIDTH.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_WIDTH
-.XE \}
-.TH GENLIB_WIDTH.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_WIDTH \- compute the width of a model
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-long GENLIB_WIDTH(cellname)
-char \(**cellname;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIcellname\fP
-Name of the cell which width is needed
-.SH DESCRIPTION
-\fBWIDTH\fP looks for the figure called \fIcellname\fP on memory, and then on
-disk. When found, the figure \fIabutment box\fP width is calculated, and
-returned.
-.SH RETURN VALUE
-\fBWIDTH\fP returns a long int beeing the cell \fIabutment box\fP width.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-long cellWidth;
-main()
-{
-	cellWidth = GENLIB_WIDTH("n1_y");
-	GENLIB_DEF_PHFIG("pwet");
-	.
-	.
-	.
-	GENLIB_PLACE("na2_y","ins1", NOSYM, 0L, 4 * cellWidth);
-	/\(** Save all that on disk \(**/
-	GENLIB_DEF_AB(0L, 0L, 0L, 0L);
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_HEIGHT (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_WIRE1.3 b/alliance/share/man/man3/GENLIB_WIRE1.3
deleted file mode 100644
index 38130fd5..00000000
--- a/alliance/share/man/man3/GENLIB_WIRE1.3
+++ /dev/null
@@ -1,175 +0,0 @@
-.\"   $Id: GENLIB_WIRE1.3,v 1.2 2000/09/28 15:25:55 fred Exp $
-.\" @(#)GENLIB_WIRE1.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_WIRE1
-.XE \}
-.TH GENLIB_WIRE1.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_WIRE1 \- place a physical segment in the current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_WIRE1(layer, width, ins1, con1, index1, ins2, con2, index2)
-char layer;
-long width;
-char \(**ins1, \(**con1, \(**ins2, \(**con2;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIlayer\fP
-Layout layer of the segment
-.TP
-\fIwidth\fP
-Width of the segment
-.TP
-\fIins1\fP
-Name of the instance in which the connector \fIcon1\fP is to be looked for
-.TP
-\fIcon1\fP
-Name of a connector, or reference, used as first endpoint of the wire
-.TP
-\fIins2\fP
-Name of the instance in which the connector \fIcon2\fP is to be looked for
-.TP
-\fIcon2\fP
-Name of a connector, or reference, used as last endpoint of the wire
-.SH DESCRIPTION
-\fBWIRE1\fP adds a segment made of the \fIlayer\fP level in the current
-layout cell, the starting point
-beeing the connector, or reference, \fIcon1\fP of the instance \fIins1\fP, and
-the ending point beeing the connector, or reference, \fIcon2\fP of the instance
-\fIins1\fP. The segment is drawn between the coordinates of \fIcon1\fP in
-the current figure and the
-coordinates of \fIcon2\fP in the current figure. 
-.LP
-If the endpoints are connectors, the indexes \fIindex1\fP and \fIindex2\fP must
-respectivly refer to \fIcon1\fP and \fIcon2\fP.
-If they are references, then they are not taked care of.
-One shall notice that connectors and references of a given model should not
-share names if \fBWIRE1\fP is to be used.
-.LP
-The \fIlayer\fP argument can take the following legal values :
-.RS
-.TP
-\fBNWELL\fP 
-.TP
-\fBPWELL\fP 
-.TP
-\fBNTIE\fP 
-.TP
-\fBPTIE\fP 
-.TP
-\fBNDIF\fP 
-.TP
-\fBPDIF\fP 
-.TP
-\fBNTRANS\fP 
-.TP
-\fBPTRANS\fP 
-.TP
-\fBPOLY\fP 
-.TP
-\fBALU1\fP 
-.TP
-\fBALU2\fP 
-.TP
-\fBALU3\fP 
-.TP
-\fBTPOLY\fP 
-.TP
-\fBTALU1\fP 
-.TP
-\fBTALU2\fP 
-.TP
-\fBTALU3\fP 
-.RE
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_WIRE1 impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place an instance inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal addphseg : x1, y1, x2, y2"
-.ft R
-.RS
-A symbolic segment must be either vertical or horizontal, so either
-\fIx1 = x2\fP, or \fIy1 = y2\fP. Since \fBWIRE1\fP creates a segment from
-relative coordinates, care must be taken to follow the previous rule.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_WIRE1 impossible : same name \fIconX\fP, for connector and reference in
-\fIinsX\fP"
-.ft R
-.RS
-The model of the instance \fIinsX\fP has both a connector and a reference
-that matches the \fIconX\fP name. This is not legal since genlib doesn't know
-which one to choose as point.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphins : instance \fIinsX\fP does not exist"
-.ft R
-.RS
-The instance called \fIinsX\fP does not currently belong to the figure.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("cell");
-	GENLIB_PLACE("gaci0_b", "r_addin_1", NOSYM, 0, 0);
-	GENLIB_PLACE_RIGHT("gapgn_b", "pg", NOSYM);
-	GENLIB_PLACE_RIGHT("gacin_b", "r_addin_2", NOSYM);
-	/\(** Draw a segment \(**/
-	GENLIB_WIRE1(ALU1, 1, "r_addin_1", "out", 0L, "r_addin_2", "in", 1L);
-	/\(** Save that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHFIG (3),
-.BR GENLIB_SAVE_PHFIG (3),
-.BR GENLIB_COPY_UP_SEG (3),
-.BR GENLIB_PHSEG (3),
-.BR GENLIB_THRU_H (3),
-.BR GENLIB_THRU_CON_H (3),
-.BR GENLIB_THRU_V (3),
-.BR GENLIB_THRU_CON_V (3),
-.BR GENLIB_WIRE2 (3),
-.BR GENLIB_WIRE3 (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_WIRE2.3 b/alliance/share/man/man3/GENLIB_WIRE2.3
deleted file mode 100644
index 054b8fb1..00000000
--- a/alliance/share/man/man3/GENLIB_WIRE2.3
+++ /dev/null
@@ -1,181 +0,0 @@
-.\"   $Id: GENLIB_WIRE2.3,v 1.2 2000/09/28 15:25:56 fred Exp $
-.\" @(#)GENLIB_WIRE2.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_WIRE2
-.XE \}
-.TH GENLIB_WIRE2.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_WIRE2 \- place two physical segments in the current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_WIRE2(layer, width, ins1, con1, index1, ins2, con2, index2, x, y)
-char layer;
-long width;
-char \(**ins1, \(**con1, \(**ins2, \(**con2;
-long x, y;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIlayer\fP
-Layout layer of the segment
-.TP
-\fIwidth\fP
-Width of the segment
-.TP
-\fIins1\fP
-Name of the instance in which the connector \fIcon1\fP is to be looked for
-.TP
-\fIcon1\fP
-Name of a connector, or reference, used as first endpoint of the wire
-.TP
-\fIins2\fP
-Name of the instance in which the connector \fIcon2\fP is to be looked for
-.TP
-\fIcon2\fP
-Name of a connector, or reference, used as last endpoint of the wire
-.TP
-\fIx, y\fP
-Coordinates of the segment's elbow in the current figure
-.SH DESCRIPTION
-\fBWIRE2\fP adds two segments made of the \fIlayer\fP level in the current
-layout cell, the starting point
-beeing the connector, or reference, \fIcon1\fP of the instance \fIins1\fP, and
-the ending point beeing the connector, or reference, \fIcon2\fP of the instance
-\fIins1\fP. The first segment is drawn between the coordinates of \fIcon1\fP in
-the current figure and \fIx, y\fP, and the second one between \fIx, y\fP and the
-coordinates of \fIcon2\fP in the current figure. 
-.LP
-If the endpoints are connectors, the indexes \fIindex1\fP and \fIindex2\fP must
-respectivly refer to \fIcon1\fP and \fIcon2\fP.
-If they are references, then they are not taked care of.
-One shall notice that connectors and references of a given model should not
-share names if \fBWIRE2\fP is to be used.
-.LP
-The \fIlayer\fP argument can take the following legal values :
-.RS
-.TP
-\fBNWELL\fP 
-.TP
-\fBPWELL\fP 
-.TP
-\fBNTIE\fP 
-.TP
-\fBPTIE\fP 
-.TP
-\fBNDIF\fP 
-.TP
-\fBPDIF\fP 
-.TP
-\fBNTRANS\fP 
-.TP
-\fBPTRANS\fP 
-.TP
-\fBPOLY\fP 
-.TP
-\fBALU1\fP 
-.TP
-\fBALU2\fP 
-.TP
-\fBALU3\fP 
-.TP
-\fBTPOLY\fP 
-.TP
-\fBTALU1\fP 
-.TP
-\fBTALU2\fP 
-.TP
-\fBTALU3\fP 
-.RE
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_WIRE2 impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place an instance inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal addphseg : x1, y1, x2, y2"
-.ft R
-.RS
-A symbolic segment must be either vertical or horizontal, so either
-\fIx1 = x2\fP, or \fIy1 = y2\fP. Since \fBWIRE2\fP creates segments from
-relative coordinates, care must be taken to follow the previous rule.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_WIRE2 impossible : same name \fIconX\fP, for connector and reference in
-\fIinsX\fP"
-.ft R
-.RS
-The model of the instance \fIinsX\fP has both a connector and a reference
-that matches the \fIconX\fP name. This is not legal since genlib doesn't know
-which one to choose as point.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphins : instance \fIinsX\fP does not exist"
-.ft R
-.RS
-The instance called \fIinsX\fP does not currently belong to the figure.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	GENLIB_DEF_PHFIG("cell");
-	GENLIB_PLACE("gaci0_b", "r_addin_1", NOSYM, 0, 0);
-	GENLIB_PLACE_TOP("gacin_b", "r_addin_2", NOSYM);
-	GENLIB_PLACE_RIGHT("gapgn_b", "pg", NOSYM);
-	/\(** Draw a segment \(**/
-	GENLIB_WIRE2(ALU1, 1, "r_addin_1", "out", 0L, "pg", "g", 1L,
-			GENLIB_GET_CON_X("pg", "g", 1L),
-			GENLIB_GET_CON_Y("r_addin_1", "out", 0L));
-	/\(** Save that on disk \(**/
-	GENLIB_SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHFIG (3),
-.BR GENLIB_SAVE_PHFIG (3),
-.BR GENLIB_COPY_UP_SEG (3),
-.BR GENLIB_PHSEG (3),
-.BR GENLIB_THRU_H (3),
-.BR GENLIB_THRU_CON_H (3),
-.BR GENLIB_THRU_V (3),
-.BR GENLIB_THRU_CON_V (3),
-.BR GENLIB_WIRE1 (3),
-.BR GENLIB_WIRE3 (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GENLIB_WIRE3.3 b/alliance/share/man/man3/GENLIB_WIRE3.3
deleted file mode 100644
index 22f05c1d..00000000
--- a/alliance/share/man/man3/GENLIB_WIRE3.3
+++ /dev/null
@@ -1,184 +0,0 @@
-.\"   $Id: GENLIB_WIRE3.3,v 1.2 2000/09/28 15:25:56 fred Exp $
-.\" @(#)GENLIB_WIRE3.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GENLIB_WIRE3
-.XE \}
-.TH GENLIB_WIRE3.3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GENLIB_WIRE3 \- place three physical segments in the current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void GENLIB_WIRE3(layer, width, ins1, con1, index1, ins2, con2, index2, x1, y1, x2, y2)
-char layer;
-long width;
-char \(**ins1, \(**con1, \(**ins2, \(**con2;
-long x1, y1, x2, y2;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIlayer\fP
-Layout layer of the segment
-.TP
-\fIwidth\fP
-Width of the segment
-.TP
-\fIins1\fP
-Name of the instance in which the connector \fIcon1\fP is to be looked for
-.TP
-\fIcon1\fP
-Name of a connector, or reference, used as first endpoint of the wire
-.TP
-\fIins2\fP
-Name of the instance in which the connector \fIcon2\fP is to be looked for
-.TP
-\fIcon2\fP
-Name of a connector, or reference, used as last endpoint of the wire
-.TP
-\fIx1, y1\fP
-Coordinates of the segment's first elbow endpoint in the current figure
-.TP
-\fIx2, y2\fP
-Coordinates of the segment's second elbow endpoint in the current figure
-.SH DESCRIPTION
-\fBWIRE3\fP adds three segments made of the \fIlayer\fP level in the current
-layout cell, the starting point
-beeing the connector, or reference, \fIcon1\fP of the instance \fIins1\fP, and
-the ending point beeing the connector, or reference, \fIcon2\fP of the instance
-\fIins1\fP. The first segment is drawn between the coordinates of \fIcon1\fP in
-the current figure and \fIx1, y1\fP. The second one between \fIx1, y1\fP and
-\fIx2, y2\fP, and the last, but not the least, between \fIx2, y2\fP and the
-coordinates of \fIcon2\fP in the current figure. 
-.LP
-If the endpoints are connectors, the indexes \fIindex1\fP and \fIindex2\fP must
-respectivly refer to \fIcon1\fP and \fIcon2\fP.
-If they are references, then they are not taked care of.
-One shall notice that connectors and references of a given model should not
-share names if \fBWIRE3\fP is to be used.
-.LP
-The \fIlayer\fP argument can take the following legal values :
-.RS
-.TP
-\fBNWELL\fP 
-.TP
-\fBPWELL\fP 
-.TP
-\fBNTIE\fP 
-.TP
-\fBPTIE\fP 
-.TP
-\fBNDIF\fP 
-.TP
-\fBPDIF\fP 
-.TP
-\fBNTRANS\fP 
-.TP
-\fBPTRANS\fP 
-.TP
-\fBPOLY\fP 
-.TP
-\fBALU1\fP 
-.TP
-\fBALU2\fP 
-.TP
-\fBALU3\fP 
-.TP
-\fBTPOLY\fP 
-.TP
-\fBTALU1\fP 
-.TP
-\fBTALU2\fP 
-.TP
-\fBTALU3\fP 
-.RE
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_WIRE3 impossible : missing GENLIB_DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place an instance inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal addphseg : x1, y1, x2, y2"
-.ft R
-.RS
-A symbolic segment must be either vertical or horizontal, so either
-\fIx1 = x2\fP, or \fIy1 = y2\fP. Since \fBWIRE3\fP creates segments from
-relative coordinates, care must be taken to follow the previous rule.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GENLIB_WIRE3 impossible : same name \fIconX\fP, for connector and reference in
-\fIinsX\fP"
-.ft R
-.RS
-The model of the instance \fIinsX\fP has both a connector and a reference
-that matches the \fIconX\fP name. This is not legal since genlib doesn't know
-which one to choose as point.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphins : instance \fIinsX\fP does not exist"
-.ft R
-.RS
-The instance called \fIinsX\fP does not currently belong to the figure.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-draw_wire(cellHeight)
-long cellHeight;
-{
-	/* draw a wire made of 1, 2, or 3 segments, given from and to connectors
-	   or reference, and the x and y coordinates of each elbow points */
-	GENLIB_WIRE1(ALU1,1,"lastpg2","g2",1,"cabl31","sg",2);
-	GENLIB_WIRE3(ALU1,1,"cabl31","sp",2, "celout2", "cin", 1,
-			GENLIB_GET_CON_X("cabl31","sp",2),
-			GENLIB_GET_CON_Y("cabl31","sp",2) + cellHeight / 2,
-			GENLIB_GET_CON_X("celout2", "cin", 1),
-			GENLIB_GET_CON_Y("cabl31","sp",2) + cellHeight / 2);
-	GENLIB_WIRE1(POLY,1,"celout3","g",1,"celout2","co",0);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR GENLIB_DEF_PHFIG (3),
-.BR GENLIB_SAVE_PHFIG (3),
-.BR GENLIB_COPY_UP_SEG (3),
-.BR GENLIB_PHSEG (3),
-.BR GENLIB_THRU_H (3),
-.BR GENLIB_THRU_CON_H (3),
-.BR GENLIB_THRU_V (3),
-.BR GENLIB_THRU_CON_V (3),
-.BR GENLIB_WIRE1 (3),
-.BR GENLIB_WIRE2 (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GETCPAT.3 b/alliance/share/man/man3/GETCPAT.3
deleted file mode 100644
index 413d2f51..00000000
--- a/alliance/share/man/man3/GETCPAT.3
+++ /dev/null
@@ -1,35 +0,0 @@
-.\"   $Id: GETCPAT.3,v 1.2 1999/09/24 14:12:18 simcity Exp $
-.\" @(#)LABEL.3 2.30  UPMC ; PITON D.
-.TH GETCPAT 3 "October 1, 1997" "ASIM/LIP6" "GENPAT functions"
-
-.SH NAME
-.PP
-\fBGETCPAT\fP, GENPAT Package
-
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.PP
-.nf
-GETCPAT();
-.fi
-
-.SH DESCRIPTION
-.PP
-Return the date of the current pattern (in ps). The current pattern is
-set by AFFECT or INIT, GETCPAT will return the date of the last modified
-(affected or initialised) pattern. 
-
-.SH EXAMPLE
-.PP
-.nf
-int t;
-t = GETCPAT();
-.fi
-
-.SH SEE ALSO
-.PP
-genpat(1), pat(5), AFFECT(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GET_CON_X.3 b/alliance/share/man/man3/GET_CON_X.3
deleted file mode 100644
index 92a33c97..00000000
--- a/alliance/share/man/man3/GET_CON_X.3
+++ /dev/null
@@ -1,110 +0,0 @@
-.\"   $Id: GET_CON_X.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.\" @(#)GET_CON_X.3 2.11 01/92; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GET_CON_X
-.XE \}
-.TH GET_CON_X 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GET_CON_X \- retrieve the x coordinate of an instance connector
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-long GET_CON_X(insname, conname, index)
-char \(**insname, \(**conname;
-long index;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIinsname\fP
-Name of the instance in the which the connector is to be searched for
-.TP
-\fIconname\fP
-Name of the connector
-.TP
-\fIindex\fP
-Connector index
-.SH DESCRIPTION
-\fBGET_CON_X\fP looks for 
-the connector, \fIconname\fP, in the instance called \fIinsname\fP.
-Then it computes its absolute coordinates in the figure, and gives back the
-x coordinate.
-.SH RETURN VALUE
-The function returns a long int beeing the x position of the connector
-in the current figure
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GET_CON_X impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a connector inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphins : instance called \fIinsname\fP does not exist"
-.ft R
-.RS
-No instance called \fIinsname\fP exists in the current figure.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphcon : connectors \fIconname\fP, index \fIindex\fP does not exist"
-.ft R
-.RS
-No connector called \fIconname\fP exists in the model of the instance
-\fIinsname\fP.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-long x, y;
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("cell");
-	PLACE("gaci0_b", "r1", NOSYM, 23L, 54L);
-	/\(** Get a connector \(**/
-	x = GET_CON_X("r1", "a", 1);
-	.
-	.
-	PHVIA(x, y, CONT_VIA);
-	/\(** Save that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHFIG (3),
-.BR SAVE_PHFIG (3),
-.BR PHCON (3),
-.BR PHSEG (3),
-.BR COPY_UP_CON (3),
-.BR COPY_UP_ALL_CON (3),
-.BR GET_CON_Y (3),
-.BR GET_REF_X (3),
-.BR GET_REF_Y (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GET_CON_Y.3 b/alliance/share/man/man3/GET_CON_Y.3
deleted file mode 100644
index 3938d92e..00000000
--- a/alliance/share/man/man3/GET_CON_Y.3
+++ /dev/null
@@ -1,110 +0,0 @@
-.\"   $Id: GET_CON_Y.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.\" @(#)GET_CON_Y.3 2.11 01/92; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GET_CON_Y
-.XE \}
-.TH GET_CON_Y 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GET_CON_Y \- retrieve the x coordinate of an instance connector
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-long GET_CON_Y(insname, conname, index)
-char \(**insname, \(**conname;
-long index;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIinsname\fP
-Name of the instance in the which the connector is to be searched for
-.TP
-\fIconname\fP
-Name of the connector
-.TP
-\fIindex\fP
-Connector index
-.SH DESCRIPTION
-\fBGET_CON_Y\fP looks for 
-the connector, \fIconname\fP, in the instance called \fIinsname\fP.
-Then it computes its absolute coordinates in the figure, and gives back the
-y coordinate.
-.SH RETURN VALUE
-The function returns a long int beeing the y position of the connector
-in the current figure
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GET_CON_Y impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a connector inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphins : instance called \fIinsname\fP does not exist"
-.ft R
-.RS
-No instance called \fIinsname\fP exists in the current figure.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphcon : connectors \fIconname\fP, index \fIindex\fP does not exist"
-.ft R
-.RS
-No connector called \fIconname\fP exists in the model of the instance
-\fIinsname\fP.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-long x, y;
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("cell");
-	PLACE("gaci0_b", "r1", NOSYM, 23L, 54L);
-	/\(** Get a connector \(**/
-	y = GET_CON_Y("r1", "a", 1);
-	.
-	.
-	PHVIA(x, y, CONT_VIA);
-	/\(** Save that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHFIG (3),
-.BR SAVE_PHFIG (3),
-.BR PHCON (3),
-.BR PHSEG (3),
-.BR COPY_UP_CON (3),
-.BR COPY_UP_ALL_CON (3),
-.BR GET_CON_X (3),
-.BR GET_REF_X (3),
-.BR GET_REF_Y (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GET_INS_X.3 b/alliance/share/man/man3/GET_INS_X.3
deleted file mode 100644
index 483d4c12..00000000
--- a/alliance/share/man/man3/GET_INS_X.3
+++ /dev/null
@@ -1,94 +0,0 @@
-.\"   $Id: GET_INS_X.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.\" @(#)GET_INS_X.3 2.11 01/92; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GET_INS_X
-.XE \}
-.TH GET_INS_X 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GET_INS_X \- retrieve the x coordinate of an instance
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-long GET_INS_X(insname)
-char \(**insname;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETER
-.TP 20
-\fIinsname\fP
-Name of the instance which x coordinate is to be given back
-.SH DESCRIPTION
-\fBGET_INS_X\fP looks for 
-the instance called \fIinsname\fP in the current figure.
-Then it computes its absolute coordinates in the figure, and gives back its
-x coordinate.
-.SH RETURN VALUE
-The function returns a long int beeing the x position of the instance
-in the current figure
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GET_INS_X impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a connector inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphins : instance called \fIinsname\fP does not exist"
-.ft R
-.RS
-No instance called \fIinsname\fP exists in the current figure.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-long x, y;
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("cell");
-	PLACE("gaci0_b", "r1", NOSYM, 23L, 54L);
-	PLACE_TOP("gaci0_b", "r2", SYM_X);
-	PLACE_RIGHT("gaci0_b", "r3", SYM_Y);
-	/\(** Get a connector \(**/
-	x = GET_INS_X("r3");
-	y = GET_INS_Y("r3");
-	.
-	.
-	/\(** Save that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHFIG (3),
-.BR SAVE_PHFIG (3),
-.BR PHINS (3),
-.BR GET_INS_Y (3),
-.BR GET_CON_X (3),
-.BR GET_CON_Y (3).
-.BR GET_REF_X (3),
-.BR GET_REF_Y (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GET_INS_Y.3 b/alliance/share/man/man3/GET_INS_Y.3
deleted file mode 100644
index 8fd36059..00000000
--- a/alliance/share/man/man3/GET_INS_Y.3
+++ /dev/null
@@ -1,94 +0,0 @@
-.\"   $Id: GET_INS_Y.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.\" @(#)GET_INS_Y.3 2.11 01/92; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GET_INS_Y
-.XE \}
-.TH GET_INS_Y 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GET_INS_Y \- retrieve the y coordinate of an instance
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-long GET_INS_Y(insname)
-char \(**insname;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETER
-.TP 20
-\fIinsname\fP
-Name of the instance which y coordinate is to be given back
-.SH DESCRIPTION
-\fBGET_INS_Y\fP looks for 
-the instance called \fIinsname\fP in the current figure.
-Then it computes its absolute coordinates in the figure, and gives back its
-y coordinate.
-.SH RETURN VALUE
-The function returns a long int beeing the y position of the instance
-in the current figure
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GET_INS_Y impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a connector inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphins : instance called \fIinsname\fP does not exist"
-.ft R
-.RS
-No instance called \fIinsname\fP exists in the current figure.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-long x, y;
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("cell");
-	PLACE("gaci0_b", "r1", NOSYM, 23L, 54L);
-	PLACE_TOP("gaci0_b", "r2", SYM_Y);
-	PLACE_RIGHT("gaci0_b", "r3", SYM_Y);
-	/\(** Get a connector \(**/
-	x = GET_INS_X("r3");
-	y = GET_INS_Y("r3");
-	.
-	.
-	/\(** Save that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHFIG (3),
-.BR SAVE_PHFIG (3),
-.BR PHINS (3),
-.BR GET_INS_X (3),
-.BR GET_CON_X (3),
-.BR GET_CON_Y (3).
-.BR GET_REF_X (3),
-.BR GET_REF_Y (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GET_REF_X.3 b/alliance/share/man/man3/GET_REF_X.3
deleted file mode 100644
index b7438db5..00000000
--- a/alliance/share/man/man3/GET_REF_X.3
+++ /dev/null
@@ -1,130 +0,0 @@
-.\"   $Id: GET_REF_X.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
-.\" @(#)GET_REF_X.3 2.11 01/92; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GET_REF_X
-.XE \}
-.TH GET_REF_X 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GET_REF_X \- retrieve the x coordinate of an instance reference
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-long GET_REF_X(insname, refname)
-char \(**insname, \(**refname;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIinsname\fP
-Name of the instance in the which the reference is to be searched for
-.TP
-\fIrefname\fP
-Name of the reference
-SH DESCRIPTION
-\fBGET_REF_X\fP looks for 
-the reference, \fIrefname\fP, in the instance called \fIinsname\fP.
-.SH RETURN VALUE
-The function returns a long int beeing the x position of the reference
-in the current figure
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GET_REF_X impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a reference inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GET_REF_X impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a reference inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GET_REF_X impossible : no abutment box"
-.ft R
-.RS
-The current figure does not have an \fIabutment box\fI. Use \fIDEF_AB\fP(3)
-before this function.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal GET_REF_X : orientation is XX"
-.ft R
-.RS
-The \fIface\fP parameter does not have a legal value, but \fIXX\fP.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphins : instance called \fIinsname\fP does not exist"
-.ft R
-.RS
-No instance called \fIinsname\fP exists in the current figure
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphref : references called \fIrefname\fP does not exist"
-.ft R
-.RS
-No reference called \fIrefname\fP exists in the model of the instance
-\fIinsname\fP.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("cell");
-	PLACE("gaci0_b", "r1", NOSYM, 23L, 54L);
-	/\(** Put a reference \(**/
-	GET_REF_X("r1", "a_0", ALU2, 2, NORTH);
-	/\(** Save that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHFIG (3),
-.BR SAVE_PHFIG (3),
-.BR PHREF (3),
-.BR PHSEG (3),
-.BR COPY_UP_REF (3),
-.BR COPY_UP_ALL_REF (3),
-.BR GET_REF_X (3),
-.BR GET_REF_X (3),
-.BR GET_REF_X (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/GET_REF_Y.3 b/alliance/share/man/man3/GET_REF_Y.3
deleted file mode 100644
index e2ccba6c..00000000
--- a/alliance/share/man/man3/GET_REF_Y.3
+++ /dev/null
@@ -1,106 +0,0 @@
-.\"   $Id: GET_REF_Y.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)GET_REF_Y.3 2.11 01/92; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-GET_REF_Y
-.XE \}
-.TH GET_REF_Y 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-GET_REF_Y \- retrieve the y coordinate of an instance reference
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-long GET_REF_Y(insname, refname)
-char \(**insname, \(**refname;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIinsname\fP
-Name of the instance in the which the reference is to be searched for
-.TP
-\fIrefname\fP
-Name of the reference
-.SH DESCRIPTION
-\fBGET_REF_Y\fP looks for 
-the reference, \fIrefname\fP, in the instance called \fIinsname\fP.
-Then it computes its absolute coordinates in the figure, and gives back the
-y coordinate.
-.SH RETURN VALUE
-The function returns a long int beeing the y position of the reference
-in the current figure
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"GET_REF_Y impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a reference inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphins : instance called \fIinsname\fP does not exist"
-.ft R
-.RS
-No instance called \fIinsname\fP exists in the current figure.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphref : references called \fIrefname\fP does not exist"
-.ft R
-.RS
-No reference called \fIrefname\fP exists in the model of the instance
-\fIinsname\fP.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-long x, y;
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("cell");
-	PLACE("gaci0_b", "r1", NOSYM, 23L, 54L);
-	/\(** Get a reference \(**/
-	y = GET_REF_Y("r1", "a_0");
-	.
-	.
-	PHVIA(x, y, CONT_VIA);
-	/\(** Save that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHFIG (3),
-.BR SAVE_PHFIG (3),
-.BR PHREF (3),
-.BR PHSEG (3),
-.BR COPY_UP_REF (3),
-.BR COPY_UP_ALL_REF (3),
-.BR GET_CON_X (3),
-.BR GET_CON_Y (3),
-.BR GET_REF_X (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/HEIGHT.3 b/alliance/share/man/man3/HEIGHT.3
deleted file mode 100644
index f3e52585..00000000
--- a/alliance/share/man/man3/HEIGHT.3
+++ /dev/null
@@ -1,59 +0,0 @@
-.\"   $Id: HEIGHT.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)HEIGHT.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-HEIGHT
-.XE \}
-.TH HEIGHT 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-HEIGHT \- compute the height of a model
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-long HEIGHT(cellname)
-char \(**cellname;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIcellname\fP
-Name of the cell which height is needed
-.SH DESCRIPTION
-\fBHEIGHT\fP looks for the figure called \fIcellname\fP on memory, and then on
-disk. When found, the figure \fIabutment box\fP height is calculated, and
-returned.
-.SH RETURN VALUE
-\fIHEIGHT\fP returns a long int beeing the cell \fIabutment box\fP height.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-long cellHeight;
-main()
-{
-	cellHeight = HEIGHT("mycell");
-	DEF_PHFIG("grumf_z");
-	PLACE("na2_y","ins1", NOSYM, 3 * cellHeight, 0L);
-	/\(** Save all that on disk \(**/
-	DEF_AB(0L, 0L, 0L, 0L);
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR WIDTH (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/INIT.3 b/alliance/share/man/man3/INIT.3
deleted file mode 100644
index 729c1f7d..00000000
--- a/alliance/share/man/man3/INIT.3
+++ /dev/null
@@ -1,62 +0,0 @@
-.\"   $Id: INIT.3,v 1.3 1999/10/25 08:03:14 simcity Exp $
-.\" @(#)INIT.3 2.30  UPMC ; VUONG H.N. & PITON D.
-.TH INIT 3 "October 1, 1997" "ASIM/LIP6" "GENPAT functions"
-
-.SH NAME
-.PP
-\fBINIT\fP, GENPAT Package
-
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.PP
-.nf
-INIT("pattern_date","ident","value");
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIpattern_date\fP
-: pattern date which may be either : integer (absolute date) or + integer
-(relative date, the date of the current pattern (last modified using INIT
-or AFFECT) is the reference). All dates are supposed to be expressed in
-the same time unit which may be set only once using SETTUNIT.
-
-.TP 10
-\fIident\fP
-Either the name of a bused register or a simple register. Path-name must be
-specified by the syntax : instance1.instance11.name
-.TP 10
-\fIvalue\fP
-The value associated with the signal which may be either a based number (ex.
-0B011 or 0H3F) or a decimal.
-
-.SH DESCRIPTION
-.PP
-Initialize registers at indicated values and set current pattern.
-
-.SH EXAMPLE
-.PP
-.nf
-SETTUNIT("ns");
-INIT( "25","regt","0B1");
-INIT("+50","y 3 downto 0","0xF");
-
-result :
-At simulation time 25 ns, the register named regt receive "1"
-	regt <= B"1" ;
-<   25 ns> : .............;
-
-At simulation time +50 ns, (related to the date of the current pattern),
-the vector y is affected with the value 15 in decimal or F in hexadecimal.
-	regt <= X"F" ;
-<   75 ns> : .............;
-.fi
-
-.SH SEE ALSO
-.PP
-genpat(1), pat(5), AFFECT(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/LABEL.3 b/alliance/share/man/man3/LABEL.3
deleted file mode 100644
index 18063efe..00000000
--- a/alliance/share/man/man3/LABEL.3
+++ /dev/null
@@ -1,42 +0,0 @@
-.\"   $Id: LABEL.3,v 1.2 1999/10/25 08:03:15 simcity Exp $
-.\" @(#)LABEL.3 2.30  UPMC ; VUONG H.N. & PITON D.
-.TH LABEL 3 "October 1, 1997" "ASIM/LIP6" "GENPAT functions"
-
-.SH NAME
-.PP
-\fBLABEL\fP, GENPAT Package
-
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.PP
-.nf
-LABEL ("ident");
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIident\fP
-label to be put on the current pattern (last modified using INIT or AFFECT)
-
-.SH DESCRIPTION
-.PP
-Set \fIident\fP as the label of the current pattern.
-
-.SH EXAMPLE
-.PP
-.nf
-LABEL ("foo");
-.fi
-
-.SH WARNING
-.PP
-The LABEL fonction from the 1.9 release doesn't have the same behaviour.
-
-.SH SEE ALSO
-.PP
-genpat(1), pat(5), AFFECT(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/LOAD_LOFIG.3 b/alliance/share/man/man3/LOAD_LOFIG.3
deleted file mode 100644
index 39e8d2cd..00000000
--- a/alliance/share/man/man3/LOAD_LOFIG.3
+++ /dev/null
@@ -1,59 +0,0 @@
-.\"   $Id: LOAD_LOFIG.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)LOAD_LOFIG.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-LOAD_LOFIG
-.XE \}
-.TH LOAD_LOFIG 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-LOAD_LOFIG \- loads a netlist form disk and opens it as current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void LOAD_LOFIG(cellname)
-char \(**cellname;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIcellname\fP
-Name of the cell which all futher calls to genlib logical functions will
-work on 
-.SH DESCRIPTION
-\fBLOAD_LOFIG\fP loads a netlist from disk and defines it as current working
-structural figure. 
-This overrides the working figure initialized by \fBDEF_LOFIG\fP(3), if any.
-So the next call to \fBSAVE_LOFIG\fP will save the cell called \fIcellname\fP.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Loads the figure to work on  \(**/
-	LOAD_LOFIG("cell");
-	/\(** Add an instance in cell \(**/
-	LOINS("model","instance", "sig1", "sig2", "sig3", "vdd", "vss", EOL);
-	/\(** Save all that on disk \(**/
-	SAVE_LOFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_LOFIG (3).
-.BR SAVE_LOFIG (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/LOAD_PHFIG.3 b/alliance/share/man/man3/LOAD_PHFIG.3
deleted file mode 100644
index 31617961..00000000
--- a/alliance/share/man/man3/LOAD_PHFIG.3
+++ /dev/null
@@ -1,59 +0,0 @@
-.\"   $Id: LOAD_PHFIG.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)LOAD_PHFIG.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-LOAD_PHFIG
-.XE \}
-.TH LOAD_PHFIG 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-\fBPHAD_PHFIG\fP \- loads a layout form disk and opens it as current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void LOAD_PHFIG(cellname)
-char \(**cellname;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIcellname\fP
-Name of the cell which all futher calls to genlib layout functions will
-work on 
-.SH DESCRIPTION
-\fBPHAD_PHFIG\fP loads a physical view from disk and defines it as current
-working layout figure. 
-This overrides the working figure initialized by \fBDEF_PHFIG\fP(3), if any.
-So the next call to \fBSAVE_PHFIG\fP will save the cell called \fIcellname\fP.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Loads the figure to work on  \(**/
-	LOAD_PHFIG("cell");
-	/\(** Add an instance in cell \(**/
-	PLACE("model","instance", NOSYM, 200, 600);
-	/\(** Save all that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHFIG (3).
-.BR SAVE_PHFIG (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/LOCON.3 b/alliance/share/man/man3/LOCON.3
deleted file mode 100644
index 31838985..00000000
--- a/alliance/share/man/man3/LOCON.3
+++ /dev/null
@@ -1,146 +0,0 @@
-.\"   $Id: LOCON.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)LOCON.3 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-LOCON
-.XE \}
-.TH LOCON 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-LOCON \- adds a logical connector to the current netlist figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void LOCON(connector, direction, signal);
-char \(**connector, \(**signal;
-char direction;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIconnector\fP
-Name of the connector to be created in the current figure
-.TP
-\fIdirection\fP
-Indicates the connector behaviour regarding signals propagation
-.TP
-\fIsignal\fP
-Name of the signal on which the connector is linked
-.SH DESCRIPTION
-\fBLOCON\fP add a logical connector to the interface of the actual
-working figure. This connector is logicaly linked to the signal \fIsignal\fP.
-The \fIdirection\fP attribut may take the following values:
-.TP
-\fBIN\fP
-as input.
-.TP
-\fBOUT\fP 
-as output.
-.TP
-\fBINOUT\fP 
-as input/output, like supplies or clock for example.
-.TP
-\fBUNKNOWN\fP 
-if one doesn't know what it is.
-.TP
-\fBTRISTATE\fP 
-as high impedance input.
-.TP
-\fBTRANSV\fP 
-as transciever. That means \fBTRISTATE\fP input plus output.
-.SH ERROR
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"LOCON impossible : missing DEF_LOFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_LOFIG\fP. So it isn't
-possible to add anything. you must call \fBDEF_LOFIG\fP before any other
-netlist call.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"LOCON : Bad signal or connector bus name"
-.ft R
-.RS
-A signal or connector, described under a bus form, has an illegal syntax.
-.RE
-.TP
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"LOCON : All LOCON should be defined befor any LOINS"
-.ft R
-.RS
-A connector is added after instances. This is a methodological error.
-Only move your \fBLOCON\fP before the first \fBLOINS\fP in your code.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"LOCON : different number of signals and connectors"
-.ft R
-.RS
-A bussed form of signal and connector has been used, but the width of
-the busses are not equal. This is an obvious error, check it.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Illegal addlocon. Connector connector already exist in figure figname"
-.ft R
-.RS
-A connector name must be unique in a given figure at a given hierachy level.
-.RE
-.SH DIAGNOSTICS
-Due to the \fBvti\fP file format, the direction of connectors is lost if
-one uses it as starting point of a netlist desciption. All the connectors
-have then the \fBUNKNOWN\fP direction.
-.br
-Alliance and edif file format know only about \fBIN\fP, \fBOUT\fP, and
-\fBUNKNOWN\fP.
-Only vhdl format fully supports the whole thing.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_LOFIG("mycell");
-	/\(** define interface  \(**/
-	LOCON("i", INPUT, "sig1");
-	LOCON("o", OUTPUT, "sig2");
-	/\(** Place an instance \(**/
-	LOINS("model","instance", "sig1", "sig2", EOL);
-	/\(** Save all that on disk \(**/
-	SAVE_LOFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR BUS (3),
-.BR ELM (3),
-.BR LOSIG (3),
-.BR LOINS (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/LOINS.3 b/alliance/share/man/man3/LOINS.3
deleted file mode 100644
index c2f19a75..00000000
--- a/alliance/share/man/man3/LOINS.3
+++ /dev/null
@@ -1,152 +0,0 @@
-.\"   $Id: LOINS.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)LOINS.3 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-LOINS
-.XE \}
-.TH LOINS 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-LOINS \- add a logical instance to the current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void LOINS(model, instance, sig1, sig2, ..., sign, EOL);
-char \(**model, \(**instance;
-char \(**sig1, \(**sig2, ..., \(**sign;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fImodel\fP
-Name of the model to be logically instanciated
-.TP
-\fIinstance\fP
-Name to be given to the new instance
-.TP
-\fIsig1, sig2, ..., sign\fP
-List of signals to be linked to the implicit connector list of the instance
-.SH DESCRIPTION
-\fBLOINS\fP add a logical instance in the actual working figure.
-\fBLOINS\fP uses environment variables to
-choose the file format and the path to the file.
-.br
-\fBMBK_IN_LO\fP set up the input file format, the valid ones beeing :
-.RS
-.br
-\fBhns
-.br
-fne
-.br
-al
-.br
-alx\fP
-.RE
-\fBMBK_WORK_LIB\fP set up the output file path. Any valid unix path is
-ok.
-\fBLOINS\fP look in memory and then, if not found, on disk for the
-figure \fImodelname\fP. This is due to the need to ensure consistency
-between the model and its ascociated instances.
-.br
-The instance is added with the name \fIinstance\fP, and each of the
-signals are connected to an instance connector. The connectors are 
-implicitly matched from the order of the signal on the list.
-This order is the one given
-in the netlist file, \fBhns\fP or \fBal\fP, or in the \fIsclib\fP
-documentation, for standard cell circuits.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"LOINS impossible : missing DEF_LOFIG"
-.ft R
-.br
-.RS
-No figure has been yet specified by a call to \fBDEF_LOFIG\fP. So it isn't
-possible to add anything. you must call \fBDEF_LOFIG\fP before any other
-netlist call.
-.RE
-.br
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"LOINS : Bad signal bus name"
-.ft R
-.br
-.RS
-A signal, described under a bus form, has an illegal syntax.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Illegal addloins. Instance insname already exist in figure figname"
-.ft R
-.br
-.RS
-An instance name must be unique in a given figure at a given hierachy level.
-.RE
-.br
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Illegal addloins. Instance model is the figure figname itself"
-.ft R
-.br
-.RS
-A figure cannot be included in itself. Be careful, the check is only
-made at current hierarchy level.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.br
-"Illegal addloins. Connector number discrepancy between
-figure modelname and instance insname in figure figname"
-.ft R
-.br
-.RS
-The number of connector in the model is not equal to the number of signals
-describing the connectivity during the \fBLOINS\fP call.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_LOFIG("mycell");
-	/\(** define interface  \(**/
-	LOCON("i", INPUT, "sig1");
-	LOCON("o", OUTPUT, "sig2");
-	/\(** Place an instance \(**/
-	LOINS("model","instance", "sig1", "sig2", EOL);
-	/\(** Save all that on disk \(**/
-	SAVE_LOFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_LOFIG (3),
-.BR MBK_IN_LO (1),
-.BR MBK_CATA_LIB (1),
-.BR MBK_WORK_LIB (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/LOINSE.3 b/alliance/share/man/man3/LOINSE.3
deleted file mode 100644
index c8a0d2f3..00000000
--- a/alliance/share/man/man3/LOINSE.3
+++ /dev/null
@@ -1,159 +0,0 @@
-.\"   $Id: LOINSE.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)LOINSE.3 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-LOINSE
-.XE \}
-.TH LOINSE 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-LOINSE \- add a logical instance to the current figure, with explicit connections
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void LOINSE(model, instance, couple1, couple2, ..., couplen, EOL);
-char \(**model, \(**instance;
-char \(**couple1, \(**couple2, ..., \(**couplen;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fImodel\fP
-Name of the model to be logically instanciated
-.TP
-\fIinstance\fP
-Name to be given to the new instance
-.TP
-\fIcouple1, couple2, ..., couplen\fP
-Explicit list of connections between connectors and signals.
-.SH DESCRIPTION
-\fBLOINSE\fP add a logical instance in the actual working figure.
-\fBLOINSE\fP uses environment variables to
-choose the file format and the path to the file.
-.br
-\fBMBK_IN_LO\fP set up the input file format, the valid ones beeing :
-.RS
-.br
-\fBhns
-.br
-fne
-.br
-al
-.br
-alx\fP
-.RE
-\fBMBK_WORK_LIB\fP set up the output file path. Any valid unix path is
-ok.
-\fBLOINSE\fP look in memory and then, if not found, on disk for the
-figure \fImodelname\fP. This is due to the need to ensure consistency
-between the model and its ascociated instances.
-.br
-The instance is added with the name \fIinstance\fP, and each of the
-signals are connected to an instance connector.
-The connector signal link is explicit, and described in the \fBcouple\fRs
-arguments.
-The \fBcouple\fRs arguments are supposed to have the form:
-.nf
-\fBconector => signal\fP
-.br
-or
-\fBconector[a:b] => signal[n:m]\fP
-where \fIa - b\fP equals, in absolute value, \fIn - m\fR.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"LOINSE impossible : missing DEF_LOFIG"
-.ft R
-.br
-.RS
-No figure has been yet specified by a call to \fBDEF_LOFIG\fP. So it isn't
-possible to add anything. you must call \fBDEF_LOFIG\fP before any other
-netlist call.
-.RE
-.br
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"LOINSE : Bad signal bus name"
-.ft R
-.br
-.RS
-A signal, described under a bus form, has an illegal syntax.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Illegal addloins. Instance insname already exist in figure figname"
-.ft R
-.br
-.RS
-An instance name must be unique in a given figure at a given hierachy level.
-.RE
-.br
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Illegal addloins. Instance model is the figure figname itself"
-.ft R
-.br
-.RS
-A figure cannot be included in itself. Be careful, the check is only
-made at current hierarchy level.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.br
-"Illegal addloins. Connector number discrepancy between
-figure modelname and instance insname in figure figname"
-.ft R
-.br
-.RS
-The number of connector in the model is not equal to the number of signals
-describing the connectivity during the \fBLOINSE\fP call.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_LOFIG("mycell");
-	/\(** define interface  \(**/
-	LOCON("i", INPUT, "sig1");
-	LOCON("o", OUTPUT, "sig2");
-	/\(** Place an instance \(**/
-	LOINSE("model","instance", "con1 => sig1", "con2 => sig2", 0L);
-	LOINSE("stuff","shirt", "i[31:0] => out[32:63]", "j[2] => sig2", 0L);
-	/\(** Save all that on disk \(**/
-	SAVE_LOFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_LOFIG (3),
-.BR LOINS (3),
-.BR MBK_IN_LO (1),
-.BR MBK_CATA_LIB (1),
-.BR MBK_WORK_LIB (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/LOSIG.3 b/alliance/share/man/man3/LOSIG.3
deleted file mode 100644
index db5a7abf..00000000
--- a/alliance/share/man/man3/LOSIG.3
+++ /dev/null
@@ -1,79 +0,0 @@
-.\"   $Id: LOSIG.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)LOSIG.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-LOSIG
-.XE \}
-.TH LOSIG 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-LOSIG \- declare an internal logical signal, or a vector of internal
-logical signals
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void LOSIG(name)
-char \(**name;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIname\fP
-Name of a signal to be declared
-.SH DESCRIPTION
-\fBLOSIG\fP creates the internal signal, or the set of internal signals
-coresponding to a vector description, represented by \fIname\fP.
-See \fBBUS(3)\fP and \fBELM(3)\fP for more details on vectors.
-.br
-The need for declaring signal is mostly felt when one wants to create a
-consistent vector declaration, for file formats that do not allow partial or
-multiple declarations, like \fIvhdl\fP.
-This way, a user can create a vector and access its member the way he wants,
-but still having an internal consistent form.
-.TP 20
-Warning
-If a signal is declared with \fBLOSIG\fP, but not used, the resulting file
-will have an internal node floating.
-This is not an error from a genlib point of view, so the user must be aware
-of it.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_LOFIG("cell");
-	/\(** Define interface \(**
-	LOCON(...
-	/\(** declare buses \(**/
-	LOSIG("grum[23:0]");
-	LOSIG("iconection[0:7]");
-	/\(** Place an instance \(**/
-	LOINS("no2_y" ,"no3" ,"grum[12]" ,"a9_s" ,"new_no3_s" ,"vdd" ,"vss" ,0);
-	LOINS("no2_y" ,"no4" ,"a12_s" ,"grum[6]" ,"no4_s" ,"vdd" ,"vss" ,0);
-	LOINS("a2_y" ,"a22" ,"no3_s" ,"grum[15]" ,"a22_s" ,"vdd" ,"vss" ,0);
-	/\(** Save all that on disk \(**/
-	SAVE_LOFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR LOINS (3),
-.BR LOCON (3),
-.BR BUS (3),
-.BR ELM (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/LOSIGMERGE.3 b/alliance/share/man/man3/LOSIGMERGE.3
deleted file mode 100644
index 97dff1e6..00000000
--- a/alliance/share/man/man3/LOSIGMERGE.3
+++ /dev/null
@@ -1,95 +0,0 @@
-.\"   $Id: LOSIGMERGE.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)LOSIGMERGE.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-LOSIGMERGE
-.XE \}
-.TH LOSIGMERGE 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-LOSIGMERGE \- merge two logical signals
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void LOSIGMERGE(signal1, signal2)
-char \(**signal1, \(**signal2;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIsignal1\fP
-Name of a signal to be merged
-.TP 20
-\fIsignal2\fP
-Name of a signal to be merged
-.SH DESCRIPTION
-\fBLOSIGMERGE\fP merges the two signals, \fIsignal1\fP and \fIsignal2\fP.
-This function can be used anywhere in the \fBgenlib\fP program, but its
-resultings actions must be known by the user.
-.TP 10
-1)
-If \fIsignal1\fP and \fIsignal2\fP have not been used yet, then the
-corresponding signal can be later accessed through any of these aliases.
-.TP 10
-2)
-If one of \fIsignal1\fP or \fIsignal2\fP has not been used yet, then all
-further reference to the not defined name will be made on the same signal than
-the defined signal.
-.TP 10
-3)
-If both signals exist, then they are merged, and both can be used for reference
-to the same signal later on.
-.LP
-Since most of the file formats do not allow multiple name for a
-single signal, the choice is made to keep for disk usage the name that appears
-in the cell interface, if any.
-Otherwise, the choice is randomly made by \fBLOSIGMERGE\fP.
-.TP 10
-Warning
-This function allows the user to internally connect two external connectors.
-This is \fInot\fP a valid disk representation for netlist generated by
-\fBgenlib\fP.
-The \fBSAVE_LOFIG\fP function will exit if encountering such a situation.
-.br
-In order to avoid it, either take care not to link such signals, or build
-all your hierarchy in memory, make sure your block does not have such signals,
-and call \fPFLATTEN_LOFIG\fP(3) just before saving.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_LOFIG("cell");
-	/\(** Define interface \(**
-	LOCON(...
-	/\(** Place an instance \(**/
-	LOINS("no2_y" ,"no3" ,"a8_s" ,"a9_s" ,"new_no3_s" ,"vdd" ,"vss" ,0);
-	LOINS("no2_y" ,"no4" ,"a12_s" ,"a15_s" ,"no4_s" ,"vdd" ,"vss" ,0);
-	LOINS("a2_y" ,"a22" ,"no3_s" ,"no4_s" ,"a22_s" ,"vdd" ,"vss" ,0);
-	LOSIGMERGE("new_no3_s", "no3_s");
-	/\(** Save all that on disk \(**/
-	SAVE_LOFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR LOINS (3),
-.BR LOCON (3),
-.BR FLATTEN_LOFIG (3),
-.BR SAVE_PHFIG (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/LOTRS.3 b/alliance/share/man/man3/LOTRS.3
deleted file mode 100644
index c6f1fe67..00000000
--- a/alliance/share/man/man3/LOTRS.3
+++ /dev/null
@@ -1,92 +0,0 @@
-.\"   $Id: LOTRS.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)LOTRS.3 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-LOTRS
-.XE \}
-.TH LOTRS 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-LOTRS \- adds a logical transistor to the current netlist figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void LOTRS(type,width,length,grid,source,drain)
-char type;
-long width, length;
-char \(**grid, \(**source, \(**drain;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fItype\fP
-Type of the transistor to be created in the current figure
-.TP
-\fIwidth, length\fP
-Size of the transistor
-.TP
-\fIgrid, source, drain\fP
-Name of the signals on which the given transitor connector are to be linked
-.SH DESCRIPTION
-\fBLOTRS\fP add a logical transistor to the current
-working figure. This transitor has each of its pin logicaly linked to the signal
-adequat signal given as parameter.
-The \fItype\fP attribut may take the following values:
-.TP
-\fBTRANSN\fP
-for a N type mos transistor.
-.TP
-\fBTRANSP\fP 
-for a P type mos transistor.
-.SH ERROR
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"LOTRS impossible : missing DEF_LOFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_LOFIG\fP. So it isn't
-possible to add anything. you must call \fBDEF_LOFIG\fP before any other
-netlist call.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on, an inverter  \(**/
-	DEF_LOFIG("n1");
-	/\(** define interface  \(**/
-	LOCON("i", IN, "input");
-	LOCON("f", OUT, "output");
-	LOCON("vdd", IN, "vdd");
-	LOCON("vss", IN, "vss");
-	/\(** Place transistors \(**/
-	LOTRS(TRANSP, 5, 4, "input", "vdd", "output");
-	LOTRS(TRANSN, 2, 4, "input", "vss", "output");
-	/\(** Save all that on disk \(**/
-	SAVE_LOFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR BUS (3),
-.BR ELM (3),
-.BR LOINS (3),
-.BR LOCON (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/OUTLINE.3 b/alliance/share/man/man3/OUTLINE.3
deleted file mode 100644
index 3b1f3f55..00000000
--- a/alliance/share/man/man3/OUTLINE.3
+++ /dev/null
@@ -1,56 +0,0 @@
-.\"   $Id: OUTLINE.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)OUTLINE.3 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-OUTLINE
-.XE \}
-.TH OUTLINE 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-OUTLINE \- build an outline from the current layout cell
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void OUTLINE();
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH DESCRIPTION
-\fBOUTLINE\fP build a black box from a layout.
-After a call to \fBOUTLINE\fP, the figure has only its abutment box,
-its connectors, references and feed through.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("cell");
-	/\(** Place an instance \(**/
-	PLACE("model","i1", NOSYM,0L,0L);
-	PLACE("model","i2", NOSYM,120L,40L);
-	DEF_PHINS("i1");
-	PLACE_TOP("model2", "i3", NOSYM);
-	/\(** define the new abutment box as the standard envelop \(**/
-	DEF_AB(0, 0, 0, 0);
-	OUTLINE();
-	/\(** Save all that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/OpenVerticalChannel.3 b/alliance/share/man/man3/OpenVerticalChannel.3
deleted file mode 100644
index 1c4e5ae7..00000000
--- a/alliance/share/man/man3/OpenVerticalChannel.3
+++ /dev/null
@@ -1,80 +0,0 @@
-.\"   $Id: OpenVerticalChannel.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)OpenVerticalChannel.2 1.0 93/10/07 ; Labo masi cao-vlsi; Author : Xavier Picat
-.TH OPENVERTICALCHANNEL 3 "October 1, 1997" "ASIM/LIP6" "APR FUNCTIONS"
-
-.SH NAME
-OpenVerticalChannel  -open a vertical channel inside a phfig
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aprnnn.h"
-phfig_list \fB*OpenVerticalChannel\fP(ptfig,x,epsilon,width)
-phfig_list    \(**ptfig;
-unsigned long  x;
-unsigned long  epsilon;
-unsigned long  width;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIptfig\fP
-Name of the figure to be created
-.TP 20
-\fIx\fP
-Where the channel must be opened
-.TP 20
-\fIepsilon\fP
-How much x can be changed
-.TP 20
-\fIwidth\fP
-Width of the channel
-.SH DESCRIPTION
-\fBOpenVerticalChannel\fP shifts toward the right all the instances
-of \fIptfig\fP, which have an \fIXINS\fP greater than the \fIx\fP
-passed. The value of the shift is determined by the fact that none
-of the instances which will have an \fIXINS\fP greater than \fIx\fP
-must overlap. If epsilon doesn't equal zero, \fBOpenVerticalChannel\fP
-looks at all the positions between \fIx\fP-\fIepsilon\fP and
-\fIx\fP+\fIepsilon\fP, so that the gap created by the channel is the
-smallest possible. The \fIwidth\fP is added to the shift to find of
-how much the \fIXINS\fP of the instances which are to be moved must
-be increased. 
-.br
-\fIx\fP, \fIepsilon\fP and \fIwidth\fP must be a multiple of PITCH_X (defined in
-scr.h).
-.br
-The least value recommended for \fIepsilon\fP is half the width of the largest
-instance.
-.br
-Opening a channel is very fast (less than a second for 10 000 instances).
-.br
-\fBOpenVerticalChannel\fP returns a pointer to the modified \fIphfig\fP
-.SH EXAMPLE
-.IP
-#include "aprnnn.h"
-.br
-phfig_list (*open_in_middle(ptfig)
-.br
-phfig_list *ptfig;
-.br
-{
-.br
-	long x;
-.br
-	x = (ptphfig->XAB2-ptphfig->XAB1)>>1;
-.br
-	x = x - x%PITCH_X;
-.br
-	return (OpenVerticalChannel (ptfig,x, 5*PITCH_X, 10*PITCH_X));
-.br
-}
-.SH SEE ALSO
-.BR apr(3)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/PHCON.3 b/alliance/share/man/man3/PHCON.3
deleted file mode 100644
index 8b737a3d..00000000
--- a/alliance/share/man/man3/PHCON.3
+++ /dev/null
@@ -1,174 +0,0 @@
-.\"   $Id: PHCON.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)PHCON.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-PHCON
-.XE \}
-.TH PHCON 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-PHCON \- place a physical connector in the current figure at absolute coordinates
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void PHCON(layer, width, name, orient, x, y)
-char layer;
-long width;
-char \(**name, orient;
-long x, y;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIlayer\fP
-Layout layer of the connector
-.TP
-\fIwidth\fP
-Width of the connector
-.TP
-\fIname\fP
-Name to be given to the connector
-.TP
-\fIorient\fP
-Face of the cell on witch the connector belongs
-.TP
-\fIx, y\fP
-Absolute coordinates of the connector
-.SH DESCRIPTION
-\fBPHCON\fP adds a connector in the current layout cell, at the specified
-coordinates, with the given attributs.
-The \fIlayer\fP argument can take the following legal values:
-.RS
-.TP
-\fBNWELL\fP 
-.TP
-\fBPWELL\fP 
-.TP
-\fBNTIE\fP 
-.TP
-\fBPTIE\fP 
-.TP
-\fBNDIF\fP 
-.TP
-\fBPDIF\fP 
-.TP
-\fBNTRANS\fP 
-.TP
-\fBPTRANS\fP 
-.TP
-\fBPOLY\fP 
-.TP
-\fBALU1\fP 
-.TP
-\fBALU2\fP 
-.TP
-\fBALU3\fP 
-.TP
-\fBTPOLY\fP 
-.TP
-\fBTALU1\fP 
-.TP
-\fBTALU2\fP 
-.TP
-\fBTALU3\fP 
-.RE
-.LP
-The name argument is not enough of an information to non ambigiously identify
-a connector.
-In order to be able to do so, an \fIindex\fP is computed for each connector
-that has an already existing name, following a topological order.
-Each time a connector is created, the \fIindex\fP is updated, regarding the
-name of the connector.
-Since someone writting a tiler needs to know exactly what connector to access,
-the indexation algorithm must be known by the user.
-.TP 20
-Connectors with a unique name:
-Such connectors have the index \fB0\fP
-.TP 20
-Connectors with a name apearing many times:
-The indexes are computed from left to right, and then from bottom to top,
-starting at \fB0\fP. 
-If two connectors are on the same location, with the same name, then the
-\fIlayer\fP decides which one is has the greater number, from lower level,
-\fBNWELL\fP to upper level, \fBALU3\fP.
-.LP
-The \fIorient\fP paramater may take the following values:
-.TP 20
-\fBNORTH\fP
-for a connector placed on the top of the cell.
-.TP
-\fBSOUTH\fP
-for a connector placed on the bottom of the cell.
-.TP
-\fBEAST\fP
-for a connector placed on the right side of the cell.
-.TP
-\fBWEST\fP
-for a connector placed on the left side of the cell.
-.TP
-Remark:
-Connectors placed on corners of leaf cells are given the \fBEAST\fP orientation
-if on top/right or bottom/right corner, and \fBWEST\fP if top/left or
-bottom/left.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"PHCON impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a connector inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal addphcon : orientation is XX in \fIname\fP"
-.ft R
-.RS
-The \fIorient\fP parameter does not have a legal value, but \fIXX\fP.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("cell");
-	.
-	.
-	.
-	DEF_AB(0L, 0L, 0L, 0L);
-	/\(** Put a connector \(**/
-	PHCON(ALU1, 1, "cin", SOUTH, 12L, 0L);
-	/\(** Save that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHFIG (3),
-.BR SAVE_PHFIG (3),
-.BR COPY_UP_ALL_CON (3),
-.BR COPY_UP_CON (3),
-.BR COPY_UP_CON_FACE (3),
-.BR THRU_CON_H (3),
-.BR THRU_CON_V (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/PHREF.3 b/alliance/share/man/man3/PHREF.3
deleted file mode 100644
index 28d87c27..00000000
--- a/alliance/share/man/man3/PHREF.3
+++ /dev/null
@@ -1,96 +0,0 @@
-.\"   $Id: PHREF.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)PHREF.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-PHREF
-.XE \}
-.TH PHREF 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-PHREF \- place a physical reference in the current figure at absolute
-coordinates
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void PHREF(type, name, x, y)
-char \(**type, \(**name;
-long x, y;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fItype\fP
-Type of the reference to be added
-.TP
-\fIname\fP
-Name of the reference
-.TP
-\fIx, y\fP
-Absolute coordinates of the reference
-.SH DESCRIPTION
-\fBPHREF\fP adds a reference in the current layout cell, at the specified
-coordinates.
-A reference is an object that allows to symbolicaly name a point for
-futur use by the designer.
-They have been mainly used in the past to \fIprogram\fP decoders, in order
-to obtain many cells from a unique cell.
-.LP
-The \fItype\fP argument may take the two following legal values:
-.TP 20
-\fBref_con\fP 
-for virtual connectors, see \fBdpr\fP(1) for details.
-.TP
-\fBref_ref\fP 
-for any other need from the designer.
-.LP
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"PHREF impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a reference inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("cell");
-	.
-	/\(** Put a reference \(**/
-	PHREF("ref_con", "in_a[0]", 102L, 10L);
-	.
-	.
-	DEF_AB(0L, 0L, 0L, 0L);
-	/\(** Save that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHFIG (3),
-.BR SAVE_PHFIG (3),
-.BR PLACE_CON_REF (3),
-.BR PLACE_SEG_REF (3),
-.BR PLACE_VIA_REF (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/PHSEG.3 b/alliance/share/man/man3/PHSEG.3
deleted file mode 100644
index 712c0d7f..00000000
--- a/alliance/share/man/man3/PHSEG.3
+++ /dev/null
@@ -1,137 +0,0 @@
-.\"   $Id: PHSEG.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)PHSEG.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-PHSEG
-.XE \}
-.TH PHSEG 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-PHSEG \- place a physical segment in the current figure at absolute coordinates
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void PHSEG(layer, width, name, x1, y1, x2, y2)
-char layer;
-long width;
-char \(**name;
-long x1, y1, x2, y2;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIlayer\fP
-Layout layer of the segment
-.TP
-\fIwidth\fP
-Width of the segment
-.TP
-\fIname\fP
-Name to be given to the segment
-.TP
-\fIx1, y1, x2, y2\fP
-Coordinates of the segment's end points in the current figure
-.SH DESCRIPTION
-\fBPHSEG\fP adds a segment in the current layout cell, at the specified
-coordinates, with the given attributs.
-The \fIlayer\fP argument can take the following legal values :
-.RS
-.TP
-\fBNWELL\fP 
-.TP
-\fBPWELL\fP 
-.TP
-\fBNTIE\fP 
-.TP
-\fBPTIE\fP 
-.TP
-\fBNDIF\fP 
-.TP
-\fBPDIF\fP 
-.TP
-\fBNTRANS\fP 
-.TP
-\fBPTRANS\fP 
-.TP
-\fBPOLY\fP 
-.TP
-\fBALU1\fP 
-.TP
-\fBALU2\fP 
-.TP
-\fBALU3\fP 
-.TP
-\fBTPOLY\fP 
-.TP
-\fBTALU1\fP 
-.TP
-\fBTALU2\fP 
-.TP
-\fBTALU3\fP 
-.RE
-.LP
-The name argument needs not to be specified, since one usually doesn't need to
-give a segment a name. To do so, just type "" as name.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"PHSEG impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place an instance inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal addphseg : x1, y1, x2, y2"
-.ft R
-.RS
-A symbolic segment must be either vertical or horizontal, so either
-\fIx1 = x2\fP, or \fIy1 = y2\fP.
-.RE
-.br
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("cell");
-	/\(** Put a segment \(**/
-	PHSEG(ALU1, 1, "", 0L, 0L, 12L, 0L);
-	/\(** Save that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHFIG (3),
-.BR SAVE_PHFIG (3),
-.BR COPY_UP_SEG (3),
-.BR THRU_H (3),
-.BR THRU_CON_H (3),
-.BR THRU_V (3),
-.BR THRU_CON_V (3),
-.BR WIRE1 (3),
-.BR WIRE2 (3),
-.BR WIRE3 (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/PHVIA.3 b/alliance/share/man/man3/PHVIA.3
deleted file mode 100644
index 9731635d..00000000
--- a/alliance/share/man/man3/PHVIA.3
+++ /dev/null
@@ -1,114 +0,0 @@
-.\"   $Id: PHVIA.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)PHVIA.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-PHVIA
-.XE \}
-.TH PHVIA 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-PHVIA \- place a physical via in the current figure at absolute coordinates
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void PHVIA(type, x, y)
-char type;
-long x, y;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fItype\fP
-Type of the contact to be made
-.TP
-\fIx, y\fP
-Absolute coordinates of the via
-.SH DESCRIPTION
-\fBPHVIA\fP adds a via in the current layout cell, at the specified
-coordinates.
-The \fItype\fP argument may take the following legal values:
-.TP 20
-\fBCONT_POLY\fP 
-links \fBPOLY\fP and \fBALU1\fP
-.TP
-\fBCONT_DIF_N\fP 
-links \fBNDIF\fP and \fBALU1\fP
-.TP
-\fBCONT_DIF_P\fP 
-links \fBPDIF\fP and \fBALU1\fP
-.TP
-\fBCONT_BODY_N\fP 
-links \fBNTIE\fP and \fBALU1\fP
-.TP
-\fBCONT_BODY_P\fP 
-links \fBPTIE\fP and \fBALU1\fP
-.TP
-\fBCONT_VIA\fP 
-links \fBALU1\fP and \fBALU2\fP
-.TP
-\fBCONT_VIA2\fP 
-links \fBALU2\fP and \fBALU3\fP
-.TP
-\fBC_X_N\fP 
-corner for L-shaped (and S-shaped) N transistor
-.TP
-\fBC_X_P\fP 
-corner for L-shaped (and S-shaped) P transistor
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"PHVIA impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a via inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal addphvia : type is XX  at \fIx, y\fP"
-.ft R
-.RS
-The \fItype\fP parameter does not have a legal value, but \fIXX\fP.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("cell");
-	.
-	/\(** Put a via \(**/
-	PHVIA(CONT_VIA, 12L, 10L);
-	.
-	.
-	DEF_AB(0L, 0L, 0L, 0L);
-	/\(** Save that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHFIG (3),
-.BR SAVE_PHFIG (3),
-.BR PLACE_VIA_REF (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/PLACE.3 b/alliance/share/man/man3/PLACE.3
deleted file mode 100644
index 6cce5a95..00000000
--- a/alliance/share/man/man3/PLACE.3
+++ /dev/null
@@ -1,137 +0,0 @@
-.\"   $Id: PLACE.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)PLACE.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-PLACE
-.XE \}
-.TH PLACE 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-PLACE \- place a physical instance in the current figure at absolute coordinates
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void PLACE(modelname, insname, symetry, x, y)
-char \(**modelname, \(**insname;
-char symetry;
-long x,y;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fImodelname\fP
-Name of the layout figure to be instanciated
-.TP
-\fIinsname\fP
-Name to be given to the instance on the model
-.TP
-\fIsymetry\fP
-Geometrical operation to be performed on the instance before beeing placed
-.TP
-\fIx, y\fP
-Coordinates of the lower left corner of the abutment box on the instance in
-the current figure
-.SH DESCRIPTION
-\fBPLACE\fP add an instance in the current layout cell. The bottom left corner
-of the instance of the model \fImodelname\fP is placed, after beeing
-symetrized and/or rotated, at \fI(x, y)\fP coordinates. 
-The placed instance becomes the new "reference instance", used in
-the relative placement functions.
-.br
-The \fIinsname\fP is the name given to the instance and must be unique at
-a given hierarchy level.
-.br
-The \fIsymetry\fP argument can take eight legal values :
-.TP 20
-\fBNOSYM\fP 
-no geometrical operation is performed
-.TP
-\fBSYM_Y\fP 
-Y becomes -Y, that means toward X axe symetry
-.TP
-\fBSYM_X\fP 
-X becomes -X, that means toward Y axe symetry
-.TP
-\fBSYMXY\fP 
-X becomes -X, Y becomes -Y
-.TP
-\fBROT_P\fP 
-a positive 90 degrees rotation take place
-.TP
-\fBROT_M\fP 
-a negative 90 degrees rotation take place
-.TP
-\fBSY_RP\fP 
-Y becomes -Y, and then a positive 90 degrees rotation take place
-.TP
-\fBSY_RM\fP 
-Y becomes -Y, and then a negative 90 degrees rotation take place
-.PP
-The model of the figure to be placed must be available, on disk or in memory.
-The path to the library is specified in the \fBMBK_CATA_LIB\fP (1) and
-\fBMBK_WORK_LIB\fP (1) environment
-variables, and its format is given by the \fBMBK_IN_PH\fP (1) environment
-variable.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"PLACE impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place an instance inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal addphins : transformation is x in insname"
-.ft R
-.RS
-The \fIsymetry\fP parameter is not one of the define given, but has the
-integer value \fBx\fP.
-.RE
-.br
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("cell");
-	/\(** Place two instances \(**/
-	PLACE("gapg0_b","ins1", NOSYM, 0L, 0L);
-	PLACE("gapg8_b","ins2", SYM_X, 80L, 100L);
-	/\(** Save all that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHFIG (3),
-.BR SAVE_PHFIG (3),
-.BR PLACE_TOP (3),
-.BR PLACE_BOTTOM (3),
-.BR PLACE_LEFT (3),
-.BR PLACE_RIGHT (3),
-.BR MBK_CATA_LIB (1),
-.BR MBK_WORK_LIB (1),
-.BR MBK_IN_PH (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/PLACE_BOTTOM.3 b/alliance/share/man/man3/PLACE_BOTTOM.3
deleted file mode 100644
index aa1554c7..00000000
--- a/alliance/share/man/man3/PLACE_BOTTOM.3
+++ /dev/null
@@ -1,146 +0,0 @@
-.\"   $Id: PLACE_BOTTOM.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)PLACE_BOTTOM.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-PLACE_BOTTOM
-.XE \}
-.TH PLACE_BOTTOM 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-PLACE_BOTTOM \- place a physical instance in the current figure under
-the "reference instance"
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void PLACE_BOTTOM(modelname, insname, symetry)
-char \(**modelname, \(**insname;
-char symetry;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fImodelname\fP
-Name of the layout figure to be instanciated
-.TP
-\fIinsname\fP
-Name to be given to the instance on the model
-.TP
-\fIsymetry\fP
-Geometrical operation to be performed on the instance before beeing placed
-.SH DESCRIPTION
-\fBPLACE_BOTTOM\fP add a instance of model \fImodelname\fP
-in the current layout cell.
-The bottom left corner
-of the abutment box of the instance is placed, after beeing symetrized
-and/or rotated,
-toward the bottom left corner of the abutment box of the
-"reference instance". The newly
-placed instance becomes the "reference instance".
-.br
-The \fIinsname\fP is the name given to the instance and must be unique at
-a given hierarchy level.
-.br
-The \fIsymetry\fP argument can take eight legal values :
-.TP 20
-\fBNOSYM\fP
-no geometrical operation is performed
-.TP
-\fBSYM_Y\fP 
-Y becomes -Y, that means toward X axe symetry
-.TP
-\fBSYM_X\fP 
-X becomes -X, that means toward Y axe symetry
-.TP
-\fBSYMXY\fP 
-X becomes -X, Y becomes -Y
-.TP
-\fBROT_P\fP 
-a positive 90 degrees rotation take place
-.TP
-\fBROT_M\fP 
-a negative 90 degrees rotation take place
-.TP
-\fBSY_RP\fP 
-Y becomes -Y, and then a positive 90 degrees rotation take place
-.TP
-\fBSY_RM\fP 
-Y becomes -Y, and then a negative 90 degrees rotation take place
-.PP
-The model of the figure to be placed must be available, on disk or in memory.
-The path to the library is specified in the \fBMBK_CATA_LIB\fP (1) and
-\fBMBK_WORK_LIB\fP (1) environment
-variables, and its format is given by the \fBMBK_IN_PH\fP (1) environment
-variable.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"PLACE_BOTTOM impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place an instance inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"PLACE_BOTTOM impossible : No previous instance"
-.ft R
-.RS
-There are no instances placed in the current layout cell, so it's
-impossible to know where to place from. Use a \fBPLACE\fP call before.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal addphins : transformation is x in insname"
-.ft R
-.RS
-The \fIsymetry\fP parameter is not one of the define given, but has the
-integer value \fBx\fP.
-.RE
-.br
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHSC("cell");
-	/\(** Place two instances \(**/
-	PLACE_PLACE("grbos", "ins1", SYMXY, -3L, 0L);
-	PLACE_BOTTOM("gln", "ins2", NOSYM);
-	/\(** Save all that on disk \(**/
-	SAVE_PHSC();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHFIG (3),
-.BR SAVE_PHFIG (3),
-.BR PLACE (3),
-.BR PLACE_TOP (3),
-.BR PLACE_RIGHT (3),
-.BR PLACE_LEFT (3),
-.BR MBK_CATA_LIB (1),
-.BR MBK_WORK_LIB (1),
-.BR MBK_IN_PH (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/PLACE_CON_REF.3 b/alliance/share/man/man3/PLACE_CON_REF.3
deleted file mode 100644
index 9c808334..00000000
--- a/alliance/share/man/man3/PLACE_CON_REF.3
+++ /dev/null
@@ -1,173 +0,0 @@
-.\"   $Id: PLACE_CON_REF.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)PLACE_CON_REF.3 2.11 01/92; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-PLACE_CON_REF
-.XE \}
-.TH PLACE_CON_REF 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-PLACE_CON_REF \- put a connector on top of a reference belonging an
-instance in the current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void PLACE_CON_REF(insname, refname, conname, layer, width, face)
-char  \(**insname, \(**refname, \(**conname;
-char layer, face;
-long width;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIinsname\fP
-Name of the instance in the which the reference is to be searched for
-.TP
-\fIrefname\fP
-Name of the reference to be used for the connector placement
-.TP
-\fIconname\fP
-Name of the connector to be placed
-.TP
-\fIlayer\fP
-Physical layer of the connector
-.TP
-\fIwidth\fP
-Width of the connector
-.TP
-\fIface\fP
-Face of the figure on which the connector is to be placed
-.SH DESCRIPTION
-\fBPLACE_CON_REF\fP places a connector called \fIconname\fP ragarding the
-position of the reference, \fIrefname\fP, in the instance called \fIinsname\fP.
-The connector coordinates are computed from the reference coordinates and
-the face given as argument.
-.br
-Two behaviours are expected, regarding the reference coordinates:
-.TP 20
-the reference is on the given face of the \fIabutment box\fP
-a connector called \fIconname\fP is added on top of the reference, with
-the given \fIlayer\fP and \fIwidth\fP.
-.TP
-the reference is anywhere else
-a connector called \fIconname\fP is added on the given face, \fIface\fP, of the
-\fIabutment box\fP, at the y coordinates of the reference if the \fIface\fP
-is \fBEAST\fP or \fBWEST\fP, or x one if the \fIface\fP is \fBNORTH\fP or
-\fBSOUTH\fP. Then a segment is drawn between the reference and the connector.
-All drawn objects are given \fIlayer\fP and \fIwidth\fP as caracteristics.
-.br
-The \fIface\fP argument is meant in the placed instance, and can take any of
-the following values:
-.TP 20
-\fBNORTH\fP
-for a connector placed on the top of the cell.
-.TP
-\fBSOUTH\fP
-for a connector placed on the bottom of the cell.
-.TP
-\fBEAST\fP
-for a connector placed on the right side of the cell.
-.TP
-\fBWEST\fP
-for a connector placed on the left side of the cell.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"PLACE_CON_REF impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a reference inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"PLACE_CON_REF impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a reference inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"PLACE_CON_REF impossible : no abutment box"
-.ft R
-.RS
-The current figure does not have an \fIabutment box\fI. Use \fIDEF_AB\fP(3)
-before this function.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal PLACE_CON_REF : orientation is XX"
-.ft R
-.RS
-The \fIface\fP parameter does not have a legal value, but \fIXX\fP.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphins : instance called \fIinsname\fP does not exist"
-.ft R
-.RS
-No instance called \fIinsname\fP exists in the current figure
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphref : references called \fIrefname\fP does not exist"
-.ft R
-.RS
-No reference called \fIrefname\fP exists in the model of the instance
-\fIinsname\fP.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("cell");
-	PLACE("gaci0_b", "r1", NOSYM, 23L, 54L);
-	/\(** Put a reference \(**/
-	PLACE_CON_REF("r1", "a_0", ALU2, 2, NORTH);
-	/\(** Save that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHFIG (3),
-.BR SAVE_PHFIG (3),
-.BR PHREF (3),
-.BR PHCON (3),
-.BR COPY_UP_REF (3),
-.BR COPY_UP_ALL_REF (3),
-.BR PLACE_CON_REF (3),
-.BR PLACE_SEG_REF (3),
-.BR PLACE_CON_REF (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/PLACE_LEFT.3 b/alliance/share/man/man3/PLACE_LEFT.3
deleted file mode 100644
index 720c86c8..00000000
--- a/alliance/share/man/man3/PLACE_LEFT.3
+++ /dev/null
@@ -1,146 +0,0 @@
-.\"   $Id: PLACE_LEFT.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)PLACE_LEFT.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-PLACE_LEFT
-.XE \}
-.TH PLACE_LEFT 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-PLACE_LEFT \- place a physical instance in the current figure at the left of the
-"reference instance"
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void PLACE_LEFT(modelname, insname, symetry)
-char \(**modelname, \(**insname;
-char symetry;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fImodelname\fP
-Name of the layout figure to be instanciated
-.TP
-\fIinsname\fP
-Name to be given to the instance on the model
-.TP
-\fIsymetry\fP
-Geometrical operation to be performed on the instance before beeing placed
-.SH DESCRIPTION
-\fBPLACE_LEFT\fP add an instance of model \fImodelname\fP
-in the current layout cell.
-The bottom right corner
-of the abutment box of the instance is placed, after beeing symetrized
-and/or rotated,
-toward the bottom left corner of the abutment box of the
-"reference instance". The newly
-placed instance becomes the "reference instance".
-.br
-The \fIinsname\fP is the name given to the instance and must be unique at
-a given hierarchy level.
-.br
-The \fIsymetry\fP argument can take eight legal values :
-.TP 20
-\fBNOSYM\fP
-no geometrical operation is performed
-.TP
-\fBSYM_Y\fP
-Y becomes -Y, that means toward X axe symetry
-.TP
-\fBSYM_X\fP
-X becomes -X, that means toward Y axe symetry
-.TP
-\fBSYMXY\fP
-X becomes -X, Y becomes -Y
-.TP
-\fBROT_P\fP
-a positive 90 degrees rotation take place
-.TP
-\fBROT_M\fP
-a negative 90 degrees rotation take place
-.TP
-\fBSY_RP\fP
-Y becomes -Y, and then a positive 90 degrees rotation take place
-.TP
-\fBSY_RM\fP
-Y becomes -Y, and then a negative 90 degrees rotation take place
-.PP
-The model of the figure to be placed must be available, on disk or in memory.
-The path to the library is specified in the \fBMBK_CATA_LIB\fP (1) and
-\fBMBK_WORK_LIB\fP (1) environment
-variables, and its format is given by the \fBMBK_IN_PH\fP (1) environment
-variable.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"PLACE_LEFT impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place an instance inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"PLACE_LEFT impossible : No previous instance"
-.ft R
-.RS
-There are no instances placed in the current layout cell, so it's
-impossible to know where to place from. Use a \fBPLACE\fP call before.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal addphins : transformation is x in insname"
-.ft R
-.RS
-The \fIsymetry\fP parameter is not one of the define given, but has the
-integer value \fBx\fP.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("cell");
-	/\(** Place two instances \(**/
-	PLACE("grbdo_3","ins1", NOSYM, 0L, 0L);
-	/\(** negative placement values are allowed \(**/
-	PLACE_LEFT("grxwh_k","ins2", SYMXY);
-	/\(** Save all that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHFIG (3),
-.BR SAVE_PHFIG (3),
-.BR PLACE (3),
-.BR PLACE_TOP (3),
-.BR PLACE_BOTTOM (3),
-.BR PLACE_RIGHT (3),
-.BR MBK_CATA_LIB (1),
-.BR MBK_WORK_LIB (1),
-.BR MBK_IN_PH (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/PLACE_ON.3 b/alliance/share/man/man3/PLACE_ON.3
deleted file mode 100644
index bd8dfc73..00000000
--- a/alliance/share/man/man3/PLACE_ON.3
+++ /dev/null
@@ -1,152 +0,0 @@
-.\"   $Id: PLACE_ON.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)PLACE_ON.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-PLACE_ON
-.XE \}
-.TH PLACE_ON 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-PLACE_ON \- place a physical instance in the current figure matching
-connectors
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void PLACE_ON(figname,ins1,con1,index1,symetry,ins2,con2,index2)
-char \(**figname, \(**ins1, \(**con1, \(**ins2, \(**con2;
-char symetry;
-long index1, index2;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIfigname\fP
-Name of the layout figure to be instanciated
-.TP
-\fIins1\fP
-Name to be given to the instance in the model
-.TP
-\fIcon1\fP
-Name of the connector of the instance to be used for placement
-.TP
-\fIindex1\fP
-Index of the connector, or reference, \fIcon1\fP of the model to be used
-for placement
-.TP
-\fIsymetry\fP
-Geometrical operation to be performed on the instance before beeing placed
-.TP
-\fIins2\fP
-Name of the instance to be used for relative placement
-.TP
-\fIcon2\fP
-Name of the connector of the instance \fIins2\fP on which the placement will
-take place
-.TP
-\fIindex2\fP
-Index of the connector \fIcon2\fP of the instance to be used for relative
-placement
-.SH DESCRIPTION
-\fBPLACE_ON\fP add an instance in the current layout cell. The bottom left corner
-of the instance of the model \fImodelname\fP is placed, after beeing
-symetrized and/or rotated, at \fI(x, y)\fP coordinates. 
-The placed instance becomes the new "reference instance", used in
-the relative placement functions.
-.br
-The \fIinsname\fP is the name given to the instance and must be unique at
-a given hierarchy level.
-.br
-The \fIsymetry\fP argument can take eight legal values :
-.TP 20
-\fBNOSYM\fP 
-no geometrical operation is performed
-.TP
-\fBSYM_Y\fP 
-Y becomes -Y, that means toward X axe symetry
-.TP
-\fBSYM_X\fP 
-X becomes -X, that means toward Y axe symetry
-.TP
-\fBSYMXY\fP 
-X becomes -X, Y becomes -Y
-.TP
-\fBROT_P\fP 
-a positive 90 degrees rotation take place
-.TP
-\fBROT_M\fP 
-a negative 90 degrees rotation take place
-.TP
-\fBSY_RP\fP 
-Y becomes -Y, and then a positive 90 degrees rotation take place
-.TP
-\fBSY_RM\fP 
-Y becomes -Y, and then a negative 90 degrees rotation take place
-.PP
-The model of the figure to be placed must be available, on disk or in memory.
-The path to the library is specified in the \fBMBK_CATA_LIB\fP (1) and
-\fBMBK_WORK_LIB\fP (1) environment
-variables, and its format is given by the \fBMBK_IN_PH\fP (1) environment
-variable.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"PLACE_ON impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place an instance inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal addphins : transformation is x in insname"
-.ft R
-.RS
-The \fIsymetry\fP parameter is not one of the define given, but has the
-integer value \fBx\fP.
-.RE
-.br
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("cell");
-	/\(** Place two instances \(**/
-	PLACE_ON("gapg0_b","ins1", NOSYM, 0L, 0L);
-	PLACE_ON("gapg8_b","ins2", SYM_X, 80L, 100L);
-	/\(** Save all that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHFIG (3),
-.BR SAVE_PHFIG (3),
-.BR PLACE_TOP (3),
-.BR PLACE_BOTTOM (3),
-.BR PLACE_LEFT (3),
-.BR PLACE_RIGHT (3),
-.BR MBK_CATA_LIB (1),
-.BR MBK_WORK_LIB (1),
-.BR MBK_IN_PH (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/PLACE_RIGHT.3 b/alliance/share/man/man3/PLACE_RIGHT.3
deleted file mode 100644
index 46ec959b..00000000
--- a/alliance/share/man/man3/PLACE_RIGHT.3
+++ /dev/null
@@ -1,145 +0,0 @@
-.\"   $Id: PLACE_RIGHT.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)PLACE_RIGHT.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-PLACE_RIGHT
-.XE \}
-.TH PLACE_RIGHT 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-PLACE_RIGHT \- place a physical instance in the current figure at
-the right of the "reference instance"
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void PLACE_RIGHT(modelname, insname, symetry)
-char \(**modelname, \(**insname;
-char symetry;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fImodelname\fP
-Name of the layout figure to be instanciated
-.TP
-\fIinsname\fP
-Name to be given to the instance on the model
-.TP
-\fIsymetry\fP
-Geometrical operation to be performed on the instance before beeing placed
-.SH DESCRIPTION
-\fBPLACE_RIGHT\fP add an instance of model \fImodelname\fP
-in the current layout cell.
-The bottom left corner
-of the abutment box of the instance is placed, after beeing symetrized
-and/or rotated,
-toward the bottom right corner of the abutment box of the
-"reference instance". The newly
-placed instance becomes the "reference instance".
-.br
-The \fIinsname\fP is the name given to the instance and must be unique at
-a given hierarchy level.
-.br
-The \fIsymetry\fP argument can take eight legal values :
-.TP 20
-\fBNOSYM\fP
-no geometrical operation is performed
-.TP
-\fBSYM_Y\fP
-Y becomes -Y, that means toward X axe symetry
-.TP
-\fBSYM_X\fP
-X becomes -X, that means toward Y axe symetry
-.TP
-\fBSYMXY\fP
-X becomes -X, Y becomes -Y
-.TP
-\fBROT_P\fP
-a positive 90 degrees rotation take place
-.TP
-\fBROT_M\fP
-a negative 90 degrees rotation take place
-.TP
-\fBSY_RP\fP
-Y becomes -Y, and then a positive 90 degrees rotation take place
-.TP
-\fBSY_RM\fP
-Y becomes -Y, and then a negative 90 degrees rotation take place
-.PP
-The model of the figure to be placed must be available, on disk or in memory.
-The path to the library is specified in the \fBMBK_CATA_LIB\fP (1) and
-\fBMBK_WORK_LIB\fP (1) environment
-variables, and its format is given by the \fBMBK_IN_PH\fP (1) environment
-variable.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"PLACE_RIGHT impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place an instance inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"PLACE_RIGHT impossible : No previous instance"
-.ft R
-.RS
-There are no instances placed in the current layout cell, so it's
-impossible to know where to place from. Use a \fBPLACE\fP call before.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal addphins : transformation is x in insname"
-.ft R
-.RS
-The \fIsymetry\fP parameter is not one of the define given, but has the
-integer value \fBx\fP.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("cell");
-	/\(** Place two instances \(**/
-	PLACE("rsa16","ins1", ROT_P, -5L, 5L);
-	PLACE_RIGHT("gnr32x16", "ins2", SYM_X);
-	/\(** Save all that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHFIG (3),
-.BR SAVE_PHFIG (3),
-.BR PLACE (3),
-.BR PLACE_TOP (3),
-.BR PLACE_BOTTOM (3),
-.BR PLACE_LEFT (3),
-.BR MBK_CATA_LIB (1),
-.BR MBK_WORK_LIB (1),
-.BR MBK_IN_PH (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/PLACE_SEG_REF.3 b/alliance/share/man/man3/PLACE_SEG_REF.3
deleted file mode 100644
index 4898c96d..00000000
--- a/alliance/share/man/man3/PLACE_SEG_REF.3
+++ /dev/null
@@ -1,175 +0,0 @@
-.\"   $Id: PLACE_SEG_REF.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)PLACE_SEG_REF.3 2.11 01/92; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-PLACE_SEG_REF
-.XE \}
-.TH PLACE_SEG_REF 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-PLACE_SEG_REF \- put a segment on a reference belonging an
-instance in the current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void PLACE_SEG_REF(insname, refname, layer, width, face)
-char  \(**insname, \(**refname;
-char layer, face;
-long width;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIinsname\fP
-Name of the instance in the which the reference is to be searched for
-.TP
-\fIrefname\fP
-Name of the reference to be used for the segment placement
-.TP
-\fIlayer\fP
-Physical layer of the segment
-.TP
-\fIwidth\fP
-Width of the segment
-.TP
-\fIface\fP
-Face of the figure on which the segment is to be placed
-.SH DESCRIPTION
-\fBPLACE_SEG_REF\fP places a segment regarding the position
-of the reference, \fIrefname\fP, in the instance called \fIinsname\fP.
-The segment coordinates are computed from the reference coordinates and
-the face given as argument.
-.br
-Two behaviours are expected, regarding the reference coordinates:
-.TP 20
-the reference is on the given face of the \fIabutment box\fP
-the segment is not added, since it would have zero as length
-.TP
-the reference is anywhere else
-A segment is drawn between the reference and the \fIabutment box\fP,  and is
-given \fIlayer\fP and \fIwidth\fP as attributs.
-One of its endpoint is given by the reference coordinates, the other one
-comes from the \fIface\fP.
-The \fIface\fP argument is meant in the placed instance, and can take any of
-the following values:
-.TP 20
-\fBNORTH\fP
-the other endpoint has, for absissa, the x coordinate of the top of the
-\fIabutment box\fP of the cell, and for ordinate, the y coordinate of
-the reference.
-.TP
-\fBSOUTH\fP
-the other endpoint has, for absissa, the x coordinate of the bottom of the
-\fIabutment box\fP of the cell, and for ordinate, the y coordinate of
-the reference.
-.TP
-\fBEAST\fP
-the other endpoint has, for absissa, the x coordinate of the reference and
-for ordinate, the y coordinate of the right of the \fIabutment box\fP of the
-cell.
-.TP
-\fBWEST\fP
-the other endpoint has, for absissa, the x coordinate of the reference and
-for ordinate, the y coordinate of the left of the \fIabutment box\fP of the
-cell.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"PLACE_SEG_REF impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a reference inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"PLACE_SEG_REF impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a reference inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"PLACE_SEG_REF impossible : no abutment box"
-.ft R
-.RS
-The current figure does not have an \fIabutment box\fI. Use \fIDEF_AB\fP(3)
-before this function.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal PLACE_SEG_REF : orientation is XX"
-.ft R
-.RS
-The \fIface\fP parameter does not have a legal value, but \fIXX\fP.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphins : instance called \fIinsname\fP does not exist"
-.ft R
-.RS
-No instance called \fIinsname\fP exists in the current figure
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphref : references called \fIrefname\fP does not exist"
-.ft R
-.RS
-No reference called \fIrefname\fP exists in the model of the instance
-\fIinsname\fP.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("cell");
-	PLACE("gaci0_b", "r1", NOSYM, 23L, 54L);
-	/\(** Put a reference \(**/
-	PLACE_SEG_REF("r1", "a_0", ALU2, 2, NORTH);
-	/\(** Save that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHFIG (3),
-.BR SAVE_PHFIG (3),
-.BR PHREF (3),
-.BR PHSEG (3),
-.BR COPY_UP_REF (3),
-.BR COPY_UP_ALL_REF (3),
-.BR PLACE_SEG_REF (3),
-.BR PLACE_SEG_REF (3),
-.BR PLACE_SEG_REF (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/PLACE_TOP.3 b/alliance/share/man/man3/PLACE_TOP.3
deleted file mode 100644
index b73d06f3..00000000
--- a/alliance/share/man/man3/PLACE_TOP.3
+++ /dev/null
@@ -1,146 +0,0 @@
-.\"   $Id: PLACE_TOP.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)PLACE_TOP.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-PLACE_TOP
-.XE \}
-.TH PLACE_TOP 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-PLACE_TOP \- place a physical instance in the current figure on the top of the
-"reference instance"
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void PLACE_TOP(modelname, insname, symetry)
-char \(**modelname, \(**insname;
-char symetry;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fImodelname\fP
-Name of the layout figure to be instanciated
-.TP
-\fIinsname\fP
-Name to be given to the instance on the model
-.TP
-\fIsymetry\fP
-Geometrical operation to be performed on the instance before beeing placed
-.SH DESCRIPTION
-\fBPLACE_TOP\fP add an instance of model \fImodelname\fP
-in the current layout cell.
-The bottom left corner
-of the abutment box of the instance is placed, after beeing symetrized
-and/or rotated,
-toward the top left corner of the abutment box of the
-"reference instance". The newly
-placed instance becomes the "reference instance".
-.br
-The \fIinsname\fP is the name given to the instance and must be unique at
-a given hierarchy level.
-.br
-The \fIsymetry\fP argument can take eight legal values :
-.TP 20
-\fBNOSYM\fP
-no geometrical operation is performed
-.TP
-\fBSYM_Y\fP 
-Y becomes -Y, that means toward X axe symetry
-.TP
-\fBSYM_X\fP 
-X becomes -X, that means toward Y axe symetry
-.TP
-\fBSYMXY\fP 
-X becomes -X, Y becomes -Y
-.TP
-\fBROT_P\fP 
-a positive 90 degrees rotation take place
-.TP
-\fBROT_M\fP 
-a negative 90 degrees rotation take place
-.TP
-\fBSY_RP\fP 
-Y becomes -Y, and then a positive 90 degrees rotation take place
-.TP
-\fBSY_RM\fP
-becomes -Y, and then a negative 90 degrees rotation take place
-.PP
-The model of the figure to be placed must be available, on disk or in memory.
-The path to the library is specified in the \fBMBK_CATA_LIB\fP (1) and
-\fBMBK_WORK_LIB\fP (1) environment
-variables, and its format is given by the \fBMBK_IN_PH\fP (1) environment
-variable.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"PLACE_TOP impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place an instance inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"PLACE_TOP impossible : No previous instance"
-.ft R
-.RS
-There are no instances placed in the current layout cell, so it's
-impossible to know where to place from. Use a \fBPLACE\fP call before.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal addphins : transformation is x in insname"
-.ft R
-.RS
-The \fIsymetry\fP parameter is not one of the define given, but has the
-integer value \fBx\fP.
-.RE
-.br
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("cell");
-	/\(** Place two instances \(**/
-	PLACE("dgl", "ins1", ROT_P, 0L, 0L);
-	PLACE_TOP("idv", "ins2", SY_RP);
-	/\(** Save all that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHFIG (3),
-.BR SAVE_PHFIG (3),
-.BR PLACE (3),
-.BR PLACE_RIGHT (3),
-.BR PLACE_BOTTOM (3),
-.BR PLACE_LEFT (3),
-.BR MBK_CATA_LIB (1),
-.BR MBK_WORK_LIB (1),
-.BR MBK_IN_PH (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/PLACE_VIA_REF.3 b/alliance/share/man/man3/PLACE_VIA_REF.3
deleted file mode 100644
index 50cc923e..00000000
--- a/alliance/share/man/man3/PLACE_VIA_REF.3
+++ /dev/null
@@ -1,130 +0,0 @@
-.\"   $Id: PLACE_VIA_REF.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)PLACE_VIA_REF.3 2.11 01/92; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-PLACE_VIA_REF
-.XE \}
-.TH PLACE_VIA_REF 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-PLACE_VIA_REF \- put a via on top of a reference belonging to an instance
-in the current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void PLACE_VIA_REF(insname, refname, viatype)
-char  \(**insname, \(**refname;
-char viatype;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIinsname\fP
-Name of the instance in the which the reference is to be searched for
-.TP
-\fIrefname\fP
-Name of the reference to be used as target point
-.TP
-\fIviatype\fP
-Type of via to be placed
-.SH DESCRIPTION
-\fBPLACE_VIA_REF\fP places a via of type \fIviatype\fP on top of the specified
-reference, \fIrefname\fP, in the instance called \fIinsname\fP.
-This function may be used to generate many cells from a single one, in order
-to "program" decoders for example, or in conjuction with \fBPLACE_SEG_REF\fP(3)
-or \fBPLACE_CON_REF\fP(3) to translate virtual connectors into fixed ones.
-.br
-The \fIviatype\fP argument may take the following legal values:
-.TP 20
-\fBCONT_POLY\fP 
-links \fBPOLY\fP and \fBALU1\fP
-.TP
-\fBCONT_DIF_N\fP 
-links \fBNDIF\fP and \fBALU1\fP
-.TP
-\fBCONT_DIF_P\fP 
-links \fBPDIF\fP and \fBALU1\fP
-.TP
-\fBCONT_BODY_N\fP 
-links \fBNTIE\fP and \fBALU1\fP
-.TP
-\fBCONT_BODY_P\fP 
-links \fBPTIE\fP and \fBALU1\fP
-.TP
-\fBCONT_VIA\fP 
-links \fBALU1\fP and \fBALU2\fP
-.TP
-\fBCONT_VIA2\fP 
-links \fBALU2\fP and \fBALU3\fP
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"PLACE_VIA_REF impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a reference inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphins : instance \fIinsname\fP does not exist"
-.ft R
-.RS
-The instance called \fIinsname\fP does not currently belong to the figure.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphref : references called \fIrefname\fP does not exist"
-.ft R
-.RS
-No reference called \fIrefname\fP exists in the model of the instance
-\fIinsname\fP.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("cell");
-	PLACE("gaci0_b", "r1", NOSYM, 23L, 54L);
-	/\(** Put a reference \(**/
-	PLACE_VIA_REF("a_0", "r1", CONT_VIA);
-	/\(** Save that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR dpr (1),
-.BR genlib (1),
-.BR DEF_PHFIG (3),
-.BR SAVE_PHFIG (3),
-.BR PHREF (3),
-.BR PHVIA (3),
-.BR COPY_UP_REF (3),
-.BR COPY_UP_ALL_REF (3),
-.BR PLACE_CON_REF (3),
-.BR PLACE_SEG_REF (3),
-.BR PLACE_VIA_REF (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/PMExpr.3 b/alliance/share/man/man3/PMExpr.3
deleted file mode 100644
index 9d7162d2..00000000
--- a/alliance/share/man/man3/PMExpr.3
+++ /dev/null
@@ -1,55 +0,0 @@
-.\"   $Id: PMExpr.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)PMExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH PMEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBPMExpr\fP \- returns 1 if the pattern matching is possible between two expressions.
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-int PMExpr(expr, pattern)
-chain_list *expr,*pattern;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIexpr\fP
-first expression
-.TP 20
-\fIpattern\fP
-pattern expression
-.SH DESCRIPTION
-\fBPMExpr()\fP returns 1 if the pattern matching is OK between \fIexpr\fP and \fIpattern\fP , in any other case, 0 is returned.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr1,*expr2; 
-
-expr1 = charToExpr("(or (and a b) (xor a d))");
-expr2 = charToExpr("(or (and x y) z)");
-printf("%d\n",PMExpr(expr1,expr2));
-/* it will display
-1
-*/
-freeExpr(expr2);
-expr2 = charToExpr("(or (and x y) (xor x y))");
-printf("%d\n",PMExpr(expr1,expr2));
-/* it will display
-0
-*/
-freeExpr(expr1);
-freeExpr(expr2);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR equalExpr (3),
-.BR equalVarExpr (3),
-.BR searchExpr (3),
-.BR searchOperExpr (3),
-.BR lengthExpr (3),
-.BR profExpr (3),
-.BR numberAtomExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/REVERSE_PHCON.3 b/alliance/share/man/man3/REVERSE_PHCON.3
deleted file mode 100644
index 07de2ae1..00000000
--- a/alliance/share/man/man3/REVERSE_PHCON.3
+++ /dev/null
@@ -1,71 +0,0 @@
-.\"   $Id: REVERSE_PHCON.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)REVERSE_PHCON.3 2.11 93/09/03 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-REVERSE_PHCON
-.XE \}
-.TH REVERSE_PHCON 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-REVERSE_PHCON \- reverse the order of physical connectors on a bus.
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void REVERSE_PHCON(basename)
-char \(**basename;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIbasename\fP
-Radical of the vector to be reversed.
-.SH DESCRIPTION
-\fBREVERSE_PHCON\fP will change the indexes of the vector called
-\fIbasename\fP, making the greatest values the smallest and so on.
-Both hard connectors, created by \fBPHCON\fR(3) like functions and
-virtual ones, done with \fBPHREF\fR(3), will be taken into account for
-the reverse operation.
-This function is mainly useful to implement the \fBmsb0\fR options of
-the \fBAlliance\fR CAD system module generators, as the whole design can
-be done with the designer choosen bit ordering, and modified on user
-demand only before saving.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	DEF_PHFIG("rom");
-	/\(** Create a figure to work on  \(**/
-	.
-	.
-	.
-	/\(** Reverse the bit ordering if needed \(**/
-	if (msb0)
-		REVERSE_PHCON("adr");
-	/\(** Save all that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR PHCON (3),
-.BR PHREF (3),
-.BR COPY_UP_CON (3),
-.BR COPY_UP_ALL_CON (3),
-.BR COPY_UP_CON_FACE (3),
-.BR COPY_UP_REF (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/RFG2CC.3 b/alliance/share/man/man3/RFG2CC.3
deleted file mode 100644
index 3bb029df..00000000
--- a/alliance/share/man/man3/RFG2CC.3
+++ /dev/null
@@ -1,73 +0,0 @@
-.\"   $Id: RFG2CC.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.TH RFG2CC 3 "October 1, 1997" "ASIM/LIP6" "FITPATH Macro-Functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBDP_RFG2CC\fP - Register File
-.SH SYNOPSYS
-.ft CR
-.nf
-#include  <fpgen.h>
-
-void  DP_RFG2CC( 
-    char *InstName,  /*            Instance name             */
-    long  RegNB   ,  /*         Number of Registers          */
-
-    char *SigAr0  ,  /*  IN    First read data adress   CTRL */
-    char *SigAr1  ,  /*  IN   Second read data adress   CTRL */
-    char *SigWe   ,  /*  IN         Write enable        CTRL */
-    char *SigAw   ,  /*  IN         Write data adress   CTRL */
-    char *BusI    ,  /*  IN         Write data input    DATA */
-    char *BusO0   ,  /* OUT    First read data output   DATA */
-    char *BusO1   ,  /* OUT   Second read data output   DATA */
-    char *SigCk   ,  /*  IN              Clock input    DATA */
-               EOL);
-.fi
-.ft R
-.SH DESCRIPTION
-.ta 4m
-	\fBDP_RFG2CC\fP creates a two-read and one-write register file of
-\fIRegNB\fP registers and then instanciates it with the name \fIInstName\fP.
-The register bit-size is the full wide of the current data-path, set by the 
-previous call to the function \fBDP_DEFLOFIG\fP. The first register R0 is
-a normal register.
-.br
-	The environment variable \fBMBK_CATA_LIB\fP have to contain an additionnal
-library path when using this macro-function, see \fBfpgen(1)\fP for more
-details.
-.br
-.SH CHARACTERISTICS
-.ta +15n +2n +2n
-Operator wide	:	Depends on the data-path wide and \fBRegNB\fP.
-.SH EXAMPLE
-.ft CR
-.nf
-DP_RFG2CC("rfg0_instance0", 8, "read_adress0[2:0]" ,
-                               "read_adress1[2:0]" ,
-                                 "pin_wen"         ,
-                               "write_adress[2:0]" ,
-                                 "data_input[31:0]", 
-                               "data_output0[31:0]",
-                               "data_output1[31:0]",
-                                 "pin_ck"          , EOL);
-	
-.fi
-.ft R
-.SH SEE ALSO
-.ft B
-rfg(1)
-,
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/SAVE.3 b/alliance/share/man/man3/SAVE.3
deleted file mode 100644
index deafc24b..00000000
--- a/alliance/share/man/man3/SAVE.3
+++ /dev/null
@@ -1,33 +0,0 @@
-.\"   $Id: SAVE.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)SAVE.3 2.30 Sep 09 1993 UPMC ; VUONG H.N. 
-.TH SAVE 3 "October 1, 1997" "ASIM/LIP6" "GENPAT functions"
-
-.SH NAME
-.PP
-\fBSAVE\fP, GENPAT Package
-
-.SH SYNOPSYS
-.PP
-.nf
-SAVE ();
-.fi
-
-.so man1/alc_origin.1
-.SH DESCRIPTION
-.PP
-Make the simulator to save the state of the circuit at the end of the
-simulation.
-
-.SH EXAMPLES
-.PP
-.nf
-SAVE ();
-.fi
-
-.SH SEE ALSO
-.PP
-genpat(1), pat(5), asimut(1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/SAVE_LOFIG.3 b/alliance/share/man/man3/SAVE_LOFIG.3
deleted file mode 100644
index edbbb880..00000000
--- a/alliance/share/man/man3/SAVE_LOFIG.3
+++ /dev/null
@@ -1,92 +0,0 @@
-.\"   $Id: SAVE_LOFIG.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)SAVE_LOFIOG.3 2.11 01/92; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-SAVE_LOFIG
-.XE \}
-.TH SAVE_LOFIG 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-SAVE_LOFIG \- save a netlist on disk
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void SAVE_LOFIG();
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH DESCRIPTION
-\fBSAVE_LOFIG\fP saves the current working figure previously definded by
-a \fBDEF_LOFIG\fP call. \fBSAVE_LOFIG\fP uses environment variables to
-choose the file format and the path to the file.
-\fBMBK_OUT_LO\fP set up the output file format, the valid ones beeing :
-.RS
-\fBhns
-.br
-fne
-.br
-al
-.br
-alx\fP
-.RE
-you could for example do :
-.br
-.RS
-\fBsetenv MBK_OUT_LO al\fP
-.RE
-\fBMBK_WORK_LIB\fP set up the output file path. Any valid unix path is
-ok.
-.br
-for example :
-.RS
-\fBsetenv MBK_WORK_LIB ~fred/booth/genlib\fP
-.RE
-\fBSAVE_LOFIG\fP doesn't look on disk for the figure \fIcellname\fP, 
-so be careful not to overwrite an existing file while saving.
-.SH ERROR
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"SAVE_LOFIG impossible : missing DEF_LOFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_LOFIG\fP. So it isn't
-possible to save anything. you must call \fBDEF_LOFIG\fP before any other
-netlist call.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_LOFIG("mycell");
-	/\(** define interface  \(**/
-	LOCON("i", INPUT, "sig1");
-	LOCON("o", OUTPUT, "sig2");
-	/\(** Place an instance \(**/
-	LOINS("model","instance", "sig1", "sig2", EOL);
-	/\(** Save all that on disk \(**/
-	SAVE_LOFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_LOFIG(3),
-.BR MBK_OUT_LO (1),
-.BR MBK_WORK_LIB (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/SAVE_PHFIG.3 b/alliance/share/man/man3/SAVE_PHFIG.3
deleted file mode 100644
index 769ee6e8..00000000
--- a/alliance/share/man/man3/SAVE_PHFIG.3
+++ /dev/null
@@ -1,85 +0,0 @@
-.\"   $Id: SAVE_PHFIG.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)SAVE_PHFIG.3 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-SAVE_PHFIG
-.XE \}
-.TH SAVE_PHFIG 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-SAVE_PHFIG \- save a layout on disk
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void SAVE_PHFIG();
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH DESCRIPTION
-\fBSAVE_PHFIG\fP saves the current working figure previously definded by
-a \fBDEF_PHFIG\fP call. \fBSAVE_PHFIG\fP uses environment variables to
-choose the file format and the path to the file.
-.br
-\fBMBK_OUT_PH\fP set up the output file format, the valid ones beeing :
-.RS
-\fBcp
-.br
-ap\fP
-.RE
-you could for example do :
-.RS
-\fBsetenv MBK_OUT_PH ap\fP
-.RE
-\fBMBK_WORK_LIB\fP set up the output file path. Any valid unix path is
-ok.
-.br
-for example :
-.RS
-	\fBsetenv MBK_WORK_LIB ~fred/booth/genlib\fP
-.RE
-\fBSAVE_PHFIG\fP doesn't look on disk for the figure \fIcellname\fP, 
-so be careful not to overwrite an existing file while saving.
-.SH ERROR
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"SAVE_PHFIG impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to save anything. you must call \fBDEF_PHFIG\fP before any other
-layout action.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("mycell");
-	/\(** Place an instance \(**/
-	PLACE("mymodel","firstinstance", NOSYM,0L,0L);
-	/\(** Save all that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR SAVE_PHSC (3),
-.BR MBK_OUT_PH (1),
-.BR MBK_WORK_LIB (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/SAVE_PHSC.3 b/alliance/share/man/man3/SAVE_PHSC.3
deleted file mode 100644
index 23d3a9ce..00000000
--- a/alliance/share/man/man3/SAVE_PHSC.3
+++ /dev/null
@@ -1,72 +0,0 @@
-.\"   $Id: SAVE_PHSC.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)SAVE_PHSC.3 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-SAVE_PHSC
-.XE \}
-.TH SAVE_PHSC 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-SAVE_PHSC \- save a layout on disk
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void SAVE_PHSC();
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH DESCRIPTION
-\fBSAVE_PHSC\fP saves the current working figure previously definded by
-a \fBDEF_PHFIG\fP or \fBDEF_PHSC\fP call, and performs a
-\fBDEF_AB(0L, 0L, 0L, 0L)\fP just before saving the figure, in order to give
-it the appropriate size for standard cell blocks.
-\fBSAVE_PHSC\fP uses environment variables to choose the file format and 
-the path to the file.
-.br
-No check is made to see if a file with the same name already exists on disk, so
-be careful not to overwrite some precious data.
-.SH ERROR
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"SAVE_PHSC impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP or
-\fBDEF_PHSC\fB. So it isn't
-possible to save anything. you must call \fBDEF_PHFIG\fP before any other
-layout action.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a physical figure to work on \(**/
-	DEF_PHSC("cell");
-	/\(** Place an instance \(**/
-	SC_PLACE("finst", NOSYM,0L,0L);
-	/\(** Save all that on disk \(**/
-	SAVE_PHSC();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHSC (3),
-.BR MBK_OUT_PH (1),
-.BR MBK_WORK_LIB (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/SAV_GENPAT.3 b/alliance/share/man/man3/SAV_GENPAT.3
deleted file mode 100644
index 31d665ec..00000000
--- a/alliance/share/man/man3/SAV_GENPAT.3
+++ /dev/null
@@ -1,32 +0,0 @@
-.\"   $Id: SAV_GENPAT.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)SAV_GENPAT.3 2.30 UPMC ; VUONG H.N. & PITON D.
-.TH SAV_GENPAT 3 "October 1, 1997" "ASIM/LIP6" "GENPAT functions"
-
-.SH NAME
-.PP
-\fBSAV_GENPAT\fP, GENPAT Package
-
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.PP
-.nf
-SAV_GENPAT ();
-.fi
-
-.SH DESCRIPTION
-.PP
-Generate output file in pat format
-
-.SH EXAMPLE
-.PP
-.nf
-SAV_GENPAT ();
-.fi
-
-.SH SEE ALSO
-.PP
-DEF_GENPAT(3), genpat(1), pat(5)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/SC_BOTTOM.3 b/alliance/share/man/man3/SC_BOTTOM.3
deleted file mode 100644
index 0a932b55..00000000
--- a/alliance/share/man/man3/SC_BOTTOM.3
+++ /dev/null
@@ -1,148 +0,0 @@
-.\"   $Id: SC_BOTTOM.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)SC_BOTTOM.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-SC_BOTTOM
-.XE \}
-.TH SC_BOTTOM 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-SC_BOTTOM \- place an instance in the current figure at the right of the
-"reference instance"
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void SC_BOTTOM(insname, symetry)
-char \(**insname;
-char symetry;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIinsname\fP
-Name to be given to the instance on the model
-.TP
-\fIsymetry\fP
-Geometrical operation to be performed on the instance before beeing placed
-.SH DESCRIPTION
-\fBSC_BOTTOM\fP add an instance in the current cell. The bottom left corner
-of the abutment box of the instance is placed, after beeing symetrized
-and/or rotated,
-toward the bottom left corner of the abutment box of the
-"reference instance". The newly
-placed instance becomes the "reference instance".
-The placement takes place only if the netlist is up to day,
-because the model of the instance is seeked there, in order to ensure
-consistency.
-.LP
-The \fIsymetry\fP argument can take eight legal values :
-.TP 20
-\fBNOSYM\fP
-no geometrical operation is performed
-.TP
-\fBSYM_Y\fP
-Y becomes -Y, that means toward X axe symetry
-.TP
-\fBSYM_X\fP
-X becomes -X, that means toward Y axe symetry
-.TP
-\fBSYMXY\fP
-X becomes -X, Y becomes -Y
-.TP
-\fBROT_P\fP
-a positive 90 degrees rotation take place
-.TP
-\fBROT_M\fP
-a negative 90 degrees rotation take place
-.TP
-\fBSY_RP\fP
-Y becomes -Y, and then a positive 90 degrees rotation take place
-.TP
-\fBSY_RM\fP
-Y becomes -Y, and then a negative 90 degrees rotation take place
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"SC_BOTTOM impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place an instance inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"SC_BOTTOM impossible : missing DEF_LOFIG"
-.ft R
-.RS
-The current netlist figure is not define, so \fBSC_BOTTOM\fP doesn't know
-where to pick up the model. A \fBDEF_LOFIG\fP or a \fBDEF_PHSC\fP
-is to be performed to avoid this error.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"SC_BOTTOM impossible : no logical instance insname"
-.ft R
-.RS
-The instance \fIinsname\fP does not exist in the netlist representation
-of the cell. It may lead us to believe that there is a consistency
-problem between the two representation of this cell.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal addphins : transformation is x in insname"
-.ft R
-.RS
-The \fIsymetry\fP parameter is not one of the define given, but has the
-integer value \fBx\fP.
-.RE
-.br
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHSC("cell");
-	/\(** Place two instances \(**/
-	SC_PLACE("ins1", NOSYM, 0L, 0L);
-	SC_BOTTOM("ins2", SYMXY);
-	/\(** Save all that on disk \(**/
-	SAVE_PHSC();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHSC (3),
-.BR SAVE_PHSC (3),
-.BR SC_PLACE (3),
-.BR SC_TOP (3),
-.BR SC_RIGHT (3),
-.BR SC_LEFT (3),
-.BR DEF_PHINS (3),
-.BR FLATTEN_PHFIG (3),
-.BR FLATTEN_ALL_PHINS (3),
-.BR LOINS (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/SC_LEFT.3 b/alliance/share/man/man3/SC_LEFT.3
deleted file mode 100644
index 706ae9b0..00000000
--- a/alliance/share/man/man3/SC_LEFT.3
+++ /dev/null
@@ -1,149 +0,0 @@
-.\"   $Id: SC_LEFT.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)SC_LEFT.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-SC_LEFT
-.XE \}
-.TH SC_LEFT 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-SC_LEFT \- place an instance in the current figure at the right of the
-"reference instance"
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void SC_LEFT(insname, symetry)
-char \(**insname;
-char symetry;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIinsname\fP
-Name to be given to the instance on the model
-.TP
-\fIsymetry\fP
-Geometrical operation to be performed on the instance before beeing placed
-.SH DESCRIPTION
-\fBSC_LEFT\fP add an instance in the current cell. The bottom right corner
-of the abutment box of the instance is placed, after beeing symetrized
-and/or rotated,
-toward the bottom left corner of the abutment box of the
-"reference instance". The newly
-placed instance becomes the "reference instance".
-The placement takes place only if the netlist is up to day,
-because the model of the instance is seeked there, in order to ensure
-consistency.
-.LP
-The \fIsymetry\fP argument can take eight legal values :
-.TP 20
-\fBNOSYM\fP 
-no geometrical operation is performed
-.TP
-\fBSYM_Y\fP 
-Y becomes -Y, that means toward X axe symetry
-.TP
-\fBSYM_X\fP 
-X becomes -X, that means toward Y axe symetry
-.TP
-\fBSYMXY\fP 
-X becomes -X, Y becomes -Y
-.TP
-\fBROT_P\fP 
-a positive 90 degrees rotation take place
-.TP
-\fBROT_M\fP 
-a negative 90 degrees rotation take place
-.TP
-\fBSY_RP\fP 
-Y becomes -Y, and then a positive 90 degrees rotation take place
-.TP
-\fBSY_RM\fP 
-Y becomes -Y, and then a negative 90 degrees rotation take place
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"SC_LEFT impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place an instance inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"SC_LEFT impossible : missing DEF_LOFIG"
-.ft R
-.RS
-The current netlist figure is not define, so \fISC_LEFT\fP doesn't know
-where to pick up the model. A \fIDEF_LOFIG\fP or a \fIDEF_PHSC\fP
-is to be performed to avoid this error.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"SC_LEFT impossible : no logical instance insname"
-.ft R
-.RS
-The instance \fIinsname\fP does not exist in the netlist representation
-of the cell. It may lead us to believe that there is a consistency
-problem between the two representation of this cell.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal addphins : transformation is x in insname"
-.ft R
-.RS
-The \fIsymetry\fP parameter is not one of the define given, but has the
-integer value \fBx\fP.
-.RE
-.br
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHSC("cell");
-	/\(** Place two instances \(**/
-	SC_PLACE("ins1", NOSYM, 0L, 0L);
-	/\(** negative placement values are allowed \(**/
-	SC_LEFT("ins2", SYM_Y);
-	/\(** Save all that on disk \(**/
-	SAVE_PHSC();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib(1),
-.BR DEF_PHSC(3),
-.BR SAVE_PHSC(3),
-.BR SC_PLACE(3),
-.BR SC_TOP(3),
-.BR SC_BOTTOM(3),
-.BR SC_RIGHT(3),
-.BR DEF_PHINS (3),
-.BR FLATTEN_PHFIG (3),
-.BR FLATTEN_ALL_PHINS (3),
-.BR LOINS(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/SC_PLACE.3 b/alliance/share/man/man3/SC_PLACE.3
deleted file mode 100644
index 4ca8bbff..00000000
--- a/alliance/share/man/man3/SC_PLACE.3
+++ /dev/null
@@ -1,150 +0,0 @@
-.\"   $Id: SC_PLACE.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)SC_PLACE.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-SC_PLACE
-.XE \}
-.TH SC_PLACE 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-SC_PLACE \- place an instance in the current figure at absolute coordinates
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void SC_PLACE(insname, symetry, x, y)
-char \(**insname;
-char symetry;
-long x,y;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIinsname\fP
-Name to be given to the instance on the model
-.TP
-\fIsymetry\fP
-Geometrical operation to be performed on the instance before beeing placed
-.TP
-\fIx, y\fP
-Coordinates of the lower left corner of the abutment box of the model in
-the current figure
-.SH DESCRIPTION
-\fISC_PLACE\fP add an instance in the current cell. The bottom left corner
-of the instance is placed, after beeing symetrized and/or rotated,
-at \fI(x, y)\fP
-coordinates. The placement takes place only if the netlist is up to day,
-because the model of the instance is seeked there, in order to ensure
-consistency.
-The placed instance becomes the new "reference instance", used in
-the relative placement functions.
-.br
-The \fIsymetry\fP argument can take eight legal values :
-.TP 20
-\fBNOSYM\fP
-no geometrical operation is performed
-.TP
-\fBSYM_Y\fP
-Y becomes -Y, that means toward X axe symetry
-.TP
-\fBSYM_X\fP
-X becomes -X, that means toward Y axe symetry
-.TP
-\fBSYMXY\fP
-X becomes -X, Y becomes -Y
-.TP
-\fBROT_P\fP
-a positive 90 degrees rotation take place
-.TP
-\fBROT_M\fP
-a negative 90 degrees rotation take place
-.TP
-\fBSY_RP\fP
-Y becomes -Y, and then a positive 90 degrees rotation take place
-.TP
-\fBSY_RM\fP
-Y becomes -Y, and then a negative 90 degrees rotation take place
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"SC_PLACE impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place an instance inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"SC_PLACE impossible : missing DEF_LOFIG"
-.ft R
-.RS
-The current netlist figure is not define, so \fBSC_PLACE\fP doesn't know
-where to pick up the model. A \fBDEF_LOFIG\fP or a \fBDEF_PHSC\fP
-is to be performed to avoid this error.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"SC_PLACE impossible : no logical instance insname"
-.ft R
-.RS
-The instance \fIinsname\fP does not exist in the netlist representation
-of the cell. It may lead us to believe that there is a consistency
-problem between the two representation of this cell.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal addphins : transformation is x in insname"
-.ft R
-.RS
-The \fIsymetry\fP parameter is not one of the define given, but has the
-integer value \fBx\fP.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHSC("cell");
-	/\(** Place two instances \(**/
-	SC_PLACE("ins1", NOSYM, 0L, 0L);
-	SC_PLACE("ins2", NOSYM, 80L, 100L);
-	/\(** Save all that on disk \(**/
-	SAVE_PHSC();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHSC (3),
-.BR SAVE_PHSC (3),
-.BR SC_TOP (3),
-.BR SC_BOTTOM (3),
-.BR SC_LEFT (3),
-.BR SC_RIGHT (3),
-.BR DEF_PHINS (3),
-.BR FLATTEN_PHFIG (3),
-.BR FLATTEN_ALL_PHINS (3),
-.BR LOINS (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/SC_RIGHT.3 b/alliance/share/man/man3/SC_RIGHT.3
deleted file mode 100644
index dc11cca7..00000000
--- a/alliance/share/man/man3/SC_RIGHT.3
+++ /dev/null
@@ -1,147 +0,0 @@
-.\"   $Id: SC_RIGHT.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)SC_RIGHT.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-SC_RIGHT
-.XE \}
-.TH SC_RIGHT 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-SC_RIGHT \- place an instance in the current figure at the right of the
-"reference instance"
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void SC_RIGHT(insname, symetry)
-char \(**insname;
-char symetry;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIinsname\fP
-Name to be given to the instance on the model
-.TP
-\fIsymetry\fP
-Geometrical operation to be performed on the instance before beeing placed
-.SH DESCRIPTION
-\fBSC_RIGHT\fP add an instance in the current cell. The bottom left corner
-of the abutment box of the instance is placed, after beeing symetrized
-and/or rotated,
-toward the bottom right corner of the abutment box of the
-"reference instance". The newly
-placed instance becomes the "reference instance".
-The placement takes place only if the netlist is up to day,
-because the model of the instance is seeked there, in order to ensure
-consistency.
-.LP
-The \fIsymetry\fP argument can take eight legal values :
-.TP 20
-\fBNOSYM\fP 
-no geometrical operation is performed
-.TP
-\fBSYM_Y\fP 
-Y becomes -Y, that means toward X axe symetry
-.TP
-\fBSYM_X\fP 
-X becomes -X, that means toward Y axe symetry
-.TP
-\fBSYMXY\fP 
-X becomes -X, Y becomes -Y
-.TP
-\fBROT_P\fP 
-a positive 90 degrees rotation take place
-.TP
-\fBROT_M\fP 
-a negative 90 degrees rotation take place
-.TP
-\fBSY_RP\fP 
-Y becomes -Y, and then a positive 90 degrees rotation take place
-.TP
-\fBSY_RM\fP 
-Y becomes -Y, and then a negative 90 degrees rotation take place
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"SC_RIGHT impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place an instance inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"SC_RIGHT impossible : missing DEF_LOFIG"
-.ft R
-.RS
-The current netlist figure is not define, so \fBSC_RIGHT\fP doesn't know
-where to pick up the model. A \fBDEF_LOFIG\fP or a \fBDEF_PHSC\fP
-is to be performed to avoid this error.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"SC_RIGHT impossible : no logical instance insname"
-.ft R
-.RS
-The instance \fIinsname\fP does not exist in the netlist representation
-of the cell. It may lead us to believe that there is a consistency
-problem between the two representation of this cell.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal addphins : transformation is x in insname"
-.ft R
-.RS
-The \fIsymetry\fP parameter is not one of the define given, but has the
-integer value \fBx\fP.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHSC("cell");
-	/\(** Place two instances \(**/
-	SC_PLACE("ins1", NOSYM, 0L, 0L);
-	SC_RIGHT("ins2", SYM_X);
-	/\(** Save all that on disk \(**/
-	SAVE_PHSC();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib(1),
-.BR DEF_PHSC(3),
-.BR SAVE_PHSC(3),
-.BR SC_PLACE(3),
-.BR SC_TOP(3),
-.BR SC_BOTTOM(3),
-.BR SC_LEFT(3),
-.BR DEF_PHINS (3),
-.BR FLATTEN_PHFIG (3),
-.BR FLATTEN_ALL_PHINS (3),
-.BR LOINS(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/SC_TOP.3 b/alliance/share/man/man3/SC_TOP.3
deleted file mode 100644
index 2c0ca845..00000000
--- a/alliance/share/man/man3/SC_TOP.3
+++ /dev/null
@@ -1,148 +0,0 @@
-.\"   $Id: SC_TOP.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)SC_TOP.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-SC_TOP
-.XE \}
-.TH SC_TOP 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-SC_TOP \- place an instance in the current figure at the right of the
-"reference instance"
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void SC_TOP(insname, symetry)
-char \(**insname;
-char symetry;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIinsname\fP
-Name to be given to the instance on the model
-.TP
-\fIsymetry\fP
-Geometrical operation to be performed on the instance before beeing placed
-.SH DESCRIPTION
-\fBSC_TOP\fP add an instance in the current cell. The bottom left corner
-of the abutment box of the instance is placed, after beeing symetrized
-and/or rotated,
-toward the top left corner of the abutment box of the
-"reference instance". The newly
-placed instance becomes the "reference instance".
-The placement takes place only if the netlist is up to day,
-because the model of the instance is seeked there, in order to ensure
-consistency.
-.LP
-The \fIsymetry\fP argument can take eight legal values :
-.TP 20
-\fBNOSYM\fP
-no geometrical operation is performed
-.TP
-\fBSYM_Y\fP
-Y becomes -Y, that means toward X axe symetry
-.TP
-\fBSYM_X\fP
-X becomes -X, that means toward Y axe symetry
-.TP
-\fBSYMXY\fP
-X becomes -X, Y becomes -Y
-.TP
-\fBROT_P\fP
-a positive 90 degrees rotation take place
-.TP
-\fBROT_M\fP
-a negative 90 degrees rotation take place
-.TP
-\fBSY_RP\fP
-Y becomes -Y, and then a positive 90 degrees rotation take place
-.TP
-\fBSY_RM\fP
-Y becomes -Y, and then a negative 90 degrees rotation take place
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"SC_TOP impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place an instance inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"SC_TOP impossible : missing DEF_LOFIG"
-.ft R
-.RS
-The current netlist figure is not define, so \fBSC_TOP\fP doesn't know
-where to pick up the model. A \fBDEF_LOFIG\fP or a \fBDEF_PHSC\fP
-is to be performed to avoid this error.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"SC_TOP impossible : no logical instance insname"
-.ft R
-.RS
-The instance \fIinsname\fP does not exist in the netlist representation
-of the cell. It may lead us to believe that there is a consistency
-problem between the two representation of this cell.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal addphins : transformation is x in insname"
-.ft R
-.RS
-The \fIsymetry\fP parameter is not one of the define given, but has the
-integer value \fBx\fP.
-.RE
-.br
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHSC("cell");
-	/\(** Place two instances \(**/
-	SC_PLACE("ins1", NOSYM, 0L, 0L);
-	SC_TOP("ins2", SYM_X);
-	/\(** Save all that on disk \(**/
-	SAVE_PHSC();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHSC (3),
-.BR SAVE_PHSC (3),
-.BR SC_PLACE (3),
-.BR SC_RIGHT (3),
-.BR SC_BOTTOM (3),
-.BR SC_LEFT (3),
-.BR DEF_PHINS (3),
-.BR FLATTEN_PHFIG (3),
-.BR FLATTEN_ALL_PHINS (3),
-.BR LOINS (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/SETTUNIT.3 b/alliance/share/man/man3/SETTUNIT.3
deleted file mode 100644
index 910d6e9e..00000000
--- a/alliance/share/man/man3/SETTUNIT.3
+++ /dev/null
@@ -1,47 +0,0 @@
-.\"   $Id: SETTUNIT.3,v 1.1 1999/10/25 08:03:16 simcity Exp $
-.\" @(#)SETTUNIT.3 2.30  UPMC ; VUONG H.N. & PITON D.
-.TH SETTUNIT 3 "October 1, 1997" "ASIM/LIP6" "GENPAT functions"
-
-.SH NAME
-.PP
-\fBSETTUNIT\fP, GENPAT Package
-
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.PP
-.nf
-SETTUNIT ("time_unit");
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fItime_unit\fP
-: legal time_unit are fs, ps, ns, us and ms.
-
-.SH DESCRIPTION
-.PP
-Set the pattern \fItime_unit\fP. Default \fItime_unit\fP is ps.
-
-.SH EXAMPLE
-.PP
-.nf
-SETTUNIT ("ps");
-SETTUNIT ("fs");
-.fi
-
-.SH WARNING
-.PP
-The SETTUNIT function is a new function of the 4.0 release.
-To generate a pattern file in an oldest pat format (3.5 release
-and oldest), you may use a virtual time_unit : SETTUNIT ("vu").
-In this case, the pattern file is generated without dates (the
-dates specified with the AFFECT and INIT functions are used as
-pattern numbers).
-
-.SH SEE ALSO
-.PP
-genpat(1), pat(5)
-
-
-.so man1/alc_bug_report.1
diff --git a/alliance/share/man/man3/SymbolicChannelRouter.3 b/alliance/share/man/man3/SymbolicChannelRouter.3
deleted file mode 100644
index 914ff390..00000000
--- a/alliance/share/man/man3/SymbolicChannelRouter.3
+++ /dev/null
@@ -1,183 +0,0 @@
-.\"   $Id: SymbolicChannelRouter.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)SymbolicChannelRouter.1 1.0 93/07/29 ; Labo masi cao-vlsi; Author : El housseine REJOUAN
-.TH SYMBOLICCHANNELROUTER 3 "October 1, 1997" "ASIM/LIP6" "APR FUNCTIONS"
-
-.SH NAME
-SymbolicChannelRouter \- routes a given channel on a Virtual grid
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aprnnn.h"
-int \fBSymbolicChannelRouter\fP( ptNorthConList,
-				ptSouthConList,
-				ptWestConList,
-				ptEastConList,
-				ChannelWidth,
-				ChannelHeight,
-				ptHorSegList,
-				ptVerSegList,
-				ptViaList)
-ConnectorList	**ptNorthConList;
-ConnectorList	**ptSouthConList;
-ConnectorList	**ptWestConList;
-ConnectorList	**ptEastConList;
-long			*ChannelWidth;
-long			*ChannelHeight;
-SegmentList		**ptHorSegList;
-SegmentList		**ptVerSegList;
-ViasList		**ptViaList;
-.br
-.SH PARAMETERS
-.TP 15
-\fIptNorthConList\fP
-List of the connectors located on the north side of the channel.
-.TP 15
-\fIptSouthConList\fP
-List of the connectors located on the south side of the channel.
-.TP 15
-\fIptWestConList\fP
-List of the connectors located on the west side of the channel.
-.TP 15
-\fIptEastConList\fP
-List of the connectors located on the east side of the channel.
-.TP 15
-\fIChannelWidth\fP
-Width of the channel.
-.TP 15
-\fIChannelHeight\fP
-Height of the channel.
-.TP 15
-\fIptHorSegList\fP
-List of horizontal wires produced by the \fBSymbolicChannelRouter\fP.
-.TP 15
-\fIptVerSegList\fP
-List of vertical wires produced by the \fBSymbolicChannelRouter\fP.
-.TP 15
-\fIptViaList\fP
-List of vias produced by the \fBSymbolicChannelRouter\fP.
-.br
-.SH DESCRIPTION
-\fBSymbolicChannelRouter\fP routes a given channel on a virtual grid using a greedy algorithm.
-.br
-The connectors on the west and east sides are placed by the router.
-.br
-The \fIptNorthConList\fP, \fIptSouthConList\fP, \fIptWestConList\fP and \fIptEastConList\fP
-can be NULL.
-.br
-The \fIChannelWidth\fP is the width of the channel. It is a virtual value.
-.br
-\fIChannelHeight\fP is the Height of the channel. It is a virtual value and  it may be a value zero.
-.br
-The \fIptHorSegList\fP, \fIptVerSegList\fP and \fIptViaList\fP are returned by the \fBSymbolicChannelRouter\fP.
-.br
-.bp
-The SymbolicChannelRouter structure is described  :
-.PP
-typedef struct SCR_ConnectorList
-.IP
-	{
-.br
-	struct SCR_ConnectorList	*NextCon;
-.br
-	long			ConName;
-.br
-	long			Mark;
-.br
-	} ConnectorList;
-.TP 15
-\fINextCon\fP
-Pointer to the next connector in the list.
-.br
-.TP 15
-\fIConName\fP
-Name of the connector. 
-.br
-.TP 15
-\fIMark\fP
-Connector index on a symbolic grid. 
-.PP
-typedef struct SCR_SegmentList
-.IP
-	{
-.br
-	struct SCR_SegmentList	*NextSeg;
-.br
-	char			*SegName;
-.br
-	long			X1Seg;
-.br
-	long			Y1Seg;
-.br
-	long			X2Seg;
-.br
-	long			Y2Seg;
-.br
-	} SegmentList;
-.br
-.TP 25
-\fINextSeg\fP
-Pointer to the next segment in the list.
-.TP 25
-\fISegName\fP
-Name of the segment. 
-.br
-.TP 25
-\fIX1Seg\fP, \fIY1Seg\fP, \fIX2Seg\fP, \fIY2Seg\fP
-Coordinates of each end of the segment. Since it's a symbolic segment.
-.PP
-typedef struct SCR_ViasList
-.IP
-        {
-.br
-        struct SCR_ViasList	*NextVia;
-.br
-        long		XVia;
-.br
-        long		YVia;
-.br
-        } ViasList;
-.br
-.TP 15
-\fINextVia\fP
-Pointer to the next via in the list.
-.TP 15
-\fIXVia\fP,\fIYVia\fP
-Coordinates of the center of the via.
-.PP
-.SH EXAMPLE
-.IP
-#include "aprnnn.h"
-.br
-if (SymbolicChannelRouter(&ptNorthConList,
-.br
-			  &ptSouthConList,
-.br
-			  &ptWestConList,
-.br
-			  &ptEastConList,
-.br
-			  &ChannelWidth,
-.br
-			  &ChannelHeight,
-.br
-			  &ptHorSegList,
-.br
-			  &ptVerSegList,
-.br
-			  &ptViaList))
-.br
-	 printf("the channel width is modified;");
-.br
-	else printf("the channel width is not modified;");
-.SH SEE ALSO
-.BR apr(3),
-.BR scr(1),
-.BR bbr(1),
-.BR dpr(1)
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/THRU_CON_H.3 b/alliance/share/man/man3/THRU_CON_H.3
deleted file mode 100644
index 3b2e45f7..00000000
--- a/alliance/share/man/man3/THRU_CON_H.3
+++ /dev/null
@@ -1,141 +0,0 @@
-.\"   $Id: THRU_CON_H.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)THRU_CON_H.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-THRU_CON_H
-.XE \}
-.TH THRU_CON_H 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-THRU_CON_H \- draw an horizontal wire from side to side of the
-\fIabutment box\fP of the current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void THRU_CON_H(layer, width, name, y)
-char layer;
-long width;
-char \(**name;
-long y;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIlayer\fP
-Layout layer of the wire and connectors
-.TP
-\fIwidth\fP
-Width of the wire and connectors
-.TP
-\fIname\fP
-Name of the connectors
-.TP
-\fIy\fP
-Absolute y coordinate of the wire and connectors
-.SH DESCRIPTION
-\fBTHRU_CON_H\fP adds an horizontal segment in the current layout cell.
-Two connectors are created on the \fBWEST\fP and \fPEQST\fP sides of the
-\fIabutment box\fP, at the \fIy\fP coordinates, and given the name \fIname\fP.
-The segment is drawn thru the figure, from the \fBWEST\fP connector to the
-\fBEAST\fP one.
-.br
-This function is mostly used to put \fIthrough routes\fP on a figure, and
-therefore, the \fBT\fP prefixed layer names are the most likely to be used
-here.
-.br
-The \fIlayer\fP argument can take the following legal values:
-.RS
-.TP
-\fBNWELL\fP 
-.TP
-\fBPWELL\fP 
-.TP
-\fBNTIE\fP 
-.TP
-\fBPTIE\fP 
-.TP
-\fBNDIF\fP 
-.TP
-\fBPDIF\fP 
-.TP
-\fBNTRANS\fP 
-.TP
-\fBPTRANS\fP 
-.TP
-\fBPOLY\fP 
-.TP
-\fBALU1\fP 
-.TP
-\fBALU2\fP 
-.TP
-\fBALU3\fP 
-.TP
-\fBTPOLY\fP 
-.TP
-\fBTALU1\fP 
-.TP
-\fBTALU2\fP 
-.TP
-\fBTALU3\fP 
-.RE
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"THRU_CON_H impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a connector inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"THRU_CON_H impossible : no or illegal abutment box"
-.ft R
-.RS
-The current figure has either no abutment box defined yet, or has a heigth
-of zero. \fBDEF_AB\fP is to be called.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("cell");
-	.
-	.
-	.
-	DEF_AB(0L, 0L, 0L, 0L);
-	/\(** Put a wire through the figure \(**/
-	THRU_CON_H(TALU2, 1, "pwet", 32L);
-	/\(** Save that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHFIG (3),
-.BR SAVE_PHFIG (3),
-.BR THRU_H (3),
-.BR THRU_V (3),
-.BR THRU_CON_V (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/THRU_CON_V.3 b/alliance/share/man/man3/THRU_CON_V.3
deleted file mode 100644
index 76b3b286..00000000
--- a/alliance/share/man/man3/THRU_CON_V.3
+++ /dev/null
@@ -1,144 +0,0 @@
-.\"   $Id: THRU_CON_V.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)THRU_CON_V.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-THRU_CON_V
-.XE \}
-.TH THRU_CON_V 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-THRU_CON_V \- draw a vertical wire with connectors from side to side
-of the \fIabutment box\fP of the current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void THRU_CON_V(layer, width, name, x)
-char layer;
-long width;
-char \(**name;
-long x;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIlayer\fP
-Layout layer of the wire and connectors
-.TP
-\fIwidth\fP
-Width of the wire and connectors
-.TP
-\fIname\fP
-Name of the connectors
-.TP
-\fIx\fP
-Absolute x coordinate of the wire and connectors
-.SH DESCRIPTION
-\fBTHRU_CON_V\fP adds a vertical segment and two connectors in the current
-layout cell.
-The \fIx\fP coordinates gives the wire and connectors horizontal position,
-vertical ones beeing extracted from the figure \fIabutment box\fP.
-Two connectors are created on the \fBNORTH\fP and \fPSOUTH\fP sides of the
-\fIabutment box\fP, at the \fIx\fP coordinates, and given the name \fIname\fP.
-The segment is drawn thru the figure, from the \fBNORTH\fP connector to the
-\fBSOUTH\fP one.
-.br
-This function is mostly used to put \fIthrough routes\fP on a figure, and
-therefore, the \fBT\fP prefixed layer names are the most likely to be used
-here.
-.br
-The \fIlayer\fP argument can take the following legal values:
-.RS
-.TP
-\fBNWELL\fP 
-.TP
-\fBPWELL\fP 
-.TP
-\fBNTIE\fP 
-.TP
-\fBPTIE\fP 
-.TP
-\fBNDIF\fP 
-.TP
-\fBPDIF\fP 
-.TP
-\fBNTRANS\fP 
-.TP
-\fBPTRANS\fP 
-.TP
-\fBPOLY\fP 
-.TP
-\fBALU1\fP 
-.TP
-\fBALU2\fP 
-.TP
-\fBALU3\fP 
-.TP
-\fBTPOLY\fP 
-.TP
-\fBTALU1\fP 
-.TP
-\fBTALU2\fP 
-.TP
-\fBTALU3\fP 
-.RE
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"THRU_CON_V impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a connector inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"THRU_CON_V impossible : no or illegal abutment box"
-.ft R
-.RS
-The current figure has either no abutment box defined yet, or has an heigth
-of zero. \fBDEF_AB\fP is to be called.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("cell");
-	.
-	.
-	.
-	DEF_AB(0L, 0L, 0L, 0L);
-	/\(** Put a wire through the figure \(**/
-	THRU_CON_V(TALU2, 1, "grumf", 12L);
-	/\(** Save that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHFIG (3),
-.BR SAVE_PHFIG (3),
-.BR THRU_H (3),
-.BR THRU_V (3),
-.BR THRU_CON_V (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/THRU_H.3 b/alliance/share/man/man3/THRU_H.3
deleted file mode 100644
index 03167ed2..00000000
--- a/alliance/share/man/man3/THRU_H.3
+++ /dev/null
@@ -1,137 +0,0 @@
-.\"   $Id: THRU_H.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)THRU_H.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-THRU_H
-.XE \}
-.TH THRU_H 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-\fBTHRU_H\fP \- draw an horizontal wire from side to side of the
-\fIabutment box\fP of the current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void THRU_H(layer, width, y)
-char layer;
-long width;
-long y;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIlayer\fP
-Layout layer of the wire
-.TP
-\fIwidth\fP
-Width of the wire
-.TP
-\fIy\fP
-Absolute y coordinate of the wire
-.SH DESCRIPTION
-\fBTHRU_H\fP adds an horizontal segment in the current layout cell.
-The \fIy\fP coordinates gives the wire its vertical position, horizontal ones
-beeing extracted from the figure \fIabutment box\fP.
-The segment is drawn thru the figure, from one side of the \fIabutment box\fP
-to the other side.
-.br
-This function is mostly used to put \fIthrough routes\fP on a figure, and
-therefore, the \fBT\fP prefixed layer names are the most likely to be used
-here.
-.br
-The \fIlayer\fP argument can take the following legal values:
-.RS
-.TP 
-\fBNWELL\fP 
-.TP
-\fBPWELL\fP 
-.TP
-\fBNTIE\fP 
-.TP
-\fBPTIE\fP 
-.TP
-\fBNDIF\fP 
-.TP
-\fBPDIF\fP 
-.TP
-\fBNTRANS\fP 
-.TP
-\fBPTRANS\fP 
-.TP
-\fBPOLY\fP 
-.TP
-\fBALU1\fP 
-.TP
-\fBALU2\fP 
-.TP
-\fBALU3\fP 
-.TP
-\fBTPOLY\fP 
-.TP
-\fBTALU1\fP 
-.TP
-\fBTALU2\fP 
-.TP
-\fBTALU3\fP 
-.RE
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"THRU_H impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a connector inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"THRU_H impossible : no or illegal abutment box"
-.ft R
-.RS
-The current figure has either no abutment box defined yet, or has a width
-of zero. \fBDEF_AB\fP is to be called.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("cell");
-	.
-	.
-	.
-	DEF_AB(0L, 0L, 0L, 0L);
-	/\(** Put a wire through the figure \(**/
-	THRU_H(TALU2, 1, 32L);
-	/\(** Save that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHFIG (3),
-.BR SAVE_PHFIG (3),
-.BR THRU_V (3),
-.BR THRU_CON_H (3),
-.BR THRU_CON_V (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/THRU_V.3 b/alliance/share/man/man3/THRU_V.3
deleted file mode 100644
index c1c16a34..00000000
--- a/alliance/share/man/man3/THRU_V.3
+++ /dev/null
@@ -1,137 +0,0 @@
-.\"   $Id: THRU_V.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)THRU_V.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-THRU_V
-.XE \}
-.TH THRU_V 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-THRU_V \- draw a vertical wire from side to side of the
-\fIabutment box\fP of the current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void THRU_V(layer, width, x)
-char layer;
-long width;
-long x;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIlayer\fP
-Layout layer of the wire
-.TP
-\fIwidth\fP
-Width of the wire
-.TP
-\fIx\fP
-Absolute x coordinate of the wire
-.SH DESCRIPTION
-\fBTHRU_V\fP adds a vertical segment in the current layout cell.
-The \fIx\fP coordinates gives the wire its horizontal position, vertical ones
-beeing extracted from the figure \fIabutment box\fP.
-The segment is drawn thru the figure, from one side of the \fIabutment box\fP
-to the other side.
-.br
-This function is mostly used to put \fIthrough routes\fP on a figure, and
-therefore, the \fBT\fP prefixed layer names are the most likely to be used
-here.
-.br
-The \fIlayer\fP argument can take the following legal values:
-.RS
-.TP
-\fBNWELL\fP 
-.TP
-\fBPWELL\fP 
-.TP
-\fBNTIE\fP 
-.TP
-\fBPTIE\fP 
-.TP
-\fBNDIF\fP 
-.TP
-\fBPDIF\fP 
-.TP
-\fBNTRANS\fP 
-.TP
-\fBPTRANS\fP 
-.TP
-\fBPOLY\fP 
-.TP
-\fBALU1\fP 
-.TP
-\fBALU2\fP 
-.TP
-\fBALU3\fP 
-.TP
-\fBTPOLY\fP 
-.TP
-\fBTALU1\fP 
-.TP
-\fBTALU2\fP 
-.TP
-\fBTALU3\fP 
-.RE
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"THRU_V impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place a connector inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"THRU_V impossible : no or illegal abutment box"
-.ft R
-.RS
-The current figure has either no abutment box defined yet, or has a width
-of zero. \fBDEF_AB\fP is to be called.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("cell");
-	.
-	.
-	.
-	DEF_AB(0L, 0L, 0L, 0L);
-	/\(** Put a wire through the figure \(**/
-	THRU_V(TALU2, 1, 32L);
-	/\(** Save that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHFIG (3),
-.BR SAVE_PHFIG (3),
-.BR THRU_H (3),
-.BR THRU_CON_H (3),
-.BR THRU_CON_V (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/UNFLATTEN_LOFIG.3 b/alliance/share/man/man3/UNFLATTEN_LOFIG.3
deleted file mode 100644
index e9fe872e..00000000
--- a/alliance/share/man/man3/UNFLATTEN_LOFIG.3
+++ /dev/null
@@ -1,72 +0,0 @@
-.\"   $Id: UNFLATTEN_LOFIG.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)UNFLATTEN_LOFIG.3 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-UNFLATTEN_LOFIG
-.XE \}
-.TH UNFLATTEN_LOFIG 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-\fBUNFLATTEN_LOFIG\fP \- creates a hierarchy level from instances in the current logical figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void UNFLATTEN_LOFIG(figurename, instancename, list_of_instances, 0)
-char \(**figurename;
-char \(**instancename;
-char \(**list_of_instances;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIfigurename\fP
-Name of the figure of the new hierarchy to be created
-.TP
-\fIinstancename\fP
-Name to be given at the instanciation of \fIfigurename\fP into the current
-structual figure
-.TP
-\fIlist_of_instances\fP
-List of strings representing the instances to be inserted into the new figure
-.SH DESCRIPTION
-\fBUNFLATTEN_LOFIG\fP creates a new level of hierarchy, whose model name will
-be \fIfigurename\fP, and instanciate it under the name \fIinstancename\fP in
-the current figure.
-The instances whose name belong to the \fIlist_of_instances\fP parameters are
-added in the new figure, and destroyed from the current figure.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_LOFIG("mycell");
-	.
-	.
-	.
-	/\(** Place an instance \(**/
-	LOINS("model","instance", "sig1", "sig2", EOL);
-	/\(** flatten an instance \(**/
-	UNFLATTEN_LOFIG("newfig", "newins", "instance", ..., 0);
-	/\(** Save all that on disk \(**/
-	SAVE_LOFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR FLATTEN_LOFIG (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/WIDTH.3 b/alliance/share/man/man3/WIDTH.3
deleted file mode 100644
index cf7ba65b..00000000
--- a/alliance/share/man/man3/WIDTH.3
+++ /dev/null
@@ -1,62 +0,0 @@
-.\"   $Id: WIDTH.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)WIDTH.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-WIDTH
-.XE \}
-.TH WIDTH 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-WIDTH \- compute the width of a model
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-long WIDTH(cellname)
-char \(**cellname;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIcellname\fP
-Name of the cell which width is needed
-.SH DESCRIPTION
-\fBWIDTH\fP looks for the figure called \fIcellname\fP on memory, and then on
-disk. When found, the figure \fIabutment box\fP width is calculated, and
-returned.
-.SH RETURN VALUE
-\fBWIDTH\fP returns a long int beeing the cell \fIabutment box\fP width.
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-long cellWidth;
-main()
-{
-	cellWidth = WIDTH("n1_y");
-	DEF_PHFIG("pwet");
-	.
-	.
-	.
-	PLACE("na2_y","ins1", NOSYM, 0L, 4 * cellWidth);
-	/\(** Save all that on disk \(**/
-	DEF_AB(0L, 0L, 0L, 0L);
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR HEIGHT (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/WIRE1.3 b/alliance/share/man/man3/WIRE1.3
deleted file mode 100644
index 195a11e1..00000000
--- a/alliance/share/man/man3/WIRE1.3
+++ /dev/null
@@ -1,175 +0,0 @@
-.\"   $Id: WIRE1.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)WIRE1.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-WIRE1
-.XE \}
-.TH WIRE1 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-WIRE1 \- place a physical segment in the current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void WIRE1(layer, width, ins1, con1, index1, ins2, con2, index2)
-char layer;
-long width;
-char \(**ins1, \(**con1, \(**ins2, \(**con2;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIlayer\fP
-Layout layer of the segment
-.TP
-\fIwidth\fP
-Width of the segment
-.TP
-\fIins1\fP
-Name of the instance in which the connector \fIcon1\fP is to be looked for
-.TP
-\fIcon1\fP
-Name of a connector, or reference, used as first endpoint of the wire
-.TP
-\fIins2\fP
-Name of the instance in which the connector \fIcon2\fP is to be looked for
-.TP
-\fIcon2\fP
-Name of a connector, or reference, used as last endpoint of the wire
-.SH DESCRIPTION
-\fBWIRE1\fP adds a segment made of the \fIlayer\fP level in the current
-layout cell, the starting point
-beeing the connector, or reference, \fIcon1\fP of the instance \fIins1\fP, and
-the ending point beeing the connector, or reference, \fIcon2\fP of the instance
-\fIins1\fP. The segment is drawn between the coordinates of \fIcon1\fP in
-the current figure and the
-coordinates of \fIcon2\fP in the current figure. 
-.LP
-If the endpoints are connectors, the indexes \fIindex1\fP and \fIindex2\fP must
-respectivly refer to \fIcon1\fP and \fIcon2\fP.
-If they are references, then they are not taked care of.
-One shall notice that connectors and references of a given model should not
-share names if \fBWIRE1\fP is to be used.
-.LP
-The \fIlayer\fP argument can take the following legal values :
-.RS
-.TP
-\fBNWELL\fP 
-.TP
-\fBPWELL\fP 
-.TP
-\fBNTIE\fP 
-.TP
-\fBPTIE\fP 
-.TP
-\fBNDIF\fP 
-.TP
-\fBPDIF\fP 
-.TP
-\fBNTRANS\fP 
-.TP
-\fBPTRANS\fP 
-.TP
-\fBPOLY\fP 
-.TP
-\fBALU1\fP 
-.TP
-\fBALU2\fP 
-.TP
-\fBALU3\fP 
-.TP
-\fBTPOLY\fP 
-.TP
-\fBTALU1\fP 
-.TP
-\fBTALU2\fP 
-.TP
-\fBTALU3\fP 
-.RE
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"WIRE1 impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place an instance inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal addphseg : x1, y1, x2, y2"
-.ft R
-.RS
-A symbolic segment must be either vertical or horizontal, so either
-\fIx1 = x2\fP, or \fIy1 = y2\fP. Since \fBWIRE1\fP creates a segment from
-relative coordinates, care must be taken to follow the previous rule.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"WIRE1 impossible : same name \fIconX\fP, for connector and reference in
-\fIinsX\fP"
-.ft R
-.RS
-The model of the instance \fIinsX\fP has both a connector and a reference
-that matches the \fIconX\fP name. This is not legal since genlib doesn't know
-which one to choose as point.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphins : instance \fIinsX\fP does not exist"
-.ft R
-.RS
-The instance called \fIinsX\fP does not currently belong to the figure.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("cell");
-	PLACE("gaci0_b", "r_addin_1", NOSYM, 0, 0);
-	PLACE_RIGHT("gapgn_b", "pg", NOSYM);
-	PLACE_RIGHT("gacin_b", "r_addin_2", NOSYM);
-	/\(** Draw a segment \(**/
-	WIRE1(ALU1, 1, "r_addin_1", "out", 0L, "r_addin_2", "in", 1L);
-	/\(** Save that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHFIG (3),
-.BR SAVE_PHFIG (3),
-.BR COPY_UP_SEG (3),
-.BR PHSEG (3),
-.BR THRU_H (3),
-.BR THRU_CON_H (3),
-.BR THRU_V (3),
-.BR THRU_CON_V (3),
-.BR WIRE2 (3),
-.BR WIRE3 (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/WIRE2.3 b/alliance/share/man/man3/WIRE2.3
deleted file mode 100644
index f13fb7cc..00000000
--- a/alliance/share/man/man3/WIRE2.3
+++ /dev/null
@@ -1,181 +0,0 @@
-.\"   $Id: WIRE2.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)WIRE2.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-WIRE2
-.XE \}
-.TH WIRE2 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-WIRE2 \- place two physical segments in the current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void WIRE2(layer, width, ins1, con1, index1, ins2, con2, index2, x, y)
-char layer;
-long width;
-char \(**ins1, \(**con1, \(**ins2, \(**con2;
-long x, y;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIlayer\fP
-Layout layer of the segment
-.TP
-\fIwidth\fP
-Width of the segment
-.TP
-\fIins1\fP
-Name of the instance in which the connector \fIcon1\fP is to be looked for
-.TP
-\fIcon1\fP
-Name of a connector, or reference, used as first endpoint of the wire
-.TP
-\fIins2\fP
-Name of the instance in which the connector \fIcon2\fP is to be looked for
-.TP
-\fIcon2\fP
-Name of a connector, or reference, used as last endpoint of the wire
-.TP
-\fIx, y\fP
-Coordinates of the segment's elbow in the current figure
-.SH DESCRIPTION
-\fBWIRE2\fP adds two segments made of the \fIlayer\fP level in the current
-layout cell, the starting point
-beeing the connector, or reference, \fIcon1\fP of the instance \fIins1\fP, and
-the ending point beeing the connector, or reference, \fIcon2\fP of the instance
-\fIins1\fP. The first segment is drawn between the coordinates of \fIcon1\fP in
-the current figure and \fIx, y\fP, and the second one between \fIx, y\fP and the
-coordinates of \fIcon2\fP in the current figure. 
-.LP
-If the endpoints are connectors, the indexes \fIindex1\fP and \fIindex2\fP must
-respectivly refer to \fIcon1\fP and \fIcon2\fP.
-If they are references, then they are not taked care of.
-One shall notice that connectors and references of a given model should not
-share names if \fBWIRE2\fP is to be used.
-.LP
-The \fIlayer\fP argument can take the following legal values :
-.RS
-.TP
-\fBNWELL\fP 
-.TP
-\fBPWELL\fP 
-.TP
-\fBNTIE\fP 
-.TP
-\fBPTIE\fP 
-.TP
-\fBNDIF\fP 
-.TP
-\fBPDIF\fP 
-.TP
-\fBNTRANS\fP 
-.TP
-\fBPTRANS\fP 
-.TP
-\fBPOLY\fP 
-.TP
-\fBALU1\fP 
-.TP
-\fBALU2\fP 
-.TP
-\fBALU3\fP 
-.TP
-\fBTPOLY\fP 
-.TP
-\fBTALU1\fP 
-.TP
-\fBTALU2\fP 
-.TP
-\fBTALU3\fP 
-.RE
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"WIRE2 impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place an instance inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal addphseg : x1, y1, x2, y2"
-.ft R
-.RS
-A symbolic segment must be either vertical or horizontal, so either
-\fIx1 = x2\fP, or \fIy1 = y2\fP. Since \fBWIRE2\fP creates segments from
-relative coordinates, care must be taken to follow the previous rule.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"WIRE2 impossible : same name \fIconX\fP, for connector and reference in
-\fIinsX\fP"
-.ft R
-.RS
-The model of the instance \fIinsX\fP has both a connector and a reference
-that matches the \fIconX\fP name. This is not legal since genlib doesn't know
-which one to choose as point.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphins : instance \fIinsX\fP does not exist"
-.ft R
-.RS
-The instance called \fIinsX\fP does not currently belong to the figure.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-main()
-{
-	/\(** Create a figure to work on  \(**/
-	DEF_PHFIG("cell");
-	PLACE("gaci0_b", "r_addin_1", NOSYM, 0, 0);
-	PLACE_TOP("gacin_b", "r_addin_2", NOSYM);
-	PLACE_RIGHT("gapgn_b", "pg", NOSYM);
-	/\(** Draw a segment \(**/
-	WIRE2(ALU1, 1, "r_addin_1", "out", 0L, "pg", "g", 1L,
-			GET_CON_X("pg", "g", 1L),
-			GET_CON_Y("r_addin_1", "out", 0L));
-	/\(** Save that on disk \(**/
-	SAVE_PHFIG();
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHFIG (3),
-.BR SAVE_PHFIG (3),
-.BR COPY_UP_SEG (3),
-.BR PHSEG (3),
-.BR THRU_H (3),
-.BR THRU_CON_H (3),
-.BR THRU_V (3),
-.BR THRU_CON_V (3),
-.BR WIRE1 (3),
-.BR WIRE3 (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/WIRE3.3 b/alliance/share/man/man3/WIRE3.3
deleted file mode 100644
index 81567161..00000000
--- a/alliance/share/man/man3/WIRE3.3
+++ /dev/null
@@ -1,184 +0,0 @@
-.\"   $Id: WIRE3.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)WIRE3.3 2.11 91/08/22 ; Labo Cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-WIRE3
-.XE \}
-.TH WIRE3 3 "October 1, 1997" "ASIM/LIP6" "PROCEDURAL GENERATION LANGUAGE"
-.SH NAME
-WIRE3 \- place three physical segments in the current figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-void WIRE3(layer, width, ins1, con1, index1, ins2, con2, index2, x1, y1, x2, y2)
-char layer;
-long width;
-char \(**ins1, \(**con1, \(**ins2, \(**con2;
-long x1, y1, x2, y2;
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH PARAMETERS
-.TP 20
-\fIlayer\fP
-Layout layer of the segment
-.TP
-\fIwidth\fP
-Width of the segment
-.TP
-\fIins1\fP
-Name of the instance in which the connector \fIcon1\fP is to be looked for
-.TP
-\fIcon1\fP
-Name of a connector, or reference, used as first endpoint of the wire
-.TP
-\fIins2\fP
-Name of the instance in which the connector \fIcon2\fP is to be looked for
-.TP
-\fIcon2\fP
-Name of a connector, or reference, used as last endpoint of the wire
-.TP
-\fIx1, y1\fP
-Coordinates of the segment's first elbow endpoint in the current figure
-.TP
-\fIx2, y2\fP
-Coordinates of the segment's second elbow endpoint in the current figure
-.SH DESCRIPTION
-\fBWIRE3\fP adds three segments made of the \fIlayer\fP level in the current
-layout cell, the starting point
-beeing the connector, or reference, \fIcon1\fP of the instance \fIins1\fP, and
-the ending point beeing the connector, or reference, \fIcon2\fP of the instance
-\fIins1\fP. The first segment is drawn between the coordinates of \fIcon1\fP in
-the current figure and \fIx1, y1\fP. The second one between \fIx1, y1\fP and
-\fIx2, y2\fP, and the last, but not the least, between \fIx2, y2\fP and the
-coordinates of \fIcon2\fP in the current figure. 
-.LP
-If the endpoints are connectors, the indexes \fIindex1\fP and \fIindex2\fP must
-respectivly refer to \fIcon1\fP and \fIcon2\fP.
-If they are references, then they are not taked care of.
-One shall notice that connectors and references of a given model should not
-share names if \fBWIRE3\fP is to be used.
-.LP
-The \fIlayer\fP argument can take the following legal values :
-.RS
-.TP
-\fBNWELL\fP 
-.TP
-\fBPWELL\fP 
-.TP
-\fBNTIE\fP 
-.TP
-\fBPTIE\fP 
-.TP
-\fBNDIF\fP 
-.TP
-\fBPDIF\fP 
-.TP
-\fBNTRANS\fP 
-.TP
-\fBPTRANS\fP 
-.TP
-\fBPOLY\fP 
-.TP
-\fBALU1\fP 
-.TP
-\fBALU2\fP 
-.TP
-\fBALU3\fP 
-.TP
-\fBTPOLY\fP 
-.TP
-\fBTALU1\fP 
-.TP
-\fBTALU2\fP 
-.TP
-\fBTALU3\fP 
-.RE
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"WIRE3 impossible : missing DEF_PHFIG"
-.ft R
-.RS
-No figure has been yet specified by a call to \fBDEF_PHFIG\fP. So it isn't
-possible to place an instance inside it.
-you must call \fBDEF_PHFIG\fP before any other layout action.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal addphseg : x1, y1, x2, y2"
-.ft R
-.RS
-A symbolic segment must be either vertical or horizontal, so either
-\fIx1 = x2\fP, or \fIy1 = y2\fP. Since \fBWIRE3\fP creates segments from
-relative coordinates, care must be taken to follow the previous rule.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"WIRE3 impossible : same name \fIconX\fP, for connector and reference in
-\fIinsX\fP"
-.ft R
-.RS
-The model of the instance \fIinsX\fP has both a connector and a reference
-that matches the \fIconX\fP name. This is not legal since genlib doesn't know
-which one to choose as point.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"illegal getphins : instance \fIinsX\fP does not exist"
-.ft R
-.RS
-The instance called \fIinsX\fP does not currently belong to the figure.
-.RE
-.SH EXAMPLE
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <genlib.h>
-draw_wire(cellHeight)
-long cellHeight;
-{
-	/* draw a wire made of 1, 2, or 3 segments, given from and to connectors
-	   or reference, and the x and y coordinates of each elbow points */
-	WIRE1(ALU1,1,"lastpg2","g2",1,"cabl31","sg",2);
-	WIRE3(ALU1,1,"cabl31","sp",2, "celout2", "cin", 1,
-			GET_CON_X("cabl31","sp",2),
-			GET_CON_Y("cabl31","sp",2) + cellHeight / 2,
-			GET_CON_X("celout2", "cin", 1),
-			GET_CON_Y("cabl31","sp",2) + cellHeight / 2);
-	WIRE1(POLY,1,"celout3","g",1,"celout2","co",0);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR genlib (1),
-.BR DEF_PHFIG (3),
-.BR SAVE_PHFIG (3),
-.BR COPY_UP_SEG (3),
-.BR PHSEG (3),
-.BR THRU_H (3),
-.BR THRU_CON_H (3),
-.BR THRU_V (3),
-.BR THRU_CON_V (3),
-.BR WIRE1 (3),
-.BR WIRE2 (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/ablToBddCct.3 b/alliance/share/man/man3/ablToBddCct.3
deleted file mode 100644
index 5894a54f..00000000
--- a/alliance/share/man/man3/ablToBddCct.3
+++ /dev/null
@@ -1,57 +0,0 @@
-.\"   $Id: ablToBddCct.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)ablToBddCct.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH ABLTOBDDCCT 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBablToBddCct\fP \- converts an ABL into a BDD within a circuit 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-pNode ablToBddCct(pC,expr)
-pCircuit pC;
-chain_list *expr;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIpC\fP
-Circuit in which is made the conversion
-.TP 20
-\fIexpr\fP
-expression to convert
-.SH DESCRIPTION
-\fBablToBddCct()\fP constructs the graph that is computed from \fIexpr\fP. This function provides the basic method for constructing easily the BDDs. The \fBapplyBdd()\fP function is called recursively by going through the ABL.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr;
-pNode res;
-pCircuit pC;
-
-initializeBdd(SMALL_BDD);
-pC = initializeCct("circuit 1",10,10);
-
-addInputCct(pC,"a");
-addInputCct(pC,"b");
-
-	/* let's suppose that expr = (OR (AND (NOT a) b) a) */
-
-res = ablToBddCct(pC,expr);
-displayBdd(res,1);
-
-/* it will display 
-@res      INDEX = 3   LOW = @nodeA   HIGH = ONE 
-@nodeA    INDEX = 2   LOW = ZERO     HIGH = ONE
-*/
-
-destroyCct(pC);
-destroyBdd(1);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR abl (1),
-.BR bddToAblCct (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/aboxmbkrds.3 b/alliance/share/man/man3/aboxmbkrds.3
deleted file mode 100644
index 3b0615da..00000000
--- a/alliance/share/man/man3/aboxmbkrds.3
+++ /dev/null
@@ -1,90 +0,0 @@
-.\"   $Id: aboxmbkrds.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)aboxmbkrds.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-aboxmbkrds
-.XE
-.XS0 \n%
-.ti 0.2i
-aboxmbkrds
-.XE0 \}
-.TH ABOXMBKRDS 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
- aboxmbkrds \- converts MBK abutment box to RDS rectangle
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rfmnnn.h"
- rdsrec_list \(**aboxmbkrds( FigureMbk, FigureRds )
-   phfig_list  \(**FigureMbk;
-   rdsfig_list \(**FigureRds;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIFigureMbk\fP
-Figure Mbk which contains the abutment box.
-.TP
-\fIFigureRds\fP
-Figure Rds which has to receive the abutment box.
-.SH DESCRIPTION
-The \fIaboxmbkrds\fP function adds to the RDS figure the abutment box from the MBK figure after conversion to the Rds format. 
-.SH RETURN VALUE
-If the abutment box of the MBK figure exists then the function returns the pointer to the Rds rectangle (abox) created. If it doesn't exist then NULL pointer is returned.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Rds202: rdsalloc error, can't continue !"
-.ft R
-.RS
-it's impossible to allocate the memory size desired
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mphnnn.h"
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rfmnnn.h"
-        #include "rtlnnn.h"
-        typedef struct UserStruct
-         {
-           char \(**STRING;
-           void \(**USER1;
-         } UserStruct;
-        main()
-          {
-            phfig_list  \(**MbkFigure;
-            rdsfig_list \(**RdsFigure;
-            rdsrec_list \(**RdsAbox;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            /\(** creates MbkFigure Named "core" \(**/
-            MbkFigure        = addphfig("core"); 
-            /\(** creates RdsFigure named "core_2" \(**/
-            RdsFigure        = addrdsfig("core_2",sizeof(UserStruct));
-            /\(** Adds Abox of MbkFigure to Rds Figure \(**/
-            RdsAbox          = \fBaboxmbkrds\fP ( MbkFigure, RdsFigure );
-            . . .
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librfm,
-.BR loadrdsparam
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addHExpr.3 b/alliance/share/man/man3/addHExpr.3
deleted file mode 100644
index 3f4fa84d..00000000
--- a/alliance/share/man/man3/addHExpr.3
+++ /dev/null
@@ -1,55 +0,0 @@
-.\"   $Id: addHExpr.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)addHExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH ADDHEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBaddHExpr\fP \- adds a new argument at the head of an operator expression. 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-void addHExpr(expr1,expr2)
-chain_list *expr1,*expr2;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIexpr1\fP
-expression that recieves \fIexpr2\fP.
-.TP 20
-\fIexpr2\fP
-Argument to add (atomic or operator expression).
-.SH DESCRIPTION
-\fBaddHExpr()\fP adds \fIexpr2\fP at the head of the expression \fIexpr1\fP. This procedure doesn't make any simplifications. 
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr1,*expr2; 
-expr1 = createExpr(OR);
-addHExpr(expr1,createAtom("var1"));
-expr2 = createExpr(OR);
-addHExpr(expr2,createAtom("var1"));
-addHExpr(expr2,createAtom("var2"));
-addHExpr(expr1,expr2);
-displayExpr(expr1);
-/* it will display
-(OR (OR var2 var1) var1)
-*/
-freeExpr(expr1);	/* don't free expr2 ! */
-.fi
-.SH ERROR
-"addHExpr : error - bad argument
-.br
-\fIexpr1\fP must be an operator expression.
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR createAtom (3),
-.BR notExpr (3),
-.BR addQExpr (3),
-.BR createBinExpr (3),
-.BR createExpr (3),
-.BR addQExpr(3),
-.BR freeExpr(3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addInputCct.3 b/alliance/share/man/man3/addInputCct.3
deleted file mode 100644
index 6ec22c18..00000000
--- a/alliance/share/man/man3/addInputCct.3
+++ /dev/null
@@ -1,58 +0,0 @@
-.\"   $Id: addInputCct.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)addInputCct.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH ADDINPUTCCT 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBaddInputCct\fP \- adds an input to a circuit 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-short addInputCct(pC,name)
-pCircuit pC;
-char *name;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIpC\fP
-Circuit 
-.TP 20
-\fIname\fP
-name to add
-.SH DESCRIPTION
-\fBaddInputCct()\fP adds a primary input \fIname\fP to \fIpC\fP. This function returns the associated index.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-pCircuit pC;
-
-initializeBdd(SMALL_BDD);
-pC = initializeCct("circuit 1",10,10);
-
-addInputCct(pC,"a");
-addInputCct(pC,"b");
-
-displayCct(pC,1);
-
-/* it will display 
-************* DISPLAY circuit 1 **********
-INPUT = a	INDEX = 2
-INPUT = b	INDEX = 3
---------- NUMBER OF INPUTS = 2
---------- NUMBER OF OUTPUTS = 0
-******************************************
-*/
-
-destroyCct(pC);
-destroyBdd(1);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR searchInputCct (3),
-.BR cpOrderCct (3),
-.bc searchOutputCct (3),
-.BR addOutputCct (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addListBdd.3 b/alliance/share/man/man3/addListBdd.3
deleted file mode 100644
index 6d1bc8c3..00000000
--- a/alliance/share/man/man3/addListBdd.3
+++ /dev/null
@@ -1,63 +0,0 @@
-.\"   $Id: addListBdd.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)addListBdd.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH ADDLISTBDD 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBaddListBdd\fP \- adds a BDD to a chained list of BDDs
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-chain_list *addListBdd(pt,pBdd)
-chain_list *pt;
-pNode pBdd;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIpt\fP
-old \fIchain_list\fP pointer
-.TP 20
-\fIpBdd\fP
-BDD to add
-.SH DESCRIPTION
-\fBaddListBdd()\fP adds \fIpBdd\fP to \fIpt\fP. This function computes an optimal reordering on \fIpt\fP that minimizes the number of nodes when the \fBapplyBdd()\fP function is called. 
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-pNode nodeA,nodeB,nodeC;
-pNode res;
-chain_list *pt;
-
-initializeBdd(SMALL_BDD);
-nodeA = createNodeTermBdd(3);
-nodeB = createNodeTermBdd(3);
-nodeC = createNodeTermBdd(4);
-pt = NULL;
-pt = addListBdd(pt,nodeA);
-pt = addListBdd(pt,nodeB);
-pt = addListBdd(pt,nodeC);
-res = applyBdd(OR,pt);
-displayBdd(res,1);
-
-/* it will display 
-@res    INDEX = 4   LOW = @inter   HIGH = ONE
-@inter  INDEX = 3   LOW = @nodeA   HIGH = ONE
-@nodeA  INDEX = 2   LOW = ZERO	   HIGH = ONE
-*/
-/* total number of nodes = 5 */
-	
-destroyBdd(1);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR addListBdd (3),
-.BR addListBdd (3),
-.BR notBdd (3),
-.BR constraintBdd (3),
-.BR composeBdd (3),
-.BR displayBdd (3),
-.BR createNodeTermBdd (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addOutputCct.3 b/alliance/share/man/man3/addOutputCct.3
deleted file mode 100644
index 9e75d4fe..00000000
--- a/alliance/share/man/man3/addOutputCct.3
+++ /dev/null
@@ -1,70 +0,0 @@
-.\"   $Id: addOutputCct.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)addOuputCct.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH ADDOUTPUTCCT 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBaddOuputCct\fP \- adds an ouput associated to a BDD in a circuit 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-void addOuputCct(pC,name,pBdd)
-pCircuit pC;
-char *name;
-pNode pBdd;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIpC\fP
-Circuit 
-.TP 20
-\fIname\fP
-name to add
-.TP 20
-\fIpBdd\fP
-node to add
-.SH DESCRIPTION
-\fBaddOuputCct()\fP adds a new output associated to a \fIpBdd\fP. 
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-pCircuit pC;
-chain_list *expr;
-
-initializeBdd(SMALL_BDD);
-pC = initializeCct("circuit 1",10,10);
-
-addInputCct(pC,"a");
-addInputCct(pC,"b");
-
-	/* let's suppose that expr = (OR a b) */
-
-addOuputCct(pC,"s1",one);
-addOuputCct(pC,"s2",ablToBddCct(pC,expr));
-
-displayBdd(pC,1)
-
-/* it will display 
-************* DISPLAY circuit 1 **********
-INPUT = a	INDEX = 2
-INPUT = b	INDEX = 3
---------- NUMBER OF INPUTS = 2
-OUTPUT = s1	s1 = 1
-OUTPUT = s2	s2 = (OR a b)
---------- NUMBER OF OUTPUTS = 2
-******************************************
-*/
-
-destroyCct(pC);
-destroyBdd(1);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR addOutputCct (3),
-.BR searchInputCct (3),
-.BR addOutputCct (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addQExpr.3 b/alliance/share/man/man3/addQExpr.3
deleted file mode 100644
index e25e7a44..00000000
--- a/alliance/share/man/man3/addQExpr.3
+++ /dev/null
@@ -1,55 +0,0 @@
-.\"   $Id: addQExpr.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)addQExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH ADDQEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBaddQExpr\fP \- adds a new argument at the queue of an operator expression. 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-void addQExpr(expr1,expr2)
-chain_list *expr1,*expr2;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIexpr1\fP
-expression that recieves \fIexpr2\fP.
-.TP 20
-\fIexpr2\fP
-Argument to add.
-.SH DESCRIPTION
-\fBaddQExpr()\fP adds \fIexpr2\fP at the queue of the expression \fIexpr1\fP. This procedure doesn't make simplifications. 
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr1,*expr2; 
-expr1 = createExpr(OR);
-addQExpr(expr1,createAtom("var1"));
-expr2 = createExpr(OR);
-addQExpr(expr2,createAtom("var1"));
-addQExpr(expr2,createAtom("var2"));
-addQExpr(expr1,expr2);
-displayExpr(expr1);
-/* it will display
-(OR var1 (OR var1 var2))
-*/
-freeExpr(expr1);	/* don't free expr2 ! */
-.fi
-.SH ERROR
-"addQExpr : error - bad argument
-.br
-\fIexpr1\fP must be an operator expression.
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR createAtom (3),
-.BR notExpr (3),
-.BR addQExpr (3),
-.BR createBinExpr (3),
-.BR createExpr (3),
-.BR addQExpr(3),
-.BR freeExpr(3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addTH.3 b/alliance/share/man/man3/addTH.3
deleted file mode 100644
index 04ebf1d8..00000000
--- a/alliance/share/man/man3/addTH.3
+++ /dev/null
@@ -1,50 +0,0 @@
-.\"   $Id: addTH.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)addTH.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH ADDTH 3 "October 1, 1997" "ASIM/LIP6" "Hash table functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBaddTH\fP \- adds a new item in a hash table.
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-void addTH(pTable,key,value)
-pTH pTable;
-char *key;
-int value;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIpTable\fP
-Hash table.
-.TP 20
-\fIkey\fP
-Key used by the hash coding function.
-.TP 20
-\fIvalue\fP
-Associated value (pointer must be casted)
-.SH DESCRIPTION
-\fBaddTH()\fP adds a new item in \fIpTable\fP. If the key already exists, the old value is replaced by the new value. \fIValue\fP must be distinct from -1 (EMPTYTH) and -2 (DELETETH). The length of the table increases automatically when the length given in \fBcreateTH()\fP is insufficient.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"
-#include "logmmm.h"
-pTH mytable; 
-mytable = createTH(100); 
-addTH(mytable,namealloc("var1"),0);
-addTH(mytable,namealloc("var2"),1);
-.fi
-.SH ERROR
-"addTH : error - value is EMPTYTH or DELETETH"
-.br
-The value must be distinct from -1 and -2.
-.SH SEE ALSO
-.BR log (1),
-.BR tsh (1),
-.BR createTH (3),
-.BR destroyTH (3),
-.BR searchTH (3),
-.BR deleteTH (3),
-.BR displayTH (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addablhexpr.3 b/alliance/share/man/man3/addablhexpr.3
deleted file mode 100644
index d2f3e425..00000000
--- a/alliance/share/man/man3/addablhexpr.3
+++ /dev/null
@@ -1,62 +0,0 @@
-.\"   $Id: addablhexpr.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)addablhexpr.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH ADDABLHEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-addablhexpr \- adds a new argument in head of an expression.
-
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-void addablhexpr( Expr1, Expr2 )
-  chain_list *Expr1;
-  chain_list *Expr2;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIExpr1\fP
-First expression.
-.TP
-\fIExpr2\fP
-Second expression.
-.SH DESCRIPTION
-\fBaddablhexpr\fP adds \fIExpr2\fP in head of \fIExpr1\fP.
-The expression pointers \fIExpr2\fP MUSTN'T be used after
-the call to this function
-.br
-.SH RETURN VALUE
-\fBaddablhexpr\fP returns nothing.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-  chain_list \(**Expr;
-  Expr = createabloper( ABL_OR );
-  addablhexpr( Expr, createablatom( "a" ) );
-  addablhexpr( Expr, createablatom( "b" ) );
-  /* displays (a or b) */
-  viewablexpr( Expr, ABL_VIEW_VHDL );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1)
-.BR createablatom(3),
-.BR createabloper(3),
-.BR createablxorbinexpr(3),
-.BR createablunaryexpr(3),
-.BR createablbinexpr(3),
-.BR createablnotexpr(3),
-.BR addablqexpr(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addablqexpr.3 b/alliance/share/man/man3/addablqexpr.3
deleted file mode 100644
index dab0174d..00000000
--- a/alliance/share/man/man3/addablqexpr.3
+++ /dev/null
@@ -1,62 +0,0 @@
-.\"   $Id: addablqexpr.3,v 1.1 1999/05/31 17:30:16 alliance Exp $
-.\" @(#)addablqexpr.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH ADDABLQEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-addablqexpr \- adds a new argument in queue of an expression.
-
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-void addablqexpr( Expr1, Expr2 )
-  chain_list *Expr1;
-  chain_list *Expr2;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIExpr1\fP
-First expression.
-.TP
-\fIExpr2\fP
-Second expression.
-.SH DESCRIPTION
-\fBaddablqexpr\fP adds \fIExpr2\fP in queue of \fIExpr1\fP.
-The expression pointers \fIExpr2\fP MUSTN'T be used after
-the call to this function
-.br
-.SH RETURN VALUE
-\fBaddablqexpr\fP returns nothing.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-  chain_list \(**Expr;
-  Expr = createabloper( ABL_OR );
-  addablqexpr( Expr, createablatom( "a" ) );
-  addablqexpr( Expr, createablatom( "b" ) );
-  /* displays (a or b) */
-  viewablexpr( Expr, ABL_VIEW_VHDL );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1)
-.BR createablatom(3),
-.BR createabloper(3),
-.BR createablxorbinexpr(3),
-.BR createablunaryexpr(3),
-.BR createablbinexpr(3),
-.BR createablnotexpr(3),
-.BR addablhexpr(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addauth2elem.3 b/alliance/share/man/man3/addauth2elem.3
deleted file mode 100644
index e486ec95..00000000
--- a/alliance/share/man/man3/addauth2elem.3
+++ /dev/null
@@ -1,86 +0,0 @@
-.\"   $Id: addauth2elem.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addauth2elem.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH ADDAUTH2ELEM 3 "October 1, 1997" "ASIM/LIP6" "AUT FUNCTIONS"
-.SH NAME
-addauth2elem \- adds an element in the hash table. 
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-auth2elem \(**addauth2elem( HashTable, Key1, Key2, Value )
-  auth2table \(**HashTable;
-  char      \(**Key1;
-  char      \(**Key2;
-  long       Value;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIHashTable\fP
-Pointer to the hash table where to add an element in.
-.TP
-\fIKey1\fP
-The first hash element key.
-.TP
-\fIKey2\fP
-The second hash element key.
-.TP
-\fIValue\fP
-The value associated to the two keys \fIKey1\fP and \fIKey2\fP.
-.SH DESCRIPTION
-\fBaddauth2elem\fP adds a new element in the hash table if there is not
-already an element associated to the two keys \fIKey1\fP and \fIKey2\fP.
-Otherwise \fBaddauth2elem\fP changes the value of the existing one.
-\fBaddauth2elem\fP stretches the hash table \fIHashTable\fP if its size
-seems to be too small.
-.br
-.SH RETURN VALUE
-\fBaddauth2elem\fP returns a pointer to the element associated to the two keys.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"auth2ash: hash key 0 error !"
-.ft R
-.RS
-The two keys \fIKey1\fP and \fIKey2\fP must be valid pointers.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-   auth2table \(**HashTable;
-   void add_in_dictionary( Name1, Name2 )
-     \(** Name1;
-     \(** Name2;
-   {
-     addauth2elem( HashTable, 
-                   namealloc( Name1 ),
-                   namealloc( Name2 ), 0 );
-   }
-   ...
-   HashTable = createauth2table( 1000 );
-   add_in_dictionary( "hello", "world"  );
-   ...
-   destroyauth2table( HashTable );
-.ft R
-.fi
-.SH SEE ALSO
-.BR aut (1)
-.BR destroyauth2table(3),
-.BR resetauth2table(3),
-.BR createauth2table(3),
-.BR searchauth2elem(3),
-.BR delauth2elem(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addauthelem.3 b/alliance/share/man/man3/addauthelem.3
deleted file mode 100644
index 60e37698..00000000
--- a/alliance/share/man/man3/addauthelem.3
+++ /dev/null
@@ -1,80 +0,0 @@
-.\"   $Id: addauthelem.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addauthelem.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH ADDAUTHELEM 3 "October 1, 1997" "ASIM/LIP6" "AUT FUNCTIONS"
-.SH NAME
-addauthelem \- adds an element in the hash table. 
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-authelem \(**addauthelem( HashTable, Key, Value )
-  authtable \(**HashTable;
-  char      \(**Key;
-  long       Value;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIHashTable\fP
-Pointer to the hash table where to add an element in.
-.TP
-\fIKey\fP
-The hash element key.
-.TP
-\fIValue\fP
-The value associated to the key \fIKey\fP.
-.SH DESCRIPTION
-\fBaddauthelem\fP adds a new element in the hash table if there is not
-already an element associated to the key \fIKey\fP.
-Otherwise \fBaddauthelem\fP changes the value of the existing one.
-\fBaddauthelem\fP stretches the hash table \fIHashTable\fP if its size
-seems to be too small.
-.br
-.SH RETURN VALUE
-\fBaddauthelem\fP returns a pointer to the element associated to the key \fIKey\fP.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"authash: hash key 0 error !"
-.ft R
-.RS
-The key \fIKey\fP of the hash table must be a valid pointer.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-   authtable \(**HashTable;
-   void add_in_dictionary( Name )
-     \(** Name;
-   {
-     addauthelem( HashTable, namealloc( Name ), 0 );
-   }
-   ...
-   HashTable = createauthtable( 1000 );
-   add_in_dictionary( "hello" );
-   add_in_dictionary( "world" );
-   ...
-   destroyauthtable( HashTable );
-.ft R
-.fi
-.SH SEE ALSO
-.BR aut (1)
-.BR destroyauthtable(3),
-.BR resetauthtable(3),
-.BR createauthtable(3),
-.BR searchauthelem(3),
-.BR delauthelem(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addbddassoc.3 b/alliance/share/man/man3/addbddassoc.3
deleted file mode 100644
index 230835f2..00000000
--- a/alliance/share/man/man3/addbddassoc.3
+++ /dev/null
@@ -1,86 +0,0 @@
-.\"   $Id: addbddassoc.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addbddassoc.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH ADDBDDASSOC 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-addbddassoc \- creates a new association variables.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddassoc \(**addbddassoc( BddSystem )
-  bddsystem  \(**BddSystem;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.SH DESCRIPTION
-\fBaddbddassoc\fP creates a new association variables in the \fBbdd\fP system
-\fIBddSystem\fP.  If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBaddbddassoc\fP returns a pointer to the new variable association.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"no more variable association, error !"
-.ft R
-.RS
-There is no variable association number left.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   bddnode    \(**BddSubst;
-   bddnode    \(**BddVariable;
-   bddassoc   \(**Assoc;
-   chain_list \(**Expr;
-   bddvar         Variable;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   Expr = createablbinexpr( ABL_AND,
-                            createablatom( "i0" ),
-                            createablatom( "i1" ) );
-   BddNode = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   Expr = createablbinexpr( ABL_OR,
-                            createablatom( "i2" ),
-                            createablatom( "i3" ) );
-   BddSubst = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   BddVariable = searchbddcircuitin( (bddcircuit \(**)0, "i0" );
-   Variable = getbddvarbyindex( (bddsystem \(**)0, BddVariable->INDEX );
-   Assoc = addbddassoc( (bddsystem \(**)0 );
-   addbddnodeassoc( (bddsystem \(**)0, Assoc, Variable, BddSubst );
-   BddNode = substbddnodeassoc( (bddsystem \(**)0, BddSubst, Assoc );
-   delbddassoc( (bddsystem \(**)0, Assoc );
-   Expr = convertbddcircuitabl( BddCircuit, BddNode );
-   /* displays ((i3 or i2) and i1) */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddassoc( (bddsystem \(**)0 );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addbddcircuitabl.3 b/alliance/share/man/man3/addbddcircuitabl.3
deleted file mode 100644
index ea24b6a6..00000000
--- a/alliance/share/man/man3/addbddcircuitabl.3
+++ /dev/null
@@ -1,82 +0,0 @@
-.\"   $Id: addbddcircuitabl.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addbddcircuitabl.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH ADDBDDCIRCUITABL 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-addbddcircuitabl \- converts an \fBabl\fP expression to a \fBbdd\fP node.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddnode \(**addbddcircuitabl( BddCircuit, Expr )
-  bddcircuit \(**BddCircuit;
-  chain_list \(**Expr;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddCircuit\fP
-The \fBbdd\fP circuit.
-.TP
-\fIExpr\fP
-The expression to convert.
-.SH DESCRIPTION
-\fBaddbddcircuitabl\fP converts the \fBabl\fP expression \fIExpr\fP
-to a \fBbdd\fP node. The \fIBddCircuit\fP is used to translate
-the atomic expressions into variable nodes.
-If a null pointer is given, the default \fBbdd\fP circuit is used.
-If an atomic expression doesn't appear in the \fIBddCircuit\fP 
-input names hash table or output names hash table,
-then \fIaddbddcircuitabl\fP adds a new input by calling the function 
-\fIaddbddcircuitin\fP with the BDD_IN_MODE_LAST mode.
-.br
-.SH RETURN VALUE
-\fBaddbddcircuitabl\fP returns a pointer to the \fBbdd\fP node translated.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"bad operator xxx error !"
-.ft R
-.RS
-The \fIExpr\fP parameter must be a well defined \fBabl\fP expression.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   chain_list \(**Expr;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   Expr = createablbinexpr( ABL_AND, 
-                            createablatom( "i0" ),
-                            createablatom( "i1" ) );
-   BddNode = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   Expr = convertbddcircuitabl( BddCircuit, BddNode );
-   /* displays (i0 and i1) */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1),
-.BR abl (1),
-.BR convertbddcircuitabl(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addbddcircuitin.3 b/alliance/share/man/man3/addbddcircuitin.3
deleted file mode 100644
index c575f044..00000000
--- a/alliance/share/man/man3/addbddcircuitin.3
+++ /dev/null
@@ -1,96 +0,0 @@
-.\"   $Id: addbddcircuitin.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addbddcircuitin.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH ADDBDDCIRCUITIN 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-addbddcircuitin \- adds an input in a \fBbdd\fP circuit.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddnode \(**addbddcircuitin( BddCircuit, InputName, Index, Mode )
-  bddcircuit \(**BddCircuit;
-  char       \(**InputName;
-  bddindex    Index;
-  long        Mode;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddCircuit\fP
-The \fBbdd\fP circuit.
-.TP
-\fIInputName\fP
-The name of the input.
-.TP
-\fIIndex\fP
-The \fBbdd\fP index of the input.
-.TP
-\fIMode\fP
-The mode.
-.SH DESCRIPTION
-\fBaddbddcircuitin\fP adds an input \fIInputName\fP in the \fBbdd\fP circuit
-\fIBddCircuit\fP. If a null pointer is given, the default \fBbdd\fP circuit is used.
-If the input \fIInputName\fP exists already, its node pointer is returned.
-The \fIMode\fP parameter specifies how to create the new variable associated
-to the name \fIInputName\fP. The \fIIndex\fP parameter is used with the 
-BDD_IN_MODE_BEFORE and BDD_IN_MODE_AFTER mode. 
-The \fIMode\fP parameter can takes the following values  :
-.TP 20
-BDD_IN_MODE_FIRST
-adds a variable before all others.
-.TP
-BDD_IN_MODE_LAST
-adds a variable after all others.
-.TP
-BDD_IN_MODE_BEFORE
-adds a variable before the one specified by \fIIndex\fP.
-.TP
-BDD_IN_MODE_AFTER
-adds a variable after the one specified by \fIIndex\fP.
-.TP
-BDD_IN_MODE_IMPOSE
-if this flag is set, only the variables found in the \fIBddCircuit\fP
-are taken into account. It permits to merge variables from different
-circuit working on the same \fBbdd\fP system.
-.br
-.SH RETURN VALUE
-\fBaddbddcircuitin\fP returns a pointer to the new created node.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"unknwon in mode xxx error !"
-.ft R
-.RS
-The \fIMode\fP parameter must be defined.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   addbddcircuitin ( (bddcircuit \(**)0, "i0", 0, BDD_IN_MODE_FIRST );
-   ...
-   BddNode = searchbddcircuitin( (bddcircuit \(**)0, "i0" );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addbddcircuitout.3 b/alliance/share/man/man3/addbddcircuitout.3
deleted file mode 100644
index f2e7ed94..00000000
--- a/alliance/share/man/man3/addbddcircuitout.3
+++ /dev/null
@@ -1,66 +0,0 @@
-.\"   $Id: addbddcircuitout.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addbddcircuitout.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH ADDBDDCIRCUITOUT 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-addbddcircuitout \- adds an output in a \fBbdd\fP circuit.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddnode \(**addbddcircuitout( BddCircuit, OutputName, BddNode )
-  bddcircuit \(**BddCircuit;
-  char       \(**OutputName;
-  bddnode    \(**BddNode;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddCircuit\fP
-The \fBbdd\fP circuit.
-.TP
-\fIOutputName\fP
-The name of the output.
-.TP
-\fIBddNode\fP
-The \fBbdd\fP node of the output.
-.SH DESCRIPTION
-\fBaddbddcircuitout\fP adds \fIBddNode\fP as an output \fIOutputName\fP in the \fBbdd\fP circuit
-\fIBddCircuit\fP. If a null pointer is given, the default \fBbdd\fP circuit is used.
-If the output \fIOutputName\fP exists already, the number of external reference of the old node
-is decremented, and the output node is replaced by the new one.
-.br
-.SH RETURN VALUE
-\fBaddbddcircuitout\fP returns the node \fIBddNode\fP with its number of external 
-reference incremented.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   ...
-   addbddcircuitout( (bddcircuit \(**)0, "Out0", BddNode );
-   ...
-   BddNode = searchbddcircuitout( (bddcircuit \(**)0, "Out0" );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-.BR searchbddcircuitout(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addbddnode.3 b/alliance/share/man/man3/addbddnode.3
deleted file mode 100644
index c59f77f5..00000000
--- a/alliance/share/man/man3/addbddnode.3
+++ /dev/null
@@ -1,83 +0,0 @@
-.\"   $Id: addbddnode.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addbddnode.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH ADDBDDNODE 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-addbddnode \- adds a new \fBbdd\fP node in the \fBbdd\fP system.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddnode \(**addbddnode( BddSystem, Index, High, Low  )
-  bddsystem \(**BddSystem;
-  bddindex   Index;
-  bddnode   \(**High;
-  bddnode   \(**Low;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIIndex\fP
-The \fBbdd\fP index.
-.TP
-\fIHigh\fP
-The \fBbdd\fP high pointer.
-.TP
-\fILow\fP
-The \fBbdd\fP low pointer.
-.SH DESCRIPTION
-\fBaddbddnode\fP adds a new node with the index \fIIndex\fP,
-\fIHigh\fP as HIGH pointer, and \fILow\fP as LOW pointer
-in the \fBbdd\fP system \fIBddSystem\fP. If the \fBbdd\fP node exist
-already \fBaddbddnode\fP return its pointer.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBaddbddnode\fP returns a pointer to the resulting \fBbdd\fP node
-with its number of external reference incremented.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"index xxx out of range"
-.ft R
-.RS
-The \fIIndex\fP parameter must be a valid index.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   chain_list \(**Expr;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   BddNode = addbddcircuitin( (bddcircuit \(**)0, "i0", 0, BDD_IN_MODE_FIRST );
-   BddNode = addbddnode( (bddsystem \(**)0, BddNode->INDEX, BddNode->LOW, BddNode->HIGH );
-   Expr = convertbddcircuitabl( (bddcircuit \(**)0, BddNode );
-   /* displays (not i0) */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addbddnodeassoc.3 b/alliance/share/man/man3/addbddnodeassoc.3
deleted file mode 100644
index aeba0096..00000000
--- a/alliance/share/man/man3/addbddnodeassoc.3
+++ /dev/null
@@ -1,101 +0,0 @@
-.\"   $Id: addbddnodeassoc.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addbddnodeassoc.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH ADDBDDNODEASSOC 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-addbddnodeassoc \- adds a \fBbdd\fP node in  a variable association.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddassoc \(**addbddnodeassoc( BddSystem, BddAssoc, Variable, BddNode )
-  bddsystem  \(**BddSystem;
-  bddassoc   \(**BddAssoc;
-  bddvar      Variable;
-  bddnode    \(**BddNode;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIBddAssoc\fP
-The variable association.
-.TP
-\fIVariable\fP
-The variable number.
-.TP
-\fIBddNode\fP
-The \fBbdd\fP node to add.
-.SH DESCRIPTION
-\fBaddbddnodeassoc\fP adds the \fBbdd\fP node \fIBddNode\fP, associated to the
-variable number \fIVariable\fP, in the variable association \fIBddAssoc\fP,
-in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-The number of external reference of \fIBddNode\fP is incremented.
-.br
-.SH RETURN VALUE
-\fBaddbddnodeassoc\fP returns a pointer to the variable association.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"variable xxx out of range, error !"
-.ft R
-.RS
-The \fIVariable\fP parameter must be less or equal to
-the \fIBddSystem->NUMBER_VAR\fP field.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   bddnode    \(**BddSubst;
-   bddnode    \(**BddVariable;
-   bddassoc   \(**Assoc;
-   chain_list \(**Expr;
-   bddvar         Variable;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   Expr = createablbinexpr( ABL_AND,
-                            createablatom( "i0" ),
-                            createablatom( "i1" ) );
-   BddNode = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   Expr = createablbinexpr( ABL_OR,
-                            createablatom( "i2" ),
-                            createablatom( "i3" ) );
-   BddSubst = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   BddVariable = searchbddcircuitin( (bddcircuit \(**)0, "i0" );
-   Variable = getbddvarbyindex( (bddsystem \(**)0, BddVariable->INDEX );
-   Assoc = addbddassoc( (bddsystem \(**)0 );
-   addbddnodeassoc( (bddsystem \(**)0, Assoc, Variable, BddSubst );
-   BddNode = substbddnodeassoc( (bddsystem \(**)0, BddSubst, Assoc );
-   Expr = convertbddcircuitabl( BddCircuit, BddNode );
-   /* displays ((i3 or i2) and i1) */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddassoc( (bddsystem \(**)0 );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addbddnodelist.3 b/alliance/share/man/man3/addbddnodelist.3
deleted file mode 100644
index 209184e3..00000000
--- a/alliance/share/man/man3/addbddnodelist.3
+++ /dev/null
@@ -1,78 +0,0 @@
-.\"   $Id: addbddnodelist.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addbddnodelist.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH ADDBDDNODELIST 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-addbddnodelist \- adds a node in a \fIchain_list\fP.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-chain_list \(**addbddnodelist( BddSystem, HeadList, BddNode )
-  bddsystem  \(**BddSystem;
-  chain_list \(**HeadList;
-  bddnode    \(**BddNode;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIHeadList\fP
-The head of the \fIchain_list\fP.
-.TP
-\fIBddNode\fP
-The \fBbdd\fP node to add.
-.SH DESCRIPTION
-\fBaddbddnodelist\fP adds the node \fIBddNode\fP in the ordered list
-\fIHeadList\fP, in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-The number of external reference of \fIBddNode\fP is incremented.
-.br
-.SH RETURN VALUE
-\fBaddbddnodelist\fP returns the new head of the list.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   chain_list \(**BddList;
-   chain_list \(**Expr;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   BddList    = (chain_list \(**)0;
-   BddList = addbddnodelist( (bddsystem \(**)0, BddList,
-                             addbddcircuitin( (bddcircuit \(**)0,
-                                              "i0", 0, BDD_IN_MODE_FIRST ) );
-   BddList = addbddnodelist( (bddsystem \(**)0, BddList,
-                              addbddcircuitin( (bddcircuit \(**)0,
-                                               "i1", 0, BDD_IN_MODE_FIRST );
-   BddList = addbddnodelist( (bddsystem \(**)0, BddList,
-                             addbddcircuitin( (bddcircuit \(**)0,
-                                              "i2", 0, BDD_IN_MODE_FIRST );
-   BddNode = applybddnodelist( (bddsystem \(**)0, ABL_AND, BddList );
-   delbddnodelist( (bddsystem \(**)0, BddList );
-   Expr = convertbddcircuitabl( (bddcircuit \(**)0, BddNode );
-   /* displays (i0 and i1 and i2) */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addbddvar.3 b/alliance/share/man/man3/addbddvar.3
deleted file mode 100644
index 9881e15e..00000000
--- a/alliance/share/man/man3/addbddvar.3
+++ /dev/null
@@ -1,73 +0,0 @@
-.\"   $Id: addbddvar.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addbddvar.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH ADDBDDVAR 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-addbddvar \- adds a new variable in the \fBbdd\fP system.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddnode \(**addbddvar( BddSystem, Variable )
-  bddsystem \(**BddSystem;
-  bddvar     Variable;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIVariable\fP
-The variable number.
-.SH DESCRIPTION
-\fBaddbddvar\fP creates a new variable, with the number \fIVariable\fP,
-in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBaddbddvar\fP returns a pointer to the \fBbdd\fP node of the new variable.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"no more variables, error !"
-.ft R
-.RS
-There is no variable number left.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"variable xxx out of range, error !"
-.ft R
-.RS
-The \fIVariable\fP parameter must be less or equal to
-the \fIBddSystem->NUMBER_VAR\fP field.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddnode    \(**BddNode;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddNode = addbddvar( (bddsystem \(**)0, 0 );
-   destroybddsystem( (bddsystem \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addbddvarafter.3 b/alliance/share/man/man3/addbddvarafter.3
deleted file mode 100644
index 54b6b09b..00000000
--- a/alliance/share/man/man3/addbddvarafter.3
+++ /dev/null
@@ -1,75 +0,0 @@
-.\"   $Id: addbddvarafter.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addbddvarafter.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH ADDBDDVARAFTER 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-addbddvarafter \- adds a new variable, after an existing one.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddnode \(**addbddvarafter( BddSystem )
-  bddsystem \(**BddSystem;
-  bddindex      Index;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIIndex\fP
-The \fBbdd\fP index of an existing variable.
-.SH DESCRIPTION
-\fBaddbddvarafter\fP creates a new variable, with the number
-\fIBddSystem\fP->INDEX_TO_VAR[ \fIIndex\fP ] + 1
-in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBaddbddvarafter\fP returns a pointer to the \fBbdd\fP node of the new variable.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"no more variables, error !"
-.ft R
-.RS
-There is no variable number left.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"index xxx out of range, error !"
-.ft R
-.RS
-The \fIIndex\fP parameter must be a valid index.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddnode    \(**BddNode1;
-   bddnode    \(**BddNode2;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddNode1 = addbddvarfirst( (bddsystem \(**)0 );
-   BddNode2 = addbddvarafter( (bddsystem \(**)0, BddNode1->INDEX );
-   destroybddsystem( (bddsystem \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addbddvarbefore.3 b/alliance/share/man/man3/addbddvarbefore.3
deleted file mode 100644
index b0913d64..00000000
--- a/alliance/share/man/man3/addbddvarbefore.3
+++ /dev/null
@@ -1,75 +0,0 @@
-.\"   $Id: addbddvarbefore.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addbddvarbefore.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH ADDBDDVARBEFORE 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-addbddvarbefore \- adds a new variable, before an existing one.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddnode \(**addbddvarbefore( BddSystem )
-  bddsystem \(**BddSystem;
-  bddindex      Index;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIIndex\fP
-The \fBbdd\fP index of an existing variable.
-.SH DESCRIPTION
-\fBaddbddvarbefore\fP creates a new variable, with the number
-\fIBddSystem\fP->INDEX_TO_VAR[ \fIIndex\fP ]
-in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBaddbddvarbefore\fP returns a pointer to the \fBbdd\fP node of the new variable.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"no more variables, error !"
-.ft R
-.RS
-There is no variable number left.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"index xxx out of range, error !"
-.ft R
-.RS
-The \fIIndex\fP parameter must be a valid index.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddnode    \(**BddNode1;
-   bddnode    \(**BddNode2;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddNode1 = addbddvarfirst( (bddsystem \(**)0 );
-   BddNode2 = addbddvarbefore( (bddsystem \(**)0, BddNode1->INDEX );
-   destroybddsystem( (bddsystem \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addbddvarfirst.3 b/alliance/share/man/man3/addbddvarfirst.3
deleted file mode 100644
index ef564c11..00000000
--- a/alliance/share/man/man3/addbddvarfirst.3
+++ /dev/null
@@ -1,59 +0,0 @@
-.\"   $Id: addbddvarfirst.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addbddvarfirst.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH ADDBDDVARFIRST 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-addbddvarfirst \- adds a new variable, before all others.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddnode \(**addbddvarfirst( BddSystem )
-  bddsystem \(**BddSystem;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.SH DESCRIPTION
-\fBaddbddvarfirst\fP creates a new variable, with the number 0,
-in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBaddbddvarfirst\fP returns a pointer to the \fBbdd\fP node of the new variable.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"no more variables, error !"
-.ft R
-.RS
-There is no variable number left.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddnode    \(**BddNode;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddNode = addbddvarfirst( (bddsystem \(**)0 );
-   destroybddsystem( (bddsystem \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addbddvarlast.3 b/alliance/share/man/man3/addbddvarlast.3
deleted file mode 100644
index 6a1e8180..00000000
--- a/alliance/share/man/man3/addbddvarlast.3
+++ /dev/null
@@ -1,59 +0,0 @@
-.\"   $Id: addbddvarlast.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addbddvarlast.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH ADDBDDVARLAST 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-addbddvarlast \- adds a new variable, after all others.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddnode \(**addbddvarlast( BddSystem )
-  bddsystem \(**BddSystem;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.SH DESCRIPTION
-\fBaddbddvarlast\fP creates a new variable, with the number
-\fIBddLocalSystem->NUMBER_VAR\fP in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBaddbddvarlast\fP returns a pointer to the \fBbdd\fP node of the new variable.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"no more variables, error !"
-.ft R
-.RS
-There is no variable number left.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddnode    \(**BddNode;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddNode = addbddvarlast( (bddsystem \(**)0 );
-   destroybddsystem( (bddsystem \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addcapa.3 b/alliance/share/man/man3/addcapa.3
deleted file mode 100644
index 1706cdaf..00000000
--- a/alliance/share/man/man3/addcapa.3
+++ /dev/null
@@ -1,57 +0,0 @@
-.\"   $Id: addcapa.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addcapa.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-addcapa
-.XE \}
-.TH ADDCAPA 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL FUNCTIONS"
-.SH NAME
-addcapa \- add a capacitance to a signal
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-void addcapa(ptsig, ctot)
-losig_list \(**ptsig;
-float ctot;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptfig\fP
-Pointer to the signal in which the capacitance should be added
-.TP
-\fIctot\fP
-Total capacitance
-.SH DESCRIPTION
-\fBaddcapa\fP add the \fIcapa\fP value to \fIptsig\->CAPA\fP.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-void more_capa(pt, i, c)
-lofig_list \(**pt;
-long i;
-float c;
-{
-	addcapa(getlosig(pt, i), c);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR losig (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addchain.3 b/alliance/share/man/man3/addchain.3
deleted file mode 100644
index a34b5876..00000000
--- a/alliance/share/man/man3/addchain.3
+++ /dev/null
@@ -1,80 +0,0 @@
-.\"   $Id: addchain.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addchain.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-addchain
-.XE
-.XS4 \n%
-.ti 0.2i
-addchain
-.XE4 \}
-.TH ADDCHAIN 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-addchain \- create a \fBchain\fP and add it to a list
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-chain_list \(**addchain(pthead, ptdata)
-chain_list \(**pthead;
-void \(**ptdata;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIpthead\fP
-Pointer to a \fBchain_list\fP
-.TP
-\fIptdata\fP
-Generic pointer to any kind of information
-.SH DESCRIPTION
-\fBaddchain\fP creates a new \fBchain\fP element and adds it to the
-front of the list pointed to by \fIpthead\fP, and becomes itself the list head.
-.br
-The \fBchain_list\fPs are mosty used to create temporary lists of homogeneous
-elements, for binary trees, and so on.
-.br
-The \fIptdata\fP points to any kind of list or may itself be a value, if proper
-cast is performed at compilation time, and fills the \fIDATA\fP field of the
-\fBchain\fP structure.
-For details on the structure, see \fBchain\fR(3).
-.SH RETURN VALUE
-\fBaddchain\fP returns a pointer to the new head of list.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-#include "mlo315.h"
-chain_list \(**get_external_connectors(ptfig)
-lofig_list \(**ptfig;
-{
-locon_list \(**pt = ptfig\->LOCON;
-chain_list \(**c = NULL; /\(** initialized for regularity \(**/
-	while (pt) {
-		if (pt\->TYPE == EXTERNAL)
-			c = addchain(c, (void \(**)pt)
-		pt = pt\->NEXT;
-	}	
-	return c;
-}	
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR chain (3),
-.BR freechain (3),
-.BR delchain (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addht.3 b/alliance/share/man/man3/addht.3
deleted file mode 100644
index 608bacf0..00000000
--- a/alliance/share/man/man3/addht.3
+++ /dev/null
@@ -1,81 +0,0 @@
-.\"   $Id: addht.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addht.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.\" slightly modified by Fred Petrot for mbk adaptation on 22/06/92
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-addht
-.XE
-.XS4 \n%
-.ti 0.2i
-addht
-.XE4 \}
-.TH ADDHT 3 "October 1, 1997" "ASIM/LIP6" "MBK HASH TABLE MANAGEMENT FUNCTIONS"
-.SH NAME
-addht \- create an hash table
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.nf
-#include "mut315.h"
-ht \(**addht(len)
-unsigned int len;
-.fi
-.ft R
-.SH PARAMETER
-.TP 20
-\fIlen\fP
-Number of entries in the hash table
-.SH DESCRIPTION
-\fBaddht()\fP creates a new hash table in memory.
-\fIlen\fP is an estimate of the maximum number of entries that the
-table will contain.
-This number may be automatically adjusted when using access functions
-by a dynamic reallocation, in order to warranty fast access time.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-ht \(**sigHtable(ptfig) /\(** h table suitable for signals \(**/
-lofig_list \(**ptfig;
-{
-losig_list \(**ptsig = ptfig->LOSIG;
-unsigned int i = 0;
-	while (ptsig) {
-		i++;
-		ptsig = ptsig->NEXT;
-	}
-	return addht(i);
-}
-.ft R
-.fi
-.SH ERROR
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** illegal addht : \fIlen\fP is '0'"
-.ft R
-.RS
-The hash table size cannot be zero, guess why!
-.RE
-.SH SEE ALSO
-.BR mbk (1),
-.BR delht (3),
-.BR addhtitem (3),
-.BR gethtitem (3),
-.BR sethtitem (3),
-.BR delhtitem (3),
-.BR viewht (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addhtitem.3 b/alliance/share/man/man3/addhtitem.3
deleted file mode 100644
index e26603a8..00000000
--- a/alliance/share/man/man3/addhtitem.3
+++ /dev/null
@@ -1,90 +0,0 @@
-.\"   $Id: addhtitem.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addhtitem.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.\" slightly modified by Fred Petrot for mbk adaptation on 22/06/92
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-addhtitem
-.XE
-.XS4 \n%
-.ti 0.2i
-addhtitem
-.XE4 \}
-.TH ADDHTITEM 3 "October 1, 1997" "ASIM/LIP6" "MBK HASH TABLE MANAGEMENT FUNCTIONS"
-.SH NAME
-addhtitem \- adds a new item in a hash table.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.nf
-#include "mut315.h"
-void addhtitem(table, key, value)
-ht \(**table;
-void \(**key;
-int value;
-.fi
-.ft R
-.SH PARAMETERS
-.TP 20
-\fItable\fP
-Hash table pointer
-.TP 20
-\fIkey\fP
-Key used by the hash coding function to add the item
-.TP 20
-\fIvalue\fP
-Value associated with the key
-.SH DESCRIPTION
-\fBaddhtitem()\fP adds a new item in the hash table pointed to by \fItable\fP.
-If the key already exists, the old value is changed to the new one.
-\fIValue\fP must be distinct from \fBEMPTYHT\fP and \fBDELETEHT\fP.
-The length of the table increases automatically when the length given
-in \fBaddht()\fP leads to a performance shut down.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.nf
-#include "mut315.h"
-void conHenter(h, ptfig)
-ht \(**h;
-lofig_list \(**ptfig;
-{
-locon_list \(**ptcon;
-	/\(** since connector names are unique, add them without check \(**/
-	for (ptcon = p->LOCON; ptcon; ptcon = ptcon->NEXT)
-		addhtitem(h, ptcon->NAME, 0);
-}
-.fi
-.ft R
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** addhtitem impossible :
-value is \fBEMPTYHT\fP or \fBDELETEHT\fP"
-.ft R
-.RS
-The values \fBEMPTYHT\fP, \fI-1\fP,  and \fBDELETEHT\fP, \fI-2\fP,
-are reserved for internal use, sorry.
-.SH DIAGNOSTICS
-The value must be distinct from \fI-1\fP and \fI-2\fP.
-.SH SEE ALSO
-.BR mbk (1),
-.BR addht (3),
-.BR delht (3),
-.BR gethtitem (3),
-.BR sethtitem (3),
-.BR delhtitem (3),
-.BR viewht (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addlocon.3 b/alliance/share/man/man3/addlocon.3
deleted file mode 100644
index 39949ab4..00000000
--- a/alliance/share/man/man3/addlocon.3
+++ /dev/null
@@ -1,111 +0,0 @@
-.\"   $Id: addlocon.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addlocon.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-addlocon
-.XE
-.XS2 \n%
-.ti 0.2i
-addlocon
-.XE2 \}
-.TH ADDLOCON 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL FUNCTIONS"
-.SH NAME
-addlocon \- create a logical connector
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-locon_list \(**addlocon(ptfig, name, ptsig, dir)
-lofig_list \(**ptfig;
-char \(**name;
-losig_list \(**ptsig;
-char dir;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptfig\fP
-Pointer to the figure in which the connector should be added
-.TP
-\fIname\fP
-Name of the connector
-.TP
-\fIptsig\fP
-Pointer on the signal linked to the connector
-.TP
-\fIdir\fP
-Connector direction type
-.SH DESCRIPTION
-\fBaddlocon\fP creates a new figure connector called \fIname\fP and adds it
-to the list of connectors pointed to by \fIptfig\->LOCON\fP.
-The new connector is added in front of the list, and becomes itself the
-list head.
-.br
-The parameters \fIname\fP, \fIptsig\fP, \fIdir\fP, 
-\fIwidth\fP fill respectivly the \fINAME\fP, \fISIG\fP and \fIDIR\fP
-fields of the \fIlocon\fP structure. The name should be unique at a given 
-hierarchical level since it's the connector identifier.
-.br
-The field \fITYPE\fP is set to \fBEXTERNAL\fP since a cell connector is
-beeing created. The instance connectors are builded up by the \fBaddloins\fP(3)
-call. See \fBaddloins\fP(3) for details.
-For a list of valid \fIdir\fP, see \fBlocon\fR(3).
-.SH RETURN VALUE
-\fBaddlocon\fP returns a pointer to the newly created connector.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** addlocon impossible : 
-connector \fIname\fP already exists in figure \fIptfig\->NAME\fP" 
-.ft R
-.RS
-The \fIname\fP beeing the logical connector idenfier, two connectors may not
-have the same name in a given figure.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** addlocon impossible :
-bad direction \fIdir\fP in \fIfigure ptfig\->NAME\fP"
-.ft R
-.RS
-The \fIdir\fP does not have a legal value. For the set of legal values, see
-\fIlocon\fP(3).
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-locon_list \(**du_con(ptfig, ptcon) /\(** duplicate connector \(**/
-lofig_list \(**ptfig;
-locon_list \(**ptcon;
-{
-   return addlocon(ptfig, ptcon\->NAME, ptcon\->SIG, ptcon\->DIR);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR locon (3),
-.BR loins (3),
-.BR lofig (3),
-.BR getlocon (3),
-.BR dellocon (3),
-.BR phcon (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addlofig.3 b/alliance/share/man/man3/addlofig.3
deleted file mode 100644
index 6ec9ab62..00000000
--- a/alliance/share/man/man3/addlofig.3
+++ /dev/null
@@ -1,90 +0,0 @@
-.\"   $Id: addlofig.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addlofig.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-addlofig
-.XE
-.XS2 \n%
-.ti 0.2i
-addlofig
-.XE2 \}
-.TH ADDLOFIG 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL FUNCTIONS"
-.SH NAME
-addlofig \- create a new structural cell model 
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-lofig_list \(**addlofig(figname)
-char \(**figname;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIfigname\fP
-Name of the figure to be created
-.SH DESCRIPTION
-\fBaddlofig\fP creates a new figure called \fIfigname\fP and adds it to the
-list of figure in memory. The new figure is added in front of the list, and
-becomes itself the list head. No check is performed to see if a figure with
-the \fIfigname\fP exists on disk. If it is the case, the preexisting file will
-be erased while saving.
-.br
-The fields \fILOCON\fP, \fILOINS\fP, \fILOSIG\fP, \fIBKSIG\fP, \fILOPAR\fP
-\fILOTRS\fP and \fIUSER\fP are set to \fBNULL\fP.
-.br
-The field \fIMODE\fP is set to \fB'A'\fP.
-.br
-The field \fINEXT\fP points to the previous head of list.
-.SH RETURN VALUE
-\fBaddlofig\fP returns a pointer to the newly created figure.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** illegal addlofig figure \fIfigname\fP already exists"
-.ft R
-.RS
-There is already a logical figure called \fIfigname\fP in memory, so it's
-impossible to give this name to a cell to be created.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-lofig_list \(**get_the_fig(name)
-char \(**name;
-{
-lofig_list \(**pt, \(**fill_fig(/\(** lofig_list \(** \(**/);
-	/\(** scan figure list \(**/
-	for (pt = HEAD_LOFIG; pt; pt = pt\->NEXT)
-		if (!strcmp(pt\->NAME, figname))
-			break;
-	return pt ? pt : fill_fig(addlofig(figname));
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR lofig (3),
-.BR getlofig (3),
-.BR dellofig (3),
-.BR loadlofig (3),
-.BR savelofig (3),
-.BR flattenlofig (3),
-.BR rflattenlofig (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addloins.3 b/alliance/share/man/man3/addloins.3
deleted file mode 100644
index da2ce58f..00000000
--- a/alliance/share/man/man3/addloins.3
+++ /dev/null
@@ -1,136 +0,0 @@
-.\"   $Id: addloins.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addloins.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-addloins
-.XE
-.XS2 \n%
-.ti 0.2i
-addloins
-.XE2 \}
-.TH ADDLOINS 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL FUNCTIONS"
-.SH NAME
-addloins \- create a logical instance
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-loins_list \(**addloins(ptfig, insname, ptmodel, sigchain)
-lofig_list \(**ptfig;
-char \(**insname;
-lofig_list \(**ptmodel;
-chain_list \(**sigchain;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptfig\fP
-Pointer to the figure in which the instance should be added
-.TP
-\fIinsname\fP
-Instance name
-.TP
-\fIptmodel\fP
-Pointer to the instance model
-.TP
-\fIsigchain\fP
-Pointer to chain list of signal pointers
-.SH DESCRIPTION
-\fBaddloins\fP creates a new instance, and adds it to the
-list of instances pointed to by \fIptfig\->LOINS\fP. The new instance is 
-added in front of the list, and becomes itself the list head.
-.br
-The parameter \fIinsname\fP fills the \fIINSNAME\fP field of the \fIloins\fP
-structure.
-.br
-The \fIptmodel\fP is used for two purposes. First, the \fIptmodel\->NAME\fP
-fills the \fIFIGNAME\fP field. Second, the connectors of the figure pointed
-to by \fIptmodel\fP are duplicated in the \fILOCON\fP field, but the signals
-linked to each connector are the one given in the \fIsigchain\fP argument. See
-\fBchain\fP(3) for details on \fBchain_list\fPs.
-.br
-The matching is done in order, it means that the first connector is linked
-to the first signal of the \fIsigchain\fP, and so on. Care must be taken when
-instanciating in order to warranty the validity of the netlist.
-For details on the structure, see \fBloins\fR(3).
-.SH RETURN VALUE
-\fBaddloins\fP returns a pointer to the newly created instance.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** addloins impossible : instance \fIinsname\fP already 
-exist in figure \fIptfig\->NAME\fP"
-.ft R
-.RS
-The \fIinsname\fP is the instance identifier. So it must be unique at a given
-hierarchy level.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** addloins impossible : instance model is the 
-figure \fIfigname\fP itself"
-.ft R
-.RS
-The model of the instance has the same name that the figure where the
-instantiation takes place. This check is only performed for a single hierarchy
-level, in terms of its instances. 
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** addloins impossible : connector number discrepancy
-between figure \fIptmodel\->NAME\fP and instance \fIinsname\fP
-in figure \fIptfig\->NAME\fP"
-.ft R
-.RS
-The number of signals in the \fIsigchain\fP is not equal to the number of
-connectors of the model. The matching is not done correctly.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-void add_na2_y(pt, in1, in2, out) /\(** add an instance of na2_y \(**/
-lofig_list \(**pt; /\(** pointer to the figure \(**/
-long in1, in2, out; /\(** signals indexes \(**/
-{
-chain_list \(**signal = NULL;
-	/\(** get the pointer when signal index is known \(**/
-	signal = addchain(signal, (void \(**)givelosig(pt, in1));
-	signal = addchain(signal, (void \(**)givelosig(pt, in2));
-	signal = addchain(signal, (void \(**)givelosig(pt, out));
-	/\(** get vdd and vss \(**/
-	signal = addchain(signal, (void \(**)give_vdd(pt));
-	signal = addchain(signal, (void \(**)give_vss(pt));
-	/\(** reverse the list \(**/
-	signal = reverse(signal);
-	addloins(pt, "nand", getlofig("na2_y"), signal);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR lofig (3),
-.BR loins (3),
-.BR chain (3),
-.BR getloins (3),
-.BR delloins (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addlomodel.3 b/alliance/share/man/man3/addlomodel.3
deleted file mode 100644
index 7216d73d..00000000
--- a/alliance/share/man/man3/addlomodel.3
+++ /dev/null
@@ -1,83 +0,0 @@
-.\"   $Id: addlomodel.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addlomodel.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-addlomodel
-.XE
-.XS2 \n%
-.ti 0.2i
-addlomodel
-.XE2 \}
-.TH ADDLOMODEL 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL FUNCTIONS"
-.SH NAME
-addlomodel \- create a tempotary logical model and add it to a list
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-lofig_list \(**addlomodel(model, name)
-lofig_list \(**model;
-char \(**name;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fImodel\fP
-Pointer to the head of a model list
-.TP
-\fIname\fP
-Name of the model to be created
-.SH DESCRIPTION
-\fBaddlomodel\fP creates a new \fBlofig_list\fP element and adds it to the
-front of the list pointed to by \fImodel\fP, and becomes itself the list head.
-.br
-The \fBaddlomodel\fP function is mosty used to create a temporary list of
-\fBlofig\fP in order to represent the "in file" instances' models.
-In fact, all the file format used with mbk have the notion of models local to
-files, so they are not figure, but are temporarly used to create instance
-connectors, for example.
-For details on the structure, see \fBlofig\fR(3).
-.SH RETURN VALUE
-\fBaddlomodel\fP returns a pointer to the new head of model list.
-.SH ERROR
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** addlomodel impossible : model \fIname\fP already exists"
-.ft R
-.RS
-The model, not the figure, is already present in the model list pointed to by
-\fImodel\fP, and since a model should be unique, this can't be.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut404.h"
-#include "mlo404.h"
-void add_model(name)
-char \(**name;
-{
-	MODEL = addlomodel(MODEL, name);
-}	
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR lofig (3),
-.BR getlomodel (3),
-.BR freelomodel (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addlosig.3 b/alliance/share/man/man3/addlosig.3
deleted file mode 100644
index 5640ecb7..00000000
--- a/alliance/share/man/man3/addlosig.3
+++ /dev/null
@@ -1,118 +0,0 @@
-.\"   $Id: addlosig.3,v 1.2 2002/01/22 18:54:57 xtof Exp $
-.\" @(#)addlosig.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-addlosig
-.XE
-.XS2 \n%
-.ti 0.2i
-addlosig
-.XE2 \}
-.TH ADDLOSIG 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL FUNCTIONS"
-.SH NAME
-addlosig \- create a logical signal
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-losig_list \(**addlosig(ptfig, index, namechain, type)
-lofig_list \(**ptfig;
-long index;
-chain_list \(**namechain;
-char type;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptfig\fP
-Pointer to the figure in which the signal should be added
-.TP
-\fIindex\fP
-Signal index
-.TP
-\fInamechain\fP
-List of names of the signal
-.TP
-\fItype\fP
-Signal type
-.SH DESCRIPTION
-\fBaddlosig\fP creates a new signal, and adds it to the
-list of signals pointed to by \fIptfig\->LOSIG\fP. The new signal is 
-added in front of the list, and becomes itself the list head.
-.br
-The \fItype\fP parameter can take two values :
-.RS
-.TP 20
-\fBEXTERNAL\fP
-The signal is attached to at least one connector of the figure.
-.TP
-\fBINTERNAL\fP
-The signal is only attached to instance or transistor connector.
-.RE
-The \fIindex\fP and \fItype\fP arguments fill the \fIINDEX\fP and
-\fITYPE\fP fields of the \fBlosig\fP(3) structure. The index
-is the signal identifier, so it should be unique at a given hierarchical level.
-.br
-The \fInamechain\fP argument is a list of names, given in a \fBchain_list\fP.
-See \fBchain\fP(3) for details. 
-.SH RETURN VALUE
-\fBaddlosig\fP returns a pointer to the newly created signal.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** addlosig impossible signal \fIindex\fP already exist
-in figure \fIptfig\->NAME\fP"
-.ft R
-.RS
-The \fIindex\fP is already used in an other signal, and since it's the signal
-identifier, it can't be.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-losig_list \(**merge_and_create(pt, s0, s1) /\(** merge two signal in a third \(**/
-lofig_list \(**pt;
-losig_list \(**s0, \(**s1;
-{
-chain_list \(**c;
-losig_list \(**s;
-long max_index;
-	/\(** merge names \(**/
-	for (c = s0\->NAMECHAIN; c; c = c\->NEXT)
-		s1\->NAMECHAIN = addchain(s1\->NAMECHAIN, c);
-	/\(** find maximum index \(**/
-	for (s = pt\->LOSIG; s; s = s\->NEXT)
-		if (max_index < s\->INDEX)
-			max_index = s\->INDEX;
-	s = addlosig(pt, ++max_index, s1\->NAMECHAIN,
-			s0\->TYPE == EXTERNAL || s1\->TYPE == EXTERNAL ?
-			EXTERNAL : INTERNAL);
-	dellosig(pt, s0);
-	dellosig(pt, s1);
-	return s;
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR lofig (3),
-.BR losig (3),
-.BR getlosig (3),
-.BR dellosig (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addlotrs.3 b/alliance/share/man/man3/addlotrs.3
deleted file mode 100644
index 1617dad3..00000000
--- a/alliance/share/man/man3/addlotrs.3
+++ /dev/null
@@ -1,135 +0,0 @@
-.\"   $Id: addlotrs.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addlotrs.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-addlotrs
-.XE
-.XS2 \n%
-.ti 0.2i
-addlotrs
-.XE2 \}
-.TH ADDLOTRS 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL FUNCTIONS"
-.SH NAME
-addlotrs \- create a logical transistor
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.ta 3n 23n
-#include "mlo404.3"
-lotrs_list \(**addlotrs(ptfig, type, x, y, width, length,
-		ps, pd, xs, xd,
-		ptgrid, ptsource, ptdrain)
-lofig_list \(**ptfig;
-char type;
-long x, y;
-unsigned short width, length;
-unsigned short ps, pd;
-unsigned short xs, xd;
-losig_list \(**ptgrid, \(**ptsource, \(**ptdrain;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptfig\fP
-Pointer to the figure in which the transistor should be added
-.TP
-\fItype\fP
-transistor type
-.TP
-\fIx, y\fP
-Transistor coordinates
-.TP
-\fIwidth, length\fP
-Transistor grid width and length
-.TP
-\fIps, pd\fP
-Perimeters of the source and drain
-.TP
-\fIxs, xd\fP
-Values to compute the areas of the source and drain, see \fBlotrs\fP(3)
-for the effective area computation
-.TP
-\fIptgrid\fP
-Pointer to the signal to be connected on the transistor grid
-.TP
-\fIptsource\fP
-Pointer to the signal to be connected on the transistor source
-.TP
-\fIptdrain\fP
-Pointer to the signal to be connected on the transistor drain
-.SH DESCRIPTION
-\fBaddlotrs\fP creates a new transistor, and adds it to the
-list of transistors pointed to by \fIptfig\->LOTRS\fP. The new transistor is 
-added in front of the list, and becomes itself the list head.
-.br
-The \fItype\fP parameter can take two values :
-.RS
-.TP 20
-\fBTRANSN\fP
-for a N channel transistor
-.TP
-\fBTRANSP\fP
-for a P channel transistor
-.RE
-.LP
-The \fIx\fP, \fIy\fP, \fIwidth\fP , \fIlength\fP, \fIps\fP, \fIpd\fP,
-\fIxs\fP and \fIxd\fP,  arguments fill
-respectivly the \fIX\fP, \fIY\fP, \fIWIDTH\fP, \fILENGTH\fP, \fIPS\fP,
-\fIPD\fP, \fIXS\fP and \fIXD\fP fields.
-.br
-Three connectors are created each time a transistor is added, and the
-\fIptgrid\fP, \fIptsource\fP and \fIptdrain\fP \fBlosig\fPs are attached to
-the \fISIG\fP field of the \fBlocon\fP of the appropriate connector. The
-connectors names are \fIgrid\fP, \fIsource\fP and \fIdrain\fP, their
-direction, \fIDIR\fP, are set to \fB'T'\fP, and their \fITYPE\fP \fBINTERNAL\fP.
-For details on the structures, see \fBlocon\fP(3) and \fBlotrs\fR(3).
-.SH RETURN VALUE
-\fBaddlotrs\fP returns a pointer to the newly created transistor.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** illegal transistor type : \fItype\fP"
-.ft R
-.RS
-The \fItype\fP is not legal a legal transistor type.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-void n1_y() /\(** transistor netlist of an inverter \(**/
-{
-lofig_list \(**pt;
-losig_list \(**in, \(**out, \(**vdd, \(**vss;
-	pt = addlofig("n1_y");
-	addlocon(pt, "in", in = givelosig(pt, 0), IN);
-	addlocon(pt, "out", out = givelosig(pt, 1), OUT);
-	addlocon(pt, "vdd", vdd = givelosig(pt, 2), IN);
-	addlocon(pt, "vss", vdd = givelosig(pt, 3), IN);
-	addlotrs(pt, TRANSN, 0, 0, 6, 1, in, vss, out);
-	addlotrs(pt, TRANSP, 0, 0, 12, 1, in, vdd, out);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR lofig (3),
-.BR lotrs (3),
-.BR locon (3),
-.BR dellotrs (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addnum.3 b/alliance/share/man/man3/addnum.3
deleted file mode 100644
index 8926958f..00000000
--- a/alliance/share/man/man3/addnum.3
+++ /dev/null
@@ -1,73 +0,0 @@
-.\"   $Id: addnum.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addnum.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-addnum
-.XE
-.XS4 \n%
-.ti 0.2i
-addnum
-.XE4 \}
-.TH ADDNUM 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-addnum \- create a \fBnum\fP and add it to a list
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-num_list \(**addnum(ptnum, data)
-num_list \(**ptnum;
-long data;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptnum\fP
-Pointer to a \fBnum_list\fP
-.TP
-\fIdata\fP
-Value of the data
-.SH DESCRIPTION
-\fBaddnum\fP creates a new \fBnum\fP element and adds it to the
-front of the list pointed to by \fIptnum\fP, and becomes itself the list head.
-.br
-The \fIdata\fP fills the \fIDATA\fP field of the \fBnum\fP strucutre.
-For details on the structure, see \fBnum\fR(3).
-.SH RETURN VALUE
-\fBaddnum\fP returns a pointer to the new head of list.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-#include "mlo315.h"
-void count(pn)
-num_list \(**pn;
-{
-num_list \(**c = NULL; /\(** initialized for regularity \(**/
-	while (pt) {
-		if (pt\->TYPE == EXTERNAL)
-			c = addnum(c, (void \(**)pt)
-		pt = pt\->NEXT;
-	}	
-	return c;
-}	
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR num (3),
-.BR freenum (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addphcon.3 b/alliance/share/man/man3/addphcon.3
deleted file mode 100644
index 8e6e9edd..00000000
--- a/alliance/share/man/man3/addphcon.3
+++ /dev/null
@@ -1,140 +0,0 @@
-.\"   $Id: addphcon.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addphcon.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-addphcon
-.XE
-.XS0 \n%
-.ti 0.2i
-addphcon
-.XE0 \}
-.TH ADDPHCON 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL FUNCTIONS"
-.SH NAME
-addphcon \- create a physical connector
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-phcon_list \(**addphcon(ptfig, orient, conname, x, y, layer, width)
-phfig_list \(**ptfig;
-char orient;
-char \(**conname;
-long x, y;
-char layer;
-long width;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptfig\fP
-Pointer to the figure in which the connector should be added
-.TP
-\fIorient\fP
-Face of the connector
-.TP
-\fIconname\fP
-Name of the connector
-.TP
-\fIx, y\fP
-Absolute connector coordinates
-.TP
-\fIlayer\fP
-Connector symbolic layer
-.TP
-\fIwidth\fP
-Connector symbolic width
-.SH DESCRIPTION
-\fBaddphcon\fP creates a new connector called \fIconname\fP and adds it to the
-list of connectors pointed to by \fIptfig\->PHCON\fP. The new connector is 
-added in front of the list, and becomes itself the list head. 
-.br
-The parameters \fIconname\fP, \fIorient\fP, \fIx\fP, \fIy\fP, \fIlayer\fP, 
-\fIwidth\fP fill respectivly the \fINAME\fP, \fIORIENT\fP, \fIXCON\fP,
-\fIYCON\fP, \fILAYER\fP, \fIWIDTH\fP fields of the \fIphcon\fP structure.
-See \fBphcon\fR(3) for details.
-.br
-The \fIINDEX\fP field is computed by the \fBaddphcon\fP function in order to
-warranty index unicity. A topological sort is performed, checking \fIx\fP,
-then \fIy\fP, then the \fIlayer\fP. So for a given figure, each connector will
-have a constant \fIINDEX\fP.
-.br
-The \fIx\fP, \fIy\fP coordinates must be placed inside the \fIbutment box\fP
-of the figure.
-.br 
-The \fIwidth\fP is a layer extension that takes place in parallel to the 
-connector face.
-.br
-For a list of valid \fIorient\fP and \fIlayer\fPs, see
-\fBlocon\fR(3).
-.SH RETURN VALUE
-\fBaddphcon\fP returns a pointer to the newly created connector.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** illegal addphcon unknow layer \fIlayer\fP in \fIconname\fP"
-.ft R
-.RS
-The \fIlayer\fP parameter is out of range, and does not represent a legal
-symbolic layer. See \fBlocon\fP(3) for a complete list of layers.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** illegal addphcon connector \fIconname\fP not in
-abutment box"
-.ft R
-.RS
-The connector coordinates are not included in the rectangle of the figure 
-\fIabutment\fP box. This means that the \fIabutment box\fP field of the
-\fIphfig\fP must be filled befor any call to \fBaddphcon\fP.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** illegal addphcon orientation is \fIorient\fP in 
-\fIconname\fP"
-.ft R
-.RS
-The \fIorient\fP parameter is not in the set of legal values. See 
-\fBlocon\fP(3) for the complete list of orientations.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-phcon_list \(**du_con(ptfig, ptcon) /\(** duplicate connector \(**/
-phfig_list \(**ptfig;
-phcon_list \(**ptcon;
-{
-   /\(** the index depends from what's in ptfig\->PHCON, not from me \(**/
-   return addphcon(ptfig, ptcon\->ORIENT, ptcon\->NAME,
-                   ptcon\->XCON, ptcon\->YCON,
-                   ptcon\->LAYER, ptcon\->WIDTH);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR phfig (3),
-.BR phcon (3),
-.BR getphcon (3),
-.BR delphcon (3),
-.BR locon (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addphfig.3 b/alliance/share/man/man3/addphfig.3
deleted file mode 100644
index f45a8987..00000000
--- a/alliance/share/man/man3/addphfig.3
+++ /dev/null
@@ -1,93 +0,0 @@
-.\"   $Id: addphfig.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addphfig.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-addphfig
-.XE
-.XS0 \n%
-.ti 0.2i
-addphfig
-.XE0 \}
-.TH ADDPHFIG 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL FUNCTIONS"
-.SH NAME
-addphfig \- create a new physical cell model 
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-phfig_list \(**addphfig(figname)
-char \(**figname;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIfigname\fP
-Name of the figure to be created
-.SH DESCRIPTION
-\fBaddphfig\fP creates a new figure called \fIfigname\fP and adds it to the
-list of figure in memory. The new figure is added in front of the list, and
-becomes itself the list head. No check is performed to see if a figure with
-the \fIfigname\fP exists on disk. If it is the case, the preexisting file will
-be erased while saving.
-.br
-The fields \fIPHCON\fP, \fIPHINS\fP, \fIPHSEG\fP, \fIPHVIA\fP, \fIPHREF\fP and
-\fIUSER\fP are set to \fBNULL\fP.
-.br
-The fields \fIXAB1\fP,  \fIYAB1\fP,  \fIXAB2\fP,  \fIXAB2\fP are set to
-\fB0L\fP.
-.br
-The field \fIMODE\fP is set to \fB'A'\fP.
-.br
-The field \fINEXT\fP points to the previous head of list.
-.SH RETURN VALUE
-\fBaddphfig\fP returns a pointer to the newly created figure.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** illegal addphfig figure \fIfigname\fP already exists"
-.ft R
-.RS
-There is already a figure called \fIfigname\fP in memory, so it's impossible
-to give this name to a cell to be created.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-phfig_list \(**get_the_fig(name)
-char \(**name;
-{
-phfig_list \(**pt, \(**fill_fig(/\(** phfig_list \(** \(**/);
-	/\(** scan figure list \(**/
-	for (pt = HEAD_PHFIG; pt; pt = pt\->NEXT)
-		if (!strcmp(pt\->NAME, figname))
-			break;
-	return pt ? pt : fill_fig(addphfig(figname));
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR phfig (3),
-.BR getphfig (3),
-.BR delphfig (3),
-.BR loadphfig (3),
-.BR savephfig (3),
-.BR flattenphfig (3),
-.BR rflattenphfig (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addphins.3 b/alliance/share/man/man3/addphins.3
deleted file mode 100644
index d336ba9d..00000000
--- a/alliance/share/man/man3/addphins.3
+++ /dev/null
@@ -1,129 +0,0 @@
-.\"   $Id: addphins.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addphins.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-addphins
-.XE
-.XS0 \n%
-.ti 0.2i
-addphins
-.XE0 \}
-.TH ADDPHINS 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL FUNCTIONS"
-.SH NAME
-addphins \- create a physical instance
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-phins_list \(**addphins(ptfig, figname, insname, sym, x, y)
-phfig_list \(**ptfig;
-char \(**figname;
-char \(**insname;
-char sym;
-long x, y;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptfig\fP
-Pointer to the figure in which the instance should be added
-.TP
-\fIfigname\fP
-Instance model name
-.TP
-\fIinsname\fP
-Instance name
-.TP
-\fIsym\fP
-Geometrical operation performed on the instance
-.TP
-\fIx, y\fP
-Coordinates of the lower left corner of the instance
-.SH DESCRIPTION
-\fBaddphins\fP creates a new instance whose lower left corner is at the given
-coordinates, and adds it to the
-list of instances pointed to by \fIptfig\->PHINS\fP. The new instance is 
-added in front of the list, and becomes itself the list head.
-.br
-The parameters \fIfigname\fP, \fIinsname\fP, \fIsym\fP, \fIx\fP and \fIy\fP
-fill respectivly
-the \fIFIGNAME\fP, \fIINSNAME\fP, \fITRANSF\fP, \fIXINS\fP and \fIYINS\fP
-fields of the \fIphins\fP structure.
-.br
-The \fBaddphins\fP function does not check in memory or on disk to see
-if the instanciated model exists, since no informations on it are needed.
-.br
-The coordinates are not transformation dependant. It means that the 
-transformation is performed before placing the instance at the given point.
-For details on the structure, see \fBphins\fR(3).
-.SH RETURN VALUE
-\fBaddphins\fP returns a pointer to the newly created instance.
-.SH ERRORS
-.LP
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** addphins figure \fIfigname\fP cannot be part of itself"
-.ft R
-.RS
-The instance has for model name of the figure on the which it is to be added.
-It's illegal and dangerous. This check is made at the actual hierachy level
-only, not recursivly on the structure, so it still may happend.
-.RE
-.LP
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** illegal addphins transformation \fIsym\fP in : \fIinsname\fP"
-.ft R
-.RS
-The geometrical operation is not in the legal range. See \fBphins\fP(3) for
-a complete list of values.
-.RE
-.LP
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** illegal addphins duplicate instance name : \fIinsname\fP"
-.ft R
-.RS
-The instance name is an identifier, so it can't appear twice in the same figure.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-phins_list \(**ins_dup(pfd, pfs) /\(** duplicate instances \(**/
-phfig_list \(**pfd, \(**pfs;
-{
-phins_list \(**pi;
-	for (pi = pfs\->phins; pi != NULL; pi = pi\->NEXT)
-		addphins(pfd, pi\->FIGNAME, pi\->INSNAME, pi\->TRANSF,
-                         pi\->XINS, pi\->YINS);
-	return pfd\->PHINS;
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR phfig (3),
-.BR phins (3),
-.BR getphins (3),
-.BR delphins (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addphref.3 b/alliance/share/man/man3/addphref.3
deleted file mode 100644
index 2602582c..00000000
--- a/alliance/share/man/man3/addphref.3
+++ /dev/null
@@ -1,93 +0,0 @@
-.\"   $Id: addphref.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addphref.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-addphref
-.XE
-.XS0 \n%
-.ti 0.2i
-addphref
-.XE0 \}
-.TH ADDPHREF 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL FUNCTIONS"
-.SH NAME
-addphref \- create a physical reference
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-phref_list \(**addphref(ptfig, type, name, x, y)
-phfig_list \(**ptfig;
-char \(**type;
-char \(**name;
-long x, y;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptfig\fP
-Pointer to the figure in which the reference should be added
-.TP
-\fItype\fP
-Reference type
-.TP
-\fIname\fP
-Reference name
-.TP
-\fIx, y\fP
-Coordinates of the center of the reference.
-.SH DESCRIPTION
-\fBaddphref\fP creates a new reference whose center is at the given coordinates,
-and adds it to the
-list of references pointed to by \fIptfig\->PHREF\fP. The new reference is 
-added in front of the list, and becomes itself the list head.
-.br
-The parameters \fItype\fP, \fIname\fP, \fIx\fP and \fIy\fP fill respectivly
-the \fIFIGNAME\fP, \fINAME\fP, \fIXREF\fP and \fIYREF\fP fields of the
-\fIphref\fP structure.
-.br
-The \fItype\fPs may have any value, but only two type
-are now recognized by tools based upon mbk :
-.TP 20
-\fB"ref_con"\fP
-for multi-access connectors
-.TP
-\fB"ref_ref"\fP
-for cell programming
-.LP
-For details on the structure, see \fBphref\fR(3).
-.SH RETURN VALUE
-\fBaddphref\fP returns a pointer to the newly created reference.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-phref_list \(**ref_dup(pfd, pfs) /\(** duplicate refs \(**/
-phfig_list \(**pfd, \(**pfs;
-{
-phref_list \(**pr;
-	for (pr = pfs\->phref; pr != NULL; pr = pr\->NEXT)
-		addphref(pfd, pr\->FIGNAME, pr\->NAME, pr\->XREF, pr\->YREF);
-	return pfd\->PHREF;
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR phfig (3),
-.BR phref (3),
-.BR getphref (3),
-.BR delphref (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addphseg.3 b/alliance/share/man/man3/addphseg.3
deleted file mode 100644
index 94365a6c..00000000
--- a/alliance/share/man/man3/addphseg.3
+++ /dev/null
@@ -1,123 +0,0 @@
-.\"   $Id: addphseg.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addphseg.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-addphseg
-.XE
-.XS0 \n%
-.ti 0.2i
-addphseg
-.XE0 \}
-.TH ADDPHSEG 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL FUNCTIONS"
-.SH NAME
-addphseg \- create a physical segment
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-phseg_list \(**addphseg(ptfig, layer, width, x1, y1, x2, y2, nodename)
-phfig_list \(**ptfig;
-char layer;
-long width;
-long x1, y1, x2, y2;
-char \(**nodename;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptfig\fP
-Pointer to the figure in which the segment should be added
-.TP
-\fIlayer\fP
-Segment symbolic layer
-.TP
-\fIwidth\fP
-Segment symbolic width
-.TP
-\fIx1, y1, x2, y2\fP
-Segment endpoints coordinates
-.TP
-\fInodename\fP
-Name of the segment
-.SH DESCRIPTION
-\fBaddphseg\fP creates a new segment at the given coordinates, possibly called
-\fIsegname\fP, and adds it to the list of segments pointed to by
-\fIptfig\->PHSEG\fP. The new segment is
-added in front of the list, and becomes itself the list head. The segment name
-is an optional information, and does not allow the segment identification. When
-not needed, this parameter should be set to \fINULL\fP.
-.br
-The parameters \fInodename\fP, \fIlayer\fP and \fIwidth\fP fill respectivly
-the \fINAME\fP, \fILAYER\fP and \fIWIDTH\fP fields of the \fIphseg\fP structure.
-.br
-\fIx1\fP, \fIy1\fP, \fIx2\fP, \fIy2\fP are sorted to warranty that the fields
-\fIX1\fP and \fIY1\fP contain the minimum of, respectivly, \fIx1\fP, \fIx2\fP
-and \fIy1\fP, \fIy2\fP, and the \fIX2\fP, \fIY2\fP fields the maximum.
-.br
-The \fITYPE\fP field is computed by the \fBaddphseg\fP function.
-It will be either \fBVER\fP if \fIx1\fP equals \fIx2\fP, or \fBHOR\fP if
-\fIy1\fP equals \fIy2\fP.
-.br
-The \fIwidth\fP is a layer extension that takes place in perpendicular to the
-segment \fITYPE\fP.
-.br
-For a list of valid \fIlayer\fPs, and details on the structure, see
-\fBphseg\fR(3).
-.SH RETURN VALUE
-\fBaddphseg\fP returns a pointer to the newly created segment.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** illegal addphseg wrong layer code \fIlayer\fP in
-\fIx1\fP, \fIy1\fP, \fIx2\fP, \fIy2\fP"
-.ft R
-.RS
-The \fIlayer\fP parameter is out of range, and does not represent a legal
-symbolic layer. See \fBphseg\fP(3) for a complete list of layers.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** illegal addphseg : \fIx1\fP, \fIy1\fP, \fIx2\fP, \fIy2\fP"
-.ft R
-.RS
-The segment coordinates are such that the segment is neither vertical nor
-horizontal. So it's not a legal symbolic segment.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-phseg_list \(**du_seg(pfd, pfs)
-phfig_list \(**pfd, \(**pfs;
-{
-phseg_list \(**ps;
-	/\(** names don't matter \(**/
-	for (ps = pfs\->PHSEG; ps != NULL; ps = ps\->NEXT)
-		addphseg(pfd, ps\->LAYER, ps\->WIDTH, ps\->X1, ps\->Y1,
-				ps\->X2, ps\->Y2, NULL);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR phfig (3),
-.BR phseg (3),
-.BR delphseg (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addphvia.3 b/alliance/share/man/man3/addphvia.3
deleted file mode 100644
index 90eeac5b..00000000
--- a/alliance/share/man/man3/addphvia.3
+++ /dev/null
@@ -1,91 +0,0 @@
-.\"   $Id: addphvia.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addphvia.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-addphvia
-.XE
-.XS0 \n%
-.ti 0.2i
-addphvia
-.XE0 \}
-.TH ADDPHVIA 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL FUNCTIONS"
-.SH NAME
-addphvia \- create a physical via
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-phvia_list \(**addphvia(ptfig, viatype, x, y)
-phfig_list \(**ptfig;
-char viatype;
-long x, y;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptfig\fP
-Pointer to the figure in which the via should be added
-.TP
-\fIviatype\fP
-Contact type
-.TP
-\fIx, y\fP
-Coordinates of the center of the via.
-.SH DESCRIPTION
-\fBaddphvia\fP creates a new via whose center is at the given coordinates,
-and adds it to the
-list of vias pointed to by \fIptfig\->PHVIA\fP. The new via is 
-added in front of the list, and becomes itself the list head.
-.br
-The parameters \fIviatype\fP, \fIx\fP and \fIy\fP fill respectivly
-the \fITYPE\fP, \fIXVIA\fP and \fIYVIA\fP fields of the \fIphvia\fP structure.
-.br
-For a list of valid \fIviatype\fPs, and details on the structure, see
-\fBphvia\fR(3).
-.SH RETURN VALUE
-\fBaddphvia\fP returns a pointer to the newly created via.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** illegal addphvia viatype : \fIviatype\fP at
-\fIx\fP, \fIy\fP"
-.ft R
-.RS
-The via type is not a predefined contact. For a list of legal via types,
-see \fBphvia\fP(3).
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-phvia_list \(**via_dup(pfd, pfs) /\(** duplicate vias \(**/
-phfig_list \(**pfd, \(**pfs;
-{
-phvia_list \(**pv;
-	for (pv = pfs\->phvia; pv != NULL; pv = pv\->NEXT)
-		addphvia(pfd, pv\->TYPE, ps\->XVIA, ps\->YVIA);
-	return pfd\->PHVIA;
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR phfig (3),
-.BR phvia (3),
-.BR delphvia (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addptype.3 b/alliance/share/man/man3/addptype.3
deleted file mode 100644
index 55cb3211..00000000
--- a/alliance/share/man/man3/addptype.3
+++ /dev/null
@@ -1,91 +0,0 @@
-.\"   $Id: addptype.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addptype.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-addptype
-.XE
-.XS4 \n%
-.ti 0.2i
-addptype
-.XE4 \}
-.TH ADDPTYPE 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-addptype \- create a \fBptype\fP and add it to a \fBptype_list\fP
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-ptype_list \(**addptype(pthead,type,ptdata)
-ptype_list \(**pthead;
-void \(**ptdata;
-long type;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIpthead\fP
-Pointer to a \fBptype\fP list
-.TP
-\fItype\fP
-Flag indicating the pointer owner
-.TP
-\fIptdata\fP
-Generic pointer to any kind of information
-.SH DESCRIPTION
-\fBaddptype\fP creates a new \fBptype\fP element and adds it to the
-front of the list pointed to by \fIpthead\fP, and becomes itself the list head.
-.br
-The \fBptype_list\fPs are mosty used to create lists of homogeneous
-elements in mbk, but also for trees, graphs, and so on.
-.br
-The \fItype\fP argument indicates the pointer type, at the C type meaning,
-for its owner.
-.br
-The \fItype\fPs allow to access the pointers with adequat cast, and for example
-to share informations in the \fIUSER\fP fields of mbk structures. 
-.br
-The \fIptdata\fP points to any kind of list or may itself be a value, if proper
-cast is performed at compilation time, and fills the \fIDATA\fP field of the
-\fBptype\fP structure.
-For details on the structure, see \fBptype\fR(3).
-.SH RETURN VALUE
-\fBaddptype\fP returns a pointer to the new head of list.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-#include "mph315.h"
-void corner(ptfig, name)
-phfig_list \(**ptfig;
-char \(**name;
-{
-phins_list \(**i = getphins(ptfig, name);
-num_list \(**ptnum;
-phfig_list \(**model;
-	model = getphfig(i\->FIGNAME);
-	ptnum = addnum((num_list \(**)NULL, model\->X2 - model\->X1);
-	ptnum = addnum(ptnum, model\->Y2 - model\->Y1);
-	i\->USER = addptype(i\->USER, (long)PLACEABOX, (void \(**)ptnum);
-}	
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR ptype (3),
-.BR freeptype (3),
-.BR getptype (3),
-.BR delptype (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addrdsfig.3 b/alliance/share/man/man3/addrdsfig.3
deleted file mode 100644
index 44be0932..00000000
--- a/alliance/share/man/man3/addrdsfig.3
+++ /dev/null
@@ -1,94 +0,0 @@
-.\"   $Id: addrdsfig.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addrdsfig.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-addrdsfig
-.XE
-.XS0 \n%
-.ti 0.2i
-addrdsfig
-.XE0 \}
-.TH ADDRDSFIG 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-addrdsfig \- adds a figure
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include"rdsnnn.h"
-rdsfig_list \(**addrdsfig( Name, Size )
-  char        \(**Name;
-  unsigned int Size;
-.SH PARAMETER
-.TP 20
-\fIName\fP
-Name of the figure to add to the figures's list.
-.TP
-\fISize\fP
-Size of the user structure (if defined) added to the rdsrec_list structure.
-.SH DESCRIPTION
-The addrdsfig function adds a new figure called 'Name' to the head of figures's list and becomes itself the list head (HEAD_RDSFIG pointer). 
-.br
-The field \fINAME\fP of the figure is set to \'Name\'.
-.br
-The field \fISIZE\fP of the figure is set to \'Size\'.
-.br
-The field MODE of the figure is set to \'A\'.
-.PP
-\fINote\fI :
-.PP
-Name allocation is done with the namealloc() MBK function.
-.PP
-If user structure isn't defined, the user has to set parameter 'Size' to 0L. 
-.SH RETURN VALUE
-Pointer to the newly created figure.It's also the HEAD_RDSFIG pointer.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Rds202: rdsalloc error, can't continue !"
-.ft R
-.RS
-it's impossible to allocate the memory size desired
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mutnnn.h"
-	#include "rdsnnn.h"
-        #include "rtlnnn.h"
-	 typedef struct UserStruct
-	  {
-	    char \(**STRING;
-	    void \(**USER1;
-	  } UserStruct;
-	 main()
-	  {
-	    rdsfig_list \(**RdsFigure;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-	    RdsFigure = \fBaddrdsfig\fP ("core",sizeof ( UserStruct ) );
-	    printf("FIGURE NAME = %s\\n",RdsFigure->NAME);
-	    /\(** The new figure is head of figure list \(**/
-	    printf("HEAD_RDSFIG : FIGURE NAME = %s\\n",HEAD_RDSFIG->NAME);
-	  }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librds,
-.BR delrdsfig,
-.BR viewrdsfig
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addrdsfigrec.3 b/alliance/share/man/man3/addrdsfigrec.3
deleted file mode 100644
index 8c514360..00000000
--- a/alliance/share/man/man3/addrdsfigrec.3
+++ /dev/null
@@ -1,141 +0,0 @@
-.\"   $Id: addrdsfigrec.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addrdsfigrec.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-addrdsfigrec
-.XE
-.XS0 \n%
-.ti 0.2i
-addrdsfigrec
-.XE0 \}
-.TH ADDRDSFIGREC 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
- addrdsfigrec \- adds a rectangle to a figure
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rdsnnn.h"
-rdsrec_list \(**addrdsfigrec( Figure, Name, Layer, X, Y, Dx, Dy )
-               rdsfig_list \(**Figure;
-               char        \(**Name;
-               char         Layer;
-               long         X;
-               long         Y;
-               long         Dx;
-               long         Dy;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIFigure\fP
-figure which contains the rectangle to add.
-.TP
-\fIName\fP
-name of the rectangle to add.
-.TP
-\fILayer\fP
-Layer of the rectangle to add.
-.TP
-\fIX,Y,DX,DY\fP
-Dimensions of the rectangle to add.
-.SH DESCRIPTION 
-\fBaddrdsfigrec\fP creates an adds a rectangle in the figure called \fIFigure\fP.
-The size of the user structure to add next to the structure rdsrec_list (if it
-exists) is defined by the field \fBSIZE\fP of the figure who has to contain 
-the rectangle. The rectangle is added in front of the list, and becomes itself
-the list head associated to the defined layer in parameters of the function.
-The fields of the rectangle structure are modified as follows :
-.br
-The field \fINAME\fP is set to \fBName\fP.
-.br
-The field \fIX\fP is set to \fBX\fP.
-.br
-The field \fIY\fP is set to \fBY\fP.
-.br
-The field \fIDX\fP is set to \fBDx\fP.
-.br
-The field \fIDY\fP is set to \fBDy\fP.
-.br
-The field \fIFLAGS\fP is modified with the value \fBLayer\fP.
-.SH RETURN VALUE
-\fBaddrdsfigrec\fP returns a pointer to the newly added rectangle.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Rds202: rdsalloc error, can't continue !"
-.ft R
-.RS
-it's impossible to allocate the memory size desired
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mutnnn.h"
-#include "rdsnnn.h"
-#include "rtlnnn.h"
-        typedef struct UserStruct
-         {
-           char \(**STRING;
-           void \(**USER1;
-         } UserStruct;
-        # define POINTER_STRING(R)                                \\
-                                                                  \\
-          (((UserStruct \(**)((char \(**)(R)+sizeof(rdsrec_list)))->STRING )
-         main()
-          {
-            rdsfig_list \(**RdsFigure;
-            rdsrec_list \(**Rectangle;
-            char Layer;
-            rdsrec_list \(**ScanRec;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            RdsFigure = addrdsfig ("core",sizeof ( UserStruct ) );
-            Rectangle = \fBaddrdsfigrec\fP (RdsFigure,
-                                            "Alu1",RDS_ALU1,
-                                            2,4,12,1);
-            POINTER_STRING(Rectangle) = namealloc ("rectangle_alu1");
-            ...
-            /\(**
-               print caracteristics of all rectangles of the Rds figure
-            \(**/
-            for ( Layer = 0 ; Layer < RDS_MAX_LAYER ; Layer ++ )
-             {
-               for (
-                      ScanRec  = RdsFigure->LAYERTAB[Layer] ;
-                      ScanRec != (rdsrec_list \(**) NULL     ;
-                      ScanRec  = ScanRec->NEXT
-                   )
-                {
-                  printf("Rectangle->LAYER = %s\\n",
-                     RDS_LAYER_NAME[GetRdsLayer(ScanRec)]);
-                  printf("Rectangle->NAME   = %s\\n",ScanRec->NAME);
-                  printf("Rectangle->X      = %ld\\n",ScanRec->X);
-                  printf("Rectangle->Y      = %ld\\n",ScanRec->Y);
-                  printf("Rectangle->DX     = %ld\\n",ScanRec->DX);
-                  printf("Rectangle->DY     = %ld\\n",ScanRec->DY);
-                  printf("Rectangle->STRING = %s\\n",POINTER_STRING(ScanRec));
-                }
-             }
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librds,
-.BR delrdsfigrec,
-.BR viewrdsfig
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addrdsins.3 b/alliance/share/man/man3/addrdsins.3
deleted file mode 100644
index faabc127..00000000
--- a/alliance/share/man/man3/addrdsins.3
+++ /dev/null
@@ -1,142 +0,0 @@
-.\"   $Id: addrdsins.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addrdsins.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-addrdsins
-.XE
-.XS0 \n%
-.ti 0.2i
-addrdsins
-.XE0 \}
-.TH ADDRDSINS 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
- addrdsins \- adds an instance to a figure
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rdsnnn.h"
-rdsins_list \(**addrdsins( Figure, Model, Name, Sym, X, Y )
-     rdsfig_list \(**Figure;
-     char        \(**Model;
-     char        \(**Name;
-     char         Sym;
-     long         X;
-     long         Y;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIFigure\fP
-figure which contains the instance.
-.TP
-\fIModel\fP
-Name of the model of the instance. 
-.TP
-\fIName\fP
-Name of the instance in the figure at which it belongs.
-.TP
-\fISym\fP
-Symmetry applied to the instance. 
-.RS
-.TP 20
-possible values :
-.TP
-\fBRDS_NOSYM\fP
-no symmetry.
-.TP
-\fBRDS_ROT_P\fP
-90 degrees rotation counter clockwise.
-.TP
-\fBRDS_SYMXY\fP
-symmetry with regard to a horizontal and vertical axis.
-.TP
-\fBRDS_ROT_M\fP
-90 degrees rotation clockwise.
-.TP
-\fBRDS_SYM_X\fP
-symmetry with regard to a vertical axis.
-.TP
-\fBRDS_SY_RM\fP
-symmetry with regard to a vertical axis and 90 degrees clockwise.
-.TP
-\fBRDS_SYM_Y\fP
-symmetry with regard to a horizontal axis.
-.TP
-\fBRDS_SY_RP\fP
-symmetry with regard to a horizontal axis and 90 degrees rotation counter clockwise.
-.RE
-.TP
-\fIX,Y\fP
-position of the lower left corner of the instance in the figure after symmetry.
-.SH DESCRIPTION
-The \fIaddrdsins\fP function adds an instance to the head of instances's list in the figure
-described in function parameter. Some fields of rdsins_list structure
-are modified as follows :
-.br               
-The field \fIFIGNAME\fP is set to \fBModel\fP
-.br
-The field \fIINSNAME\fP is set to \fBName\fP
-.br
-The field \fIX\fP is set to \fBX\fP
-.br
-The field \fIY\fP is set to \fBY\fP 
-.br
-The field \fITRANSF\fP is set to \fBSym\fP
-.br
-The field \fISIZE\fP is set to \fBFigure->SIZE\fP
-.SH RETURN VALUE
-\fBaddrdsins\fP returns a pointer to the newly created instance which is head of instances's list of the figure.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Rds202: rdsalloc error, can't continue !"
-.ft R
-.RS
-it's impossible to allocate the memory size desired.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mutnnn.h"
-#include "rdsnnn.h"
-#include "rtlnnn.h"
-        typedef struct UserStruct
-         {
-           char \(**STRING;
-           void \(**USER1;
-         } UserStruct;
-         main()
-          {
-            rdsfig_list \(**RdsFigure;
-            rdsins_list \(**Instance;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            RdsFigure = addrdsfig ("core",sizeof ( UserStruct ) );
-            Instance = \fBaddrdsins\fP (RdsFigure,"na2_y","and2",RDS_NOSYM,8,6); 
-            printf("(RdsFigure->INSTANCE)->NAME = %s\\n",
-                    (RdsFigure->INSTANCE)->NAME);
-            /\(** Instance is head of instance list of the figure \(**/
-            printf("Instance->NAME = %s\\n", Instance->NAME);
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librds,
-.BR delrdsins,
-.BR viewrdsins
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addrdsinsrec.3 b/alliance/share/man/man3/addrdsinsrec.3
deleted file mode 100644
index 6e35083c..00000000
--- a/alliance/share/man/man3/addrdsinsrec.3
+++ /dev/null
@@ -1,141 +0,0 @@
-.\"   $Id: addrdsinsrec.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addrdsinsrec.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-addrdsinsrec
-.XE
-.XS0 \n%
-.ti 0.2i
-addrdsinsrec
-.XE0 \}
-.TH ADDRDSINSREC 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
- addrdsinsrec \- adds a rectangle to an instance
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include"rdsnnn.h"
- rdsrec_list \(**addrdsinsrec( Instance, Name, Layer, X, Y, Dx, Dy )
-   rdsins_list \(**Instance;
-   char        \(**Name;
-   char         Layer;
-   long         X;
-   long         Y;
-   long         Dx;
-   long         Dy;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIInstance\fP
-The instance which contains the rectangle to add.
-.TP
-\fIName\fP
-Name of the rectangle to add.
-.TP
-\fILayer\fP
-Layer of the rectangle to add.
-.TP
-\fIX,Y,DX,DY\fP
-Dimensions of the the rectangle to add.
-.SH DESCRIPTION
-This function creates an adds a rectangle to an instance. The size of the user structure to add (if if exists) next to the structure rdsrec_list is defined by the field SIZE of the instance which has to contain the rectangle. The rectangle is chained to the head of the rectangles's list associated to the defined layer in parameters of the function addrdsinsrec(). The fields of the rectangle structure are modified as follows :
-.PP
-The field \fINAME\fP is set to \'Name\'.
-.br
-The field \fIX\fP is set to \'X\'.
-.br
-The field \fIY\fP is set to \'Y\'.
-.br
-The field \fIDX\fP is set to \'Dx\'.
-.br
-The field \fIDY\fP is set to \'Dy\'.
-.br
-The field \fIFLAGS\fP is modified with the value \'Layer\'.
-.PP
-\fINote\fP :
-.PP 
-\- This function uses MBK namealloc() function.
-.PP
-\- coordinates of the rectangle are related to the instance before geometrical transformation.
-.SH RETURN VALUE
-The pointer to the added rectangle. It is also the head of rectangles's list associated to the corresponding layer.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Rds202: rdsalloc error, can't continue !"
-.ft R
-.RS
-it's impossible to allocate the memory size desired
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rtlnnn.h"
-        typedef struct UserStruct
-         {
-           char \(**STRING;
-           void \(**USER1;
-         } UserStruct;
-        # define POINTER_STRING(R)                                \\
-                                                                  \\
-          (((UserStruct \(**)((char \(**)(R)+sizeof(rdsrec_list)))->STRING )
-         main()
-          {
-            rdsfig_list \(**RdsFigure;
-            rdsins_list \(**Instance;
-            rdsrec_list \(**Rectangle;
-            char Layer;
-            rdsrec_list \(**ScanRec;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            RdsFigure = addrdsfig ("core",sizeof ( UserStruct ) );
-            Instance  = addrdsins (RdsFigure,"na2_y","and2",RDS_NOSYM,8,6);
-            Rectangle = \fBaddrdsinsrec\fP (Instance,"Alu1",RDS_ALU1,2,4,12,1);
-            POINTER_STRING( Rectangle ) = namealloc ("un_alu1");
-            /\(**
-               Displays caracteristics of all the rectangles of the instance
-            \(**/
-           for ( Layer = 0 ; Layer < RDS_MAX_LAYER ; Layer ++ )
-            {
-              for (
-                     ScanRec  = Instance->LAYERTAB[Layer] ;
-                     ScanRec != (rdsrec_list \(**) NULL      ;
-                     ScanRec  = ScanRec->NEXT
-                  )
-               {
-                 printf("Rectangle->LAYER = %s\\n",
-                    RDS_LAYER_NAME[GetRdsLayer(ScanRec)]);
-                 printf("Rectangle->NAME   = %s\\n",ScanRec->NAME);
-                 printf("Rectangle->X      = %ld\\n",ScanRec->X);
-                 printf("Rectangle->Y      = %ld\\n",ScanRec->Y);
-                 printf("Rectangle->DX     = %ld\\n",ScanRec->DX);
-                 printf("Rectangle->DY     = %ld\\n",ScanRec->DY);
-                 printf("Rectangle->STRING = %s\\n",POINTER_STRING(ScanRec));
-               }
-            }
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librds,
-.BR delrdsinsrec,
-.BR viewrdsins
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/addrdsrecwindow.3 b/alliance/share/man/man3/addrdsrecwindow.3
deleted file mode 100644
index 0f991a20..00000000
--- a/alliance/share/man/man3/addrdsrecwindow.3
+++ /dev/null
@@ -1,129 +0,0 @@
-.\"   $Id: addrdsrecwindow.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)addrdsrecwindow.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-addrdsrecwindow
-.XE
-.XS0 \n%
-.ti 0.2i
-addrdsrecwindow
-.XE0 \}
-.TH ADDRDSRECWINDOW 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-addrdsrecwindow \- adds a rectangle in the windowing of rds structure.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rwinnn.h"
- void addrdsrecwindow( Rectangle, RdsWindow )
-    rdsrec_list \(**Rectangle;
-    rdswindow   \(**RdsWindow;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIRectangle\fP
-The rectangle to add to the windowing.
-.TP
-\fIRdsWindow\fP
-The head of the windowing which has to contain the rectangle.
-.SH DESCRIPTION
-The \fIaddrdsrecwindow\fP function inserts a rdsrec_list rectangle structure in the windowing of the rds structure. The rectangle is added in one or many windows of the table (it depends on his dimensions). The field \'USER\' of the rectangle is used to point to the list of windows which contains the rectangle. So, the field \'USER\' has to be saved in an added structure to the rdsrec_list structure if librfm functions are used because somes use the field \'USER\' to link rectangles (see librds about field \'USER\').
-.TP
-\fINote\fP
-If the rectangle is contained in only one window, then the field \'USER\' points to a "rdswin_list" window structure.
-.br
-If the rectangle is contained in many windows, the field \'USER\' points to a "rdsrecwin_list" structure which is a list which contains windows.
-.PP
-To know if a rectangle belongs to one or many windows, use the macro \fIIsRdsOneWindow\fP defined in librwi.
-.SH RETURN VALUE
-none
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Rds202: rdsalloc error, can't continue !"
-.ft R
-.RS
-it's impossible to allocate the memory size desired
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rwinnn.h"
-        #include "rtlnnn.h"
-        # define POINTER_LINKREC(R)                               \\
-                                                                  \\
-          (((UserStruct \(**)((char \(**)(R)+sizeof(rdsrec_list)))->LINKREC )
-        typedef struct UserStruct
-          {
-            void \(**LINKREC; 
-          } UserStruct;
-        main()
-          {
-            rdsfig_list \(**Figure;
-            rdsrec_list \(**Rectangle;
-            rdswindow \(**RdsWindow;
-            rdswin_list \(**ScanWin;
-            rdsrecwin_list \(**ScanRecWin;
-             mbkenv();
-             rdsenv();
-             loadrdsparam(); 
-             Figure = addrdsfig( "core",sizeof ( UserStruct ) );
-             Rectangle =
-               addrdsfigrec(Figure,"Alu1",RDS_ALU1,2,4,5,1);
-             /\(** Using the field \'USER\' \(**/
-             Rectangle->USER = Rectangle;
-            . . . .
-            RdsWindow = allocrdswindow();
-            RdsWindow->XMIN = -200;
-            RdsWindow->YMIN = -200;
-            RdsWindow->XMAX =  200;
-            RdsWindow->YMAX =  200;
-            RdsWindow->DX   =  4;
-            RdsWindow->DY   =  4;
-            RdsWindow->SIDE =  100;
-            RdsWindow->SIZE =  RdsWindow->DX \(** RdsWindow->DY ;
-            RdsWindow->WINTAB = allocrdswin( RdsWindow->SIZE );
-            /\(** Save the field \'USER\' of the rectangle \(**/
-            POINTER_LINKREC(Rectangle) = Rectangle->USER; 
-            /\(** \(**/ \fBaddrdsrecwindow\fP( Rectangle, RdsWindow ); 
-            /\(** windows associated to a rectangle are pointed by the
-               field \'USER\' of the rectangle \(**/
-            /\(** getting windows (pointer \(**ScanWin) of a rectangle \(**/
-            if ( IsRdsOneWindow(Rectangle) )
-             {
-               ScanWin = (rdswin_list \(**) Rectangle->USER;
-             }
-            else
-             {
-               ScanRecWin = Rectangle->USER;
-               while ( ScanRecWin != NULL )
-                {
-                  ScanWin = (rdswin_list \(**) (ScanRecWin)->WINDOW;
-                  ScanRecWin = ScanRecWin->NEXT;
-                }
-             }
-            . . .
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librwi,
-.BR delrdsrecwindow
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/alliancebanner.3 b/alliance/share/man/man3/alliancebanner.3
deleted file mode 100644
index fbcd2b4e..00000000
--- a/alliance/share/man/man3/alliancebanner.3
+++ /dev/null
@@ -1,72 +0,0 @@
-.\"   $Id: alliancebanner.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)alliancebanner.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.ie t \{\
-.fp 4 C \}
-.el \{\
-.fp 4 B \}
-.TH ALLIANCEBANNER 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-alliancebanner \- display the standardized Alliance banner
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.ft 4
-#include "mut315.h"
-void alliancebanner(tool, tv, comment, date, av)
-char \(**tool, \(**tv, \(**comment, \(**date, \(**av;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\f4tool\fP
-Name of the tool.
-This is what will be displayed as banner.
-.TP 20
-\f4tv\fP
-Tool version.
-.TP 20
-\f4comment\fP
-Indicates the tool's usefulness.
-.TP 20
-\f4date\fP
-Copyright dates.
-.TP 20
-\f4av\fP
-Alliance version.
-.SH DESCRIPTION
-\fBalliancebanner\fP ouputs on \f4stdout\fR a standardized banner with
-the name of the tool in large letters, and a cartouche containing some
-informations about the Alliance CAD system.
-This function is to be used by all the Alliance tools, and expect a
-display 80 columns wide.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.ft 4
-#include "ba315n.h"
-#define nfloptitle(name) \\
-        alliancebanner("nFloP", VERSION,\\
-                       "not a FloorPlan router", "92, 93",\\
-                       ALLIANCE_VERSION)
-.ft R
-.fi
-.SH SEE ALSO
-.BR alliance (1).
-
-
-.SH DIAGNOSTICS
-\f4alliancebanner: Error: Resulting size bigger than 80 columns not allowed\fR
-.RS
-The \fItool\fR argument must be such that its resulting size isn't wider that
-80 culumns.
-This means, since the character set is proportional, that the longest name
-to be output is about 8 characters long.
-.RE
-\f4alliancebanner: Error: Character out of [0-9A-Za-z] range\fR
-.RS
-The \fItool\fR parameter has a non allowed character in it.
-For simplicity purposes, only numbers and letters are accepted.
-.RE
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/allocrdsfig.3 b/alliance/share/man/man3/allocrdsfig.3
deleted file mode 100644
index f6da2e7c..00000000
--- a/alliance/share/man/man3/allocrdsfig.3
+++ /dev/null
@@ -1,74 +0,0 @@
-.\"   $Id: allocrdsfig.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)allocrdsfig.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-allocrdsfig
-.XE
-.XS0 \n%
-.ti 0.2i
-allocrdsfig
-.XE0 \}
-.TH ALLOCRDSFIG 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
- allocrdsfig \- allocs memory for a figure
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rdsnnn.h"
-rdsfig_list \(**allocrdsfig()
-.ft R
-.fi
-.SH PARAMETER
-none
-.SH DESCRIPTION
-The \fIallocrdsfig\fP function allocates a memory block for rdsfig_list structure. Fields contained in the structure are set to NULL for pointers or 0L for numbers.
-.TP
-NOTE: Allocation by block ( see rdsalloc() function ).
-.SH RETURN VALUE
-\fBallocrdsfig\fP returns a pointer to the rdsfig_list structure allocated.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Rds202: rdsalloc error, can't continue !"
-.ft R
-.RS
-it's impossible to allocate the memory size desired.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-         #include "mutnnn.h"
-         #include "rdsnnn.h"
-         #include "rtlnnn.h"
-	    main()
-	     {
-	       rdsfig_list \(**RdsFigure;
-               mbkenv();
-               rdsenv();
-               loadrdsparam();
-	       RdsFigure = \fBallocrdsfig\fP ();
-	       RdsFigure->NAME = namealloc ("core");
-	       ...
-	     }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librds,
-.BR rdsalloc,
-.BR rdsfree,
-.BR freerdsfig
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/allocrdsins.3 b/alliance/share/man/man3/allocrdsins.3
deleted file mode 100644
index 7bc114fe..00000000
--- a/alliance/share/man/man3/allocrdsins.3
+++ /dev/null
@@ -1,75 +0,0 @@
-.\"   $Id: allocrdsins.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)allocrdsins.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-allocrdsins
-.XE
-.XS0 \n%
-.ti 0.2i
-allocrdsins
-.XE0 \}
-.TH ALLOCRDSINS 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
- allocrdsins \- allocates memory for an instance
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include"rdsnnn.h"
-rdsins_list \(**allocrdsins()
-.ft R
-.fi
-.SH PARAMETER
-none
-.SH DESCRIPTION
-Allocates a memory block for rdsins_list structure. Fields contained in the structure are set to NULL for the pointers and 0L for numbers.
-.PP
-NOTE: Allocation by block ( see rdsalloc() function ).
-.SH RETURN VALUE
-The pointer to the allocated instance.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Rds202: rdsalloc error, can't continue !"
-.ft R
-.RS
-it's impossible to allocate the memory size desired.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-            #include "mutnnn.h" 
-	    #include "rdsnnn.h"
-	    #include "rtlnnn.h"
-	    main()
-	     {
-	       rdsins_list \(**RdsInstance;
-               mbkenv();
-               rdsenv();
-               loadrdsparam();
-	       RdsInstance = \fBallocrdsins\fP ();
-	       RdsInstance->FIGNAME = namealloc ("na2_y");
-	       RdsInstance->INSNAME = namealloc ("and2");
-	       ...
-	     }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librds,
-.BR freerdsins,
-.BR rdsalloc,
-.BR rdsfree
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/allocrdsrec.3 b/alliance/share/man/man3/allocrdsrec.3
deleted file mode 100644
index d5b7b5a5..00000000
--- a/alliance/share/man/man3/allocrdsrec.3
+++ /dev/null
@@ -1,96 +0,0 @@
-.\"   $Id: allocrdsrec.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)allocrdsrec.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-allocrdsrec
-.XE
-.XS0 \n%
-.ti 0.2i
-allocrdsrec
-.XE0 \}
-.TH ALLOCRDSREC 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
- allocrdsrec \- allocates memory for a rectangle
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include"rdsnnn.h"
-rdsrec_list \(**allocrdsrec( Size )
-  unsigned int Size;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fISize\fP
-Size of the added structure to the rdsrec_list structure.
-.SH DESCRIPTION
-Allocates a memory block for rdsrec_list structure and an added structure defined by the user. Fields contained in the two structures are set to NULL for pointers and 0L for numbers.
-.PP
-NOTE: Allocation by heap ( see rdsalloc function ).
-.SH RETURN VALUE
-The pointer to the rectangle structure allocated.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Rds202: rdsalloc error, can't continue !"
-.ft R
-.RS
-it's impossible to allocate the memory size desired.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        # include "mutnnn.h"
-        # include "rdsnnn.h"
-        # include "rtlnnn.h"
-	 /\(** Name and fields of UserStruct are defined by the user \(**/
-	 typedef struct UserStruct
-	  {
-	    char \(**STRING;
-	    void \(**USER1;
-	  } UserStruct;
-	# define POINTER_STRING(R)                                \\
-                                                                  \\
-	  (((UserStruct \(**)((char \(**)(R)+sizeof(rdsrec_list)))->STRING )
-	# define POINTER_USER1(R)                                 \\
-                                                                  \\
-	  (((UserStruct \(**)((char \(**)(R)+sizeof(rdsrec_list)))->USER1  )
-	    main()
-	     {
-	       rdsfig_list \(**Figure;
-	       rdsrec_list \(**Rectangle;
-               mbkenv();
-               rdsenv();
-               loadrdsparam();
-	       Rectangle = \fBallocrdsrec\fP ( sizeof ( UserStruct ) );
-	       Rectangle->X               = 20;
-	       Rectangle->Y               = 20;
-	       Rectangle->DX              = 48;
-	       Rectangle->DY              = 8;
-	       POINTER_STRING (Rectangle) = (char \(**) malloc (strlen ("Alu1")+1);
-	       strcpy(POINTER_STRING(Rectangle),"Alu1");
-	       POINTER_USER1  (Rectangle) = (void \(**) Figure;
-	       ...
-	     }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librds,
-.BR freerdsrec,
-.BR rdsalloc,
-.BR rdsfree
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/allocrdsrecwin.3 b/alliance/share/man/man3/allocrdsrecwin.3
deleted file mode 100644
index 7dda1797..00000000
--- a/alliance/share/man/man3/allocrdsrecwin.3
+++ /dev/null
@@ -1,84 +0,0 @@
-.\"   $Id: allocrdsrecwin.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)allocrdsrecwin.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-allocrdsrecwin
-.XE
-.XS0 \n%
-.ti 0.2i
-allocrdsrecwin
-.XE0 \}
-.TH ALLOCRDSRECWIN 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-allocrdsrecwin \- allocates a structure used to know windows which contains a rectangle. 
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rwinnn.h"
- rdsrecwin_list \(**allocrdsrecwin()
-.ft R
-.fi
-.SH PARAMETER
-none
-.SH DESCRIPTION
-The \fIallocrdsrecwin\fP function allocates a rdsrecwin_list structure item. This structure contains a pointer to a window structure so it permits to chain all windows which contains a same rectangle (see librwi).
-.SH RETURN VALUE
-The pointer to the newly allocated structure is returned.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Rds202: rdsalloc error, can't continue !"
-.ft R
-.RS
-it's impossible to allocate the memory size desired
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rwinnn.h"
-        #include "rtlnnn.h"
-        # define POINTER_WINDOW(R)                                \\
-                                                                  \\
-          (((UserStruct \(**)((char \(**)(R)+sizeof(rdsrec_list)))->WINDOW )
-        typedef struct UserStruct
-         {
-           rdsrecwin_list \(**WINDOW;
-         } UserStruct;
-        main()
-          {
-             rdsfig_list \(**Figure;
-             rdsrec_list \(**Rectangle;
-             rdswin_list \(**Window;
-             mbkenv();
-             rdsenv();
-             loadrdsparam();
-             Figure = addrdsfig( "core",sizeof ( UserStruct ) );
-             Rectangle =
-               addrdsfigrec(Figure,"Alu1",RDS_ALU1,2,4,5,1);
-             POINTER_WINDOW (Rectangle) = \fBallocrdsrecwin\fP();
-             . . . .
-             Window = ...
-             (POINTER_WINDOW (Rectangle))->WINDOW = Window;
-             . . . .
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librwi
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/allocrdswin.3 b/alliance/share/man/man3/allocrdswin.3
deleted file mode 100644
index cb1055bd..00000000
--- a/alliance/share/man/man3/allocrdswin.3
+++ /dev/null
@@ -1,78 +0,0 @@
-.\"   $Id: allocrdswin.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)allocrdswin.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-allocrdswin
-.XE
-.XS0 \n%
-.ti 0.2i
-allocrdswin
-.XE0 \}
-.TH ALLOCRDSWIN 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-allocrdswin \- allocates window's table
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rwinnn.h"
- rdswin_list \(**allocrdswin( Number )
-    unsigned int Number;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fINumber\fP
-Number of windows contained in the window's table.
-.SH DESCRIPTION
-The \fIallocrdswin\fP allocates a window's table. The number of windows is specified by the parameter \'Number\' of the function. To determine the size of the parameter \'Number\', the user has to multiplicate width by height of his table in number of windows. Each item of the table is a pointer to a rdswin_list structure which contains rectangles sorted by layer (see librwi).
-.SH RETURN VALUE
-The pointer to the table is returned.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Rds202: rdsalloc error, can't continue !"
-.ft R
-.RS
-it's impossible to allocate the memory size for the table
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rwinnn.h"
-        #include "rtlnnn.h"
-        main()
-          {
-            rdswindow \(**RdsWindow;
-            RdsWindow = allocrdswindow();
-            RdsWindow->XMIN = -200;
-            RdsWindow->YMIN = -200;
-            RdsWindow->XMAX =  200;
-            RdsWindow->YMAX =  200;
-            RdsWindow->DX   =  4;
-            RdsWindow->DY   =  4;
-            RdsWindow->SIDE =  100;
-            RdsWindow->SIZE =  RdsWindow->DX \(** RdsWindow->DY ;
-            RdsWindow->WINTAB = \fBallocrdswin\fP( RdsWindow->SIZE ); 
-            . . .
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librwi
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/allocrdswindow.3 b/alliance/share/man/man3/allocrdswindow.3
deleted file mode 100644
index 8cd6aec5..00000000
--- a/alliance/share/man/man3/allocrdswindow.3
+++ /dev/null
@@ -1,78 +0,0 @@
-.\"   $Id: allocrdswindow.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)allocrdswindow.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-allocrdswindow
-.XE
-.XS0 \n%
-.ti 0.2i
-allocrdswindow
-.XE0 \}
-.TH ALLOCRDSWINDOW 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-allocrdswindow \- allocates a window structure 
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rwinnn.h"
- rdswindow \(**allocrdswindow()
-.ft R
-.fi
-.SH PARAMETER
-none
-.SH DESCRIPTION
-The \fIallocrdswindow\fP allocates a window structure (rdswindow) which is used to create an \'object\' window (see librwi). It contains fields information about the window's table and the pointer to the window's table. It's the head of windowing.
-.SH RETURN VALUE
-The pointer to the rdswindow structure allocated is returned.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Rds202: rdsalloc error, can't continue !"
-.ft R
-.RS
-it's impossible to allocate the memory size desired.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rwinnn.h"
-        #include "rtlnnn.h"
-        main()
-          {
-            rdswindow \(**RdsWindow;
-            RdsWindow = \fBallocrdswindow\fP();
-            RdsWindow->XMIN = -200;
-            RdsWindow->YMIN = -200;
-            RdsWindow->XMAX =  200;
-            RdsWindow->YMAX =  200;
-            RdsWindow->DX   =  4;
-            RdsWindow->DY   =  4;
-            RdsWindow->SIDE =  100;
-            RdsWindow->SIZE =  RdsWindow->DX \(** RdsWindow->DY ;
-            RdsWindow->WINTAB = allocrdswin( RdsWindow->SIZE );
-            . . .
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librwi,
-.BR buildrdswindow,
-.BR destroyrdswindow,
-.BR viewrdswindow
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/allocrdswinrec.3 b/alliance/share/man/man3/allocrdswinrec.3
deleted file mode 100644
index 03c5f917..00000000
--- a/alliance/share/man/man3/allocrdswinrec.3
+++ /dev/null
@@ -1,83 +0,0 @@
-.\"   $Id: allocrdswinrec.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)allocrdswinrec.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-allocrdswinrec
-.XE
-.XS0 \n%
-.ti 0.2i
-allocrdswinrec
-.XE0 \}
-.TH ALLOCRDSWINREC 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-allocrdswinrec \- allocates a structure used to create a list of tables of rectangles.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rwinnn.h"
- rdswinrec_list \(**allocrdswinrec()
-.ft R
-.fi
-.SH PARAMETER
-none
-.SH DESCRIPTION
-The \fIallocrdswinrec\fP function allocates a data structure named "rdswinrec_list" used to contain rectangles. This structure contains a list of tables of rdsrec_list structures (see librwi and librds).
-.SH RETURN VALUE
-The pointer to the newly allocated structure is returned.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Rds202: rdsalloc error, can't continue !"
-.ft R
-.RS
-it's impossible to allocate the memory size desired
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rwinnn.h"
-        #include "rtlnnn.h"
-        main()
-          {
-            rdsrec_list    \(**Rectangle;
-            rdswinrec_list \(**WinRec, \(**HeadWinRec;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            WinRec = HeadWinRec = \fBallocrdswinrec\fP();
-            /\(** Fill the table with rectangles \(**/
-            for ( Counter = 0 ; Counter < RWI_MAX_REC ; Counter ++ )
-             {
-               if ( Rectangle == (rdsrec_list \(**) NULL ) break;
-               WinRec->RECTAB[Counter] = Rectangle;
-               Rectangle = Rectangle->NEXT;
-             }
-            if ( Counter == RWI_MAX_REC ) 
-             {
-               /\(** the table is full : allocation of a new table \(**/
-               WinRec->NEXT = allocrdswinrec();
-               WinRec = WinRec->NEXT;
-             }
-            . . . . 
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librwi
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/anyExpr.3 b/alliance/share/man/man3/anyExpr.3
deleted file mode 100644
index f05c3eaa..00000000
--- a/alliance/share/man/man3/anyExpr.3
+++ /dev/null
@@ -1,43 +0,0 @@
-.\"   $Id: anyExpr.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)anyExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH ANYEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBanyExpr\fP \- returns the value of a logical OR applied on the results of the application of a function on the arguments of an operator expression 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-int anyExpr(func,expr)
-int (*func)();
-chain_list *expr;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIfunc\fP
-function to apply
-.TP 20
-\fIexpr\fP
-expression
-.SH DESCRIPTION
-\fBanyExpr()\fP applies a boolean function \fIfunc()\fP to all the arguments of \fIexpr\fP and computes OR-logic. The function \fIfunc()\fP must be an \fIinteger\fP function that is false if 0 is returned and true otherwise and must have an expression as argument. 
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr;
-expr = createExpr(XOR);
-addQExpr(expr,createAtom("a"));
-addQExpr(expr,createAtom("b"));
-if (!anyExpr(profExpr,expr))
-   printf("expr is only made up of atomic expressions");
-freeExpr(expr);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR everyExpr (3),
-.BR mapExpr (3),
-.BR mapCarExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/append.3 b/alliance/share/man/man3/append.3
deleted file mode 100644
index 9e63dde0..00000000
--- a/alliance/share/man/man3/append.3
+++ /dev/null
@@ -1,67 +0,0 @@
-.\"   $Id: append.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)append.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-append
-.XE
-.XS4 \n%
-.ti 0.2i
-append
-.XE4 \}
-.TH APPEND 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-append \- append a \fBchain_list\fP to an other \fBchain_list\fP
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-chain_list \(**append(pt1, pt2)
-chain_list \(**pt1,\(**pt2;	
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIpt1\fP
-Pointer to a \fBchain_list\fP
-.TP
-\fIpt2\fP
-Pointer to a \fBchain_list\fP
-.SH DESCRIPTION
-\fBappend\fP appends the contains of the \fBchain_list\fP pointed to by
-\fIpt2\fP at the end of the one pointed to by \fIpt1\fP.
-.br
-The lists consistency is warranted by the use of the adequat \fBadd\fI
-functions.
-.SH RETURN VALUE
-\fBappend\fP returns a pointer to the new head of list.
-If \fIpt1\fP is not \fBNULL\fP, it has the value of \fIpt1\fP, else it is
-\fIpt2\fP.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-#include "mlo315.h"
-void sig_names(s0, s1)
-losig_list \(**s0, \(**s1;
-{
-	s0\->NAMECHAIN = append(s0\->NAMECHAIN, s1\->NAMECHAIN);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR chain (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/applyBdd.3 b/alliance/share/man/man3/applyBdd.3
deleted file mode 100644
index ff7c3da1..00000000
--- a/alliance/share/man/man3/applyBdd.3
+++ /dev/null
@@ -1,77 +0,0 @@
-.\"   $Id: applyBdd.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)applyBdd.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH APPLYBDD 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBapplyBdd\fP \- applies an operator to a list of BDD. 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-pNode applyBdd(oper,pt)
-short oper;
-chain_list *pt;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIoper\fP
-operator number to apply (OR,AND,XOR,NAND,NOR,NXOR,NOT)
-.TP 20
-\fIpt\fP
-\fIchain_list\fP of BDD.
-.SH DESCRIPTION
-\fBapplyBdd()\fP applies \fIoper\fP to a list of Bdd. This list can be created by \fBaddListBdd()\fP function. This function provides the basic method for creating the representation of a function according to the operators in a boolean expression.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-pNode nodeA,nodeB,nodeC;
-pNode res;
-chain_list *pt;
-
-initializeBdd(SMALL_BDD);
-nodeA = createNodeTermBdd(3);
-nodeB = createNodeTermBdd(3);
-nodeC = createNodeTermBdd(4);
-pt = NULL;
-pt = addListBdd(pt,nodeA);
-pt = addListBdd(pt,nodeB);
-pt = addListBdd(pt,nodeC);
-res = applyBdd(OR,pt);
-displayBdd(res,1);
-
-/* it will display 
-@res    INDEX = 4   LOW = @inter   HIGH = ONE
-@inter  INDEX = 3   LOW = @nodeA   HIGH = ONE
-@nodeA  INDEX = 2   LOW = ZERO	   HIGH = ONE
-*/
-	
-destroyBdd(1);
-.fi
-.SH ERRORS
-"applyBdd : error - unknown operator"
-.br
-the operator number must be in (OR,AND,XOR,NAND,NOR,NXOR,NOT)
-.br
-"applyBdd : error - chained list is empty"
-.br
-chained list pointer \fIpt = NULL\fP.
-.br
-"applyBdd : error - bad operator"
-.br
-The  number of arguments is 1 and the operator is distinct from NOT.
-.br
-chained list pointer \fIpt = NULL\fP.
-.br
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR addListBdd (3),
-.BR applyBinBdd (3),
-.BR notBdd (3),
-.BR constraintBdd (3),
-.BR composeBdd (3),
-.BR displayBdd (3),
-.BR createNodeTermBdd (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/applyBinBdd.3 b/alliance/share/man/man3/applyBinBdd.3
deleted file mode 100644
index 0e554786..00000000
--- a/alliance/share/man/man3/applyBinBdd.3
+++ /dev/null
@@ -1,59 +0,0 @@
-.\"   $Id: applyBinBdd.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)applyBinBdd.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH APPLYBINBDD 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBapplyBinBdd\fP \- applies an operator to two BDD. 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-pNode applyBinBdd(oper,pBdd1,pBdd2)
-short oper;
-pNode pBdd1;
-pNode pBdd2;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIoper\fP
-operator number to apply (OR,AND,XOR,NAND,NOR,NXOR)
-.TP 20
-\fIpBdd1\fP
-first argument
-.TP 20
-\fIpBdd2\fP
-second argument
-.SH DESCRIPTION
-\fBapplyBinBdd()\fP applies \fIoper\fP to \fIpBdd1\fP and \fIpBdd2\fP. This function provides the basic method for creating the representation of a boolean function.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-pNode nodeA,nodeB;
-pNode res;
-
-initializeBdd(SMALL_BDD);
-nodeA = createNodeTermBdd(3);
-nodeB = createNodeTermBdd(3);
-res = applyBinBdd(OR,nodeA,nodeB);
-displayBdd(res,1);
-
-/* it will display 
-@res    INDEX = 3   LOW = @nodeA   HIGH = ONE
-@nodeA  INDEX = 2   LOW = ZERO     HIGH = ONE
-*/
-	
-destroyBdd(1);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR applyBdd (3),
-.BR notBdd (3),
-.BR constraintBdd (3),
-.BR composeBdd (3),
-.BR addListBdd (3),
-.BR displayBdd (3),
-.BR createNodeTermBdd (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/applybddnode.3 b/alliance/share/man/man3/applybddnode.3
deleted file mode 100644
index 105a085b..00000000
--- a/alliance/share/man/man3/applybddnode.3
+++ /dev/null
@@ -1,85 +0,0 @@
-.\"   $Id: applybddnode.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)applybddnode.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH APPLYBDDNODE 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-applybddnode \- applies an operator on two \fBbdd\fP nodes.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddnode \(**applybddnode( BddSystem, Oper, BddNode1, BddNode2 )
-  bddsystem \(**BddSystem;
-  long       Oper;
-  bddnode   \(**BddNode1;
-  bddnode   \(**BddNode2;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIOper\fP
-The binary operator.
-.TP
-\fIBddNode1\fP
-The first \fBbdd\fP node.
-.TP
-\fIBddNode2\fP
-The second \fBbdd\fP node.
-.SH DESCRIPTION
-\fBapplybddnode\fP computes the boolean function \fIBddNode1\fP
-\fIOper\fP \fIBddNode2\fP in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBapplybddnode\fP returns a pointer to the resulting \fBbdd\fP node
-with its number of external reference incremented.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"bad operator xxx error !"
-.ft R
-.RS
-The \fIOper\fP parameter must be a valid binary operator.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   chain_list \(**Expr;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   addbddcircuitin( (bddcircuit \(**)0, "i0", 0, BDD_IN_MODE_FIRST );
-   addbddcircuitin( (bddcircuit \(**)0, "i1", 0, BDD_IN_MODE_FIRST );
-   BddNode = applybddnode( (bddsystem \(**)0,
-                           ABL_AND,
-                           searchbddcircuitin( (bddcircuit \(**)0, "i0" ),
-                           searchbddcircuitin( (bddcircuit \(**)0, "i1" ) );
-   Expr = convertbddcircuitabl( (bddcircuit \(**)0, BddNode );
-   /* displays (i0 and i1) */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/applybddnodeite.3 b/alliance/share/man/man3/applybddnodeite.3
deleted file mode 100644
index 42b8857e..00000000
--- a/alliance/share/man/man3/applybddnodeite.3
+++ /dev/null
@@ -1,78 +0,0 @@
-.\"   $Id: applybddnodeite.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)applybddnodeite.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH APPLYBDDNODEITE 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-applybddnodeite \- computes the IF-THEN-ELSE logical operation.
-
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddnode \(**applybddnodeite( BddSystem, BddIf, BddThen, BddElse )
-  bddnode   \(**BddSystem;
-  bddnode   \(**BddIf;
-  bddnode   \(**BddThen;
-  bddnode   \(**BddElse;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIBddIf\fP
-The IF \fBbdd\fP node.
-.TP
-\fIBddThen\fP
-The THEN \fBbdd\fP node.
-.TP
-\fIBddElse\fP
-The ELSE \fBbdd\fP node.
-.SH DESCRIPTION
-\fBapplybddnodeite\fP computes the following logical function
-(\fIBddIf\fP AND \fIBddThen\fP) OR ((NOT \fIBddIf\fP) AND \fIBddElse\fP)
-in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBapplybddnodeite\fP returns a pointer to the resulting \fBbdd\fP node
-with its number of external reference incremented.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   chain_list \(**Expr;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   addbddcircuitin( (bddcircuit \(**)0, "i0", 0, BDD_IN_MODE_FIRST );
-   addbddcircuitin( (bddcircuit \(**)0, "i1", 0, BDD_IN_MODE_FIRST );
-   addbddcircuitin( (bddcircuit \(**)0, "i2", 0, BDD_IN_MODE_FIRST );
-   BddNode = applybddnodeite( (bddsystem \(**)0,
-                              searchbddcircuitin( (bddcircuit \(**)0, "i0" ),
-                              searchbddcircuitin( (bddcircuit \(**)0, "i1" ),
-                              searchbddcircuitin( (bddcircuit \(**)0, "i2" ) );
-   Expr = convertbddcircuitabl( (bddcircuit \(**)0, BddNode );
-   /* displays ((i0 and i1) or ((not i0) and i2) */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/applybddnodelist.3 b/alliance/share/man/man3/applybddnodelist.3
deleted file mode 100644
index fc992bbb..00000000
--- a/alliance/share/man/man3/applybddnodelist.3
+++ /dev/null
@@ -1,96 +0,0 @@
-.\"   $Id: applybddnodelist.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)applybddnodelist.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH APPLYBDDNODELIST 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-applybddnodelist \- applies an opertor to a \fBbdd\fP nodes list.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddnode \(**applybddnodelist( BddSystem, Oper, BddList )
-  bddsystem  \(**BddSystem;
-  long        Oper;
-  chain_list \(**BddList;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIOper\fP
-The operator.
-.TP
-\fIBddList\fP
-The \fBbdd\fP nodes list.
-.SH DESCRIPTION
-\fBapplybddnodelist\fP applies the boolean operator \fIOper\fP to the
-\fBbdd\fP nodes list \fIBddList\fP in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBapplybddnodelist\fP returns a pointer to the resulting \fBbdd\fP node
-with its number of external reference incremented.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"bad operator xxx error !"
-.ft R
-.RS
-The \fIOper\fP parameter must be a valid binary operator.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"bad list !"
-.ft R
-.RS
-The \fIBddList\fP parameter must be a valid list.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   chain_list \(**BddList;
-   chain_list \(**Expr;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   BddList    = (chain_list \(**)0;
-   BddList = addbddnodelist( (bddsystem \(**)0, BddList, 
-                             addbddcircuitin( (bddcircuit \(**)0,
-                                              "i0", 0, BDD_IN_MODE_FIRST ) );
-   BddList = addbddnodelist( (bddsystem \(**)0, BddList, 
-                              addbddcircuitin( (bddcircuit \(**)0,
-                                               "i1", 0, BDD_IN_MODE_FIRST );
-   BddList = addbddnodelist( (bddsystem \(**)0, BddList,
-                             addbddcircuitin( (bddcircuit \(**)0,
-                                              "i2", 0, BDD_IN_MODE_FIRST );
-   BddNode = applybddnodelist( (bddsystem \(**)0, ABL_AND, BddList );
-   Expr = convertbddcircuitabl( (bddcircuit \(**)0, BddNode );
-   /* displays (i0 and i1 and i2) */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/applybddnodenot.3 b/alliance/share/man/man3/applybddnodenot.3
deleted file mode 100644
index ec6cb7d1..00000000
--- a/alliance/share/man/man3/applybddnodenot.3
+++ /dev/null
@@ -1,68 +0,0 @@
-.\"   $Id: applybddnodenot.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)applybddnodenot.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH APPLYBDDNODENOT 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-applybddnodenot \- complements a \fBbdd\fP.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddnode \(**applybddnodenot( BddSystem, BddNode )
-  bddsystem \(**BddSystem;
-  bddnode   \(**BddNode;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIBddNode\fP
-The \fBbdd\fP node to complement.
-.SH DESCRIPTION
-\fBapplybddnodenot\fP complements \fIBddNode\fP in the \fBbdd\fP
-system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBapplybddnodenot\fP returns a pointer to the resulting \fBbdd\fP node
-with its number of external reference incremented.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   chain_list \(**Expr;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   addbddcircuitin( (bddcircuit \(**)0, "i0", 0, BDD_IN_MODE_FIRST );
-   addbddcircuitin( (bddcircuit \(**)0, "i1", 0, BDD_IN_MODE_FIRST );
-   BddNode = applybddnode( (bddsystem \(**)0,
-                           ABL_AND,
-                           searchbddcircuitin( (bddcircuit \(**)0, "i0" ),
-                           searchbddcircuitin( (bddcircuit \(**)0, "i1" ) );
-   BddNode = applybddnodenot( (bddsystem \(**)0, decbddrefext( BddNode ) );
-   Expr = convertbddcircuitabl( (bddcircuit \(**)0, BddNode );
-   /* displays (i0 nand i1) */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/applybddnodeterm.3 b/alliance/share/man/man3/applybddnodeterm.3
deleted file mode 100644
index d7515386..00000000
--- a/alliance/share/man/man3/applybddnodeterm.3
+++ /dev/null
@@ -1,85 +0,0 @@
-.\"   $Id: applybddnodeterm.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)applybddnodeterm.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH APPLYBDDNODETERM 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-applybddnodeterm \- applies an operator on two \fBbdd\fP nodes.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddnode \(**applybddnodeterm( BddSystem, Oper, Index, BddNode )
-  bddsystem \(**BddSystem;
-  long       Oper;
-  bddindex   Index;
-  bddnode   \(**BddNode;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIOper\fP
-The binary operator.
-.TP
-\fIIndex\fP
-The index of the terminal \fBbdd\fP node.
-.TP
-\fIBddNode\fP
-The \fBbdd\fP node.
-.SH DESCRIPTION
-\fBapplybddnodeterm\fP computes the boolean function \fIBddNode\fP
-\fIOper\fP and the terminal node corresponding to \fIIndex\fP
-in the \fBbdd\fP system \fIBddSystem\fP. The \fIIndex\fP parameter
-can take only the two following values BDD_INDEX_ONE and BDD_INDEX_ZERO.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBapplybddnodeterm\fP returns a pointer to the resulting \fBbdd\fP node
-with its number of external reference incremented.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"bad operator xxx error !"
-.ft R
-.RS
-The \fIOper\fP parameter must be a valid binary operator.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   chain_list \(**Expr;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   addbddcircuitin( (bddcircuit \(**)0, "i0", 0, BDD_IN_MODE_FIRST );
-   BddNode = applybddnodeterm( (bddsystem \(**)0,
-                               ABL_XOR, BDD_INDEX_ONE,
-                               searchbddcircuitin( (bddcircuit \(**)0, "i0" ) );
-   Expr = convertbddcircuitabl( (bddcircuit \(**)0, BddNode );
-   /* displays (not i0) */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/applyrdssym.3 b/alliance/share/man/man3/applyrdssym.3
deleted file mode 100644
index 0232e3ad..00000000
--- a/alliance/share/man/man3/applyrdssym.3
+++ /dev/null
@@ -1,116 +0,0 @@
-.\"   $Id: applyrdssym.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)applyrdssym.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-applyrdssym
-.XE
-.XS0 \n%
-.ti 0.2i
-applyrdssym
-.XE0 \}
-.TH APPLYRDSSYM 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-applyrdssym \- applies a transformation to a rectangle from a model
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rutnnn.h"
-void applyrdssym( X, Y, Dx, Dy, Xins, Yins, Sym )
-      long  \(**X;
-      long  \(**Y;
-      long  \(**Dx;
-      long  \(**Dy;
-      long  Xins;
-      long  Yins;
-      char  Sym;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIX,Y,Dx,Dy\fP : 
-Coordinates  of the rectangle (of a model) to modify.
-.TP
-\fIXins,Yins\fP :
-Position where the instance has to be set.
-.TP
-\fISym\fP :
-Symmetry applied to the instance.
-.SH DESCRIPTION
-The \fIapplyrdssym\fP function sets coordinates of a rectangle (which belongs to a model) relative to the figure which contains the instance of this model. When the field \'\fBMODE\fP\' of a figure is set to the value \'A\' then only the figure and its instances empty are loaded in memory. So, if the user wants to load a rectangle of an instance in memory, he has to get the model of the instance and use the applyrdssym function. For mode information about loading modes of a figure in memory, see librds.
-.SH RETURN VALUE
-The coordinates (\fBX,Y,DX,DY\fP) of the rectangle are modified.
-.SH ERRORS
-none
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mphnnn.h"
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rutnnn.h"
-        #include "rtlnnn.h"
-       typedef struct UserStruct
-         {
-           void \(**USER1;
-         } UserStruct;
-        main()
-         {
-           rdsfig_list \(**Figure;
-           rdsfig_list \(**Instance;
-           rdsfig_list \(**InstanceModel;
-           rdsrec_list \(**Rectangle;
-           rdsrec_list \(**InsRectangle;
-           char         Layer;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            RdsFigure = addrdsfig ("core",sizeof ( UserStruct ) );
-            Instance = addrdsins (RdsFigure,"na2_y","and2",RDS_SYM_X,8,6);
-            /\(** loads instance model \(**/
-            InstanceModel = getrdsfig(
-                                       Instance->FIGNAME,
-                                       'A',
-                                       sizeof ( UserStruct )
-                                     );
-            /\(** gets one rectangle of the model (layer ALU1) \(**/ 
-            if ( InstanceModel->LAYERTAB[RDS_ALU1] != (rdsrec_list\(**) NULL )
-              Rectangle = InstanceModel->LAYERTAB[RDS_ALU1];
-            else exit(1);
-            /\(** Displays rectangle coordinates relative to the model \(**/
-            viewrdsrec ( Rectangle ); 
-            /\(** adds the rectangle in the instance \(**/
-            Layer = GetRdsLayer ( Rectangle ); 
-            InsRectangle = 
-              addrdsinsrec ( Instance, Rectangle->NAME, Layer,
-                             Rectangle->X, Rectangle->Y,
-                             Rectangle->DX, Rectangle->DY );
-           /\(** apply symmetry \(**/
-           /\(**\(**/ \fBapplyrdssym\fP(
-                             &InsRectangle->X,&InsRectangle->Y,
-                             &InsRectangle->DX,&InsRectangle->DY, 
-                             Instance->X,Instance->Y,Instance->TRANSF
-                           );
-           /\(** Displays rectangle coordinates relative to the figure \(**/
-           viewrdsrec ( InsRectangle );
-         }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librut,
-.BR librds,
-.BR addrdsins,
-.BR addrdsinsrec
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/apr.3 b/alliance/share/man/man3/apr.3
deleted file mode 100644
index d0b9d317..00000000
--- a/alliance/share/man/man3/apr.3
+++ /dev/null
@@ -1,27 +0,0 @@
-.\"   $Id: apr.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)apr.l 0.0 93/07/30 UPMC; Author : Xavier Picat & El housseine REJOUAN
-.if t \{\
-.XS \n%
-.XE \}
-.TH APR 3 "October 1, 1997" "ASIM/LIP6" "ALLIANCE APR LIBRARIES"
-.SH NAME
-apr \- routing and placement functions
-.so man1/alc_origin.1
-.SH DESCRIPTION
-Here is the list of functions that contains the apr library
-.TP 25
-\fBSymbolicChannelRouter\fP
-routes a given channel on virtual grid
-.TP 25
-\fBOpenVerticalChannel\fP
-opens a vertical channel inside a phfig_list
-.TP 25
-\fBplace\fP
-places the cells of a lofig_list
-.SH SEE ALSO
-.BR SymbolicChannelRouter(3),
-.BR OpenVerticalChannel(3),
-.BR place(3)
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/arp.3 b/alliance/share/man/man3/arp.3
deleted file mode 100644
index 67df29f9..00000000
--- a/alliance/share/man/man3/arp.3
+++ /dev/null
@@ -1,24 +0,0 @@
-.\"   $Id: arp.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)arp.l 0.0 93/07/30 UPMC; Author : Xavier Picat & El housseine REJOUAN
-.if t \{\
-.XS \n%
-.XE \}
-.TH ARP 3 "October 1, 1997" "ASIM/LIP6" "ALLIANCE ARP LIBRARIES"
-.SH NAME
-arp \- routing and placement functions
-.so man1/alc_origin.1
-.SH DESCRIPTION
-Here is the list of functions that contains the arp library
-.TP 20
-\fBSymbolicChannelRouter\fP
-\- routes a given channel on symbolic grid
-.TP 20
-\fBOpenVerticalChannel\fP
-\- open a channel inside a phfig_list
-.TP 20
-\fBPlace\fP
-\- places the cells of a lofig_list
-.SH SEE ALSO
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/autallocblock.3 b/alliance/share/man/man3/autallocblock.3
deleted file mode 100644
index d826cdbd..00000000
--- a/alliance/share/man/man3/autallocblock.3
+++ /dev/null
@@ -1,63 +0,0 @@
-.\"   $Id: autallocblock.3,v 1.1 1999/05/31 17:30:17 alliance Exp $
-.\" @(#)autallocblock.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH AUTALLOCBLOCK 3 "October 1, 1997" "ASIM/LIP6" "AUT FUNCTIONS"
-.SH NAME
-autallocblock \- memory allocator
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-char *autallocblock( Size )
-   unsigned int Size;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fISize\fP
-Number of memory bytes to be contiguously allocated
-.TP
-.SH DESCRIPTION
-\fBautallocblock\fP returns a block of \fISize\fP bytes length.
-The memory block is set to zero.
-.br
-.SH RETURN VALUE
-\fBautallocblock\fP returns a pointer to a \fISize\fP bytes long block.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"autalloc: alloc error, can't continue !"
-.ft R
-.RS
-System break can't be moved anymore, no more memory can be retrieved from the system.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-char \(**dup_str(s)
-  char \(** s;
-{
-  char \(**t = (char \(**)autalocblock(strlen(s) + (unsigned int)1);
-  strcpy(t, s); return t;
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR aut (1),
-.BR autresizeblock(3),
-.BR autallocheap(3),
-.BR autfreeblock(3),
-.BR autfreeheap(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/autallocheap.3 b/alliance/share/man/man3/autallocheap.3
deleted file mode 100644
index fb47a09c..00000000
--- a/alliance/share/man/man3/autallocheap.3
+++ /dev/null
@@ -1,68 +0,0 @@
-.\"   $Id: autallocheap.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)autallocheap.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH AUTALLOCHEAP 3 "October 1, 1997" "ASIM/LIP6" "AUT FUNCTIONS"
-.SH NAME
-autallocheap \- heap memory allocator
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-char *autallocheap( Size )
-   unsigned int Size;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fISize\fP
-Number of memory bytes to be contiguously allocated
-.SH DESCRIPTION
-\fBautallocheap\fP returns a block of \fISize\fP bytes length,
-allocated on the heap. The memory block is set to zero.
-Its use is strongly encouraged when the \fISize\fP is very small.
-.br
-.SH RETURN VALUE
-\fBautallocheap\fP returns a pointer to a \fISize\fP bytes long block.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"autalloc: alloc error, can't continue !"
-.ft R
-.RS
-System break can't be moved anymore, no more memory can be retrieved from the system.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-typedef struct bipointer
-{
-  struct bipointer \(**NEXT;
-  void             \(**DATA; 
-} bipointer;
-bipointer \(**addbipointer( Data );
-  void \(**Data;
-{
-  bipointer \(**Bp = (bipointer \(**)autallocheap( sizeof( bipointer ) );
-  Bp->DATA = Data; return Bp;
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR aut(1),
-.BR autresizeblock(3),
-.BR autallocblock(3),
-.BR autfreeblock(3),
-.BR autfreeheap(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/autfreeblock.3 b/alliance/share/man/man3/autfreeblock.3
deleted file mode 100644
index dd4f4282..00000000
--- a/alliance/share/man/man3/autfreeblock.3
+++ /dev/null
@@ -1,52 +0,0 @@
-.\"   $Id: autfreeblock.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)autfreeblock.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH AUTFREEBLOCK 3 "October 1, 1997" "ASIM/LIP6" "AUT FUNCTIONS"
-.SH NAME
-autfreeblock \- releases a memory block
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-void autfreeblock( Pointer )
-   char \(** Pointer;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIPointer\fP
-Pointer to be given back to the system
-.SH DESCRIPTION
-\fBautfreeblock\fP frees a pointer. It is now a day just
-an encapsulation of the system free function, but may evolve to a
-special allocator in the future. Its use is strongly encouraged.
-.br
-.SH RETURN VALUE
-\fBautfreeblock\fP returns nothing.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-  char \(**Pointer;
-  Pointer = autallocblock( 1024 );
-  ...
-  autfreeblock( Pointer );
-.ft R
-.fi
-.SH SEE ALSO
-.BR aut (1),
-.BR autresizeblock(3),
-.BR autallocheap(3),
-.BR autallocblock(3),
-.BR autfreeheap(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/autfreeheap.3 b/alliance/share/man/man3/autfreeheap.3
deleted file mode 100644
index 0156de63..00000000
--- a/alliance/share/man/man3/autfreeheap.3
+++ /dev/null
@@ -1,69 +0,0 @@
-.\"   $Id: autfreeheap.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)autfreeheap.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH AUTFREEHEAP 3 "October 1, 1997" "ASIM/LIP6" "AUT FUNCTIONS"
-.SH NAME
-autfreeheap \- releases a memory block, and put it on the heap.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-void autfreeheap( Pointer, Size )
-   char         \(**Pointer;
-   unsigned int Size;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIPointer\fP
-Pointer to be given back to the heap.
-.TP
-\fISize\fP
-Size of the block previously allocated by \fIautallocheap\fP.
-.SH DESCRIPTION
-\fBautfreeheap\fP frees a pointer and puts the block back to the heap.
-Its use is necessary to free memory blocks, previously allocated
-by \fIautallocheap\fP.
-.br
-.SH RETURN VALUE
-\fBautfreeheap\fP returns nothing.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-typedef struct bipointer
-{
-  struct bipointer \(**NEXT;
-  void             \(**DATA;
-} bipointer;
-bipointer \(**addbipointer( Data );
-  void \(**Data;
-{
-  bipointer \(**Bp = (bipointer \(**)autallocheap( sizeof( bipointer ) );
-  Bp->DATA = Data;
-  return Bp;
-}
-void delbipointer( Bp );
-  bipointer \(**Bp;
-{
-  autfreeheap( Pointer, sizeof( bipointer ) );
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR aut (1),
-.BR autresizeblock(3),
-.BR autallocheap(3),
-.BR autallocblock(3),
-.BR autfreeblock(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/auth2elem.3 b/alliance/share/man/man3/auth2elem.3
deleted file mode 100644
index 44c9fa43..00000000
--- a/alliance/share/man/man3/auth2elem.3
+++ /dev/null
@@ -1,44 +0,0 @@
-.\"   $Id: auth2elem.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)auth2elem.2 1.01 96/02/07 UPMC; Author: Jacomme Ludovic
-.TH AUTH2ELEM 3 "October 1, 1997" "ASIM/LIP6" "AUT STRUCTURE DEFINITIONS"
-.SH NAME
-auth2elem \- element in an hash table with two keys.
-.SH DESCRIPTION
-The \fBauth2elem\fP structure is used to describe an hash element.
-.LP
-The declarations needed to work on \fBauth2elem\fP are available in the header file
-\fI"/labo/include/aut101.h"\fP, where '\fI101\fP' is the actual aut version.
-.LP
-The following C structure supports the description of an hash element :
-.RS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.ta 3n 20n 30n
-  typedef struct auth2elem
-  {
-    char \(**KEY1;
-    char \(**KEY2;
-    long  VALUE;
-  } auth2elem;
-.ft R
-.fi
-.RE
-.TP 20
-\fIKEY1\fP
- KEY1 is the first hash element key, for example a name created with \fInamealloc\fP.
-.TP
-\fIKEY2\fP
- KEY2 is the second hash element key, for example a name created with \fInamealloc\fP.
-.TP
-\fIVALUE\fP
- VALUE is the value associated to the two keys \fIKEY1\fP and \fIKEY2\fP. 
-.SH SEE ALSO
-.BR aut (1),
-.BR auth2table(3),
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/auth2table.3 b/alliance/share/man/man3/auth2table.3
deleted file mode 100644
index 0ca26aeb..00000000
--- a/alliance/share/man/man3/auth2table.3
+++ /dev/null
@@ -1,60 +0,0 @@
-.\"   $Id: auth2table.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)auth2table.2 1.01 96/02/07 UPMC; Author: Jacomme Ludovic
-.TH AUTH2TABLE 3 "October 1, 1997" "ASIM/LIP6" "AUT STRUCTURE DEFINITIONS"
-.SH NAME
-auth2table \- hash table structure
-.SH DESCRIPTION
-The \fBauth2table\fP structure is used to describe an hash table with two keys.
-.LP
-The declarations needed to work on \fBauth2table\fP are available in the header file
-\fI"/labo/include/aut101.h"\fP, where '\fI101\fP' is the actual aut version.
-.LP
-The following C structure supports the description of an hash element :
-.RS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.ta 3n 20n 30n
-  typedef struct auth2table
-  {
-    auth2elem \(**TABLE;
-    long      TABLE_SIZE;
-    long      NUMBER_ELEM;
-    long      NUMBER_ADD;
-    long      NUMBER_SCAN;
-    long      NUMBER_DEL;
-    long      NUMBER_STRETCH;
-  } auth2table;
-.ft R
-.fi
-.RE
-.TP 20
-\fITABLE\fP
- TABLE is the hash element array.
-.TP
-\fITABLE_SIZE\fP
- TABLE_SIZE is the size of the hash table.
-.TP
-\fINUMBER_ELEM\fP
- NUMBER_ELEM is the number of element in the hash table.
-.TP
-\fINUMBER_ADD\fP
- NUMBER_ADD is the number of added elements.
-.TP
-\fINUMBER_SCAN\fP
- NUMBER_SCAN is the number of scans to find an element.
-.TP
-\fINUMBER_DEL\fP
- NUMBER_DEL is the number of deleted elements.
-.TP
-\fINUMBER_STRETCH\fP
- NUMBER_STRETCH is the number of hash table stretch.
-.SH SEE ALSO
-.BR aut (1),
-.BR auth2table(3),
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/authelem.3 b/alliance/share/man/man3/authelem.3
deleted file mode 100644
index ca99a2dc..00000000
--- a/alliance/share/man/man3/authelem.3
+++ /dev/null
@@ -1,40 +0,0 @@
-.\"   $Id: authelem.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)authelem.2 1.01 96/02/07 UPMC; Author: Jacomme Ludovic
-.TH AUTHELEM 3 "October 1, 1997" "ASIM/LIP6" "AUT STRUCTURE DEFINITIONS"
-.SH NAME
-authelem \- element in an hash table
-.SH DESCRIPTION
-The \fBauthelem\fP structure is used to describe an hash element.
-.LP
-The declarations needed to work on \fBauthelem\fP are available in the header file
-\fI"/labo/include/aut101.h"\fP, where '\fI101\fP' is the actual aut version.
-.LP
-The following C structure supports the description of an hash element :
-.RS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.ta 3n 20n 30n
-  typedef struct authelem
-  {
-    char \(**KEY;
-    long  VALUE;
-  } authelem;
-.ft R
-.fi
-.RE
-.TP 20
-\fIKEY\fP
- KEY is the hash element key, for example a name created with \fInamealloc\fP.
-.TP
-\fIVALUE\fP
- VALUE is the value associated to the key \fIKEY\fP. 
-.SH SEE ALSO
-.BR aut (1),
-.BR authtable(3),
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/authtable.3 b/alliance/share/man/man3/authtable.3
deleted file mode 100644
index 8980cdc5..00000000
--- a/alliance/share/man/man3/authtable.3
+++ /dev/null
@@ -1,60 +0,0 @@
-.\"   $Id: authtable.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)authtable.2 1.01 96/02/07 UPMC; Author: Jacomme Ludovic
-.TH AUTHTABLE 3 "October 1, 1997" "ASIM/LIP6" "AUT STRUCTURE DEFINITIONS"
-.SH NAME
-authtable \- hash table structure
-.SH DESCRIPTION
-The \fBauthtable\fP structure is used to describe an hash table.
-.LP
-The declarations needed to work on \fBauthtable\fP are available in the header file
-\fI"/labo/include/aut101.h"\fP, where '\fI101\fP' is the actual aut version.
-.LP
-The following C structure supports the description of an hash element :
-.RS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.ta 3n 20n 30n
-  typedef struct authtable
-  {
-    authelem \(**TABLE;
-    long      TABLE_SIZE;
-    long      NUMBER_ELEM;
-    long      NUMBER_ADD;
-    long      NUMBER_SCAN;
-    long      NUMBER_DEL;
-    long      NUMBER_STRETCH;
-  } authtable;
-.ft R
-.fi
-.RE
-.TP 20
-\fITABLE\fP
- TABLE is the hash element array.
-.TP
-\fITABLE_SIZE\fP
- TABLE_SIZE is the size of the hash table.
-.TP
-\fINUMBER_ELEM\fP
- NUMBER_ELEM is the number of element in the hash table.
-.TP
-\fINUMBER_ADD\fP
- NUMBER_ADD is the number of added elements.
-.TP
-\fINUMBER_SCAN\fP
- NUMBER_SCAN is the number of scans to find an element.
-.TP
-\fINUMBER_DEL\fP
- NUMBER_DEL is the number of deleted elements.
-.TP
-\fINUMBER_STRETCH\fP
- NUMBER_STRETCH is the number of hash table stretch.
-.SH SEE ALSO
-.BR aut (1),
-.BR authtable(3),
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/autresizeblock.3 b/alliance/share/man/man3/autresizeblock.3
deleted file mode 100644
index d6d9bf58..00000000
--- a/alliance/share/man/man3/autresizeblock.3
+++ /dev/null
@@ -1,73 +0,0 @@
-.\"   $Id: autresizeblock.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)autresizeblock.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH AUTRESIZEBLOCK 3 "October 1, 1997" "ASIM/LIP6" "AUT FUNCTIONS"
-.SH NAME
-autresizeblock \- resizes a memory block
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-  char \(**autresize( Source, OldSize, NewSize )
-   char         \(**Source;
-   unsigned int OldSize;
-   unsigned int NewSize;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fISource\fP
-Pointer to the memory block to be resized.
-.TP
-\fIOldSize\fP
-Old size of the memory block.
-.TP
-\fINewSize\fP
-New size of the memory block.
-.SH DESCRIPTION
-\fBautresizeblock\fP resizes a memory block  from \fIOldSize\fP to 
-\fINewSize\fP. if \fINewSize\fP is greater than \fIOldSize\fP then
-the new bytes are set to zero.
-.br
-.SH RETURN VALUE
-\fBautresizeblock\fP returns the pointer to the resized block.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"autresize: resize error, can't continue !"
-.ft R
-.RS
-System break can't be moved anymore, no more memory can be retrieved from the system.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-     char \(**concatstring( t, s )
-        char \(** t;
-        char \(** s;
-     {
-        t = (char \(**)autresizeblock( t, strlen(t)+1, strlen(t)+strlen(s)+1);
-        strcat(t, s);
-        return t;
-     }
-.ft R
-.fi
-.SH SEE ALSO
-.BR aut (1),
-.BR autallocheap(3),
-.BR autallocblock(3),
-.BR autfreeblock(3),
-.BR autfreeheap(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/bddToAblCct.3 b/alliance/share/man/man3/bddToAblCct.3
deleted file mode 100644
index 55ef6066..00000000
--- a/alliance/share/man/man3/bddToAblCct.3
+++ /dev/null
@@ -1,58 +0,0 @@
-.\"   $Id: bddToAblCct.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)bddToAblCct.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH BDDTOABLCCT 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBbddToAblCct\fP \- converts a BDD into an ABL within a circuit 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-chain_list *bddToAblCct(pC,pBdd)
-pCircuit pC;
-pNode pBdd;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIpC\fP
-Circuit in which is made the conversion
-.TP 20
-\fIpBdd\fP
-BDD to convert
-.SH DESCRIPTION
-\fBbddToAblCct()\fP converts \fIpBdd\fP into an expression. This function returns a result that depends from the ordering of the primary input. This function provides the basic method for the logical optimizer called in BOP.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr;
-pNode res;
-pCircuit pC;
-
-initializeBdd(SMALL_BDD);
-pC = initializeCct("circuit 1",10,10);
-
-addInputCct(pC,"a");
-addInputCct(pC,"b");
-
-	/* let's suppose that res = (OR a b) */
-
-expr = bddToAblCct(pC,applyBinBdd(OR,
-                    createNodeTermBdd(searchInputCct(pC,"a"))),
-                    createNodeTermBdd(searchInputCct(pC,"b")));
-displayExpr(expr);
-
-/* it will display 
-(OR a b)
-*/
-
-destroyCct(pC);
-destroyBdd(1);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR abl (1),
-.BR ablToBddCct (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beaux.3 b/alliance/share/man/man3/beaux.3
deleted file mode 100644
index 4a9efdcd..00000000
--- a/alliance/share/man/man3/beaux.3
+++ /dev/null
@@ -1,44 +0,0 @@
-.\"   $Id: beaux.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beaux.2 108 Feb 15 1995 UPMC; Pirouz BAZARGAN SABET
-.TH BEAUX 3 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBbeaux\fP - BEH data structure
-
-.SH DESCRIPTION
-.PP
-\fIbeaux\fP is a data structure used in \fBBEH\fP to represent a one\-bit
-simple internal signal. An internal signal is considered as a simple signal
-when its value is set by one and only one driver.
-For an array, each element is represented by a single structure.
-These are organized in the reverse order of the array\'s range declaration.
-\fIbeaux\fP has been designed to be used in a simply chained list.
-
-.PP
-A \fIbeaux\fP structure is composed of the following fields.
-
-.TP 25
-\fI(char *) NAME\fP
-the signal\'s name. For an array\'s element, the name is the array\'s identifier
-added to the element\'s index seperated by a \' \' (blank space).
-This string is supposed been produced by \fBnamealloc()\fP
-.TP 25
-\fI(struct chain *) ABL\fP
-signal\'s expression represented by an ABL
-.TP 25
-\fI(struct node *) BDD\fP
-signal\'s expression represented by a BDD
-.TP 25
-\fI(struct beaux *) NEXT\fP
-next beaux
-
-.SH SEE ALSO
-.PP
-log(1), beh(3), beh_addbeaux(3), beh_delbeaux(3), beh_frebeaux(3),
-beh_rmvbeaux(3), namealloc(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/bebus.3 b/alliance/share/man/man3/bebus.3
deleted file mode 100644
index fcbf67b1..00000000
--- a/alliance/share/man/man3/bebus.3
+++ /dev/null
@@ -1,47 +0,0 @@
-.\"   $Id: bebus.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)bebus.2 108 Feb 15 1995 UPMC; Pirouz BAZARGAN SABET
-.TH BEBUS 3 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBbebus\fP - BEH data structure
-
-.SH DESCRIPTION
-.PP
-\fIbebus\fP is a data structure used in \fBBEH\fP to represent a one\-bit
-bused output port. A port is considered as a bused output when its value
-is set by at least one deconnectable driver from the inside of the circuit.
-For an array, each element is represented by a single structure.
-These are organized in the reverse order of the array\'s range declaration.
-\fIbebus\fP has been designed to be used in a simply chained list.
-
-.PP
-A \fIbebus\fP structure is composed of the following fields.
-
-.TP 25
-\fI(char *) NAME\fP
-the port\'s name. For an array\'s element, the name is the array\'s identifier
-added to the element\'s index seperated by a \' \' (blank space).
-This string is supposed been produced by \fBnamealloc()\fP
-.TP 25
-\fI(char) TYPE\fP
-port\'s type : W (wor_bit) and, M (mux_bit)
-.TP 25
-\fI(struct biabl *) BIABL\fP
-list of drivers using ABLs to represent expressions
-.TP 25
-\fI(struct binode *) BINODE\fP
-list of drivers using BDDs to represent expressions
-.TP 25
-\fI(struct bebus *) NEXT\fP
-next port
-
-.SH SEE ALSO
-.PP
-log(1), beh(3), biabl(3), binode(3), beh_addbebus(3),
-beh_delbebus(3), beh_frebebus(3), beh_rmvbebus(3), namealloc(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/bebux.3 b/alliance/share/man/man3/bebux.3
deleted file mode 100644
index 9d9c2430..00000000
--- a/alliance/share/man/man3/bebux.3
+++ /dev/null
@@ -1,47 +0,0 @@
-.\"   $Id: bebux.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)bebux.2 108 Feb 15 1995 UPMC; Pirouz BAZARGAN SABET
-.TH BEBUX 3 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBbebux\fP - BEH data structure
-
-.SH DESCRIPTION
-.PP
-\fIbebux\fP is a data structure used in \fBBEH\fP to represent a one\-bit
-bused internal signal. An internal signal is considered as a bused signal
-when its value is set by at least one deconnectable driver.
-For an array, each element is represented by a single structure.
-These are organized in the reverse order of the array\'s range declaration.
-\fIbebux\fP has been designed to be used in a simply chained list.
-
-.PP
-A \fIbebux\fP structure is composed of the following fields.
-
-.TP 25
-\fI(char *) NAME\fP
-the signal\'s name. For an array\'s element, the name is the array\'s identifier
-added to the element\'s index seperated by a \' \' (blank space).
-This string is supposed been produced by \fBnamealloc()\fP
-.TP 25
-\fI(char) TYPE\fP
-port\'s type : W (wor_bit) and, M (mux_bit)
-.TP 25
-\fI(struct biabl *) BIABL\fP
-list of drivers using ABLs to represent expressions
-.TP 25
-\fI(struct binode *) BINODE\fP
-list of drivers using BDDs to represent expressions
-.TP 25
-\fI(struct bebux *) NEXT\fP
-next bebux
-
-.SH SEE ALSO
-.PP
-log(1), beh(3), biabl(3), binode(3), beh_addbebux(3),
-beh_delbebux(3), beh_frebebux(3), beh_rmvbebux(3), namealloc(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/befig.3 b/alliance/share/man/man3/befig.3
deleted file mode 100644
index a11b6f0e..00000000
--- a/alliance/share/man/man3/befig.3
+++ /dev/null
@@ -1,78 +0,0 @@
-.\"   $Id: befig.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)befig.2 108 Feb 15 1995 UPMC; Pirouz BAZARGAN SABET
-.TH BEFIG 3 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBbefig\fP - BEH data structure
-
-.SH DESCRIPTION
-.PP
-\fIbefig\fP is a data structure used in \fBBEH\fP to represent a complete
-behavioural description of a circuit. \fIbefig\fP has been designed to be
-used in a simply chained list.
-
-.PP
-A \fIbefig\fP structure is composed of the following fields.
-
-.TP 25
-\fI(char *) NAME\fP
-the circuit\'s name. This string is supposed been produced by \fBnamealloc()\fP
-.TP 25
-\fI(struct bepor *) BEPOR\fP
-list of ordered ports
-.TP 25
-\fI(struct begen *) BEGEN\fP
-list of generic data
-.TP 25
-\fI(struct beout *) BEOUT\fP
-list of simple output ports (a port is said to be an output when there is at
-least one driver inside the circuit setting its value)
-.TP 25
-\fI(struct bebus *) BEBUS\fP
-list of bused output ports (a port is said to be an output when there is at
-least one driver inside the circuit setting its value)
-.TP 25
-\fI(struct berin *) BERIN\fP
-list of inputs (is considered as input an input port or an internal register)
-.TP 25
-\fI(struct beaux *) BEAUX\fP
-list of internal simple signals
-.TP 25
-\fI(struct beaux *) BEDLY\fP
-list of delayed signals
-.TP 25
-\fI(struct bebux *) BEBUX\fP
-list of internal bused signals
-.TP 25
-\fI(struct bereg *) BEREG\fP
-list of internal registers
-.TP 25
-\fI(struct bemsg *) BEMSG\fP
-list of conditions noticed by the circuit\'s designer that are to be checked to
-insure a correct usage of the circuit
-.TP 25
-\fI(char) ERRFLG\fP
-error flag : set to 0 for a coherent errorless befig
-.TP 25
-\fI(char) TYPE\fP
-type of the description (not used)
-.TP 25
-\fI(struct circuit *) CIRCUI\fP
-circuit pointer used when expressions are represented with BDDs
-.TP 25
-\fI(struct ptype *) USER\fP
-user defined data
-.TP 25
-\fI(struct befig *) NEXT\fP
-next befig
-
-.SH SEE ALSO
-.PP
-bdd(1), beh(3), beh_addbefig(3), beh_delbefig(3), beh_frebefig(3),
-beh_rmvbefig(3), namealloc(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/begen.3 b/alliance/share/man/man3/begen.3
deleted file mode 100644
index f1d11f37..00000000
--- a/alliance/share/man/man3/begen.3
+++ /dev/null
@@ -1,49 +0,0 @@
-.\"   $Id: begen.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)begen.2 108 Feb 15 1995 UPMC; Pirouz BAZARGAN SABET
-.TH BEGEN 3 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBbegen\fP - BEH data structure
-
-.SH DESCRIPTION
-.PP
-\fIbegen\fP is a data structure used in \fBBEH\fP to represent a one\-bit
-global constant relative to the circuit. A \fBbegen\fP list must be ordered
-in the reverse order of the constant declarations in the text file.
-For an array, each element is represented by a single structure.
-These are organized in the reverse order of the array\'s range declaration.
-\fIbegen\fP has been designed to be used in a simply chained list.
-
-.PP
-A \fIbegen\fP structure is composed of the following fields.
-
-.TP 25
-\fI(char *) NAME\fP
-the constant\'s name. For an array\'s element, the name is the array\'s
-identifier added to the element\'s index seperated by a \' \' (blank space).
-This string is supposed been produced by \fBnamealloc()\fP
-.TP 25
-\fI(char *) TYPE\fP
-constant\'s type. This string is supposed been produced by \fBnamealloc()\fP
-Up to now only \fInatural\fP type is legal.
-.TP 25
-\fI(void *) VALUE\fP
-constant\'s value
-.TP 25
-\fI(struct begen *) NEXT\fP
-next begen
-
-.PP
-It is to be noticed that \fBbegen\fP list can be accessed in a \fBbefig\fP
-through the USER field.
-
-.SH SEE ALSO
-.PP
-beh(3), befig(3), beh_addbegen(3), beh_delbegen(3), beh_frebegen(3),
-beh_rmvbegen(3), namealloc(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh.3 b/alliance/share/man/man3/beh.3
deleted file mode 100644
index ef030899..00000000
--- a/alliance/share/man/man3/beh.3
+++ /dev/null
@@ -1,152 +0,0 @@
-.\"   $Id: beh.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh.2 108  Feb 15 1995 UPMC; Pirouz BAZARGAN SABET
-.TH BEH 3 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBBEH\fP \- Generic behavioural data structures
-
-.SH DESCRIPTION
-.PP
-\fBBEH\fP is a generic data structure supporting vlsi concepts.
-It allows representation of a behavioral description in a data structure.
-
-.PP
-The goal of \fBBEH\fP is to define an ad hoc single data structure (object),
-with well known fixed meaning for each concept manipulated within a behavioural
-description. So any tools that needs to work with a behavioral view can be
-build upon it using these structures.
-
-.PP
-For each object (data structure), a set of functions has been defined in order
-to add, delete or access it. These functions are defined in a low\-level library
-\fIlibBeh108.a\fP. Some other functions are higher level. They are defined in a
-high\-level library \fIlibBhl108.a\fP. There are also some parsers\-drivers.
-A pareser reads a behavioural description file in a given format and build up a
-complete \fBBEH\fP data base. A driver creates a text file in a given
-behavioural description format from a \fBBEH\fP data base. A VHDL
-parser\-driver is available in the \fIlibBvl103.a\fP library.
-
-.PP
-The behavioural view envolves the following notions:
-
-.TP 20
-\fIfigure\fP
-behavioural representation of a circuit (see \fBBEFIG\fP).
-.TP 20
-\fIport list\fP
-ordered list of the circuit's logical ports (see \fBBEPOR\fP).
-.TP 20
-\fIgeneric\fP
-a global data (constants) relative to a circuit other than logical ports (see
-\fBBEGEN\fP).
-.TP 20
-\fIsimple output\fP
-a simple output port of the circuit (see \fBBEOUT\fP). 
-.TP 20
-\fIbused output\fP
-a bused output port of the circuit (see \fBBEBUS\fP).
-.TP 20
-\fIinput\fP
-an input port of the circuit (see \fBBERIN\fP).
-.TP 20
-\fIinternal register\fP
-an internal memorizing element (see \fBBEREG\fP).
-.TP 20
-\fIinternal signal\fP
-an internal simple signal of the circuit (see \fBBEAUX\fP).
-.TP 20
-\fIinternal bus\fP
-an internal bused signal of the circuit (see \fBBEBUX\fP).
-.TP 20
-\fIassert\fP
-a condition, noticed by the circuit designer, that insures a correct usage of
-the circuit. The validity of these conditions is to be checked continuously at
-run time (see \fBBEMSG\fP).
-
-.PP
-In order to use \fBBEH\fP, concepts on use of libraries are needed. And, since
-these libraries are under development, the code is subject to change.
-
-.PP
-To enable work, a static version of each library is always present for the
-user. Libraries and header files are suffixed by a number (the library's
-version). The programmer can prefer to work with an earlier version of a
-library rather than the most recent one. However, it is recommended to adapt
-softwares to libraries as soon as possible in order to spotlight potential
-compatibility problems before old libraries are removed.
-
-.PP
-A \fImakefile\fP is necessary for all \fBBEH\fP applications.
-This is required because any soft must be easily recompilable, and knowing
-the needed libraries for a \fBBEH\fP based program is not an easy matter.
-It can't be achieved an other way, so do use \fImakefile\fP.
-
-.PP
-For each behavioural description format a parser and a driver have been
-developed . These are organized in as many seperate libraries as description
-format. So if a parser or driver changes it is not needed to recompile
-\fBBEH\fP. Only a relink of the application is needed.
-
-.PP
-In terms of software organization, \fBBEH\fP is splitted into two libraries
-for the basic functions, a header file for structures and variable declarations,
-and , up to now, one parser\-driver library for VHDL format.
-
-.PP
-It is to be noticed that library's version number is incremented when, at least,
-one function composing the library has been modified. Therefore, \fBBEH\fP
-libraries may evolve independently form each other.
-
-.ta 1.5i 3i 4.5i
-.PP
-Here follows the list of the libraries and their contents.
-
-.TP 20
-libBeh108.a:
-\fBbeh_addbefig,	beh_addbeaux,	beh_addbebux\fP,
-\fBbeh_addbegen,	beh_addbebus,	beh_addbemsg\fP,
-\fBbeh_addbeout,	beh_addbepor,	beh_addbereg\fP,
-\fBbeh_addberin,	beh_addbiabl,	beh_addbinode\fP,
-\fBbeh_delbefig,	beh_delbeaux,	beh_delbebux\fP,
-\fBbeh_delbegen,	beh_delbebus,	beh_delbemsg\fP,
-\fBbeh_delbeout,	beh_delbepor,	beh_delbereg\fP,
-\fBbeh_delberin,	beh_delbiabl,	beh_delbinode\fP,
-\fBbeh_frebefig,	beh_frebeaux,	beh_frebebux\fP,
-\fBbeh_frebegen,	beh_frebebus,	beh_frebemsg\fP,
-\fBbeh_frebeout,	beh_frebepor,	beh_frebereg\fP,
-\fBbeh_freberin,	beh_frebiabl,	beh_frebinode\fP,
-\fBbeh_rmvbefig,	beh_rmvbeaux,	beh_rmvbebux\fP,
-\fBbeh_rmvbegen,	beh_rmvbebus,	beh_rmvbemsg\fP,
-\fBbeh_rmvbeout,	beh_rmvbepor,	beh_rmvbereg\fP,
-\fBbeh_rmvberin\fP
-
-.TP 20
-libBhl108.a:
-\fBbeh_debug\fP
-
-.PP
-The libraries are organized in such a way that no cycle can appear through
-calls. It means that if a given library a function calls another function
-in another library, then none of the functions of this one does call any
-function that belongs to the first library.
-
-.SH EXAMPLE
-.PP
-In order to use BEH libraries, one needs something like that in its
-\fImakefile\fP:
-
-.RS
-HEADER = -I/labo/include
-.br
-LIB = -L/labo/lib -lBeh108 -lBhl108 -lBvl109 -llog200 -lMut315
-.RE
-
-.SH SEE ALSO
-.PP
-mbk(1), log(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_addbeaux.3 b/alliance/share/man/man3/beh_addbeaux.3
deleted file mode 100644
index db208892..00000000
--- a/alliance/share/man/man3/beh_addbeaux.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_addbeaux.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_addbeaux.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbeaux.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_addbebus.3 b/alliance/share/man/man3/beh_addbebus.3
deleted file mode 100644
index 53eb7359..00000000
--- a/alliance/share/man/man3/beh_addbebus.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_addbebus.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_addbebus.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbebus.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_addbebux.3 b/alliance/share/man/man3/beh_addbebux.3
deleted file mode 100644
index 52a5bebd..00000000
--- a/alliance/share/man/man3/beh_addbebux.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_addbebux.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_addbebux.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbebux.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_addbefig.3 b/alliance/share/man/man3/beh_addbefig.3
deleted file mode 100644
index 0366ec4b..00000000
--- a/alliance/share/man/man3/beh_addbefig.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_addbefig.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_addbefig.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbefig.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_addbegen.3 b/alliance/share/man/man3/beh_addbegen.3
deleted file mode 100644
index 6b39cc08..00000000
--- a/alliance/share/man/man3/beh_addbegen.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_addbegen.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_addbegen.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbegen.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_addbemsg.3 b/alliance/share/man/man3/beh_addbemsg.3
deleted file mode 100644
index c07a484e..00000000
--- a/alliance/share/man/man3/beh_addbemsg.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_addbemsg.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_addbemsg.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbemsg.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_addbeout.3 b/alliance/share/man/man3/beh_addbeout.3
deleted file mode 100644
index fc3986d0..00000000
--- a/alliance/share/man/man3/beh_addbeout.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_addbeout.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_addbeout.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbeout.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_addbepor.3 b/alliance/share/man/man3/beh_addbepor.3
deleted file mode 100644
index 3bd1ead2..00000000
--- a/alliance/share/man/man3/beh_addbepor.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_addbepor.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_addbepor.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbepor.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_addbereg.3 b/alliance/share/man/man3/beh_addbereg.3
deleted file mode 100644
index fa8e90dd..00000000
--- a/alliance/share/man/man3/beh_addbereg.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_addbereg.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_addbereg.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbereg.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_addberin.3 b/alliance/share/man/man3/beh_addberin.3
deleted file mode 100644
index 31322cd3..00000000
--- a/alliance/share/man/man3/beh_addberin.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_addberin.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_addberin.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funberin.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_addbiabl.3 b/alliance/share/man/man3/beh_addbiabl.3
deleted file mode 100644
index 0ddb3345..00000000
--- a/alliance/share/man/man3/beh_addbiabl.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_addbiabl.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_addbiabl.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbiabl.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_addbinod.3 b/alliance/share/man/man3/beh_addbinod.3
deleted file mode 100644
index 6f0d19b6..00000000
--- a/alliance/share/man/man3/beh_addbinod.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_addbinod.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_addbinod.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbinod.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_debug.3 b/alliance/share/man/man3/beh_debug.3
deleted file mode 100644
index d39e8af5..00000000
--- a/alliance/share/man/man3/beh_debug.3
+++ /dev/null
@@ -1,133 +0,0 @@
-.\"   $Id: beh_debug.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_debug.3 109 Oct 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.TH BEH_DEBUG 3 "October 1, 1997" "ASIM/LIP6" "BHL functions"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBbeh_debug\fP \- BEH structures displayer\-debugger
-
-.SH SYNOPSYS
-.PP
-.nf
-void beh_debug (pnt, type)
-void *pnt;
-char *type;
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIpnt\fP
-pointer of the structure to be displayed
-.TP 10
-\fItype\fP
-name of the structure to be displayed. \fItype\fP can be any of "befig",
-"beout", "bereg", "bemsg", "bepor", "begen", "berin", "bebus", "beaux",
-"bebux", "biabl", "binode", "beder", "bequad", "abl", "integer", "long",
-"short", "character", "ptype", "chain"
-
-.SH DESCRIPTION
-.PP
-When called, \fBbeh_debug()\fP displaies the structure pointed by
-\fIpnt\fP then, prints the line:
-
-.RS
-COMMAND   >>
-.RE
-
-and waits for a command being entered by the user. If \fIpnt\fP is a NULL
-pointer or \fItype\fP doesn\'t represent a known structure, \fBbeh_debug()\fP
-exits without making any action.
-
-.PP
-To display the structure, \fBbeh_debug()\fP prints a line per field. Fields
-containing immediate value (integer, character, string, ...) are displayed
-in the following form:
-
-.RS
-name_of_the_field  :  value_of_the_field
-.RE
-
-.PP
-Fields containing a pointer are marked by the symbol \fB\->\fP. If the field
-contains a NULL pointer, the field is displayed as:
-
-.RS
--> name_of_the_field  :
-.RE
-
-In the other case, \fBbeh_debug()\fP prints :
-
-.RS
--> name_of_the_field  :  available
-.RE
-
-.PP
-Two kinds of command are accepted by the displayer.
-
-.PP
-A command can be the name of a field containing a pointer. The command is
-accepted only if the pointer is not a NULL pointer (field displayed as
-"available"). When the debugger receives such a command, it first pushes the
-current structure on its stack then, displaies the structure pointed by the
-named field.
-
-.PP
-The second kind of commands are predefined commands :
-
-.RS
-.TP 10
-\fB_exit\fP
-to exit from the debugger
-.TP 10
-\fB_up\fP
-to return to the previous structure
-.TP 10
-\fB_stop\fP
-to put a stop mark on the current structure
-.TP 10
-\fB_top\fP
-to return to the first structure (pointed by \fIpnt\fP)
-.TP 10
-\fB_back\fP
-to return to the last structure marked with a stop mark
-.TP 10
-\fB_save\fP
-to save the current structure in a static table. At most 10 structures may
-be saved. (example : "_save 1" saves the current structure in the entry
-number ! of the table)
-.TP 10
-\fB_jump\fP
-to jump to a saved structure (example : "_jump 1" dislpaies the etructure
-save in the entry number 1 of the table).
-.TP 10
-\fB_display\fP
-displaies a field under a given format. (example : "_display next integer" displaies the field named \fInext\fP as an integer).
-.RE
-
-.PP
-In addition to these commands, the command \fB.\fP (dot) can be used to repete
-the last command.
-
-.SH EXAMPLE
-.PP
-.nf
-#include <beh109.h>
-struct beout *beout_pnt;
-
-beh_debug (beout_pnt , "beout");
-.fi
-
-.SH NOTES
-.PP
-\fBbeh_debug()\fP uses an internal stack. The message \fI"stack overflow"\fP
-is printed if too many structures have been pushed on the stack.
-
-.SH SEE ALSO
-.PP
-beh(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_delbeaux.3 b/alliance/share/man/man3/beh_delbeaux.3
deleted file mode 100644
index cc3464ae..00000000
--- a/alliance/share/man/man3/beh_delbeaux.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_delbeaux.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_delbeaux.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbeaux.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_delbebus.3 b/alliance/share/man/man3/beh_delbebus.3
deleted file mode 100644
index 5bc4a51a..00000000
--- a/alliance/share/man/man3/beh_delbebus.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_delbebus.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_delbebus.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbebus.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_delbebux.3 b/alliance/share/man/man3/beh_delbebux.3
deleted file mode 100644
index aff60184..00000000
--- a/alliance/share/man/man3/beh_delbebux.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_delbebux.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_delbebux.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbebux.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_delbefig.3 b/alliance/share/man/man3/beh_delbefig.3
deleted file mode 100644
index 49f44d43..00000000
--- a/alliance/share/man/man3/beh_delbefig.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_delbefig.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_delbefig.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbefig.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_delbegen.3 b/alliance/share/man/man3/beh_delbegen.3
deleted file mode 100644
index 26ef4de0..00000000
--- a/alliance/share/man/man3/beh_delbegen.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_delbegen.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_delbegen.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbegen.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_delbemsg.3 b/alliance/share/man/man3/beh_delbemsg.3
deleted file mode 100644
index 5110f9da..00000000
--- a/alliance/share/man/man3/beh_delbemsg.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_delbemsg.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_delbemsg.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbemsg.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_delbeout.3 b/alliance/share/man/man3/beh_delbeout.3
deleted file mode 100644
index ef187632..00000000
--- a/alliance/share/man/man3/beh_delbeout.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_delbeout.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_delbeout.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbeout.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_delbepor.3 b/alliance/share/man/man3/beh_delbepor.3
deleted file mode 100644
index d14c22a0..00000000
--- a/alliance/share/man/man3/beh_delbepor.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_delbepor.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_delbepor.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbepor.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_delbereg.3 b/alliance/share/man/man3/beh_delbereg.3
deleted file mode 100644
index 7b4a73e3..00000000
--- a/alliance/share/man/man3/beh_delbereg.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_delbereg.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_delbereg.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbereg.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_delberin.3 b/alliance/share/man/man3/beh_delberin.3
deleted file mode 100644
index 894fdb47..00000000
--- a/alliance/share/man/man3/beh_delberin.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_delberin.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_delberin.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funberin.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_delbiabl.3 b/alliance/share/man/man3/beh_delbiabl.3
deleted file mode 100644
index c4282f9a..00000000
--- a/alliance/share/man/man3/beh_delbiabl.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_delbiabl.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_delbiabl.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbiabl.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_delbinod.3 b/alliance/share/man/man3/beh_delbinod.3
deleted file mode 100644
index f532bd1a..00000000
--- a/alliance/share/man/man3/beh_delbinod.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_delbinod.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_delbinod.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbinod.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_depend.3 b/alliance/share/man/man3/beh_depend.3
deleted file mode 100644
index 5f4e8d46..00000000
--- a/alliance/share/man/man3/beh_depend.3
+++ /dev/null
@@ -1,53 +0,0 @@
-.\"   $Id: beh_depend.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_depend.3 109 Oct 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.TH BEH_DEPEND 3 "October 1, 1997" "ASIM/LIP6" "BHL functions"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBbeh_depend\fP \- compute forward dependencies in a description
-
-.SH SYNOPSYS
-.PP
-.nf
-void beh_depend (fig_pnt)
-struct befig *fig_pnt;
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIfig_pnt\fP
-pointer of the BEFIG structure
-
-.SH DESCRIPTION
-.PP
-\fBbeh_depend()\fP analyzes the forward dependencies in a whole description
-(a BEFIG). Forward dependency means, for each input finding out the set of
-outputs that depend on it.
-
-.PP
-\fIfig_pnt\fP represents the pointer of the description to be analyzed.
-
-.PP
-After the analysis is acheived, \fBbeh_depend\fP produces a set of dependency
-lists for each input. Each dependency list is a list of pointers to those
-outputs that depends on the input. A seprate list is produced for each type
-of outputs (BEOUT, BEREG, BEAUX, BEBUX, BEMSG, BEDLY, BEBUS).
-
-.SH EXAMPLE
-.PP
-.nf
-#include <beh109.h>
-struct befig *befig_pnt;
-
-beh_depend (befig_pnt);
-.fi
-
-.SH SEE ALSO
-.PP
-beh(3), befig(3), berin(3), beaux(3), bereg(3), beh_debug(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_error.3 b/alliance/share/man/man3/beh_error.3
deleted file mode 100644
index f7e59dad..00000000
--- a/alliance/share/man/man3/beh_error.3
+++ /dev/null
@@ -1,39 +0,0 @@
-.\"   $Id: beh_error.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_error.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.TH BEH_ERROR 3 "October 1, 1997" "ASIM/LIP6" "BEH functions"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBbeh_error\fP
-
-.SH SYNOPSYS
-.PP
-.nf
-int beh_error (code, str)
-int code;
-char *str;
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIcode\fP
-error\'s code
-.TP 10
-\fIstr\fP
-a string to be printed within the error message
-
-.SH DESCRIPTION
-.PP
-\fBbeh_error()\fP prints an error message on the standard error output
-depending on an error code. The \fIcode\fP parameter determines the message
-to be printed.
-
-.SH SEE ALSO
-.PP
-beh(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_frebeaux.3 b/alliance/share/man/man3/beh_frebeaux.3
deleted file mode 100644
index 44b81ef2..00000000
--- a/alliance/share/man/man3/beh_frebeaux.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_frebeaux.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_frebeaux.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbeaux.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_frebebus.3 b/alliance/share/man/man3/beh_frebebus.3
deleted file mode 100644
index 3b0c04b9..00000000
--- a/alliance/share/man/man3/beh_frebebus.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_frebebus.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_frebebus.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbebus.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_frebebux.3 b/alliance/share/man/man3/beh_frebebux.3
deleted file mode 100644
index 967e54e2..00000000
--- a/alliance/share/man/man3/beh_frebebux.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_frebebux.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_frebebux.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbebux.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_frebefig.3 b/alliance/share/man/man3/beh_frebefig.3
deleted file mode 100644
index f3c7f33b..00000000
--- a/alliance/share/man/man3/beh_frebefig.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_frebefig.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_frebefig.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbefig.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_frebegen.3 b/alliance/share/man/man3/beh_frebegen.3
deleted file mode 100644
index 345a6e31..00000000
--- a/alliance/share/man/man3/beh_frebegen.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_frebegen.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_frebegen.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbegen.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_frebemsg.3 b/alliance/share/man/man3/beh_frebemsg.3
deleted file mode 100644
index 537f3d06..00000000
--- a/alliance/share/man/man3/beh_frebemsg.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_frebemsg.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_frebemsg.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbemsg.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_frebeout.3 b/alliance/share/man/man3/beh_frebeout.3
deleted file mode 100644
index cdce2177..00000000
--- a/alliance/share/man/man3/beh_frebeout.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_frebeout.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_frebeout.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbeout.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_frebepor.3 b/alliance/share/man/man3/beh_frebepor.3
deleted file mode 100644
index d7d0cb34..00000000
--- a/alliance/share/man/man3/beh_frebepor.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_frebepor.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_frebepor.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbepor.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_frebereg.3 b/alliance/share/man/man3/beh_frebereg.3
deleted file mode 100644
index 4b650afc..00000000
--- a/alliance/share/man/man3/beh_frebereg.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_frebereg.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_frebereg.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbereg.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_freberin.3 b/alliance/share/man/man3/beh_freberin.3
deleted file mode 100644
index bf1aefac..00000000
--- a/alliance/share/man/man3/beh_freberin.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_freberin.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_freberin.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funberin.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_frebiabl.3 b/alliance/share/man/man3/beh_frebiabl.3
deleted file mode 100644
index e95724c5..00000000
--- a/alliance/share/man/man3/beh_frebiabl.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_frebiabl.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_frebiabl.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbiabl.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_frebinod.3 b/alliance/share/man/man3/beh_frebinod.3
deleted file mode 100644
index 03ddb7fa..00000000
--- a/alliance/share/man/man3/beh_frebinod.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_frebinod.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_frebinod.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbinod.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_getgenva.3 b/alliance/share/man/man3/beh_getgenva.3
deleted file mode 100644
index de01614e..00000000
--- a/alliance/share/man/man3/beh_getgenva.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_getgenva.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_getgenva.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbegen.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_makbdd.3 b/alliance/share/man/man3/beh_makbdd.3
deleted file mode 100644
index 914b2385..00000000
--- a/alliance/share/man/man3/beh_makbdd.3
+++ /dev/null
@@ -1,53 +0,0 @@
-.\"   $Id: beh_makbdd.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_makbdd.3 109 Oct 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.TH BEH_MAKBDD 3 "October 1, 1997" "ASIM/LIP6" "BHL functions"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBbeh_makbdd\fP \- create a BDD for each expression in a description
-
-.SH SYNOPSYS
-.PP
-.nf
-void beh_makbdd (fig_pnt)
-struct befig *fig_pnt;
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIfig_pnt\fP
-pointer of the BEFIG structure
-
-.SH DESCRIPTION
-.PP
-\fBbeh_makbdd()\fP reads a whole behavioral description (a BEFIG) and
-creates a BDD for each expression present in the description. For simple
-signals (simple outputs - BEOUT, simple iternal signals - BEAUX, simple
-internal delayed signals - BEDLY), one BDD is created which corresponds to
-the expression that drives the signal. The BDD is stored into a specific
-field in the corresponding structure (NODE). For signals that have multiple
-expressions (registers, internal busses, bussed ports), one BDD is created
-for each expression and stored in the corresponding field of the structure
-(CNDNODE for conditions or VALNODE for the value).
-
-.PP
-\fIfig_pnt\fP represents the pointer of the description.
-
-.SH EXAMPLE
-.PP
-.nf
-#include <beh109.h>
-struct befig *befig_pnt;
-
-beh_makbdd (befig_pnt);
-.fi
-
-.SH SEE ALSO
-.PP
-beh(3), befig(3), berin(3), beaux(3), bereg(3), beh_debug(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_makgex.3 b/alliance/share/man/man3/beh_makgex.3
deleted file mode 100644
index 7267c28f..00000000
--- a/alliance/share/man/man3/beh_makgex.3
+++ /dev/null
@@ -1,55 +0,0 @@
-.\"   $Id: beh_makgex.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_makgex.3 109 Oct 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.TH BEH_MAKGEX 3 "October 1, 1997" "ASIM/LIP6" "BHL functions"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBbeh_makgex\fP \- create a GEX for each expression in a description
-
-.SH SYNOPSYS
-.PP
-.nf
-void beh_makgex (fig_pnt)
-struct befig *fig_pnt;
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIfig_pnt\fP
-pointer of the BEFIG structure
-
-.SH DESCRIPTION
-.PP
-\fBbeh_makgex()\fP reads a whole behavioral description (a BEFIG) and
-creates a GEX for each expression present in the description. A GEX is
-a structure able to represents binary expressions. It has almost the same
-organization as an ABL but, like a BDD, uses an index to represent variables.
-For simple signals (simple outputs - BEOUT, simple iternal signals - BEAUX,
-simple internal delayed signals - BEDLY), one GEX is created which corresponds
-to the expression that drives the signal. The GEX is stored into a specific
-field in the corresponding structure (NODE). For signals that have multiple
-expressions (registers, internal busses, bussed ports), one GEX is created
-for each expression and stored in the corresponding field of the structure
-(CNDNODE for conditions or VALNODE for the value).
-
-.PP
-\fIfig_pnt\fP represents the pointer of the description.
-
-.SH EXAMPLE
-.PP
-.nf
-#include <beh109.h>
-struct befig *befig_pnt;
-
-beh_makgex (befig_pnt);
-.fi
-
-.SH SEE ALSO
-.PP
-beh(3), befig(3), berin(3), beaux(3), bereg(3), beh_debug(3), beh_makbdd(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_message.3 b/alliance/share/man/man3/beh_message.3
deleted file mode 100644
index bcb1d851..00000000
--- a/alliance/share/man/man3/beh_message.3
+++ /dev/null
@@ -1,39 +0,0 @@
-.\"   $Id: beh_message.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_message.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.TH BEH_MESSAGE 3 "October 1, 1997" "ASIM/LIP6" "BEH functions"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBbeh_message\fP
-
-.SH SYNOPSYS
-.PP
-.nf
-void beh_message (code, str)
-int code;
-char *str;
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIcode\fP
-error\'s code
-.TP 10
-\fIstr\fP
-a string to be printed within the error message
-
-.SH DESCRIPTION
-.PP
-\fBbeh_message()\fP prints an error message on the standard output depending
-on a message code. The \fIcode\fP parameter determines the message to be
-printed.
-
-.SH SEE ALSO
-.PP
-beh (3), beh_error(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_rmvbeaux.3 b/alliance/share/man/man3/beh_rmvbeaux.3
deleted file mode 100644
index 841fa5fe..00000000
--- a/alliance/share/man/man3/beh_rmvbeaux.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_rmvbeaux.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_rmvbeaux.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbeaux.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_rmvbebus.3 b/alliance/share/man/man3/beh_rmvbebus.3
deleted file mode 100644
index 3983e0a6..00000000
--- a/alliance/share/man/man3/beh_rmvbebus.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_rmvbebus.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_rmvbebus.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbebus.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_rmvbebux.3 b/alliance/share/man/man3/beh_rmvbebux.3
deleted file mode 100644
index 9c5d56df..00000000
--- a/alliance/share/man/man3/beh_rmvbebux.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_rmvbebux.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_rmvbebux.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbebux.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_rmvbefig.3 b/alliance/share/man/man3/beh_rmvbefig.3
deleted file mode 100644
index 1ad17696..00000000
--- a/alliance/share/man/man3/beh_rmvbefig.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_rmvbefig.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_rmvbefig.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbefig.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_rmvbegen.3 b/alliance/share/man/man3/beh_rmvbegen.3
deleted file mode 100644
index 7a220d26..00000000
--- a/alliance/share/man/man3/beh_rmvbegen.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_rmvbegen.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_rmvbegen.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbegen.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_rmvbemsg.3 b/alliance/share/man/man3/beh_rmvbemsg.3
deleted file mode 100644
index ca9cd40f..00000000
--- a/alliance/share/man/man3/beh_rmvbemsg.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_rmvbemsg.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)beh_rmvbemsg.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbemsg.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_rmvbeout.3 b/alliance/share/man/man3/beh_rmvbeout.3
deleted file mode 100644
index 1a46acc1..00000000
--- a/alliance/share/man/man3/beh_rmvbeout.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_rmvbeout.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)beh_rmvbeout.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbeout.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_rmvbepor.3 b/alliance/share/man/man3/beh_rmvbepor.3
deleted file mode 100644
index b9d124ec..00000000
--- a/alliance/share/man/man3/beh_rmvbepor.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_rmvbepor.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)beh_rmvbepor.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbepor.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_rmvbereg.3 b/alliance/share/man/man3/beh_rmvbereg.3
deleted file mode 100644
index 4183126c..00000000
--- a/alliance/share/man/man3/beh_rmvbereg.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_rmvbereg.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)beh_rmvbereg.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funbereg.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beh_rmvberin.3 b/alliance/share/man/man3/beh_rmvberin.3
deleted file mode 100644
index ba8e6456..00000000
--- a/alliance/share/man/man3/beh_rmvberin.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: beh_rmvberin.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)beh_rmvberin.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funberin.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/bemsg.3 b/alliance/share/man/man3/bemsg.3
deleted file mode 100644
index f986f998..00000000
--- a/alliance/share/man/man3/bemsg.3
+++ /dev/null
@@ -1,47 +0,0 @@
-.\"   $Id: bemsg.3,v 1.1 1999/05/31 17:30:18 alliance Exp $
-.\" @(#)bemsg.2 108 Feb 15 1995 UPMC; Pirouz BAZARGAN SABET
-.TH BEMSG 3 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBbemsg\fP - BEH data structure
-
-.SH DESCRIPTION
-.PP
-\fIbemsg\fP is a data structure used in \fBBEH\fP to represent a condition.
-To check the correct usage of the circuit, the circuit designer can asserts
-a set of normal\-usage conditions. The validity of these conditions is to
-be checked continiously during circuit\'s simulation.
-\fIbemsg\fP has been designed to be used in a simply chained list.
-
-.PP
-A \fIbemsg\fP structure is composed of the following fields.
-
-.TP 25
-\fI(char *) LABEL\fP
-the assert\'s label. This string is supposed been produced by \fBnamealloc()\fP
-.TP 25
-\fI(struct chain *) ABL\fP
-condition\'s expression represented by an ABL
-.TP 25
-\fI(struct node *) BDD\fP
-condition\'s expression represented by a BDD
-.TP 25
-\fI(char) LEVEL\fP
-severity level : E (error) or, W (warning)
-.TP 25
-\fI(char *) MESSAGE\fP
-message to be printed out when the condition goes to flase
-.TP 25
-\fI(struct bemsg *) NEXT\fP
-next bemsg
-
-.SH SEE ALSO
-.PP
-log(3), beh(3), beh_addbemsg(3), beh_delbemsg(3), beh_frebemsg(3),
-beh_rmvbemsg(3), namealloc(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/beout.3 b/alliance/share/man/man3/beout.3
deleted file mode 100644
index dc52971a..00000000
--- a/alliance/share/man/man3/beout.3
+++ /dev/null
@@ -1,44 +0,0 @@
-.\"   $Id: beout.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)beout.2 108 Feb 15 1995 UPMC; Pirouz BAZARGAN SABET
-.TH BEOUT 3 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBbeout\fP - BEH data structure
-
-.SH DESCRIPTION
-.PP
-\fIbeout\fP is a data structure used in \fBBEH\fP to represent a one\-bit
-simple output port. A port is considered as a simple output when its value
-is set by one and only one driver from the inside of the circuit.
-For an array, each element is represented by a single structure.
-These are organized in the reverse order of the array\'s range declaration.
-\fIbeout\fP has been designed to be used in a simply chained list.
-
-.PP
-A \fIbeout\fP structure is composed of the following fields.
-
-.TP 25
-\fI(char *) NAME\fP
-the port\'s name. For an array\'s element, the name is the array\'s identifier
-added to the element\'s index seperated by a \' \' (blank space).
-This string is supposed been produced by \fBnamealloc()\fP
-.TP 25
-\fI(struct chain *) ABL\fP
-port\'s expression represented by an ABL
-.TP 25
-\fI(struct node *) BDD\fP
-port\'s expression represented by a BDD
-.TP 25
-\fI(struct beout *) NEXT\fP
-next port
-
-.SH SEE ALSO
-.PP
-log(1), beh(3), beh_addbeout(3), beh_delbeout(3), beh_frebeout(3),
-beh_rmvbeout(3), namealloc(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/bepor.3 b/alliance/share/man/man3/bepor.3
deleted file mode 100644
index ed2e6f8a..00000000
--- a/alliance/share/man/man3/bepor.3
+++ /dev/null
@@ -1,45 +0,0 @@
-.\"   $Id: bepor.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)bepor.2 108 Feb 15 1995 UPMC; Pirouz BAZARGAN SABET
-.TH BEPOR 3 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBbepor\fP - BEH data structure
-
-.SH DESCRIPTION
-.PP
-\fIbepor\fP is a data structure used in \fBBEH\fP to represent a one\-bit
-port. A \fBbepor\fP list must be ordered in the reverse order of the port
-declarations in the text file. For an array, each element is represented
-by a single structure. These are organized in the reverse order of the
-array\'s range declaration. \fIbepor\fP has been designed to be used in a
-simply chained list.
-
-.PP
-A \fIbepor\fP structure is composed of the following fields.
-
-.TP 25
-\fI(char *) NAME\fP
-the port\'s name. For an array\'s element, the name is the array\'s identifier
-added to the element\'s index seperated by a \' \' (blank space).
-This string is supposed been produced by \fBnamealloc()\fP
-.TP 25
-\fI(char) DIRECTION\fP
-port\'s mode : I (input), O (output), Z (bused output), B (inout) and,
-T (bused inout)
-.TP 25
-\fI(char) TYPE\fP
-port\'s type : B (bit), M (mux_bit) and, W (wor_bit)
-.TP 25
-\fI(struct bepor *) NEXT\fP
-next port
-
-.SH SEE ALSO
-.PP
-beh(3), beh_addbepor(3), beh_delbepor(3), beh_frebepor(3), beh_rmvbepor(3),
-namealloc(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/bereg.3 b/alliance/share/man/man3/bereg.3
deleted file mode 100644
index 59682611..00000000
--- a/alliance/share/man/man3/bereg.3
+++ /dev/null
@@ -1,43 +0,0 @@
-.\"   $Id: bereg.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)bereg.2 108 Feb 15 1995 UPMC; Pirouz BAZARGAN SABET
-.TH BEREG 3 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBbereg\fP - BEH data structure
-
-.SH DESCRIPTION
-.PP
-\fIbereg\fP is a data structure used in \fBBEH\fP to represent a one\-bit
-internal register.
-For an array, each element is represented by a single structure.
-These are organized in the reverse order of the array\'s range declaration.
-\fIbereg\fP has been designed to be used in a simply chained list.
-
-.PP
-A \fIbereg\fP structure is composed of the following fields.
-
-.TP 25
-\fI(char *) NAME\fP
-the register\'s name. For an array\'s element, the name is the array\'s
-identifier added to the element\'s index seperated by a \' \' (blank space).
-This string is supposed been produced by \fBnamealloc()\fP
-.TP 25
-\fI(struct biabl *) BIABL\fP
-list of drivers using ABLs to represent expressions
-.TP 25
-\fI(struct binode *) BINODE\fP
-list of drivers using BDDs to represent expressions
-.TP 25
-\fI(struct bereg *) NEXT\fP
-next bereg
-
-.SH SEE ALSO
-.PP
-log(1), beh(3), biabl(3), binode(3), beh_addbereg(3),
-beh_delbereg(3), beh_frebereg(3), beh_rmvbereg(3), namealloc(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/berin.3 b/alliance/share/man/man3/berin.3
deleted file mode 100644
index 022a160c..00000000
--- a/alliance/share/man/man3/berin.3
+++ /dev/null
@@ -1,59 +0,0 @@
-.\"   $Id: berin.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)berin.2 108 Feb 15 1995 UPMC; Pirouz BAZARGAN SABET
-.TH BERIN 3 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBberin\fP - BEH data structure
-
-.SH DESCRIPTION
-.PP
-\fIberin\fP is a data structure used in \fBBEH\fP to represent a one\-bit
-input signal. For an array, each element is represented by a single structure.
-Is considered as input signal either an input port of circuit (a port is said
-input when its value is readable inside the circuit) or, an internal register.
-An internal signal can also be considered as an input. \fIberin\fP has been
-designed to be used in a simply chained list.
-
-.PP
-A \fIberin\fP structure is composed of the following fields.
-
-.TP 25
-\fI(char *) NAME\fP
-the object\'s name. For an array\'s element, the name is the array\'s identifier
-added to the element\'s index seperated by a \' \' (blank space).
-This string is supposed been produced by \fBnamealloc()\fP
-.TP 25
-\fI(struct chain *) OUT_REF\fP
-list of simple out ports that depend on the current input.
-.TP 25
-\fI(struct chain *) BUS_REF\fP
-list of bussed out ports that depend on the current input.
-.TP 25
-\fI(struct chain *) AUX_REF\fP
-list of simple internal signals that depend on the current input.
-.TP 25
-\fI(struct chain *) BUX_REF\fP
-list of bussed internal signals that depend on the current input.
-.TP 25
-\fI(struct chain *) REG_REF\fP
-list of internal registers that depend on the current input.
-.TP 25
-\fI(struct chain *) MSG_REF\fP
-list of internal assert statements that depend on the current input.
-.TP 25
-\fI(struct chain *) DLY_REF\fP
-list of delayed internal signals that depend on the current input.
-.TP 25
-\fI(struct berin *) NEXT\fP
-next berin
-
-.SH SEE ALSO
-.PP
-beh(3), beh_addberin(3), beh_delberin(3), beh_freberin(3),
-beh_rmvberin(3), namealloc(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/biabl.3 b/alliance/share/man/man3/biabl.3
deleted file mode 100644
index ed6601fd..00000000
--- a/alliance/share/man/man3/biabl.3
+++ /dev/null
@@ -1,37 +0,0 @@
-.\"   $Id: biabl.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)biabl.2 108 Feb 15 1995 UPMC; Pirouz BAZARGAN SABET
-.TH BIABL 3 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBbiabl\fP - BEH data structure
-
-.SH DESCRIPTION
-.PP
-\fIbiabl\fP is a data structure used in \fBBEH\fP to represent a deconnectable
-driver. \fIbiabl\fP has been designed to be used in a simply chained list.
-
-.PP
-A \fIbiabl\fP structure is composed of the following fields.
-
-.TP 25
-\fI(char *) LABEL\fP
-driver's label
-.TP 25
-\fI(struct chain *) CNDABL\fP
-connection codition of the driver expressed with an ABL
-.TP 25
-\fI(struct chain *) VALABL\fP
-value emitted by the driver expressed with an ABL
-.TP 25
-\fI(struct biabl *) NEXT\fP
-next biabl
-
-.SH SEE ALSO
-.PP
-log(1), beh(3), beh_addbiabl(3), beh_delbiabl(3), beh_frebiabl(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/bigvia.3 b/alliance/share/man/man3/bigvia.3
deleted file mode 100644
index d97705d7..00000000
--- a/alliance/share/man/man3/bigvia.3
+++ /dev/null
@@ -1,81 +0,0 @@
-.\"   $Id: bigvia.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)bigvia.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-bigvia
-.XE
-.XS1 \n%
-.ti 0.2i
-bigvia
-.XE1 \}
-.TH BIGVIA 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL UTILITY FUNCTIONS"
-.SH NAME
-bigvia \- draws a non minimal via as a bunch of vias
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph403.h"
-void \(**bigvia(figure, viatype, x, y, dx, dy)
-phfig_list \(**figure;
-char viatype;
-long x, y, dx, dy;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIfigure\fP
-Pointer to the physical figure in the which vias must be put.
-.TP 20
-\fIviatype\fP
-Contact type to be put.
-.TP 20
-\fIx, y\fP
-Coordinate of the center of the bigvia.
-.TP 20
-\fIdx, dy\fP
-Maximun rectangle to be filled with vias.
-.SH DESCRIPTION
-\fBbigvia\fP draws as many vias as necessary to fill the rectangle defined by
-its \fIdx\fP and \fPdy\fP arguments.
-The ``bigvia'' center is indicated with \fIdx\fP and \fPdy\fP, thus making this
-function much like \fBaddphvia\fP.
-The necessary segments are drawn to avoid having notches or other drc rules
-violated.
-.br
-This function is tipically used by routers when connecting two non minimal wires,
-like supplies or clocks.
-.br
-The values for drawing the via correctly, ie avoid drc violations, are taken
-from the idps set of rules, and are not changeable at run time.
-.SH ERRORS
-.RS
-"*** mbk error ***
-bigvia impossible : negative values dx, dy in figure figure at (x, y)"
-.RE
-If either \fIdx\fP or \fIdy\fP are negative, the function complains and exits.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph403.h"
-#define BigVia(x, y, dx, dy) \\
-	bigvia(WORK_PHFIG, CONT_VIA, x, y, dx, dy)
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR addphvia (3),
-.BR addphseg (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/binod.3 b/alliance/share/man/man3/binod.3
deleted file mode 100644
index 022e9512..00000000
--- a/alliance/share/man/man3/binod.3
+++ /dev/null
@@ -1,34 +0,0 @@
-.\"   $Id: binod.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)binode.2 107 Jun 30 1994 UPMC; Pirouz BAZARGAN SABET
-.TH BINOD 3 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBbinode\fP - BEH data structure
-
-.SH DESCRIPTION
-.PP
-\fIbinode\fP is a data structure used in \fBBEH\fP to represent a deconnectable
-driver. \fIbinode\fP has been designed to be used in a simply chained list.
-
-.PP
-A \fIbinode\fP structure is composed of the following fields.
-
-.TP 25
-\fI(struct node *) CNDBDD\fP
-connection codition of the driver expressed with a BDD
-.TP 25
-\fI(struct node *) VALBDD\fP
-value emitted by the driver expressed with an BDD
-.TP 25
-\fI(struct binode *) NEXT\fP
-next binode
-
-.SH SEE ALSO
-.PP
-log(1), beh(3), beh_addbinode(3), beh_delbinode(3), beh_frebinode(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/binode.3 b/alliance/share/man/man3/binode.3
deleted file mode 100644
index 1f20a64b..00000000
--- a/alliance/share/man/man3/binode.3
+++ /dev/null
@@ -1,34 +0,0 @@
-.\"   $Id: binode.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)binode.2 108 Feb 15 1995 UPMC; Pirouz BAZARGAN SABET
-.TH BINODE 3 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBbinode\fP - BEH data structure
-
-.SH DESCRIPTION
-.PP
-\fIbinode\fP is a data structure used in \fBBEH\fP to represent a deconnectable
-driver. \fIbinode\fP has been designed to be used in a simply chained list.
-
-.PP
-A \fIbinode\fP structure is composed of the following fields.
-
-.TP 25
-\fI(struct node *) CNDBDD\fP
-connection codition of the driver expressed with a BDD
-.TP 25
-\fI(struct node *) VALBDD\fP
-value emitted by the driver expressed with an BDD
-.TP 25
-\fI(struct binode *) NEXT\fP
-next binode
-
-.SH SEE ALSO
-.PP
-log(1), beh(3), beh_addbinode(3), beh_delbinode(3), beh_frebinode(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/buildrdswindow.3 b/alliance/share/man/man3/buildrdswindow.3
deleted file mode 100644
index 88db4754..00000000
--- a/alliance/share/man/man3/buildrdswindow.3
+++ /dev/null
@@ -1,119 +0,0 @@
-.\"   $Id: buildrdswindow.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)buildrdswindow.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-buildrdswindow
-.XE
-.XS0 \n%
-.ti 0.2i
-buildrdswindow
-.XE0 \}
-.TH BUILDRDSWINDOW 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-buildrdswindow \- builds windowing of a figure
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rwinnn.h"
- rdswindow \(**buildrdswindow( Figure )
-    rdsfig_list \(**Figure;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIFigure\fP
-The figure where has to be built the windowing.
-.SH DESCRIPTION
-The \fIbuildrdswindow\fP function permits to build windowing on the figure named \'Figure\'.
-.SH RETURN VALUE
-The pointer to the windowing structure "rdswindow".
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Rds202: rdsalloc error, can't continue !"
-.ft R
-.RS
-it's impossible to allocate the memory size desired
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mphnnn.h"
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rfmnnn.h"
-        #include "rwinnn.h"
-        #include "rtlnnn.h"
-        main()
-          {
-            phfig_list     \(**MbkFigure;
-            rdsfig_list    \(**RdsFigure;
-            rdswindow      \(**Window;
-            long            X,Y,Offset;
-            rdswin_list    \(**Win;
-            rdswinrec_list \(**WinRec;
-            rdsrec_list    \(**ScanRec;
-            char            Layer;
-            char            Index;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            MbkFigure = getphfig("na2_y",'A');
-            RdsFigure = figmbkrds(MbkFigure,0,0); 
-            Window    =  \fBbuildrdswindow\fP ( RdsFigure );
-            /\(** gets each window of the table \(**/
-            for ( X = 0 ; X < Window->DX ; X ++ )
-             for ( Y = 0 ; Y < Window->DY ; Y ++ ) 
-              {
-                printf("WINDOW (%ld,%ld)\\n",X,Y);              
-                Offset = Y \(** Window->DX + X;
-                Win = Window->WINTAB + Offset;
-                /\(** gets all rectangles of a window \(**/
-                for ( Layer = 0 ; Layer < RWI_MAX_LAYER ; Layer ++ )               
-                 {
-                   printf("LAYER = %s\\n",RDS_LAYER_NAME[Layer]);
-                   for ( WinRec  = Win->LAYERTAB[ Layer ];
-                         WinRec != (rdswinrec_list \(**)NULL;
-                         WinRec  = WinRec->NEXT )
-                    {
-                      for (
-                            Index = 0;
-                            Index < RWI_MAX_REC;
-                            Index++
-                          )
-                       {
-                        ScanRec = WinRec->RECTAB[ Index ];
-                        /\(** prints dimensions of each rectangle \(**/
-                        if ( ScanRec != NULL )
-                        printf("X=%ld, Y=%ld, DX=%ld, DY=%ld\\n",
-                               ScanRec->X,ScanRec->Y,ScanRec->DX,
-                               ScanRec->DY);
-                        else break;
-                       }
-                    }
-                 }
-              }
-            . . .
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librwi,
-.BR allocrdswindow,
-.BR destroyrdswindow,
-.BR viewrdswindow
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/chain.3 b/alliance/share/man/man3/chain.3
deleted file mode 100644
index edd04495..00000000
--- a/alliance/share/man/man3/chain.3
+++ /dev/null
@@ -1,58 +0,0 @@
-.\"   $Id: chain.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)chain.l 0.0 90/22/08 UPMC; Author: Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-chain
-.XE
-.XS4 \n%
-.ti 0.2i
-chain
-.XE4 \}
-.TH CHAIN 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY STRUCTURE DEFINITIONS"
-.SH NAME
-chain \- mbk lisp-like service structure 
-.SH DESCRIPTION
-The \fBchain\fP is used for any purpose, when a list of pointer is required.
-The use of this structure is strongly recommanded, when such a need occurs.
-.LP
-The declarations needed to work on \fBchain\fP are available in the header file
-\fI"/labo/include/mut315.h"\fP, where '\fI315\fP' is the actual mbk version.
-.LP
-The following C structure supports the description of the chain :
-.RS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.ta 3n 20n 30n
-typedef struct chain {
-	struct chain	\(**NEXT;
-	void	\(**DATA;
-} chain_list;
-.ft R
-.fi
-.RE
-.TP 20
-\fINEXT\fP
-Pointer to the next \fBchain\fP of the list.
-.TP
-\fIDATA\fP
-Generic pointer used to point to any kind of object. Do not forget to
-cast the pointer back to its previous type when using this field.
-.TP
-Remark :
-a specialized memory allocator has been built in order to create and free
-\fBchain_list\fPs, so absolutly avoid to create or free them an other way than
-through the access functions.
-.SH SEE ALSO
-.BR mbk (1),
-.BR addchain (3),
-.BR freechain (3),
-.BR delchain (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/changeOperExpr.3 b/alliance/share/man/man3/changeOperExpr.3
deleted file mode 100644
index 2daf3535..00000000
--- a/alliance/share/man/man3/changeOperExpr.3
+++ /dev/null
@@ -1,53 +0,0 @@
-.\"   $Id: changeOperExpr.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)changeOperExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH CHANGEOPEREXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBchangeOperExpr\fP \- changes the operator of the head of an expression.
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-void changeOperExpr(expr,oper)
-chain_list *expr;
-short oper;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIexpr\fP
-expression
-.TP 20
-\fIoper\fP
-the new operator of the expression
-.SH DESCRIPTION
-\fBchangeOperExpr()\fP changes the operator of the head of \fIexpr\fP with \fIoper\fP.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr; 
-expr = createExpr(OR);
-addQExpr(expr,createAtom("a"));
-addQExpr(expr,createAtom("b"));
-displayExpr(expr);
-changeOperExpr(expr, NAND);
-displayExpr(expr);
-/* it will display
- (or a b)
- (nand a b)
-*/
-freeExpr(expr);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR searchExpr (3),
-.BR searchOperExpr (3),
-.BR searchNumExpr (3),
-.BR equalExpr (3),
-.BR equalVarExpr (3),
-.BR lengthExpr (3),
-.BR profExpr (3),
-.BR numberAtomExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/charToExpr.3 b/alliance/share/man/man3/charToExpr.3
deleted file mode 100644
index 49e71b4f..00000000
--- a/alliance/share/man/man3/charToExpr.3
+++ /dev/null
@@ -1,41 +0,0 @@
-.\"   $Id: charToExpr.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)charToExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH CHARTOEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBcharToExpr\fP \- converts a string into an expression 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-chain_list *charToExpr(stringExpr)
-char *stringExpr;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIstringExpr\fP
-String to convert. 
-.SH DESCRIPTION
-\fBcharToExpr()\fP converts \fIstringExpr\fP into an expression.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-displayExpr(charToExpr("(nor a (and b c))"));
-displayInfExpr(charToExpr("(nor a (and b c))"));
-/* it will display
-(nor a (and b c))
-(a nor (b and c))
-*/
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR exprToChar (3),
-.BR displayExpr (3),
-.BR displayInfExpr (3),
-.BR charToOper (3),
-.BR operToChar (3),
-.BR identExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/charToOper.3 b/alliance/share/man/man3/charToOper.3
deleted file mode 100644
index 3631bc8f..00000000
--- a/alliance/share/man/man3/charToOper.3
+++ /dev/null
@@ -1,39 +0,0 @@
-.\"   $Id: charToOper.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)charToOper.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH CHARTOOPER 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBcharToOper\fP \- converts an operator string into an operator number
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-short charToOper(name)
-char *name;
-.fi
-.SH PARAMETER
-.TP 20
-\fIname\fP
-Operator char *.
-.SH DESCRIPTION
-\fBcharToOper()\fP returns the operator number associated to \fIname\fP. If there's no associated value, the function returns -1.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-printf("OR = %d   ",charToOper("OR"));
-printf("AND = %d",charToOper("AND"));
-/* it will display
-OR = 0   AND = 1
-*/
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR operToChar (3),
-.BR displayExpr (3),
-.BR displayInfExpr (3),
-.BR exprToChar (3),
-.BR identExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/checkloconorder.3 b/alliance/share/man/man3/checkloconorder.3
deleted file mode 100644
index 72986980..00000000
--- a/alliance/share/man/man3/checkloconorder.3
+++ /dev/null
@@ -1,112 +0,0 @@
-.\"   $Id: checkloconorder.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)checkloconorder.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-checkloconorder
-.XE
-.XS2 \n%
-.ti 0.2i
-checkloconorder
-.XE2 \}
-.TH CHECKLOCONORDER 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL FUNCTIONS"
-.SH NAME
-checkloconorder \- checks the consistency of a list of logical connectors
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo412.h"
-void checkloconorder(connectors)
-locon_list \(**connectors;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIconnectors\fP
-Pointer to the head of the connector list that is to be sorted
-.SH DESCRIPTION
-\fBcheckloconorder\fP checks the list of logical connectors pointed to
-by \fI\(**connectors\fP for conformity towards \fBmbk\fP(1) consistency
-rules.
-Checks are done to warranty :
-.TP 20
-\fBorder\fP
-the functions checks that vectorized connectors are ordered and evolve
-monotonically, with a step of 1.
-.TP 20
-\fBname unicity\fP
-Vector radicals may not appear as single entity.
-.TP 20
-\fBname validity\fP
-No space should appear in the name, but a single one followed by a number
-in a vector.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** radical \fIname\fP already used in a
-connector"
-.ft R
-.RS
-The \fIname\fP is already used in a connector, either vectorized or not,
-and therefore cannot be used once more.
-This ensures that \fBf\fP and \fBf 3\fP will not be used simultaneously.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** the radical \fIname\fP has a spurious 
-vectorized value"
-.ft R
-.RS
-The \fIname\fP is seen as a vector in \fBmbk\fP(1), but its index is not a
-number or some text follows that number.
-.RE
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** the radical \fIname\fP is not
-vectorized properly"
-.ft R
-.RS
-The \fIname\fP is seen as a vector in \fBmbk\fP(1), but its index changes
-in such a way that it is not monotonically increasing or decreasing with
-a step of 1.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo412.h"
-void savewithcheck(figname)
-char \(**figname;
-{
-lofig_list \(**figure = getlocon(figname, 'A');
-  checkloconorder(figure->LOCON);
-  savelofig(figure);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR locon (3),
-.BR addlocon (3),
-.BR dellocon (3),
-.BR checkloconorder (3),
-.BR qsort (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/clearbddsystemref.3 b/alliance/share/man/man3/clearbddsystemref.3
deleted file mode 100644
index d6537618..00000000
--- a/alliance/share/man/man3/clearbddsystemref.3
+++ /dev/null
@@ -1,52 +0,0 @@
-.\"   $Id: clearbddsystemref.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)clearbddsystemref.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH CLEARBDDSYSTEMREF 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-clearbddsystemref \- clears the references for all \fBbdd\fP nodes.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-void clearbddsystemref( BddSystem )
-  bddsystem \(*BddSystem;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.SH DESCRIPTION
-\fBclearbddsystemref\fP clears the internal and external references
-of all the \fBbdd\fP nodes in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBclearbddsystemref\fP returns nothing.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   ...
-   clearbddsystemref( (bddsystem \(**)0 );
-   ...
-   destroybddsystem( (bddsystem \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1),
-.BR clearbddsystemrefint(3),
-.BR clearbddsystemrefext(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/clearbddsystemrefext.3 b/alliance/share/man/man3/clearbddsystemrefext.3
deleted file mode 100644
index b8504248..00000000
--- a/alliance/share/man/man3/clearbddsystemrefext.3
+++ /dev/null
@@ -1,52 +0,0 @@
-.\"   $Id: clearbddsystemrefext.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)clearbddsystemrefext.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH CLEARBDDSYSTEMREFEXT 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-clearbddsystemrefext \- clears the external references for all \fBbdd\fP nodes.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-void clearbddsystemrefext( BddSystem )
-  bddsystem \(*BddSystem;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.SH DESCRIPTION
-\fBclearbddsystemrefext\fP clears the external references
-of all the \fBbdd\fP nodes in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBclearbddsystemrefext\fP returns nothing.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   ...
-   clearbddsystemrefext( (bddsystem \(**)0 );
-   ...
-   destroybddsystem( (bddsystem \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1),
-.BR clearbddsystemref(3),
-.BR clearbddsystemrefint(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/clearbddsystemrefint.3 b/alliance/share/man/man3/clearbddsystemrefint.3
deleted file mode 100644
index 5b2235fc..00000000
--- a/alliance/share/man/man3/clearbddsystemrefint.3
+++ /dev/null
@@ -1,52 +0,0 @@
-.\"   $Id: clearbddsystemrefint.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)clearbddsystemrefint.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH CLEARBDDSYSTEMREFINT 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-clearbddsystemrefint \- clears the internal references for all \fBbdd\fP nodes.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-void clearbddsystemrefint( BddSystem )
-  bddsystem \(*BddSystem;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.SH DESCRIPTION
-\fBclearbddsystemrefint\fP clears the internal references
-of all the \fBbdd\fP nodes in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBclearbddsystemrefint\fP returns nothing.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   ...
-   clearbddsystemrefint( (bddsystem \(**)0 );
-   ...
-   destroybddsystem( (bddsystem \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1),
-.BR clearbddsystemref(3),
-.BR clearbddsystemrefext(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/cofactorbddnode.3 b/alliance/share/man/man3/cofactorbddnode.3
deleted file mode 100644
index b55c77f4..00000000
--- a/alliance/share/man/man3/cofactorbddnode.3
+++ /dev/null
@@ -1,88 +0,0 @@
-.\"   $Id: cofactorbddnode.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)cofactorbddnode.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH COFACTORBDDNODE 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-cofactorbddnode \- computes the generalized cofactor.
-
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddnode \(**cofactorbddnode( BddSystem, BddNode1, BddNode2 )
-  bddsystem \(**BddSystem;
-  bddnode   \(**BddNode1;
-  bddnode   \(**BddNode2;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIBddNode1\fP
-The first \fBbdd\fP node.
-.TP
-\fIBddNode2\fP
-The second \fBbdd\fP node.
-.SH DESCRIPTION
-\fBcofactorbddnode\fP computes the generalized cofactor of
-\fIBddNode1\fP by \fIBddNode2\fP, in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBcofactorbddnode\fP returns the resulting \fBbdd\fP node.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"index xxx out of range"
-.ft R
-.RS
-The \fIBddNode2\fP parameter must be different to the zero \fBbdd\fP node.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode1;
-   bddnode    \(**BddNode2;
-   bddnode    \(**BddNode;
-   chain_list \(**Expr;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   Expr = createablbinexpr( ABL_OR,
-                            createablatom( "i0" ),
-                            createablatom( "i1" ) );
-   BddNode1 = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   Expr = createablbinexpr( ABL_AND,
-                            createablatom( "i0" ),
-                            createablatom( "i1" ) );
-   BddNode2 = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   BddNode = cofactorbddnode( (bddsystem \(**)0, BddNode1, BddNode2 );
-   Expr = convertbddcircuitabl( BddCircuit, BddNode );
-   /* displays '1' */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/comment.3 b/alliance/share/man/man3/comment.3
deleted file mode 100644
index f72a0418..00000000
--- a/alliance/share/man/man3/comment.3
+++ /dev/null
@@ -1,39 +0,0 @@
-.\"   $Id: comment.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)COMMENT.2 1.9  UPMC ; VUONG H.N.
-.TH COMMENT 3 "October 1, 1997" "ASIM/LIP6" "GENPAT functions"
-
-.SH NAME
-.PP
-\fBcomment\fP, GENPAT Package
-
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.PP
-.nf
-comment("chain of char");
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIchain of char\fP
-The COMMENT asked.
-
-.SH DESCRIPTION
-.PP
-the comment is inserted in the output file in the list of pattern where it
-is declared.
-
-.SH EXAMPLE
-.PP
-.nf
-comment("This is my first comment");
-.fi
-
-.SH SEE ALSO
-.PP
-genpat(1), pat(5)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/composeBdd.3 b/alliance/share/man/man3/composeBdd.3
deleted file mode 100644
index 04ec5170..00000000
--- a/alliance/share/man/man3/composeBdd.3
+++ /dev/null
@@ -1,60 +0,0 @@
-.\"   $Id: composeBdd.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)composeBdd.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH COMPOSEBDD 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBcomposeBdd\fP \- substitutes an index by a BDD in another BDD
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-pNode composeBdd(pBdd1,pBdd2,index)
-pNode pBdd1;
-pNode pBdd2;
-short index;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIpBdd1\fP
-BDD in wich \fIindex\fP is substituted
-.TP 20
-\fIpBdd2\fP
-BDD that replaces \fIindex\fP
-.TP 20
-\fIindex\fP
-index to substitute
-.SH DESCRIPTION
-\fBcomposeBdd()\fP constructs the graph for the function obtained by composing \fIpBdd1\fP and \fIpBdd2\fP.
-This function can be used when an auxiliary variable has been mistaken for a primary input. 
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-pNode nodeA,nodeB;
-pNode res;
-
-initializeBdd(SMALL_BDD);
-nodeA = createNodeTermBdd(3);
-nodeB = createNodeTermBdd(3);
-res = applyBinBdd(OR,nodeA,nodeB);	/* res = (OR a b) */
-res = composeBdd(res,notBdd(nodeB),2);	/* composition : a = (NOT B) */
-displayBdd(res,1);
-
-/* it will display 
-@res   ONE 
-*/
-	
-destroyBdd(1);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR applyBdd (3),
-.BR notBdd (3),
-.BR constraintBdd (3),
-.BR applyBinBdd (3),
-.BR addListBdd (3),
-.BR displayBdd (3),
-.BR createNodeTermBdd (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/composeCct.3 b/alliance/share/man/man3/composeCct.3
deleted file mode 100644
index 06e1b543..00000000
--- a/alliance/share/man/man3/composeCct.3
+++ /dev/null
@@ -1,71 +0,0 @@
-.\"   $Id: composeCct.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)composeCct.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH COMPOSECCT 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBcomposeCct\fP \- composes all the outputs within a circuit with a BDD
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-void composeCct(pC,name,pBdd)
-pCircuit pC;
-char *name;
-pNode pBdd;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIpC\fP
-Circuit in which is made the composition
-.TP 20
-\fIname\fP
-name to substitute
-.TP 20
-\fIpBdd\fP
-BDD that replaces the variable
-.SH DESCRIPTION
-\fBcomposeCct()\fP substitutes the nodes associated to \fIname\fP by \fIpBdd\fP within \fIpC\fP.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr;
-pNode res;
-pCircuit pC;
-
-initializeBdd(SMALL_BDD);
-pC = initializeCct("circuit 1",10,10);
-
-addInputCct(pC,"a");
-addInputCct(pC,"b");
-
-addOutputCct(pC,"s",applyBinBdd(OR,
-                        createNodeTermBdd(searchInputCct(pC,"a")),
-                        createNodeTermBdd(searchInputCct(pC,"b"))));
-
-	/* a is replaced by (not b) */
-
-composeCct(pC,"a",notBdd(createNodeTermBdd(searchInputCct(pC,"b"))));
-
-displayCct(pC,1);
-
-/* it will display 
-************* DISPLAY circuit 1 *********
-INPUT = b	INDEX = 3
------------ NUMBER OF INPUTS = 1
-OUTPUT = s	s = 1
------------ NUMBER OF OUTPUTS = 1
-*****************************************
-*/
-
-destroyCct(pC);
-destroyBdd(1);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR abl (1),
-.BR upVarCct (3),
-.BR constraintCct (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/composebddnode.3 b/alliance/share/man/man3/composebddnode.3
deleted file mode 100644
index ae59fcc9..00000000
--- a/alliance/share/man/man3/composebddnode.3
+++ /dev/null
@@ -1,97 +0,0 @@
-.\"   $Id: composebddnode.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)composebddnode.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH COMPOSEBDDNODE 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-composebddnode \- substitutes a variable by a \fBbdd\fP in another \fBbdd\fP.
-
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddnode \(**composebddnode( BddSystem, BddNode, Variable, BddSubst )
-  bddsystem \(**BddSystem;
-  bddnode   \(**BddNode;
-  bddvar     Variable;
-  bddnode   \(**BddSubst;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIBddNode\fP
-The \fBbdd\fP node.
-.TP
-\fIVariable\fP
-The variable to find.
-.TP
-\fIBddSubst\fP
-The \fBbdd\fP to substitute with.
-.SH DESCRIPTION
-\fBcomposebddnode\fP substitutes all the occurency of the variable \fIVariable\fP
-in the \fBbdd\fP node \fIBddNode\fP by the \fBbdd\fP node \fIBddSubst\fP, in the
-\fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBcomposebddnode\fP returns the resulting \fBbdd\fP node.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"variable xxx out of range, error !"
-.ft R
-.RS
-The \fIVariable\fP parameter must be less or equal to
-the \fIBddSystem->NUMBER_VAR\fP field.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddVariable;
-   bddnode    \(**BddNode;
-   bddnode    \(**BddSubst;
-   chain_list \(**Expr;
-   bddvar         Variable;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   Expr = createablbinexpr( ABL_AND,
-                            createablatom( "i0" ),
-                            createablatom( "i1" ) );
-   BddNode = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   Expr = createablbinexpr( ABL_OR,
-                            createablatom( "i2" ),
-                            createablatom( "i3" ) );
-   BddSubst = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   BddVariable = searchbddcircuitin( (bddcircuit \(**)0, "i0" );
-   Variable = getbddvarbyindex( (bddsystem \(**)0, BddVariable->INDEX );
-   BddNode = composebddnode( (bddsystem \(**)0, BddNode, Variable, BddSubst );
-   Expr = convertbddcircuitabl( BddCircuit, BddNode );
-   /* displays (i1 and (i2 or i3)) */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/concatname.3 b/alliance/share/man/man3/concatname.3
deleted file mode 100644
index b89a0b10..00000000
--- a/alliance/share/man/man3/concatname.3
+++ /dev/null
@@ -1,69 +0,0 @@
-.\"   $Id: concatname.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)concatname.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-concatname
-.XE
-.XS4 \n%
-.ti 0.2i
-concatname
-.XE4 \}
-.TH CONCATNAME 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-concatname \- concatenate two names with user separator
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-char \(**concatname(s, t)
-char \(**s, \(**t;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIs\fP
-Pointer to a string
-.TP
-\fIt\fP
-Pointer to a string
-.SH DESCRIPTION
-The \fBconcatname\fP function adds the separator defined by \fBMBK_SEPAR\fP(1),
-and then the string \fIt\fP at the end of string \fIs\fP. This is not like a
-\fBstrcat\fP(3) of the standard library, because \fIs\fP is not beeing modified.
-The string returned has already been put in the names dictionary by
-a call to \fBnamealloc\fP(3).
-.SH RETURN VALUE
-\fBconcatname\fP returns a pointer to a string in the name hash table.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-#include "mlo315.h"
-void flat_sig_alias(ptsig, insname)
-losig_list \(**ptsig;
-char \(**insname;
-{
-chain_list \(**pt;
-	for (pt = ptsig\->NAMECHAIN; pt; pt = pt\->NEXT)
-		pt\->DATA = (void \(**)concatname(insname, (char \(**)pt\->DATA);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR namealloc (3),
-.BR MBK_SEPAR (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/conmbkrds.3 b/alliance/share/man/man3/conmbkrds.3
deleted file mode 100644
index 5097ee61..00000000
--- a/alliance/share/man/man3/conmbkrds.3
+++ /dev/null
@@ -1,89 +0,0 @@
-.\"   $Id: conmbkrds.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)conmbkrds.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-conmbkrds
-.XE
-.XS0 \n%
-.ti 0.2i
-conmbkrds
-.XE0 \}
-.TH CONMBKRDS 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
- conmbkrds \- converts MBK connector to RDS rectangle
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
- #include "rfmnnn.h"
-  rdsrec_list \(**conmbkrds( Figure, Connector )
-    rdsfig_list \(**Figure;
-    phcon_list  \(**Connector;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIFigure\fP
-Rds Figure which has to receive the connector.
-.TP
-\fIConnector\fP
-MBK connector to convert to RDS format.
-.SH DESCRIPTION
-The \fIconmbkrds\fP function creates a RDS rectangle (connector) with a connector from MBK structure \fIphcon_list\fP. The RDS rectangle is added to the figure defined in parameter of the function.
-.SH RETURN VALUE
-The pointer to the RDS rectangle created.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Rds202: rdsalloc error, can't continue !"
-.ft R
-.RS
-it's impossible to allocate the memory size desired
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mphnnn.h"
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rfmnnn.h"
-        #include "rtlnnn.h"
-        typedef struct UserStruct
-         {
-           char \(**STRING;
-           void \(**USER1;
-         } UserStruct;
-        main()
-          {
-            phfig_list  \(**MbkFigure;
-            rdsfig_list \(**RdsFigure;
-            rdsrec_list \(**Con;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            RdsFigure = addrdsfig ("core",sizeof ( UserStruct ) );
-            MbkFigure->PHCON =
-                addphcon ( MbkFigure,NORTH, "in_1", 9, 15, ALU1, 2);
-            Con = \fBconmbkrds\fI (RdsFigure, MbkFigure->PHCON);
-            . . .
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librfm,
-.BR viewrfmcon,
-.BR loadrdsparam
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/constraintBdd.3 b/alliance/share/man/man3/constraintBdd.3
deleted file mode 100644
index 364d4ef7..00000000
--- a/alliance/share/man/man3/constraintBdd.3
+++ /dev/null
@@ -1,58 +0,0 @@
-.\"   $Id: constraintBdd.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)constraintBdd.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH CONSTRAINTBDD 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBconstraintBdd\fP \- restricts a BDD to another BDD
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-pNode constraintBdd(pBdd1,pBdd2)
-pNode pBdd1;
-pNode pBdd2;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIpBdd1\fP
-BDD to restrict 
-.TP 20
-\fIpBdd2\fP
-constraint BDD  
-.SH DESCRIPTION
-\fBconstraintBdd()\fP constructs the graph for the function obtained by restricting \fIpBdd1\fP on \fIpBdd2\fP.
-This function can be used for example when a primary input is stuck at 0 or 1. 
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-pNode nodeA,nodeB;
-pNode res;
-
-initializeBdd(SMALL_BDD);
-nodeA = createNodeTermBdd(3);
-nodeB = createNodeTermBdd(3);
-res = applyBinBdd(OR,nodeA,nodeB);	/* res = (OR a b)
-res = constraintBdd(res,nodeA);		/* a = 1 */
-displayBdd(res,1);
-
-/* it will display 
-@res   ONE 
-*/
-	
-destroyBdd(1);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR simplifDcOneBdd (3),
-.BR simplifDcZeroBdd (3),
-.BR composeBdd (3),
-.BR applyBdd (3),
-.BR notBdd (3),
-.BR applyBinBdd (3),
-.BR addListBdd (3),
-.BR displayBdd (3),
-.BR createNodeTermBdd (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/constraintCct.3 b/alliance/share/man/man3/constraintCct.3
deleted file mode 100644
index bb0d2bf1..00000000
--- a/alliance/share/man/man3/constraintCct.3
+++ /dev/null
@@ -1,68 +0,0 @@
-.\"   $Id: constraintCct.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)constraintCct.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH CONSTRAINTCCT 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBconstraintCct\fP \- restricts all the outputs within a circuit with a BDD constraint
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-void constraintCct(pC,pBdd)
-pCircuit pC;
-pNode pBdd;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIpC\fP
-Circuit in which is made the restriction
-.TP 20
-\fIpBdd\fP
-BDD constraint 
-.SH DESCRIPTION
-\fBconstraintCct()\fP restricts the boolean space to the sub-space corresponding to the on-set of \fIpBdd\fP. This function can be called when a primary input is stuck at 0 or 1. 
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr;
-pNode res;
-pCircuit pC;
-
-initializeBdd(SMALL_BDD);
-pC = initializeCct("circuit 1",10,10);
-
-addInputCct(pC,"a");
-addInputCct(pC,"b");
-
-addOutputCct(pC,"s",applyBinBdd(XOR,
-                        createNodeTermBdd(searchInputCct(pC,"a")),
-                        createNodeTermBdd(searchInputCct(pC,"b"))));
-
-	/* b is stuck at 1 */
-
-constraintCct(pC,createNodeTermBdd(searchInputCct(pC,"b")));
-
-displayCct(pC,1);
-
-/* it will display 
-************* DISPLAY circuit 1 *********
-INPUT = a	INDEX = 2 
-INPUT = b	INDEX = 3 
------------ NUMBER OF INPUTS = 2
-OUTPUT = s	s = (NOT a)
------------ NUMBER OF OUTPUTS = 1
-*****************************************
-*/
-
-destroyCct(pC);
-destroyBdd(1);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR abl (1),
-.BR upVarCct (3),
-.BR composeCct (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/conv.3 b/alliance/share/man/man3/conv.3
deleted file mode 100644
index 7418dd0d..00000000
--- a/alliance/share/man/man3/conv.3
+++ /dev/null
@@ -1,40 +0,0 @@
-.\"   $Id: conv.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)CONV.2  1.9 UPMC ; VUONG H.N.
-.TH CONV 3 "October 1, 1997" "ASIM/LIP6" "GENPAT functions"
-
-.SH NAME
-.PP
-\fBconv\fP, GENPAT Package
-
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.PP
-.nf
-conv(variable or constant(integer));
-.fi
-
-.SH DESCRIPTION
-.PP
-Convert an decimal integer, an decimal integer expression or a variable in
-a chain of char considered of base decimal.
-
-.SH EXAMPLE
-.PP
-.nf
-affect(CONV(bar),"ck",CONV(foo),0);
-At pattern number (content of bar), ck is affected with 
-the value represented by the content of the variable foo. 
-Let's suppose bar = 3, foo = 1, so this AFFECT is equivalent to 
-affect("3","ck","1",0);
-
-affect(CONV(bar + foo),"ck","1",0);
-At pattern number (foo + bar, here 4), ck is affected with the value 1.
-.fi
-
-.SH SEE ALSO
-.PP
-genpat(1); pat(5)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/convcmp.3 b/alliance/share/man/man3/convcmp.3
deleted file mode 100644
index 3df0d9db..00000000
--- a/alliance/share/man/man3/convcmp.3
+++ /dev/null
@@ -1,41 +0,0 @@
-.\"   $Id: convcmp.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)CONVCMP.2 1.9  UPMC ; VUONG H.N.
-.TH CONVCMP 3 "October 1, 1997" "ASIM/LIP6" "GENPAT functions"
-
-.SH NAME
-.PP
-\fBconvcmp\fP, GENPAT Package
-
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.PP
-.nf
-convcmp(variable or constant(integer));
-.fi
-
-.SH DESCRIPTION
-.PP
-Convert an decimal integer, an decimal integer expression or a variable in
-a chain of char considered of base decimal suffixed with a '?', it permits to
-compare simulated values with projected values.
-
-.SH EXAMPLE
-.PP
-.nf
-affect(conv(bar),"cl",convcmp(foo),0);
-At pattern number (content of bar), cl is affected with 
-the value represented by the content of the variable foo. 
-Let's suppose bar = 3, foo = 1, so this AFFECT is equivalent to 
-affect("3","ck","?1",0);
-
-affect(conv(bar + foo),"ck","1",0);
-At pattern number (foo + bar, here 4), ck is affected with the value 1.
-.fi
-
-.SH SEE ALSO
-.PP
-genpat(1), pat(5)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/convertbddcircuitabl.3 b/alliance/share/man/man3/convertbddcircuitabl.3
deleted file mode 100644
index 30967c76..00000000
--- a/alliance/share/man/man3/convertbddcircuitabl.3
+++ /dev/null
@@ -1,69 +0,0 @@
-.\"   $Id: convertbddcircuitabl.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)convertbddcircuitabl.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH CONVERTBDDCIRCUITABL 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-convertbddcircuitabl \- converts a \fBbdd\fP node to an \fBabl\fP expression.
-
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-chain_list \(**convertbddcircuitabl( BddCircuit, BddNode )
-  bddcircuit \(**BddCircuit;
-  bddnode    \(**BddNode;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddCircuit\fP
-The \fBbdd\fP circuit.
-.TP
-\fIBddNode\fP
-The \fBbdd\fP node to convert.
-.SH DESCRIPTION
-\fBconvertbddcircuitabl\fP converts the \fBbdd\fP node
-to an \fBabl\fP expression. The \fIBddCircuit\fP is used to translate
-the variable nodes into atomic expressions.
-If a null pointer is given, the default \fBbdd\fP circuit is used.
-.br
-.SH RETURN VALUE
-\fBconvertbddcircuitabl\fP returns a pointer to the \fBabl\fP expression translated.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   chain_list \(**Expr;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   Expr = createablbinexpr( ABL_AND,
-                            createablatom( "i0" ),
-                            createablatom( "i1" ) );
-   BddNode = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   Expr = convertbddcircuitabl( BddCircuit, BddNode );
-   /* displays (i0 and i1) */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1),
-.BR abl (1),
-.BR addbddcircuitabl(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/convertbddcircuitsumabl.3 b/alliance/share/man/man3/convertbddcircuitsumabl.3
deleted file mode 100644
index dbe47551..00000000
--- a/alliance/share/man/man3/convertbddcircuitsumabl.3
+++ /dev/null
@@ -1,69 +0,0 @@
-.\"   $Id: convertbddcircuitsumabl.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)convertbddcircuitsumabl.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH CONVERTBDDCIRCUITSUMABL 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-convertbddcircuitsumabl \- converts a \fBbdd\fP node to an \fBabl\fP expression.
-
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-chain_list \(**convertbddcircuitsumabl( BddCircuit, BddNode )
-  bddcircuit \(**BddCircuit;
-  bddnode    \(**BddNode;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddCircuit\fP
-The \fBbdd\fP circuit.
-.TP
-\fIBddNode\fP
-The \fBbdd\fP node to convert.
-.SH DESCRIPTION
-\fBconvertbddcircuitsumabl\fP converts the \fBbdd\fP node
-to a non optimal \fBabl\fP expression. The \fIBddCircuit\fP is used to translate
-the variable nodes into atomic expressions.
-If a null pointer is given, the default \fBbdd\fP circuit is used.
-.br
-.SH RETURN VALUE
-\fBconvertbddcircuitsumabl\fP returns a pointer to the \fBabl\fP expression translated.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   chain_list \(**Expr;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   Expr = createablbinexpr( ABL_AND,
-                            createablatom( "i0" ),
-                            createablatom( "i1" ) );
-   BddNode = addbddcircuitsumabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   Expr = convertbddcircuitsumabl( BddCircuit, BddNode );
-   /* displays (i0 and i1) */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1),
-.BR abl (1),
-.BR addbddcircuitabl(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/convertbddindexabl.3 b/alliance/share/man/man3/convertbddindexabl.3
deleted file mode 100644
index f5ed2eaf..00000000
--- a/alliance/share/man/man3/convertbddindexabl.3
+++ /dev/null
@@ -1,76 +0,0 @@
-.\"   $Id: convertbddindexabl.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)convertbddindexabl.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH CONVERTBDDINDEXABL 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-convertbddindexabl \- converts a \fBbdd\fP index to an \fBabl\fP expression.
-
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-chain_list *convertbddnodeabl( BddSystem, NameArray, IndexArray, BddNode )
-  bddsystem \(**BddSystem;
-  char     \(**\(**NameArray;
-  bddindex  \(**IndexArray;
-  bddindex      Index;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fINameArray\fP
-The array of names.
-.TP
-\fIIndexArray\fP
-The array of indexes.
-.TP
-\fIIndex\fP
-The \fBbdd\fP index to convert.
-.SH DESCRIPTION
-\fBconvertbddindexabl\fP converts the \fBbdd\fP index \fIIndex\fP
-to an \fBabl\fP expression in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-The \fINameArray\fP, and \fIIndexArray\fP parameters are used
-to translate the variable nodes into atomic expressions.
-The array \fINameArray\fP is list of names.
-The array \fIIndexArray\fP does the correspondence between a \fBbdd\fP index
-and a slot in the \fINameArray\fP. If the \fIIndexArray\fP parameter
-is a null pointer, then the name of the \fBbdd\fP index BDD_INDEX_MIN is assumed
-to be the first slot of the \fINameArray\fP, and so on.
-.br
-.SH RETURN VALUE
-\fBconvertbddindexabl\fP returns a pointer to the \fBabl\fP expression translated.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddnode    \(**BddNode;
-   chain_list \(**Expr;
-   char       \(**NameArray[ 1 ];
-   BddSystem = createbddsystem( 100, 1000, 100, 50000 );
-   BddNode   = addbddvarlast( BddSystem );
-   NameArray[ 0 ] = namealloc( "i0" );
-   Expr = convertbddindexabl( BddSystem, NameArray, (bddindex \(**)0,  BddNode->INDEX );
-   /* displays i0 */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddsystem( (bddsystem \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/convertbddmuxabl.3 b/alliance/share/man/man3/convertbddmuxabl.3
deleted file mode 100644
index b339f1af..00000000
--- a/alliance/share/man/man3/convertbddmuxabl.3
+++ /dev/null
@@ -1,90 +0,0 @@
-.\"   $Id: convertbddmuxabl.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)convertbddmuxabl.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH CONVERTBDDMUXABL 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-convertbddmuxabl \- converts two \fBbdd\fP nodes to an \fBabl\fP multiplexor expression.
-
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-chain_list *convertbddmuxabl( BddSystem, NameArray, IndexArray, Equation, BddHigh, BddLow )
-  bddsystem  \(*BddSystem;
-  char      \(*\(*NameArray;
-  bddindex   \(*IndexArray;
-  chain_list \(*Equation;
-  bddnode    \(*BddHigh;
-  bddnode    \(*BddLow;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fINameArray\fP
-The array of names.
-.TP
-\fIIndexArray\fP
-The array of indexes.
-.TP
-\fIEquation\fP
-The multiplexor command.
-.TP
-\fIBddHigh\fP
-The first \fBbdd\fP node.
-.TP
-\fIBddLow\fP
-The second \fBbdd\fP node.
-.SH DESCRIPTION
-\fBconvertbddmuxabl\fP creates the following \fBabl\fP expression
-( \fIBddHigh\fP AND \fIEquation\fP ) OR ( \fIBddLow\fP AND (NOT \fIEquation\fP ) )
-in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-The \fINameArray\fP, and \fIIndexArray\fP parameters are used
-to translate the variable nodes into atomic expressions.
-The array \fINameArray\fP is list of names.
-The array \fIIndexArray\fP does the correspondence between a \fBbdd\fP node 
-index and a slot in the \fINameArray\fP. If the \fIIndexArray\fP parameter
-is a null pointer, then the name of the \fBbdd\fP index BDD_INDEX_MIN is assumed
-to be the first slot of the \fINameArray\fP, and so on.
-.br
-.SH RETURN VALUE
-\fBconvertbddmuxabl\fP returns a pointer to the \fBabl\fP expression translated.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddnode    \(**BddNode1;
-   bddnode    \(**BddNode2;
-   chain_list \(**Expr;
-   char       \(**NameArray[ 2 ];
-   BddSystem = createbddsystem( 100, 1000, 100, 50000 );
-   BddNode1  = addbddvarlast( BddSystem );
-   BddNode2  = addbddvarlast( BddSystem );
-   NameArray[ 0 ] = namealloc( "i0" );
-   NameArray[ 1 ] = namealloc( "i1" );
-   Expr = convertbddmuxabl( BddSystem, NameArray, (bddindex \(**)0,
-                            createablatom( "C" ),  BddNode1, BddNode2 );
-   /* displays (i0 and C) or (i1 and (not C)) */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddsystem( (bddsystem \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1),
-.BR abl (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/convertbddnodeabl.3 b/alliance/share/man/man3/convertbddnodeabl.3
deleted file mode 100644
index ac86c7f9..00000000
--- a/alliance/share/man/man3/convertbddnodeabl.3
+++ /dev/null
@@ -1,77 +0,0 @@
-.\"   $Id: convertbddnodeabl.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)convertbddnodeabl.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH CONVERTBDDNODEABL 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-convertbddnodeabl \- converts a \fBbdd\fP node to an \fBabl\fP expression.
-
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-chain_list *convertbddnodeabl( BddSystem, NameArray, IndexArray, BddNode )
-  bddsystem \(**BddSystem;
-  char     \(**\(**NameArray;
-  bddindex  \(**IndexArray;
-  bddnode   \(**BddNode;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fINameArray\fP
-The array of names.
-.TP
-\fIIndexArray\fP
-The array of indexes.
-.TP
-\fIBddNode\fP
-The \fBbdd\fP node to convert.
-.SH DESCRIPTION
-\fBconvertbddnodeabl\fP converts the \fBbdd\fP node \fIBddNode\fP
-to an \fBabl\fP expression in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-The \fINameArray\fP, and \fIIndexArray\fP parameters are used
-to translate the variable nodes into atomic expressions.
-The array \fINameArray\fP is list of names.
-The array \fIIndexArray\fP does the correspondence between a \fBbdd\fP node 
-index and a slot in the \fINameArray\fP. If the \fIIndexArray\fP parameter
-is a null pointer, then the name of the \fBbdd\fP index BDD_INDEX_MIN is assumed
-to be the first slot of the \fINameArray\fP, and so on.
-.br
-.SH RETURN VALUE
-\fBconvertbddnodeabl\fP returns a pointer to the \fBabl\fP expression translated.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddnode    \(**BddNode;
-   chain_list \(**Expr;
-   char       \(**NameArray[ 1 ];
-   BddSystem = createbddsystem( 100, 1000, 100, 50000 );
-   BddNode   = addbddvarlast( BddSystem );
-   NameArray[ 0 ] = namealloc( "i0" );
-   Expr = convertbddnodeabl( BddSystem, NameArray, (bddindex \(**)0,  BddNode );
-   /* displays i0 */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddsystem( (bddsystem \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1),
-.BR abl (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/convertbddnodesumabl.3 b/alliance/share/man/man3/convertbddnodesumabl.3
deleted file mode 100644
index 85932c85..00000000
--- a/alliance/share/man/man3/convertbddnodesumabl.3
+++ /dev/null
@@ -1,77 +0,0 @@
-.\"   $Id: convertbddnodesumabl.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)convertbddnodesumabl.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH CONVERTBDDNODESUMABL 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-convertbddnodesumabl \- converts a \fBbdd\fP node to an \fBabl\fP expression.
-
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-chain_list *convertbddnodesumabl( BddSystem, NameArray, IndexArray, BddNode )
-  bddsystem \(**BddSystem;
-  char     \(**\(**NameArray;
-  bddindex  \(**IndexArray;
-  bddnode   \(**BddNode;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fINameArray\fP
-The array of names.
-.TP
-\fIIndexArray\fP
-The array of indexes.
-.TP
-\fIBddNode\fP
-The \fBbdd\fP node to convert.
-.SH DESCRIPTION
-\fBconvertbddnodesumabl\fP converts the \fBbdd\fP node
-to a non optimal \fBabl\fP expression in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-The \fINameArray\fP, and \fIIndexArray\fP parameters are used
-to translate the variable nodes into atomic expressions.
-The array \fINameArray\fP is list of names.
-The array \fIIndexArray\fP does the correspondence between a \fBbdd\fP node 
-index and a slot in the \fINameArray\fP. If the \fIIndexArray\fP parameter
-is a null pointer, then the name of the \fBbdd\fP index BDD_INDEX_MIN is assumed
-to be the first slot of the \fINameArray\fP, and so on.
-.br
-.SH RETURN VALUE
-\fBconvertbddnodesumabl\fP returns a pointer to the \fBabl\fP expression translated.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddnode    \(**BddNode;
-   chain_list \(**Expr;
-   char       \(**NameArray[ 1 ];
-   BddSystem = createbddsystem( 100, 1000, 100, 50000 );
-   BddNode   = addbddvarlast( BddSystem );
-   NameArray[ 0 ] = namealloc( "i0" );
-   Expr = convertbddnodesumabl( BddSystem, NameArray, (bddindex \(**)0,  BddNode );
-   /* displays i0 */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddsystem( (bddsystem \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1),
-.BR abl (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/copyExpr.3 b/alliance/share/man/man3/copyExpr.3
deleted file mode 100644
index e2a85019..00000000
--- a/alliance/share/man/man3/copyExpr.3
+++ /dev/null
@@ -1,50 +0,0 @@
-.\"   $Id: copyExpr.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)copyExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH COPYEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBcopyExpr\fP \- copies an expression 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-chain_list *copyExpr(expr)
-chain_list *expr;
-.fi
-.SH PARAMETER
-.TP 20
-\fIexpr\fP
-expression to copy
-.SH DESCRIPTION
-\fBcopyExpr()\fP creates a new ABL wich is strictly equal to \fIexpr\fP.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr1,*expr2; 
-expr1 = createExpr(OR);
-addQExpr(expr1,createAtom("a"));
-addQExpr(expr1,createAtom("b"));
-expr2 = copyExpr(expr1);
-displayExpr(expr1);
-displayExpr(expr2);
-/* it will display
-(OR a b)
-(OR a b)
-*/
-freeExpr(expr1);
-freeExpr(expr2);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR substExpr (3),
-.BR substPhyExpr (3),
-.BR flatArityExpr (3),
-.BR flatPolarityExpr (3),
-.BR maxExpr (3),
-.BR minExpr (3),
-.BR sortExpr (3),
-.BR normExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/cpOrderCct.3 b/alliance/share/man/man3/cpOrderCct.3
deleted file mode 100644
index 30cb239b..00000000
--- a/alliance/share/man/man3/cpOrderCct.3
+++ /dev/null
@@ -1,68 +0,0 @@
-.\"   $Id: cpOrderCct.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)cpOrderCct.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH CPORDERCCT 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBcpOrderCct\fP \- copies the association order of the inputs with the indexes in another circuit
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-void cpOrderCct(pC1,pC2)
-pCircuit pC1;
-pCircuit pC2;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIpC1\fP
-circuit from which the order is copied
-.TP 20
-\fIpC2\fP
-circuit that recieves the new order 
-.SH DESCRIPTION
-\fBcpOrderCct()\fP copies the association order of \fIpC1\fP in \fIpC2\fP. 
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-pCircuit pC;
-pCircuit pCp;
-
-displayBdd(SMALL_BDD);
-pC = initializeCct("circuit 1",10,10);
-pCp = initializeCct("circuit 1p",10,10);
-
-addInputCct(pC,"a");
-addInputCct(pC,"b");
-
-cpOrderCct(pC,pCp)
-
-displayCct(pC,1)
-displayCct(pCp,1)
-
-/* it will display 
-************* DISPLAY circuit 1 **********
-INPUT = a	INDEX = 2
-INPUT = b	INDEX = 3
---------- NUMBER OF INPUTS = 2
---------- NUMBER OF OUTPUTS = 0
-******************************************
-************* DISPLAY circuit 1p **********
-INPUT = a	INDEX = 2
-INPUT = b	INDEX = 3
---------- NUMBER OF INPUTS = 2
---------- NUMBER OF OUTPUTS = 0
-******************************************
-*/
-
-destroyCct(pC);
-destroyCct(pCp);
-destroyBdd(1);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR addInputCct (3),
-.BR searchInputCct (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/createAtom.3 b/alliance/share/man/man3/createAtom.3
deleted file mode 100644
index e05c149b..00000000
--- a/alliance/share/man/man3/createAtom.3
+++ /dev/null
@@ -1,42 +0,0 @@
-.\"   $Id: createAtom.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)createAtom.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH CREATEATOM 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBcreateAtom\fP \- creates an atomic expression.
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-chain_list *createAtom(name)
-char *name;
-.fi
-.SH PARAMETER
-.TP 20
-\fIname\fP
-Name of the atom.
-.SH DESCRIPTION
-\fBcreateAtom()\fP creates an atomic expression. This function uses the \fBnamealloc()\fP function to speed up the treatements and minimize the memory space.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *atom; 
-atom = createAtom("var1");
-displayExpr(atom);
-/* it will display
-var1
-*/
-freeExpr(atom);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR createExpr (3),
-.BR notExpr (3),
-.BR createBinExpr (3),
-.BR addQExpr (3),
-.BR addHExpr(3),
-.BR freeExpr(3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/createBinExpr.3 b/alliance/share/man/man3/createBinExpr.3
deleted file mode 100644
index 64282895..00000000
--- a/alliance/share/man/man3/createBinExpr.3
+++ /dev/null
@@ -1,61 +0,0 @@
-.\"   $Id: createBinExpr.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)createBinExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH CREATEBINEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBcreateBinExpr\fP \- creates a binary operator expression with an eventual merging of the operators.
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-chain_list *createBinExpr(oper,expr1,expr2)
-short oper;
-chain_list *expr1,*expr2;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIoper\fP
-Operator number (#define OR,AN,XOR,NAND,NOR...).
-.TP 20
-\fIexpr1\fP
-first expression.
-.TP 20
-\fIexpr2\fP
-second expression.
-.SH DESCRIPTION
-\fBcreateBinExpr()\fP creates the head of an expression that has got \fIoper\fP as operator and \fIexpr1\fP and \fIexpr2\fP as arguments. If \fIexpr1\fP or \fIexpr2\fP have already \fIoper\fP as operator, \fIoper\fP is merged in the expression that the function returns.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr; 
-chain_list *expr1,*expr2;
-
-expr1 = createExpr(OR);
-addQExpr(expr1,createAtom("var1"));
-addQExpr(expr1,createAtom("var2"));
-expr2 = notExpr(createAtom("var3"));
-expr = createBinExpr(OR,expr1,expr2);
-displayExpr(expr);
-
-/* it will display
-(OR var1 var2 (NOT var 3))
-*/
-freeExpr(expr);		/* don't free expr1 or expr2 ! */
-
-.SH ERROR
-"createBinExpr : error - bad operator"
-.br
-The operator number must be included between \fIMIN_OPER\fP and \fIMAX_OPER\fP and must be different from NOT. 
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR createAtom (3),
-.BR notExpr (3),
-.BR createExpr (3),
-.BR addQExpr (3),
-.BR addHExpr(3),
-.BR freeExpr(3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/createExpr.3 b/alliance/share/man/man3/createExpr.3
deleted file mode 100644
index 42729a73..00000000
--- a/alliance/share/man/man3/createExpr.3
+++ /dev/null
@@ -1,46 +0,0 @@
-.\"   $Id: createExpr.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)createExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH CREATEEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBcreateExpr\fP \- creates the head of an operator expression.
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-chain_list *createExpr(oper)
-short oper;
-.fi
-.SH PARAMETER
-.TP 20
-\fIoper\fP
-Operator number (OR,AND,XOR,NAND,NOR...).
-.SH DESCRIPTION
-\fBcreateExpr()\fP creates the head of an operator expression (arity = 0). After that it's possible to add arguments with the \fBaddHExpr()\fP or \fBaddQExpr()\fP functions.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr; 
-expr = createExpr(OR);
-displayExpr(expr);
-/* it will display
-(OR)
-*/
-freeExpr(expr);
-.fi
-.SH ERROR
-"createExpr : error - unknown operator"
-.br
-The operator number must be included between \fIMIN_OPER\fP and \fIMAX_OPER\fP.
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR createAtom (3),
-.BR notExpr (3),
-.BR createBinExpr (3),
-.BR addQExpr (3),
-.BR addHExpr (3),
-.BR freeExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/createNodeTermBdd.3 b/alliance/share/man/man3/createNodeTermBdd.3
deleted file mode 100644
index 3b032741..00000000
--- a/alliance/share/man/man3/createNodeTermBdd.3
+++ /dev/null
@@ -1,50 +0,0 @@
-.\"   $Id: createNodeTermBdd.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)createNodeTermBdd.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH CREATENODETERMBDD 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBcreateNodeTermBdd\fP \- creates a terminal node of variable.
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-pNode createNodeTermBdd(index)
-short index;
-.fi
-.SH PARAMETER
-.TP 20
-\fIindex\fP
-associated index 
-.SH DESCRIPTION
-\fBcreateNodeTermBdd()\fP creates a terminal node corresponding to \fIindex\fP. Because of reduction table, this function always returns the same \fIpNode\fP for a given \fIindex\fP. 0 and 1 \fIindex\fP are reserved to the \fIzero\fP and \fIone\fP nodes.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-pNode nodeA;
-
-initializeBdd(SMALL_BDD);
-nodeA = createNodeTermBdd(3);
-displayBdd(nodeA,1);
-
-/* it will display 
-@nodeA   INDEX = 2   LOW = ZERO   HIGH = ONE
-*/
-nodeA = createNodeTermBdd(3);	/* nodeA doesn't change */
-	
-destroyBdd(1);
-.fi
-.SH ERROR
-"createNodeTermBdd : error - index < 2"
-.br
-\fIindex\fP must be strictly higher than 1.
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR applyBinBdd (3),
-.BR applyBdd (3),
-.BR addListBdd (3),
-.BR displayBdd (3),
-.BR notBdd (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/createTH.3 b/alliance/share/man/man3/createTH.3
deleted file mode 100644
index a453e476..00000000
--- a/alliance/share/man/man3/createTH.3
+++ /dev/null
@@ -1,40 +0,0 @@
-.\"   $Id: createTH.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)createTH.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH CREATETH 3 "October 1, 1997" "ASIM/LIP6" "Hash table functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBcreateTH\fP \- create a hash table
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-pTH createTH(len)
-int len;
-.fi
-.SH PARAMETER
-.TP 20
-\fIlen\fP
-Length of the hash table.
-.SH DESCRIPTION
-\fBcreateTH()\fP creates a hash table in memory. \fIlen\fP is an estimate of the maximum number of entries that the table will contain. This number may be adjusted by a dynamic reallocation.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-pTH mytable; 
-mytable = createTH(100);      	/* easy to make */
-.fi
-.SH ERROR
-"createTH : error length <= 0"
-.br
-Hash table can't be created with length <= 0.
-.SH SEE ALSO
-.BR log (1),
-.BR tsh (1),
-.BR destroyTH (3),
-.BR searchTH (3),
-.BR addTH (3),
-.BR deleteTH (3),
-.BR displayTH(3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/createablatom.3 b/alliance/share/man/man3/createablatom.3
deleted file mode 100644
index e5ee8d35..00000000
--- a/alliance/share/man/man3/createablatom.3
+++ /dev/null
@@ -1,56 +0,0 @@
-.\"   $Id: createablatom.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)createablatom.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH CREATEABLATOM 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-createablatom \- creates an atomic expression.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-chain_list \(**createablatom( Atom )
-  char \(**Atom;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIAtom\fP
-Name of the atom.
-.SH DESCRIPTION
-\fBcreateablatom\fP creates an atomic expression with the name \fIAtom\fP.
-This function uses \fInamealloc\fP with \fIAtom\fP as parameter.
-.br
-.SH RETURN VALUE
-\fBcreateablatom\fP returns a pointer to the new atomic expression.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-   chain_list \(**ExprA;
-   chain_list \(**ExprB;
-   chain_list \(**ExprAorB;
-   ExprA = createablatom( "a" );
-   ExprB = createablatom( "b" );
-   ExprAorB = createablbinexpr( ABL_OR, ExprA, ExprB );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1),
-.BR createabloper(3),
-.BR createablnotexpr(3),
-.BR createablbinexpr(3),
-.BR createablunaryexpr(3),
-.BR createablxorbinexpr(3),
-.BR addablhexpr(3),
-.BR addablqexpr(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/createablbinexpr.3 b/alliance/share/man/man3/createablbinexpr.3
deleted file mode 100644
index d7de36eb..00000000
--- a/alliance/share/man/man3/createablbinexpr.3
+++ /dev/null
@@ -1,76 +0,0 @@
-.\"   $Id: createablbinexpr.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)createablbinexpr.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH CREATEABLBINEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-createablbinexpr \- creates a binary operator expression.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-chain_list \(**createablbinexpr( Oper, Expr1, Expr2 )
-  long        Oper;
-  chain_list \(**Expr1;
-  chain_list \(**Expr2;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIOper\fP
-The operator number.
-.TP
-\fIExpr1\fP
-The first expression.
-.TP
-\fIExpr2\fP
-The second expression.
-.SH DESCRIPTION
-\fBcreateablbinexpr\fP creates the binary operator expression 
-\fIExpr1\fP \fIOperator\fP \fIExpr2\fP.  If the operator of \fIExpr1\fP 
-and/or \fIExpr2\fP, and \fIOperator\fP are identicals \fBcreateablbinexpr\fP
-merges eventually the sub-expressions.  The expression pointers \fIExpr1\fP
-and \fIExpr2\fP MUSTN'T be used after the call to this function.
-.br
-.SH RETURN VALUE
-\fBcreateablbinexpr\fP returns a pointer to the new operator expression.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"ablcreate: bad operator xx !",
-.ft R
-.RS
-\fIOperator\fP must be defined and must be a binary operator.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-   chain_list \(**ExprA;
-   chain_list \(**ExprB;
-   chain_list \(**ExprAorB;
-   ExprA = createablatom( "a" );
-   ExprB = createablatom( "b" );
-   ExprAorB  = createablbinexpr( ABL_OR, ExprA, ExprB );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1)
-.BR createablatom(3),
-.BR createabloper(3),
-.BR createablxorbinexpr(3),
-.BR createablunaryexpr(3),
-.BR createablnotexpr(3),
-.BR addablhexpr(3),
-.BR addablqexpr(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/createablnotexpr.3 b/alliance/share/man/man3/createablnotexpr.3
deleted file mode 100644
index 6108bc04..00000000
--- a/alliance/share/man/man3/createablnotexpr.3
+++ /dev/null
@@ -1,55 +0,0 @@
-.\"   $Id: createablnotexpr.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)createablnotexpr.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH CREATEABLNOTEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-createablnotexpr \- complements an expression.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-chain_list \(**createablnotexpr( Expr )
-  chain_list \(**Expr;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIExpr\fP
-The expression to be complemented.
-.SH DESCRIPTION
-\fBcreateablnotexpr\fP complements the expression \fIExpr\fP and
-eventually does a simplification. The expression pointer \fIExpr\fP
-MUSTN'T be used after the call to this function.
-.br
-.SH RETURN VALUE
-\fBcreateablnotexpr\fP returns the new complemented expression.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-   chain_list \(**ExprA;
-   chain_list \(**ExprNotA;
-   ExprA = createablatom( "a" );
-   ExprNotA = createablnotexpr( ExprA );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1)
-.BR createablatom(3),
-.BR createabloper(3),
-.BR createablbinexpr(3),
-.BR createablunaryexpr(3),
-.BR createablxorbinexpr(3),
-.BR addablhexpr(3),
-.BR addablqexpr(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/createabloper.3 b/alliance/share/man/man3/createabloper.3
deleted file mode 100644
index 0584052f..00000000
--- a/alliance/share/man/man3/createabloper.3
+++ /dev/null
@@ -1,69 +0,0 @@
-.\"   $Id: createabloper.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)createabloper.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH CREATEABLOPER 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-createabloper \- creates the head of an operator expression.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
- chain_list \(**createabloper( Oper )
-  long Oper;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIOper\fP
-The operator number.
-.SH DESCRIPTION
-\fBcreateabloper\fP creates the head of an operator expression.
-Arguments can be added to this expression with the \fIaddablhexpr\fP
-and \fIaddablqexpr\fP functions. 
-\fIOperator\fP can take the following values ABL_AND, ABL_OR,
-ABL_AND, ABL_XOR, ABL_NOT, ABL_NOR, ABL_NAND, ABL_NXOR, 
-ABL_STABLE, ABL_AF, ABL_AG, ABL_AX, ABL_AU, ABL_EF, ABL_EG, ABL_EX, ABL_EU.
-.br
-.SH RETURN VALUE
-\fBcreateabloper\fP returns a pointer to the new operator expression.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"ablcreate: bad operator xx !",
-.ft R
-.RS
-The operator number must be defined.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-  chain_list \(**Expr;
-  Expr = createabloper( ABL_OR );
-  addablhexpr( Expr, createablatom( "a" ) );
-  addablhexpr( Expr, createablatom( "b" ) );
-  /* displays (a or b) */
-  viewablexpr( Expr, ABL_VIEW_VHDL );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1)
-.BR createablatom(3),
-.BR createablnotexpr(3),
-.BR createablbinexpr(3),
-.BR createablunaryexpr(3),
-.BR createablxorbinexpr(3),
-.BR addablhexpr(3),
-.BR addablqexpr(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/createablunaryexpr.3 b/alliance/share/man/man3/createablunaryexpr.3
deleted file mode 100644
index 191c1d82..00000000
--- a/alliance/share/man/man3/createablunaryexpr.3
+++ /dev/null
@@ -1,74 +0,0 @@
-.\"   $Id: createablunaryexpr.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)createablunaryexpr.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH CREATEABLUNARYEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-createablunaryexpr \- creates an unary operator expression.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-chain_list \(**createablunaryexpr( Oper, Expr )
-  long        Oper;
-  chain_list \(**Expr;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIOper\fP
-The unary operator number.
-.TP
-\fIExpr\fP
-Expression.
-.SH DESCRIPTION
-\fBcreateablunaryexpr\fP creates the unary operator expression
-\fIOperator\fP \fIExpr\fP. \fBcreateablbinexpr\fP combines
-eventualy the operator of \fIExpr\fP with \fIOperator\fP.
-The expression pointer \fIExpr\fP MUSTN'T be used after 
-the call to this function.
-.br
-.SH RETURN VALUE
-\fBcreateablunaryexpr\fP returns a pointer to the new operator expression.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"ablcreate: bad operator xx !",
-.ft R
-.RS
-\fIOperator\fP must be defined and must be a unary operator.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-   chain_list \(**ExprA;
-   chain_list \(**ExprB;
-   chain_list \(**ExprAorB;
-   chain_list \(**ExprAnorB;
-   ExprA = createablatom( "a" );
-   ExprB = createablatom( "b" );
-   ExprAorB  = createablbinexpr( ABL_OR, ExprA, ExprB );
-   ExprAnorB = createablunaryexpr( ABL_NOT, ExprAorB );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1)
-.BR createablatom(3),
-.BR createabloper(3),
-.BR createablnotexpr(3),
-.BR createablbinexpr(3),
-.BR createablxorbinexpr(3),
-.BR addablhexpr(3),
-.BR addablqexpr(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/createablxorbinexpr.3 b/alliance/share/man/man3/createablxorbinexpr.3
deleted file mode 100644
index f1df1eb6..00000000
--- a/alliance/share/man/man3/createablxorbinexpr.3
+++ /dev/null
@@ -1,79 +0,0 @@
-.\"   $Id: createablxorbinexpr.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)createablxorbinexpr.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH CREATEABLXORBINEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-createablxorbinexpr \- creates an 'xor' or 'xnor' operator expression.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-chain_list *createablxorbinexpr( Oper, Expr1, Expr2 )
-  long        Oper;
-  chain_list \(**Expr1;
-  chain_list \(**Expr2;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIOper\fP
-Operator ABL_XOR or ABL_NXOR.
-.TP
-\fIExpr1\fP
-First expression.
-.TP
-\fIExpr2\fP
-Second expression.
-.SH DESCRIPTION
-\fBcreateablxorbinexpr\fP creates a binary 'xor' or 'xnor'
-operator expression with the 'and', 'or' form.  \fBcreateablbinexpr\fP
-simplifies eventually the sub-expressions.
-The expression pointers \fIExpr1\fP and \fIExpr2\fP MUSTN'T 
-be used after the call to this function.
-.br
-.SH RETURN VALUE
-\fBcreateablxorbinexpr\fP returns a pointer to the new operator expression.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"ablcreate: bad operator xx !",
-.ft R
-.RS
-\fIOperator\fP must be ABL_XOR or ABL_NXOR.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-   chain_list \(**ExprA;
-   chain_list \(**ExprB;
-   chain_list \(**ExprAxorB;
-   ExprA = createablatom( "a" );
-   ExprB = createablatom( "b" );
-   ExprAxorB  = createablxorbinexpr( ABL_XOR, ExprA, ExprB );
-   /* displays (a and (not b) or (b and (not a)) */
-   viewablexpr( ExprAxorB, ABL_VIEW_VHDL );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1)
-.BR abl (1)
-.BR createablatom(3),
-.BR createabloper(3),
-.BR createablbinexpr(3),
-.BR createablunaryexpr(3),
-.BR createablnotexpr(3),
-.BR addablhexpr(3),
-.BR addablqexpr(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/createauth2table.3 b/alliance/share/man/man3/createauth2table.3
deleted file mode 100644
index 0c035e44..00000000
--- a/alliance/share/man/man3/createauth2table.3
+++ /dev/null
@@ -1,61 +0,0 @@
-.\"   $Id: createauth2table.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)createauth2table.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH CREATEAUTH2TABLE 3 "October 1, 1997" "ASIM/LIP6" "AUT FUNCTIONS"
-.SH NAME
-createauth2table \- creates an hash table with two keys.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-auth2table \(**createauth2table( Length )
-  long Length;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fILength\fP
-Initial size of the hash table.
-.SH DESCRIPTION
-\fBcreateauth2table\fP creates an hash table with a prime number of entries.
-The number of entrie is the closest known prime number from \fILength\fP.
-.br
-.SH RETURN VALUE
-\fBcreateauth2table\fP returns a pointer to the new hash table.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"authash2: hash table size xxx error !"
-.ft R
-.RS
-The initial \fILength\fP of the hash table must be a positive value.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-   auth2table \(**HashTable;
-   HashTable = createauth2table( 1000 ); 
-   ...
-   destroyauth2table( HashTable );
-.ft R
-.fi
-.SH SEE ALSO
-.BR aut (1)
-.BR destroyauth2table(3),
-.BR resetauth2table(3),
-.BR addauth2elem(3),
-.BR searchauth2elem(3),
-.BR delauth2elem(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/createauthtable.3 b/alliance/share/man/man3/createauthtable.3
deleted file mode 100644
index e046c3ca..00000000
--- a/alliance/share/man/man3/createauthtable.3
+++ /dev/null
@@ -1,61 +0,0 @@
-.\"   $Id: createauthtable.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)createauthtable.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH CREATEAUTHTABLE 3 "October 1, 1997" "ASIM/LIP6" "AUT FUNCTIONS"
-.SH NAME
-createauthtable \- creates a simple hash table.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-authtable \(**createauthtable( Length )
-  long Length;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fILength\fP
-Initial size of the hash table.
-.SH DESCRIPTION
-\fBcreateauthtable\fP creates an hash table with a prime number of entries.
-The number of entrie is the closest known prime number from \fILength\fP.
-.br
-.SH RETURN VALUE
-\fBcreateauthtable\fP returns a pointer to the new hash table.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"authash: hash table size xxx error !"
-.ft R
-.RS
-The initial \fILength\fP of the hash table must be a positive value.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-   authtable \(**HashTable;
-   HashTable = createauthtable( 1000 ); 
-   ...
-   destroyauthtable( HashTable );
-.ft R
-.fi
-.SH SEE ALSO
-.BR aut (1)
-.BR destroyauthtable(3),
-.BR resetauthtable(3),
-.BR addauthelem(3),
-.BR searchauthelem(3),
-.BR delauthelem(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/createbddcircuit.3 b/alliance/share/man/man3/createbddcircuit.3
deleted file mode 100644
index 3bfbfeb9..00000000
--- a/alliance/share/man/man3/createbddcircuit.3
+++ /dev/null
@@ -1,66 +0,0 @@
-.\"   $Id: createbddcircuit.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)createbddcircuit.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH CREATEBDDCIRCUIT 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-createbddcircuit \- creates a \fBbdd\fP circuit.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-  bddcircuit \(**createbddcircuit( Name, NumberIn, NumberOut, BddSystem )
-  char      \(**Name;
-  long       NumberIn;
-  long       NumberOut;
-  bddsystem \(**BddSystem;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIName\fP
-Name of the \fBbdd\fP circuit.
-.TP
-\fINumberIn\fP
-Number of inputs.
-.TP
-\fINumberOut\fP
-Number of outputs.
-.TP
-\fIBddSystem\fP
-The \fBbdd\fP system to work on.
-.SH DESCRIPTION
-\fBcreatebddcircuit\fP creates a \fBbdd\fP circuit with the name \fIName\fP,
-with \fINumberIn\fP inputs, and \fINumberOut\fP outputs.
-This \fBbdd\fP circuit will use the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBcreatebddcircuit\fP returns a pointer to the \fBbdd\fP circuit created.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   ...
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1),
-.BR resetbddcircuit(3),
-.BR destroybddcircuit(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/createbddsystem.3 b/alliance/share/man/man3/createbddsystem.3
deleted file mode 100644
index 11459c3c..00000000
--- a/alliance/share/man/man3/createbddsystem.3
+++ /dev/null
@@ -1,89 +0,0 @@
-.\"   $Id: createbddsystem.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)createbddsystem.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH CREATEBDDSYSTEM 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-createbddsystem \- creates a \fBbdd\fP system.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddsystem \(**createbddsystem( ModelVar, ModelOper, MaxVar, MaxNode  )
-  long   ModelVar;
-  long   ModelOper;
-  long   MaxVar;
-  long   MaxNode;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIModelVar\fP
-Initial size of the hash table uses for a variable.
-.TP
-\fIModelOper\fP
-Size of the hash table uses as a cache.
-.TP
-\fIMaxVar\fP
-Initial maximum number of variables.
-.TP
-\fIMaxNode\fP
-Maximum nodes allowed.
-.SH DESCRIPTION
-\fBcreatebddsystem\fP creates and initializes a \fBbdd\fP system. 
-.br
-.SH RETURN VALUE
-\fBcreatebddsystem\fP returns a pointer to the \fBbdd\fP system created.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"system model variable xxx error !"
-.ft R
-.RS
-The \fIModelVar\fP parameter must be a positive value.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"system model oper xxx error !"
-.ft R
-.RS
-The \fIModelOper\fP parameter must be a positive value.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"variable xxx out of range error !"
-.ft R
-.RS
-The \fIMaxVar\fP parameter must be less than \fIBDD_MAX_VAR\fP.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem \(**BddSystem;
-   BddSystem = createbddsystem( 100, 1000, 100, 50000 );
-   ...
-   destroybddsystem( BddSystem );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-.BR resetbddsytem(3),
-.BR destroybddsytem(3).
-.
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/decbddrefext.3 b/alliance/share/man/man3/decbddrefext.3
deleted file mode 100644
index a584492e..00000000
--- a/alliance/share/man/man3/decbddrefext.3
+++ /dev/null
@@ -1,70 +0,0 @@
-.\"   $Id: decbddrefext.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)decbddrefext.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH DECBDDREFEXT 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-decbddrefext \- decrements the external reference of a \fBbdd\fP node.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddnode \(**decbddrefext( BddNode )
-  bddnode \(**BddNode;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddNode\fP
-The \fBbdd\fP node.
-.SH DESCRIPTION
-\fBdecbddrefext\fP decrements the number of external reference
-of the \fBbdd\fP node \fIBddNode\fP.
-.br
-.SH RETURN VALUE
-\fBdecbddrefext\fP returns the \fIBddNode\fP pointer.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"negative reference, index xxx error !"
-.ft R
-.RS
-The \fIBddNode\fP must have a postive number of external reference.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   chain_list \(**Expr;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   BddNode = addbddcircuitin( (bddcircuit \(**)0, "i0", 0, BDD_IN_MODE_FIRST );
-   BddNode = addbddnode( (bddsystem \(**)0, BddNode->INDEX, BddNode->LOW, BddNode->HIGH );
-   Expr = convertbddcircuitabl( (bddcircuit \(**)0, BddNode );
-   decbddrefext( BddNode );
-   /* displays Node VAR: 0  INDEX: 2  MARK: 0  REF_EXT: 0  REF_INT: 0 */
-   viewbddnode( (bddsystem \(**)0, BddNode );
-   /* displays (not i0) */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/decbddrefint.3 b/alliance/share/man/man3/decbddrefint.3
deleted file mode 100644
index 7e9dee8e..00000000
--- a/alliance/share/man/man3/decbddrefint.3
+++ /dev/null
@@ -1,71 +0,0 @@
-.\"   $Id: decbddrefint.3,v 1.1 1999/05/31 17:30:19 alliance Exp $
-.\" @(#)decbddrefint.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH DECBDDREFINT 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-decbddrefint \- decrements the internal reference of a \fBbdd\fP node.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddnode \(**decbddrefint( BddNode )
-  bddnode \(**BddNode;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddNode\fP
-The \fBbdd\fP node.
-.SH DESCRIPTION
-\fBdecbddrefint\fP decrements the number of internal reference
-of the \fBbdd\fP node \fIBddNode\fP.
-.br
-.SH RETURN VALUE
-\fBdecbddrefint\fP returns the \fIBddNode\fP pointer.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"negative reference, index xxx error !"
-.ft R
-.RS
-The \fIBddNode\fP must have a postive number of internal reference.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   chain_list \(**Expr;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   BddNode = addbddcircuitin( (bddcircuit \(**)0, "i0", 0, BDD_IN_MODE_FIRST );
-   BddNode = addbddnode( (bddsystem \(**)0, BddNode->INDEX, BddNode->LOW, BddNode->HIGH );
-   Expr = convertbddcircuitabl( (bddcircuit \(**)0, BddNode );
-   incbddrefint( BddNode );
-   decbddrefint( BddNode );
-   /* displays Node VAR: 0  INDEX: 2  MARK: 0  REF_EXT: 1  REF_INT: 0 */
-   viewbddnode( (bddsystem \(**)0, BddNode );
-   /* displays (not i0) */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/defab.3 b/alliance/share/man/man3/defab.3
deleted file mode 100644
index 29ee5c91..00000000
--- a/alliance/share/man/man3/defab.3
+++ /dev/null
@@ -1,59 +0,0 @@
-.\"   $Id: defab.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)defab.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-defab
-.XE \}
-.TH DEFAB 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL FUNCTIONS"
-.SH NAME
-defab \- defines the \fIabutment box\fP of a \fBphfig\fP
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-void defab(ptfig, x1, y1, x2, y2)
-phfig_list \(**ptfig;
-long x1, x2, y1, y2;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptfig\fP
-Pointer to a \fBphfig\fP
-.TP
-\fIx1, y1, x2, y2\fP
-Coordinates of the \fIabutment box\fP
-.SH DESCRIPTION
-\fBdefab\fP redefines the \fIabutment box\fP of the figure pointed to by
-\fIptfig\fP.
-It overwrite any existing value in the \fIXAB1\fP, \fIYAB1\fP, \fIXAB2\fP and
-\fIYAB2\fP by the given arguments.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-void add_half_rules(fig)
-phfig_list \(**fig;
-{
-	defab(fig, fig\->XAB1 + HALF_RULE, fig\->YAB1 + HALF_RULE,
-		fig\->XAB2 + HALF_RULE, fig\->YAB2 + HALF_RULE);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR phfig (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/delablexpr.3 b/alliance/share/man/man3/delablexpr.3
deleted file mode 100644
index 061e4790..00000000
--- a/alliance/share/man/man3/delablexpr.3
+++ /dev/null
@@ -1,54 +0,0 @@
-.\"   $Id: delablexpr.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)delablexpr.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH DELABLEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-delablexpr \- deletes an expression. 
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-  void delablexpr( Expr )
-   chain_list \(**Expr;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIExpr\fP
-Expression to delete.
-.SH DESCRIPTION
-\fBdelablexpr\fP deletes the expression \fIExpr\fP.
-.br
-.SH RETURN VALUE
-\fBdelablexpr\fP returns nothing.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-   chain_list \(**ExprA;
-   chain_list \(**ExprB;
-   chain_list \(**ExprAorB;
-   ExprA = createablatom( "a" );
-   ExprB = createablatom( "b" );
-   ExprAorB  = createablbinexpr( ABL_OR, ExprA, ExprB );
-   ...
-   delablexpr( ExprAorB );
-   ExprAorB = (chain_list \(**)0;
-   ...
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1)
-.BR freeablexpr(3).
-.BR delablexprnum(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/delablexprnum.3 b/alliance/share/man/man3/delablexprnum.3
deleted file mode 100644
index c928cb0f..00000000
--- a/alliance/share/man/man3/delablexprnum.3
+++ /dev/null
@@ -1,61 +0,0 @@
-.\"   $Id: delablexprnum.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)delablexprnum.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH DELABLEXPRNUM 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-delablexprnum \- deletes an operand in an expression.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-void delablexprnum( Expr, Number )
-  chain_list \(**Expr;
-  int         Number;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIExpr\fP
-Expression where to delete an operand.
-.TP
-\fIsecond_param\fP
-Operand number.
-.SH DESCRIPTION
-\fBdelablexprnum\fP deletes the operand \fINumber\fP + 1 in \fIExpr\fP.
-.br
-.SH RETURN VALUE
-\fBdelablexprnum\fP returns nothing.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-   chain_list \(**ExprA;
-   chain_list \(**ExprB;
-   chain_list \(**ExprC;
-   chain_list \(**ExprAorBorC;
-   ExprA = createablatom( "a" );
-   ExprB = createablatom( "b" );
-   ExprC = createablatom( "c" );
-   ExprAorBorC = createablbinexpr( ABL_OR, ExprA, ExprB );
-   ExprAorBorC = createablbinexpr( ABL_OR, ExprAorBorC, ExprC );
-   ...
-   delablexprnum( ExprAorBorC, 2 );
-   /* displays (a or b) */
-   viewablexpr( ExprAorBorC, ABL_VIEW_VHDL );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1),
-.BR freeablexpr(3),
-.BR delablexpr(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/delauth2elem.3 b/alliance/share/man/man3/delauth2elem.3
deleted file mode 100644
index 7e1f38e5..00000000
--- a/alliance/share/man/man3/delauth2elem.3
+++ /dev/null
@@ -1,88 +0,0 @@
-.\"   $Id: delauth2elem.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)delauth2elem.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH DELAUTH2ELEM 3 "October 1, 1997" "ASIM/LIP6" "AUT FUNCTIONS"
-.SH NAME
-delauth2elem \- deletes an element in the hash table.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-int delauth2elem( HashTable, Key1, Key2 )
-  auth2table \(**HashTable;
-  char      \(**Key1;
-  char      \(**Key2;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIHashTable\fP
-Pointer to the hash table where to delete an element.
-.TP
-\fIKey1\fP
-The first hash element key.
-.TP
-\fIKey2\fP
-The second hash element key.
-.SH DESCRIPTION
-\fBdelauth2elem\fP deletes the element associated to the tow keys \fIKey1\fP
-and \fIKey2\fP in the hash table.
-.br
-.SH RETURN VALUE
-if the element can be found \fBdelauth2elem\fP returns 1 and 0 otherwise.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"auth2ash: hash key 0 error !"
-.ft R
-.RS
-The two keys \fIKey1\fP and \fIKey2\fP must be valid pointers.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-   auth2table \(**HashTable;
-   void add_dictionary( Name1, Name2 )
-     \(** Name1;
-     \(** Name2;
-   {
-     addauth2elem( HashTable,
-                   namealloc( Name1 ),
-                   namealloc( Name2 ), 0 );
-   }
-   void del_dictionary( Name1, Name2 )
-     \(** Name1;
-     \(** Name2;
-   {
-     delauth2elem( HashTable,
-                   namealloc( Name1 ),
-                   namealloc( Name2 ) );
-   }
-   ...
-   HashTable = createauth2table( 1000 );
-   add_dictionary( "hello", "world" );
-   ...
-   del_dictionary( "hello", "world" );
-   destroyauth2table( HashTable );
-.ft R
-.fi
-.SH SEE ALSO
-.BR aut (1)
-.BR destroyauth2table(3),
-.BR resetauth2table(3),
-.BR createauth2table(3),
-.BR searchauth2elem(3),
-.BR addauth2elem(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/delauthelem.3 b/alliance/share/man/man3/delauthelem.3
deleted file mode 100644
index 1765c2a7..00000000
--- a/alliance/share/man/man3/delauthelem.3
+++ /dev/null
@@ -1,79 +0,0 @@
-.\"   $Id: delauthelem.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)delauthelem.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH DELAUTHELEM 3 "October 1, 1997" "ASIM/LIP6" "AUT FUNCTIONS"
-.SH NAME
-delauthelem \- deletes an element in the hash table.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-int delauthelem( HashTable, Key )
-  authtable \(**HashTable;
-  char      \(**Key;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIHashTable\fP
-Pointer to the hash table where to delete an element.
-.TP
-\fIKey\fP
-The hash element key.
-.SH DESCRIPTION
-\fBdelauthelem\fP deletes the element associated to the key \fIKey\fP
-in the hash table.
-.br
-.SH RETURN VALUE
-if the element can be found \fBdelauthelem\fP returns 1 and 0 otherwise.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"authash: hash key 0 error !"
-.ft R
-.RS
-The key \fIKey\fP of the hash table must be a valid pointer.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-   authtable \(**HashTable;
-   void add_dictionary( Name )
-     \(** Name;
-   {
-     addauthelem( HashTable, namealloc( Name ), 0 );
-   }
-   void del_dictionary( Name )
-     \(** Name;
-   {
-     delauthelem( HashTable, namealloc( Name ) );
-   }
-   ...
-   HashTable = createauthtable( 1000 );
-   add_dictionary( "hello" );
-   ...
-   del_dictionary( "hello" );
-   ...
-   destroyauthtable( HashTable );
-.ft R
-.fi
-.SH SEE ALSO
-.BR aut (1)
-.BR destroyauthtable(3),
-.BR resetauthtable(3),
-.BR createauthtable(3),
-.BR searchauthelem(3),
-.BR addauthelem(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/delbddassoc.3 b/alliance/share/man/man3/delbddassoc.3
deleted file mode 100644
index 08f3481b..00000000
--- a/alliance/share/man/man3/delbddassoc.3
+++ /dev/null
@@ -1,82 +0,0 @@
-.\"   $Id: delbddassoc.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)delbddassoc.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH DELBDDASSOC 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-delbddassoc \- deletes a variable association.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-int delbddassoc( BddSystem, BddAssoc )
-  bddsystem  \(**BddSystem;
-  bddassoc   \(**BddAssoc;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIBddAssoc\fP
-The variable association to delete.
-.SH DESCRIPTION
-\fBdelbddassoc\fP deletes the variable association \fIBddAssoc\fP in the \fBbdd\fP system
-\fIBddSystem\fP.  If a null pointer is given, the default \fBbdd\fP system is used.
-For all the \fBbdd\fP nodes of the variable association
-\fIBddAssoc\fP, the number of external reference is decremented.
-.br
-.SH RETURN VALUE
-\fBdelbddassoc\fP returns 1 if the variable association is found, 0 otherwise.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   bddnode    \(**BddSubst;
-   bddnode    \(**BddVariable;
-   bddassoc   \(**Assoc;
-   chain_list \(**Expr;
-   bddvar         Variable;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   Expr = createablbinexpr( ABL_AND,
-                            createablatom( "i0" ),
-                            createablatom( "i1" ) );
-   BddNode = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   Expr = createablbinexpr( ABL_OR,
-                            createablatom( "i2" ),
-                            createablatom( "i3" ) );
-   BddSubst = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   BddVariable = searchbddcircuitin( (bddcircuit \(**)0, "i0" );
-   Variable = getbddvarbyindex( (bddsystem \(**)0, BddVariable->INDEX );
-   Assoc = delbddassoc( (bddsystem \(**)0 );
-   addbddnodeassoc( (bddsystem \(**)0, Assoc, Variable, BddSubst );
-   BddNode = substbddnodeassoc( (bddsystem \(**)0, BddSubst, Assoc );
-   delbddassoc( (bddsystem \(**)0, Assoc );
-   Expr = convertbddcircuitabl( BddCircuit, BddNode );
-   /* displays ((i3 or i2) and i1) */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddassoc( (bddsystem \(**)0 );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/delbddcircuitout.3 b/alliance/share/man/man3/delbddcircuitout.3
deleted file mode 100644
index 675aec55..00000000
--- a/alliance/share/man/man3/delbddcircuitout.3
+++ /dev/null
@@ -1,63 +0,0 @@
-.\"   $Id: delbddcircuitout.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)delbddcircuitout.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH DELBDDCIRCUITOUT 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-delbddcircuitout \- deletes an output in a \fBbdd\fP circuit.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-int delbddcircuitout( BddCircuit, OutputName )
-  bddcircuit \(**BddCircuit;
-  char       \(**OutputName;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddCircuit\fP
-The \fBbdd\fP circuit.
-.TP
-\fIOutputName\fP
-The name of the output to delete.
-.SH DESCRIPTION
-\fBdelbddcircuitout\fP deletes the output \fIOutputName\fP 
-in the \fBbdd\fP circuit \fIBddCircuit\fP. If a null pointer is given,
-the default \fBbdd\fP circuit is used.  If the output \fIOutputName\fP exists,
-the number of external reference of the output node
-is decremented.
-.br
-.SH RETURN VALUE
-\fBdelbddcircuitout\fP returns 1 if the output \fIOutputName\fP exist, 0 otherwise.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   ...
-   addbddcircuitout( (bddcircuit \(**)0, "Out0", BddNode );
-   ...
-   delbddcircuitout( (bddcircuit \(**)0, "Out0" );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-.BR searchbddcircuitout(3),
-.BR addbddcircuitout(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/delbddnode.3 b/alliance/share/man/man3/delbddnode.3
deleted file mode 100644
index 2c80683f..00000000
--- a/alliance/share/man/man3/delbddnode.3
+++ /dev/null
@@ -1,66 +0,0 @@
-.\"   $Id: delbddnode.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)delbddnode.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH DELBDDNODE 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-delbddnode \- deletes an unused \fBbdd\fP node.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-void delbddnode( BddSystem, BddNode )
-  bddsystem \(**BddSystem;
-  bddnode   \(**BddNode;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIBddNode\fP
-The \fBbdd\fP node.
-.SH DESCRIPTION
-\fBdelbddnode\fP tries to delete the \fBbdd\fP node \fIBddNode\fP and its
-children, if they have not external reference, in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used. The use of this
-function is not recommended because, it takes time.
-It is better to call the \fIdecbddrefext\fP function, and do a garbage collection
-with the \fIgarbagebddsystem\fP function.
-.br
-.SH RETURN VALUE
-\fBdelbddnode\fP returns nothing.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   chain_list \(**Expr;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   BddNode = addbddcircuitin( (bddcircuit \(**)0, "i0", 0, BDD_IN_MODE_FIRST );
-   BddNode = addbddnode( (bddsystem \(**)0, BddNode->INDEX, BddNode->LOW, BddNode->HIGH );
-   Expr = convertbddcircuitabl( (bddcircuit \(**)0, BddNode );
-   delbddnode( (bddsystem \(**)0, decbddrefext( BddNode ) );
-   /* displays (not i0) */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/delbddnodeassoc.3 b/alliance/share/man/man3/delbddnodeassoc.3
deleted file mode 100644
index 4969236b..00000000
--- a/alliance/share/man/man3/delbddnodeassoc.3
+++ /dev/null
@@ -1,98 +0,0 @@
-.\"   $Id: delbddnodeassoc.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)delbddnodeassoc.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH DELBDDNODEASSOC 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-delbddnodeassoc \- deletes a \fBbdd\fP node in a variable association.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-int delbddnodeassoc( BddSystem, BddAssoc, Variable )
-  bddsystem  \(**BddSystem;
-  bddassoc   \(**BddAssoc;
-  bddvar      Variable;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIBddAssoc\fP
-The variable association.
-.TP
-\fIVariable\fP
-The variable number.
-.SH DESCRIPTION
-\fBdelbddnodeassoc\fP deletes the \fBbdd\fP node associated to the
-variable number \fIVariable\fP, in the variable association \fIBddAssoc\fP,
-in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-The number of external reference of the associated \fBbdd\fP node is incremented.
-.br
-.SH RETURN VALUE
-\fBdelbddnodeassoc\fP returns 1 if the variable is found, 0 otherwise.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"variable xxx out of range, error !"
-.ft R
-.RS
-The \fIVariable\fP parameter must be less or equal to
-the \fIBddSystem->NUMBER_VAR\fP field.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   bddnode    \(**BddSubst;
-   bddnode    \(**BddVariable;
-   bddassoc   \(**Assoc;
-   chain_list \(**Expr;
-   bddvar         Variable;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   Expr = createablbinexpr( ABL_AND,
-                            createablatom( "i0" ),
-                            createablatom( "i1" ) );
-   BddNode = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   Expr = createablbinexpr( ABL_OR,
-                            createablatom( "i2" ),
-                            createablatom( "i3" ) );
-   BddSubst = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   BddVariable = searchbddcircuitin( (bddcircuit \(**)0, "i0" );
-   Variable = getbddvarbyindex( (bddsystem \(**)0, BddVariable->INDEX );
-   Assoc = addbddassoc( (bddsystem \(**)0 );
-   addbddnodeassoc( (bddsystem \(**)0, Assoc, Variable, BddSubst );
-   BddNode = substbddnodeassoc( (bddsystem \(**)0, BddSubst, Assoc );
-   delbddnodeassoc( (bddsystem \(**)0, Assoc, Variable );
-   Expr = convertbddcircuitabl( BddCircuit, BddNode );
-   /* displays ((i3 or i2) and i1) */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddassoc( (bddsystem \(**)0 );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/delbddnodelist.3 b/alliance/share/man/man3/delbddnodelist.3
deleted file mode 100644
index f218b164..00000000
--- a/alliance/share/man/man3/delbddnodelist.3
+++ /dev/null
@@ -1,74 +0,0 @@
-.\"   $Id: delbddnodelist.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)delbddnodelist.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH DELBDDNODELIST 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-delbddnodelist \- deletes a list of \fBbdd\fP nodes.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-void delbddnodelist( BddSystem, HeadList )
-  bddsystem  \(**BddSystem;
-  chain_list \(**HeadList;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIHeadList\fP
-The head of the \fIchain_list\fP.
-.SH DESCRIPTION
-\fBdelbddnodelist\fP deletes all the \fBbdd\fP nodes of the
-list \fIHeadList\fP in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-All the nodes have their external references decremented.
-.br
-.SH RETURN VALUE
-\fBdelbddnodelist\fP returns nothing.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   chain_list \(**BddList;
-   chain_list \(**Expr;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   BddList    = (chain_list \(**)0;
-   BddList = addbddnodelist( (bddsystem \(**)0, BddList,
-                             addbddcircuitin( (bddcircuit \(**)0,
-                                              "i0", 0, BDD_IN_MODE_FIRST ) );
-   BddList = addbddnodelist( (bddsystem \(**)0, BddList,
-                              addbddcircuitin( (bddcircuit \(**)0,
-                                               "i1", 0, BDD_IN_MODE_FIRST );
-   BddList = addbddnodelist( (bddsystem \(**)0, BddList,
-                             addbddcircuitin( (bddcircuit \(**)0,
-                                              "i2", 0, BDD_IN_MODE_FIRST );
-   BddNode = applybddnodelist( (bddsystem \(**)0, ABL_AND, BddList );
-   delbddnodelist( (bddsystem \(**)0, BddList );
-   Expr = convertbddcircuitabl( (bddcircuit \(**)0, BddNode );
-   /* displays (i0 and i1 and i2) */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/delchain.3 b/alliance/share/man/man3/delchain.3
deleted file mode 100644
index a498bfdd..00000000
--- a/alliance/share/man/man3/delchain.3
+++ /dev/null
@@ -1,83 +0,0 @@
-.\"   $Id: delchain.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)delchain.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-delchain
-.XE
-.XS4 \n%
-.ti 0.2i
-delchain
-.XE4 \}
-.TH DELCHAIN 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-delchain \- delete an element of a \fBchain_list\fP
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-chain_list \(**delchain(pthead, ptdel)
-chain_list \(**pthead;
-chain_list \(**ptdel;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIpthead\fP
-Pointer to a \fBchain\fP list
-.TP
-\fIptdel\fP
-Pointer to the element to be deleted.
-.SH DESCRIPTION
-\fBdelchain\fP deletes the element of the \fBchain_list\fP pointed to by
-\fIptdel\fP in the list pointed to by \fIpthead\fP.
-The list consistency is maintainded, and the element put back in the list
-of free blocks.
-.SH RETURN VALUE
-\fBdelchain\fP returns a pointer to the new head of list if the \fIptdel\fP
-pointer used to belong to the list. In most case, it has the value of
-\fIpthead\fP. If the pointer doesn't belong to the list, \fBNULL\fP is returned.
-.SH ERROR
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** delchain impossible : pointer NULL"
-.ft R
-.RS
-At least one of the arguments are pointing to \fBNULL\fP, and that clear that
-such a pointer can't be deleted, or used for freeing.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-void delete_match(c0, c1)
-chain_list \(**c0, \(**c1;
-{
-chain_list \(**t0, \(**t1, \(**next;
-	for (t0 = c0; t0; t0 = next)
-		for (t1 = c1; t1; t1 = t1\->NEXT)
-			if (t1\->DATA == t0\->DATA)
-				next = delchain(c0, t0);	 
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR chain (3),
-.BR addchain (3),
-.BR freechain (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/deleteNumExpr.3 b/alliance/share/man/man3/deleteNumExpr.3
deleted file mode 100644
index de5e28aa..00000000
--- a/alliance/share/man/man3/deleteNumExpr.3
+++ /dev/null
@@ -1,55 +0,0 @@
-.\"   $Id: deleteNumExpr.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)deleteNumExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH DELETENUMEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBdeleteNumExpr\fP \- removes the i-th argument of an operator expression. 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-void deleteNumExpr(expr,i)
-chain_list *expr;
-int i;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIexpr\fP
-expression
-.TP 20
-\fIi\fP
-index of the argument
-.SH DESCRIPTION
-\fBdeleteNumExpr()\fP removes the \fIi-th\fP argument of \fIexpr\fP. As the array structures of C-programming, the index of the first argument is 0.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr; 
-expr = createExpr(OR);
-addQExpr(expr,createAtom("a"));
-addQExpr(expr,createAtom("b"));
-deleteNumExpr(expr,1);
-displayExpr(expr);
-/* it will display
-(OR a)
-*/
-freeExpr(expr);
-.fi
-.SH ERROR
-"deleteNumExpr : error - index out of bound"
-.br
-index i must be included between 0 and \fIlengthExpr(expr)-1\fP.
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR searchNumExpr (3),
-.BR searchOperExpr (3),
-.BR equalExpr (3),
-.BR equalVarExpr (3),
-.BR lengthExpr (3),
-.BR profExpr (3),
-.BR numberAtomExpr (3),
-.BR numberOccExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/deleteTH.3 b/alliance/share/man/man3/deleteTH.3
deleted file mode 100644
index c469d431..00000000
--- a/alliance/share/man/man3/deleteTH.3
+++ /dev/null
@@ -1,51 +0,0 @@
-.\"   $Id: deleteTH.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)deleteTH.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH DELETETH 3 "October 1, 1997" "ASIM/LIP6" "Hash table functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBdeleteTH\fP \- removes an item in a hash table.
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-int deleteTH(pTable,key)
-pTH pTable;
-char *key;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIpTable\fP
-Hash table.
-.TP 20
-\fIkey\fP
-Key used by the hash coding function.
-.SH DESCRIPTION
-\fBdeleteTH()\fP removes an item in \fIpTable\fP. If the key doesn't exist, the function returns EMPTYTH, if it does then its associated value. 
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"
-#include "logmmm.h"
-pTH mytable; 
-int val;
-
-mytable = createTH(100); 
-addTH(mytable,namealloc("var1"),0);
-addTH(mytable,namealloc("var2"),1);
-val = deleteTH(mytable,namealloc("var1"));
-	/* val = 0 */
-val = deleteTH(mytable,namealloc("var3"));
-	/* val = -1  EMPTYTH */
-val = deleteTH(mytable,namealloc("var2"));
-	/* val = 1 */
-	/* mytable is empty */
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR tsh (1),
-.BR createTH (3),
-.BR destroyTH (3),
-.BR searchTH (3),
-.BR addTH (3),
-.BR displayTH (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/delht.3 b/alliance/share/man/man3/delht.3
deleted file mode 100644
index 9924b07e..00000000
--- a/alliance/share/man/man3/delht.3
+++ /dev/null
@@ -1,71 +0,0 @@
-.\"   $Id: delht.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)delht.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.\" slightly modified by Fred Petrot for mbk adaptation on 22/06/92
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-delht
-.XE
-.XS4 \n%
-.ti 0.2i
-delht
-.XE4 \}
-.TH DELHT 3 "October 1, 1997" "ASIM/LIP6" "MBK HASH TABLE MANAGEMENT FUNCTIONS"
-.SH NAME
-delht \- removes an hash table
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-#include "mut315.h"
-void delht(table)
-ht \(**table;
-.fi
-.SH PARAMETER
-.TP 20
-\fItable\fP
-Hash table pointer
-.SH DESCRIPTION
-\fBdelht()\fP removes the hash table pointed to by \fItable\fP from
-memory.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-checksigname(p)
-lofig_list \(**p;
-{
-ht \(**h; 
-int i;
-char \(**amatla;
-	for (i = 0, ptsig = p->LOSIG; ptsig; i++, ptsig = ptsig->NEXT);
-	h = addht(i);
-	for (ptcon = p->LOCON; ptcon; ptcon = ptcon->NEXT)
-		addhtitem(h, ptcon->NAME, 0);
-	for (ptsig = p->LOSIG; ptsig; ptsig = ptsig->NEXT) {
-		if (ptsig->TYPE == INTERNAL) {
-			amatla = getsigname(ptsig);
-			if (!sethtitem(h, amatla, 0)) {
-				printf("N %s;\\n", amatla);
-			}
-		}
-	}
-	delht(h);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR addht (3),
-.BR addhtitem (3),
-.BR gethtitem (3),
-.BR delhtitem (3),
-.BR viewht (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/delhtitem.3 b/alliance/share/man/man3/delhtitem.3
deleted file mode 100644
index c8d041dc..00000000
--- a/alliance/share/man/man3/delhtitem.3
+++ /dev/null
@@ -1,84 +0,0 @@
-.\"   $Id: delhtitem.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)delhtitem.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.\" slightly modified by Fred Petrot for mbk adaptation on 22/06/92
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-delhtitem
-.XE
-.XS4 \n%
-.ti 0.2i
-delhtitem
-.XE4 \}
-.TH DELHTITEM 3 "October 1, 1997" "ASIM/LIP6" "MBK HASH TABLE MANAGEMENT FUNCTIONS"
-.SH NAME
-delhtitem \- removes an item in an hash table
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.nf
-#include "mut315.h"
-int delhtitem(table, key)
-ht \(**table;
-void \(**key;
-.fi
-.ft R
-.SH PARAMETERS
-.TP 20
-\fItable\fP
-Hash table pointer
-.TP 20
-\fIkey\fP
-Key used by the hash coding function indicating the item to be deleted
-.SH DESCRIPTION
-\fBdelhtitem()\fP removes an item in the hash table pointed to by \fItable\fP.
-.SH RETURN VALUE
-If the key doesn't exist, the function returns \fBEMPTYHT\fP,
-if it does, then its associated value is returned.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.nf
-#include "mut315.h"
-checksigname(p, h)
-lofig_list \(**p;
-ht \(**h; 
-{
-int i;
-char \(**amatla;
-	/\(** check for signal and connector name unicity \(**/
-	for (ptcon = p->LOCON; ptcon; ptcon = ptcon->NEXT)
-		addhtitem(h, ptcon->NAME, 0);
-	for (ptsig = p->LOSIG; ptsig; ptsig = ptsig->NEXT) {
-		if (ptsig->TYPE == INTERNAL) {
-			amatla = getsigname(ptsig);
-			if (!sethtitem(h, amatla, 0)) {
-				printf("N %s;\\n", amatla);
-			}
-		}
-	}
-	/\(** keep only internal signal names in the hash table \(**/
-	for (ptcon = p->LOCON; ptcon; ptcon = ptcon->NEXT)
-		(void)delhtitem(h, ptcon->NAME);
-}
-.fi
-.ft R
-.SH SEE ALSO
-.BR mbk (1),
-.BR addth (3),
-.BR delht (3),
-.BR addhtitem (3),
-.BR gethtitem (3),
-.BR sethtitem (3),
-.BR viewht (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/dellocon.3 b/alliance/share/man/man3/dellocon.3
deleted file mode 100644
index 8de5c447..00000000
--- a/alliance/share/man/man3/dellocon.3
+++ /dev/null
@@ -1,69 +0,0 @@
-.\"   $Id: dellocon.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)dellocon.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-dellocon
-.XE
-.XS2 \n%
-.ti 0.2i
-dellocon
-.XE2 \}
-.TH DELLOCON 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL FUNCTIONS"
-.SH NAME
-dellocon \- delete a logical connector
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-int dellocon(ptfig, name)
-lofig_list \(**ptfig;
-char \(**name;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptfig\fP
-Pointer to the figure in which the connector should be deleted
-.TP
-\fIname\fP
-Name of the connector to be deleted.
-.SH DESCRIPTION
-\fBdellocon\fP deletes the connector called \fIname\fP in the figure 
-pointed to by \fIptfig\fP. The list consistency is maintained, and the space
-freed.
-.SH RETURN VALUE
-\fBdellocon\fP returns \fB1\fP if the connector has been deleted, \fB0\fP
-if no such connector exists in the list.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-char \(**was_existing(p, s)
-lofig_list \(**p;
-char \(**s;
-{
-   return dellocon(p, s) ? "you just killed it!\n" 
-                         : "wasn't here anyway\n"; 
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR lofig (3),
-.BR locon (3),
-.BR addlocon (3),
-.BR getlocon (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/dellofig.3 b/alliance/share/man/man3/dellofig.3
deleted file mode 100644
index 6b5914c8..00000000
--- a/alliance/share/man/man3/dellofig.3
+++ /dev/null
@@ -1,68 +0,0 @@
-.\"   $Id: dellofig.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)dellofig.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-dellofig
-.XE
-.XS2 \n%
-.ti 0.2i
-dellofig
-.XE2 \}
-.TH DELLOFIG 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL FUNCTIONS"
-.SH NAME
-dellofig \- delete and free a logical figure 
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-int dellofig(figname)
-char \(**figname;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIfigname\fP
-Name of the figure to be deleted
-.SH DESCRIPTION
-\fBdellofig\fP deletes the figure called \fIfigname\fP from the list of
-logical figure in memory. All the lists of elements belonging to the figure
-are also deleted and freed.
-.SH RETURN VALUE
-\fBdellofig\fP returns \fB1\fP if the figure was delete, and \fB0\fP if no
-figure called \fIfigname\fP was present in memory.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-void delete_na2_y()
-{
-	if (dellofig("na2_y"))
-		(void)fputs("deleted na2_y successfully", stdout);
-	else
-		(void)fputs("na2_y not present in ram !", stdout);		
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR lofig (3),
-.BR addlofig (3),
-.BR getlofig (3),
-.BR loadlofig (3),
-.BR savelofig (3),
-.BR flattenlofig (3),
-.BR rflattenlofig (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/delloins.3 b/alliance/share/man/man3/delloins.3
deleted file mode 100644
index a1714e10..00000000
--- a/alliance/share/man/man3/delloins.3
+++ /dev/null
@@ -1,72 +0,0 @@
-.\"   $Id: delloins.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)delloins.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-delloins
-.XE
-.XS2 \n%
-.ti 0.2i
-delloins
-.XE2 \}
-.TH DELLOINS 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL FUNCTIONS"
-.SH NAME
-delloins \- delete a logical instance
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-int delloins(ptfig, insname)
-lofig_list \(**ptfig;
-char \(**insname;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptfig\fP
-Pointer to the figure in which the instance should be deleted
-.TP
-\fIinsname\fP
-Name of the instance to be deleted.
-.SH DESCRIPTION
-\fBdelloins\fP delete the instance called \fIinsname\fP in the figure 
-pointed to by \fIptfig\fP. This instance is warrantied to be unique, because
-its name is an identifier at the given hierarchical level.
-The list consistency is maintainded, and the space freed. The instance
-connectors are also freed, since if the instance disapear, no more connections
-can occur on it.
-.SH RETURN VALUE
-\fBdelloins\fP returns \fB1\fP if the instance has been deleted, \fB0\fP
-if no such instance exists in the list.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-char \(**was_existing(ptfig, insname)
-lofig_list \(**ptfig;
-char \(**insname;
-{
-   return delloins(ptfig, insname) ? "you just killed it!"
-                                 : "wasn't here anyway"; 
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR lofig (3),
-.BR loins (3),
-.BR addloins (3),
-.BR getloins (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/dellosig.3 b/alliance/share/man/man3/dellosig.3
deleted file mode 100644
index 6580e7df..00000000
--- a/alliance/share/man/man3/dellosig.3
+++ /dev/null
@@ -1,69 +0,0 @@
-.\"   $Id: dellosig.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)dellosig.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-dellosig
-.XE
-.XS2 \n%
-.ti 0.2i
-dellosig
-.XE2 \}
-.TH DELLOSIG 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL FUNCTIONS"
-.SH NAME
-dellosig \- delete a logical signal
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-int dellosig(ptfig, index)
-lofig_list \(**ptfig;
-long index;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptfig\fP
-Pointer to the figure in which the signal should be deleted
-.TP
-\fIindex\fP
-Index of the signal to be deleted.
-.SH DESCRIPTION
-\fBdellosig\fP delete the signal that has \fIindex\fP as \fIINDEX\fP 
-in the figure pointed to by \fIptfig\fP. 
-The list consistency is maintainded, and the space freed.
-.SH RETURN VALUE
-\fBdellosig\fP returns \fB1\fP if the signal has been deleted, \fB0\fP
-if the signal index does not exists in the list.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-char \(**was_existing(ptfig, index)
-lofig_list \(**ptfig;
-long index;
-{
-   return dellosig(ptfig, index) ? "you just killed it!"
-                                 : "wasn't here anyway"; 
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR lofig (3),
-.BR losig (3),
-.BR addlosig (3),
-.BR getlosig (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/dellotrs.3 b/alliance/share/man/man3/dellotrs.3
deleted file mode 100644
index 95b28244..00000000
--- a/alliance/share/man/man3/dellotrs.3
+++ /dev/null
@@ -1,70 +0,0 @@
-.\"   $Id: dellotrs.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)dellotrs.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-dellotrs
-.XE
-.XS2 \n%
-.ti 0.2i
-dellotrs
-.XE2 \}
-.TH DELLOTRS 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL FUNCTIONS"
-.SH NAME
-dellotrs \- delete a logical transistor
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-int dellotrs(ptfig, pttrs)
-lofig_list \(**ptfig;
-lotrs_list \(**pttrs;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptfig\fP
-Pointer to the figure in which the transistor should be deleted
-.TP
-\fIpttrs\fP
-Pointer to the transistor to be deleted.
-.SH DESCRIPTION
-\fBdellotrs\fP delete the transistor pointed to by \fIpttrs\fP in the figure 
-pointed to by \fIptfig\fP. 
-The list consistency is maintainded, and the space freed. The transistor
-connectors are also freed, since if the transistor disapear,
-no more connections can occur on it.
-.SH RETURN VALUE
-\fBdellotrs\fP returns \fB1\fP if the transistor has been deleted, \fB0\fP
-if the transistor pointer does nit exists in the list.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-char \(**was_existing(ptfig, pttrs)
-lofig_list \(**ptfig;
-lotrs_list \(**pttrs;
-{
-   return dellotrs(ptfig, pttrs) ? "you just killed it!"
-                                 : "wasn't here anyway"; 
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR lofig (3),
-.BR lotrs (3),
-.BR addlotrs (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/delnum.3 b/alliance/share/man/man3/delnum.3
deleted file mode 100644
index a8eae498..00000000
--- a/alliance/share/man/man3/delnum.3
+++ /dev/null
@@ -1,82 +0,0 @@
-.\"   $Id: delnum.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)delnum.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-delnum
-.XE
-.XS4 \n%
-.ti 0.2i
-delnum
-.XE4 \}
-.TH DELNUM 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-delnum \- delete an element of a \fBnum_list\fP
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-num_list \(**delnum(pthead, ptdel)
-num_list \(**pthead, \(**ptdel;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIpthead\fP
-Pointer to a \fBnum\fP list
-.TP
-\fIptdel\fP
-Pointer to the element to be deleted.
-.SH DESCRIPTION
-\fBdelnum\fP deletes the element of the \fBnum_list\fP pointed to by
-\fIptdel\fP in the list pointed to by \fIpthead\fP.
-The list consistency is maintainded, and the element put back in the list
-of free blocks.
-.SH RETURN VALUE
-\fBdelnum\fP returns a pointer to the new head of list if the \fIptdel\fP
-pointer used to belong to the list. In most case, it has the value of
-\fIpthead\fP. If the pointer doesn't belong to the list, \fBNULL\fP is returned.
-.SH ERROR
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** delnum impossible : pointer NULL"
-.ft R
-.RS
-At least one of the arguments are pointing to \fBNULL\fP, and that clear that
-such a pointer can't be deleted.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-void delete_match(c0, c1)
-num_list \(**c1, \(**c2;
-{
-num_list \(**t0, \(**t1, \(**next;
-	for (t0 = c0; t0; t0 = next)
-		for (t1 = c1; t1; t1 = t1\->NEXT)
-			if (t1\->DATA == t0\->DATA)
-				next = delnum(c0, t0);	 
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR num (3),
-.BR addnum (3),
-.BR freenum (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/delphcon.3 b/alliance/share/man/man3/delphcon.3
deleted file mode 100644
index 5ef44c7b..00000000
--- a/alliance/share/man/man3/delphcon.3
+++ /dev/null
@@ -1,70 +0,0 @@
-.\"   $Id: delphcon.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)delphcon.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-delphcon
-.XE
-.XS0 \n%
-.ti 0.2i
-delphcon
-.XE0 \}
-.TH DELPHCON 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL FUNCTIONS"
-.SH NAME
-delphcon \- delete a physical connector
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-int delphcon(ptfig, ptcon)
-phfig_list \(**ptfig;
-phcon_list \(**ptcon;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptfig\fP
-Pointer to the figure in which the connector should be deleted
-.TP
-\fIptcon\fP
-Pointer to the connector to be deleted.
-.SH DESCRIPTION
-\fBdelphcon\fP delete the connector pointed to by \fIptcon\fP in the figure 
-pointed to by \fIptfig\fP.
-The list and index consistency is maintainded, and the space freed.
-.SH RETURN VALUE
-\fBdelphcon\fP returns \fB1\fP if the connector has been deleted, \fB0\fP
-if no such connector exists in the list.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-char \(**was_existing(ptfig, ptcon)
-phfig_list \(**ptfig;
-phcon_list \(**ptcon;
-{
-   /\(** if only one exists, it's this one \(**/
-   return delphcon(ptfig, ptcon) ? "you just killed it!\n"
-                                 : "wasn't here anyway\n"; 
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR phfig (3),
-.BR phcon (3),
-.BR addphcon (3),
-.BR getphcon (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/delphfig.3 b/alliance/share/man/man3/delphfig.3
deleted file mode 100644
index 53da71b3..00000000
--- a/alliance/share/man/man3/delphfig.3
+++ /dev/null
@@ -1,68 +0,0 @@
-.\"   $Id: delphfig.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)delphfig.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-delphfig
-.XE
-.XS0 \n%
-.ti 0.2i
-delphfig
-.XE0 \}
-.TH DELPHFIG 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL FUNCTIONS"
-.SH NAME
-delphfig \- delete and free a physical figure 
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-int delphfig(figname)
-char \(**figname;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIfigname\fP
-Name of the figure to be deleted
-.SH DESCRIPTION
-\fBdelphfig\fP deletes the figure called \fIfigname\fP from the list of
-physical figure in memory. All the lists of elements belonging to the figure
-are also deleted and freed.
-.SH RETURN VALUE
-\fBdelphfig\fP returns \fB1\fP if the figure was delete, and \fB0\fP if no
-figure called \fIfigname\fP was present in memory.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-void delete_na2_y()
-{
-	if (delphfig("na2_y"))
-		(void)fputs("deleted na2_y successfully", stdout);
-	else
-		(void)fputs("na2_y not present in ram !", stdout);		
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR phfig (3),
-.BR addphfig (3),
-.BR getphfig (3),
-.BR loadphfig (3),
-.BR savephfig (3),
-.BR flattenphfig (3),
-.BR rflattenphfig (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/delphins.3 b/alliance/share/man/man3/delphins.3
deleted file mode 100644
index df8c210a..00000000
--- a/alliance/share/man/man3/delphins.3
+++ /dev/null
@@ -1,70 +0,0 @@
-.\"   $Id: delphins.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)delphins.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-delphins
-.XE
-.XS0 \n%
-.ti 0.2i
-delphins
-.XE0 \}
-.TH DELPHINS 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL FUNCTIONS"
-.SH NAME
-delphins \- delete a physical instance
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-int delphins(ptfig, insname)
-phfig_list \(**ptfig;
-char \(**insname;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptfig\fP
-Pointer to the figure in which the instance should be deleted
-.TP
-\fIinsname\fP
-Name of the instance to be deleted.
-.SH DESCRIPTION
-\fBdelphins\fP delete the instance called \fIinsname\fP in the figure 
-pointed to by \fIptfig\fP. This instance is warrantied to be unique, because
-its name is an identifier at the given hierarchical level.
-The list consistency is maintainded, and the space freed.
-.SH RETURN VALUE
-\fBdelphins\fP returns \fB1\fP if the instance has been deleted, \fB0\fP
-if no such instance exists in the list.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-char \(**was_existing(ptfig, insname)
-phfig_list \(**ptfig;
-char \(**insname;
-{
-   return delphins(ptfig, insname) ? "you just killed it!"
-												: "wasn't here anyway"; 
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR phfig (3),
-.BR phins (3),
-.BR addphins (3),
-.BR getphins (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/delphref.3 b/alliance/share/man/man3/delphref.3
deleted file mode 100644
index c3101624..00000000
--- a/alliance/share/man/man3/delphref.3
+++ /dev/null
@@ -1,70 +0,0 @@
-.\"   $Id: delphref.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)delphref.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-delphref
-.XE
-.XS0 \n%
-.ti 0.2i
-delphref
-.XE0 \}
-.TH DELPHREF 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL FUNCTIONS"
-.SH NAME
-delphref \- delete a physical reference
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-int delphref(ptfig, ptref)
-phfig_list \(**ptfig;
-phref_list \(**ptref;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptfig\fP
-Pointer to the figure in which the reference should be deleted
-.TP
-\fIptref\fP
-Pointer to the reference to be deleted.
-.SH DESCRIPTION
-\fBdelphref\fP delete the reference pointed to by \fIptref\fP in the figure 
-pointed to by \fIptfig\fP.
-The list consistency is maintainded, and the space freed.
-.SH RETURN VALUE
-\fBdelphref\fP returns \fB1\fP if the reference has been deleted, \fB0\fP
-if no such reference exists in the list.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-char \(**was_existing(ptfig, ptref)
-phfig_list \(**ptfig;
-phref_list \(**ptref;
-{
-   /\(** if only one exists, it's this one \(**/
-   return delphref(ptfig, ptref) ? "you just killed it!"
-                                 : "wasn't here anyway"; 
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR phfig (3),
-.BR phref (3),
-.BR addphref (3),
-.BR getphref (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/delphseg.3 b/alliance/share/man/man3/delphseg.3
deleted file mode 100644
index 0f54ebeb..00000000
--- a/alliance/share/man/man3/delphseg.3
+++ /dev/null
@@ -1,69 +0,0 @@
-.\"   $Id: delphseg.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)delphseg.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-delphseg
-.XE
-.XS0 \n%
-.ti 0.2i
-delphseg
-.XE0 \}
-.TH DELPHSEG 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL FUNCTIONS"
-.SH NAME
-delphseg \- delete a physical segment
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-int delphseg(ptfig, ptseg)
-phfig_list \(**ptfig;
-phseg_list \(**ptseg;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptfig\fP
-Pointer to the figure in which the segment should be deleted
-.TP
-\fIptseg\fP
-Pointer to the segment to be deleted
-.SH DESCRIPTION
-\fBdelphseg\fP delete the segment pointed to by \fIptseg\fP in the figure 
-pointed to by \fIptfig\fP.
-The list consistency is maintainded, and the space freed.
-.SH RETURN VALUE
-\fBdelphseg\fP returns \fB1\fP if the segment has been deleted, \fB0\fP
-if no such segment exists in the list.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-char \(**was_existing(ptfig, ptseg)
-phfig_list \(**ptfig;
-phseg_list \(**ptseg;
-{
-   /\(** if only one exists, it's this one \(**/
-   return delphseg(ptfig, ptseg) ? "you just killed it!"
-                                 : "wasn't here anyway"; 
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR phfig (3),
-.BR phseg (3),
-.BR addphseg (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/delphvia.3 b/alliance/share/man/man3/delphvia.3
deleted file mode 100644
index 0d2e146b..00000000
--- a/alliance/share/man/man3/delphvia.3
+++ /dev/null
@@ -1,69 +0,0 @@
-.\"   $Id: delphvia.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)delphvia.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-delphvia
-.XE
-.XS0 \n%
-.ti 0.2i
-delphvia
-.XE0 \}
-.TH DELPHVIA 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL FUNCTIONS"
-.SH NAME
-delphvia \- delete a physical via
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-int delphvia(ptfig, ptvia)
-phfig_list \(**ptfig;
-phvia_list \(**ptvia;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptfig\fP
-Pointer to the figure in which the via should be deleted
-.TP
-\fIptvia\fP
-Pointer to the via to be deleted.
-.SH DESCRIPTION
-\fBdelphvia\fP delete the via pointed to by \fIptvia\fP in the figure 
-pointed to by \fIptfig\fP.
-The list consistency is maintainded, and the space freed.
-.SH RETURN VALUE
-\fBdelphvia\fP returns \fB1\fP if the via has been deleted, \fB0\fP
-if no such via exists in the list.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-char \(**was_existing(ptfig, ptvia)
-phfig_list \(**ptfig;
-phvia_list \(**ptvia;
-{
-   /\(** if only one exists, it's this one \(**/
-   return delphvia(ptfig, ptvia) ? "you just killed it!"
-                                 : "wasn't here anyway"; 
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR phfig (3),
-.BR phvia (3),
-.BR addphvia (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/delptype.3 b/alliance/share/man/man3/delptype.3
deleted file mode 100644
index 13ee4b93..00000000
--- a/alliance/share/man/man3/delptype.3
+++ /dev/null
@@ -1,84 +0,0 @@
-.\"   $Id: delptype.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)delptype.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-delptype
-.XE
-.XS4 \n%
-.ti 0.2i
-delptype
-.XE4 \}
-.TH DELPTYPE 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-delptype \- delete an element of a \fBptype_list\fP
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-ptype_list \(**delptype(pthead, type)
-ptype_list \(**pthead;
-long type;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIpthead\fP
-Pointer to a \fBptype\fP list
-.TP
-\fItype\fP
-The pointer of this type is to be deleted.
-.SH DESCRIPTION
-\fBdelptype\fP deletes the element of the \fBptype_list\fP that has the type
-\fItype\fP in the list pointed to by \fIpthead\fP.
-The list consistency is maintained, and the element put back in the list
-of free blocks.
-.SH RETURN VALUE
-\fBdelptype\fP returns a pointer to the new head of list if a \fItype\fPd
-pointer used to belong to the list. In most case, it has the value of
-\fIpthead\fP. If the \fItype\fP doesn't belong to the list, \fBNULL\fP is
-returned.
-.SH ERROR
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** delptype impossible : pthead = NULL"
-.ft R
-.RS
-The pointer to the head of list is \fBNULL\fP, and that clear that
-such a list can't be ran thru.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-#include "mph315.h"
-void delete_user(ptfig)
-phfig_list \(**ptfig;
-{
-phins_list \(**i;
-	for (i = ptfig\->PHINS; i; i = i\->NEXT) 
-		i\->USER = delptype(i\->USER, PLACEABOX);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR ptype (3),
-.BR addptype (3),
-.BR getptype (3),
-.BR freeptype (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/delrdsfig.3 b/alliance/share/man/man3/delrdsfig.3
deleted file mode 100644
index 4bda2632..00000000
--- a/alliance/share/man/man3/delrdsfig.3
+++ /dev/null
@@ -1,84 +0,0 @@
-.\"   $Id: delrdsfig.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)delrdsfig.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-delrdsfig
-.XE
-.XS0 \n%
-.ti 0.2i
-delrdsfig
-.XE0 \}
-.TH DELRDSFIG 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
- delrdsfig \- deletes a figure
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rdsnnn.h"
-int delrdsfig( Name )
-     char \(**Name;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIName\fP
-Name of the figure to delete.
-.SH DESCRIPTION
-This function deletes the figure called \'\fIName\fP\' from the list of figures in memory. All objets (instances and rectangles) contained in this figure are deleted and freed. 
-.TP
-\fINOTE\fP : The figure is identified by its name.
-.SH RETURN VALUE
-1 => The figure has been deleted.
-.TP
-0 => The figure doesn't exist.
-.SH ERRORS
-none
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-      #include "mutnnn.h"
-      #include "rdsnnn.h"
-      #include "rtlnnn.h"
-        typedef struct UserStruct
-         {
-           char \(**STRING;
-           void \(**USER1;
-         } UserStruct;
-         main()
-          {
-            rdsfig_list \(**Figure;
-            rdsrec_list \(**Rectangle;
-            rdsins_list \(**Instance;
-            int          Result;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            Figure = addrdsfig ("core",sizeof ( UserStruct ) );
-            Instance  = delrdsfig (Figure,"na2_y","and2",RDS_NOSYM,8,6); 
-            Rectangle =
-             addrdsfigrec(RdsFigure,"Alu1",RDS_ALU1,2,4,12,1);
-            /\(**
-              destruction of the figure , its instance, its rectangle 
-            \(**/
-            Result = \fBdelrdsfig\fP ( "core" );
-            if ( Result == 0 ) printf("Figure 'core' not found !\\n"); 
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librds,
-.BR allocrdsfig
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/delrdsfigrec.3 b/alliance/share/man/man3/delrdsfigrec.3
deleted file mode 100644
index 536b3d24..00000000
--- a/alliance/share/man/man3/delrdsfigrec.3
+++ /dev/null
@@ -1,84 +0,0 @@
-.\"   $Id: delrdsfigrec.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)delrdsfigrec.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-delrdsfigrec
-.XE
-.XS0 \n%
-.ti 0.2i
-delrdsfigrec
-.XE0 \}
-.TH DELRDSFIGREC 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-delrdsfigrec \- deletes a rectangle of a figure
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include"rdsnnn.h"
- int delrdsfigrec( Figure, Rectangle )
-      rdsfig_list \(**Figure;
-      rdsrec_list \(**Rectangle;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIFigure\fP
-Figure which contains the rectangle to delete.
-.TP
-\fIRectangle\fP
-The rectangle to delete
-.SH DESCRIPTION
-The \fIdelrdsfigrec\fP function deletes a rectangle object (which is composed of the rdsrec_list structure and an eventually added structure) from a figure.
-.SH RETURN VALUE
-1 => The rectangle has been deleted.
-.br
-0 => The rectangle doesn't exist.
-.SH ERRORS
-None
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rtlnnn.h"
-        typedef struct UserStruct
-         {
-           char \(**STRING;
-           void \(**USER1;
-         } UserStruct;
-         main()
-          {
-            rdsfig_list \(**Figure;
-            rdsrec_list \(**Rectangle;
-            int          Result;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            Figure = addrdsfig ("core",sizeof ( UserStruct ) );
-            Rectangle =
-             addrdsfigrec(Figure,"Alu1",RDS_ALU1,2,4,12,1);
-            /\(**
-              deletes the rectangle of the figure
-            \(**/
-            Result = \fBdelrdsfigrec\fP ( Figure,Rectangle );
-            if ( Result == 0 ) printf("Rectangle not found !\\n");
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librds,
-.BR allocrdsfigrec
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/delrdsins.3 b/alliance/share/man/man3/delrdsins.3
deleted file mode 100644
index 23c72b41..00000000
--- a/alliance/share/man/man3/delrdsins.3
+++ /dev/null
@@ -1,86 +0,0 @@
-.\"   $Id: delrdsins.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)delrdsins.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-delrdsins
-.XE
-.XS0 \n%
-.ti 0.2i
-delrdsins
-.XE0 \}
-.TH DELRDSINS 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
- delrdsins \- deletes an instance of a figure
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rdsnnn.h"
-int delrdsins( Figure, Name )
-     rdsfig_list \(**Figure;
-     char        \(**Name;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIFigure\fP
-figure which contains the instance to delete. 
-.TP
-\fIName\fP
-Name of the instance to delete in the figure 'Figure'.
-.SH DESCRIPTION
-Deletes an instance and objects contained in it. The instance is identified by its name in the figure which contains it. This instance is warrantied to be unique, because its name is an identifier at the given hierarchical  level.
-.SH RETURN VALUE 
-1 => the instance has been deleted.
-.TP
-0 => the instance doesn't exist.
-.SH ERRORS
-none
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-      #include "mutnnn.h"
-      #include "rdsnnn.h"
-      #include "rtlnnn.h"
-        typedef struct UserStruct
-         {
-           char \(**STRING;
-           void \(**USER1;
-         } UserStruct;
-         main()
-          {
-            rdsfig_list \(**Figure;
-            rdsrec_list \(**Rectangle;
-            rdsins_list \(**Instance;
-            int          Result;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            Figure = addrdsfig ("core",sizeof ( UserStruct ) );
-            Instance  = addrdsins (Figure,"na2_y","and2",RDS_NOSYM,8,6);
-            Rectangle =
-             addrdsinsrec(Instance,"Alu1",RDS_ALU1,2,4,12,1);
-            /\(**
-              destruction of instance and its objects
-            \(**/
-            Result = \fBdelrdsins\fP ( Figure,"and2" );
-            if ( Result == 0 ) printf("Instance 'and2' not found !\\n");
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librds,
-.BR allocrdsins
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/delrdsinsrec.3 b/alliance/share/man/man3/delrdsinsrec.3
deleted file mode 100644
index 4757e4a8..00000000
--- a/alliance/share/man/man3/delrdsinsrec.3
+++ /dev/null
@@ -1,86 +0,0 @@
-.\"   $Id: delrdsinsrec.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)delrdsinsrec.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-delrdsinsrec
-.XE
-.XS0 \n%
-.ti 0.2i
-delrdsinsrec
-.XE0 \}
-.TH DELRDSINSREC 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-delrdsinsrec \- deletes a rectangle of an instance
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include"rdsnnn.h"
- int delrdsinsrec( Instance, Rectangle )
-      rdsins_list \(**Instance;
-      rdsrec_list \(**Rectangle;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIInstance\fP
-Instance which contains the rectangle to delete.
-.TP
-\fIRectangle\fP
-The rectangle to delete.
-.SH DESCRIPTION
-The \fIdelrdsinsrec\fP function deletes a rectangle of an RDS instance.
-.SH RETURN VALUE
-1 => The rectangle has been deleted.
-.br
-0 => The rectangle doesn't exist.
-.SH ERRORS
-None
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rtlnnn.h"
-        typedef struct UserStruct
-         {
-           char \(**STRING;
-           void \(**USER1;
-         } UserStruct;
-         main()
-          {
-            rdsfig_list \(**Figure;
-            rdsrec_list \(**Rectangle;
-            rdsins_list \(**Instance;
-            int          Result;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            Figure = addrdsfig ("core",sizeof ( UserStruct ) );
-            Instance  = addrdsins (Figure,"na2_y","and2",RDS_NOSYM,8,6);
-            Rectangle =
-             addrdsinsrec(Instance,"Alu1",RDS_ALU1,2,4,12,1);
-            /\(**
-              destruction of the rectangle of the instance
-            \(**/
-            Result = \fBdelrdsinsrec\fP ( Instance,Rectangle );
-            if ( Result == 0 ) printf("Rectangle not found !\\n");
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librds,
-.BR allocrdsinsrec
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/delrdsrecwindow.3 b/alliance/share/man/man3/delrdsrecwindow.3
deleted file mode 100644
index 8ed8cd9f..00000000
--- a/alliance/share/man/man3/delrdsrecwindow.3
+++ /dev/null
@@ -1,95 +0,0 @@
-.\"   $Id: delrdsrecwindow.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)delrdsrecwindow.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-delrdsrecwindow
-.XE
-.XS0 \n%
-.ti 0.2i
-delrdsrecwindow
-.XE0 \}
-.TH DELRDSRECWINDOW 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-delrdsrecwindow \- deletes a rectangle from the windowing of rds structure.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rwinnn.h"
-void delrdsrecwindow( Rectangle, RdsWindow )
-   rdsrec_list \(**Rectangle;
-   rdswindow   \(**RdsWindow;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIRectangle\fP
-The rectangle to delete from the windowing.
-.TP
-\fIRdsWindow\fP
-Pointer to the windowing of rds structure.
-.SH DESCRIPTION
-The \fIdelrdsrecwindow\fP function deletes a rectangle from the windowing of the rds structure. Some fields of the rectangle structure are modified :
-.br
-Field \'USER\' is set to NULL.
-.br 
-Field \'FLAGS\' is modified (bits about the windowing - see librds : the field \'FLAGS\' of rdsrec_list structure).
-.SH RETURN VALUE
-nothing
-.SH ERRORS
-none
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rwinnn.h"
-        #include "rtlnnn.h"
-        typedef struct UserStruct 
-         {
-           void \(**POINTER;
-         } UserStruct;
-        main()
-          {
-            rdsfig_list \(**Figure;
-            rdsrec_list \(**Rectangle;
-            rdswindow \(**RdsWindow;
-             mbkenv();
-             rdsenv();
-             loadrdsparam();
-             Figure = addrdsfig( "core",sizeof ( UserStruct ) );
-             Rectangle =
-               addrdsfigrec(Figure,"Alu1",RDS_ALU1,2,4,5,1);
-            RdsWindow = allocrdswindow();
-            RdsWindow->XMIN = -200;
-            RdsWindow->YMIN = -200;
-            RdsWindow->XMAX =  200;
-            RdsWindow->YMAX =  200;
-            RdsWindow->DX   =  4;
-            RdsWindow->DY   =  4;
-            RdsWindow->SIDE =  100;
-            RdsWindow->SIZE =  RdsWindow->DX \(** RdsWindow->DY ;
-            RdsWindow->WINTAB = allocrdswin( RdsWindow->SIZE );
-            addrdsrecwindow( Rectangle, RdsWindow );
-            . . .
-            /\(** \(**/ \fBdelrdsrecwindow\fP( Rectangle, RdsWindow );
-            . . .
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librwi,
-.BR addrdsrecwindow
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/destroyBdd.3 b/alliance/share/man/man3/destroyBdd.3
deleted file mode 100644
index 58d93902..00000000
--- a/alliance/share/man/man3/destroyBdd.3
+++ /dev/null
@@ -1,39 +0,0 @@
-.\"   $Id: destroyBdd.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)destroyBdd.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH DESTROYBDD 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBdestroyBdd\fP \- removes the BDDs system 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-void destroyBdd(level)
-.fi
-.SH PARAMETER
-.TP 20
-\fIlevel\fP
-desallocate level
-.SH DESCRIPTION
-\fBdestroyBdd()\fP removes the BDDs system. This function can be called only after the \fBinitializeBdd()\fP function. if \fIlevel = 0\fP the nodes are saved and it's possible to go through the BDD for treatements that don't modify the BDD (simulation for example).
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-
-initializeBdd(MEDIUM_BDD);
-
-/* application using BDD ... */
-
-destroyBdd(1);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR initializeBdd (3),
-.BR gcNodeBdd (3),
-.BR markAllBdd (3),
-.BR numberNodeAllBdd (3),
-.BR resetBdd (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/destroyCct.3 b/alliance/share/man/man3/destroyCct.3
deleted file mode 100644
index 4dc90355..00000000
--- a/alliance/share/man/man3/destroyCct.3
+++ /dev/null
@@ -1,40 +0,0 @@
-.\"   $Id: destroyCct.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)destroyCct.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH DESTROYCCT 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBdestroyCct\fP \- removes a circuit 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-void destroyCct(pC)
-pCircuit pC;
-.fi
-.SH PARAMETER
-.TP 20
-\fIpC\fP
-circuit to remove
-.SH DESCRIPTION
-\fBdestroyCct()\fP removes a circuit.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-pCircuit pC;
-
-initializeBdd(SMALL_BDD);
-pC = initializeCct("circuit 1",10,10);
-
-	/* application using pC */
-
-destroyCct(pC);
-destroyBdd(1);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR resetCct (3),
-.BR initializeCct (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/destroyTH.3 b/alliance/share/man/man3/destroyTH.3
deleted file mode 100644
index fce9802f..00000000
--- a/alliance/share/man/man3/destroyTH.3
+++ /dev/null
@@ -1,37 +0,0 @@
-.\"   $Id: destroyTH.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)destroyTH.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH DESTROYTH 3 "October 1, 1997" "ASIM/LIP6" "Hash table functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBdestroyTH\fP \- removes a hash table
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-void destroyTH(pTable)
-pTH pTable;
-.fi
-.SH PARAMETER
-.TP 20
-\fIpTable\fP
-Hash table.
-.SH DESCRIPTION
-\fBdestroyTH()\fP removes \fIptable\fP in memory.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"
-#include "logmmm.h"
-pTH mytable; 
-mytable = createTH(100);
-destroyTH(myTable);    
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR tsh (1),
-.BR createTH (3),
-.BR searchTH (3),
-.BR addTH (3),
-.BR deleteTH (3),
-.BR displayTH(3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/destroyauth2table.3 b/alliance/share/man/man3/destroyauth2table.3
deleted file mode 100644
index 3d46b4ac..00000000
--- a/alliance/share/man/man3/destroyauth2table.3
+++ /dev/null
@@ -1,51 +0,0 @@
-.\"   $Id: destroyauth2table.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)destroyauth2table.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH DESTROYAUTH2TABLE 3 "October 1, 1997" "ASIM/LIP6" "AUT FUNCTIONS"
-.SH NAME
-destroyauth2table \- destroys an hash table with two keys.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-void destroyauth2table( HashTable )
-  auth2table \(**HashTable;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIHashTable\fP
-Pointer to the hash table to destroy.
-.SH DESCRIPTION
-\fBdestroyauth2table\fP destroys an hash table.
-.br
-.SH RETURN VALUE
-\fBdestroyauth2table\fP returns nothing.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-   auth2table \(**HashTable;
-   HashTable = createauth2table( 1000 );
-   ...
-   destroyauth2table( HashTable );
-.ft R
-.fi
-.SH SEE ALSO
-.BR aut (1)
-.BR createauth2table(3),
-.BR resetauth2table(3),
-.BR addauth2elem(3),
-.BR searchauth2elem(3),
-.BR delauth2elem(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/destroyauthtable.3 b/alliance/share/man/man3/destroyauthtable.3
deleted file mode 100644
index 3e1e607a..00000000
--- a/alliance/share/man/man3/destroyauthtable.3
+++ /dev/null
@@ -1,51 +0,0 @@
-.\"   $Id: destroyauthtable.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)destroyauthtable.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH DESTROYAUTHTABLE 3 "October 1, 1997" "ASIM/LIP6" "AUT FUNCTIONS"
-.SH NAME
-destroyauthtable \- destroys a simple hash table.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-void destroyauthtable( HashTable )
-  authtable \(**HashTable;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIHashTable\fP
-Pointer to the hash table to destroy.
-.SH DESCRIPTION
-\fBdestroyauthtable\fP destroys an hash table.
-.br
-.SH RETURN VALUE
-\fBdestroyauthtable\fP returns nothing.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-   authtable \(**HashTable;
-   HashTable = createauthtable( 1000 );
-   ...
-   destroyauthtable( HashTable );
-.ft R
-.fi
-.SH SEE ALSO
-.BR aut (1)
-.BR createauthtable(3),
-.BR resetauthtable(3),
-.BR addauthelem(3),
-.BR searchauthelem(3),
-.BR delauthelem(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/destroybddassoc.3 b/alliance/share/man/man3/destroybddassoc.3
deleted file mode 100644
index 7868cced..00000000
--- a/alliance/share/man/man3/destroybddassoc.3
+++ /dev/null
@@ -1,77 +0,0 @@
-.\"   $Id: destroybddassoc.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)destroybddassoc.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH DESTROYBDDASSOC 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-destroybddassoc \- frees all the variable associations.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddassoc \(**destroybddassoc( BddSystem )
-  bddsystem  \(**BddSystem;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.SH DESCRIPTION
-\fBdestroybddassoc\fP frees all the variable associations in the \fBbdd\fP system
-\fIBddSystem\fP.  If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBdestroybddassoc\fP returns nothing.
-.SH ERRORS
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   bddnode    \(**BddSubst;
-   bddnode    \(**BddVariable;
-   bddassoc   \(**Assoc;
-   chain_list \(**Expr;
-   bddvar         Variable;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   Expr = createablbinexpr( ABL_AND,
-                            createablatom( "i0" ),
-                            createablatom( "i1" ) );
-   BddNode = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   Expr = createablbinexpr( ABL_OR,
-                            createablatom( "i2" ),
-                            createablatom( "i3" ) );
-   BddSubst = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   BddVariable = searchbddcircuitin( (bddcircuit \(**)0, "i0" );
-   Variable = getbddvarbyindex( (bddsystem \(**)0, BddVariable->INDEX );
-   Assoc = addbddassoc( (bddsystem \(**)0 );
-   addbddnodeassoc( (bddsystem \(**)0, Assoc, Variable, BddSubst );
-   BddNode = substbddnodeassoc( (bddsystem \(**)0, BddSubst, Assoc );
-   delbddassoc( (bddsystem \(**)0, Assoc );
-   Expr = convertbddcircuitabl( BddCircuit, BddNode );
-   /* displays ((i3 or i2) and i1) */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddassoc( (bddsystem \(**)0 );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/destroybddcircuit.3 b/alliance/share/man/man3/destroybddcircuit.3
deleted file mode 100644
index 1f798db9..00000000
--- a/alliance/share/man/man3/destroybddcircuit.3
+++ /dev/null
@@ -1,50 +0,0 @@
-.\"   $Id: destroybddcircuit.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)destroybddcircuit.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH DESTROYBDDCIRCUIT 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-destroybddcircuit \- destroys a \fBbdd\fP circuit.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
- void destroybddcircuit( BddCircuit )
-  bddcircuit \(**BddCircuit;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddCircuit\fP
-The \fBbdd\fP circuit to destroy.
-.SH DESCRIPTION
-\fBdestroybddcircuit\fP destroys the \fBbdd\fP circuit \fIBddCircuit\fP.
-If a null pointer is given, the default \fBbdd\fP circuit is used.
-.br
-.SH RETURN VALUE
-\fBdestroybddcircuit\fP returns nothing.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   ...
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/destroybddsystem.3 b/alliance/share/man/man3/destroybddsystem.3
deleted file mode 100644
index 92cdf4fd..00000000
--- a/alliance/share/man/man3/destroybddsystem.3
+++ /dev/null
@@ -1,47 +0,0 @@
-.\"   $Id: destroybddsystem.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)destroybddsystem.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH DESTROYBDDSYSTEM 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-destroybddsystem \- destroys a \fBbdd\fP system.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-  void destroybddsystem( BddSystem )
-  bddsystem \(**BddSystem;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system to destroy.
-.SH DESCRIPTION
-\fBdestroybddsystem\fP destroys the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBdestroybddsystem\fP returns nothing.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem \(**BddSystem;
-   BddSystem = createbddsystem( 100, 1000, 100, 50000 );
-   ...
-   destroybddsystem( (bddsystem \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/destroyrdswindow.3 b/alliance/share/man/man3/destroyrdswindow.3
deleted file mode 100644
index babbb92d..00000000
--- a/alliance/share/man/man3/destroyrdswindow.3
+++ /dev/null
@@ -1,80 +0,0 @@
-.\"   $Id: destroyrdswindow.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)destroyrdswindow.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-destroyrdswindow
-.XE
-.XS0 \n%
-.ti 0.2i
-destroyrdswindow
-.XE0 \}
-.TH DESTROYRDSWINDOW 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-destroyrdswindow \- destroys windowing of a figure
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rwinnn.h"
-void destroyrdswindow( Figure, RdsWindow )
-  rdsfig_list \(**Figure;
-  rdswindow   \(**RdsWindow;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIFigure\fP
-The figure where has to be destroyed the windowing.
-.TP
-\fIRdsWindow\fP
-Pointer to the head of windowing (rdswindow structure) to destroy.
-.SH DESCRIPTION
-The \fIdestroyrdswindow\fP function destroys the windowing applied to a figure and built with the \fIbuildrdswindow\fP function.
-.SH RETURN VALUE
-nothing
-.SH ERRORS
-none
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mphnnn.h"
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rfmnnn.h"
-        #include "rwinnn.h"
-        #include "rtlnnn.h"
-        main()
-          {
-            phfig_list  \(**MbkFigure;
-            rdsfig_list \(**RdsFigure;
-            rdswindow   \(**Window;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            MbkFigure = getphfig("na2_y",'A');
-            RdsFigure = figmbkrds(MbkFigure,0,0);
-            Window    =  buildrdswindow ( RdsFigure );
-            . . .
-            /\(** \(**/ \fBdestroyrdswindow\fP ( RdsFigure, Window );
-            . . .
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librwi,
-.BR buildrdswindow,
-.BR allocrdswindow,
-.BR viewrdswindow
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/devXor2Expr.3 b/alliance/share/man/man3/devXor2Expr.3
deleted file mode 100644
index f6ffef0b..00000000
--- a/alliance/share/man/man3/devXor2Expr.3
+++ /dev/null
@@ -1,50 +0,0 @@
-.\"   $Id: devXor2Expr.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)devXor2Expr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH DEVXOR2EXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBdevXor2Expr\fP \- converts XOR 2 to OR-AND 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-chain_list *devXor2Expr(expr)
-chain_list *expr;
-.fi
-.SH PARAMETER
-.TP 20
-\fIexpr\fP
-XOR expression 
-.SH DESCRIPTION
-\fBdevXor2Expr()\fP removes XOR 2 at the first level by applying the rule :
-.br
-.TP
-(XOR a b) --> (OR (AND a (NOT b)) (AND (NOT a) b))
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr1,*expr2; 
-
-/* let's suppose that expr1 = (XOR a b) */
-
-expr2 = devXor2Expr(expr1); 
-displayExpr(expr2);
-/* it will display
-(OR (AND a (NOT b)) (AND (NOT a) b))
-*/
-freeExpr(expr1);
-freeExpr(expr2);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR devXorExpr (3),
-.BR simplifNotExpr (3),
-.BR notExpr (3),
-.BR flatPolarityExpr (3),
-.BR flatArityExpr (3),
-.BR sortExpr(3),
-.BR normExpr(3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/devXorExpr.3 b/alliance/share/man/man3/devXorExpr.3
deleted file mode 100644
index 2461dce4..00000000
--- a/alliance/share/man/man3/devXorExpr.3
+++ /dev/null
@@ -1,48 +0,0 @@
-.\"   $Id: devXorExpr.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)devXorExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH DEVXOREXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBdevXorExpr\fP \- removes XOR in an expression 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-chain_list *devXorExpr(expr)
-chain_list *expr;
-.fi
-.SH PARAMETER
-.TP 20
-\fIexpr\fP
-expression to convert
-.SH DESCRIPTION
-\fBdevXorExpr()\fP removes XOR in \fIexpr\fP by recursively calling the \fBdevXor2Expr()\fP function. 
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr1,*expr2; 
-
-/* let's suppose that expr1 = (XOR a b c) */
-
-expr2 = devXorExpr(expr1); 
-displayExpr(expr2);
-/* it will display
-(OR (AND (NOT a) (OR (AND b (NOT c)) (AND (NOT b) c)))
-    (AND a (NOT (OR (AND b (NOT c)) (AND (NOT b) c)))))  
-*/
-freeExpr(expr1);
-freeExpr(expr2);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR devXor2Expr (3),
-.BR simplifNotExpr (3),
-.BR notExpr (3),
-.BR flatPolarityExpr (3),
-.BR flatArityExpr (3),
-.BR sortExpr(3),
-.BR normExpr(3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/devablxorexpr.3 b/alliance/share/man/man3/devablxorexpr.3
deleted file mode 100644
index 056876fa..00000000
--- a/alliance/share/man/man3/devablxorexpr.3
+++ /dev/null
@@ -1,51 +0,0 @@
-.\"   $Id: devablxorexpr.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)devablxorexpr.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH DEVABLXOREXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-devablxorexpr \- develops 'xor', 'nxor' in an expression.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-chain_list \(**devablxorexpr( Expr )
-  chain_list \(**Expr;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIExpr\fP
-Expression to develop.
-.SH DESCRIPTION
-\fBdevablxorexpr\fP develops 'xor' or 'xnor' in \fIExpr\fP.
-The expression pointer \fIExpr\fP MUSTN'T be used after the call to this function.
-.br
-.SH RETURN VALUE
-\fBdevablxorexpr\fP returns a pointer to the modified expression.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-  chain_list \(**Expr;
-  Expr = createablbinexpr( ABL_XOR,
-                           createablatom( "a" ),
-                           createablatom( "b" ) );
-  Expr = devablxorexpr( Expr );
-  /* displays (a and (not b)) or ((not a) and b) */
-  viewablexpr( Expr, ABL_VIEW_VHDL );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1),
-.BR devdupablxorexpr(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/devdupablxorexpr.3 b/alliance/share/man/man3/devdupablxorexpr.3
deleted file mode 100644
index 34fd14fd..00000000
--- a/alliance/share/man/man3/devdupablxorexpr.3
+++ /dev/null
@@ -1,51 +0,0 @@
-.\"   $Id: devdupablxorexpr.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)devdupablxorexpr.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH DEVDUPABLXOREXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-devdupablxorexpr \- duplicates and develops 'xor', 'nxor'.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-chain_list \(**devdupablxorexpr( Expr )
-  chain_list \(**Expr;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIExpr\fP
-Expression to develop.
-.SH DESCRIPTION
-\fBdevdupablxorexpr\fP develops 'xor' or 'xnor' in \fIExpr\fP.
-.br
-.SH RETURN VALUE
-\fBdevdupablxorexpr\fP returns a pointer to the modified expression.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-  chain_list \(**Expr1;
-  chain_list \(**Expr2;
-  Expr1 = createablbinexpr( ABL_XOR,
-                            createablatom( "a" ),
-                            createablatom( "b" ) );
-  Expr2 = devdupablxorexpr( Expr1 );
-  /* displays (a and (not b)) or ((not a) and b) */
-  viewablexpr( Expr2, ABL_VIEW_VHDL );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1),
-.BR devdupablxorexpr(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/displayBdd.3 b/alliance/share/man/man3/displayBdd.3
deleted file mode 100644
index c664d6d2..00000000
--- a/alliance/share/man/man3/displayBdd.3
+++ /dev/null
@@ -1,66 +0,0 @@
-.\"   $Id: displayBdd.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)displayBdd.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH DISPLAYBDD 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBdisplayBdd\fP \- displays a BDD
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-void displayBdd(pBdd,level)
-pNode pBdd;
-int level;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIpBdd\fP
-BDD to display
-.TP 20
-\fIlevel\fP
-displaying level
-.SH DESCRIPTION
-\fBdisplayBdd()\fP displays \fIpBDD\fP. if \fIlevel= 1\fP, this function displays all the nodes of \fIpBdd\fP, if \fIlevel = 0\fP the function displays the root node of \fIpBdd\fP.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-pNode nodeA,nodeB,nodeC;
-pNode res;
-
-initializeBdd(SMALL_BDD);
-nodeA = createNodeTermBdd(3);
-nodeB = createNodeTermBdd(3);
-nodeC = createNodeTermBdd(4);
-
-res = applyBinBdd(OR,applyBinBdd(AND,nodeB,nodeC),nodeA);  
-		/* corresponding to  (OR (AND b c) a) */
-
-displayBdd(res,1);
-
-/* it will display 
-@res      INDEX = 4   LOW = @nodeA   HIGH = @inter1
-@nodeA    INDEX = 2   LOW = ZERO     HIGH = ONE
-@inter1   INDEX = 3   LOW = @nodeA   HIGH = ONE
-*/
-
-displayBdd(res,0);
-
-/* it will display 
-@res      INDEX = 4   LOW = @nodeA   HIGH = @inter1
-*/
-
-destroyBdd(1);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR createNodeTermBdd (3),
-.BR applyBinBdd (3),
-.BR applyBdd (3),
-.BR constraintBdd (3),
-.BR composeBdd (3),
-.BR addListBdd (3),
-.BR notBdd (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/displayCct.3 b/alliance/share/man/man3/displayCct.3
deleted file mode 100644
index 38e5a5f1..00000000
--- a/alliance/share/man/man3/displayCct.3
+++ /dev/null
@@ -1,65 +0,0 @@
-.\"   $Id: displayCct.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)displayCct.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH DISPLAYCCT 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBdisplayCct\fP \- displays a circuit 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-void displayCct(pC,mode)
-pCircuit pC;
-int mode;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIpC\fP
-circuit to display
-.TP 20
-\fImode\fP
-displaying mode
-.SH DESCRIPTION
-\fBdisplayCct()\fP displays on the screen all the informations concerning \fIpC\fP (number of inputs, index input, number of outputs, BDD associated). if \fImode = 0\fP the BDDs are display with the \fBdisplayBdd()\fP function, if it does, the BDDs are convert into ABLs and the ABL are displayed.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-pCircuit pC;
-chain_list *expr;
-
-displayBdd(SMALL_BDD);
-pC = initializeCct("circuit 1",10,10);
-
-addInputCct(pC,"a");
-addInputCct(pC,"b");
-
-	/* let's suppose that expr = (OR a b) */
-
-addOuputCct(pC,"s1",one);
-addOuputCct(pC,"s2",ablToBddCct(pC,expr));
-
-displayCct(pC,1)
-
-/* it will display 
-************* DISPLAY circuit 1 **********
-INPUT = a	INDEX = 2
-INPUT = b	INDEX = 3
---------- NUMBER OF INPUTS = 2
-OUTPUT = s1	s1 = 1
-OUTPUT = s2	s2 = (OR a b)
---------- NUMBER OF OUTPUTS = 2
-******************************************
-*/
-
-destroyCct(pC);
-destroyBdd(1);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR initializeCct (3),
-.BR resetCct (3),
-.BR destroyCct (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/displayExpr.3 b/alliance/share/man/man3/displayExpr.3
deleted file mode 100644
index 4ff94eae..00000000
--- a/alliance/share/man/man3/displayExpr.3
+++ /dev/null
@@ -1,59 +0,0 @@
-.\"   $Id: displayExpr.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)displayExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH DISPLAYEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBdisplayExpr\fP \- displays an expression in a prefixed notation. 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-void displayExpr(expr)
-chain_list *expr;
-.fi
-.SH PARAMETER
-.TP 20
-\fIexpr\fP
-Expression to display.
-.SH DESCRIPTION
-\fBdisplayExpr()\fP displays on the screen \fIexpr\fP in a prefixed notation. 
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr;
-expr = createExpr(OR);
-addQExpr(expr,createAtom("a"));
-addQExpr(expr,createAtom("b"));
-displayExpr(expr);
-/* it will display
-(OR a b)
-*/
-freeExpr(expr);
-.fi
-.SH PROGRAM
-.nf
-void displayExpr(expr)
-chain_list *expr;
-
-if (ATOM(expr))		/* atomic treatement */
-   printf(" %s",VALUE_ATOM(expr));
-else
-   {			/* go through the arguments */
-   printf("(%s",operToChar(OPER(expr)));
-   while (expr = CDR(expr))
-      displayExpr(CAR(expr));
-   printf(")");
-   }
-}
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR displayInfExpr (3),
-.BR exprToChar (3),
-.BR charToOper (3),
-.BR operToChar (3),
-.BR identExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/displayInfExpr.3 b/alliance/share/man/man3/displayInfExpr.3
deleted file mode 100644
index 52f38248..00000000
--- a/alliance/share/man/man3/displayInfExpr.3
+++ /dev/null
@@ -1,43 +0,0 @@
-.\"   $Id: displayInfExpr.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)displayInfExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH DISPLAYINFEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBdisplayInfExpr\fP \- displays an expression in infixed notation. 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-void displayInfExpr(expr)
-chain_list *expr;
-.fi
-.SH PARAMETER
-.TP 20
-\fIexpr\fP
-Expression to display.
-.SH DESCRIPTION
-\fBdisplayInfExpr()\fP displays on the screen \fIexpr\fP in infixed notation. 
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr;
-expr = createExpr(OR);
-addQExpr(expr,createAtom("a"));
-addQExpr(expr,createAtom("b"));
-displayInfExpr(expr);
-/* it will display
-(a OR b)
-*/
-freeExpr(expr);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR displayExpr (3),
-.BR exprToChar (3),
-.BR charToOper (3),
-.BR operToChar (3),
-.BR identExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/displayTH.3 b/alliance/share/man/man3/displayTH.3
deleted file mode 100644
index e5937bc3..00000000
--- a/alliance/share/man/man3/displayTH.3
+++ /dev/null
@@ -1,48 +0,0 @@
-.\"   $Id: displayTH.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)displayTH.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH DISPLAYTH 3 "October 1, 1997" "ASIM/LIP6" "Hash table functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBdisplayTH\fP \- displays a hash table
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-void displayTH(pTable)
-pTH pTable;
-.fi
-.SH PARAMETER
-.TP 20
-\fIpTable\fP
-Hash table to be viewed.
-.SH DESCRIPTION
-\fBdisplayTH()\fP displays all items of \fIpTable\fP (index in the table, key and value). The key is displayed as a \fIchar *\fP and the value as an \fIint\fP.
-.SH EXAMPLE
-.nf
-#include "logmmm.h"
-pTH mytable; 
-mytable = createTH(100);
-addTH(mytable,namealloc("var1"),0);
-addTH(mytable,namealloc("var2"),1);
-displayTH(mytable);
-
-/* it will display
-
-============== DISPLAYTH =================
-Length = 100		         Count = 2
-==========================================
-index 	7	key	var2	value	1
-index 	91	key	var1	value	0
-==========================================
-*/
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR tsh (1),
-.BR destroyTH (3),
-.BR createTH(3).
-.BR searchTH (3),
-.BR addTH (3),
-.BR deleteTH (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/downstr.3 b/alliance/share/man/man3/downstr.3
deleted file mode 100644
index c13bf3f6..00000000
--- a/alliance/share/man/man3/downstr.3
+++ /dev/null
@@ -1,64 +0,0 @@
-.\"   $Id: downstr.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)downstr.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-downstr
-.XE
-.XS4 \n%
-.ti 0.2i
-downstr
-.XE4 \}
-.TH DOWNSTR 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-downstr \- convert a string to lower case
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-void downstr(s, t)
-char \(**s, \(**t;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIs\fP
-Pointer to the source string
-.TP
-\fIt\fP
-Pointer to the destination string
-.SH DESCRIPTION
-\fBdownstr\fP converts the \fIs\fP string to lower case in \fIt\fP.
-The space for \fIt\fP must be allocated by the caller, and be at least
-\fBstrlen(s) + 1\fP long.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-void cmp()
-{
-char \(**s = "PWET", t[5];
-	downstr(s, t);
-	if (strcmp(t, "pwet")) {
-		fprintf(stderr, "Downstr sucks, man");
-		EXIT();
-	}
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR upstr (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/dupablexpr.3 b/alliance/share/man/man3/dupablexpr.3
deleted file mode 100644
index 46eb08fe..00000000
--- a/alliance/share/man/man3/dupablexpr.3
+++ /dev/null
@@ -1,53 +0,0 @@
-.\"   $Id: dupablexpr.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)dupablexpr.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH DUPABLEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-dupablexpr \- duplicates an expression.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-chain_list \(**dupablexpr( Expr )
-  chain_list \(**Expr;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIExpr\fP
-Expression to duplicate.
-.SH DESCRIPTION
-\fBdupablexpr\fP duplicates the expression \fIExpr\fP.
-.br
-.SH RETURN VALUE
-\fBdupablexpr\fP returns the duplicated expression.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-  chain_list \(**ExprAorB;
-  chain_list \(**ExprAnorB;
-  ExprAorB = createabloper( ABL_OR );
-  addablhexpr( ExprAorB, createablatom( "a" ) );
-  addablhexpr( ExprAorB, createablatom( "b" ) );
-  ExprAnorB = createablnotexpr( dupablexpr( ExprAorB ) );
-  /* displays (a or b) (a nor b) */
-  viewablexpr( ExprAorB, ABL_VIEW_VHDL );
-  viewablexpr( ExprAnorB, ABL_VIEW_VHDL );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1),
-.BR delablexpr(3),
-.BR freeablexpr(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/equalExpr.3 b/alliance/share/man/man3/equalExpr.3
deleted file mode 100644
index ec11428c..00000000
--- a/alliance/share/man/man3/equalExpr.3
+++ /dev/null
@@ -1,58 +0,0 @@
-.\"   $Id: equalExpr.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)equalExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH EQUALEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBequalExpr\fP \- checks that two expressions are strictly equal 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-int equalExpr(expr1,expr2)
-chain_list *expr1,*expr2;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIexpr1\fP
-first expression
-.TP 20
-\fIexpr1\fP
-second expression
-.SH DESCRIPTION
-\fBequalExpr()\fP compares its arguments and returns 0 if \fIexpr1\fP and \fIexpr2\fP are differents, in any other case, 1 is returns.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr1,*expr2; 
-
-	/* let's suppose that 
-		expr1 = (OR (AND a b) c)
-		expr2 = (OR (AND a b) c) */
-
-printf("%d",equalExpr(expr1,expr2));
-/* it will display
-1
-*/
-freeExpr(expr2);
-expr2 = createExpr(OR);
-addQExpr(expr2,createAtom("b"));
-addQExpr(expr2,createAtom("a"));
-printf("%d",equalExpr(expr1,expr2));
-/* it will display
-0
-*/
-freeExpr(expr1);
-freeExpr(expr2);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR equalVarExpr (3),
-.BR searchExpr (3),
-.BR searchOperExpr (3),
-.BR lengthExpr (3),
-.BR profExpr (3),
-.BR numberAtomExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/equalVarExpr.3 b/alliance/share/man/man3/equalVarExpr.3
deleted file mode 100644
index 089caee3..00000000
--- a/alliance/share/man/man3/equalVarExpr.3
+++ /dev/null
@@ -1,60 +0,0 @@
-.\"   $Id: equalVarExpr.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)equalVarExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH EQUALVAREXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBequalVarExpr\fP \- checks that two expressions are syntactically equal 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-int equalVarExpr(expr1,expr2)
-chain_list *expr1,*expr2;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIexpr1\fP
-first expression
-.TP 20
-\fIexpr1\fP
-second expression
-.SH DESCRIPTION
-\fBequalVarExpr()\fP compares its arguments and returns 0 if \fIexpr1\fP and \fIexpr2\fP are syntactically different, in any other case, 1 is returned. Contrary to the \fBequalExpr()\fP function, atomic expressions aren't compared.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr1,*expr2; 
-
-	/* Let's suppose that
-		expr1 = (OR (AND a b) (XOR c d))
-		expr1 = (OR (AND f b) (XOR a t))
-	*/
-printf("%d",equalVarExpr(expr1,expr2));
-/* it will display
-1
-*/
-freeExpr(expr2);
-expr2 = createExpr(OR);
-addQExpr(expr2,createAtom("b"));
-addQExpr(expr2,createAtom("a"));
-addQExpr(expr2,createAtom("c"));
-printf("%d",equalVarExpr(expr1,expr2));
-/* it will display
-0
-*/
-freeExpr(expr1);
-freeExpr(expr2);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR equalExpr (3),
-.BR PMExpr (3),
-.BR searchExpr (3),
-.BR searchOperExpr (3),
-.BR lengthExpr (3),
-.BR profExpr (3),
-.BR numberAtomExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/everyExpr.3 b/alliance/share/man/man3/everyExpr.3
deleted file mode 100644
index e8e61414..00000000
--- a/alliance/share/man/man3/everyExpr.3
+++ /dev/null
@@ -1,44 +0,0 @@
-.\"   $Id: everyExpr.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)everyExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH EVERYEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBeveryExpr\fP \- returns the value of a logical AND applied on the results of the application of a function on the argument of an operator expression. 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-int everyExpr(func,expr)
-int (*func)();
-chain_list *expr;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIfunc\fP
-function to apply
-.TP 20
-\fIexpr\fP
-expression
-.SH DESCRIPTION
-\fBeveryExpr()\fP applies a boolean function \fIfunc()\fP to all th arguments of \fIexpr\fP and computes a logical AND. \fIfunc()\fP must be an \fIinteger\fP function that is false if 0 is returned and true otherwise and must have an expression as argument. 
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr;
-expr = createExpr(XOR);
-addQExpr(expr,createAtom("a"));
-addQExpr(expr,createAtom("b"));
-	/* \fIprofExpr\fP returns 0 when \fIexpr\fP is an atomic expression */
-if (everyExpr(profExpr,expr))
-   printf("expr is only made up of operator expressions");
-freeExpr(expr);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR anyExpr (3),
-.BR mapExpr (3),
-.BR mapCarExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/existbddnodeassocoff.3 b/alliance/share/man/man3/existbddnodeassocoff.3
deleted file mode 100644
index 3a3a079e..00000000
--- a/alliance/share/man/man3/existbddnodeassocoff.3
+++ /dev/null
@@ -1,90 +0,0 @@
-.\"   $Id: existbddnodeassocoff.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)existbddnodeassocoff.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH EXISTBDDNODEASSOCOFF 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-existbddnodeassocoff \- computes an existantial quantification.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddnode \(**existbddnodeassocoff( BddSystem, BddNode, BddAssoc )
-  bddsystem \(**BddSystem;
-  bddnode   \(**BddNode;
-  bddassoc  \(**BddAssoc;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIBddNode\fP
-The \fBbdd\fP node to treat.
-.TP
-\fIBddAssoc\fP
-The variable association.
-.SH DESCRIPTION
-\fBexistbddnodeassocoff\fP suppress in the \fBbdd\fP node \fIBddNode\fP complemented,
-all the variables associated with something in the variable association
-\fIBddAssoc\fP, in the \fBbdd\fP system \fIBddSystem\fP. 
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBexistbddnodeassocoff\fP returns the computed \fBbdd\fP node.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"bad variable association xxx, error !"
-.ft R
-.RS
-The \fIBddAssoc\fP parameter must a valid variable association.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   bddnode    \(**BddSubst;
-   bddnode    \(**BddVariable;
-   bddassoc   \(**Assoc;
-   chain_list \(**Expr;
-   bddvar         Variable;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   Expr = createablbinexpr( ABL_NAND,
-                            createablatom( "i0" ),
-                            createablatom( "i1" ) );
-   BddNode = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   BddVariable = searchbddcircuitin( (bddcircuit \(**)0, "i0" );
-   Variable = getbddvarbyindex( (bddsystem \(**)0, BddVariable->INDEX );
-   Assoc = addbddassoc( (bddsystem \(**)0 );
-   addbddnodeassoc( (bddsystem \(**)0, Assoc, Variable, BddSystem->ONE );
-   BddNode = existbddnodeassocoff( (bddsystem \(**)0, BddNode, Assoc );
-   Expr = convertbddcircuitabl( BddCircuit, BddNode );
-   /* displays (not i1) */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddassoc( (bddsystem \(**)0 );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/existbddnodeassocon.3 b/alliance/share/man/man3/existbddnodeassocon.3
deleted file mode 100644
index e9074fbb..00000000
--- a/alliance/share/man/man3/existbddnodeassocon.3
+++ /dev/null
@@ -1,90 +0,0 @@
-.\"   $Id: existbddnodeassocon.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)existbddnodeassocon.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH EXISTBDDNODEASSOCON 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-existbddnodeassocon \- computes an existantial quantification.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddnode \(**existbddnodeassocon( BddSystem, BddNode, BddAssoc )
-  bddsystem \(**BddSystem;
-  bddnode   \(**BddNode;
-  bddassoc  \(**BddAssoc;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIBddNode\fP
-The \fBbdd\fP node to treat.
-.TP
-\fIBddAssoc\fP
-The variable association.
-.SH DESCRIPTION
-\fBexistbddnodeassocon\fP suppress in \fIBddNode\fP,
-all the variables associated with something in the variable association
-\fIBddAssoc\fP, in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBexistbddnodeassocon\fP returns the computed \fBbdd\fP node.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"bad variable association xxx, error !"
-.ft R
-.RS
-The \fIBddAssoc\fP parameter must a valid variable association.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   bddnode    \(**BddSubst;
-   bddnode    \(**BddVariable;
-   bddassoc   \(**Assoc;
-   chain_list \(**Expr;
-   bddvar         Variable;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   Expr = createablbinexpr( ABL_AND,
-                            createablatom( "i0" ),
-                            createablatom( "i1" ) );
-   BddNode = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   BddVariable = searchbddcircuitin( (bddcircuit \(**)0, "i0" );
-   Variable = getbddvarbyindex( (bddsystem \(**)0, BddVariable->INDEX );
-   Assoc = addbddassoc( (bddsystem \(**)0 );
-   addbddnodeassoc( (bddsystem \(**)0, Assoc, Variable, BddSystem->ONE );
-   BddNode = existbddnodeassocon( (bddsystem \(**)0, BddNode, Assoc );
-   Expr = convertbddcircuitabl( BddCircuit, BddNode );
-   /* displays i1 */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddassoc( (bddsystem \(**)0 );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/exprToChar.3 b/alliance/share/man/man3/exprToChar.3
deleted file mode 100644
index f725ecf5..00000000
--- a/alliance/share/man/man3/exprToChar.3
+++ /dev/null
@@ -1,50 +0,0 @@
-.\"   $Id: exprToChar.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)exprToChar.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH EXPRTOCHAR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBexprToChar\fP \- converts an expression into a string 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-char *exprToChar(expr,mode)
-chain_list *expr;
-int mode;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIexpr\fP
-Expression to convert. 
-.TP 20
-\fImode\fP
-Infixed or prefixed.
-.SH DESCRIPTION
-\fBexprToChar()\fP converts \fIexpr\fP into a string. if \fImode = 0\fP, the function is in a prefixed notation mode, if \fImode = 1\fP then in infixed notation mode.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr;
-expr = createExpr(OR);
-addQExpr(expr,createAtom("a"));
-addQExpr(expr,createAtom("b"));
-printf("%s",exprToChar(expr,1));
-printf("%s",exprToChar(expr,0));
-/* it will display
-(a OR b)
-(OR a b)
-*/
-freeExpr(expr);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR charToExpr (3),
-.BR displayExpr (3),
-.BR displayInfExpr (3),
-.BR charToOper (3),
-.BR operToChar (3),
-.BR identExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/figmbkrds.3 b/alliance/share/man/man3/figmbkrds.3
deleted file mode 100644
index 2274999a..00000000
--- a/alliance/share/man/man3/figmbkrds.3
+++ /dev/null
@@ -1,92 +0,0 @@
-.\"   $Id: figmbkrds.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)figmbkrds.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-figmbkrds
-.XE
-.XS0 \n%
-.ti 0.2i
-figmbkrds
-.XE0 \}
-.TH FIGMBKRDS 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
- figmbkrds \- converts MBK figure to RDS figure
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rfmnnn.h"
-rdsfig_list \(**figmbkrds( FigureMbk, Size, Lynx )
-   phfig_list   \(**FigureMbk;
-   unsigned int  Size;
-   char          Lynx;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIFigureMbk\fP
-Figure Mbk to convert to RDS figure.
-.TP
-\fISize\fP
-Size of the user structure (if it exists) added to the rdsrec_list structure. If the user structure doesn't exist, the parameter 'Size' has to be set to 0L.
-.TP
-\fILynx\fP
-Flag used for the segment conversion. If the parameter Lynx is set to 0 then this is the
-normal conversion mode. If the parameter Lynx is set to 1 then the rds structure generated permits to extract equipotentials rectangles.
-.SH DESCRIPTION
-The \fIfigmbkrds\fP function creates a RDS figure with a figure from MBK structure \fIphfig_list\fP which is converted to RDS format.
-.SH RETURN VALUE
-The pointer to the newly created RDS figure.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Rds202: rdsalloc error, can't continue !"
-.ft R
-.RS
-it's impossible to allocate the memory size desired
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mphnnn.h"
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rfmnnn.h"
-        #include "rtlnnn.h"
-        typedef struct UserStruct
-         {
-           char \(**STRING;
-           void \(**USER1;
-         } UserStruct;
-        main()
-          {
-            phfig_list  \(**MbkFigure;
-            rdsfig_list \(**RdsFigure;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            MbkFigure        = getphfig("na2_y",'A'); 
-            RdsFigure        = \fBfigmbkrds\fP (MbkFigure,sizeof(UserStruct),0);
-            viewrdsfig ( RdsFigure );
-            . . .
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librfm,
-.BR viewrfmfig,
-.BR loadrdsparam
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/filepath.3 b/alliance/share/man/man3/filepath.3
deleted file mode 100644
index 3fc20918..00000000
--- a/alliance/share/man/man3/filepath.3
+++ /dev/null
@@ -1,81 +0,0 @@
-.\"   $Id: filepath.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)filepath.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-filepath
-.XE
-.XS4 \n%
-.ti 0.2i
-filepath
-.XE4 \}
-.TH FILEPATH 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-filepath \- return the whole search path of a file
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-char \(**filepath(name, extension)
-char \(**name, \(**extension;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIname\fP
-Name of the file to be search for
-.TP
-\fIextension\fP
-File extension
-.SH DESCRIPTION
-\fBfilepath\fP return the absolute path of a cell.
-This is useful for error messages, since the caller of mbk file functions
-is not able to specify explicitly which file it opened.
-Having such an information is also necessary when last modification times or
-access times are needed, as for consistency checks.
-The file is searched through the environment variable \fBMBK_WORK_LIB\fP(1),
-and if not found, through \fBMBK_CATA_LIB\fP(1) in the user defined order.
-.br
-The file to be searched is called \fIname.extension\fP, if extension is not
-\fBNULL\fP, else it is \fIname\fP. If \fIextension\fP is the empty string,
-\fB""\fP, then the file name will be \fIname.\fP\ .
-.br
-.SH RETURN VALUE
-\fBfilepath\fP returns \fBNULL\fP on failure, ie the file is not in the pathes,
-or the absolute path on success.
-The value returned, when not \fBNULL\fP, is stored in a \fBstatic\fP buffer,
-so this values is to use at return time or copied into a user buffer.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <stdio.h>
-#include "mut315.h"
-#include "mph315.h"
-void vti_error(fig, error)
-phfig_list \(**fig;
-char *(*error)();
-{
-		fprintf(stderr, "Syntax error in %s\\n", filepath(fig->NAME, "cp"));
-		fprintf(stderr, "%s\\n", error());
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR MBK_WORK_LIB (1),
-.BR MBK_CATA_LIB (1),
-.BR mbkfopen (3).
-.BR mbkunlink (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/flatArityExpr.3 b/alliance/share/man/man3/flatArityExpr.3
deleted file mode 100644
index f7250b71..00000000
--- a/alliance/share/man/man3/flatArityExpr.3
+++ /dev/null
@@ -1,55 +0,0 @@
-.\"   $Id: flatArityExpr.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)flatArityExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH FLATARITYEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBflatArityExpr\fP \- flattens the operators of an expression
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-void *latArityExpr(expr)
-chain_list *expr;
-.fi
-.SH PARAMETER
-.TP 20
-\fIexpr\fP
-expression to flatten
-.SH DESCRIPTION
-\fBflatArityExpr()\fP removes the useless operators. This function doesn't make any simplifications.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr1,*expr2,*expr3; 
-expr1 = createExpr(OR);
-addQExpr(expr1,createAtom("a"));
-addQExpr(expr1,createAtom("b"));
-expr2 = createExpr(OR);
-addQExpr(expr2,createAtom("a"));
-addQExpr(expr2,createAtom("c"));
-addQExpr(expr1,expr2);
-expr3 = copyExpr(expr1);
-flatArityExpr(expr3);
-displayExpr(expr1);
-displayExpr(expr3);
-/* it will display
-(OR a b (OR a c))
-(OR a b a c)
-*/
-freeExpr(expr1);
-freeExpr(expr3);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR flatPolarityExpr (3),
-.BR copyExpr (3),
-.BR substExpr (3),
-.BR substPhyExpr (3),
-.BR maxExpr (3),
-.BR minExpr (3),
-.BR sortExpr (3),
-.BR normExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/flatPolarityExpr.3 b/alliance/share/man/man3/flatPolarityExpr.3
deleted file mode 100644
index 0bb65106..00000000
--- a/alliance/share/man/man3/flatPolarityExpr.3
+++ /dev/null
@@ -1,65 +0,0 @@
-.\"   $Id: flatPolarityExpr.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)flatPolarityExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH FLATPOLARITYEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBflatPolarityExpr\fP \- translates the inverters of an expression to the level of atomic expressions 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-chain_list *flatPolarityExpr(expr,sign)
-chain_list *expr;
-int sign;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIexpr\fP
-expression to transform
-.TP 20
-\fIsign\fP
-expression or expression inverted
-.SH DESCRIPTION
-\fBflatPolarityExpr()\fP creates a new ABL in which inverters are translated to the level of atomic expressions by applying Morgan's laws and simplification law. If \fIsign = 0\fP the function returns the transformed expression after having complemented it.
-.nf
-\fITranformation law\fP
-- (NOT (NOT a))   --> a
-- (NOT (AND a b)) --> (OR (NOT a) (NOT b))
-- (NOT (OR a b))  --> (AND (NOT a) (NOT b))
-.fi
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr1,*expr2,*expr3; 
-expr1 = createExpr(OR);
-addQExpr(expr1,createAtom("a"));
-addQExpr(expr1,createAtom("b"));
-expr1 = notExpr(expr1);
-expr2 = flatPolarityExpr(expr1,0);
-expr3 = flatPolarityExpr(expr1,1);
-displayExpr(expr1);
-displayExpr(expr2);
-displayExpr(expr3);
-/* it will display
-(NOT (OR a b))
-(AND (NOT a) (NOT b))
-(OR a b)
-*/
-freeExpr(expr1);
-freeExpr(expr2);
-freeExpr(expr3);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR copyExpr (3),
-.BR substExpr (3),
-.BR substPhyExpr (3),
-.BR flatArityExpr (3),
-.BR maxExpr (3),
-.BR minExpr (3),
-.BR sortExpr (3),
-.BR normExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/flatablexpr.3 b/alliance/share/man/man3/flatablexpr.3
deleted file mode 100644
index a4115316..00000000
--- a/alliance/share/man/man3/flatablexpr.3
+++ /dev/null
@@ -1,56 +0,0 @@
-.\"   $Id: flatablexpr.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)flatablexpr.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH FLATABLEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-flatablexpr \- merges the operators of an expression
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-void flatablexpr( Expr )
-  chain_list \(**Expr;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIExpr\fP
-Expression to flat.
-.SH DESCRIPTION
-\fBflatablexpr\fP merges all the common operators in \fIExpr\fP.
-.br
-.SH RETURN VALUE
-\fBflatablexpr\fP returns nothing.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-  chain_list \(**Expr1;
-  chain_list \(**Expr2;
-  Expr1 = createbinexpr( ABL_OR, 
-                         createablatom( "a" ),
-                         createablatom( "b" ) );
-  Expr2 = createabloper( ABL_OR );
-  addablhexpr( Expr2, createablatom( "c" ) );
-  addablhexpr( Expr2, Expr1 );
-  Expr1 = dupablexpr( Expr2 );
-  flatablexpr( Expr1 );
-  /* displays ((a or b) or c) (a or b or c) */
-  viewablexpr( Expr2, ABL_VIEW_VHDL );
-  viewablexpr( Expr1, ABL_VIEW_VHDL );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1),
-.BR unflatablexpr(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/flattenlofig.3 b/alliance/share/man/man3/flattenlofig.3
deleted file mode 100644
index f4061234..00000000
--- a/alliance/share/man/man3/flattenlofig.3
+++ /dev/null
@@ -1,87 +0,0 @@
-.\"   $Id: flattenlofig.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)flattenlofig.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-flattenlofig
-.XE
-.XS3 \n%
-.ti 0.2i
-flattenlofig
-.XE3 \}
-.TH FLATTENLOFIG 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL UTILITY FUNCTIONS"
-.SH NAME
-flattenlofig \- flatten a instance in a logical figure 
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo412.h"
-void flattenlofig(ptfig, insname, concat)
-lofig_list \(**ptfig;
-char \(**insname;
-char concat;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptfig\fP
-Pointer to a logical figure
-.TP
-\fIinsname\fP
-Name of the instance to be flattened
-.TP
-\fIconcat\fP
-Name generation mode
-.SH DESCRIPTION
-\fBflattenlofig\fP flattens the instance called \fIinsname\fP in the figure
-pointed to by \fIptfig\fP. Flattening means incorporating the
-contents of the instance in the figure and removing it from its instance list.
-.br
-the \fIconcat\fP argument can take either the value \fBYES\fP in which case the
-name of the objects comming from the instance are named
-\fIinsname'X'objectname\fP, where \fI'X'\fP is the caracter set int the
-\fBMBK_SEPAR\fP(1) environment variable, or the value \fBNO\fP, and then the
-object name remains inchanged. This is quite dangerous since name unicity is
-no more warrantied, and may cause the flatten to fail. See \fBMBK_SEPAR\fP(1),
-\fBmbkenv\fP(3) and \fBconcatname\fP(3) for details.
-.SH ERRORS
-No errors can directly result from a call to \fBflattenlofig\fP, but since it
-uses many other mbk functions, it may be an error starting point.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo412.h"
-void flatten_na2_y_s(ptfig)
-lofig_list \(**ptfig;
-{
-loins_list \(**pt;
-	for (pt = ptfig\->LOINS; pt; pt = pt\->NEXT) /\(** scan instance list \(**/
-		if (!strcmp(pt\->FIGNAME, "na2_y"))
-			flattenlofig(ptfig, pt\->INSNAME, NO);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR mbkenv (3),
-.BR lofig (3),
-.BR addlofig (3),
-.BR getlofig (3),
-.BR dellofig (3),
-.BR loadlofig (3),
-.BR savelofig (3),
-.BR rflattenlofig (3),
-.BR MBK_SEPAR (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/flattenphfig.3 b/alliance/share/man/man3/flattenphfig.3
deleted file mode 100644
index c70cc71a..00000000
--- a/alliance/share/man/man3/flattenphfig.3
+++ /dev/null
@@ -1,87 +0,0 @@
-.\"   $Id: flattenphfig.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)flatenphfig.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-flattenphfig
-.XE
-.XS1 \n%
-.ti 0.2i
-flattenphfig
-.XE1 \}
-.TH FLATTENPHFIG 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL UTILITY FUNCTIONS"
-.SH NAME
-flatenphfig \- flatten a instance in a figure 
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph403.h"
-void flatenphfig(ptfig, insname, concat)
-phfig_list \(**ptfig;
-char \(**insname;
-char concat;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptfig\fP
-Pointer to a physical figure
-.TP
-\fIinsname\fP
-Name of the instance to be flattened
-.TP
-\fIconcat\fP
-Name generation mode
-.SH DESCRIPTION
-\fBflatenphfig\fP flattens the instance called \fIinsname\fP in the figure
-pointed to by \fIptfig\fP. Flattening means incorporating the
-contents of the instance in the figure and removing it from its instance list.
-.br
-the \fIconcat\fP argument can take either the value \fBYES\fP in which case the
-name of the object comming from the instance are named
-\fIinsname'X'objectname\fP, where \fI'X'\fP is the caracter set int the
-\fBMBK_SEPAR\fP(1) environment variable, or the value \fBNO\fP, and then the
-object name remains inchanged. This is quite dangerous since name unicity is
-no more warrantied, and may cause the flatten to fail. See \fBMBK_SEPAR(1)\fP,
-\fBmbkenv(3)\fP and \fBconcatname(3)\fP for details.
-.SH ERRORS
-No errors can directly result from a call to \fBflatenphfig\fP, but since it
-uses many other mbk functions, it may be an error starting point.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph403.h"
-void flatten_na2_y_s(ptfig)
-phfig_list \(**ptfig;
-{
-phins_list \(**pt;
-	for (pt = ptfig\->PHINS; pt; pt = pt\->NEXT) /\(** scan instance list \(**/
-		if (!strcmp(pt\->FIGNAME, "na2_y"))
-			flatenphfig(ptfig, pt\->INSNAME, NO);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR mbkenv (3),
-.BR phfig (3),
-.BR addphfig (3),
-.BR getphfig (3),
-.BR delphfig (3),
-.BR loadphfig (3),
-.BR savephfig (3),
-.BR rflatenphfig (3),
-.BR MBK_SEPAR (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/freeExpr.3 b/alliance/share/man/man3/freeExpr.3
deleted file mode 100644
index cccbd76f..00000000
--- a/alliance/share/man/man3/freeExpr.3
+++ /dev/null
@@ -1,40 +0,0 @@
-.\"   $Id: freeExpr.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)freeExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH FREEEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBfreeExpr\fP \- frees an expression. 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-void freeExpr(expr)
-chain_list *expr;
-.fi
-.SH PARAMETER
-.TP 20
-\fIexpr\fP
-Expression to free.
-.SH DESCRIPTION
-\fBfreeExpr()\fP frees an expression (operator expression or atomic expression) by giving back to MBK allocator system all the \fIchain_list\fP doublets used in \fPexpr\fP. It's very important to call \fIfreeExpr\fP as often as possible to minimize memory use. Many functions like \fBcopyExpr()\fP or \fBflatPolarityExpr()\fP create new ABLs , so great care should be taken concerning memory allocation problems. For each example given in this documentation, the \fBfreeExpr()\fP function is called as often as possible.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr; 
-expr = createExpr(OR);
-addHExpr(expr,createAtom("var1"));
-addHExpr(expr,createAtom("var2"));
-freeExpr(expr);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR createAtom (3),
-.BR createExpr(3),
-.BR notExpr (3),
-.BR createBinExpr (3),
-.BR addQExpr (3),
-.BR addHExpr(3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/freeablexpr.3 b/alliance/share/man/man3/freeablexpr.3
deleted file mode 100644
index 548ea9ef..00000000
--- a/alliance/share/man/man3/freeablexpr.3
+++ /dev/null
@@ -1,54 +0,0 @@
-.\"   $Id: freeablexpr.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)freeablexpr.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH FREEABLEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-freeablexpr \- frees an expression. 
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-  void freeablexpr( Expr )
-   chain_list \(**Expr;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIExpr\fP
-Expression to free.
-.SH DESCRIPTION
-\fBfreeablexpr\fP frees the expression \fIExpr\fP even if
-this expression is not a valid one.
-.br
-.SH RETURN VALUE
-\fBfreeablexpr\fP returns nothing.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-   chain_list \(**ExprA;
-   chain_list \(**ExprB;
-   chain_list \(**ExprAorB;
-   ExprA = createablatom( "a" );
-   ExprB = createablatom( "b" );
-   ExprAorB  = createablbinexpr( ABL_OR, ExprA, ExprB );
-   ...
-   freeablexpr( ExprAorB );
-   ExprAorB = (chain_list \(**)0;
-   ...
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1)
-.BR delablexpr(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/freechain.3 b/alliance/share/man/man3/freechain.3
deleted file mode 100644
index cd0311b7..00000000
--- a/alliance/share/man/man3/freechain.3
+++ /dev/null
@@ -1,63 +0,0 @@
-.\"   $Id: freechain.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)freechain.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-freechain
-.XE
-.XS4 \n%
-.ti 0.2i
-freechain
-.XE4 \}
-.TH FREECHAIN 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-freechain \- free a \fBchain_list\fP
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-void freechain(pt)
-chain_list \(**pt;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIpt\fP
-Pointer to the \fBchain\fP list to be freed
-.SH DESCRIPTION
-\fBfreechain\fP frees the \fBchain_list\fP pointed to by \fIpt\fP.
-All the elements of the list are put back in the list of free blocks.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-void free_from(c, i) /\(** erase list from ith element \(**/
-chain_list \(**c;
-int i;
-{
-chain_list \(**t;
-	while (i--)
-		c = c\->NEXT;
-	t = c\->NEXT, c\->NEXT = NULL;
-	freechain(t);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR chain (3),
-.BR addchain (3),
-.BR delchain (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/freelomodel.3 b/alliance/share/man/man3/freelomodel.3
deleted file mode 100644
index 4c872114..00000000
--- a/alliance/share/man/man3/freelomodel.3
+++ /dev/null
@@ -1,57 +0,0 @@
-.\"   $Id: freelomodel.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)freelomodel.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-freelomodel
-.XE
-.XS2 \n%
-.ti 0.2i
-freelomodel
-.XE2 \}
-.TH FREELOMODEL 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL FUNCTIONS"
-.SH NAME
-freelomodel \- free a \fBlofig_list\fP for temporary models
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-void freelomodel(ptmodel)
-lofig_list \(**ptmodel;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIptmodel\fP
-Pointer to the model list to be freed
-.SH DESCRIPTION
-\fBfreelomodel\fP free the \fBlofig_list\fP pointed to by \fIptmodel\fP.
-All the elements of the list are given back to the system.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-void end_of_parse() /\(** erase model list \(**/
-{
-	freelomodel(MODEL);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR lofig (3),
-.BR addlomodel (3),
-.BR getlomodel (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/freenum.3 b/alliance/share/man/man3/freenum.3
deleted file mode 100644
index 6a36326b..00000000
--- a/alliance/share/man/man3/freenum.3
+++ /dev/null
@@ -1,62 +0,0 @@
-.\"   $Id: freenum.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)freenum.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-freenum
-.XE
-.XS4 \n%
-.ti 0.2i
-freenum
-.XE4 \}
-.TH FREENUM 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-freenum \- free a \fBnum_list\fP
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-void freenum(pt)
-num_list \(**pt;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIpt\fP
-Pointer to the \fBnum\fP list to be freed
-.SH DESCRIPTION
-\fBfreenum\fP frees the \fBnum_list\fP pointed to by \fIpt\fP.
-All the elements of the list are put back in the list of free blocks.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-void free_from(c, i) /\(** erase list from ith element \(**/
-num_list \(**c;
-int i;
-{
-num_list \(**t;
-	while (i--)
-		c = c\->NEXT;
-	t = c\->NEXT, c\->NEXT = NULL;
-	freenum(t);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR num (3),
-.BR addnum (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/freeptype.3 b/alliance/share/man/man3/freeptype.3
deleted file mode 100644
index f4cbe87b..00000000
--- a/alliance/share/man/man3/freeptype.3
+++ /dev/null
@@ -1,64 +0,0 @@
-.\"   $Id: freeptype.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)freeptype.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-freeptype
-.XE
-.XS4 \n%
-.ti 0.2i
-freeptype
-.XE4 \}
-.TH FREEPTYPE 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-freeptype \- free a \fBptype_list\fP
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-ptype_list \(**freeptype(pt)
-ptype_list \(**pt;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIpt\fP
-Pointer to the ptype list to be freed
-.SH DESCRIPTION
-\fBfreeptype\fP frees the \fBptype_list\fP pointed to by \fIpt\fP.
-All the elements of the list are put back in the list of free blocks.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-void free_from(c, i) /\(** erase list from ith element \(**/
-ptype_list \(**c;
-int i;
-{
-ptype_list \(**t;
-	while (i--)
-		c = c\->NEXT;
-	t = c\->NEXT, c\->NEXT = NULL;
-	freeptype(t);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR ptype (3),
-.BR addptype (3),
-.BR getptype (3),
-.BR delptype (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/freerdsfig.3 b/alliance/share/man/man3/freerdsfig.3
deleted file mode 100644
index 9a21bb8a..00000000
--- a/alliance/share/man/man3/freerdsfig.3
+++ /dev/null
@@ -1,69 +0,0 @@
-.\"   $Id: freerdsfig.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)freerdsfig.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-freerdsfig
-.XE
-.XS0 \n%
-.ti 0.2i
-freerdsfig
-.XE0 \}
-.TH FREERDSFIG 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
- freerdsfig \- frees memory associated to a figure
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rdsnnn.h"
-void freerdsfig( Figure )
-  rdsfig_list \(**Figure;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIFigure\fP
-it's the pointer of the figure to be deleted.
-.SH DESCRIPTION
-This function free the memory associated to the figure. Memory place used by the Pointers of the rdsfig_list structure is not free so the user has to free these pointers before calling the freerdsfig function.
-.SH RETURN VALUE
-nothing
-.SH ERRORS
-none
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mutnnn.h"
-#include "rdsnnn.h"
-#include "rtlnnn.h"
-	    main()
-	     {
-	       rdsfig_list \(**Figure;
-               mbkenv();
-               rdsenv();
-               loadrdsparam();
-	       Figure = allocrdsfig ();
-	       Figure->NAME = rdsalloc(strlen("core")+1,RDS_ALLOC_BLOCK);
-	       strcpy(Figure->NAME,"core");
-	       ...
-	       rdsfree    (Figure->NAME,RDS_ALLOC_BLOCK); 
-	       /\(** \(**/ \fBfreerdsfig\fP ( Figure,RDS_ALLOC_BLOCK);
-	     }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librds,
-.BR allocrdsfig
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/freerdsins.3 b/alliance/share/man/man3/freerdsins.3
deleted file mode 100644
index 9024a21c..00000000
--- a/alliance/share/man/man3/freerdsins.3
+++ /dev/null
@@ -1,69 +0,0 @@
-.\"   $Id: freerdsins.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)freerdsins.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-freerdsins
-.XE
-.XS0 \n%
-.ti 0.2i
-freerdsins
-.XE0 \}
-.TH FREERDSINS 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
- freerdsins \- frees memory associated to an instance
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
- #include "rdsnnn.h"
- void freerdsins ( Instance )
-   rdsins_list \(**Instance;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
- \fIInstance\fP
-Pointer of the instance to free 
-.SH DESCRIPTION
-This function frees the memory associated to the instance. Memory place used by the Pointers of the rdsins_list structure is not free so the user has to free these pointers before calling the freerdsins() function.
-.SH RETURN VALUE
-nothing
-.SH ERRORS
-none
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-          #include "mutnnn.h"
-          #include "rdsnnn.h"
-          #include "rtlnnn.h"
-	    main()
-	     {
-	       rdsins_list \(**Instance;
-               mbkenv();
-               rdsenv();
-               loadrdsparam();
-	       Instance = allocrdsins ();
-	       Instance->NAME = rdsalloc(strlen("and1")+1,RDS_ALLOC_BLOCK);
-	       strcpy(Instance->NAME,"and1");
-	       ...
-	       rdsfree    (Instance->NAME,RDS_ALLOC_BLOCK); 
-	       /\(** \(**/ \fBfreerdsins\fP ( Instance,RDS_ALLOC_BLOCK);
-	     }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librds,
-.BR allocrdsins
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/freerdsrec.3 b/alliance/share/man/man3/freerdsrec.3
deleted file mode 100644
index c729b294..00000000
--- a/alliance/share/man/man3/freerdsrec.3
+++ /dev/null
@@ -1,76 +0,0 @@
-.\"   $Id: freerdsrec.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)freerdsrec.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-freerdsrec
-.XE
-.XS0 \n%
-.ti 0.2i
-freerdsrec
-.XE0 \}
-.TH FREERDSREC 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
- freerdsrec \- free memory associated to a rectangle
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
- #include "rdsnnn.h"
-  void freerdsrec( Rectangle, Size )
-    rdsrec_list  \(**Rectangle;
-    unsigned int  Size;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIRectangle\fP
-Pointer of the rectangle structure to free.
-.TP
-\fISize\fP
-Size of the structure added (if it exists) to rdsrec_list structure.
-.SH DESCRIPTION
-This function deletes the memory associated to the rectangle. Memory used is both memory of rdsrec_list structure and memory of the structure added by the user. If the user structure doesn't exist, the parameter \'Size\' must be to 0L. Memory place used by the Pointers of the rdsrec_list structure (and the added structure) is not deleted so the user has to free these pointers before calling the freerdsrec() function.
-.SH RETURN VALUE 
-nothing
-.SH ERRORS
-none
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-           #include "mutnnn.h"
-           #include "rdsnnn.h"
-           #include "rtlnnn.h"
-	    typedef struct UserStruct
-	     {
-	       char \(**STRING;
-	       void \(**USER1;
-	     } UserStruct;
-	    main()
-	     {
-	       rdsrec_list \(**Rectangle;
-               mbkenv();
-               rdsenv();
-               loadrdsparam();
-	       Rectangle = allocrdsrec ( sizeof ( UserStruct ) );
-	       ...
-	       /\(** \(**/ \fBfreerdsrec\fP ( Rectangle, sizeof ( UserStruct ) );            
-	     }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librds,
-.BR freerdsrec,
-.BR rdsfree
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/funbeaux.3 b/alliance/share/man/man3/funbeaux.3
deleted file mode 100644
index d92f4c01..00000000
--- a/alliance/share/man/man3/funbeaux.3
+++ /dev/null
@@ -1,106 +0,0 @@
-.\"   $Id: funbeaux.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)beaux.2 108 Feb 15 1995 UPCM ; Pirouz BAZARGAN SABET
-.TH FUNBEAUX 3 "October 1, 1997" "ASIM/LIP6" "BEH functions"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBbeh_addbeaux , beh_delbeaux , beh_rmvbeaux , beh_frebeaux\fP
-
-.SH SYNOPSYS
-.PP
-.nf
-struct beaux *beh_addbeaux (list, name, abl, bdd)
-struct beaux *list;
-char *name;
-struct chain *abl;
-struct node *bdd;
-
-struct beaux *beh_delbeaux (list, pnt, mode)
-struct beaux *list;
-struct beaux *pnt;
-char mode;
-
-struct beaux *beh_rmvbeaux (list, name, mode)
-struct beaux *list;
-char *name;
-char mode;
-
-void beh_frebeaux (list)
-struct beaux *list;
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIlist\fP
-pointer of a list of beaux structures
-.TP 10
-\fIname\fP
-name of the simple internal signal to be added to or removed from the list
-.TP 10
-\fIabl\fP
-the abl representing the expression of the simple internal signal
-.TP 10
-\fIbdd\fP
-the bdd representing the expression of the simple internal signal
-.TP 10
-\fIpnt\fP
-pointer of the beaux structure to be removed from the list
-.TP 10
-\fImode\fP
-recursive mode (Y or N)
-
-.SH DESCRIPTION
-.PP
-A beaux is a data structure representing a one\-bit simple internal signal.
-
-.PP
-\fBbeh_addbeaux()\fP adds a beaux structure at the top of a list of beaux
-structures. The name registred in the beaux structure is produced by
-\fBnamealloc()\fP. The function returns the pointer of the new list.
-No checks are made by this function.
-
-.PP
-\fBbeh_delbeaux()\fP deletes a beaux structure (pointed by \fIpnt\fP) from a
-list of beaux structures. The function returns the pointer of the new list.
-No action is made if the structure pointed by \fIpnt\fP doesn't belong to the
-list. If \fImode\fP is set to 'Y' all objects (abl) pointed by the beaux will
-also be removed. If \fImode\fP is set to 'N' and there is any object (abl)
-pointed by the beaux a warning message is printed on the standard error output.
-
-.PP
-\fBbeh_rmvbeaux()\fP deletes a beaux structure (named \fIname\fP) from a list
-of beaux structures. \fIname\fP is supposed to be produced by \fBnamealloc()\fP.
-The function returns the pointer of the new list. No action is made if the
-structure named by \fIname\fP doesn't belong to the list.
-If \fImode\fP is set to 'Y' all objects (abl) pointed by the beaux will also
-be removed. If \fImode\fP is set to 'N' and there is any object (abl) pointed
-by the beaux a warning message is printed on the standard error output.
-
-.PP
-\fBbeh_frebeaux()\fP deletes a list of beaux structures (pointed by
-\fIlist\fP) and all objects (abl) pointed by any beaux structure of the list.
-No action is made if \fIlist\fP is an empty list (NULL pointer).
-No checks are made by this function.
-
-.SH EXAMPLE
-.PP
-.nf
-#include <beh108.h>
-
-struct beaux *list;
-char *name;
-
-name = namealloc ("carry_3");
-list = beh_addbeaux (list,"carry_2", NULL, NULL);
-list = beh_rmvbeaux (list,name);
-.fi
-
-.SH SEE ALSO
-.PP
-beh(3), log(1), beaux(3), namealloc(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/funbebus.3 b/alliance/share/man/man3/funbebus.3
deleted file mode 100644
index af10190d..00000000
--- a/alliance/share/man/man3/funbebus.3
+++ /dev/null
@@ -1,122 +0,0 @@
-.\"   $Id: funbebus.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)bebus.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.TH FUNBEBUS 3 "October 1, 1997" "ASIM/LIP6" "BEH functions"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBbeh_addbebus , beh_delbebus , beh_rmvbebus , beh_frebebus\fP
-
-.SH SYNOPSYS
-.PP
-.nf
-struct bebus *beh_addbebus (list, name, biabl, bibdd, type)
-struct bebus *list;
-char *name;
-struct biabl *biabl;
-struct binode *bibdd;
-char type;
-
-struct bebus *beh_delbebus (list, pnt, mode)
-struct bebus *list;
-struct bebus *pnt;
-char mode;
-
-struct bebus *beh_rmvbebus (list, name, mode)
-struct bebus *list;
-char *name;
-char mode;
-
-void beh_frebebus (list)
-struct bebus *list;
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIlist\fP
-pointer of a list of bebus structures
-.TP 10
-\fIname\fP
-name of the bused output port to be added to or removed from the list
-.TP 10
-\fIbiabl\fP
-list of biabl representing the expression of drivers setting the value of
-the bused output port
-.TP 10
-\fIbibdd\fP
-list of bibdd representing the expression of drivers setting the value of
-the bused output port
-.TP 10
-\fIpnt\fP
-pointer of the bebus structure to be removed from the list
-.TP 10
-\fItype\fP
-type of the bused output port :
-.RS
-.TP 5
-W
-for a WOR_BIT
-.TP 5
-M
-for a MUX_BIT
-.RE
-.TP 10
-\fImode\fP
-recursive mode (Y or N)
-
-.SH DESCRIPTION
-.PP
-A bebus is a data structure representing a one\-bit bused output port.
-
-.PP
-\fBbeh_addbebus()\fP adds a bebus structure at the top of a list of bebus
-structures. The name registred in the bebus structure is produced by
-\fBnamealloc()\fP. The function returns the pointer of the new list.
-No checks are made by this function.
-
-.PP
-\fBbeh_delbebus()\fP deletes a bebus structure (pointed by \fIpnt\fP) from a
-list of bebus structures. The function returns the pointer of the new list.
-No action is made if the structure pointed by \fIpnt\fP doesn't belong to the
-list. If \fImode\fP is set to 'Y' all objects (biabl, binode) pointed by the
-bebus will also be deleted. If \fImode\fP is set to 'N' and there is any object
-(biabl, binode) pointed by the bebus, a warning message is printed on the
-standard error output.
-
-.PP
-\fBbeh_rmvbebus()\fP deletes a bebus structure (named \fIname\fP) from a list
-of bebus structures. \fIname\fP is supposed to be produced by \fBnamealloc()\fP.
-The function returns the pointer of the new list.
-No action is made if no structure named \fIname\fP has been found in the list.
-If \fImode\fP is set to 'Y' all objects (biabl, binode) pointed by the bebus
-will also be deleted. If \fImode\fP is set to 'N' and there is any object
-(biabl, binode) pointed by the bebus, a warning message is printed on the
-standard error output.
-
-.PP
-\fBbeh_frebebus()\fP deletes a list of bebus structures (pointed by
-\fIlist\fP) and all objects (biabl, binode) pointed by any bebus structure of
-the list. No action is made if \fIlist\fP is an empty list (NULL pointer).
-No checks are made by this function.
-
-.SH EXAMPLE
-.PP
-.nf
-#include <beh108.h>
-
-struct bebus *list;
-char *name;
-
-name = namealloc ("data_bus_0");
-list = beh_addbebus (list,"result_bus_0", NULL, NULL, 'M');
-list = beh_rmvbebus (list,name);
-.fi
-
-.SH SEE ALSO
-.PP
-beh(3), log(1), biabl(3), binode(3), bebus(3), namealloc(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/funbebux.3 b/alliance/share/man/man3/funbebux.3
deleted file mode 100644
index b93cb403..00000000
--- a/alliance/share/man/man3/funbebux.3
+++ /dev/null
@@ -1,122 +0,0 @@
-.\"   $Id: funbebux.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)bebux.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.TH FUNBEBUX 3 "October 1, 1997" "ASIM/LIP6" "BEH functions"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBbeh_addbebux , beh_delbebux , beh_rmvbebux , beh_frebebux\fP
-
-.SH SYNOPSYS
-.PP
-.nf
-struct bebux *beh_addbebux (list, name, biabl, bibdd, type)
-struct bebux *list;
-char *name;
-struct biabl *biabl;
-struct binode *bibdd;
-char type;
-
-struct bebux *beh_delbebux (list, pnt, mode)
-struct bebux *list;
-struct bebux *pnt;
-char mode;
-
-struct bebux *beh_rmvbebux (list, name, mode)
-struct bebux *list;
-char *name;
-char mode;
-
-void beh_frebebux (list)
-struct bebux *list;
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIlist\fP
-pointer of a list of bebux structures
-.TP 10
-\fIname\fP
-name of the bused internal signal to be added to or removed from the list
-.TP 10
-\fIbiabl\fP
-list of biabl representing the expression of drivers setting the value of
-the bused internal signal
-.TP 10
-\fIbibdd\fP
-list of bibdd representing the expression of drivers setting the value of
-the bused internal signal
-.TP 10
-\fIpnt\fP
-pointer of the bebux structure to be removed from the list
-.TP 10
-\fItype\fP
-type of the bused internal signal :
-.RS
-.TP 5
-W
-for a WOR_BIT
-.TP 5
-M
-for a MUX_BIT
-.RE
-.TP 10
-\fImode\fP
-recursive mode (Y or N)
-
-.SH DESCRIPTION
-.PP
-A bebux is a data structure representing a one\-bit bused internal signal.
-
-.PP
-\fBbeh_addbebux()\fP adds a bebux structure at the top of a list of bebux
-structures. The name registred in the bebux structure is produced by
-\fBnamealloc()\fP. The function returns the pointer of the new list.
-No checks are made by this function.
-
-.PP
-\fBbeh_delbebux()\fP deletes a bebux structure (pointed by \fIpnt\fP) from a
-list of bebux structures. The function returns the pointer of the new list.
-No action is made if the structure pointed by \fIpnt\fP doesn't belong to the
-list. If \fImode\fP is set to 'Y' all objects (biabl, binode) pointed by the
-bebux will also be deleted. If \fImode\fP is set to 'N' and there is any object
-(biabl, binode) pointed by the bebux a warning message is printed on the
-standard error output.
-
-.PP
-\fBbeh_rmvbebux()\fP deletes a bebux structure (named \fIname\fP) from a list
-of bebux structures. \fIname\fP is supposed to be produced by \fBnamealloc()\fP.
-The function returns the pointer of the new list.
-No action is made if no structure named \fIname\fP has been found in the list.
-If \fImode\fP is set to 'Y' all objects (biabl, binode) pointed by the bebux
-will also be deleted. If \fImode\fP is set to 'N' and there is any object
-(biabl, binode) pointed by the bebux a warning message is printed on the
-standard error output.
-
-.PP
-\fBbeh_frebebux()\fP deletes a list of bebux structures (pointed by
-\fIlist\fP) and all objects (biabl, binode) pointed by any bebux structure of
-the list. No action is made if \fIlist\fP is an empty list (NULL pointer).
-No checks are made by this function.
-
-.SH EXAMPLE
-.PP
-.nf
-#include <beh108.h>
-
-struct bebux *list;
-char *name;
-
-name = namealloc ("data_bus_0");
-list = beh_addbebux (list,"result_bus_0", NULL, NULL, 'M');
-list = beh_rmvbebux (list,name);
-.fi
-
-.SH SEE ALSO
-.PP
-beh(3), log(1), biabl(3), binode(3), bebux(3), namealloc(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/funbefig.3 b/alliance/share/man/man3/funbefig.3
deleted file mode 100644
index c272496b..00000000
--- a/alliance/share/man/man3/funbefig.3
+++ /dev/null
@@ -1,103 +0,0 @@
-.\"   $Id: funbefig.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)befig.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.TH FUNBEFIG 3 "October 1, 1997" "ASIM/LIP6" "BEH functions"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBbeh_addbefig , beh_delbefig , beh_rmvbefig , beh_frebefig\fP
-
-.SH SYNOPSYS
-.PP
-.nf
-struct befig *beh_addbefig (list, name)
-struct befig *list;
-char *name;
-
-struct befig *beh_delbefig (list, pnt, mode)
-struct befig *list;
-struct befig *pnt;
-char mode;
-
-struct befig *beh_rmvbefig (list, name, mode)
-struct befig *list;
-char *name;
-char mode;
-
-void beh_frebefig (list)
-struct befig *list;
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIlist\fP
-pointer of a list of befig structures
-.TP 10
-\fIname\fP
-name of the behavioural figure to be added to or removed from the list
-\fIpnt\fP
-pointer of the befig structure to be removed from the list
-.TP 10
-\fIpnt\fP
-pointer of the befig to be removed form the list
-.TP 10
-\fImode\fP
-recursive mode (Y or N)
-
-.SH DESCRIPTION
-.PP
-A befig is a data structure representing a complete behavioural description of a
-circuit.
-
-.PP
-\fBbeh_addbefig()\fP adds a befig structure at the top of a list of befig
-structures. The name registred in the befig structure is produced by
-\fBnamealloc()\fP. The function returns the pointer of the new list.
-No checks are made by this function.
-
-.PP
-\fBbeh_delbefig()\fP deletes a befig structure (pointed by \fIpnt\fP) from a
-list of befig structures. The function returns the pointer of the new list.
-No action is made if the structure pointed by \fIpnt\fP doesn't belong to the
-list. If \fImode\fP is set to 'Y' all objects (berin, bepor, bemsg, beout,
-bereg, bebus, bebux, beaux, binode, biabl, abl) pointed by the befig will also
-be deleted. If \fImode\fP is set to 'N' and there is any object pointed
-by the structure a warning message is printed on the standard error output.
-
-.PP
-\fBbeh_rmvbefig()\fP deletes a befig structure (named \fIname\fP) from a list
-of befig structures. \fIname\fP is supposed to be produced by \fBnamealloc()\fP.
-The function returns the pointer of the new list.
-No action is made if no structure named \fIname\fP has been found in the list.
-If \fImode\fP is set to 'Y' all objects (berin, bepor, bemsg, beout, bereg,
-bebus, bebux, beaux, binode, biabl, abl) pointed by the befig will also
-be deleted. If \fImode\fP is set to 'N' and there is any object pointed
-by the structure a warning message is printed on the standard error output.
-
-.PP
-\fBbeh_frebefig()\fP deletes a list of befig structures (pointed by
-\fIlist\fP) and all objects pointed by any of befig structures of the list.
-No action is made if \fIlist\fP is an empty list (NULL pointer).
-No checks are made by this function.
-
-.SH EXAMPLE
-.PP
-.nf
-#include <beh108.h>
-
-struct befig *list;
-char *name;
-
-name = namealloc ("adder");
-list = beh_addbefig (list,"amd2901");
-list = beh_rmvbefig (list,name);
-.fi
-
-.SH SEE ALSO
-.PP
-beh(3), befig(3), namealloc(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/funbegen.3 b/alliance/share/man/man3/funbegen.3
deleted file mode 100644
index 5b8c77e4..00000000
--- a/alliance/share/man/man3/funbegen.3
+++ /dev/null
@@ -1,105 +0,0 @@
-.\"   $Id: funbegen.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)begen.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.TH FUNBEGEN 3 "October 1, 1997" "ASIM/LIP6" "BEH functions"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBbeh_addbegen , beh_delbegen , beh_rmvbegen , beh_frebegen\fP
-
-.SH SYNOPSYS
-.PP
-.nf
-struct begen *beh_addbegen (list, name, type, value)
-struct begen *list;
-char *name;
-char *type;
-void *value;
-
-struct begen *beh_delbegen (list, pnt, mode)
-struct begen *list;
-struct begen *pnt;
-char mode;
-
-struct begen *beh_rmvbegen (list, name, mode)
-struct begen *list;
-char *name;
-char mode;
-
-void beh_frebegen (list)
-struct begen *list;
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIlist\fP
-pointer of a list of begen structures
-.TP 10
-\fIname\fP
-name of the generic to be added to or removed from the list
-.TP 10
-\fIpnt\fP
-pointer of the begen structure to be removed from the list
-.TP 10
-\fItype\fP
-type of the generic
-.TP 10
-\fItype\fP
-type of the generic (integer, bit, natural, ...)
-.TP 10
-\fIvalue\fP
-pointer on the structure representing the value of the genereic
-.TP 10
-\fImode\fP
-recursive mode (Y or N)
-
-.SH DESCRIPTION
-.PP
-A begen is a data structure representing a constant value relative to a circuit.
-
-.PP
-\fBbeh_addbegen()\fP adds a begen structure at the top of a list of begen
-structures. The name registred in the begen structure is produced by
-\fBnamealloc()\fP. The function returns the pointer of the new list.
-No checks are made by this function.
-
-.PP
-\fBbeh_delbegen()\fP deletes a begen structure (pointed by \fIpnt\fP)
-from a list of begen structures. The function returns the pointer of the new
-list. No action is made if the structure pointed by \fIpnt\fP doesn't belong
-to the list. If \fImode\fP is set to 'Y' all objects pointed by the begen will
-also be removed. If \fImode\fP is set to 'N' and there is any object pointed
-by the begen a warning message is printed on the standard error output.
-
-.PP
-\fBbeh_rmvbegen()\fP deletes a begen structure (named \fIname\fP) from a list
-of begen structures. \fIname\fP is supposed to be produced by \fBnamealloc()\fP.
-The function returns the pointer of the new list.
-No action is made if no structure named \fIname\fP has been found in the list.
-If \fImode\fP is set to 'Y' all objects pointed by the begen will also
-be removed. If \fImode\fP is set to 'N' and there is any object pointed
-by the begen a warning message is printed on the standard error output.
-
-.PP
-\fBbeh_frebegen()\fP deletes a list of begen structures (pointed by
-\fIlist\fP). No action is made if \fIlist\fP is an empty list (NULL pointer).
-No checks are made by this function.
-
-.SH EXAMPLE
-.PP
-.nf
-#include <beh108.h>
-
-struct begen *list;
-
-list = beh_addbegen (list,"surface","natural",600);
-.fi
-
-.SH SEE ALSO
-.PP
-beh(3), begen(3), namealloc(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/funbemsg.3 b/alliance/share/man/man3/funbemsg.3
deleted file mode 100644
index 7255c666..00000000
--- a/alliance/share/man/man3/funbemsg.3
+++ /dev/null
@@ -1,122 +0,0 @@
-.\"   $Id: funbemsg.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)bemsg.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.TH FUNBEMSG 3 "October 1, 1997" "ASIM/LIP6" "BEH functions"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBbeh_addbemsg , beh_delbemsg , beh_rmvbemsg , beh_frebemsg\fP
-
-.SH SYNOPSYS
-.PP
-.nf
-struct bemsg *beh_addbemsg (list, label, level, message, abl, bdd)
-struct bemsg *list;
-char *label;
-char level;
-char *message;
-struct chain *abl;
-struct node *bdd;
-
-struct bemsg *beh_delbemsg (list, pnt, mode)
-struct bemsg *list;
-struct bemsg *pnt;
-char mode;
-
-struct bemsg *beh_rmvbemsg (list, label, mode)
-struct bemsg *list;
-char *label;
-char mode;
-
-void beh_frebemsg (list)
-struct bemsg *list;
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIlist\fP
-pointer of a list of bemsg structures
-.TP 10
-\fIlabel\fP
-label of the assert instruction
-.TP 10
-\fIlevel\fP
-the severity level of the assert :
-.RS
-.TP 5
-E
-for an assert with severity level ERROR
-.TP 5
-W
-for an assert with severity level WARNING
-.RE
-.TP 10
-\fImessage\fP
-a string representing the message printed in case of assert violation
-.TP 10
-\fIabl\fP
-the abl representing the expression specified in the assert's condition
-.TP 10
-\fIbdd\fP
-the bdd representing the expression specified in the assert's condition
-.TP 10
-\fIpnt\fP
-pointer of the bemsg structure to be removed from the list
-.TP 10
-\fImode\fP
-recursive mode (Y or N)
-
-.SH DESCRIPTION
-.PP
-A bemsg structure represents a VHDL concurrent assert instruction.
-
-.PP
-\fBbeh_addbemsg()\fP adds a bemsg structure at the top of a list of bemsg
-structures. The label registred in the bemsg structure is produced by
-\fBnamealloc()\fP. The function returns the pointer of the new list.
-No checks are made by this function.
-
-.PP
-\fBbeh_delbemsg()\fP deletes a bemsg structure (pointed by \fIpnt\fP) from a
-list of bemsg structures. The function returns the pointer of the new list.
-No action is made if the structure pointed by \fIpnt\fP doesn't belong to the
-list. If \fImode\fP is set to 'Y' all objects (abl) pointed by the bemsg will
-also be deleted. If \fImode\fP is set to 'N' and there is any object (abl)
-pointed by the bemsg a warning message is printed on the standard error output.
-
-.PP
-\fBbeh_rmvbemsg()\fP deletes a bemsg structure (labeled \fIlabel\fP) from a
-list of bemsg structures. \fIlabel\fP is supposed to be produced by
-\fBnamealloc()\fP. The function returns the pointer of the new list.
-No action is made if no structure labeled \fIlabel\fP has been found in the
-list. If \fImode\fP is set to 'Y' all objects (abl) pointed by the bemsg will
-also be deleted. If \fImode\fP is set to 'N' and there is any object (abl)
-pointed by the bemsg a warning message is printed on the standard error output.
-
-.PP
-\fBbeh_frebemsg()\fP deletes a list of bemsg structures (pointed by
-\fIlist\fP) and all objects (abl) pointed by any bemsg structure of the list.
-No action is made if \fIlist\fP is an empty list (NULL pointer).
-No checks are made by this function.
-
-.SH EXAMPLE
-.PP
-.nf
-#include <beh108.h>
-
-struct bemsg *list;
-char *label;
-
-label = namealloc ("power_supply_check");
-list = beh_addbemsg (list, label, 'E', "conflict on bus", NULL, NULL);
-list = beh_rmvbemsg (list, label);
-.fi
-
-.SH SEE ALSO
-.PP
-beh(3), log(1), bemsg(3), namealloc(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/funbeout.3 b/alliance/share/man/man3/funbeout.3
deleted file mode 100644
index 641bc28d..00000000
--- a/alliance/share/man/man3/funbeout.3
+++ /dev/null
@@ -1,106 +0,0 @@
-.\"   $Id: funbeout.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)beout.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.TH FUNBEOUT 3 "October 1, 1997" "ASIM/LIP6" "BEH functions"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBbeh_addbeout , beh_delbeout , beh_rmvbeout , beh_frebeout\fP
-
-.SH SYNOPSYS
-.PP
-.nf
-struct beout *beh_addbeout (list, name, abl, bdd)
-struct beout *list;
-char *name;
-struct chain *abl;
-struct node *bdd;
-
-struct beout *beh_delbeout (list, pnt, mode)
-struct beout *list;
-struct beout *pnt;
-char mode;
-
-struct beout *beh_rmvbeout (list, name, mode)
-struct beout *list;
-char *name;
-char mode;
-
-void beh_frebeout (list)
-struct beout *list;
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIlist\fP
-pointer of a list of beout structures
-.TP 10
-\fIname\fP
-name of the output port to be added to or removed from the list
-.TP 10
-\fIabl\fP
-the abl representing the expression of the output port
-.TP 10
-\fIbdd\fP
-the bdd representing the expression of the output port
-.TP 10
-\fIpnt\fP
-pointer of the beout structure to be removed from the list
-.TP 10
-\fImode\fP
-recursive mode (Y or N)
-
-.SH DESCRIPTION
-.PP
-A beout is a data structure representing a one\-bit simple output port.
-
-.PP
-\fBbeh_addbeout()\fP adds a beout structure at the top of a list of beout
-structures. The name registred in the beout structure is produced by
-\fBnamealloc()\fP. The function returns the pointer of the new list.
-No checks are made by this function.
-
-.PP
-\fBbeh_delbeout()\fP deletes a beout structure (pointed by \fIpnt\fP) from a
-list of beout structures. The function returns the pointer of the new list. No
-action is made if the structure pointed by \fIpnt\fP doesn't belong to the list.
-If \fImode\fP is set to 'Y' all objects (abl) pointed by the beout will also
-be deleted. If \fImode\fP is set to 'N' and there is any object (abl) pointed
-by the structure a warning message is printed on the standard error output.
-
-.PP
-\fBbeh_rmvbeout()\fP deletes a beout structure (named \fIname\fP) from a list
-of beout structures. \fIname\fP is supposed to be produced by \fBnamealloc()\fP.
-The function returns the pointer of the new list.
-No action is made if no structure named \fIname\fP has been found in the list.
-If \fImode\fP is set to 'Y' all objects (abl) pointed by the beout will also
-be deleted. If \fImode\fP is set to 'N' and there is any object (abl) pointed
-by the structure a warning message is printed on the standard error output.
-
-.PP
-\fBbeh_frebeout()\fP deletes a list of beout structures (pointed by
-\fIlist\fP) and all objects (abl) pointed by any beout structure of the list.
-No action is made if \fIlist\fP is an empty list (NULL pointer).
-No checks are made by this function.
-
-.SH EXAMPLE
-.PP
-.nf
-#include <beh108.h>
-
-struct beout *list;
-char *name;
-
-name = namealloc ("carry_out");
-list = beh_addbeout (list,"sum_0", NULL, NULL);
-list = beh_rmvbeout (list,name);
-.fi
-
-.SH SEE ALSO
-.PP
-beh(3), log(1), beout(3), namealloc(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/funbepor.3 b/alliance/share/man/man3/funbepor.3
deleted file mode 100644
index e2d23740..00000000
--- a/alliance/share/man/man3/funbepor.3
+++ /dev/null
@@ -1,124 +0,0 @@
-.\"   $Id: funbepor.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)bepor.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.TH FUNBEPOR 3 "October 1, 1997" "ASIM/LIP6" "BEH functions"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBbeh_addbepor , beh_delbepor , beh_rmvbepor , beh_frebepor\fP
-
-.SH SYNOPSYS
-.PP
-.nf
-struct bepor *beh_addbepor (list, name, dir, type)
-struct bepor *list;
-char *name;
-char dir;
-char type;
-
-struct bepor *beh_delbepor (list, pnt)
-struct bepor *list;
-struct bepor *pnt;
-
-struct bepor *beh_rmvbepor (list, name)
-struct bepor *list;
-char *name;
-
-void beh_frebepor (list)
-struct bepor *list;
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIlist\fP
-pointer of a list of bepor structures
-.TP 10
-\fIname\fP
-name of the port to be added to or removed from the list
-.TP 10
-\fIdir\fP
-direction of the port :
-.RS
-.TP 5
-I
-for a simple input port
-.TP 5
-O
-for a simple output port
-.TP 5
-B
-for a simple input\-output port
-.TP 5
-Z
-for an output port drived by a tri\-state emitter
-.TP 5
-T
-for an input\-output port drived by a tri\-state emitter
-.RE
-.TP 10
-\fItype\fP
-type of the port :
-.RS
-.TP 5
-B
-for a BIT
-.TP 5
-W
-for a WOR_BIT
-.TP 5
-M
-for a MUX_BIT
-.RE
-.TP 10
-\fIpnt\fP
-pointer of the bepor structure to be removed from the list
-
-.SH DESCRIPTION
-.PP
-A bepor is a data structure representing a one\-bit port. A bepor list must be
-ordered in the reverse order of port declarations.
-
-.PP
-\fBbeh_addbepor()\fP adds a bepor structure at the top of a list of bepor
-structures. The name registred in the bepor structure is produced by
-\fBnamealloc()\fP. The function returns the pointer of the new list.
-No checks are made by this function.
-
-.PP
-\fBbeh_delbepor()\fP deletes a bepor structure (pointed by \fIpnt\fP) from a
-list of bepor structures. The function returns the pointer of the new list.
-No action is made if the structure pointed by \fIpnt\fP doesn't belong to the
-list.
-
-.PP
-\fBbeh_rmvbepor()\fP deletes a bepor structure (named \fIname\fP) from a list
-of bepor structures. \fIname\fP is supposed to be produced by \fBnamealloc()\fP.
-The function returns the pointer of the new list.
-No action is made if no structure named \fIname\fP has been found in the list.
-
-.PP
-\fBbeh_frebepor()\fP deletes a list of bepor structures (pointed by
-\fIlist\fP). No action is made if \fIlist\fP is an empty list (NULL pointer).
-No checks are made by this function.
-
-.SH EXAMPLE
-.PP
-.nf
-#include <beh108.h>
-
-struct bepor *list;
-char *name;
-
-name = namealloc ("slave_clock");
-list = beh_addbepor (list,"master_clock",'I','B');
-list = beh_rmvbepor (list,name);
-.fi
-
-.SH SEE ALSO
-.PP
-beh(3), bepor(3), namealloc(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/funbereg.3 b/alliance/share/man/man3/funbereg.3
deleted file mode 100644
index e18fabaf..00000000
--- a/alliance/share/man/man3/funbereg.3
+++ /dev/null
@@ -1,110 +0,0 @@
-.\"   $Id: funbereg.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)bereg.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.TH FUNBEREG 3 "October 1, 1997" "ASIM/LIP6" "BEH functions"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBbeh_addbereg , beh_delbereg , beh_rmvbereg , beh_frebereg\fP
-
-.SH SYNOPSYS
-.PP
-.nf
-struct bereg *beh_addbereg (list, name, biabl, bibdd)
-struct bereg *list;
-char *name;
-struct biabl *biabl;
-struct binode *bibdd;
-
-struct bereg *beh_delbereg (list, pnt, mode)
-struct bereg *list;
-struct bereg *pnt;
-char mode;
-
-struct bereg *beh_rmvbereg (list, name, mode)
-struct bereg *list;
-char *name;
-char mode;
-
-void beh_frebereg (list)
-struct bereg *list;
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIlist\fP
-pointer of a list of bereg structures
-.TP 10
-\fIname\fP
-name of the internal register to be added to or removed from the list
-.TP 10
-\fIbiabl\fP
-list of biabl representing the expression of drivers setting the value of
-the internal register
-.TP 10
-\fIbibdd\fP
-list of bibdd representing the expression of drivers setting the value of
-the internal register
-.TP 10
-\fIpnt\fP
-pointer of the bereg structure to be removed from the list
-.TP 10
-\fImode\fP
-recursive mode (Y or N)
-
-.SH DESCRIPTION
-.PP
-A bereg is a data structure representing a one\-bit internal register.
-
-.PP
-\fBbeh_addbereg()\fP adds a bereg structure at the top of a list of bereg
-structures. The name registred in the bereg structure is produced by
-\fBnamealloc()\fP. The function returns the pointer of the new list.
-No checks are made by this function.
-
-.PP
-\fBbeh_delbereg()\fP deletes a bereg structure (pointed by \fIpnt\fP) from a
-list of bereg structures. The function returns the pointer of the new list.
-No action is made if the structure pointed by \fIpnt\fP doesn't belong to the
-list. If \fImode\fP is set to 'Y' all objects (biabl, binode) pointed by the
-bereg will also be deleted. If \fImode\fP is set to 'N' and there is any object
-(biabl, binode) pointed by the structure a warning message is printed on the
-standard error output.
-
-.PP
-\fBbeh_rmvbereg()\fP deletes a bereg structure (named \fIname\fP) from a list
-of bereg structures. \fIname\fP is supposed to be produced by \fBnamealloc()\fP.
-The function returns the pointer of the new list.
-No action is made if no structure named \fIname\fP has been found in the list.
-If \fImode\fP is set to 'Y' all objects (biabl, binode) pointed by the bereg
-will also be deleted. If \fImode\fP is set to 'N' and there is any object
-(biabl, binode) pointed by the structure a warning message is printed on the
-standard error output.
-
-.PP
-\fBbeh_frebereg()\fP deletes a list of bereg structures (pointed by
-\fIlist\fP) and all objects (biabl, binode) pointed by any bereg structure of
-the list. No action is made if \fIlist\fP is an empty list (NULL pointer).
-No checks are made by this function.
-
-.SH EXAMPLE
-.PP
-.nf
-#include <beh108.h>
-
-struct bereg *list;
-char *name;
-
-name = namealloc ("counter_2");
-list = beh_addbereg (list,"ram_0", NULL, NULL);
-list = beh_rmvbereg (list,name);
-.fi
-
-.SH SEE ALSO
-.PP
-beh(3), log(1), biabl(3), binode(3), bereg(3), namealloc(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/funberin.3 b/alliance/share/man/man3/funberin.3
deleted file mode 100644
index 79e8c21d..00000000
--- a/alliance/share/man/man3/funberin.3
+++ /dev/null
@@ -1,87 +0,0 @@
-.\"   $Id: funberin.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)berin.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.TH FUNBERIN 3 "October 1, 1997" "ASIM/LIP6" "BEH functions"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBbeh_addberin , beh_delberin , beh_rmvberin , beh_freberin\fP
-
-.SH SYNOPSYS
-.PP
-.nf
-struct berin *beh_addberin (list, name)
-struct berin *list;
-char *name;
-
-struct berin *beh_delberin (list, pnt)
-struct berin *list;
-struct berin *pnt;
-
-struct berin *beh_rmvberin (list, name)
-struct berin *list;
-char *name;
-
-void beh_freberin (list)
-struct berin *list;
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIlist\fP
-pointer of a list of berin structures
-.TP 10
-\fIname\fP
-name of the port or register to be added to or removed from the list
-.TP 10
-\fIpnt\fP
-pointer of the berin structure to be removed from the list
-
-.SH DESCRIPTION
-.PP
-A berin is a data structure representing a one\-bit port or internal register.
-
-.PP
-\fBbeh_addberin()\fP adds a berin structure at the top of a list of berin
-structures. The name registred in the berin structure is produced by
-\fBnamealloc()\fP. The function returns the pointer of the new list.
-No checks are made by this function.
-
-.PP
-\fBbeh_delberin()\fP deletes a berin structure (pointed by \fIpnt\fP)
-from a list of berin structures. The function returns the pointer of the new
-list. No action is made if the structure pointed by \fIpnt\fP doesn't belong
-to the list.
-
-.PP
-\fBbeh_rmvberin()\fP deletes a berin structure (named \fIname\fP) from a list
-of berin structures. \fIname\fP is supposed to be produced by \fBnamealloc()\fP.
-The function returns the pointer of the new list.
-No action is made if no structure named \fIname\fP has been found in the list.
-
-.PP
-\fBbeh_freberin()\fP deletes a list of berin structures (pointed by
-\fIlist\fP). No action is made if \fIlist\fP is an empty list (NULL pointer).
-No checks are made by this function.
-
-.SH EXAMPLE
-.PP
-.nf
-#include <beh108.h>
-
-struct berin *list;
-char *name;
-
-name = namealloc ("slave_clock");
-list = beh_addberin (list,"master_clock");
-list = beh_rmvberin (list,name);
-.fi
-
-.SH SEE ALSO
-.PP
-beh(3), berin(3), namealloc(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/funbiabl.3 b/alliance/share/man/man3/funbiabl.3
deleted file mode 100644
index 29770a29..00000000
--- a/alliance/share/man/man3/funbiabl.3
+++ /dev/null
@@ -1,92 +0,0 @@
-.\"   $Id: funbiabl.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)biabl.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.TH FUNBIABL 3 "October 1, 1997" "ASIM/LIP6" "BEH functions"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBbeh_addbiabl , beh_delbiabl , beh_frebiabl\fP
-
-.SH SYNOPSYS
-.PP
-.nf
-struct biabl *beh_addbiabl (list, label, cond, value)
-struct biabl *list;
-char *label;
-struct chain *cond;
-struct chain *value;
-
-struct biabl *beh_delbiabl (list, pnt, mode)
-struct biabl *list;
-struct biabl *pnt;
-char mode;
-
-void beh_frebiabl (list)
-struct biabl *list;
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIlist\fP
-pointer of a list of biabl structures
-.TP 10
-\fIlabel\fP
-driver's label
-.TP 10
-\fIcond\fP
-abl representing the expression of the connection condition of the driver
-.TP 10
-\fIvalue\fP
-abl representing the expression of the value emitted by the driver
-.TP 10
-\fIpnt\fP
-pointer of the biabl structure to be removed from the list
-.TP 10
-\fImode\fP
-recursive mode (Y or N)
-
-.SH DESCRIPTION
-.PP
-A biabl is a data structure representing a one\-bit deconnectable VHDL driver.
-
-.PP
-\fBbeh_addbiabl()\fP adds a biabl structure at the top of a list of biabl
-structures. \fIcond\fP is a pointer on the abl representing the condition that
-makes the driver active. \fIvalue\fP is the abl of the expression of the value
-produced by the driver. \fIlabel\fP is the identification of the driver. The
-label registred in the biabl structure is produced by \fBnamealloc()\fP.
-The function returns the pointer of the new list.
-No checks are made by this function.
-
-.PP
-\fBbeh_delbiabl()\fP deletes a biabl structure (pointed by \fIpnt\fP)
-from a list of biabl structures. The function returns the pointer of the new
-list. No action is made if the structure pointed by \fIpnt\fP doesn't belong
-to the list.
-
-.PP
-\fBbeh_frebiabl()\fP deletes a list of biabl structures (pointed by
-\fIlist\fP). No action is made if \fIlist\fP is an empty list (NULL pointer).
-No checks are made by this function.
-If \fImode\fP is set to 'Y' all objects (abl) pointed by the biabl will also
-be deleted. If \fImode\fP is set to 'N' and there is any object (abl) pointed
-by the structure a warning message is printed on the standard error output.
-
-.SH EXAMPLE
-.PP
-.nf
-#include <beh108.h>
-
-struct biabl *list;
-
-list = beh_addbiabl (list, "write_reg", NULL, NULL);
-.fi
-
-.SH SEE ALSO
-.PP
-beh(3), biabl(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/funbinod.3 b/alliance/share/man/man3/funbinod.3
deleted file mode 100644
index 6fab6feb..00000000
--- a/alliance/share/man/man3/funbinod.3
+++ /dev/null
@@ -1,86 +0,0 @@
-.\"   $Id: funbinod.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)binode.2 108 Feb 15 1995 UPMC ; Pirouz BAZARGAN SABET
-.TH FUNBINOD 3 "October 1, 1997" "ASIM/LIP6" "BEH functions"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBbeh_addbinode , beh_delbinode , beh_frebinode\fP
-
-.SH SYNOPSYS
-.PP
-.nf
-struct binode *beh_addbinode (list, cond, value)
-struct binode *list;
-struct node *cond;
-struct node *value;
-
-struct binode *beh_delbinode (list, pnt, mode)
-struct binode *list;
-struct binode *pnt;
-char mode;
-
-void beh_frebinode (list)
-struct binode *list;
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIlist\fP
-pointer of a list of binode structures
-.TP 10
-\fIcond\fP
-bdd representing the expression of the connection condition of the driver
-.TP 10
-\fIvalue\fP
-bdd representing the expression of the value emitted by the driver
-.TP 10
-\fIpnt\fP
-pointer of the binode structure to be removed from the list
-.TP 10
-\fImode\fP
-recursive mode (Y or N)
-
-.SH DESCRIPTION
-.PP
-A binode is a data structure representing a one\-bit deconnectable VHDL driver.
-
-.PP
-\fBbeh_addbinode()\fP adds a binode structure at the top of a list of binode
-structures. \fIcond\fP is a pointer on the bdd representing the condition that
-makes the driver active. \fIvalue\fP is the bdd of the expression of the value
-produced by the driver. The function returns the pointer of the new list.
-No checks are made by this function.
-
-.PP
-\fBbeh_delbinode()\fP deletes a binode structure (pointed by \fIpnt\fP)
-from a list of binode structures. The function returns the pointer of the new
-list. No action is made if the structure pointed by \fIpnt\fP doesn't belong
-to the list.
-
-.PP
-\fBbeh_frebinode()\fP deletes a list of binode structures (pointed by
-\fIlist\fP). No action is made if \fIlist\fP is an empty list (NULL pointer).
-No checks are made by this function.
-If \fImode\fP is set to 'Y' all objects (bdd) pointed by the binode will also
-be deleted. If \fImode\fP is set to 'N' and there is any object (bdd) pointed
-by the structure a warning message is printed on the standard error output.
-
-.SH EXAMPLE
-.PP
-.nf
-#include <beh108.h>
-
-struct binode *list;
-
-list = beh_addbinode (list, NULL, NULL);
-.fi
-
-.SH SEE ALSO
-.PP
-beh(3), binode(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/funpacom.3 b/alliance/share/man/man3/funpacom.3
deleted file mode 100644
index 06018a21..00000000
--- a/alliance/share/man/man3/funpacom.3
+++ /dev/null
@@ -1,71 +0,0 @@
-.\"   $Id: funpacom.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)funpacom.2 106 Sep 30 1996 UPMC ; VUONG Huu-Nghia 
-.TH FUNPACOM 3 "October 1, 1997" "ASIM/LIP6" "PAT functions"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBpat_addpacom, pat_frepacom\fP
-
-.SH SYNOPSYS
-.PP
-.nf
-struct pacom *pat_addpacom (lastpacom, text, position)
-struct pacom *lastpacom;
-char         *text;
-unsigned short position;
-
-void pat_frepacom (listpacom)
-struct pacom *listpacom;
-
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIlastpacom\fP
-pointer on the last pacom structure
-.TP 10
-\fItext\fP
-text of the comment
-.TP 10
-\fIposition\fP
-number of statements (input\-output declaration or pattern) to be printed
-before the comment line
-.TP 10
-\fIlistpacom\fP
-list of pacom structures to be deleted
-
-.SH DESCRIPTION
-.PP
-A pacom is a data structure representing a comment read from the pattern
-description file to be reproduced in the result file at the same place.
-
-.PP
-\fBpat_addpacom()\fP adds a pacom structure at the top of a list of pacom
-structures. The function returns the pointer of the new list.
-No check is made by this function.
-
-.PP
-\fBpat_frepacom()\fP deletes a list of pacom structures. If the list to be
-deleted is an empty list (NULL pointer), no action is produced. No check is
-made by this function.
-
-.SH EXAMPLE
-.PP
-.nf
-#include <pat106.h>
-
-struct pacom *list;
-
-list = pat_addpacom (list,"This is a comment",10);
-pat_frepacom (list);
-.fi
-
-.SH SEE ALSO
-.PP
-libpat(3), pacom(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/funpaevt.3 b/alliance/share/man/man3/funpaevt.3
deleted file mode 100644
index 0dcb4397..00000000
--- a/alliance/share/man/man3/funpaevt.3
+++ /dev/null
@@ -1,69 +0,0 @@
-.\"   $Id: funpaevt.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)paevt.2 106 Sep 30 1996 UPMC ; VUONG Huu-Nghia 
-.TH FUNPAEVT 3 "October 1, 1997" "ASIM/LIP6" "PAT functions"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBpat_addpaevt, pat_frepaevt\fP
-
-.SH SYNOPSYS
-.PP
-.nf
-struct paevt *pat_addpaevt (lastpaevt, index, usrval)
-struct paevt *lastpaevt;
-unsigned short index;
-char          usrval;
-
-void pat_frepaevt (listpaevt)
-struct paevt *listpaevt;
-
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIlastpaevt\fP
-pointer on the last paevt structure
-.TP 10
-\fIindex\fP
-index of the input-output
-.TP 10
-\fIusrval\fP
-user predicted value
-.TP 10
-\fIlistpaevt\fP
-list of paevt structures to be deleted
-
-.SH DESCRIPTION
-.PP
-A paevt is a data structure representing an event on a one-bit input-output. 
-
-.PP
-\fBpat_addpaevt()\fP adds a paevt structure at the top of a list of paevt
-structures. The function returns the pointer of the new list.
-No check is made by this function.
-
-.PP
-\fBpat_frepaevt()\fP deletes a list of paevt structures. If the list to be
-deleted is an empty list (NULL pointer), no action is produced. No check is
-made by this function.
-
-.SH EXAMPLE
-.PP
-.nf
-#include <pat106.h>
-
-struct paevt *list;
-
-list = pat_addpaevt (list, 10, '+');
-pat_frepaevt (list);
-.fi
-
-.SH SEE ALSO
-.PP
-libpat(3), paevt(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/funpagrp.3 b/alliance/share/man/man3/funpagrp.3
deleted file mode 100644
index 1cc6d842..00000000
--- a/alliance/share/man/man3/funpagrp.3
+++ /dev/null
@@ -1,66 +0,0 @@
-.\"   $Id: funpagrp.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)funpagrp.2 106 Sep 30 1996 UPMC ; VUONG Huu\-Nghia 
-.TH FUNPAGRP 3 "October 1, 1997" "ASIM/LIP6" "PAT functions"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBpat_addpagrp\fP
-
-.SH SYNOPSYS
-.PP
-.nf
-struct pagrp *pat_addpagrp (lastpagrp, name, length, index, flag)
-struct pagrp *lastpagrp;
-char *name;
-unsigned short length;
-unsigned short index;
-short flag;
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIlastpagrp\fP
-pointer on the last pagrp structure
-.TP 10
-\fIname\fP
-array\'s name
-.TP 10
-\fIlength\fP
-array\'s number of bit
-.TP 10
-\fIindex\fP
-index of the first paiol of the array
-.TP 10
-\fIflag\fP
-set to 0 for an actual array and to 1 for a virtual one
-
-.SH DESCRIPTION
-.PP
-A pagrp is a data structure representing an actual or virtual array. 
-
-.PP
-\fBpat_addpagrp()\fP adds a pagrp structure at the top of a list of pagrp
-structures. The name registered in the pagrp is produced by \fBnamealloc()\fP.
-The function returns the pointer of the new list. No check is made by
-this function.
-
-.SH EXAMPLE
-.PP
-.nf
-#include <pat106.h>
-
-struct pagrp *list;
-char *name;
-
-list = pat_addpagrp (list, "INA", 32, 10, 0);
-.fi
-
-.SH SEE ALSO
-.PP
-libpat(3), pagrp(3), namealloc(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/funpaini.3 b/alliance/share/man/man3/funpaini.3
deleted file mode 100644
index 567925c0..00000000
--- a/alliance/share/man/man3/funpaini.3
+++ /dev/null
@@ -1,70 +0,0 @@
-.\"   $Id: funpaini.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)funpaini.2 106 Sep 30 1996 UPMC ; VUONG Huu\-Nghia 
-.TH FUNPAINI 3 "October 1, 1997" "ASIM/LIP6" "PAT functions"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBpat_addpaini, pat_frepaini\fP
-
-.SH SYNOPSYS
-.PP
-.nf
-struct paini *pat_addpaini (lastpaini, name, value)
-struct paini *lastpaini;
-char         *name;
-char          value;
-
-void pat_frepaini (listpaini)
-struct paini *listpaini;
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIlastpaini\fP
-pointer on the last paini structure
-.TP 10
-\fIname\fP
-register\'s name
-.TP 10
-\fIvalue\fP
-value to be forced into the register
-.TP 10
-\fIlistpaini\fP
-list of paini structures to be deleted
-
-.SH DESCRIPTION
-.PP
-A paini is a data structure representing the initialization of a one\-bit
-register.
-
-.PP
-\fBpat_addpaini()\fP adds a paini structure at the top of a list of paini
-structures. The name registered in the paini is produced by \fBnamealloc()\fP.
-The function returns the pointer of the new list. No check is made by this
-function.
-
-.PP
-\fBpat_frepaini()\fP deletes a list of paini structures. If the list to be
-deleted is an empty list (NULL pointer), no action is produced. No check is
-made by this function.
-
-.SH EXAMPLE
-.PP
-.nf
-#include <pat106.h>
-
-struct paini *list;
-
-list = pat_addpaini (list, "general_register", '1');
-pat_frepaini (list);
-.fi
-
-.SH SEE ALSO
-.PP
-libpat(3), paini(3), namealloc(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/funpaiol.3 b/alliance/share/man/man3/funpaiol.3
deleted file mode 100644
index c3584399..00000000
--- a/alliance/share/man/man3/funpaiol.3
+++ /dev/null
@@ -1,87 +0,0 @@
-.\"   $Id: funpaiol.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)funpaiol.2 106 Sep 30 1996 UPMC ; VUONG Huu\-Nghia 
-.TH FUNPAIOL 3 "October 1, 1997" "ASIM/LIP6" "PAT functions"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBpat_addpaiol, pat_crtpaiol, pat_frepaiol\fP
-
-.SH SYNOPSYS
-.PP
-.nf
-struct paiol *pat_addpaiol (lastpaiol, name, format, mode, blank)
-struct paiol *lastpaiol;
-char *name;
-char format;
-char mode;
-unsigned char blank;
- 
-struct paiol *pat_crtpaiol (listpaiol)
-struct paiol *listpaiol;
-
-void pat_frepaiol (listpaiol)
-struct paiol *listpaiol;
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIlastpaiol\fP
-pointer on the last paiol structure
-.TP 10
-\fIname\fP
-input\-output\'s name
-.TP 10
-\fIformat\fP
-input\-output\'s format
-.TP 10
-\fImode\fP
-input\-output\'s mode
-.TP 10
-\fIblank\fP
-number of blank columns to be printed after the input\-output value
-.TP 10
-\fIlistpaiol\fP
-list of paiol structures to be deleted or put in a table
-
-.SH DESCRIPTION
-.PP
-A paiol is a data structure representing a one\-bit input\-output.
-
-.PP
-\fBpat_addpaiol()\fP adds a paiol structure at the top of a list of paiol
-structures. The name registered in the paiol is produced by \fBnamealloc()\fP.
-The function returns the pointer of the new list. No check is made by
-this function.
-
-.PP
-\fBpat_crtpaiol()\fP creates a table of paiol structures. This table is
-organized in a simply chained list. Then, \fBpat_crtpaiol()\fP copies the
-content of the old paiol list in the new table. No check is made by this
-function.
-
-.PP
-\fBpat_frepaiol()\fP deletes a list of paiol structures. No check is made
-by this function.
-
-.SH EXAMPLE
-.PP
-.nf
-#include <pat106.h>
-
-struct paiol *list;
-struct paiol *final_list;
-
-list = pat_addpaiol (list, "INA", 'X', 'I', 10);
-final_list = pat_crtpaiol (list);
-pat_frepaiol (list);
-.fi
-
-.SH SEE ALSO
-.PP
-libpat(3), paiol(3), namealloc(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/funpapat.3 b/alliance/share/man/man3/funpapat.3
deleted file mode 100644
index 644d6982..00000000
--- a/alliance/share/man/man3/funpapat.3
+++ /dev/null
@@ -1,74 +0,0 @@
-.\"   $Id: funpapat.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)funpapat.2 106 Sep 30 1996 UPMC ; VUONG Huu\-Nghia 
-.TH FUNPAPAT 3 "October 1, 1997" "ASIM/LIP6" "PAT functions"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBpat_addpapat, pat_frepapat\fP
-
-.SH SYNOPSYS
-.PP
-.nf
-struct papat *pat_addpapat (lastpapat, label, line)
-struct papat *lastpapat;
-char *label;
-unsigned short line;
-
-void pat_frepapat (listpapat)
-struct papat *listpapat;
-
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIlastpapat\fP
-pointer on the last papat structure
-.TP 10
-\fIlabel\fP
-pattern\'s label
-.TP 10
-\fIline\fP
-pattern\'s line number
-.TP 10
-\fIlistpapat\fP
-list of papat structures to be deleted
-
-.SH DESCRIPTION
-.PP
-A papat is a data structure representing a complete pattern including the
-actions associated with the pattern. A pattern is a set of values either
-forced (at the same time) on the inputs or predicted for the outputs (after
-the simulation step).
-
-.PP
-\fBpat_addpapat()\fP adds a papat structure at the top of a list of papat
-structures. The label registered in the papat is produced by \fBnamealloc()\fP.
-The function returns the pointer of the new list. No check is made by
-this function.
-
-.PP
-\fBpat_frepapat()\fP deletes a list of papat structures and all objects (paini
-and paevt) referenced by each papat structure in the list. If the list to be
-deleted is an empty list (NULL pointer), no action is produced. No check is
-made by this function.
-
-.SH EXAMPLE
-.PP
-.nf
-#include <pat106.h>
-
-struct papat *list;
-
-list = pat_addpapat (list, "ram_test", 123);
-pat_frepapat (list);
-.fi
-
-.SH SEE ALSO
-.PP
-libpat(3), papat(3), namealloc(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/funpaseq.3 b/alliance/share/man/man3/funpaseq.3
deleted file mode 100644
index ad975376..00000000
--- a/alliance/share/man/man3/funpaseq.3
+++ /dev/null
@@ -1,49 +0,0 @@
-.\"   $Id: funpaseq.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)paseq.2 106 Sep 30 1996 UPMC ; VUONG Huu-Nghia 
-.TH FUNPASEQ 3 "October 1, 1997" "ASIM/LIP6" "PAT functions"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBpat_addpaseq\fP
-
-.SH SYNOPSYS
-.PP
-.nf
-struct paseq *pat_addpaseq (lastpaseq)
-struct paseq *lastpaseq;
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIlastpaseq\fP
-pointer on the last paseq structure
-
-.SH DESCRIPTION
-.PP
-A paseq is a data structure representing a whole sequence of simulation
-patterns.
-
-.PP
-\fBpat_addpaseq()\fP adds an empty paseq structure at the top of a list of paseq
-structures. The function returns the pointer of the new list.
-No check is made by this function.
-
-.SH EXAMPLE
-.PP
-.nf
-#include <pat106.h>
-
-struct paseq *list;
-
-list = pat_addpaseq (list);
-.fi
-
-.SH SEE ALSO
-.PP
-libpat(3), paseq(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/garbagebddsystem.3 b/alliance/share/man/man3/garbagebddsystem.3
deleted file mode 100644
index 8e99a338..00000000
--- a/alliance/share/man/man3/garbagebddsystem.3
+++ /dev/null
@@ -1,62 +0,0 @@
-.\"   $Id: garbagebddsystem.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)garbagebddsystem.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH GARBAGEBDDSYSTEM 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-garbagebddsystem \- Forces a \fBbdd\fP garbage collection.
-
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-void garbagebddsystem( BddSystem )
-  bddsystem \(**BddSystem;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.SH DESCRIPTION
-\fBgarbagebddsystem\fP frees all the unused \fBbdd\fP nodes in the 
-system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-A \fBbdd\fP node is unused if its number of reference is null.
-.br
-.SH RETURN VALUE
-\fBgarbagebddsystem\fP returns nothing.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   chain_list \(**Expr;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   addbddcircuitin( (bddcircuit \(**)0, "i0", 0, BDD_IN_MODE_FIRST );
-   addbddcircuitin( (bddcircuit \(**)0, "i1", 0, BDD_IN_MODE_FIRST );
-   BddNode = applybddnode( (bddsystem \(**)0,
-                           ABL_AND,
-                           searchbddcircuitin( (bddcircuit \(**)0, "i0" ),
-                           searchbddcircuitin( (bddcircuit \(**)0, "i1" ) );
-   decbddrefext( BddNode );
-   garbagebddsystem( (bddsystem \(**)0 );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/gcNodeBdd.3 b/alliance/share/man/man3/gcNodeBdd.3
deleted file mode 100644
index 6812af0c..00000000
--- a/alliance/share/man/man3/gcNodeBdd.3
+++ /dev/null
@@ -1,59 +0,0 @@
-.\"   $Id: gcNodeBdd.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)gcNodeBdd.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH GCNODEBDD 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBgcNodeBdd\fP \- does a garbage collection 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-void gcNodeBdd(pt)
-chain_list *pt;
-.fi
-.SH PARAMETER
-.TP 20
-\fIpt\fP
-chained list of BDD to rescue
-.SH DESCRIPTION
-\fBgcNodeBdd()\fP removes all the nodes that aren't used in the BDD pointed in the chained list \fIpt\fP. 
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-pNode nodeA,nodeB,nodeC;
-pNode res1,res2;
-chain_list *ptCL;
-
-initializeBdd(SMALL_BDD);
-nodeA = createNodeTermBdd(3);
-nodeB = createNodeTermBdd(3);
-nodeC = createNodeTermBdd(4);
-
-res1 = applyBinBdd(OR,applyBinBdd(OR,nodeA,nodeB),nodeC);
-res2 = applyBinBdd(AND,applyBinBdd(AND,nodeA,nodeB),nodeC);
-printf("number of nodes in memory = %d",numberAllNodeBdd());
-
-/* it will display
-7
-*/
-ptCL = addchain(NULL,res1);
-gcNodeBdd(ptCL);		/* only res1 nodes are saved */ 
-
-freechain(ptCL);
-printf("number of nodes in memory = %d",numberAllNodeBdd());
-
-/* it will display
-number of nodes in memory = 5
-*/
-destroyBdd(1);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR markBdd (3),
-.BR supportChain_listBdd (3),
-.BR markAllBdd (3),
-.BR numberNodeBdd (3),
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/gcNodeCct.3 b/alliance/share/man/man3/gcNodeCct.3
deleted file mode 100644
index 640bb166..00000000
--- a/alliance/share/man/man3/gcNodeCct.3
+++ /dev/null
@@ -1,56 +0,0 @@
-.\"   $Id: gcNodeCct.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)gcNodeCct.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH GCNODECCT 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBgcNodeCct\fP \- does a garbage collection 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-void gcNodeCct(pC)
-pCircuit pC;
-.fi
-.SH PARAMETER
-.TP 20
-\fIpC\fP
-circuit on which the nodes are saved
-.SH DESCRIPTION
-\fBgcNodeCct()\fP does a garbarge collection by removing the nodes that aren't pointed in \fIpC\fP.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-pCircuit pC;
-chain_list *expr;
-
-initializeBdd(SMALL_BDD);
-pC = initializeCct("circuit 1",10,10);
-
-addInputCct(pC,"a");
-addInputCct(pC,"b");
-
-	/* let's suppose that expr = (OR a b) */
-
-addOuputCct(pC,"s1",one);
-addOuputCct(pC,"s2",ablToBddCct(pC,expr));
-
-printf("number of nodes of the BDDs system = %d",numberNodeAllBdd());
-gcNodeCct(pC,1)
-printf("After GC : number of nodes of the BDDs system = %d",numberNodeAllBdd());
-
-/* it will display
-number of nodes of the BDDs system = 3
-After GC : number of nodes of the BDDs system = 2
-*/
-
-destroyCct(pC);
-destroyBdd(1);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR gcNodeCct (3),
-.BR numberAllNodeBdd (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/getablexprdepth.3 b/alliance/share/man/man3/getablexprdepth.3
deleted file mode 100644
index a8c47f95..00000000
--- a/alliance/share/man/man3/getablexprdepth.3
+++ /dev/null
@@ -1,50 +0,0 @@
-.\"   $Id: getablexprdepth.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)getablexprdepth.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH GETABLEXPRDEPTH 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-getablexprdepth \- gives the depth of an expression.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-long getablexprdepth( Expr )
-  chain_list \(**Expr;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIExpr\fP
-Expression.
-.SH DESCRIPTION
-\fBgetablexprdepth\fP gives the depth of an expression.
-.br
-.SH RETURN VALUE
-\fBgetablexprdepth\fP returns the depth of \fIExpr\fP.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-   chain_list \(**ExprA;
-   chain_list \(**ExprB;
-   chain_list \(**ExprAorB;
-   ExprA = createablatom( "a" );
-   ExprB = createablatom( "b" );
-   ExprAorB  = createablbinexpr( ABL_OR, ExprA, ExprB );
-   /* displays 1 */
-   printf( "%d", getablexprdepth( ExprAorB ) );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/getablexprlength.3 b/alliance/share/man/man3/getablexprlength.3
deleted file mode 100644
index 1548ad5e..00000000
--- a/alliance/share/man/man3/getablexprlength.3
+++ /dev/null
@@ -1,50 +0,0 @@
-.\"   $Id: getablexprlength.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)getablexprlength.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH GETABLEXPRLENGTH 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-getablexprlength \- gives the length of an expression.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-long getablexprlength( Expr )
-  chain_list \(**Expr;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIExpr\fP
-Expression.
-.SH DESCRIPTION
-\fBgetablexprlength\fP gives the length of an expression.
-.br
-.SH RETURN VALUE
-\fBgetablexprlength\fP returns the length of \fIExpr\fP.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-   chain_list \(**ExprA;
-   chain_list \(**ExprB;
-   chain_list \(**ExprAorB;
-   ExprA = createablatom( "a" );
-   ExprB = createablatom( "b" );
-   ExprAorB  = createablbinexpr( ABL_OR, ExprA, ExprB );
-   /* displays 2 */
-   printf( "%d", getablexprlength( ExprAorB ) );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/getablexprmax.3 b/alliance/share/man/man3/getablexprmax.3
deleted file mode 100644
index bda8c6b5..00000000
--- a/alliance/share/man/man3/getablexprmax.3
+++ /dev/null
@@ -1,61 +0,0 @@
-.\"   $Id: getablexprmax.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)getablexprmax.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH GETABLEXPRMAX 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-getablexprmax \- applies a function to all operands.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-chain_list \(**getablexprmax( Function, Expr )
-  int       (\(**Function)();
-  chain_list \(**Expr;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIFunction\fP
-Cost function.
-.TP
-\fIExpr\fP
-Expression to scan.
-.SH DESCRIPTION
-\fBgetablexprmax\fP applies the cost function \fIFunction\fP to all operands of \fIExpr\fP.
-.br
-.SH RETURN VALUE
-\fBgetablexprmax\fP returns the operand for which \fFunction\fP gives the maximum cost.
-The expression pointer returned MUSTN'T be modified after the call to this function.
-.SH ERRORS
-getablexprmax error ...
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-    int MapFunction( MapExpr )
-      chain_list \(**MapExpr;
-    {
-      return( getabldepthexpr( MapExpr ) );
-    }
-    ...
-    chain_list \(**Expr;
-    chain_list \(**Expr1;
-    Expr = createablbinexpr( ABL_AND, 
-                             createablatom( "a" ),
-                             createablatom( "b" ) );
-   Expr1 = getablexprmax( MapFunction, Expr );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/getablexprmin.3 b/alliance/share/man/man3/getablexprmin.3
deleted file mode 100644
index ecfbc296..00000000
--- a/alliance/share/man/man3/getablexprmin.3
+++ /dev/null
@@ -1,61 +0,0 @@
-.\"   $Id: getablexprmin.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)getablexprmin.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH GETABLEXPRMIN 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-getablexprmin \- applies a function to all operands.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-chain_list \(**getablexprmin( Function, Expr )
-  int       (\(**Function)();
-  chain_list \(**Expr;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIFunction\fP
-Cost function.
-.TP
-\fIExpr\fP
-Expression to scan.
-.SH DESCRIPTION
-\fBgetablexprmin\fP applies the cost function \fIFunction\fP to all operands of \fIExpr\fP.
-.br
-.SH RETURN VALUE
-\fBgetablexprmin\fP returns the operand for which \fFunction\fP gives the minimum cost.
-The expression pointer returned MUSTN'T be modified after the call to this function.
-.SH ERRORS
-getablexprmin error ...
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-    int MapFunction( MapExpr )
-      chain_list \(**MapExpr;
-    {
-      return( getabldepthexpr( MapExpr ) );
-    }
-    ...
-    chain_list \(**Expr;
-    chain_list \(**Expr1;
-    Expr = createablbinexpr( ABL_AND, 
-                             createablatom( "a" ),
-                             createablatom( "b" ) );
-   Expr1 = getablexprmin( MapFunction, Expr );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/getablexprnum.3 b/alliance/share/man/man3/getablexprnum.3
deleted file mode 100644
index 9f8b2fe5..00000000
--- a/alliance/share/man/man3/getablexprnum.3
+++ /dev/null
@@ -1,52 +0,0 @@
-.\"   $Id: getablexprnum.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)getablexprnum.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH GETABLEXPRNUM 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-getablexprnum \- gives a specified operand of an expression.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-chain_list \(**getablexprnum( Expr, Number )
-  chain_list \(**Expr;
-  int        Number;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIExpr\fP
-Expression.
-.TP
-\fINumber\fP
-Operand number.
-.SH DESCRIPTION
-\fBgetablexprnum\fP gives the operand \fINumber\fP of \fIExpr\fP.
-.br
-.SH RETURN VALUE
-\fBgetablexprnum\fP returns the operand \fINumber\fP of \fIExpr\fP.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-  chain_list \(**Expr;
-  Expr = createablbinexpr( ABL_AND,
-                           createablatom( "a" ),
-                           createablatom( "b" ) );
-  /* displays    b */
-  viewablexpr( getablexprnum( Expr, 1 ), ABL_VIEW_VHDL );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/getablexprnumatom.3 b/alliance/share/man/man3/getablexprnumatom.3
deleted file mode 100644
index 8eb6d147..00000000
--- a/alliance/share/man/man3/getablexprnumatom.3
+++ /dev/null
@@ -1,48 +0,0 @@
-.\"   $Id: getablexprnumatom.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)getablexprnumatom.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH GETABLEXPRNUMATOM 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-getablexprnumatom \- gives the number of atom in an expression.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-long getablexprnumatom( Expr )
-  chain_list \(**Expr;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIExpr\fP
-Expression.
-.SH DESCRIPTION
-\fBgetablexprnumatom\fP gives the number of atom in \fIExpr\fP.
-.br
-.SH RETURN VALUE
-\fBgetablexprnumatom\fP returns the number of atom in \fIExpr\fP.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-  chain_list \(**Expr;
-  Expr = createablbinexpr( ABL_AND,
-                           createablatom( "'0'" ),
-                           createablatom( "'1'" ) );
-  /* displays 2 */
-  printf( "%d", getablexprnumatom( Expr ) );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/getablexprnumbinoper.3 b/alliance/share/man/man3/getablexprnumbinoper.3
deleted file mode 100644
index 904839f6..00000000
--- a/alliance/share/man/man3/getablexprnumbinoper.3
+++ /dev/null
@@ -1,48 +0,0 @@
-.\"   $Id: getablexprnumbinoper.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)getablexprnumbinoper.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH GETABLEXPRNUMBINOPER 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-getablexprnumbinoper \- gives the number of binary operators in an expression.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-long getablexprnumbinoper( Expr )
-  chain_list \(**Expr;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIExpr\fP
-Expression.
-.SH DESCRIPTION
-\fBgetablexprnumbinoper\fP gives the number of binary operators in \fIExpr\fP.
-.br
-.SH RETURN VALUE
-\fBgetablexprnumbinoper\fP returns the number of binary operators in \fIExpr\fP.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-  chain_list \(**Expr;
-  Expr = createablbinexpr( ABL_AND,
-                           createablatom( "'0'" ),
-                           createablatom( "'1'" ) );
-  /* displays 1 */
-  printf( "%d", getablexprnumbinoper( Expr ) );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/getablexprnumocc.3 b/alliance/share/man/man3/getablexprnumocc.3
deleted file mode 100644
index 8ce57345..00000000
--- a/alliance/share/man/man3/getablexprnumocc.3
+++ /dev/null
@@ -1,52 +0,0 @@
-.\"   $Id: getablexprnumocc.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)getablexprnumocc.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH GETABLEXPRNUMOCC 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-getablexprnumocc \- how many times a name appears in an expression.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-long getablexprnumocc( Expr, Name )
-  chain_list \(**Expr;
-  char       \(**Name;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIExpr\fP
-Expression.
-.TP
-\fIName\fP
-Name to find.
-.SH DESCRIPTION
-\fBgetablexprnumocc\fP gives the number of occurents of \fIName\fP in \fIExpr\fP.
-.br
-.SH RETURN VALUE
-\fBgetablexprnumocc\fP returns number of occurents of \fIName\fP in \fIExpr\fP.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-  chain_list \(**Expr;
-  Expr = createablbinexpr( ABL_AND,
-                           createablatom( "a" ),
-                           createablatom( "b" ) );
-  /* displays 1 */
-  printf( "%d", getablexprnumocc( Expr, "a" ) );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/getablexprsupport.3 b/alliance/share/man/man3/getablexprsupport.3
deleted file mode 100644
index 77f8c39a..00000000
--- a/alliance/share/man/man3/getablexprsupport.3
+++ /dev/null
@@ -1,65 +0,0 @@
-.\"   $Id: getablexprsupport.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)getablexprsupport.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH GETABLEXPRSUPPORT 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-getablexprsupport \- gives the expression's support.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
- void \(**getablexprsupport( Expr, Mode )
-  chain_list \(**Expr;
-  int         Mode;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIExpr\fP
-Expression.
-.TP
-\fIMode\fP
-The returned support's mode.
-.SH DESCRIPTION
-\fBgetablexprsupport\fP gives the support of \fIExpr\fP. if \fIMode\fP
-is ABL_SUPPORT_CHAIN the support is returned using \fIchain_list\fP
-else it is returned using \fIptype_list\fP. The support must be freed
-using the \fIfreechain\fP or \fIfreeptype\fP functions.
-.br
-.SH RETURN VALUE
-\fBgetablexprsupport\fP returns a pointer to a \fIchain_list\fP or
-a \fIptype_list\fP.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-  chain_list \(**Expr;
-  ptype_list \(**Support;
-  ptype_list \(**ScanSupport;
-  Expr = createablbinexpr( ABL_AND,
-                           createablatom( "a" ),
-                           createablatom( "b" ) );
-  Support = getablexprsupport( Expr, ABL_SUPPORT_PTYPE );
-  /* displays a b */
-  for ( ScanSupport  = Support; 
-        ScanSupport != (ptype_list \(**)0;
-        ScanSupport  = ScanSupport->NEXT )
-  {
-    printf( "%s ", (char *)ScanSupport->DATA );
-  }
-  freeptype( Support );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/getbddnodenum.3 b/alliance/share/man/man3/getbddnodenum.3
deleted file mode 100644
index e887357c..00000000
--- a/alliance/share/man/man3/getbddnodenum.3
+++ /dev/null
@@ -1,63 +0,0 @@
-.\"   $Id: getbddnodenum.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)getbddnodenum.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH GETBDDNODENUM 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-getbddnodenum \- gets the number of nodes in a \fBbdd\fP.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-long getbddnodenum( BddSystem, BddNode )
-  bddsystem \(**BddSystem;
-  bddnode   \(**BddNode;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIBddNode\fP
-The \fBbdd\fP node.
-.SH DESCRIPTION
-\fBgetbddnodenum\fP computes the number of different nodes in \fIBddNode\fP,
-in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBgetbddnodenum\fP returns the number of the different nodes reached.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   chain_list \(**Expr;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   Expr = createablbinexpr( ABL_AND,
-                            createablatom( "i0" ),
-                            createablatom( "i1" ) );
-   BddNode = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   printf( "Number nodes: %ld\n",
-           getbddnodenum( (bddsystem \(**)0, BddNode ) );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/getbddnodesize.3 b/alliance/share/man/man3/getbddnodesize.3
deleted file mode 100644
index 6be2f3df..00000000
--- a/alliance/share/man/man3/getbddnodesize.3
+++ /dev/null
@@ -1,63 +0,0 @@
-.\"   $Id: getbddnodesize.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)getbddnodesize.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH GETBDDNODESIZE 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-getbddnodesize \- gets the number of nodes in a \fBbdd\fP.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-long getbddnodesize( BddSystem, BddNode )
-  bddsystem \(**BddSystem;
-  bddnode   \(**BddNode;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIBddNode\fP
-The \fBbdd\fP node.
-.SH DESCRIPTION
-\fBgetbddnodesize\fP computes the total number of nodes in \fIBddNode\fP,
-in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBgetbddnodesize\fP returns the number of nodes reached.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   chain_list \(**Expr;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   Expr = createablbinexpr( ABL_AND,
-                            createablatom( "i0" ),
-                            createablatom( "i1" ) );
-   BddNode = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   printf( "Number nodes: %ld\n",
-           getbddnodesize( (bddsystem \(**)0, BddNode ) );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/getbddnodesupport.3 b/alliance/share/man/man3/getbddnodesupport.3
deleted file mode 100644
index 0e65ccdf..00000000
--- a/alliance/share/man/man3/getbddnodesupport.3
+++ /dev/null
@@ -1,81 +0,0 @@
-.\"   $Id: getbddnodesupport.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)getbddnodesupport.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH GETBDDNODESUPPORT 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-getbddnodesupport \- gives the variable support of a \fBbdd\fP node.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-void \(**getbddnodesupport( BddSystem, BddNode, Mode )
-  bddsystem \(**BddSystem;
-  bddnode   \(**BddNode;
-  int        Mode;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIBddNode\fP
-The \fBbdd\fP node.
-.TP
-\fIMode\fP
-The type of support.
-.SH DESCRIPTION
-\fBgetbddnodesupport\fP gives the support of the \fBbdd\fP node \fIBddNode\fP
-in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-If \fIMode\fP is BDD_SUPPORT_CHAIN the support is returned using 
-\fIchain_list\fP else it is returned using \fIptype_list\fP.
-The support must be freed using the \fIfreechain\fP or \fIfreeptype\fP functions.
-.br
-.SH RETURN VALUE
-\fBgetablexprsupport\fP returns a pointer to a \fIchain_list\fP or
-a \fIptype_list\fP.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   chain_list \(**Expr;
-   chain_list \(**Support;
-   chain_list \(**ScanSupport;
-   bddindex       Index;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   Expr = createablbinexpr( ABL_AND,
-                            createablatom( "i0" ),
-                            createablatom( "i1" ) );
-   BddNode = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   Support = getablbddnodesupport( (bddsystem \(**0), BddNode, BDD_SUPPORT_CHAIN );
-   for ( ScanSupport  = Support;
-         ScanSupport != (chain_list \(**)0;
-         ScanSupport  = ScanSupport->NEXT )
-   {
-     Index = (bddnode \(**)ScanSupport->INDEX;
-     printf( "%s ", BddCircuit->NAME_IN[ Index - BDD_INDEX_MIN ] );
-   }
-   freechain( Support );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/getbddvarbyindex.3 b/alliance/share/man/man3/getbddvarbyindex.3
deleted file mode 100644
index 392c2beb..00000000
--- a/alliance/share/man/man3/getbddvarbyindex.3
+++ /dev/null
@@ -1,66 +0,0 @@
-.\"   $Id: getbddvarbyindex.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)getbddvarbyindex.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH GETBDDVARBYINDEX 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-getbddvarbyindex \- converts \fBbdd\fP index to a variable number.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddindex getbddvarbyindex( BddSystem, Index )
-  bddsystem \(**BddSystem;
-  bddindex   Index;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIIndex\fP
-The \fBbdd\fP index to convert.
-.SH DESCRIPTION
-\fBgetbddvarbyindex\fP converts the \fBbdd\fP index  \fIIndex
-to a variable number, in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-The function uses simply the translation table \fIBddSystem\fP->INDEX_TO_VAR.
-.br
-.SH RETURN VALUE
-\fBgetbddvarbyindex\fP returns the variable number of the \fBbdd\fP index \fIIndex\fP.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"index xxx out of range, error !"
-.ft R
-.RS
-The \fIIndex parameter must be a valid index.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddnode    \(**BddNode;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddNode = addbddvar( (bddsystem \(**)0, 0 );
-   /* displays 0 */
-   printf( "%d", getbddvarbyindex( (bddsystem \(**)0, BddNode->INDEX ) );
-   destroybddsystem( (bddsystem \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/getbddvarindex.3 b/alliance/share/man/man3/getbddvarindex.3
deleted file mode 100644
index b1d2256d..00000000
--- a/alliance/share/man/man3/getbddvarindex.3
+++ /dev/null
@@ -1,67 +0,0 @@
-.\"   $Id: getbddvarindex.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)getbddvarindex.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH GETBDDVARINDEX 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-getbddvarindex \- converts a variable number in a \fBbdd\fP index.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddindex getbddvarindex( BddSystem, Variable )
-  bddsystem \(**BddSystem;
-  bddvar     Variable;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIVariable\fP
-The variable number to convert.
-.SH DESCRIPTION
-\fBgetbddvarindex\fP converts the variable number \fIVariable\fP
-to a \fBbdd\fP index, in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-The function uses simply the translation table \fIBddSystem\fP->VAR_TO_INDEX.
-.br
-.SH RETURN VALUE
-\fBgetbddvarindex\fP returns the \fBbdd\fP index of \fIVariable\fP.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"variable xxx out of range, error !"
-.ft R
-.RS
-The \fIVariable\fP parameter must be less or equal to
-the \fIBddSystem->NUMBER_VAR\fP field.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddnode    \(**BddNode;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddNode = addbddvar( (bddsystem \(**)0, 0 );
-   /* displays 2 */
-   printf( "%d", getbddvarindex( (bddsystem \(**)0, 0 ) );
-   destroybddsystem( (bddsystem \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/getbddvarnode.3 b/alliance/share/man/man3/getbddvarnode.3
deleted file mode 100644
index fde44a54..00000000
--- a/alliance/share/man/man3/getbddvarnode.3
+++ /dev/null
@@ -1,66 +0,0 @@
-.\"   $Id: getbddvarnode.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)getbddvarnode.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH GETBDDVARNODE 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-getbddvarnode \- gives the \fBbdd\fP node of a variable.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddnode \(**getbddvarnode( BddSystem, Variable )
-  bddsystem \(**BddSystem;
-  bddvar     Variable;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIVariable\fP
-The variable number.
-.SH DESCRIPTION
-\fBgetbddvarnode\fP gives the \fBbdd\fP node of the variable number
-\fIVariable\fP, in the \fBbdd\fP system BddSystem.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBgetbddvarnode\fP returns a pointer to the variable \fBbdd\fP node.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"variable xxx out of range, error !"
-.ft R
-.RS
-The \fIVariable\fP parameter must be less or equal to
-the \fIBddSystem->NUMBER_VAR\fP field.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddnode    \(**BddNode;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   addbddvar( (bddsystem \(**)0, 0 );
-   BddNode = getbddvarnode( (bddsystem \(**)0, 0 );
-   ...
-   destroybddsystem( (bddsystem \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/getbddvarnodebyindex.3 b/alliance/share/man/man3/getbddvarnodebyindex.3
deleted file mode 100644
index 5bdf0c34..00000000
--- a/alliance/share/man/man3/getbddvarnodebyindex.3
+++ /dev/null
@@ -1,66 +0,0 @@
-.\"   $Id: getbddvarnodebyindex.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)getbddvarnode.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH GETBDDVARNODEBYINDEX 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-getbddvarnode \- gives the \fBbdd\fP node of a variable.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddnode \(**getbddvarnodebyindex( BddSystem, Index )
-  bddsystem \(**BddSystem;
-  bddindex   Index;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIIndex\fP
-The \fBbdd\fP index.
-.SH DESCRIPTION
-\fBgetbddvarnode\fP gives the \fBbdd\fP node of the \fBbdd\fP index
-\fIIndex\fP, in the \fBbdd\fP system BddSystem.
-If a null pointer is given, the default \fBbdd\fP system is used.
-The function uses simply the table \fIBddSystem\fP->VAR_NODE.
-.br
-.SH RETURN VALUE
-\fBgetbddvarnode\fP returns a pointer to the variable \fBbdd\fP node.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"index xxx out of range, error !"
-.ft R
-.RS
-The \fIIndex\fP parameter must be a valid index.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddnode    \(**BddNode;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   addbddvar( (bddsystem \(**)0, 0 );
-   BddNode = getbddvarnodebyindex( (bddsystem \(**)0, 2 );
-   ...
-   destroybddsystem( (bddsystem \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/gethtitem.3 b/alliance/share/man/man3/gethtitem.3
deleted file mode 100644
index 98c7f416..00000000
--- a/alliance/share/man/man3/gethtitem.3
+++ /dev/null
@@ -1,87 +0,0 @@
-.\"   $Id: gethtitem.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)gethtitem.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.\" slightly modified by Fred Petrot for mbk adaptation on 22/06/92
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-gethtitem
-.XE
-.XS4 \n%
-.ti 0.2i
-gethtitem
-.XE4 \}
-.TH GETHTITEM 3 "October 1, 1997" "ASIM/LIP6" "MBK HASH TABLE MANAGEMENT FUNCTIONS"
-.SH NAME
-gethtitem \- searches an item in a hash table
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.nf
-#include "mut315.h"
-int gethtitem(table, key)
-ht \(**table;
-void \(**key;
-.fi
-.ft R
-.SH PARAMETERS
-.TP 20
-\fItable\fP
-Hash table pointer
-.TP 20
-\fIkey\fP
-Key used by the hash coding function
-.SH DESCRIPTION
-\fBgethtitem()\fP searches an item in the hash table pointed to by \fItable\fP.
-.SH RETURN VALUE
-If the key \fIkey\fP exists, the associated value is returned,
-if it doesn't, the function returns \fBEMPTYHT\fP.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.nf
-#include <stdio.h>
-#include "mut315.h"
-check(p)
-losig_list *p;
-{
-char *amatla;
-losig_list *ptsig;
-locon_list *ptcon;
-ht *h;
-	for (i = 0, ptsig = p->LOSIG; ptsig; i++, ptsig = ptsig->NEXT);
-	h = addht(i);
-	/* two connectors can't have the same name! */
-	for (ptcon = p->LOCON; ptcon; ptcon = ptcon->NEXT)
-		addhtitem(h, ptcon->NAME, 0);
-	for (ptsig = p->LOSIG; ptsig; ptsig = ptsig->NEXT) {
-		if (ptsig->TYPE == INTERNAL) {
-			amatla = getsigname(ptsig);
-			/* this is nicely done with sethtitem! */
-			if (gethtitem(h, amatla) == EMPTYHT) { 
-				printf("N %s;\\n", amatla);
-				addhtitem(h, amatla, 0);
-			}
-		}
-	}
-	delht();
-}
-.fi
-.ft R
-.SH SEE ALSO
-.BR mbk (1),
-.BR addht (3),
-.BR delht (3),
-.BR addhtitem (3),
-.BR delhtitem (3),
-.BR viewht (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/getlocon.3 b/alliance/share/man/man3/getlocon.3
deleted file mode 100644
index 09ff6c73..00000000
--- a/alliance/share/man/man3/getlocon.3
+++ /dev/null
@@ -1,77 +0,0 @@
-.\"   $Id: getlocon.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)getlocon.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-getlocon
-.XE
-.XS2 \n%
-.ti 0.2i
-getlocon
-.XE2 \}
-.TH GETLOCON 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL FUNCTIONS"
-.SH NAME
-getlocon \- retrieve a logical connector
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-locon_list \(**getlocon(ptfig, name)
-lofig_list \(**ptfig;
-char \(**name;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptfig\fP
-Pointer to the figure in which the connector should be seeked
-.TP
-\fIname\fP
-Name of the connector
-.SH DESCRIPTION
-\fBgetlocon\fP looks in the list of connectors of the logical model pointed
-to by \fIptfig\fP for a connector identified by its \fIname\fP, since it
-should be unique at a given hierachical level.
-.SH RETURN VALUE
-\fBgetlocon\fP returns a pointer to the given connector.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** getlocon impossible :
-connector \fIname\fP doesn't exist in figure \fIptfig\->NAME\fP"
-.ft R
-.RS
-No connector matches the name. 
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-locon_list \(**exist(figname, conname)
-char \(**figname, \(**conname;
-{
-   return getlocon(getlofig(figname), conname);   
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR lofig (3),
-.BR locon (3),
-.BR addlocon (3),
-.BR dellocon (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/getlofig.3 b/alliance/share/man/man3/getlofig.3
deleted file mode 100644
index f5de7131..00000000
--- a/alliance/share/man/man3/getlofig.3
+++ /dev/null
@@ -1,81 +0,0 @@
-.\"   $Id: getlofig.3,v 1.1 1999/05/31 17:30:21 alliance Exp $
-.\" @(#)getlofig.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-getlofig
-.XE
-.XS3 \n%
-.ti 0.2i
-getlofig
-.XE3 \}
-.TH GETLOFIG 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL UTILITY FUNCTIONS"
-.SH NAME
-getlofig \- give back a pointer to a \fIlofig\fP 
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo412.h"
-lofig_list \(**getlofig(figname, mode)
-char \(**figname;
-char mode;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIfigname\fP
-Name of the figure to be created
-.TP
-\fImode\fP
-Demanded mode for the figure
-.SH DESCRIPTION
-\fBgetlofig\fP returns a pointer to the figure called \fIfigname\fP with the
-warranty that the expected information is present in memory.
-.br
-If \fImode\fP is \fB'A'\fP then the figure has all its lists filled, else
-the figure may either be complete or interface only.
-.br
-This function allows to completly mask disk access for applications
-programs. If the figure is in memory, with the specified \fImode\fP,
-then the function returns the appropriate pointer. Else, the function performs
-a call to the \fBloadlofig(3)\fP and returns a pointer to the loaded
-figure.
-.SH RETURN VALUE
-\fBgetlofig\fP returns a pointer to the wanted figure.
-.SH ERRORS
-\fBgetlofig\fP cannot give any errors, but the subsequent calls it performs
-to parsers do. So the source of trouble may be the call to \fBgetlofig\fP.
-See \fBloadlofig\fP(3) for details.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo412.h"
-lofig_list \(**na2_y()
-{
-	/\(** find in memory or load from disk na2_y \(**/
-	return getlofig("na2_y", 'A');
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR lofig (3),
-.BR addlofig (3),
-.BR dellofig (3),
-.BR loadlofig (3),
-.BR savelofig (3),
-.BR flattenlofig (3),
-.BR rflattenlofig (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/getloins.3 b/alliance/share/man/man3/getloins.3
deleted file mode 100644
index 597ca8ac..00000000
--- a/alliance/share/man/man3/getloins.3
+++ /dev/null
@@ -1,78 +0,0 @@
-.\"   $Id: getloins.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)getloins.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-getloins
-.XE
-.XS2 \n%
-.ti 0.2i
-getloins
-.XE2 \}
-.TH GETLOINS 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL FUNCTIONS"
-.SH NAME
-getloins \- retrieve a logical instance
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-loins_list \(**getloins(ptfig, name)
-lofig_list \(**ptfig;
-char \(**name;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptfig\fP
-Pointer to the figure in which the instance should be seeked
-.TP
-\fIname\fP
-Name of the instance
-.SH DESCRIPTION
-\fBgetloins\fP looks in the list of instances of the logical model pointed
-to by \fIptfig\fP for a instance identified by its \fIname\fP. This instance
-is unique, since the \fIname\fP is the instance identifier.
-.SH RETURN VALUE
-\fBgetloins\fP returns a pointer to the instance that matches the
-\fIname\fP.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** illegal getloins instance \fIname\fP doesn't exist
-in figure \fIptfig\->NAME\fP" 
-.ft R
-.RS
-No instance is called \fIname\fP in the figure. 
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-loins_list \(**get_ins_by_name(figname, insname)
-char \(**figname, \(**insname;
-{
-   return getloins(getlofig(figname), insname);   
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR lofig (3),
-.BR loins (3),
-.BR addloins (3),
-.BR delloins (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/getlomodel.3 b/alliance/share/man/man3/getlomodel.3
deleted file mode 100644
index 7a2a71a6..00000000
--- a/alliance/share/man/man3/getlomodel.3
+++ /dev/null
@@ -1,68 +0,0 @@
-.\"   $Id: getlomodel.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)getlomodel.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-getlomodel
-.XE
-.XS2 \n%
-.ti 0.2i
-getlomodel
-.XE2 \}
-.TH GETLOMODEL 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL FUNCTIONS"
-.SH NAME
-getlomodel \- retrieve a model from a \fBlofig_list\fP
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut404.h"
-lofig_list \(**getlomodel(model, name)
-lofig_list \(**model;
-char \(**name;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fImodel\fP
-Pointer to a lofig list
-.TP
-\fIname\fP
-String indicating the model to be looked for
-.SH DESCRIPTION
-\fBgetlomodel\fP seeks a \fBlofig\fP element in the list pointed to by
-\fImodel\fP.
-.SH RETURN VALUE
-\fBgetlomodel\fP returns a pointer to the \fBlofig\fP that match the \fIname\fP.
-If no \fBlofig\fP has the given \fIname\fP, then \fBNULL\fP is returned.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-locon_list *get_model_cons(model, name)
-lofig_list \(**model;
-char \(**name;
-{
-lofig_list \(**p = getlomodel(model, name);
-	return p ? p\->LOCON : NULL;
-}	
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR lofig (3),
-.BR addlomodel (3),
-.BR freelomodel (3),
-.BR dellomodel (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/getlosig.3 b/alliance/share/man/man3/getlosig.3
deleted file mode 100644
index 76206a30..00000000
--- a/alliance/share/man/man3/getlosig.3
+++ /dev/null
@@ -1,79 +0,0 @@
-.\"   $Id: getlosig.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)getlosig.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-getlosig
-.XE
-.XS2 \n%
-.ti 0.2i
-getlosig
-.XE2 \}
-.TH GETLOSIG 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL FUNCTIONS"
-.SH NAME
-getlosig \- retrieve a logical signal
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-losig_list \(**getlosig(ptfig, index)
-lofig_list \(**ptfig;
-long index;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptfig\fP
-Pointer to the figure in which the signal should be seeked
-.TP
-\fIindex\fP
-Index of the signal
-.SH DESCRIPTION
-\fBgetlosig\fP looks in the list of signals of the logical model pointed
-to by \fIptfig\fP for a signal identified by its \fIindex\fP. This signal
-is unique, since the \fIindex\fP is the signal identifier.
-.SH RETURN VALUE
-\fBgetlosig\fP returns a pointer to the signal that matches the
-\fIindex\fP.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** illegal getlosig signal \fIindex\fP doesn't exist
-in figure \fIptfig\->NAME\fP" 
-.ft R
-.RS
-No signal has \fIindex\fP as \fIINDEX\fP in the figure.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-losig_list \(**get_sig_by_name(figname, index)
-char \(**figname;
-long index;
-{
-   return getlosig(getlofig(figname), index);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR lofig (3),
-.BR losig (3),
-.BR addlosig (3),
-.BR dellosig (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/getphcon.3 b/alliance/share/man/man3/getphcon.3
deleted file mode 100644
index 22d1d157..00000000
--- a/alliance/share/man/man3/getphcon.3
+++ /dev/null
@@ -1,83 +0,0 @@
-.\"   $Id: getphcon.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)getphcon.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-getphcon
-.XE
-.XS0 \n%
-.ti 0.2i
-getphcon
-.XE0 \}
-.TH GETPHCON 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL FUNCTIONS"
-.SH NAME
-getphcon \- retrieve a physical connector
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-phcon_list \(**getphcon(ptfig, conname, index)
-phfig_list \(**ptfig;
-char \(**conname;
-long index;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptfig\fP
-Pointer to the figure in which the connector should be seeked
-.TP
-\fIconname\fP
-Name of the connector
-.TP
-\fIindex\fP
-Connector index
-.SH DESCRIPTION
-\fBgetphcon\fP looks in the list of connectors of the physical model pointed
-to by \fIptfig\fP for a connector identified by its \fIconname\fP and
-\fIindex\fP. Both are needed to make sure the right connector is given back
-since \fIn\fP internally wired connectors have the same name.
-.SH RETURN VALUE
-\fBgetphcon\fP returns a pointer to the given connector.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** illegal getphcon connector \fIconname.index\fP 
-doesn't exist in figure \fIptfig\->NAME\fP"
-.ft R
-.RS
-No connectors match both arguments. 
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-phcon_list \(**exist(figname, conname)
-char \(**figname, \(**conname;
-{
-   /\(** if only one exists, it's this one \(**/
-   return getphcon(getphfig(figname), conname, 0L);   
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR phfig (3),
-.BR phcon (3),
-.BR addphcon (3),
-.BR delphcon (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/getphfig.3 b/alliance/share/man/man3/getphfig.3
deleted file mode 100644
index bd218d1e..00000000
--- a/alliance/share/man/man3/getphfig.3
+++ /dev/null
@@ -1,80 +0,0 @@
-.\"   $Id: getphfig.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)getphfig.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-getphfig
-.XE
-.XS1 \n%
-.ti 0.2i
-getphfig
-.XE1 \}
-.TH GETPHFIG 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL UTILITY FUNCTIONS"
-.SH NAME
-getphfig \- give back a pointer to a \fIphfig\fP 
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph403.h"
-phfig_list \(**getphfig(figname, mode)
-char \(**figname;
-char mode;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIfigname\fP
-Name of the figure to be created
-\fImode\fP
-Demanded mode for the figure
-.SH DESCRIPTION
-\fBgetphfig\fP returns a pointer to the figure called \fIfigname\fP with the
-warranty that the expected information is present in memory.
-.br
-If \fImode\fP is \fB'A'\fP then the figure has all its lists filled, else
-the figure may either be complete or interface only.
-.br
-This function allows to completly mask disk access for applications
-programs. If the figure is in memory, with the specified \fImode\fP,
-then the function returns the appropriate pointer. Else, the function performs
-a call to the \fBloadphfig\fP(3) and returns a pointer to the loaded
-figure.
-.SH RETURN VALUE
-\fBgetphfig\fP returns a pointer to the wanted figure.
-.SH ERRORS
-\fBgetphfig\fP cannot give any errors, but the subsequent calls it performs
-to parsers do. So the source of trouble may be the call to \fBgetphfig\fP.
-See \fBloadphfig\fP(3) for details.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph403.h"
-phfig_list \(**na2_y()
-{
-	/\(** find in memory or load from disk na2_y \(**/
-	return getphfig("na2_y", 'A');
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR phfig (3),
-.BR addphfig (3),
-.BR delphfig (3),
-.BR loadphfig (3),
-.BR savephfig (3),
-.BR flattenphfig (3),
-.BR rflattenphfig (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/getphins.3 b/alliance/share/man/man3/getphins.3
deleted file mode 100644
index ee4fba6e..00000000
--- a/alliance/share/man/man3/getphins.3
+++ /dev/null
@@ -1,77 +0,0 @@
-.\"   $Id: getphins.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)getphins.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-getphins
-.XE
-.XS0 \n%
-.ti 0.2i
-getphins
-.XE0 \}
-.TH GETPHINS 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL FUNCTIONS"
-.SH NAME
-getphins \- retrieve a physical instance
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-phins_list \(**getphins(ptfig, insname)
-phfig_list \(**ptfig;
-char \(**insname;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptfig\fP
-Pointer to the figure in which the instance should be seeked
-.TP
-\fIinsname\fP
-Name of the instance
-.SH DESCRIPTION
-\fBgetphins\fP looks in the list of instances of the physical model pointed
-to by \fIptfig\fP for a instance identified by its \fIinsname\fP.
-.SH RETURN VALUE
-\fBgetphins\fP returns a pointer to the instance that matches the
-\fIinsname\fP.
-.SH ERROR
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** illegal getphins instance \fIinsname\fP doesn't exist
-in figure \fIptfig\->NAME\fP" 
-.ft R
-.RS
-No instance is called \fIinsname\fP in the figure. 
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-phins_list \(**exist(figname, insname)
-char \(**figname, \(**insname;
-{
-   return getphins(getphfig(figname), insname);   
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR phfig (3),
-.BR phins (3),
-.BR addphins (3),
-.BR delphins (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/getphref.3 b/alliance/share/man/man3/getphref.3
deleted file mode 100644
index a4f4eb1f..00000000
--- a/alliance/share/man/man3/getphref.3
+++ /dev/null
@@ -1,77 +0,0 @@
-.\"   $Id: getphref.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)getphref.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-getphref
-.XE
-.XS0 \n%
-.ti 0.2i
-getphref
-.XE0 \}
-.TH GETPHREF 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL FUNCTIONS"
-.SH NAME
-getphref \- retrieve a physical reference
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-phref_list \(**getphref(ptfig, refname)
-phfig_list \(**ptfig;
-char \(**refname;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptfig\fP
-Pointer to the figure in which the reference should be seeked
-.TP
-\fIrefname\fP
-Name of the reference
-.SH DESCRIPTION
-\fBgetphref\fP looks in the list of references of the physical model pointed
-to by \fIptfig\fP for a reference identified by its \fIrefname\fP.
-.SH RETURN VALUE
-\fBgetphref\fP returns a pointer to the reference that matches the
-\fIrefname\fP.
-.SH ERROR
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** illegal getphref reference \fIrefname\fP doesn't exist
-in figure \fIptfig\->NAME\fP" 
-.ft R
-.RS
-No reference is called \fIrefname\fP in the figure. 
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-phref_list \(**exist(figname, refname)
-char \(**figname, \(**refname;
-{
-   return getphref(getphfig(figname), refname);   
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR phfig (3),
-.BR phref (3),
-.BR addphref (3),
-.BR delphref (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/getptype.3 b/alliance/share/man/man3/getptype.3
deleted file mode 100644
index ffdda315..00000000
--- a/alliance/share/man/man3/getptype.3
+++ /dev/null
@@ -1,73 +0,0 @@
-.\"   $Id: getptype.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)getptype.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-getptype
-.XE
-.XS4 \n%
-.ti 0.2i
-getptype
-.XE4 \}
-.TH GETPTYPE 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-getptype \- retrieve a \fBptype\fP from a \fBptype_list\fP
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-ptype_list \(**getptype(pthead,type)
-ptype_list \(**pthead;
-long type;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIpthead\fP
-Pointer to a \fBptype\fP list
-.TP
-\fItype\fP
-Flag indicating the pointer owner
-.SH DESCRIPTION
-\fBgetptype\fP looks for a \fBptype\fP element in the list pointed to by
-\fIpthead\fP.
-.SH RETURN VALUE
-\fBgetptype\fP returns a pointer to the \fBptype\fP that match the \fItype\fP.
-Be careful, it is not the \fIptype\->DATA\fP that is returned.
-If no \fBptype\fP has the given \fItype\fP, then \fBNULL\fP is returned.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-#include "mph315.h"
-void get_corner(ptfig, name, x2, y2)
-phfig_list \(**ptfig;
-char \(**name;
-int \(**x2, \(**y2;
-{
-phins_list \(**i = getphins(ptfig, name);
-ptype_list \(**p = getptype(i\->USER, (long)PLACEABOX);
-	\(**x2 = (num_list \(**)(p\->DATA)\->DATA;
-	\(**y2 = (num_list \(**)(p\->DATA)\->NEXT\->DATA;
-}	
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR ptype (3),
-.BR addptype (3),
-.BR freeptype (3),
-.BR delptype (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/getrdsfig.3 b/alliance/share/man/man3/getrdsfig.3
deleted file mode 100644
index f99de947..00000000
--- a/alliance/share/man/man3/getrdsfig.3
+++ /dev/null
@@ -1,88 +0,0 @@
-.\"   $Id: getrdsfig.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)getrdsfig.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-getrdsfig
-.XE
-.XS0 \n%
-.ti 0.2i
-getrdsfig
-.XE0 \}
-.TH GETRDSFIG 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-getrdsfig \- gets a pointer to a figure called by its name.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rtlnnn.h"
- rdsfig_list \(**getrdsfig( Name, Mode, Size )
-    char        \(**Name;
-    char         Mode;
-    unsigned int Size;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIName\fP
-Name of the Rds figure to get.
-.TP
-\fIMODE\fP :  
-Caracter indicating the status of the figure in memory.
-.PP
-This field can take three values :
-.RS
-.TP
-\fI\'A\'\fP
-All the cell is loaded in ram (The figure, its rectangles and its instances empty).
-.TP
-\fI\'P\'\fP
-Only information concerning the model interface is present, that means : connectors, the abutment box and through routes of the figure.
-.TP
-\fI\'V\'\fP
-Visualization mode : all is loaded in RAM : The figure, its rectangles, its instances and the rectangles of its instances.
-.RE
-.TP
-\fISize\fP
-Size of the additionnal user structure if it exists.
-.SH DESCRIPTION
-The \fIgetrdsfig\fP function gets a rds figure by its name. If the figure is already in memory then a pointer is returned. If the figure isn't loaded in memory then it's loaded in memory totaly or partialy according to the value of the field \'Mode\'. The parameter 'Size' is necessary to know the size of the structure added to the rdsrec_list structure. If the user structure doesn't exist then field \'Size\' has to be set to 0L.
-.SH RETURN VALUE
-The pointer to the figure is returned.
-.SH ERRORS
-UNKNOWN
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rtlnnn.h"
-        main()
-         {
-           rdsfig_list \(**RdsFigure;
-           rdsfig_list \(**GetFigure;
-           mbkenv();
-           rdsenv();
-           loadrdsparam();
-           loadrdsfig(RdsFigure, "core", 'A');
-           GetFigure = \fBgetrdsfig\fP ( "core" ,'A', 0 );
-         }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librtl,
-.BR loadrdsfig,
-.BR rdsenv
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/getrdsmodellist.3 b/alliance/share/man/man3/getrdsmodellist.3
deleted file mode 100644
index a42a59bb..00000000
--- a/alliance/share/man/man3/getrdsmodellist.3
+++ /dev/null
@@ -1,95 +0,0 @@
-.\"   $Id: getrdsmodellist.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)getrdsmodellist.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-getrdsmodellist
-.XE
-.XS0 \n%
-.ti 0.2i
-getrdsmodellist
-.XE0 \}
-.TH GETRDSMODELLIST 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-getrdsmodellist \- gets model list of the instances of a figure
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rutnnn.h"
- ptype_list \(**getrdsmodellist( Figure )
-   rdsfig_list \(**Figure;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIFigure\fP
-The figure which contains the models to extract. 
-.SH DESCRIPTION
-The \fIgetrdsmodellist\fP function gets list of instance's models of the figure \'Figure\'. The data structure returned "ptype_list" is defined ( in MBK library mutnnn.h ) as follows :
-.RS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-typedef struct ptype 
-  {
-     struct ptype \(**NEXT;  /\(** next pointer                \(**/
-     void         \(**DATA;  /\(** generic pointer             \(**/
-     long         TYPE;   /\(** type                        \(**/
-  } ptype_list;
-.ft R
-.fi
-.RE
-.PP
-The field \'DATA\' of ptype_list structure contains the pointer to the rdsfig_list structure.
-.SH RETURN VALUE
-The getrdsmodellist function returns a pointer which is head of pointer's list of the instances's models of the figure. If the list is empty, NULL pointer is returned.
-.SH ERRORS
-none
-.SH EXAMPLE :
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-    #include "mphnnn.h"
-    #include "mutnnn.h"
-    #include "rdsnnn.h"
-    #include "rutnnn.h"
-    #include "rtlnnn.h"
-    main()
-     {
-      phfig_list  \(**MbkFigure;
-      rdsfig_list \(**RdsFigure;
-      ptype_list  \(**FigureList;
-      ptype_list  \(**ScanFigureList;
-      mbkenv(); 
-      rdsenv();
-      loadrdsparam();
-      MbkFigure        = getphfig("core",'A');
-      RdsFigure = figmbkrds(MbkFigure,0,0); 
-      FigureList = \fBgetrdsmodellist\fP( RdsFigure );
-      for (
-            ScanFigureList  = FigureList ;
-            ScanFigureList != (ptype_list \(**) NULL ;
-            ScanFigureList  = ScanFigureList->NEXT
-          )
-        viewrdsfig ( (rdsfig_list \(**) ScanFigureList->DATA );
-      . . .
-    }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librut,
-.BR Mut library
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/getsigname.3 b/alliance/share/man/man3/getsigname.3
deleted file mode 100644
index dcf6e91a..00000000
--- a/alliance/share/man/man3/getsigname.3
+++ /dev/null
@@ -1,60 +0,0 @@
-.\"   $Id: getsigname.3,v 1.2 2002/01/22 19:51:18 xtof Exp $
-.\" @(#)getsigname.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-getsigname
-.XE \}
-.TH GETSIGNAME 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL FUNCTIONS"
-.SH NAME
-getsigname \- choose a signal name in alias list 
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-char \(**getsigname(ptsig)
-losig_list \(**ptsig;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIptsig\fP
-Pointer to \fBlosig_list\fP
-.SH DESCRIPTION
-The \fBgetsigname\fP function choose the higher hierachical level name of the
-alias list of a signal.
-The alias list is pointer to by the \fINAMECHAIN\fP pointer of the \fBlosig\fP
-structure, and contains zero or more names corresponding to the signal.
-Since the signal may result from a flatten, instance names may be concatenated
-to the actual signal name.
-.SH RETURN VALUE
-\fBgetsigname\fP returns the higher hierachy level name, if
-\fIptsig\->NAMECHAIN\fP is not \fBNULL\fP, else a name constructed with
-the signal \fBINDEX\fP is returned.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-void print_signame(p)
-losig_list \(**p;
-{
-	fprintf(stdout, "signal name : %s\\n", getsigname(p));
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR losig (3),
-.BR chain (3).
-
-
-.so man1/alc_bug_report.1
diff --git a/alliance/share/man/man3/givelosig.3 b/alliance/share/man/man3/givelosig.3
deleted file mode 100644
index 1536cb69..00000000
--- a/alliance/share/man/man3/givelosig.3
+++ /dev/null
@@ -1,70 +0,0 @@
-.\"   $Id: givelosig.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)givelosig.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-givelosig
-.XE
-.XS3 \n%
-.ti 0.2i
-givelosig
-.XE3 \}
-.TH GIVELOSIG 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL UTILITY FUNCTIONS"
-.SH NAME
-givelosig \- give a logical signal
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo412.h"
-losig_list \(**givelosig(ptfig, index)
-lofig_list \(**ptfig;
-long index;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptfig\fP
-Pointer to the figure in which the signal should be seeked or created
-.TP
-\fIindex\fP
-Index of the signal to find or create
-.SH DESCRIPTION
-\fBgivelosig\fP looks in the list of signals of the logical model pointed
-to by \fIptfig\fP for a signal identified by its \fIindex\fP. If this signal
-exists, then its pointer is returned, else, the signal is created, with
-direction, \fIDIR\fP, \fBUNKNOWN\fP, and \fITYPE\fP \fBINTERNAL\fP, and, of
-course \fIINDEX\fP \fIindex\fP, and the pointer is returned.
-.SH RETURN VALUE
-\fBgivelosig\fP returns a pointer to the signal.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo412.h"
-losig_list \(**give_sig_by_name(figname, index)
-char \(**figname;
-long index;
-{
-   /\(** never fails \(**/
-   return givelosig(getlofig(figname), index);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR lofig (3),
-.BR losig (3),
-.BR addlosig (3),
-.BR dellosig (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/grog.3 b/alliance/share/man/man3/grog.3
deleted file mode 100644
index 462690e8..00000000
--- a/alliance/share/man/man3/grog.3
+++ /dev/null
@@ -1,105 +0,0 @@
-.\"   $Id: grog.3,v 1.1 1999/05/31 17:30:20 alliance Exp $
-.\" @(#)grog.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.ie t \{\
-.fp 4 C \}
-.el \{\
-.fp 4 B \}
-.TH GROG 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL FUNCTIONS"
-.SH NAME
-grog \- call the \fIROM\fP generator
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "ggr000.h"
-char \(**grog(name, nb, nw, codefile, tr, hz, r, msb,
-           layout, logicalbox, vhdl, pattern, icon,
-           physicalbox, datasheet)
-char \(**name, \(**codefile;
-long nb, nw, tr, hz, r, msb, layout, logicalbox,
-     vhdl, pat, icon, physicalbox, datasheet;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIname\fP
-Name of the generated block.
-.TP 20
-\fInb\fP
-Number of bits of the \fIROM\fR.
-This number ranges from 1 to 64 inclusive.
-.TP 20
-\fInw\fP
-Number of words of the \fIROM\fR.
-The acceptables values are 64, 128, 256, 512 * n, where n belongs to {1,...,8}
-.TP 20
-\fIcodefile\fP
-Name of the file that contains the values to be poked in the \fIROM\fR.
-.TP 20
-\fItr\fP
-Ask for feed through every bit line if not set to zero.
-.TP 20
-\fIhz\fP
-Ask for three state buffer if not set to zero.
-.TP 20
-\fIr\fP
-Ask for output order from right to left if not zero.
-.TP 20
-\fImsb0\fP
-Indicate that \f4a[0]\fR is the most significant bit if not zero.
-.TP 20
-\fIlayout\fP
-If not zero, generate the layout.
-.TP 20
-\fIlogicalbox\fP
-If not zero, generate the interface of the netlist.
-.TP 20
-\fIvhdl\fP
-If not zero, generate the behavior.
-.TP 20
-\fIpattern\fP
-If not zero, generate the pattern for simulation.
-.TP 20
-\fIicon\fP
-If not zero, generate the icon.
-.TP 20
-\fIphysicalbox\fP
-If not zero, generate an outline of the layout.
-.TP 20
-\fIdatasheet\fP
-If not zero, generate the datasheet.
-.SH DESCRIPTION
-\fBgrog\fP is a library function that allows to directly call \f4grog\fR(1),
-the \fBAlliance\fR \fIROM\fR generator from a programm.
-Details on the arguments can be found in the \f4grog\fR(1) manual.
-.SH OUTPUT FILES
-.TP 20
-\fIname\fR.\f4xx\fR
-Layout, netlist and icon views.
-For these views, the suffixes depend on the
-\f4MBK_OUT_PH\fR(1), \f4MBK_OUT_LO\fR(1) and \f4ICON_OUT\fR
-environment variables.
-The \fIname\fP is either the one specified by the user, or an internally
-generated one prefixed by \f4r\fIwords\f4x\fIbits\fR.
-.TP
-\fIname\fR.\f4vbe\fR
-\fIvhdl\fR behavior.
-.TP
-\fIname\fR.\f4pat\fR
-Set of patterns for validation.
-.TP
-\fIname\fR.\f4dts\fR
-Datasheet.
-.SH SEE ALSO
-.BR mbk (1),
-.BR genlib (1),
-.BR grog (1),
-.BR rfg (3),
-.BR bsg (3),
-.BR rsa (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/guessextdir.3 b/alliance/share/man/man3/guessextdir.3
deleted file mode 100644
index 918aeb8d..00000000
--- a/alliance/share/man/man3/guessextdir.3
+++ /dev/null
@@ -1,86 +0,0 @@
-.\"   $Id: guessextdir.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)guessextdir.2 1.00 92/10/27 ; Labo masi cao-vlsi; Author : Vincent POUILLEY
-.\"modified by Frederic Petrot to meet english language requirements!
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-guessextdir
-.XE
-.XS2 \n%
-.ti 0.2i
-guessextdir
-.XE2 \}
-.TH GUESSEXTDIR 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL UTILITY FUNCTIONS"
-.SH NAME
-guessextdir \- guess external connectors directions from internal connectors directions
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo412.h"
-int guessextdir(ptfig)
-lofig_list \(**ptfig;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIptfig\fP
-Pointer to a lofig_list
-.SH DESCRIPTION
-The \fBguessextdir\fP function guesses external connectors directions from
-internal connectors' ones.
-The translation table below indicates the resulting direction
-for two internals connectors.
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-         IN      OUT      INOUT  UNKNOWN  TRISTATE TRANSCV
-IN       IN      INOUT    INOUT  IN       TRANSCV  TRANSCV
-OUT      INOUT   OUT+     INOUT+ OUT      OUT+     TRANSCV+
-INOUT    INOUT   INOUT+   INOUT+ INOUT    INOUT+   INOUT+
-UNKNOWN  IN      OUT      INOUT  UNKNOWN  TRISTATE TRANSCV
-TRISTATE TRANSCV OUT+     INOUT+ TRISTATE TRISTATE TRANSCV
-TRANSCV  TRANSCV TRANSCV+ INOUT+ TRANSCV  TRANSCV  TRANSCV
-.SH RETURN VALUE
-\fBguessextdir\fP returns \fB1\fP on success, \fB0\fP
-if there is an error in the translation.
-.SH ERROR
-The values followed by a \fB+\fP character in the translation table indicate
-an error.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut412.h"
-#include "mlo412.h"
-lofig_list \(** getgoodlofig(figname, mode)
-char \(**figname;
-char mode;
-{
-lofig_list \(**ptfig;
-	ptfig = getlofig(figname, mode);
-	restorealldir(ptfig);
-	guessextdir(ptfig);
-	return ptfig;
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR lofig (3),
-.BR locon (3),
-.BR getlofig (3),
-.BR restorealldir (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/identExpr.3 b/alliance/share/man/man3/identExpr.3
deleted file mode 100644
index e26e083f..00000000
--- a/alliance/share/man/man3/identExpr.3
+++ /dev/null
@@ -1,53 +0,0 @@
-.\"   $Id: identExpr.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)identExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH IDENTEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBidentExpr\fP \- gives an ident from an operator expression. 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-char *identExpr(expr)
-chain_list *expr;
-.fi
-.SH PARAMETER
-.TP 20
-\fIexpr\fP
-expression from wich the identifier will be extracted 
-.SH DESCRIPTION
-\fBidentExpr()\fP returns the \fIchar *\fP identifier associated to \fIexpr\fP. If you want to obtain a quasi-unique identifier, this function must be called after the \fBnormExpr()\fP function. 
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr1,*expr2;
-expr1 = createExpr(OR)
-addQExpr(expr1,createAtom("a"));
-addQExpr(expr1,createAtom("b"));
-addQExpr(expr1,createAtom("c"));
-printf("%s",identExpr(expr));
-/* it will display
-or3
-*/
-expr2 = createExpr(XOR);
-addQExpr(expr2,createAtom("a"));
-addQExpr(expr2,createAtom("b"));
-addQExpr(expr1,expr2);
-printf("%s",identExpr(expr));
-/* it will display
-ox24
-*/
-freeExpr(expr1);		/* don't free expr2 ! */
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR normExpr (3).
-.BR charToOper (3),
-.BR operToChar (3),
-.BR displayExpr (3),
-.BR displayInfExpr (3),
-.BR exprToChar (3),
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/implybddnode.3 b/alliance/share/man/man3/implybddnode.3
deleted file mode 100644
index 6d093cc4..00000000
--- a/alliance/share/man/man3/implybddnode.3
+++ /dev/null
@@ -1,78 +0,0 @@
-.\"   $Id: implybddnode.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)implybddnode.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH IMPLYBDDNODE 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-implybddnode \- computes a \fBbdd\fP that implies a conjonction of two \fBbdd\fP nodes.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddnode \(**implybddnode( BddSystem, BddNode1, BddNode2 )
-  bddsystem \(**BddSystem;
-  bddnode   \(**BddNode1;
-  bddnode   \(**BddNode2;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIBddNode1\fP
-The first \fBbdd\fP node.
-.TP
-\fIBddNode2\fP
-The second \fBbdd\fP node.
-.SH DESCRIPTION
-\fBimplybddnode\fP tests if the intersection of \fIBddNode1\fP and not \fIBddNode2\fP,
-exists, in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBimplybddnode\fP returns the \fBbdd\fP node zero if there is no 
-intersection, and a computed \fBbdd\fP node otherwise.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode1;
-   bddnode    \(**BddNode2;
-   bddnode    \(**BddImply;
-   chain_list \(**Expr;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   Expr = createablbinexpr( ABL_OR,
-                            createablatom( "i0" ),
-                            createablatom( "i1" ) );
-   BddNode1 = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   Expr = createablbinexpr( ABL_AND,
-                            createablatom( "i0" ),
-                            createablatom( "i1" ) );
-   BddNode1 = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   BddImply = implybddnode( (bddsystem \(**)0, BddNode1, BddNode2 );
-   Expr = convertbddcircuitabl( BddCircuit, BddNode );
-   /* displays (i0 and (not i1)) */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/incatalog.3 b/alliance/share/man/man3/incatalog.3
deleted file mode 100644
index b68a9ea1..00000000
--- a/alliance/share/man/man3/incatalog.3
+++ /dev/null
@@ -1,75 +0,0 @@
-.\"   $Id: incatalog.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)incatalog.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-incatalog
-.XE
-.XS4 \n%
-.ti 0.2i
-incatalog
-.XE4 \}
-.TH INCATALOG 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-incatalog \- test if cell belongs to the catalog file
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-int incatalog(figname)
-char \(**figname;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIfigname\fP
-Name of the cell to be checked
-.SH DESCRIPTION
-\fBincatalog\fP checks a cell represented by its \fIfigname\fP beeing
-present in the catalog file with the \fB'C'\fP attribut.
-.br
-This means that when flattening, the hierachy destruction stops when
-encountering a cell belonging to the catalog.
-This is meant for both logical and physical views, of course.
-.br
-The catalog is the sum of all the catalogs of the cells libraries specified
-in the \fBMBK_CATA_LIB\fP(1) and \fBMBK_WORK_LIB\fP(1).
-The catalogs of the \fBMBK_CATA_LIB\fP(1) are the files called \fBCATAL\fP,
-and the \fBMBK_WORK_LIB\fP(1) is by default \fBCATAL\fP but can be changed
-to \fBMBK_CATAL_NAME\fP(1).
-.SH RETURN VALUE
-\fBincatalog\fP returns \fB0\fP if the cell does not belong to the catalog
-with the \fB'C'\fP attribut,
-a value different from \fB0\fP if it does.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-char \(**tell_if_incatalog(name)
-char \(**name;
-{
-	return incatalog(name) ? "Jawohl, mein Herr" : "Nein, danke";
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR incatalogfeed (3),
-.BR incatalogdelete (3),
-.BR incataloggds (3),
-.BR MBK_CATAL_NAME (1),
-.BR MBK_CATA_LIB (1),
-.BR MBK_WORK_LIB (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/incatalogdelete.3 b/alliance/share/man/man3/incatalogdelete.3
deleted file mode 100644
index d51d37c9..00000000
--- a/alliance/share/man/man3/incatalogdelete.3
+++ /dev/null
@@ -1,71 +0,0 @@
-.\"   $Id: incatalogdelete.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)incatalogdelete.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-incatalogdelete
-.XE
-.XS4 \n%
-.ti 0.2i
-incatalogdelete
-.XE4 \}
-.TH INCATALOGDELETE 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-incatalogdelete \- test if cell belongs to the catalog file
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mutnnn.h"
-int incatalogdelete(figname)
-char \(**figname;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIfigname\fP
-Name of the cell to be checked
-.SH DESCRIPTION
-\fBincatalogdelete\fP checks a cell represented by its \fIfigname\fP beeing
-present in the catalog file with the \fB'D'\fP attribut.
-This means that the cell is to be deleted from the catalog.
-\fBincatalogdelete\fP returns \fB0\fP if the cell does not belong to the
-catalog with the \fB'D'\fP attribut, \fB1\fP if it does.
-.br
-The catalog is the sum of all the catalogs of the cells libraries specified
-in the \fBMBK_CATA_LIB\fP(1) and \fBMBK_WORK_LIB\fP(1).
-The catalogs of the \fBMBK_CATA_LIB\fP(1) are the files called \fBCATAL\fP,
-and the \fBMBK_WORK_LIB\fP(1) is by default \fBCATAL\fP but can be changed
-to \fBMBK_CATAL_NAME\fP(1).
-.SH RETURN VALUE
-\fBincatalogdelete\fP returns \fB0\fP if the cell does not belong to the
-catalog with the \fB'D'\fP attribut,
-a value different from \fB0\fP if it does.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mutnnn.h"
-char \(**tell_if_incatalogdelete(name)
-char \(**name;
-{
-	return incatalogdelete(name) ? "Not checked for catalog" : "Checked";
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR incatalog (3),
-.BR incatalogfeed (3).
-.BR incataloggds (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/incatalogfeed.3 b/alliance/share/man/man3/incatalogfeed.3
deleted file mode 100644
index da9abe75..00000000
--- a/alliance/share/man/man3/incatalogfeed.3
+++ /dev/null
@@ -1,73 +0,0 @@
-.\"   $Id: incatalogfeed.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)incatalogfeed.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-incatalogfeed
-.XE
-.XS4 \n%
-.ti 0.2i
-incatalogfeed
-.XE4 \}
-.TH INCATALOGFEED 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-incatalogfeed \- test if cell belongs to the catalog file
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-int incatalogfeed(figname)
-char \(**figname;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIfigname\fP
-Name of the cell to be checked
-.SH DESCRIPTION
-\fBincatalogfeed\fP checks a cell represented by its \fIfigname\fP beeing
-present in the catalog file with the \fI'F'\fP attribut.
-This means that the cell is a feed through, and does not have a logical
-equivalent representation while beeing physicaly used.
-.br
-This information is mostly needed by routers, since \fI"logical feed through"\fP
-has no design meaning.
-.br
-The catalog is the sum of all the catalogs of the cells libraries specified
-in the \fBMBK_CATA_LIB\fP(1) and \fBMBK_WORK_LIB\fP(1).
-The catalogs of the \fBMBK_CATA_LIB\fP(1) are the files called \fBCATAL\fP,
-and the \fBMBK_WORK_LIB\fP(1) is by default \fBCATAL\fP but can be changed
-to \fBMBK_CATAL_NAME\fP(1).
-.SH RETURN VALUE
-\fBincatalogfeed\fP returns \fB0\fP if the cell does not belong to the
-catalog with the \fB'F'\fP attribut, 
-a value different from \fB0\fP if it does.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-char \(**tell_if_incatalogfeed(name)
-char \(**name;
-{
-	return incatalogfeed(name) ? "Jawohl, mein Herr" : "Nein, danke";
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR incatalog (3),
-.BR incatalogdelete (3),
-.BR incataloggds (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/incataloggds.3 b/alliance/share/man/man3/incataloggds.3
deleted file mode 100644
index 7d840661..00000000
--- a/alliance/share/man/man3/incataloggds.3
+++ /dev/null
@@ -1,74 +0,0 @@
-.\"   $Id: incataloggds.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)incataloggds.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-incataloggds
-.XE
-.XS4 \n%
-.ti 0.2i
-incataloggds
-.XE4 \}
-.TH INCATALOGGDS 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-incataloggds \- test if cell belongs to the catalog file
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-int incataloggds(figname)
-char \(**figname;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIfigname\fP
-Name of the cell to be checked
-.SH DESCRIPTION
-\fBincataloggds\fP checks a cell represented by its \fIfigname\fP beeing
-present in the catalog file with the \fB'G'\fP attribut.
-This means that the cell is a phantom of a gds cell.
-.br
-This is useful when traducing a symbolic layout into physical one, because
-then the \fB'G'\fP attribued cells are not to be translated, but just replaced
-in the output.
-This is mostly used for pads.
-.br
-The catalog is the sum of all the catalogs of the cells libraries specified
-in the \fBMBK_CATA_LIB\fP(1) and \fBMBK_WORK_LIB\fP(1).
-The catalogs of the \fBMBK_CATA_LIB\fP(1) are the files called \fBCATAL\fP,
-and the \fBMBK_WORK_LIB\fP(1) is by default \fBCATAL\fP but can be changed
-to \fBMBK_CATAL_NAME\fP(1).
-.SH RETURN VALUE
-\fBincataloggds\fP returns \fB0\fP if the cell does not belong to the
-catalog with the \fB'G'\fP attribut,
-a value different from \fB0\fP if it does.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-char \(**tell_if_incataloggds(name)
-char \(**name;
-{
-	return incataloggds(name) ? "Jawohl, es ist ein pad" : "Nein, keine";
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR incatalog (3),
-.BR incatalogdelete (3),
-.BR incatalogfeed (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/incbddrefext.3 b/alliance/share/man/man3/incbddrefext.3
deleted file mode 100644
index 1da65b76..00000000
--- a/alliance/share/man/man3/incbddrefext.3
+++ /dev/null
@@ -1,60 +0,0 @@
-.\"   $Id: incbddrefext.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)incbddrefext.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH INCBDDREFEXT 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-incbddrefext \- increments the external reference of a \fBbdd\fP node.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddnode \(**incbddrefext( BddNode )
-  bddnode \(**BddNode;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddNode\fP
-The \fBbdd\fP node.
-.SH DESCRIPTION
-\fBincbddrefext\fP increments the number of external reference
-of the \fBbdd\fP node \fIBddNode\fP.
-.br
-.SH RETURN VALUE
-\fBincbddrefext\fP returns the \fIBddNode\fP pointer.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   chain_list \(**Expr;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   BddNode = addbddcircuitin( (bddcircuit \(**)0, "i0", 0, BDD_IN_MODE_FIRST );
-   BddNode = addbddnode( (bddsystem \(**)0, BddNode->INDEX, BddNode->LOW, BddNode->HIGH );
-   Expr = convertbddcircuitabl( (bddcircuit \(**)0, BddNode );
-   incbddrefext( BddNode );
-   /* displays Node VAR: 0  INDEX: 2  MARK: 0  REF_EXT: 2  REF_INT: 0 */
-   viewbddnode( (bddsystem \(**)0, BddNode );
-   /* displays (not i0) */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/incbddrefint.3 b/alliance/share/man/man3/incbddrefint.3
deleted file mode 100644
index 01831834..00000000
--- a/alliance/share/man/man3/incbddrefint.3
+++ /dev/null
@@ -1,60 +0,0 @@
-.\"   $Id: incbddrefint.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)incbddrefint.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH INCBDDREFINT 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-incbddrefint \- increments the internal reference of a \fBbdd\fP node.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddnode \(**incbddrefint( BddNode )
-  bddnode \(**BddNode;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddNode\fP
-The \fBbdd\fP node.
-.SH DESCRIPTION
-\fBincbddrefint\fP increments the number of internal reference
-of the \fBbdd\fP node \fIBddNode\fP.
-.br
-.SH RETURN VALUE
-\fBincbddrefint\fP returns the \fIBddNode\fP pointer.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   chain_list \(**Expr;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   BddNode = addbddcircuitin( (bddcircuit \(**)0, "i0", 0, BDD_IN_MODE_FIRST );
-   BddNode = addbddnode( (bddsystem \(**)0, BddNode->INDEX, BddNode->LOW, BddNode->HIGH );
-   Expr = convertbddcircuitabl( (bddcircuit \(**)0, BddNode );
-   incbddrefint( BddNode );
-   /* displays Node VAR: 0  INDEX: 2  MARK: 0  REF_EXT: 1  REF_INT: 1 */
-   viewbddnode( (bddsystem \(**)0, BddNode );
-   /* displays (not i0) */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/initializeBdd.3 b/alliance/share/man/man3/initializeBdd.3
deleted file mode 100644
index 7be19833..00000000
--- a/alliance/share/man/man3/initializeBdd.3
+++ /dev/null
@@ -1,48 +0,0 @@
-.\"   $Id: initializeBdd.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)initializeBdd.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH INITIALIZEBDD 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBinitializeBdd\fP \- initializes the BDDs system 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-void initializeBdd(size)
-int size;
-.fi
-.SH PARAMETER
-.TP 20
-\fIsize\fP
-First size of BDD system
-.SH DESCRIPTION
-\fBinitializeBdd()\fP initializes the BDDs system. \fIsize\fP can be equal to SMALL_BDD, MEDIUM_BDD or LARGE_BDD according to the application size. This function creates the \fIzero\fP and \fIone\fP node that correspond to the 0 and 1 boolean constants.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-
-initializeBdd(MEDIUM_BDD);
-
-dislayBdd(one);
-/* it will display
-ONE
-*/
-
-/* application using BDD ... */
-
-destroyBdd(1);
-.fi
-.SH ERROR
-"initializeBdd : error - size out of bound"
-.br
-\fIsize\fP must be included into \fISMALL_BDD\fP and \fILARGE_BDD\fP.
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR destroyBdd (3),
-.BR resetBdd (3),
-.BR markAllBdd (3),
-.BR numberNodeAllBdd (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/initializeCct.3 b/alliance/share/man/man3/initializeCct.3
deleted file mode 100644
index dc2c47d9..00000000
--- a/alliance/share/man/man3/initializeCct.3
+++ /dev/null
@@ -1,68 +0,0 @@
-.\"   $Id: initializeCct.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)initializeCct.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH INITIALIZECCT 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBinitializeCct\fP \- creates a circuit 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-pCircuit initializeCct(name,numberInput,numberOutput)
-char *name;
-int numberInput;
-int numberOutput;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIname\fP
-name to add
-.TP 20
-\fInumberInput\fP
-number of inputs
-.TP 20
-\fInumberOutput\fP
-number of outputs
-.SH DESCRIPTION
-\fBinitializeCct()\fP creates a circuit. This function returns a circuit pointer that is allocated. 
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-pCircuit pC;
-chain_list *expr;
-
-initializeBdd(SMALL_BDD);
-pC = initializeCct("circuit 1",10,10);
-
-addInputCct(pC,"a");
-addInputCct(pC,"b");
-
-	/* let's suppose that expr = (OR a b) */
-
-addOuputCct(pC,"s1",one);
-addOuputCct(pC,"s2",ablToBddCct(pC,expr));
-
-displayBdd(pC,1)
-
-/* it will display 
-************* DISPLAY circuit 1 **********
-INPUT = a	INDEX = 2
-INPUT = b	INDEX = 3
---------- NUMBER OF INPUTS = 2
-OUTPUT = s1	s1 = 1
-OUTPUT = s2	s2 = (OR a b)
---------- NUMBER OF OUTPUTS = 2
-******************************************
-*/
-
-destroyCct(pC);
-destroyBdd(1);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR resetCct (3),
-.BR destroyCct (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/insconmbkrds.3 b/alliance/share/man/man3/insconmbkrds.3
deleted file mode 100644
index 20541feb..00000000
--- a/alliance/share/man/man3/insconmbkrds.3
+++ /dev/null
@@ -1,111 +0,0 @@
-.\"   $Id: insconmbkrds.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)insconmbkrds.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-insconmbkrds
-.XE
-.XS0 \n%
-.ti 0.2i
-insconmbkrds
-.XE0 \}
-.TH INSCONMBKRDS 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
- insconmbkrds \- adds in RDS instance all the connectors of MBK instance
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rfmnnn.h"
-rdsrec_list \(**insconmbkrds( InstanceMbk, ModelMbk, InstanceRds )
-   phins_list  \(**InstanceMbk;
-   phfig_list  \(**ModelMbk;
-   rdsins_list \(**InstanceRds;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIInstanceMbk\fP
-The MBK instance which contains the connectors to convert.
-.TP
-\fIModelMbk\fP
-Pointer to the model of the MBK instance.
-.TP
-\fIInstanceRds\fP
-The instance which has to receive converted connectors from MBK to RDS format.
-.SH DESCRIPTION
-This function adds in the RDS instance all connectors from the MBK instance converted to RDS format. All newly created connectors are chained each other (circulary list) using the USER field of the rdsrec_list structure (see librds). 
-.SH RETURN VALUE
-Pointer to the head of list of the added rectangles to the RDS instance.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Rds202: rdsalloc error, can't continue !"
-.ft R
-.RS
-it's impossible to allocate the memory size desired
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mphnnn.h"
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rfmnnn.h"
-        #include "rtlnnn.h"
-        typedef struct UserStruct
-         {
-           char \(**STRING;
-           void \(**USER1;
-         } UserStruct;
-        main()
-          {
-            phfig_list  \(**MbkFigure;
-            phins_list  \(**MbkInstance;
-            phfig_list  \(**MbkModelInstance;
-            rdsfig_list \(**RdsFigure;
-            rdsins_list \(**RdsInstance;
-            rdsrec_list \(**RdsConnectorList;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            /\(** creates MbkFigure Named "core" \(**/
-            MbkFigure        = addphfig("core"); 
-            /\(** creates RdsFigure named "core_2" \(**/
-            RdsFigure        = addrdsfig("core_2",sizeof(UserStruct));
-            /\(** adds Mbk instance "n1_y" to MbkFigure named "core" \(**/
-            MbkInstance      = addphins(MbkFigure,"n1_y","inv_1",NOSYM,4,9);
-            /\(** gets Model of instance n1_y \(**/ 
-            MbkModelInstance = getphfig("n1_y",'A');
-            /\(** creates Rds instance named "block_1" added to RdsFigure \(**/
-            RdsInstance =
-                addrdsins(RdsFigure,"block","block_1",RDS_NOSYM,8,6);
-            /\(** 
-                  adds connectors of "inv_1" instance Mbk in Rds instance named
-                  "block_1"
-            \(**/ 
-            RdsConnectorList   = \fBinsconmbkrds\fP ( MbkInstance,
-                                                      MbkModelInstance,
-                                                      RdsInstance );
-            viewrfmrec ( RdsConnectorList );
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librfm
-.BR librds,
-.BR viewrfmrec,
-.BR loadrdsparam
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/insmbkrds.3 b/alliance/share/man/man3/insmbkrds.3
deleted file mode 100644
index eb1b904d..00000000
--- a/alliance/share/man/man3/insmbkrds.3
+++ /dev/null
@@ -1,117 +0,0 @@
-.\"   $Id: insmbkrds.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)insmbkrds.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-insmbkrds
-.XE
-.XS0 \n%
-.ti 0.2i
-insmbkrds
-.XE0 \}
-.TH INSMBKRDS 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-insmbkrds \- converts MBK figure to RDS figure
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rfmnnn.h"
-rdsins_list \(**insmbkrds( FigureRds, InstanceMbk, Mode, Lynx )
-   rdsfig_list \(**FigureRds;
-   phins_list  \(**InstanceMbk;
-   char         Mode;
-   char         Lynx;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIFigureRds\fP
-The Rds figure which has to receive the RDS instance issue to the MBK instance conversion.
-.TP
-\fIInstanceMbk\fP
-MBK instance which has to be converted and added to the RDS figure.
-.TP
-\fIMode\fP
-This field can take three values :
-.RS
-.PP
-\'A\' : All the cell is loaded in ram.
-.PP
-\'P\' : Only information concerning the model interface is present, that means connector
-s and the abutment box.
-.PP
-\'C\' : Finishes to fill an already loaded figure in \'P\' mode, in order to have it all in memory. After this, the conversion is applied.
-.PP
-\fINote\fP : The loading mode here is the \fBMBK\fP mode.
-.RE
-.TP
-\fILynx\fP
-Flag used for the segment conversion. If the parameter Lynx is set to 0 then thi
-s is the normal conversion mode. If the parameter Lynx is set to 1 then the rds
-structure generated permits to extract equipotentials rectangles.
-.SH DESCRIPTION
-The \fIinsmbkrds\fP function creates in the RDS figure the RDS instance issue to the convertion of the MBK instance to RDS format. If the parameter \'Mode\' is set to \'A\' then all the instance is loaded, else if parameter \'Mode\' is set to \'P\' then connectors and abutment box and through routes are loaded (for more information, see getphfig and loadphfig MBK functions).
-.SH RETURN VALUE
-A pointer to the newly created instance is returned.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Rds202: rdsalloc error, can't continue !"
-.ft R
-.RS
-it's impossible to allocate the memory size desired
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mphnnn.h"
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rfmnnn.h"
-        #include "rtlnnn.h"
-        typedef struct UserStruct
-         {
-           char \(**STRING;
-           void \(**USER1;
-         } UserStruct;
-        main()
-          {
-            phfig_list  \(**MbkFigure;
-            phins_list  \(**MbkInstance;
-            rdsfig_list \(**RdsFigure;
-            rdsins_list \(**RdsInstance;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            /\(** create MbkFigure Named "core" \(**/
-            MbkFigure    = addphfig("core"); 
-            /\(** add Mbk instance "n1_y" to MbkFigure named "core" \(**/
-            MbkInstance  = addphins(MbkFigure,"n1_y","inv_1",NOSYM,4,9);
-            /\(** create RdsFigure named "core_2" \(**/
-            RdsFigure    = addrdsfig("core_2",sizeof(UserStruct));
-            /\(** create RdsInstance with MbkInstance \(**/
-            RdsInstance  = \fBinsmbkrds\fP ( RdsFigure, MbkInstance, 'A', 0 );
-            viewrdsins ( RdsInstance );
-            . . .
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librfm,
-.BR librds,
-.BR viewrfmins,
-.BR loadrdsparam
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/insrefmbkrds.3 b/alliance/share/man/man3/insrefmbkrds.3
deleted file mode 100644
index 029b5b43..00000000
--- a/alliance/share/man/man3/insrefmbkrds.3
+++ /dev/null
@@ -1,111 +0,0 @@
-.\"   $Id: insrefmbkrds.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)insrefmbkrds.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-insrefmbkrds
-.XE
-.XS0 \n%
-.ti 0.2i
-insrefmbkrds
-.XE0 \}
-.TH INSREFMBKRDS 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-insrefmbkrds \- adds in RDS instance all the references of MBK instance.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rfmnnn.h"
-rdsrec_list \(**insrefmbkrds( InstanceMbk, ModelMbk, InstanceRds )
-   phins_list  \(**InstanceMbk;
-   phfig_list  \(**ModelMbk;
-   rdsins_list \(**InstanceRds;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIInstanceMbk\fP
-MBK instance which contains references to treat.
-.TP
-\fIModelMbk\fP
-Pointer to the model of the MBK instance.
-.TP
-\fIInstanceRds\fP
-RDS Instance which has to receive converted references from MBK to RDS format.
-.SH DESCRIPTION
-The \fIinsrefmbkrds\fP function adds in the RDS instance all references of the MBK instance converted to RDS format. All newly created references are chained each other (circulary list) using the USER field of the rdsrec_list structure.
-.SH RETURN VALUE
-Pointer to the head of list of the added rectangles to the RDS instance.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Rds202: rdsalloc error, can't continue !"
-.ft R
-.RS
-it's impossible to allocate the memory size desired
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mphnnn.h"
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rfmnnn.h"
-        #include "rtlnnn.h"
-        typedef struct UserStruct
-         {
-           char \(**STRING;
-           void \(**USER1;
-         } UserStruct;
-        main()
-          {
-            phfig_list  \(**MbkFigure;
-            phins_list  \(**MbkInstance;
-            phfig_list  \(**MbkModelInstance;
-            rdsfig_list \(**RdsFigure;
-            rdsins_list \(**RdsInstance;
-            rdsrec_list \(**RdsReferenceList;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            /\(** creates MbkFigure Named "core" \(**/
-            MbkFigure        = addphfig("core"); 
-            /\(** creates RdsFigure named "core_2" \(**/
-            RdsFigure        = addrdsfig("core_2",sizeof(UserStruct));
-            /\(** adds Mbk instance "n1_y" to MbkFigure named "core" \(**/
-            MbkInstance      = addphins(MbkFigure,"n1_y","inv_1",NOSYM,4,9);
-            /\(** Gets Model of instance n1_y \(**/ 
-            MbkModelInstance = getphfig("n1_y",'A');
-            /\(** creates Rds instance named "block_1" added to RdsFigure \(**/
-            RdsInstance =
-                addrdsins(RdsFigure,"block","block_1",RDS_NOSYM,8,6);
-            /\(**
-                adds reference of "inv_1" instance Mbk in Rds instance
-                named "block_1"
-            \(**/ 
-            RdsReferenceList = \fBinsrefmbkrds\fP ( MbkInstance,
-                                              MbkModelInstance,
-                                              RdsInstance );
-            viewrfmrec ( RdsReferenceList );
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librfm,
-.BR librds,
-.BR viewrfmrec,
-.BR loadrdsparam
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/inssegmbkrds.3 b/alliance/share/man/man3/inssegmbkrds.3
deleted file mode 100644
index 90ca3549..00000000
--- a/alliance/share/man/man3/inssegmbkrds.3
+++ /dev/null
@@ -1,122 +0,0 @@
-.\"   $Id: inssegmbkrds.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)inssegmbkrds.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-inssegmbkrds
-.XE
-.XS0 \n%
-.ti 0.2i
-inssegmbkrds
-.XE0 \}
-.TH INSSEGMBKRDS 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-inssegmbkrds \- adds in RDS instance all the segments of MBK instance
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rdsnnn.h"
- rdsrec_list \(**inssegmbkrds( InstanceMbk, ModelMbk, InstanceRds, Lynx )
-    phins_list  \(**InstanceMbk;
-    phfig_list  \(**ModelMbk;
-    rdsins_list \(**InstanceRds;
-    char         Lynx;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIInstanceMbk\fP
-The MBK instance which contains the segments to convert.
-.TP
-\fIModelMbk\fP
-Pointer to the model of the MBK instance.
-.TP
-\fIInstanceRds\fP
-The instance which has to receive converted segments from MBK to RDS format.
-.TP
-\fILynx\fP
-Flag used for the segment conversion. If the parameter Lynx is set to 0 then thi
-s is the normal conversion mode. If the parameter Lynx is set to 1 then the rds structure generated permits to extract equipotentials rectangles.
-.SH DESCRIPTION
-The \fIinssegmbkrds\fP function adds in the RDS instance all segments of the MBK instance converted to RDS format. All newly created segments are chained each other (circulary list) using the USER field of the rdsrec_list structure.
-.SH RETURN VALUE
-Pointer to the head of list of the added rectangles to the RDS instance.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Rds202: rdsalloc error, can't continue !"
-.ft R
-.RS
-it's impossible to allocate the memory size desired
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mphnnn.h"
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rfmnnn.h"
-        #include "rtlnnn.h"
-        typedef struct UserStruct
-         {
-           char \(**STRING;
-           void \(**USER1;
-         } UserStruct;
-        main()
-          {
-            phfig_list  \(**MbkFigure;
-            phins_list  \(**MbkInstance;
-            phfig_list  \(**MbkModelInstance;
-            rdsfig_list \(**RdsFigure;
-            rdsins_list \(**RdsInstance;
-            rdsrec_list \(**RdsSegmentList;
-            rdsrec_list \(**ScanSegment;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            /\(** creates MbkFigure Named "core" \(**/
-            MbkFigure        = addphfig("core"); 
-            /\(** creates RdsFigure named "core_2" \(**/
-            RdsFigure        = addrdsfig("core_2",sizeof(UserStruct));
-            /\(** adds Mbk instance "n1_y" to MbkFigure named "core" \(**/
-            MbkInstance      = addphins(MbkFigure,"n1_y","inv_1",NOSYM,4,9);
-            /\(** Gets Model of instance n1_y \(**/ 
-            MbkModelInstance = getphfig("n1_y",'A');
-            /\(** creates Rds instance named "block_1" added to RdsFigure \(**/
-            RdsInstance =
-               addrdsins(RdsFigure,"block","block_1",RDS_NOSYM,8,6);
-            /\(**
-                  adds segments of "inv_1" instance Mbk in Rds instance
-                  named "block_1"
-            \(**/ 
-            RdsSegmentList   = \fBinssegmbkrds\fP ( MbkInstance,
-                                              MbkModelInstance,
-                                              RdsInstance,0 );
-            viewrdsrec ( RdsSegmentList );
-            for ( ScanSegment  = RdsSegmentList->USER ;
-                  ScanSegment != RdsSegmentList ;
-                  ScanSegment  = ScanSegment->USER ) 
-             { 
-               viewrdsrec ( (rdsrec_list \(**) ScanSegment );
-             }
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librfm,
-.BR librds,
-.BR loadrdsparam
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/instanceface.3 b/alliance/share/man/man3/instanceface.3
deleted file mode 100644
index a2fa7867..00000000
--- a/alliance/share/man/man3/instanceface.3
+++ /dev/null
@@ -1,80 +0,0 @@
-.\"   $Id: instanceface.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)instanceface.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-instanceface
-.XE
-.XS1 \n%
-.ti 0.2i
-instanceface
-.XE1 \}
-.TH INSTANCEFACE 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL UTILITY FUNCTIONS"
-.SH NAME
-instanceface \- returns the face of a connector in a placed instance
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph403.h"
-void \(**instanceface(modelface, symmetry)
-char modelface, symmetry;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fImodelface\fP
-Face of a connector in its figure.
-.TP 20
-\fIsymmetry\fP
-Geometrical operation applied to the instanciation of the figure.
-.SH DESCRIPTION
-\fBinstanceface\fP determines the orientation of a connector in an instance of
-its model.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph403.h"
-char channelFace(channelDir, i, c)
-char channelDir;
-phins_list *i;
-phcon_list *c;
-{
-	if (channelDir == VER)
-		switch (instanceface(c->ORIENT, i->TRANSF)) {
-			case EAST :
-				return WEST;
-			case WEST :
-				return EAST;
-			default :
-				return instanceface(c->ORIENT, i->TRANSF);
-		}
-	else
-		switch (instanceface(c->ORIENT, i->TRANSF)) {
-			case NORTH :
-				return SOUTH;
-			case SOUTH :
-				return NORTH;
-			default :
-				return instanceface(c->ORIENT, i->TRANSF);
-		}
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR phcon (3),
-.BR phfig (3),
-.BR phins (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/instr.3 b/alliance/share/man/man3/instr.3
deleted file mode 100644
index 548cc73d..00000000
--- a/alliance/share/man/man3/instr.3
+++ /dev/null
@@ -1,77 +0,0 @@
-.\"   $Id: instr.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)instr.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-instr
-.XE
-.XS4 \n%
-.ti 0.2i
-instr
-.XE4 \}
-.TH INSTR 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-instr \- find an occurence of a string in a string, starting at a
-specified character.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-char \(**instr(s, find, from)
-char \(**s, \(**find, from;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIs\fP
-Pointer to the string to be searched for the pattern
-.TP
-\fIfind\fP
-Pointer to the string to be found, the pattern
-.TP
-\fIfrom\fP
-Character to be searched backwards before searching for the pattern
-.SH DESCRIPTION
-\fBinstr\fP searches the first occurence of the string \fIfind\fP in the string
-\fIs\fP, starting its search at the last occurence of the \fIfrom\fP character
-in the string \fIs\fP.
-.LP
-If either \fIs\fP or \fIfind\fP is \fBNULL\fP, the function returns \fBNULL\fP.
-If \fIfrom\fP is \fB(char)0\fP, the pattern is searched from the begining of
-\fIs\fP.
-.br
-This quite exotic behaviour is useful to search the occurence of a name in a
-string resulting from a flatten, when only a terminal object name is to be
-taken into account.
-.SH RETURN VALUES
-\fBinstr\fP return \fBNULL\fP either if the pattern \fIfind\fP is not present 
-in the searched string \fIs\fP, or if one at least of these two string are
-\fBNULL\fP.
-If the pattern is found, a value different from \fBNULL\fP is returned.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-/* check for the pattern 'ck' anywhere in the string */
-#define contains_ck(name)	instr(name, "ck", '\0')
-/* check for the pattern 'ck' in the signal name, not instance ones */
-#define isclock(ptsig)		 instr(getsigname(ptsig), "ck", SEPAR)
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR isvdd (3),
-.BR isvss (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/insviambkrds.3 b/alliance/share/man/man3/insviambkrds.3
deleted file mode 100644
index 559c2104..00000000
--- a/alliance/share/man/man3/insviambkrds.3
+++ /dev/null
@@ -1,117 +0,0 @@
-.\"   $Id: insviambkrds.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)insviambkrds.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-insviambkrds
-.XE
-.XS0 \n%
-.ti 0.2i
-insviambkrds
-.XE0 \}
-.TH INSVIAMBKRDS 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-insviambkrds \- adds to RDS instance all the contacts from MBK instance 
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rfmnnn.h"
-  rdsrec_list \(**insviambkrds( InstanceMbk, ModelMbk, InstanceRds )
-     phins_list  \(**InstanceMbk;
-     phfig_list  \(**ModelMbk;
-     rdsins_list \(**InstanceRds;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIInstanceMbk\fP
-The MBK instance which contains the contacts to convert.
-.TP
-\fIModelMbk\fP
-Pointer to the model of the MBK instance.
-.TP
-\fIInstanceRds\fP
-The instance which has to receive converted segments from MBK to RDS format.
-.SH DESCRIPTION
-This function adds in the RDS instance all the contacts of the MBK instance converted to RDS format. All newly created segments are chained each other (circulary list) using the USER field of the rdsrec_list structure.
-.SH RETURN VALUE
-Pointer to the head of list of the added rectangles to the RDS instance.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Rds202: rdsalloc error, can't continue !"
-.ft R
-.RS
-it's impossible to allocate the memory size desired
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mphnnn.h"
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rfmnnn.h"
-        #include "rtlnnn.h"
-        typedef struct UserStruct
-         {
-           char \(**STRING;
-           void \(**USER1;
-         } UserStruct;
-        main()
-          {
-            phfig_list  \(**MbkFigure;
-            phins_list  \(**MbkInstance;
-            phfig_list  \(**MbkModelInstance;
-            rdsfig_list \(**RdsFigure;
-            rdsins_list \(**RdsInstance;
-            rdsrec_list \(**RdsViaList;
-            rdsrec_list \(**ScanVia;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            /\(** creates MbkFigure Named "core" \(**/
-            MbkFigure        = addphfig("core"); 
-            /\(** creates RdsFigure named "core_2" \(**/
-            RdsFigure        = addrdsfig("core_2",sizeof(UserStruct));
-            /\(** adds Mbk instance "n1_y" to MbkFigure named "core" \(**/
-            MbkInstance      = addphins(MbkFigure,"n1_y","inv_1",NOSYM,4,9);
-            /\(** Gets Model of instance n1_y \(**/ 
-            MbkModelInstance = getphfig("n1_y",'A');
-            /\(** creates Rds instance named "block_1" added to RdsFigure \(**/
-            RdsInstance =
-                addrdsins(RdsFigure,"block","block_1",RDS_NOSYM,8,6);
-            /\(**
-               adds contacts of "inv_1" instance Mbk in Rds instance
-               named "block_1"
-            \(**/ 
-            RdsViaList = \fBinsviambkrds\fP ( MbkInstance,
-                                        MbkModelInstance,
-                                        RdsInstance);
-            viewrdsrec ( RdsViaList );
-            for ( ScanVia  = RdsViaList->USER ;
-                  ScanVia != RdsViaList ;
-                  ScanVia  = ScanVia->USER )
-             {
-               viewrdsrec ( (rdsrec_list \(**) ScanVia );
-             }
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librfm,
-.BR librds,
-.BR loadrdsparam
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/intersectbddnode.3 b/alliance/share/man/man3/intersectbddnode.3
deleted file mode 100644
index 9f277883..00000000
--- a/alliance/share/man/man3/intersectbddnode.3
+++ /dev/null
@@ -1,78 +0,0 @@
-.\"   $Id: intersectbddnode.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)intersectbddnode.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH INTERSECTBDDNODE 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-intersectbddnode \- tests for an intersection between two \fBbdd\fP nodes.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddnode \(**intersectbddnode( BddSystem, BddNode1, BddNode2 )
-  bddsystem \(**BddSystem;
-  bddnode   \(**BddNode1;
-  bddnode   \(**BddNode2;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIBddNode1\fP
-The first \fBbdd\fP node.
-.TP
-\fIBddNode2\fP
-The second \fBbdd\fP node.
-.SH DESCRIPTION
-\fBintersectbddnode\fP tests if the intersection of \fIBddNode1\fP and \fIBddNode2\fP
-exists, in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBintersectbddnode\fP returns the \fBbdd\fP node zero if there is no 
-intersection, and a computed \fBbdd\fP node otherwise.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode1;
-   bddnode    \(**BddNode2;
-   bddnode    \(**BddImply;
-   chain_list \(**Expr;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   Expr = createablbinexpr( ABL_AND,
-                            createablatom( "i0" ),
-                            createablatom( "i1" ) );
-   BddNode1 = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   Expr = createablbinexpr( ABL_OR,
-                            createablatom( "i0" ),
-                            createablatom( "i1" ) );
-   BddNode1 = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   BddImply = intersectbddnode( (bddsystem \(**)0, BddNode1, BddNode2 );
-   Expr = convertbddcircuitabl( BddCircuit, BddNode );
-   /* displays (i0 and i1)) */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/isablbinaryoper.3 b/alliance/share/man/man3/isablbinaryoper.3
deleted file mode 100644
index eef9e094..00000000
--- a/alliance/share/man/man3/isablbinaryoper.3
+++ /dev/null
@@ -1,46 +0,0 @@
-.\"   $Id: isablbinaryoper.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)isablbinaryoper.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH ISABLBINARYOPER 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-isablbinaryoper \- tests if an operator is binary.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-int isablbinaryoper( Oper )
-  long Oper;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIOper\fP
-Operator number.
-.SH DESCRIPTION
-\fBisablbinaryoper\fP tests if \fIOper\fP is binary.
-.br
-.SH RETURN VALUE
-\fBisablbinaryoper\fP returns 1 if \fIOper\fP is binary, -1
-if \fIOper\fP is not a valid number, and 0 otherwise.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-  /* displays    1 0 */
-  printf( "%d  ", isablbinaryoper( ABL_OR  ) );
-  printf( "%d\n", isablbinaryoper( ABL_NOT ) );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/isablequalexpr.3 b/alliance/share/man/man3/isablequalexpr.3
deleted file mode 100644
index 77098a8e..00000000
--- a/alliance/share/man/man3/isablequalexpr.3
+++ /dev/null
@@ -1,57 +0,0 @@
-.\"   $Id: isablequalexpr.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)isablequalexpr.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH ISABLEQUALEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-isablequalexpr \- tests if two expressions are strictly identicals.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-int isablequalexpr( Expr1, Expr2 )
-  chain_list \(**Expr1;
-  chain_list \(**Expr2;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIExpr1\fP
-First expression.
-.TP
-\fIExpr2\fP
-Second expression.
-.SH DESCRIPTION
-\fBisablequalexpr\fP compares \fIExpr1\fP and \fIExpr2\fP.
-.br
-.SH RETURN VALUE
-if \fIExpr1\fP and \fIExpr2\fP are strictly identicals
-\fBisablequalexpr\fP returns 1 and 0 otherwise.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-   chain_list \(**Expr1;
-   chain_list \(**Expr2;
-   Expr1 = createablbinexpr( ABL_AND,
-                             createablatom( "a" ),
-                             createablatom( "b" ) );
-   Expr2 = createablbinexpr( ABL_AND,
-                             createablatom( "a" ),
-                             createablatom( "b" ) );
-   /* displays 1 */
-   printf( "%d", isablequalexpr( Expr1, Expr2 ) );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/isablnameinexpr.3 b/alliance/share/man/man3/isablnameinexpr.3
deleted file mode 100644
index 9ddbf3ae..00000000
--- a/alliance/share/man/man3/isablnameinexpr.3
+++ /dev/null
@@ -1,53 +0,0 @@
-.\"   $Id: isablnameinexpr.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)isablnameinexpr.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH ISABLNAMEINEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH OPER
-isablnameinexpr \- tests if a name appears in an expression.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-int isablnameinexpr( Expr, Name )
-  chain_list \(**Expr;
-  char       \(**Name;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIExpr\fP
-Expression where to search.
-.TP
-\fIName\fP
-Name to search.
-.SH DESCRIPTION
-\fBisablnameinexpr\fP tests if \fIName\fP appears in \fIExpr\fP.
-.br
-.SH RETURN VALUE
-\fBisablnameinexpr\fP returns 1 if \fIName\fP appears in \fIExpr\fP
-and 0 otherwise.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-  chain_list \(**Expr;
-   Expr = createablbinexpr( ABL_AND, 
-                            createablatom( "a" ),
-                            createablatom( "b" ) );
-   /* displays   1 */
-   printf( "%d", isablnameinexpr( Expr, "a" ) );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/isabloperinexpr.3 b/alliance/share/man/man3/isabloperinexpr.3
deleted file mode 100644
index c5157bdf..00000000
--- a/alliance/share/man/man3/isabloperinexpr.3
+++ /dev/null
@@ -1,53 +0,0 @@
-.\"   $Id: isabloperinexpr.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)isabloperinexpr.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH ISABLOPERINEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-isabloperinexpr \- tests if an operator appears in an expression.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-int isabloperinexpr( Expr, Oper )
-  chain_list \(**Expr;
-  long        Oper;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIExpr\fP
-Expression where to search.
-.TP
-\fIOper\fP
-Operator to search.
-.SH DESCRIPTION
-\fBisabloperinexpr\fP tests if \fIOper\fP appears in \fIExpr\fP.
-.br
-.SH RETURN VALUE
-\fBisabloperinexpr\fP returns 1 if \fIOper\fP appears in \fIExpr\fP
-and 0 otherwise.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-  chain_list \(**Expr;
-   Expr = createablbinexpr( ABL_AND, 
-                            createablatom( "a" ),
-                            createablatom( "b" ) );
-   /* displays   1 */
-   printf( "%d", isabloperinexpr( Expr, ABL_AND ) );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/isablsimilarexpr.3 b/alliance/share/man/man3/isablsimilarexpr.3
deleted file mode 100644
index af14508e..00000000
--- a/alliance/share/man/man3/isablsimilarexpr.3
+++ /dev/null
@@ -1,57 +0,0 @@
-.\"   $Id: isablsimilarexpr.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)isablsimilarexpr.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH ISABLSIMILAREXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-isablsimilarexpr \- tests if two expressions have the same morphology.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-int isablsimilarexpr( Expr1, Expr2 )
-  chain_list \(**Expr1;
-  chain_list \(**Expr2;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIExpr1\fP
-First expression.
-.TP
-\fIExpr2\fP
-Second expression.
-.SH DESCRIPTION
-\fBisablequalexpr\fP compares \fIExpr1\fP and \fIExpr2\fP.
-.br
-.SH RETURN VALUE
-if \fIExpr1\fP and \fIExpr2\fP have got the same morphology
-\fBisablequalexpr\fP returns 1 and 0 otherwise.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-   chain_list \(**Expr1;
-   chain_list \(**Expr2;
-   Expr1 = createablbinexpr( ABL_AND,
-                             createablatom( "a" ),
-                             createablatom( "b" ) );
-   Expr2 = createablbinexpr( ABL_AND,
-                             createablatom( "c" ),
-                             createablatom( "d" ) );
-   /* displays 1 */
-   printf( "%d", isablsimilarexpr( Expr1, Expr2 ) );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/isablunaryoper.3 b/alliance/share/man/man3/isablunaryoper.3
deleted file mode 100644
index 204df488..00000000
--- a/alliance/share/man/man3/isablunaryoper.3
+++ /dev/null
@@ -1,46 +0,0 @@
-.\"   $Id: isablunaryoper.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)isablunaryoper.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH ISABLUNARYOPER 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-isablunaryoper \- tests if an operator is unary.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-int isablunaryoper( Oper )
-  long Oper;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIOper\fP
-Operator number.
-.SH DESCRIPTION
-\fBisablunaryoper\fP tests if \fIOper\fP is unary.
-.br
-.SH RETURN VALUE
-\fBisablunaryoper\fP returns 1 if \fIOper\fP is unary, -1
-if \fIOper\fP is not a valid number, and 0 otherwise.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-  /* displays    0 1 */
-  printf( "%d  ", isablunaryoper( ABL_OR  ) );
-  printf( "%d\n", isablunaryoper( ABL_NOT ) );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/isbddvarinsupport.3 b/alliance/share/man/man3/isbddvarinsupport.3
deleted file mode 100644
index ddb0921b..00000000
--- a/alliance/share/man/man3/isbddvarinsupport.3
+++ /dev/null
@@ -1,83 +0,0 @@
-.\"   $Id: isbddvarinsupport.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)isbddvarinsupport.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH ISBDDVARINSUPPORT 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-isbddvarinsupport \- tests if a variable appears in a \fBbdd\fP.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-int isbddvarinsupport( BddSystem, BddNode, Variable )
-  bddsystem \(**BddSystem;
-  bddnode   \(**BddNode;
-  bddvar     Variable;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIBddNode\fP
-The \fBbdd\fP node.
-.TP
-\fIVariable\fP
-The variable number.
-.SH DESCRIPTION
-\fBisbddvarinsupport\fP tests if the variable number \fIVariable\fP
-appears in the support of the \fBbdd\fP node \fIBddNode\fP, in the
-\fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBisbddvarinsupport\fP returns 1 if \fIVariable\fP appears, 0 otherwise.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"variable xxx out of range, error !"
-.ft R
-.RS
-The \fIVariable\fP parameter must be less or equal to
-the \fIBddSystem->NUMBER_VAR\fP field.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   bddnode    \(**BddVariable;
-   chain_list \(**Expr;
-   bddvar         Variable;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   Expr = createablbinexpr( ABL_AND,
-                            createablatom( "i0" ),
-                            createablatom( "i1" ) );
-   BddNode = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   BddVariable = searchbddcircuitin( (bddcircuit \(**)0, "i0" );
-   Variable = getbddvarbyindex( (bddsystem \(** 0), BddVariable->INDEX ) );
-   /* displays 1 */
-   printf( "%d", isbddvarinsupport( (bddsystem \(**)0, BddNode, Variable ) );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/isvdd.3 b/alliance/share/man/man3/isvdd.3
deleted file mode 100644
index 828a421c..00000000
--- a/alliance/share/man/man3/isvdd.3
+++ /dev/null
@@ -1,79 +0,0 @@
-.\"   $Id: isvdd.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)isvdd.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-isvdd
-.XE
-.XS4 \n%
-.ti 0.2i
-isvdd
-.XE4 \}
-.TH ISVDD 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-isvdd \-tells if a name contains the pattern defined by the user
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-void isvdd(s)
-char \(**s;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIs\fP
-Pointer to the string to be check as power high
-.SH DESCRIPTION
-\fBisvdd\fP searches an occurence of the string defined by the \fBMBK_VDD\fP(1)
-environment variable in the string \fIs\fP.
-If this string is not set by the user, its default value is "vdd".
-.SH RETURN VALUE
-\fBisvdd\fP return \fBNULL\fP the pattern is not present 
-If the pattern is found, a value different from \fBNULL\fP is returned.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-#include "mlo315.h"
-find_a_vdd(f)
-lofig_list *f;
-{
-locon_list *c;
-losig_list *s;
-	/* first check connectors */
-	for (c = f->LOCON; c; c = c->NEXT) {
-		if (isvdd(c->NAME))
-			return c->SIG;
-		if (isvdd(getsigname(c->SIG)))
-			return c->SIG;
-	}
-	/* then check internal signals */
-	for (s = f->LOSIG; s; s = s->NEXT)
-		if (s->TYPE == INTERNAL)
-			if (isvdd(getsigname(s)))
-				return s;
-	return NULL;
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR mbkenv (3),
-.BR instr (3),
-.BR isvss (3),
-.BR MBK_VDD (1),
-.BR MBK_VSS (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/isvss.3 b/alliance/share/man/man3/isvss.3
deleted file mode 100644
index b03cffa2..00000000
--- a/alliance/share/man/man3/isvss.3
+++ /dev/null
@@ -1,79 +0,0 @@
-.\"   $Id: isvss.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)isvss.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-isvss
-.XE
-.XS4 \n%
-.ti 0.2i
-isvss
-.XE4 \}
-.TH ISVSS 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-isvss \-tells if a name contains the pattern defined by the user
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-void isvss(s)
-char \(**s;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIs\fP
-Pointer to the string to be check as power high
-.SH DESCRIPTION
-\fBisvss\fP searches an occurence of the string defined by the \fBMBK_VSS\fP(1)
-environment variable in the string \fIs\fP.
-If this string is not set by the user, its default value is "vss".
-.SH RETURN VALUE
-\fBisvss\fP return \fBNULL\fP the pattern is not present 
-If the pattern is found, a value different from \fBNULL\fP is returned.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-#include "mlo315.h"
-find_a_vss(f)
-lofig_list *f;
-{
-locon_list *c;
-losig_list *s;
-	/* first check connectors */
-	for (c = f->LOCON; c; c = c->NEXT) {
-		if (isvss(c->NAME))
-			return c->SIG;
-		if (isvss(getsigname(c->SIG)))
-			return c->SIG;
-	}
-	/* then check internal signals */
-	for (s = f->LOSIG; s; s = s->NEXT)
-		if (s->TYPE == INTERNAL)
-			if (isvss(getsigname(s)))
-				return s;
-	return NULL;
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR mbkenv (3),
-.BR instr (3),
-.BR isvdd (3),
-.BR MBK_VDD (1),
-.BR MBK_VSS (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/lengthExpr.3 b/alliance/share/man/man3/lengthExpr.3
deleted file mode 100644
index 5709d9a9..00000000
--- a/alliance/share/man/man3/lengthExpr.3
+++ /dev/null
@@ -1,59 +0,0 @@
-.\"   $Id: lengthExpr.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)lengthExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH LENGTHEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBlengthExpr\fP \- returns the number of arguments in an expression
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-int lengthExpr(expr)
-chain_list *expr;
-.fi
-.SH PARAMETER
-.TP 20
-\fIexpr\fP
-expression
-.SH DESCRIPTION
-\fBlengthExpr()\fP returns the number of arguments of \fIexpr\fP of the first level. If \fIexpr\fP is an atomic expression, the function returns 1.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr;
-expr = createExpr(OR);
-addQExpr(expr,createAtom("a"));
-addQExpr(expr,createAtom("b"));
-printf("%d",lengthExpr(expr));
-/* it will display
-2
-*/
-freeExpr(expr);
-.fi
-.SH PROGRAM
-.nf
-int lengthExpr(expr)
-chain_list *expr;
-{
-if (ATOM(expr))
-   return(1)
-else
-   {
-   int cpt = 0;
-   while (expr = CDR(expr)) cpt++;
-   return(cpt);
-   }
-} 
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR profExpr (3),
-.BR numberAtomExpr (3),
-.BR equalExpr (3),
-.BR equalVarExpr (3),
-.BR searchExpr (3),
-.BR searchOperExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/libpat.3 b/alliance/share/man/man3/libpat.3
deleted file mode 100644
index 13225ec0..00000000
--- a/alliance/share/man/man3/libpat.3
+++ /dev/null
@@ -1,146 +0,0 @@
-.\"   $Id: libpat.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)pat.2 106  Sep 30 1996 UPMC; Pirouz BAZARGAN SABET
-.TH LIBPAT 3 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBPAT\fP \- Generic pattern data structure
-
-.SH DESCRIPTION
-.PP
-\fBPAT\fP is a generic data structure supporting vlsi concepts.
-It allows representation of a sequence of simulation patterns in a data
-structure.
-
-.PP
-The goal of \fBPAT\fP is to define an ad hoc single data structure (object),
-with well known fixed meaning for each concept manipulated in pattern
-description. So any tools that needs to access simulation patterns can be
-build upon it, using these structures.
-
-.PP
-For each object (data structure), a set of functions has been defined in order
-to add, delete or access it. These functions are defined in a low\-level library
-\fIlibPat106.a\fP. Some other functions are higher level. They are defined in a
-high\-level library \fIlibPhl106.a\fP. There are also some parsers\-drivers.
-A parser reads a pattern description file in a given format and build up a
-complete \fBPAT\fP data base. A driver creates a text file in a given format
-from a \fBPAT\fP data base. A \fBpat\fP format parser\-driver is available
-in the \fIlibPpt106.a\fP library.
-
-.PP
-Pattern description envolves the following notions (for further details see
-pat(5)):
-
-.TP 20
-\fIinput\fP
-port controlled by the user
-.TP 20
-\fIoutput\fP
-signal or port observed by the user
-.TP 20
-\fIinitialization\fP
-forcing the value of a register
-.TP 20
-\fIpattern sequence\fP
-list of values to be forced on inputs or to be checked as the result of the
-simulation on outputs 
-
-.PP
-The input\-output list is represented by two data structures: \fIpagrp\fP
-contains informations relative to actual or virtual arraies and, \fIpaiol\fP
-represents a one\-bit input\-output. Both are simply chained lists. However,
-to make a more efficient access to \fIpaiol\fP structures, they are organized
-in a table. So, a \fIpaiol\fP can also be addressed using an offset.
-
-.PP
-Another group of data structures is used to represent a pattern. \fIpaini\fP
-contains values to be forced into registers before processing the pattern.
-An event (a modification of value) on an input\-output is given by a
-\fIpaevt\fP structure. A third structure, \fIpapat\fP gathers all information
-concerning a pattern (including initializations \- \fIpaini\fP \- and events \-
-\fIpaevt\fP).
-
-.PP
-A \fIpacom\fP is used to represent a comment.
-
-.PP
-Finally, all these structures can be accessed through a unique structure,
-\fIpaseq\fP, designed to represent a complete sequence of simulation patterns.
-
-.SH ORGANIZATION
-.PP
-In order to use \fBPAT\fP, concepts on use of libraries are needed. And, since
-these libraries are under development, the code is subject to change.
-
-.PP
-To enable work, a static version of each library is always present for the
-user. Libraries and header files are suffixed by a number (the library's
-version). The programmer can prefer to work with an earlier version of a
-library rather than the most recent one. However, it is recommended to adapt
-softwares to libraries as soon as possible in order to spotlight potential
-compatibility problems before old libraries are removed.
-
-.PP
-A \fImakefile\fP is necessary for all \fBPAT\fP applications.
-This is required because any soft must be easily recompilable, and knowing
-the needed libraries for a \fBPAT\fP based program is not an easy matter.
-It can't be achieved by an other way, so do use \fImakefile\fP.
-
-.PP
-In terms of software organization, \fBPAT\fP is splitted into two libraries
-for the basic functions, a header file for structures and variable declarations
-and, up to now, one parser\-driver library for \fBpat\fP format.
-
-.PP
-It is to be noticed that library's version number is incremented when, at least,
-one function composing the library has been modified. Therefore, \fBPAT\fP
-libraries may evolve independently form each other.
-
-.PP
-Here follows the list of the libraries and their contents.
-
-.TP 20
-libPat106.a:
-\fBpat_addpaseq,	pat_addpagrp,\fP
-\fBpat_addpaiol,	pat_addpapat,\fP
-\fBpat_addpaevt,	pat_addpaini,\fP
-\fBpat_addpacom,	pat_frepaini,\fP
-\fBpat_frepaiol,	pat_frepacom,\fP
-\fBpat_frepapat,	pat_frepaevt,\fP
-\fBpat_crtpaiol\fP
-
-.TP 20
-libPhl106.a:
-\fBpat_debug,	pat_getcount\fP
-
-.TP 20
-libPpt106.a:
-\fBpat_lodpaseq,	pat_savpaseq,\fP
-\fBpat_drvpat,	pat_prspat\fP
-
-.PP
-The libraries are organized in such a way that no cycle can appear through
-calls. It means that, if in a given library a function calls another function
-in another library, then none of the functions of this one does call any
-function that belongs to the first library.
-
-.SH EXAMPLE
-.PP
-In order to use \fBPAT\fP libraries, one needs something like this in its
-\fImakefile\fP:
-
-.RS
-HEADER = -I/labo/include
-.br
-LIB = -L/labo/lib -lPat106 -lPhl106 -lPpt106 -lMut315
-.RE
-
-.SH SEE ALSO
-.PP
-mbk(1), pat(5)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/loadlofig.3 b/alliance/share/man/man3/loadlofig.3
deleted file mode 100644
index a075eb29..00000000
--- a/alliance/share/man/man3/loadlofig.3
+++ /dev/null
@@ -1,138 +0,0 @@
-.\"   $Id: loadlofig.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)loadlofig.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-loadlofig
-.XE
-.XS3 \n%
-.ti 0.2i
-loadlofig
-.XE3 \}
-.TH LOADLOFIG 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL UTILITY FUNCTIONS"
-.SH NAME
-loadlofig \- load a new logical cell model from disk 
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo412.h"
-void loadlofig(ptfig, figname, mode)
-lofig_list \(**ptfig;
-char \(**figname;
-char mode;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptfig\fP
-Pointer to an allocated but empty \fIlofig\fP
-.TP
-\fIfigname\fP
-Name of the figure to be loaded
-.TP
-\fImode\fP
-Loading mode
-.SH DESCRIPTION
-\fBloadlofig\fP fills the \fIlofig\fP pointed to by \fIptfig\fP with the 
-contents of a disk file called \fIfigname\fP. The loading mode may be either
-\fB'A'\fP, then the entire content is parsed, or \fB'P'\fP then only
-connectors and extrernal signals are loaded in memory, or \fB'C'\fP, that
-loads the "complement" of an already partially loaded cell in order to
-keep the same pointer when accessing the same file.
-.br
-The \fBloadlofig\fP(3) function in fact performs a call to a parser, choosen
-by the \fBMBK_IN_LO\fP(1) environment variable. The directories searched for the
-file are first the one sets by \fBMBK_WORK_LIB\fP(1) and then, in the described
-order, the ones set by \fBMBK_CATA_LIB\fP(1).
-See \fBMBK_IN_LO\fP(1), \fBMBK_WORK_LIB\fP(1), \fBMBK_CATA_LIB\fP(1) and
-\fBmbkenv\fP(3) for details.
-.SH ERRORS
-Some errors resulting from a call to \fBloadlofig\fP are due to the parsers,
-and are prefixed by the parser format (pf). 
-.br
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** not supported logical input format 'xxx'"
-.ft R
-.RS
-The environment variable \fBMBK_IN_LO\fP is not set to a legal logical
-format.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** pfloadlofig : could not open file \fIfigname\fP"
-.ft R
-.RS
-No file called \fIfigname.ext\fP, where \fIext\fP is the file format extension,
-has been found in the directories set by the environment.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** pfloadlofig : syntax error line x parsing \fIfigname.ext\fP"
-.ft R
-.RS
-Either the file has been corrupted and its syntax is not legal, or there is a
-bug in the given parser.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo412.h"
-lofig_list \(**get_the_lofig(figname, mode)
-char \(**figname;
-char mode;
-{
-lofig_list \(**pt;
-	for (pt = HEAD_LOFIG; pt; pt = pt\->NEXT) /\(** scan figure list \(**/
-		if (!strcmp(pt\->NAME, figname))
-			break;
-	if (!pt) { /\(** figure doesn't exist \(**/
-		pt = addlofig(figname);
-		pt\->MODE = mode == 'A' ? mode : 'P';
-		loadlofig(pt, figname, pt\->MODE);
-		return pt;
-	}
-	if (ptfig\->MODE != 'A') { /\(** figure exists interface only \(**/
-		if (mode == 'A') {
-			pt\->MODE = 'A';
-			loadlofig(pt, figname, 'C');
-			return pt;
-		} else
-			return pt;
-	} else /\(** figure exists interface and body \(**/
-		return pt;
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR mbkenv (3),
-.BR lofig (3),
-.BR addlofig (3),
-.BR getlofig (3),
-.BR dellofig (3),
-.BR savelofig (3),
-.BR flattenlofig (3),
-.BR rflattenlofig (3),
-.BR MBK_IN_LO (1),
-.BR MBK_WORK_LIB (1),
-.BR MBK_CATA_LIB (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/loadphfig.3 b/alliance/share/man/man3/loadphfig.3
deleted file mode 100644
index 4ff6baf7..00000000
--- a/alliance/share/man/man3/loadphfig.3
+++ /dev/null
@@ -1,139 +0,0 @@
-.\"   $Id: loadphfig.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)loadphfig.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-loadphfig
-.XE
-.XS1 \n%
-.ti 0.2i
-loadphfig
-.XE1 \}
-.TH LOADPHFIG 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL UTILITY FUNCTIONS"
-.SH NAME
-loadphfig \- load a new physical cell model from disk 
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph403.h"
-void loadphfig(ptfig, figname, mode)
-phfig_list \(**ptfig;
-char \(**figname;
-char mode;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptfig\fP
-Pointer to an allocated but empty \fIphfig\fP
-.TP
-\fIfigname\fP
-Name of the figure to be loaded
-.TP
-\fImode\fP
-Loading mode
-.SH DESCRIPTION
-\fBloadphfig\fP fills the \fIphfig\fP pointed to by \fIptfig\fP with the 
-contents of a disk file called \fIfigname\fP. The loading mode may be either
-\fB'A'\fP, then the entire content is parsed, or \fB'P'\fP then only
-connectors, abutment box, and through routes are loaded, or \fB'C'\fP, that
-finishes to fill an already loaded figure in \fB'P'\fP mode, in order to have
-it all in memory. This last mode allows to keep the same \fIptfig\fP pointer
-when reaccessing the same file.
-.br
-The \fBloadphfig\fP function in fact performs a call to a parser, choosen
-by the \fBMBK_IN_PH\fP(1) environment variable. The directories seached for the
-file are first the one set by \fBMBK_WORK_LIB\fP(1) and then, in the described
-order, the ones set by \fBMBK_CATA_LIB\fP(1).
-See \fBMBK_IN_PH\fP(1), \fBMBK_WORK_LIB\fP(1), \fBMBK_CATA_LIB\fP(1) and
-\fBmbkenv\fP(3) for details.
-.SH ERRORS
-Some errors resulting from a call to \fBloadphfig\fP are due to the parsers,
-and are prefixed by the parser format (pf). 
-.br
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** not supported physical input format 'xxx'"
-.ft R
-.RS
-The environment variable \fIMBK_IN_PH\fP is not set to a legal physical
-format.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** pfloadphfig : could not open file \fIfigname\fP"
-.ft R
-.RS
-No file called \fIfigname.ext\fP, where \fIext\fP is the file format extension,
-has been found in the directories set by the environment.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** pfloadphfig : syntax error line x parsing \fIfigname.ext\fP"
-.ft R
-.RS
-Either the file has been corrupted and its syntax is not legal, or there is a
-bug in the given parser.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph403.h"
-phfig_list \(**get_the_phfig(figname, mode)
-char \(**figname;
-char mode;
-{
-phfig_list \(**pt;
-	for (pt = HEAD_PHFIG; pt; pt = pt\->NEXT) /\(** scan figure list \(**/
-		if (!strcmp(pt\->NAME, figname))
-			break;
-	if (!pt) { /\(** figure doesn't exist \(**/
-		pt = addphfig(figname);
-		pt\->MODE = mode == 'A' ? mode : 'P';
-		loadphfig(pt, figname, pt\->MODE);
-		return pt;
-	}
-	if (ptfig\->MODE != 'A') { /\(** figure exists interface only \(**/
-		if (mode == 'A') {
-			pt\->MODE = 'A';
-			loadphfig(pt, figname, 'C');
-			return pt;
-		} else
-			return pt;
-	} else /\(** figure exists interface and body \(**/
-		return pt;
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR mbkenv (3),
-.BR phfig (3),
-.BR addphfig (3),
-.BR getphfig (3),
-.BR delphfig (3),
-.BR savephfig (3),
-.BR flattenphfig (3),
-.BR rflattenphfig (3),
-.BR MBK_IN_PH (1),
-.BR MBK_WORK_LIB (1),
-.BR MBK_CATA_LIB (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/loadrdsfig.3 b/alliance/share/man/man3/loadrdsfig.3
deleted file mode 100644
index f6fadc10..00000000
--- a/alliance/share/man/man3/loadrdsfig.3
+++ /dev/null
@@ -1,90 +0,0 @@
-.\"   $Id: loadrdsfig.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)loadrdsfig.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-loadrdsfig
-.XE
-.XS0 \n%
-.ti 0.2i
-loadrdsfig
-.XE0 \}
-.TH LOADRDSFIG 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-loadrdsfig \- give back a pointer to a figure 
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rtlnnn.h"
- void loadrdsfig( Figure, Name, Mode )
-    rdsfig_list \(**Figure;
-    char        \(**Name;
-    char         Mode;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIFigure\fP
-Pointer to the RDS Figure created. 
-.TP
-\fIName\fP
-Name of the model of the figure.
-.TP
-\fIMODE\fP :  
-Caracter indicating the status of the figure in memory.
-.PP
-This field can take three values :
-.RS
-.TP
-\fI\'A\'\fP
-All the cell is loaded in ram (The figure, its rectangles and its instances empty).
-.TP
-\fI\'P\'\fP
-Only information concerning the model interface is present, that means : connectors, the abutment box and through routes of the figure.
-.TP
-\fI\'V\'\fP
-Visualization mode : all is loaded in RAM : The figure, its rectangles, its instances and the rectangles of its instances.
-.SH DESCRIPTION
-The \fIloadrdsfig\fP function loads in memory a cell model from disk. The loadrdsfig function in fact performs a call to a  parser ,chosen by the RDS_IN environment variable. 
-.SH RETURN VALUE
-The pointer to the created figure. (it's the parameter \'Figure\' of the loadrdsfig function).
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Rtl103.h: Unknown rds input format"
-.ft R
-.RS
-The input format defined by the unix environment variable RDS_IN is not supported by the driver (supported formats are "cif" and "gds").
-.PP
-Other errors can appear because the loadrdsfig function calls cif and gds parsers.
-.SH EXAMPLE
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rtlnnn.h"
-        main()
-         {
-           rdsfig_list \(**RdsFigure;
-           mbkenv();
-           rdsenv();
-           loadrdsparam();
-           /\(** \(**/ \fBloadrdsfig\fP (RdsFigure, "core", 'A');
-           viewrdsfig( Figure );
-         }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librtl,
-.BR getrdsfig,
-.BR rdsenv,
-.BR RDS_IN
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/loadrdsparam.3 b/alliance/share/man/man3/loadrdsparam.3
deleted file mode 100644
index 90bb20d9..00000000
--- a/alliance/share/man/man3/loadrdsparam.3
+++ /dev/null
@@ -1,78 +0,0 @@
-.\"   $Id: loadrdsparam.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)loadrdsparam.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-loadrdsparam
-.XE
-.XS0 \n%
-.ti 0.2i
-loadrdsparam
-.XE0 \}
-.TH LOADRDSPARAM 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-loadrdsparam \- load parameters from symbolic to real conversion. 
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-void loadrdsparam()
-.ft R
-.fi
-.SH PARAMETER
-none
-.SH DESCRIPTION
-The \fIloadrdsparam\fP function loads parameters contained in a file with extention ".rds" which is the translation file from symbolic to real. Some of these files are contained in the path "/labo/etc".See them for more information.
-.br
-When programming, this function must be called before using the functions of the RFM library ( MBK to RDS convertion functions).
-.br
-The name of the file "nnn.rds" is set with the environment variable of unix system "RDS_TECHNO_NAME". For more information about it, see the RTL library.
-Before calling the loadrdsparam function, environment variables must be set by using the function \fIrdsenv\fP.
-.SH RETURN VALUE
-none
-.SH ERRORS
-Errors can appear during loading of the "file.rds". All error messages have the header "Rpr203:" and an explanation of the error.
-.br
-example :
-.br
-"Rpr203: Some tables missing"
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mphnnn.h"
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rtlnnn.h"
-        #include "rprnnn.h"
-        #include "rfmnnn.h"
-        main()
-         {
-           rdsfig_list *RdsFigure;
-           phfig_list  *MbkFigure;
-           mbkenv();
-           rdsenv();
-           /* */ \fBloadrdsparam\fP ();
-           MbkFigure = getphfig ( "na2_y", 'A' );
-           RdsFigure = figmbkrds ( MbkFigure, 0, 1);
-           viewrfmfig ( MbkFigure, RdsFigure );
-           . . .
-         }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librpr,
-.BR librtl,
-.BR rdsenv,
-.BR mbkenv
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/locon.3 b/alliance/share/man/man3/locon.3
deleted file mode 100644
index bbaf9594..00000000
--- a/alliance/share/man/man3/locon.3
+++ /dev/null
@@ -1,119 +0,0 @@
-.\"   $Id: locon.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)locon.l 0.0 90/22/08 UPMC; Author: Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-locon
-.XE
-.XS2 \n%
-.ti 0.2i
-locon
-.XE2 \}
-.TH LOCON 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL STRUCTURE DEFINITIONS"
-.SH NAME
-locon \- mbk logical connector 
-.SH DESCRIPTION
-The \fBlocon\fP is used to describe a connector of the logical view	
-of a figure. Connectors are describing the cell interface, and are the link
-between its physical and logical views, so the names must be the same. 
-.LP
-The declarations needed to work on \fBlocon\fP are available in the header file
-\fI"/labo/include/mlo404.h"\fP, where '\fI404\fP' is the actual mbk version.
-.LP
-The following C structure supports the description of the logical connector :
-.RS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.ta 3n 20n 30n
-typedef struct locon {
-	struct locon	\(**NEXT;
-	char	\(**NAME;
-	struct losig	\(**SIG;
-	void	\(**ROOT;
-	char	DIRECTION;
-	char	TYPE;
-	struct ptype	\(**USER;
-} locon_list;
-.ft R
-.fi
-.RE
-.TP 20
-\fINEXT\fP
-Pointer to the next \fBlocon\fP of the list.
-.TP
-\fINAME\fP
-Name of the connector. It identifies the connector, so it should unique in a
-given logical figure. A logical connector with a given name correspond to the
-physical connector or connectors of this name.
-.TP
-\fISIG\fP
-Pointer to the signal linked to the connector. This signal is, of course, 
-unique. See \fBlosig\fP(3) for details. 
-.TP
-\fIROOT\fP
-Pointer to the object it belongs to. This object may be either a \fBlofig\fP,
-or a \fBloins\fP, depending on the type of the connector.
-See \fBlofig\fP(3) and \fBloins\fP for details.
-.TP
-\fIDIRECTION\fP
-This indicates the way of the information going through the connector.
-Six directions are legal :
-.RS
-.TP 20
-\fBIN\fP
-input
-.TP
-\fBOUT\fP
-output
-.TP
-\fBINOUT\fP
-input and output
-.TP
-\fBUNKNOWN\fP
-no information is available
-.TP
-\fBTRISTATE\fP
-tristate output
-.TP
-\fBTRANSCV\fP
-tristate output and input
-.RE   
-.fi
-.TP
-\fITYPE\fP
-Character indicating if the connector belongs to a model or an instance. It
-can take two values :
-.RS
-.TP 20
-\fBEXTERNAL\fP
-for figure connectors
-.TP
-\fBINTERNAL\fP
-for instance connectors
-.LP
-The \fITYPE\fP is needed to appropriatly cast the \fIROOT\fP field, and must
-be approriatly filled by the parsers. A misuse of it may cause strange
-behaviours.
-.RE
-.TP
-\fIUSER\fP
-Pointer to a ptype list, see \fBptype\fP for details, that is a general purpose
-pointer used to share informations on the connector.
-.SH SEE ALSO
-.BR mbk(1),
-.BR mbk(3),
-.BR addlocon (3),
-.BR getlocon (3),
-.BR dellocon (3),
-.BR losig (3),
-.BR ptype (3),
-.BR loins (3),
-.BR lofig (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/lofig.3 b/alliance/share/man/man3/lofig.3
deleted file mode 100644
index f1cd82ed..00000000
--- a/alliance/share/man/man3/lofig.3
+++ /dev/null
@@ -1,118 +0,0 @@
-.\"   $Id: lofig.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)lofig.l 0.0 90/22/08 UPMC; Author: Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-lofig
-.XE
-.XS2 \n%
-.ti 0.2i
-lofig
-.XE2 \}
-.TH LOFIG 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL STRUCTURE DEFINITIONS"
-.SH NAME
-lofig \- mbk logical figure 
-.SH DESCRIPTION
-The \fBlofig\fP is used to describe a hierarchical level of the logical view
-of a figure. The logical view is also called the netlist, for list of nets,
-because it represents the interconections between elements of a cell.
-.LP
-The declarations needed to work on \fBlofig\fP are available in the header file
-\fI"/labo/include/mlo404.h"\fP, where '\fI404\fP' is the actual mbk version.
-.LP
-The following C structure supports the description of the netlist
-representation :
-.RS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.ta 3n 20n 30n
-typedef struct lofig {
-	struct lofig	\(**NEXT;
-	struct chain	\(**MODELCHAIN;
-	struct locon	\(**LOCON;
-	struct losig	\(**LOSIG;
-	struct ptype	\(**BKSIG;
-	struct loins	\(**LOINS;
-	struct lotrs	\(**LOTRS;
-	char	\(**NAME;
-	char	MODE;
-	struct ptype	\(**USER;
-} lofig_list;
-.ft R
-.fi
-.RE
-.TP 20
-\fINEXT\fP
-Pointer to the next \fBlofig\fP loaded in ram.
-.TP
-\fINAME\fP
-Name of the figure. It identifies a figure (or \fImodel\fP), so it should
-be unique in order to warranty consistency of cells libraries. In order
-to ensure this consistency, the \fINAME\fP field must be filled with the
-disk file name while parsing, and must be used as file name for driving.
-.TP
-\fILOINS\fP
-Pointer to the head of the list of instances being used for the model 
-description. See \fBloins\fP(3) for details.
-.TP
-\fILOCON\fP
-Pointer to the head of the list of connectors (terminals) of the model.
-See \fBlocon\fP(3) for details.
-.TP
-\fILOSIG\fP
-Pointer to the head of the list of signal of the model.
-See \fBlosig\fP(3) for details.
-.TP
-\fIBKSIG\fP
-Pointer to a hash table that contains arrays of \fILOSIG\fP. It is only an
-other way to represent the same elements that in the list, but allows a
-faster access. The Mbk Logical Functions warranty the consitency between
-the two representations.
-.TP
-\fILOTRS\fP
-Pointer to the list of transistors belonging to the figure. It is to be noticed
-that transistors are not instances of a particular type.
-.TP
-\fIMODE\fP
-Caracter indicating the status of the figure in memory. This field can
-take two values :
-.RS
-.TP 10
-.B \'A\'
-all the cell is loaded in ram.
-.TP
-.B \'P\'
-only information concerning the model interface is present, that
-means connectors, and signals linked to external connectors.
-All other lists are empty.
-.RE
-.TP
-\fIMODELCHAIN\fP
-Pointer to a chain list, see \fBchain\fP(3) for details, of names. These are
-the names of the models that are at least instanciated once in the figure.
-.TP
-\fIUSER\fP
-Pointer to a ptype list, see \fBptype\fP(3) for details, that is a general
-purpose pointer used to share informations on the model.
-.SH SEE ALSO
-.BR mbk (1),
-.BR addlofig (3),
-.BR getlofig (3),
-.BR dellofig (3),
-.BR loadlofig (3),
-.BR savelofig (3),
-.BR loins (3),
-.BR lotrs (3),
-.BR locon (3),
-.BR losig (3),
-.BR ptype (3),
-.BR chain (3),
-.BR phfig (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/lofigchain.3 b/alliance/share/man/man3/lofigchain.3
deleted file mode 100644
index 5211ac5b..00000000
--- a/alliance/share/man/man3/lofigchain.3
+++ /dev/null
@@ -1,97 +0,0 @@
-.\"   $Id: lofigchain.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)lofigchain.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-lofigchain
-.XE
-.XS2 \n%
-.ti 0.2i
-lofigchain
-.XE2 \}
-.TH LOFIGCHAIN 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL FUNCTIONS"
-.SH NAME
-lofigchain \- creates a netlist in terms of connectors on signals
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-void lofigchain(ptfig)
-lofig_list \(**ptfig;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIptfig\fP
-Pointer to a lofig_list
-.SH DESCRIPTION
-The \fBlofigchain\fP function creates the dual representation of natural
-mbk netlists. In mbk, netlists are described in terms of signal attached to
-connectors.
-With \fBlofigchain\fP, one can have the dual sight : connectors attached to
-signals.
-This can be very useful, depending on the application, but it's also memory
-consuming on big netlists, since two views of the same thing are present in
-memory at the same time.
-.LP
-The information resulting of a call to \fBlofigchain\fP is present in the
-\fIUSER\fP field of all signals of the figure, accessible through
-\fIptfig\->LOSIG\fP. The \fIUSER\fP field has a \fBptype\fP typed
-\fILOFIGCHAIN\fP, that points on a \fBchain_list\fP whose \fIDATA\fP points on
-each \fBlocon\fP beeing connected to the given signal.
-.SH ERROR
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** lofigchain impossible : figure \fIptfig\->NAME\fP is
-interface only"
-.ft R
-.RS
-In order to be valid, the netlist resulting of a call to \fBlofigchain\fP must
-be done on a figure entirely loaded in ram. See \fBgetlofig\fP for details. 
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut404.h"
-#include "mlo404.h"
-void print_netlist(p)
-lofig_list \(**p;
-{
-losig_list \(**s;
-chain_list \(**c;
-	lofigchain(p);
-	for (s = p\->LOSIG; s; s = s\->NEXT){ 
-		(void)fprintf(stdout, "signal : index = %ld name = %s\\n",
-				s\->INDEX, getsigname(s));
-		c = (chain_list \(**)(getptype(s\->USER, (long)LOFIGCHAIN)\->DATA);
-		while (c) {
-			fprintf(stdout, "conname : %s\\n",
-				(locon_list \(**)(c\->DATA)\->NAME);
-			c = c\->NEXT;
-		}
-	}
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR lofig (3),
-.BR locon (3),
-.BR losig (3),
-.BR getlofig (3),
-.BR loadlofig (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/log.3 b/alliance/share/man/man3/log.3
deleted file mode 100644
index 3ad6a2ea..00000000
--- a/alliance/share/man/man3/log.3
+++ /dev/null
@@ -1,34 +0,0 @@
-.\"   $Id: log.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)log.2 0.0 92/08/01 UPMC; Author: Luc Burgun
-.pl -.4
-.TH LOG 3 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-.SH NAME
-\fBlog\fP \- logical representations for boolean functions and utilities.
-.so man1/alc_origin.1
-.SH DESCRIPTION
-\fBlog\fP is a set of structures and functions that permits to manipulate several representations of boolean functions. Several programs and libraries of the \fIcao-vlsi cad tools\fP rest on the \fIlog\fP package. Two different kind of functions are available for:
-.TP 20
-Prefixed representation for boolean functions
-.TP 20
-Ordered binary decision diagrams representation
-.SH EXAMPLE
-Let's suppose that actual mbk version is 'nnn'.
-In order to use log, \fIlibMutnnn.a\fP library must be called. 
-.br
-\fImakefile\fP:
-.br
-HEADER = -I/labo/include 
-.br
-LIB = -L/labo/lib -lMutnnn -ltshmmm -lablmmm -lbddmmm
-.br
-Each library can be called separatly. The "logmmm.h" header file must be inserted in the files that use the functions or the structures defined in a library.  
-.br
-.SH SEE ALSO
-.BR mbk (1),
-.BR beh (1),
-.SH AUTHOR
-L. BURGUN salle 30 T. 55-65 Universite P&M Curie - 4 pl. Jussieu - FRANCE
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/loins.3 b/alliance/share/man/man3/loins.3
deleted file mode 100644
index 80b8be92..00000000
--- a/alliance/share/man/man3/loins.3
+++ /dev/null
@@ -1,73 +0,0 @@
-.\"   $Id: loins.3,v 1.1 1999/05/31 17:30:22 alliance Exp $
-.\" @(#)loins.l 0.0 90/22/08 UPMC; Author: Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-loins
-.XE
-.XS2 \n%
-.ti 0.2i
-loins
-.XE2 \}
-.TH LOINS 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL STRUCTURE DEFINITIONS"
-.SH NAME
-loins \- mbk logical instance 
-.SH DESCRIPTION
-The \fBloins\fP is used to describe an instance of the logical view
-of a figure.
-.LP
-The declarations needed to work on \fBloins\fP are available in the header file
-\fI"/labo/include/mlo404.h"\fP, where '\fI404\fP' is the actual mbk version.
-.LP
-The following C structure supports the description of the logical instance :
-.RS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.ta 3n 20n 30n
-typedef struct loins {
-	struct loins	\(**NEXT;
-	struct locon	\(**LOCON;
-	char	\(**INSNAME;
-	char	\(**FIGNAME;
-	struct ptype	\(**USER;
-} loins_list;
-.ft R
-.fi
-.RE
-.TP 20
-\fINEXT\fP
-Pointer to the next \fBloins\fP of the list.
-.TP
-\fIINSNAME\fP
-Local name of the instance. It identifies the instance at a given hierarchical
-level, so it should unique. When working on both layout and netlist views of
-a cell, instance names should be the same on each representation.
-.TP
-\fIFIGNAME\fP
-Name of the model of the instanciated cell.
-.TP
-\fILOCON\fP
-Pointer to the head of the list of connectors of the instance. Consistency
-between the connectors of the instance and the connectors of its model on disk
-is not ensured by the parsers, because a model local to the file beeing parsed
-is used, not the possible model on disk. See \fBlocon\fP(3) for details.
-.TP
-\fIUSER\fP
-Pointer to a ptype list, see \fBptype\fP(3) for details, that is a general purpose
-pointer used to share informations on the instance.
-.SH SEE ALSO
-.BR mbk (1),
-.BR addloins (3),
-.BR getloins (3),
-.BR delloins (3),
-.BR locon (3),
-.BR lofig (3),
-.BR ptype (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/losig.3 b/alliance/share/man/man3/losig.3
deleted file mode 100644
index 08368b57..00000000
--- a/alliance/share/man/man3/losig.3
+++ /dev/null
@@ -1,100 +0,0 @@
-.\"   $Id: losig.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)losig.l 0.0 90/22/08 UPMC; Author: Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-losig
-.XE
-.XS2 \n%
-.ti 0.2i
-losig
-.XE2 \}
-.TH LOSIG 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL STRUCTURE DEFINITIONS"
-.SH NAME
-losig \- mbk logical signal
-.SH DESCRIPTION
-The \fBlosig\fP is used to describe a logical signal.
-.LP
-The declarations needed to work on \fBlosig\fP are available in the header file
-\fI"/labo/include/mlo404.h"\fP, where '\fI404\fP' is the actual mbk version.
-.LP
-The following C structure supports the description of the logical signal :
-.RS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.ta 3n 20n 30n
-typedef struct losig {
-	struct losig	\(**NEXT; 
-	struct chain	\(**NAMECHAIN;
-	float	CAPA;
-	long	INDEX;
-	char	TYPE;
-	struct ptype	\(**USER;
-} losig_list;
-.ft R
-.fi
-.RE
-.TP 20
-\fINEXT\fP
-Pointer to the next \fBlosig\fP of the list.
-.TP
-\fIINDEX\fP
-Long integer beeing the signal identifier. It represents the net
-number at a given hierachical level, and must be unique.
-.TP
-\fINAMECHAIN\fP
-Pointer to a list of names, aliases, attached to the signal. If no names
-are given then the field points to \fINULL\fP. Many names can be present if
-the signal result of the flatten of a netlist.
-See \fBchain\fP(3) for details.
-.TP
-\fICAPA\fP
-Floating point number containing the value of the total capacitance attached
-to a signal in respect to ground. This field may be set to zero, since it
-make sens only if the signal is the result of a layout extraction, or has
-been used for electrical simulation purposes.
-.TP
-\fITYPE\fP
-This field can take two legal values depending on the types of the connectors
-attached to it. See \fBlocon\fP(3) for detail. 
-.RS
-.TP 20
-\fBEXTERNAL\fP
-The signal is connected at least to one external
-connector, a connector of the figure beeing described.
-.TP
-\fBINTERNAL\fP
-The signal is connected only to instances or
-transistors connectors.
-.LP
-The tools using the \fITYPE\fP should fill it with care, since unexpected
-results may appear if the consistency with connectors is violated.
-.RE
-.TP
-\fIUSER\fP
-Pointer to a ptype list, see \fBptype\fP(3) for details, that is a general
-purpose pointer used to share informations on the signal.
-.TP
-Remark :
-the netlist view is given in terms of connectors pointing to signals,
-but it may be useful to have also the dual representation, in term of
-list of connectors attached to a single signal. This may be obtained by
-the \fBlofigchain\fP function.
-.SH SEE ALSO
-.BR mbk (1),
-.BR addlosig (3),
-.BR getlosig (3),
-.BR dellosig (3),
-.BR lofigchain (3),
-.BR locon (3),
-.BR lofig (3),
-.BR chain (3),
-.BR ptype (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/lotrs.3 b/alliance/share/man/man3/lotrs.3
deleted file mode 100644
index bc732740..00000000
--- a/alliance/share/man/man3/lotrs.3
+++ /dev/null
@@ -1,115 +0,0 @@
-.\"   $Id: lotrs.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)lotrs.l 0.0 90/22/08 UPMC; Author: Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-lotrs
-.XE
-.XS2 \n%
-.ti 0.2i
-lotrs
-.XE2 \}
-.TH LOTRS 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL STRUCTURE DEFINITIONS"
-.SH NAME
-lotrs \- mbk logical transistor
-.SH DESCRIPTION
-The \fBlotrs\fP is used to describe a logical transistor. It is mostly used
-to describe leaf cells in terms of transistors interconnections, and as a
-result of layout extractions. Since the only target technology is CMOS, only
-NMOS and PMOS transistors are used.
-.LP
-The declarations needed to work on \fBlotrs\fP are available in the header file
-\fI"/labo/include/mlo404.h"\fP, where '\fI404\fP' is the actual mbk version.
-.LP
-The following C structure supports the description of the logical transistor :
-.RS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.ta 3n 20n 30n
-typedef struct lotrs {
-	struct lotrs	\(**NEXT; 
-	struct locon	\(**DRAIN;
-	struct locon	\(**GRID; 
-	struct locon	\(**SOURCE;
-	long	X,Y;
-	unsigned short	WIDTH, LENGTH;
-	unsigned short	PS, PD;
-	unsigned short	XS, XD;
-	char	TYPE;
-	struct ptype	\(**USER;
-} lotrs_list;
-.ft R
-.fi
-.RE
-.TP 20
-\fINEXT\fP
-Pointer to the next \fBlotrs\fP of the list.
-.TP
-\fIDRAIN\fP
-Pointer to the drain connector of the transistor. This connector is,
-of course unique. See \fBlocon\fP(3) for details.
-.TP
-\fIGRID\fP
-Pointer to the grid connector of the transistor. This connector is,
-of course unique. See \fBlocon\fP(3) for details.
-.TP
-\fISOURCE\fP
-Pointer to the source connector of the transistor. This connector is,
-of course unique. See \fBlocon\fP(3) for details.
-.TP
-\fIX, Y\fP
-Coordinates of the transistor in a layout. These informations have sens only if
-the transistor netlist is the result of a layout extraction. They are
-otherwise set to zero.
-These coordinates are given in micron times the scale factor \fBSCALE_X\fP,
-since the extracted view is technology
-dependant.
-.TP
-\fIWIDTH, LENGTH\fP
-Respectivly width and length of the transistor grid.
-.TP
-\fIPS, PD\fP
-Respectivly perimeter of the source and drain, in micron times the scale
-factor \fBSCALE_X\fP.
-.TP
-\fIXS, XD\fP
-These values are needed to compute respectivly the source and drain areas.
-Let \fIAs\fP be the source area in square microns, and \fIWidth\fP be the
-transistor grid width in micron, then
-\fIlotrs->XS = As / Width * SCALE_X\fP
-.TP
-\fITYPE\fP
-Canal type of the transistor. Two legal values are available :
-.RS
-.TP 20
-\fBTRANSN\fP
-N type MOS transistor
-.TP
-\fBTRANSP\fP
-P type MOS transistor
-.RE
-.TP
-\fIUSER\fP
-Pointer to a ptype list, see \fBptype\fP(3) for details, 
-that is a general purpose
-pointer used to share informations on the transistor.
-.TP
-Remark :
-The transistors do not have a bulk connector, since in integrated techniques
-NMOS transistor bulk is always set to ground, and PMOS transistor bulk is
-always set to positive supply.
-.SH SEE ALSO
-.BR mbk (1),
-.BR addlotrs (3),
-.BR dellotrs (3),
-.BR locon (3),
-.BR lofig (3),
-.BR ptype (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/mapCarExpr.3 b/alliance/share/man/man3/mapCarExpr.3
deleted file mode 100644
index 812ba11a..00000000
--- a/alliance/share/man/man3/mapCarExpr.3
+++ /dev/null
@@ -1,54 +0,0 @@
-.\"   $Id: mapCarExpr.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)mapCarExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH MAPCAREXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBmapCarExpr\fP \- creates a new expression by applying a function to all the arguments of an operator expression
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-chain_list *mapCarExpr(func,oper,expr)
-chain_list *(*func)();
-short oper;
-chain_list *expr;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIfunc\fP
-function to apply
-.TP 20
-\fIoper\fP
-Operator number (OR,AN,XOR,NAND,NOR...).
-.TP 20
-\fIexpr\fP
-expression from wich th new expression is deduced 
-.SH DESCRIPTION
-\fBmapCarExpr()\fP creates a head of an operator expression having \fIoper\fP as operator and adds the arguments calculated by applying \fIfunc()\fP to each arguments of \fIexpr\fP. \fIfunc()\fP must return an expression and must have a unique expression as argument. 
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr1,*expr2; 
-expr1 = createExpr(NOR);
-addHExpr(expr1,createAtom("a"));
-addHExpr(expr1,createAtom("b"));
-
-		/* it looks like Morgan's Law... */
-
-expr2 = mapCarExpr(notExpr,AND,expr1);
-displayExpr(expr2);	
-/* it will display
-(AND (NOT b) (NOT a))
-*/
-freeExpr(expr1);
-freeExpr(expr2);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR mapExpr (3),
-.BR anyExpr (3),
-.BR everyExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/mapExpr.3 b/alliance/share/man/man3/mapExpr.3
deleted file mode 100644
index 72eb7eff..00000000
--- a/alliance/share/man/man3/mapExpr.3
+++ /dev/null
@@ -1,50 +0,0 @@
-.\"   $Id: mapExpr.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)mapExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH MAPEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBmapExpr\fP \- applies a procedure to all arguments of an operator expression
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-void mapExpr(func,expr)
-void (*func)();
-chain_list *expr;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIfunc\fP
-function to apply
-.TP 20
-\fIexpr\fP
-expression
-.SH DESCRIPTION
-\fBmapExpr()\fP applies \fIfunc()\fP to all the arguments of \fIexpr\fP. \fIfunc()\fP must be a procedure (it returns \fIvoid\fP) and must have an expression as argument . 
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-				/*newDisplayExpr */
-
-void newDisplayExpr(expr)
-chain_list *expr;
-{
-if (ATOM(expr))
-   printf(" %s",VALUE_ATOM(expr));
-else
-   {
-   printf("(%s ",operToChar(OPER(expr)));
-   mapExpr(newDisplayExpr,expr);
-   printf(")");
-   }
-}
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR mapCarExpr (3),
-.BR anyExpr (3),
-.BR everyExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/mapablanyexpr.3 b/alliance/share/man/man3/mapablanyexpr.3
deleted file mode 100644
index c2301e0f..00000000
--- a/alliance/share/man/man3/mapablanyexpr.3
+++ /dev/null
@@ -1,68 +0,0 @@
-.\"   $Id: mapablanyexpr.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)mapablanyexpr.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH MAPABLANYEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-mapablanyexpr \- applies a function to all operands.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-int mapablanyexpr( Function, Expr )
-  void      (\(**Function)();
-  chain_list \(**Expr;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-.TP
-\fIFunction\fP
-Function name to apply to all operands.
-.TP
-\fIExpr\fP
-Expression to scan.
-.SH DESCRIPTION
-\fBmapablanyexpr\fP applies \fIFunction\fP to all operands of \fIExpr\fP.
-.br
-.SH RETURN VALUE
-\fBmapablanyexpr\fP returns the value of a logical OR applied on
-the results of the application of the function on the arguments of
-an operator expression.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-   int MapFunction( MapExpr )
-     chain_list \(**MapExpr;
-   {
-     if ( ABL_ATOM( MapExpr ) )
-     {
-       if ( ABL_ATOM_VALUE( MapExpr ) == getablatomzero() )
-       {
-         return( 1 );
-       }
-     }
-     return( 0 );
-   }
-   ...
-   chain_list \(**Expr;
-   ...
-   mapablanyexpr( MapFunction, Expr );
-   ...
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1),
-.BR mapablexpr(3),
-.BR mapableveryexpr(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/mapableveryexpr.3 b/alliance/share/man/man3/mapableveryexpr.3
deleted file mode 100644
index 05138990..00000000
--- a/alliance/share/man/man3/mapableveryexpr.3
+++ /dev/null
@@ -1,68 +0,0 @@
-.\"   $Id: mapableveryexpr.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)mapableveryexpr.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH MAPABLEVERYEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-mapableveryexpr \- applies a function to all operands.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-int mapableveryexpr( Function, Expr )
-  void      (\(**Function)();
-  chain_list \(**Expr;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-.TP
-\fIFunction\fP
-Function name to apply to all operands.
-.TP
-\fIExpr\fP
-Expression to scan.
-.SH DESCRIPTION
-\fBmapableveryexpr\fP applies \fIFunction\fP to all operands of \fIExpr\fP.
-.br
-.SH RETURN VALUE
-\fBmapableveryexpr\fP returns the value of a logical AND applied on
-the results of the application of the function on the arguments of
-the expression \fIExpr\fP.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-   int MapFunction( MapExpr )
-     chain_list \(**MapExpr;
-   {
-     if ( ABL_ATOM( MapExpr ) )
-     {
-       if ( ABL_ATOM_VALUE( MapExpr ) == getablatomzero() )
-       {
-         return( 1 );
-       }
-     }
-     return( 0 );
-   }
-   ...
-   chain_list \(**Expr;
-   ...
-   mapableveryexpr( MapFunction, Expr );
-   ...
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1),
-.BR mapablexpr(3),
-.BR mapablanyexpr(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/mapablexpr.3 b/alliance/share/man/man3/mapablexpr.3
deleted file mode 100644
index 110ec705..00000000
--- a/alliance/share/man/man3/mapablexpr.3
+++ /dev/null
@@ -1,64 +0,0 @@
-.\"   $Id: mapablexpr.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)mapablexpr.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH MAPABLEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-mapablexpr \- applies a function to all operands.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-void mapablexpr( Function, Expr )
-  void      (\(**Function)();
-  chain_list \(**Expr;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-.TP
-\fIFunction\fP
-Function name to apply to all operands.
-.TP
-\fIExpr\fP
-Expression to scan.
-.SH DESCRIPTION
-\fBmapablexpr\fP applies \fIFunction\fP to all operands of \fIExpr\fP.
-.br
-.SH RETURN VALUE
-\fBmapablexpr\fP returns nothing.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-   void MapFunction( MapExpr )
-     chain_list \(**MapExpr;
-   {
-     if ( ABL_ATOM( MapExpr ) )
-     {
-       printf( stdout, "%s", ABL_ATOM_VALUE( MapExpr ) );
-     }
-     else
-     {
-       mapablexpr( MapFunction, MapExpr );
-     }
-   }
-   ...
-   chain_list \(**Expr;
-   ...
-   mapablexpr( MapFunction, Expr );
-   ...
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/mapabloperexpr.3 b/alliance/share/man/man3/mapabloperexpr.3
deleted file mode 100644
index c254a1b1..00000000
--- a/alliance/share/man/man3/mapabloperexpr.3
+++ /dev/null
@@ -1,70 +0,0 @@
-.\"   $Id: mapabloperexpr.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)mapabloperexpr.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH MAPABLOPEREXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-mapabloperexpr \- applies a function to all operands.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-chain_list \(**mapabloperexpr( Function, Oper, Expr )
-  chain_list \(** (\(**Function)();
-  long       Oper;
-  chain_list \(**Expr;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-.TP
-\fIFunction\fP
-Function name to apply to all operands.
-.TP
-\fIOper\fP
-Operator number.
-.TP
-\fIExpr\fP
-Expression to scan.
-.SH DESCRIPTION
-\fBmapabloperexpr\fP applies \fIFunction\fP to all operands of \fIExpr\fP.
-\fBmapabloperexpr\fP creates a head of an operator expression having
-\fIOper\fP as operator and adds the arguments calculated by applying
-\fIFunction\fP to each arguments of \fIExpr\fP.
-\fIFunction\fP must return an expression and must have a 
-unique expression as argument.
-.br
-.SH RETURN VALUE
-\fBmapabloperexpr\fP returns a new expression by applying \fIFunction\fP
-to all the arguments of the operator expression \fIExpr\fP.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-   chain_list \(**MapFunction( MapExpr )
-      chain_list \(**MapExpr;
-   {
-     return( createablnotexpr( dupablexpr( MapExpr ) ) );
-   }
-   chain_list \(**Expr;
-   chain_list \(**Expr1;
-   Expr = createablbinexpr( ABL_NOR,
-                            createablatom( "a" ),
-                            createablatom( "b" ) );
-   Expr1 = mapabloperexpr( MapFunction, ABL_AND, Expr );
-   /* displays ((not a) and (not b))  */
-   viewablexpr( Expr1, ABL_VIEW_VHDL );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/markAllBdd.3 b/alliance/share/man/man3/markAllBdd.3
deleted file mode 100644
index aa4f5b57..00000000
--- a/alliance/share/man/man3/markAllBdd.3
+++ /dev/null
@@ -1,28 +0,0 @@
-.\"   $Id: markAllBdd.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)markAllBdd.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH MARKALLBDD 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBmarkAllBdd\fP \- marks all the nodes of the BDDs system
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-void markAllBdd(value)
-short value;
-.fi
-.SH PARAMETER
-.TP 20
-\fIvalue\fP
-value to assign
-.SH DESCRIPTION
-\fBmarkAllBdd()\fP assigns to \fIvalue\fP the marks of all the nodes used in the BDDs system. 
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR markBdd (3),
-.BR numberNodeBdd (3),
-.BR numberNodeAllBdd (3),
-.BR supportChain_listBdd (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/markBdd.3 b/alliance/share/man/man3/markBdd.3
deleted file mode 100644
index a2e89e54..00000000
--- a/alliance/share/man/man3/markBdd.3
+++ /dev/null
@@ -1,32 +0,0 @@
-.\"   $Id: markBdd.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)markBdd.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH MARKBDD 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBmarkBdd\fP \- marks all nodes of a BDD 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-void markBdd(pBdd,value)
-pNode pBdd;
-short value;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIpBdd\fP
-BDD to mark 
-.TP 20
-\fIvalue\fP
-value to assign
-.SH DESCRIPTION
-\fBmarkBdd()\fP assigns to \fIvalue\fP the field \fImark\fP of all the nodes used in \fIpBdd\fP. This function is used for the garbage collection. When a node is created, its mark is set to 0 (the default value).
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR markAllBdd (3),
-.BR numberNodeBdd (3),
-.BR numberNodeAllBdd (3),
-.BR gcNodeBdd (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/markbddnode.3 b/alliance/share/man/man3/markbddnode.3
deleted file mode 100644
index c68fbf73..00000000
--- a/alliance/share/man/man3/markbddnode.3
+++ /dev/null
@@ -1,70 +0,0 @@
-.\"   $Id: markbddnode.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)markbddnode.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH MARKBDDNODE 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-markbddnode \- marks \fBbdd\fP node with a specified mask.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-long markbddnode( BddSystem, BddNode, Mark )
-  bddsystem \(**BddSystem;
-  bddnode   \(**BddNode;
-  bddmark    Mark;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIBddNode\fP
-The \fBbdd\fP node to mark.
-.TP
-\fIMark\fP
-The bit mask.
-.SH DESCRIPTION
-\fBmarkbddnode\fP marks the \fBbdd\fP node \fIBddNode\fP
-with the bit mask \fIMark\fP, in the \fBbdd\fP system BddSystem.
-If a null pointer is given, the default \fBbdd\fP system is used.
-This function does a OR with the field MARK of the \fBbdd\fP node \fIBddNode\fP,
-and the bit mask \fIMark\fP.
-.br
-.SH RETURN VALUE
-\fBmarkbddnode\fP returns the number of the differents marked nodes. 
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   chain_list \(**Expr;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   Expr = createablbinexpr( ABL_AND,
-                            createablatom( "i0" ),
-                            createablatom( "i1" ) );
-   BddNode = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   printf( "Number nodes: %ld\n", 
-           markbddnode( (bddsystem \(**)0, BddNode, 0x0001 ) );
-   unmarkbddnode( (bddsystem \(**)0, BddNode, 0x0001 );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/maxExpr.3 b/alliance/share/man/man3/maxExpr.3
deleted file mode 100644
index e8f49cf0..00000000
--- a/alliance/share/man/man3/maxExpr.3
+++ /dev/null
@@ -1,58 +0,0 @@
-.\"   $Id: maxExpr.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)maxExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH MAXEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBmaxExpr\fP \- returns the highest argument of an operator expression.
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-chain_list *maxExpr(expr,func)
-chain_list *expr;
-int (*func)();
-.fi
-.SH PARAMETERS
-.TP 20
-\fIexpr\fP
-operator expression 
-.TP 20
-\fIfunc\fP
-integer function
-.SH DESCRIPTION
-\fBmaxExpr()\fP returns the highest argument found by using the integer function \fIfunc()\fP. This function doesn't copy the returned argument.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr1,*expr2,*expr3; 
-expr1 = createExpr(OR);
-addQExpr(expr1,createAtom("a"));
-addQExpr(expr1,createAtom("b"));
-expr2 = createExpr(AND);
-addQExpr(expr2,createAtom("c"));
-addQExpr(expr2,createAtom("d"));
-addQExpr(expr1,expr2);
-displayExpr(expr1);
-expr3 = maxExpr(expr1,numberAtomExpr);
-displayExpr(expr3);
-
-/* it will display
-(OR a b (AND c d))
-(AND c d)
-*/
-freeExpr(expr1);	/* don't free expr3 or expr2 ! */
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR sortExpr (3),
-.BR minExpr (3),
-.BR copyExpr (3),
-.BR substExpr (3),
-.BR substPhyExpr (3),
-.BR flatArityExpr (3),
-.BR flatPolarityExpr (3),
-.BR normExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/mbk.3 b/alliance/share/man/man3/mbk.3
deleted file mode 100644
index a171fb03..00000000
--- a/alliance/share/man/man3/mbk.3
+++ /dev/null
@@ -1,20 +0,0 @@
-.\"   $Id: mbk.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)mbk.l 0.0 90/22/08 UPMC; Author: Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-\fBPresentation of generic \fIlayout\fP and \fInetlist\fP data structures\fR
-.XE \}
-.TH MBK 3 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-.SH NAME
-mbk \- Generic \fIlayout\fP ,\fInetlist\fP and \fIutility\fP data structures
-.so man1/alc_origin.1
-.SH DESCRIPTION
-\fBmbk\fP has several global variables that need to be known by the programmer.
-
-.SH SEE ALSO
-.BR mbk (1),
-.BR genlib (1).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/mbkalloc.3 b/alliance/share/man/man3/mbkalloc.3
deleted file mode 100644
index 989d174e..00000000
--- a/alliance/share/man/man3/mbkalloc.3
+++ /dev/null
@@ -1,76 +0,0 @@
-.\"   $Id: mbkalloc.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)mbkalloc.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-mbkalloc
-.XE
-.XS4 \n%
-.ti 0.2i
-mbkalloc
-.XE4 \}
-.TH MBKALLOC 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-mbkalloc \- mbk memory allocator
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-char \(**mbkalloc(bytes)
-unsigned int bytes;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIbytes\fP
-Number of memory bytes to be contiguously allocated
-.SH DESCRIPTION
-\fBmbkalloc\fP returns a block of \fIbytes\fP length, for any purpose.
-It is now a day just an encapsulation of the system \fBmalloc\fP function,
-but may evolve to a special allocator in the future. Its use is strongly
-encouraged.
-.TP 20
-Remark :
-a global variable, \fBlong mbkalloc_stat\fP, updates the number of allocated
-bytes, and may be accessed by anyone to see the amount of allocated memory.
-.SH RETURN VALUE
-\fBmbkalloc\fP returns a pointer to a \fIbytes\fP long block.
-.SH ERROR
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** mbkalloc impossible : not enough memory"
-.ft R
-.RS
-System break can't be moved anymore, no more memory can be retrieved from
-the system.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-char \(**dup_str(s);
-{
-char \(**t = (char \(**)mbkalloc(strlen(s) + (unsigned int)1);
-	strcpy(t, s);
-	return t;
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR mbkfree (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/mbkenv.3 b/alliance/share/man/man3/mbkenv.3
deleted file mode 100644
index 2b28694a..00000000
--- a/alliance/share/man/man3/mbkenv.3
+++ /dev/null
@@ -1,150 +0,0 @@
-.\"   $Id: mbkenv.3,v 1.2 2000/11/20 12:44:28 gregoire Exp $
-.\" @(#)mbkenv.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-mbkenv
-.XE
-.XS4 \n%
-.ti 0.2i
-mbkenv
-.XE4 \}
-.TH MBKENV 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-mbkenv \- set user preferences
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-void mbkenv();
-.ft R
-.fi
-.SH DESCRIPTION
-The \fBmbkenv\fP function set the user preferences through unix
-environment variables. if all the variables are not defined, default values
-are used.
-.LP the environment variables are :
-.TP 30
-\fBMBK_WORK_LIB\fP
-internally \fBchar \(**WORK_LIB\fP, sets the working directory for reading and
-writting, result of a \fBsavephfig\fP for example. Its value is \fB"."\fP by
-default.
-.TP
-\fBMBK_CATA_LIB\fP
-internally \fBchar \(**\(**CATA_LIB\fP, sets the working directories for reading only.
-This is a set of pathes, like the unix \fBPATH\fP variable.
-It is used in \fBloadlofig\fP for example. Its value is \fB"."\fP by default.
-.TP
-\fBMBK_CATAL_NAME\fP
-internally \fBchar \(**CATAL_NAME\fP, sets the name of the catalog file, needed
-to know where to stop a flatten, and so on. Set to \fB"CATAL"\fP by default.
-.TP
-\fBMBK_SEPAR\fP
-internally \fBchar SEPAR\fP, sets the character used for string concatenation.
-Used for example in \fBconcatname\fP.
-By default it is \fB"."\fP.
-.TP
-\fBMBK_VDD\fP
-internally \fBchar *VDD\fP, sets the name to be used as power level
-recognition pattern by the tools based upon mbk that needs to identify
-supplies.
-The default is \fB"vdd"\fP.
-.TP
-\fBMBK_VSS\fP
-internally \fBchar *VSS\fP, sets the name to be used as ground level
-recognition pattern by the tools based upon mbk that needs to identify
-supplies.
-The default is \fB"vss"\fP.
-.TP
-\fBMBK_TRACE_MODE\fP
-internally \fBchar TRACE_MODE\fP, output information in each mbk access
-function it enters.
-Used for debugging purposes.
-By default it is \fB'N'\fP.
-.TP
-\fBMBK_DEBUG_MODE\fP
-internally \fBchar DEBUG_MODE\fP, output information in function that
-makes a check on its values : mostly parsers for debug. It is very
-verbose, and mostly unusable. No mbk function take care of it.
-By default it is \fB'N'\fP.
-.TP
-\fBMBK_FAST_MODE\fP
-internally \fBchar FAST_MODE\fP. If set to \fB'Y'\fP, no consistency checked are
-performed on many mbk functions. This can work only on a program that is
-warrantied to be bugless, else undefined results would occur.
-By default it is \fB'N'\fP.
-.TP
-\fBMBK_IN_LO\fP
-internally \fBchar IN_LO[5]\fP. Defines the logical input format demanded
-by the user. See \fBMBK_IN_LO\fP(1) for a list of valid formats.
-By default its value is \fB"al"\fP.
-.TP
-\fBMBK_OUT_LO\fP
-internally \fBchar OUT_LO[5]\fP. Defines the logical input format demanded
-by the user. See \fBMBK_OUT_LO\fP(1) for a list of valid formats.
-By default its value is \fB"al"\fP.
-.TP
-\fBMBK_IN_PH\fP
-internally \fBchar IN_PH[5]\fP. Defines the logical input format demanded
-by the user. See \fBMBK_IN_PH\fP(1) for a list of valid formats.
-By default its value is \fB"ap"\fP.
-.TP
-\fBMBK_OUT_PH\fP
-internally \fBchar OUT_PH[5]\fP. Defines the logical input format demanded
-by the user. See \fBMBK_OUT_PH\fP(1) for a list of valid formats.
-By default its value is \fB"ap"\fP.
-.TP
-\fBMBK_SCALE_X\fP
-internally \fBlong SCALE_X\fP. Defines a scale factor for all coordinates, in
-order to be able to use files that works with half lambda rules for example.
-Parsers, drivers and genlib's macros use it extensivly.
-Its value is ten by default.
-.TP
-\fbMBK_IN_FILTER\fp
-internaly \fbIN_FILTER\fb. Filter string for reading compressed Alliance files.
-It has no value by default, means no filter is used.
-.TP
-\fbMBK_OUT_FILTER\fp
-internaly \fbOUT_FILTER\fb. Filter string for writing compressed Alliance files.
-It has no value by default, means no filter is used.
-.TP
-\fbMBK_FILTER_SFX\fp
-internaly \fbFILTER_SFX\fb. Extention of compressed files.
-It has no value by default, means no filter is used.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-#include "mlo315.h"
-lofig_list \(**load_fig(name)
-char \(**name;
-{
-	mbkenv(); /\(** make sure the good environnement is used \(**/
-	return getlofig(name, 'A');
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR genlib (1),
-.BR loadlofig (3),
-.BR loadphfig (3),
-.BR savelofig (3),
-.BR savephfig (3),
-.BR isvdd (3),
-.BR isvss (3),
-.BR concatname (3),
-.BR nameindex (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/mbkfopen.3 b/alliance/share/man/man3/mbkfopen.3
deleted file mode 100644
index 9ec158ba..00000000
--- a/alliance/share/man/man3/mbkfopen.3
+++ /dev/null
@@ -1,115 +0,0 @@
-.\"   $Id: mbkfopen.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)mbkfopen.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-mbkfopen
-.XE
-.XS4 \n%
-.ti 0.2i
-mbkfopen
-.XE4 \}
-.TH MBKFOPEN 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-mbkfopen \- open a file with several search pathes
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-FILE \(**mbkfopen(name, extension, mode)
-char \(**name, \(**extension, \(**mode;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIname\fP
-Name of the file to be opened
-.TP
-\fIextension\fP
-Extension to the file name
-.TP
-\fImodel\fP
-File opening mode
-.SH DESCRIPTION
-\fBmbkfopen\fP opens a file, searching it through the pathes given in the
-environment variables \fBMBK_CATA_LIB\fP(1) and \fBMBK_WORK_LIB\fP(1).
-Its main issue is to enable simple file access for any program that works
-with mbk path environment variables.
-.br
-The file to be opened is called \fIname.extension\fP, if extension is not
-\fBNULL\fP, else it is \fIname\fP. If \fIextension\fP is the empty string,
-\fB""\fP, then the file name will be \fIname.\fP\~.
-.br
-The legal values for \fImode\fP are
-.TP 20
-\fBREAD_TEXT\fP
-opens for reading
-.TP
-\fBWRITE_TEXT\fP
-discards and opens for writting
-.br
-since disk access should be a straight forward operation knowing mbk's needs.
-.LP
-The search algorithm depends on the value of \fImode\fP.
-If \fImode\fP is \fBWRITE_TEXT\fP, then the file is open for writting in
-\fBMBK_WORK_LIB\fP(1). If \fImode\fP is \fBREAD_TEXT\fP then the file is first
-searched through \fBMBK_WORK_LIB\fP(1), and if not found, through each directory
-specified in \fBMBK_CATA_LIB\fP(1), in the order of declaration under unix.
-No internal hash table is generated, in order to let the user choose its
-directory priority.
-As soon as the file is found, it is opened.
-There is no check for redundant files in the specified pathes, since it is
-neither illegal nor bad to have many files with the same names.
-.SH RETURN VALUE
-\fBmbkfopen\fP returns a pointer to the opened file.
-If the file read or write access are violated, or the file not found,
-a \fBNULL\fP pointer is returned.
-.SH ERROR
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** mbkfopen : unknown file opening mode \fImode\fP"
-.ft R
-.RS
-The \fImode\fP parameter is not one of the two legal values.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-#include "mph315.h"
-phfig_list \(**load_vti_ph(name)
-char \(**name;
-{
-FILE \(**file;
-	if ((file = mbkfopen(name, "cp", READ_TEXT)) == NULL) {
-		(void)fprintf(stderr, "Pfhhh, can't open \fIname.cp\fP\\n");
-		EXIT();
-	}
-	ph_parse(file);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR MBK_CATA_LIB (1),
-.BR MBK_WORK_LIB (1),
-.BR loadlofig (3),
-.BR loadphfig (3),
-.BR savelofig (3),
-.BR savephfig (3),
-.BR fopen (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/mbkfree.3 b/alliance/share/man/man3/mbkfree.3
deleted file mode 100644
index b51a2213..00000000
--- a/alliance/share/man/man3/mbkfree.3
+++ /dev/null
@@ -1,65 +0,0 @@
-.\"   $Id: mbkfree.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)mbkfree.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-mbkfree
-.XE
-.XS4 \n%
-.ti 0.2i
-mbkfree
-.XE4 \}
-.TH MBKFREE 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-mbkfree \- mbk memory allocator
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-void mbkfree(p)
-void \(**p;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIp\fP
-Pointer to be given back to the system
-.SH DESCRIPTION
-\fBmbkfree\fP frees a pointer.
-It is now a day just an encapsulation of the system \fBfree\fP function,
-but may evolve to a special allocator in the future. Its use is strongly
-encouraged.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-#include "mlo315.h"
-void free_con(pt)
-lofig_list \(**pt;
-{
-locon_list \(**c = pt\->LOCON, \(**next;
-	while (c) {
-		next = c\->NEXT;
-		mbkfree((void \(**)c);
-		c = next;
-	}
-	pt\->LOCON = NULL;
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR mbkalloc (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/mbkgetenv.3 b/alliance/share/man/man3/mbkgetenv.3
deleted file mode 100644
index f730dd03..00000000
--- a/alliance/share/man/man3/mbkgetenv.3
+++ /dev/null
@@ -1,30 +0,0 @@
-.TH MBKGETENV 3 "$Date: 2001/11/02 14:51:10 $" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-\fBmbkgetenv\fP \- get an environment variable
-
-.so man1/alc_origin.1
-
-.SH SYNOPSIS
-.nf
-.B #include "MUT_H"
-.sp
-.BI "char *mbkgetenv(const char *" name );
-.fi
-.SH DESCRIPTION
-The \fBmbkgetenv()\fP function searches the environment list for a string
-that matches the string pointed to by \fIname\fP.  The strings are of
-the form \fIname = value\fP.
-.SH "RETURN VALUE"
-The \fBmbkgetenv()\fP function returns a pointer to the value in the
-environment, or NULL if there is no match.
-If \fBMBK_TRACE_GETENV\fR is set to "yes", mbkgetenv() will print debug info to stdout before thre real getenv() syscall is done.
-
-.SH SEE ALSO
-.PP
-.BR mbk(1)
-.BR MBK_TRACE_GETENV(1)
-.BR getenv(3).
-
-.so man1/alc_bug_report.1
-
-
diff --git a/alliance/share/man/man3/mbkps.3 b/alliance/share/man/man3/mbkps.3
deleted file mode 100644
index 96f644b3..00000000
--- a/alliance/share/man/man3/mbkps.3
+++ /dev/null
@@ -1,77 +0,0 @@
-.\"   $Id: mbkps.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)mbkps.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-mbkps
-.XE
-.XS4 \n%
-.ti 0.2i
-mbkps
-.XE4 \}
-.TH MBKPS 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-mbkps \- mbk process state
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-void mbkps()
-.ft R
-.fi
-.SH DESCRIPTION
-\fBmbkps\fP does some functions calls and gathers informations about
-time and memory spend during a program run.
-encouraged.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-#include "mlo315.h"
-lofig_list \(**check_flat(pt)
-lofig_list \(**pt;
-{
-	mbkps();
-	pt = rflattenlofig(pt, YES, NO);
-	mbkps();
-	return pt;
-}
-.ft R
-.fi
-that would output something like :
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-mbk stats          : 1 call
-user     time      : 0 sec
-system   time      : 0 sec
-real     size      : 504 k
-mbkalloc peak size : 68 k
-mallinfo size      : 96 k
-mbk stats          : 2 call
-user     time      : 1 sec
-system   time      : 0 sec
-real     size      : 924 k
-mbkalloc peak size : 2560 k
-mallinfo size      : 512 k
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR getrusage (3),
-.BR mallinfo (3V).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/mbkrealloc.3 b/alliance/share/man/man3/mbkrealloc.3
deleted file mode 100644
index 14a9083a..00000000
--- a/alliance/share/man/man3/mbkrealloc.3
+++ /dev/null
@@ -1,83 +0,0 @@
-.\"   $Id: mbkrealloc.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)mbkrealloc.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-mbkrealloc
-.XE
-.XS4 \n%
-.ti 0.2i
-mbkrealloc
-.XE4 \}
-.TH MBKREALLOC 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-mbkrealloc \- mbk memory reallocator
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mutnnn.h"
-void \(**mbkrealloc(pt, bytes)
-void \(**pt;
-unsigned int bytes;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIpt\fP
-Pointer to an already allocated area, allocated using \fBmbkalloc\P
-.TP 20
-\fIbytes\fP
-Number of memory bytes to be contiguously allocated
-.SH DESCRIPTION
-\fBmbkrealloc\fP returns a block of \fIbytes\fP length, for any purpose.
-It increases or decreases the size of the area, and return a pointer to
-the new block.
-It is now a day only an encapsulation of the system \fBrealloc\fP function,
-but may evolve to a special allocator in the future. Its use is strongly
-encouraged.
-.TP 20
-Remark :
-a global variable, \fBlong mbkrealloc_stat\fP, updates the number of allocated
-bytes, and may be accessed by anyone to see the amount of allocated memory.
-.SH RETURN VALUE
-\fBmbkrealloc\fP returns a pointer to a \fIbytes\fP long block.
-.SH ERROR
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** mbkrealloc impossible : not enough memory"
-.ft R
-.RS
-System break can't be moved anymore, no more memory can be retrieved from
-the system.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mutnnn.h"
-char \(**concatstring(t, s);
-{
-	t = (char \(**)mbkrealloc(strlen(t) + strlen(s) + 1);
-	strcat(t, s);
-	return t;
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR mbkalloc (3),
-.BR mbkfree (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/mbksetautoackchld.3 b/alliance/share/man/man3/mbksetautoackchld.3
deleted file mode 100644
index 33efa2fe..00000000
--- a/alliance/share/man/man3/mbksetautoackchld.3
+++ /dev/null
@@ -1,48 +0,0 @@
-.\"   $Id: mbksetautoackchld.3,v 1.1 2000/11/20 12:44:28 gregoire Exp $
-.\" @(#)mbkalloc.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-mbkalloc
-.XE
-.XS4 \n%
-.ti 0.2i
-mbkalloc
-.XE4 \}
-.TH MBKSETAUTOACKCHLD 3 "November 20, 2000" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-mbksetautoackchld \- Tells Alliance to automatically handle terminaison of child process.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-void mbksetautoackchld( pid )
-int pid;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIpid\fP
-Process pid to automatically handle.
-.SH DESCRIPTION
-\fBmbksetautoackchld\fP provide a centralised way to catch terminated child
-process. Because some Alliance library can create a child process, and user
-application can do so, there must be a centralized way to get the exit status
-of process. If the programmer don't want to know the state of a child process,
-or if he don't want to know what is the terminaison code of such process, he
-must tells it to Alliance with this call. The programmer should never modify
-the handler of SIGCHLD.
-.SH RETURN VALUE
-\fBmbksetautoackchld\fP don't return value.
-.SH SEE ALSO
-.BR mbk (1),
-.BR mbkwaitpid (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/mbkunlink.3 b/alliance/share/man/man3/mbkunlink.3
deleted file mode 100644
index 40410626..00000000
--- a/alliance/share/man/man3/mbkunlink.3
+++ /dev/null
@@ -1,80 +0,0 @@
-.\"   $Id: mbkunlink.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)mbkunlink.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-mbkunlink
-.XE
-.XS4 \n%
-.ti 0.2i
-mbkunlink
-.XE4 \}
-.TH MBKUNLINK 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-mbkunlink \- delete a file in the \fBWORK_LIB\P.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-FILE \(**mbkunlink(name, extension)
-char \(**name, \(**extension;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIname\fP
-Name of the file to be deleted
-.TP
-\fIextension\fP
-Extension to the file name
-.SH DESCRIPTION
-\fBmbkunlink\fP deletes a file, searching it in the path specified with
-the environment variable \fBMBK_WORK_LIB\fP(1).
-Its main issue is to enable simple file deletion for any program that works
-with mbk path environment variables.
-.br
-The file to be erased is called \fIname.extension\fP, if extension is not
-\fBNULL\fP, else it is \fIname\fP. If \fIextension\fP is the empty string,
-\fB""\fP, then the file name will be \fIname.\fP\~.
-.br
-.SH RETURN VALUE
-\fBmbkunlink\fP returns :
-.TP 20
-\-\fB1\fP
-on failure, ie the file is not in the \fBMBK_WORK_LIB\fP path.
-.TP 20
-\fB0\fP
-on success.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-#include "mph315.h"
-void update_work_lib(name)
-char \(**name;
-{
-char *path;
-	if (incatalogdelete(name))
-		if (mbkunlink(name, "cp"))
-			fprintf(stdout, "The file %s.cp was not in the work lib\n",
-						name);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR MBK_WORK_LIB (1),
-.BR unlink (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/mbkwaitpid.3 b/alliance/share/man/man3/mbkwaitpid.3
deleted file mode 100644
index 797f6bd0..00000000
--- a/alliance/share/man/man3/mbkwaitpid.3
+++ /dev/null
@@ -1,53 +0,0 @@
-.\"   $Id: mbkwaitpid.3,v 1.1 2000/11/20 12:44:29 gregoire Exp $
-.\" @(#)mbkalloc.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-mbkalloc
-.XE
-.XS4 \n%
-.ti 0.2i
-mbkalloc
-.XE4 \}
-.TH MBKWAITPID 3 "November 20, 2000" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-mbkwaitpid \- wait for the end of a particular child process.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-int mbkwaitpid( pid, mode, status )
-int pid;
-int mode;
-int \(**status;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIpid\fP
-Process number to wait.
-.TP
-\fImode\fP
-If mode is set to 1, this function return only when the child process is
-terminated. Otherwise, function return immediatly.
-.TP
-\fIstatus\fP
-If not NULL, the exit status of terminated child process.
-.SH DESCRIPTION
-\fBmbkwaitpid\fP provides a centralized way to catch terminated child process.
-Because some Alliance library can create a child process, and user application
-can do so, there must be a centralized way to get the exit status of process.
-The programmer should never modify the handler for SIGCHLD.
-.SH RETURN VALUE
-\fBmbkwaitpid\fP return 1 if child process is terminated, and 0 if isn't (case 
-mode != 1 ).
-.SH SEE ALSO
-.BR mbk (1),
-.BR mbksetautoackchld().
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/minExpr.3 b/alliance/share/man/man3/minExpr.3
deleted file mode 100644
index 64804c4c..00000000
--- a/alliance/share/man/man3/minExpr.3
+++ /dev/null
@@ -1,58 +0,0 @@
-.\"   $Id: minExpr.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)minExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH MINEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBminExpr\fP \- returns the lowest argument of an operator expression.
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-chain_list *minExpr(expr,func)
-chain_list *expr;
-int (*func)();
-.fi
-.SH PARAMETERS
-.TP 20
-\fIexpr\fP
-operator expression
-.TP 20
-\fIfunc\fP
-integer function
-.SH DESCRIPTION
-\fBminExpr()\fP returns the lowest argument found by using the integer function \fIfunc()\fP. This function doesn't copy the returned argument.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr1,*expr2,*expr3; 
-expr1 = createExpr(OR);
-addQExpr(expr1,createAtom("a"));
-addQExpr(expr1,createAtom("b"));
-expr2 = createExpr(AND);
-addQExpr(expr2,createAtom("c"));
-addQExpr(expr2,createAtom("d"));
-addQExpr(expr1,expr2);
-displayExpr(expr1);
-expr3 = minExpr(expr1,numberAtomExpr);
-displayExpr(expr3);
-
-/* it will display
-(OR a b (AND c d))
-a
-*/
-freeExpr(expr1);	/* don't free expr3 or expr2 ! */
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR sortExpr (3),
-.BR maxExpr (3),
-.BR copyExpr (3),
-.BR substExpr (3),
-.BR substPhyExpr (3),
-.BR flatArityExpr (3),
-.BR flatPolarityExpr (3),
-.BR normExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/mlodebug.3 b/alliance/share/man/man3/mlodebug.3
deleted file mode 100644
index 7b275831..00000000
--- a/alliance/share/man/man3/mlodebug.3
+++ /dev/null
@@ -1,96 +0,0 @@
-.\"   $Id: mlodebug.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)mlodebug.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-mlodebug
-.XE
-.XS3 \n%
-.ti 0.2i
-mlodebug
-.XE3 \}
-.TH MLODEBUG 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL UTILITY FUNCTIONS"
-.SH NAME
-mlodebug \- logical data structure contents debug function
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo412.h"
-void mlodebug(headpointer, structurename)
-void \(**headpointer;
-char \(**structurename;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIheadpointer\fP
-Pointer to a structure to be displayed
-.TP 20
-\fIstructurename\fP
-Name of the structure to be explored
-.SH DESCRIPTION
-\fBmlodebug\fP allows a user interactive visualisation of the internal contents
-of the structural view of \fBmbk\fP.
-.br
-Through the use of a small, but convenient, textual user interface, a step
-by step exploration of each fields of the data structure is made available.
-However, if the structure is big, it may be painful to use.
-.br
-First of all, the contents of the expected struture is displayed, with
-its fields named as they appear in the appropriate header file.
-Then the user is prompted by a `>>' for an input.
-.br
-The input may be either a field name, or a predefined symbol.
-Field names are to be typed the way they are displayed.
-.br
-Predefined symbols are:
-.TP 20
-\fI_exit\fP
-that quit the current debugging session.
-.TP
-\fI_up\fP
-that comes back to the previous structure.
-.TP
-\fI_top\fP
-returns to the root of the function invocation.
-.TP
-\fI_stop\fP
-puts kind of a tag at the current position in the structure.
-It will be available later on to return to this position.
-.TP
-\fI_back\fP
-returns to the previous \fI_stop\fP position.
-.LP
-The debugger functions are easy to understand, so just try it!
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo412.h"
-void scan_n1_y()
-{
-	getlofig("n1_y", 'A');
-	mlodebug(HEAD_LOFIG, "lofig");
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR lofig (3),
-.BR locon (3),
-.BR loins (3),
-.BR losig (3),
-.BR lotrs (3),
-.BR mphdebug (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/modelmbkrds.3 b/alliance/share/man/man3/modelmbkrds.3
deleted file mode 100644
index 1a5dab43..00000000
--- a/alliance/share/man/man3/modelmbkrds.3
+++ /dev/null
@@ -1,93 +0,0 @@
-.\"   $Id: modelmbkrds.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)modelmbkrds.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-modelmbkrds
-.XE
-.XS0 \n%
-.ti 0.2i
-modelmbkrds
-.XE0 \}
-.TH MODELMBKRDS 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
- modelmbkrds \- gets all models of instances contained in a figure.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
- #include "rfmnnn.h"
-rdsfig_list \(**modelmbkrds( Figure, Lynx )
-   rdsfig_list \(**Figure;
-   char         Lynx;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIFigure\fP :
-The figure which has to be treated.
-.TP
-\fILynx\fP :
-Flag used for the segment conversion. If the parameter Lynx is set to 0 then this is the normal conversion mode. If the parameter Lynx is set to 1 then the rds structure generated permits to extract equipotentials rectangles.
-.SH DESCRIPTION
-The \fImodelmbkrds\fP function gets all models of instances of the RDS figure and chains them to the head of figures's list. For each newly created figure, the function is applied recursively. So the function flats all models contained in the figure named \'Figure\'.
-.SH RETURN VALUE
-Pointer to the head of the list of figures.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Rds202: rdsalloc error, can't continue !"
-.ft R
-.RS
-it's impossible to allocate the memory size desired
-.RE
-.PP
-Other errors can be generated by the getphfig function called in the modelmbkrds function (see getphfig).
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mphnnn.h"
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rfmnnn.h"
-        #include "rtlnnn.h"
-        main()
-          {
-            phfig_list  \(**MbkFigure;
-            rdsfig_list \(**RdsFigure;
-            rdsfig_list \(**RdsModelList;
-            rdsfig_list \(**ScanRdsFigure;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            MbkFigure       = getphfig("core",'A');
-            RdsFigure       = figmbkrds(MbkFigure,0,1);
-            RdsModelList    = \fBmodelmbkrds\fP (RdsFigure,1);
-            for ( ScanRdsFigure  = RdsModelList ;
-                  ScanRdsFigure != NULL     ;
-                  ScanRdsFigure  = ScanRdsFigure->NEXT )
-             {
-               viewrfmfig ( ScanRdsFigure );
-             }
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librfm,
-.BR viewrfmfig,
-.BR getphfig,
-.BR loadrdsparam
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/mphdebug.3 b/alliance/share/man/man3/mphdebug.3
deleted file mode 100644
index 87d6d979..00000000
--- a/alliance/share/man/man3/mphdebug.3
+++ /dev/null
@@ -1,95 +0,0 @@
-.\"   $Id: mphdebug.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)mphdebug.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-mphdebug
-.XE
-.XS1 \n%
-.ti 0.2i
-mphdebug
-.XE1 \}
-.TH MPHDEBUG 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL UTILITY FUNCTIONS"
-.SH NAME
-mphdebug \- physical data structure contents debug function
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph403.h"
-void mphdebug(headpointer, structurename)
-void \(**headpointer;
-char \(**structurename;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIheadpointer\fP
-Pointer to a structure to be displayed
-.TP 20
-\fIstructurename\fP
-Name of the structure to be explored
-.SH DESCRIPTION
-\fBmphdebug\fP allows a user interactive visualisation of the internal contents
-of the physical view of \fBmbk\fP.
-.br
-Through the use of a small, but convenient, textual user interface, a step
-by step exploration of each fields of the data structure is made available.
-However, if the structure is big, it may be painful to use.
-.br
-First of all, the contents of the expected struture is displayed, with
-its fields named as they appear in the appropriate header file.
-Then the user is prompted by a `>>' for an input.
-.br
-The input may be either a field name, or a predefined symbol.
-Field names are to be typed the way they are displayed.
-Predefined symbols are:
-.TP 20
-\fI_exit\fP
-that quit the current debugging session.
-.TP
-\fI_up\fP
-that comes back to the previous structure.
-.TP
-\fI_top\fP
-returns to the root of the function invocation.
-.TP
-\fI_stop\fP
-puts kind of a tag at the current position in the structure.
-It will be available later on to return to this position.
-.TP
-\fI_back\fP
-returns to the previous \fI_stop\fP position.
-.LP
-The debugger functions are easy to understand, so just try it!
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph403.h"
-void scan_na2_y()
-{
-	getphfig("na2_y", 'A');
-	mphdebug(HEAD_PHFIG, "phfig");
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR phfig (3),
-.BR phcon (3),
-.BR phins (3),
-.BR phvia (3),
-.BR phref (3),
-.BR mlodebug (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/namealloc.3 b/alliance/share/man/man3/namealloc.3
deleted file mode 100644
index 261a8017..00000000
--- a/alliance/share/man/man3/namealloc.3
+++ /dev/null
@@ -1,85 +0,0 @@
-.\"   $Id: namealloc.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)namealloc.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-namealloc
-.XE
-.XS4 \n%
-.ti 0.2i
-namealloc
-.XE4 \}
-.TH NAMEALLOC 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-namealloc \- hash table for strings
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mutnnn.h"
-char \(**namealloc(inputname)
-char \(**inputname;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIinputname\fP
-Pointer to a string of characters
-.SH DESCRIPTION
-The \fBnamealloc\fP function creates a dictionnary of names in mbk.
-It warranties equality on characters string if the pointers to these
-strings are equal, at \fBstrcmp\fP(3) meaning. This means also that there
-is a single memory address for a given string.
-.br
-The case of the letters do not matter. All names are changed to lower case
-before beeing introduced in the symbol table. This is needed because most
-of the file format do not check case.
-.br
-\fBnamealloc\fP is used by all mbk utility function using names, so its use
-should be needed only when directly filling or modifing the structure, or when
-having to compare an external string to mbk internal ones. This should speed
-up string comparisons.
-.br
-One shall never modify the contains of a string pointed to by a result of
-\fBnamealloc\fP, since all the field that points to this name would have
-there values modified, and that there is no chance that the new hash code
-will be the same as the old one, so pointer comparison would be
-meaningless. All string used by \fBnamealloc\fP are constants string, and
-therefore must be left alone.
-.SH RETURN VALUE
-\fBnamealloc\fP returns a string pointer.
-If the \fIinputname\fP is already in the hash table, then its internal pointer
-is returned, else a new entry is created, and then the new pointer returned.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mutnnn.h"
-#include "mlonnn.h"
-lofig_list \(**find_fig(name)
-char \(**name;
-{
-lofig_list \(**p;
-	name = namealloc(name);
-	for (p = HEAD_LOFIG; p; p = p\->NEXT)
-		if (p\->NAME == name) /\(** pointer equality \(**/
-			return p;
-	return NULL;
-}
-.ft R
-.fi
-.SH DIAGNOSTICS
-\fBnamealloc\fP can be used only after a call to \fBmbkenv\fP(3).
-.SH SEE ALSO
-.BR mbk (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/namefind.3 b/alliance/share/man/man3/namefind.3
deleted file mode 100644
index eb26de84..00000000
--- a/alliance/share/man/man3/namefind.3
+++ /dev/null
@@ -1,86 +0,0 @@
-.\"   $Id: namefind.3,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)namefind.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-namefind
-.XE
-.XS4 \n%
-.ti 0.2i
-namefind
-.XE4 \}
-.TH namefind 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-namefind \- hash table for strings
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mutnnn.h"
-char \(**namefind(inputname)
-char \(**inputname;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIinputname\fP
-Pointer to a string of characters
-.SH DESCRIPTION
-The \fBnamefind\fP function search the mbk dictionnary of names.
-If the string has already been inserted in the dictionnary, then a pointer
-to this string is return, else \fBnamefind\fP returns NULL.
-.br
-The case of the letters do not matter. All names are changed to lower case
-before beeing searched in the symbol table. This is needed because most
-of the file format do not check case.
-.br
-\fBnamefind\fP is used by all mbk utility function using names, so its use
-should be needed only when directly filling or modifing the structure, or when
-having to compare an external string to mbk internal ones. This should speed
-up string comparisons.
-.br
-One shall never modify the contains of a string pointed to by a result of
-\fBnamefind\fP, since all the field that points to this name would have
-there values modified, and that there is no chance that the new hash code
-will be the same as the old one, so pointer comparison would be
-meaningless. All string used by \fBnamefind\fP are constants string, and
-therefore must be left alone.
-.SH RETURN VALUE
-\fBnamefind\fP returns a string pointer if the \fIinputname\fP is already
-in the hash table, else NULL.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mutnnn.h"
-#include "mlonnn.h"
-lofig_list \(**find_fig(name)
-char \(**name;
-{
-lofig_list \(**p;
-	name = namefind(name);
-	if (name == NULL)
-	    return NULL;
-	for (p = HEAD_LOFIG; p; p = p\->NEXT)
-		if (p\->NAME == name) /\(** pointer equality \(**/
-			return p;
-	return NULL;
-}
-.ft R
-.fi
-.SH DIAGNOSTICS
-\fBnamefind\fP can be used only after a call to \fBmbkenv\fP(3).
-.SH SEE ALSO
-.BR mbk (1)
-.BR namealloc(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/nameindex.3 b/alliance/share/man/man3/nameindex.3
deleted file mode 100644
index 51d9ea34..00000000
--- a/alliance/share/man/man3/nameindex.3
+++ /dev/null
@@ -1,70 +0,0 @@
-.\"   $Id: nameindex.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)nameindex.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-nameindex
-.XE
-.XS4 \n%
-.ti 0.2i
-nameindex
-.XE4 \}
-.TH NAMEINDEX 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-nameindex \- concatenate a name and index with user separator
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-char \(**nameindex(s, i)
-char \(**s;
-long i;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIs\fP
-Pointer to a string
-.TP
-\fIt\fP
-Long integer
-.SH DESCRIPTION
-The \fBnameindex\fP function adds the separator defined by \fBMBK_SEPAR\fP(1),
-and then the string version of \fIi\fP at the end of string \fIs\fP.
-This is not like a \fBstrcat\fP(3) of the standard library, because \fIs\fP is
-not beeing modified.
-.br
-The string returned has already been put in the names dictionary by
-a call to \fBnamealloc\fP(3).
-.SH RETURN VALUE
-\fBnameindex\fP returns a pointer to a string in the name hash table.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-#include "mlo315.h"
-void a_sig_name(ptsig)
-losig_list \(**ptsig;
-{
-	return pt\->NAMECHAIN ? (char \(**)(pt\->NAMECHAIN\->DATA)
-				: nameindex("mbk_sig", pt\->INDEX);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR namealloc (3),
-.BR MBK_SEPAR (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/naturalstrcmp.3 b/alliance/share/man/man3/naturalstrcmp.3
deleted file mode 100644
index da5d49d0..00000000
--- a/alliance/share/man/man3/naturalstrcmp.3
+++ /dev/null
@@ -1,66 +0,0 @@
-.\"   $Id: naturalstrcmp.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)naturalstrcmp.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-naturalstrcmp
-.XE
-.XS4 \n%
-.ti 0.2i
-naturalstrcmp
-.XE4 \}
-.TH NATURALSTRCMP 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-naturalstrcmp \- compare string in alphabetical order for letters
-and numerical for digits.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-int naturalstrcmp(s, t)
-char \(**s, \(**t;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIs\fP
-Pointer to the first string to compare
-.TP
-\fIt\fP
-Pointer to the second string to compare
-.SH DESCRIPTION
-\fBnaturalstrcmp\fP is an alphanumerical comparison function that ensures
-\fBx12 > x2\fP for example.
-First, the alphabetical part of the string is compared, using \fBstrcmp\fP(3),
-then, if it has trailing numbers, they are compared using a numerical function.
-.SH RETURN VALUES
-\fBnaturalstrcmp\fP has the same return values than the standard library
-\fBstrcmp\fP(3) function.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-static int
-	connectorcmp(flc, slc)
-locon_list **flc, **slc;
-{
-	return naturalstrcmp((*slc)->NAME, (*flc)->NAME);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR strcmp (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/normExpr.3 b/alliance/share/man/man3/normExpr.3
deleted file mode 100644
index 5c53afb3..00000000
--- a/alliance/share/man/man3/normExpr.3
+++ /dev/null
@@ -1,48 +0,0 @@
-.\"   $Id: normExpr.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)normExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH NORMEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBnormExpr\fP \- normalizes an expression 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-void normExpr(expr)
-chain_list *expr;
-.fi
-.SH PARAMETER
-.TP 20
-\fIexpr\fP
-expression to normalize
-.SH DESCRIPTION
-\fBnormExpr()\fP sorts recursively the arguments of an expression by using predefined rules. The operator expressions are sorted by increasing operator number and arity of the first level. The atomic expressions are put at the end of the operator expressions.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr1; 
-
-/* let's suppose that expr1 = (AND a (XOR b c a) (NOT h) (AND e g) (OR b a)) */
-
-normExpr(expr1);
-displayExpr(expr1);
-
-/* it will display
-(AND (OR b a) (AND e g) (XOR b c a) (NOT h) a)
-*/
-freeExpr(expr1);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR sortExpr (3),
-.BR maxExpr (3),
-.BR minExpr (3),
-.BR copyExpr (3),
-.BR substExpr (3),
-.BR substPhyExpr (3),
-.BR flatArityExpr (3),
-.BR flatPolarityExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/notBdd.3 b/alliance/share/man/man3/notBdd.3
deleted file mode 100644
index ee671df2..00000000
--- a/alliance/share/man/man3/notBdd.3
+++ /dev/null
@@ -1,48 +0,0 @@
-.\"   $Id: notBdd.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)notBdd.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH NOTBDD 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBnotBdd\fP \- complements a BDD 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-pNode notBdd(pBdd)
-pNode pBdd;
-.fi
-.SH PARAMETER
-.TP 20
-\fIpBdd\fP
-BDD to complement
-.SH DESCRIPTION
-\fBnotBdd()\fP applies NOT operator to \fIpBdd\fP. 
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-pNode nodeA;
-
-initializeBdd(SMALL_BDD);
-nodeA = createNodeTermBdd(3);
-
-displayBdd(notBdd(nodeA),1);
-
-/* it will display 
-@nodeA   INDEX = 2   LOW = ONE   HIGH = ZERO
-*/
-	
-destroyBdd(1);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR applyBinBdd (3),
-.BR applyBdd (3),
-.BR constraintBdd (3),
-.BR composeBdd (3),
-.BR addListBdd (3),
-.BR displayBdd (3),
-.BR createNodeTermBdd (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/notExpr.3 b/alliance/share/man/man3/notExpr.3
deleted file mode 100644
index 5ed97826..00000000
--- a/alliance/share/man/man3/notExpr.3
+++ /dev/null
@@ -1,45 +0,0 @@
-.\"   $Id: notExpr.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)notExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH NOTEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBnotExpr\fP \- complements an expressio and eventually does a simplification
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-chain_list *notExpr(expr)
-chain_list *expr;
-.fi
-.SH PARAMETER
-.TP 20
-\fIexpr\fP
-expression to complement
-.SH DESCRIPTION
-\fBnotExpr()\fP complements \fIexpr\fP as follows : if \fIexpr\fP has a NOT as head operator, \fBnotExpr\fP removes it by simplification, if it doesn't, \fBnotExpr\fP adds an inverter before \fIexpr\fP. You mustn't free \fIexpr\fP because \fBnotExpr()\fP makes a physical modification on \fIexpr\fP so that it becomes undefined after this function call.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr1,*expr2; 
-expr1 = createExpr(NOT);
-addQExpr(expr1,createAtom("var1"));
-expr2 = notExpr(expr1);   	/* expr1 becomes undefined */
-displayExpr(expr2);
-
-/* it will display
-var1
-*/
-freeExpr(expr2);		/* don't free expr1 ! */
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR createAtom (3),
-.BR createExpr (3),
-.BR createBinExpr (3),
-.BR addQExpr (3),
-.BR addHExpr(3),
-.BR freeExpr(3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/num.3 b/alliance/share/man/man3/num.3
deleted file mode 100644
index 9a27ec3f..00000000
--- a/alliance/share/man/man3/num.3
+++ /dev/null
@@ -1,57 +0,0 @@
-.\"   $Id: num.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)num.l 0.0 90/22/08 UPMC; Author: Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-num
-.XE
-.XS4 \n%
-.ti 0.2i
-num
-.XE4 \}
-.TH NUM 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY STRUCTURE DEFINITIONS"
-.SH NAME
-num \- mbk list of number 
-.SH DESCRIPTION
-The \fBnum\fP is used to save numbers in a list.
-The use of this structure is strongly recommanded, when such a need occurs.
-.LP
-The declarations needed to work on \fBnum\fP are available in the header file
-\fI"/labo/include/mut315.h"\fP, where '\fI315\fP' is the actual mbk version.
-.LP
-The following C structure describes the list of number :
-.RS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.ta 3n 20n 30n
-typedef struct num {
-	struct num	\(**NEXT;
-	long	DATA;
-} num_list;
-.ft R
-.fi
-.RE
-.TP 20
-\fINEXT\fP
-Pointer to the next \fBnum\fP of the list.
-.TP
-\fIDATA\fP
-Value of the data.
-.TP
-Remark :
-a specialized memory allocator has been built in order to create and free
-\fBnum_list\fPs, so absolutly avoid to create or free them an other way than
-through the access functions.
-.SH SEE ALSO
-.BR mbk (1),
-.BR addnum (3),
-.BR freenum (3),
-.BR delnum (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/numberAtomExpr.3 b/alliance/share/man/man3/numberAtomExpr.3
deleted file mode 100644
index 51d387c5..00000000
--- a/alliance/share/man/man3/numberAtomExpr.3
+++ /dev/null
@@ -1,64 +0,0 @@
-.\"   $Id: numberAtomExpr.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)numberAtomExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH NUMBERATOMEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBnumberAtomExpr\fP \- returns the number of atoms in an expression
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-int numberAtomExpr(expr)
-chain_list *expr;
-.fi
-.SH PARAMETER
-.TP 20
-\fIexpr\fP
-expression
-.SH DESCRIPTION
-\fBnumberAtomExpr()\fP returns the number of atoms of \fIexpr\fP.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr1,*expr2;
-expr1 = createExpr(OR);
-addQExpr(expr1,createAtom("a"));
-addQExpr(expr1,createAtom("b"));
-expr2 = createExpr(OR);
-addQExpr(expr2,createAtom("c"));
-addQExpr(expr2,createAtom("d"));
-addQExpr(expr1,expr2);
-printf("%d",numberAtomExpr(expr1));
-/* it will display
-4
-*/
-freeExpr(expr1);		/* don't free expr2 ! */
-.fi
-.SH PROGRAM
-.nf
-int numberAtomExpr(expr)
-chain_list *expr;
-{
-if (ATOM(expr))
-   return(1)
-else
-   {
-   int cpt = 0;
-   while (expr = CDR(expr))
-      cpt = cpt + numberAtomExpr(CAR(expr));
-   return(cpt);
-   }
-} 
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR profExpr (3),
-.BR lengthExpr (3),
-.BR equalExpr (3),
-.BR equalVarExpr (3),
-.BR searchExpr (3),
-.BR searchOperExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/numberNodeAllBdd.3 b/alliance/share/man/man3/numberNodeAllBdd.3
deleted file mode 100644
index 37e86029..00000000
--- a/alliance/share/man/man3/numberNodeAllBdd.3
+++ /dev/null
@@ -1,51 +0,0 @@
-.\"   $Id: numberNodeAllBdd.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)numberNodeAllBdd.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH NUMBERNODEALLBDD 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBnumberNodeAllBdd\fP \- count the number of nodes used in the BDD system
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-int numberNodeAllBdd()
-.fi
-.SH DESCRIPTION
-\fBnumberNodeAllBdd()\fP count the number of the nodes that are used in the BDD system 
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-pNode nodeA,nodeB,nodeC;
-pNode res;
-chain_list *pt;
-
-initializeBdd(SMALL_BDD);
-nodeA = createNodeTermBdd(3);
-nodeB = createNodeTermBdd(3);
-nodeC = createNodeTermBdd(4);
-pt = NULL;
-pt = addListBdd(pt,nodeA);
-pt = addListBdd(pt,nodeB);
-pt = addListBdd(pt,nodeC);
-res = applyBdd(OR,pt);
-printf("number of nodes = %d",numberNodeAllBdd());
-
-/* it will display 
-number of nodes = 5
-*/
-	
-destroyBdd(1);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR addListBdd (3),
-.BR numberNodeBdd (3),
-.BR notBdd (3),
-.BR constraintBdd (3),
-.BR composeBdd (3),
-.BR displayBdd (3),
-.BR createNodeTermBdd (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/numberNodeBdd.3 b/alliance/share/man/man3/numberNodeBdd.3
deleted file mode 100644
index 3e405597..00000000
--- a/alliance/share/man/man3/numberNodeBdd.3
+++ /dev/null
@@ -1,56 +0,0 @@
-.\"   $Id: numberNodeBdd.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)numberNodeBdd.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH NUMBERNODEBDD 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBnumberNodeBdd\fP \- computes the number of nodes used in a BDD 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-int numberNodeBdd(pBdd)
-pNode pBdd;
-.fi
-.SH PARAMETER
-.TP 20
-\fIpBdd\fP
-BDD on wich the compute does
-.SH DESCRIPTION
-\fBnumberNodeBdd()\fP computes the number of reduced nodes that are used in \fIpBdd\fP. 
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-pNode nodeA,nodeB,nodeC;
-pNode res;
-chain_list *pt;
-
-initializeBdd(SMALL_BDD);
-nodeA = createNodeTermBdd(3);
-nodeB = createNodeTermBdd(3);
-nodeC = createNodeTermBdd(4);
-pt = NULL;
-pt = addListBdd(pt,nodeA);
-pt = addListBdd(pt,nodeB);
-pt = addListBdd(pt,nodeC);
-res = applyBdd(XOR,pt);
-printf("number of nodes = %d",numberNodeBdd(res));
-
-/* it will display 
-number of nodes = 5
-*/
-	
-destroyBdd(1);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR addListBdd (3),
-.BR numberNodeBdd (3),
-.BR notBdd (3),
-.BR constraintBdd (3),
-.BR composeBdd (3),
-.BR displayBdd (3),
-.BR createNodeTermBdd (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/numberNodeCct.3 b/alliance/share/man/man3/numberNodeCct.3
deleted file mode 100644
index 5072ba97..00000000
--- a/alliance/share/man/man3/numberNodeCct.3
+++ /dev/null
@@ -1,55 +0,0 @@
-.\"   $Id: numberNodeCct.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)numberNodeCct.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH NUMBERNODECCT 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBnumberNodeCct\fP \- counts the number of nodes used within a circuit
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-int numberNodeCct(pC)
-pCircuit pC;
-.fi
-.SH PARAMETER
-.TP 20
-\fIpC\fP
-circuit on which the count is done 
-.SH DESCRIPTION
-\fBnumberNodeCct()\fP counts the nodes that are used in \fIpC\fP.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-pCircuit pC;
-chain_list *expr;
-
-displayBdd(SMALL_BDD);
-pC = initializeCct("circuit 1",10,10);
-
-addInputCct(pC,"a");
-addInputCct(pC,"b");
-
-	/* let's suppose that expr = (OR a (AND (NOT a) b)) */
-
-addOuputCct(pC,"s1",one);
-addOuputCct(pC,"s2",ablToBddCct(pC,expr));
-
-printf("number of nodes of the circuit = %d",numberNodeCct(pC));
-
-/* it will display 
-number of nodes of the circuit = 2
-*/
-
-destroyCct(pC);
-destroyBdd(1);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR initializeCct (3),
-.BR resetCct (3),
-.BR cpOrderCct (3),
-.BR destroyCct (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/numberOccExpr.3 b/alliance/share/man/man3/numberOccExpr.3
deleted file mode 100644
index 72302b86..00000000
--- a/alliance/share/man/man3/numberOccExpr.3
+++ /dev/null
@@ -1,53 +0,0 @@
-.\"   $Id: numberOccExpr.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)numberOccExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH NUMBEROCCEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBnumberOccExpr\fP \- returns the number of time an atom appears in an expression. 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-int numberOccExpr(expr,name)
-chain_list *expr;
-char *name;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIexpr\fP
-expression
-.TP 20
-\fIname\fP
-name of the atom 
-.SH DESCRIPTION
-\fBnumberOccExpr()\fP returns the number of time \fIname\fP appears in \fIexpr\fP.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr1,*expr2;
-expr1 = createExpr(OR);
-addQExpr(expr1,createAtom("a"));
-addQExpr(expr1,createAtom("b"));
-expr2 = createExpr(OR);
-addQExpr(expr2,createAtom("c"));
-addQExpr(expr2,createAtom("a"));
-addQExpr(expr1,expr2);
-printf("%d",numberOccExpr(expr1));
-/* it will display
-2
-*/
-freeExpr(expr1);	/* don't free expr2 ! */
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR numberAtomExpr (3),
-.BR profExpr (3),
-.BR lengthExpr (3),
-.BR equalExpr (3),
-.BR equalVarExpr (3),
-.BR searchExpr (3),
-.BR searchOperExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/numberOperBinExpr.3 b/alliance/share/man/man3/numberOperBinExpr.3
deleted file mode 100644
index 4539be7c..00000000
--- a/alliance/share/man/man3/numberOperBinExpr.3
+++ /dev/null
@@ -1,47 +0,0 @@
-.\"   $Id: numberOperBinExpr.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)numberOperBinExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH NUMBEROPERBINEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBnumberOperBinExpr\fP \- returns the number of equivalent binary operators in an expression
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-int numberOperBinExpr(expr)
-chain_list *expr;
-.fi
-.SH PARAMETER
-.TP 20
-\fIexpr\fP
-expression
-.SH DESCRIPTION
-\fBnumberOperBinExpr()\fP returns the number of equivalent binary operators of \fIexpr\fP.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr1,*expr2;
-expr1 = charToExpr("(nor a (and b (and c (and d e))))");
-expr2 = charToExpr("(nor a (and b c d e))");
-printf("%d\n",numberOperBinExpr(expr1));
-printf("%d\n",numberOperBinExpr(expr2));
-/* it will display
-4
-4
-*/
-freeExpr(expr1);
-freeExpr(expr2);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR charToExpr (3),
-.BR profExpr (3),
-.BR lengthExpr (3),
-.BR equalExpr (3),
-.BR equalVarExpr (3),
-.BR searchExpr (3),
-.BR searchOperExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/operToChar.3 b/alliance/share/man/man3/operToChar.3
deleted file mode 100644
index a636c3ef..00000000
--- a/alliance/share/man/man3/operToChar.3
+++ /dev/null
@@ -1,39 +0,0 @@
-.\"   $Id: operToChar.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)operToChar.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH OPERTOCHAR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBoperToChar\fP \- converts an operator number into an operator string
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-char *operToChar(oper)
-short oper;
-.fi
-.SH PARAMETER
-.TP 20
-\fIoper\fP
-Operator number
-.SH DESCRIPTION
-\fBoperToChar()\fP returns the \fIchar *\fP operator associated to \fIoper\fP. if \fIoper\fP isn't an operator number, the function returns "???".
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-printf("%d = %s   ",OR,operToChar(OR));
-printf("%d = %s",AND,operToChar(AND));
-/* it will display
-0 = OR   1 = AND
-*/
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR charToOper (3),
-.BR displayExpr (3),
-.BR displayInfExpr (3),
-.BR exprToChar (3),
-.BR identExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/pacom.3 b/alliance/share/man/man3/pacom.3
deleted file mode 100644
index 7e889f04..00000000
--- a/alliance/share/man/man3/pacom.3
+++ /dev/null
@@ -1,36 +0,0 @@
-.\"   $Id: pacom.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)pacom.2 106 Sep 30 1996 UPMC; Pirouz BAZARGAN SABET
-.TH PACOM 3 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBpacom\fP - PAT data structure
-
-.SH DESCRIPTION
-.PP
-\fIpacom\fP is a data structure used in \fBPAT\fP to represent a comment read
-from the pattern description file to be reproduced in the result file at the
-same place. \fIpacom\fP has been designed to be used in a simply chained list.
-
-.PP
-A \fIpacom\fP structure is composed of the following fields.
-
-.TP 25
-\fI(char *) TEXT\fP
-the text of the comment
-.TP 25
-\fI(unsigned short) POSITION\fP
-the number of statements (input\-output declaration or pattern) to be printed
-before the comment line 
-.TP 25
-\fI(struct pacom *) NEXT\fP
-next pacom
-
-.SH SEE ALSO
-.PP
-libpat(3), pat(5)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/paevt.3 b/alliance/share/man/man3/paevt.3
deleted file mode 100644
index 05aac45c..00000000
--- a/alliance/share/man/man3/paevt.3
+++ /dev/null
@@ -1,50 +0,0 @@
-.\"   $Id: paevt.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)paevt.2 106 Sep 30 1996 UPMC; Pirouz BAZARGAN SABET
-.TH PAEVT 3 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBpaevt\fP - PAT data structure
-
-.SH DESCRIPTION
-.PP
-\fIpaevt\fP is a data structure used in \fBPAT\fP to represent an event on
-a one\-bit input\-output.
-
-.PP
-For an input, a modification of the value forced on the port between two
-consecutive patterns is considered as an event.
-
-.PP
-For an output, a modification of the value predicted for the output by the
-user between two consecutive patterns is considered as an event. In
-addition, whatever the last value of the output would be, it is considered
-as an event, when no value has been predicted by the user (see pat(5)).
-
-.PP
-\fIpaevt\fP has been designed to be used in a simply chained list.
-
-.PP
-A \fIpaevt\fP structure is composed of the following fields.
-
-.TP 20
-\fI(unsigned short) INDEX\fP
-the offset of the input\-output in the \fIpaiol\fP table
-.TP 20
-\fI(char) USERVAL\fP
-value to be forced on the input or predicted for the output
-.TP 20
-\fI(char) SIMVAL\fP
-value resulted from the simulation
-.TP 20
-\fI(struct paevt *) NEXT\fP
-next paevt
-
-.SH SEE ALSO
-.PP
-libpat(3), pat(5)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/pagrp.3 b/alliance/share/man/man3/pagrp.3
deleted file mode 100644
index 25a471aa..00000000
--- a/alliance/share/man/man3/pagrp.3
+++ /dev/null
@@ -1,42 +0,0 @@
-.\"   $Id: pagrp.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)pagrp.2 106 Sep 30 1996 UPMC; Pirouz BAZARGAN SABET
-.TH PAGRP 3 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBpagrp\fP - PAT data structure
-
-.SH DESCRIPTION
-.PP
-\fIpagrp\fP is a data structure used in \fBPAT\fP to represent an actual or
-virtual array. \fIpagrp\fP has been designed to be used in a simply chained
-list.
-
-.PP
-A \fIpagrp\fP structure is composed of the following fields.
-
-.TP 25
-\fI(char *) NAME\fP
-the array\'s name. This string is supposed been produced by \fBnamealloc()\fP
-.TP 25
-\fI(unsigned short) LENGTH\fP
-the array\'s range
-.TP 25
-\fI(unsigned short) FINDEX\fP
-the index of the first \fIpaiol\fP data structure corresponding to the first
-element of the array.
-.TP 25
-\fI(short) FLAG\fP
-set to 0 (zero) for an actual array and to 1 (one) for a virtual array.
-.TP 25
-\fI(struct pagrp *) NEXT\fP
-next pagrp
-
-.SH SEE ALSO
-.PP
-libpat(3), pat(5), namealloc(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/paini.3 b/alliance/share/man/man3/paini.3
deleted file mode 100644
index d650cb31..00000000
--- a/alliance/share/man/man3/paini.3
+++ /dev/null
@@ -1,37 +0,0 @@
-.\"   $Id: paini.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)paini.2 106 Sep 30 1996 UPMC; Pirouz BAZARGAN SABET
-.TH PAINI 3 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBpaini\fP - PAT data structure
-
-.SH DESCRIPTION
-.PP
-\fIpaini\fP is a data structure used in \fBPAT\fP to represent the
-initialization of a one\-bit register. \fIpaini\fP has been designed to be
-used in a simply chained list.
-
-.PP
-A \fIpaini\fP structure is composed of the following fields.
-
-.TP 20
-\fI(char *) NAME\fP
-the register\'s name. For an array\'s element, the name is the array\'s
-identifier added to the element\'s index separated by a \' \' (blank space).
-This string is supposed been produced by \fBnamealloc()\fP.
-.TP 20
-\fI(char) VALUE\fP
-value to be forced into the register
-.TP 20
-\fI(struct paini *) NEXT\fP
-next paini
-
-.SH SEE ALSO
-.PP
-libpat(3), pat(5), namealloc(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/paiol.3 b/alliance/share/man/man3/paiol.3
deleted file mode 100644
index 83d7da17..00000000
--- a/alliance/share/man/man3/paiol.3
+++ /dev/null
@@ -1,97 +0,0 @@
-.\"   $Id: paiol.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)paiol.2 106 Sep 30 1996 UPMC; Pirouz BAZARGAN SABET
-.TH PAIOL 3 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBpaiol\fP - PAT data structure
-
-.SH DESCRIPTION
-.PP
-\fIpaiol\fP is a data structure used in \fBPAT\fP to represent a one\-bit
-input\-output. \fIpagrp\fP has been designed to be used in a simply chained
-list. For more efficient accessibility a \fIpaiol\fP list must be organized
-as a table (to allow indexed addressing).
-
-.PP
-A \fIpaiol\fP structure is composed of the following fields.
-
-.TP 20
-\fI(char *) NAME\fP
-the input\-output\'s name. For an actual array\'s element, the name is the
-array\'s identifier added to the element\'s index seperated by a \' \'
-(blank space).  This string is supposed been produced by \fBnamealloc()\fP.
-.TP 20
-\fI(char) FORMAT\fP
-the read\-write format: \fBX\fP (hexa.), \fBO\fP (octal) and, \fBB\fP (binary
-scalar)
-.TP 20
-\fI(char) BLANK\fP
-number of blank column to be printed after the value
-.TP 20
-\fI(char) VALUE\fP
-not used
-.TP 20
-\fI(char) MODE\fP
-the input\-output\'s mode. This flag is first, setup by the compiler:
-.RS
-.TP 5
-I
-input\-output declared as in
-.TP 5
-O
-input\-output declared as out
-.TP
-T
-input\-output declared as inout
-.TP 5
-S
-input\-output declared as signal
-.TP 5
-R
-input\-output declared as register
-.TP 5
-then modified by the linker (Asimut simulation tool) :
-.TP 5
-I
-I \- port of mode in
-.TP 5
-B
-O \- simple port of mode inout
-.TP 5
-O
-O \- simple port of mode out
-.TP 5
-Z
-O \- bused port of mode out
-.TP 5
-T
-T \- bused port of mode inout
-.TP 5
-S
-S \- simple behavioural signal
-.TP 5
-W
-S \- simple structural signal
-.TP 5
-X
-S \- bused structural signal
-.TP 5
-U
-S \- bused behavioural signal
-.TP 5
-R
-R \- behavioural signal of kind register
-.RE
-.TP 20
-\fI(struct paiol *) NEXT\fP
-next paiol
-
-.SH SEE ALSO
-.PP
-libpat(3), pat(5), namealloc(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/papat.3 b/alliance/share/man/man3/papat.3
deleted file mode 100644
index 9ad31dc9..00000000
--- a/alliance/share/man/man3/papat.3
+++ /dev/null
@@ -1,54 +0,0 @@
-.\"   $Id: papat.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)papat.2 106 Sep 30 1996 UPMC; Pirouz BAZARGAN SABET
-.TH PAPAT 3 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBpapat\fP - PAT data structure
-
-.SH DESCRIPTION
-.PP
-\fIpapat\fP is a data structure used in \fBPAT\fP to represent a pattern.
-A pattern is a set of values either forced at the same time on the inputs or
-predicted for the outputs after the simulation step. \fIpapat\fP has been
-designed to be used in a simply chained list.
-
-.PP
-A \fIpapat\fP structure is composed of the following fields.
-
-.TP 20
-\fI(char *) LABEL\fP
-the label of the pattern (set to NULL if not present in the description file).
-This string is supposed been produced by \fBnamealloc()\fP
-.TP 20
-\fI(unsigned short) LINE\fP
-the location (line number) of the pattern in the pattern description file
-.TP 20
-\fI(char) BLANK\fP
-number of empty lines to be printed after the pattern (up to 15)
-.TP 20
-\fI(char) ACTFLAG\fP
-a flag representing the action associated with the pattern: I (initialize
-registers before processing the pattern) and, U (no action)
-.TP 20
-\fI(char) SIMFLAG\fP
-simulation flag : S (pattern already processed) and, U (pattern not yet
-processed)
-.TP
-\fI(struct paevt *) PAEVT\fP
-list of events
-.TP
-\fI(struct paini *) PAINI\fP
-list of initialized registers
-.TP 20
-\fI(struct papat *) NEXT\fP
-next papat
-
-.SH SEE ALSO
-.PP
-libpat(3), pat(5), paevt(3), paini(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/paseq.3 b/alliance/share/man/man3/paseq.3
deleted file mode 100644
index 975a34cc..00000000
--- a/alliance/share/man/man3/paseq.3
+++ /dev/null
@@ -1,82 +0,0 @@
-.\"   $Id: paseq.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)paseq.2 106 Sep 30 1996 UPMC; Pirouz BAZARGAN SABET
-.TH PASEQ 3 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBpaseq\fP - PAT data structure
-
-.SH DESCRIPTION
-.PP
-\fIpaseq\fP is a data structure used in \fBPAT\fP to represent a whole
-sequence of simulation patterns. \fIpaseq\fP has been designed to be used
-in a simply chained list.
-
-.PP
-A \fIpaseq\fP structure is composed of the following fields.
-
-.TP 25
-\fI(struct pagrp *) PAGRP\fP
-list of actual or virtual arraies
-.TP 25
-\fI(struct paiol *) PAIOL\fP
-list of inputs\-outputs
-.TP 25
-\fI(unsigned short) IOLNBR\fP
-number of inputs\-outputs
-.TP 25
-\fI(struct pacom *) DECCOM\fP
-list of comments (declaration part) to be printed in the result file
-.TP 25
-\fI(struct papat *) OLDPAT\fP
-old patterns' list
-.TP 25
-\fI(struct pacom *) OLDCOM\fP
-old comments
-.TP 25
-\fI(struct papat *) CURPAT\fP
-current patterns' list
-.TP 25
-\fI(unsigned int) PATNBR\fP
-number of patterns in the current patterns' list
-.TP 25
-\fI(struct pacom *) CURCOM\fP
-current comments
-.TP 25
-\fI(struct papat *) NXTPAT\fP
-next pattern
-.TP 25
-\fI(unsigned short) SUBSEQ\fP
-number of the present patterns' sub-sequence in partial loading mode
-.TP 25
-\fI(unsigned short) DRVSEQ\fP
-number of the last drived sub-sequence
-.TP 25
-\fI(unsigned int) LINENO\fP
-current line number in the pattern file
-.TP 25
-\fI(char) SAVFLG\fP
-is set to 'Y' if a save action is asked
-.TP 25
-\fI(char) ENDFLG\fP
-is set to 'Y' if the end of the file is reached
-.TP 25
-\fI(char) ERRFLG\fP
-contains a non zero value for a erroneous description
-.TP 25
-\fI(char) FLAGS\fP
-contains some flags on the type of the sequence of patterns. The
-\fBPAT_SEQ__IOLARRAY\fP flag is set when the input-output list is organized
-as an array
-.TP 25
-\fI(struct paseq *) NEXT\fP
-next paseq
-
-.SH SEE ALSO
-.PP
-libpat(3), pat(5), pacom(3), pagrp(3), paiol(3), papat(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/pat.3 b/alliance/share/man/man3/pat.3
deleted file mode 100644
index 0029c3f1..00000000
--- a/alliance/share/man/man3/pat.3
+++ /dev/null
@@ -1,143 +0,0 @@
-.\"   $Id: pat.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)pat.2 102  Sep  8 1992 UPMC; Pirouz BAZARGAN SABET
-.TH PAT 3 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBPAT\fP \- Generic pattern data structure
-
-.SH DESCRIPTION
-.PP
-\fBPAT\fP is a generic data structure supporting vlsi concepts.
-It allows representation of a sequence of simulation patterns in a data
-structure.
-
-.PP
-The goal of \fBPAT\fP is to define an ad hoc single data structure (object),
-with well known fixed meaning for each concept manipulated in pattern
-description. So any tools that needs to access simulation patterns can be
-build upon it, using these structures.
-
-.PP
-For each object (data structure), a set of functions has been defined in order
-to add, delete or access it. These functions are defined in a low\-level library
-\fIlibPat102.a\fP. Some other functions are higher level. They are defined in a
-high\-level library \fIlibPhl102.a\fP. There are also some parsers\-drivers.
-A parser reads a pattern description file in a given format and build up a
-complete \fBPAT\fP data base. A driver creates a text file in a given format
-from a \fBPAT\fP data base. A \fBpat\fP format parser\-driver is available
-in the \fIlibPpt102.a\fP library.
-
-.PP
-Pattern description envolves the following notions (for further details see
-pat(5)):
-
-.TP 20
-\fIinput\fP
-port controlled by the user
-.TP 20
-\fIoutput\fP
-signal or port observed by the user
-.TP 20
-\fIinitialization\fP
-forcing the value of a register
-.TP 20
-\fIpattern sequence\fP
-list of values to be forced on inputs or to be checked as the result of the
-simulation on outputs 
-
-.PP
-The input\-output list is represented by two data structures: \fIpagrp\fP
-contains informations relative to actual or virtual arraies and, \fIpaiol\fP
-represents a one\-bit input\-output. Both are simply chained lists. However,
-to make a more efficient access to \fIpaiol\fP structures, they are organized
-in a table. So, a \fIpaiol\fP can also be addressed using an offset.
-
-.PP
-Another group of data structures is used to represent a pattern. \fIpaini\fP
-contains values to be forced into registers before processing the pattern.
-An event (a modification of value) on an input\-output is given by a
-\fIpaevt\fP structure. A third structure, \fIpapat\fP gathers all information
-concerning a pattern (including initializations \- \fIpaini\fP \- and events \-
-\fIpaevt\fP).
-
-.PP
-A \fIpacom\fP is used to represent a comment.
-
-.PP
-Finally, all these structures can be accessed through a unique structure,
-\fIpaseq\fP, designed to represent a complete sequence of simulation patterns.
-
-.SH ORGANIZATION
-.PP
-In order to use \fBPAT\fP, concepts on use of libraries are needed. And, since
-these libraries are under development, the code is subject to change.
-
-.PP
-To enable work, a static version of each library is always present for the
-user. Libraries and header files are suffixed by a number (the library's
-version). The programmer can prefer to work with an earlier version of a
-library rather than the most recent one. However, it is recommended to adapt
-softwares to libraries as soon as possible in order to spotlight potential
-compatibility problems before old libraries are removed.
-
-.PP
-A \fImakefile\fP is necessary for all \fBPAT\fP applications.
-This is required because any soft must be easily recompilable, and knowing
-the needed libraries for a \fBPAT\fP based program is not an easy matter.
-It can't be achieved by an other way, so do use \fImakefile\fP.
-
-.PP
-In terms of software organization, \fBPAT\fP is splitted into two libraries
-for the basic functions, a header file for structures and variable declarations
-and, up to now, one parser\-driver library for \fBpat\fP format.
-
-.PP
-It is to be noticed that library's version number is incremented when, at least,
-one function composing the library has been modified. Therefore, \fBPAT\fP
-libraries may evolve independently form each other.
-
-.PP
-Here follows the list of the libraries and their contents.
-
-.TP 20
-libPat102.a:
-\fBpat_addpaseq,	pat_addpagrp,	pat_addpaiol,	\fP
-\fBpat_addpapat,	pat_addpaevt,	pat_addpaini,	\fP
-\fBpat_addpacom,	pat_frepaini,	pat_frepaiol,	\fP
-\fBpat_frepacom,	pat_frepapat,	pat_frepaevt,	\fP
-\fBpat_crtpaiol\fP
-
-.TP 20
-libPhl102.a:
-\fBpat_debug\fP
-
-.TP 20
-libPpt102.a:
-\fBpat_drvpat,	pat_prspat\fP
-
-.PP
-The libraries are organized in such a way that no cycle can appear through
-calls. It means that, if in a given library a function calls another function
-in another library, then none of the functions of this one does call any
-function that belongs to the first library.
-
-.SH EXAMPLE
-.PP
-In order to use \fBPAT\fP libraries, one needs something like that in its
-\fImakefile\fP:
-
-.RS
-HEADER = -I/labo/include
-.br
-LIB = -L/labo/lib -lPat102 -lPhl102 -lPpt102 -lMut306
-.RE
-
-.SH SEE ALSO
-.PP
-mbk (1), pat (5)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/pat_addpacom.3 b/alliance/share/man/man3/pat_addpacom.3
deleted file mode 100644
index eb9b3639..00000000
--- a/alliance/share/man/man3/pat_addpacom.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: pat_addpacom.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)pat_addpacom.2 106 Sep 30 1996 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funpacom.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/pat_addpaevt.3 b/alliance/share/man/man3/pat_addpaevt.3
deleted file mode 100644
index ae2c7adb..00000000
--- a/alliance/share/man/man3/pat_addpaevt.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: pat_addpaevt.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)pat_addpaevt.2 106 Sep 30 1996 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funpaevt.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/pat_addpagrp.3 b/alliance/share/man/man3/pat_addpagrp.3
deleted file mode 100644
index e8e6ee4b..00000000
--- a/alliance/share/man/man3/pat_addpagrp.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: pat_addpagrp.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)pat_addpagrp.2 106 Sep 30 1996 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funpagrp.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/pat_addpaini.3 b/alliance/share/man/man3/pat_addpaini.3
deleted file mode 100644
index d714aa1e..00000000
--- a/alliance/share/man/man3/pat_addpaini.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: pat_addpaini.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)pat_addpaini.2 106 Sep 30 1996 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funpaini.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/pat_addpaiol.3 b/alliance/share/man/man3/pat_addpaiol.3
deleted file mode 100644
index d4ea95d5..00000000
--- a/alliance/share/man/man3/pat_addpaiol.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: pat_addpaiol.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)pat_addpaiol.2 106 Sep 30 1996 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funpaiol.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/pat_addpapat.3 b/alliance/share/man/man3/pat_addpapat.3
deleted file mode 100644
index 5f804c1f..00000000
--- a/alliance/share/man/man3/pat_addpapat.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: pat_addpapat.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)pat_addpapat.2 106 Sep 30 1996 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funpapat.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/pat_addpaseq.3 b/alliance/share/man/man3/pat_addpaseq.3
deleted file mode 100644
index a0e5f748..00000000
--- a/alliance/share/man/man3/pat_addpaseq.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: pat_addpaseq.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)pat_addpaseq.2 106 Sep 30 1996 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funpaseq.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/pat_crtpaiol.3 b/alliance/share/man/man3/pat_crtpaiol.3
deleted file mode 100644
index aa3153f3..00000000
--- a/alliance/share/man/man3/pat_crtpaiol.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: pat_crtpaiol.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)pat_crtpaiol.2 106 Sep 30 1996 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funpaiol.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/pat_debug.3 b/alliance/share/man/man3/pat_debug.3
deleted file mode 100644
index 163e9f3f..00000000
--- a/alliance/share/man/man3/pat_debug.3
+++ /dev/null
@@ -1,119 +0,0 @@
-.\"   $Id: pat_debug.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)pat_debug.3 106 Sep 30 1996 UPMC ; Pirouz BAZARGAN SABET
-.TH PAT_DEBUG 3 "October 1, 1997" "ASIM/LIP6" "PHL functions"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBpat_debug\fP \- PAT structures displayer\-debugger
-
-.SH SYNOPSYS
-.PP
-.nf
-void pat_debug (pnt, type)
-void *pnt;
-char *type;
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIpnt\fP
-pointer of the structure to be displayed
-.TP 10
-\fItype\fP
-name of the structure to be displayed. \fItype\fP can be any of "paseq",
-"pagrp", "paiol", "papat", "paini", "pacom", "paevt"
-
-.SH DESCRIPTION
-.PP
-When called, \fBpat_debug()\fP first displaies the structure pointed by
-\fIpnt\fP then, prints the line:
-
-.RS
-COMMAND   >>
-.RE
-
-and waits for a command being entered by the user. If \fIpnt\fP is a NULL
-pointer or \fItype\fP doesn\'t represent a legal structure, \fBpat_debug()\fP
-exits without making any action.
-
-.PP
-To display the structure, \fBpat_debug()\fP prints a line per field. Fields
-containing immediate value (integer, character, string, ...) are displayed
-in the following form:
-
-.RS
-name_of_the_field  :  value_of_the_field
-.RE
-
-.PP
-Fields containing a pointer are marked by the symbol \fB\->\fP. If the pointer
-is a NULL pointer, the field is displayed as:
-
-.RS
--> name_of_the_field  :
-.RE
-
-In the other case, \fBpat_debug()\fP prints :
-
-.RS
--> name_of_the_field  :  AVAILABLE
-.RE
-
-.PP
-Two kinds of command can be introduced by the user.
-
-.PP
-A command can be the name of a field containing a pointer. The command is
-accepted only if the pointer is not a NULL pointer (field displayed as
-"AVAILABLE"). Reading such a command, \fBpat_debug()\fP first pushes the current
-structure on its stack then, displaies the structure pointed by the named field.
-
-.PP
-The second kind of commands are predefined commands :
-
-.RS
-.TP 10
-\fB_exit\fP
-to exit from the debugger
-.TP 10
-\fB_up\fP
-to return to the previous structure
-.TP 10
-\fB_stop\fP
-to put a stop mark on the current structure
-.TP 10
-\fB_top\fP
-to return to the first structure (pointed by \fIpnt\fP)
-.TP 10
-\fB_back\fP
-to return to the last structure marked with a stop mark
-.RE
-
-.PP
-In addition to these commands, the command \fB.\fP (dot) can be used to repete
-the last command.
-
-.SH EXAMPLE
-.PP
-.nf
-#include <pat106.h>
-struct paseq *paseq_pnt;
-
-pat_debug (paseq_pnt , "paseq");
-.fi
-
-.SH NOTES
-.PP
-Scanning structures, \fBpat_debug()\fP uses an internal stack. The message
-\fI"stack overflow"\fP is printed if too many structures have been pushed on
-the stack.
-
-.SH SEE ALSO
-.PP
-libpat(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/pat_frepacom.3 b/alliance/share/man/man3/pat_frepacom.3
deleted file mode 100644
index fb84cc22..00000000
--- a/alliance/share/man/man3/pat_frepacom.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: pat_frepacom.3,v 1.1 1999/05/31 17:30:23 alliance Exp $
-.\" @(#)pat_frepacom.2 106 Sep 30 1996 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funpacom.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/pat_frepaevt.3 b/alliance/share/man/man3/pat_frepaevt.3
deleted file mode 100644
index 1fbd8e40..00000000
--- a/alliance/share/man/man3/pat_frepaevt.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: pat_frepaevt.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)pat_frepaevt.2 106 Sep 30 1996 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funpaevt.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/pat_frepaini.3 b/alliance/share/man/man3/pat_frepaini.3
deleted file mode 100644
index 3ff05ecc..00000000
--- a/alliance/share/man/man3/pat_frepaini.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: pat_frepaini.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)pat_frepaini.2 106 Sep 30 1996 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funpaini.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/pat_frepaiol.3 b/alliance/share/man/man3/pat_frepaiol.3
deleted file mode 100644
index a4abc155..00000000
--- a/alliance/share/man/man3/pat_frepaiol.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: pat_frepaiol.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)pat_frepaiol.2 106 Sep 30 1996 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funpaiol.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/pat_frepapat.3 b/alliance/share/man/man3/pat_frepapat.3
deleted file mode 100644
index 93708383..00000000
--- a/alliance/share/man/man3/pat_frepapat.3
+++ /dev/null
@@ -1,6 +0,0 @@
-.\"   $Id: pat_frepapat.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)pat_frepapat.2 106 Sep 30 1996 UPMC ; Pirouz BAZARGAN SABET
-.so man3/funpapat.3
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/pat_lodpaseq.3 b/alliance/share/man/man3/pat_lodpaseq.3
deleted file mode 100644
index 0a32998b..00000000
--- a/alliance/share/man/man3/pat_lodpaseq.3
+++ /dev/null
@@ -1,90 +0,0 @@
-.\"   $Id: pat_lodpaseq.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)pat_lodpaseq.3 106 Sep 30 1996 UPMC ; Pirouz BAZARGAN SABET
-.TH PAT_LODPASEQ 3 "October 1, 1997" "ASIM/LIP6" "PPT functions"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBpat_lodpaseq\fP \- pattern file compiler
-
-.SH SYNOPSYS
-.PP
-.nf
-struct paseq *pat_lodpaseq (name, ptseq, maxpat)
-
-char         *name  ;
-struct paseq *ptseq ;
-unsigned int  maxpat;
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIname\fP
-pattern file's name
-.TP 10
-\fIptseq\fP
-pointer on a list of patterns' sequence
-.TP 10
-\fImaxpat\fP
-number of patterns to be loaded from the file
-
-.SH DESCRIPTION
-.PP
-\fBpat_lodpaseq\fP reads a sequence of patterns from a file named \fIname\fP.
-(according to MBK_CATA_LIB and VH_PATSFX environment variables). It loads at
-most \fImaxpat\fP number of patterns from the file and fills the structures.
-
-.PP
-For the first call, \fBpat_lodpaseq\fP first creates a new sequence (paseq
-structure) and puts it at the head of the \fIptseq\fP list. Then, it reads the
-declaration part and \fImaxpat\fP pattern from the description part. It
-returns the pointer of the new sequence.
-
-.PP
-For subsequence calls, \fBpat_lodpaseq\fP first, removes the old patterns
-from the paseq, then read a new series of patterns.
-
-.PP
-The pattern file remains openned until the last subsequence is loaded.
-
-.PP
-Each call of \fBpat_lodpaseq\fP increments the \fBSUBSEQ\fP field of the
-paseq structure. When the end of file is reached, the \fBENDFLG\fP of the
-paseq is set to 'Y'. The pattern file is closed before the function returns.
-
-.PP
-Setting \fImaxpat\fP to zero makes the whole file be read at once.
-
-.SH RETURN VALUES
-.PP
-\fBpat_lodpaseq\fP returns a NULL pointer if an error occurs when openning
-the pattern file.
-
-.PP
-If an error occurs at compil time \fBpat_lodpaseq\fP returns a paseq structure
-with the \fBERRFLG\fP set to a non-zero value.
-
-.SH EXAMPLE
-.PP
-.nf
-#include <pat106.h>
-#include <ppt106.h>
-
-struct paseq *paseq_pnt = NULL;
-
-while ((paseq_pnt != NULL) && (paseq_pnt->ENDFLG != 'Y'))
-  {
-  paseq_pnt = pat_lodpaseq ("my_sequence", paseq_pnt, 1000);
-  ...
-  }
-
-.fi
-
-.SH SEE ALSO
-.PP
-libpat(3), paseq(3), pat_addpaseq(3), pat_savpaseq(3), mbkfopen(3), mbkenv(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/pat_savpaseq.3 b/alliance/share/man/man3/pat_savpaseq.3
deleted file mode 100644
index 257f5d3f..00000000
--- a/alliance/share/man/man3/pat_savpaseq.3
+++ /dev/null
@@ -1,77 +0,0 @@
-.\"   $Id: pat_savpaseq.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)pat_savpaseq.3 106 Sep 30 1996 UPMC ; Pirouz BAZARGAN SABET
-.TH PAT_SAVPASEQ 3 "October 1, 1997" "ASIM/LIP6" "PPT functions"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBpat_savpaseq\fP \- save pattern structures in a pattern description file
-
-.SH SYNOPSYS
-.PP
-.nf
-int pat_savpaseq (name, ptseq, labelsiz)
-
-char         *name    ;
-struct paseq *ptseq   ;
-unsigned int  labelsiz;
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIname\fP
-pattern file's name
-.TP 10
-\fIptseq\fP
-pointer on a list of patterns' sequence
-.TP 10
-\fIlabelsiz\fP
-length of the longest pattern's label
-
-.SH DESCRIPTION
-.PP
-\fBpat_savpaseq\fP produces a pattern file named \fIname\fP from a paseq
-structure.
-
-.PP
-For the first call, \fBpat_savpaseq\fP opens a file (according to
-MBK_WORK_LIB and VH_PATSFX environment variables) named \fIname\fP. Then,
-the input\-output declarations is produced followed by the pattern
-description. When calling \fBpat_savpaseq\fP the input-output list (list
-of PAIOL) is supposed to be organized as an array. If the input-output list
-is not an array (flag PAT_SEQ__IOLARRAY not set) the functions makes an array
-from the input-output list and releases the list.
-
-.PP
-For subsequent calls, the file is completed with the newly processed patterns.
-The file remains openned util the last subsequence is written into the file.
-
-.SH RETURN VALUES
-.PP
-\fBpat_lodpaseq\fP returns a non-zero value if an error has been occured.
-
-.SH EXAMPLE
-.PP
-.nf
-#include <pat106.h>
-#include <ppt106.h>
-
-struct paseq *paseq_pnt = NULL;
-
-while ((paseq_pnt != NULL) && (paseq_pnt->ENDFLG != 'Y'))
-  {
-  paseq_pnt = pat_lodpaseq ("my_sequence", paseq_pnt, 1000);
-  ......
-  pat_savpaseq ("result", paseq_pnt, 10);
-  }
-
-.fi
-
-.SH SEE ALSO
-.PP
-libpat(3), paseq(3), pat_addpaseq(3), pat_lodpaseq(3), mbkfopen(3), mbkenv(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/phcon.3 b/alliance/share/man/man3/phcon.3
deleted file mode 100644
index be095801..00000000
--- a/alliance/share/man/man3/phcon.3
+++ /dev/null
@@ -1,154 +0,0 @@
-.\"   $Id: phcon.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)phcon.l 0.0 90/22/08 UPMC; Author: Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-phcon
-.XE
-.XS0 \n%
-.ti 0.2i
-phcon
-.XE0 \}
-.TH PHCON 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL STRUCTURE DEFINITIONS"
-.SH NAME
-phcon \- mbk physical connector
-.SH DESCRIPTION
-The \fBphcon\fP structure is used to describe a connector belonging to a
-symbolic layout model, see \fBphfig\fP(3) for details. A strong convention on
-the mbk data structure is that two connector internally wired have the same
-name, the 'logical' name.
-.LP
-The declarations needed to work on \fBphcon\fP are available in the header file
-\fI"/labo/include/mph402.h"\fP, where '\fI402\fP' is the actual mbk version.
-.LP
-The following C structure supports the description of the connector :
-.RS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.ta 3n 20n 30n
-typedef struct phcon {
-	struct phcon	\(**NEXT;
-	char	\(**NAME;
-	long	INDEX;
-	long	XCON, YCON;
-	long	WIDTH;
-	char	ORIENT;
-	char	LAYER;
-	struct ptype	\(**USER;
-} phcon_list;
-.ft R
-.fi
-.RE
-.TP 20
-\fINEXT\fP
-Pointer to the next connector of the model.
-.TP
-\fINAME\fP
-Name of the connector. A model may posseses more than one connector with a
-given name, if they are internally wired.
-.TP
-\fIINDEX\fP
-Index of the connector. Since a model may have many connectors with the same
-name, it is needed to be able to point out one of them. The index allows to
-distinguish every connector using a topological order. This field is filled
-by the \fBaddphcon\fP function, and shall not be modified otherwise.
-.TP
-\fIXCON, YCON\fP
-Connector coordinates. the point \fI(XCON, YCON)\fP must be placed on or
-inside of the \fIabutment box\fP of the model.
-.TP
-\fIORIENT\fP
-Caracter indicating the face of the model on the which the connector is placed.
-It may take four values :
-.RS
-.TP 20
-\fBNORTH\fP
-connector placed on top of cell
-.TP
-\fBSOUTH\fP
-connector placed on bottom of cell
-.TP
-\fBEAST\fP
-connector placed on right of cell
-.TP
-\fBWEST\fP
-connector placed on left of cell
-.RE
-.TP
-\fILAYER\fP
-Symbolic layer used for the connector. The legal values are :
-.RS
-.TP 20
-\fBNWELL\fP
-N bulk
-.TP
-\fBPWELL\fP
-P bulk
-.TP
-\fBNTIE\fP
-N implant in P bulk
-.TP
-\fBPTIE\fP
-P implant in N bulk
-.TP
-\fBNDIF\fP
-N diffusion
-.TP
-\fBPDIF\fP
-P diffusion
-.TP
-\fBNTRANS\fP
-N transistor
-.TP
-\fBPTRANS\fP
-P transistor
-.TP
-\fBPOLY\fP
-polysilicium
-.TP
-\fBALU1\fP
-first metal
-.TP
-\fBALU2\fP
-second metal
-.TP
-\fBALU3\fP
-third metal
-.TP
-\fBTPOLY\fP
-polysilicum through route
-.TP
-\fBTALU1\fP
-first metal through route
-.TP
-\fBTALU2\fP
-second metal through route
-.TP
-\fBTALU3\fP
-third metal through route
-.RE
-.TP
-\fIWIDTH\fP
-Width of the connector. The physical extension, concerning the width, of a
-connector is paralell to its face.
-.TP
-\fIUSER\fP
-Pointer to a ptype list, see \fBptype\fP for details, that is a general purpose
-pointer used to share informations on the connector.
-.SH SEE ALSO
-.BR mbk (1),
-.BR addphcon (3),
-.BR getphcon (3),
-.BR delphcon (3),
-.BR phfig (3),
-.BR phref (3),
-.BR locon (3),
-.BR ptype (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/phfig.3 b/alliance/share/man/man3/phfig.3
deleted file mode 100644
index a41df916..00000000
--- a/alliance/share/man/man3/phfig.3
+++ /dev/null
@@ -1,135 +0,0 @@
-.\"   $Id: phfig.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)phfig.l 0.0 90/22/08 UPMC; Author: Frederic Petrot
-.ta 1.5i 5.0i
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-phfig
-.XE
-.XS0 \n%
-.ti 0.2i
-phfig
-.XE0 \}
-.TH PHFIG 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL STRUCTURE DEFINITIONS"
-.SH NAME
-phfig \- mbk physical figure 
-.SH DESCRIPTION
-The \fBphfig\fP is used to describe a hierarchical level of a
-\fIsymbolic layout\fP
-and may contain any of the legal physical objects needed for a layout but
-a \fBphfig\fP.
-All coordinates are \fIsymbolic\fP and therefor put on a virtual grid in booth
-x and y directions.
-.LP
-The declarations needed to work on \fBphfig\fP are available in the header file
-\fI"/labo/include/mph402.h"\fP, where '\fI402\fP' is the actual mbk version.
-.LP
-The following C structure supports the description of the layout view :
-.RS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.ta 3n 20n 30n
-typedef struct phfig {
-	struct phfig	\(**NEXT;
-	struct chain	\(**MODELCHAIN;
-	struct phseg	\(**PHSEG;
-	struct phvia	\(**PHVIA;
-	struct phref	\(**PHREF;
-	struct phins	\(**PHINS;
-	struct phcon	\(**PHCON;
-	char	\(**NAME;
-	char	MODE;
-	long	XAB1, YAB1, XAB2, YAB2;
-	struct ptype	\(**USER;
-} phfig_list;
-.ft R
-.fi
-.RE
-.TP 20
-\fINEXT\fP
-Pointer to the next \fBphfig\fP present in ram.
-.TP
-\fINAME\fP
-Name of the figure. It identifies a figure (or \fImodel\fP), so it should
-be unique in order to warranty consistency of cells libraries. In order
-to ensure this consistency, the \fINAME\fP field must be filled with the
-disk file name while parsing, and must be used as file name for driving.
-.TP
-\fIPHINS\fP
-Pointer to the head of the list of instances being used for the model 
-description. See \fBphins\fP(3) for details.
-.TP
-\fIPHCON\fP
-Pointer to the head of the list of connectors (terminals) of the model.
-See \fBphcon\fP(3) for details.
-.TP
-\fIPHSEG\fP
-Pointer to the head of the list of segments (wires) of the model.
-See \fBphseg\fP(3) for details.
-.TP
-\fIPHVIA\fP
-Pointer to the head of the list of contacs and vias of the model.
-See \fBphvia\fP(3) for details.
-.TP
-\fIPHREF\fP
-Pointer to the head of the list of references of the model.
-See \fBphref\fP(3) for details.
-.TP
-\fIXAB1, YAB1, XAB2, YAB2\fP
-Coordinates of the bottom left corner of the \fIabutment box\fP of the
-figure. The \fIabutment box\fP of a model represents the external visibility of
-a figure and is what reference is made to when instanciating the model.
-One should well distinguish the \fIabutment box\fP from the \fIbounding box\fP,
-which is the smallest rectangle that includes all cell descriptors.
-The size and position of the \fIabutment box\fP is a designer concern, and
-cannot be computed.
-.TP
-\fIMODE\fP
-Caracter indicating the status of the figure in memory. This field can
-take two values :
-.RS
-.TP 10
-.B
-\'A\'
-all the cell is loaded in ram.
-.TP
-.B
-\'P\'
-only information concerning the model interface is present, that
-means connectors and the \fIabutment box\fP. All other lists are empty.
-.RE
-.TP
-\fIMODELCHAIN\fP
-Pointer to a chain list, see \fBchain\fP(3) for details, of names. These are the
-names of the models that are at least instanciated once in the figure.
-.TP
-\fIUSER\fP
-Pointer to a ptype list, see \fBptype\fP(3) for details, 
-that is a general purpose
-pointer used to share informations on the model.
-.TP
-Remark :
-mbk's physical view of a cell is releted to it's logical view by means 
-of connector names, that must be identical.
-.SH SEE ALSO
-.BR mbk (1),
-.BR addphfig (3),
-.BR getphfig (3),
-.BR delphfig (3),
-.BR loadphfig(3),
-.BR savephfig (3),
-.BR phins (3),
-.BR phvia (3),
-.BR phcon (3),
-.BR phseg (3),
-.BR phref (3),
-.BR ptype (3),
-.BR lofig (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/phins.3 b/alliance/share/man/man3/phins.3
deleted file mode 100644
index 02a7f9e7..00000000
--- a/alliance/share/man/man3/phins.3
+++ /dev/null
@@ -1,106 +0,0 @@
-.\"   $Id: phins.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)phins.l 0.0 90/22/08 UPMC; Author: Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-phins
-.XE
-.XS0 \n%
-.ti 0.2i
-phins
-.XE0 \}
-.TH PHINS 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL STRUCTURE DEFINITIONS"
-.SH NAME
-phins \- mbk physical instance 
-.SH DESCRIPTION
-The \fBphins\fP structure is used to describe a instance belonging to a
-symbolic layout model, see \fBphfig\fP(3) for details.
-.LP
-The declarations needed to work on \fBphins\fP are available in the header file
-\fI"/labo/include/mph402.h"\fP, where '\fI402\fP' is the actual mbk version.
-.LP
-The following C structure supports the description of the instance :
-.RS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.ta 3n 20n 30n
-typedef struct phins {
-	struct phins	\(**NEXT;
-	char	\(**INSNAME;
-	char	\(**FIGNAME;
-	long	XINS,YINS;
-	char	TRANSF;
-	struct ptype	\(**USER;
-} phins_list;
-.ft R
-.fi
-.RE
-.TP 20
-\fINEXT\fP
-Pointer to the next instance in the list.
-.TP
-\fIFIGNAME\fP
-Model of the instance. This gives the name of the figure that is currently
-beeing instanciated. The model may not be present in memory.
-.TP
-\fINAME\fP
-Name of the instance. The instance is identified by its name, so it should be
-unique at a given hierarchical level.
-.TP
-\fIXINS, YINS\fP
-Coordinates of the lower left corner of the instance, after possible
-geometrical operation.
-.TP
-\fITRANSF\fP
-Contains the geometrical operations that should be performed before placing
-the instance. Eight legal values are allowed :
-.RS
-.TP 20
-\fBNOSYM\fP
-no operation
-.TP
-\fBSYM_X\fP
-x becomes -x  
-.TP
-\fBSYM_Y\fP
-y becomes -y
-.TP
-\fBSYMXY\fP
-x becomes -x and y becomes -y
-.TP
-\fBROT_P\fP
-rotates 90 degrees counter clockwise
-.TP
-\fBROT_M\fP
-rotates 90 degrees clockwise
-.TP
-\fBSY_RP\fP
-x becomes -x then rotates 90 degrees counter clockwise
-.TP
-\fBSY_RM\fP
-x becomes -x then rotates 90 degrees clockwise
-.RE
-.TP
-\fIUSER\fP
-Pointer to a ptype list, see \fBptype\fP(3) for details, that is a general
-purpose pointer used to share informations on the instance.
-.TP
-Remark :
-the \fBphins\fP structure does not contain any information about
-the size of the instance. Neither the \fIabutment box\fP nor the connectors
-are available. The model must be loaded when such information is needed.
-.SH SEE ALSO
-.BR mbk (1),
-.BR addphins (3),
-.BR getphins (3),
-.BR delphins (3),
-.BR phfig (3),
-.BR ptype (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/phref.3 b/alliance/share/man/man3/phref.3
deleted file mode 100644
index b73d4ad9..00000000
--- a/alliance/share/man/man3/phref.3
+++ /dev/null
@@ -1,81 +0,0 @@
-.\"   $Id: phref.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)phref.l 0.0 90/22/08 UPMC; Author: Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-phref
-.XE
-.XS0 \n%
-.ti 0.2i
-phref
-.XE0 \}
-.TH PHREF 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL STRUCTURE DEFINITIONS"
-.SH NAME
-phref \- mbk physical reference 
-.SH DESCRIPTION
-The \fBphref\fP structure is used to describe a reference belonging to a
-symbolic layout model, see \fBphfig\fP(3) for details.
-A reference allows to name a point anywhere in a given model. It may then
-be seen as a name, and not anymore as a couple of coordinates.
-References are mostly used for cell programming and multi-access connector
-representation.
-.LP
-The declarations needed to work on \fBphref\fP are available in the header file
-\fI"/labo/include/mph402.h"\fP, where '\fI402\fP' is the actual mbk version.
-.LP
-The following C structure supports the description of the reference :
-.RS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.ta 3n 20n 30n
-typedef struct phref {
-	struct phref	\(**NEXT;
-	char	\(**FIGNAME;
-	char	\(**NAME;
-	long	XREF,YREF;
-	struct ptype	\(**USER;
-} phref_list;
-.ft R
-.fi
-.RE
-.TP 20
-\fINEXT\fP
-Pointer to the next reference in the list.
-.TP
-\fIFIGNAME\fP
-Kind of reference. Gives information about the possible uses of the object.
-Some \fIFIGNAME\fP are in use today :
-.RS
-.TP 20
-\fB"ref_con"\fP
-for multi-access connectors
-.TP
-\fB"ref_ref"\fP
-for all other uses
-.RE
-.TP
-\fINAME\fP
-Name of the reference. The refence is identified by its name, so it should be
-unique at a given hierarchical level.
-.TP
-\fIXREF, YREF\fP
-Coordinates of the point beeing referenced.
-.TP
-\fIUSER\fP
-Pointer to a ptype list, see \fBptype\fP(3) for details, that is a general
-purpose pointer used to share informations on the reference.
-.SH SEE ALSO
-.BR mbk (1),
-.BR addphref (3),
-.BR getphref (3),
-.BR delphref (3),
-.BR phfig (3),
-.BR ptype (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/phseg.3 b/alliance/share/man/man3/phseg.3
deleted file mode 100644
index 803831be..00000000
--- a/alliance/share/man/man3/phseg.3
+++ /dev/null
@@ -1,141 +0,0 @@
-.\"   $Id: phseg.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)phseg.l 0.0 90/22/08 UPMC; Author: Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-phseg
-.XE
-.XS0 \n%
-.ti 0.2i
-phseg
-.XE0 \}
-.TH PHSEG 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL STRUCTURE DEFINITIONS"
-.SH NAME
-phseg \- mbk physical segment 
-.SH DESCRIPTION
-The \fBphseg\fP structure is used to describe a segment belonging to a
-symbolic layout model, see \fBphfig\fP(3) for details.
-Transistors are segments of a particular layer.
-.LP
-The declarations needed to work on \fBphseg\fP are available in the header file
-\fI"/labo/include/mph402.h"\fP, where '\fI402\fP' is the actual mbk version.
-.LP
-The following C structure supports the description of the segment :
-.RS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.ta 3n 20n 30n
-typedef struct phseg {
-	struct phseg	\(**NEXT;
-	char	\(**NAME;
-	long	X1,Y1,X2,Y2;
-	long	WIDTH;
-	char	TYPE;
-	char	LAYER;
-	struct ptype	\(**USER;
-} phseg_list;
-.ft R
-.fi
-.RE
-.TP 20
-\fINEXT\fP
-Pointer to the next segment in the list.
-.TP
-\fINAME\fP
-Name of the segment. The name is not an identifier, and a name is present only
-if the designer used one for debug purposes.
-.TP
-\fIX1, Y1, X2, Y2\fP
-Coordinates of each end of the segment. Since it's a symbolic segment, one
-alway has either \fIX1 = X2\fP or \fIY1 = Y2\fP. Furthermore, by construction,
-it is warranty, if one accesses the data structure through the legal functions,
-that \fIX1 <= X2\fP and \fIY1 <= Y2\fP.
-.TP
-\fITYPE\fP
-This caracter can take four values :
-.RS
-.TP 20
-\fBLEFT\fP or \fBRIGHT\fR
-if \fIY1 = Y2\fP.
-The exact value is chosen by \fBaddphseg\fR, depending upon \fIX1\fR and 
-\fBX2\fP relations.
-.TP
-\fBUP\fP or \fBDOWN\fR
-if \fIX1 = X2\fP
-.RE
-.TP
-\fILAYER\fP
-Symbolic layer used for the segment. The legal values are :
-.RS
-.TP 20
-\fBNWELL\fP
-N bulk
-.TP
-\fBPWELL\fP
-P bulk
-.TP
-\fBNTIE\fP
-N implant in P bulk
-.TP
-\fBPTIE\fP
-P implant in N bulk
-.TP
-\fBNDIF\fP
-N diffusion
-.TP
-\fBPDIF\fP
-P diffusion
-.TP
-\fBNTRANS\fP
-N transistor
-.TP
-\fBPTRANS\fP
-P transistor
-.TP
-\fBPOLY\fP
-polysilicium
-.TP
-\fBALU1\fP
-first metal
-.TP
-\fBALU2\fP
-second metal
-.TP
-\fBALU3\fP
-third metal
-.TP
-\fBTPOLY\fP
-polysilicum through route
-.TP
-\fBTALU1\fP
-first metal through route
-.TP
-\fBTALU2\fP
-second metal through route
-.TP
-\fBTALU3\fP
-third metal through route
-.RE
-.TP
-\fIWIDTH\fP
-Width of the segment. The physical extension of a segment is perpendicular
-to its direction.
-.TP
-\fIUSER\fP
-Pointer to a ptype list, see \fBptype\fP for details, that is a general purpose
-pointer used to share informations on the segment.
-.SH SEE ALSO
-.BR mbk (1),
-.BR addphseg (3),
-.BR getphseg (3),
-.BR delphseg (3),
-.BR phfig (3),
-.BR ptype (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/phvia.3 b/alliance/share/man/man3/phvia.3
deleted file mode 100644
index b2ef0a0f..00000000
--- a/alliance/share/man/man3/phvia.3
+++ /dev/null
@@ -1,92 +0,0 @@
-.\"   $Id: phvia.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)phvia.l 0.0 90/22/08 UPMC; Author: Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-phvia
-.XE
-.XS0 \n%
-.ti 0.2i
-phvia
-.XE0 \}
-.TH PHVIA 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL STRUCTURE DEFINITIONS"
-.SH NAME
-phvia \- mbk physical contact 
-.SH DESCRIPTION
-The \fBphvia\fP structure is used to describe a via or contact belonging to a
-symbolic layout model, see \fBphfig\fP(3) for details.
-.LP
-The declarations needed to work on \fBphvia\fP are available in the header file
-\fI"/labo/include/mph402.h"\fP, where '\fI402\fP' is the actual mbk version.
-.LP
-The following C structure supports the description of the via :
-.RS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.ta 3n 20n 30n
-typedef struct phvia {
-	struct phvia	\(**NEXT;
-	char	TYPE;
-	long	XVIA,YVIA;
-	struct ptype	\(**USER;
-} phvia_list;
-.ft R
-.fi
-.RE
-.TP 20
-\fINEXT\fP
-Pointer to the next \fBphvia\fP in the list.
-.TP
-\fIXVIA, YVIA\fP
-Coordinates of the center of the via. Vias are macro generated patterns, 
-so only their center is a matter of concern.
-.TP
-\fITYPE\fP
-Via type. The legal types for via are
-.RS
-.TP 20
-\fBCONT_POLY\fP
-poly alu1  contact
-.TP
-\fBCONT_VIA\fP
-alu2 alu1  contact
-.TP
-\fBCONT_DIF_N\fP
-alu1 difn  contact
-.TP
-\fBCONT_DIF_P\fP
-alu1 difp  contact
-.TP
-\fBCONT_BODY_N\fP
-alu1 nwell contact
-.TP
-\fBCONT_BODY_P\fP
-alu1 pwell contact
-.TP
-\fBCONT_VIA2\fP
-alu2 alu3  contact
-.TP
-\fBC_X_N\fP
-L shaped N transistor corner filling
-.TP
-\fBC_X_P\fP
-L shaped P transistor corner filling
-.RE
-.TP
-\fIUSER\fP
-Pointer to a ptype list, see \fBptype\fP(3) for details, that is a general
-purpose pointer used to share informations on the via.
-.SH SEE ALSO
-.BR mbk (1),
-.BR addphvia (3),
-.BR delphvia (3),
-.BR phfig (3),
-.BR ptype (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/polarablexpr.3 b/alliance/share/man/man3/polarablexpr.3
deleted file mode 100644
index c91d00d4..00000000
--- a/alliance/share/man/man3/polarablexpr.3
+++ /dev/null
@@ -1,58 +0,0 @@
-.\"   $Id: polarablexpr.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)polarablexpr.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH POLARABLEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-polarablexpr \- moves inverters to the atomic level.
-
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-chain_list \(**polarablexpr( Expr, Polar )
-  chain_list \(**Expr;
-  int         Polar;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIExpr\fP
-Expression to modify.
-.TP
-\fIPolar\fP
-Expression polarity.
-.SH DESCRIPTION
-\fBpolarablexpr\fP modifies \fIExpr\fP by moving down the inverters to the atomic level.
-\fBpolarablexpr\fP applies the Morgan's laws. If \fIPolar\fP is equal to ABL_POLAR_NEGATIVE 
-the function returns the modified expression after having complemented it.
-The expression pointer \fIExpr\fP MUSTN'T be used after the call to this function.
-.SH RETURN VALUE
-\fBpolarablexpr\fP returns the modified expression.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-  chain_list \(**Expr1;
-  chain_list \(**Expr2;
-  Expr1 = createabloper( ABL_NOT );
-  Expr2 = createabloper( ABL_NOT );
-  addablhexpr( Expr1, createablatom( "a" ) );
-  addablhexpr( Expr2, Expr1 );
-  Expr1 = polarablexpr( Expr2, ABL_POLAR_POSITIVE );
-  /* displays  a */
-  viewablexpr( Expr1, ABL_VIEW_VHDL );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/polardupablexpr.3 b/alliance/share/man/man3/polardupablexpr.3
deleted file mode 100644
index a3f11548..00000000
--- a/alliance/share/man/man3/polardupablexpr.3
+++ /dev/null
@@ -1,57 +0,0 @@
-.\"   $Id: polardupablexpr.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)polardupablexpr.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH POLARDUPABLEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-polardupablexpr \- duplicates an expression and moves down the inverters.
-
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-chain_list \(**polardupablexpr( Expr, Polar )
-  chain_list \(**Expr;
-  int         Polar;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIExpr\fP
-Expression to modify.
-.TP
-\fIPolar\fP
-Expression polarity.
-.SH DESCRIPTION
-\fBpolardupablexpr\fP modifies \fIExpr\fP by moving down the inverters to the atomic level.
-\fBpolardupablexpr\fP applies the Morgan's laws. If \fIPolar\fP is equal to ABL_POLAR_NEGATIVE 
-the function returns the modified expression after having complemented it.
-.SH RETURN VALUE
-\fBpolardupablexpr\fP returns the modified expression.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-  chain_list \(**Expr1;
-  chain_list \(**Expr2;
-  Expr1 = createabloper( ABL_NOT );
-  Expr2 = createabloper( ABL_NOT );
-  addablhexpr( Expr1, createablatom( "a" ) );
-  addablhexpr( Expr2, Expr1 );
-  Expr1 = polardupablexpr( Expr2, ABL_POLAR_POSITIVE );
-  /* displays  a */
-  viewablexpr( Expr1, ABL_VIEW_VHDL );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/port.3 b/alliance/share/man/man3/port.3
deleted file mode 100644
index 75998c8d..00000000
--- a/alliance/share/man/man3/port.3
+++ /dev/null
@@ -1,70 +0,0 @@
-.\"   $Id: port.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)PORT.2 1.9 UPMC ; VUONG H.N.
-.TH PORT 3 "October 1, 1997" "ASIM/LIP6" "GENPAT functions"
-
-.SH NAME
-.PP
-\fBport\fP, GENPAT Package
-
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.PP
-.nf
-port("ident","ident", ... ,":nb_space","format","mode","size",0);
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIident\fP
-external connector's name, the number of character is limited to 20
-.TP 10
-\fInb_space\fP
-Specify the number of blank space between each group of value. 0,1,2,3,4,5,6,7,8,9 or nothing.
-.TP 10
-\fIformat\fP
-Specify the format that will be used to represent the value associated to
-the connectors. X for Hexadecimal, O for Octal and B for Binary.
-.TP 10
-\fImode\fP
-Specify the type of the connectors. I for Input, O for Output and T for Input/Output.
-.TP 10
-\fIsize\fP
-Specify the size of the bused connectors. ' ' : empty, (the chain is empty and the " are omitted) for the scalar
-connectors, nb1 for the numbered connectors, nb1 TO nb2 (nb1 < nb2, nb1 and
-nb2 integers), nb1 DOWNTO nb2 (nb2 < nb1). 
-
-.SH DESCRIPTION
-.PP
-Describes a set of connectors of the same format, size and mode.
-
-.SH EXAMPLE
-.PP
-.nf
-port("a","b","c","d",":2","X","O","3 DOWNTO 0",0);
-describes : a 3, a 2, a 1, a 0, b 3, b 2, b 1, b 0, c 3, c 2, c 1, c 0, d
-3, d 2, d 1, d 0.
-format : Hexadecimal.
-mode   : Output.
-each group is separated of the others with 2 blank spaces.
-
-port("toto",":","O","T","7 TO 11",0);
-describes : toto 7, toto 8, toto 9, toto 10, toto 11.
-format : Octal.
-mode   : Input/Output.
-the group is separated of the following with 0 blank space.
-
-port("ck",":2","B","i", 0);
-describes : ck.
-format : Binary.
-mode : Input.
-the port is separated of the following with 2 blank spaces.
-.fi
-
-.SH SEE ALSO
-.PP
-signal(3), register(3), genpat(1), pat(5)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/process.3 b/alliance/share/man/man3/process.3
deleted file mode 100644
index b2746196..00000000
--- a/alliance/share/man/man3/process.3
+++ /dev/null
@@ -1,52 +0,0 @@
-.\"   $Id: process.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)PROCESS.2 1.9 UPMC ; VUONG H.N.
-.TH PROCESS 3 "October 1, 1997" "ASIM/LIP6" "GENPAT functions"
-
-.SH NAME
-.PP
-\fBprocess\fP, GENPAT Package
-
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.PP
-.nf
-void process_name(parameter, ...)
-int/char/char * parameter;
-  {
-  ...
-  }
-.fi
-
-.SH DESCRIPTION
-.PP
-PROCESS permit to describe routine (C Language meaning), but with the subset of C language of GENPAT. They are always of type void (declared explicitely), they can't access to the variables of the parents and of the environment.
-
-.SH EXAMPLE
-.PP
-.nf
-void horloge_1(pat,ckm,cks)
-int pat;
-int ckm,cks;
-  {
-  affect(conv(pat),"ck",conv(ckm),0);
-  affect(conv(pat+1),"ck",conv(cks),0);
-  }
-
-void horloge_2(pat)
-int pat;
-  {
-  for(i=0;i<10;i=i+2)
-    {
-    affect(conv(pat+i),"ck","1",0);
-    affect(conv(pat+i+1),"ck",ZERO_B,0);
-    }
-  }
-
-.fi
-
-.SH SEE ALSO
-genpat(1), pat(5)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/profAOExpr.3 b/alliance/share/man/man3/profAOExpr.3
deleted file mode 100644
index 818e76ad..00000000
--- a/alliance/share/man/man3/profAOExpr.3
+++ /dev/null
@@ -1,50 +0,0 @@
-.\"   $Id: profAOExpr.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)profAOExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH PROFAOEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBprofAOExpr\fP \- returns the depth of an expression without taking the inverters into account. 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-int profAOExpr(expr)
-chain_list *expr;
-.fi
-.SH PARAMETER
-.TP 20
-\fIexpr\fP
-expression
-.SH DESCRIPTION
-\fBprofAOExpr()\fP returns the depth of \fIexpr\fP without taking the inverters into account.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr1,*expr2;
-expr1 = createExpr(OR);
-addQExpr(expr1, notExpr(createAtom("a")));
-addQExpr(expr1,createAtom("b"));
-expr2 = createAtom("c");
-printf("%d  %d\n",profAOExpr(expr2), profAOExpr(notExpr(expr2)));
-printf("%d  %d\n", profExpr(expr1), profAOExpr(expr1));
-/* it will display
-0  0
-2  1
-*/
-freeExpr(expr1);
-freeExpr(expr2);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR profExpr (3),
-.BR lengthExpr (3),
-.BR numberAtomExpr (3),
-.BR numberOccExpr (3),
-.BR equalExpr (3),
-.BR equalVarExpr (3),
-.BR searchExpr (3),
-.BR searchOperExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/profExpr.3 b/alliance/share/man/man3/profExpr.3
deleted file mode 100644
index 175f5146..00000000
--- a/alliance/share/man/man3/profExpr.3
+++ /dev/null
@@ -1,53 +0,0 @@
-.\"   $Id: profExpr.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)profExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH PROFEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBprofExpr\fP \- returns the depth of an expression. 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-int profExpr(expr)
-chain_list *expr;
-.fi
-.SH PARAMETER
-.TP 20
-\fIexpr\fP
-expression
-.SH DESCRIPTION
-\fBprofExpr()\fP returns the depth of \fIexpr\fP.  
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr1,*expr2;
-expr1 = createExpr(OR);
-addQExpr(expr1,createAtom("a"));
-addQExpr(expr1,createAtom("b"));
-expr2 = createAtom("a");
-printf("%d",profExpr(expr2));
-printf("%d",profExpr(expr1));
-expr = notExpr(expr1);
-printf("%d",profExpr(expr1));
-/* it will display
-0
-1
-2
-*/
-freeExpr(expr1);
-freeExpr(expr2);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR profAOExpr (3),
-.BR lengthExpr (3),
-.BR numberAtomExpr (3),
-.BR numberOccExpr (3),
-.BR equalExpr (3),
-.BR equalVarExpr (3),
-.BR searchExpr (3),
-.BR searchOperExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/proofCct.3 b/alliance/share/man/man3/proofCct.3
deleted file mode 100644
index 694a9872..00000000
--- a/alliance/share/man/man3/proofCct.3
+++ /dev/null
@@ -1,58 +0,0 @@
-.\"   $Id: proofCct.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)proofCct.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH PROOFCCT 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBproofCct\fP \- checks the equivalence of two circuits 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-int proofCct(pC1,pC2)
-pCircuit pC1;
-pCircuit pC2;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIpC1\fP
-first circuit to proof
-.TP 20
-\fIpC2\fP
-second circuit to proof
-.SH DESCRIPTION
-\fBproofCct()\fP checks the logical equivalence of \fIpC1\fP and \fIpC2\fP. In order to correctly compare the two description, the circuits must contains the same primary inputs, primary outputs and association order of the primary inputs with the indexes (You can use for example the \fBcpOrderCct()\fP function).
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-pCircuit pC1,pC2;
-chain_list *expr;
-
-initializeBdd(SMALL_BDD);
-pC1 = initializeCct("circuit 1",10,10);
-pC2= initializeCct("circuit 2",10,10);
-
-	/* let's suppose that pC1 and pC2 are set */
-
-proofCct(pC1,pC2)
-
-/* it will display 
-************* PROOF between circuit 1 & circuit 2 **********
-OUTPUT = s1 is equal
-OUTPUT = s2 is different
-s2 = (AND a b)
-s2 = (AND (OR a b) c)
-*********************** END OF PROOF ***********************
-*/
-
-destroyCct(pC1);
-destroyCct(pC2);
-destroyBdd(1);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR cpOrderCct (3),
-.BR gcNodeCct (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/ptype.3 b/alliance/share/man/man3/ptype.3
deleted file mode 100644
index e707c198..00000000
--- a/alliance/share/man/man3/ptype.3
+++ /dev/null
@@ -1,88 +0,0 @@
-.\"   $Id: ptype.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)ptype.l 0.0 90/22/08 UPMC; Author: Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-ptype
-.XE
-.XS4 \n%
-.ti 0.2i
-ptype
-.XE4 \}
-.TH PTYPE 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY STRUCTURE DEFINITIONS"
-.SH NAME
-ptype \- mbk list of typed pointers 
-.SH DESCRIPTION
-The \fBptype\fP is used to save typed pointers in a list.
-The use of this structure is strongly recommanded, when such a need occurs.
-It is the case in the \fIUSER\fP field of all mbk layout and netlist objects,
-where data specific to different proccessing may be accessed through this
-unique field. It is the charge of the user to give its pointers a type that
-will not collide with existing types. 
-.LP
-The declarations needed to work on \fBptype\fP are available in the header file
-\fI"/labo/include/mut315.h"\fP, where '\fI315\fP' is the actual mbk version.
-.LP
-The following C structure describes the list of typed pointers :
-.RS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.ta 3n 20n 30n
-typedef struct ptype {
-	struct ptype	\(**NEXT;
-	void	\(**DATA;
-	long	TYPE;
-} ptype_list;
-.ft R
-.fi
-.RE
-.TP 20
-\fINEXT\fP
-Pointer to the next \fBptype\fP of the list.
-.TP
-\fIDATA\fP
-Generic pointer that may point where the user wants to. 
-.TP
-\fITYPE\fP
-Identifier of the user of the pointed data. One shall not access someone else
-\fBptype\fP since it doesn't know what's in it. This means also that a
-\fBptype\fP user should free the space taken by its datas since it is the only
-one to know how to do it.
-.TP
-Remark 1:
-a specialized memory allocator has been built in order to create and free
-\fIptype_list\fPs, so absolutly avoid to create or free them an other way than
-through the access functions.
-.TP
-Remark 2:
-Now a day, three tools are known to use the \fIUSER\fP field of some
-mbk structures :
-.RS
-.TP 20
-\fBVTIPARSER\fP
-the parser of vti physical format '\fI.cp\fP' files uses the \fBphcon\fP(3)
-\fIUSER\fP field.
-.TP
-\fBLOFIGCHAIN\fP
-the \fBlofigchain\fP function constructs a dual representation of the netlist
-in the \fIUSER\fP field of the \fBlosig\fP(3) structure.
-.TP
-\fBPLACEABOX\fP
-Genlib's physical placement functions, in order to have model sizes in 
-instances.
-It uses the \fBphins\fP(3) \fIUSER\fP field.
-.RE
-.SH SEE ALSO
-.BR mbk (1),
-.BR addptype (3),
-.BR freeptype (3),
-.BR getptype (3),
-.BR delptype (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/rdsalloc.3 b/alliance/share/man/man3/rdsalloc.3
deleted file mode 100644
index 370282c5..00000000
--- a/alliance/share/man/man3/rdsalloc.3
+++ /dev/null
@@ -1,79 +0,0 @@
-.\"   $Id: rdsalloc.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)rdsalloc.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-rdsalloc
-.XE
-.XS0 \n%
-.ti 0.2i
-rdsalloc
-.XE0 \}
-.TH RDSALLOC 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
- rdsalloc \- memory allocation function
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
- #include "rdsnnn.h"
-   char \(**rdsalloc( Size, Heap )
-     unsigned int Size;
-     char         Heap;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fISize\fP
-memory size to allocate
-.TP
-\fIHeap\fP
-takes the values RDS_ALLOC_BLOCK or RDS_ALLOC_HEAP (two defined constants).
-.SH DESCRIPTION 
-The \fIrdsalloc\fP function can do memory allocation by block or by heap. If the user wants to allocate by block, he sets the parameter Heap to the constant RDS_ALLOC_BLOCK else, he wants to allocate by heap so the parameter Heap is set to RDS_ALLOC_HEAP.
-If rdsalloc is used with the constant RDS_ALLOC_BLOCK then rdsalloc is used as standard language C function malloc().
-If the user allocates by heap then :
-At the first allocation of the block of \fIsize\fP the parameter \'Size\', a heap of size multiple of the block Size is allocated. When another allocation of the same size is done then if the the heap isn't full then a pointer (of \fIsize\fP=\'Size\') is returned else a new heap is allocated and a pointer returned. Like this, the user does really one allocation (he has many pointers) to minimize fragmentation. Heap allocation is usefull if the user has to allocate many pointers of the same size (ex: rdsrec_list structure).
-.TP
-Note: Memory place allocated is set to NULL.
-.SH RETURN VALUE
-pointer to the allocated memory is returned.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Rds202: rdsalloc error, can't continue !" 
-.ft R
-.RS
-it's impossible to allocate the memory size desired.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-      #include "rdsnnn.h"
-	main()
-	 {
-	    rdsrec_list \(**Rectangle;
-	    rdsfig_list \(**Figure;
-	  Rectangle =
-          (rdsrec_list \(**) \fBrdsalloc\fP (sizeof(rdsrec_list \(**),RDS_ALLOC_HEAP);
-	  Figure    =
-          (rdsfig_list \(**) \fBrdsalloc\fP (sizeof(rdsfig_list \(**),RDS_ALLOC_BLOCK);
-	 }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librds,
-.BR rdsfree
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/rdsenv.3 b/alliance/share/man/man3/rdsenv.3
deleted file mode 100644
index c51a2178..00000000
--- a/alliance/share/man/man3/rdsenv.3
+++ /dev/null
@@ -1,73 +0,0 @@
-.\"   $Id: rdsenv.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)rdsenv.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-rdsenv
-.XE
-.XS0 \n%
-.ti 0.2i
-rdsenv
-.XE0 \}
-.TH RDSENV 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-rdsenv \- set user preference
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rtlnnn.h"
-void rdsenv()
-.ft R
-.fi
-.SH PARAMETER
-none
-.SH DESCRIPTION
-The \fIrdsenv\fP function sets the user preferences through  unix environment variables. if all the variables are not defined, default values are used.
-.TP
-\fIRDS_TECHNO_NAME\fP
-Path to the RDS technology file. The default value is "/labo/etc/cmos.rds".
-.TP
-\fIRDS_IN\fP
-Defines the physical input file format demanded by the user. The two possible formats are "cif" and "gds". By default, its value is set to "gds".
-.TP
-\fIRDS_OUT\fP
-Defines the physical output file format demanded by the user. The two possible formats are "cif" and "gds". By default, its value is set to "gds".
-.SH RETURN VALUE
-none
-.SH ERRORS
-nothing
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mutnnn.h"
-        #include "rtlnnn.h"
-        main()
-         {
-           rdsfig_list \(**RdsFigure;
-           mbkenv();
-           /\(** \(**/ \fBrdsenv\fP ();
-           loadrdsparam(); 
-           loadrdsfig(RdsFigure, "core", 'A');
-         }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librtl,
-.BR loadrdsfig,
-.BR saverdsfig,
-.BR RDS_IN,
-.BR RDS_OUT,
-.BR RDS_TECHNO_NAME
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/rdsfree.3 b/alliance/share/man/man3/rdsfree.3
deleted file mode 100644
index 0b3d5c4a..00000000
--- a/alliance/share/man/man3/rdsfree.3
+++ /dev/null
@@ -1,75 +0,0 @@
-.\"   $Id: rdsfree.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)rdsfree.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-rdsfree
-.XE
-.XS0 \n%
-.ti 0.2i
-rdsfree
-.XE0 \}
-.TH RDSFREE 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
- rdsfree \- free memory place
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
- #include "rdsnnn.h"
-  void  rdsfree( Pointer, Size )
-    char         \(**Pointer;
-    unsigned int  Size;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIPointer\fP
-pointer to the memory to free.
-.TP
-\fISize\fP
-Size of the memory to free.
-.SH DESCRIPTION
-The \fIrdsfree\fP function deletes memory of \fIsize\fP=\'Size\' allocated with rdsalloc function. If the parameter Size is set to ZERO (or RDS_ALLOC_BLOCK) then the memory is deleted by BLOCK else the memory is deleted by HEAP.
-.PP
-\fINote\fP : A memory allocated by BLOCK (resp. by HEAP) must be deleted by BLOCK (resp. by HEAP).
-.SH RETURN VALUE
-nothing
-.SH ERRORS
-none
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-          #include "rdsnnn.h"
-	    main()
-	     {
-	       rdsrec_list \(**Rectangle;
-	       rdsfig_list \(**Figure;
-               Figure    = allocrdsfig ();
-	       Rectangle = allocrdsrec ();
-	       Rectangle->X  = 20;
-	       Rectangle->Y  = 20;
-	       Rectangle->DX = 48;
-	       Rectangle->DY = 8;
-	       ...
-	       /\(** \(**/ \fBrdsfree\fP ( Rectangle, sizeof (rdsrec_list));
-               /\(** deletes a figure allocated by block \(**/
-               /\(** \(**/ \fBrdsfree\fP ( Figure , RDS_ALLOC_BLOCK);
-	     }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librds,
-.BR rdsalloc
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/refmbkrds.3 b/alliance/share/man/man3/refmbkrds.3
deleted file mode 100644
index d82878a2..00000000
--- a/alliance/share/man/man3/refmbkrds.3
+++ /dev/null
@@ -1,88 +0,0 @@
-.\"   $Id: refmbkrds.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)refmbkrds.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-refmbkrds
-.XE
-.XS0 \n%
-.ti 0.2i
-refmbkrds
-.XE0 \}
-.TH REFMBKRDS 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-refmbkrds \- adds to RDS figure a references from a MBK figure
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rfmnnn.h"
- rdsrec_list \(**refmbkrds( Figure, Reference )
-   rdsfig_list \(**Figure;
-   phref_list  \(**Reference;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIFigure\fP
-The RDS figure which has to receive the reference to convert.
-.TP
-\fIReference\fP
-MBK reference to convert to RDS rectangle.
-.SH DESCRIPTION
-The \fIrefmbkrds\fP function creates a RDS reference with a MBK reference. The reference is attached to the RDS figure in parameter of the refmbkrds function.
-.SH RETURN VALUE
-Pointer to the newly created RDS reference.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Rds202: rdsalloc error, can't continue !"
-.ft R
-.RS
-it's impossible to allocate the memory size desired
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mphnnn.h"
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rfmnnn.h"
-        #include "rtlnnn.h"
-        typedef struct UserStruct
-         {
-           char \(**STRING;
-           void \(**USER1;
-         } UserStruct;
-        main()
-          {
-            phfig_list  \(**MbkFigure;
-            rdsfig_list \(**RdsFigure;
-            rdsrec_list \(**Ref;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            RdsFigure = addrdsfig ("core",sizeof ( UserStruct ) );
-            MbkFigure->PHREF = addphref ( MbkFigure,"ref_con", "ref_1", 9, 15);
-            Ref = \fBrefmbkrds\fP (RdsFigure, MbkFigure->PHREF);
-            viewrdsrec ( Ref );
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librfm,
-.BR viewrfmref,
-.BR loadrdsparam
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/register.3 b/alliance/share/man/man3/register.3
deleted file mode 100644
index 8975933b..00000000
--- a/alliance/share/man/man3/register.3
+++ /dev/null
@@ -1,64 +0,0 @@
-.\"   $Id: register.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)REGISTER.2 1.9  UPMC ; VUONG H.N.
-.TH REGISTER 3 "October 1, 1997" "ASIM/LIP6" "GENPAT functions"
-
-.SH NAME
-.PP
-\fBregister\fP, GENPAT Package
-
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.PP
-.nf
-register("ident","ident", ... ,":nb_space","format","size",0);
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIident\fP
-Register's name, the number of character is limited to 20
-.TP 10
-\fInb_space\fP
-Specify the number of blank space between each group of value. 0,1,2,3,4,5,6,7,8,9 or nothing.
-.TP 10
-\fIformat\fP
-Specify the format that will be used to represent the value associated to
-the connectors. X for Hexadecimal, O for Octal and B for Binary.
-.TP 10
-\fIsize\fP
-Specify the size of the bused connectors. ' ' : empty, (the chain is empty and the " are omitted) for the scalar
-connectors, nb1 for the numbered connectors, nb1 TO nb2 (nb1 < nb2, nb1 and
-nb2 integers), nb1 DOWNTO nb2 (nb2 < nb1).
-
-.SH DESCRIPTION
-.PP
-Describes a set of internal registers of the same format and size.
-
-.SH EXAMPLE
-.PP
-.nf
-register("a","b","c","d",":2","X","3 DOWNTO 0",0);
-describes : a 3, a 2, a 1, a 0, b 3, b 2, b 1, b 0, c 3, c 2, c 1, c 0, d
-3, d 2, d 1, d 0.
-format : Hexadecimal.
-each group is separated of the others with 2 blank spaces.
-
-register("toto",":","O","7 TO 11",0);
-describes : toto 7, toto 8, toto 9, toto 10, toto 11.
-format : Octal.
-the group is separated of the following with 0 blank space.
-
-register("ck",":2","B",0);
-describes : ck.
-format : Binary.
-the register ck is separated of the following with 2 blank spaces.
-.fi
-
-.SH SEE ALSO
-.PP
-port(3), signal(3), genpat(1), pat(5)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/relprodbddnodeassoc.3 b/alliance/share/man/man3/relprodbddnodeassoc.3
deleted file mode 100644
index eb70a672..00000000
--- a/alliance/share/man/man3/relprodbddnodeassoc.3
+++ /dev/null
@@ -1,100 +0,0 @@
-.\"   $Id: relprodbddnodeassoc.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)relprodbddnodeassoc.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH RELPRODBDDNODEASSOC 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-relprodbddnodeassoc \- computes a relational product.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddnode \(**relprodbddnodeassoc( BddSystem, BddNode1, BddNode2, BddAssoc )
-  bddsystem \(**BddSystem;
-  bddnode   \(**BddNode1;
-  bddnode   \(**BddNode2;
-  bddassoc  \(**BddAssoc;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIBddNode1\fP
-The first \fBbdd\fP node.
-.TP
-\fIBddNode2\fP
-The second \fBbdd\fP node.
-.TP
-\fIBddAssoc\fP
-The variable association.
-.SH DESCRIPTION
-\fBrelprodbddnodeassoc\fP computes \fIBddNode1\fP AND \fIBddNode2\fP,
-and suppress the variables associated with something in the variable association
-\fIBddAssoc\fP, in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBrelprodbddnodeassoc\fP returns the computed \fBbdd\fP node.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"bad variable association xxx, error !"
-.ft R
-.RS
-The \fIBddAssoc\fP parameter must a valid variable association.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   bddnode    \(**BddNode1;
-   bddnode    \(**BddNode2;
-   bddnode    \(**BddVariable;
-   bddassoc   \(**Assoc;
-   chain_list \(**Expr;
-   bddvar         Variable;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   Expr = createablbinexpr( ABL_AND,
-                            createablatom( "i0" ),
-                            createablatom( "i1" ) );
-   BddNode1 = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   Expr = createablbinexpr( ABL_OR,
-                            createablatom( "i0" ),
-                            createablatom( "i1" ) );
-   BddNode2 = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   BddVariable = searchbddcircuitin( (bddcircuit \(**)0, "i0" );
-   Variable = getbddvarbyindex( (bddsystem \(**)0, BddVariable->INDEX );
-   Assoc = addbddassoc( (bddsystem \(**)0 );
-   addbddnodeassoc( (bddsystem \(**)0, Assoc, Variable, BddSystem->ONE );
-   BddNode = relprodbddnodeassoc( (bddsystem \(**)0, BddNode1, BddNode2, Assoc );
-   Expr = convertbddcircuitabl( BddCircuit, BddNode );
-   /* displays i1 */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddassoc( (bddsystem \(**)0 );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/reorderbddsystemdynamic.3 b/alliance/share/man/man3/reorderbddsystemdynamic.3
deleted file mode 100644
index ec694dea..00000000
--- a/alliance/share/man/man3/reorderbddsystemdynamic.3
+++ /dev/null
@@ -1,67 +0,0 @@
-.\"   $Id: reorderbddsystemdynamic.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)reorderbddsystemdynamic.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH REORDERBDDSYSTEMDYNAMIC 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-reorderbddsystemdynamic \- specifies the dynamic \fBbdd\fP reorder parameters.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-void reorderbddsystemdynamic( BddSystem, ReorderFunc, ReorderLow, ReorderRatio )
-  bddsystem \(**BddSystem;
-  void     (\(**ReorderFunc)();
-  long       ReorderLow;
-  long       ReorderRatio;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIReorderFunc\fP
-The dynamic reorder method.
-.TP
-\fIReorderLow\fP
-The minimum number of \fBbdd\fP nodes.
-.TP
-\fIReorderRatio\fP
-The reorder ratio in percent.
-.SH DESCRIPTION
-\fBreorderbddsystemdynamic\fP specifies to parameters for the dynamic reorder
-in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-If the number of \fBbdd\fP nodes is greater than \fIReorderLow\fP, then
-the dynamic reorder function \fIReorderFunc\fP is called. The new 
-reorder limit is computed as the product of the number of \fBbdd\fP nodes
-and the \fIReorderRatio\fP value plus 100.  If this limit is less than \fIReorderLow\fP
-then the new limit is fixed to \fIReorderLow\fP. If the function \fIReorderFunc\fP is a null 
-pointer, then the dynamic reorder process is skipped.
-.br
-.SH RETURN VALUE
-\fBreorderbddsystemdynamic\fP returns nothing.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem \(**BddSystem;
-   BddSystem = createbddsystem( 100, 1000, 100, 50000 );
-   reorderbddsystemdynamic( BddSystem, reorderbddsystemwindow, 1000, 50 );
-   ...
-   destroybddsystem( BddSystem );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/reorderbddsystemsimple.3 b/alliance/share/man/man3/reorderbddsystemsimple.3
deleted file mode 100644
index 814cc8e0..00000000
--- a/alliance/share/man/man3/reorderbddsystemsimple.3
+++ /dev/null
@@ -1,51 +0,0 @@
-.\"   $Id: reorderbddsystemsimple.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)reorderbddsystemsimple.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH REORDERBDDSYSTEMSIMPLE 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-reorderbddsystemsimple \- reorders the \fBbdd\fP nodes of a \fBbdd\fP system.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-void reorderbddsystemsimple( BddSystem )
-  bddsystem \(**BddSystem;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.SH DESCRIPTION
-\fBreorderbddsystemsimple\fP reorders all the \fBbdd\fP nodes of the
-\fBbdd\fP system \fIBddSystem\fP, in order to minimize the total
-number of \fBbdd\fP nodes.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBreorderbddsystemsimple\fP returns nothing.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem \(**BddSystem;
-   BddSystem = createbddsystem( 100, 1000, 100, 50000 );
-   ...
-   reorderbddsystemsimple( BddSystem );
-   ...
-   destroybddsystem( BddSystem );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/reorderbddsystemtop.3 b/alliance/share/man/man3/reorderbddsystemtop.3
deleted file mode 100644
index 6ec843a8..00000000
--- a/alliance/share/man/man3/reorderbddsystemtop.3
+++ /dev/null
@@ -1,51 +0,0 @@
-.\"   $Id: reorderbddsystemtop.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)reorderbddsystemtop.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH REORDERBDDSYSTEMTOP 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-reorderbddsystemtop \- reorders the \fBbdd\fP nodes of a \fBbdd\fP system.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-void reorderbddsystemtop( BddSystem )
-  bddsystem \(**BddSystem;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.SH DESCRIPTION
-\fBreorderbddsystemtop\fP reorders all the \fBbdd\fP nodes of the
-\fBbdd\fP system \fIBddSystem\fP, in order to minimize the total
-number of \fBbdd\fP nodes.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBreorderbddsystemtop\fP returns nothing.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem \(**BddSystem;
-   BddSystem = createbddsystem( 100, 1000, 100, 50000 );
-   ...
-   reorderbddsystemtop( BddSystem );
-   ...
-   destroybddsystem( BddSystem );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/reorderbddsystemwindow.3 b/alliance/share/man/man3/reorderbddsystemwindow.3
deleted file mode 100644
index 55d45ae5..00000000
--- a/alliance/share/man/man3/reorderbddsystemwindow.3
+++ /dev/null
@@ -1,51 +0,0 @@
-.\"   $Id: reorderbddsystemwindow.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)reorderbddsystemwindow.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH REORDERBDDSYSTEMWINDOW 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-reorderbddsystemwindow \- reorders the \fBbdd\fP nodes of a \fBbdd\fP system.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-void reorderbddsystemwindow( BddSystem )
-  bddsystem \(**BddSystem;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.SH DESCRIPTION
-\fBreorderbddsystemwindow\fP reorders all the \fBbdd\fP nodes of the
-\fBbdd\fP system \fIBddSystem\fP, in order to minimize the total
-number of \fBbdd\fP nodes.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBreorderbddsystemwindow\fP returns nothing.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem \(**BddSystem;
-   BddSystem = createbddsystem( 100, 1000, 100, 50000 );
-   ...
-   reorderbddsystemwindow( BddSystem );
-   ...
-   destroybddsystem( BddSystem );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/resetBdd.3 b/alliance/share/man/man3/resetBdd.3
deleted file mode 100644
index ebcca0d4..00000000
--- a/alliance/share/man/man3/resetBdd.3
+++ /dev/null
@@ -1,39 +0,0 @@
-.\"   $Id: resetBdd.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)resetBdd.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH RESETBDD 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBresetBdd\fP \- resets the BDDs system 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-void resetBdd()
-.fi
-.SH DESCRIPTION
-\fBresetBdd()\fP resets the BDDs system. This function can be only called after the \fBinitializeBdd()\fP function.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-
-initializeBdd(LARGE_BDD);
-
-/* first application using BDD ... */
-
-resetBdd();
-
-/* second application using BDD ... */
-
-destroyBdd(1);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR destroyBdd (3),
-.BR gcNodeBdd (3),
-.BR markAllBdd (3),
-.BR numberNodeAllBdd (3),
-.BR resetBdd (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/resetCct.3 b/alliance/share/man/man3/resetCct.3
deleted file mode 100644
index a7406785..00000000
--- a/alliance/share/man/man3/resetCct.3
+++ /dev/null
@@ -1,43 +0,0 @@
-.\"   $Id: resetCct.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)resetCct.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH RESETCCT 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBresetCct\fP \- resets a circuit 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-void resetCct(pC)
-.fi
-.SH PARAMETER
-.TP 20
-\fIpC\fP
-circuit to reset
-.SH DESCRIPTION
-\fBresetCct()\fP resets a circuit.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-pCircuit pC;
-
-initializeBdd(SMALL_BDD);
-pC = initializeCct("circuit 1",10,10);
-
-	/* first application using pC */
-
-resetCct(pC);
-
-	/* second application using pC */
-
-destroyCct(pC);
-destroyBdd(1);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR initializeCct (3),
-.BR destroyCct (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/resetauth2table.3 b/alliance/share/man/man3/resetauth2table.3
deleted file mode 100644
index fe96750a..00000000
--- a/alliance/share/man/man3/resetauth2table.3
+++ /dev/null
@@ -1,53 +0,0 @@
-.\"   $Id: resetauth2table.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)resetauth2table.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH RESETAUTH2TABLE 3 "October 1, 1997" "ASIM/LIP6" "AUT FUNCTIONS"
-.SH NAME
-resetauth2table \- resets an hash table with two keys.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-void resetauth2table( HashTable )
-  auth2table \(**HashTable;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIHashTable\fP
-Pointer to the hash table to reset.
-.SH DESCRIPTION
-\fBresetauth2table\fP sets the hash table contents to zero.
-.br
-.SH RETURN VALUE
-\fBresetauth2table\fP returns nothing.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-   auth2table \(**HashTable;
-   HashTable = createauth2table( 1000 );
-   ...
-   resetauth2table( HashTable );
-   ...
-   destroyauth2table( HashTable );
-.ft R
-.fi
-.SH SEE ALSO
-.BR aut (1)
-.BR createauth2table(3),
-.BR destroyauth2table(3),
-.BR addauth2elem(3),
-.BR searchauth2elem(3),
-.BR delauth2elem(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/resetauthtable.3 b/alliance/share/man/man3/resetauthtable.3
deleted file mode 100644
index 333a0501..00000000
--- a/alliance/share/man/man3/resetauthtable.3
+++ /dev/null
@@ -1,53 +0,0 @@
-.\"   $Id: resetauthtable.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)resetauthtable.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH RESETAUTHTABLE 3 "October 1, 1997" "ASIM/LIP6" "AUT FUNCTIONS"
-.SH NAME
-resetauthtable \- resets a simple hash table.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-void resetauthtable( HashTable )
-  authtable \(**HashTable;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIHashTable\fP
-Pointer to the hash table to reset.
-.SH DESCRIPTION
-\fBresetauthtable\fP sets the hash table contents to zero.
-.br
-.SH RETURN VALUE
-\fBresetauthtable\fP returns nothing.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-   authtable \(**HashTable;
-   HashTable = createauthtable( 1000 );
-   ...
-   resetauthtable( HashTable );
-   ...
-   destroyauthtable( HashTable );
-.ft R
-.fi
-.SH SEE ALSO
-.BR aut (1)
-.BR createauthtable(3),
-.BR destroyauthtable(3),
-.BR addauthelem(3),
-.BR searchauthelem(3),
-.BR delauthelem(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/resetbddcircuit.3 b/alliance/share/man/man3/resetbddcircuit.3
deleted file mode 100644
index 848281e7..00000000
--- a/alliance/share/man/man3/resetbddcircuit.3
+++ /dev/null
@@ -1,53 +0,0 @@
-.\"   $Id: resetbddcircuit.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)resetbddcircuit.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH RESETBDDCIRCUIT 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-resetbddcircuit \- resets a \fBbdd\fP circuit.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-void resetbddcircuit( BddCircuit )
-  bddcircuit \(**BddCircuit;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddCircuit\fP
-The \fBbdd\fP circuit to reset.
-.SH DESCRIPTION
-\fBresetbddcircuit\fP resets the \fBbdd\fP circuit \fIBddCircuit\fP.
-If a null pointer is given, the default \fBbdd\fP circuit is used.
-.br
-.SH RETURN VALUE
-\fBresetbddcircuit\fP returns nothing.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   ...
-   resetbddcircuit( (bddcircuit \(**)0 );
-   ...
-   destroybddsystem( (bddsystem \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1),
-.BR createbddcircuit(3),
-.BR destroybddcircuit(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/resetbddsystem.3 b/alliance/share/man/man3/resetbddsystem.3
deleted file mode 100644
index de37f6b4..00000000
--- a/alliance/share/man/man3/resetbddsystem.3
+++ /dev/null
@@ -1,50 +0,0 @@
-.\"   $Id: resetbddsystem.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)resetbddsystem.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH RESETBDDSYSTEM 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-resetbddsystem \- resets a \fBbdd\fP system.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-void resetbddsystem( BddSystem )
-  bddsystem \(**BddSystem;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system to reset.
-.SH DESCRIPTION
-\fBresetbddsystem\fP resets the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBresetbddsystem\fP returns nothing.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem \(**BddSystem;
-   BddSystem = createbddsystem( 100, 1000, 100, 50000 );
-   ...
-   resetbddsystem( (bddsystem \(**)0 );
-   destroybddsystem( BddSystem );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-.BR createbddsytem(3),
-.BR destroybddsytem(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/restorealldir.3 b/alliance/share/man/man3/restorealldir.3
deleted file mode 100644
index 3da188ff..00000000
--- a/alliance/share/man/man3/restorealldir.3
+++ /dev/null
@@ -1,82 +0,0 @@
-.\"   $Id: restorealldir.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)restorealldir.2 1.00 92/10/27 ; Labo masi cao-vlsi; Author : Vincent POUILLEY
-.\"modified by Frederic Petrot to meet the english language requirements!
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-restorealldir
-.XE
-.XS2 \n%
-.ti 0.2i
-restorealldir
-.XE2 \}
-.TH RESTOREALLDIR 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL FUNCTIONS"
-.SH NAME
-restorealldir \- restore all instances' connectors directions
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo412.h"
-int restorealldir(ptfig)
-lofig_list \(**ptfig;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIptfig\fP
-Pointer to a lofig_list
-.SH DESCRIPTION
-The \fBrestorealldir\fP function restores the directions of all the
-connectors of the instances.
-Each instance model logical view is loaded,  and the \fBrestoredirvbe\fP
-function applied.
-If a model doesn't have a \fBvbe\fP file on the path,
-the \fBrestorealldir\fP and \fBguessextdir\fP functions
-are used on the model.
-.br
-It is the charge of the user to delete the models loaded in memory for the
-function purpose.
-.SH RETURN VALUE
-\fBrestorealldir\fP returns \fB1\fP on success, \fB0\fP
-if there is an error while reading the vbe file.
-.SH ERROR
-\fBrestorealldir\fP cannot give any errors, but the function use
-\fBrestoredirvbe\fP
-that can give errors reading vbe files.
-see \fBrestoredirvbe\fP for details.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut412.h"
-#include "mlo412.h"
-lofig_list \(** getgoodlofig(figname, mode)
-char \(**figname;
-char mode;
-{
-lofig_list \(**ptfig;
-	ptfig = getlofig(figname, mode);
-	restorealldir(ptfig);
-	return ptfig;
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR lofig (3),
-.BR locon (3),
-.BR getlofig (3),
-.BR restoredirvbe (3).
-.BR guessextdir (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/restoredirvbe.3 b/alliance/share/man/man3/restoredirvbe.3
deleted file mode 100644
index c79d86b2..00000000
--- a/alliance/share/man/man3/restoredirvbe.3
+++ /dev/null
@@ -1,107 +0,0 @@
-.\"   $Id: restoredirvbe.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)restoredirvbe.2 1.00 92/10/27 ; Labo masi cao-vlsi; Author : Vincent POUILLEY
-.\"modified by Frederic Petrot to meet the english language requirements!
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-restoredirvbe
-.XE
-.XS2 \n%
-.ti 0.2i
-restoredirvbe
-.XE2 \}
-.TH RESTOREDIRVBE 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL FUNCTIONS"
-.SH NAME
-restoredirvbe \- restore connectors directions from behavioral view
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo412.h"
-int restoredirvbe(ptfig)
-lofig_list \(**ptfig;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIptfig\fP
-Pointer to a lofig_list
-.SH DESCRIPTION
-The \fBrestoredirvbe\fP function read the \fBPORT\fP section of the
-\fIvhdl\fP behavuoiral view of the
-figure, restores the externals connectors directions and order them
-as indicated in the vbe.
-.SH RETURN VALUE
-\fBrestoredirvbe\fP returns \fB1\fP on success, \fB0\fP
-if there is an error while reading the vbe file, \fB-1\fP if their is no vbe.
-.SH ERROR
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** restoredirvbe : no figure given"
-.ft R
-.RS
-The ptfig parameter is NULL.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** restoredirvbe : figure %s have more connectors than vbe"
-.ft R
-.RS
-Number of connetors in vbe and in figure must be identical. If the vbe have more
-connectors, the getlocon function give an error on the unknown connector.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** restoredirvbe : cannot read port well!"
-.ft R
-.RS
-To restore the connectors directions, the vbe description must have a port well.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** restoredirvbe : bit_vect neither to nor downto"
-.ft R
-.RS
-In a port section of a vbe, the bit vector must have indication of the sens of incrementation.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut412.h"
-#include "mlo412.h"
-lofig_list \(** getgoodlofig(figname, mode)
-char \(**figname;
-char mode;
-{
-lofig_list \(**ptfig;
-	ptfig = getlofig(figname, mode);
-	restoredirvbe(ptfig);
-	return ptfig;
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR lofig (3),
-.BR locon (3),
-.BR getlofig (3),
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/restrictbddnode.3 b/alliance/share/man/man3/restrictbddnode.3
deleted file mode 100644
index 672dbeb9..00000000
--- a/alliance/share/man/man3/restrictbddnode.3
+++ /dev/null
@@ -1,103 +0,0 @@
-.\"   $Id: restrictbddnode.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)restrictbddnode.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH RESTRICTBDDNODE 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-restrictbddnode \- substitutes a variable by a zero or one, in a \fBbdd\fP.
-
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddnode \(**restrictbddnode( BddSystem, BddNode, Variable, BddSubst )
-  bddsystem \(**BddSystem;
-  bddnode   \(**BddNode;
-  bddvar     Variable;
-  bddnode   \(**BddSubst;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIBddNode\fP
-The \fBbdd\fP node.
-.TP
-\fIVariable\fP
-The variable to find.
-.TP
-\fIBddSubst\fP
-The \fBbdd\fP to substitute with.
-.SH DESCRIPTION
-\fBrestrictbddnode\fP substitutes all the occurency of the variable \fIVariable\fP
-in the \fBbdd\fP node \fIBddNode\fP by the \fBbdd\fP node \fIBddSubst\fP, in the
-\fBbdd\fP system \fIBddSystem\fP. 
-If a null pointer is given, the default \fBbdd\fP system is used.
-The \fIBddSubst\fP must be a the node \fIBddSystem\fP->ONE or \fIBddSystem\fP->ZERO.
-.br
-.SH RETURN VALUE
-\fBrestrictbddnode\fP returns the resulting \fBbdd\fP node.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"variable xxx out of range, error !"
-.ft R
-.RS
-The \fIVariable\fP parameter must be less or equal to
-the \fIBddSystem->NUMBER_VAR\fP field.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"index xxx out of range, error !"
-.ft R
-.RS
-The \fIBddSubst\fP parameter must have its index less than BDD_INDEX_MIN.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddVariable;
-   bddnode    \(**BddNode;
-   bddnode    \(**BddSubst;
-   chain_list \(**Expr;
-   bddvar         Variable;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   Expr = createablbinexpr( ABL_OR,
-                            createablatom( "i0" ),
-                            createablatom( "i1" ) );
-   BddNode = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   BddSubst = BddSystem->ONE;
-   BddVariable = searchbddcircuitin( (bddcircuit \(**)0, "i0" );
-   Variable = getbddvarbyindex( (bddsystem \(**)0, BddVariable->INDEX );
-   BddNode = restrictbddnode( (bddsystem \(**)0, BddNode, Variable, BddSubst );
-   Expr = convertbddcircuitabl( BddCircuit, BddNode );
-   /* displays '1' */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/reverse.3 b/alliance/share/man/man3/reverse.3
deleted file mode 100644
index 8afa3107..00000000
--- a/alliance/share/man/man3/reverse.3
+++ /dev/null
@@ -1,67 +0,0 @@
-.\"   $Id: reverse.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)reverse.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-reverse
-.XE
-.XS4 \n%
-.ti 0.2i
-reverse
-.XE4 \}
-.TH REVERSE 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-reverse \- reverse a list of \fBchain\fPed elements
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-chain_list \(**reverse(ptold)
-chain_list \(**ptold;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIptold\fP
-Pointer to a \fBchain_list\fP to be reversed
-.SH DESCRIPTION
-The \fBreverse\fP function allows to reverse the order of the elements of
-a \fIchain_list\fP. It means that the last element becomes the first one,
-the one before the last one the second one, and so on.
-.TP
-remark :
-all mbk structures have for first field the \fINEXT\fP field, so, with
-appropriate cast, one can reverse any mbk list. Let's notice that nothing
-in the C language description demands a structure to be defined in
-memory the same way its members are defined in C. But all compiler do it
-this way now a day.
-Let's hope it will continue!
-.SH RETURN VALUE
-\fBreverse\fP returns a pointer to the head of the reversed list.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-void reverse_con(p)
-lofig_list \(**p;
-{
-	p\->LOCON = (locon_list \(**)reverse((chain_list \(**)p\->LOCON);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR chain (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/rflattenlofig.3 b/alliance/share/man/man3/rflattenlofig.3
deleted file mode 100644
index 75fe9457..00000000
--- a/alliance/share/man/man3/rflattenlofig.3
+++ /dev/null
@@ -1,94 +0,0 @@
-.\"   $Id: rflattenlofig.3,v 1.3 2001/10/29 10:49:12 xtof Exp $
-.\" @(#)rflattenlofig.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-rflattenlofig
-.XE
-.XS3 \n%
-.ti 0.2i
-rflattenlofig
-.XE3 \}
-.TH RFLATTENLOFIG 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL UTILITY FUNCTIONS"
-.SH NAME
-rflattenlofig \- recursivly flatten a figure 
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlu412.h"
-void rflattenlofig(ptfig, concat, catal)
-lofig_list \(**ptfig;
-char concat;
-char catal;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptfig\fP
-Pointer to a logical figure
-.TP
-\fIconcat\fP
-Name generation mode
-.TP
-\fIcatal\fP
-End level choice
-.SH DESCRIPTION
-\fBrflattenlofig\fP recursivly flattens all the instances of the figure
-pointed to by \fIptfig\fP. 
-.br
-The \fIconcat\fP argument can take either the value \fBYES\fP in which case the
-name of the objects comming from instances are named
-\fIinsname'X'objectname\fP, where \fI'X'\fP is the caracter set int the
-\fBMBK_SEPAR\fP(1) environment variable, or the value \fBNO\fP, and then the
-object name remains inchanged. This is quite dangerous since name unicity is
-no more warrantied, and may cause the flatten to fail. See \fBMBK_SEPAR\fP(1),
-\fBmbkenv\fP(3) and \fBconcatname\fP(3) for details.
-.br
-The \fIcatal\fP argument may be set to \fBNO\fP, in which case flattening stops
-at the transistor level, all hierachies and instances have desapeard, only
-terminal elements remains. If set to \fBYES\fP, flattening stops when it
-encounters an instance model beeing present in the catalog file, set by
-the \fBMBK_CATAL_NAME\fP(1) environment variable.
-See \fBMBK_CATAL_NAME\fP(1) and \fBincatalog\fP(3) for details.
-.SH ERRORS
-No errors can directly result from a call to \fBrflattenlofig\fP, but since it
-uses many other mbk functions, it may be a good error starting point.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlu502.h"
-void flatten_my_amd2901()
-{
-loins_list \(**pt;
-	pt = getlofig("my_amd2901", 'A');
-	rflattenlofig(pt, YES, YES);
-	pt\->NAME = "my_flattened_amd2901";
-	savelofig(pt);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR incatalog (3),
-.BR mbkenv (3),
-.BR lofig (3),
-.BR addlofig (3),
-.BR getlofig (3),
-.BR dellofig (3),
-.BR loadlofig (3),
-.BR savelofig (3),
-.BR flattenlofig (3),
-.BR MBK_CATAL_NAME (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/rflattenphfig.3 b/alliance/share/man/man3/rflattenphfig.3
deleted file mode 100644
index 7a14dbc1..00000000
--- a/alliance/share/man/man3/rflattenphfig.3
+++ /dev/null
@@ -1,94 +0,0 @@
-.\"   $Id: rflattenphfig.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)rflattenphfig.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-rflattenphfig
-.XE
-.XS1 \n%
-.ti 0.2i
-rflattenphfig
-.XE1 \}
-.TH RFLATTENPHFIG 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL UTILITY FUNCTIONS"
-.SH NAME
-rflattenphfig \- recursivly flatten a figure 
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph403.h"
-void rflattenphfig(ptfig, concat, catal)
-phfig_list \(**ptfig;
-char concat;
-char catal;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptfig\fP
-Pointer to a physical figure
-.TP
-\fIconcat\fP
-Name generation mode
-.TP
-\fIcatal\fP
-End level choice
-.SH DESCRIPTION
-\fBrflattenphfig\fP recursivly flattens all the instances of the figure
-pointed to by \fIptfig\fP. 
-.br
-The \fIconcat\fP argument can take either the value \fBYES\fP in which case the
-name of the objects comming from instances are named
-\fIinsname'X'objectname\fP, where \fI'X'\fP is the caracter set int the
-\fBMBK_SEPAR\fP(1) environment variable, or the value \fBNO\fP, and then the
-object name remains inchanged. This is quite dangerous since name unicity is
-no more warrantied, and may cause the flatten to fail. See \fBMBK_SEPAR\fP(1),
-\fBmbkenv\fP(3) and \fBconcatname\fP(3) for details.
-.br
-The \fIcatal\fP argument may be set to \fBNO\fP, in which case flattening stops
-at the transistor level, all hierachies and instances have desapeard, only
-terminal elements remains. If set to \fBYES\fP, flattening stops when it
-encounters an instance model beeing present in the catalog file, set by
-the \fBMBK_CATAL_NAME\fP(1) environment variable. See \fBMBK_CATAL_NAME\fP(1) and
-\fBincatalog\fP(3) for details.
-.SH ERRORS
-No errors can directly result from a call to \fBrflattenphfig\fP, but since it
-uses many other mbk functions, it may be a good error starting point.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph403.h"
-void flatten_my_amd2901()
-{
-phins_list \(**pt;
-	pt = getphfig("my_amd2901", 'A');
-	rflattenphfig(pt, YES, YES);
-	pt\->NAME = "my_flattened_amd2901";
-	savephfig(pt);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR incatalog (3),
-.BR mbkenv (3),
-.BR phfig (3),
-.BR addphfig (3),
-.BR getphfig (3),
-.BR delphfig (3),
-.BR loadphfig (3),
-.BR savephfig (3),
-.BR flattenphfig (3),
-.BR MBK_CATAL_NAME (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/roundrdsrec.3 b/alliance/share/man/man3/roundrdsrec.3
deleted file mode 100644
index 19563ebc..00000000
--- a/alliance/share/man/man3/roundrdsrec.3
+++ /dev/null
@@ -1,79 +0,0 @@
-.\"   $Id: roundrdsrec.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)roundrdsrec.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-roundrdsrec
-.XE
-.XS0 \n%
-.ti 0.2i
-roundrdsrec
-.XE0 \}
-.TH ROUNDRDSREC 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-roundrdsrec \- adjusts a rectangle to lambda grid step
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rfmnnn.h"
- void roundrdsrec( Rectangle )
-    rdsrec_list \(**Rectangle;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIRectangle\fP
-RDS rectangle to treat.
-.SH DESCRIPTION
-the \fIroundrdsrec\fP function adjusts (in lambda) to lower grid step for rectangle extremity which has coordinates (X,Y), adjusts to upper grid step for rectangle extremity which has coordinates (X+DX,Y+DY).
-.SH RETURN VALUE
-nothing
-.SH ERRORS
-none
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mphnnn.h"
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rfmnnn.h"
-        #include "rtlnnn.h"
-        typedef struct UserStruct
-         {
-           char \(**STRING;
-           void \(**USER1;
-         } UserStruct;
-        main()
-          {
-            rdsfig_list \(**RdsFigure;  
-            rdsrec_list \(**Rectangle;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            RdsFigure        = addrdsfig("core_2",sizeof(UserStruct));
-            Rectangle   =
-               addrdsfigrec(RdsFigure, "seg", RDS_ALU1, 2.5, 3.5, 6, 7);
-            viewrfmrec ( Rectangle );            
-            /\(** \(**/ \fBroundrdsrec\fP ( Rectangle );
-            /\(** view rectangle after rounding \(**/
-            viewrfmrec ( Rectangle );
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librfm,
-.BR viewrfmrec
-.BR et_un_autre_see_also
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/rsa.3 b/alliance/share/man/man3/rsa.3
deleted file mode 100644
index 9c8e5a4e..00000000
--- a/alliance/share/man/man3/rsa.3
+++ /dev/null
@@ -1,138 +0,0 @@
-.\"   $Id: rsa.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)Labo.l 0.0 91/04/02 UPMC; Author: Luis LUCAS
-.TH RSA 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL FUNCTIONS"
-.SH NAME
-rsa \- call the Recurrence Solver Adder generator
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "gga300.h"
-char \(**rsa(n, cin, cout, overn, not,
-             csa, sub, addsub,
-             over, deci, stretch, stretch2,
-             msb0, virtual,
-             layout, icon, vhdl, patterns, datasheet,
-             physicalbox-logicalbox-perf,
-             name)
-int n, cin, cout, overn, not,
-       csa, sub, addsub,
-       over, deci, stretch, stretch2,
-       msb0, virtual,
-       layout, icon, vhdl, patterns, datasheet,
-       physicalbox-logicalbox-perf,
-char \(**name;
-.ft R
-.fi
-.SH PARAMETER
-.TP
-.IB n
-The range is from 3 to 128 bits.
-.TP
-.B cin
-The generated adder will contain a carry input connector on the North side in
-Metal1 layer.
-.TP
-.B cout
-The generated adder will contain all the intermediates carry, accessible in
-Metal2 Layer, with the multi-access possibilities.
-.TP
-.B overn
-The generated adder will contain the previous carry output \fBover\fP in Metal1
-layer on the North side.
-This signal could be used to calculate an overflow flag = over^cout.
-.TP
-.B not
-The output sum will be complemented but still keep the connector name
-.BR s .
-.TP
-.B csa
-The generated adder will be an adder with 3 operands, and one overflow connector
-on the North side in Metal1 layer.
-.TP
-.B sub
-The adder generated is, in fact, a subtractor, and performs always a-b. If the
-option \fB-cin\fP is present, then the block calculates a+not(b)+cin .
-.TP
-.B addsub
-The block obtained is a adder/subtractor. If the input terminal is set to 5V
-then it is a subtractor. If the option \fB-cin\fP is present, then the block
-performs a+xor(b,sub)+cin.
-.TP
-.B over -deci -stretch -stretch2
-Bull Options.
-.TP
-.B msb0
-Default is index 0 for the least significant bit. When \fB-msb0\fP is present
-the the most significant bit is indexed with 0.
-.TP
-.B virtual
-Default blocks contain fixed terminals. Virtual terminals can be obtained
-using this option. This way,
-.BR dpr (1) router should optimized the resultant routed data-path.
-.TP
-.B layout
-The generated view asked is a layout view. The different formats are given by
-.BR mbk (1)
-documentation, using
-.BR MBK_OUT_PH (1)
-environment variable.
-.TP
-.B icon
-Icon view for schematic capture. The possible output formats are specified
-setting the ICON_OUT (1) environement variable.
-.TP 
-.B vhdl
-The generated view asked is a data-flow behavioural view. The description of
-the VHDL used is gived by
-.BR vhdl (5).
-.TP
-.B patterns
-Some test vectors are proposed to validate the generated block. The format used
-is the
-.BR pat (5)
-one accepted by the VHDL simulator
-.BR asimut (1).
-.TP
-.B datasheet
-Principals process dependent informations are proposed to estimate the adder
-performances. It is the default view if none is specified.
-.TP
-.B physicalbox
-The generated view asked is a interface view. The different formats are given by
-.BR mbk (1)
-documentation, using
-.BR MBK_OUT_PH (1)
-environment variable.
-.TP
-.B logicalbox
-The generated view asked is an interface netlist view.
-The different formats are given by
-.BR mbk (1)
-documentation, using
-.BR MBK_OUT_LO (1)
-environment variable.
-.TP
-.B perf
-Programmer Option
-.TP
-.BI name
-The generated adder name will be \fIname\fP.
-.SH SEE ALSO
-.BR MBK_CATA_LIB (1),
-.BR MBK_WORK_LIB (1),
-.BR MBK_OUT_PH (1),
-.BR MBK_OUT_LO (1),
-.BR MBK_IN_PH (1),
-.BR vhdl (5),
-.BR pat (5),
-.BR rsa (1),
-.BR rfg (1),
-.BR bsg (1),
-.BR grog (1),
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/satisfybddnode.3 b/alliance/share/man/man3/satisfybddnode.3
deleted file mode 100644
index 0d7a3f61..00000000
--- a/alliance/share/man/man3/satisfybddnode.3
+++ /dev/null
@@ -1,76 +0,0 @@
-.\"   $Id: satisfybddnode.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)satisfybddnode.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH SATISFYBDDNODE 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-satisfybddnode \- finds a satisfying path for a \fBbdd\fP node.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddnode \(**satisfybddnode( BddSystem, BddNode )
-  bddsystem \(**BddSystem;
-  bddnode   \(**BddNode;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem
-The \fBbdd\fP system.
-.TP
-\fIBddNode\fP
-The \fBbdd\fP node.
-.SH DESCRIPTION
-\fBsatisfybddnode\fP finds a simple path throw the \fBbdd\fP \fIBddNode\fP
-that reaches the constant \fBbdd\fP node one, in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBsatisfybddnode\fP returns a \fBbdd\fP node that satisfies \fIBddNode\fP.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"index xxx out of range, error !"
-.ft R
-.RS
-The \fIBddNode\fP parameter must be different from the \fBbdd\fP node zero.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   chain_list \(**Expr;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   Expr = createablbinexpr( ABL_OR,
-                            createablatom( "i0" ),
-                            createablatom( "i1" ) );
-   BddNode = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   BddNode = satisfybddnode( (bddsystem \(**)0, BddNode );
-   Expr = convertbddcircuitabl( BddCircuit, BddNode );
-   /* displays  i0 */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/savelofig.3 b/alliance/share/man/man3/savelofig.3
deleted file mode 100644
index 51507685..00000000
--- a/alliance/share/man/man3/savelofig.3
+++ /dev/null
@@ -1,93 +0,0 @@
-.\"   $Id: savelofig.3,v 1.2 2002/01/21 14:56:11 xtof Exp $
-.\" @(#)savelofig.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-savelofig
-.XE
-.XS2 \n%
-.ti 0.2i
-savelofig
-.XE2 \}
-.TH SAVELOFIG 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL UTILITY FUNCTIONS"
-.SH NAME
-savelofig \- save a logical figure on disk 
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlu502.h"
-void savelofig(ptfig)
-lofig_list \(**ptfig;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIptfig\fP
-Pointer to the \fIlofig\fP to be written on disk
-.SH DESCRIPTION
-\fBsavelofig\fP writes on disk the contents of the figure pointer to by 
-\fIptfig\fP. All the figure lists are ran through, and the appropriate objects
-written, independently of the figure \fImode\fP. 
-.br
-The \fBsavelofig\fP function in fact performs a call to a driver, choosen
-by the \fBMBK_OUT_LO\fP(1) environment variable. The directory in which the file
-is to be written is the one set by \fBMBK_WORK_LIB\fP(1).
-See \fBMBK_OUT_LO\fP(1), \fBMBK_WORK_LIB\fP(1) and
-\fBmbkenv\fP(3) for details.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** not supported logical output format 'xxx'"
-.ft R
-.RS
-The environment variable \fIMBK_OUT_LO\fP is not set to a legal logical
-format.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** savelofig : could not open file \fIfigname.ext\fP"
-.ft R
-.RS
-Either the directory or the file are write protected, so it's not possible to
-open \fIfigname.ext\fP, where \fIext\fP is the file format extension, for 
-writting.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlu502.h"
-void save_na2_y()
-{
-	savelofig(getlofig("na2_y"));
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR mbkenv (3),
-.BR lofig (3),
-.BR addlofig (3),
-.BR getlofig (3),
-.BR dellofig (3),
-.BR loadlofig (3),
-.BR flattenlofig (3),
-.BR rflattenlofig (3),
-.BR MBK_OUT_LO (1),
-.BR MBK_WORK_LIB (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/savephfig.3 b/alliance/share/man/man3/savephfig.3
deleted file mode 100644
index 1af13d7f..00000000
--- a/alliance/share/man/man3/savephfig.3
+++ /dev/null
@@ -1,93 +0,0 @@
-.\"   $Id: savephfig.3,v 1.2 2002/01/21 14:56:11 xtof Exp $
-.\" @(#)savephfig.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-savephfig
-.XE
-.XS0 \n%
-.ti 0.2i
-savephfig
-.XE0 \}
-.TH SAVEPHFIG 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL UTILITY FUNCTIONS"
-.SH NAME
-savephfig \- save a physical figure on disk 
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mpu408.h"
-void savephfig(ptfig)
-phfig_list \(**ptfig;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIptfig\fP
-Pointer to the \fIphfig\fP to write on disk
-.SH DESCRIPTION
-\fBsavephfig\fP writes on disk the contents of the figure pointer to by 
-\fIptfig\fP. All the figure lists are ran through, and the appropriate objects
-written, independently of the figure \fImode\fP. 
-.br
-The \fBsavephfig\fP function in fact performs a call to a driver, choosen
-by the \fIMBK_OUT_PH\fP(1) environment variable. The directory in which the file
-is to be written is the one set by \fBMBK_WORK_LIB\fP(1).
-See \fBMBK_OUT_PH\fP(1), \fBMBK_WORK_LIB\fP(1) and
-\fBmbkenv\fP(3) for details.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** not supported physical output format 'xxx'"
-.ft R
-.RS
-The environment variable \fIMBK_OUT_PH\fP is not set to a legal physical
-format.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** savephfig : could not open file \fIfigname.ext\fP"
-.ft R
-.RS
-Either the directory or the file are write protected, so it's not possible to
-open \fIfigname.ext\fP, where \fIext\fP is the file format extension, for 
-writting.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mpu408.h"
-void save_na2_y()
-{
-	savephfig(getphfig("na2_y"));
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR mbkenv (3),
-.BR phfig (3),
-.BR addphfig (3),
-.BR getphfig (3),
-.BR delphfig (3),
-.BR loadphfig (3),
-.BR flattenphfig (3),
-.BR rflattenphfig (3),
-.BR MBK_OUT_PH (1),
-.BR MBK_WORK_LIB (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/saverdsfig.3 b/alliance/share/man/man3/saverdsfig.3
deleted file mode 100644
index c171cd6d..00000000
--- a/alliance/share/man/man3/saverdsfig.3
+++ /dev/null
@@ -1,72 +0,0 @@
-.\"   $Id: saverdsfig.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)saverdsfig.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-saverdsfig
-.XE
-.XS0 \n%
-.ti 0.2i
-saverdsfig
-.XE0 \}
-.TH SAVERDSFIG 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-saverdsfig \- save a physical figure on disk.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rtlnnn.h"
- void saverdsfig( Figure )
-    rdsfig_list \(**Figure;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIFigure\fP
-Pointer to the RDS Figure to save.
-.SH DESCRIPTION
-The \fIsaverdsfig\fP function writes on disk the contents of the figure pointer to by rdsfig_list. The savephfig function in fact performs a call to a driver, choosen by the RDS_OUT environment  variable. 
-.SH RETURN VALUE
-none
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Rtl103.h: Unknown rds output format"
-.ft R
-.RS
-The output format defined by the unix environment variable RDS_OUT is not supported by the driver (supported formats are "cif" and "gds").
-.PP
-Other errors can appear because the saverdsfig function calls cif and gds drivers.
-.SH EXAMPLE
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rtlnnn.h"
-        main()
-         {
-           rdsfig_list \(**RdsFigure;
-           mbkenv();
-           rdsenv();
-           loadrdsparam();
-           loadrdsfig( RdsFigure, "core", 'A');
-           RdsFigure->NAME = namealloc ( "core_2" );
-           /\(** \(**/ \fBsaverdsfig\fP ( RdsFigure );
-         }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librtl,
-.BR loadrdsfig,
-.BR rdsenv,
-.BR getrdsfig,
-.BR RDS_OUT
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/searchExpr.3 b/alliance/share/man/man3/searchExpr.3
deleted file mode 100644
index ddcf9c95..00000000
--- a/alliance/share/man/man3/searchExpr.3
+++ /dev/null
@@ -1,50 +0,0 @@
-.\"   $Id: searchExpr.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)searchExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH SEARCHEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBsearchExpr\fP \- searches for a specific atom in an expression.
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-int searchExpr(expr,name)
-chain_list *expr;
-char *name;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIexpr\fP
-expression
-.TP 20
-\fIname\fP
-name to look for
-.SH DESCRIPTION
-\fBsearchExpr()\fP searches for \fIname\fP in \fIexpr\fP and returns 1 if \fIname\fP is an atom of \fBexpr\fP.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr; 
-expr = createExpr(OR);
-addQExpr(expr,createAtom("a"));
-addQExpr(expr,createAtom("b"));
-printf("%d",searchExpr(expr,"a"));
-/* it will display
-1
-*/
-freeExpr(expr);
-.fi
-
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR searchOperExpr (3),
-.BR equalExpr (3),
-.BR equalVarExpr (3),
-.BR lengthExpr (3),
-.BR profExpr (3),
-.BR numberAtomExpr (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/searchInputCct.3 b/alliance/share/man/man3/searchInputCct.3
deleted file mode 100644
index 3fb68d4a..00000000
--- a/alliance/share/man/man3/searchInputCct.3
+++ /dev/null
@@ -1,58 +0,0 @@
-.\"   $Id: searchInputCct.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)searchInputCct.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH SEARCHINPUTCCT 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBsearchInputCct\fP \- searches for the index number associated to an input.
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-short searchInputCct(pC,name)
-pCircuit pC;
-char *name;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIpC\fP
-Circuit 
-.TP 20
-\fIname\fP
-name to look for
-.SH DESCRIPTION
-\fBsearchInputCct()\fP searches for the index associated to \fIname\fP. This function returns \fIEMPTYTH\fP if the primary input doesn't exist in \fIpC\fP.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-short index;
-pCircuit pC;
-
-initializeBdd(SMALL_BDD);
-pC = initializeCct("circuit 1",10,10);
-
-addInputCct(pC,"a");
-addInputCct(pC,"b");
-
-index = searchInputCct(pC,"a");
-printf("index(a) = %d",index);
-index = searchInputCct(pC,"c");
-printf("index(c) = %d",index);
-
-/* it will display 
-index(a) = 2
-index(c) = -1
-*/
-
-destroyCct(pC);
-destroyBdd(1);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR addInputCct (3),
-.BR cpOrderCct (3),
-.BR searchOutputCct (3),
-.BR addOutputCct (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/searchNumExpr.3 b/alliance/share/man/man3/searchNumExpr.3
deleted file mode 100644
index 011c73a4..00000000
--- a/alliance/share/man/man3/searchNumExpr.3
+++ /dev/null
@@ -1,54 +0,0 @@
-.\"   $Id: searchNumExpr.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)searchNumExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH SEARCHNUMEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBsearchNumExpr\fP \- fetches the i-th argument in an operator expression. 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-chain_list *searchNumExpr(expr,i)
-chain_list *expr;
-int i;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIexpr\fP
-expression
-.TP 20
-\fIi\fP
-index of the argument
-.SH DESCRIPTION
-\fBsearchNumExpr()\fP fetches the \fIi-th\fP argument of \fIexpr\fP. As an \fIarray\fP of C-programming, the indedx of the first argument is 0. This function returns an argument that isn't duplicated. 
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr; 
-expr = createExpr(OR);
-addQExpr(expr,createAtom("a"));
-addQExpr(expr,createAtom("b"));
-displayExpr(searchNumExpr(expr,1));
-/* it will display
-b
-*/
-freeExpr(expr);
-.fi
-.SH ERROR
-"searchNumExpr : error - index out of bound"
-.br
-index i must be included between 0 and \fIlengthExpr(expr)-1\fP.
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR deleteNumExpr (3),
-.BR searchOperExpr (3),
-.BR equalExpr (3),
-.BR equalVarExpr (3),
-.BR lengthExpr (3),
-.BR profExpr (3),
-.BR numberAtomExpr (3),
-.BR numberOccExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/searchOperExpr.3 b/alliance/share/man/man3/searchOperExpr.3
deleted file mode 100644
index b62e2744..00000000
--- a/alliance/share/man/man3/searchOperExpr.3
+++ /dev/null
@@ -1,48 +0,0 @@
-.\"   $Id: searchOperExpr.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)searchOperExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH SEARCHOPEREXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBsearchOperExpr\fP \- searches for an operator in an expression.
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-int searchOperExpr(expr,oper)
-chain_list *expr;
-short oper;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIexpr\fP
-expression
-.TP 20
-\fIoper\fP
-oper to look for
-.SH DESCRIPTION
-\fBsearchOperExpr()\fP searches for \fIoper\fP in \fIexpr\fP and returns 1 if \fIoper\fP is an operator of \fIexpr\fP.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr; 
-expr = createExpr(OR);
-addQExpr(expr,createAtom("a"));
-addQExpr(expr,createAtom("b"));
-printf("%d",searchOperExpr(expr,OR));
-/* it will display
-1
-*/
-freeExpr(expr);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR searchExpr (3),
-.BR equalExpr (3),
-.BR equalVarExpr (3),
-.BR lengthExpr (3),
-.BR profExpr (3),
-.BR numberAtomExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/searchOutputCct.3 b/alliance/share/man/man3/searchOutputCct.3
deleted file mode 100644
index 90fe8855..00000000
--- a/alliance/share/man/man3/searchOutputCct.3
+++ /dev/null
@@ -1,58 +0,0 @@
-.\"   $Id: searchOutputCct.3,v 1.1 1999/05/31 17:30:24 alliance Exp $
-.\" @(#)searchOuputCct.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH SEARCHOUTPUTCCT 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBsearchOuputCct\fP \- searches for the BDD associated to an output 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-pNode searchOuputCct(pC,name)
-pCircuit pC;
-char *name;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIpC\fP
-Circuit 
-.TP 20
-\fIname\fP
-name to look for
-.SH DESCRIPTION
-\fBsearchOuputCct()\fP searches for the BDD asociated to \fIname\fP. This function returns NULL if the BDD doesn't exist. 
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-pCircuit pC;
-chain_list *expr;
-
-initializeBdd(SMALL_BDD);
-pC = initializeCct("circuit 1",10,10);
-
-addInputCct(pC,"a");
-addInputCct(pC,"b");
-
-	/* let's suppose that expr = (OR a b) */
-
-addOuputCct(pC,"s",ablToBddCct(pC,expr));
-
-res = searchOutputCct(pC,"s");
-displayBdd(res,0);
-
-/* it will display 
-@res	LOW = @nodeA	HIGH = ONE
-*/
-
-destroyCct(pC);
-destroyBdd(1);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR searchOutputCct (3),
-.BR searchInputCct (3),
-.BR addOutputCct (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/searchTH.3 b/alliance/share/man/man3/searchTH.3
deleted file mode 100644
index e21d04a5..00000000
--- a/alliance/share/man/man3/searchTH.3
+++ /dev/null
@@ -1,51 +0,0 @@
-.\"   $Id: searchTH.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)searchTH.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH SEARCHTH 3 "October 1, 1997" "ASIM/LIP6" "Hash table functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBsearchTH\fP \- searches an item in a hash table.
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-int searchTH(pTable,key)
-pTH pTable;
-char *key;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIpTable\fP
-Hash table.
-.TP 20
-\fIkey\fP
-Key used by the hash coding function.
-.SH DESCRIPTION
-\fBsearchTH()\fP searches an item in \fIpTable\fP. If the key exists, the associated value is returned, if it doesn't, the function returns -1 (EMPTYTH).
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"
-#include "logmmm.h"
-pTH mytable; 
-int val;
-
-mytable = createTH(100); 
-addTH(mytable,namealloc("var1"),0);
-val = searchTH(mytable,namealloc("var1"));
-	/* val = 0 */
-val = searchTH(mytable,namealloc("var2"));
-	/* val = -1 */
-if (val != EMPTYTH)
-   printf("found !");
-else
-   printf("var2 doesn't exist in mytable!");
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR tsh (1),
-.BR createTH (3),
-.BR destroyTH (3),
-.BR addTH (3),
-.BR deleteTH (3),
-.BR displayTH (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/searchauth2elem.3 b/alliance/share/man/man3/searchauth2elem.3
deleted file mode 100644
index 318afdad..00000000
--- a/alliance/share/man/man3/searchauth2elem.3
+++ /dev/null
@@ -1,92 +0,0 @@
-.\"   $Id: searchauth2elem.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)searchauth2elem.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH SEARCHAUTH2ELEM 3 "October 1, 1997" "ASIM/LIP6" "AUT FUNCTIONS"
-.SH NAME
-searchauth2elem \-  searches an element in the hash table.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-auth2elem \(**searchauth2elem( HashTable, Key1, Key2 )
-  auth2table \(**HashTable;
-  char      \(**Key1;
-  char      \(**Key2;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIHashTable\fP
-Pointer to the hash table where to search an element.
-.TP
-\fIKey1\fP
-The first hash element key.
-.TP
-\fIKey2\fP
-The second hash element key.
-.SH DESCRIPTION
-\fBsearchauth2elem\fP searches the element associated to the two keys \fIKey1\fP
-and \fIKey2\fP in the hash table.
-.br
-.SH RETURN VALUE
-if the element can be found \fBsearchauth2elem\fP returns a pointer to this element
-and a null pointer otherwise.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"auth2ash: hash key 0 error !"
-.ft R
-.RS
-The two keys \fIKey1\fP and \fIKey2\fP must be valid pointers.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-   auth2table \(**HashTable;
-   void add_dictionary( Name1, Name2 )
-     \(** Name1;
-     \(** Name2;
-   {
-     addauth2elem( HashTable, 
-                   namealloc( Name1 ),
-                   namealloc( Name2 ), 0 );
-   }
-   int search_dictionary( Name1, Name2 )
-     \(** Name1;
-     \(** Name2;
-   {
-     auth2elem \(**HashElement;
-     HashElement = searchauth2elem( HashTable,
-                                    namealloc( Name1 ),
-                                    namealloc( Name2 ) );
-     return( HashElement != (auth2elem \(**0) );
-   }
-   ...
-   HashTable = createauth2table( 1000 );
-   add_dictionary( "hello", "world" );
-   ...
-   if ( search_dictionary( "hello", "world" ) )
-   ...
-   destroyauth2table( HashTable );
-.ft R
-.fi
-.SH SEE ALSO
-.BR aut (1)
-.BR destroyauth2table(3),
-.BR resetauth2table(3),
-.BR createauth2table(3),
-.BR addhauth2elem(3),
-.BR delauth2elem(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/searchauthelem.3 b/alliance/share/man/man3/searchauthelem.3
deleted file mode 100644
index 7474ee1b..00000000
--- a/alliance/share/man/man3/searchauthelem.3
+++ /dev/null
@@ -1,82 +0,0 @@
-.\"   $Id: searchauthelem.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)searchauthelem.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH SEARCHAUTHELEM 3 "October 1, 1997" "ASIM/LIP6" "AUT FUNCTIONS"
-.SH NAME
-searchauthelem \-  searches an element in the hash table.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-authelem \(**searchauthelem( HashTable, Key )
-  authtable \(**HashTable;
-  char      \(**Key;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIHashTable\fP
-Pointer to the hash table where to search an element.
-.TP
-\fIKey\fP
-The hash element key.
-.SH DESCRIPTION
-\fBsearchauthelem\fP searches the element associated to the key \fIKey\fP
-in the hash table.
-.br
-.SH RETURN VALUE
-if the element can be found \fBsearchauthelem\fP returns a pointer to this element
-and a null pointer otherwise.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"authash: hash key 0 error !"
-.ft R
-.RS
-The key \fIKey\fP of the hash table must be a valid pointer.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-   authtable \(**HashTable;
-   void add_dictionary( Name )
-     \(** Name;
-   {
-     addauthelem( HashTable, namealloc( Name ), 0 );
-   }
-   int search_dictionary( Name )
-     \(** Name;
-   {
-     authelem \(**HashElement;
-     HashElement = searchauthelem( HashTable, namealloc( Name ) );
-     return( HashElement != (authelem \(**0) );
-   }
-   ...
-   HashTable = createauthtable( 1000 );
-   add_dictionary( "hello" );
-   ...
-   if ( search_dictionary( "hello" ) )
-   ...
-   destroyauthtable( HashTable );
-.ft R
-.fi
-.SH SEE ALSO
-.BR aut (1)
-.BR destroyauthtable(3),
-.BR resetauthtable(3),
-.BR createauthtable(3),
-.BR addhauthelem(3),
-.BR delauthelem(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/searchbddcircuitin.3 b/alliance/share/man/man3/searchbddcircuitin.3
deleted file mode 100644
index 34b30599..00000000
--- a/alliance/share/man/man3/searchbddcircuitin.3
+++ /dev/null
@@ -1,60 +0,0 @@
-.\"   $Id: searchbddcircuitin.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)searchbddcircuitin.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH SEARCHBDDCIRCUITIN 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-searchbddcircuitin \- searchs an input in a \fBbdd\fP circuit.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-  bddnode \(**searchbddcircuitin( BddCircuit, InputName )
-  bddcircuit \(**BddCircuit;
-  char       \(**InputName;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddCircuit\fP
-The \fBbdd\fP circuit.
-.TP
-\fIInputName\fP
-The name of the input to look for.
-.SH DESCRIPTION
-\fBsearchbddcircuitin\fP searchs the input \fIInputName\fP in the \fBbdd\fP
-circuit \fIBddCircuit\fP.
-If a null pointer is given, the default \fBbdd\fP circuit is used.
-.br
-.SH RETURN VALUE
-\fBsearchbddcircuitin\fP returns the node corresponding to the input \fIInputName\fP
-or a null pointer if no such input is found.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   addbddcircuitin ( (bddcircuit \(**)0, "i0", 0, BDD_IN_MODE_FIRST );
-   ...
-   BddNode = searchbddcircuitin( (bddcircuit \(**)0, "i0" );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1),
-.BR addbddcircuitin(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/searchbddcircuitout.3 b/alliance/share/man/man3/searchbddcircuitout.3
deleted file mode 100644
index 728a6b9b..00000000
--- a/alliance/share/man/man3/searchbddcircuitout.3
+++ /dev/null
@@ -1,61 +0,0 @@
-.\"   $Id: searchbddcircuitout.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)searchbddcircuitout.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH SEARCHBDDCIRCUITOUT 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-searchbddcircuitout \- searchs an output in a \fBbdd\fP circuit.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-  bddnode \(**searchbddcircuitout( BddCircuit, OutputName )
-  bddcircuit \(**BddCircuit;
-  char       \(**OutputName;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddCircuit\fP
-The \fBbdd\fP circuit.
-.TP
-\fIOutputName\fP
-The name of the output to look for.
-.SH DESCRIPTION
-\fBsearchbddcircuitout\fP searchs the output \fIOutputName\fP in the \fBbdd\fP
-circuit \fIBddCircuit\fP.
-If a null pointer is given, the default \fBbdd\fP circuit is used.
-.br
-.SH RETURN VALUE
-\fBsearchbddcircuitout\fP returns the node corresponding to 
-the output \fIOutputName\fP or a null pointer if no such output is found.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   ...
-   addbddcircuitout( (bddcircuit \(**)0, "Out0", BddNode );
-   ...
-   BddNode = searchbddcircuitout( (bddcircuit \(**)0, "Out0" );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1),
-.BR addbddcircuitout(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/searchrdsfig.3 b/alliance/share/man/man3/searchrdsfig.3
deleted file mode 100644
index 57523821..00000000
--- a/alliance/share/man/man3/searchrdsfig.3
+++ /dev/null
@@ -1,71 +0,0 @@
-.\"   $Id: searchrdsfig.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)searchrdsfig.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-searchrdsfig
-.XE
-.XS0 \n%
-.ti 0.2i
-searchrdsfig
-.XE0 \}
-.TH SEARCHRDSFIG 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-searchrdsfig \- searchs by name a figure in the list of figures 
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rutnnn.h"
- rdsfig_list \(**searchrdsfig( Name )
-   char \(**Name;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIName\fP
-Name of the figure to search.
-.SH DESCRIPTION
-The \fIsearchrdsfig\fP function searchs a figure by its name in the list of figures in memory.
-.SH RETURN VALUE
-Pointer to the figure searched. If the figure is not found then pointer NULL is returned.
-.SH ERRORS
-none
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rutnnn.h"
-        #include "rtlnnn.h"
-        main()
-         {
-           rdsfig_list \(**Figure;
-           rdsfig_list \(**ScanFigure;
-           mbkenv();
-           rdsenv();
-           loadrdsparam();
-           Figure = addrdsfig("na2",0);
-           Figure = addrdsfig("no2",0);
-           Figure = addrdsfig("xr2",0);
-           Figure = addrdsfig("n03",0);
-           ScanFigure = \fBsearchrdsfig\fP("xr2");
-           viewrdsfig ( ScanFigure );
-         }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librtl,
-.BR librds
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/segmbkrds.3 b/alliance/share/man/man3/segmbkrds.3
deleted file mode 100644
index 4310860c..00000000
--- a/alliance/share/man/man3/segmbkrds.3
+++ /dev/null
@@ -1,95 +0,0 @@
-.\"   $Id: segmbkrds.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)segmbkrds.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-segmbkrds
-.XE
-.XS0 \n%
-.ti 0.2i
-segmbkrds
-.XE0 \}
-.TH SEGMBKRDS 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-segmbkrds \- adds to RDS figure a segment from a MBK figure
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rfmnnn.h"
- rdsrec_list \(**segmbkrds( Figure, Segment, Lynx )
-    rdsfig_list \(**Figure;
-    phseg_list  \(**Segment;
-    char         Lynx;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIFigure\fP
-The RDS figure which has to receive the converted segment. 
-.TP
-\fISegment\fP
-MBK segment to convert to RDS rectangle.
-.TP
-\fILynx\fP
-Flag used for the segment conversion. If the parameter Lynx is set to 0 then this is the normal conversion mode. If the parameter Lynx is set to 1 then the rds structure generated permits to extract equipotentials rectangles.
-.SH DESCRIPTION
-The \fIsegmbkrds\fP function converts and creates a RDS segment from a MBK segment. The segment is attached to the RDS figure in parameter of the segmbkrds function. See the \fIrdsfig_list\fP structure in librds.
-.SH RETURN VALUE
-Pointer to the newly created RDS segment.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Rds202: rdsalloc error, can't continue !"
-.ft R
-.RS
-it's impossible to allocate the memory size desired
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mphnnn.h"  
-        #include "mutnnn.h"  
-        #include "rdsnnn.h"
-        #include "rfmnnn.h"
-        #include "rtlnnn.h"
-        typedef struct UserStruct
-         {
-           char \(**STRING;
-           void \(**USER1;
-         } UserStruct;
-        main()
-          {
-            phfig_list  \(**MbkFigure;
-            rdsfig_list \(**RdsFigure;
-            rdsrec_list \(**Segment;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            RdsFigure =
-               addrdsfig ("core",sizeof ( UserStruct ) );
-            MbkFigure->PHSEG =
-               addphseg ( MbkFigure, ALU1, 1, 1, 1, 2, 12, "seg_alu1");
-            Segment = \fBsegmbkrds\fP (RdsFigure, MbkFigure->PHSEG, 0);
-            viewrdsrec ( Segment );
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librds,
-.BR librfm,
-.BR viewrfmseg,
-.BR loadrdsparam
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/setbddrefext.3 b/alliance/share/man/man3/setbddrefext.3
deleted file mode 100644
index f98b64d2..00000000
--- a/alliance/share/man/man3/setbddrefext.3
+++ /dev/null
@@ -1,73 +0,0 @@
-.\"   $Id: setbddrefext.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)setbddrefext.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH SETBDDREFEXT 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-setbddrefext \- increments the external reference,
-and decrements the internal reference of a \fBbdd\fP node.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddnode \(**setbddrefext( BddNode )
-  bddnode \(**BddNode;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddNode\fP
-The \fBbdd\fP node.
-.SH DESCRIPTION
-\fBsetbddrefext\fP increments the number of external reference
-of the \fBbdd\fP node \fIBddNode\fP and decrements its number of
-internal reference.
-.br
-.SH RETURN VALUE
-\fBsetbddrefext\fP returns the \fIBddNode\fP pointer.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"negative reference, index xxx error !"
-.ft R
-.RS
-The \fIBddNode\fP must have a postive number of internal reference.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   chain_list \(**Expr;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   BddNode = addbddcircuitin( (bddcircuit \(**)0, "i0", 0, BDD_IN_MODE_FIRST );
-   BddNode = addbddnode( (bddsystem \(**)0, BddNode->INDEX, BddNode->LOW, BddNode->HIGH );
-   Expr = convertbddcircuitabl( (bddcircuit \(**)0, BddNode );
-   incbddrefint( BddNode );
-   setbddrefext( BddNode );
-   /* displays Node VAR: 0  INDEX: 2  MARK: 0  REF_EXT: 1  REF_INT: 0 */
-   viewbddnode( (bddsystem \(**)0, BddNode );
-   /* displays (not i0) */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/sethtitem.3 b/alliance/share/man/man3/sethtitem.3
deleted file mode 100644
index 6fc1df4a..00000000
--- a/alliance/share/man/man3/sethtitem.3
+++ /dev/null
@@ -1,99 +0,0 @@
-.\"   $Id: sethtitem.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)sethtitem.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.\" slightly modified by Fred Petrot for mbk adaptation on 22/06/92
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-sethtitem
-.XE
-.XS4 \n%
-.ti 0.2i
-sethtitem
-.XE4 \}
-.TH SETHTITEM 3 "October 1, 1997" "ASIM/LIP6" "MBK HASH TABLE MANAGEMENT FUNCTIONS"
-.SH NAME
-sethtitem \- test and set an item in an hash table.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.nf
-#include "mut315.h"
-int sethtitem(table, key)
-ht \(**table;
-void \(**key;
-.fi
-.SH PARAMETERS
-.TP 20
-\fItable\fP
-Hash table pointer
-.TP 20
-\fIkey\fP
-Key used by the hash coding function to set an item
-.SH DESCRIPTION
-\fBsethtitem()\fP adds an item in the hash table pointed to by \fItable\fP,
-whether it existed or not, and returns an appropriate value.
-This is kind of a \fItest and set\fP operator.
-.SH RETURN VALUE
-If the key exists, the funtion return 1,
-if it doesn't, the item is stored and the function returns 0.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.nf
-#include <stdio.h>
-#include "mut315.h"
-checksigname(p)
-lofig_list *p;
-{
-int i;
-losig_list *ptsig;
-locon_list *ptcon;
-ht *h;
-char *amatla;
-	for (i = 0, ptsig = p->LOSIG; ptsig; i++, ptsig = ptsig->NEXT);
-	h = addht(i << 1); /* half empty hash tables are faster! */
-	for (ptcon = p->LOCON; ptcon; ptcon = ptcon->NEXT)
-		addhtitem(h, ptcon->NAME, 0);
-	for (ptsig = p->LOSIG; ptsig; ptsig = ptsig->NEXT) {
-		if (ptsig->TYPE == INTERNAL) {
-			amatla = getsigname(ptsig);
-			if (!sethtitem(h, amatla, 0))
-				printf("node %s is now unique\\n", amatla);
-		}
-	}
-	delht(h);
-}
-.fi
-.ft R
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"\(**\(**\(** mbk error \(**\(**\(** sethtitem impossible :
-value is \fBEMPTYHT\fP or \fBDELETEHT\fP"
-.ft R
-.RS
-The values \fBEMPTYHT\fP, \fI-1\fP,  and \fBDELETEHT\fP, \fI-2\fP, are reserved
-for internal use, sorry.
-.SH DIAGNOSTICS
-The value must be distinct from \fI-1\fP and \fI-2\fP.
-.SH SEE ALSO
-.BR mbk (1),
-.BR addht (3),
-.BR delht (3),
-.BR addhtitem (3),
-.BR gethtitem (3),
-.BR delhtitem (3),
-.BR viewht (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/signal.3 b/alliance/share/man/man3/signal.3
deleted file mode 100644
index e2e8cbce..00000000
--- a/alliance/share/man/man3/signal.3
+++ /dev/null
@@ -1,64 +0,0 @@
-.\"   $Id: signal.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)SIGNAL.2 1.9  UPMC ; VUONG H.N.
-.TH SIGNAL 3 "October 1, 1997" "ASIM/LIP6" "GENPAT functions"
-
-.SH NAME
-.PP
-\fBsignal\fP, GENPAT Package
-
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.PP
-.nf
-signal("ident","ident", ... ,":nb_space","format","size",0);
-.fi
-
-.SH PARAMETERS
-.PP
-.TP 10
-\fIident\fP
-internal signal's name, the number of character is limited to 20
-.TP 10
-\fInb_space\fP
-Specify the number of blank space between each group of value. 0,1,2,3,4,5,6,7,8,9 or nothing.
-.TP 10
-\fIformat\fP
-Specify the format that will be used to represent the value associated to
-the connectors. X for Hexadecimal, O for Octal and B for Binary.
-.TP 10
-\fIsize\fP
-Specify the size of the bused connectors. ' ' : empty, (the chain is empty and the " are omitted) for the scalar
-connectors, nb1 for the numbered connectors, nb1 TO nb2 (nb1 < nb2, nb1 and
-nb2 integers), nb1 DOWNTO nb2 (nb2 < nb1).
-
-.SH DESCRIPTION
-.PP
-Describes a set of internal signals of the same format and size.
-
-.SH EXAMPLE
-.PP
-.nf
-signal("a","b","c","d",":2","X","3 DOWNTO 0",0);
-describes : a 3, a 2, a 1, a 0, b 3, b 2, b 1, b 0, 
-	    c 3, c 2, c 1, c 0, d 3, d 2, d 1, d 0.
-format : Hexadecimal.
-each group is separated of the others with 2 blank spaces.
-
-signal("toto",":","O","7 TO 11",0);
-describes : toto 7, toto 8, toto 9, toto 10, toto 11.
-format : Octal.
-the group is separated of the following with 0 blank space.
-
-signal("ck",":2","B",0);
-describes : ck.
-format : Binary.
-the signal is separated of the following with 2 blank spaces.
-.fi
-
-.SH SEE ALSO
-.PP
-port(3), register(3), genpat(1), pat(1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/simpablexpr.3 b/alliance/share/man/man3/simpablexpr.3
deleted file mode 100644
index 5fe6fb53..00000000
--- a/alliance/share/man/man3/simpablexpr.3
+++ /dev/null
@@ -1,51 +0,0 @@
-.\"   $Id: simpablexpr.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)simpablexpr.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH SIMPABLEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-simpablexpr \- simplies an expression.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-chain_list \(**simpablexpr( Expr )
-  chain_list \(**Expr;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIExpr\fP
-Expression to simplfy.
-.SH DESCRIPTION
-\fBsimpablexpr\fP simplifies \fIExpr\fP.  The expression pointer \fIExpr\fP
-MUSTN'T be used after the call to this function.
-.br
-.SH RETURN VALUE
-\fBsimpablexpr\fP returns a pointer to the simplied expression.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-  chain_list \(**Expr;
-  Expr = createablbinexpr( ABL_AND,
-                           createablatom( "'0'" ),
-                           createablatom( "'1'" ) );
-  Expr = simpablexpr( Expr );
-  /* displays '0' */
-  viewablexpr( Expr, ABL_VIEW_VHDL );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1),
-.BR simpdupablexpr(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/simpbddnodedcoff.3 b/alliance/share/man/man3/simpbddnodedcoff.3
deleted file mode 100644
index 3ef0ec99..00000000
--- a/alliance/share/man/man3/simpbddnodedcoff.3
+++ /dev/null
@@ -1,80 +0,0 @@
-.\"   $Id: simpbddnodedcoff.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)simpbddnodedcoff.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH SIMPBDDNODEDCOFF 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-simpbddnodedcoff \- simplifies a \fBbdd\fP with don't cares on its off-set part.
-
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddnode \(**simpbddnodedcoff( BddSystem, BddOff, BddDc )
-  bddsystem \(**BddSystem;
-  bddnode   \(**BddOff;
-  bddnode   \(**BddDc;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIBddOff\fP
-The first \fBbdd\fP node.
-.TP
-\fIBddDc\fP
-The second \fBbdd\fP node.
-.SH DESCRIPTION
-\fBsimpbddnodedcoff\fP simplifies the \fBbdd\fP node \fIBddOff\fP with
-\fIBddDc\fP, in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-The \fBbdd\fP node \fIBddDc\fP must be included imperatively
-in the off-set part of the \fBbdd\fP node \fIBddOff\fP.
-.br
-.SH RETURN VALUE
-\fBsimpbddnodedcoff\fP returns the simplified \fBbdd\fP node.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddOff;
-   bddnode    \(**BddDc;
-   bddnode    \(**BddNode;
-   chain_list \(**Expr;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   Expr = createablbinexpr( ABL_OR,
-                            createablatom( "i0" ),
-                            createablatom( "i1" ) );
-   BddOff = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   Expr = createablbinexpr( ABL_NOR,
-                            createablatom( "i0" ),
-                            createablatom( "i1" ) );
-   BddDc = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   BddNode = simpbddnodedcoff( (bddsystem \(**)0, BddOff, BddDc );
-   Expr = convertbddcircuitabl( BddCircuit, BddNode );
-   /* displays '1' */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/simpbddnodedcon.3 b/alliance/share/man/man3/simpbddnodedcon.3
deleted file mode 100644
index 8af11922..00000000
--- a/alliance/share/man/man3/simpbddnodedcon.3
+++ /dev/null
@@ -1,80 +0,0 @@
-.\"   $Id: simpbddnodedcon.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)simpbddnodedcon.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH SIMPBDDNODEDCON 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-simpbddnodedcon \- simplifies a \fBbdd\fP with don't cares on its on-set part.
-
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddnode \(**simpbddnodedcon( BddSystem, BddOn, BddDc )
-  bddsystem \(**BddSystem;
-  bddnode   \(**BddOn;
-  bddnode   \(**BddDc;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIBddOn\fP
-The first \fBbdd\fP node.
-.TP
-\fIBddDc\fP
-The second \fBbdd\fP node.
-.SH DESCRIPTION
-\fBsimpbddnodedcon\fP simplifies the \fBbdd\fP node \fIBddOn\fP with
-\fIBddDc\fP, in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-The \fBbdd\fP node \fIBddDc\fP must be included imperatively
-in the on-set part of the \fBbdd\fP node \fIBddOn\fP.
-.br
-.SH RETURN VALUE
-\fBsimpbddnodedcon\fP returns the simplified \fBbdd\fP node.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddOn;
-   bddnode    \(**BddDc;
-   bddnode    \(**BddNode;
-   chain_list \(**Expr;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   Expr = createablbinexpr( ABL_OR,
-                            createablatom( "i0" ),
-                            createablatom( "i1" ) );
-   BddOn = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   Expr = createablbinexpr( ABL_NOR,
-                            createablatom( "i0" ),
-                            createablatom( "i1" ) );
-   BddDc = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   BddNode = simpbddnodedcon( (bddsystem \(**)0, BddOn, BddDc );
-   Expr = convertbddcircuitabl( BddCircuit, BddNode );
-   /* displays '1' */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/simpdupablexpr.3 b/alliance/share/man/man3/simpdupablexpr.3
deleted file mode 100644
index cd4f53b9..00000000
--- a/alliance/share/man/man3/simpdupablexpr.3
+++ /dev/null
@@ -1,52 +0,0 @@
-.\"   $Id: simpdupablexpr.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)simpdupablexpr.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH SIMPDUPABLEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-simpdupablexpr \- duplicates and simplies an expression.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-chain_list \(**simpdupablexpr( Expr )
-  chain_list \(**Expr;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIExpr\fP
-Expression to simplfy.
-.SH DESCRIPTION
-\fBsimpdupablexpr\fP simplifies \fIExpr\fP.
-.br
-.SH RETURN VALUE
-\fBsimpdupablexpr\fP returns a pointer to the simplied expression.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-  chain_list \(**Expr;
-  chain_list \(**ExprSimp;
-  Expr = createablbinexpr( ABL_AND,
-                           createablatom( "'0'" ),
-                           createablatom( "'1'" ) );
-  ExprSimp = simpdupablexpr( Expr );
-  /* displays ('0' and '1')  '0' */
-  viewablexpr( Expr, ABL_VIEW_VHDL );
-  viewablexpr( ExprSimp, ABL_VIEW_VHDL );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1),
-.BR simpdupablexpr(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/simplif10Expr.3 b/alliance/share/man/man3/simplif10Expr.3
deleted file mode 100644
index 1037fc65..00000000
--- a/alliance/share/man/man3/simplif10Expr.3
+++ /dev/null
@@ -1,85 +0,0 @@
-.\"   $Id: simplif10Expr.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)simplif10Expr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH SIMPLIF10EXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBsimplif10Expr\fP \- makes simplifications on an expression including constant atomic expressions
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-chain_list *simplif10Expr(expr)
-chain_list *expr;
-.fi
-.SH PARAMETER
-.TP 20
-\fIexpr\fP
-expression to simplify
-.SH DESCRIPTION
-\fBsimplif10Expr()\fP makes simplifications by applying the following rules :
-.br
-.TP
-(or 0 x1 x2 ... xn) --> (or x1 x2 ... xn)  if n>1
-.TP
-(or 1 x1 x2 ... xn) --> 1 
-.TP
-(or 0 x1) --> x1
-.TP
-(and 0 x1 x2 ... xn) --> 0 
-.TP
-(and 1 x1 x2 ... xn) --> (and x1 x2 ... xn)  if n>1
-.TP
-(and 1 x1) --> x1
-.TP
-(nor 0 x1 x2 ... xn) --> (nor x1 x2 ... xn)  if n>1
-.TP
-(nor 1 x1 x2 ... xn) --> 0 
-.TP
-(nor 0 x1) --> (not x1)
-.TP
-(nand 0 x1 x2 ... xn) --> 1 
-.TP
-(nand 1 x1 x2 ... xn) --> (nand x1 x2 ... xn)  if n>1
-.TP
-(nand 1 x1) --> (not x1)
-.TP
-(xor 0 x1 x2 ... xn) --> (xor x1 x2 ... xn)  if n>1
-.TP
-(xor 1 x1 x2 ... xn) --> (not (xor x1 x2 ... xn))  if n>1
-.TP
-(xor 1 x1) --> (not x1)
-.TP
-(xor 0 x1) --> x1
-.TP
-(not 1) --> 0
-.TP
-(not 0) --> 1
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr1,*expr2; 
-
-/* let's suppose that expr1 = (OR (OR 1 (NOT a)) (NAND 0 (NOT b))) */
-
-expr2 = simplif10Expr(expr1); 
-displayExpr(expr2);
-/* it will display
-1
-*/
-freeExpr(expr1);
-freeExpr(expr2);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR simplifNotExpr (3),
-.BR devXorExpr (3),
-.BR devXor2Expr (3),
-.BR notExpr (3),
-.BR flatPolarityExpr (3),
-.BR flatArityExpr (3),
-.BR sortExpr(3),
-.BR normExpr(3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/simplifDcOneBdd.3 b/alliance/share/man/man3/simplifDcOneBdd.3
deleted file mode 100644
index d29eeb5d..00000000
--- a/alliance/share/man/man3/simplifDcOneBdd.3
+++ /dev/null
@@ -1,50 +0,0 @@
-.\"   $Id: simplifDcOneBdd.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)simplifDcZeroBdd.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH SIMPLIFDCONEBDD 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBsimplifDcOneBdd\fP \- simplifies a BDD with don't cares on its on-set part
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-pNode simplifDcOneBdd(pBdd1,pBdd2)
-pNode pBdd1;
-pNode pBdd2;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIpBdd1\fP
-BDD to simplify
-.TP 20
-\fIpBdd2\fP
-"don't care" function
-.SH DESCRIPTION
-\fBsimplifDcOneBdd()\fP simplifies \fIpBdd1\fP with \fIpBdd2\fP. \fIpBdd2\fP must be included imperatively in the on-set part of pBdd1. This function returns a BDD that depends to the order of the BDD. 
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-pNode nodeA,nodeB;
-pNode res,res1,res2;
-
-initializeBdd(SMALL_BDD);
-nodeA = createNodeTermBdd(3);
-nodeB = createNodeTermBdd(3);
-res1 = applyBinBdd(XOR,nodeA,nodeB);		/* res1 = (XOR a b) */
-res2 = applyBinBdd(AND,notBdd(nodeA),nodeB);	/* res2 = (AND (not a) b) */
-res = simplifDcOneBdd(res1,res2);	/* res1 and res2 = res2 */
-
-/* res = (AND a (not b)) */
-	
-destroyBdd(1);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR simplifDcZeroBdd (3),
-.BR constraintBdd (3),
-.BR composeBdd (3),
-.BR upVarBdd (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/simplifDcZeroBdd.3 b/alliance/share/man/man3/simplifDcZeroBdd.3
deleted file mode 100644
index ad41035f..00000000
--- a/alliance/share/man/man3/simplifDcZeroBdd.3
+++ /dev/null
@@ -1,57 +0,0 @@
-.\"   $Id: simplifDcZeroBdd.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)simplifDcZeroBdd.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH SIMPLIFDCZEROBDD 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBsimplifDcZeroBdd\fP \- simplifies a BDD with don't cares on its off-set part
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-pNode simplifDcZeroBdd(pBdd1,pBdd2)
-pNode pBdd1;
-pNode pBdd2;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIpBdd1\fP
-BDD to simplify
-.TP 20
-\fIpBdd2\fP
-"don't care" function
-.SH DESCRIPTION
-\fBsimplifDcZeroBdd()\fP simplifies \fIpBdd1\fP with \fIpBdd2\fP. \fIpBdd2\fP must be included imperatively in the off-set part of pBdd1. This function returns a BDD that depends to the order of the BDD.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-pNode nodeA,NodeB;
-pNode res,res1,res2;
-
-initializeBdd(SMALL_BDD);
-nodeA = createNodeTermBdd(3);
-nodeB = createNodeTermBdd(3);
-res1 = applyBinBdd(OR,nodeA,nodeB);	/* res1 = (OR a b) */
-res2 = applyBinBdd(NOR,nodeA,nodeB);	/* res2 = (NOR a b) */
-res = simplifDcZeroBdd(res1,res2);	/* res1 and res2 = 0 */
-displayBdd(res,1);
-
-/* it will display 
-@res   ONE 
-*/
-	
-destroyBdd(1);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR simplifDcOneBdd (3),
-.BR applyBdd (3),
-.BR notBdd (3),
-.BR constraintBdd (3),
-.BR applyBinBdd (3),
-.BR addListBdd (3),
-.BR displayBdd (3),
-.BR createNodeTermBdd (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/simplifNotExpr.3 b/alliance/share/man/man3/simplifNotExpr.3
deleted file mode 100644
index f833317f..00000000
--- a/alliance/share/man/man3/simplifNotExpr.3
+++ /dev/null
@@ -1,51 +0,0 @@
-.\"   $Id: simplifNotExpr.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)simplifNotExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH SIMPLIFNOTEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBsimplifNotExpr\fP \- makes simplifications on an expression including inverters
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-chain_list *simplifNotExpr(expr)
-chain_list *expr;
-.fi
-.SH PARAMETER
-.TP 20
-\fIexpr\fP
-expression to simplify
-.SH DESCRIPTION
-\fBsimplifNotExpr()\fP makes simplifications by applying the following rule :
-.br
-.TP
-(not (not a)) --> a
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr1,*expr2; 
-
-/* let's suppose that expr1 = (OR (NOT (NOT a)) (NOT (NOT (NOT b)))) */
-
-expr2 = simplifNotExpr(expr1); 
-displayExpr(expr2);
-/* it will display
-(OR a (NOT b))
-*/
-freeExpr(expr1);
-freeExpr(expr2);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR simplifExpr10 (3),
-.BR devXorExpr (3),
-.BR devXor2Expr (3),
-.BR notExpr (3),
-.BR flatPolarityExpr (3),
-.BR flatArityExpr (3),
-.BR sortExpr(3),
-.BR normExpr(3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/sortExpr.3 b/alliance/share/man/man3/sortExpr.3
deleted file mode 100644
index 902d9eb3..00000000
--- a/alliance/share/man/man3/sortExpr.3
+++ /dev/null
@@ -1,61 +0,0 @@
-.\"   $Id: sortExpr.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)sortExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH SORTEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBsortExpr\fP \- sorts an expression 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-void sortExpr(expr,func,direction)
-chain_list *expr;
-int (*func)();
-int direction;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIexpr\fP
-expression to sort
-.TP 20
-\fIfunc\fP
-integer function
-.TP 20
-\fIdirection\fP
-increasing or discreasing direction
-.SH DESCRIPTION
-\fBsortExpr()\fP sorts recursively the arguments of an expression by using a integer function \fIfunc()\fP. If \fIdirection = 1\fP then the arguments are sorted in increasing order.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr1,*expr2; 
-expr1 = createExpr(OR);
-addQExpr(expr1,createAtom("a"));
-addQExpr(expr1,createAtom("b"));
-expr2 = createExpr(AND);
-addQExpr(expr2,createAtom("c"));
-addQExpr(expr2,createAtom("d"));
-addQExpr(expr1,expr2);
-displayExpr(expr1);
-sortExpr(expr1,numberAtomExpr,0);
-displayExpr(expr1);
-/* it will display
-(OR a b (AND c d))
-(OR (AND c d) a b)
-*/
-freeExpr(expr1);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR maxExpr (3),
-.BR minExpr (3),
-.BR copyExpr (3),
-.BR substExpr (3),
-.BR substPhyExpr (3),
-.BR flatArityExpr (3),
-.BR flatPolarityExpr (3),
-.BR normExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/sortautarray.3 b/alliance/share/man/man3/sortautarray.3
deleted file mode 100644
index 889d1cde..00000000
--- a/alliance/share/man/man3/sortautarray.3
+++ /dev/null
@@ -1,88 +0,0 @@
-.\"   $Id: sortautarray.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)sortautarray.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH SORTAUTARRAY 3 "October 1, 1997" "ASIM/LIP6" "AUT FUNCTIONS"
-.SH NAME
-sortautarray \- heap sort.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-void sortautarray( ValueArray, IndexArray, ArraySize, FuncCompare )
-  void  \(**ValueArray;
-  long  \(**IndexArray;
-  long   ArraySize;
-  long (\(**FuncCompare)();
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIValueArray\fP
-Array of values to be compared.
-.TP
-\fIIndexArray\fP
-Array of indexes.
-.TP
-\fIArraySize\fP
-Size of the arrays.
-.TP
-\fIFuncCompare\fP
-The name of the comparison function.
-.SH DESCRIPTION
-\fBsortautarray\fP is an implementation of the heap-sort algorithm.
-It sorts an array of values pointed by \fIValueArray\fP, and saves the
-values order in the array of indexes pointed by \fIIndexArray\fP.
-The comparison function is called with three arguments. The First is
-a pointer to the  array of values, the second one and the last one is 
-respectively the index of the first and second value being compared.
-If \fIFuncCompare\fP is a null pointer, a default comparison function
-is used and sort \fIValueArray\fP in decrease order.
-\fIValueArray\fP is not modified by this function, and this seems to
-be usefull in many cases. A the end \fIIndexArray\fP contains the 
-indexes of the sorted values.
-.br
-.SH RETURN VALUE
-\fBsortautarray\fP returns nothing.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "aut101.h"
-  long SortCompare( ValueArray, Index1, Index2 )
-    long \(**ValueArray;
-    long  Index1;
-    long  Index2;
-  {
-    return( ValueArray[ Index2 ] - ValueArray[ Index1 ] );
-  }
-  ...
-  long ValueArray[ 5 ] = { 3, 2, 1, 5, 4 };
-  long IndexArray[ 5 ];
-  sortautarray( ValueArray, IndexArray, 5, NULL );
-  /* display 5 4 3 2 1 */
-  for ( Counter = 0; Counter < 5; Counter++ )
-  {
-    printf( " %d", ValueArray[ IndexArray[ Counter ] ] );
-  }
-  printf( "\n" );
-  sortautarray( ValueArray, IndexArray, SortCompare );
-  /* display 1 2 3 4 5 */
-  for ( Counter = 0; Counter < 5; Counter++ )
-  {
-    printf( " %d", ValueArray[ IndexArray[ Counter ] ] );
-  }
-  printf( "\n" );
-.ft R
-.fi
-.SH SEE ALSO
-.BR aut (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/sortlocon.3 b/alliance/share/man/man3/sortlocon.3
deleted file mode 100644
index 3c27c8d8..00000000
--- a/alliance/share/man/man3/sortlocon.3
+++ /dev/null
@@ -1,71 +0,0 @@
-.\"   $Id: sortlocon.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)sortlocon.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-sortlocon
-.XE
-.XS2 \n%
-.ti 0.2i
-sortlocon
-.XE2 \}
-.TH SORTLOCON 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL FUNCTIONS"
-.SH NAME
-sortlocon \- sort the logical connectors of a figure by name
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo412.h"
-void sortlocon(connectors)
-locon_list \(**\(**connectors;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIconnectors\fP
-Pointer to the head of the connector list that is to be sorted
-.SH DESCRIPTION
-\fBsortlocon\fP sorts the list of logical connectors pointed to
-by \fI\(**connectors\fP.
-The connectors are sorted by names, using a numerical comparison function
-that ensures \fBx_12 > x_2\fP.
-.br
-The standart \fBqsort\fP(3) function library is called for sorting.
-Therefore, a table the number of connectors wide is created.
-This is not very memory consuming since the number of connectors in a circuit
-interface is quite small, nor very time consuming since this algorithm runs
-in a n log n time.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo412.h"
-void savesorted(figname)
-char \(**figname;
-{
-lofig_list \(**figure = getlocon(figname, 'A');
-  sortlocon(&figure->LOCON);
-  sortlosig(&figure->LOSIG);
-  savelofig(figure);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR locon (3),
-.BR addlocon (3),
-.BR dellocon (3),
-.BR checkloconorder (3),
-.BR qsort (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/sortlosig.3 b/alliance/share/man/man3/sortlosig.3
deleted file mode 100644
index fa198972..00000000
--- a/alliance/share/man/man3/sortlosig.3
+++ /dev/null
@@ -1,74 +0,0 @@
-.\"   $Id: sortlosig.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)sortlosig.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-sortlosig
-.XE
-.XS2 \n%
-.ti 0.2i
-sortlosig
-.XE2 \}
-.TH SORTLOSIG 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL FUNCTIONS"
-.SH NAME
-sortlosig \- sort the logical signals of a figure by name
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo412.h"
-void sortlosig(signals)
-losig_list \(**\(**signals;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fI\(**\(**signals\fP
-Pointer to the head of the list of signals that is to be sorted
-.SH DESCRIPTION
-\fBsortlosig\fP sorts the list of signals pointed to by \fIsignals\fP.
-The signals are sorted by names, but since names are not the signals
-identifier, the \fBgetsigname\fP(3) routine is called to retrieve a
-signal name.
-.br
-The standart \fBqsort\fP(3) function library is called for sorting.
-Therefore, a table the number of signal wide is created, requiring
-a lot of memory with big circuits.
-Also, even if \fBqsort\fP(3) runs in n log n time, \fBgetsigname\fP(3)
-is called twice, and the natural comparison function once, and this is
-quite time consuming with big circuits.
-It is recommended to use this function only if needed.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo412.h"
-void savesorted(figname)
-char \(**figname;
-{
-lofig_list \(**figure = getlosig(figname, 'A');
-  sortlocon(&figure->LOCON);
-  sortlosig(&figure->LOSIG);
-  savelofig(figure);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR losig (3),
-.BR addlosig (3),
-.BR dellosig (3),
-.BR getsigname (3),
-.BR sortlocon (3),
-.BR qsort (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/substExpr.3 b/alliance/share/man/man3/substExpr.3
deleted file mode 100644
index 25814aa1..00000000
--- a/alliance/share/man/man3/substExpr.3
+++ /dev/null
@@ -1,60 +0,0 @@
-.\"   $Id: substExpr.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)substExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH SUBSTEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBsubstExpr\fP \- copies an expression by substituting a given atom by an expression
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-chain_list *substExpr(expr1,name,expr2)
-chain_list *expr1;
-char *name;
-chain_list *expr2;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIexpr1\fP
-expression to copy
-.TP 20
-\fIname\fP
-name to substitute
-.TP 20
-\fIexpr2\fP
-expression  that will remplace \fIname\fP
-.SH DESCRIPTION
-\fBsubstExpr()\fP creates a new ABL by copying \fIexpr1\fP in wich each occurence of \fIname\fP is replaced by \fIexpr2\fP. \fIexpr2\fP is only copied, therefore it's possible to free it.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr1,*expr2,*expr3; 
-expr1 = createExpr(OR);
-addQExpr(expr1,createAtom("a"));
-addQExpr(expr1,createAtom("b"));
-expr2 = notExpr(createAtom("x"));
-expr3 = substExpr(expr1,"a",expr2);
-displayExpr(expr1);
-displayExpr(expr3);
-/* it will display
-(OR a b)
-(OR (NOT x) b)
-*/
-freeExpr(expr1);
-freeExpr(expr2);
-freeExpr(expr3);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR substPhyExpr (3),
-.BR copyExpr (3),
-.BR flatArityExpr (3),
-.BR flatPolarityExpr (3),
-.BR maxExpr (3),
-.BR minExpr (3),
-.BR sortExpr (3),
-.BR normExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/substPhyExpr.3 b/alliance/share/man/man3/substPhyExpr.3
deleted file mode 100644
index 663202e2..00000000
--- a/alliance/share/man/man3/substPhyExpr.3
+++ /dev/null
@@ -1,57 +0,0 @@
-.\"   $Id: substPhyExpr.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)substPhyExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH SUBSTPHYEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBsubstPhyExpr\fP \- substitutes an atomic expression by an expression within an operator expression 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-void substPhyExpr(expr1,name,expr2)
-chain_list *expr1;
-char *name;
-chain_list *expr2;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIexpr1\fP
-expression on wich the susbstition will be made
-.TP 20
-\fIname\fP
-name to substitute
-.TP 20
-\fIexpr2\fP
-expression  that will remplace \fIname\fP
-.SH DESCRIPTION
-\fBsubstPhyExpr()\fP replaces each occurence of \fIname\fP within \fIexpr1\fP by \fIexpr2\fP.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr1,*expr2; 
-expr1 = createExpr(OR);
-addQExpr(expr1,createAtom("a"));
-addQExpr(expr1,createAtom("b"));
-expr2 = notExpr(createAtom("x"));
-substPhyExpr(expr1,"a",expr2);
-displayExpr(expr1);
-/* it will display
-(OR (NOT x) b)
-*/
-freeExpr(expr1);
-freeExpr(expr2);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR substExpr (3),
-.BR copyExpr (3),
-.BR flatArityExpr (3),
-.BR flatPolarityExpr (3),
-.BR maxExpr (3),
-.BR minExpr (3),
-.BR sortExpr (3),
-.BR normExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/substablexpr.3 b/alliance/share/man/man3/substablexpr.3
deleted file mode 100644
index 83ea1073..00000000
--- a/alliance/share/man/man3/substablexpr.3
+++ /dev/null
@@ -1,64 +0,0 @@
-.\"   $Id: substablexpr.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)substablexpr.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH SUBSTABLEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-substablexpr \- substitutes a given atom by an expression.
-
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-chain_list \(**substablexpr( Expr1, Name, Expr2 )
-  chain_list \(**Expr1;
-  char       \(**Name;
-  chain_list \(**Expr2;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIExpr1\fP
-First expression.
-.TP
-\fIName\fP
-Atom name.
-.TP
-\fIExpr\fP
-Second expression.
-.SH DESCRIPTION
-\fBsubstablexpr\fP substitutes \fIAtom\fP in \fIExpr1\fP by \fIExpr2\fP.
-The expression pointer \fIExpr1\fP MUSTN'T be used after the call to this function.
-.br
-.SH RETURN VALUE
-\fBsubstablexpr\fP returns the modified expression.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-  chain_list \(**Expr1;
-  chain_list \(**Expr2;
-  Expr1 = createablbinexpr( ABL_OR,
-                            createablatom( "a" ),
-                            createablatom( "b" ) );
-  Expr2 = createablbinexpr( ABL_AND,
-                            createablatom( "c" ),
-                            createablatom( "d" ) );
-  Expr1 = substablexpr( Expr1, "a", Expr2 );
-  /* displays ((c and d) or b) */
-  viewablexpr( Expr1, ABL_VIEW_VHDL );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1),
-.BR substdupablexpr(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/substbddnodeassoc.3 b/alliance/share/man/man3/substbddnodeassoc.3
deleted file mode 100644
index a47e5342..00000000
--- a/alliance/share/man/man3/substbddnodeassoc.3
+++ /dev/null
@@ -1,106 +0,0 @@
-.\"   $Id: substbddnodeassoc.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)substbddnodeassoc.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH SUBSTBDDNODEASSOC 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-substbddnodeassoc \- substitutes a set of variables with a set of \fBbdd\fP node.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddnode \(**substbddnodeassoc( BddSystem, BddNode, BddAssoc )
-  bddsystem \(**BddSystem;
-  bddnode   \(**BddNode;
-  bddassoc  \(**BddAssoc;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIBddNode\fP
-The \fBbdd\fP node to treat.
-.TP
-\fIBddAssoc\fP
-The variable association.
-.SH DESCRIPTION
-\fBsubstbddnodeassoc\fP substitutes in the \fBbdd\fP node \fIBddNode\fP
-all the variables associated to something in the variable association
-\fIBddAssoc\fP, with the corresponding \fBbdd\fP node,
-in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBsubstbddnodeassoc\fP returns the computed \fBbdd\fP node.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"variable xxx out of range, error !"
-.ft R
-.RS
-The \fIVariable\fP parameter must be less or equal to
-the \fIBddSystem->NUMBER_VAR\fP field.
-.RE
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"bad variable association xxx, error !"
-.ft R
-.RS
-The \fIBddAssoc\fP parameter must a valid variable association.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   bddnode    \(**BddSubst;
-   bddnode    \(**BddVariable;
-   bddassoc   \(**Assoc;
-   chain_list \(**Expr;
-   bddvar         Variable;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   Expr = createablbinexpr( ABL_AND,
-                            createablatom( "i0" ),
-                            createablatom( "i1" ) );
-   BddNode = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   Expr = createablbinexpr( ABL_OR,
-                            createablatom( "i2" ),
-                            createablatom( "i3" ) );
-   BddSubst = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   BddVariable = searchbddcircuitin( (bddcircuit \(**)0, "i0" );
-   Variable = getbddvarbyindex( (bddsystem \(**)0, BddVariable->INDEX );
-   Assoc = addbddassoc( (bddsystem \(**)0 );
-   addbddnodeassoc( (bddsystem \(**)0, Assoc, Variable, BddSubst );
-   BddNode = substbddnodeassoc( (bddsystem \(**)0, BddSubst, Assoc );
-   Expr = convertbddcircuitabl( BddCircuit, BddNode );
-   /* displays ((i3 or i2) and i1) */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddassoc( (bddsystem \(**)0 );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/substdupablexpr.3 b/alliance/share/man/man3/substdupablexpr.3
deleted file mode 100644
index 095147ab..00000000
--- a/alliance/share/man/man3/substdupablexpr.3
+++ /dev/null
@@ -1,64 +0,0 @@
-.\"   $Id: substdupablexpr.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)substdupablexpr.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH SUBSTDUPABLEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-substdupablexpr \- substitutes a given atom by an expression.
-
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-chain_list \(**substdupablexpr( Expr1, Name, Expr2 )
-  chain_list \(**Expr1;
-  char       \(**Name;
-  chain_list \(**Expr2;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIExpr1\fP
-First expression.
-.TP
-\fIName\fP
-Atom name.
-.TP
-\fIExpr\fP
-Second expression.
-.SH DESCRIPTION
-\fBsubstdupablexpr\fP duplicates and substitutes \fIAtom\fP in \fIExpr1\fP by \fIExpr2\fP.
-.br
-.SH RETURN VALUE
-\fBsubstdupablexpr\fP returns the duplicated and modified expression.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-  chain_list \(**Expr1;
-  chain_list \(**Expr2;
-  chain_list \(**Expr3;
-  Expr1 = createablbinexpr( ABL_OR,
-                            createablatom( "a" ),
-                            createablatom( "b" ) );
-  Expr2 = createablbinexpr( ABL_AND,
-                            createablatom( "c" ),
-                            createablatom( "d" ) );
-  Expr3 = substdupablexpr( Expr1, "a", Expr2 );
-  /* displays ((c and d) or b) */
-  viewablexpr( Expr1, ABL_VIEW_VHDL );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1),
-.BR substablexpr(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/supportChain_listBdd.3 b/alliance/share/man/man3/supportChain_listBdd.3
deleted file mode 100644
index e073492a..00000000
--- a/alliance/share/man/man3/supportChain_listBdd.3
+++ /dev/null
@@ -1,65 +0,0 @@
-.\"   $Id: supportChain_listBdd.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)supportChain_listBdd.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH SUPPORTCHAIN_LISTBDD 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBsupportChain_listBdd\fP \- returns a chained list of nodes that are used in a given BDD. 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-chain_list *supportChain_listBdd(pBdd)
-pNode pBdd;
-.fi
-.SH PARAMETER
-.TP 20
-\fIpBdd\fP
-BDD
-.SH DESCRIPTION
-\fBsupportChain_listBdd()\fP creates a chained list in wich all the nodes of \fIpBdd\fP are represented.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-pNode nodeA,nodeB,nodeC;
-pNode res;
-chain_list *pt;
-
-initializeBdd(SMALL_BDD);
-nodeA = createNodeTermBdd(3);
-nodeB = createNodeTermBdd(3);
-nodeC = createNodeTermBdd(4);
-pt = NULL;
-pt = addListBdd(pt,nodeA);
-pt = addListBdd(pt,nodeB);
-pt = addListBdd(pt,nodeC);
-res = applyBdd(OR,pt);
-pt = supportChain_listBdd(res);
-
-while (pt)
-   {
-   printf("--- ");
-   displayBdd((pNode) pt->DATA,0);	/* displays the node */
-   pt = pt->NEXT;
-   }
-/* it will display 
-
---- @nodeA   index = 2  LOW = ZERO    HIGH = ONE
---- @inter   index = 3  LOW = @nodeA  HIGH = ONE
---- @res     index = 4  LOW = @inter  HIGH = ONE
-*/
-	
-destroyBdd(1);
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR numberNodeBdd (3),
-.BR addListBdd (3),
-.BR notBdd (3),
-.BR constraintBdd (3),
-.BR composeBdd (3),
-.BR displayBdd (3),
-.BR createNodeTermBdd (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/supportChain_listExpr.3 b/alliance/share/man/man3/supportChain_listExpr.3
deleted file mode 100644
index ea365527..00000000
--- a/alliance/share/man/man3/supportChain_listExpr.3
+++ /dev/null
@@ -1,47 +0,0 @@
-.\"   $Id: supportChain_listExpr.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)supportChain_listExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH SUPPORTCHAIN_LISTEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBsupportChain_listExpr\fP \- returns the support of an expression in a \fIchain_list\fP.
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-chain_list *supportChain_listExpr(expr)
-chain_list *expr;
-.fi
-.SH PARAMETER
-.TP 20
-\fIexpr\fP
-expression
-.SH DESCRIPTION
-\fBsupportChain_listExpr()\fP creates a \fIchain_list\fP wich contains all the atoms appearing in \fIexpr\fP. Each atom in \fIchain_list\fP appears only once in it.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr; 
-chain_list *pt;
-expr = createExpr(OR);
-addQExpr(expr,createAtom("a"));
-addQExpr(expr,createAtom("b"));
-addQExpr(expr,createAtom("a"));
-pt = supportChain_listExpr(expr);
-while (pt)
-   {
-   printf("%s ",pt->DATA);
-   pt = pt->NEXT;
-   }
-/* it will display
-a b
-*/
-freeExpr(expr);
-freechain(pt);		/* mbk function */
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR supportPtype_listExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/supportPtype_listExpr.3 b/alliance/share/man/man3/supportPtype_listExpr.3
deleted file mode 100644
index a4a7b388..00000000
--- a/alliance/share/man/man3/supportPtype_listExpr.3
+++ /dev/null
@@ -1,47 +0,0 @@
-.\"   $Id: supportPtype_listExpr.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)supportPtype_listExpr.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH SUPPORTPTYPE_LISTEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBsupportPtype_listExpr\fP \- returns the support of an expression in a \fIptype_list\fP.
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-ptype_list *supportPtype_listExpr(expr)
-chain_list *expr;
-.fi
-.SH PARAMETER
-.TP 20
-\fIexpr\fP
-expression
-.SH DESCRIPTION
-\fBsupportPtype_listExpr()\fP creates a \fIptype_list\fP wich contains all the atoms appearing in \fIexpr\fP. Each atom in \fIchain_list\fP appears only once in it.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr; 
-ptype_list *pt;
-expr = createExpr(OR);
-addQExpr(expr,createAtom("a"));
-addQExpr(expr,createAtom("b"));
-addQExpr(expr,createAtom("a"));
-pt = supportPtype_listExpr(expr);
-while (pt)
-   {
-   printf("%s ",pt->DATA);
-   pt = pt->NEXT;
-   }
-/* it will display
-a b
-*/
-freeExpr(expr);
-freeptype(pt);		/* mbk function */
-.fi
-.SH SEE ALSO
-.BR log (1),
-.BR abl (1),
-.BR supportChain_listExpr (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/swapbddvar.3 b/alliance/share/man/man3/swapbddvar.3
deleted file mode 100644
index 15b778c0..00000000
--- a/alliance/share/man/man3/swapbddvar.3
+++ /dev/null
@@ -1,67 +0,0 @@
-.\"   $Id: swapbddvar.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)swapbddvar.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH SWAPBDDVAR 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-swapbddvar \- swaps two contiguous variables.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-void swapbddvar( BddSystem, Variable )
-  bddsystem \(**BddSystem;
-  bddvar     Variable;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIVariable\fP
-The variable to swap.
-.SH DESCRIPTION
-\fBswapbddvar\fP swaps the variable number \fIVariable\fP with
-the variable number \fIVariable\fP + 1, in the \fBbdd\fP system \fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-This function is usefull for the \fBbdd\fP nodes reordering.
-.br
-.SH RETURN VALUE
-\fBswapbddvar\fP returns nothing.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"variable xxx out of range, error !"
-.ft R
-.RS
-The \fIVariable\fP and \fIVariable\fP + 1, must be valid variables number. 
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddnode    \(**BddNode1;
-   bddnode    \(**BddNode2;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddNode1 = addbddvar( (bddsystem \(**)0, 0 );
-   BddNode2 = addbddvar( (bddsystem \(**)0, 0 );
-   swapbddvar( (bddsystem \(**)0, 0 );
-   destroybddsystem( (bddsystem \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/testbddcircuit.3 b/alliance/share/man/man3/testbddcircuit.3
deleted file mode 100644
index f250ae23..00000000
--- a/alliance/share/man/man3/testbddcircuit.3
+++ /dev/null
@@ -1,54 +0,0 @@
-.\"   $Id: testbddcircuit.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)testbddcircuit.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH TESTBDDCIRCUIT 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-testbddcircuit \- debugs a \fBbdd\fP circuit.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-int testbddcircuit( BddCircuit )
-  bddcircuit \(**BddCircuit;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddCircuit\fP
-The \fBbdd\fP circuit to debug.
-.SH DESCRIPTION
-\fBtestbddcircuit\fP calls a debugger of \fIBddCircuit\fP.
-If a null pointer is given, the default \fBbdd\fP circuit is used.
-This function provides a multiple commands to debug all the
-functions include in this \fBbdd\fP package.
-.br
-.SH RETURN VALUE
-\fBtestbddcircuit\fP returns 0 if the debugger is interrupt by user, and 1 otherwise.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   ...
-   testbddcircuit( (bddcircuit \(**)0 );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/unflatablexpr.3 b/alliance/share/man/man3/unflatablexpr.3
deleted file mode 100644
index 9d6f9a1e..00000000
--- a/alliance/share/man/man3/unflatablexpr.3
+++ /dev/null
@@ -1,54 +0,0 @@
-.\"   $Id: unflatablexpr.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)unflatablexpr.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH UNFLATABLEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-unflatablexpr \- unflats the operators of an expression
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-void unflatablexpr( Expr )
-  chain_list \(**Expr;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIExpr\fP
-Expression to unflat.
-.SH DESCRIPTION
-\fBunflatablexpr\fP modifies all the operators in \fIExpr\fP in order
-to have exclusively binary or unary operators.
-.br
-.SH RETURN VALUE
-\fBunflatablexpr\fP returns the modified expression.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-  chain_list \(**Expr1;
-  chain_list \(**Expr2;
-  Expr1 = createbinexpr( ABL_OR, 
-                         createablatom( "a" ),
-                         createablatom( "b" ) );
-  addablqexpr( Expr1, createablatom( "c" ) );
-  Expr2 = unflatablexpr( dupablexpr( Expr1 ) );
-  /* displays ((a or b) or c) (a or b or c) */
-  viewablexpr( Expr2, ABL_VIEW_VHDL );
-  viewablexpr( Expr1, ABL_VIEW_VHDL );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1),
-.BR ununflatablexpr(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/unflattenlofig.3 b/alliance/share/man/man3/unflattenlofig.3
deleted file mode 100644
index 3d442f91..00000000
--- a/alliance/share/man/man3/unflattenlofig.3
+++ /dev/null
@@ -1,97 +0,0 @@
-.\"   $Id: unflattenlofig.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)unflattenlofig.2 2.11 92/10/01 ; Labo masi cao-vlsi; Author : Francois Nacabal
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-unflattenlofig
-.XE
-.XS3 \n%
-.ti 0.2i
-unflattenlofig
-.XE3 \}
-.TH UNFLATTENLOFIG 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL UTILITY FUNCTIONS"
-.SH NAME
-unflattenlofig \- creates a hierarchy level from instances of a figure 
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo412.h"
-void unflattenlofig(ptfig, figname, insname, list)
-lofig_list \(**ptfig;
-char \(**figname;
-char \(**insname;
-chain_list \(**list;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIptfig\fP
-Pointer to a logical figure
-.TP
-\fIfigname\fP
-Name of the new figure (model)
-.TP
-\fIinsname\fP
-Instance name of the new figure
-.TP
-\fIlist\fP
-Pointer to the head of a chain_list, containing instance pointers
-.SH DESCRIPTION
-\fBunflattenlofig\fP creates a new figure, \fIfigname\fP, containing the
-instances listed in \fIlist\fP, and adds it in the figure pointed to by
-\fIptfig\fP, with the name \fIinsname\fP. 
-.br
-All the terminals of the new figure are called using the name of the
-corresponding signal if it exists, or with the name of a connector
-connected to this signal.
-The new name is suffixed with a number, obtained with an internal counter,
-in order to ensure that names are differents.
-.SH ERRORS
-No errors can directly result from a call to \fBunflattenlofig\fP, but since it
-uses many other mbk functions, it may be a good error starting point.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo412.h"
-{
- lofig_list *lofig;
- chain_list *list = NULL;
- lofig = getlofig ( "rootfig", 'A');
- list = addchain (list, (void *)getloins (lofig, "nan0");
- list = addchain (list, (void *)getloins (lofig, "nor2");
- unflattenlofig ( lofig, "newfig", "newins", list);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR mbkenv (3),
-.BR lofig (3),
-.BR getlofig (3),
-.BR addlofig (3),
-.BR addloins (3),
-.BR delloins (3),
-.BR addlocon (3),
-.BR addlosig (3),
-.BR dellosig (3),
-.BR getsigname (3),
-.BR lofigchain (3),
-.BR getptype (3),
-.BR addptype (3),
-.BR delptype (3),
-.BR addchain (3),
-.BR freechain (3),
-.BR reverse (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/unmarkbddnode.3 b/alliance/share/man/man3/unmarkbddnode.3
deleted file mode 100644
index 52ab8612..00000000
--- a/alliance/share/man/man3/unmarkbddnode.3
+++ /dev/null
@@ -1,70 +0,0 @@
-.\"   $Id: unmarkbddnode.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)unmarkbddnode.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH UNMARKBDDNODE 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-unmarkbddnode \- unmarks \fBbdd\fP node with a specified mask.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-long unmarkbddnode( BddSystem, BddNode, Mark )
-  bddsystem \(**BddSystem;
-  bddnode   \(**BddNode;
-  bddunmark    Mark;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIBddNode\fP
-The \fBbdd\fP node to unmark.
-.TP
-\fIMark\fP
-The bit mask.
-.SH DESCRIPTION
-\fBunmarkbddnode\fP unmarks the \fBbdd\fP node \fIBddNode\fP
-with the bit mask \fIMark\fP, in the \fBbdd\fP system BddSystem.
-If a null pointer is given, the default \fBbdd\fP system is used.
-This function does a AND with the field MARK of the \fBbdd\fP node \fIBddNode\fP,
-and the complemented bit mask \fIMark\fP.
-.br
-.SH RETURN VALUE
-\fBunmarkbddnode\fP returns the number of the differents unmarked nodes. 
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   chain_list \(**Expr;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   Expr = createablbinexpr( ABL_AND,
-                            createablatom( "i0" ),
-                            createablatom( "i1" ) );
-   BddNode = addbddcircuitabl( BddCircuit, Expr );
-   freeablexpr( Expr );
-   printf( "Number nodes: %ld\n", 
-           markbddnode( (bddsystem \(**)0, BddNode, 0x0001 ) );
-   unmarkbddnode( (bddsystem \(**)0, BddNode, 0x0001 );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/unsetbddrefext.3 b/alliance/share/man/man3/unsetbddrefext.3
deleted file mode 100644
index 0291db03..00000000
--- a/alliance/share/man/man3/unsetbddrefext.3
+++ /dev/null
@@ -1,73 +0,0 @@
-.\"   $Id: unsetbddrefext.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)unsetbddrefext.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH UNSETBDDREFEXT 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-unsetbddrefext \- increments the internal reference,
-and decrements the external reference of a \fBbdd\fP node.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-bddnode \(**unsetbddrefext( BddNode )
-  bddnode \(**BddNode;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddNode\fP
-The \fBbdd\fP node.
-.SH DESCRIPTION
-\fBunsetbddrefext\fP increments the number of internal reference
-of the \fBbdd\fP node \fIBddNode\fP and decrements its number of
-external reference.
-.br
-.SH RETURN VALUE
-\fBunsetbddrefext\fP returns the \fIBddNode\fP pointer.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"negative reference, index xxx error !"
-.ft R
-.RS
-The \fIBddNode\fP must have a postive number of external reference.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   chain_list \(**Expr;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   BddNode = addbddcircuitin( (bddcircuit \(**)0, "i0", 0, BDD_IN_MODE_FIRST );
-   BddNode = addbddnode( (bddsystem \(**)0, BddNode->INDEX, BddNode->LOW, BddNode->HIGH );
-   Expr = convertbddcircuitabl( (bddcircuit \(**)0, BddNode );
-   incbddrefext( BddNode );
-   unsetbddrefext( BddNode );
-   /* displays Node VAR: 0  INDEX: 2  MARK: 0  REF_EXT: 0  REF_INT: 1 */
-   viewbddnode( (bddsystem \(**)0, BddNode );
-   /* displays (not i0) */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/upVarBdd.3 b/alliance/share/man/man3/upVarBdd.3
deleted file mode 100644
index 60f59906..00000000
--- a/alliance/share/man/man3/upVarBdd.3
+++ /dev/null
@@ -1,64 +0,0 @@
-.\"   $Id: upVarBdd.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)upVarBdd.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH UPVARBDD 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBupVarBdd\fP \- brings up an index in a BDD 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-pNode upVarBdd(pBdd,oldIndex,newIndex)
-pNode pBdd;
-short oldIndex,newIndex;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIpBdd\fP
-BDD in wich \fIindex\fP is came up
-.TP 20
-\fIoldIndex\fP
-index to come up
-.TP 20
-\fInewIndex\fP
-new index
-.SH DESCRIPTION
-\fBupVarBdd()\fP constructs a graph obtained by bringing up \fIoldIndex\fP to \fInewIndex\fP. This function is called by the BDDs reordering function.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-pNode nodeA,nodeB;
-pNode res;
-
-initializeBdd(SMALL_BDD);
-nodeA = createNodeTermBdd(3);
-nodeB = createNodeTermBdd(3);
-res = applyBinBdd(OR,nodeA,nodeB);	/* res = (OR a b)
-res = upVarBdd(res,2,4);
-displayBdd(res,1);
-
-/* it will display 
-@res     INDEX 4    LOW = @nodeB     HIGH = ONE 
-@nodeB   INDEX 3    LOW = ZERO       HIGH = ONE 
-*/
-	
-destroyBdd(1);
-.fi
-.SH ERROR
-"upVarBdd : error - newIndex <= oldIndex"
-.br
-The new index must be higher than the old index.
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR applyBdd (3),
-.BR notBdd (3),
-.BR constraintBdd (3),
-.BR composeBdd (3),
-.BR applyBinBdd (3),
-.BR addListBdd (3),
-.BR displayBdd (3),
-.BR createNodeTermBdd (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/upVarCct.3 b/alliance/share/man/man3/upVarCct.3
deleted file mode 100644
index 0a635187..00000000
--- a/alliance/share/man/man3/upVarCct.3
+++ /dev/null
@@ -1,73 +0,0 @@
-.\"   $Id: upVarCct.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)upVarCct.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.TH UPVARCCT 3 "October 1, 1997" "ASIM/LIP6" "BDD functions"
-.so man1/alc_origin.1
-.SH NAME
-\fBupVarCct\fP \- brings up the index of a primary input within a circuit 
-.SH SYNOPSYS
-.nf
-#include "logmmm.h"
-void upVarCct(pC,index1,index2)
-pCircuit pC;
-short index1,index2;
-.fi
-.SH PARAMETERS
-.TP 20
-\fIpC\fP
-Circuit in which the index is bring up 
-.TP 20
-\fIindex1\fP
-old index
-.TP 20
-\fIindex2\fP
-new index
-.SH DESCRIPTION
-\fBupVarCct()\fP brings up \fIindex1\fP back to \fIindex2\fP. this function provides the basic method for the BDD reorder.
-.SH EXAMPLE
-.nf
-#include "mutnnn.h"		/* mbk utilities */
-#include "logmmm.h"
-chain_list *expr;
-pNode res;
-pCircuit pC;
-
-initializeBdd(SMALL_BDD);
-pC = initializeCct("circuit 1",10,10);
-
-addInputCct(pC,"a");
-addInputCct(pC,"b");
-
-addOutputCct(pC,"s",applyBinBdd(XOR,
-                        createNodeTermBdd(searchInputCct(pC,"a")),
-                        createNodeTermBdd(searchInputCct(pC,"b"))));
-
-upVarCct(pC,2,4);
-
-displayCct(pC,1);
-
-/* it will display 
-************* DISPLAY circuit 1 *********
-INPUT = b	INDEX = 3 
-INPUT = a	INDEX = 4 
------------ NUMBER OF INPUTS = 2
-OUTPUT = s	s = (XOR b a)
------------ NUMBER OF OUTPUTS = 1
-*****************************************
-*/
-
-destroyCct(pC);
-destroyBdd();
-.fi
-.SH ERROR
-"upVarCct : error - old index is higher than new index"
-.br
-The new index must be higher than the old index.
-.SH SEE ALSO
-.BR log (1),
-.BR bdd (1),
-.BR abl (1),
-.BR constraintCct (3),
-.BR composeCct (3).
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/upstr.3 b/alliance/share/man/man3/upstr.3
deleted file mode 100644
index 2a8afb41..00000000
--- a/alliance/share/man/man3/upstr.3
+++ /dev/null
@@ -1,64 +0,0 @@
-.\"   $Id: upstr.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)upstr.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-upstr
-.XE
-.XS4 \n%
-.ti 0.2i
-upstr
-.XE4 \}
-.TH UPSTR 3 "October 1, 1997" "ASIM/LIP6" "MBK UTILITY FUNCTIONS"
-.SH NAME
-upstr \- convert a string to upper case
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-void upstr(s, t)
-char \(**s, \(**t;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIs\fP
-Pointer to the source string
-.TP
-\fIt\fP
-Pointer to the destination string
-.SH DESCRIPTION
-\fBupstr\fP converts the \fIs\fP string to upper case in \fIt\fP.
-The space for \fIt\fP must be allocated by the caller, and be at least
-\fBstrlen(s) + 1\fP long.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mut315.h"
-void cmp()
-{
-char \(**s = "pwet", t[5];
-	upstr(s, t);
-	if (strcmp(t, "PWET")) {
-		fprintf(stderr, "Upstr sucks, man");
-		EXIT();
-	}
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR downstr (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/vhdlablname.3 b/alliance/share/man/man3/vhdlablname.3
deleted file mode 100644
index 618d62ac..00000000
--- a/alliance/share/man/man3/vhdlablname.3
+++ /dev/null
@@ -1,45 +0,0 @@
-.\"   $Id: vhdlablname.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)vhdlablname.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH VHDLABLNAME 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-vhdlablname \- returns a compatible VHDL name.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-char \(**vhdlablname( Name )
-  char \(**Name;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIName\fP
-Name to be translated.
-.SH DESCRIPTION
-\fBvhdlablname\fP translates a name according to the VHDL syntax.
-.br
-.SH RETURN VALUE
-\fBvhdlablname\fP return a new name, using \fInamealloc\fP.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-   /* displays      v_hello_world */
-   printf( "%s\n", vhdlablname( "_hello_world" ) );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1),
-.BR vhdlablvector(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/vhdlablvector.3 b/alliance/share/man/man3/vhdlablvector.3
deleted file mode 100644
index 0c5ce99f..00000000
--- a/alliance/share/man/man3/vhdlablvector.3
+++ /dev/null
@@ -1,54 +0,0 @@
-.\"   $Id: vhdlablvector.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)vhdlablvector.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH VHDLABLVECTOR 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-vhdlablvector \- gives the index and the name of a vectorized name.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-char \(**vhdlablvector( Name, Index )
-  char \(**Name;
-  long \(**Index;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIName\fP
-A vectorized name.
-.TP
-\fIIndex\fP
-A pointer to long.
-.SH DESCRIPTION
-\fBvhdlablvector\fP searches the index of a vectorized name, and the vector's name.
-.br
-.SH RETURN VALUE
-If \fIName\fP is a vectorized name, \fBvhdlablvector\fP
-returns the vector's name using \fInamealloc\fP, and its index throw \fIIndex\fP.
-Otherwise, it returns a null pointer.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-   long Index;
-   char \(**Name;
-   Name = vhdlablvector( "vec 2", &Index );
-   /* displays Name:vec, Index:2  */
-   printf( "Name:%s, Index:%d\n", Name, Index );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1),
-.BR ablvhdlname(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viambkrds.3 b/alliance/share/man/man3/viambkrds.3
deleted file mode 100644
index 9d03c6d3..00000000
--- a/alliance/share/man/man3/viambkrds.3
+++ /dev/null
@@ -1,96 +0,0 @@
-.\"   $Id: viambkrds.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)viambkrds.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-viambkrds
-.XE
-.XS0 \n%
-.ti 0.2i
-viambkrds
-.XE0 \}
-.TH VIAMBKRDS 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-viambkrds \- adds to RDS figure a contact from a MBK figure
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rfmnnn.h"
- rdsrec_list \(**viambkrds( Figure, Via, Lynx )
-    rdsfig_list \(**Figure;
-    phvia_list  \(**Via;
-    char         Lynx;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIFigure\fP
-The RDS figure which has to receive the converted contact.
-.TP
-\fIVia\fP
-MBK contact to convert to RDS rectangles.
-.TP
-\fILynx\fP
-Flag used for the via conversion. If the parameter Lynx is set to 0 then this is the normal conversion mode. If the parameter Lynx is set to 1 then the rds structure generated permits to extract equipotentials rectangles.
-.SH DESCRIPTION
-The \fIviambkrds\fP function converts and creates a RDS contact from a MBK contact. The contact is attached to the RDS figure in parameter of the viambkrds function. See the \fIrdsfig_list\fP structure of librds.
-.TP
-\fINote\fP :
-This function generates many rectangles to create a RDS contact. These rectangle are chained each other (circulary list) with the field USER of the rdsrec_list structure.
-.SH RETURN VALUE
-Pointer to one of the RDS rectangles created.
-.SH ERRORS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-"Rds202: rdsalloc error, can't continue !"
-.ft R
-.RS
-it's impossible to allocate the memory size desired
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mphnnn.h"
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rfmnnn.h"
-        #include "rtlnnn.h"
-        typedef struct UserStruct
-         {
-           char \(**STRING;
-           void \(**USER1;
-         } UserStruct;
-        main()
-          {
-            phfig_list  \(**MbkFigure;
-            rdsfig_list \(**RdsFigure;
-            rdsrec_list \(**Via;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            RdsFigure = addrdsfig ("core",sizeof ( UserStruct ) );
-            MbkFigure->PHVIA = addphvia ( MbkFigure, CONT_VIA, 4, 7);
-            Via = \fBviambkrds\fP (RdsFigure, MbkFigure->PHVIA);
-            viewrfmvia ( MbkFigure->PHVIA, Via ); 
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librds,
-.BR librfm,
-.BR viewrfmvia,
-.BR loadrdsparam
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viewablexpr.3 b/alliance/share/man/man3/viewablexpr.3
deleted file mode 100644
index 5bff3ec3..00000000
--- a/alliance/share/man/man3/viewablexpr.3
+++ /dev/null
@@ -1,56 +0,0 @@
-.\"   $Id: viewablexpr.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)viewablexpr.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH VIEWABLEXPR 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-viewablexpr \- displays an expression.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-void viewablexpr( Expr, Mode )
-  chain_list \(**Expr;
-  int         Mode;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIExpr\fP
-Expression to display.
-.TP
-\fIMode\fP
-The notation type.
-.SH DESCRIPTION
-\fBviewablexpr\fP displays \fIExpr\fP in the notation specified
-by \fIMode\fP. The following notation types are available
-ABL_VIEW_INFIX, ABL_VIEW_PREFIX, ABL_VIEW_POSTFIX or ABL_VIEW_VHDL.
-.br
-.SH RETURN VALUE
-\fBviewablexpr\fP returns nothing.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-  chain_list \(**Expr;
-  Expr = createabloper( ABL_OR );
-  addablhexpr( Expr, createablatom( "a" ) );
-  addablhexpr( Expr, createablatom( "b" ) );
-  /* displays (a or b) */
-  viewablexpr( Expr, ABL_VIEW_VHDL );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1),
-.BR viewablexprstr(3),
-.BR viewablexprfile(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viewablexprfile.3 b/alliance/share/man/man3/viewablexprfile.3
deleted file mode 100644
index 7822614a..00000000
--- a/alliance/share/man/man3/viewablexprfile.3
+++ /dev/null
@@ -1,61 +0,0 @@
-.\"   $Id: viewablexprfile.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)viewablexprfile.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH VIEWABLEXPRFILE 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-viewablexprfile \- displays an expression in a file.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-void viewablexprfile( AblFile, Expr, Mode )
-  FILE       \(**AblFile;
-  chain_list \(**Expr;
-  int         Mode;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIAblFile\fP
-The target file.
-.TP
-\fIExpr\fP
-Expression to display.
-.TP
-\fIMode\fP
-The notation type.
-.SH DESCRIPTION
-\fBviewablexprfile\fP displays \fIExpr\fP in the file \fIAblFile\fP 
-with the notation specified by \fIMode\fP.
-The following notation types are available ABL_VIEW_INFIX, ABL_VIEW_PREFIX,
-ABL_VIEW_POSTFIX or ABL_VIEW_VHDL.
-.br
-.SH RETURN VALUE
-\fBviewablexprfile\fP returns nothing.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-  chain_list \(**Expr;
-  Expr = createabloper( ABL_OR );
-  addablhexpr( Expr, createablatom( "a" ) );
-  addablhexpr( Expr, createablatom( "b" ) );
-  /* displays (a or b) */
-  viewablexprfile( stderr, Expr, ABL_VIEW_VHDL );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1),
-.BR viewablexprstr(3),
-.BR viewablexpr(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viewablexprstr.3 b/alliance/share/man/man3/viewablexprstr.3
deleted file mode 100644
index 96117dc8..00000000
--- a/alliance/share/man/man3/viewablexprstr.3
+++ /dev/null
@@ -1,59 +0,0 @@
-.\"   $Id: viewablexprstr.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)viewablexprstr.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH VIEWABLEXPRSTR 3 "October 1, 1997" "ASIM/LIP6" "ABL FUNCTIONS"
-.SH NAME
-viewablexprstr \- displays an expression in a str.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-char *viewablexprstr( Expr, Mode )
-  chain_list \(**Expr;
-  int         Mode;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIExpr\fP
-Expression to display.
-.TP
-\fIMode\fP
-The notation type.
-.SH DESCRIPTION
-\fBviewablexprstr\fP displays \fIExpr\fP in a string, with the notation 
-specified by \fIMode\fP.  The following notation types are available 
-ABL_VIEW_INFIX, ABL_VIEW_PREFIX, ABL_VIEW_POSTFIX or ABL_VIEW_VHDL.
-.br
-.SH RETURN VALUE
-\fBviewablexprstr\fP returns a pointer to the string where the expression
-has been displayed in. This string MUSTN'T be freed.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "abl101.h"
-  chain_list \(**Expr;
-  char       \(**String;
-  Expr = createabloper( ABL_OR );
-  addablhexpr( Expr, createablatom( "a" ) );
-  addablhexpr( Expr, createablatom( "b" ) );
-  /* displays (a or b) */
-  String = viewablexprstr( Expr, ABL_VIEW_VHDL );
-  printf( String );
-.ft R
-.fi
-.SH SEE ALSO
-.BR abl (1),
-.BR viewablexprfile(3),
-.BR viewablexpr(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viewbddcircuit.3 b/alliance/share/man/man3/viewbddcircuit.3
deleted file mode 100644
index 85ded4f0..00000000
--- a/alliance/share/man/man3/viewbddcircuit.3
+++ /dev/null
@@ -1,56 +0,0 @@
-.\"   $Id: viewbddcircuit.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)viewbddcircuit.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH VIEWBDDCIRCUIT 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-viewbddcircuit \- displays a \fBbdd\fP circuit.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-void viewbddcircuit( BddCircuit, ViewIndex )
-  bddcircuit \(**BddCircuit;
-  char       ViewName;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddCircuit\fP
-The \fBbdd\fP circuit to display.
-.TP
-\fIViewName\fP
-Flag to display more informations.
-.SH DESCRIPTION
-\fBviewbddcircuit\fP displays the \fBbdd\fP circuit \fIBddCircuit\fP.
-If \fIViewName\fP is true, \fBviewbddcircuit\fP displays also the field \fINAME_IN\fP.
-If a null pointer is given, the default \fBbdd\fP circuit is used.
-.br
-.SH RETURN VALUE
-\fBviewbddcircuit\fP returns nothing.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   ...
-   viewbddcircuit( (bddcircuit \(**)0, 0 );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viewbddnode.3 b/alliance/share/man/man3/viewbddnode.3
deleted file mode 100644
index 62083bac..00000000
--- a/alliance/share/man/man3/viewbddnode.3
+++ /dev/null
@@ -1,68 +0,0 @@
-.\"   $Id: viewbddnode.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)viewbddnode.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH VIEWBDDNODE 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-viewbddnode \- displays a \fBbdd\fP node.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-void viewbddnode( BddSystem, BddNode )
-  bddsystem \(**BddSystem;
-  bddnode   \(**BddNode;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system.
-.TP
-\fIBddNode\fP
-The \fBbdd\fP node to display.
-.SH DESCRIPTION
-\fBviewbddnode\fP displays the node \fIBddNode\fP, in the \fBbdd\fP system
-\fIBddSystem\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBviewbddnode\fP returns nothing.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem  \(**BddSystem;
-   bddcircuit \(**BddCircuit;
-   bddnode    \(**BddNode;
-   chain_list \(**Expr;
-   BddSystem  = createbddsystem( 100, 1000, 100, 50000 );
-   BddCircuit = createbddcircuit( "hello_world", 10, 10, BddSystem );
-   addbddcircuitin( (bddcircuit \(**)0, "i0", 0, BDD_IN_MODE_FIRST );
-   addbddcircuitin( (bddcircuit \(**)0, "i1", 0, BDD_IN_MODE_FIRST );
-   BddNode = applybddnode( (bddsystem \(**)0,
-                           ABL_AND,
-                           searchbddcircuitin( (bddcircuit \(**)0, "i0" ),
-                           searchbddcircuitin( (bddcircuit \(**)0, "i1" ) );
-   Expr = convertbddcircuitabl( (bddcircuit \(**)0, BddNode );
-   /* displays (i0 and i1) */
-   viewablexpr( Expr, ABL_VIEW_VHDL );
-   freeablexpr( Expr );
-   /* displays Node VAR: 0  INDEX: 2  MARK: 0  REF_EXT: 1  REF_INT: 0 */
-   viewbddnode( (bddsystem \(**)0, BddNode );
-   destroybddsystem( (bddsystem \(**)0 );
-   destroybddcircuit( (bddcircuit \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viewbddsystem.3 b/alliance/share/man/man3/viewbddsystem.3
deleted file mode 100644
index ef6981d9..00000000
--- a/alliance/share/man/man3/viewbddsystem.3
+++ /dev/null
@@ -1,54 +0,0 @@
-.\"   $Id: viewbddsystem.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)viewbddsystem.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH VIEWBDDSYSTEM 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-viewbddsystem \- displays a \fBbdd\fP system.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-void viewbddsystem( BddSystem, ViewIndex )
-  bddsystem \(**BddSystem;
-  char       ViewIndex;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system to display.
-.TP
-\fIViewIndex\fP
-Flag to display more informations.
-.SH DESCRIPTION
-\fBviewbddsystem\fP displays the \fBbdd\fP system \fIBddSystem\fP.
-If \fIViewIndex\fP is true, \fBviewbddsystem\fP displays also
-the two fields \fIINDEX_TO_VAR\fP and \fIVAR_TO_INDEX\fP.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBviewbddsystem\fP returns nothing.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem \(**BddSystem;
-   BddSystem = createbddsystem( 100, 1000, 100, 50000 );
-   ...
-   viewbddsystem( BddSystem, 0 );
-   destroybddsystem( (bddsystem \(**)0 );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viewbddsysteminfo.3 b/alliance/share/man/man3/viewbddsysteminfo.3
deleted file mode 100644
index e380443a..00000000
--- a/alliance/share/man/man3/viewbddsysteminfo.3
+++ /dev/null
@@ -1,51 +0,0 @@
-.\"   $Id: viewbddsysteminfo.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)viewbddsysteminfo.2 2.7 96/07/02 ; Labo masi cao-vlsi; Author : Jacomme Ludovic
-.TH VIEWBDDSYSTEMINFO 3 "October 1, 1997" "ASIM/LIP6" "BDD FUNCTIONS"
-.SH NAME
-viewbddsysteminfo \- displays statistical informations.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-void viewbddsysteminfo( BddSystem )
-  bddsystem \(**BddSystem;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIBddSystem\fP
-The \fBbdd\fP system to examines.
-.SH DESCRIPTION
-\fBviewbddsysteminfo\fP provides statistical informations
-on the \fBbdd\fP system \fIBddSystem\fP, for example the 
-perfomance of the different caches.
-If a null pointer is given, the default \fBbdd\fP system is used.
-.br
-.SH RETURN VALUE
-\fBviewbddsysteminfo\fP returns nothing.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "bdd101.h"
-   bddsystem \(**BddSystem;
-   BddSystem = createbddsystem( 100, 1000, 100, 50000 );
-   ...
-   viewbddsysteminfo( BddSystem );
-   destroybddsystem( BddSystem );
-.ft R
-.fi
-.SH SEE ALSO
-.BR bdd (1)
-.BR viewbddsystem(3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viewht.3 b/alliance/share/man/man3/viewht.3
deleted file mode 100644
index e0b3b547..00000000
--- a/alliance/share/man/man3/viewht.3
+++ /dev/null
@@ -1,95 +0,0 @@
-.\"   $Id: viewht.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)viewht.2 7.01 92/08/22 ; Labo masi cao-vlsi; Author : Luc Burgun
-.\" slightly modified by Fred Petrot for mbk adaptation on 22/06/92
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-viewht
-.XE
-.XS4 \n%
-.ti 0.2i
-viewht
-.XE4 \}
-.TH VIEWHT 3 "October 1, 1997" "ASIM/LIP6" "MBK HASH TABLE MANAGEMENT FUNCTIONS"
-.SH NAME
-viewht \- displays a hash table contents
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.nf
-#include "mut315.h"
-void viewht(table, display)
-ht \(**table;
-char \(**(\(**display)();
-.fi
-.ft R
-.SH PARAMETER
-.TP 20
-\fItable\fP
-Hash table to be viewed
-.TP 20
-\fIdisplay\fP
-Function to be used for displaying an item of the table
-This function needs a user supplied parameter, the pointer
-to the item.
-.SH DESCRIPTION
-\fBviewht()\fP displays all items of \fItable\fP :
-.TP 20
-index 
-This is the entry index of the hash table
-.TP
-key
-This pointer is the one given by the user.
-It is displayed using something like
-.br
-\fBfprintf(stdout, "%s\\n", \fIdisplay(key)\fP);\fP.
-.TP
-value
-This is the value associated with the key.
-It is displayed as an \fIint\fP.
-.LP
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-.nf
-#include "mut315.h"
-#include <stdio.h>
-typedef struct of_fp {
-	char \(**name;
-	float f;
-	void \(**p;
-} fp;
-char \(**printout(s)
-fp \(**s;
-{
-char t[BUFSIZ];
-	sprintf(t, "name : `%s' :~~~: float value : `%.6f' <%#x>",
-		s->name, s->f, s->p);
-	return t;
-}
-void displayall(h)
-ht *h;
-{
-	viewht(h, printout);
-}
-.fi
-.ft R
-.SH SEE ALSO
-.BR mbk (1),
-.BR addht (3),
-.BR delht (3),
-.BR addhtitem (3),
-.BR gethtitem (3),
-.BR sethtitem (3),
-.BR delhtitem (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viewlo.3 b/alliance/share/man/man3/viewlo.3
deleted file mode 100644
index e22a5a2d..00000000
--- a/alliance/share/man/man3/viewlo.3
+++ /dev/null
@@ -1,70 +0,0 @@
-.\"   $Id: viewlo.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)viewlo.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-viewlo
-.XE
-.XS2 \n%
-.ti 0.2i
-viewlo
-.XE2 \}
-.TH VIEWLO 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL FUNCTIONS"
-.SH NAME
-viewlo \- scan all \fBlofig_list\fPs and display their elements
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-void viewlo();
-.ft R
-.fi
-.SH DESCRIPTION
-\fBviewlo\fP scans all the elements of the entire \fBlofig_list\fP 
-loaded in ram, and displays a textual output of the data strcuture contents.
-All the figures are treated, the first one beeing pointed to by
-\fBHEAD_LOFIG\fP, the global variable that points to the head of all
-\fBlofig\fPs.
-.br
-Its use is mostly for debugging purposes, and educational ones, since the
-output is quite verbose, if very easy to understand.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <stdio.h>
-#include "mlo404.h"
-void view_all_to_file(name)
-char \(**name;
-{
-FILE \(**file = freopen(name, WRITE_TEXT, stdout);
-	if (!file) {
-		(void)fputs("Can't reopen stdout!\\n", stderr);
-		EXIT();
-	}
-	viewlo(); /\(** to file called name \(**/
-	(void)fclose(file);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR lofig (3),
-.BR viewlofig (3),
-.BR viewloins (3),
-.BR viewlotrs (3),
-.BR viewlosig (3),
-.BR viewloinscon (3),
-.BR viewlofigcon (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viewlofig.3 b/alliance/share/man/man3/viewlofig.3
deleted file mode 100644
index 8c51ee61..00000000
--- a/alliance/share/man/man3/viewlofig.3
+++ /dev/null
@@ -1,74 +0,0 @@
-.\"   $Id: viewlofig.3,v 1.1 1999/05/31 17:30:25 alliance Exp $
-.\" @(#)viewlofig.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-viewlofig
-.XE
-.XS2 \n%
-.ti 0.2i
-viewlofig
-.XE2 \}
-.TH VIEWLOFIG 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL FUNCTIONS"
-.SH NAME
-viewlofig \- display elements of a \fBlofig_list\fP
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-void viewlofig(ptfig)
-lofig_list \(**ptfig;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIptfig\fP
-Pointer to the \fBlofig\fP to be scaned
-.SH DESCRIPTION
-\fBviewlofig\fP scans all the primary elements of the \fBlofig_list\fP 
-loaded in ram, and displays a textual output of the data strcuture contents.
-The \fILOINS\fP, \fILOCON\fP, \fILOSIG\fP and \fILOTRS\fP are scaned, and
-their contents displayed.
-.br
-Its use is mostly for debugging purposes, and educational ones, since the
-output is quite verbose, if very easy to understand.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <stdio.h>
-#include "mlo404.h"
-void view_fig_to_file(ptfig)
-lofig_list \(**ptfig;
-{
-FILE \(**file = freopen(ptfig\->NAME, WRITE_TEXT, stdout);
-	if (!file) {
-		(void)fputs("Can't reopen stdout!\\n", stderr);
-		EXIT();
-	}
-	viewlofig(ptfig\->NAME); /\(** to file called name \(**/
-	(void)fclose(file);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR lofig (3),
-.BR viewlo (3),
-.BR viewloins (3),
-.BR viewlotrs (3),
-.BR viewlosig (3),
-.BR viewloinscon (3),
-.BR viewlofigcon (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viewlofigcon.3 b/alliance/share/man/man3/viewlofigcon.3
deleted file mode 100644
index 15f13dbb..00000000
--- a/alliance/share/man/man3/viewlofigcon.3
+++ /dev/null
@@ -1,69 +0,0 @@
-.\"   $Id: viewlofigcon.3,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.\" @(#)viewlofigcon.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-viewlofigcon
-.XE
-.XS2 \n%
-.ti 0.2i
-viewlofigcon
-.XE2 \}
-.so man1/alc_origin.1
-.SH NAME
-viewlofigcon \- display elements of a \fBlocon_list\fP attached to a
-figure
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-void viewlofigcon(ptcon)
-locon_list \(**ptcon;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIptcon\fP
-Pointer to the \fBlocon\fP to be scaned
-.SH DESCRIPTION
-\fBviewlofigcon\fP scans all the primary elements of the \fBlocon_list\fP 
-loaded in ram, and displays a textual output of the data strcuture contents.
-.br
-Its use is mostly for debugging purposes, and educational ones, since the
-output is quite verbose, even if very easy to understand.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <stdio.h>
-#include "mlo404.h"
-void view_figcon(ptfig)
-lofig_list \(**ptfig;
-{
-locon_list \(**figcon;
-	for (figcon = ptfig\->LOCON; figcon; figcon = figcon\->NEXT)
-		viewlofigcon(figcon);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR locon (3),
-.BR lofig (3),
-.BR viewlo (3),
-.BR viewlofig (3),
-.BR viewlotrs (3),
-.BR viewlosig (3),
-.BR viewloinscon (3),
-.BR viewlofigcon (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viewloins.3 b/alliance/share/man/man3/viewloins.3
deleted file mode 100644
index 5df3370f..00000000
--- a/alliance/share/man/man3/viewloins.3
+++ /dev/null
@@ -1,70 +0,0 @@
-.\"   $Id: viewloins.3,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.\" @(#)viewloins.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-viewloins
-.XE
-.XS2 \n%
-.ti 0.2i
-viewloins
-.XE2 \}
-.TH VIEWLOINS 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL FUNCTIONS"
-.SH NAME
-viewloins \- display elements of a \fBloins_list\fP
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-void viewloins(pt)
-loins_list \(**pt;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIpt\fP
-Pointer to the \fBloins\fP to be scaned
-.SH DESCRIPTION
-\fBviewloins\fP scans all the primary elements of the \fBloins_list\fP 
-pointed to by \fIpt\fP, and displays a textual output of the data strcuture
-contents.
-The \fILOCON\fP field is scaned, and its contents displayed.
-.br
-Its use is mostly for debugging purposes, and educational ones, since the
-output is quite verbose, even if very easy to understand.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <stdio.h>
-#include "mlo404.h"
-void view_ins(ptfig)
-lofig_list \(**ptfig;
-{
-loins_list \(**ins;
-	for (ins = ptfig\->LOINS; ins; ins = ins\->NEXT)
-		viewloins(ins);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR loins (3),
-.BR viewlo (3),
-.BR viewlofig (3),
-.BR viewlotrs (3),
-.BR viewlosig (3),
-.BR viewloinscon (3),
-.BR viewloinscon (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viewloinscon.3 b/alliance/share/man/man3/viewloinscon.3
deleted file mode 100644
index ef1cbf10..00000000
--- a/alliance/share/man/man3/viewloinscon.3
+++ /dev/null
@@ -1,70 +0,0 @@
-.\"   $Id: viewloinscon.3,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.\" @(#)viewloinscon.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-viewloinscon
-.XE
-.XS2 \n%
-.ti 0.2i
-viewloinscon
-.XE2 \}
-.TH VIEWLOINSCON 3 "October 1, 1997" "ASIM/LIP6" "Mbk Logical Functions"
-.SH NAME
-\fBviewloinscon\fP \- display elements of a \fBlocon_list\fP attached to an
-instance
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-void viewloinscon(ptcon)
-locon_list \(**ptcon;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIptcon\fP
-Pointer to the \fBlocon\fP to be scaned
-.SH DESCRIPTION
-\fBviewloinscon\fP scans all the primary elements of the \fBlocon_list\fP 
-loaded in ram, and displays a textual output of the data strcuture contents.
-.br
-Its use is mostly for debugging purposes, and educational ones, since the
-output is quite verbose, even if very easy to understand.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <stdio.h>
-#include "mlo404.h"
-void view_inscon(ptins)
-loins_list \(**ptins;
-{
-locon_list \(**inscon;
-	for (inscon = ptins\->LOCON; inscon; inscon = inscon\->NEXT)
-		viewloinscon(inscon);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR locon (3),
-.BR loins (3),
-.BR viewlo (3),
-.BR viewlofig (3),
-.BR viewlotrs (3),
-.BR viewlosig (3),
-.BR viewloinscon (3),
-.BR viewlofigcon (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viewlosig.3 b/alliance/share/man/man3/viewlosig.3
deleted file mode 100644
index 410ad3cc..00000000
--- a/alliance/share/man/man3/viewlosig.3
+++ /dev/null
@@ -1,68 +0,0 @@
-.\"   $Id: viewlosig.3,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.\" @(#)viewlosig.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-viewlosig
-.XE
-.XS2 \n%
-.ti 0.2i
-viewlosig
-.XE2 \}
-.TH VIEWLOSIG 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL FUNCTIONS"
-.SH NAME
-viewlosig \- display elements of a \fBlosig_list\fP
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-void viewlosig(ptsig)
-losig_list \(**ptsig;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIptsig\fP
-Pointer to the \fBlosig\fP to be scaned
-.SH DESCRIPTION
-\fBviewlosig\fP scans all the primary elements of the \fBlosig_list\fP 
-loaded in ram, and displays a textual output of the data strcuture contents.
-.br
-Its use is mostly for debugging purposes, and educational ones, since the
-output is quite verbose, even if very easy to understand.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <stdio.h>
-#include "mlo404.h"
-void view_sig(ptfig)
-lofig_list \(**ptfig;
-{
-losig_list \(**sig;
-	for (sig = ptfig\->LOSIG; sig; sig = sig\->NEXT)
-		viewlosig(sig);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR losig (3),
-.BR viewlo (3),
-.BR viewlofig (3),
-.BR viewlotrs (3),
-.BR viewlosig (3),
-.BR viewloinscon (3),
-.BR viewlofigcon (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viewlotrs.3 b/alliance/share/man/man3/viewlotrs.3
deleted file mode 100644
index a58533d2..00000000
--- a/alliance/share/man/man3/viewlotrs.3
+++ /dev/null
@@ -1,70 +0,0 @@
-.\"   $Id: viewlotrs.3,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.\" @(#)viewlotrs.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-viewlotrs
-.XE
-.XS2 \n%
-.ti 0.2i
-viewlotrs
-.XE2 \}
-
-.TH VIEWLOTRS 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL FUNCTIONS"
-.SH NAME
-viewlotrs \- display elements of a \fBlotrs_list\fP
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mlo404.h"
-void viewlotrs(pttrs)
-lotrs_list \(**pttrs;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIpttrs\fP
-Pointer to the \fBlotrs\fP to be scaned
-.SH DESCRIPTION
-\fBviewlotrs\fP scans all the primary elements of the \fBlotrs_list\fP 
-loaded in ram, and displays a textual output of the data strcuture contents.
-.br
-Its use is mostly for debugging purposes, and educational ones, since the
-output is quite verbose, even if very easy to understand.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <stdio.h>
-#include "mlo404.h"
-void view_trs(ptfig)
-lofig_list \(**ptfig;
-{
-lotrs_list \(**trs;
-	for (trs = ptfig\->LOTRS; trs; trs = trs\->NEXT)
-		viewlotrs(trs);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR lotrs (3),
-.BR viewlo (3),
-.BR viewlofig (3),
-.BR viewlotrs (3),
-.BR viewlosig (3),
-.BR viewloinscon (3),
-.BR viewlofigcon (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viewph.3 b/alliance/share/man/man3/viewph.3
deleted file mode 100644
index 650c58f5..00000000
--- a/alliance/share/man/man3/viewph.3
+++ /dev/null
@@ -1,70 +0,0 @@
-.\"   $Id: viewph.3,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.\" @(#)viewph.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-viewph
-.XE
-.XS0 \n%
-.ti 0.2i
-viewph
-.XE0 \}
-.TH VIEWPH 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL FUNCTIONS"
-.SH NAME
-viewph \- display all the \fBphfig_list\fPs and their elements
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-void viewph();
-.ft R
-.fi
-.SH DESCRIPTION
-\fBviewph\fP scans all the elements of the entire \fBphfig_list\fP 
-loaded in ram, and displays a textual output of the data strcuture contents.
-All the figures are treated, the first one beeing pointed to by
-\fBHEAD_PHFIG\fP, the  global variable that points to the head of all
-\fBphfig\fPs.
-.br
-Its use is mostly for debugging purposes, and educational ones, since the
-output is quite verbose, even if very easy to understand.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <stdio.h>
-#include "mph402.h"
-void view_all_to_file(name)
-char \(**name;
-{
-FILE \(**file = freopen(name, WRITE_TEXT, stdout);
-	if (!file) {
-		(void)fputs("Can't reopen stdout!\\n", stderr);
-		EXIT();
-	}
-	viewph(); /\(** to file called name \(**/
-	(void)fclose(file);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR phfig (3),
-.BR view_phfig (3),
-.BR view_phins (3),
-.BR view_phseg (3),
-.BR view_phref (3),
-.BR view_phvia (3),
-.BR view_phfigcon (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viewphcon.3 b/alliance/share/man/man3/viewphcon.3
deleted file mode 100644
index c7a81828..00000000
--- a/alliance/share/man/man3/viewphcon.3
+++ /dev/null
@@ -1,69 +0,0 @@
-.\"   $Id: viewphcon.3,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.\" @(#)viewphcon.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-viewphcon
-.XE
-.XS0 \n%
-.ti 0.2i
-viewphcon
-.XE0 \}
-.TH VIEWPHCON 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL FUNCTIONS"
-.SH NAME
-viewphcon \- display elements of a \fBphcon_list\fP
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-void viewphcon(pt)
-phcon_list \(**pt;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIpt\fP
-Pointer to the \fBphcon\fP to be scaned
-.SH DESCRIPTION
-\fBviewphcon\fP scans all the primary elements of the \fBphcon_list\fP 
-pointed to by \fIpt\fP, and displays a textual output of the data strcuture
-contents.
-.br
-Its use is mostly for debugging purposes, and educational ones, since the
-output is quite verbose, even if very easy to understand.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <stdio.h>
-#include "mph402.h"
-void view_con(ptfig)
-phfig_list \(**ptfig;
-{
-phcon_list \(**con;
-	for (con = ptfig\->PHCON; con; con = con\->NEXT)
-		viewphcon(con);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR phcon (3),
-.BR viewph (3),
-.BR viewphfig (3),
-.BR viewphseg (3),
-.BR viewphref (3),
-.BR viewphvia (3),
-.BR viewphins (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viewphfig.3 b/alliance/share/man/man3/viewphfig.3
deleted file mode 100644
index b27a7259..00000000
--- a/alliance/share/man/man3/viewphfig.3
+++ /dev/null
@@ -1,73 +0,0 @@
-.\"   $Id: viewphfig.3,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.\" @(#)viewphfig.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-viewphfig
-.XE
-.XS0 \n%
-.ti 0.2i
-viewphfig
-.XE0 \}
-.so man1/alc_origin.1
-.SH NAME
-viewphfig \- display elements of a \fBphfig_list\fP
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-void viewphfig(ptfig)
-phfig_list \(**ptfig;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIptfig\fP
-Pointer to the \fBphfig\fP to be scaned
-.SH DESCRIPTION
-\fBviewphfig\fP scans all the primary elements of the \fBphfig_list\fP 
-loaded in ram, and displays a textual output of the data strcuture contents.
-The \fIPHINS\fP, \fIPHCON\fP, \fIPHSEG\fP, \fIPHVIA\fP and \fIPHREF\fP are
-scaned, and their contents displayed.
-.br
-Its use is mostly for debugging purposes, and educational ones, since the
-output is quite verbose, if very easy to understand.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <stdio.h>
-#include "mph402.h"
-void view_fig_to_file(ptfig)
-phfig_list \(**ptfig;
-{
-FILE \(**file = freopen(ptfig\->NAME, WRITE_TEXT, stdout);
-	if (!file) {
-		(void)fputs("Can't reopen stdout!\\n", stderr);
-		EXIT();
-	}
-	viewphfig(ptfig); /\(** to file called name \(**/
-	(void)fclose(file);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR phfig (3),
-.BR viewph (3),
-.BR viewphins (3),
-.BR viewphseg (3),
-.BR viewphref (3),
-.BR viewphvia (3),
-.BR viewphcon (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viewphins.3 b/alliance/share/man/man3/viewphins.3
deleted file mode 100644
index fef66147..00000000
--- a/alliance/share/man/man3/viewphins.3
+++ /dev/null
@@ -1,69 +0,0 @@
-.\"   $Id: viewphins.3,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.\" @(#)viewphins.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-viewphins
-.XE
-.XS0 \n%
-.ti 0.2i
-viewphins
-.XE0 \}
-.TH VIEWPHINS 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL FUNCTIONS"
-.SH NAME
-viewphins \- display elements of a \fBphins_list\fP
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-void viewphins(pt)
-phins_list \(**pt;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIpt\fP
-Pointer to the \fBphins\fP to be scaned
-.SH DESCRIPTION
-\fBviewphins\fP scans all the primary elements of the \fBphins_list\fP 
-pointed to by \fIpt\fP, and displays a textual output of the data strcuture
-contents.
-.br
-Its use is mostly for debugging purposes, and educational ones, since the
-output is quite verbose, even if very easy to understand.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <stdio.h>
-#include "mph402.h"
-void view_ins(ptfig)
-phfig_list \(**ptfig;
-{
-phins_list \(**ins;
-	for (ins = ptfig\->PHINS; ins; ins = ins\->NEXT)
-		viewphins(ins);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR phins (3),
-.BR viewph (3),
-.BR viewphfig (3),
-.BR viewphseg (3),
-.BR viewphref (3),
-.BR viewphvia (3),
-.BR viewphcon (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viewphref.3 b/alliance/share/man/man3/viewphref.3
deleted file mode 100644
index 4a95eb0e..00000000
--- a/alliance/share/man/man3/viewphref.3
+++ /dev/null
@@ -1,69 +0,0 @@
-.\"   $Id: viewphref.3,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.\" @(#)viewphref.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-viewphref
-.XE
-.XS0 \n%
-.ti 0.2i
-viewphref
-.XE0 \}
-.TH VIEWPHREF 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL FUNCTIONS"
-.SH NAME
-viewphref \- display elements of a \fBphref_list\fP
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-void viewphref(pt)
-phref_list \(**pt;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIpt\fP
-Pointer to the \fBphref\fP to be scaned
-.SH DESCRIPTION
-\fBviewphref\fP scans all the primary elements of the \fBphref_list\fP 
-pointed to by \fIpt\fP, and displays a textual output of the data strcuture
-contents.
-.br
-Its use is mostly for debugging purposes, and educational ones, since the
-output is quite verbose, even if very easy to understand.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <stdio.h>
-#include "mph402.h"
-void view_ref(ptfig)
-phfig_list \(**ptfig;
-{
-phref_list \(**ref;
-	for (ref = ptfig\->PHREF; ref; ref = ref\->NEXT)
-		viewphref(ref);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR phref (3),
-.BR viewph (3),
-.BR viewphfig (3),
-.BR viewphseg (3),
-.BR viewphins (3),
-.BR viewphvia (3),
-.BR viewphcon (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viewphseg.3 b/alliance/share/man/man3/viewphseg.3
deleted file mode 100644
index a66dae8c..00000000
--- a/alliance/share/man/man3/viewphseg.3
+++ /dev/null
@@ -1,69 +0,0 @@
-.\"   $Id: viewphseg.3,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.\" @(#)viewphseg.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-viewphseg
-.XE
-.XS0 \n%
-.ti 0.2i
-viewphseg
-.XE0 \}
-.TH VIEWPHSEG 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL FUNCTIONS"
-.SH NAME
-viewphseg \- display elements of a \fBphseg_list\fP
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-void viewphseg(pt)
-phseg_list \(**pt;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIpt\fP
-Pointer to the \fBphseg\fP to be scaned
-.SH DESCRIPTION
-\fBviewphseg\fP scans all the primary elements of the \fBphseg_list\fP 
-pointed to by \fIpt\fP, and displays a textual output of the data strcuture
-contents.
-.br
-Its use is mostly for debugging purposes, and educational ones, since the
-output is quite verbose, even if very easy to understand.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <stdio.h>
-#include "mph402.h"
-void view_seg(ptfig)
-phfig_list \(**ptfig;
-{
-phseg_list \(**seg;
-	for (seg = ptfig\->PHSEG; seg; seg = seg\->NEXT)
-		viewphseg(seg);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR phseg (3),
-.BR viewph (3),
-.BR viewphfig (3),
-.BR viewphins (3),
-.BR viewphref (3),
-.BR viewphvia (3),
-.BR viewphcon (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viewphvia.3 b/alliance/share/man/man3/viewphvia.3
deleted file mode 100644
index a8fd654b..00000000
--- a/alliance/share/man/man3/viewphvia.3
+++ /dev/null
@@ -1,68 +0,0 @@
-.\"   $Id: viewphvia.3,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.\" @(#)viewphvia.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-viewphvia
-.XE
-.XS0 \n%
-.ti 0.2i
-viewphvia
-.XE0 \}
-.so man1/alc_origin.1
-.SH NAME
-viewphvia \- display elements of a \fBphvia_list\fP
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-void viewphvia(pt)
-phvia_list \(**pt;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIpt\fP
-Pointer to the \fBphvia\fP to be scaned
-.SH DESCRIPTION
-\fBviewphvia\fP scans all the primary elements of the \fBphvia_list\fP 
-pointed to by \fIpt\fP, and displays a textual output of the data strcuture
-contents.
-.br
-Its use is mostly for debugging purposes, and educational ones, since the
-output is quite verbose, even if very easy to understand.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <stdio.h>
-#include "mph402.h"
-void view_via(ptfig)
-phfig_list \(**ptfig;
-{
-phvia_list \(**via;
-	for (via = ptfig\->PHVIA; via; via = via\->NEXT)
-		viewphvia(via);
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR phvia (3),
-.BR viewph (3),
-.BR viewphfig (3),
-.BR viewphseg (3),
-.BR viewphref (3),
-.BR viewphins (3),
-.BR viewphcon (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viewrdsfig.3 b/alliance/share/man/man3/viewrdsfig.3
deleted file mode 100644
index 5778df11..00000000
--- a/alliance/share/man/man3/viewrdsfig.3
+++ /dev/null
@@ -1,93 +0,0 @@
-.\"   $Id: viewrdsfig.3,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.\" @(#)viewrdsfig.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-viewrdsfig
-.XE
-.XS0 \n%
-.ti 0.2i
-viewrdsfig
-.XE0 \}
-.TH VIEWRDSFIG 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
- viewrdsfig \- view caracteristics of a figure
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
- #include "rdsnnn.h"
-  void viewrdsfig( Figure )
-   rdsins_list \(**Figure;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIFigure\fP
-Pointer to the figure to visualize.
-.SH DESCRIPTION
-The \fIviewrdsfig\fP function displays caracteristics of the figure called \'Figure\' and all the objets contained in this figure.
-.TP
-figure's parameters displayed to screen :
-.RS
-.TP 
-\fINAME\fP
-figure's name.
-.TP 
-\fIMODE\fP
-loading mode of the figure.
-.TP 
-\fISIZE\fP
-size of user structure added to the rdsrec_list structure.
-.RE
-Displays also rectangle and instance parameters of the figure (see viewrdsins and viewrdsrec functions).
-.SH RETURN VALUE
-nothing
-.SH ERRORS
-none
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rtlnnn.h"
-        typedef struct UserStruct
-         {
-           char \(**STRING;
-           void \(**USER1;
-         } UserStruct;
-         main()
-          {
-            rdsfig_list \(**Figure;
-            rdsrec_list \(**Rectangle;
-            rdsins_list \(**Instance;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            Figure = addrdsfig ("core",sizeof ( UserStruct ) );
-            Instance  = addrdsins (Figure,"na2_y","and2",RDS_NOSYM,8,6);
-            Rectangle =
-             addrdsfigrec(Figure,"Alu1",RDS_ALU1,2,4,12,1);
-            /\(**
-              visualization of the figure and its items
-            \(**/
-            /\(** \(**/ \fBviewrdsfig\fP ( Figure );
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librds,
-.BR viewrdsrec,
-.BR viewrdsins
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viewrdsins.3 b/alliance/share/man/man3/viewrdsins.3
deleted file mode 100644
index 00df3ea3..00000000
--- a/alliance/share/man/man3/viewrdsins.3
+++ /dev/null
@@ -1,99 +0,0 @@
-.\"   $Id: viewrdsins.3,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.\" @(#)viewrdsins.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-viewrdsins
-.XE
-.XS0 \n%
-.ti 0.2i
-viewrdsins
-.XE0 \}
-.TH VIEWRDSINS 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-viewrdsins \- Displays caracteristics of an instance
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
- #include "rdsnnn.h"
-   void viewrdsins( Instance )
-    rdsins_list \(**Instance;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIInstance\fP
-Instance to display.
-.SH DESCRIPTION
-The \fIviewrdsins\fP function displays caracteristics of the instance pointed by \'Instance\' and its items. 
-.TP
-instance's parameters displayed :
-.RS
-.TP 20
-\fIINSNAME\fP
-name of the instance.
-.TP
-\fIFIGNAME\fP
-model's name of the instance.
-.TP
-\fIX,Y\fP
-position of the lower left corner of the instance.
-.TP
-\fITRANSF\fP
-transformation applied to the instance.
-.TP
-\fISIZE\fP
-size of the user structure added to the rdsrec_list structure.
-.RE
-This function displays also rectangles of the instance (see viewrdsrec() function).
-.SH RETURN VALUE
-nothing
-.SH ERRORS
-none
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rtlnnn.h"
-        typedef struct UserStruct
-         {
-           char \(**STRING;
-           void \(**USER1;
-         } UserStruct;
-         main()
-          {
-            rdsfig_list \(**Figure;
-            rdsrec_list \(**Rectangle;
-            rdsins_list \(**Instance;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            Figure = addrdsfig ("core",sizeof ( UserStruct ) );
-            Instance  = addrdsins (Figure,"na2_y","and2",RDS_NOSYM,8,6);
-            Rectangle =
-             addrdsinsrec(Instance,"Alu1",RDS_ALU1,2,4,12,1);
-            /\(**
-              visualization of the instance and its rectangle
-            \(**/
-            /\(** \(**/ \fBviewrdsins\fP ( Instance );
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librds,
-.BR viewrdsfig,
-.BR viewrdsrec
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viewrdsparam.3 b/alliance/share/man/man3/viewrdsparam.3
deleted file mode 100644
index 51210ff2..00000000
--- a/alliance/share/man/man3/viewrdsparam.3
+++ /dev/null
@@ -1,66 +0,0 @@
-.\"   $Id: viewrdsparam.3,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.\" @(#)viewrdsparam.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-viewrdsparam
-.XE
-.XS0 \n%
-.ti 0.2i
-viewrdsparam
-.XE0 \}
-.TH VIEWRDSPARAM 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-viewrdsparam \- displays tables in memory filled by loadrdsparam function. 
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-void viewrdsparam()
-.ft R
-.fi
-.SH PARAMETER
-none
-.SH DESCRIPTION
-The \fIviewrdsparam\fP function displays tables in RAM filled by the loadrdsparam function.
-For more information, see loadrdsparam function.
-.SH RETURN VALUE
-nothing
-.SH ERRORS
-none
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mphnnn.h"
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rtlnnn.h"
-        #include "rprnnn.h"
-        #include "rfmnnn.h"
-        main()
-         {
-           rdsfig_list \(**RdsFigure;
-           phfig_list  \(**MbkFigure;
-           mbkenv();
-           rdsenv();
-           loadrdsparam();
-           /\(** \(**/ \fBviewrdsparam\fP ();
-           . . .
-         }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librpr,
-.BR loadrdsparam
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viewrdsrec.3 b/alliance/share/man/man3/viewrdsrec.3
deleted file mode 100644
index 4d02e806..00000000
--- a/alliance/share/man/man3/viewrdsrec.3
+++ /dev/null
@@ -1,81 +0,0 @@
-.\"   $Id: viewrdsrec.3,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.\" @(#)viewrdsrec.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-viewrdsrec
-.XE
-.XS0 \n%
-.ti 0.2i
-viewrdsrec
-.XE0 \}
-.TH VIEWRDSREC 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-viewrdsrec \- Displays caracteristics of a rectangle
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
- #include "rdsnnn.h"
-  void viewrdsrec( Rectangle )
-   rdsrec_list \(**Rectangle;
-.ft R
-.fi
-.SH PARAMETERS
-\fIRectangle\fP
-The rectangle to display. 
-.SH DESCRIPTION
-The \fIviewrdsrec\fP function displays rectangle's caracteristics :
-.RS
-.TP 20
-\- its coordinates (X,Y,DX,DY)
-.TP
-\- its Layer
-.TP
-\- its name
-.TP
-\- its field FLAGS 
-.RE
-.SH RETURN VALUE
-nothing
-.SH ERRORS
-none
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rtlnnn.h"
-           main()
-          {
-            rdsfig_list \(**Figure;
-            rdsrec_list \(**Rectangle;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            Figure = addrdsfig ("core",sizeof ( UserStruct ) );
-            Rectangle =
-             addrdsfigrec(Figure,"Alu1",RDS_ALU1,2,4,12,1);
-            /\(**
-              visualization of rectangle's caracteristics 
-            \(**/
-            /* */ \fBviewrdsrec\fP ( Rectangle );
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librds,
-.BR viewrdsfig,
-.BR viewrdsins
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viewrdswindow.3 b/alliance/share/man/man3/viewrdswindow.3
deleted file mode 100644
index f4f5c685..00000000
--- a/alliance/share/man/man3/viewrdswindow.3
+++ /dev/null
@@ -1,80 +0,0 @@
-.\"   $Id: viewrdswindow.3,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.\" @(#)viewrdswindow.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-viewrdswindow
-.XE
-.XS0 \n%
-.ti 0.2i
-viewrdswindow
-.XE0 \}
-.TH VIEWRDSWINDOW 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-viewrdswindow \- displays caracteristics of the windowing. 
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rwinnn.h"
-void viewrdswindow( RdsWindow )
-   rdswindow \(**RdsWindow;
-.ft R
-.fi
-.SH PARAMETER
-\fIRdsWindow\fP :
-The head of the windowing of the RDS structure.
-.SH DESCRIPTION
-The \fIviewrdswindow\fP function displays :
-.PP
-Caracteristics of the windowing (number of windows, width, height,size of a window,...).
-.br
-Size and position of each window.
-.br
-All the rectangles of each window.
-.SH RETURN VALUE
-nothing
-.SH ERRORS
-none
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mphnnn.h"
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rfmnnn.h"
-        #include "rwinnn.h"
-        #include "rtlnnn.h"
-        main()
-          {
-            phfig_list     \(**MbkFigure;
-            rdsfig_list    \(**RdsFigure;
-            rdswindow      \(**Window;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            MbkFigure = getphfig("na2_y",'A');
-            RdsFigure = figmbkrds(MbkFigure,0,0);
-            Window    =  buildrdswindow ( RdsFigure );
-            /\(** \(**/ \fBviewrdswindow\fP ( Window );
-            . . .
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librwi,
-.BR buildrdswindow,
-.BR destroyrdswindow,
-.BR allocrdswindow
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viewrfmcon.3 b/alliance/share/man/man3/viewrfmcon.3
deleted file mode 100644
index ea6f37c0..00000000
--- a/alliance/share/man/man3/viewrfmcon.3
+++ /dev/null
@@ -1,83 +0,0 @@
-.\"   $Id: viewrfmcon.3,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.\" @(#)viewrfmcon.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-viewrfmcon
-.XE
-.XS0 \n%
-.ti 0.2i
-viewrfmcon
-.XE0 \}
-.TH VIEWRFMCON 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-viewrfmcon \- displays connector caracteristics in MBK and RDS format.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rfmnnn.h"
- void viewrfmcon( Connector, Rectangle )
-    phcon_list  \(**Connector;
-    rdsrec_list \(**Rectangle;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIConnector\fP
-MBK Connector to visualizate
-.TP
-\fIRectangle\fP
-RDS Connector to visualizate
-.SH DESCRIPTION
-The \fIviewrfmcon\fP function displays caracteristics of a connector in MBK and RDS format.
-.SH RETURN VALUE
-nothing
-.SH ERRORS
-none
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mphnnn.h"
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rfmnnn.h"
-        #include "rtlnnn.h"
-        typedef struct UserStruct
-         {
-           char \(**STRING;
-           void \(**USER1;
-         } UserStruct;
-        main()
-          {
-            phfig_list  \(**MbkFigure;
-            rdsfig_list \(**RdsFigure;
-            rdsrec_list \(**RdsConnector;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            RdsFigure =
-               addrdsfig ("core",sizeof ( UserStruct ) );
-            MbkFigure->PHCON =
-               addphcon ( MbkFigure, NORTH, "c_1", 14, 5, ALU1, 2);
-            RdsConnector = conmbkrds(RdsFigure, MbkFigure->PHCON);
-            /\(** \(**/ \fBviewrfmcon\fP ( MbkFigure->PHCON, RdsConnector );            
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librfm,
-.BR conmbkrds,
-.BR insconmbkrds
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viewrfmfig.3 b/alliance/share/man/man3/viewrfmfig.3
deleted file mode 100644
index 4d911d99..00000000
--- a/alliance/share/man/man3/viewrfmfig.3
+++ /dev/null
@@ -1,79 +0,0 @@
-.\"   $Id: viewrfmfig.3,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.\" @(#)viewrfmfig.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-viewrfmfig
-.XE
-.XS0 \n%
-.ti 0.2i
-viewrfmfig
-.XE0 \}
-.TH VIEWRFMFIG 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-viewrfmfig \- displays figure caracteristics in MBK and RDS format.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rfmnnn.h"
- void viewrfmfig( FigureMbk, FigureRds )
-    phfig_list  \(**FigureMbk;
-    rdsfig_list \(**FigureRds;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIFigureMbk\fP
-MBK figure to visualizate
-.TP
-\fIFigureRds\fP
-RDS figure to visualizate
-.SH DESCRIPTION
-The \fIviewrfmfig\fP function displays caracteristics of a figure in MBK and RDS format.
-.SH RETURN VALUE
-nothing
-.SH ERRORS
-none
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mphnnn.h"
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rfmnnn.h"
-        #include "rtlnnn.h"
-        typedef struct UserStruct
-         {
-           char \(**STRING;
-           void \(**USER1;
-         } UserStruct;
-        main()
-          {
-            phfig_list  \(**MbkFigure;
-            rdsfig_list \(**RdsFigure;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            MbkFigure        = getphfig("na2_y",'A');
-            RdsFigure        = figmbkrds(FigureMbk,sizeof(UserStruct),0);
-            /\(** view Mbk and Rds Figure \(**/
-            /\(** \(**/ \fBviewrfmfig\fP ( MbkFigure, RdsFigure );            
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librfm,
-.BR figmbkrds
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viewrfmins.3 b/alliance/share/man/man3/viewrfmins.3
deleted file mode 100644
index 1a8c91e8..00000000
--- a/alliance/share/man/man3/viewrfmins.3
+++ /dev/null
@@ -1,87 +0,0 @@
-.\"   $Id: viewrfmins.3,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.\" @(#)viewrfmins.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-viewrfmins
-.XE
-.XS0 \n%
-.ti 0.2i
-viewrfmins
-.XE0 \}
-.TH VIEWRFMINS 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-viewrfmins \- displays instance caracteristics in MBK and RDS format.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rfmnnn.h"
- void viewrfmins( InstanceMbk, InstanceRds )
-    phins_list  \(**InstanceMbk;
-    rdsins_list \(**InstanceRds;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIInstanceMbk\fP
-MBK instance to visualizate
-.TP
-\fIInstanceRds\fP
-RDS instance to visualizate
-.SH DESCRIPTION
-The \fIviewrfmins\fP function displays caracteristics of an instance in MBK and RDS format.
-.SH RETURN VALUE
-nothing
-.SH ERRORS
-none
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mphnnn.h"
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rfmnnn.h"
-        #include "rtlnnn.h"
-        typedef struct UserStruct
-         {
-           char \(**STRING;
-           void \(**USER1;
-         } UserStruct;
-        main()
-          {
-            phfig_list  \(**MbkFigure;
-            phins_list  \(**MbkInstance;
-            rdsfig_list \(**RdsFigure;
-            rdsins_list \(**RdsInstance;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            /\(** creates MbkFigure Named "core" \(**/
-            MbkFigure        = addphfig("core");
-            /\(** adds Mbk instance "n1_y" to MbkFigure named "core" \(**/
-            MbkInstance      = addphins(MbkFigure,"n1_y","inv_1",NOSYM,4,9);
-            /\(** creates RdsFigure named "core_2" \(**/
-            RdsFigure        = addrdsfig("core_2",sizeof(UserStruct));
-            /\(** creates RdsInstance with MbkInstance \(**/
-            RdsInstance      = insmbkrds ( RdsFigure, MbkInstance, 'A', 0 );
-            /\(** views Mbk and Rds Instance \(**/
-            /\(** \(**/ \fBviewrfmins\fP ( MbkInstance, RdsInstance );            
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librfm,
-.BR insmbkrds
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viewrfmrec.3 b/alliance/share/man/man3/viewrfmrec.3
deleted file mode 100644
index 0ee94b85..00000000
--- a/alliance/share/man/man3/viewrfmrec.3
+++ /dev/null
@@ -1,75 +0,0 @@
-.\"   $Id: viewrfmrec.3,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.\" @(#)viewrfmrec.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-viewrfmrec
-.XE
-.XS0 \n%
-.ti 0.2i
-viewrfmrec
-.XE0 \}
-.TH VIEWRFMREC 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-viewrfmrec \- displays rectangle caracteristics in RDS format.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rfmnnn.h"
- Void viewrfmrec( Rectangle )
-    rdsrec_list \(**Rectangle;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIRectangle\fP
-RDS rectangle to visualizate.
-.SH DESCRIPTION
-The \fIviewrfmrec\fP function displays all rectangles which constitute a RDS object.
-.SH RETURN VALUE
-nothing
-.SH ERRORS
-none
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mphnnn.h"
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rfmnnn.h"
-        #include "rtlnnn.h"
-        typedef struct UserStruct
-         {
-           char \(**STRING;
-           void \(**USER1;
-         } UserStruct;
-        main()
-          {
-            phfig_list  \(**MbkFigure;
-            rdsfig_list \(**RdsFigure;
-            rdsrec_list \(**Via;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            RdsFigure = addrdsfig ("core",sizeof ( UserStruct ) );
-            MbkFigure->PHVIA = addphvia ( MbkFigure, CONT_VIA, 4, 7);
-            Via = viambkrds(RdsFigure, MbkFigure->PHVIA);
-            /\(** \(**/ \fBviewrfmrec\fP ( Via );            
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librfm
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viewrfmref.3 b/alliance/share/man/man3/viewrfmref.3
deleted file mode 100644
index e636cc19..00000000
--- a/alliance/share/man/man3/viewrfmref.3
+++ /dev/null
@@ -1,81 +0,0 @@
-.\"   $Id: viewrfmref.3,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.\" @(#)viewrfmref.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-viewrfmref
-.XE
-.XS0 \n%
-.ti 0.2i
-viewrfmref
-.XE0 \}
-.TH VIEWRFMREF 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-viewrfmref \- displays reference caracteristics in MBK and RDS format.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rfmnnn.h"
- void viewrfmref( Reference, Rectangle )
-    phref_list  \(**Reference;
-    rdsrec_list \(**Rectangle;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIreference\fP
-MBK reference to visualizate.
-.TP
-\fIRectangle\fP
-RDS reference to visualizate.
-.SH DESCRIPTION
-The \fIviewrfmref\fP function displays caracteristics of a reference in MBK and RDS format.
-.SH RETURN VALUE
-nothing
-.SH ERRORS
-none
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mphnnn.h"
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rfmnnn.h"
-        #include "rtlnnn.h"
-        typedef struct UserStruct
-         {
-           char \(**STRING;
-           void \(**USER1;
-         } UserStruct;
-        main()
-          {
-            phfig_list  \(**MbkFigure;
-            rdsfig_list \(**RdsFigure;
-            rdsrec_list \(**RdsReference;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            RdsFigure = addrdsfig ("core",sizeof ( UserStruct ) );
-            MbkFigure->PHREF = addphref ( MbkFigure, "ref_con", "rc_1", 2, 12);
-            RdsReference = refmbkrds(RdsFigure, MbkFigure->PHREF);
-            /\(** \(**/ \fBviewrfmref\fP ( MbkFigure->PHREF, RdsReference);            
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librfm,
-.BR refmbkrds,
-.BR insrefmbkrds
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viewrfmseg.3 b/alliance/share/man/man3/viewrfmseg.3
deleted file mode 100644
index 0f850ef1..00000000
--- a/alliance/share/man/man3/viewrfmseg.3
+++ /dev/null
@@ -1,83 +0,0 @@
-.\"   $Id: viewrfmseg.3,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.\" @(#)viewrfmseg.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-viewrfmseg
-.XE
-.XS0 \n%
-.ti 0.2i
-viewrfmseg
-.XE0 \}
-.TH VIEWRFMSEG 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-viewrfmseg \- displays segment caracteristics in MBK and RDS format.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rfmnnn.h"
- void viewrfmseg( Segment, Rectangle )
-    phseg_list  \(**Segment;
-    rdsrec_list \(**Rectangle;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fISegment\fP
-MBK segment to visualizate. 
-.TP
-\fIRectangle\fP
-RDS segment to visualizate.
-.SH DESCRIPTION
-The \fIviewrfmseg\fP function displays caracteristics of a segment in MBK and RDS format.
-.SH RETURN VALUE
-nothing
-.SH ERRORS
-none
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mphnnn.h"
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rfmnnn.h"
-        #include "rtlnnn.h"
-        typedef struct UserStruct
-         {
-           char \(**STRING;
-           void \(**USER1;
-         } UserStruct;
-        main()
-          {
-            phfig_list  \(**MbkFigure;
-            rdsfig_list \(**RdsFigure;
-            rdsrec_list \(**RdsSegment;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            RdsFigure =
-                addrdsfig ("core",sizeof ( UserStruct ) );
-            MbkFigure->PHSEG =
-                addphseg ( MbkFigure, ALU1, 1, 1, 1, 2, 12, "seg_alu1");
-            RdsSegment = segmbkrds(RdsFigure, MbkFigure->PHSEG,0);
-            /\(** \(**/ \fBviewrfmseg\fP ( MbkFigure->PHSEG, RdsSegment );            
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librfm,
-.BR segmbkrds,
-.BR inssegmbkrds
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/viewrfmvia.3 b/alliance/share/man/man3/viewrfmvia.3
deleted file mode 100644
index 22923b13..00000000
--- a/alliance/share/man/man3/viewrfmvia.3
+++ /dev/null
@@ -1,81 +0,0 @@
-.\"   $Id: viewrfmvia.3,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.\" @(#)viewrfmvia.1 1.11 93/08/18 ; Labo masi cao-vlsi
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-viewrfmvia
-.XE
-.XS0 \n%
-.ti 0.2i
-viewrfmvia
-.XE0 \}
-.TH VIEWRFMVIA 3 "October 1, 1997" "ASIM/LIP6" "RDS PHYSICAL FUNCTIONS"
-.SH NAME
-viewrfmvia \- displays contact caracteristics in MBK and RDS format.
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "rfmnnn.h"
-void viewrfmvia( Via, Rectangle )
-   phvia_list  \(**Via;
-   rdsrec_list \(**Rectangle;
-.ft R
-.fi
-.SH PARAMETER
-.TP 20
-\fIVia\fP
-MBK contact to visualizate.
-.TP
-\fIRectangle\fP
-RDS contact Rds to visualizate.
-.SH DESCRIPTION
-The \fIviewrfmvia\fP function displays caracteristics of a contact in MBK and RDS format.
-.SH RETURN VALUE
-nothing
-.SH ERRORS
-none
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-        #include "mphnnn.h"
-        #include "mutnnn.h"
-        #include "rdsnnn.h"
-        #include "rfmnnn.h"
-        #include "rtlnnn.h"
-        typedef struct UserStruct
-         {
-           char \(**STRING;
-           void \(**USER1;
-         } UserStruct;
-        main()
-          {
-            phfig_list  \(**MbkFigure;
-            rdsfig_list \(**RdsFigure;
-            rdsrec_list \(**RdsVia;
-            mbkenv();
-            rdsenv();
-            loadrdsparam();
-            RdsFigure = addrdsfig ("core",sizeof ( UserStruct ) );
-            MbkFigure->PHVIA = addphvia ( MbkFigure, CONT_VIA, 3, 7);
-            RdsVia = viambkrds(RdsFigure, MbkFigure->PHVIA);
-            /\(** \(**/ \fBviewrfmvia\fP ( MbkFigure->PHVIA, RdsVia );            
-          }
-.ft R
-.fi
-.SH SEE ALSO
-.BR librfm,
-.BR viambkrds,
-.BR insviambkrds
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man3/xyflat.3 b/alliance/share/man/man3/xyflat.3
deleted file mode 100644
index 6995b20f..00000000
--- a/alliance/share/man/man3/xyflat.3
+++ /dev/null
@@ -1,90 +0,0 @@
-.\"   $Id: xyflat.3,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.\" @(#)xyflat.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-xyflat
-.XE \}
-.TH XYFLAT 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL FUNCTIONS"
-.SH NAME
-xyflat \- compute hierarchical coordinates
-.so man1/alc_origin.1
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-void xyflat(xout, yout, x, y, xins, yins, x1, y1, x2, y2, trsf)
-long \(**xout, \(**yout;
-long x, y;
-long xins, yins;
-long x1, y1, x2, y2;
-char trsf;
-.ft R
-.fi
-.SH PARAMETERS
-.TP 20
-\fIxout, yout\fP
-Values filled by the function call, return values, that represent coordinates
-of the point in the figure
-.TP
-\fIx, y\fP
-Coordinates of a point in the instance
-.TP
-\fIxins, yins\fP
-Coordinates of the lower left corner of the instance
-.TP
-\fIx1, y1, x2, y2\fP
-Coordinates of the \fIabutment box\fP of the model of the instance
-.TP
-\fItrsf\fP
-Geometrical operation applied to the instance
-.SH DESCRIPTION
-\fBxyflat\fP computes coordinates relative to a model of instance in order to
-give them in figure coordinates, taking care of the transformation performed
-on the instance.
-.br
-This function is very useful when flattening, or getting coordinates of an
-object belonging to an istance at figure level.
-.br
-Care must be taken that the \fIx1, y1, x2, y2\fP parameters are \fInot\fP the
-current figure \fIabutment box\fP coordinates, but the instance model
-\fIabutment box\fP coordinates.
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include "mph402.h"
-long GET_CON_X(insname, conname, index)
-char \(**insname, \(**conname;
-long index;
-{
-phfig_list \(**ptfig; /\(** pointer on model of instance called insname \(**/
-phins_list \(**ptins; /\(** pointer on instance called insname \(**/
-phcon_list \(**ptcon; /\(** pointer on the conname called con inside ptins \(**/
-long x_con, y_con; /\(** return values, y_con here for beauty \(**/
-	ptins = getphins(WORK_PHFIG, insname);
-	ptfig = getphfig(ptins\->FIGNAME, 'P');
-	ptcon = getphcon(ptfig, conname, index);
-	xyflat(&x_con, &y_con, ptcon\->XCON, ptcon\->YCON,
-		ptins\->XINS, ptins\->YIINS,
-		ptfig\->XAB1, ptfig\->YAB1, ptfig\->XAB2, ptfig\->YAB2,
-		ptins\->TRANSF);
-	return x_con;
-}
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR phfig (3),
-.BR phins (3).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/a2_dp.5 b/alliance/share/man/man5/a2_dp.5
deleted file mode 100644
index 2759b2ab..00000000
--- a/alliance/share/man/man5/a2_dp.5
+++ /dev/null
@@ -1,68 +0,0 @@
-.\"   $Id: a2_dp.5,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.TH A2_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBa2_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "a2_dp", "insname", "i0", "i1", "o", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  a2_dp  IS
-  PORT(
-         i0 : in        BIT;
-         i1 : in        BIT;
-          o :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  a2_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  a2_dp  IS
-
-BEGIN
-  -- Logical equations.
-  o     <= (i0 and i1);
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 24 lambdas, or 4 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-i1	:	cin	=	34	(fF)
-.br
-		tphh	=	835	(ps) +	2998	(ohms) x Cload (pF)
-.br
-		tpll	=	1360	(ps) +	2418	(ohms) x Cload (pF)
-.br
-
-i0	:	cin	=	34	(fF)
-.br
-		tphh	=	902	(ps) +	2998	(ohms) x Cload (pF)
-.br
-		tpll	=	1258	(ps) +	2418	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/a2_y.5 b/alliance/share/man/man5/a2_y.5
deleted file mode 100644
index 11a8f121..00000000
--- a/alliance/share/man/man5/a2_y.5
+++ /dev/null
@@ -1,39 +0,0 @@
-.\"   $Id: a2_y.5,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.pl -.4
-.TH A2_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B a2_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("a2_y","name","i0","i1","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity a2_y is
-     port(
-        i0 : in bit;
-        i1 : in bit;
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    t <= (i0 and i1);
-   
-.br
-.I - Physical features
-   number of grids : 4
-   number of feed-through : 1
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 35 (fF)
-.br
-   i1 : 36 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/a2p_dp.5 b/alliance/share/man/man5/a2p_dp.5
deleted file mode 100644
index 6005e905..00000000
--- a/alliance/share/man/man5/a2p_dp.5
+++ /dev/null
@@ -1,68 +0,0 @@
-.\"   $Id: a2p_dp.5,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.TH A2P_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBa2p_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "a2p_dp", "insname", "i0", "i1", "o", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  a2p_dp  IS
-  PORT(
-         i0 : in        BIT;
-         i1 : in        BIT;
-          o :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  a2p_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  a2p_dp  IS
-
-BEGIN
-  -- Logical equations.
-  o     <= (i0 and i1);
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 24 lambdas, or 4 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-i1	:	cin	=	43	(fF)
-.br
-		tphh	=	793	(ps) +	1699	(ohms) x Cload (pF)
-.br
-		tpll	=	1293	(ps) +	1314	(ohms) x Cload (pF)
-.br
-
-i0	:	cin	=	44	(fF)
-.br
-		tphh	=	858	(ps) +	1699	(ohms) x Cload (pF)
-.br
-		tpll	=	1197	(ps) +	1314	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/a2p_y.5 b/alliance/share/man/man5/a2p_y.5
deleted file mode 100644
index c77a9cd3..00000000
--- a/alliance/share/man/man5/a2p_y.5
+++ /dev/null
@@ -1,39 +0,0 @@
-.\"   $Id: a2p_y.5,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.pl -.4
-.TH A2P_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B a2p_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("a2p_y","name","i0","i1","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity a2p_y is
-     port(
-        i0 : in bit;
-        i1 : in bit;
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    t <= (i0 and i1);
-   
-.br
-.I - Physical features
-   number of grids : 4
-   number of feed-through : 1
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 47 (fF)
-.br
-   i1 : 47 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/a3_dp.5 b/alliance/share/man/man5/a3_dp.5
deleted file mode 100644
index aeb5e4cb..00000000
--- a/alliance/share/man/man5/a3_dp.5
+++ /dev/null
@@ -1,76 +0,0 @@
-.\"   $Id: a3_dp.5,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.TH A3_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBa3_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "a3_dp", "insname", "i0", "i1", "i2", "o", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  a3_dp  IS
-  PORT(
-         i0 : in        BIT;
-         i1 : in        BIT;
-         i2 : in        BIT;
-          o :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  a3_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  a3_dp  IS
-
-BEGIN
-  -- Logical equations.
-  o     <= ((i0 and i1) and i2);
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 30 lambdas, or 5 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-i2	:	cin	=	33	(fF)
-.br
-		tphh	=	1155	(ps) +	2998	(ohms) x Cload (pF)
-.br
-		tpll	=	1545	(ps) +	2418	(ohms) x Cload (pF)
-.br
-
-i1	:	cin	=	33	(fF)
-.br
-		tphh	=	1229	(ps) +	2998	(ohms) x Cload (pF)
-.br
-		tpll	=	1449	(ps) +	2418	(ohms) x Cload (pF)
-.br
-
-i0	:	cin	=	33	(fF)
-.br
-		tphh	=	1263	(ps) +	2998	(ohms) x Cload (pF)
-.br
-		tpll	=	1350	(ps) +	2418	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/a3_y.5 b/alliance/share/man/man5/a3_y.5
deleted file mode 100644
index 4e3f7204..00000000
--- a/alliance/share/man/man5/a3_y.5
+++ /dev/null
@@ -1,42 +0,0 @@
-.\"   $Id: a3_y.5,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.pl -.4
-.TH A3_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B a3_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("a3_y","name","i0","i1","i2","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity a3_y is
-     port(
-        i0 : in bit;
-        i1 : in bit;
-        i2 : in bit;
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    t <= ((i0 and i1) and i2);
-   
-.br
-.I - Physical features
-   number of grids : 5
-   number of feed-through : 1
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 36 (fF)
-.br
-   i1 : 36 (fF)
-.br
-   i2 : 36 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/a3p_dp.5 b/alliance/share/man/man5/a3p_dp.5
deleted file mode 100644
index 611dc026..00000000
--- a/alliance/share/man/man5/a3p_dp.5
+++ /dev/null
@@ -1,76 +0,0 @@
-.\"   $Id: a3p_dp.5,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.TH A3P_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBa3p_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "a3p_dp", "insname", "i0", "i1", "i2", "o", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  a3p_dp  IS
-  PORT(
-         i0 : in        BIT;
-         i1 : in        BIT;
-         i2 : in        BIT;
-          o :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  a3p_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  a3p_dp  IS
-
-BEGIN
-  -- Logical equations.
-  o     <= ((i0 and i1) and i2);
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 30 lambdas, or 5 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-i2	:	cin	=	51	(fF)
-.br
-		tphh	=	1064	(ps) +	1699	(ohms) x Cload (pF)
-.br
-		tpll	=	1354	(ps) +	1314	(ohms) x Cload (pF)
-.br
-
-i1	:	cin	=	53	(fF)
-.br
-		tphh	=	1135	(ps) +	1699	(ohms) x Cload (pF)
-.br
-		tpll	=	1267	(ps) +	1314	(ohms) x Cload (pF)
-.br
-
-i0	:	cin	=	52	(fF)
-.br
-		tphh	=	1163	(ps) +	1699	(ohms) x Cload (pF)
-.br
-		tpll	=	1177	(ps) +	1314	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/a3p_y.5 b/alliance/share/man/man5/a3p_y.5
deleted file mode 100644
index 9084050c..00000000
--- a/alliance/share/man/man5/a3p_y.5
+++ /dev/null
@@ -1,42 +0,0 @@
-.\"   $Id: a3p_y.5,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.pl -.4
-.TH A3P_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B a3p_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("a3p_y","name","i0","i1","i2","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity a3p_y is
-     port(
-        i0 : in bit;
-        i1 : in bit;
-        i2 : in bit;
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    t <= ((i0 and i1) and i2);
-   
-.br
-.I - Physical features
-   number of grids : 5
-   number of feed-through : 1
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 58 (fF)
-.br
-   i1 : 58 (fF)
-.br
-   i2 : 58 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/a4_dp.5 b/alliance/share/man/man5/a4_dp.5
deleted file mode 100644
index b856bbb5..00000000
--- a/alliance/share/man/man5/a4_dp.5
+++ /dev/null
@@ -1,84 +0,0 @@
-.\"   $Id: a4_dp.5,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.TH A4_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBa4_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "a4_dp", "insname", "i0", "i1", "i2", "i3", "o", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  a4_dp  IS
-  PORT(
-         i0 : in        BIT;
-         i1 : in        BIT;
-         i2 : in        BIT;
-         i3 : in        BIT;
-          o :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  a4_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  a4_dp  IS
-
-BEGIN
-  -- Logical equations.
-  o     <= (((i0 and i1) and i2) and i3);
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 36 lambdas, or 6 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-i3	:	cin	=	67	(fF)
-.br
-		tphh	=	885	(ps) +	2998	(ohms) x Cload (pF)
-.br
-		tpll	=	1940	(ps) +	2418	(ohms) x Cload (pF)
-.br
-
-i2	:	cin	=	69	(fF)
-.br
-		tphh	=	936	(ps) +	2998	(ohms) x Cload (pF)
-.br
-		tpll	=	1773	(ps) +	2418	(ohms) x Cload (pF)
-.br
-
-i1	:	cin	=	69	(fF)
-.br
-		tphh	=	949	(ps) +	2998	(ohms) x Cload (pF)
-.br
-		tpll	=	1603	(ps) +	2418	(ohms) x Cload (pF)
-.br
-
-i0	:	cin	=	69	(fF)
-.br
-		tphh	=	917	(ps) +	2998	(ohms) x Cload (pF)
-.br
-		tpll	=	1427	(ps) +	2418	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/a4_y.5 b/alliance/share/man/man5/a4_y.5
deleted file mode 100644
index 7b85342e..00000000
--- a/alliance/share/man/man5/a4_y.5
+++ /dev/null
@@ -1,45 +0,0 @@
-.\"   $Id: a4_y.5,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.pl -.4
-.TH A4_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B a4_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("a4_y","name","i0","i1","i2","i3","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity a4_y is
-     port(
-        i0 : in bit;
-        i1 : in bit;
-        i2 : in bit;
-        i3 : in bit;
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    t <= (((i0 and i1) and i2) and i3);
-   
-.br
-.I - Physical features
-   number of grids : 6
-   number of feed-through : 1
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 46 (fF)
-.br
-   i1 : 46 (fF)
-.br
-   i2 : 46 (fF)
-.br
-   i3 : 46 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/a4p_dp.5 b/alliance/share/man/man5/a4p_dp.5
deleted file mode 100644
index 512035ff..00000000
--- a/alliance/share/man/man5/a4p_dp.5
+++ /dev/null
@@ -1,84 +0,0 @@
-.\"   $Id: a4p_dp.5,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.TH A4P_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBa4p_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "a4p_dp", "insname", "i0", "i1", "i2", "i3", "o", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  a4p_dp  IS
-  PORT(
-         i0 : in        BIT;
-         i1 : in        BIT;
-         i2 : in        BIT;
-         i3 : in        BIT;
-          o :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  a4p_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  a4p_dp  IS
-
-BEGIN
-  -- Logical equations.
-  o     <= (((i0 and i1) and i2) and i3);
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 36 lambdas, or 6 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-i3	:	cin	=	67	(fF)
-.br
-		tphh	=	952	(ps) +	1699	(ohms) x Cload (pF)
-.br
-		tpll	=	2012	(ps) +	1314	(ohms) x Cload (pF)
-.br
-
-i2	:	cin	=	68	(fF)
-.br
-		tphh	=	1005	(ps) +	1699	(ohms) x Cload (pF)
-.br
-		tpll	=	1846	(ps) +	1314	(ohms) x Cload (pF)
-.br
-
-i1	:	cin	=	68	(fF)
-.br
-		tphh	=	1022	(ps) +	1699	(ohms) x Cload (pF)
-.br
-		tpll	=	1678	(ps) +	1314	(ohms) x Cload (pF)
-.br
-
-i0	:	cin	=	68	(fF)
-.br
-		tphh	=	996	(ps) +	1699	(ohms) x Cload (pF)
-.br
-		tpll	=	1505	(ps) +	1314	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/a4p_y.5 b/alliance/share/man/man5/a4p_y.5
deleted file mode 100644
index ce62414a..00000000
--- a/alliance/share/man/man5/a4p_y.5
+++ /dev/null
@@ -1,45 +0,0 @@
-.\"   $Id: a4p_y.5,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.pl -.4
-.TH A4P_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B a4p_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("a4p_y","name","i0","i1","i2","i3","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity a4p_y is
-     port(
-        i0 : in bit;
-        i1 : in bit;
-        i2 : in bit;
-        i3 : in bit;
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    t <= (((i0 and i1) and i2) and i3);
-   
-.br
-.I - Physical features
-   number of grids : 7
-   number of feed-through : 2
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 80 (fF)
-.br
-   i1 : 80 (fF)
-.br
-   i2 : 80 (fF)
-.br
-   i3 : 83 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/ai.5 b/alliance/share/man/man5/ai.5
deleted file mode 100644
index 92c2fd9a..00000000
--- a/alliance/share/man/man5/ai.5
+++ /dev/null
@@ -1,210 +0,0 @@
-.\"   $Id: ai.5,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.\" @(#)ai.5 2.00 27 July 1993 UPMC; Author: Vincent POUILLEY
-.TH AI 5 "October 1, 1997" "ASIM/LIP6" "File Formats"
-.SH NAME
-ai \- Alliance icon format
-.so man1/alc_origin.1
-.SH DESCRIPTION
-The .ai format is the ALLIANCE format for the icon view of
-a cell. We give below the BNF description of the format :
-.nf
-
-file ::=
-     version
-     header
-     bounding_box
-     model_name
-     instance_name
-     label
-     connectors
-     lines
-     shapes
-     circles
-     arcs
-     end_of_file
-
-version ::= 'V ALLIANCE : ' version_number
-
-header ::= 'H ' name ',' file_type ',' date
-   /// name : name of the figure
-   /// date : saving file date
-
-bounding_box ::= 'B ' x ',' y ',' width ',' height
-
-model_name ::= 'M ' x ',' y ',' horizontal_alignment
-               vertical_halignment ',' direction
-
-instance_name ::= 'I ' x ',' y ',' horizontal_alignment
-                  vertical_halignment ',' direction
-
-label ::= 'T ' x ',' y ',' horizontal_alignment
-          vertical_halignment ',' direction
-
-connectors ::= { connector }
-
-connector ::= 'C ' x ',' y ',' side ',' logical_direction
-              ',' name ',' x_name ',' y_name ','
-              horizontal_alignment vertical_halignment ','
-              direction
-
-lines ::= { line }
-
-line ::= 'L ' x0 ',' y0 ',' x1 ',' y1
-
-shapes ::= { shape components }
-   /// a shape is folowed by his components
-
-shape ::= 'S ' number_of_component
-
-components ::= { component }
-
-component ::= 'P ' x ',' y ',' type
-
-circles ::= { circle }
-
-circle ::= 'R ' x0 ',' y0 ',' width ',' height
-
-arcs ::= { arc }
-
-arc ::= 'A ' x0 ',' y0 ',' width ',' height ',' angle1 ','
-        angle2
-
-end_of_file ::= 'EOF'
-
-version_number ::= number
-
-file_type ::= 'I'
-
-date ::= day '/' month '/' year
-
-horizontal_alignment ::= 'R' | 'C' | 'L'
-   /// R : right
-   /// C : center
-   /// L : left
-
-vertical_alignment ::= 'U' | 'C' | 'D'
-   /// U : up
-   /// C : center
-   /// D : down
-
-direction ::= 'H' | 'V'
-   /// H : horizontal
-   /// V : vertical
-
-side ::= 'N' | 'S' | 'W' | 'E'
-   /// N : north
-   /// S : south
-   /// W : west
-   /// E : east
-
-logical_direction ::= 'IN' | 'OUT' | 'INOUT' | 'UNKNOWN' |
-                      'TRISTATE' | 'TRANSCV'
-   /// in : input
-   /// out : output
-   /// inout : input and output
-   /// unknown : no information is available
-   /// tristate : tristate output
-   /// transcv : tristate output and input
-
-x ::= number
-
-y ::= number
-
-width ::= number
-
-height ::= number
-
-x_name ::= number
-
-y_name ::= number
-
-x0 ::= number
-
-y0 ::= number
-
-x1 ::= number
-
-y1 ::= number
-
-number_of_component ::= number
-
-type ::= 'L' | 'S' | 'E' | 'C' | 'A'
-   /// L : COMP_ISLINE
-   /// S : COMP_ISARCSTART
-   /// E : COMP_ISARCEND
-   /// C : COMP_ISARCCOMP
-   /// A : COMP_ISARCSTART & COMP_ISARCEND
-
-angle1 ::= number
-
-angle2 ::= number
-
-number ::= { '0' | '1'| '2' | '3' | '4' | '5' |
-             '6' | '7'| '8' | '9' }
-
-name ::= word
-
-.fi
-.SH EXAMPLES
-.LP
-.SS Example 1
-This example is the representation of a nand whith two input.
-.LP
-.nf
-V ALLIANCE : 2
-H na2_y,I,09/08/93
-B 0,-40,90,60
-M 40,-10,CC,H
-I 40,-40,CC,H
-T 40,20,CC,H
-C 0,-20,W,IN,i0,0,-25,RD,H
-C 0,0,W,IN,i1,0,-5,RD,H
-C 90,-10,E,OUT,f,90,-15,LD,H
-L 40,-30,20,-30
-L 20,10,20,-30
-L 20,10,40,10
-L 70,-10,90,-10
-L 0,-20,20,-20
-L 20,0,0,0
-R 60,-15,10,10
-A 20,-30,40,40,270,180
-EOF
-.fi
-.SS Example 2
-This example is a latch with a shape.
-.LP
-.nf
-V ALLIANCE : 2
-H l1_dp,I,03/03/93
-B 0,0,100,90
-M 50,60,CC,H
-I 50,0,CC,H
-T 40,80,CC,H
-C 0,40,W,IN,i,0,35,RD,H
-C 100,40,E,OUT,o,100,35,LD,H
-C 50,90,S,IN,ck,50,85,CD,H
-L 100,40,80,40
-L 20,40,0,40
-L 50,70,50,90
-L 50,40,20,70
-L 50,40,80,70
-S 4
-P 20,70,L
-P 80,70,L
-P 80,10,L
-P 20,10,L
-EOF
-.fi
-.SH SEE ALSO
-.BR Alliance (1),
-.BR icongate (3),
-.BR iconcon (3),
-.BR iconline (3),
-.BR iconshape (3),
-.BR iconcomp (3),
-.BR iconcircle (3),
-.BR iconarc (3),
-.BR MBK (1)
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/al.5 b/alliance/share/man/man5/al.5
deleted file mode 100644
index 5c5a0fb5..00000000
--- a/alliance/share/man/man5/al.5
+++ /dev/null
@@ -1,348 +0,0 @@
-.\" @(#)al.5 6.0 29 Mar 1999 UPMC; Author: Gregoire AVOT
-.TH AL 5 "October 1, 1997 Release 5.0" "ASIM/LIP6" "File Formats"
-.SH NAME
-al \- Alliance logical format
-.so man1/alc_origin.1
-.SH DESCRIPTION
-The .al format is the ALLIANCE format for the logical view
-of a cell. We give below the BNF description of the format :
-.nf
-
-file ::=
-     version
-     header
-     connectors
-     instances
-     transistors
-     signals
-     crosstalk_capacitances
-     end_of_file
-
-version ::= 'V ALLIANCE : ' version_number
-
-header ::= 'H ' name ',' file_type ',' date
-   /// name : name of the figure
-   /// date : saving file date
-
-connectors ::= { connector }
-
-connector ::= 'C ' name ',' connector_direction ','
-              connector_type ',' net_num [list_of_physical_node]
-
-list_of_physical_node ::= { ',' node_num }
-
-instances ::= { instance connectors }
-   /// An instance is followed by his connectors
-
-instance ::= 'I ' model_name ',' instance_name
-
-transistors ::= { transistor }
-
-transistor ::= 'T' type ',' lenght ',' width ',' drain ','
-               grid ',' source ',' bulk ',' xs ',' xd ',' ps ',' pd
-               ',' x ',' y [ ',' node_drain ',' node_grid ','
-               node_source ',' node_bulk ] ',' trname
-               
-   /// drain : number of the net connected to the drain
-   /// grid : number of the net connected to the grid
-   /// source : number of the net connected to the source
-   /// bulk : number of the net connected to the bulk
-   /// xs, xd : To compute respectivly the source and
-   ///          drain area
-   /// ps, pd : perimeter of the source and drain
-   /// x, y : coordinate of the transistor in a layout
-   /// node_drain : number of the node connected to the drain
-   /// node_grid : number of the node connected to the grid
-   /// node_source : number of the node connected to the source
-   /// node_bulk : number of the node connected to the bulk
-
-signals ::= { signal }
-
-signal := sig_index [ { resistance } ] [ { capacitance } ]
-
-sig_index ::= 'S ' net_num ',' signal_type [ list_of_signal_name ]
-
-list_of_signal_name ::= { ',' signal_name }
-
-resistance := 'R ' layer ',' node1 ',' node2 ',' resi ',' capa ','
-              x ',' y ',' dx ',' dy               
-
-capacitance := 'Q ' capa
-
-   /// Each resistance is describe as a resistor beetwen two nodes
-   /// connected to the ground with capacitor with a value of capa/2.
-   /// Capacitance is the entire capacitance of the net to ground.
-
-crosstalk_capacitances ::= { crosstalk_capacitance }
-
-crosstalk_capacitance ::= K capa ',' sig1 ',' node1 ',' sig2 ',' node2
-
-end_of_file ::= 'EOF'
-
-version_number ::= number
-
-file_type ::= 'L'
-
-date ::= day '/' month '/' year
-
-connector_direction ::= 'IN' | 'OUT' | 'INOUT' | 'UNKNOWN' |
-                        'TRISTATE' | 'TRANSCV'
-   /// in : input
-   /// out : output
-   /// inout : input and output
-   /// unknown : no information is available
-   /// tristate : tristate output
-   /// transcv : tristate output and input
-
-connector_type ::= 'EXTERNAL' | 'INTERNAL'
-
-net_num ::= number
-
-node_num ::= number
-
-model_name ::= name
-
-instance_name ::= name
-
-type ::= 'N' | 'P'
-
-lenght ::= float
-
-width ::= float
-
-drain ::= net_num
-
-grid ::= net_num
-
-source ::= net_num
-
-bulk ::= net_num
-
-node1 ::= node_num
-
-node2 ::= node_num
-
-sig1 ::= net_num
-
-sig2 ::= net_num
-
-xs ::= float
-
-xd ::= float
-
-ps ::= float
-
-pd ::= float
-
-x ::= float
-
-y ::= float
-
-dx ::= float
-
-dy ::= float
-
-trname :: name
-
-layer ::= 'X' | 'PY' | 'A1' | 'A2' | 'CY' | 'CN' | 'CP' | 'CV'
-          | 'CW' | 'CA' | 'RE'
-          
-signal_type ::= 'EXTERNAL' | 'INTERNAL'
-
-capa ::= float
-
-resi ::= float
-
-signal_name ::= name
-
-number ::= { '0' | '1'| '2' | '3' | '4' | '5' |
-             '6' | '7'| '8' | '9' }
-
-float ::= number [ '.' number ]
-
-name ::= word
-
-.fi
-.SH EXAMPLES
-.LP
-.SS Example 1
-This example is the representation of a nand whith two input, extracted
-with Lynx at transistor level.
-.LP
-.nf
-V ALLIANCE : 6
-H na2_y,L,29/ 3/99
-C vss,UNKNOWN,EXTERNAL,2,1,9
-C vdd,UNKNOWN,EXTERNAL,1,9,13
-C i1,UNKNOWN,EXTERNAL,6,1,8
-C i0,UNKNOWN,EXTERNAL,5,2,8
-C f,UNKNOWN,EXTERNAL,3,1,11
-T P,1,12,1,5,3,1,2,2,28,28,17,32.5,4,3,7,3,tr_00004
-T P,1,12,3,6,1,1,2,2,28,28,11,32.5,7,7,1,2,tr_00003
-T N,1,12,3,5,4,2,2,2,28,28,17,12.5,3,1,1,8,tr_00002
-T N,1,12,4,6,2,2,2,2,28,28,11,12.5,1,2,2,5,tr_00001
-S 6,EXTERNAL,i1
-Q 0.020455
-W 4,3,CV,0,0,7.2,17.6,0,0
-W 6,5,CV,0,0,6.4,22.4,0,0
-W 5,8,A2,0.4,0.00408,6.4,22.4,1.6,13.6
-W 1,5,A2,0.6,0.006,6.4,2.4,1.6,20
-W 3,6,A1,0.3,0.00168,6.4,17.6,1.6,4.8
-W 4,7,PY,500,0.00315,8.8,17.6,0.8,8.4
-W 2,4,PY,450,0.00285,8.8,10,0.8,7.6
-S 5,EXTERNAL,i0
-Q 0.020455
-W 5,4,CV,0,0,15.2,17.6,0,0
-W 7,6,CV,0,0,16,22.4,0,0
-W 6,8,A2,0.4,0.00408,16,22.4,1.6,13.6
-W 2,6,A2,0.6,0.006,16,2.4,1.6,20
-W 4,7,A1,0.3,0.00168,16,17.6,1.6,4.8
-W 5,3,PY,500,0.00315,13.6,17.6,0.8,8.4
-W 1,5,PY,450,0.00285,13.6,10,0.8,7.6
-S 4,INTERNAL
-Q 0
-S 3,EXTERNAL,f
-Q 0.021985
-W 3,4,CV,0,0,16,10.4,0,0
-W 6,5,CV,0,0,11.2,17.6,0,0
-W 8,7,CV,0,0,11.2,23.2,0,0
-W 9,7,CV,0,0,11.2,28,0,0
-W 5,11,A2,0.55,0.00552,11.2,17.6,1.6,18.4
-W 1,5,A2,0.45,0.00456,11.2,2.4,1.6,15.2
-W 10,9,A1,0.2,0.00126,11.2,24.4,1.6,3.6
-W 8,10,A1,0,0.00042,11.2,23.2,1.6,1.2
-W 6,8,A1,0.7,0.00161,11.2,17.6,0.8,5.6
-W 2,6,A1,0.9,0.00207,11.2,10.4,0.8,7.2
-W 2,4,A1,0.6,0.00138,11.2,10.4,4.8,0.8
-S 2,EXTERNAL,vss
-Q 0.0245
-W 4,3,CV,0,0,6.4,1.6,0,0
-W 7,6,CV,0,0,11.2,1.6,0,0
-W 11,10,CV,0,0,16,1.6,0,0
-W 3,2,CV,0,0,6.4,6.4,0,0
-W 12,2,CV,0,0,6.4,10.4,0,0
-W 3,12,A1,0.4,0.00224,6.4,4,1.6,6.4
-W 10,9,A1,0,0.00174,16,4,2.4,6.4
-W 6,10,A1,0,0.00348,11.2,4,4.8,6.4
-W 3,6,A1,0,0.00348,6.4,4,4.8,6.4
-W 1,3,A1,0,0.00174,4,4,2.4,6.4
-S 1,EXTERNAL,vdd
-Q 0.02846
-W 5,1,CV,0,0,6.4,26.4,0,0
-W 6,4,CV,0,0,16,26.4,0,0
-W 7,1,CV,0,0,6.4,29.6,0,0
-W 8,4,CV,0,0,16,29.6,0,0
-W 14,10,CV,0,0,6.4,36,0,0
-W 15,11,CV,0,0,11.2,36,0,0
-W 16,12,CV,0,0,16,36,0,0
-W 7,10,A1,0.3,0.00168,6.4,29.6,1.6,4.8
-W 5,7,A1,0.2,0.00112,6.4,26.4,1.6,3.2
-W 8,12,A1,0.3,0.00168,16,29.6,1.6,4.8
-W 6,8,A1,0.2,0.00112,16,26.4,1.6,3.2
-W 12,13,A1,0,0.00174,16,34.4,2.4,6.4
-W 9,10,A1,0,0.00174,4,34.4,2.4,6.4
-W 11,12,A1,0,0.00348,11.2,36,4.8,6.4
-W 10,11,A1,0,0.00348,6.4,36,4.8,6.4
-K 0.00213,1,1,2,1
-K 0.00454,5,6,2,1
-K 0.00199,6,8,2,1
-EOF
-.fi
-.SS Example 2
-This example is a xor designed with three cells.
-.LP
-.nf
-V ALLIANCE : 6
-H gxor,L,29/ 3/99
-C vss,UNKNOWN,EXTERNAL,4,1,2,9,10
-C vdd,UNKNOWN,EXTERNAL,6,1,2,10,3
-C s,UNKNOWN,EXTERNAL,8,2
-C b,UNKNOWN,EXTERNAL,5,5
-C a,UNKNOWN,EXTERNAL,3,1
-I ndrvp_y,auxsc3
-C vss,UNKNOWN,INTERNAL,4,8,9
-C vdd,UNKNOWN,INTERNAL,6,9,10
-C i,UNKNOWN,INTERNAL,5,4,9
-C f,UNKNOWN,INTERNAL,7,8,12
-I mx2_y,s
-C vss,UNKNOWN,INTERNAL,4,4,8
-C vdd,UNKNOWN,INTERNAL,6,5,9
-C t,UNKNOWN,INTERNAL,8,1,3
-C l1,UNKNOWN,INTERNAL,7,1,11
-C l0,UNKNOWN,INTERNAL,2,4,8
-C i1,UNKNOWN,INTERNAL,3,11,13
-C i0,UNKNOWN,INTERNAL,5,1,8
-I ndrvp_y,auxsc1
-C vss,UNKNOWN,INTERNAL,4,2,3
-C vdd,UNKNOWN,INTERNAL,6,2,4
-C i,UNKNOWN,INTERNAL,3,10,12
-C f,UNKNOWN,INTERNAL,2,1,7
-S 8,EXTERNAL,s
-Q 0.0072
-W 2,1,A2,0.55,0.00528,79.2,0,1.6,17.6
-S 7,INTERNAL,auxsc3
-Q 0.02142
-W 3,2,CV,0,0,64.8,8.8,0,0
-W 5,4,CV,0,0,74.4,8.8,0,0
-W 7,6,CV,0,0,74.4,12.8,0,0
-W 10,9,CV,0,0,88.8,12.8,0,0
-W 9,8,A2,0.15,0.00144,88.8,12.8,1.6,4.8
-W 6,10,A1,1.8,0.00414,74.4,12.8,14.4,0.8
-W 4,7,A2,0.1,0.0012,74.4,8.8,1.6,4
-W 2,1,A2,0.25,0.00264,64.8,8.8,1.6,8.8
-W 3,5,A1,1.2,0.00276,64.8,8.8,9.6,0.8
-S 6,EXTERNAL,vdd
-Q 0.05453
-W 7,6,CV,0,0,37.6,48,0,0
-W 8,6,CV,0,0,37.6,51.2,0,0
-W 6,5,A1,0.1,0.00754,37.6,49.6,10.4,6.4
-W 4,6,A1,0,0.0029,33.6,49.6,4,6.4
-W 8,3,A2,0.05,0.00203,37.6,51.2,3.2,5.6
-W 7,8,A2,0.05,0.00116,37.6,48,3.2,3.2
-W 1,7,A2,0.75,0.0174,37.6,0,3.2,48
-S 5,EXTERNAL,b
-Q 0.02922
-W 3,2,CV,0,0,50.4,4.8,0,0
-W 7,6,CV,0,0,98.4,4.8,0,0
-W 6,4,A2,0.4,0.00384,98.4,4.8,1.6,12.8
-W 5,6,A2,0.15,0.00144,98.4,0,1.6,4.8
-W 2,1,A2,0.4,0.00384,50.4,4.8,1.6,12.8
-W 3,7,A1,6,0.0138,50.4,4.8,48,0.8
-S 4,EXTERNAL,vss
-Q 0.05453
-W 6,5,CV,0,0,44,17.6,0,0
-W 6,7,CV,0,0,44,20.8,0,0
-W 7,10,A2,0.55,0.01305,44,20.8,3.2,36
-W 1,5,A2,0.25,0.00638,44,0,3.2,17.6
-W 5,7,A2,0.05,0.00116,44,17.6,3.2,3.2
-W 6,4,A1,0,0.0029,44,19.2,4,6.4
-W 3,6,A1,0.1,0.00754,33.6,19.2,10.4,6.4
-S 3,EXTERNAL,a
-Q 0.03282
-W 3,2,CV,0,0,16.8,8.8,0,0
-W 5,4,CV,0,0,60,8.8,0,0
-W 7,6,CV,0,0,60,12.8,0,0
-W 9,8,CV,0,0,69.6,12.8,0,0
-W 8,11,A2,0.15,0.00144,69.6,12.8,1.6,4.8
-W 6,9,A1,1.2,0.00276,60,12.8,9.6,0.8
-W 4,7,A2,0.1,0.0012,60,8.8,1.6,4
-W 2,10,A2,0.25,0.00264,16.8,8.8,1.6,8.8
-W 1,2,A2,0.25,0.00264,16.8,0,1.6,8.8
-W 3,5,A1,5.4,0.01242,16.8,8.8,43.2,0.8
-S 2,INTERNAL,auxsc1
-Q 0.0225
-W 3,2,CV,0,0,7.2,12.8,0,0
-W 6,5,CV,0,0,55.2,12.8,0,0
-W 5,4,A2,0.15,0.00144,55.2,12.8,1.6,4.8
-W 2,1,A2,0.15,0.00144,7.2,12.8,1.6,4.8
-W 3,6,A1,6,0.0138,7.2,12.8,48,0.8
-S 1,INTERNAL,implicit
-Q 0
-EOF
-.fi
-.SH SEE ALSO
-.BR Alliance (1),
-.BR MBK (1)
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/annup_dp.5 b/alliance/share/man/man5/annup_dp.5
deleted file mode 100644
index fdeef355..00000000
--- a/alliance/share/man/man5/annup_dp.5
+++ /dev/null
@@ -1,84 +0,0 @@
-.\"   $Id: annup_dp.5,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.TH ANNUP_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBannup_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "annup_dp", "insname", "i0", "i1", "i2", "i3", "o", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  annup_dp  IS
-  PORT(
-         i0 : in        BIT;
-         i1 : in        BIT;
-         i2 : in        BIT;
-         i3 : in        BIT;
-          o :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  annup_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  annup_dp  IS
-
-BEGIN
-  -- Logical equations.
-  o     <= not ((i0 or i1) and (i2 or i3));
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 30 lambdas, or 5 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-i3	:	cin	=	67	(fF)
-.br
-		tplh	=	792	(ps) +	2979	(ohms) x Cload (pF)
-.br
-		tphl	=	713	(ps) +	2175	(ohms) x Cload (pF)
-.br
-
-i2	:	cin	=	67	(fF)
-.br
-		tplh	=	851	(ps) +	2979	(ohms) x Cload (pF)
-.br
-		tphl	=	519	(ps) +	2175	(ohms) x Cload (pF)
-.br
-
-i1	:	cin	=	67	(fF)
-.br
-		tplh	=	1065	(ps) +	2979	(ohms) x Cload (pF)
-.br
-		tphl	=	486	(ps) +	2175	(ohms) x Cload (pF)
-.br
-
-i0	:	cin	=	66	(fF)
-.br
-		tplh	=	994	(ps) +	2979	(ohms) x Cload (pF)
-.br
-		tphl	=	660	(ps) +	2175	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/annup_y.5 b/alliance/share/man/man5/annup_y.5
deleted file mode 100644
index 71918ac6..00000000
--- a/alliance/share/man/man5/annup_y.5
+++ /dev/null
@@ -1,45 +0,0 @@
-.\"   $Id: annup_y.5,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.pl -.4
-.TH ANNUP_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B annup_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("annup_y","name","i1","i2","i3","i4","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity annup_y is
-     port(
-        i1 : in bit;
-        i2 : in bit;
-        i3 : in bit;
-        i4 : in bit;
-        f : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    f <= ((i2 or i1) nand (i3 or i4));
-   
-.br
-.I - Physical features
-   number of grids : 5
-   number of feed-through : 0
-.br
-   
-.I - Timing caracteristics
-.br
-   i1 : 48 (fF)
-.br
-   i2 : 48 (fF)
-.br
-   i3 : 48 (fF)
-.br
-   i4 : 48 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/ap.5 b/alliance/share/man/man5/ap.5
deleted file mode 100644
index 65c25cc6..00000000
--- a/alliance/share/man/man5/ap.5
+++ /dev/null
@@ -1,348 +0,0 @@
-.\"   $Id: ap.5,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.\" @(#)Labo.l 0.0 91/04/02 UPMC; Author: Vincent POUILLEY
-.TH AP 5 "October 1, 1997" "ASIM/LIP6" "FILE FORMATS"
-.SH NAME
-ap \- Alliance physical format
-.so man1/alc_origin.1
-.SH BNF DESCRIPTION
-file ::=
-   version
-   header
-   connectors
-   segments
-   instances
-   transistors
-   patterns
-   end_of_file
-
-version ::= 'V ALLIANCE 2.2 SETUP : ' version_number
-
-header ::= 'H ' name ',' file_type ',' abindex ',' nb_desc
-           ',' date ',' index_beg ',' link_mode ','
-           bounding_box ',' [ abutment_box ]
-   /* name         : name of the figure                   */
-   /* file_type    : type of the file                     */
-   /* abindex      : index of the abutment box            */
-   /* nb_desc      : number of descriptors                */
-   /* date         : saving file date                     */
-   /* index_beg    : index of the begining of the linkage */
-   /* link_mode    : indication on the linkage            */
-   /*                (update or not)                      */
-   /* bounding_box : coordinates and size of the          */
-   /*                bounding box                         */
-   /* abutment_box : coordinates and size, if defined,    */
-   /*                of the abutment box                  */
-
-connectors ::= { connector }
-
-connector ::= 'C ' index ',' x ',' y ',' w ',' orientation
-              ',' layer ',' name ',' connector_type ','
-              nextindex ',' endnet
-   /* x, y, w  : coordinates and size of the connector    */
-   /* orientation    : north, south, east, or west        */
-   /* layer          : layer of the connector             */
-   /* name           : name of the connector              */
-   /* connector_type : input or output or ...             */
-   /* nextindex      : next index in the linkage          */
-   /* endnet         : end in the linkage of the net      */
-
-segments ::= { segment }
-
-segment ::= 'S ' index ',' x ',' y ',' d ',' w ',' direction
-            ',' layer ',' name ',' nextindex ',' endnet
-   /* x, y, d, w    : coordinates and size of the segment */
-   /* direction     : horizontaly or verticaly            */
-   /* layer         : layer of the segment                */
-   /* name          : name of the segment                 */
-   /* nextindex     : next index in the linkage           */
-   /* endnet        : end in the linkage of the net       */
-
-instances ::= { instance [ connectors ] }
-   /* In case of updated linkage, an instance is followed */
-   /* by his connectors                                   */
-
-instance ::= 'I ' index ',' x ',' y ',' instance_name ','
-             model_name ',' geoop ',' nextindex ',' endnet
-   /* x, y           : coordinates of the instance        */
-   /* instance_name  : local name of the instance         */
-   /* model_name     : name of the model                  */
-   /* geoop          : geometric operation                */
-   /* nextindex      : next index in the linkage          */
-   /* endnet         : end in the linkage of the net      */
-
-transistors ::= { transistor }
-
-transistor ::= 'T ' index ',' x ',' y ',' instance_name ','
-               trans_name ',' geoop ',' nextindex ',' endnet
-   /* x, y           : coordinates of the transistor      */
-   /* instance_name  : name of the instance               */
-   /* trans_name     : generic name of the transistor     */
-   /* geoop          : geometric operation                */
-   /* nextindex      : next index in the linkage          */
-   /* endnet         : end in the linkage of the net      */
-
-patterns ::= { pattern }
-
-pattern ::= 'M ' index ',' x ',' y ',' instance_name ','
-            pattern_name ',' int_index ',' nextindex ','
-            endnet
-   /* x, y          : coordinates of the pattern          */
-   /* instance_name : name of the instance of the pattern */
-   /* pattern_name  : name of the pattern                 */
-   /* int_index     : internal index of the pattern       */
-   /* nextindex     : next index in the linkage           */
-   /* endnet        : end in the linkage of the net       */
-
-end_of_file ::= 'EOF'
-
-version_number ::= number
-
-file_type ::= 'P'
-
-abindex ::= index
-
-nb_desc ::= number
-
-date ::= day '/' month '/' year
-
-index_beg ::= index
-
-index ::= number
-
-link_mode ::= 'A JOUR' | 'PAS A JOUR'
-   /* updated, not updated */
-
-bounding_box ::= x ',' y ',' dx ',' dy
-
-abutment_box ::= x ',' y ',' dx ',' dy
-
-x ::= number
-
-y ::= number
-
-d ::= number
-   /* lenght */
-
-w ::= number
-   /* width */
-
-dx ::= number
-
-dy ::= number
-
-direction ::= 'H' | 'V'
-   /* horizontaly or verticaly */
-
-orientation ::= 'NORD' | 'SUD' | 'EST' | 'OUEST'
-   /* North, south, east, west */
-
-layer ::= 'POLY' | 'ALU1' | 'ALU2' | 'DIFN' | 'DIFP' |
-          'T_ALU1' | 'T_ALU2' | 'CAISSON_N' | 'CAISSON_P'
-   /* poly       : polysilicium                           */
-   /* alu1       : first metal                            */
-   /* alu2       : second metal                           */
-   /* difn       : N diffusion                            */
-   /* difp       : P diffusion                            */
-   /* t_alu1     : first metal through route              */
-   /* t_alu2     : second metal through route             */
-   /* caisson_n  : N bulk                                 */
-   /* caisson_p  : P bulk                                 */
-
-connector_type ::= 'IN' | 'OUT' | 'INOUT'
-
-nextindex ::= index
-
-endnet ::= 'NON' | 'FIN'
-   /* non        : not the end of the net                 */
-   /* fin        : end of the net                         */
-
-model_name ::= name
-
-instance_name ::= name
-
-geoop ::= 'NOSYM' | 'ROT_P' | 'ROT_M' | 'SYM_X' | 'SYM_Y' |
-          'SYMXY' | 'SY_RP' | 'SY_RM'
-   /* nosym  : no operation                               */
-   /* rot_p  : rotates 90 degrees counter clockwise       */
-   /* rot_m  : rotates 90 degrees clockwise               */
-   /* sym_y  : y becomes -y                               */
-   /* sym_x  : x becomes -x                               */
-   /* symxy  : x becomes -x and y becomes -y              */
-   /* sy_rp  : x becomes -x then rotates 90 degrees       */
-   /*          counter clockwyse                          */
-   /* sy_rm  : x becomes -x then rotates 90 degrees       */
-   /*          clockwyse                                  */
-
-trans_name ::= 'T' transistor_type '_' d '_' w
-
-pattern_name ::= 'CONT_POLY' | 'CONT_DIF_N' | 'CONT_DIF_P' |
-                 'CONT_VIA' | 'C_X_N' | 'C_X_P' | 'REF_CON'
-                 | 'REF_REF'
-   /* cont_poly  : poly alu1 contact                      */
-   /* cont_dif_n : alu1 difn contact                      */
-   /* cont_dif_p : alu1 difp contact                      */
-   /* cont_via   : alu2 alu1 contact                      */
-   /* c_x_n      : L shaped N transistor corner filling   */
-   /* c_x_p      : L shaped P transistor corner filling   */
-   /* ref_con    : kind of reference, for multi-acces     */
-   /*              connectors                             */
-   /* ref_ref    : kind of reference, for all other uses  */
-
-int_index ::= index
-
-transistor_type ::= 'P' | 'N'
-
-number ::= { '0' | '1'| '2' | '3' | '4' | '5' |
-             '6' | '7'| '8' | '9' }
-
-name ::= word
-.SH EXAMPLES
-.LP
-.SS Example 1
-This example is the physical design of a nand with two input. See
-example 1 in the description of alc logical format for more
-details.
-.LP
-.nf
-V ALLIANCE 2.2 SETUP : 2
-H na2_y,P,10,66,25/10/91,-1,PAS A JOUR,0,0,28,53,5,3,18,42
-C 0,20,45,2,NORD,ALU2,i0,INOUT,-1,FIN
-C 1,14,45,2,NORD,ALU2,f,INOUT,-1,FIN
-C 2,8,45,2,NORD,ALU2,i1,INOUT,-1,FIN
-C 3,20,3,2,SUD,ALU2,i0,INOUT,-1,FIN
-C 4,14,3,2,SUD,ALU2,f,INOUT,-1,FIN
-C 5,8,3,2,SUD,ALU2,i1,INOUT,-1,FIN
-C 6,23,43,8,EST,ALU1,vdd,INOUT,-1,FIN
-C 7,5,43,8,OUEST,ALU1,vdd,INOUT,-1,FIN
-C 8,5,5,8,OUEST,ALU1,vss,INOUT,-1,FIN
-C 9,23,5,8,EST,ALU1,vss,INOUT,-1,FIN
-S 11,5,5,18,8,H,ALU1,vss,-1,FIN
-S 12,8,2,12,2,H,DIFP,*,-1,FIN
-S 13,8,27,11,3,V,DIFP,*,-1,FIN
-S 14,20,27,11,3,V,DIFP,*,-1,FIN
-S 15,20,22,6,2,V,ALU1,*,-1,FIN
-S 16,19,22,1,2,H,ALU1,*,-1,FIN
-S 17,5,43,18,8,H,ALU1,vdd,-1,FIN
-S 18,8,33,10,2,V,ALU1,vdd,-1,FIN
-S 19,8,22,6,2,V,ALU1,*,-1,FIN
-S 20,8,22,1,2,H,ALU1,*,-1,FIN
-S 21,14,30,5,2,V,ALU1,*,-1,FIN
-S 22,14,13,17,1,V,ALU1,*,-1,FIN
-S 23,14,13,6,1,H,ALU1,*,-1,FIN
-S 24,17,22,2,2,H,POLY,*,-1,FIN
-S 25,17,20,5,1,V,POLY,*,-1,FIN
-S 26,9,22,2,2,H,POLY,*,-1,FIN
-S 27,11,20,5,1,V,POLY,*,-1,FIN
-S 28,8,45,12,2,H,DIFN,*,-1,FIN
-S 29,5,39,18,26,H,CAISSON_N,*,-1,FIN
-S 30,8,7,11,3,V,DIFN,*,-1,FIN
-S 31,8,3,42,2,V,ALU2,i1,-1,FIN
-S 32,14,3,42,2,V,ALU2,f,-1,FIN
-S 33,14,27,11,3,V,DIFP,*,-1,FIN
-S 34,20,7,11,3,V,DIFN,*,-1,FIN
-S 35,14,7,11,3,V,DIFN,*,-1,FIN
-S 36,20,3,42,2,V,ALU2,i0,-1,FIN
-T 37,17,5,*,TN_15_1,NOSYM,-1,FIN
-T 38,11,5,*,TN_15_1,NOSYM,-1,FIN
-T 39,17,25,*,TP_15_1,NOSYM,-1,FIN
-T 40,11,25,*,TP_15_1,NOSYM,-1,FIN
-S 41,20,43,2,1,V,ALU1,vdd,-1,FIN
-S 42,8,45,12,1,H,ALU1,vdd,-1,FIN
-S 43,20,33,10,2,V,ALU1,vdd,-1,FIN
-S 44,8,2,11,2,V,ALU1,vss,-1,FIN
-S 45,8,2,12,2,H,ALU1,vss,-1,FIN
-M 46,20,37,*,CONT_DIF_P,2,-1,FIN
-M 47,8,37,*,CONT_DIF_P,2,-1,FIN
-M 48,14,45,*,CONT_DIF_N,1,-1,FIN
-M 49,14,2,*,CONT_DIF_P,2,-1,FIN
-M 50,8,13,*,CONT_DIF_N,1,-1,FIN
-M 51,20,13,*,CONT_DIF_N,1,-1,FIN
-M 52,8,33,*,CONT_DIF_P,2,-1,FIN
-M 53,20,33,*,CONT_DIF_P,2,-1,FIN
-M 54,9,22,*,CONT_POLY,0,-1,FIN
-M 55,19,22,*,CONT_POLY,0,-1,FIN
-M 56,8,28,*,CONT_VIA,3,-1,FIN
-M 57,20,28,*,CONT_VIA,3,-1,FIN
-M 58,14,22,*,CONT_VIA,3,-1,FIN
-M 59,8,8,*,CONT_DIF_N,1,-1,FIN
-M 60,20,2,*,CONT_DIF_P,2,-1,FIN
-M 61,8,2,*,CONT_DIF_P,2,-1,FIN
-M 62,20,45,*,CONT_DIF_N,1,-1,FIN
-M 63,8,45,*,CONT_DIF_N,1,-1,FIN
-M 64,14,29,*,CONT_DIF_P,2,-1,FIN
-M 65,14,35,*,CONT_DIF_P,2,-1,FIN
-EOF
-.fi
-.SS Example 2
-This example is the physical design of a small circuit including
-three nand.
-.LP
-.nf
-V ALLIANCE 2.2 SETUP : 2
-H test_nand,P,-1,57,12/ 4/92,10,A JOUR,3,1,61,60,
-C 0,12,2,2,SUD,ALU2,a,IN,8,FIN
-C 1,24,2,2,SUD,ALU2,b,IN,21,FIN
-C 2,30,2,2,SUD,ALU2,c,IN,19,FIN
-C 3,42,2,2,SUD,ALU2,d,IN,31,FIN
-C 4,54,2,2,SUD,ALU2,s,OUT,36,FIN
-C 5,4,47,1,EST,ALU1,vdd,IN,39,FIN
-C 6,4,8,1,EST,ALU1,vss,IN,7,FIN
-I 7,9,7,I1,na2_y,NOSYM,33,FIN
-C 8,24,49,2,NORD,ALU2,i0,INOUT,11,NON
-C 9,18,49,2,NORD,ALU2,f,INOUT,18,FIN
-C 10,12,49,2,NORD,ALU2,i1,INOUT,13,NON
-C 11,24,7,2,SUD,ALU2,i0,INOUT,41,NON
-C 12,18,7,2,SUD,ALU2,f,INOUT,9,NON
-C 13,12,7,2,SUD,ALU2,i1,INOUT,40,NON
-C 14,27,47,8,EST,ALU1,vdd,INOUT,15,NON
-C 15,9,47,8,OUEST,ALU1,vdd,INOUT,46,NON
-C 16,9,9,8,OUEST,ALU1,vss,INOUT,45,NON
-C 17,27,9,8,EST,ALU1,vss,INOUT,16,NON
-I 18,27,7,I2,na2_y,NOSYM,35,FIN
-C 19,42,49,2,NORD,ALU2,i0,INOUT,22,NON
-C 20,36,49,2,NORD,ALU2,f,INOUT,29,FIN
-C 21,30,49,2,NORD,ALU2,i1,INOUT,24,NON
-C 22,42,7,2,SUD,ALU2,i0,INOUT,43,NON
-C 23,36,7,2,SUD,ALU2,f,INOUT,20,NON
-C 24,30,7,2,SUD,ALU2,i1,INOUT,42,NON
-C 25,45,47,8,EST,ALU1,vdd,INOUT,26,NON
-C 26,27,47,8,OUEST,ALU1,vdd,INOUT,14,NON
-C 27,27,9,8,OUEST,ALU1,vss,INOUT,17,NON
-C 28,45,9,8,EST,ALU1,vss,INOUT,27,NON
-I 29,45,7,I3,na2_y,NOSYM,-1,FIN
-C 30,60,49,2,NORD,ALU2,i0,INOUT,52,NON
-C 31,54,49,2,NORD,ALU2,f,INOUT,34,NON
-C 32,48,49,2,NORD,ALU2,i1,INOUT,51,NON
-C 33,60,7,2,SUD,ALU2,i0,INOUT,30,NON
-C 34,54,7,2,SUD,ALU2,f,INOUT,44,NON
-C 35,48,7,2,SUD,ALU2,i1,INOUT,32,NON
-C 36,63,47,8,EST,ALU1,vdd,INOUT,37,NON
-C 37,45,47,8,OUEST,ALU1,vdd,INOUT,25,NON
-C 38,45,9,8,OUEST,ALU1,vss,INOUT,28,NON
-C 39,63,9,8,EST,ALU1,vss,INOUT,38,NON
-S 40,12,2,5,2,V,ALU2,*,0,NON
-S 41,24,2,5,2,V,ALU2,*,1,NON
-S 42,30,2,5,2,V,ALU2,*,2,NON
-S 43,42,2,5,2,V,ALU2,*,3,NON
-S 44,54,2,5,2,V,ALU2,*,4,NON
-S 45,4,8,5,1,H,ALU1,*,6,NON
-S 46,4,47,5,1,H,ALU1,*,5,NON
-S 47,18,55,42,1,H,ALU1,x,53,NON
-S 48,36,60,12,1,H,ALU1,y,54,NON
-S 49,18,49,6,2,V,ALU2,*,12,NON
-S 50,36,49,11,2,V,ALU2,*,23,NON
-S 51,48,49,11,2,V,ALU2,*,55,NON
-S 52,60,49,6,2,V,ALU2,*,56,NON
-M 53,18,55,*,CONT_VIA,3,49,NON
-M 54,36,60,*,CONT_VIA,3,50,NON
-M 55,48,60,*,CONT_VIA,3,48,NON
-M 56,60,55,*,CONT_VIA,3,47,NON
-EOF
-.fi
-.SH SEE ALSO
-.BR Alliance (1),
-.BR alc (1),
-.BR MBK (1)
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/b1_dp.5 b/alliance/share/man/man5/b1_dp.5
deleted file mode 100644
index 856c7a04..00000000
--- a/alliance/share/man/man5/b1_dp.5
+++ /dev/null
@@ -1,60 +0,0 @@
-.\"   $Id: b1_dp.5,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.TH B1_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBb1_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "b1_dp", "insname", "i", "o", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  b1_dp  IS
-  PORT(
-          i : in        BIT;
-          o :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  b1_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  b1_dp  IS
-
-BEGIN
-  -- Logical equations.
-  o     <= i;
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 24 lambdas, or 4 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-i	:	cin	=	43	(fF)
-.br
-		tphh	=	1018	(ps) +	849	(ohms) x Cload (pF)
-.br
-		tpll	=	1140	(ps) +	657	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/b1_y.5 b/alliance/share/man/man5/b1_y.5
deleted file mode 100644
index a76ef5de..00000000
--- a/alliance/share/man/man5/b1_y.5
+++ /dev/null
@@ -1,36 +0,0 @@
-.\"   $Id: b1_y.5,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.pl -.4
-.TH B1_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B b1_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("b1_y","name","i","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity b1_y is
-     port(
-        i : in bit;
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    t <= i;
-   
-.br
-.I - Physical features
-   number of grids : 4
-   number of feed-through : 2
-.br
-   
-.I - Timing caracteristics
-.br
-   i : 57 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/catal.5 b/alliance/share/man/man5/catal.5
deleted file mode 100644
index 8da2cd0f..00000000
--- a/alliance/share/man/man5/catal.5
+++ /dev/null
@@ -1,141 +0,0 @@
-.\"   $Id: catal.5,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.\" @(#)catal.2 2.11 91/08/22 ; Labo masi cao-vlsi; Author : Frederic Petrot
-.TH CATAL 5 "October 1, 1997" "ASIM/LIP6" "ALLIANCE FILE FORMATS"
-.if t \{\
-.so man1/alc_contents.mac
-.XS \n%
-.ti 0.2i
-catal
-.XE \}
-.SH NAME
-catal \- catalog file format
-.SH SYNOPSYS
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-#include <mutnnn.h>
-$MBK_WORK_LIB/$MBK_CATAL_NAME
-($MBK_CATA_LIB)/$MBK_CATAL_NAME
-.ft R
-.fi
-.so man1/alc_origin.1
-.SH DESCRIPTION
-.TP 
-Predefined libraries
-The environment variable \fBMBK_CATA_LIB\fP(1) defines several paths
-corresponding to the \fIAlliance\fP predefined cell libraries.
-Each library is in one unix directory.
-.RS
-.TP 20
-\fIsclib\fP
-standard cell library
-.TP 20
-\fIdplib\fP
-data-path compiler library
-.TP 20
-\fIgrlib\fP
-register file generator library
-.TP 20
-\fIbslib\fP
-barrel shifter generator library
-.TP 20
-\fIgalib\fP
-fast adder generator library
-.TP 20
-\fIrolib\fP
-high speed rom generator library
-.TP 20
-\fIralib\fP
-static ram generator library
-.PP
-Only the standart cell library \fBsclib\fP(1) is available in the Alliance 1.1
-release.
-.LP
-For each library, a special file named \fBCATAL\fP describes the library
-contents.
-This file must be in the same directory as the library cells.
-For the \fBAlliance\fP tools, the cells described in the predefined libraries
-are read only.
-.RE
-.TP
-The working library
-The environment variable \fBMBK_WORK_LIB\fP(1) defines the current working
-directory.
-Its default value is \fB.\fP (dot).
-This directory will contain the user cells, seen as read write by the
-\fIAlliance\fP tools.
-It is not necessary to describe all the user cells in a catalog file.
-But the user can locally define a catalog file for the working library.
-The local catalog file name is set by the environment variable
-\fBMBK_CATAL_NAME\fP(1), \fBCATAL\fP by default.
-\fIAlliance\fP will concatenate all catalog files of the predefined libraries
-and the optional catalog file of the working library to access the attributs
-of each cell.
-.TP
-Cells attributs
-A cell may be characterized by four attributs:
-.RS
-.TP 20
-\fBC\fP
-this attribut means that the cell is a leaf cell in the context of a recursive
-flatten, for either the layout or netlist view.
-The cell will not be flattened.
-.TP
-\fBG\fP
-this attribut means that the cell has an existing equivalent \fIGDS\fP or
-\fICIF\fP representation.
-It is used by the symbolic to real translation tool, \fBs2r\fP(1), to
-make direct replacements.
-.TP
-\fBF\fP
-this attribut means that the cell is used as a feed through by a router.
-For example, the standard cell router, \fBscr\fP(1), will use such cells to
-fill gaps in the cells rows.
-.TP
-\fBD\fP
-this attribut is used only in the user defined catalog.
-As the user is not allowed to delete a cell in a predefined library, it is 
-possible to virtually remove a cell of a predefined library with the \fBD\fP
-attribut in the user defined catalog.
-.RE
-.SH EXAMPLE
-.ta 3n 6n 9n 12n 15n 18n 21n
-.nf
-.if n \{\
-.ft B \}
-.if t \{\
-.ft CR \}
-a2_y    C
-a2p_y   C
-a3_y    C
-a3p_y   C
-n1_y    C
-na2_y   C
-p1_y    C
-tie_y   C
-	\&.
-	\&.
-	\&.
-p1_y    G
-	\&.
-	\&.
-	\&.
-tie_y   F
-.ft R
-.fi
-.SH SEE ALSO
-.BR mbk (1),
-.BR sclib (1),
-.BR incatalog (3),
-.BR incatalogdelete (3),
-.BR incatalogfeed (3),
-.BR incataloggds (3),
-.BR MBK_CATA_LIB (1),
-.BR MBK_CATAL_NAME (1),
-.BR MBK_WORK_LIB (1).
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/cmx2_y.5 b/alliance/share/man/man5/cmx2_y.5
deleted file mode 100644
index b2550d28..00000000
--- a/alliance/share/man/man5/cmx2_y.5
+++ /dev/null
@@ -1,42 +0,0 @@
-.\"   $Id: cmx2_y.5,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.pl -.4
-.TH CMX2_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B cmx2_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("cmx2_y","name","i0","i1","c","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity cmx2_y is
-     port(
-        i0 : in bit;
-        i1 : in bit;
-        c : in bit;
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    t <= ((i0 and c) or (i1 and not c));
-   
-.br
-.I - Physical features
-   number of grids : 9
-   number of feed-through : 5
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 46 (fF)
-.br
-   i1 : 46 (fF)
-.br
-   c : 88 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/cry_dp.5 b/alliance/share/man/man5/cry_dp.5
deleted file mode 100644
index be7c5614..00000000
--- a/alliance/share/man/man5/cry_dp.5
+++ /dev/null
@@ -1,76 +0,0 @@
-.\"   $Id: cry_dp.5,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.TH CRY_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBcry_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "cry_dp", "insname", "pi", "ci", "si", "f", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  cry_dp  IS
-  PORT(
-         pi : in        BIT;
-         ci : in        BIT;
-         si : in        BIT;
-          f :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  cry_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  cry_dp  IS
-
-BEGIN
-  -- Logical equations.
-  f     <= not ((si and ci) or (pi and (si or ci)));
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 36 lambdas, or 6 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-si	:	cin	=	52	(fF)
-.br
-		tplh	=	940	(ps) +	4837	(ohms) x Cload (pF)
-.br
-		tphl	=	452	(ps) +	2702	(ohms) x Cload (pF)
-.br
-
-ci	:	cin	=	100	(fF)
-.br
-		tplh	=	1310	(ps) +	4837	(ohms) x Cload (pF)
-.br
-		tphl	=	746	(ps) +	2702	(ohms) x Cload (pF)
-.br
-
-pi	:	cin	=	97	(fF)
-.br
-		tplh	=	1341	(ps) +	4837	(ohms) x Cload (pF)
-.br
-		tphl	=	779	(ps) +	2702	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/cry_y.5 b/alliance/share/man/man5/cry_y.5
deleted file mode 100644
index 60a988fe..00000000
--- a/alliance/share/man/man5/cry_y.5
+++ /dev/null
@@ -1,42 +0,0 @@
-.\"   $Id: cry_y.5,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.pl -.4
-.TH CRY_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B cry_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("cry_y","name","pi","ci","si","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity cry_y is
-     port(
-        pi : in bit;
-        ci : in bit;
-        si : in bit;
-        f : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    f <= not ((si and ci) or (pi and (si or ci)));
-   
-.br
-.I - Physical features
-   number of grids : 6
-   number of feed-through : 2
-.br
-   
-.I - Timing caracteristics
-.br
-   pi : 102 (fF)
-.br
-   ci : 99 (fF)
-.br
-   si : 53 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/d1_y.5 b/alliance/share/man/man5/d1_y.5
deleted file mode 100644
index 39c3653d..00000000
--- a/alliance/share/man/man5/d1_y.5
+++ /dev/null
@@ -1,36 +0,0 @@
-.\"   $Id: d1_y.5,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.pl -.4
-.TH D1_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B d1_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("d1_y","name","i","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity d1_y is
-     port(
-        i : in bit;
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    t <= i;
-   
-.br
-.I - Physical features
-   number of grids : 6
-   number of feed-through : 4
-.br
-   
-.I - Timing caracteristics
-.br
-   i : 29 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/dplib.5 b/alliance/share/man/man5/dplib.5
deleted file mode 100644
index 0b3fbf92..00000000
--- a/alliance/share/man/man5/dplib.5
+++ /dev/null
@@ -1,137 +0,0 @@
-.\"   $Id: dplib.5,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.TH DPLIB 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBdplib\fP \- Cell library for data-path custom operators.
-.SH DESCRIPTION
-.ta  4n +4n +2n
-	With the cells of the \fBdplib\fP library, a designer can do the two
-following things :
-.br
-		\fB-\fP	Build heterogeneous operators using \fBGenLib(1)\fP.
-.br
-		\fB-\fP	Synthetize blocs of glue logic using \fBscmap(1)\fP.
-.br
-
-	The functionality set of the cells is nearly the same as the \fBsclib\fP
-library. All cell terminals are of the \fIDATA\fP type. As all cells of
-the \fBAlliance\fP CAD system, the layout use the \fIsymbolic layout\fP
-approach.
-.br
-	In order to use this library you must include his access path in the
-\fBMBK_CATA_LIB\fP environment variable. Notice that this access path
-depend on where you have install the \fBAlliance\fP distribution package.
-.br
-
-.ta  4n +2n +9n +2n
-	For each cell, six files are provided :
-.br
-	\fB-\fP	\fIcell\fP.vbe	:	VHDL behavioral description.
-.br
-	\fB-\fP	\fIcell\fP.ap	:	Symbolic layout.
-.br
-	\fB-\fP	\fIcell\fP.al	:	Transistor netlist, for timing analysis.
-.br
-	\fB-\fP	\fIcell\fP.ai	:	Icon.
-.br
-	\fB-\fP	\fIcell\fP.5	:	Manual file.
-.br
-	\fB-\fP	\fIcell\fP.ps	:	Postscript documentation.
-.br
-
-.nf
-.ta +10n +2n +12n
-.cs R 16
-\fBDrivers :\fP
-b1_dp	:	(drive = 2)	o <= i;
-p1_dp	:	(drive = 4)	o <= i;
-n1_dp	:	(drive = 1)	o <= not( i );
-np1_dp	:	(drive = 2)	o <= not( i );
-ndrv_dp	:	(drive = 4)	o <= not( i );
-
-\fBBoolean functions :\fP
-a2_dp	:	(drive = 1)	o <=     i0 and i1;
-a2p_dp	:	(drive = 2)	o <=     i0 and i1;
-na2_dp	:	(drive = 1)	o <= not(i0 and i1);
-na2p_dp	:	(drive = 2)	o <= not(i0 and i1);
-
-a3_dp	:	(drive = 1)	o <=     i0 and i1 and i2;
-a3p_dp	:	(drive = 2)	o <=     i0 and i1 and i2;
-na3_dp	:	(drive = 1)	o <= not(i0 and i1 and i2);
-na3p_dp	:	(drive = 2)	o <= not(i0 and i1 and i2);
-
-a4_dp	:	(drive = 1)	o <=     i0 and i1 and i2 and i3;
-a4p_dp	:	(drive = 2)	o <=     i0 and i1 and i2 and i3;
-na4_dp	:	(drive = 1)	o <= not(i0 and i1 and i2 and i3);
-
-o2_dp	:	(drive = 1)	o <=     i0 or i1;
-op2_dp	:	(drive = 2)	o <=     i0 or i1;
-no2_dp	:	(drive = 1)	o <= not(i0 or i1);
-nop2_dp	:	(drive = 2)	o <= not(i0 or i1);
-.bp
-o3_dp	:	(drive = 1)	o <=     i0 or i1 or i2;
-op3_dp	:	(drive = 2)	o <=     i0 or i1 or i2;
-no3_dp	:	(drive = 1)	o <= not(i0 or i1 or i2);
-nop3_dp	:	(drive = 2)	o <= not(i0 or i1 or i2);
-
-xr2_dp	:	(drive = 1)	o <=     i0 xor i1;
-nxr2_dp	:	(drive = 1)	o <= not(i0 xor i1);
-
-noa3_dp	:	(drive = 1)	f <= not((i0  or i1) and i2);
-nao3_dp	:	(drive = 1)	f <= not((i0 and i1)  or i2);
-noa4_dp	:	(drive = 1)	f <= not((i0  or i1   or i2) and i3);
-nao4_dp	:	(drive = 1)	f <= not((i0 and i1  and i2)  or i);
-
-noue4_dp	:	(drive = 1)	f <= not((i0  or i1) and  i2 and i3);
-neou4_dp	:	(drive = 1)	f <= not((i0 and i1)  or (i2  or i3));
-
-annup_dp	:	(drive = 1)	o <= not((i0 or i1) and (i2 or i3));
-
-.cs R
-\fBMultiplexer :\fP
-mx2_dp	:	(drive = 1)	2 input mux, two controls.
-mx2_dp	:	(drive = 2)	2 input mux, two controls.
-nmx2_dp	:	(drive = 1)	2 input mux, two controls, complemented output.
-
-mx3_dp	:	(drive = 1)	3 input mux, three controls.
-
-\fBTristates :\fP
-ts_dp	:		Tristate with direct output.
-tsn_dp	:		Tristate with complemented output.
-
-\fBMemory components :\fP
-ms_dp	:		D Flip-Flop.
-msn_dp	:		D Flip-Flop, complemented output.
-msx_dp	:		D Flip-Flop, dual output.
-mssx_dp	:		D Flip-Flop, dual output, set.
-msrx_dp	:		D Flip-Flop, dual output, reset.
-
-ms2_dp	:		D Flip-Flop, scan-path.
-ms2n_dp	:		D Flip-Flop, scan-path, complemented output.
-ms2x_dp	:		D Flip-Flop, scan-path, dual output.
-ms2sx_dp	:		D Flip-Flop, scan-path, dual output, set.
-ms2rx_dp	:		D Flip-Flop, scan-path, dual output, reset.
-.bp
-\fBMiscellaneous :\fP
-one_dp	:		Pull down.
-zero_dp	:		Pull up.
-
-cry_dp	:		Carry part of the full adder.
-sum_dp	:		Sum part of the full adder.
-.SH SEE ALSO
-.ft B
-sclib(1), scmap(1),
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/dtv.5 b/alliance/share/man/man5/dtv.5
deleted file mode 100644
index 93a2a8ac..00000000
--- a/alliance/share/man/man5/dtv.5
+++ /dev/null
@@ -1,153 +0,0 @@
-.\" @(#)dtv.5 1.00  Oct 6 1995 UPMC; Marie-Minerve LOUERAT
-.TH DTV 5 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-
-.SH NAME
-.PP
-\fBdtv\fP \- The timing analyzer \fBtas\fP report : 'detailed perfmodule' format.
-
-.so man1/alc_origin.1
-.SH DESCRIPTION
-.PP
-
-The timing analyzer \fBtas\fP reports its results in
-a file, named 'perfmodule'. There are two kind of  perfmodules:
-the 'intermediate' (or 'detailed")  and the 'general'. The first one has a \fBht\fPv
-extension  and is  obtained if  the \fB-t\fP  option is used. It
-contains gate delays  between two  signals. The second one 
-has the \fBttv\fP  extension and  contains  all critical paths
-between  two  reference  points.  The perfmodule has several
-articles.
-
-
-.TP 20
-\fBTerminals\fP
-Terminals are reported on the \fBX\fP article.
-
-.RS 5
-.PP
-X \fIdirection name capacitance\fP ;
-.RE
-
-.PP
-The 'terminal' direction can be:
-
-.RS 5
-.TP 5 
-\fII\fP
-for an input terminal
-
-.TP 5
-\fIT\fP 
-for a transceiver terminal
-
-.TP 5
-\fIB\fP 
-for a bidirectional terminal
-
-.TP 5
-\fIO\fP
-for an output terminal
-
-.TP 5
-\fIZ\fP
-for a high-impedance terminal
-
-.TP 5
-\fIU\fP 
-for an unknown direction
-.RE
-
-.TP 20
-\fBLatches\fP
-Latches are reported on the \fBL S\fP article.
-
-.RS 5
-.PP
-L S \fIname ( cmd1 cmd2 ... )\fP ;
-.RE
-
-.TP 20
-\fBFlipflop\fP
-Flipflop are reported on the \fBL F\fP article.
-
-.RS 5
-.PP
-L F \fIname ( cmd1 cmd2 ... )\fP ;
-.RE
-
-.PP
-A latch or a flipflop may have several commands. All of them  belong to
-the \fBL S\fP or \fBL F\fP article .
-
-.TP 20
-\fBPrecharged signals\fP
-Precharged signals are reported on the \fBP\fP article.
-
-.RS 5
-.PP
-P \fIname\fP ;
-.RE
-
-.TP 20
-\fBTransitions\fP
-Transitions between signals are reported to the \fBT\fP
-article.
-
-.RS 5
-.PP
-T \fItype begin end ( (control (input_commutation output_commutation
-delay resistance slope)))\fP ;
-.RE
-
-.PP
-Each 'transition' has one of the following type:
-
-.RS 5
-.TP 5
-\fIE\fP 
-if  the path output is a precharged  signal  and
-the transition concerns an evaluation phase.
-
-.TP 5
-\fIP\fP 
-if the path output is a  precharged  signal  and
-the transition concerns an precharged phase.
-
-.TP 5
-\fIX\fP 
-if the output is not a precharged signal.
-.RE
-
-.PP
-Each 'commutation' has one of the following type:
-
-.RS 5
-.TP 5
-\fIU\fP 
-for a rising edge.
-
-.TP 5
-\fID\fP
-for a falling edge.
-
-.TP 5
-\fIZ\fP
-for a  commutation when  the output  is a  
-precharged signal.
-.RE
-
-.PP
-If the end of path is a register, the 'control' field 
-indicates which signal controls the transition.  And  if the end
-of path  is  a  terminal, in  each  transition,  the  output
-resistance  and  the output  slope  will be  reported.  This
-allows a hierarchical analysis. In the other case, only  the
-delay appears in the transition line.
-
-.SH SEE ALSO
-.PP
-     tas(1),ttv(5)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/fcl.5 b/alliance/share/man/man5/fcl.5
deleted file mode 100644
index 2578d7c8..00000000
--- a/alliance/share/man/man5/fcl.5
+++ /dev/null
@@ -1,124 +0,0 @@
-.\" @(#)Labo.5 1.0 96/10/21 UPMC; Author: LESTER A.
-.pl -.4
-.TH FCL 5 "Sep 29 1997" "Release 1.01" "CAO\-VLSI Reference Manual"
-
-.SH NAME
-.TP 10
-FCL
-\- Transistor net-list pattern-matching library
-
-.so man1/alc_origin.1
-
-.SH DESCRIPTION
-A static library which allows the transistor net-list disassembler YAGLE to deal
-with unusual gate structures, for example complex latches or analog circuit blocks
-such as differential amplifiers. In order to accomplish this, the user must provide
-a set of transistor net-lists, annotated with a number of predefined types,
-together with the corresponding behavioural descriptions.
-
-.SH USAGE
-YAGLE calls the FCL library if the '-fcl' option is specified. The transistor
-net-lists (in extended spice format), and the behavioural descriptions (in ALLIANCE
-vbe format) should be placed in a dedicated directory, whose access path is
-specified by an environment variable. The list of net-lists to be identified is
-specified in a special library file located in the same directory, whose name is
-specified in an additional environment variable.
-
-.SH NET-LIST FORMAT
-The format for the transistor net-list is a standard flat spice SUBCKT contained
-in a file with the '.spi' extension. However, a number of special extensions are
-recognised. These are accomodated as spice comments, lines commencing with an
-asterisk. The asterisk is followed by a space and one of the following directives,
-together with parameters (non case-sensitive) :-
-.br
-.TP 7
-.B NETTYPE <index> <typemask>
-Associates the types indicated in <typemask> to any signal in the main circuit
-corresponding to the signal in the searched for net-list identified by <index>.
-Predefined tyes are :-
-.TP 20
-     NET_LATCH
-Signal corresponds to a latch memory-point.
-.TP 20
-     NET_FLIPFLOP
-Signal corresponds to a flip-flop memory-point.
-.TP 20
-     NET_MASTER
-Signal corresponds to the master memory-point of a flip-flop.
-.TP 20
-     NET_SLAVE
-Signal corresponds to the slave memory-point of a flip-flop.
-.TP 20
-     NET_MEMSYM
-Signal corresponds to one side of a symmetric memory.
-.TP 20
-     NET_RS
-Signal corresponds to one side of an RS bistable.
-.TP 20
-     NET_BLOCKER
-No branch of a cone (see man yagle) can go through the signal.
-.TP 20
-     NET_STOP
-Cannot exploit logic beyond this point for functional analysis in YAGLE.
-.TP 7
-.B TRANSTYPE <name> <typemask>
-Associates the types indicated in <typemask> to any transistor in the main circuit
-corresponding to the transistor in the searched for net-list identified by <name>.
-Predfefined tyes are :-
-.TP 20
-     TRANS_BLEEDER
-Transistor corresponds to a bleeder.
-.TP 20
-     TRANS_FEEDBACK
-Transistor corresponds to a feedback transistor of a memory-point.
-.TP 20
-     TRANS_COMMAND
-Transistor corresponds to a command transistor of a memory-point, i.e driven by command signal.
-.TP 20
-     TRANS_NOT_FUNCTIONAL
-Transistor should be ignored when calculating gate functionality.
-.TP 20
-     TRANS_BLOCKER
-No branch of a cone (see man yagle) can contain this transistor unless it is the first transistor of the branch.
-.TP 20
-     TRANS_UNUSED
-No branch of a cone (see man yagle) can contain this transistor.
-.SH
-The <typemask> parameter is made up of a list of one or more of the predefined types, 
-separated by the vertical bar '|' character. 
-.SH BEHAVIOUR FORMAT
-The behavioural description is specified in ALLIANCE '.vbe' format (see man vbe).
-A behavioural file must be provided for each net-list, however the description can
-be either a complete bahavioural description or specify only the external interface.
-In both cases the type must be indicated in the library file.
-
-.SH LIBRARY FILE
-This file is a simple text file containing the list of net-lists to be identified.
-Each line of the file a single name followed by a space and a character ('A' or 'P')
-indicating the type of the behavioural description (complete or interface only).
-.SH ENVIRONMENT VARIABLES
-.TP 7
-.B FCL_LIB_PATH
-Indicates the access path to the directory containing the user-defined cell
-library used if the
-.B \-fcl
-option is set. The default is a subdirectory
-.B /cells
-in
-.B MBK_WORK_LIB
-.TP 7
-.B FCL_LIB_NAME
-The name of the file (located in
-.B FCL_LIB_PATH
-) containing the list of cells in the user-defined cell library used if the
-.B \-fcl
-option is set. The default is
-.B LIBRARY.
-
-.so man1/alc_bug_rprt.1
-
-.SH SEE ALSO
-.br
-yagle(1)
-
-
diff --git a/alliance/share/man/man5/fplib.5 b/alliance/share/man/man5/fplib.5
deleted file mode 100644
index 275bc2a4..00000000
--- a/alliance/share/man/man5/fplib.5
+++ /dev/null
@@ -1,82 +0,0 @@
-.\"   $Id: fplib.5,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.TH FPLIB 5 "October 1, 1997" "ASIM/LIP6" "FITPATH Cells Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBFPLIB\fP \- Cells library for \fBFITPATH\fP dedicated generators.
-.SH DESCRIPTION
-.ta  4n
-	The \fBfplib\fP leaf cells library contain all the cells needed by the
-\fBfpgen\fP \fImacro-functions\fP. Thus his access path must be include
-in the \fBMBK_CATA_LIB\fP environment variable. For example, it could be
-done by the following command :
-.br
-
-.ft CR
-.nf
-	setenv MBK_CATA_LIB /labo/cells/fitpath/fplib:/labo/cells/fitpath/dplib
-.fi
-.ft R
-
-	Notice that the library access path depend on where you have install
-the \fBAlliance\fP distribution package.
-
-
-.nf
-Boolean Operators :
-.ta 13n +11nR +1n +11nR +1n +11nR +1n +11nR
-.\"DP_BUF	:			p1_fp	,	b1_fp	,	bp1_fp
-DP_INV	:	n1_fp	,	np1_fp	,	ndrv_fp	,	ndrvp_fp
-DP_AND2	:	a2_fp	,	a2p_fp
-DP_NAND2	:	na2_fp	,	na2p_fp
-DP_AND3	:	a3_fp	,	a3p_fp
-DP_NAND3	:	na3_fp	,	na3p_fp
-DP_OR2	:	o2_fp	,	o2p_fp
-DP_NOR2	:	no2_fp	,	no2p_fp
-DP_OR3	:	o3_fp	,	o3p_fp
-DP_NOR3	:	no3_fp	,	no3p_fp
-DP_XOR	:	xr2_fp
-DP_XNOR	:	nxr2_fp
-
-Masks Operators :
-.ta 18n +12nR +1n +12nR +1n +12nR
-DP_NAND2MASK	:	bna2x_fp	,	na2x_fp	,	n1na2x_fp
-DP_NOR2MASK	:	bno2x_fp	,	no2x_fp	,	n1no2x_fp
-DP_XNOR2MASK	:	bnxr2x_fp	,	nxr2x_fp	,	n1xr2x_fp
-
-Multiplexers Operators (encoded commands) :
-.ta 18n +12nR +1n +12nR +1n +12nR
-DP_NMUX2CS	:	nmx2sb0_fp	,	nmx2sc_fp
-DP_MUX2CS	:	mx2sb0_fp	,	mx2sc_fp
-DP_MUX3CD	:	mx3db0_fp	,	mx3dc_fp
-
-Buses Operators (Tristates) :
-.ta 13n +11nR +1n +11nR
-DP_BUSE	:	bt1_fp	,	t1_fp
-DP_NBUSE	:	nbt1_fp	,	nt1_fp
-
-Miscellaneous Operators :
-.ta 13n +11nR +1n +11nR
-DP_NUL	:	no2_fp	,	o2_fp
-DP_CONST	:	zero_dp	,	one_dp
-
-D Flip-Flop Operators :
-.ta 13n +11nR +1n +11nR +1n +11nR +1n +11nR +1n +11nR
-DP_DFF	:	pdffb3_fp	,	pdffa3_fp
-DP_DFFT	:	pdffb7_fp	,	pdffi7_fp	,	pdffj7_fp	,	pdffp7_fp	,	pdffq7_fp
-.SH SEE ALSO
-.ft B
-fpgen(1), dpr(1), genlib(1), mbk(1),
-DP_DEFLOFIG(3), DP_SAVLOFIG(3), DP_LOCON(3), DP_IMPORT(3),
-DP_INV(3), DP_BUSE(3), DP_AND2(3), DP_NAND2(3), DP_AND3(3), DP_NAND3(3),
-DP_OR2(3), DP_NOR2(3), DP_OR3(3), DP_NOR3(3), DP_XOR2(3), DP_XNOR2(3),
-DP_NAND2MASK(3), DP_NOR2MASK(3), DP_XNOR2MASK(3), DP_CONST(3),
-DP_NMUX2CS(3), DP_MUX2CS(3), DP_MUX3CS(3), DP_MUX4CS(3), DP_MUX5CS(3),
-DP_BUSE(3), DP_NBUSE(3), DP_ADD2F(3), DP_ADSB2F(3),
-DP_SHIFT(3), DP_MULT(3), DP_MULTP(3), DP_NUL(3),
-DP_PDFF(3), DP_PDFFR(3), DP_PDFFT(3), DP_PDFFRT(3),
-DP_RFG1C0(3), DP_RFG1CC(3), DP_RFG2C0(3), DP_RFG2CC(3)
-,
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/fsm.5 b/alliance/share/man/man5/fsm.5
deleted file mode 100644
index 122aa8ac..00000000
--- a/alliance/share/man/man5/fsm.5
+++ /dev/null
@@ -1,242 +0,0 @@
-.\"   $Id: fsm.5,v 1.2 1999/09/28 08:47:50 syf Exp $
-.\" @(#)FSM.5 2.1 Sep 24 1995 UPMC ; Jacomme L.
-.TH FSM 5 "October 1, 1997" "ASIM/LIP6" "VHDL subset of ASIM/LIP6/CAO-VLSI lab."
-
-.SH NAME
-.PP
-\fBfsm\fP - Alliance VHDL Finite State Machine description subset.
-
-.so man1/alc_origin.1
-.SH DESCRIPTION
-.PP
-This document describes the Alliance VHDL subset for Finite State Machine description.
-
-.br
-This FSM subset is neither accepted by the logic simulator \fBasimut\fP(1),
-nor the formal prover \fBproof\fP(1).
-
-.br
-This VHDL subset is defined to enable classical MOORE and MEALEY synchronous
-finite state machine description as well as stack FSM description (see \fBsyf\fP(1) 
-for further information about this kind of FSM).
-.br
-A FSM description is made of two and only two processes.
-Connectors and signals can only be of \fBin\fP, \fBout\fP, and two user defined
-enumerated types.
-Vectors of \fBin\fP and \fBout\fP types are also allowed.
-.br
-FSM's states and stack control signals must be declared as enumerated type.
-.br
-For the scan-path, three more signals are required :
-.RS
-- scan_test: in bit
-.br
-- scan_in: in bit
-.br
-- scan_out: out bit
-.RE
-.br
-For a ROM implementation, the vdd and vss signals must be explicitely declared as :
-.RS
-.br
-- rom_vdd : in bit
-.br
-- rom_vss : in bit
-.SH
-These signals, declared in the interface, are not used or assigned in the FSM description.
-The '-P' option of \fBsyf\fP(1) allows scan-path implementation.
-.br
-.PP
-Pragmas :
-.br
-.RS
-A pragma is a comment that gives necessary informations to the synthesis and formal
-proof tools.
-.br
-
-Three pragmas are used, their generic names are :
-.br
-.RS
-- CLOCK : External clock signal name.
-.br
-- CURRENT_STATE : Current State name.
-.br
-- NEXT_STATE : Next State name.
-.SH
-Ten other pragmas are optional.
-.br
-Three pragmas are required only for scan-path implementation.
-.br
-.RS
-- SCAN_TEST : Enable test mode (scan-path).
-.br
-- SCAN_IN : scan-path input.
-.br
-- SCAN_OUT : scan-path output.
-.br
-.SH
-Five others are used only in a STACK FSM.
-.br
-.RS
-- RETURN_STATE : Return State name.
-.br
-- CONTROL : Stack Control signal name.
-.br
-- POP : POP operation on the stack.
-.br
-- PUSH : PUSH operation on the stack.
-.br
-- NOP : NOP operation on the stack.
-.SH
-The last ones for ROM implementation
-.RS
-- ROM_VDD : Name of the vdd signal of the ROM.
-.br
-- ROM_VSS :Name of the vss signal of the ROM.
-
-.SH
-.br
-Two different processes are used : The first process, called state process,
-allows to describe state transition and outputs generation.
-It is not controlled by the clock.
-The second process is controlled by the clock and descibes the state 
-register and stack registers modifications. 
-.br
-State process sensitivity list contains inputs and CURRENT_STATE, it means 
-that the state process is activated when the CURRENT_STATE or an input signal changes. 
-A case statement is used to describe, for each state, the next state and outputs.
-.br
-The second process sensitivity list contains the clock signal, so this process 
-is enabled whenever clock changes.
-Both Level sensitive latches, and edge triggered flip flops can be used for
-state registers and stack implementation.
-.br
-.SH EXAMPLES
-.PP
-.nf
-Entity FSM_EX is
-
-port(
-   ck    : in bit ;
-   reset :in bit;
-   t_mode:in bit;
-   s_in  :in bit;
-   i     :in bit;
-   s_out :out bit;
-   o     :out bit
-);
-End FSM_EX;
-
-architecture auto of FSM_EX is
-
-type STATE_TYPE is (S0,S1,S2,S3,S4,S5);
-type CONTROL is (PUSH,POP,NOP);
-
--- pragma CLOCK ck
--- pragma CURRENT_STATE CURRENT_STATE
--- pragma NEXT_STATE NEXT_STATE
--- pragma RETURN_STATE RETURN_STATE
--- pragma CONTROL CTRL
--- pragma PUSH PUSH
--- pragma POP POP
--- pragma NOP NOP
--- pragma SCAN_TEST t_mode
--- pragma SCAN_IN s_in
--- pragma SCAN_OUT s_out
-
-signal CURRENT_STATE, NEXT_STATE, RETURN_STATE : STATE_TYPE;
-signal CTRL : CONTROL;
-signal STACK_0, STACK_1 : STATE_TYPE ;
-
-
-begin 
-  
-PROCESS(CURRENT_STATE,I,reset)
-  begin
-    if(reset) then
-      NEXT_STATE <= S0 ;
-      o <= '0' ;
-  else
-      case CURRENT_STATE is
-        WHEN S0 =>
-        NEXT_STATE <= S1;
-        RETURN_STATE <= S5;
-        CTRL <= PUSH;
-
-        o <= '0';
-
-        WHEN S1 =>
-        if (I = '1') then
-          NEXT_STATE <= S2;
-          CTRL <= NOP;
-        else
-          NEXT_STATE <= S3;
-          CTRL <= NOP;
-        end if;
-
-        o <= '0';
-
-        WHEN S2 =>
-        NEXT_STATE <= S4;
-        CTRL <= NOP;
-
-        o <= '0';
-
-        WHEN S3 =>
-        NEXT_STATE <= S4;
-        CTRL <= NOP;
-
-        o <= '0';
-
-        WHEN S4 =>
-        NEXT_STATE <= STACK_0;
-        CTRL <= POP;
-
-        o <= '1';
-
-        WHEN S5 =>
-        if (I = '1') then
-          NEXT_STATE <= S1;
-          RETURN_STATE <= S0 ;
-          CTRL <= PUSH;
-        else
-          NEXT_STATE <= S5;
-          CTRL <= NOP;
-        end if ;
-
-        o <= '0';
-
-       WHEN others =>
-        assert ('1')
-        report "illegal state";
-
-    end case;
-  end if ;
-end process;
-
-process(ck) 
-  begin
-    if(ck = '0' and not ck' stable) then
-      CURRENT_STATE <= NEXT_STATE;
-      case CTRL is
-        WHEN POP =>
-          STACK_0 <= STACK_1;
-
-        WHEN PUSH =>
-          STACK_1 <= STACK_0;
-          STACK_0 <= RETURN_STATE;
-        WHEN NOP =>
-          NULL;
-      end case;
-    end if;
-end process;
-
-end auto;
-
-.SH SEE ALSO
-.PP
-\fBvbe\fP(5), \fBsyf\fP(1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/htv.5 b/alliance/share/man/man5/htv.5
deleted file mode 100644
index 1abe6b38..00000000
--- a/alliance/share/man/man5/htv.5
+++ /dev/null
@@ -1,145 +0,0 @@
-.\"   $Id: htv.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.\" @(#)htv.5 1.00  Oct 6 1995 UPMC; Marie-Minerve LOUERAT
-.TH HTV 5 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-
-.SH NAME
-.PP
-\fBhtv\fP \- The timing analyzer \fBtas\fP report : 'detailed perfmodule' format.
-
-.so man1/alc_origin.1
-.SH DESCRIPTION
-.PP
-
-The timing analyzer \fBtas\fP reports its results in
-a file, named 'perfmodule'. There are two kind of  perfmodules:
-the 'intermediate' (or 'detailed")  and the 'general'. The first one has a \fBht\fPv
-extension  and is  obtained if  the \fB-t\fP  option is used. It
-contains gate delays  between two  signals. The second one 
-has the \fBttv\fP  extension and  contains  all critical paths
-between  two  reference  points.  The perfmodule has several
-articles.
-
-
-.TP 20
-\fBTerminals\fP
-Terminals are reported on the \fBX\fP article.
-
-.RS 5
-.PP
-X \fIdirection name capacitance\fP ;
-.RE
-
-.PP
-The 'terminal' direction can be:
-
-.RS 5
-.TP 5 
-\fII\fP
-for an input terminal
-
-.TP 5
-\fIT\fP 
-for a transceiver terminal
-
-.TP 5
-\fIB\fP 
-for a bidirectional terminal
-
-.TP 5
-\fIO\fP
-for an output terminal
-
-.TP 5
-\fIZ\fP
-for a high-impedance terminal
-
-.TP 5
-\fIU\fP 
-for an unknown direction
-.RE
-
-.TP 20
-\fBLatches\fP
-Latches are reported on the \fBL\fP article.
-
-.RS 5
-.PP
-L \fIname ( cmd1 cmd2 ... )\fP ;
-.RE
-
-.PP
-A latch may have several commands. All of them  belong to
-the \fBL\fP article.
-
-.TP 20
-\fBPrecharged signals\fP
-Precharged signals are reported on the \fBP\fP article.
-
-.RS 5
-.PP
-P \fIname\fP ;
-.RE
-
-.TP 20
-\fBTransitions\fP
-Transitions between signals are reported to the \fBT\fP
-article.
-
-.RS 5
-.PP
-T \fItype begin end ( (control (input_commutation output_commutation
-delay resistance slope)))\fP ;
-.RE
-
-.PP
-Each 'transition' has one of the following type:
-
-.RS 5
-.TP 5
-\fIE\fP 
-if  the path output is a precharged  signal  and
-the transition concerns an evaluation phase.
-
-.TP 5
-\fIP\fP 
-if the path output is a  precharged  signal  and
-the transition concerns an precharged phase.
-
-.TP 5
-\fIX\fP 
-if the output is not a precharged signal.
-.RE
-
-.PP
-Each 'commutation' has one of the following type:
-
-.RS 5
-.TP 5
-\fIU\fP 
-for a rising edge.
-
-.TP 5
-\fID\fP
-for a falling edge.
-
-.TP 5
-\fIZ\fP
-for a  commutation when  the output  is a  
-precharged signal.
-.RE
-
-.PP
-If the end of path is a register, the 'control' field 
-indicates which signal controls the transition.  And  if the end
-of path  is  a  terminal, in  each  transition,  the  output
-resistance  and  the output  slope  will be  reported.  This
-allows a hierarchical analysis. In the other case, only  the
-delay appears in the transition line.
-
-.SH SEE ALSO
-.PP
-     tas(1),ttv(5)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/inf.5 b/alliance/share/man/man5/inf.5
deleted file mode 100644
index 86854468..00000000
--- a/alliance/share/man/man5/inf.5
+++ /dev/null
@@ -1,197 +0,0 @@
-.\" @(#)Labo.5 1.0 96/10/21 UPMC; Author: LESTER A.
-.pl -.4
-.TH INF 5 "Oct 21 1996" "Release 1.08" "CAO\-VLSI Reference Manual"
-
-.SH NAME
-.TP 10
-INF
-\- YAGLE and TAS information file
-
-.so man1/alc_origin.1
-
-.SH DESCRIPTION
-The information file should be used to help the functional abstractor YAGLE or the timing analyzer TAS. It contains information which reduces run time and avoids false errors.
-The information file should have the '.inf' extension and its name must be the name of the corresponding circuit. YAGLE and TAS will take it into account if the '-i' option is used.
-This file contains several sections. Each one begins with a keyword. The declaration order is not important and it is possible to use a section more than once. Seperators are blanks, tabulations or newlines and there is no difference between upper or lower case characters. A word can be surrounded by quotation marks to prevent it being interpreted as a keyword.
-
-.SH MUTUAL EXCLUSION
-If some of the circuit terminals are mutually exclusive, this should be indicated in the MUTEX section using:
-.br
-.TP 2
--
-muxUP{term1, term2, ...}  to express that one port at most in the list is "one".
-.br
-.TP 2
--
-muxDN{term1, term2, ...}  to express that one port at most in the list is "zero".
-.br
-.TP 2
--
-cmpUP{term1, term2, ...} to express that one and only one port in the list is "one".
-.br
-.TP 2
--
-cmpDN{term1, term2, ...} to express that one and only one port in the list is "zero".
-.br
-Each list ends with semi-colon character ';' and the section ends with the END keyword.
-
-.br
-          MUTEX
-.br
-          muxUP{a,...,d};
-.br
-          muxDN{m,...,p};
-.br
-          cmpUP{i,...,l};
-.br
-          cmpDN{x,...,z};
-.br
-          ...
-.br
-          END
-
-.SH SIGNAL RENAMING
-User can renames some signals in the RENAME section. For each signal, the old name and the new name should be given.
-
-.br
-          RENAME
-.br
-          existing_name : new_name  ;
-.br
-          *gno* : *latch_data* ;
-.br
-          ...
-.br
-          END
-
-.br
-"new_name" will replace "existing_name" in the behavioural description file. It is possible to use the joker '*'. When the names contain the string "gno", this string is replaced by the string "latch_data" (l2_y_gno_01 is replaced by l2_y_latch_data_01).
-
-.SH BLOCKING FUNCTIONAL ANALYSIS
-User can specify a list of signals which should be considered as stop points for the functional analysis phase of the disassembly. This means that any logic preceding the stop points will not be used in order to analyse the behaviour of any gate following the stop point.
-
-.br
-          STOP
-.br
-          sig1 ;
-.br
-          sig2 ;
-.br
-          sigs* ;
-.br
-          ...
-.br
-          END
-
-.br
-Each line ends with the semi-colon character and the section ends with the END keyword. It is possible to use the joker '*' as for signal renaming.
-
-.SH PATH ELIMINATION
-To eliminate some critical paths, a BYPASS section should be used.
-
-.br
-          BYPASS
-.br
-          sig1 ;
-.br
-          sig2 > ;
-.br
-          sig3 < ;
-.br
-          ...
-.br
-          END
-
-.br
-Each line ends with the semi-colon character and the section ends with the END keyword. If a signal appears with no argument, the timing analyzer eliminates all pathes which cross it. With the '>' argument, all paths which end on the signal will be supressed and with the '<' argument, all paths beginning on the signal are suppressed.
-
-.SH CASE ANALYSIS
-To perform timing analysis in a specific case, the user can apply a pattern on the netlist with the CONSTRAINT section. It contains internal or external signals constrained by "one" or "zero". The timing analyser propagates the pattern before delay estimation.
-
-.br
-          CONSTRAINT
-.br
-          sig1: 0;
-.br
-          sig2: 1;
-.br
-          sig3: 0;
-.br
-          ...
-.br
-          END
-
-.br
-Each line ends with the semi-colon character and the section ends with the END keyword.
-
-.SH PRECHARGED SIGNALS
-Signals whose names end in "_p" are considered to be precharged and therefore dealt with differently by the timing analyzer. If any other signals should be considered precharged these can be specified in the PRECHARGE section.
-
-.br
-          PRECHARGE
-.br
-          sig1 ;
-.br
-          sig2 ;
-.br
-          ~ sig3 ;
-.br
-          ...
-.br
-          END
-
-.br
-Each line ends with the semi-colon character and the section ends with the END keyword. If a signal name is preceded by the '~' character then this signal will not be treated as a precharge, this is to deal with the case of non-precharge signals whose names end in "_p".
-
-.SH INTERMEDIARY POINTS
-In order to reduce the number of critical paths identified by the timing analyzer, it can sometimes be useful to specify that certain internal signals be considered as though they were path terminals. The list of these intermediary points is specified in the INTER section. Correct choice of these signals can lead to factorization of the critical paths, and hence a significant reduction in the size of the output file generated.
-
-.br
-          INTER
-.br
-          sig1 ;
-.br
-          sig2 ;
-.br
-          ...
-.br
-          END
-
-.br
-Each line ends with the semi-colon character and the section ends with the END keyword.
-
-.SH PATH SELECTION
-Another technique for reducing the size of the critical path list is to limit the number of signals which are considered to be path terminals. The list of signals which are allowed to start a critical path is specified in the PATHIN section, and the list of signals allowed to end a critical path is specified in the PATHOUT section.
-
-.br
-          PATHIN
-.br
-          sig1 ;
-.br
-          sig2 ;
-.br
-          ...
-.br
-          END
-
-.br
-          PATHOUT
-.br
-          sig3 ;
-.br
-          sig4 ;
-.br
-          ...
-.br
-          END
-
-.br
-Each line ends with the semi-colon character and both sections end with the END keyword.
-
-.so man1/alc_bug_rprt.1
-
-.SH SEE ALSO
-.br
-yagle(1), tas(1)
-
-
diff --git a/alliance/share/man/man5/l1_y.5 b/alliance/share/man/man5/l1_y.5
deleted file mode 100644
index be8e7889..00000000
--- a/alliance/share/man/man5/l1_y.5
+++ /dev/null
@@ -1,49 +0,0 @@
-.\"   $Id: l1_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH L1_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B l1_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("l1_y","name","i","l","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity l1_y is
-     port(
-        i : in bit;
-        l : in bit;
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-   label0 : block (l = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i;
-.br
-   end block;
-.br
-   
-    t <= mpx_s;
-   
-.br
-.I - Physical features
-   number of grids : 5
-   number of feed-through : 2
-.br
-   
-.I - Timing caracteristics
-.br
-   i : 82 (fF)
-.br
-   l : 24 (fF)
-.br
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/l1n_y.5 b/alliance/share/man/man5/l1n_y.5
deleted file mode 100644
index 42f4566c..00000000
--- a/alliance/share/man/man5/l1n_y.5
+++ /dev/null
@@ -1,49 +0,0 @@
-.\"   $Id: l1n_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH L1N_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B l1n_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("l1n_y","name","i","l","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity l1n_y is
-     port(
-        i : in bit;
-        l : in bit;
-        f : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-   label0 : block (l = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i;
-.br
-   end block;
-.br
-   
-    f <= not mpx_s;
-   
-.br
-.I - Physical features
-   number of grids : 5
-   number of feed-through : 2
-.br
-   
-.I - Timing caracteristics
-.br
-   i : 118 (fF)
-.br
-   l : 24 (fF)
-.br
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/l1x_y.5 b/alliance/share/man/man5/l1x_y.5
deleted file mode 100644
index 8b157e5a..00000000
--- a/alliance/share/man/man5/l1x_y.5
+++ /dev/null
@@ -1,51 +0,0 @@
-.\"   $Id: l1x_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH L1X_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B l1x_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("l1x_y","name","i","l","t","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity l1x_y is
-     port(
-        i : in bit;
-        l : in bit;
-        t : out bit;
-        f : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-   label0 : block (l = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded not i;
-.br
-   end block;
-.br
-   
-    f <= mpx_s;
-    t <= not mpx_s;
-   
-.br
-.I - Physical features
-   number of grids : 9
-   number of feed-through : 5
-.br
-   
-.I - Timing caracteristics
-.br
-   i : 46 (fF)
-.br
-   l : 24 (fF)
-.br
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/l2_y.5 b/alliance/share/man/man5/l2_y.5
deleted file mode 100644
index e56b2304..00000000
--- a/alliance/share/man/man5/l2_y.5
+++ /dev/null
@@ -1,64 +0,0 @@
-.\"   $Id: l2_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH L2_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B l2_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("l2_y","name","i0","l0","i1","l1","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity l2_y is
-     port(
-        i0 : in bit;
-        l0 : in bit;
-        i1 : in bit;
-        l1 : in bit;
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-   label1 : block (l1 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i1;
-.br
-   end block;
-.br
-   
-   label0 : block (l0 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i0;
-.br
-   end block;
-.br
-   
-    t <= mpx_s;
-   
-.br
-.I - Physical features
-   number of grids : 7
-   number of feed-through : 2
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 94 (fF)
-.br
-   l0 : 24 (fF)
-.br
-   i1 : 95 (fF)
-.br
-   l1 : 24 (fF)
-.br
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/l2n_y.5 b/alliance/share/man/man5/l2n_y.5
deleted file mode 100644
index 221fd628..00000000
--- a/alliance/share/man/man5/l2n_y.5
+++ /dev/null
@@ -1,64 +0,0 @@
-.\"   $Id: l2n_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH L2N_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B l2n_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("l2n_y","name","i0","l0","i1","l1","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity l2n_y is
-     port(
-        i0 : in bit;
-        l0 : in bit;
-        i1 : in bit;
-        l1 : in bit;
-        f : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-   label1 : block (l1 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i1;
-.br
-   end block;
-.br
-   
-   label0 : block (l0 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i0;
-.br
-   end block;
-.br
-   
-    f <= not mpx_s;
-   
-.br
-.I - Physical features
-   number of grids : 7
-   number of feed-through : 2
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 176 (fF)
-.br
-   l0 : 24 (fF)
-.br
-   i1 : 178 (fF)
-.br
-   l1 : 24 (fF)
-.br
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/l3_y.5 b/alliance/share/man/man5/l3_y.5
deleted file mode 100644
index 30af90aa..00000000
--- a/alliance/share/man/man5/l3_y.5
+++ /dev/null
@@ -1,79 +0,0 @@
-.\"   $Id: l3_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH L3_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B l3_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("l3_y","name","i0","l0","i1","l1","i2","l2","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity l3_y is
-     port(
-        i0 : in bit;
-        l0 : in bit;
-        i1 : in bit;
-        l1 : in bit;
-        i2 : in bit;
-        l2 : in bit;
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-   label2 : block (l2 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i2;
-.br
-   end block;
-.br
-   
-   label1 : block (l1 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i1;
-.br
-   end block;
-.br
-   
-   label0 : block (l0 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i0;
-.br
-   end block;
-.br
-   
-    t <= mpx_s;
-   
-.br
-.I - Physical features
-   number of grids : 8
-   number of feed-through : 1
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 108 (fF)
-.br
-   l0 : 24 (fF)
-.br
-   i1 : 107 (fF)
-.br
-   l1 : 25 (fF)
-.br
-   i2 : 107 (fF)
-.br
-   l2 : 23 (fF)
-.br
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/l3r_y.5 b/alliance/share/man/man5/l3r_y.5
deleted file mode 100644
index 80d669c6..00000000
--- a/alliance/share/man/man5/l3r_y.5
+++ /dev/null
@@ -1,76 +0,0 @@
-.\"   $Id: l3r_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH L3R_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B l3r_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("l3r_y","name","i0","l0","i1","l1","l2","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity l3r_y is
-     port(
-        i0 : in bit;
-        l0 : in bit;
-        i1 : in bit;
-        l1 : in bit;
-        l2 : in bit;
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-   label2 : block (l2 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded '0';
-.br
-   end block;
-.br
-   
-   label1 : block (l1 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i1;
-.br
-   end block;
-.br
-   
-   label0 : block (l0 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i0;
-.br
-   end block;
-.br
-   
-    t <= mpx_s;
-   
-.br
-.I - Physical features
-   number of grids : 8
-   number of feed-through : 2
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 108 (fF)
-.br
-   l0 : 24 (fF)
-.br
-   i1 : 107 (fF)
-.br
-   l1 : 25 (fF)
-.br
-   l2 : 23 (fF)
-.br
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/l3s_y.5 b/alliance/share/man/man5/l3s_y.5
deleted file mode 100644
index ef38b88e..00000000
--- a/alliance/share/man/man5/l3s_y.5
+++ /dev/null
@@ -1,76 +0,0 @@
-.\"   $Id: l3s_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH L3S_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B l3s_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("l3s_y","name","i0","l0","i1","l1","l2","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity l3s_y is
-     port(
-        i0 : in bit;
-        l0 : in bit;
-        i1 : in bit;
-        l1 : in bit;
-        l2 : in bit;
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-   label2 : block (l2 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded '1';
-.br
-   end block;
-.br
-   
-   label1 : block (l1 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i1;
-.br
-   end block;
-.br
-   
-   label0 : block (l0 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i0;
-.br
-   end block;
-.br
-   
-    t <= mpx_s;
-   
-.br
-.I - Physical features
-   number of grids : 8
-   number of feed-through : 2
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 108 (fF)
-.br
-   l0 : 24 (fF)
-.br
-   i1 : 107 (fF)
-.br
-   l1 : 25 (fF)
-.br
-   l2 : 24 (fF)
-.br
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/l4_y.5 b/alliance/share/man/man5/l4_y.5
deleted file mode 100644
index 6f5e7a2d..00000000
--- a/alliance/share/man/man5/l4_y.5
+++ /dev/null
@@ -1,94 +0,0 @@
-.\"   $Id: l4_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH L4_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B l4_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("l4_y","name","i0","l0","i1","l1","i2","l2","i3","l3","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity l4_y is
-     port(
-        i0 : in bit;
-        l0 : in bit;
-        i1 : in bit;
-        l1 : in bit;
-        i2 : in bit;
-        l2 : in bit;
-        i3 : in bit;
-        l3 : in bit;
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-   label3 : block (l3 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i3;
-.br
-   end block;
-.br
-   
-   label2 : block (l2 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i2;
-.br
-   end block;
-.br
-   
-   label1 : block (l1 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i1;
-.br
-   end block;
-.br
-   
-   label0 : block (l0 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i0;
-.br
-   end block;
-.br
-   
-    t <= mpx_s;
-   
-.br
-.I - Physical features
-   number of grids : 10
-   number of feed-through : 1
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 126 (fF)
-.br
-   l0 : 24 (fF)
-.br
-   i1 : 125 (fF)
-.br
-   l1 : 25 (fF)
-.br
-   i2 : 125 (fF)
-.br
-   l2 : 24 (fF)
-.br
-   i3 : 125 (fF)
-.br
-   l3 : 24 (fF)
-.br
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/l4r_y.5 b/alliance/share/man/man5/l4r_y.5
deleted file mode 100644
index b0aca53f..00000000
--- a/alliance/share/man/man5/l4r_y.5
+++ /dev/null
@@ -1,91 +0,0 @@
-.\"   $Id: l4r_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH L4R_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B l4r_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("l4r_y","name","i0","l0","i1","l1","i2","l2","l3","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity l4r_y is
-     port(
-        i0 : in bit;
-        l0 : in bit;
-        i1 : in bit;
-        l1 : in bit;
-        i2 : in bit;
-        l2 : in bit;
-        l3 : in bit;
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-   label3 : block (l3 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded '0';
-.br
-   end block;
-.br
-   
-   label2 : block (l2 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i2;
-.br
-   end block;
-.br
-   
-   label1 : block (l1 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i1;
-.br
-   end block;
-.br
-   
-   label0 : block (l0 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i0;
-.br
-   end block;
-.br
-   
-    t <= mpx_s;
-   
-.br
-.I - Physical features
-   number of grids : 9
-   number of feed-through : 1
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 122 (fF)
-.br
-   l0 : 24 (fF)
-.br
-   i1 : 121 (fF)
-.br
-   l1 : 25 (fF)
-.br
-   i2 : 121 (fF)
-.br
-   l2 : 24 (fF)
-.br
-   l3 : 24 (fF)
-.br
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/l4s_y.5 b/alliance/share/man/man5/l4s_y.5
deleted file mode 100644
index 38df13ae..00000000
--- a/alliance/share/man/man5/l4s_y.5
+++ /dev/null
@@ -1,91 +0,0 @@
-.\"   $Id: l4s_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH L4S_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B l4s_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("l4s_y","name","i0","l0","i1","l1","i2","l2","l3","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity l4s_y is
-     port(
-        i0 : in bit;
-        l0 : in bit;
-        i1 : in bit;
-        l1 : in bit;
-        i2 : in bit;
-        l2 : in bit;
-        l3 : in bit;
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-   label3 : block (l3 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded '1';
-.br
-   end block;
-.br
-   
-   label2 : block (l2 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i2;
-.br
-   end block;
-.br
-   
-   label1 : block (l1 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i1;
-.br
-   end block;
-.br
-   
-   label0 : block (l0 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i0;
-.br
-   end block;
-.br
-   
-    t <= mpx_s;
-   
-.br
-.I - Physical features
-   number of grids : 9
-   number of feed-through : 1
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 123 (fF)
-.br
-   l0 : 24 (fF)
-.br
-   i1 : 122 (fF)
-.br
-   l1 : 25 (fF)
-.br
-   i2 : 122 (fF)
-.br
-   l2 : 24 (fF)
-.br
-   l3 : 24 (fF)
-.br
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/l5_y.5 b/alliance/share/man/man5/l5_y.5
deleted file mode 100644
index 00914cee..00000000
--- a/alliance/share/man/man5/l5_y.5
+++ /dev/null
@@ -1,109 +0,0 @@
-.\"   $Id: l5_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH L5_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B l5_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("l5_y","name","i0","l0","i1","l1","i2","l2","i3","l3","i4","l4","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity l5_y is
-     port(
-        i0 : in bit;
-        l0 : in bit;
-        i1 : in bit;
-        l1 : in bit;
-        i2 : in bit;
-        l2 : in bit;
-        i3 : in bit;
-        l3 : in bit;
-        i4 : in bit;
-        l4 : in bit;
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-   label4 : block (l4 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i4;
-.br
-   end block;
-.br
-   
-   label3 : block (l3 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i3;
-.br
-   end block;
-.br
-   
-   label2 : block (l2 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i2;
-.br
-   end block;
-.br
-   
-   label1 : block (l1 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i1;
-.br
-   end block;
-.br
-   
-   label0 : block (l0 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i0;
-.br
-   end block;
-.br
-   
-    t <= mpx_s;
-   
-.br
-.I - Physical features
-   number of grids : 12
-   number of feed-through : 1
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 140 (fF)
-.br
-   l0 : 24 (fF)
-.br
-   i1 : 139 (fF)
-.br
-   l1 : 25 (fF)
-.br
-   i2 : 139 (fF)
-.br
-   l2 : 24 (fF)
-.br
-   i3 : 140 (fF)
-.br
-   l3 : 24 (fF)
-.br
-   i4 : 140 (fF)
-.br
-   l4 : 22 (fF)
-.br
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/l5r_y.5 b/alliance/share/man/man5/l5r_y.5
deleted file mode 100644
index cc8eae91..00000000
--- a/alliance/share/man/man5/l5r_y.5
+++ /dev/null
@@ -1,106 +0,0 @@
-.\"   $Id: l5r_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH L5R_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B l5r_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("l5r_y","name","i0","l0","i1","l1","i2","l2","i3","l3","l4","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity l5r_y is
-     port(
-        i0 : in bit;
-        l0 : in bit;
-        i1 : in bit;
-        l1 : in bit;
-        i2 : in bit;
-        l2 : in bit;
-        i3 : in bit;
-        l3 : in bit;
-        l4 : in bit;
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-   label4 : block (l4 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded '0';
-.br
-   end block;
-.br
-   
-   label3 : block (l3 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i3;
-.br
-   end block;
-.br
-   
-   label2 : block (l2 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i2;
-.br
-   end block;
-.br
-   
-   label1 : block (l1 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i1;
-.br
-   end block;
-.br
-   
-   label0 : block (l0 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i0;
-.br
-   end block;
-.br
-   
-    t <= mpx_s;
-   
-.br
-.I - Physical features
-   number of grids : 11
-   number of feed-through : 1
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 140 (fF)
-.br
-   l0 : 24 (fF)
-.br
-   i1 : 139 (fF)
-.br
-   l1 : 25 (fF)
-.br
-   i2 : 139 (fF)
-.br
-   l2 : 24 (fF)
-.br
-   i3 : 140 (fF)
-.br
-   l3 : 24 (fF)
-.br
-   l4 : 22 (fF)
-.br
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/l5s_y.5 b/alliance/share/man/man5/l5s_y.5
deleted file mode 100644
index 4e86e826..00000000
--- a/alliance/share/man/man5/l5s_y.5
+++ /dev/null
@@ -1,106 +0,0 @@
-.\"   $Id: l5s_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH L5S_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B l5s_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("l5s_y","name","i0","l0","i1","l1","i2","l2","i3","l3","l4","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity l5s_y is
-     port(
-        i0 : in bit;
-        l0 : in bit;
-        i1 : in bit;
-        l1 : in bit;
-        i2 : in bit;
-        l2 : in bit;
-        i3 : in bit;
-        l3 : in bit;
-        l4 : in bit;
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-   label4 : block (l4 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded '1';
-.br
-   end block;
-.br
-   
-   label3 : block (l3 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i3;
-.br
-   end block;
-.br
-   
-   label2 : block (l2 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i2;
-.br
-   end block;
-.br
-   
-   label1 : block (l1 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i1;
-.br
-   end block;
-.br
-   
-   label0 : block (l0 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i0;
-.br
-   end block;
-.br
-   
-    t <= mpx_s;
-   
-.br
-.I - Physical features
-   number of grids : 11
-   number of feed-through : 1
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 140 (fF)
-.br
-   l0 : 24 (fF)
-.br
-   i1 : 140 (fF)
-.br
-   l1 : 25 (fF)
-.br
-   i2 : 140 (fF)
-.br
-   l2 : 24 (fF)
-.br
-   i3 : 140 (fF)
-.br
-   l3 : 24 (fF)
-.br
-   l4 : 23 (fF)
-.br
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/l6r_y.5 b/alliance/share/man/man5/l6r_y.5
deleted file mode 100644
index b15f0178..00000000
--- a/alliance/share/man/man5/l6r_y.5
+++ /dev/null
@@ -1,121 +0,0 @@
-.\"   $Id: l6r_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH L6R_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B l6r_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("l6r_y","name","i0","l0","i1","l1","i2","l2","i3","l3","i4","l4","l5","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity l6r_y is
-     port(
-        i0 : in bit;
-        l0 : in bit;
-        i1 : in bit;
-        l1 : in bit;
-        i2 : in bit;
-        l2 : in bit;
-        i3 : in bit;
-        l3 : in bit;
-        i4 : in bit;
-        l4 : in bit;
-        l5 : in bit;
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-   label5 : block (l5 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded '0';
-.br
-   end block;
-.br
-   
-   label4 : block (l4 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i4;
-.br
-   end block;
-.br
-   
-   label3 : block (l3 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i3;
-.br
-   end block;
-.br
-   
-   label2 : block (l2 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i2;
-.br
-   end block;
-.br
-   
-   label1 : block (l1 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i1;
-.br
-   end block;
-.br
-   
-   label0 : block (l0 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i0;
-.br
-   end block;
-.br
-   
-    t <= mpx_s;
-   
-.br
-.I - Physical features
-   number of grids : 13
-   number of feed-through : 1
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 158 (fF)
-.br
-   l0 : 24 (fF)
-.br
-   i1 : 157 (fF)
-.br
-   l1 : 25 (fF)
-.br
-   i2 : 157 (fF)
-.br
-   l2 : 24 (fF)
-.br
-   i3 : 157 (fF)
-.br
-   l3 : 24 (fF)
-.br
-   i4 : 157 (fF)
-.br
-   l4 : 24 (fF)
-.br
-   l5 : 22 (fF)
-.br
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/l6s_y.5 b/alliance/share/man/man5/l6s_y.5
deleted file mode 100644
index 04d3c8fc..00000000
--- a/alliance/share/man/man5/l6s_y.5
+++ /dev/null
@@ -1,121 +0,0 @@
-.\"   $Id: l6s_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH L6S_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B l6s_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("l6s_y","name","i0","l0","i1","l1","i2","l2","i3","l3","i4","l4","l5","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity l6s_y is
-     port(
-        i0 : in bit;
-        l0 : in bit;
-        i1 : in bit;
-        l1 : in bit;
-        i2 : in bit;
-        l2 : in bit;
-        i3 : in bit;
-        l3 : in bit;
-        i4 : in bit;
-        l4 : in bit;
-        l5 : in bit;
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-   label5 : block (l5 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded '1';
-.br
-   end block;
-.br
-   
-   label4 : block (l4 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i4;
-.br
-   end block;
-.br
-   
-   label3 : block (l3 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i3;
-.br
-   end block;
-.br
-   
-   label2 : block (l2 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i2;
-.br
-   end block;
-.br
-   
-   label1 : block (l1 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i1;
-.br
-   end block;
-.br
-   
-   label0 : block (l0 = '1')
-.br
-   begin
-.br
-     mpx_s <= guarded i0;
-.br
-   end block;
-.br
-   
-    t <= mpx_s;
-   
-.br
-.I - Physical features
-   number of grids : 13
-   number of feed-through : 1
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 158 (fF)
-.br
-   l0 : 24 (fF)
-.br
-   i1 : 157 (fF)
-.br
-   l1 : 25 (fF)
-.br
-   i2 : 157 (fF)
-.br
-   l2 : 24 (fF)
-.br
-   i3 : 158 (fF)
-.br
-   l3 : 24 (fF)
-.br
-   i4 : 158 (fF)
-.br
-   l4 : 25 (fF)
-.br
-   l5 : 24 (fF)
-.br
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/lax.5 b/alliance/share/man/man5/lax.5
deleted file mode 100644
index 30f1f914..00000000
--- a/alliance/share/man/man5/lax.5
+++ /dev/null
@@ -1,199 +0,0 @@
-.\"   $Id: lax.5,v 1.3 2001/11/14 11:23:24 francois Exp $
-.\"                ,,,
-.\"               (o o)
-.\"  ####=====oOO--(_)--OOO=========================================####
-.\"  ##                                                               ##
-.\"  ##   This file is part of FPT : A Formal Proof Toolkit           ##
-.\"  ##   (C) 1996, ASIM/LIP6, CAO-VLSI Team                               ##
-.\"  ##                                                               ##
-.\"  ##   File            :  magic.1 (manual file)                    ##
-.\"  ##   Author          :  Olivier SIROL                            ##
-.\"  ##   Date            :  Sep 1996                                 ##
-.\"  ##                                                               ##
-.\"  ##   E-mail support  :  alliance\-support@asim.lip6.fr                     ##
-.\"  ##                                                               ##
-.\"  ####===========================================================####
-.\" 
-.\" 
-.\"   $Id: lax.5,v 1.3 2001/11/14 11:23:24 francois Exp $
-.\" 
-.\" 
-.TH LAX 5 "October 1, 1997" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
-
-.SH NAME
-lax \-  Parameter file for logic synthesis
-
-.so man1/alc_origin.1
-
-.SH SYNOPSIS
-.TP
-\fIfilename.lax\fP
-
-.SH DESCRIPTION
-.PP
-The
-.I .lax
-file contains user modifiable parameters that
-lead to different logic synthesis.
-
-.SH EXAMPLE
-.PP
-.I Circuit Interfce
-
-.nf
-
--- Entity Declaration
-
-ENTITY digia IS
-  PORT (
-  clock : in BIT;	-- clock
-  jour : in BIT;	-- jour
-  reset : in BIT;	-- reset
-  vdd : in BIT;	-- vdd
-  vss : in BIT;	-- vss
-  i : in bit_vector(3 DOWNTO 0) ;	-- i
-  porte : out BIT;	-- porte
-  alarm : out BIT;	-- alarm
-  ep_0 : out BIT;	-- ep_0
-  ep_1 : out BIT;	-- ep_1
-  ep_2 : out BIT;	-- ep_2
-  ep_3 : out BIT;	-- ep_3
-  ep_4 : out BIT;	-- ep_4
-  ep_5 : out BIT;	-- ep_5
-  ep_a : out BIT	-- ep_a
-  );
-END digia;
-
-
--- Architecture Declaration
-
-ARCHITECTURE behaviour_data_flow OF digia IS
-  SIGNAL cs : REG_VECTOR(0 TO 2) REGISTER;	-- cs
-  SIGNAL cs_ea : BIT;		-- cs_ea
-  SIGNAL ef_ea : BIT;		-- ef_ea
-  SIGNAL cs_e5 : BIT;		-- cs_e5
-  SIGNAL ef_e5 : BIT;		-- ef_e5
-  SIGNAL cs_e4 : BIT;		-- cs_e4
-  SIGNAL ef_e4 : BIT;		-- ef_e4
-  SIGNAL cs_e3 : BIT;		-- cs_e3
-  SIGNAL ef_e3 : BIT;		-- ef_e3
-  SIGNAL cs_e2 : BIT;		-- cs_e2
-  SIGNAL ef_e2 : BIT;		-- ef_e2
-  SIGNAL cs_e1 : BIT;		-- cs_e1
-  SIGNAL ef_e1 : BIT;		-- ef_e1
-  SIGNAL cs_e0 : BIT;		-- cs_e0
-  SIGNAL ef_e0 : BIT;		-- ef_e0
-  SIGNAL ef : BIT_VECTOR(0 TO 2);	-- ef
-
-.fi
-
-.I .Lax parameter file
-
-.nf
-
-
-## This line is a comment
-
-## Set the Optimisation Mode (0..4)
-## 0 : full area optimisation
-## 2 : 50% area, 50% delay
-## 4 : full delay optimisation
-## Used by boog and loon
-#M{4}
-
-
-## Set the Optimisation Level (1..5)
-## 1 : poor optimisation - small computation time
-## 5 : best optimisation - long computation time
-#L{5}
-
-
-## External Input Delay (in ns)
-## Those signals are taken into account to optimise
-## the global delay of the circuit.
-## Used by boog and loon
-#D{
-i(3):300;
-i(0):100;
-jour:120;
-}
-
-
-## Set the list of early outputs
-## Some outputs may be critical. They can be 
-## optimized in delay before others regardless
-## of the optimisation mode.
-#E{
-porte;
-ep_3;
-}
-
-
-## Set the list of auxiliary (intermediate) signals to keep
-## This can be used to decrease the memory consuption
-## when trying to reorder Bdds. Those signals wont
-## be reordered.
-#S{
-cs_ea;
-ef_0;
-ef_1;
-ef_e4;
-}
-
-
-## The following parameters are used for whith C4
-
-## Number of serial transistor in  N-graph
-#N{4}
-
-## Number of serial transistor in  P-graph
-#P{4}
-
-
-## The following parameters are used for whith glop
-## (Delayed --#D--inputs are also used)
-
-## Fanout factor : the max fanout of the 
-## output connector is multiplied by this factor
-#T{1000}
-
-## Input Capacitance : The primary inputs of the circuit 
-## can have fanout values. (in fF)
-#F{
-jour:50; 
-}
-
-## External Output Capacitance (in fF)
-## Used by boog and loon
-#C{
-porte:50;
-}
-
-## External Input Impedance (in Ohms)
-## Used by boog and loon
-#I{
-jour:5000;
-}
-
-## Buffered Input : this is a list of primary inputs whith 
-## the number of buffer you want to add.
-#B{
-clock:1;
-}
-
-.fi
-
-.SH SEE ALSO
-.br
-.BR \fBboom\fP (1),
-.BR \fBboog\fP (1),
-.BR \fBloon\fP (1),
-.BR \fBglop\fP (1),
-.BR \fBc4map\fP (1),
-
-
-
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/ms2_dp.5 b/alliance/share/man/man5/ms2_dp.5
deleted file mode 100644
index e9c56396..00000000
--- a/alliance/share/man/man5/ms2_dp.5
+++ /dev/null
@@ -1,77 +0,0 @@
-.\"   $Id: ms2_dp.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.TH MS2_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBms2_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "ms2_dp", "insname", "di", "si", "se", "l", "t", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  ms2_dp  IS
-  PORT(
-         di : in        BIT;
-         si : in        BIT;
-         se : in        BIT;
-          l : in        BIT;
-          t :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  ms2_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  ms2_dp  IS
-
-  -- Internal registers.
-  SIGNAL dff_s : REG_BIT REGISTER;
-
-BEGIN
-  -- Register affectations.
-  label0 :BLOCK( (not l and not l'stable ) = '1' )
-  BEGIN
-    dff_s <= GUARDED ((not di and not se) or (not si and se));
-  END BLOCK label0;
-
-  -- Logical equations.
-  t     <= not dff_s;
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 90 lambdas, or 15 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-l	:	cin	=	68	(fF)
-.br
-
-se	:	cin	=	114	(fF)
-.br
-
-si	:	cin	=	70	(fF)
-.br
-
-di	:	cin	=	68	(fF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/ms2_y.5 b/alliance/share/man/man5/ms2_y.5
deleted file mode 100644
index c9a55303..00000000
--- a/alliance/share/man/man5/ms2_y.5
+++ /dev/null
@@ -1,55 +0,0 @@
-.\"   $Id: ms2_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH MS2_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B ms2_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("ms2_y","name","di","si","se","l","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity ms2_y is
-     port(
-        di : in bit;
-        si : in bit;
-        se : in bit;
-        l : in bit;
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-   label0 : block ((not l and not l'stable ) = '1')
-.br
-   begin
-.br
-     dff_s <= guarded not ((se and si) or (not se and di));
-.br
-   end block;
-.br
-   
-    t <= not dff_s;
-   
-.br
-.I - Physical features
-   number of grids : 17
-   number of feed-through : 12
-.br
-   
-.I - Timing caracteristics
-.br
-   di : 78 (fF)
-.br
-   si : 78 (fF)
-.br
-   se : 121 (fF)
-.br
-   l : 81 (fF)
-.br
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/ms2n_dp.5 b/alliance/share/man/man5/ms2n_dp.5
deleted file mode 100644
index 14fef6df..00000000
--- a/alliance/share/man/man5/ms2n_dp.5
+++ /dev/null
@@ -1,77 +0,0 @@
-.\"   $Id: ms2n_dp.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.TH MS2N_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBms2n_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "ms2n_dp", "insname", "di", "si", "se", "l", "f", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  ms2n_dp  IS
-  PORT(
-         di : in        BIT;
-         si : in        BIT;
-         se : in        BIT;
-          l : in        BIT;
-          f :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  ms2n_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  ms2n_dp  IS
-
-  -- Internal registers.
-  SIGNAL dff_s : REG_BIT REGISTER;
-
-BEGIN
-  -- Register affectations.
-  label0 :BLOCK( (not l and not l'stable ) = '1' )
-  BEGIN
-    dff_s <= GUARDED ((not di and not se) or (not si and se));
-  END BLOCK label0;
-
-  -- Logical equations.
-  f     <= dff_s;
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 90 lambdas, or 15 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-l	:	cin	=	69	(fF)
-.br
-
-se	:	cin	=	115	(fF)
-.br
-
-si	:	cin	=	70	(fF)
-.br
-
-di	:	cin	=	69	(fF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/ms2n_y.5 b/alliance/share/man/man5/ms2n_y.5
deleted file mode 100644
index d083547b..00000000
--- a/alliance/share/man/man5/ms2n_y.5
+++ /dev/null
@@ -1,55 +0,0 @@
-.\"   $Id: ms2n_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH MS2N_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B ms2n_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("ms2n_y","name","di","si","se","l","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity ms2n_y is
-     port(
-        di : in bit;
-        si : in bit;
-        se : in bit;
-        l : in bit;
-        f : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-   label0 : block ((not l and not l'stable ) = '1')
-.br
-   begin
-.br
-     dff_s <= guarded not ((se and si) or (not se and di));
-.br
-   end block;
-.br
-   
-    f <= dff_s;
-   
-.br
-.I - Physical features
-   number of grids : 17
-   number of feed-through : 12
-.br
-   
-.I - Timing caracteristics
-.br
-   di : 78 (fF)
-.br
-   si : 78 (fF)
-.br
-   se : 121 (fF)
-.br
-   l : 81 (fF)
-.br
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/ms2rx_dp.5 b/alliance/share/man/man5/ms2rx_dp.5
deleted file mode 100644
index 23451b13..00000000
--- a/alliance/share/man/man5/ms2rx_dp.5
+++ /dev/null
@@ -1,87 +0,0 @@
-.\"   $Id: ms2rx_dp.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.TH MS2RX_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBms2rx_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "ms2rx_dp", "insname", "di", "si", "se", "l", "c", "t", "f", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  ms2rx_dp  IS
-  PORT(
-         di : in        BIT;
-         si : in        BIT;
-         se : in        BIT;
-          l : in        BIT;
-          c : in        BIT;
-          t :   out     BIT;
-          f :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  ms2rx_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  ms2rx_dp  IS
-
-  -- Internal registers.
-  SIGNAL dff_s : REG_BIT REGISTER;
-
-BEGIN
-  -- Register affectations.
-  label1 :BLOCK( c = '1' )
-  BEGIN
-    dff_s <= GUARDED '1';
-  END BLOCK label1;
-  label0 :BLOCK( (not l and not l'stable ) = '1' )
-  BEGIN
-    dff_s <= GUARDED ((not di and not se) or (not si and se));
-  END BLOCK label0;
-
-  -- Logical equations.
-  f     <= dff_s;
-  t     <= not dff_s;
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 102 lambdas, or 17 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-c	:	cin	=	15	(fF)
-.br
-
-l	:	cin	=	70	(fF)
-.br
-
-se	:	cin	=	114	(fF)
-.br
-
-si	:	cin	=	70	(fF)
-.br
-
-di	:	cin	=	68	(fF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/ms2rx_y.5 b/alliance/share/man/man5/ms2rx_y.5
deleted file mode 100644
index 8d0a0484..00000000
--- a/alliance/share/man/man5/ms2rx_y.5
+++ /dev/null
@@ -1,69 +0,0 @@
-.\"   $Id: ms2rx_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH MS2RX_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B ms2rx_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("ms2rx_y","name","di","si","se","l","r","t","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity ms2rx_y is
-     port(
-        di : in bit;
-        si : in bit;
-        se : in bit;
-        l : in bit;
-        r : in bit;
-        t : out bit;
-        f : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-   label1 : block ((not l and not l'stable ) = '1')
-.br
-   begin
-.br
-     dff_s <= guarded ((se and not si) or (not se and not di));
-.br
-   end block;
-.br
-   
-   label0 : block (r = '1')
-.br
-   begin
-.br
-     dff_s <= guarded '1';
-.br
-   end block;
-.br
-   
-    f <= dff_s;
-    t <= not dff_s;
-   
-.br
-.I - Physical features
-   number of grids : 21
-   number of feed-through : 13
-.br
-   
-.I - Timing caracteristics
-.br
-   di : 78 (fF)
-.br
-   si : 78 (fF)
-.br
-   se : 120 (fF)
-.br
-   l : 84 (fF)
-.br
-   r : 46 (fF)
-.br
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/ms2sx_dp.5 b/alliance/share/man/man5/ms2sx_dp.5
deleted file mode 100644
index 2acc193d..00000000
--- a/alliance/share/man/man5/ms2sx_dp.5
+++ /dev/null
@@ -1,87 +0,0 @@
-.\"   $Id: ms2sx_dp.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.TH MS2SX_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBms2sx_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "ms2sx_dp", "insname", "di", "si", "se", "l", "s", "t", "f", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  ms2sx_dp  IS
-  PORT(
-         di : in        BIT;
-         si : in        BIT;
-         se : in        BIT;
-          l : in        BIT;
-          s : in        BIT;
-          t :   out     BIT;
-          f :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  ms2sx_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  ms2sx_dp  IS
-
-  -- Internal registers.
-  SIGNAL dff_s : REG_BIT REGISTER;
-
-BEGIN
-  -- Register affectations.
-  label1 :BLOCK( s = '1' )
-  BEGIN
-    dff_s <= GUARDED '0';
-  END BLOCK label1;
-  label0 :BLOCK( (not l and not l'stable ) = '1' )
-  BEGIN
-    dff_s <= GUARDED ((not di and not se) or (not si and se));
-  END BLOCK label0;
-
-  -- Logical equations.
-  f     <= dff_s;
-  t     <= not dff_s;
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 102 lambdas, or 17 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-s	:	cin	=	16	(fF)
-.br
-
-l	:	cin	=	70	(fF)
-.br
-
-se	:	cin	=	114	(fF)
-.br
-
-si	:	cin	=	70	(fF)
-.br
-
-di	:	cin	=	68	(fF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/ms2sx_y.5 b/alliance/share/man/man5/ms2sx_y.5
deleted file mode 100644
index a24a5c33..00000000
--- a/alliance/share/man/man5/ms2sx_y.5
+++ /dev/null
@@ -1,69 +0,0 @@
-.\"   $Id: ms2sx_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH MS2SX_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B ms2sx_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("ms2sx_y","name","di","si","se","l","s","t","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity ms2sx_y is
-     port(
-        di : in bit;
-        si : in bit;
-        se : in bit;
-        l : in bit;
-        s : in bit;
-        t : out bit;
-        f : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-   label1 : block ((not l and not l'stable ) = '1')
-.br
-   begin
-.br
-     dff_s <= guarded ((se and not si) or (not se and not di));
-.br
-   end block;
-.br
-   
-   label0 : block (s = '1')
-.br
-   begin
-.br
-     dff_s <= guarded '0';
-.br
-   end block;
-.br
-   
-    f <= dff_s;
-    t <= not dff_s;
-   
-.br
-.I - Physical features
-   number of grids : 23
-   number of feed-through : 16
-.br
-   
-.I - Timing caracteristics
-.br
-   di : 78 (fF)
-.br
-   si : 78 (fF)
-.br
-   se : 121 (fF)
-.br
-   l : 80 (fF)
-.br
-   s : 30 (fF)
-.br
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/ms2x_dp.5 b/alliance/share/man/man5/ms2x_dp.5
deleted file mode 100644
index 8b4ed8b0..00000000
--- a/alliance/share/man/man5/ms2x_dp.5
+++ /dev/null
@@ -1,79 +0,0 @@
-.\"   $Id: ms2x_dp.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.TH MS2X_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBms2x_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "ms2x_dp", "insname", "di", "si", "se", "l", "t", "f", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  ms2x_dp  IS
-  PORT(
-         di : in        BIT;
-         si : in        BIT;
-         se : in        BIT;
-          l : in        BIT;
-          t :   out     BIT;
-          f :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  ms2x_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  ms2x_dp  IS
-
-  -- Internal registers.
-  SIGNAL dff_s : REG_BIT REGISTER;
-
-BEGIN
-  -- Register affectations.
-  label0 :BLOCK( (not l and not l'stable ) = '1' )
-  BEGIN
-    dff_s <= GUARDED ((not di and not se) or (not si and se));
-  END BLOCK label0;
-
-  -- Logical equations.
-  f     <= dff_s;
-  t     <= not dff_s;
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 102 lambdas, or 17 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-l	:	cin	=	68	(fF)
-.br
-
-se	:	cin	=	114	(fF)
-.br
-
-si	:	cin	=	70	(fF)
-.br
-
-di	:	cin	=	68	(fF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/ms2x_y.5 b/alliance/share/man/man5/ms2x_y.5
deleted file mode 100644
index 4c3609db..00000000
--- a/alliance/share/man/man5/ms2x_y.5
+++ /dev/null
@@ -1,57 +0,0 @@
-.\"   $Id: ms2x_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH MS2X_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B ms2x_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("ms2x_y","name","di","si","se","l","t","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity ms2x_y is
-     port(
-        di : in bit;
-        si : in bit;
-        se : in bit;
-        l : in bit;
-        t : out bit;
-        f : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-   label0 : block ((not l and not l'stable ) = '1')
-.br
-   begin
-.br
-     dff_s <= guarded ((se and not si) or (not se and not di));
-.br
-   end block;
-.br
-   
-    f <= dff_s;
-    t <= not dff_s;
-   
-.br
-.I - Physical features
-   number of grids : 20
-   number of feed-through : 14
-.br
-   
-.I - Timing caracteristics
-.br
-   di : 78 (fF)
-.br
-   si : 78 (fF)
-.br
-   se : 121 (fF)
-.br
-   l : 81 (fF)
-.br
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/ms_dp.5 b/alliance/share/man/man5/ms_dp.5
deleted file mode 100644
index dcad23cd..00000000
--- a/alliance/share/man/man5/ms_dp.5
+++ /dev/null
@@ -1,69 +0,0 @@
-.\"   $Id: ms_dp.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.TH MS_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBms_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "ms_dp", "insname", "i", "l", "t", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  ms_dp  IS
-  PORT(
-          i : in        BIT;
-          l : in        BIT;
-          t :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  ms_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  ms_dp  IS
-
-  -- Internal registers.
-  SIGNAL dff_s : REG_BIT REGISTER;
-
-BEGIN
-  -- Register affectations.
-  label0 :BLOCK( (not l and not l'stable ) = '1' )
-  BEGIN
-    dff_s <= GUARDED not i;
-  END BLOCK label0;
-
-  -- Logical equations.
-  t     <= not dff_s;
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 66 lambdas, or 11 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-l	:	cin	=	70	(fF)
-.br
-
-i	:	cin	=	43	(fF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/ms_y.5 b/alliance/share/man/man5/ms_y.5
deleted file mode 100644
index a29d2fa1..00000000
--- a/alliance/share/man/man5/ms_y.5
+++ /dev/null
@@ -1,49 +0,0 @@
-.\"   $Id: ms_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH MS_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B ms_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("ms_y","name","i","l","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity ms_y is
-     port(
-        i : in bit;
-        l : in bit;
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-   label0 : block ((not l and not l'stable ) = '1')
-.br
-   begin
-.br
-     dff_s <= guarded not i;
-.br
-   end block;
-.br
-   
-    t <= not dff_s;
-   
-.br
-.I - Physical features
-   number of grids : 12
-   number of feed-through : 9
-.br
-   
-.I - Timing caracteristics
-.br
-   i : 47 (fF)
-.br
-   l : 81 (fF)
-.br
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/msn_dp.5 b/alliance/share/man/man5/msn_dp.5
deleted file mode 100644
index 3dfac052..00000000
--- a/alliance/share/man/man5/msn_dp.5
+++ /dev/null
@@ -1,69 +0,0 @@
-.\"   $Id: msn_dp.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.TH MSN_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBmsn_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "msn_dp", "insname", "i", "l", "f", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  msn_dp  IS
-  PORT(
-          i : in        BIT;
-          l : in        BIT;
-          f :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  msn_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  msn_dp  IS
-
-  -- Internal registers.
-  SIGNAL dff_s : REG_BIT REGISTER;
-
-BEGIN
-  -- Register affectations.
-  label0 :BLOCK( (not l and not l'stable ) = '1' )
-  BEGIN
-    dff_s <= GUARDED not i;
-  END BLOCK label0;
-
-  -- Logical equations.
-  f     <= dff_s;
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 66 lambdas, or 11 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-l	:	cin	=	70	(fF)
-.br
-
-i	:	cin	=	43	(fF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/msn_y.5 b/alliance/share/man/man5/msn_y.5
deleted file mode 100644
index 2eaf788d..00000000
--- a/alliance/share/man/man5/msn_y.5
+++ /dev/null
@@ -1,49 +0,0 @@
-.\"   $Id: msn_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH MSN_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B msn_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("msn_y","name","i","l","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity msn_y is
-     port(
-        i : in bit;
-        l : in bit;
-        f : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-   label0 : block ((not l and not l'stable ) = '1')
-.br
-   begin
-.br
-     dff_s <= guarded not i;
-.br
-   end block;
-.br
-   
-    f <= dff_s;
-   
-.br
-.I - Physical features
-   number of grids : 12
-   number of feed-through : 9
-.br
-   
-.I - Timing caracteristics
-.br
-   i : 47 (fF)
-.br
-   l : 81 (fF)
-.br
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/msrx_dp.5 b/alliance/share/man/man5/msrx_dp.5
deleted file mode 100644
index ba2b9c34..00000000
--- a/alliance/share/man/man5/msrx_dp.5
+++ /dev/null
@@ -1,79 +0,0 @@
-.\"   $Id: msrx_dp.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.TH MSRX_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBmsrx_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "msrx_dp", "insname", "i", "l", "c", "t", "f", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  msrx_dp  IS
-  PORT(
-          i : in        BIT;
-          l : in        BIT;
-          c : in        BIT;
-          t :   out     BIT;
-          f :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  msrx_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  msrx_dp  IS
-
-  -- Internal registers.
-  SIGNAL dff_s : REG_BIT REGISTER;
-
-BEGIN
-  -- Register affectations.
-  label1 :BLOCK( c = '1' )
-  BEGIN
-    dff_s <= GUARDED '1';
-  END BLOCK label1;
-  label0 :BLOCK( (not l and not l'stable ) = '1' )
-  BEGIN
-    dff_s <= GUARDED not i;
-  END BLOCK label0;
-
-  -- Logical equations.
-  f     <= dff_s;
-  t     <= not dff_s;
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 78 lambdas, or 13 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-c	:	cin	=	15	(fF)
-.br
-
-l	:	cin	=	70	(fF)
-.br
-
-i	:	cin	=	43	(fF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/msrx_y.5 b/alliance/share/man/man5/msrx_y.5
deleted file mode 100644
index 09374453..00000000
--- a/alliance/share/man/man5/msrx_y.5
+++ /dev/null
@@ -1,63 +0,0 @@
-.\"   $Id: msrx_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH MSRX_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B msrx_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("msrx_y","name","i","l","r","t","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity msrx_y is
-     port(
-        i : in bit;
-        l : in bit;
-        r : in bit;
-        t : out bit;
-        f : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-   label1 : block ((not l and not l'stable ) = '1')
-.br
-   begin
-.br
-     dff_s <= guarded not i;
-.br
-   end block;
-.br
-   
-   label0 : block (r = '1')
-.br
-   begin
-.br
-     dff_s <= guarded '1';
-.br
-   end block;
-.br
-   
-    f <= dff_s;
-    t <= not dff_s;
-   
-.br
-.I - Physical features
-   number of grids : 17
-   number of feed-through : 12
-.br
-   
-.I - Timing caracteristics
-.br
-   i : 48 (fF)
-.br
-   l : 89 (fF)
-.br
-   r : 41 (fF)
-.br
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/mssx_dp.5 b/alliance/share/man/man5/mssx_dp.5
deleted file mode 100644
index f3af3553..00000000
--- a/alliance/share/man/man5/mssx_dp.5
+++ /dev/null
@@ -1,79 +0,0 @@
-.\"   $Id: mssx_dp.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.TH MSSX_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBmssx_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "mssx_dp", "insname", "i", "l", "s", "t", "f", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  mssx_dp  IS
-  PORT(
-          i : in        BIT;
-          l : in        BIT;
-          s : in        BIT;
-          t :   out     BIT;
-          f :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  mssx_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  mssx_dp  IS
-
-  -- Internal registers.
-  SIGNAL dff_s : REG_BIT REGISTER;
-
-BEGIN
-  -- Register affectations.
-  label1 :BLOCK( s = '1' )
-  BEGIN
-    dff_s <= GUARDED '0';
-  END BLOCK label1;
-  label0 :BLOCK( (not l and not l'stable ) = '1' )
-  BEGIN
-    dff_s <= GUARDED not i;
-  END BLOCK label0;
-
-  -- Logical equations.
-  f     <= dff_s;
-  t     <= not dff_s;
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 78 lambdas, or 13 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-s	:	cin	=	16	(fF)
-.br
-
-l	:	cin	=	70	(fF)
-.br
-
-i	:	cin	=	43	(fF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/mssx_y.5 b/alliance/share/man/man5/mssx_y.5
deleted file mode 100644
index 8e70cb73..00000000
--- a/alliance/share/man/man5/mssx_y.5
+++ /dev/null
@@ -1,63 +0,0 @@
-.\"   $Id: mssx_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH MSSX_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B mssx_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("mssx_y","name","i","l","s","t","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity mssx_y is
-     port(
-        i : in bit;
-        l : in bit;
-        s : in bit;
-        t : out bit;
-        f : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-   label1 : block ((not l and not l'stable ) = '1')
-.br
-   begin
-.br
-     dff_s <= guarded not i;
-.br
-   end block;
-.br
-   
-   label0 : block (s = '1')
-.br
-   begin
-.br
-     dff_s <= guarded '0';
-.br
-   end block;
-.br
-   
-    f <= dff_s;
-    t <= not dff_s;
-   
-.br
-.I - Physical features
-   number of grids : 16
-   number of feed-through : 11
-.br
-   
-.I - Timing caracteristics
-.br
-   i : 47 (fF)
-.br
-   l : 83 (fF)
-.br
-   s : 28 (fF)
-.br
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/msx_dp.5 b/alliance/share/man/man5/msx_dp.5
deleted file mode 100644
index 27caa35a..00000000
--- a/alliance/share/man/man5/msx_dp.5
+++ /dev/null
@@ -1,71 +0,0 @@
-.\"   $Id: msx_dp.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.TH MSX_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBmsx_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "msx_dp", "insname", "i", "l", "t", "f", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  msx_dp  IS
-  PORT(
-          i : in        BIT;
-          l : in        BIT;
-          t :   out     BIT;
-          f :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  msx_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  msx_dp  IS
-
-  -- Internal registers.
-  SIGNAL dff_s : REG_BIT REGISTER;
-
-BEGIN
-  -- Register affectations.
-  label0 :BLOCK( (not l and not l'stable ) = '1' )
-  BEGIN
-    dff_s <= GUARDED not i;
-  END BLOCK label0;
-
-  -- Logical equations.
-  f     <= dff_s;
-  t     <= not dff_s;
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 78 lambdas, or 13 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-l	:	cin	=	69	(fF)
-.br
-
-i	:	cin	=	43	(fF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/msx_y.5 b/alliance/share/man/man5/msx_y.5
deleted file mode 100644
index ca14bc52..00000000
--- a/alliance/share/man/man5/msx_y.5
+++ /dev/null
@@ -1,51 +0,0 @@
-.\"   $Id: msx_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH MSX_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B msx_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("msx_y","name","i","l","t","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity msx_y is
-     port(
-        i : in bit;
-        l : in bit;
-        t : out bit;
-        f : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-   label0 : block ((not l and not l'stable ) = '1')
-.br
-   begin
-.br
-     dff_s <= guarded not i;
-.br
-   end block;
-.br
-   
-    f <= dff_s;
-    t <= not dff_s;
-   
-.br
-.I - Physical features
-   number of grids : 14
-   number of feed-through : 10
-.br
-   
-.I - Timing caracteristics
-.br
-   i : 47 (fF)
-.br
-   l : 81 (fF)
-.br
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/mx2_dp.5 b/alliance/share/man/man5/mx2_dp.5
deleted file mode 100644
index c734f6a8..00000000
--- a/alliance/share/man/man5/mx2_dp.5
+++ /dev/null
@@ -1,84 +0,0 @@
-.\"   $Id: mx2_dp.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.TH MX2_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBmx2_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "mx2_dp", "insname", "i0", "l0", "i1", "l1", "t", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  mx2_dp  IS
-  PORT(
-         i0 : in        BIT;
-         l0 : in        BIT;
-         i1 : in        BIT;
-         l1 : in        BIT;
-          t :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  mx2_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  mx2_dp  IS
-
-BEGIN
-  -- Logical equations.
-  t     <= ((l1 and i1) or (l0 and i0));
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 42 lambdas, or 7 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-l1	:	cin	=	44	(fF)
-.br
-		tphh	=	1134	(ps) +	2998	(ohms) x Cload (pF)
-.br
-		tpll	=	1431	(ps) +	2418	(ohms) x Cload (pF)
-.br
-
-i1	:	cin	=	44	(fF)
-.br
-		tphh	=	1049	(ps) +	2998	(ohms) x Cload (pF)
-.br
-		tpll	=	1530	(ps) +	2418	(ohms) x Cload (pF)
-.br
-
-l0	:	cin	=	44	(fF)
-.br
-		tphh	=	1529	(ps) +	2998	(ohms) x Cload (pF)
-.br
-		tpll	=	1510	(ps) +	2418	(ohms) x Cload (pF)
-.br
-
-i0	:	cin	=	44	(fF)
-.br
-		tphh	=	1417	(ps) +	2998	(ohms) x Cload (pF)
-.br
-		tpll	=	1603	(ps) +	2418	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/mx2_y.5 b/alliance/share/man/man5/mx2_y.5
deleted file mode 100644
index fb0044a1..00000000
--- a/alliance/share/man/man5/mx2_y.5
+++ /dev/null
@@ -1,45 +0,0 @@
-.\"   $Id: mx2_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH MX2_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B mx2_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("mx2_y","name","i0","l0","i1","l1","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity mx2_y is
-     port(
-        i0 : in bit;
-        l0 : in bit;
-        i1 : in bit;
-        l1 : in bit;
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    t <= ((i1 and l1) or (i0 and l0));
-   
-.br
-.I - Physical features
-   number of grids : 7
-   number of feed-through : 2
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 46 (fF)
-.br
-   l0 : 46 (fF)
-.br
-   i1 : 46 (fF)
-.br
-   l1 : 46 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/mx2p_dp.5 b/alliance/share/man/man5/mx2p_dp.5
deleted file mode 100644
index f106ceba..00000000
--- a/alliance/share/man/man5/mx2p_dp.5
+++ /dev/null
@@ -1,84 +0,0 @@
-.\"   $Id: mx2p_dp.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.TH MX2P_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBmx2p_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "mx2p_dp", "insname", "i0", "l0", "i1", "l1", "t", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  mx2p_dp  IS
-  PORT(
-         i0 : in        BIT;
-         l0 : in        BIT;
-         i1 : in        BIT;
-         l1 : in        BIT;
-          t :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  mx2p_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  mx2p_dp  IS
-
-BEGIN
-  -- Logical equations.
-  t     <= ((l1 and i1) or (l0 and i0));
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 48 lambdas, or 8 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-l1	:	cin	=	54	(fF)
-.br
-		tphh	=	1460	(ps) +	1499	(ohms) x Cload (pF)
-.br
-		tpll	=	1663	(ps) +	1209	(ohms) x Cload (pF)
-.br
-
-i1	:	cin	=	54	(fF)
-.br
-		tphh	=	1577	(ps) +	1499	(ohms) x Cload (pF)
-.br
-		tpll	=	1574	(ps) +	1209	(ohms) x Cload (pF)
-.br
-
-l0	:	cin	=	54	(fF)
-.br
-		tphh	=	1115	(ps) +	1499	(ohms) x Cload (pF)
-.br
-		tpll	=	1607	(ps) +	1209	(ohms) x Cload (pF)
-.br
-
-i0	:	cin	=	54	(fF)
-.br
-		tphh	=	1209	(ps) +	1499	(ohms) x Cload (pF)
-.br
-		tpll	=	1514	(ps) +	1209	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/mx2p_y.5 b/alliance/share/man/man5/mx2p_y.5
deleted file mode 100644
index c876647b..00000000
--- a/alliance/share/man/man5/mx2p_y.5
+++ /dev/null
@@ -1,45 +0,0 @@
-.\"   $Id: mx2p_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH MX2P_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B mx2p_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("mx2p_y","name","i0","l0","i1","l1","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity mx2p_y is
-     port(
-        i0 : in bit;
-        l0 : in bit;
-        i1 : in bit;
-        l1 : in bit;
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    t <= ((i1 and l1) or (i0 and l0));
-   
-.br
-.I - Physical features
-   number of grids : 8
-   number of feed-through : 3
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 57 (fF)
-.br
-   l0 : 57 (fF)
-.br
-   i1 : 57 (fF)
-.br
-   l1 : 57 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/mx3_dp.5 b/alliance/share/man/man5/mx3_dp.5
deleted file mode 100644
index f8528c94..00000000
--- a/alliance/share/man/man5/mx3_dp.5
+++ /dev/null
@@ -1,100 +0,0 @@
-.\"   $Id: mx3_dp.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.TH MX3_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBmx3_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "mx3_dp", "insname", "i0", "l0", "i1", "l1", "i2", "l2", "t", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  mx3_dp  IS
-  PORT(
-         i0 : in        BIT;
-         l0 : in        BIT;
-         i1 : in        BIT;
-         l1 : in        BIT;
-         i2 : in        BIT;
-         l2 : in        BIT;
-          t :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  mx3_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  mx3_dp  IS
-
-BEGIN
-  -- Logical equations.
-  t     <= (((l1 and i1) or (l2 and i2)) or (l0 and i0));
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 66 lambdas, or 11 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-l2	:	cin	=	46	(fF)
-.br
-		tphh	=	1197	(ps) +	1994	(ohms) x Cload (pF)
-.br
-		tpll	=	1444	(ps) +	1603	(ohms) x Cload (pF)
-.br
-
-i2	:	cin	=	47	(fF)
-.br
-		tphh	=	1267	(ps) +	1994	(ohms) x Cload (pF)
-.br
-		tpll	=	1349	(ps) +	1603	(ohms) x Cload (pF)
-.br
-
-l1	:	cin	=	46	(fF)
-.br
-		tphh	=	1122	(ps) +	1994	(ohms) x Cload (pF)
-.br
-		tpll	=	1497	(ps) +	1603	(ohms) x Cload (pF)
-.br
-
-i1	:	cin	=	45	(fF)
-.br
-		tphh	=	1193	(ps) +	1994	(ohms) x Cload (pF)
-.br
-		tpll	=	1402	(ps) +	1603	(ohms) x Cload (pF)
-.br
-
-l0	:	cin	=	45	(fF)
-.br
-		tphh	=	1031	(ps) +	1994	(ohms) x Cload (pF)
-.br
-		tpll	=	1499	(ps) +	1603	(ohms) x Cload (pF)
-.br
-
-i0	:	cin	=	46	(fF)
-.br
-		tphh	=	1102	(ps) +	1994	(ohms) x Cload (pF)
-.br
-		tpll	=	1404	(ps) +	1603	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/mx3_y.5 b/alliance/share/man/man5/mx3_y.5
deleted file mode 100644
index f1f2d64a..00000000
--- a/alliance/share/man/man5/mx3_y.5
+++ /dev/null
@@ -1,51 +0,0 @@
-.\"   $Id: mx3_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH MX3_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B mx3_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("mx3_y","name","i0","l0","i1","l1","i2","l2","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity mx3_y is
-     port(
-        i0 : in bit;
-        l0 : in bit;
-        i1 : in bit;
-        l1 : in bit;
-        i2 : in bit;
-        l2 : in bit;
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    t <= (((i1 and l1) or (i2 and l2)) or (i0 and l0));
-   
-.br
-.I - Physical features
-   number of grids : 11
-   number of feed-through : 4
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 50 (fF)
-.br
-   l0 : 50 (fF)
-.br
-   i1 : 49 (fF)
-.br
-   l1 : 50 (fF)
-.br
-   i2 : 50 (fF)
-.br
-   l2 : 50 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/mx4_y.5 b/alliance/share/man/man5/mx4_y.5
deleted file mode 100644
index 76ce7406..00000000
--- a/alliance/share/man/man5/mx4_y.5
+++ /dev/null
@@ -1,57 +0,0 @@
-.\"   $Id: mx4_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH MX4_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B mx4_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("mx4_y","name","i0","i1","i2","i3","l0","l1","l2","l3","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity mx4_y is
-     port(
-        i0 : in bit;
-        i1 : in bit;
-        i2 : in bit;
-        i3 : in bit;
-        l0 : in bit;
-        l1 : in bit;
-        l2 : in bit;
-        l3 : in bit;
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    t <= ((((i0 and l0) or (i1 and l1)) or (i2 and l2)) or (i3 and l3));
-   
-.br
-.I - Physical features
-   number of grids : 13
-   number of feed-through : 4
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 78 (fF)
-.br
-   i1 : 78 (fF)
-.br
-   i2 : 78 (fF)
-.br
-   i3 : 78 (fF)
-.br
-   l0 : 78 (fF)
-.br
-   l1 : 78 (fF)
-.br
-   l2 : 78 (fF)
-.br
-   l3 : 78 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/n1_dp.5 b/alliance/share/man/man5/n1_dp.5
deleted file mode 100644
index 27b5b306..00000000
--- a/alliance/share/man/man5/n1_dp.5
+++ /dev/null
@@ -1,60 +0,0 @@
-.\"   $Id: n1_dp.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.TH N1_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBn1_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "n1_dp", "insname", "i", "o", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  n1_dp  IS
-  PORT(
-          i : in        BIT;
-          o :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  n1_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  n1_dp  IS
-
-BEGIN
-  -- Logical equations.
-  o     <= not i;
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 12 lambdas, or 2 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-i	:	cin	=	45	(fF)
-.br
-		tplh	=	454	(ps) +	2998	(ohms) x Cload (pF)
-.br
-		tphl	=	264	(ps) +	2418	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/n1_y.5 b/alliance/share/man/man5/n1_y.5
deleted file mode 100644
index a4f06b1d..00000000
--- a/alliance/share/man/man5/n1_y.5
+++ /dev/null
@@ -1,36 +0,0 @@
-.\"   $Id: n1_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH N1_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B n1_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("n1_y","name","i","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity n1_y is
-     port(
-        i : in bit;
-        f : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    f <= not i;
-   
-.br
-.I - Physical features
-   number of grids : 2
-   number of feed-through : 0
-.br
-   
-.I - Timing caracteristics
-.br
-   i : 46 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/na2_dp.5 b/alliance/share/man/man5/na2_dp.5
deleted file mode 100644
index fce22d53..00000000
--- a/alliance/share/man/man5/na2_dp.5
+++ /dev/null
@@ -1,68 +0,0 @@
-.\"   $Id: na2_dp.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.TH NA2_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBna2_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "na2_dp", "insname", "i0", "i1", "o", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  na2_dp  IS
-  PORT(
-         i0 : in        BIT;
-         i1 : in        BIT;
-          o :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  na2_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  na2_dp  IS
-
-BEGIN
-  -- Logical equations.
-  o     <= not (i0 and i1);
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 18 lambdas, or 3 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-i1	:	cin	=	54	(fF)
-.br
-		tplh	=	672	(ps) +	2998	(ohms) x Cload (pF)
-.br
-		tphl	=	301	(ps) +	1803	(ohms) x Cload (pF)
-.br
-
-i0	:	cin	=	54	(fF)
-.br
-		tplh	=	776	(ps) +	2998	(ohms) x Cload (pF)
-.br
-		tphl	=	250	(ps) +	1803	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/na2_y.5 b/alliance/share/man/man5/na2_y.5
deleted file mode 100644
index 3b735711..00000000
--- a/alliance/share/man/man5/na2_y.5
+++ /dev/null
@@ -1,39 +0,0 @@
-.\"   $Id: na2_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH NA2_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B na2_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("na2_y","name","i0","i1","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity na2_y is
-     port(
-        i0 : in bit;
-        i1 : in bit;
-        f : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    f <= (i1 nand i0);
-   
-.br
-.I - Physical features
-   number of grids : 3
-   number of feed-through : 0
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 58 (fF)
-.br
-   i1 : 58 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/na2p_dp.5 b/alliance/share/man/man5/na2p_dp.5
deleted file mode 100644
index d34cfeb7..00000000
--- a/alliance/share/man/man5/na2p_dp.5
+++ /dev/null
@@ -1,68 +0,0 @@
-.\"   $Id: na2p_dp.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.TH NA2P_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBna2p_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "na2p_dp", "insname", "i0", "i1", "o", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  na2p_dp  IS
-  PORT(
-         i0 : in        BIT;
-         i1 : in        BIT;
-          o :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  na2p_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  na2p_dp  IS
-
-BEGIN
-  -- Logical equations.
-  o     <= not (i0 and i1);
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 18 lambdas, or 3 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-i1	:	cin	=	86	(fF)
-.br
-		tplh	=	652	(ps) +	1699	(ohms) x Cload (pF)
-.br
-		tphl	=	288	(ps) +	1030	(ohms) x Cload (pF)
-.br
-
-i0	:	cin	=	86	(fF)
-.br
-		tplh	=	753	(ps) +	1699	(ohms) x Cload (pF)
-.br
-		tphl	=	236	(ps) +	1030	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/na2p_y.5 b/alliance/share/man/man5/na2p_y.5
deleted file mode 100644
index 49b3f30b..00000000
--- a/alliance/share/man/man5/na2p_y.5
+++ /dev/null
@@ -1,39 +0,0 @@
-.\"   $Id: na2p_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH NA2P_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B na2p_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("na2p_y","name","i0","i1","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity na2p_y is
-     port(
-        i0 : in bit;
-        i1 : in bit;
-        f : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    f <= (i1 nand i0);
-   
-.br
-.I - Physical features
-   number of grids : 4
-   number of feed-through : 1
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 99 (fF)
-.br
-   i1 : 99 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/na3_dp.5 b/alliance/share/man/man5/na3_dp.5
deleted file mode 100644
index 2fa5d517..00000000
--- a/alliance/share/man/man5/na3_dp.5
+++ /dev/null
@@ -1,76 +0,0 @@
-.\"   $Id: na3_dp.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.TH NA3_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBna3_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "na3_dp", "insname", "i0", "i1", "i2", "o", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  na3_dp  IS
-  PORT(
-         i0 : in        BIT;
-         i1 : in        BIT;
-         i2 : in        BIT;
-          o :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  na3_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  na3_dp  IS
-
-BEGIN
-  -- Logical equations.
-  o     <= not ((i0 and i1) and i2);
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 24 lambdas, or 4 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-i2	:	cin	=	54	(fF)
-.br
-		tplh	=	757	(ps) +	2998	(ohms) x Cload (pF)
-.br
-		tphl	=	474	(ps) +	2395	(ohms) x Cload (pF)
-.br
-
-i1	:	cin	=	54	(fF)
-.br
-		tplh	=	857	(ps) +	2998	(ohms) x Cload (pF)
-.br
-		tphl	=	455	(ps) +	2395	(ohms) x Cload (pF)
-.br
-
-i0	:	cin	=	54	(fF)
-.br
-		tplh	=	953	(ps) +	2998	(ohms) x Cload (pF)
-.br
-		tphl	=	391	(ps) +	2395	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/na3_y.5 b/alliance/share/man/man5/na3_y.5
deleted file mode 100644
index 84884380..00000000
--- a/alliance/share/man/man5/na3_y.5
+++ /dev/null
@@ -1,42 +0,0 @@
-.\"   $Id: na3_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH NA3_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B na3_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("na3_y","name","i0","i1","i2","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity na3_y is
-     port(
-        i0 : in bit;
-        i1 : in bit;
-        i2 : in bit;
-        f : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    f <= not ((i2 and i1) and i0);
-   
-.br
-.I - Physical features
-   number of grids : 4
-   number of feed-through : 0
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 58 (fF)
-.br
-   i1 : 58 (fF)
-.br
-   i2 : 58 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/na3p_dp.5 b/alliance/share/man/man5/na3p_dp.5
deleted file mode 100644
index 8aa1ef51..00000000
--- a/alliance/share/man/man5/na3p_dp.5
+++ /dev/null
@@ -1,76 +0,0 @@
-.\"   $Id: na3p_dp.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.TH NA3P_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBna3p_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "na3p_dp", "insname", "i0", "i1", "i2", "o", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  na3p_dp  IS
-  PORT(
-         i0 : in        BIT;
-         i1 : in        BIT;
-         i2 : in        BIT;
-          o :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  na3p_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  na3p_dp  IS
-
-BEGIN
-  -- Logical equations.
-  o     <= not ((i0 and i1) and i2);
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 24 lambdas, or 4 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-i2	:	cin	=	86	(fF)
-.br
-		tplh	=	729	(ps) +	1699	(ohms) x Cload (pF)
-.br
-		tphl	=	451	(ps) +	1368	(ohms) x Cload (pF)
-.br
-
-i1	:	cin	=	86	(fF)
-.br
-		tplh	=	827	(ps) +	1699	(ohms) x Cload (pF)
-.br
-		tphl	=	432	(ps) +	1368	(ohms) x Cload (pF)
-.br
-
-i0	:	cin	=	86	(fF)
-.br
-		tplh	=	921	(ps) +	1699	(ohms) x Cload (pF)
-.br
-		tphl	=	370	(ps) +	1368	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/na3p_y.5 b/alliance/share/man/man5/na3p_y.5
deleted file mode 100644
index 1cf3c93c..00000000
--- a/alliance/share/man/man5/na3p_y.5
+++ /dev/null
@@ -1,42 +0,0 @@
-.\"   $Id: na3p_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH NA3P_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B na3p_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("na3p_y","name","i0","i1","i2","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity na3p_y is
-     port(
-        i0 : in bit;
-        i1 : in bit;
-        i2 : in bit;
-        f : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    f <= not ((i2 and i1) and i0);
-   
-.br
-.I - Physical features
-   number of grids : 5
-   number of feed-through : 1
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 99 (fF)
-.br
-   i1 : 99 (fF)
-.br
-   i2 : 99 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/na4_dp.5 b/alliance/share/man/man5/na4_dp.5
deleted file mode 100644
index 8681d3ba..00000000
--- a/alliance/share/man/man5/na4_dp.5
+++ /dev/null
@@ -1,84 +0,0 @@
-.\"   $Id: na4_dp.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.TH NA4_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBna4_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "na4_dp", "insname", "i0", "i1", "i2", "i3", "o", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  na4_dp  IS
-  PORT(
-         i0 : in        BIT;
-         i1 : in        BIT;
-         i2 : in        BIT;
-         i3 : in        BIT;
-          o :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  na4_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  na4_dp  IS
-
-BEGIN
-  -- Logical equations.
-  o     <= not (((i0 and i1) and i2) and i3);
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 30 lambdas, or 5 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-i3	:	cin	=	69	(fF)
-.br
-		tplh	=	1553	(ps) +	3288	(ohms) x Cload (pF)
-.br
-		tphl	=	392	(ps) +	1631	(ohms) x Cload (pF)
-.br
-
-i2	:	cin	=	69	(fF)
-.br
-		tplh	=	1388	(ps) +	3288	(ohms) x Cload (pF)
-.br
-		tphl	=	446	(ps) +	1631	(ohms) x Cload (pF)
-.br
-
-i1	:	cin	=	69	(fF)
-.br
-		tplh	=	1219	(ps) +	3288	(ohms) x Cload (pF)
-.br
-		tphl	=	462	(ps) +	1631	(ohms) x Cload (pF)
-.br
-
-i0	:	cin	=	69	(fF)
-.br
-		tplh	=	1046	(ps) +	3288	(ohms) x Cload (pF)
-.br
-		tphl	=	435	(ps) +	1631	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/na4_y.5 b/alliance/share/man/man5/na4_y.5
deleted file mode 100644
index 6bbb96f5..00000000
--- a/alliance/share/man/man5/na4_y.5
+++ /dev/null
@@ -1,45 +0,0 @@
-.\"   $Id: na4_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH NA4_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B na4_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("na4_y","name","i0","i1","i2","i3","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity na4_y is
-     port(
-        i0 : in bit;
-        i1 : in bit;
-        i2 : in bit;
-        i3 : in bit;
-        f : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    f <= not (((i2 and i3) and i0) and i1);
-   
-.br
-.I - Physical features
-   number of grids : 6
-   number of feed-through : 1
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 80 (fF)
-.br
-   i1 : 80 (fF)
-.br
-   i2 : 80 (fF)
-.br
-   i3 : 80 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/nao3_dp.5 b/alliance/share/man/man5/nao3_dp.5
deleted file mode 100644
index 5a9a0c2c..00000000
--- a/alliance/share/man/man5/nao3_dp.5
+++ /dev/null
@@ -1,76 +0,0 @@
-.\"   $Id: nao3_dp.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.TH NAO3_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBnao3_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "nao3_dp", "insname", "i0", "i1", "i2", "f", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  nao3_dp  IS
-  PORT(
-         i0 : in        BIT;
-         i1 : in        BIT;
-         i2 : in        BIT;
-          f :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  nao3_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  nao3_dp  IS
-
-BEGIN
-  -- Logical equations.
-  f     <= ((i0 and i1) nor i2);
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 24 lambdas, or 4 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-i2	:	cin	=	44	(fF)
-.br
-		tplh	=	668	(ps) +	4201	(ohms) x Cload (pF)
-.br
-		tphl	=	476	(ps) +	3582	(ohms) x Cload (pF)
-.br
-
-i1	:	cin	=	51	(fF)
-.br
-		tplh	=	872	(ps) +	4201	(ohms) x Cload (pF)
-.br
-		tphl	=	588	(ps) +	2702	(ohms) x Cload (pF)
-.br
-
-i0	:	cin	=	51	(fF)
-.br
-		tplh	=	774	(ps) +	4201	(ohms) x Cload (pF)
-.br
-		tphl	=	682	(ps) +	2702	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/nao3_y.5 b/alliance/share/man/man5/nao3_y.5
deleted file mode 100644
index 51564c1a..00000000
--- a/alliance/share/man/man5/nao3_y.5
+++ /dev/null
@@ -1,42 +0,0 @@
-.\"   $Id: nao3_y.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.pl -.4
-.TH NAO3_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B nao3_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("nao3_y","name","i0","i1","i2","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity nao3_y is
-     port(
-        i0 : in bit;
-        i1 : in bit;
-        i2 : in bit;
-        f : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    f <= ((i0 and i1) nor i2);
-   
-.br
-.I - Physical features
-   number of grids : 4
-   number of feed-through : 0
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 56 (fF)
-.br
-   i1 : 56 (fF)
-.br
-   i2 : 48 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/nao4_dp.5 b/alliance/share/man/man5/nao4_dp.5
deleted file mode 100644
index d996239d..00000000
--- a/alliance/share/man/man5/nao4_dp.5
+++ /dev/null
@@ -1,84 +0,0 @@
-.\"   $Id: nao4_dp.5,v 1.1 1999/05/31 17:30:27 alliance Exp $
-.TH NAO4_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBnao4_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "nao4_dp", "insname", "i", "i0", "i1", "i2", "f", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  nao4_dp  IS
-  PORT(
-          i : in        BIT;
-         i0 : in        BIT;
-         i1 : in        BIT;
-         i2 : in        BIT;
-          f :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  nao4_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  nao4_dp  IS
-
-BEGIN
-  -- Logical equations.
-  f     <= (not i and not ((i0 and i1) and i2));
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 30 lambdas, or 5 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-i2	:	cin	=	74	(fF)
-.br
-		tplh	=	1127	(ps) +	2979	(ohms) x Cload (pF)
-.br
-		tphl	=	655	(ps) +	1921	(ohms) x Cload (pF)
-.br
-
-i1	:	cin	=	74	(fF)
-.br
-		tplh	=	999	(ps) +	2979	(ohms) x Cload (pF)
-.br
-		tphl	=	735	(ps) +	1921	(ohms) x Cload (pF)
-.br
-
-i0	:	cin	=	74	(fF)
-.br
-		tplh	=	870	(ps) +	2979	(ohms) x Cload (pF)
-.br
-		tphl	=	775	(ps) +	1921	(ohms) x Cload (pF)
-.br
-
-i	:	cin	=	58	(fF)
-.br
-		tplh	=	678	(ps) +	2979	(ohms) x Cload (pF)
-.br
-		tphl	=	464	(ps) +	2418	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/nao4_y.5 b/alliance/share/man/man5/nao4_y.5
deleted file mode 100644
index f54f1a42..00000000
--- a/alliance/share/man/man5/nao4_y.5
+++ /dev/null
@@ -1,45 +0,0 @@
-.\"   $Id: nao4_y.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.pl -.4
-.TH NAO4_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B nao4_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("nao4_y","name","i","j0","j1","j2","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity nao4_y is
-     port(
-        i : in bit;
-        j0 : in bit;
-        j1 : in bit;
-        j2 : in bit;
-        f : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    f <= (((j0 and j1) and j2) nor i);
-   
-.br
-.I - Physical features
-   number of grids : 6
-   number of feed-through : 1
-.br
-   
-.I - Timing caracteristics
-.br
-   i : 67 (fF)
-.br
-   j0 : 84 (fF)
-.br
-   j1 : 84 (fF)
-.br
-   j2 : 84 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/ndrv_dp.5 b/alliance/share/man/man5/ndrv_dp.5
deleted file mode 100644
index 17381af8..00000000
--- a/alliance/share/man/man5/ndrv_dp.5
+++ /dev/null
@@ -1,60 +0,0 @@
-.\"   $Id: ndrv_dp.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.TH NDRV_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBndrv_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "ndrv_dp", "insname", "i", "o", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  ndrv_dp  IS
-  PORT(
-          i : in        BIT;
-          o :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  ndrv_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  ndrv_dp  IS
-
-BEGIN
-  -- Logical equations.
-  o     <= not i;
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 18 lambdas, or 3 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-i	:	cin	=	133	(fF)
-.br
-		tplh	=	399	(ps) +	893	(ohms) x Cload (pF)
-.br
-		tphl	=	207	(ps) +	724	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/ndrv_y.5 b/alliance/share/man/man5/ndrv_y.5
deleted file mode 100644
index 29d7e7d9..00000000
--- a/alliance/share/man/man5/ndrv_y.5
+++ /dev/null
@@ -1,36 +0,0 @@
-.\"   $Id: ndrv_y.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.pl -.4
-.TH NDRV_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B ndrv_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("ndrv_y","name","i","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity ndrv_y is
-     port(
-        i : in bit;
-        f : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    f <= not i;
-   
-.br
-.I - Physical features
-   number of grids : 4
-   number of feed-through : 2
-.br
-   
-.I - Timing caracteristics
-.br
-   i : 146 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/neou4_dp.5 b/alliance/share/man/man5/neou4_dp.5
deleted file mode 100644
index 77962747..00000000
--- a/alliance/share/man/man5/neou4_dp.5
+++ /dev/null
@@ -1,84 +0,0 @@
-.\"   $Id: neou4_dp.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.TH NEOU4_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBneou4_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "neou4_dp", "insname", "i0", "i1", "i2", "i3", "f", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  neou4_dp  IS
-  PORT(
-         i0 : in        BIT;
-         i1 : in        BIT;
-         i2 : in        BIT;
-         i3 : in        BIT;
-          f :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  neou4_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  neou4_dp  IS
-
-BEGIN
-  -- Logical equations.
-  f     <= not ((i0 and i1) or (i2 or i3));
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 30 lambdas, or 5 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-i3	:	cin	=	60	(fF)
-.br
-		tplh	=	925	(ps) +	4206	(ohms) x Cload (pF)
-.br
-		tphl	=	475	(ps) +	2418	(ohms) x Cload (pF)
-.br
-
-i2	:	cin	=	59	(fF)
-.br
-		tplh	=	1052	(ps) +	4206	(ohms) x Cload (pF)
-.br
-		tphl	=	679	(ps) +	2418	(ohms) x Cload (pF)
-.br
-
-i1	:	cin	=	70	(fF)
-.br
-		tplh	=	1209	(ps) +	4206	(ohms) x Cload (pF)
-.br
-		tphl	=	804	(ps) +	1803	(ohms) x Cload (pF)
-.br
-
-i0	:	cin	=	69	(fF)
-.br
-		tplh	=	1368	(ps) +	4206	(ohms) x Cload (pF)
-.br
-		tphl	=	700	(ps) +	1803	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/nmx2_dp.5 b/alliance/share/man/man5/nmx2_dp.5
deleted file mode 100644
index d6be37ee..00000000
--- a/alliance/share/man/man5/nmx2_dp.5
+++ /dev/null
@@ -1,84 +0,0 @@
-.\"   $Id: nmx2_dp.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.TH NMX2_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBnmx2_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "nmx2_dp", "insname", "i0", "i1", "i2", "i3", "o", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  nmx2_dp  IS
-  PORT(
-         i0 : in        BIT;
-         i1 : in        BIT;
-         i2 : in        BIT;
-         i3 : in        BIT;
-          o :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  nmx2_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  nmx2_dp  IS
-
-BEGIN
-  -- Logical equations.
-  o     <= not ((i0 and i1) or (i2 and i3));
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 30 lambdas, or 5 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-i3	:	cin	=	66	(fF)
-.br
-		tplh	=	1001	(ps) +	2979	(ohms) x Cload (pF)
-.br
-		tphl	=	803	(ps) +	2175	(ohms) x Cload (pF)
-.br
-
-i2	:	cin	=	67	(fF)
-.br
-		tplh	=	918	(ps) +	2979	(ohms) x Cload (pF)
-.br
-		tphl	=	915	(ps) +	2175	(ohms) x Cload (pF)
-.br
-
-i1	:	cin	=	66	(fF)
-.br
-		tplh	=	851	(ps) +	2979	(ohms) x Cload (pF)
-.br
-		tphl	=	519	(ps) +	2175	(ohms) x Cload (pF)
-.br
-
-i0	:	cin	=	67	(fF)
-.br
-		tplh	=	940	(ps) +	2979	(ohms) x Cload (pF)
-.br
-		tphl	=	435	(ps) +	2175	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/nmx2_y.5 b/alliance/share/man/man5/nmx2_y.5
deleted file mode 100644
index 1fe4938c..00000000
--- a/alliance/share/man/man5/nmx2_y.5
+++ /dev/null
@@ -1,45 +0,0 @@
-.\"   $Id: nmx2_y.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.pl -.4
-.TH NMX2_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B nmx2_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("nmx2_y","name","j0","j1","i0","i1","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity nmx2_y is
-     port(
-        j0 : in bit;
-        j1 : in bit;
-        i0 : in bit;
-        i1 : in bit;
-        f : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    f <= ((j0 and j1) nor (i0 and i1));
-   
-.br
-.I - Physical features
-   number of grids : 6
-   number of feed-through : 1
-.br
-   
-.I - Timing caracteristics
-.br
-   j0 : 78 (fF)
-.br
-   j1 : 78 (fF)
-.br
-   i0 : 78 (fF)
-.br
-   i1 : 78 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/no2_dp.5 b/alliance/share/man/man5/no2_dp.5
deleted file mode 100644
index 41a2ae9c..00000000
--- a/alliance/share/man/man5/no2_dp.5
+++ /dev/null
@@ -1,68 +0,0 @@
-.\"   $Id: no2_dp.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.TH NO2_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBno2_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "no2_dp", "insname", "i0", "i1", "o", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  no2_dp  IS
-  PORT(
-         i0 : in        BIT;
-         i1 : in        BIT;
-          o :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  no2_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  no2_dp  IS
-
-BEGIN
-  -- Logical equations.
-  o     <= not (i0 or i1);
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 18 lambdas, or 3 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-i1	:	cin	=	61	(fF)
-.br
-		tplh	=	572	(ps) +	2979	(ohms) x Cload (pF)
-.br
-		tphl	=	626	(ps) +	2418	(ohms) x Cload (pF)
-.br
-
-i0	:	cin	=	61	(fF)
-.br
-		tplh	=	607	(ps) +	2979	(ohms) x Cload (pF)
-.br
-		tphl	=	410	(ps) +	2418	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/no2_y.5 b/alliance/share/man/man5/no2_y.5
deleted file mode 100644
index 7be5974c..00000000
--- a/alliance/share/man/man5/no2_y.5
+++ /dev/null
@@ -1,39 +0,0 @@
-.\"   $Id: no2_y.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.pl -.4
-.TH NO2_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B no2_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("no2_y","name","i0","i1","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity no2_y is
-     port(
-        i0 : in bit;
-        i1 : in bit;
-        f : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    f <= (i0 nor i1);
-   
-.br
-.I - Physical features
-   number of grids : 4
-   number of feed-through : 1
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 67 (fF)
-.br
-   i1 : 67 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/no3_dp.5 b/alliance/share/man/man5/no3_dp.5
deleted file mode 100644
index eba7b992..00000000
--- a/alliance/share/man/man5/no3_dp.5
+++ /dev/null
@@ -1,76 +0,0 @@
-.\"   $Id: no3_dp.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.TH NO3_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBno3_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "no3_dp", "insname", "i0", "i1", "i2", "o", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  no3_dp  IS
-  PORT(
-         i0 : in        BIT;
-         i1 : in        BIT;
-         i2 : in        BIT;
-          o :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  no3_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  no3_dp  IS
-
-BEGIN
-  -- Logical equations.
-  o     <= not ((i0 or i1) or i2);
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 24 lambdas, or 4 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-i2	:	cin	=	61	(fF)
-.br
-		tplh	=	862	(ps) +	4206	(ohms) x Cload (pF)
-.br
-		tphl	=	442	(ps) +	2418	(ohms) x Cload (pF)
-.br
-
-i1	:	cin	=	61	(fF)
-.br
-		tplh	=	994	(ps) +	4206	(ohms) x Cload (pF)
-.br
-		tphl	=	654	(ps) +	2418	(ohms) x Cload (pF)
-.br
-
-i0	:	cin	=	61	(fF)
-.br
-		tplh	=	969	(ps) +	4206	(ohms) x Cload (pF)
-.br
-		tphl	=	845	(ps) +	2418	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/no3_y.5 b/alliance/share/man/man5/no3_y.5
deleted file mode 100644
index 6dec6731..00000000
--- a/alliance/share/man/man5/no3_y.5
+++ /dev/null
@@ -1,42 +0,0 @@
-.\"   $Id: no3_y.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.pl -.4
-.TH NO3_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B no3_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("no3_y","name","i0","i1","i2","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity no3_y is
-     port(
-        i0 : in bit;
-        i1 : in bit;
-        i2 : in bit;
-        f : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    f <= not ((i0 or i1) or i2);
-   
-.br
-.I - Physical features
-   number of grids : 5
-   number of feed-through : 1
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 67 (fF)
-.br
-   i1 : 67 (fF)
-.br
-   i2 : 67 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/noa3_dp.5 b/alliance/share/man/man5/noa3_dp.5
deleted file mode 100644
index e7938e9e..00000000
--- a/alliance/share/man/man5/noa3_dp.5
+++ /dev/null
@@ -1,76 +0,0 @@
-.\"   $Id: noa3_dp.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.TH NOA3_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBnoa3_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "noa3_dp", "insname", "i0", "i1", "i2", "f", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  noa3_dp  IS
-  PORT(
-         i0 : in        BIT;
-         i1 : in        BIT;
-         i2 : in        BIT;
-          f :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  noa3_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  noa3_dp  IS
-
-BEGIN
-  -- Logical equations.
-  f     <= ((i0 or i1) nand i2);
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 24 lambdas, or 4 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-i2	:	cin	=	53	(fF)
-.br
-		tplh	=	746	(ps) +	2998	(ohms) x Cload (pF)
-.br
-		tphl	=	378	(ps) +	1860	(ohms) x Cload (pF)
-.br
-
-i1	:	cin	=	67	(fF)
-.br
-		tplh	=	897	(ps) +	2979	(ohms) x Cload (pF)
-.br
-		tphl	=	544	(ps) +	1860	(ohms) x Cload (pF)
-.br
-
-i0	:	cin	=	67	(fF)
-.br
-		tplh	=	963	(ps) +	2979	(ohms) x Cload (pF)
-.br
-		tphl	=	384	(ps) +	1860	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/noa3_y.5 b/alliance/share/man/man5/noa3_y.5
deleted file mode 100644
index 138e9d11..00000000
--- a/alliance/share/man/man5/noa3_y.5
+++ /dev/null
@@ -1,42 +0,0 @@
-.\"   $Id: noa3_y.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.pl -.4
-.TH NOA3_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B noa3_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("noa3_y","name","i0","i1","i2","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity noa3_y is
-     port(
-        i0 : in bit;
-        i1 : in bit;
-        i2 : in bit;
-        f : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    f <= ((i0 or i1) nand i2);
-   
-.br
-.I - Physical features
-   number of grids : 4
-   number of feed-through : 0
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 76 (fF)
-.br
-   i1 : 76 (fF)
-.br
-   i2 : 57 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/noa4_dp.5 b/alliance/share/man/man5/noa4_dp.5
deleted file mode 100644
index 62b5db46..00000000
--- a/alliance/share/man/man5/noa4_dp.5
+++ /dev/null
@@ -1,84 +0,0 @@
-.\"   $Id: noa4_dp.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.TH NOA4_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBnoa4_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "noa4_dp", "insname", "i0", "i1", "i2", "i3", "f", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  noa4_dp  IS
-  PORT(
-         i0 : in        BIT;
-         i1 : in        BIT;
-         i2 : in        BIT;
-         i3 : in        BIT;
-          f :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  noa4_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  noa4_dp  IS
-
-BEGIN
-  -- Logical equations.
-  f     <= not (i3 and ((i0 or i1) or i2));
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 30 lambdas, or 5 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-i3	:	cin	=	53	(fF)
-.br
-		tplh	=	740	(ps) +	2998	(ohms) x Cload (pF)
-.br
-		tphl	=	364	(ps) +	1803	(ohms) x Cload (pF)
-.br
-
-i2	:	cin	=	70	(fF)
-.br
-		tplh	=	1428	(ps) +	4206	(ohms) x Cload (pF)
-.br
-		tphl	=	370	(ps) +	1803	(ohms) x Cload (pF)
-.br
-
-i1	:	cin	=	70	(fF)
-.br
-		tplh	=	1544	(ps) +	4206	(ohms) x Cload (pF)
-.br
-		tphl	=	523	(ps) +	1803	(ohms) x Cload (pF)
-.br
-
-i0	:	cin	=	70	(fF)
-.br
-		tplh	=	1516	(ps) +	4206	(ohms) x Cload (pF)
-.br
-		tphl	=	667	(ps) +	1803	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/noa4_y.5 b/alliance/share/man/man5/noa4_y.5
deleted file mode 100644
index 5561a4bf..00000000
--- a/alliance/share/man/man5/noa4_y.5
+++ /dev/null
@@ -1,45 +0,0 @@
-.\"   $Id: noa4_y.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.pl -.4
-.TH NOA4_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B noa4_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("noa4_y","name","i0","i1","i2","i3","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity noa4_y is
-     port(
-        i0 : in bit;
-        i1 : in bit;
-        i2 : in bit;
-        i3 : in bit;
-        f : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    f <= (((i0 or i1) or i2) nand i3);
-   
-.br
-.I - Physical features
-   number of grids : 5
-   number of feed-through : 0
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 79 (fF)
-.br
-   i1 : 79 (fF)
-.br
-   i2 : 79 (fF)
-.br
-   i3 : 58 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/nop2_dp.5 b/alliance/share/man/man5/nop2_dp.5
deleted file mode 100644
index d2e5ded1..00000000
--- a/alliance/share/man/man5/nop2_dp.5
+++ /dev/null
@@ -1,68 +0,0 @@
-.\"   $Id: nop2_dp.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.TH NOP2_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBnop2_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "nop2_dp", "insname", "i0", "i1", "o", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  nop2_dp  IS
-  PORT(
-         i0 : in        BIT;
-         i1 : in        BIT;
-          o :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  nop2_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  nop2_dp  IS
-
-BEGIN
-  -- Logical equations.
-  o     <= not (i0 or i1);
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 36 lambdas, or 6 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-i1	:	cin	=	60	(fF)
-.br
-		tplh	=	1409	(ps) +	1699	(ohms) x Cload (pF)
-.br
-		tphl	=	1432	(ps) +	1314	(ohms) x Cload (pF)
-.br
-
-i0	:	cin	=	60	(fF)
-.br
-		tplh	=	1441	(ps) +	1699	(ohms) x Cload (pF)
-.br
-		tphl	=	1214	(ps) +	1314	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/nop2_y.5 b/alliance/share/man/man5/nop2_y.5
deleted file mode 100644
index 5c9d5325..00000000
--- a/alliance/share/man/man5/nop2_y.5
+++ /dev/null
@@ -1,39 +0,0 @@
-.\"   $Id: nop2_y.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.pl -.4
-.TH NOP2_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B nop2_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("nop2_y","name","i0","i1","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity nop2_y is
-     port(
-        i0 : in bit;
-        i1 : in bit;
-        f : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    f <= (i0 nor i1);
-   
-.br
-.I - Physical features
-   number of grids : 6
-   number of feed-through : 3
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 67 (fF)
-.br
-   i1 : 67 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/nop3_dp.5 b/alliance/share/man/man5/nop3_dp.5
deleted file mode 100644
index 82fde844..00000000
--- a/alliance/share/man/man5/nop3_dp.5
+++ /dev/null
@@ -1,76 +0,0 @@
-.\"   $Id: nop3_dp.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.TH NOP3_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBnop3_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "nop3_dp", "insname", "i0", "i1", "i2", "o", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  nop3_dp  IS
-  PORT(
-         i0 : in        BIT;
-         i1 : in        BIT;
-         i2 : in        BIT;
-          o :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  nop3_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  nop3_dp  IS
-
-BEGIN
-  -- Logical equations.
-  o     <= not ((i0 or i1) or i2);
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 42 lambdas, or 7 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-i2	:	cin	=	60	(fF)
-.br
-		tplh	=	1789	(ps) +	1699	(ohms) x Cload (pF)
-.br
-		tphl	=	1241	(ps) +	1314	(ohms) x Cload (pF)
-.br
-
-i1	:	cin	=	60	(fF)
-.br
-		tplh	=	1924	(ps) +	1699	(ohms) x Cload (pF)
-.br
-		tphl	=	1457	(ps) +	1314	(ohms) x Cload (pF)
-.br
-
-i0	:	cin	=	60	(fF)
-.br
-		tplh	=	1900	(ps) +	1699	(ohms) x Cload (pF)
-.br
-		tphl	=	1651	(ps) +	1314	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/nop3_y.5 b/alliance/share/man/man5/nop3_y.5
deleted file mode 100644
index c33fd748..00000000
--- a/alliance/share/man/man5/nop3_y.5
+++ /dev/null
@@ -1,42 +0,0 @@
-.\"   $Id: nop3_y.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.pl -.4
-.TH NOP3_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B nop3_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("nop3_y","name","i0","i1","i2","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity nop3_y is
-     port(
-        i0 : in bit;
-        i1 : in bit;
-        i2 : in bit;
-        f : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    f <= not ((i0 or i1) or i2);
-   
-.br
-.I - Physical features
-   number of grids : 7
-   number of feed-through : 3
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 68 (fF)
-.br
-   i1 : 68 (fF)
-.br
-   i2 : 68 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/noue4_dp.5 b/alliance/share/man/man5/noue4_dp.5
deleted file mode 100644
index a075d430..00000000
--- a/alliance/share/man/man5/noue4_dp.5
+++ /dev/null
@@ -1,84 +0,0 @@
-.\"   $Id: noue4_dp.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.TH NOUE4_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBnoue4_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "noue4_dp", "insname", "i0", "i1", "i2", "i3", "f", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  noue4_dp  IS
-  PORT(
-         i0 : in        BIT;
-         i1 : in        BIT;
-         i2 : in        BIT;
-         i3 : in        BIT;
-          f :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  noue4_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  noue4_dp  IS
-
-BEGIN
-  -- Logical equations.
-  f     <= not ((i2 and i3) and (i0 or i1));
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 30 lambdas, or 5 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-i3	:	cin	=	64	(fF)
-.br
-		tplh	=	904	(ps) +	2998	(ohms) x Cload (pF)
-.br
-		tphl	=	398	(ps) +	1603	(ohms) x Cload (pF)
-.br
-
-i2	:	cin	=	63	(fF)
-.br
-		tplh	=	1039	(ps) +	2998	(ohms) x Cload (pF)
-.br
-		tphl	=	388	(ps) +	1603	(ohms) x Cload (pF)
-.br
-
-i1	:	cin	=	80	(fF)
-.br
-		tplh	=	1380	(ps) +	2979	(ohms) x Cload (pF)
-.br
-		tphl	=	369	(ps) +	1603	(ohms) x Cload (pF)
-.br
-
-i0	:	cin	=	79	(fF)
-.br
-		tplh	=	1299	(ps) +	2979	(ohms) x Cload (pF)
-.br
-		tphl	=	504	(ps) +	1603	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/noue4_y.5 b/alliance/share/man/man5/noue4_y.5
deleted file mode 100644
index a3e597b0..00000000
--- a/alliance/share/man/man5/noue4_y.5
+++ /dev/null
@@ -1,45 +0,0 @@
-.\"   $Id: noue4_y.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.pl -.4
-.TH NOUE4_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B noue4_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("noue4_y","name","i0","i1","i2","i3","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity noue4_y is
-     port(
-        i0 : in bit;
-        i1 : in bit;
-        i2 : in bit;
-        i3 : in bit;
-        f : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    f <= not (((i0 or i1) and i2) and i3);
-   
-.br
-.I - Physical features
-   number of grids : 6
-   number of feed-through : 1
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 90 (fF)
-.br
-   i1 : 90 (fF)
-.br
-   i2 : 69 (fF)
-.br
-   i3 : 69 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/np1_dp.5 b/alliance/share/man/man5/np1_dp.5
deleted file mode 100644
index 6ab05e7c..00000000
--- a/alliance/share/man/man5/np1_dp.5
+++ /dev/null
@@ -1,60 +0,0 @@
-.\"   $Id: np1_dp.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.TH NP1_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBnp1_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "np1_dp", "insname", "i", "o", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  np1_dp  IS
-  PORT(
-          i : in        BIT;
-          o :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  np1_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  np1_dp  IS
-
-BEGIN
-  -- Logical equations.
-  o     <= not i;
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 12 lambdas, or 2 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-i	:	cin	=	65	(fF)
-.br
-		tplh	=	444	(ps) +	1787	(ohms) x Cload (pF)
-.br
-		tphl	=	253	(ps) +	1448	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/np1_y.5 b/alliance/share/man/man5/np1_y.5
deleted file mode 100644
index 0d2e0c30..00000000
--- a/alliance/share/man/man5/np1_y.5
+++ /dev/null
@@ -1,36 +0,0 @@
-.\"   $Id: np1_y.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.pl -.4
-.TH NP1_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B np1_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("np1_y","name","i","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity np1_y is
-     port(
-        i : in bit;
-        f : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    f <= not i;
-   
-.br
-.I - Physical features
-   number of grids : 3
-   number of feed-through : 1
-.br
-   
-.I - Timing caracteristics
-.br
-   i : 78 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/nxr2_dp.5 b/alliance/share/man/man5/nxr2_dp.5
deleted file mode 100644
index 580ac23c..00000000
--- a/alliance/share/man/man5/nxr2_dp.5
+++ /dev/null
@@ -1,76 +0,0 @@
-.\"   $Id: nxr2_dp.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.TH NXR2_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBnxr2_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "nxr2_dp", "insname", "i0", "i1", "o", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  nxr2_dp  IS
-  PORT(
-         i0 : in        BIT;
-         i1 : in        BIT;
-          o :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  nxr2_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  nxr2_dp  IS
-
-BEGIN
-  -- Logical equations.
-  o     <= not ((i0 and not i1) or (i1 and not i0));
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 48 lambdas, or 8 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-i1	:	cin	=	124	(fF)
-.br
-		tplh	=	967	(ps) +	2998	(ohms) x Cload (pF)
-.br
-		tphl	=	342	(ps) +	1803	(ohms) x Cload (pF)
-.br
-		tphh	=	892	(ps) +	2998	(ohms) x Cload (pF)
-.br
-		tpll	=	1278	(ps) +	1803	(ohms) x Cload (pF)
-.br
-
-i0	:	cin	=	123	(fF)
-.br
-		tplh	=	903	(ps) +	2998	(ohms) x Cload (pF)
-.br
-		tphl	=	499	(ps) +	1803	(ohms) x Cload (pF)
-.br
-		tphh	=	950	(ps) +	2998	(ohms) x Cload (pF)
-.br
-		tpll	=	1177	(ps) +	1803	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/nxr2_y.5 b/alliance/share/man/man5/nxr2_y.5
deleted file mode 100644
index ead62357..00000000
--- a/alliance/share/man/man5/nxr2_y.5
+++ /dev/null
@@ -1,39 +0,0 @@
-.\"   $Id: nxr2_y.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.pl -.4
-.TH NXR2_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B nxr2_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("nxr2_y","name","i0","i1","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity nxr2_y is
-     port(
-        i0 : in bit;
-        i1 : in bit;
-        f : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    f <= not (i0 xor i1);
-   
-.br
-.I - Physical features
-   number of grids : 7
-   number of feed-through : 4
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 126 (fF)
-.br
-   i1 : 127 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/o2_dp.5 b/alliance/share/man/man5/o2_dp.5
deleted file mode 100644
index b2457286..00000000
--- a/alliance/share/man/man5/o2_dp.5
+++ /dev/null
@@ -1,68 +0,0 @@
-.\"   $Id: o2_dp.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.TH O2_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBo2_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "o2_dp", "insname", "i0", "i1", "o", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  o2_dp  IS
-  PORT(
-         i0 : in        BIT;
-         i1 : in        BIT;
-          o :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  o2_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  o2_dp  IS
-
-BEGIN
-  -- Logical equations.
-  o     <= (i0 or i1);
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 24 lambdas, or 4 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-i1	:	cin	=	48	(fF)
-.br
-		tphh	=	1151	(ps) +	2998	(ohms) x Cload (pF)
-.br
-		tpll	=	975	(ps) +	2418	(ohms) x Cload (pF)
-.br
-
-i0	:	cin	=	48	(fF)
-.br
-		tphh	=	920	(ps) +	2998	(ohms) x Cload (pF)
-.br
-		tpll	=	1014	(ps) +	2418	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/o2_y.5 b/alliance/share/man/man5/o2_y.5
deleted file mode 100644
index df5aa125..00000000
--- a/alliance/share/man/man5/o2_y.5
+++ /dev/null
@@ -1,39 +0,0 @@
-.\"   $Id: o2_y.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.pl -.4
-.TH O2_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B o2_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("o2_y","name","i0","i1","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity o2_y is
-     port(
-        i0 : in bit;
-        i1 : in bit;
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    t <= (i0 or i1);
-   
-.br
-.I - Physical features
-   number of grids : 4
-   number of feed-through : 1
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 51 (fF)
-.br
-   i1 : 51 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/o3_dp.5 b/alliance/share/man/man5/o3_dp.5
deleted file mode 100644
index 8ae40c8a..00000000
--- a/alliance/share/man/man5/o3_dp.5
+++ /dev/null
@@ -1,76 +0,0 @@
-.\"   $Id: o3_dp.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.TH O3_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBo3_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "o3_dp", "insname", "i0", "i1", "i2", "o", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  o3_dp  IS
-  PORT(
-         i0 : in        BIT;
-         i1 : in        BIT;
-         i2 : in        BIT;
-          o :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  o3_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  o3_dp  IS
-
-BEGIN
-  -- Logical equations.
-  o     <= ((i0 or i1) or i2);
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 30 lambdas, or 5 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-i2	:	cin	=	47	(fF)
-.br
-		tphh	=	1418	(ps) +	2998	(ohms) x Cload (pF)
-.br
-		tpll	=	1493	(ps) +	2418	(ohms) x Cload (pF)
-.br
-
-i1	:	cin	=	47	(fF)
-.br
-		tphh	=	1211	(ps) +	2998	(ohms) x Cload (pF)
-.br
-		tpll	=	1525	(ps) +	2418	(ohms) x Cload (pF)
-.br
-
-i0	:	cin	=	47	(fF)
-.br
-		tphh	=	986	(ps) +	2998	(ohms) x Cload (pF)
-.br
-		tpll	=	1392	(ps) +	2418	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/o3_y.5 b/alliance/share/man/man5/o3_y.5
deleted file mode 100644
index b67b666c..00000000
--- a/alliance/share/man/man5/o3_y.5
+++ /dev/null
@@ -1,42 +0,0 @@
-.\"   $Id: o3_y.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.pl -.4
-.TH O3_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B o3_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("o3_y","name","i0","i1","i2","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity o3_y is
-     port(
-        i0 : in bit;
-        i1 : in bit;
-        i2 : in bit;
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    t <= ((i0 or i1) or i2);
-   
-.br
-.I - Physical features
-   number of grids : 5
-   number of feed-through : 1
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 51 (fF)
-.br
-   i1 : 51 (fF)
-.br
-   i2 : 50 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/one_dp.5 b/alliance/share/man/man5/one_dp.5
deleted file mode 100644
index aea3ed92..00000000
--- a/alliance/share/man/man5/one_dp.5
+++ /dev/null
@@ -1,57 +0,0 @@
-.\"   $Id: one_dp.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.TH ONE_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBone_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "one_dp", "insname", "o", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  one_dp  IS
-  PORT(
-          o :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  one_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  one_dp  IS
-
-BEGIN
-  -- Logical equations.
-  o     <= '1';
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 12 lambdas, or 2 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-		rup	=	2637	(ohms)
-.br
-		rdown	=	0	(ohms)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/one_y.5 b/alliance/share/man/man5/one_y.5
deleted file mode 100644
index a3193747..00000000
--- a/alliance/share/man/man5/one_y.5
+++ /dev/null
@@ -1,33 +0,0 @@
-.\"   $Id: one_y.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.pl -.4
-.TH ONE_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B one_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("one_y","name","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity one_y is
-     port(
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    t <= '1';
-   
-.br
-.I - Physical features
-   number of grids : 2
-   number of feed-through : 1
-.br
-   
-.I - Timing caracteristics
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/op2_dp.5 b/alliance/share/man/man5/op2_dp.5
deleted file mode 100644
index b14ab80a..00000000
--- a/alliance/share/man/man5/op2_dp.5
+++ /dev/null
@@ -1,68 +0,0 @@
-.\"   $Id: op2_dp.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.TH OP2_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBop2_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "op2_dp", "insname", "i0", "i1", "o", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  op2_dp  IS
-  PORT(
-         i0 : in        BIT;
-         i1 : in        BIT;
-          o :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  op2_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  op2_dp  IS
-
-BEGIN
-  -- Logical equations.
-  o     <= (i0 or i1);
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 24 lambdas, or 4 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-i1	:	cin	=	59	(fF)
-.br
-		tphh	=	1095	(ps) +	1699	(ohms) x Cload (pF)
-.br
-		tpll	=	1003	(ps) +	1314	(ohms) x Cload (pF)
-.br
-
-i0	:	cin	=	61	(fF)
-.br
-		tphh	=	885	(ps) +	1699	(ohms) x Cload (pF)
-.br
-		tpll	=	1044	(ps) +	1314	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/op2_y.5 b/alliance/share/man/man5/op2_y.5
deleted file mode 100644
index 07c2a9ea..00000000
--- a/alliance/share/man/man5/op2_y.5
+++ /dev/null
@@ -1,39 +0,0 @@
-.\"   $Id: op2_y.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.pl -.4
-.TH OP2_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B op2_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("op2_y","name","i0","i1","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity op2_y is
-     port(
-        i0 : in bit;
-        i1 : in bit;
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    t <= (i0 or i1);
-   
-.br
-.I - Physical features
-   number of grids : 5
-   number of feed-through : 2
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 67 (fF)
-.br
-   i1 : 68 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/op3_dp.5 b/alliance/share/man/man5/op3_dp.5
deleted file mode 100644
index f0b9caf9..00000000
--- a/alliance/share/man/man5/op3_dp.5
+++ /dev/null
@@ -1,76 +0,0 @@
-.\"   $Id: op3_dp.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.TH OP3_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBop3_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "op3_dp", "insname", "i0", "i1", "i2", "o", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  op3_dp  IS
-  PORT(
-         i0 : in        BIT;
-         i1 : in        BIT;
-         i2 : in        BIT;
-          o :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  op3_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  op3_dp  IS
-
-BEGIN
-  -- Logical equations.
-  o     <= ((i0 or i1) or i2);
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 30 lambdas, or 5 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-i2	:	cin	=	59	(fF)
-.br
-		tphh	=	1334	(ps) +	1699	(ohms) x Cload (pF)
-.br
-		tpll	=	1524	(ps) +	1314	(ohms) x Cload (pF)
-.br
-
-i1	:	cin	=	60	(fF)
-.br
-		tphh	=	1146	(ps) +	1699	(ohms) x Cload (pF)
-.br
-		tpll	=	1550	(ps) +	1314	(ohms) x Cload (pF)
-.br
-
-i0	:	cin	=	60	(fF)
-.br
-		tphh	=	941	(ps) +	1699	(ohms) x Cload (pF)
-.br
-		tpll	=	1422	(ps) +	1314	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/op3_y.5 b/alliance/share/man/man5/op3_y.5
deleted file mode 100644
index 3e0a7884..00000000
--- a/alliance/share/man/man5/op3_y.5
+++ /dev/null
@@ -1,42 +0,0 @@
-.\"   $Id: op3_y.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.pl -.4
-.TH OP3_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B op3_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("op3_y","name","i0","i1","i2","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity op3_y is
-     port(
-        i0 : in bit;
-        i1 : in bit;
-        i2 : in bit;
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    t <= ((i0 or i1) or i2);
-   
-.br
-.I - Physical features
-   number of grids : 6
-   number of feed-through : 2
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 67 (fF)
-.br
-   i1 : 67 (fF)
-.br
-   i2 : 67 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/p1_dp.5 b/alliance/share/man/man5/p1_dp.5
deleted file mode 100644
index 94910a8d..00000000
--- a/alliance/share/man/man5/p1_dp.5
+++ /dev/null
@@ -1,60 +0,0 @@
-.\"   $Id: p1_dp.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.TH P1_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBp1_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "p1_dp", "insname", "i", "o", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  p1_dp  IS
-  PORT(
-          i : in        BIT;
-          o :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  p1_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  p1_dp  IS
-
-BEGIN
-  -- Logical equations.
-  o     <= i;
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 18 lambdas, or 3 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-i	:	cin	=	43	(fF)
-.br
-		tphh	=	752	(ps) +	1699	(ohms) x Cload (pF)
-.br
-		tpll	=	900	(ps) +	1314	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/p1_y.5 b/alliance/share/man/man5/p1_y.5
deleted file mode 100644
index 52d5f12a..00000000
--- a/alliance/share/man/man5/p1_y.5
+++ /dev/null
@@ -1,36 +0,0 @@
-.\"   $Id: p1_y.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.pl -.4
-.TH P1_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B p1_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("p1_y","name","i","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity p1_y is
-     port(
-        i : in bit;
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    t <= i;
-   
-.br
-.I - Physical features
-   number of grids : 3
-   number of feed-through : 1
-.br
-   
-.I - Timing caracteristics
-.br
-   i : 46 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/pat.5 b/alliance/share/man/man5/pat.5
deleted file mode 100644
index b7a2ddd4..00000000
--- a/alliance/share/man/man5/pat.5
+++ /dev/null
@@ -1,292 +0,0 @@
-.\"   $Id: pat.5,v 1.2 1999/09/24 14:12:24 simcity Exp $
-.\" @(#)pat.5 106 Sep 30 1996 UPMC ; Pirouz BAZARGAN SABET
-.TH PAT 5 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-
-.so man1/alc_origin.1
-.SH NAME
-.PP
-\fBPAT\fP \- Pattern description format
-
-.SH DESCRIPTION
-.PP
-The \fBpat\fP is a specific format used in simulation pattern\'s description.
-\fBpat\fP format has been designed to represent undifferently patterns to be
-simulated or simulation's results. It offers the possibility of:
-
-.PP
-specifying the \fIinput\fP list of the circuit: signals to be controled during
-the simulation by the user. For a circuit described in VHDL, are considered as
-\fIinput\fP:
-.RS
-.PP
-external ports of the mode \fBin\fP.
-.br
-guarded external ports of the mode \fBinout\fP (declared with the reserved word
-\fBbus\fP).
-.RE
-
-.PP
-specifying the \fIoutput\fP list of the circuit: signals to be observed during
-the simulation. For a circuit described in VHDL, are considered as \fIoutput\fP:
-.RS
-.PP
-external ports of the mode \fBout\fP (declared either with or without the
-reserved word \fBbus\fP).
-.br
-external ports of the mode \fBinout\fP (declared either with or without the
-reserved word \fBbus\fP).
-.br
-internal signals of a hierarchical description.
-.br
-internal signals of a behavioural description (declared as \fBbus\fP,
-\fBregister\fP or simple signal)
-.RE
-
-.PP
-specifying a read\-write format for inputs and outputs.
-
-.PP
-forcing the value of each input.
-
-.PP
-checking the resulted value on each output.
-
-.PP
-changing the value of an internal register (a guarded internal signal of kind
-\fBregister\fP in a behavioural description).
-
-.PP
-saving the state of the circuit.
-
-.SH THE FORMAT
-.PP
-A pattern file written in \fBpat\fP format can be divided into two parts: the
-declaration block and the description block. The instruction \fBbegin\fP marks
-the end of the declaration and the beginning of the description block. The
-instruction \fBend;\fP marks the end of the file.
-
-.PP
-\fBThe declaration block\fP is a set of input\-output declaration statements.
-The order of these declarations is important. In the description block, values
-will be associated with an input\-output in the order of their declaration.
-That is, the first value will be associated with the first declared
-input\-output and, the last value with the last one.
-
-.PP
-A declaration statement has of one of the two following forms :
-.RS
-\fImode\fP input_output_name [\fIformat\fP] [\fIspy_option\fP];
-.br
-\fImode\fP group_name (input_output_name, ...) [\fIformat\fP] [\fIspy_option\fP];
-.RE
-
-.PP
-The second form allows the user to give a name to a group of signals. This
-group of signals will be called virtual array. Using this grouping
-possibility, great care must be taken. Two guarded outputs (of kind \fBbus\fP)
-can be grouped only if their guard expression are exactly the same.
-
-.TP 10
-\fIinputs\fP
-An external port of the mode \fBin\fP must be declared with the \fImode\fP
-\fBin\fP. A guarded external port of the \fImode\fP \fBinout\fP must be
-declared with the \fImode\fP \fBinout\fP.
-
-.TP 10
-\fIoutputs\fP
-An external port (guarded or not) of the mode \fBout\fP must be declared with
-the \fImode\fP \fBout\fP. An unguarded external port of the mode \fBinout\fP
-must be declared with the \fImode\fP \fBout\fP. A guarded external port of the
-mode \fBinout\fP must be declared with the \fImode\fP \fBinout\fP. An internal
-signal (simple or guarded of kind \fBbus\fP) of a behavioural or structural
-description must be declared with the \fImode\fP \fBsignal\fP. An internal
-register (guarded signal of kind \fBregister\fP) is to be declared with
-\fImode\fP \fBregister\fP.
-
-.PP
-The \fIformat\fP specifies the format under which values associated with an
-input\-output must be read or written. Legal formats are \fBX\fP for
-hexadecimal, \fBO\fP for octal and, \fBB\fP for binary. The binary format is
-the default format.
-
-.PP
-The \fIinput_output_name\fP is used to identify the input\-output signal.
-For an external port, the signal\'s identifier added, if the signal is an array,
-to its constraint (the range of the array) constitutes the input\-output name.
-For an internal signal the \fIinput_output_name\fP is made from the
-concatenation of the \fIaccess_path\fP and the signal\'s name (identifier and
-if needed constraint). The \fIaccess_path\fP is a string representing the
-instance where the signal is declared. It is a list of instance names separated
-by \'.\' (dot).
-
-.PP
-The \fIspy option\fP (keyword \fIspy\fP) may be used for outputs (out port,
-inout port, internal signal). This option makes one additional pattern be
-printed in the result file each time an event occurs on this signal during
-the simulation and the corresponding pattern (with this event date) has been
-omitted in the input pattern file.
-
-.PP
-Putting one or several additional \';\' (semicolon) at the end of an
-input\-output declaration makes one or several blank columns (up to 15) be
-printed in the result file after the input\-output's value.
-
-.PP
-\fBThe description block\fP is a series of pattern description statements.
-Each pattern is a list of values preceded by a date and optionally by a label.
-.RS
-[\fIdate\fP] [\fIlabel\fP] : \fIlist_of_values\fP ;
-.RE
-
-.PP
-Patterns statements should be ordered with stict growing dates in the series.
-
-.PP
-The \fIdate\fP may be either an \fIabsolute date\fP or a relative date.
-An \fIabsolute date\fP is an integer followed by a \fPtime unit\fP.
-A \fIrelative date\fP is a '+' followed by an integer and a \fPtime unit\fP
-(the reference is the date of the previous pattern description statement).
-Legal \fItime unit\fP are ps, ns, us and ms.
-.RS
-< 200 ps >,<4500ns>,< 12us > are legal absolute dates.
-< +200 ps >,<+4500ns>,<+1 us> are legal relative dates.
-.RE
-
-.PP
-A \fIlabel\fP is an identifier (in VHDL syntax). The \fIlist_of_values\fP is
-a set of values. Each value is associated with one input\-output. The value
-of rank i corresponds to the i\-th input\-output. Depending on the format,
-legal values for inputs are:
-
-.TP 10
-\fBB\fP (binary)
-0 and, 1
-.TP 10
-\fBO\fP (octal)
-0, 1, 2, 3, 4, 5, 6 and, 7
-.TP 10
-\fBX\fP (hexa.)
-0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E and, F
-
-.PP
-For each output the user can predict a value. This bring the simulator to make
-a comparison between this value and the one calculated during the simulation.
-Predicting a \'*\' (star) as an output value disables the comparison. Values
-must be preceeded by a \'?\' (question mark). The \'?\' can be omitted when
-using a \'*\'. Depending on the format, legal values for outputs are :
-
-.TP 10
-\fBB\fP (binary)
-0, 1 and *
-.TP 10
-\fBO\fP (octal)
-0, 1, 2, 3, 4, 5, 6, 7 and *
-.TP 10
-\fBX\fP (hexa.)
-0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F and *
-
-.PP
-Using the binary format \'?1\' can be replaced by \'+\' (plus) and \'?0\' by
-\'\-\' (minus).
-
-.PP
-.TP 10
-Example
-.nf
-in  A (0 to 15) X;
-in  B (0 to 15) X;
-in  Cin;
-out Cout;
-signal S (0 to 15) X;
-register Accu.A (0 to 15) X;
-
-begin
-
-<   0 ns > pattern_0 : F0F0 0A0A 1 ?0 ?FAFA ?6DE7;
-< +10 ns > pattern_1 : 0F0F F6F0 0  +  **** ?54FC;
-
-end;
-.fi
-
-.PP
-Putting one or several additional \';\' (semicolon) at the end of a pattern
-makes one or several blank lines (up to 15) be printed in the result file
-after the pattern.
-
-.PP
-\fBOther statements (called actions)\fP such as changing registers value or
-saving the state of the circuit can be placed in the description block.
-
-.PP
-The content of a register can be forced to a user defined value using the
-following statement:
-.RS
-\fIregister_name\fP <= \fIvalue\fP ;
-.RE
-
-.PP
-\fIRegister_name\fP is a string representing the name of the register to be
-forced (written in the same form as described above).
-
-.PP
-\fIValue\fP can be given in hexadecimal (\fBX\fP), octal (\fBO\fP) or binary
-(\fBB\fP) format :
-.TP 10
-Examples
-X"0FE46"
-.br
-O"0345"
-.br
-B"01010111"
-.br
-"0111000"
-.br
-\'0\'
-
-.PP
-The value of the register will be forced to \fIvalue\fP just before the
-pattern following the statement is executed.
-
-.PP
-The state of the circuit can be saved after all patterns are processed using:
-.RS
-\fBsave;\fP
-.RE
-
-.PP
-The \fBsave;\fP statement must be placed just before the \fBend;\fP instruction.
-When writing a long sequence of patterns, this feature can be used to split
-the sequence into several small sequences (with a \fBsave\fP statement at the
-end of each sequence) (see asimut(1)).
-
-.PP
-In \fBpat\fP format a \fBcomment\fP begins with either a \'#\' (sharp) or a
-\'\-\-\' (two adjacent minus) and extends up to the end of the line. A comment
-marked by a \'\-\-\' is simply ignored. A comment maked by a \'#\' is
-kept at compile time and reproduced at the same place in the result file.
-
-.SH DIAGNOSTICS
-.PP
-\fBPat\fP does not make the difference between upper and lower case letters.
-
-.PP
-When the specified read\-write format is \fBO\fP (octal) for an array
-input\-output and the range of the input\-output doesn\'t match a multiple of
-3, the most significant bits \- 1 or 2 bits \- of the value are ignored.
-
-.PP
-When the specified read\-write format is \fBX\fP (hexadecimal) for an array
-input\-output and the range of the input\-output doesn\'t match a multiple of
-4, the most significant bits \- 1, 2 or 3 bits \- of the value are ignored.
-
-.PP
-A comment beginning with a \'#\' (sharp) placed after the \fBend;\fP statement
-causes a syntax error.
-
-.SH SEE ALSO
-.PP
-asimut(1), genpat(1), libpat(3)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/pck_sp.5 b/alliance/share/man/man5/pck_sp.5
deleted file mode 100644
index cb4595d5..00000000
--- a/alliance/share/man/man5/pck_sp.5
+++ /dev/null
@@ -1,42 +0,0 @@
-.\" $Id: pck_sp.5,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.pl -.4
-.TH pck_sp 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B pck_sp
-
-.so man1/alc_origin.1
-
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("pck_sp","name","pad","ck","vdde","vddi","vsse","vssi",0);
-.SH DESCRIPTION
-.I - Interface
-   entity pck_sp is
-     port(
-        pad : in bit;
-        ck : out bit;
-        vdde : in bit;
-        vddi : in bit;
-        vsse : in bit;
-        vssi : in bit);
-.br
-.I - Logical description
-.br
-    ck <= pad;
-   
-.br
-.I - Physical features
-   number of grids : 341
-   number of feed-through : 0
-.br
-   
-.I - Timing caracteristics
-.br
-   pad : 1326 (fF)
-        tphh = 228 (ps) + 68 (Ohms) x Cload (pF)
-        tpll = 1443 (ps) + 58 (Ohms) x Cload (pF)
-.br
-.br
-
-.so man1/alc_bug_report.1
diff --git a/alliance/share/man/man5/pi_sp.5 b/alliance/share/man/man5/pi_sp.5
deleted file mode 100644
index c309d42f..00000000
--- a/alliance/share/man/man5/pi_sp.5
+++ /dev/null
@@ -1,44 +0,0 @@
-.\" $Id: pi_sp.5,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.pl -.4
-.TH pi_sp 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B pi_sp
-
-.so man1/alc_origin.1
-
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("pi_sp","name","pad","t","ck","vdde","vddi","vsse","vssi",0);
-.SH DESCRIPTION
-.I - Interface
-   entity pi_sp is
-     port(
-        pad : in bit;
-        t : out bit;
-        ck : in bit;
-        vdde : in bit;
-        vddi : in bit;
-        vsse : in bit;
-        vssi : in bit);
-.br
-.I - Logical description
-.br
-    t <= pad;
-   
-.br
-.I - Physical features
-   number of grids : 341
-   number of feed-through : 0
-.br
-   
-.I - Timing caracteristics
-.br
-   pad : 654 (fF)
-        tphh = 233 (ps) + 273 (Ohms) x Cload (pF)
-        tpll = 1487 (ps) + 234 (Ohms) x Cload (pF)
-.br
-.br
-.br
-
-.so man1/alc_bug_report.1
diff --git a/alliance/share/man/man5/piot_sp.5 b/alliance/share/man/man5/piot_sp.5
deleted file mode 100644
index be61ea02..00000000
--- a/alliance/share/man/man5/piot_sp.5
+++ /dev/null
@@ -1,52 +0,0 @@
-.\" $Id: piot_sp.5,v 1.1 1999/05/31 17:30:26 alliance Exp $
-.pl -.4
-.TH piot_sp 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B piot_sp
-
-.so man1/alc_origin.1
-
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("piot_sp","name","i","b","t","pad","ck","vdde","vddi","vsse","vssi",0);
-.SH DESCRIPTION
-.I - Interface
-   entity piot_sp is
-     port(
-        i : in bit;
-        b : in bit;
-        t : out bit;
-        pad : mux_bit;
-        ck : in bit;
-        vdde : in bit;
-        vddi : in bit;
-        vsse : in bit;
-        vssi : in bit);
-.br
-.I - Logical description
-.br
-   label0 : block (b6 = '1')
-.br
-   begin
-.br
-     pad <= guarded i;
-.br
-   end block;
-.br
-   
-    t <= pad;
-   
-.br
-.I - Physical features
-   number of grids : 341
-   number of feed-through : 0
-.br
-   
-.I - Timing caracteristics
-.br
-.br
-.br
-.br
-
-.so man1/alc_bug_report.1
diff --git a/alliance/share/man/man5/piotw_sp.5 b/alliance/share/man/man5/piotw_sp.5
deleted file mode 100644
index 1fd990e6..00000000
--- a/alliance/share/man/man5/piotw_sp.5
+++ /dev/null
@@ -1,52 +0,0 @@
-.\" $Id: piotw_sp.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.pl -.4
-.TH piotw_sp 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B piotw_sp
-
-.so man1/alc_origin.1
-
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("piotw_sp","name","i","b","t","pad","ck","vdde","vddi","vsse","vssi",0);
-.SH DESCRIPTION
-.I - Interface
-   entity piotw_sp is
-     port(
-        i : in bit;
-        b : in bit;
-        t : out bit;
-        pad : mux_bit;
-        ck : in bit;
-        vdde : in bit;
-        vddi : in bit;
-        vsse : in bit;
-        vssi : in bit);
-.br
-.I - Logical description
-.br
-   label0 : block (b6 = '1')
-.br
-   begin
-.br
-     pad <= guarded i;
-.br
-   end block;
-.br
-   
-    t <= pad;
-   
-.br
-.I - Physical features
-   number of grids : 341
-   number of feed-through : 0
-.br
-   
-.I - Timing caracteristics
-.br
-.br
-.br
-.br
-
-.so man1/alc_bug_report.1
diff --git a/alliance/share/man/man5/po_sp.5 b/alliance/share/man/man5/po_sp.5
deleted file mode 100644
index 7f6eb634..00000000
--- a/alliance/share/man/man5/po_sp.5
+++ /dev/null
@@ -1,44 +0,0 @@
-.\" $Id: po_sp.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.pl -.4
-.TH po_sp 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B po_sp
-
-.so man1/alc_origin.1
-
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("po_sp","name","i","pad","ck","vdde","vddi","vsse","vssi",0);
-.SH DESCRIPTION
-.I - Interface
-   entity po_sp is
-     port(
-        i : in bit;
-        pad : out bit;
-        ck : in bit;
-        vdde : in bit;
-        vddi : in bit;
-        vsse : in bit;
-        vssi : in bit);
-.br
-.I - Logical description
-.br
-    pad <= i;
-   
-.br
-.I - Physical features
-   number of grids : 341
-   number of feed-through : 0
-.br
-   
-.I - Timing caracteristics
-.br
-   i : 191 (fF)
-        tphh = 2032 (ps) + 16 (Ohms) x Cload (pF)
-        tpll = 2176 (ps) + 15 (Ohms) x Cload (pF)
-.br
-.br
-.br
-
-.so man1/alc_bug_report.1
diff --git a/alliance/share/man/man5/pot_sp.5 b/alliance/share/man/man5/pot_sp.5
deleted file mode 100644
index 42b52d72..00000000
--- a/alliance/share/man/man5/pot_sp.5
+++ /dev/null
@@ -1,51 +0,0 @@
-.\" $Id: pot_sp.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.pl -.4
-.TH pot_sp 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B pot_sp
-
-.so man1/alc_origin.1
-
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("pot_sp","name","i","b","pad","ck","vdde","vddi","vsse","vssi",0);
-.SH DESCRIPTION
-.I - Interface
-   entity pot_sp is
-     port(
-        i : in bit;
-        b : in bit;
-        pad : mux_bit;
-        ck : in bit;
-        vdde : in bit;
-        vddi : in bit;
-        vsse : in bit;
-        vssi : in bit);
-.br
-.I - Logical description
-.br
-   label0 : block (b6 = '1')
-.br
-   begin
-.br
-     pad <= guarded i;
-.br
-   end block;
-.br
-   
-   
-.br
-.I - Physical features
-   number of grids : 341
-   number of feed-through : 0
-.br
-   
-.I - Timing caracteristics
-.br
-.br
-.br
-
-.so man1/alc_bug_report.1
-
-
diff --git a/alliance/share/man/man5/potw_sp.5 b/alliance/share/man/man5/potw_sp.5
deleted file mode 100644
index a5bdc5c1..00000000
--- a/alliance/share/man/man5/potw_sp.5
+++ /dev/null
@@ -1,49 +0,0 @@
-.\" $Id: potw_sp.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.pl -.4
-.TH potw_sp 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B potw_sp
-
-.so man1/alc_origin.1
-
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("potw_sp","name","i","b","pad","ck","vdde","vddi","vsse","vssi",0);
-.SH DESCRIPTION
-.I - Interface
-   entity potw_sp is
-     port(
-        i : in bit;
-        b : in bit;
-        pad : mux_bit;
-        ck : in bit;
-        vdde : in bit;
-        vddi : in bit;
-        vsse : in bit;
-        vssi : in bit);
-.br
-.I - Logical description
-.br
-   label0 : block (b6 = '1')
-.br
-   begin
-.br
-     pad <= guarded i;
-.br
-   end block;
-.br
-   
-   
-.br
-.I - Physical features
-   number of grids : 341
-   number of feed-through : 0
-.br
-   
-.I - Timing caracteristics
-.br
-.br
-.br
-
-.so man1/alc_bug_report.1
diff --git a/alliance/share/man/man5/pow_sp.5 b/alliance/share/man/man5/pow_sp.5
deleted file mode 100644
index 81ef838d..00000000
--- a/alliance/share/man/man5/pow_sp.5
+++ /dev/null
@@ -1,44 +0,0 @@
-.\" $Id: pow_sp.5,v 1.1 1999/05/31 17:30:29 alliance Exp $
-.pl -.4
-.TH pow_sp 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B pow_sp
-
-.so man1/alc_origin.1
-
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("pow_sp","name","i","pad","ck","vdde","vddi","vsse","vssi",0);
-.SH DESCRIPTION
-.I - Interface
-   entity pow_sp is
-     port(
-        i : in bit;
-        pad : out bit;
-        ck : in bit;
-        vdde : in bit;
-        vddi : in bit;
-        vsse : in bit;
-        vssi : in bit);
-.br
-.I - Logical description
-.br
-    pad <= i;
-   
-.br
-.I - Physical features
-   number of grids : 341
-   number of feed-through : 0
-.br
-   
-.I - Timing caracteristics
-.br
-   i : 191 (fF)
-        tphh = 1608 (ps) + 32 (Ohms) x Cload (pF)
-        tpll = 1777 (ps) + 30 (Ohms) x Cload (pF)
-.br
-.br
-.br
-
-.so man1/alc_bug_report.1
diff --git a/alliance/share/man/man5/prol.5 b/alliance/share/man/man5/prol.5
deleted file mode 100644
index 8b922830..00000000
--- a/alliance/share/man/man5/prol.5
+++ /dev/null
@@ -1,819 +0,0 @@
-.\"   $Id: prol.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.\" @(#)prol.5 2.11 91/08/22; Labo Cao-vlsi; Author : Frederic Petrot & Franck Wajsburt
-.TH PROL 5 "October 1, 1997" "ASIM/LIP6" "RDS FILE FORMATS"
-.SH NAME
-\fBprol\fP \- define the rules for symbolic to real layout translation
-.so man1/alc_origin.1
-.SH DESCRIPTION
-This file describes the rules used by the \fBmbk\fP(1) to \fBrds\fP translator.
-In the following file, symbolic layout objects are refered as \fBmbk\fP(1)
-objects, \fBmbk\fP(1) being the internal data structure that supports
-symbolic representation.
-On the other hand, \fBrds\fP is a data structure describing mainly rectangles,
-and is therefore used for real layout representation.
-.PP
-Some syntaxic remarques on the way to write the file follow.
-The case of identifiers is not significant, so NDIF is equivalent to NdiF.
-Comments are allowed anywhere in the file, using the \fIsharp\fP (#) as start of
-comment, and \fInewline\fP as end of comment.
-A line begining with a \fIsharp\fP will be ignored, and a line containing a
-\fIsharp\fP will be read up to the character preeceding it.
-A \fInewline\fP can be escaped using the \fIbackslash\fP (\) followed by
-the \fInewline\fP.
-If some character, spaces or tabs for example, follow the \fIbackslash\fP,
-chances are that a syntax error will be issued.
-.PP
-First, some important process parameters are needed, the physical grid step,
-that is the least common multiple of all the technologies values in terms of
-layout distances, and the
-.ie t \(*l,
-.el lambda,
-computed from a careful observation of the process design rules.
-.br
-Then, a set of tables is needed, to describe how to translate a symbolic
-object, belonging to the \fBmbk\fP(1) world, and a set of layout rectangles,
-in \fBrds\fP.
-.br
-Each table has a special meaning, and its parametrization exend beeing not
-full, some borders are to be evocated.
-Several type of table exists indeed.
-Some are needed for object translation, others for post treatment
-parametrization, others to define cif or gds identifiers regarding rds ones.
-.br
-Many things seem to be parametrizable, but in fact, mostly, if not only,
-numbers, names in cif and gds translation tables, and boolean value in post
-treatement may be changed without problems.
-.PP
-For any table, if some layer is not applicable, it can simply be omitted.
-The default action is `do nothing', or use a value of 0.0 for all entries.
-.SH LAYERS AND PATTERNS
-Since the goal of this file is to allow translation from \fBmbk\fP(1)
-to \fBrds\fP, the meaning of the layers in both representation shall be known.
-.br
-\s+2\fBMbk layers\fP\s-2
-.RS 5
-.TP 20
-NWELL
-minimum width 4 ; N-well.
-.TP 20
-PWELL
-minimum width 4 ; P-well.
-.TP 20
-NTIE
-minimum width 2 ; N diffusion for polarisation.
-.TP 20
-PTIE
-minimum width 2 ; P diffusion for polarisation.
-.TP 20
-NDIF
-minimum width 2 ; N diffusion for transistor.
-.TP 20
-PDIF
-minimum width 2 ; P diffusion for transistor.
-.TP 20
-NTRANS
-minimum width 1 (gate width) ; N transistor.
-.TP 20
-PTRANS
-minimum width 1 (gate width) ; P transistor.
-.TP 20
-POLY
-minimum width 1 ; polysilicon, not transistor gate.
-.TP 20
-ALU1
-minimum width 1 ; first level of metal.
-.TP 20
-ALU2
-minimum width 2 ; second level of metal.
-.TP 20
-ALU3
-minimum width 3 ; third level of metal (unused).
-.TP 20
-TPOLY
-minimum width 1 ; through route for POLY.
-.TP 20
-TALU1
-minimum width 1 ; through route for ALU1.
-.TP 20
-TALU2
-minimum width 2 ; through route for ALU2.
-.TP 20
-TALU3
-minimum width 3 ; through route for ALU3 (unused).
-.RE
-\s+2\fBMbk patterns\fP\s-2
-.RS 5
-.TP 20
-CONT_POLY
-cut pattern from ALU1 to POLY
-.TP 20
-CONT_VIA
-cut pattern from ALU1 to ALU2
-.TP 20
-CONT_VIA2
-cut pattern from ALU2 to ALU3
-.TP 20
-CONT_DIF_N
-cut pattern from ALU1 to NDIF
-.TP 20
-CONT_DIF_P
-cut pattern from ALU1 to PDIF
-.TP 20
-CONT_BODY_N
-cut pattern from ALU1 to NTIE
-.TP 20
-CONT_BODY_P
-cut pattern from ALU1 to PTIE
-.TP 20
-C_X_N
-corner primitive for L or S shaped N transistor
-.TP 20
-C_X_P
-corner primitive for L or S shaped P transistor
-.RE
-\s+2\fBRds layers\fP\s-2
-.RS 5
-.TP 20
-RDS_NWELL
-N-well (or N-tub), bulk for P transistors.
-.TP 20
-RDS_PWELL
-P-well (or P-tub), bulk for N transistors.
-.TP 20
-RDS_NDIF
-use for symbolic extractor as equivalent of NDIF.
-.TP 20
-RDS_PDIF
-use for symbolic extractor as equivalent of PDIF.
-.TP 20
-RDS_NTIE
-use for symbolic extractor as equivalent of NTIE.
-.TP 20
-RDS_PTIE
-use for symbolic extractor as equivalent of PTIE.
-.TP 20
-RDS_POLY
-polysillicon run, for cell internal wirering.
-.TP 20
-RDS_GATE
-transistor polysillicon, for gate.
-.TP 20
-RDS_TPOLY
-polysillicon feed through.
-Indicate to a router that a track is free of polysillicon.
-.TP 20
-RDS_CONT
-hole in the isolating layer between polysillicon or active area and
-first metal level.
-.TP 20
-RDS_ALU1
-first metal level run.
-.TP 20
-RDS_TALU1
-first metal level feed through.
-Indicates to a router that a track is free of first metal level.
-.TP 20
-RDS_VIA1
-hole in the isolating layer between first metal level and second metal level.
-.TP 20
-RDS_ALU2
-second metal level run.
-.TP 20
-RDS_TALU2
-second metal level feed through.
-Indicate to a router that a track is free of second metal level.
-.TP 20
-RDS_VIA2
-hole in the isolating layer between second metal level and third metal level.
-.TP 20
-RDS_ALU3
-third metal level run.
-.TP 20
-RDS_TALU3
-third metal level feed through.
-Indicate to a router that a track is free of third metal level.
-.TP 20
-RDS_ALU4
-fourth metal.
-(Used only for GaAs designs.)
-.TP 20
-RDS_VIA3
-hole in the isolating layer between third metal level and fourth metal level.
-(Used only for GaAs designs.)
-.TP 20
-RDS_ACTIV
-active area dropped in N or P implant to build transistors.
-.TP 20
-RDS_NIMP
-implant area, (sometime known as N select), for N transistors.
-.TP 20
-RDS_PIMP
-implant area, (sometime known as P select), for P transistors.
-.TP 20
-RDS_CPAS
-passivation, used in pads.
-.TP 20
-RDS_USER0
-user defined purpose layer.
-(May be used for DRC logical operations.)
-.TP 20
-RDS_USER1
-user defined purpose layer.
-(May be used for DRC logical operations.)
-.TP 20
-RDS_USER2
-user defined purpose layer.
-(May be used for DRC logical operations.)
-.TP 20
-RDS_REF
-virtual layer for the representation of symbolic references
-.TP 20
-RDS_ABOX
-virtual layer needed to indicate the abutment box of a model.
-.TP 20
-RDS_DEFAULT
-default layer, shall never appear anywhere.
-.RE
-.SH FILE DESCRIPTION
-The following lines describe the file, entry by entry, specifying what is
-expected.
-.TP 20
-\s+2\fBPhysical grid\fP\s-2
-.ie t \{\
-.ta 9m
-.ft CR \}
-.el \{\
-.ta 25m
-.ft B \}
-DEFINE PHYSICAL_GRID  .5
-.ft R
-.br
-This statement defines the minimum grid spacing enforced by the foundry.
-.TP
-\s+2\fBLambda\fP\s-2
-.ie t \{\
-.ft CR \}
-.el \{\
-.ft B \}
-DEFINE LAMBDA  1
-.ft R
-.br
-This defines the value of the
-.ie n lambda
-.el \(*l
-in
-.ie n microns.
-.el \(*m.
-This value, like any other one in the rest of the file \fImust\fP be a multiple
-of the
-.ie t \{\
-.ft CR \}
-.el \{\
-.ft B \}
-PHYSICAL_GRID\fR.
-.TP
-\s+2\fBSegment translation table\fP\s-2
-.ie t \{\
-.ft CR \}
-.el \{\
-.ft B \}
-TABLE MBK_TO_RDS_SEGMENT\fR
-.br
-This table contains all the informations needed to translate a symbolic
-segment of a given layer onto one, two or three real rectangles of
-specified layers.
-An example of this table is given below, with values needed for a
-technology where one
-.ie n lambda
-.el \(*l
-is equal to 1.05
-.ie microns
-.el \(*m
-and the design grid is set to 0.15
-.ie n microns.
-.el \(*m.
-.PP
-.ie n \{\
-.ft B \}
-.el \{\
-.ft CR \}
-.nf
-TABLE MBK_TO_RDS_SEGMENT
-
-  NWELL    RDS_NWELL   VW  3.15  6.30  0.0  ALL
-  NDIF     RDS_ACTIV   VW  0.60 -0.90  0.0  ALL \\
-           RDS_NIMP    VW  2.10  2.10  0.0  ALL
-  PDIF     RDS_ACTIV   VW  0.60 -0.90  0.0  ALL \\
-           RDS_PIMP    VW  2.10  2.10  0.0  ALL
-  NTIE     RDS_ACTIV   VW  0.60 -0.90  0.0  ALL \\
-           RDS_NIMP    VW  1.20  0.30  0.0  ALL
-  PTIE     RDS_ACTIV   VW  0.60 -0.90  0.0  ALL \\
-           RDS_PIMP    VW  1.20  0.30  0.0  ALL
-  NTRANS   RDS_GATE    VW  0.00  0.15  0.0  ALL \\
-           RDS_ACTIV   VW -1.50  4.35  0.0  ALL \\
-           RDS_NIMP    VW  0.00  7.35  0.0  ALL
-  PTRANS   RDS_GATE    VW  0.00  0.15  0.0  ALL \\
-           RDS_ACTIV   VW -1.50  4.35  0.0  ALL \\
-           RDS_PIMP    VW  0.00  7.35  0.0  ALL
-  POLY     RDS_POLY    VW  0.60  0.15  0.0  ALL
-  ALU1     RDS_ALU1    VW  0.90  0.75  0.0  ALL
-  ALU2     RDS_ALU2    VW  0.90 -0.30  0.0  ALL
-  TPOLY    RDS_TPOLY   VW  0.60  0.15  0.0  ALL
-  TALU1    RDS_TALU1   VW  0.90  0.75  0.0  ALL
-  TALU2    RDS_TALU2   VW  0.90 -0.30  0.0  ALL
-
-END
-
-.fi
-.ft R
-.RS 20
-The first column is the \fBmbk\fP(1) layer name to be translated, then there
-one or more groups of 6 columns each.
-For each physical rectangle, there are 3 parameters :
-.br
-\- rds layer name
-.br
-\- One of \fBVW\fR, \fBLCW\fR, \fBRCW\fR that indicates the `type' of segment
-to be generated
-.br
-\- physical length extension: \fIDLR\fP
-.br
-\- physical width oversize: \fIDWR\fP
-.br
-\- offset from symbolic axis: \fIOFFSET\fP
-.br
-\- tools for which the generated rectangle is applicable:
-\fBALL\fR, \fBDRC\fR (for the symbolic design rule checker,
-see \fBdruc\fR(1)), \fBEXT\fR
-(for the symbolic extractor, see \fBlynx\fR(1))
-These parameters are meant regarding the symbolic segment.
-.RE
-.TP 20
-\s+2\fBConnectors translation table\fP\s-2
-.ie t \{\
-.ft CR \}
-.el \{\
-.ft B \}
-TABLE MBK_TO_RDS_CONNECTOR\fR
-.br
-This table contains all the informations needed to translate a symbolic
-connector of a given layer onto one \fIsingle\fP real rectangle.
-.br
-An example of this table is given below, with values needed for a
-technology where one
-.ie n lambda
-.el \(*l
-is equal to 1.05
-.ie microns
-.el \(*m
-and the design grid is set to 0.15
-.ie n micron.
-.el \(*m.
-.PP
-.ie t \{\
-.ft CR \}
-.el \{\
-.ft B \}
-.nf
-TABLE MBK_TO_RDS_CONNECTOR
-
-  POLY     RDS_POLY  0.6   0.15
-  ALU1     RDS_ALU1  0.9   0.75
-  ALU2     RDS_ALU2  0.9  -0.3
-
-END
-.fi
-.ft R
-.RS 20
-One symbolic connector is translated into one
-physical rectangle using 3 parameters :
-.br
-\- rds layer name
-.br
-\- physical width oversize: \fIDWR\fP
-.br
-\- physical extension on each side of the abutment box: \fIDER\fP
-
-.RE
-.RS 20
-It is discouraged to use active or well layers as connectors while
-designing.
-.RE
-.TP 20
-\s+2\fBVias translation table\fP\s-2
-.ie t \{\
-.ft CR \}
-.el \{\
-.ft B \}
-TABLE MBK_TO_RDS_VIA\fR
-.br
-This table contains all the informations needed to translate a symbolic
-via of a given layer onto one to four real rectangles of user
-specified layers.
-An example of this table is given below, with values needed for a
-technology where one
-.ie n lambda
-.el \(*l
-is equal to 1.05
-.ie microns
-.el \(*m
-and the design grid is set to 0.15
-.ie n micron.
-.el \(*m.
-.PP
-.ie t \{\
-.ft CR \}
-.el \{\
-.ft B \}
-.nf
-TABLE MBK_TO_RDS_VIA
-
-  CONT_BODY_N RDS_ALU1 3   RDS_CONT  1.5 RDS_ACTIV 3.3 RDS_NIMP 4.5
-  CONT_BODY_P RDS_ALU1 3   RDS_CONT  1.5 RDS_ACTIV 3.3 RDS_PIMP 4.5
-  CONT_DIF_N  RDS_ALU1 3   RDS_CONT  1.5 RDS_ACTIV 3.3 RDS_NIMP 6.3
-  CONT_DIF_P  RDS_ALU1 3   RDS_CONT  1.5 RDS_ACTIV 3.3 RDS_PIMP 6.3
-  CONT_POLY   RDS_ALU1 3   RDS_CONT  1.5 RDS_POLY  3
-  CONT_VIA    RDS_ALU1 3   RDS_VIA1  1.5 RDS_ALU2  3
-  CONT_VIA2
-  C_X_N       RDS_GATE 1.2 RDS_ACTIV 5.4 RDS_NIMP  8.4
-  C_X_P       RDS_GATE 1.2 RDS_ACTIV 5.4 RDS_PIMP  8.4
-
-END
-
-.fi
-.br
-.ft R
-.RS 20
-This table describes how to translate one symbolic via,
-to 2, 3 or 4 physical rectangles.
-The table is defined as follow :
-The first column is the \fBmbk\fP(1) via name to translate, then there are
-4 groups of 2 columns each, which correspond to four potential targets
-\fBrds\fP rectangles of user specified layer.
-In one group the first column is the \fBrds\fP layer name, the second one is
-the \fBrds\fP layer width.
-The rectangle is centered on the contact coordinates, and expands in the four
-direction of half the given width value.
-.RE
-.TP 20
-\s+2\fBDenotching values table\fP\s-2
-.ie t \{\
-.ft CR \}
-.el \{\
-.ft B \}
-TABLE S2R_OVERSIZE_DENOTCH\fR
-.br
-This table contains the oversize value needed to erase notches.
-All the rectangles of the same \fBrds\fP layer are oversized by this value
-and then merged alltogether and undersized by the same value.
-An example of this table is given below.
-.PP
-.ie t \{\
-.ft CR \}
-.el \{\
-.ft B \}
-.nf
-TABLE S2R_OVERSIZE_DENOTCH
-
-  RDS_NWELL   3.00
-  RDS_POLY    0.75
-  RDS_GATE    0.75
-  RDS_ALU1    0.75
-  RDS_ALU2    0.75
-  RDS_ACTIV   1.05
-  RDS_NIMP    2.55
-  RDS_PIMP    2.55
-
-END
-.fi
-.ft R
-.RS 20
-For some \fBrds\fP layers, like RDS_NWELL, RDS_NIMP and RDS_PIMP, two
-rectangles distant from less or equal the minimun spacing design
-rule must be merged in a single one.
-In this case, the oversize value is equal to the minimum spacing rule
-between two edges of the same layer divided by 2. 
-.br
-Some other \fBrds\fP layers, like RDS_ALU1, ..., must not be merged.
-In this case, the oversize value is equal to the minimum spacing rule
-between two edges of the same layer divided by 2, minus the physical
-grid. 
-.br
-Some layers never create notch, such as RDS_VIA1 or RDS_CONT, so
-the oversize value is null.
-.RE
-.TP 20
-\s+2\fBRing width\fP\s-2
-.ie t \{\
-.ft CR \}
-.el \{\
-.ft B \}
-TABLE S2R_BLOC_RING_WIDTH\fR
-.br
-s2r must merge segments to erase notches even if those segments
-are in two different hierarchical level blocs, for example, two
-blocs abuted side to side.
-So, it must be able to fetch segments inside blocs. 
-It is not needed to flatten the entire bloc, only a ring is
-necessary. The ring is computed from the abutment box edges or from 
-the envelop edges of the overlapping blocs.
-.br
-An example of this table is given below.
-.PP
-.ie t \{\
-.ft CR \}
-.el \{\
-.ft B \}
-.nf
-TABLE S2R_BLOC_RING_WIDTH
-
-  RDS_NWELL   6
-  RDS_POLY    1.8
-  RDS_GATE    1.8
-  RDS_ALU1    1.8
-  RDS_ALU2    1.8
-  RDS_ACTIV   2.4
-  RDS_NIMP    1.8
-  RDS_PIMP    1.8
-
-END
-.fi
-.br
-.ft R
-.RS 20
-The normal ring width is the minimum spacing design rule between two
-segments of the same rds layer. 
-.br
-A zero means that no ring is wanted for that rds layer. 
-.RE
-.TP 20
-\s+2\fBMinimum real layer width design rule\fP\s-2
-.ie t \{\
-.ft CR \}
-.el \{\
-.ft B \}
-TABLE S2R_MINIMUM_LAYER_WIDTH\fR
-.br
-This table contains the minimum width of each rds layer.
-It is used by s2r to avoid creating rectangles below the minimum 
-required, during the merge operation.
-.PP
-.ie t \{\
-.ft CR \}
-.el \{\
-.ft B \}
-.nf
-TABLE S2R_MINIMUM_LAYER_WIDTH
-  RDS_NWELL   6
-  RDS_POLY    1.2
-  RDS_GATE    1.2
-  RDS_ALU1    1.8
-  RDS_ALU2    1.8
-  RDS_ACTIV   1.2
-  RDS_NIMP    2.7
-  RDS_PIMP    2.7
-
-END
-.fi
-.ft R
-.RS 20
-A zero can be specified, when it is sure that this layer is 
-not to be merged, because not treated by s2r.
-.RE
-.TP 20
-\s+2\fBPost treatment configuration table\fP\s-2
-.ie t \{\
-.ft CR \}
-.el \{\
-.ft B \}
-TABLE S2R_POST_TREAT\fR
-.br
-This table indicates to s2r which rds layers must be post-processed.
-Precicely if a layer is only to be be translated, or translated
-and then post-processed.
-Translated means translate and fit from symbolic to real, and
-postreated that it should also be merged with its neighbours.
-For example, it's not necesary to merge cut layers such as RDS_CONT. 
-.PP
-.ie t \{\
-.ft CR \}
-.el \{\
-.ft B \}
-.nf
-TABLE S2R_POST_TREAT
-
-  RDS_NWELL        TREAT NULL
-  RDS_PWELL      NOTREAT NULL
-  RDS_NDIF       NOTREAT NULL
-  RDS_PDIF       NOTREAT NULL
-  RDS_NTIE       NOTREAT NULL
-  RDS_PTIE       NOTREAT NULL
-  RDS_POLY         TREAT NULL
-  RDS_GATE         TREAT NULL
-  RDS_TPOLY      NOTREAT NULL
-  RDS_CONT       NOTREAT NULL
-  RDS_ALU1         TREAT NULL
-  RDS_TALU1      NOTREAT NULL
-  RDS_VIA1       NOTREAT NULL
-  RDS_ALU2         TREAT NULL
-  RDS_TALU2      NOTREAT NULL
-  RDS_VIA2       NOTREAT NULL
-  RDS_ALU3       NOTREAT NULL
-  RDS_TALU3      NOTREAT NULL
-  RDS_ACTIV        TREAT NULL
-  RDS_NIMP         TREAT RDS_PIMP
-  RDS_PIMP         TREAT RDS_NIMP
-  RDS_REF        NOTREAT NULL
-  RDS_ABOX       NOTREAT NULL
-
-END
-.fi
-.ft R
-.RS 20
-If set to NOTREAT, the first parameter indicates a translation.
-If set to TREAT, then the layer is translated and then post-treated
-.br
-To post-process creates problems with the implantation layers.
-It is possible to have a good symbolic layout (no symbolic design
-rule errors), and have a resulting layout with DRC violations,
-created by a poor post-processing.
-It is due to the fact that these layers do not exist in symbolic,
-so it is not possible to apply them drc verifications.
-If two rectangles of these layers are too close (less than a
-given value), they must be merged.
-Generally, there is no problem, but when corners are too near it is
-impossible to merge with the classical algorithm,
-\fIexpand\fP, \fImerge\fP, then \fIshrink\fP.
-.br
-Rectangles, known as scotches, are created to merge anyway,
-like this :
-.RE
-.ie t \{\
-.ft CR \}
-.el \fB
-.nf
-+--------+            +--------+           +-----+--+
-|////////|            |////////|           |/////|//|
-|//+--+//|            |//+--+//|           |//+--|//|
-|//|  |//|  gives ->  |//|  |//|     or -> |//|  |//|
-|//+--+//|            +-----------+        |//+--|//|
-|////////|            |///////////|        |/////|//|
-+--------+            +--------+//|        +-----|//|     
-    ^    +--------+            |//|-----+        |//+--------+
-    |    |////////|            |//|/////|        |///////////|
-    o--->|//+--+//|            |//|--+//|        +-----------+
-    |    |//|  |//|            |//|  |//|           |//|  |//|
-implant  |//+--+//|            |//|--+//|           |//|--+//|
- areas   |////////|            |//|/////|           |//|/////|
-         +--------+            +--+-----+           +--+-----+
-.fi
-.ft R
-.RS 20
-A N implantation layer should not overlap a P implantation one.
-We say that P implantations and N implantations are 
-complementary. A scotch will not be created if it intersects with 
-any of the rectangles of the complementary layers.
-.br
-If a record contains in the second field a rds layer different from
-NULL, it indicates the complementary layer.
-This implies that if it is a layer that might need scotches
-the algorithm will try not to intersect with it when creating
-scotches.
-.RE
-.TP 20
-\s+2\fBExtraction graph table\fP\s-2
-.ie t \{\
-.ft CR \}
-.el \{\
-.ft B \}
-TABLE LYNX_GRAPH\fR
-.br
-This table gives the connexion graph between the rds layers.
-For each layer, the list of the connectable layers is written.
-Up to now, the extractor works only on translated symbolic layout.
-.PP
-.ie t \{\
-.ft CR \}
-.el \{\
-.ft B \}
-.nf
-TABLE LYNX_GRAPH
-
-  RDS_NDIF RDS_CONT RDS_NDIF
-  RDS_PDIF RDS_CONT RDS_PDIF
-  RDS_NTIE RDS_CONT RDS_NTIE
-  RDS_PTIE RDS_CONT RDS_PTIE
-  RDS_POLY RDS_CONT RDS_GATE RDS_POLY
-  RDS_GATE RDS_POLY RDS_GATE
-  RDS_CONT RDS_PDIF RDS_NDIF RDS_POLY RDS_PTIE RDS_NTIE RDS_ALU1 RDS_CONT
-  RDS_ALU1 RDS_CONT RDS_VIA1 RDS_ALU1 RDS_REF
-  RDS_REF  RDS_CONT RDS_VIA1 RDS_ALU1 RDS_REF
-  RDS_VIA1 RDS_ALU1 RDS_ALU2 RDS_VIA1
-  RDS_ALU2 RDS_VIA1 RDS_VIA2 RDS_ALU2
-  RDS_VIA2 RDS_ALU2 RDS_ALU3 RDS_VIA2
-  RDS_ALU3 RDS_VIA2 RDS_ALU3
-
-END
-.fi
-.TP 20
-\s+2\fBExtraction capacitance table\fP\s-2
-.ie t \{\
-.ft CR \}
-.el \{\
-.ft B \}
-TABLE LYNX_CAPA\fR
-.br
-This table gives the capacitance in picofarad per square lambda of each
-layer.
-The extractor computes only substrat capacitances.
-The capacitances associated with gate or drain or sources are not computed.
-On the other hand the transistor sizes (area, perimeter) are computed.
-(This is to ensure compatibility with Spice).
-.PP
-.ie t \{\
-.ft CR \}
-.el \{\
-.ft B \}
-.nf
-TABLE LYNX_CAPA
-
-  RDS_POLY    1.00e-04
-  RDS_ALU1    0.50e-04
-  RDS_ALU2    0.25e-04
- 
-END
-.fi
-.TP 20
-\s+2\fBCif translation table\fP\s-2
-.ie t \{\
-.ft CR \}
-.el \{\
-.ft B \}
-TABLE CIF_LAYER\fR
-.br
-This table gives the equivalence between internal layers and their
-representation in the \fBcif\fP file format.
-A table may look like that (for MOSIS layers):
-.PP
-.ie t \{\
-.ft CR \}
-.el \{\
-.ft B \}
-.nf
-TABLE CIF_LAYER
-
-  RDS_NWELL   CWN
-  RDS_PWELL   CWP
-  RDS_ACTIV   CAA
-  RDS_NIMP    CSN
-  RDS_PIMP    CSP
-  RDS_POLY    CPG
-  RDS_GATE    CPG
-  RDS_CONT    CCA
-  RDS_ALU1    CMF
-  RDS_VIA1    CVA
-  RDS_ALU2    CMS
-
-END
-.fi
-.ft R
-.TP 20
-\s+2\fBGds translation table\fP\s-2
-.ie t \{\
-.ft CR \}
-.el \{\
-.ft B \}
-TABLE GDS_LAYER\fR
-.br
-This table gives the equivalence between internal layers and there
-representation in the \fBgds\fP file.
-A table may look like that (for CMP layers):
-.PP
-.ie t \{\
-.ft CR \}
-.el \{\
-.ft B \}
-.nf
-TABLE GDS_LAYER
-
-  RDS_NWELL    1
-  RDS_POLY    11
-  RDS_GATE    11
-  RDS_CONT    16
-  RDS_ALU1    17
-  RDS_VIA1    18
-  RDS_ALU2    19
-  RDS_ACTIV    2
-  RDS_NIMP    12
-  RDS_PIMP    14
-  RDS_CPAS    20
-
-END
-.fi
-.ft R
-.SH SEE ALSO
-Insights on the symbolic to real translation process are available in
-the file \fBmapping.ps\fR
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/pvdde_sp.5 b/alliance/share/man/man5/pvdde_sp.5
deleted file mode 100644
index 1f6a0de7..00000000
--- a/alliance/share/man/man5/pvdde_sp.5
+++ /dev/null
@@ -1,37 +0,0 @@
-.\" $Id: pvdde_sp.5,v 1.1 1999/05/31 17:30:29 alliance Exp $
-.pl -.4
-.TH pvdde_sp 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B pvdde_sp
-
-.so man1/alc_origin.1
-
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("pvdde_sp","name","ck","vdde","vddi","vsse","vssi",0);
-.SH DESCRIPTION
-.I - Interface
-   entity pvdde_sp is
-     port(
-        ck : in bit;
-        vdde : in bit;
-        vddi : in bit;
-        vsse : in bit;
-        vssi : in bit);
-.br
-.I - Logical description
-.br
-   
-.br
-.I - Physical features
-   number of grids : 341
-   number of feed-through : 0
-.br
-   
-.I - Timing caracteristics
-.br
-.br
-.br
-
-.so man1/alc_bug_report.1
diff --git a/alliance/share/man/man5/pvddeck_sp.5 b/alliance/share/man/man5/pvddeck_sp.5
deleted file mode 100644
index 34197ca6..00000000
--- a/alliance/share/man/man5/pvddeck_sp.5
+++ /dev/null
@@ -1,50 +0,0 @@
-.\" $Id: pvddeck_sp.5,v 1.1 1999/05/31 17:30:29 alliance Exp $
-.pl -.4
-.TH pvddeck_sp 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B pvddeck_sp
-
-.so man1/alc_origin.1
-
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("pvddeck_sp","name","cko","ck","vdde","vddi","vsse","vssi",0);
-.SH DESCRIPTION
-.I - Interface
-   entity pvddeck_sp is
-     port(
-        cko : ;
-        ck : in bit;
-        vdde : in bit;
-        vddi : in bit;
-        vsse : in bit;
-        vssi : in bit);
-.br
-.I - Logical description
-.br
-   label0 : block ('1' = '1')
-.br
-   begin
-.br
-     cko <= guarded ck;
-.br
-   end block;
-.br
-   
-   
-.br
-.I - Physical features
-   number of grids : 341
-   number of feed-through : 0
-.br
-   
-.I - Timing caracteristics
-.br
-   ck : 127 (fF)
-        tphh = 963 (ps) + 183 (Ohms) x Cload (pF)
-        tpll = 1055 (ps) + 126 (Ohms) x Cload (pF)
-.br
-.br
-
-.so man1/alc_bug_report.1
diff --git a/alliance/share/man/man5/pvddi_sp.5 b/alliance/share/man/man5/pvddi_sp.5
deleted file mode 100644
index 4095a904..00000000
--- a/alliance/share/man/man5/pvddi_sp.5
+++ /dev/null
@@ -1,38 +0,0 @@
-.\" $Id: pvddi_sp.5,v 1.1 1999/05/31 17:30:29 alliance Exp $
-.pl -.4
-.TH pvddi_sp 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B pvddi_sp
-
-.so man1/alc_origin.1
-
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("pvddi_sp","name","ck","vdde","vddi","vsse","vssi",0);
-.SH DESCRIPTION
-.I - Interface
-   entity pvddi_sp is
-     port(
-        ck : in bit;
-        vdde : in bit;
-        vddi : in bit;
-        vsse : in bit;
-        vssi : in bit);
-.br
-.I - Logical description
-.br
-   
-.br
-.I - Physical features
-   number of grids : 341
-   number of feed-through : 0
-.br
-   
-.I - Timing caracteristics
-.br
-.br
-.br
-.br
-
-.so man1/alc_bug_report.1
diff --git a/alliance/share/man/man5/pvddick_sp.5 b/alliance/share/man/man5/pvddick_sp.5
deleted file mode 100644
index 02edbf1f..00000000
--- a/alliance/share/man/man5/pvddick_sp.5
+++ /dev/null
@@ -1,51 +0,0 @@
-.\" $Id: pvddick_sp.5,v 1.1 1999/05/31 17:30:29 alliance Exp $
-.pl -.4
-.TH pvddick_sp 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B pvddick_sp
-
-.so man1/alc_origin.1
-
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("pvddick_sp","name","cko","ck","vdde","vddi","vsse","vssi",0);
-.SH DESCRIPTION
-.I - Interface
-   entity pvddick_sp is
-     port(
-        cko : ;
-        ck : in bit;
-        vdde : in bit;
-        vddi : in bit;
-        vsse : in bit;
-        vssi : in bit);
-.br
-.I - Logical description
-.br
-   label0 : block ('1' = '1')
-.br
-   begin
-.br
-     cko <= guarded ck;
-.br
-   end block;
-.br
-   
-   
-.br
-.I - Physical features
-   number of grids : 341
-   number of feed-through : 0
-.br
-   
-.I - Timing caracteristics
-.br
-   ck : 127 (fF)
-        tphh = 1109 (ps) + 311 (Ohms) x Cload (pF)
-        tpll = 1235 (ps) + 253 (Ohms) x Cload (pF)
-.br
-.br
-.br
-
-.so man1/alc_bug_report.1
diff --git a/alliance/share/man/man5/pvsse_sp.5 b/alliance/share/man/man5/pvsse_sp.5
deleted file mode 100644
index debd6ac3..00000000
--- a/alliance/share/man/man5/pvsse_sp.5
+++ /dev/null
@@ -1,38 +0,0 @@
-.\" $Id: pvsse_sp.5,v 1.1 1999/05/31 17:30:29 alliance Exp $
-.pl -.4
-.TH pvsse_sp 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B pvsse_sp
-
-.so man1/alc_origin.1
-
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("pvsse_sp","name","ck","vdde","vddi","vsse","vssi",0);
-.SH DESCRIPTION
-.I - Interface
-   entity pvsse_sp is
-     port(
-        ck : in bit;
-        vdde : in bit;
-        vddi : in bit;
-        vsse : in bit;
-        vssi : in bit);
-.br
-.I - Logical description
-.br
-   
-.br
-.I - Physical features
-   number of grids : 341
-   number of feed-through : 0
-.br
-   
-.I - Timing caracteristics
-.br
-.br
-.br
-.br
-
-.so man1/alc_bug_report.1
\ No newline at end of file
diff --git a/alliance/share/man/man5/pvsseck_sp.5 b/alliance/share/man/man5/pvsseck_sp.5
deleted file mode 100644
index aa9c5c42..00000000
--- a/alliance/share/man/man5/pvsseck_sp.5
+++ /dev/null
@@ -1,51 +0,0 @@
-.\" $Id: pvsseck_sp.5,v 1.1 1999/05/31 17:30:29 alliance Exp $
-.pl -.4
-.TH pvsseck_sp 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B pvsseck_sp
-
-.so man1/alc_origin.1
-
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("pvsseck_sp","name","cko","ck","vdde","vddi","vsse","vssi",0);
-.SH DESCRIPTION
-.I - Interface
-   entity pvsseck_sp is
-     port(
-        cko : ;
-        ck : in bit;
-        vdde : in bit;
-        vddi : in bit;
-        vsse : in bit;
-        vssi : in bit);
-.br
-.I - Logical description
-.br
-   label0 : block ('1' = '1')
-.br
-   begin
-.br
-     cko <= guarded ck;
-.br
-   end block;
-.br
-   
-   
-.br
-.I - Physical features
-   number of grids : 341
-   number of feed-through : 0
-.br
-   
-.I - Timing caracteristics
-.br
-   ck : 127 (fF)
-        tphh = 963 (ps) + 183 (Ohms) x Cload (pF)
-        tpll = 1055 (ps) + 126 (Ohms) x Cload (pF)
-.br
-.br
-.br
-
-.so man1/alc_bug_report.1
diff --git a/alliance/share/man/man5/pvssi_sp.5 b/alliance/share/man/man5/pvssi_sp.5
deleted file mode 100644
index f8169845..00000000
--- a/alliance/share/man/man5/pvssi_sp.5
+++ /dev/null
@@ -1,36 +0,0 @@
-.\" $Id: pvssi_sp.5,v 1.1 1999/05/31 17:30:29 alliance Exp $
-.pl -.4
-.TH pvssi_sp 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B pvssi_sp
-
-.so man1/alc_origin.1
-
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("pvssi_sp","name","ck","vdde","vddi","vsse","vssi",0);
-.SH DESCRIPTION
-.I - Interface
-   entity pvssi_sp is
-     port(
-        ck : in bit;
-        vdde : in bit;
-        vddi : in bit;
-        vsse : in bit;
-        vssi : in bit);
-.br
-.I - Logical description
-.br
-   
-.br
-.I - Physical features
-   number of grids : 341
-   number of feed-through : 0
-.br
-   
-.I - Timing caracteristics
-.br
-.br
-
-.so man1/alc_bug_report.1
\ No newline at end of file
diff --git a/alliance/share/man/man5/pvssick_sp.5 b/alliance/share/man/man5/pvssick_sp.5
deleted file mode 100644
index 3ba542d8..00000000
--- a/alliance/share/man/man5/pvssick_sp.5
+++ /dev/null
@@ -1,50 +0,0 @@
-.\" $Id: pvssick_sp.5,v 1.1 1999/05/31 17:30:29 alliance Exp $
-.pl -.4
-.TH pvssick_sp 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B pvssick_sp
-
-.so man1/alc_origin.1
-
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("pvssick_sp","name","cko","ck","vdde","vddi","vsse","vssi",0);
-.SH DESCRIPTION
-.I - Interface
-   entity pvssick_sp is
-     port(
-        cko : ;
-        ck : in bit;
-        vdde : in bit;
-        vddi : in bit;
-        vsse : in bit;
-        vssi : in bit);
-.br
-.I - Logical description
-.br
-   label0 : block ('1' = '1')
-.br
-   begin
-.br
-     cko <= guarded ck;
-.br
-   end block;
-.br
-   
-   
-.br
-.I - Physical features
-   number of grids : 341
-   number of feed-through : 0
-.br
-   
-.I - Timing caracteristics
-.br
-   ck : 127 (fF)
-        tphh = 1109 (ps) + 311 (Ohms) x Cload (pF)
-        tpll = 1235 (ps) + 253 (Ohms) x Cload (pF)
-.br
-.br
-
-.so man1/alc_bug_report.1
\ No newline at end of file
diff --git a/alliance/share/man/man5/sclib.5 b/alliance/share/man/man5/sclib.5
deleted file mode 100644
index 716091f6..00000000
--- a/alliance/share/man/man5/sclib.5
+++ /dev/null
@@ -1,249 +0,0 @@
-.\"   $Id: sclib.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.\" @(#)Labo.l 0.0 92/09/24 UPMC; Author: El Housseine REJOUAN
-.pl -.4
-.TH SCLIB 5 "October 1, 1997" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
-.SH NAME
-.TP
-.B sclib
- - a portable CMOS Standard Cell Library
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.TP
-The library directory is defined by the environment variable \fBMBK_CATA_LIB\fP.
-.br
-.SH DESCRIPTION
-
- The symbolic layout approach is used for cell layout in order to provide process independance. The mapping to a specific process CIF or GDS2 layout is performed by s2r tool.
-.br
- Four files are attached to each cell :
-.br
-- layout			cellname.ap
-.br
-- transistor net-list	cellname.al
-.br
-- VHDL behaviour	cellname.vbe
-.br
-- postscript doc		cellname.ps
-.br
-For each cell, you can get detailed information using "man cellname".
-.br
-At the moment, sclib contains standard cells that have been developped at UPMC-ASIM/LIP6.
-.br
-It is possible to add new cells in the library just by providing the 3 files .ap, .al and .vbe in the standard cell directory.
-.br
-The layout view can be created with the symbolic editor graal.
-.br
-The topological constraints for the standard cell router scr are the abutment box size (height = 42 , width = 6 x n ), the metal1 VDD and VSS lines, the N well abutment, and I/Os in metal2 on south and north sides.
-.br
-The net-list view can be automatically generated with the lynx extractor
-.br
-The behavioural view can be checked with the yagle functional abstractor. The file must contain the generic fields in order to be used by the logic synthesis tools and the I/Os terminals must be in the same order in the .vbe and .al files.
-.br
-If you develop new cells, please send the corresponding files to alliance\-support@asim.lip6.fr
-
-.B List of cells :
-.br
-
--------------------------------------------------------------------------------------------------------
-.br
-|	Description				Fanout		Name            |
-.br
--------------------------------------------------------------------------------------------------------
-.br
-	\fB=> AND\fP
-.br
-	  (A.B)					(drive=1)	a2_y                               
-.br
-	  (A.B)					(drive=2)	a2p_y
-.br
-	  (A.B.C)				(drive=1)	a3_y
-.br
-	  (A.B.C)				(drive=2)	a3p_y
-.br
-	  (A.B.C.D)				(drive=1)	a4_y
-.br
-	  (A.B.C.D)				(drive=2)	a4p_y
-.br
-	  /(A.B)					(drive=1)	na2_y
-.br
-	  /(A.B)					(drive=2)	na2p_y
-.br
-	  /(A.B.C)				(drive=1)	na3_y
-.br
-	  /(A.B.C)				(drive=2)	na3p_y
-.br
-	  /(A.B.C.D)				(drive=1)	na4_y
-.br
-
-	\fB=> OR\fP 
-.br
-	   (A+B)					(drive=1)	o2_y
-.br
-	   (A+B)					(drive=2)	op2_y
-.br
-	   (A+B+C)				(drive=1)	o3_y
-.br
-	   (A+B+C)				(drive=2)	op3_y
-.br
-	   /(A+B)				(drive=1)	no2_y
-.br
-	   /(A+B)				(drive=2)	nop2_y
-.br
-	   /(A+B+C)				(drive=1)	no3_y
-.br
-	   /(A+B+C)				(drive=2)	nop3_y
-.br
-
-	\fB=>INV/BUF/DELAY\fP
-.br
-	   inv					(drive=1)	n1_y
-.br
-	   inv					(drive=2)	np1_y
-.br
-	   inv					(drive=4)	ndrv_y
-.br
-	   buf					(drive=2)	p1_y
-.br
-	   buf					(drive=4)	b1_y
-.br
-	   delay					(drive=1)	d1_y
-.br
-
-	\fB=> T STATE\fP
-.br
-	   3-state-inv				(drive=1)	tsn_y
-.br
-	   3-state-buf				(drive=1)	ts_y
-.br
-	   3-state-buf				(drive=2)	tsp_y
-.br
-
-	\fB=> XOR\fP
-.br
-	   xor					(drive=1)	xr2_y
-.br
-	   nxor					(drive=1)	nxr2_y
-.br
-
-	\fB=> COMPLEX\fP
-.br
-	   /(AB+CD)				(drive=1)	nmx2_y
-.br
-	   /(A+B)(C+D)				(drive=1)	annup_y
-.br
-	   /((A+B)C)				(drive=1)	noa3_y
-.br
-	   /(AB+C)				(drive=1)	nao3_y
-.br
-	   /(ABC+D)				(drive=1)	nao4_y
-.br
-	   /(A.B.(C+D))				(drive=1)	noue4_y
-.br
-	   /(A.(B+C+D))				(drive=1)	noa4_y
-.br
-
-	\fB=> LATCH\fP
-.br
-	   latch one input (Q,QN)			(drive=1)	lx_y
-.br
-	   latch one input (Q)			(drive=2)	l1_y
-.br
-	   latch one input (QN)			(drive=1)	l1n_y
-.br
-	   latch two inputs (Q)			(drive=2)	l2_y
-.br
-	   latch two inputs (QN)			(drive=1)	l2n_y
-.br
-	   latch three inputs (Q)			(drive=1)	l3_y
-.br
-	   latch two inputs with reset (Q)		(drive=1)	l3r_y
-.br
-	   latch two inputs with set (Q)		(drive=1)	l3s_y
-.br
-	   latch four inputs (Q)			(drive=1)	l4_y
-.br
-	   latch three inputs with reset (Q)		(drive=1)	l4r_y
-.br
-	   latch three inputs with set (Q)		(drive=1)	l4s_y
-.br
-	   latch five inputs (Q)			(drive=1)	l5_y
-.br
-	   latch four inputs with reset (Q)		(drive=1)	l5r_y
-.br
-	   latch four inputs with set (Q)		(drive=1)	l5s_y
-.br
-	   latch five inputs with reset (Q)		(drive=1)	l6r_y
-.br
-	   latch five inputs with set (Q)		(drive=1)	l6s_y
-.br
-
-	\fB=>FF\fP
-.br
-	   master-slave (Q,QN)			(drive=1)	msx_y
-.br
-	   master-slave (Q)			(drive=1)	ms_y
-.br
-	   master-slave (QN)			(drive=1)	msn_y
-.br
-	   master-slave with set (Q,QN)		(drive=1)	mssx_y
-.br
-	   master-slave with reset (Q,QN)		(drive=1)	msrx_y
-.br
-	   scannable master-slave (Q)		(drive=1)	ms2_y
-.br
-	   scannable master-slave(QN)		(drive=1)	ms2n_y
-.br
-	   scannable master-slave (Q,QN)		(drive=1)	ms2x_y
-.br
-	   scannable master-slave with set (Q,QN)	(drive=1)	ms2sx_y
-.br
-	   scannable master-slave with reset (Q,QN)	(drive=1)	ms2rx_y
-.br
-
-	\fB=>BUS\fP
-.br
-	   bus hold (inverted)			(drive=1)	zbli_y
-.br
-	   pull-up						one_y
-.br
-	   pull-down						zero_y
-.br
-	   feed-through						tie_y
-.br
-
-	\fB=>MUX\fP
-.br
-	   mux 2 to 1 (two controls)		(drive=1)	mx2_y
-.br
-	   mux 2 to 1 (two controls)		(drive=2)	mx2p_y
-.br
-	   mux 2 to 1 (one control)			(drive=1)	cmx2_y
-.br
-	   mux 3 to 1 (three controls)		(drive=1)	mx3_y
-.br
-	   mux 4 to 1 (four controls)		(drive=1)	mx4_y
-.br
-
-	\fB=>SPECIAL\fP
-.br
-	   full-adder (sum)			(drive=1)	sum_y
-.br
-	   full-adder (carry)			(drive=1)	cry_y
-.br
-.SH SEE ALSO
-.BR MBK_CATA_LIB (1),
-.BR catal (1),
-.BR scr (1),
-.BR lynx (1),
-.BR bop(1), 
-.BR glop(1), 
-.BR scmap(1), 
-.BR c4map(1), 
-.BR yagle (1),
-.BR genlib (1),
-.BR ap (1),
-.BR al (1),
-.BR vbe (1),
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/spi.5 b/alliance/share/man/man5/spi.5
deleted file mode 100644
index e015b39a..00000000
--- a/alliance/share/man/man5/spi.5
+++ /dev/null
@@ -1,198 +0,0 @@
-.TH SPI 5 "30 March 1999" "ASIM/LIP6" "File Formats"
-
-.SH NAME
-
-spi \- Alliance parser and driver for Spice netlist.
-
-.so man1/alc_origin.1
-
-.SH FILES
-
-The description of a netlist foo must be contained  in a \fB.SUBCKT\fP of a file named \fIfoo.spi\fP. This description can include others \fB.SUBCKT\fP that must be in the same file or files included with the command \fB.INCLUDE\fP in the source file.
-
-Recognized elements are :
-
-.RS
-Resistances
-
-Capacitances
-
-Instances
-
-MOS  transistors.
-
-.RE
-Others elements are not considered.
-
-Nodes can be either numbered or nameed. It's possible to assign a name to a node which is designated by a number with the directive
-
-.B * NET number = name
-
-in the \fB.SUBCKT\fP. The word NET can be replaced by positioning the environment variable \fIMBK_SPI_NETNAME\fP. Names are used to named the signals and the connectors in the \fILOFIG\fP.
-
-On the \fB.SUBCKT\fP interface, nodes of the same name followed by a period and a number are considered to be on the net, even if no connected in the circuit. For example :
-
-.RS
- .SUBCKT nand2 in out out.1 out.2 vss vdd out.3
-.RE
-
-The nodes out, out.1, out.2 and out.3 are considered to be the same signal of the Alliance \fILOFIG\fP. This feature can be turned off if the environment variable \fIMBK_SPI_MERGE\fP is set, and the period can be replaced by another character with the environment variable \fIMBK_SPI_SEPAR\fP.
-
-No particular information is needed to build a \fILOFIG\fP from a \fB.SUBCKT\fP, the parser rebuild all signals, even they contains many resistances and capacitances. If names are not provided, the parser will create then in order to provide a valid lofig.
-
-.SH DRIVER
-
-The driver creates a Spice netlist of the \fILOFIG\fP passed as a parameter.  The file contain a single \fB.SUBCKT\fP representing the figure and commands \fB.INCLUDE\fP with name of instances contained in the \fILOFIG\fP.  Nodes are number named with the directive \fB* NET\fP, or strings, depending on \fIMBK_SPI_NAMEDNODES\fP. A comment at the beginning of the file represents the interface of the \fILOFIG\fP. This comment is not used by the parser.
-
-Environment variable considered are
-
-.RS
-.B MBK_SPI_MODEL
-
-.B MBK_SPI_NETNAME
-
-.B MBK_SPI_NAMEDNODES
-.RE
-
-.SH PARSER
-
-The parser load all \fB.SUBCKT\fP in memory, even those in files included with the command \fB.INCLUDE\fP until the required \fILOFIG\fP is loaded. For each \fB.SUBCKT\fP loaded, the parser build the equipotentials with both nodes of resistances on the same net and both nodes of capacitances on differents net unless more information is given. The RCN library is used to handle resistances and capacitances.
-
-As the \fILOWIRE\fP can contain a resistance and a capacitance, the parser groups a resistance and two capacitances in a single \fILOWIRE\fP if the following conditions are met :
-
-.RS
-The resistance is named 'name' and the two capacitances are named 'name1' and 'name2'
-
-The two capacitances must have the same value
-
-The two capacitances must be between the net of the resistance and VSS.
-
-.RE
-The driver supports this feature.
-
-Environment variable considered are
-
-.RS
-.B MBK_SPI_MODEL
-
-.B MBK_SPI_NETNAME
-
-.B MBK_SPI_SEPAR
-
-.B MBK_SPI_MERGE
-
-.B MBK_SPI_FILE
-
-.B MBK_SPI_VERBOSE
-
-.B MBK_SPI_ONE_NODE_NORC
-
-.B MBK_SPI_NO_AFF_UNK
-.RE
-
-.SH ENVIRONMENT VARIABLES
-
-.B MBK_SPI_MODEL
-
-File name where transistors models are described. Syntax for file is :
-.RS
-MODELNAME N|P [FAST] [HVIO]
-.RE
-Blank lines are allowed, and line comment begin with a '#'.
-
-.B MBK_SPI_NETNAME
-
-Comment used to name the nodes. Default is
-.I NET.
-
-.B MBK_SPI_SEPAR
-
-Character used to separate a name from a node number on the interface of the \fB.SUBCKT\fP. The parser considers nodes of the same name to be on the same equipotential. Default is '\fB.\fP'.
-
-.B MBK_SPI_NOMERGE
-
-If this variable is set, the parser does not merge interface nodes of the same name, but different number, on the same equipotential.
-
-.B MBK_SPI_FILE
-
-If this variable is set, the name of the files opened are displayed on the error output.
-
-.B MBK_SPI_VERBOSE
-
-If this variable is set, display debug various information on the error output.
-
-.B MBK_SPI_ONE_NODE_NORC
-
-If this variable is set, an RCN view is not created for a net containing only one node.
-
-.B MBK_SPI_NO_AFF_UNK
-
-Default behaviour of Spice parser is to display an error message when an unknown element is read in the input file. Setting this variable prevent this display. Usefull when file contain command for Spice simulator.
-
-.B MBK_SPI_NAMEDNODES
-
-When this environment variable is set, spice netlist's nodes are named using one of the following convention, if signal name is set or no, or if signal has an RCN view :
-
-.RS
-"SIGNAL NAME" $MBK_SEPAR "RCN NODE"
-
-"SIGNAL NAME"
-
-SIG "SIGNAL INDEX" $MBK_SEPAR "RCN NODE"
-
-SIG "SIGNAL INDEX"
-.RE
-
-$MBK_SEPAR is a single character defined by a environment variable with the same name.
-
-.SH EXAMPLE
-
-This is an example of a file generated by the Spice driver.
-
-.nf
-
- * Spice description of gxor
- * Spice driver version 700
- * Date ( dd/mm/yyyy hh:mm:ss ): 29/03/1999 at 17:43:53
-
- * INTERF a b s vdd vdd vdd vdd vss vss vss vss 
-
- .INCLUDE mx2_y.spi
- .INCLUDE ndrvp_y.spi
-
- .subckt gxor 24 42 49 52 53 61 54 63 64 71 72 
- * NET 1 = implicit 
- * NET 4 = auxsc1 
- * NET 13 = auxsc3 
- * NET 26 = a 
- * NET 40 = b 
- * NET 49 = s 
- * NET 52 = vdd 
- * NET 65 = vss 
- xauxsc1 64 65 53 55 33 35 2 8 ndrvp_y
- xs 66 70 56 60 48 50 11 21 5 9 34 36 38 45 mx2_y
- xauxsc3 70 71 60 61 41 46 18 22 ndrvp_y
- R2_1 4 7 6
- C2_11 4 63 6.9e-15
- C2_12 7 63 6.9e-15
- R2_2 3 2 0.15
- C2_21 3 63 7.2e-16
-
-.B [----- CUT -----]
-
- C4_51 69 63 6.525e-15
- C4_52 72 63 6.525e-15
- R4_6 68 69 0.001
- R4_7 68 67 0.001
- .ends gxor
-
-.SH SEE ALSO
-
-.B Alliance(1) MBK(1) Al(1) RCN(1) MBK_SEPAR(1)
-
-.SH AUTHOR
-
-Gregoire AVOT.
-.I Gregoire.AVOT@lip6.fr
-
-.so man1/alc_bug_report.1
diff --git a/alliance/share/man/man5/sum_dp.5 b/alliance/share/man/man5/sum_dp.5
deleted file mode 100644
index 8cc36745..00000000
--- a/alliance/share/man/man5/sum_dp.5
+++ /dev/null
@@ -1,84 +0,0 @@
-.\"   $Id: sum_dp.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.TH SUM_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBsum_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "sum_dp", "insname", "pi", "ci", "si", "c0b", "f", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  sum_dp  IS
-  PORT(
-         pi : in        BIT;
-         ci : in        BIT;
-         si : in        BIT;
-        c0b : in        BIT;
-          f :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  sum_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  sum_dp  IS
-
-BEGIN
-  -- Logical equations.
-  f     <= not (((si and pi) and ci) or (c0b and ((si or pi) or ci)));
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 48 lambdas, or 8 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-c0b	:	cin	=	54	(fF)
-.br
-		tplh	=	940	(ps) +	4837	(ohms) x Cload (pF)
-.br
-		tphl	=	452	(ps) +	2702	(ohms) x Cload (pF)
-.br
-
-si	:	cin	=	101	(fF)
-.br
-		tplh	=	1946	(ps) +	6829	(ohms) x Cload (pF)
-.br
-		tphl	=	1052	(ps) +	3588	(ohms) x Cload (pF)
-.br
-
-ci	:	cin	=	99	(fF)
-.br
-		tplh	=	2381	(ps) +	6829	(ohms) x Cload (pF)
-.br
-		tphl	=	1271	(ps) +	3588	(ohms) x Cload (pF)
-.br
-
-pi	:	cin	=	104	(fF)
-.br
-		tplh	=	2242	(ps) +	6829	(ohms) x Cload (pF)
-.br
-		tphl	=	1180	(ps) +	3588	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/sum_y.5 b/alliance/share/man/man5/sum_y.5
deleted file mode 100644
index 42c5f8a6..00000000
--- a/alliance/share/man/man5/sum_y.5
+++ /dev/null
@@ -1,45 +0,0 @@
-.\"   $Id: sum_y.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.pl -.4
-.TH SUM_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B sum_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("sum_y","name","pi","ci","si","c0b","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity sum_y is
-     port(
-        pi : in bit;
-        ci : in bit;
-        si : in bit;
-        c0b : in bit;
-        f : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    f <= not (((si and pi) and ci) or (c0b and ((si or pi) or ci)));
-   
-.br
-.I - Physical features
-   number of grids : 8
-   number of feed-through : 3
-.br
-   
-.I - Timing caracteristics
-.br
-   pi : 102 (fF)
-.br
-   ci : 99 (fF)
-.br
-   si : 96 (fF)
-.br
-   c0b : 52 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/sxlib.5 b/alliance/share/man/man5/sxlib.5
deleted file mode 100644
index f6e91453..00000000
--- a/alliance/share/man/man5/sxlib.5
+++ /dev/null
@@ -1,412 +0,0 @@
-.\" $Id: sxlib.5,v 1.7 1999/10/21 11:45:10 franck Exp $
-.\" @(#)Labo.l 0.0 92/09/24 UPMC; Author: Franck Wajsburt
-.TH SXLIB 5 "October 19, 1999" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
-.SH NAME
-.B sxlib - a portable CMOS Standard Cell Library
-.so man1/alc_origin.1
-
-.SH DESCRIPTION
-
-\fBsxlib\fP library contains standard cells that have been developed at
-UPMC-ASIM/LIP6. This manual gives the list of available cells, with their
-behavior, width, maximum delay and input fan-in. This manual gives also
-few thumb rules to help the user to well use the cells. The given delay
-are the maximum (that means worst case for a generic .35 micron process).
-More precise delay can be found in ALLIANCE VHDL behavior files (.vbe file).
-Cell-name is built that way <behavior>_<output drive>
-(see explanations below).
-
-.nf
-Four files are attached to each cell:-
-- ALLIANCE Layout ............... cell-name.ap
-- ALLIANCE Transistor net-list .. cell-name.al
-- ALLIANCE VHDL behavior ........ cell-name.vbe
-- Compiled HILO behavior ........ 0000000xx.dat
-
-And few files more:-
-- CATAL ......................... ALLIANCE catalog file
-- sxlib.cct ..................... Cell definition for HILO CAD tools
-- CIRCUIT.idx ................... HILO catalog file
-- sxlib.lib ..................... Cell definition for Synopsys CAD tools
-- sxlib.db ...................... Compiled cell definition for Synopsys
-- sxlib.sdb ..................... Icon definition for Synopys
-
-.fi
-
-.SH PHYSICAL OUTLINE
-
-\fBsxlib\fP uses the symbolic layout promoted by Alliance in order to
-provide process independence. All dimensions are in lambda units. The
-mapping to a specific process CIF or GDS2 layout must be performed by the
-\fBs2r\fP tool (symbolic to real), which uses a value for the lambda
-(e.g. 1 lambda=0.3um).
-.nf
-
-       _________________
-   50 |       VDD       |
-   45 |_________________|     x : place of virtual connector.
-   40 |           x     |
-   35 |        x  x     |         they are named : name_<y>
-   30 |  x     x        |
-   25 |  x     x        |         for example : i0_20
-   20 |  x              |                       i0_25
-   15 |           x     |                       i0_30
-   10 |_________________|
-    5 |       VSS       |
-    0 |_________________|
-      0  5 10 15 20 25 30
-
-.fi
-All cells are 50 lambdas high and \fBN\fP times 5 lambdas wide, where
-\fBN\fP is the number of pitches. That is the only physical information
-given in the cell list below.  Power supplies are in horizontal ALU1 and
-are 6 lambdas wide.  Connectors are inside the cells, placed on a 5x5 grid.
-Half layout design rules are a warranty for any layer on any face, except
-for the power supply and NWELL.  Cells can be abutted in all directions
-whenever the supply is well connected and connectors are always placed on
-the 5x5 grid.
-
-.SH DELAY MODEL
-
-Cells have been extracted and simulated by using a generic 0.35um process
-in order to give realistic values for the delays and capacitances.  We
-chose to give only the worst delay for each output signal, though it is not
-very realistic (since delay depends on each input, an input can be easily
-up to twice faster than another). However, we just wanted to give an idea
-of the relative delay.
-
-Furthermore, we added 0.6ns to each output delay in order to take into
-account the delay due to the signal commutation. We have supposed the
-output drives the maximum capacitance. This capacitance have been computed
-as follow. We considered that a good slope signal for this process was
-0.8ns.  Then we searched for the capacitance required to obtain the same
-input and output slope (0.8ns) for the smaller inverter (inv_x1). That was
-125fF. We simulated the same inverter without output capacitance. The delay
-difference was about 0.6ns. This result is not exactly the same for all
-cells, but 0.6ns is a good approximation.
-
-The given delay is then a worst case (70degree, 2.7Volt, slow process,
-worst input), an idea of the typical delay can be obtain by dividing worst
-delay by 1.5, and best delay by dividing by 2.  More detailed data can be
-found in GENERIC data included in the VHDL files (.vbe). Examples can be
-found at the end of this manual.
-
-At last, to get a very better idea about the real delay without simulating
-the spice transistor netlist, it is required to use the TAS (1) tool, which
-is a timing static analyzer able to give the longer and the shorter path for
-a given process.
-
-.SH OUTPUT DRIVE
-
-The output drive of a cell gives an information on the faculty for the cell
-to drive a big capacitance. This faculty depends on the rising and falling
-output resistance. The smaller the resistance, the bigger can be the
-capacitance.  Minimum drive is \fBx1\fP. This corresponds to the smallest
-available inverter (inv_x1). \fBx2\fP means the cell is equivalent (from
-the driving point of view) at two smaller inverters in parallel, and so
-on.
-
-The maximum output drive is \fBx8\fP. It is limited because of the maximum
-output slope and the maximum authorized instantaneous current. If it was
-bigger the output slope could be very tight and the current too big.
-
-With the 0.35um process, an \fBx1\fP is able to drive about \fB125fF\fP,
-\fBx2\fP -> \fB250fF\fP, \fBx4\fP -> \fB500fF\fP,\fBx8\fP -> \fB1000fF\fP.
-This is just an indication since if a cell is overloaded, the only
-consequence is to increase the propagation time. On the other hand, it is
-not very good to under-load a cell because this leads to a signal overshoot.
-Actually, for big gate, such as noa3ao322_x1, \fBx1\fP means maximal
-driving strength reachable with a single logic layer, that can be much
-less than an inv_x1. That is why is the cell list below contains more precise
-drive strengh. As you can see noa3ao322_x1 as a output drive strengh of 0.6,
-that means 0.6 time an inverter, so say it can drive about 0.6*125fF=75fF.
-
-With the 0.35um process, a \fB1\fP lambda interconnect wire is about
-\fB0.15fF\fP, an average cell fan-in is 10fF. Then, if it needs about 50
-lambdas to connect 2 cells, an \fBx1\fP cell is able to drive about 7
-cells (125/(10+50*.15)=7). With 100 lambdas, 5 cells, with 750 lambdas
-only 2 cells. Note that 50 lambdas means cells are very close one from
-each other, nearly abutted, 100 lambdas is an average value.
-
-All this are indications.  Only a timing analysis on the extracted
-transistor net-list from layout can tell if a cell is well used or not
-(see tas(1) for informations about static timing analysis).
-
-.SH BEHAVIOR
-
-For most of cells, the user can deduce the cell behavior just by reading its
-name.  That is very intuitive for \fBinv\fPerter and more complex for and/or
-cells.  For the last, the name gives the and/or tree structure.  The input
-order for the VHDL interface component is always the alphabetic order.
-
-.nf
-\fBinv\fP           : \fBinv\fPersor buffer
-\fBbuf\fP           : \fBbuf\fPfer
-[\fBn\fP]\fBts\fP         : [\fBn\fPot] \fBt\fPree-\fBs\fPtate
-[\fBn\fP]\fBxr\fP<i>      : [\fBn\fPot] \fBx\fPo\fBr\fP <i> inputs
-[\fBn\fP]\fBmx\fP<i>      : [\fBn\fPot] \fBm\fPultiple\fBx\fPor <i> inputs with coded command
-[\fBn\fP][\fBsd\fP]\fBff\fP<i>  : [\fBn\fPot] [\fBs\fPtatic|\fBd\fPynamic] \fBf\fPlip-\fBf\fPlop <i> inputs
-[\fBn\fP]\fBoa\fP...      : [\fBn\fPot] \fBa\fPnd/\fBo\fPr function (see below)
-
-\fBand_or cell (YACC (1) grammar):-\fP
-
-NAME     : \fBn\fP OA_CELL                 -> not OA_CELL
-         | OA_CELL                   -> OA_CELL
-
-OA_CELL  : OPERATOR INPUTS           -> function with INPUTS inputs
-         | OPERATOR OA_CELLS INPUTS  -> function with INPUTS inputs
-                                        where some inputs are OA_CELL
-
-OPERATOR : \fBa\fP                         -> and
-         | \fBo\fP                         -> or
-         | \fBn\fP                         -> not
-
-OA_CELLS : OA_CELLS OA_CELL          -> list of OA_CELL
-         | OA_CELL                   -> last OA_CELL of the list
-
-INPUTS   : \fBinteger\fP                   -> number of inputs
-
-The input names are implicit and formed that way \fBi<number>\fP.
-They are attributed in order beginning by \fBi0\fP.
-
-\fBnx\fP where x is a number means there are x inverters in parallel. For
-example an23 is an \fBand\fP with 3 inputs of which two are inverted, that
-is \fBand( not(i0), not(i1), i2)\fP.
-
-\fBExamples:-\fP (some are not in sxlib)
-
-na2       : not( and(i0,i1))
-on12      : or( not(i0), i1)
-noa2a22   : not( or( and(i0,i1), and(i2,i3)))
-noa23     : not( or( and(i0,i1), i3))
-noao22a34 : not( or( and( or(i0,i1), i2), and(i3,i4,i5), i6, i7))
-
-Note that xr2 could not be expressed with an and/or formulea even if
-.br
-xr2 = or( and( not(i0), i1), and( not(i1), i0)) = oan12an122
-.br
-but the input names are not well distributed.
-.fi
-
-.SH CELL LIST
-
-All available cells are listed below. The first column is the pitch width.
-The pitch value is 5 lambdas. The height is 50. Area is then <number>*5*50.
-
-The second column is the output drive strenght compared with the \fBinv_x1\fP
-output drive strenght (see explanation above in section OUTPUT DRIVE).
-
-The following column is the delay in nano-seconds.
-Remember this delay corresponds to the slower
-input+0.6ns (see explanation above in section DELAY MODEL).
-
-The last column gives the function behavior with input capacitance.
-\fB/\fP means \fBnot\fP, \fB+\fP means \fBor\fP, \fB.\fP
-means \fBand\fP, \fB^\fP means \fBxor\fP.
-Each input is followed by fan-in capacitance in fF,
-(e.g. i0<11> means i0 pin capacitance is 11fF).
-
-For some cells, such as
-\fBfulladder\fP, it was not possible to internally connect all inputs.
-That means there are several inputs that \fBmust be externally connected\fP.
-In the following list, these inputs are followed by a star (*) character in
-the equation.
-
-For example, fulladder equation is sout <= (a* . b* . cin*).
-a* replaces a0, a1, a2, a3 that must be explicitly connected by the user.
-Note also few cells have more than one output. In that case there are
-several lines in the list, one by output.
-.nf
-\fB=================================================================\fP
-\fBWIDTH NAME  DRIVE DELAY BEHAVIOR with cin\fP
-\fB-------------------------------------------------------- INVERSOR\fP
- 3 inv_x1       1.0 0.7  nq <= /i<8>
- 3 inv_x2       1.6 0.7  nq <= /i<12>
- 4 inv_x4       3.6 0.7  nq <= /i<26>
- 7 inv_x8       8.4 0.7  nq <= /i<54>
-\fB---------------------------------------------------------- BUFFER\fP
- 4 buf_x2       2.1 1.0   q <=  i<6>
- 5 buf_x4       4.3 1.0   q <=  i<9>
- 8 buf_x8       8.4 1.0   q <=  i<15>
-\fB------------------------------------------------------ THREE STATE\fP
- 6 nts_x1       1.2 0.8  IF (cmd<14>) nq <= /i<14>
- 8 nts_x2       2.4 0.9  IF (cmd<18>) nq <= /i<28>
-10 ts_x4        4.3 1.1  IF (cmd<19>)  q <= i<8>
-13 ts_x8        8.4 1.2  IF (cmd<19>)  q <= i<8>
-\fB-------------------------------------------------------------- AND\fP
- 4 na2_x1       1.0 0.9  nq <= /(i0<11>.i1<11>)
- 7 na2_x4       4.3 1.2  nq <= /(i0<10>.i1<10>)
- 5 na3_x1       0.9 1.0  nq <= /(i0<11>.i1<11>.i2<11>)
- 8 na3_x4       4.3 1.3  nq <= /(i0<10>.i1<10>.i2<10>)
- 6 na4_x1       0.7 1.0  nq <= /(i0<10>.i1<11>.i2<11>.i3<11>)
-10 na4_x4       4.3 1.4  nq <= /(i0<10>.i1<11>.i2<11>.i3<11>)
- 5 a2_x2        2.1 1.0   q <=  (i0<9>.i1<11>)
- 6 a2_x4        4.3 1.1   q <=  (i0<9>.i1<11>)
- 6 a3_x2        2.1 1.1   q <=  (i0<10>.i1<10>.i2<10>)
- 7 a3_x4        4.3 1.2   q <=  (i0<10>.i1<10>.i2<10>)
- 7 a4_x2        2.1 1.2   q <=  (i0<10>.i1<10>.i2<10>.i3<10>)
- 8 a4_x4        4.3 1.3   q <=  (i0<10>.i1<10>.i2<10>.i3<10>)
- 5 an12_x1      1.0 1.0   q <=  (/i0<12>).i1<9>
- 8 an12_x4      4.3 1.1   q <=  (/i0<9>).i1<11>
-\fB--------------------------------------------------------------- OR\fP
- 4 no2_x1       1.0 0.9  nq <= /(i0<12>+i1<12>)
- 8 no2_x4       4.3 1.2  nq <= /(i0<12>+i1<11>)
- 5 no3_x1       0.8 1.0  nq <= /(i0<12>+i1<12>+i2<12>)
- 8 no3_x4       4.3 1.3  nq <= /(i0<12>+i1<12>+i2<11>)
- 6 no4_x1       0.6 1.1  nq <= /(i0<12>+i1<12>+i2<12>+i3<12>)
-10 no4_x4       4.3 1.4  nq <= /(i0<12>+i1<12>+i2<12>+i3<12>)
- 5 o2_x2        2.1 1.0   q <=  (i0<10>+i1<10>)
- 6 o2_x4        4.3 1.1   q <=  (i0<10>+i1<10>)
- 6 o3_x2        2.1 1.1   q <=  (i0<10>+i1<10>+i2<9>)
-10 o3_x4        4.3 1.2   q <=  (i0<10>+i1<10>+i2<9>)
- 7 o4_x2        2.1 1.2   q <=  (i0<10>+i1<10>+i2<10>+i3<9>)
- 8 o4_x4        4.3 1.3   q <=  (i0<12>+i1<12>+i2<12>+i3<12>)
- 5 on12_x1      1.0 0.9   q <=  (/i0<11>)+i1<9>
- 8 on12_x4      4.3 1.1   q <=  (/i0<9>)+i1<10>
-\fB--------------------------------------------------------- AND/OR 3\fP
- 6 nao22_x1     1.2 0.9  nq <= /((i0<14>+i1<14>).i2<14>)
-10 nao22_x4     4.3 1.3  nq <= /((i0<8> +i1<8>) .i2<9>)
- 6 noa22_x1     1.2 0.9  nq <= /((i0<14>.i1<14>)+i2<14>)
-10 noa22_x4     4.3 1.3  nq <= /((i0<8> .i1<8>) +i2<9>)
- 6 ao22_x2      2.1 1.2   q <=  ((i0<8>+i1<8>).i2<9>)
- 8 ao22_x4      4.3 1.3   q <=  ((i0<8>+i1<8>).i2<9>)
- 6 oa22_x2      2.1 1.2   q <=  ((i0<8>.i1<8>)+i2<9>)
- 8 oa22_x4      4.3 1.3   q <=  ((i0<8>.i1<8>)+i2<9>)
-\fB--------------------------------------------------------- AND/OR 4\fP
- 7 nao2o22_x1   1.2 1.0  nq <= /((i0<14>+i1<14>).(i2<14>+i3<14>))
-11 nao2o22_x4   4.3 1.4  nq <= /((i0<8> +i1<8>) .(i2<8> +i3<8>))
- 7 noa2a22_x1   1.2 1.0  nq <= /((i0<14>.i1<14>)+(i2<14>.i3<14>))
-11 noa2a22_x4   4.3 1.4  nq <= /((i0<8> .i1<8>) +(i2<8> .i3<8>))
- 9 ao2o22_x2    2.1 1.2   q <=  ((i0<8>+i1<8>).(i2<8>+i3<8>))
-10 ao2o22_x4    4.3 1.3   q <=  ((i0<8>+i1<8>).(i2<8>+i3<8>))
- 9 oa2a22_x2    2.1 1.2   q <=  ((i0<8>.i1<8>)+(i2<8>.i3<8>))
-10 oa2a22_x4    4.3 1.4   q <=  ((i0<8>.i1<8>)+(i2<8>.i3<8>))
-\fB--------------------------------------------------------- AND/OR 5\fP
- 7 noa2ao222_x1 0.7 1.1 nq <= /((i0<11>.i1<11>)+((i2<13>+i3<13>).i4<13>))
-11 noa2ao222_x4 4.3 1.4 nq <= /((i0<11>.i1<11>)+((i2<11>+i3<11>).i4<11>))
-10 oa2ao222_x2  2.1 1.2  q <=  ((i0<8> .i1<8>) +((i2<8> +i3<8>) .i4<8>))
-11 oa2ao222_x4  4.3 1.3  q <=  ((i0<8> .i1<8>) +((i2<8> +i3<8>) .i4<8>))
-\fB--------------------------------------------------------- AND/OR 6\fP
-10 noa2a2a23_x1 0.8 1.2 nq <= /((i0<13>.i1<14>) +(i2<14>.i3<14>)
-                               +(i4<14>.i5<14>))
-13 noa2a2a23_x4 4.3 1.3 nq <= /((i0<13>.i1<14>) +(i2<14>.i3<14>)
-                               +(i4<14>.i5<14>))
-12 oa2a2a23_x2  2.1 1.4  q <=  ((i0<13>.i1<14>) +(i2<14>.i3<14>)
-                               +(i4<14>.i5<14>))
-13 oa2a2a23_x4  4.3 1.4  q <=  ((i0<13>.i1<14>) +(i2<14>.i3<14>)
-                               +(i4<14>.i5<14>))
-\fB--------------------------------------------------------- AND/OR 7\fP
- 9 noa3ao322_x1 0.6 1.2 nq <= /((i0<13>.i1<13>.i2<12>)
-                               +((i3<13>+i4<13>+i5<13>).i6<13>))
-11 noa3ao322_x4 4.3 1.4 nq <= /((i0<10>.i1<9>.i2<9>)
-                               +((i3<9>+i4<9>+i5<9>).i6<9>))
-10 oa3ao322_x2  2.1 1.2  q <= /((i0<10>.i1<9>.i2<9>)
-                               +((i3<9>+i4<9>+i5<9>).i6<9>))
-11 oa3ao322_x4  4.3 1.3  q <= /((i0<10>.i1<9>.i2<9>)
-                               +((i3<9>+i4<9>+i5<9>).i6<9>))
-\fB--------------------------------------------------------- AND/OR 8\fP
-14 noa2a2a2a24_x1 0.6 1.4 nq <= /((i0<14>.i1<14>)+(i2<13>.i3<13>)
-                                 +(i4<13>.i5<13>)+(i6<14>.i7<14>))
-17 noa2a2a2a24_x4 4.3 1.7 nq <= /((i0<14>.i1<14>)+(i2<14>.i3<13>)
-                                 +(i4<13>.i5<13>)+(i6<14>.i7<14>))
-15 oa2a2a2a24_x2  2.1 1.5  q <=  ((i0<14>.i1<14>)+(i2<14>.i3<13>)
-                                 +(i4<13>.i5<13>)+(i6<14>.i7<14>))
-16 oa2a2a2a24_x4  4.3 1.6  q <=  ((i0<14>.i1<14>)+(i2<14>.i3<13>)
-                                 +(i4<13>.i5<13>)+(i6<14>.i7<14>))
-\fB------------------------------------------------------ MULTIPLEXER\fP
- 7 nmx2_x1      1.2 1.0  nq <= /((i0<14>./cmd<21>)+(i1<14>.cmd))
-12 nmx2_x4      4.3 1.3  nq <= /((i0<8>./cmd<14>)+(i1<9>.cmd))
- 9 mx2_x2       2.1 1.1   q <=   (i0<8>./cmd<17>)+(i1<9>.cmd)
-10 mx2_x4       4.3 1.3   q <=   (i0<8>./cmd<17>)+(i1<9>.cmd)
-12 nmx3_x1      0.4 1.2  nq <= /((i0<9>./cmd0<15>)
-                                +(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0))
-15 nmx3_x4      4.3 1.7  nq <= /((i0<9>./cmd0<15>)
-                                +(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0))
-13 mx3_x2       2.1 1.4   q <=  ((i0<9>./cmd0<15>)
-                                +(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0))
-14 mx3_x4       4.3 1.6   q <=  ((i0<9>./cmd0<15>)
-                                +(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0))
-\fB-------------------------------------------------------------- XOR\fP
- 9 nxr2_x1      1.2 1.1  nq <= /(i0<21>^i1<22>)
-11 nxr2_x4      4.3 1.2  nq <= /(i0<20>^i1<21>)
- 9 xr2_x1       1.2 1.0   q <=  (i0<21>^i1<22>)
-12 xr2_x4       4.3 1.2   q <=  (i0<20>^i1<21>)
-\fB-------------------------------------------------------- FLIP-FLOP\fP
-."25 nsdff2_x4  4.3 1.0  IF RISE(ck<23>)
-                            nq <=/((i0<11>./cmd<13>)+(i1<7>.cmd))
-18 sff1_x4      4.3 1.7  IF RISE(ck<8>)
-                             q <= i<8>
-24 sff2_x4      4.3 1.9  IF RISE(ck<8>)
-                             q <= ((i0<8>./cmd<16>)+(i1<7>.cmd))
-28 sff3_x4      4.3 2.4  IF RISE(ck<8>)
-                             q <= (i0<9>./cmd0<15>)
-                                 +(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0)
-\fB------------------------------------------------------------ ADDER\fP
-16 halfadder_x2 2.1 1.2 sout <= (a<27>^b<22>)
-                2.1 1.0 cout <= (a.b)
-18 halfadder_x4 4.3 1.3 sout <= (a<27>^b<22>)
-                4.3 1.1 cout <= (a.b)
-20 fulladder_x2 2.1 1.8 sout <= (a*<28>^b*<28>^cin*<19>)
-                2.1 1.4 cout <= (a*.b*+a*.cin*+b*.cin*)
-21 fulladder_x4 4.3 2.2 sout <= (a*<28>^b*<28>^cin*<19>)
-                4.3 1.5 cout <= (a*.b*+a*.cin*+b*.cin*)
-\fB---------------------------------------------------------- SPECIAL\fP
- 3 zero_x0       0   0  nq <= '0'
- 3 one_x0        0   0   q <= '1'
- 2 tie_x0        0   0  Body tie cell
- 1 rowend_x0     0   0  Empty cell
-\fB==================================================================\fP
-.fi
-
-.SH NEW CELLS
-
-It is possible to add new cells in the library just by providing the 3
-files .ap, .al and .vbe in the standard cell directory.  The layout view
-can be created with the symbolic editor graal.  The physical outline is
-given above.  The net-list view can be automatically generated with the
-lynx extractor.  The behavioral view must be written by the designer and
-checked with the yagle functional abstractor.  The file must contain the
-generic fields in order to be used by the logic synthesis tools and the
-I/Os terminals must be in the same order (alphabetic) in the .vbe and .al
-files.
-
-If you develop new cells, please send the corresponding files
-to alliance\-support@asim.lip6.fr
-
-.SH VHDL FILES
-
-You can find below the commented VHDL GENERIC for the na2_x4 cell.
-.nf
-ENTITY na2_x4 IS
-GENERIC (
-  CONSTANT area          : NATURAL := 1750; -- lamba * lambda
-  CONSTANT transistors   : NATURAL := 10;   -- number of
-  CONSTANT cin_i0        : NATURAL := 10;   -- femto Farad for i0
-  CONSTANT cin_i1        : NATURAL := 10;   -- femto Farad for i1
-  CONSTANT tplh_i1_nq    : NATURAL := 606;  -- propag. time in pico-sec
-                                            -- from i1 falling
-                                            -- to   nq rizing
-  CONSTANT rup_i1_nq     : NATURAL := 890;  -- resitance in Ohms when nq
-                                            -- rizing due to i1 change
-  CONSTANT tphl_i1_nq    : NATURAL := 349;  -- propag time when nq falls
-  CONSTANT rdown_i1_nq   : NATURAL := 800;  -- resist when nq falls
-  CONSTANT tplh_i0_nq    : NATURAL := 557;  -- idem for i0
-  CONSTANT rup_i0_nq     : NATURAL := 890;
-  CONSTANT tphl_i0_nq    : NATURAL := 408;
-  CONSTANT rdown_i0_nq   : NATURAL := 800
-);
-PORT (
-  i0     : in  BIT;
-  i1     : in  BIT;
-  nq     : out BIT;
-  vdd    : in  BIT;
-  vss    : in  BIT
-);
-.fi
-
-.SH SEE ALSO
-
-\fBMBK_CATA_LIB (1), catal(1), scr(1), lynx(1), bop(1), glop(1), scmap(1),
-c4map(1), tas(1), yagle(1), genlib(1), ap(1), al(1), vbe(1)\fP
-
-.so man1/alc_bug_report.1
diff --git a/alliance/share/man/man5/tie_y.5 b/alliance/share/man/man5/tie_y.5
deleted file mode 100644
index e0c4de51..00000000
--- a/alliance/share/man/man5/tie_y.5
+++ /dev/null
@@ -1,31 +0,0 @@
-.\"   $Id: tie_y.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.pl -.4
-.TH TIE_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B tie_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("tie_y","name","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity tie_y is
-     port(
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-   
-.br
-.I - Physical features
-   number of grids : 1
-   number of feed-through : 1
-.br
-   
-.I - Timing caracteristics
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/tpl.5 b/alliance/share/man/man5/tpl.5
deleted file mode 100644
index 53b8dbd0..00000000
--- a/alliance/share/man/man5/tpl.5
+++ /dev/null
@@ -1,108 +0,0 @@
-.\"   $Id: tpl.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.\" @(#)tpl.5 1.0 Oct 05 1994 UPMC; Author: FLORENT O.
-.TH TPL 5 "October 1, 1997" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
-.SH NAME
-.PP
-\fBtpl\fP \- LV500 Template description format. 
-
-.so man1/alc_origin.1
-.SH DESCRIPTION
-.PP
-The TPL format is used by \fBpatest\fP with PAT format to produce a MSA file 
-readable by the LV500 tester.
-It provides two types of informations:
-.RS
-.PP
-\- Timing characteristics of the pattern file.
-.br
-\- Wiring description of the chip.
-.RE 
-
-.SH THE FORMAT
-.SS Timing characteristics
-
-First, \fBclock\fP signal must be declared using a declaration of the form:
-.RS
-
-\fICLOCK\fP input_output_name [\fIformat\fP] ;
-.RE
-
-where \fIformat\fP is either \fIR0\fP (default value) or \fIR1\fP. 
-R0 represents an active HIGH signal, and R1 an active LOW signal.
-There can be severals clock signals.
-
-Then each combination of the "clock" signals in the pattern file must be
-associated with 5 timing indications in nano\-seconds.
-The order in wich this 5 timing indications are described is indicated 
-in a line of the form:
-
-\fIPARAM CYCLE DELAY WIDTH FORCE COMPARE\fP ; 
-
-This line if followed by the timing indications associated to each 
-combination of the "clock" signals :
-
-\fIPHASE\fP "<phase_description>" time1 time2 time3 time4 time5 ;
-
-The signification of each timing indication is :
-
-.TP 10
-\fBCYCLE\fP
-The pattern length.
-.TP 10
-\fBDELAY\fP
-The time when "clock" signals rise (or fall) from the beginning of the pattern.
-.TP 10
-\fBWIDTH\fP
-The length of the high (or low) state of "clock" signals.
-.TP 10
-\fBFORCE\fP
-The time when inputs signals change their values from the beginning of the pattern.
-.TP 10
-\fBCOMPARE\fP
-The time when outputs are checked from the beginning of the pattern.
-
-.SS Wiring description
-
-Each logical connector of the chip must be associated with its physical
-sector and channel on the tester using :
-
-\fIPIN\fP <input_output_name> <sector>.<channel> ;
-
-All the logical connector must be listed here. The list is end whith a
-\fB"end ;"\fP statement.
-
-.SH EXAMPLE
-
-.nf
-
-## My circuit is a latch design, with two clocks
-## active high: the master clock and the slave clock
-CLOCK	ckm		R0;
-CLOCK	cks		R0;
-
-## In my pattern file, I cannot find a combination 
-## of ckm/cks different from the two following one :
-## '10' : loading master latches
-## '01' : loading slave  latches
-PARAM          CYCLE   DELAY   WIDTH  FORCE   COMPARE ;
-PHASE   '10'   200     50      100    10      160     ;
-PHASE   '01'   200     40       50    10      160     ;
-
-## my chip is a 7 pin chip.
-PIN   ckm   0.0 ;
-PIN   cks   0.a ;
-PIN   in1   0.f ;
-PIN   in2   1.1 ;
-PIN   out   0.b ;
-PIN   vdd   3.0 ;
-PIN   vss   0.c ;
-end ;
-.fi
-
-.SH SEE ALSO
-.PP
-patest(1), pat(5)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/ts_dp.5 b/alliance/share/man/man5/ts_dp.5
deleted file mode 100644
index 1670677e..00000000
--- a/alliance/share/man/man5/ts_dp.5
+++ /dev/null
@@ -1,71 +0,0 @@
-.\"   $Id: ts_dp.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.TH TS_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBts_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "ts_dp", "insname", "i", "o", "v", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  ts_dp  IS
-  PORT(
-          i : in        BIT;
-          o :   out MUX_BIT BUS;
-          v : in        BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  ts_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  ts_dp  IS
-
-BEGIN
-  -- Bus affectations.
-  label0 :BLOCK( v = '1' )
-  BEGIN
-    o <= GUARDED i;
-  END BLOCK label0;
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 54 lambdas, or 9 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-v	:	cin	=	99	(fF)
-.br
-		tphl	=	1148	(ps) +	657	(ohms) x Cload (pF)
-.br
-		tphh	=	1145	(ps) +	849	(ohms) x Cload (pF)
-.br
-
-i	:	cin	=	47	(fF)
-.br
-		tphh	=	1281	(ps) +	849	(ohms) x Cload (pF)
-.br
-		tpll	=	1370	(ps) +	657	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/ts_y.5 b/alliance/share/man/man5/ts_y.5
deleted file mode 100644
index cb767b9a..00000000
--- a/alliance/share/man/man5/ts_y.5
+++ /dev/null
@@ -1,47 +0,0 @@
-.\"   $Id: ts_y.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.pl -.4
-.TH TS_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B ts_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("ts_y","name","i","v","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity ts_y is
-     port(
-        i : in bit;
-        v : in bit;
-        t : mux_bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-   label0 : block (v = '1')
-.br
-   begin
-.br
-     t <= guarded i;
-.br
-   end block;
-.br
-   
-   
-.br
-.I - Physical features
-   number of grids : 8
-   number of feed-through : 5
-.br
-   
-.I - Timing caracteristics
-.br
-   i : 52 (fF)
-.br
-   v : 95 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/tsn_dp.5 b/alliance/share/man/man5/tsn_dp.5
deleted file mode 100644
index 55025ea0..00000000
--- a/alliance/share/man/man5/tsn_dp.5
+++ /dev/null
@@ -1,71 +0,0 @@
-.\"   $Id: tsn_dp.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.TH TSN_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBtsn_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "tsn_dp", "insname", "i", "o", "v", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  tsn_dp  IS
-  PORT(
-          i : in        BIT;
-          o :   out MUX_BIT BUS;
-          v : in        BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  tsn_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  tsn_dp  IS
-
-BEGIN
-  -- Bus affectations.
-  label0 :BLOCK( v = '1' )
-  BEGIN
-    o <= GUARDED not i;
-  END BLOCK label0;
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 24 lambdas, or 4 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-v	:	cin	=	66	(fF)
-.br
-		tphl	=	245	(ps) +	1974	(ohms) x Cload (pF)
-.br
-		tphh	=	731	(ps) +	2979	(ohms) x Cload (pF)
-.br
-
-i	:	cin	=	67	(fF)
-.br
-		tplh	=	706	(ps) +	2979	(ohms) x Cload (pF)
-.br
-		tphl	=	442	(ps) +	1974	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/tsn_y.5 b/alliance/share/man/man5/tsn_y.5
deleted file mode 100644
index 26d6aea2..00000000
--- a/alliance/share/man/man5/tsn_y.5
+++ /dev/null
@@ -1,47 +0,0 @@
-.\"   $Id: tsn_y.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.pl -.4
-.TH TSN_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B tsn_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("tsn_y","name","i","v","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity tsn_y is
-     port(
-        i : in bit;
-        v : in bit;
-        f : mux_bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-   label0 : block (v = '1')
-.br
-   begin
-.br
-     f <= guarded not i;
-.br
-   end block;
-.br
-   
-   
-.br
-.I - Physical features
-   number of grids : 4
-   number of feed-through : 1
-.br
-   
-.I - Timing caracteristics
-.br
-   i : 78 (fF)
-.br
-   v : 72 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/tsp_y.5 b/alliance/share/man/man5/tsp_y.5
deleted file mode 100644
index 2592c9bd..00000000
--- a/alliance/share/man/man5/tsp_y.5
+++ /dev/null
@@ -1,47 +0,0 @@
-.\"   $Id: tsp_y.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.pl -.4
-.TH TSP_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B tsp_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("tsp_y","name","i","v","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity tsp_y is
-     port(
-        i : in bit;
-        v : in bit;
-        t : mux_bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-   label0 : block (v = '1')
-.br
-   begin
-.br
-     t <= guarded i;
-.br
-   end block;
-.br
-   
-   
-.br
-.I - Physical features
-   number of grids : 10
-   number of feed-through : 7
-.br
-   
-.I - Timing caracteristics
-.br
-   i : 52 (fF)
-.br
-   v : 95 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/ttv.5 b/alliance/share/man/man5/ttv.5
deleted file mode 100644
index 9da97653..00000000
--- a/alliance/share/man/man5/ttv.5
+++ /dev/null
@@ -1,153 +0,0 @@
-.\" @(#)ttv.5 1.00  Oct 6 1995 UPMC; Marie-Minerve LOUERAT
-.TH TTV 5 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
-
-.SH NAME
-.PP
-\fBttv\fP \- The timing analyzer \fBtas\fP report : 'general perfmodule' format.
-
-.so man1/alc_origin.1
-.SH DESCRIPTION
-.PP
-
-The timing analyzer \fBtas\fP reports its results in
-a file, named 'perfmodule'. There are two kind of  perfmodules:
-the 'intermediate' (or 'detailed")  and the 'general'. The first one has a \fBht\fPv
-extension  and is  obtained if  the \fB-t\fP  option is used. It
-contains gate delays  between two  signals. The second one 
-has the \fBttv\fP  extension and  contains  all critical paths
-between  two  reference  points.  The perfmodule has several
-articles.
-
-
-.TP 20
-\fBTerminals\fP
-Terminals are reported on the \fBX\fP article.
-
-.RS 5
-.PP
-X \fIdirection name capacitance\fP ;
-.RE
-
-.PP
-The 'terminal' direction can be:
-
-.RS 5
-.TP 5 
-\fII\fP
-for an input terminal
-
-.TP 5
-\fIT\fP 
-for a transceiver terminal
-
-.TP 5
-\fIB\fP 
-for a bidirectional terminal
-
-.TP 5
-\fIO\fP
-for an output terminal
-
-.TP 5
-\fIZ\fP
-for a high-impedance terminal
-
-.TP 5
-\fIU\fP 
-for an unknown direction
-.RE
-
-.TP 20
-\fBLatches\fP
-Latches are reported on the \fBL S\fP article.
-
-.RS 5
-.PP
-L S \fIname ( cmd1 cmd2 ... )\fP ;
-.RE
-
-.TP 20
-\fBFlipflop\fP
-Flipflop are reported on the \fBL F\fP article.
-
-.RS 5
-.PP
-L F \fIname ( cmd1 cmd2 ... )\fP ;
-.RE
-
-.PP
-A latch or a flipflop may have several commands. All of them  belong to
-the \fBL S\fP or \fBL F\fP article .
-
-.TP 20
-\fBPrecharged signals\fP
-Precharged signals are reported on the \fBP\fP article.
-
-.RS 5
-.PP
-P \fIname\fP ;
-.RE
-
-.TP 20
-\fBTransitions\fP
-Transitions between signals are reported to the \fBT\fP
-article.
-
-.RS 5
-.PP
-T \fItype begin end ( (control (input_commutation output_commutation
-delay resistance slope)))\fP ;
-.RE
-
-.PP
-Each 'transition' has one of the following type:
-
-.RS 5
-.TP 5
-\fIE\fP 
-if  the path output is a precharged  signal  and
-the transition concerns an evaluation phase.
-
-.TP 5
-\fIP\fP 
-if the path output is a  precharged  signal  and
-the transition concerns an precharged phase.
-
-.TP 5
-\fIX\fP 
-if the output is not a precharged signal.
-.RE
-
-.PP
-Each 'commutation' has one of the following type:
-
-.RS 5
-.TP 5
-\fIU\fP 
-for a rising edge.
-
-.TP 5
-\fID\fP
-for a falling edge.
-
-.TP 5
-\fIZ\fP
-for a  commutation when  the output  is a  
-precharged signal.
-.RE
-
-.PP
-If the end of path is a register, the 'control' field 
-indicates which signal controls the transition.  And  if the end
-of path  is  a  terminal, in  each  transition,  the  output
-resistance  and  the output  slope  will be  reported.  This
-allows a hierarchical analysis. In the other case, only  the
-delay appears in the transition line.
-
-.SH SEE ALSO
-.PP
-     tas(1),dtv(5)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/vasy.5 b/alliance/share/man/man5/vasy.5
deleted file mode 100644
index 2f6ed5e8..00000000
--- a/alliance/share/man/man5/vasy.5
+++ /dev/null
@@ -1,261 +0,0 @@
-.\"   $Id: vasy.5,v 1.4 2000/03/02 17:15:49 syf Exp $
-.\" @(#)VASY.5 1.0 Jan 28 1992 UPMC ; Ludovic Jacomme
-.TH VASY 5 "December 11, 1999" "ASIM/LIP6" "VHDL subset of VASY."
-
-.SH NAME
-.PP
-\fBvasy\fP VHDL RTL subset.
-
-.so man1/alc_origin.1
-.SH DESCRIPTION
-.PP
-This document describes the VHDL subset accepted by VASY for RTL descriptions.
-
-.PP
-\fBCONCURRENT STATEMENTS\fP
-.br
-In an RTL architecture most of the concurrent statements are supported.
-
-.PP
-Allowed concurrent statements are:
-.RS
-block
-.br
-concurrent assertion
-.br
-process
-.br
-concurrent signal assignment
-.br
-component instantiation statement
-.RE
-generate statement
-.RE
-
-.PP
-\fBSEQUENTIAL STATEMENTS\fP
-.br
-Inside a process, all sequential statements including loops, signal assignment,
-variable assignment are supported.
-
-.PP
-\fBTYPE\fP
-.br
-All types usefull for synthesis are accepted (IEEE-1164 and IEEE-1076.3), and
-all types defined in the VHDL Alliance subset (see vbe(5) for more details).
-
-.PP
-\fBOPERATORS\fP
-.br
-All operators usefull  for synthesis are accepted, such as arithmetic, logical and relationnal operators  (IEEE-1164 and IEEE-1076.3), and those defined in the VHDL Alliance subset
-(see vbe(5) for more details).
-
-.PP
-\fBHARDWARE DESCRIPTION EXAMPLES\fP
-.br
-.PP
-A MULTIPLEXER may be described as follow:
-.nf
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-entity mux is
-port(
-  sel,a,b : in std_logic;
-  mux_out : out std_logic );
-end mux;
-
-architecture rtl_1 of mux is
-begin
- process( sel,a,b )
- begin
-   if (sel='1') then mux_out <= a;
-                else mux_out <= b;
-   end if;
- end process;
-end rtl_1;
-
-architecture rtl_2 of mux is
-begin
-  mux_out <= a when sel='1' else b;
-end rtl_2;
-.fi
-
-.PP
-A LATCH may be described as follow:
-.nf
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-entity latch is
-port(
-  en,a : in std_logic;
-  latch_out : out std_logic );
-end latch;
-
-architecture rtl_1 of latch is
-begin
- process( en, a )
- begin
-   if (en='1') then latch_out <= a;
-   end if;
- end process;
-end rtl_1;
-.fi
-
-.PP
-A D-FLIP-FLOP may be described as follow:
-.nf
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-entity d_ff is
-port(
-   ck,a : in std_logic;
-  d_ff_out : out std_logic );
-end d_ff;
-
-architecture rtl_1 of d_ff is
-begin
- process( ck )
- begin
-   if (ck='1') then d_ff_out <= a;
-   end if;
- end process;
-end rtl_1;
-
-architecture rtl_2 of d_ff is
-begin
- process( ck )
- begin
-   if (ck='1' and ck'event)
-   then d_ff_out <= a;
-   end if;
- end process;
-end rtl_2;
-
-architecture rtl_3 of d_ff is
-begin
- process
- begin
-   wait until ck='1';
-   d_ff_out <= a;
- end process;
-end rtl_3;
-.fi
-
-.PP
-A TRISTATE BUFFER may be described as follow:
-.nf
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-entity trs is
-port(
-   en,a : in std_logic;
-   trs_out : out std_logic );
-end trs;
-
-architecture rtl_1 of trs is
-begin
- process( en,a )
- begin
-   if (en='1') then trs_out <= a;
-               else trs_out <= 'Z';
-   end if;
- end process;
-end rtl_1;
-
-architecture rtl_2 of d_ff is
-begin
- trs_out <= a when en='1' else 'Z';
-end rtl_2;
-.fi
-
-.PP
-A RAM may be described as follow:
-.nf
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity ram is
-port( clk,wr : in std_logic;
-      adr : std_logic_vector(1 downto 0);
-      i0  : in std_logic_vector(3 downto 0);
-      o0  : out std_logic_vector(3 downto 0)
-     );
-end ram;
-
-architecture rtl_1 of ram is
-  type my_array is array (0 to 3) of std_logic_vector(3 downto 0);
-  signal s : my_array;
-begin
- process
- begin
-   wait until (clk='0' and clk'event);
-   if (wr='1')
-   then s(to_integer(unsigned(adr))) <= I0;
-   end if;
- end process;
- o0 <= s(to_integer(unsigned(adr)));
-end rtl_1;
-.fi
-
-.PP
-A ROM may be described as follow:
-.nf
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity rom is
-port( adr : in  std_logic_vector(1 downto 0);
-      o0  : out std_logic_vector(3 downto 0)
-    );
-end rom;
-
-architecture rtl_1 of rom is
-  subtype my_word is std_logic_vector(3 downto 0);
-  type my_array is array (0 to 3) of my_word;
-  constant s : my_array := ( "0000", "0001", "0010", "0011" );
-begin
-  o0 <= s(to_integer(unsigned(adr)));
-end rtl_1;
-.fi
-
-.PP
-A PRIORITY DECODER may be described as follow:
-.nf
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity decod is
-port( A : in std_logic_vector(3 downto 0);
-      B : out std_logic_vector(2 downto 0));
-end decod;
-architecture rtl_1 of decod is
-begin
- process( a )
- begin
-   b <= "111";
-   for i in a'range   -- Static For Loop are unrolled !
-   loop
-     exit when a(i)='1';
-     b <= std_logic_vector(to_unsigned(i,3));
-   end loop;
- end process;
-end rtl_1;
-.fi
-
-.SH SEE ALSO
-.PP
-vasy(1), vbe(5), vhdl(5), vst(5), bop(1), glop(1), scmap(1), c4map(1), asimut(1), proof(1), yagle(1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/vbe.5 b/alliance/share/man/man5/vbe.5
deleted file mode 100644
index 44457960..00000000
--- a/alliance/share/man/man5/vbe.5
+++ /dev/null
@@ -1,283 +0,0 @@
-.\"   $Id: vbe.5,v 1.2 1999/09/24 14:12:24 simcity Exp $
-.\" @(#)VBE.5 1.0 Jan 28 1992 UPMC ; VUONG H.N.
-.TH VBE 5 "October 1, 1997" "ASIM/LIP6" "VHDL subset of ASIM/LIP6/CAO-VLSI lab."
-
-.SH NAME
-.PP
-\fBvbe\fP
-.br
-VHDL behavioural subset.
-
-.so man1/alc_origin.1
-.SH DESCRIPTION
-.PP
-This document describes the ALLIANCE VHDL subset for behavioural data
-flow descriptions.
-
-.PP
-\fBCONCURRENT STATEMENTS\fP
-.br
-In a data flow architecture only concurrent statements (except \fIprocess\fP)
-are supported. All sequential statements including loops, signal assignment,
-etc .. are to be banished.
-
-.PP
-Allowed concurrent statements are:
-.RS
-simple signal assignment
-.br
-conditional signal assignment
-.br
-selected signal assignment
-.br
-concurrent assert statement
-.br
-block statement
-.RE
-
-.PP
-\fBBUSES\fP
-.br
-When using concurrent statements, an ordinary signal can be assigned only once.
-The value of the signal must be explicitly defined by the signal assignment
-(for example, in a selected signal assignment the value of the target signal
-is to be defined for \fBevery\fP value that the select expression can take).
-
-.PP
-The above constraint may be felt as a hard restriction when designing
-distributed controled hardware (precharged line, distributed multiplexer,
-etc ...). To hurdle this, VHDL uses a special feature: guarded-resolved signals.
-
-.PP
-A resolved signal is a signal declared with a resolved subtype (see vhdl(5)). 
-A resolved subtype is a type combined with a resolution function. A resolved
-signal can be assigned by multiple signal assignments. Depending on the value
-of each driver, the resolution function determines the effective value of the
-signal.
-
-.PP
-A guarded signal is a resolved signal with drivers that can be disconected.
-A guarded signal must be assigned inside a \fIblock\fP statement through a
-\fIguarded\fP signal assignment.
-
-.PP
-A distributed multiplexer may be described as :
-.nf
-
-signal Distributed_Mux : mux_bit bus;
-
-begin
-
-first_driver_of_mux : block (Sel1 = '1')
-begin
-  Distributed_Mux <= guarded Data1;
-end block;
-
-second_driver_of_mux : block (Sel2 = '1')
-begin
-  Distributed_Mux <= guarded Data2;
-end block;
-
-.fi
-
-.PP
-\fBLATCHES and REGISTERS\fP
-.br
-Sequential elements must be explicitly declared using the type \fIreg_bit\fP
-or \fIreg_vector\fP (and must be of kind \fIregister\fP). A sequential element
-must be assigned inside a \fIblock\fP statement by a \fIguarded\fP signal
-assignment.
-
-.PP
-Rising edge triggered D flip flop :
-.nf
-
-signal Reg : reg_bit register;
-
-begin
-
-flip_flop : block (ck = '1' and not ck'STABLE)
-begin
-  Reg <= guarded Din;
-end block;
-.fi
-
-.PP
-Level sensitive latch:
-.nf
-
-signal Reg : reg_bit register;
-
-begin
-
-latch : block (ck = '1')
-begin
-  Lat <= guarded Din;
-end block;
-.fi
-
-.PP
-In both cases, the guard expression must depend only on one signal if the
-description is to be processed by the logic synthetizer (bop + scmap).
-
-.PP
-The following operators are only supported: \fBnot, and, or, xor, nor, nand,
-&, =, /=\fP
-
-.PP
-They can be applied on all types supported by the subset. Other standard VHDL
-operators (+, -, >, <, ...) have not been implemented in the present release.
-
-.\" .PP
-.\" \fBTIMING\fP
-.\" .br
-.\" A VHDL description can be used for:
-.\" .RS
-.\" a) validation of a specification (behavioural)
-.\" .br
-.\" b) direct synthesis of hardware (behavioural)
-.\" .br
-.\" c) validation of a structural netlist
-.\" .RE
-.\"
-.\" .PP
-.\" Detailed timing information is not available at design time (cases a and b).
-.\" .PP
-.\" For an extracted netlist (case c) the detailed timing analysis is performed
-.\" by a specific tool: the static timing analyser TAS (not delivered in the
-.\" present version of ALLIANCE).
-.\"
-.\" .PP
-.\" Thus, timing specification is not supported by the ALLIANCE VHDL subset.
-.\" Simulation is performed in zero delay mode.
-
-.PP
-\fBTIMING\fP
-.br
-Timing information can be specified in behavioural descriptions using
-\fIafter clauses\fP. However, those delays are currently only used for
-simulation. \fIAfter clauses\fP are supported but not used for synthesis
-and formal proof.
-
-.PP
-\fIAfter clauses\fP in block statements (for guarded signal assignments)
-are not supported for sequential elements (signals of kind register), but
-supported for bus elements (signals of kind bus). This is because the VHDL
-default \fIdisconnection time\fP is null and this can generate
-unexpected behavior for sequential elements.
-
-.PP
-In selected signal assignment, only uniform delays are supported 
-(the same \fIAfter clause\fP in all assignments).
-
-.PP
-\fITransport option\fP is not supported. All delays are inertial delays.
-.PP
-\fBASSERT STATEMENT\fP
-.br
-Only two severity levels are supported in concurrent
-assert statements:
-.TP 15
-\fBwarning\fP
-print a warning message if the assert condition is not satisfied.
-.TP 15
-\fBerror\fP
-print an error message if the assert condition is not satisfied. Then, stop
-the simulation.
-
-.PP
-Assert statements are ignored by the logic synthesis tool.
-
-.PP
-\fBDON'T CARE\fP
-.br
-A special feature has been introduced in order to allow "don't care"
-specification when the logic synthtizer is targeted (\fB Beware : this feature
-is incompatible with the IEEE VHDL standard !!\fP).
-
-.PP
-An output can be assigned to the value 'D' (don't care). This is taken into
-account by the logic synthesis tool in the optimization process. When the value
-of an output is 'D' the logic synthesis tool may turn it into a '1' or a '0'.
-
-.PP
-A 'D' value is understood as a '0' by the logic simulator (asimut).
-
-.PP
-\fBARRAIES\fP
-.br
-Arraies other than bit_vector, reg_vector, mux_vector and wor_vector are not
-supported.
-
-.SH EXAMPLES
-.PP
-Here is the description of an adder with an accumulator register.
-
-.nf
-entity add_accu is
-port (
-  clk      : in  bit;
-  command  : in  bit;
-  data_in  : in  bit_vector (31 downto 0);
-  data_out : out bit_vector (31 downto 0);
-  cry_out  : out bit;
-  vdd      : in  bit;
-  vss      : in  bit
-  );
-end add_accu;
-
-architecture data_flow of add_accu is
-
-signal eff_data  : bit_vector (31 downto 0);		-- effective operande
-signal adder_out : bit_vector (31 downto 0);		-- adder's result
-signal adder_cry : bit_vector (32 downto 0);		-- adder's carry
-signal accum_reg : reg_vector (31 downto 0) register;	-- accumulator
-
-constant initialize : bit := '0';
-constant accumulate : bit := '1';
-
-begin
-
-  -- select the effective operand
-
-  with command select
-  eff_data <= X"0000_0000" when initialize,
-              accum_reg    when accumulate;
-
-  -- compute the result out of the adder
-
-  adder_out               <= eff_data xor data_in xor adder_cry;
-  adder_cry (0)           <= '0';
-  adder_cry (32 downto 1) <= (eff_data and adder_cry (31 downto 0)) or
-                             (data_in  and adder_cry (31 downto 0)) or
-                             (aff_data and data_in                ) ;
-
-  -- write the result into the register on the rising edge of clk
-
-  write : block (clk = '1' and not clk'STABLE)
-  begin
-    accum_reg <= guarded adder_out;
-  end block;
-
-  -- assign outputs
-
-  cry_out  <= adder_cry (32);
-  data_out <= accum_reg     ;
-
-  -- check power supply
-
-  assert (vdd = '1' and vss = '0')
-  report "power sypply is missing"
-  severity ERROR;
-
-end;
-
-.fi
-
-.SH SEE ALSO
-.PP
-vhdl(5), vst(5), bop(1), glop(1), scmap(1), c4map(1), asimut(1), proof(1), yagle(1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/vhdl.5 b/alliance/share/man/man5/vhdl.5
deleted file mode 100644
index 08638c59..00000000
--- a/alliance/share/man/man5/vhdl.5
+++ /dev/null
@@ -1,133 +0,0 @@
-.\"   $Id: vhdl.5,v 1.2 1999/09/24 14:12:25 simcity Exp $
-.\" @(#)vhdl.5 1.0 Jan 28 1993 UPMC ; VUONG H.N.
-.TH VHDL 5 "October 1, 1997" "ASIM/LIP6" "VHDL subset of ASIM/LIP6/CAO-VLSI lab."
-
-.SH NAME
-.PP
-\fBALLIANCE VHDL Subset\fP
-
-.so man1/alc_origin.1
-.SH DESCRIPTION
-.PP
-The ALLIANCE VHDL subset is dedicated to digital synchronous circuits design.
-The same subset is used for:
-.RS
-logic simulation (asimut)
-.br
-logic synthesis (bop, scmap, glop)
-.br
-functionnal abstraction (yagle)
-.br
-formal proof (proof)
-.RE
-
-.PP
-The ALLIANCE VHDL subset is fully compatible with the IEEE VHDL standard Ref.
-1076 (1987). That means that a VHDL description using the ALLIANCE subset can
-be simulated with any full-VHDL commercial compiler-simulator.
-
-.PP
-Here follows the main restrictions of the ALLIANCE subset.
-
-.PP
-The VHDL description of a circuit is made of two seperate parts: the external
-view and the internal view.
-
-.PP
-The external view defines the name of the circuit and its interface. The
-interface of a circuit is a list of ports. Each port is specified by its name,
-its mode, its type, its constraint for an array and, its kind.
-
-.PP
-The mode of a port depends only on the manner the port is used inside the
-circuit (in the internal view of the circuit). If the value of a port is to be
-read in the view of the description, the port must be declared with the mode
-\fIin\fP. If the value of a port is to be written by the internal view, the
-port must be declared with the mode \fIout\fP. If both above conditions are
-satisfied the port must be declared with the mode \fIinout\fP.
-
-.PP
-Only \fIstructural\fP and \fIbehavioural data flow\fP are supported as internal
-view.
-
-.PP
-In order to allow automatic translation from structural VHDL to other netlist
-formats (EDIF, ALLIANCE, COMPASS, ...) it is not possible to mix behavioural
-and structural description. Of course, a circuit, a subcircuit or a cell can
-have two different descriptions:
-.RS
-a structural view may be defined in a file with a .vst extension (see vst(5)).
-.br
-a behavioural data flow description may be defined in a file with a .vbe
-extension (see vbe(5)).
-.RE
-.PP
-A typical VHDL model will be made of a hierarcical structural description (a
-hierarchy of structural files) and, for each leaf cell, a behavioural
-description.
-
-.PP
-In a behavioural description, only concurrent statements (except \fIprocess\fP)
-are supported. Up to now, sequential statements are not allowed by the ALLIANCE
-VHDL compiler.
-
-.\" .PP
-.\" As behavioural descriptions are used for both logic simulation and logic
-.\" synthesis, detailed timing information is not needed. That means, within a
-.\" concurrent statement no delay can be specified (\fIafter\fP is not supported).
-
-.PP
-Timing information can be specified in behavioural descriptions using \fIAfter clauses\fP. However, those delays are currently only used for simulation. \fIAfter clauses\fP are supported but not used for synthesis and formal proof.
-
-.PP
-A predefined set of types has been defined (other user defined types are not
-supported):
-.TP 15
-\fBbit\fP
-the predefined standard bit type ('0' or '1')
-.TP 15
-\fBbit_vector\fP
-array of bit
-.TP 15
-\fBmux_bit\fP
-a resolved subtype of bit using the \fImux\fP resolution function. This
-function checks that only one driver is actually connected to a signal. The
-effective value of the signal is the value of the active driver. If all drivers
-are disconnected, the value of the signal is '1' (pull up). A signal of type
-mux_bit must be declared with the kind \fIbus\fP.
-.TP 15
-\fBmux_vector\fP
-array of mux_bit
-.TP 15
-\fBwor_bit\fP
-a resolved subtype of bit using the \fIwor\fP resolution function. This
-function allows a signal be driven by more than one driver. All active drivers
-have to drive the same value. The effective value of the signal is the value
-of active drivers. If all drivers are disconnected, the value of the signal
-is '1' (pull up). A signal of type wor_bit must be declared with the kind
-\fIbus\fP.
-.TP 15
-\fBwor_vector\fP
-array of wor_bit
-.TP 15
-\fBreg_bit\fP
-a resolved subtype of bit using the \fIreg\fP resolution function. This
-function checks that only one driver is actually connected to a signal. The
-effective value of the signal is the value of the active driver. A signal of
-type reg_bit must be declared with the kind \fIregister\fP (which makes the
-signal keep its previous value when all drivers are disconnected).
-.TP 15
-\fBreg_vector\fP
-array of reg_bit
-
-.PP
-In the next ALLIANCE release the VHDL subset will be largely extended
-(sequential statements, user defined types) .
-
-.SH SEE ALSO
-.PP
-vst(5), vbe(5), asimut(1), bop(1), glop(1), scmap(1), c4map(1),  proof(1), yagle(1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/vst.5 b/alliance/share/man/man5/vst.5
deleted file mode 100644
index 5139fabe..00000000
--- a/alliance/share/man/man5/vst.5
+++ /dev/null
@@ -1,104 +0,0 @@
-.\"   $Id: vst.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.\" @(#)VST.5 1.0 Jan 28 1992 UPMC ; VUONG H.N.
-.TH VST 5 "October 1, 1997" "ASIM/LIP6" "VHDL subset of ASIM/LIP6/CAO-VLSI lab."
-
-.SH NAME
-.PP
-\fBvst\fP
-.br
-VHDL structural subset.
-
-.so man1/alc_origin.1
-.SH DESCRIPTION
-.PP
-This document describes the ALLIANCE VHDL subset for structural descriptions.
-
-.PP
-The declaration part of a structural description includes signal decalarations
-and component declarations.
-
-.PP
-An internal signal can be declared of any type supported by the present VHDL
-subset except reg_bit and reg_vector.
-
-.PP
-A component must be declared with exactly the same port description as in its
-entity specification. This means that local ports are to be declared with the
-same name, type and kind and in the same order.
-
-.PP
-A structural description is a set of component instanciation statements.
-Instances' ports are connected to each other trough signals in a port map
-specification. Both explicit and implicit port map specifications are supported
-by the ALLIANCE VHDL subset.
-
-.PP
-The present version of the VHDL compiler does not allow unconnected ports (the
-\fIopen\fP mode is not supported).
-
-.PP
-Only the concatenation operator (&) can be used in the actual part (effective
-signal conntected to a formal port) of a port map specification.
-
-.SH EXAMPLES
-.PP
-Here is the description of an adder with an accumulator register.
-
-.nf
-entity add_accu is
-port (
-  clk      : in  bit;
-  command  : in  bit;
-  data_in  : in  bit_vector (31 downto 0);
-  data_out : out bit_vector (31 downto 0);
-  cry_out  : out bit;
-  vdd      : in  bit;
-  vss      : in  bit
-  );
-end add_accu;
-
-architecture structural of add_accu is
-
-signal eff_data  : bit_vector (31 downto 0);		-- effective operande
-signal adder_out : bit_vector (31 downto 0);		-- adder's result
-signal accu_out  : bit_vector (31 downto 0);		-- accumulator
-
-component adder 
-port (a   : in  bit_vector (31 downto 0);
-      b   : in  bit_vector (31 downto 0);
-      res : out bit_vector (31 downto 0));
-end component;
-
-component and_32
-port (a   : in  bit_vector (31 downto 0);
-      cmd : in  bit;
-      res : out bit_vector (31 downto 0));
-end component;
-
-component falling_edge_reg
-port (din  : in  bit_vector (31 downto 0);
-      clk  : in  bit;
-      dout : out bit_vector (31 downto 0));
-end component;
-
-begin
-
-  my_adder : adder
-  port map (a => eff_data, b => accu_out, res => adder_out);
-
-  my_mux   : and_32
-  port map (cmd => command, a => accu_out, res => eff_data);
-
-  my_reg   : falling_edge_reg
-  port map (din => adder_out, clk => clk, dout => accu_out);
-
-end;
-.fi
-
-.SH SEE ALSO
-.PP
-vhdl(5), vbe(5), asimut(1)
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/xr2_dp.5 b/alliance/share/man/man5/xr2_dp.5
deleted file mode 100644
index 3491744d..00000000
--- a/alliance/share/man/man5/xr2_dp.5
+++ /dev/null
@@ -1,76 +0,0 @@
-.\"   $Id: xr2_dp.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.TH XR2_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBxr2_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "xr2_dp", "insname", "i0", "i1", "o", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  xr2_dp  IS
-  PORT(
-         i0 : in        BIT;
-         i1 : in        BIT;
-          o :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  xr2_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  xr2_dp  IS
-
-BEGIN
-  -- Logical equations.
-  o     <= not (((not i1 and not i0) or (not i0 and not i1)) or (i1 and i0));
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 48 lambdas, or 8 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-i1	:	cin	=	131	(fF)
-.br
-		tplh	=	757	(ps) +	2979	(ohms) x Cload (pF)
-.br
-		tphl	=	634	(ps) +	2418	(ohms) x Cload (pF)
-.br
-		tphh	=	1269	(ps) +	2979	(ohms) x Cload (pF)
-.br
-		tpll	=	1176	(ps) +	2418	(ohms) x Cload (pF)
-.br
-
-i0	:	cin	=	131	(fF)
-.br
-		tplh	=	861	(ps) +	2979	(ohms) x Cload (pF)
-.br
-		tphl	=	545	(ps) +	2418	(ohms) x Cload (pF)
-.br
-		tphh	=	1059	(ps) +	2979	(ohms) x Cload (pF)
-.br
-		tpll	=	1217	(ps) +	2418	(ohms) x Cload (pF)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/xr2_y.5 b/alliance/share/man/man5/xr2_y.5
deleted file mode 100644
index cdee7569..00000000
--- a/alliance/share/man/man5/xr2_y.5
+++ /dev/null
@@ -1,39 +0,0 @@
-.\"   $Id: xr2_y.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.pl -.4
-.TH XR2_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B xr2_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("xr2_y","name","i0","i1","t","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity xr2_y is
-     port(
-        i0 : in bit;
-        i1 : in bit;
-        t : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    t <= (i0 xor i1);
-   
-.br
-.I - Physical features
-   number of grids : 8
-   number of feed-through : 5
-.br
-   
-.I - Timing caracteristics
-.br
-   i0 : 142 (fF)
-.br
-   i1 : 139 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/zbli_y.5 b/alliance/share/man/man5/zbli_y.5
deleted file mode 100644
index 85a3fcef..00000000
--- a/alliance/share/man/man5/zbli_y.5
+++ /dev/null
@@ -1,38 +0,0 @@
-.\"   $Id: zbli_y.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.pl -.4
-.TH ZBLI_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B zbli_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("zbli_y","name","i","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity zbli_y is
-     port(
-        i : in bit;
-        f : bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    f <= not i;
-   
-.br
-.I - Physical features
-   number of grids : 3
-   number of feed-through : 1
-.br
-   
-.I - Timing caracteristics
-.br
-   i : 54 (fF)
-.br
-   f : 68 (fF)
-.br
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/zero_dp.5 b/alliance/share/man/man5/zero_dp.5
deleted file mode 100644
index 2911d817..00000000
--- a/alliance/share/man/man5/zero_dp.5
+++ /dev/null
@@ -1,57 +0,0 @@
-.\"   $Id: zero_dp.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.TH ZERO_DP 5 "October 1, 1997" "ASIM/LIP6" "FITPATH - User Cell Library"
-.so man1/alc_origin.1
-.SH NAME
-\fBzero_dp\fP
-.SH SYNOPSIS
-.ft CR
-.nf
-\fIGenLib Call :\fP
-    LOINS( "zero_dp", "insname", "o", "vdd", "vss", 0L );
-.fi
-.ft R
-.SH DESCRIPTION
-\fIVHDL Behavioral description :\fP
-.ft CR
-.nf
-
--- Interface declaration.
-ENTITY  zero_dp  IS
-  PORT(
-          o :   out     BIT;
-        vdd : in        BIT;
-        vss : in        BIT
-      );
-END  zero_dp;
-
--- Architecture declaration.
-ARCHITECTURE  behavior_data_flow  OF  zero_dp  IS
-
-BEGIN
-  -- Logical equations.
-  o     <= '0';
-END  behavior_data_flow;
-.fi
-.ft R
-
-\fIPhysical features :\fP
-.br
-.ta +4n
-	Cell wide : 12 lambdas, or 2 pitchs.
-.br
-
-\fITiming characteristics :\fP
-.br
-.ta +6n  +2n  +6n +6nR +1n    +12nR +1n
-
-		rup	=	0	(ohms)
-.br
-		rdown	=	2143	(ohms)
-.br
-.SH SEE ALSO
-.ft B
-dplib(1), fpgen(1), scmap(1)
-.ft R
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/man5/zero_y.5 b/alliance/share/man/man5/zero_y.5
deleted file mode 100644
index 94884540..00000000
--- a/alliance/share/man/man5/zero_y.5
+++ /dev/null
@@ -1,34 +0,0 @@
-.\"   $Id: zero_y.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
-.pl -.4
-.TH ZERO_Y 5 "October 1, 1997" "ASIM/LIP6" "STANDARD-CELL LIBRARY"
-.SH NAME
-.B zero_y
-.so man1/alc_origin.1
-.SH SYNOPSIS
-.B Genlib call :
-.br
-  LOINS("zero_y","name","f","vdd","vss",0);
-.SH DESCRIPTION
-.I - Interface
-   entity zero_y is
-     port(
-        f : out bit;
-        vdd : in bit;
-        vss : in bit);
-.br
-.I - Logical description
-.br
-    f <= '0';
-   
-.br
-.I - Physical features
-   number of grids : 2
-   number of feed-through : 1
-.br
-   
-.I - Timing caracteristics
-.br
-
-
-.so man1/alc_bug_report.1
-
diff --git a/alliance/share/man/whatis b/alliance/share/man/whatis
deleted file mode 100644
index 8a80ec41..00000000
--- a/alliance/share/man/whatis
+++ /dev/null
@@ -1,919 +0,0 @@
-ACTION, GENPAT Package
-AFFECT, GENPAT Package
-ALLIANCE VHDL Subset
-AMG (1)              - Array Multiplior Generator
-ARRAY, GENPAT Package
-BEH (3)              - Generic behavioural data structures
-BOOM (1)             - BOOlean Minimization
-BUS (3)              - Creates a bus name for netlist
-BooG (1)             - Binding and Optimizing On Gates.
-COPY_UP_ALL_CON (3)  - copy all physical connectors of an instance face in the current figure
-COPY_UP_ALL_REF (3)  - copy a several physical reference from an instance in the current figure
-COPY_UP_CON (3)      - copy a physical connector from an instance in the current figure
-COPY_UP_CON_FACE (3) - copy a physical connector from an instance in the current figure
-COPY_UP_REF (3)      - copy a physical reference from an instance in the current figure
-COPY_UP_SEG (3)      - copy a physical segment from an instance in the current figure
-DECLAR, GENPAT Package
-DEF_AB (3)           - define a new abutment box to the current layout cell
-DEF_GENPAT, GENPAT Package
-DEF_LOFIG (3)        - open a netlist model as current figure
-DEF_PHFIG (3)        - open a layout model as current figure
-DEF_PHINS (3)        - define a new reference instance
-DEF_PHSC (3)         - load a netlist and open a layout model as current figure
-DLX_ASM (1)          - assembly language for DLX processor
-DPR (1)              - Placer-Router for Datapath Compiler
-DP_ADD2F (3)         - Adder-Substractor
-DP_ADSB2 (3)         - adder-substractor
-DP_ADSB2F (3)        - Adder-Substractor
-DP_AND2 (3)          - Logical and 2.
-DP_AND3 (3)          - logical and 3
-DP_BUFF (3)          - inverter
-DP_BUSE (3)          - Tristate with direct output.
-DP_CONST (3)         - Constant Generator
-DP_DEFLOFIG (3)      - Open a new Data-Path figure/model.
-DP_IMPORT (3)        - Add a new data-path component inside the current data-path.
-DP_INV (3)           - inverter
-DP_LOCON (3)         - Logical connector
-DP_MULT (3)          - Unpipelined array multiplier.
-DP_MULTP (3)         - Unpipelined array multiplier.
-DP_MUX2CS (3)        - 2 input multiplexer.
-DP_MUX3CD (3)        - 3 input multiplexer.
-DP_MUX3CS (3)        - 3 input multiplexer.
-DP_MUX4CS (3)        - 4 input multiplexer.
-DP_MUX5CS (3)        - 5 input multiplexer.
-DP_NAND2 (3)         - logical not and 2
-DP_NAND2MASK (3)     - Logical not and 2 controllable mask.
-DP_NAND3 (3)         - logical not and 3
-DP_NBUSE (3)         - Tristate with complemented output.
-DP_NMUX2CS (3)       - 2 input multiplexer, with complemented output.
-DP_NOR2 (3)          - logical not or 2
-DP_NOR2MASK (3)      - Logical not or 2 controllable mask.
-DP_NOR3 (3)          - logical not or 3
-DP_NUL (3)           - Zero Detect
-DP_OR2 (3)           - logical or 2
-DP_OR3 (3)           - logical or 3
-DP_PDFF (3)          - D Flip-Flop with write enable.
-DP_PDFFQ (3)         - D Flip-Flop with write enable.
-DP_PDFFR (3)         - D Flip-Flop with write enable and reset.
-DP_PDFFRT (3)        - D Flip-Flop with scan-path, write enable and reset.
-DP_PDFFT (3)         - D Flip-Flop with scan-path and write enable.
-DP_PDFFTQ (3)        - D Flip-Flop with scan-path and write enable.
-DP_RFG1C0 (3)        - Register File
-DP_RFG1CC (3)        - Register File
-DP_RFG2C0 (3)        - Register File
-DP_RFG2CC (3)        - Register File
-DP_SAVLOFIG (3)      - Save Data-Path figure/model.
-DP_SHIFT (3)         - Barrel Shifter
-DP_TRACE (3)         - Eanble/disable trace mode.
-DP_XNOR2 (3)         - logical not exclusive or 2
-DP_XNOR2MASK (3)     - Logical not exclusive or 2 controllable mask.
-DP_XOR2 (3)          - logical exclusive or 2
-DRuC (1)             - Design Rule Checker
-ELM (3)              - Creates a single element bus name for netlist
-FCL (5)              - Transistor net-list pattern-matching library
-FLATTEN_ALL_LOINS (3) - flatten all instances in the current netlist figure
-FLATTEN_ALL_PHINS (3) - flatten all instances in the current layout figure
-FLATTEN_LOFIG (3)    - flatten an instance in the current netlist figure
-FLATTEN_PHFIG (3)    - flatten an instance in the current layout figure
-FPLIB (5)            - Cells library for FITPATH dedicated generators.
-GENLIB_BUS (3)       - Creates a bus name for netlist
-GENLIB_COPY_UP_ALL_CON (3) - copy all physical connectors of an instance face in the current figure
-GENLIB_COPY_UP_ALL_REF (3) - copy a several physical reference from an instance in the current figure
-GENLIB_COPY_UP_CON (3) - copy a physical connector from an instance in the current figure
-GENLIB_COPY_UP_CON_FACE (3) - copy a physical connector from an instance in the current figure
-GENLIB_COPY_UP_REF (3) - copy a physical reference from an instance in the current figure
-GENLIB_COPY_UP_SEG (3) - copy a physical segment from an instance in the current figure
-GENLIB_DEF_AB (3)    - define a new abutment box to the current layout cell
-GENLIB_DEF_LOFIG (3) - open a netlist model as current figure
-GENLIB_DEF_PHFIG (3) - open a layout model as current figure
-GENLIB_DEF_PHINS (3) - define a new reference instance
-GENLIB_DEF_PHSC (3)  - load a netlist and open a layout model as current figure
-GENLIB_ELM (3)       - Creates a single element bus name for netlist
-GENLIB_FLATTEN_ALL_LOINS (3) - flatten all instances in the current netlist figure
-GENLIB_FLATTEN_ALL_PHINS (3) - flatten all instances in the current layout figure
-GENLIB_FLATTEN_LOFIG (3) - flatten an instance in the current netlist figure
-GENLIB_FLATTEN_PHFIG (3) - flatten an instance in the current layout figure
-GENLIB_GET_CON_X (3) - retrieve the x coordinate of an instance connector
-GENLIB_GET_CON_Y (3) - retrieve the x coordinate of an instance connector
-GENLIB_GET_INS_X (3) - retrieve the x coordinate of an instance
-GENLIB_GET_INS_Y (3) - retrieve the y coordinate of an instance
-GENLIB_GET_REF_X (3) - retrieve the x coordinate of an instance reference
-GENLIB_GET_REF_Y (3) - retrieve the y coordinate of an instance reference
-GENLIB_HEIGHT (3)    - compute the height of a model
-GENLIB_LOAD_LOFIG (3) - loads a netlist form disk and opens it as current figure
-GENLIB_LOCON (3)     - adds a logical connector to the current netlist figure
-GENLIB_LOINS (3)     - add a logical instance to the current figure
-GENLIB_LOINSE (3)    - add a logical instance to the current figure, with explicit connections
-GENLIB_LOSIG (3)     - declare an internal logical signal, or a vector of internal logical signals
-GENLIB_LOSIGMERGE (3) - merge two logical signals
-GENLIB_LOTRS (3)     - adds a logical transistor to the current netlist figure
-GENLIB_OUTLINE (3)   - build an outline from the current layout cell
-GENLIB_PHCON (3)     - place a physical connector in the current figure at absolute coordinates
-GENLIB_PHREF (3)     - place a physical reference in the current figure at absolute coordinates
-GENLIB_PHSEG (3)     - place a physical segment in the current figure at absolute coordinates
-GENLIB_PHVIA (3)     - place a physical via in the current figure at absolute coordinates
-GENLIB_PLACE (3)     - place a physical instance in the current figure at absolute coordinates
-GENLIB_PLACE_BOTTOM (3) - place a physical instance in the current figure under the "reference instance"
-GENLIB_PLACE_CON_REF (3) - put a connector on top of a reference belonging an instance in the current figure
-GENLIB_PLACE_LEFT (3) - place a physical instance in the current figure at the left of the "reference instance"
-GENLIB_PLACE_ON (3)  - place a physical instance in the current figure matching connectors
-GENLIB_PLACE_RIGHT (3) - place a physical instance in the current figure at the right of the "reference instance"
-GENLIB_PLACE_SEG_REF (3) - put a segment on a reference belonging an instance in the current figure
-GENLIB_PLACE_TOP (3) - place a physical instance in the current figure on the top of the "reference instance"
-GENLIB_PLACE_VIA_REF (3) - put a via on top of a reference belonging to an instance in the current figure
-GENLIB_REVERSE_PHCON (3) - reverse the order of physical connectors on a bus.
-GENLIB_SAVE_LOFIG (3) - save a netlist on disk
-GENLIB_SAVE_PHFIG (3) - save a layout on disk
-GENLIB_SAVE_PHSC (3) - save a layout on disk
-GENLIB_SC_BOTTOM (3) - place an instance in the current figure at the right of the "reference instance"
-GENLIB_SC_LEFT (3)   - place an instance in the current figure at the right of the "reference instance"
-GENLIB_SC_PLACE (3)  - place an instance in the current figure at absolute coordinates
-GENLIB_SC_RIGHT (3)  - place an instance in the current figure at the right of the "reference instance"
-GENLIB_SC_TOP (3)    - place an instance in the current figure at the right of the "reference instance"
-GENLIB_THRU_CON_H (3) - draw an horizontal wire from side to side of the abutment box of the current figure
-GENLIB_THRU_CON_V (3) - draw a vertical wire with connectors from side to side of the abutment box of the current figure
-GENLIB_THRU_V (3)    - draw a vertical wire from side to side of the abutment box of the current figure
-GENLIB_WIDTH (3)     - compute the width of a model
-GENLIB_WIRE1 (3)     - place a physical segment in the current figure
-GENLIB_WIRE2 (3)     - place two physical segments in the current figure
-GENLIB_WIRE3 (3)     - place three physical segments in the current figure
-GETCPAT, GENPAT Package
-GET_CON_X (3)        - retrieve the x coordinate of an instance connector
-GET_CON_Y (3)        - retrieve the x coordinate of an instance connector
-GET_INS_X (3)        - retrieve the x coordinate of an instance
-GET_INS_Y (3)        - retrieve the y coordinate of an instance
-GET_REF_X (3)        - retrieve the x coordinate of an instance reference
-GET_REF_Y (3)        - retrieve the y coordinate of an instance reference
-HEIGHT (3)           - compute the height of a model
-INF (5)              - YAGLE and TAS information file
-INIT, GENPAT Package
-LABEL, GENPAT Package
-LOAD_LOFIG (3)       - loads a netlist form disk and opens it as current figure
-LOCON (3)            - adds a logical connector to the current netlist figure
-LOINS (3)            - add a logical instance to the current figure
-LOINSE (3)           - add a logical instance to the current figure, with explicit connections
-LOSIG (3)            - declare an internal logical signal, or a vector of internal logical signals
-LOSIGMERGE (3)       - merge two logical signals
-LOTRS (3)            - adds a logical transistor to the current netlist figure
-LooN (1)             - Light optimizing on Nets.
-MBK_CATAL_NAME (1)   - define the mbk catalog file
-MBK_CATA_LIB (1)     - define the mbk catalog directory
-MBK_FILTER_SFX (1)   - define the input/output filter suffixe.
-MBK_IN_FILTER (1)    - define the input filter
-MBK_IN_LO (1)        - define the logical input format of mbk and genlib
-MBK_IN_PH (1)        - define the physical input format of mbk and genlib
-MBK_OUT_FILTER (1)   - define the input filter
-MBK_OUT_LO (1)       - define the logical output format of mbk and genlib
-MBK_OUT_PH (1)       - define the physical output format of mbk and genlib
-MBK_SEPAR (1)        - define the separator character for hierarchy
-MBK_VDD (1)          - define the high level power name pattern
-MBK_VSS (1)          - define the ground power name pattern
-MBK_WORK_LIB (1)     - define the mbk working directory
-OUTLINE (3)          - build an outline from the current layout cell
-OpenVerticalChannel -open a vertical channel inside a phfig
-PAT (3)              - Generic pattern data structure
-PAT (5)              - Pattern description format
-PHAD_PHFIG (3)       - loads a layout form disk and opens it as current figure
-PHCON (3)            - place a physical connector in the current figure at absolute coordinates
-PHREF (3)            - place a physical reference in the current figure at absolute coordinates
-PHSEG (3)            - place a physical segment in the current figure at absolute coordinates
-PHVIA (3)            - place a physical via in the current figure at absolute coordinates
-PLACE (3)            - place a physical instance in the current figure at absolute coordinates
-PLACE_BOTTOM (3)     - place a physical instance in the current figure under the "reference instance"
-PLACE_CON_REF (3)    - put a connector on top of a reference belonging an instance in the current figure
-PLACE_LEFT (3)       - place a physical instance in the current figure at the left of the "reference instance"
-PLACE_ON (3)         - place a physical instance in the current figure matching connectors
-PLACE_RIGHT (3)      - place a physical instance in the current figure at the right of the "reference instance"
-PLACE_SEG_REF (3)    - put a segment on a reference belonging an instance in the current figure
-PLACE_TOP (3)        - place a physical instance in the current figure on the top of the "reference instance"
-PLACE_VIA_REF (3)    - put a via on top of a reference belonging to an instance in the current figure
-PMExpr (3)           - returns 1 if the pattern matching is possible between two expressions.
-RDS_IN (1)           - define the real layout input file format of rds
-RDS_OUT (1)          - define the real layout output format of rds
-RDS_TECHNO_NAME (1)  - define the rds technology file
-REVERSE_PHCON (3)    - reverse the order of physical connectors on a bus.
-RING (1)             - PAD RING router
-SAVE, GENPAT Package
-SAVE_LOFIG (3)       - save a netlist on disk
-SAVE_PHFIG (3)       - save a layout on disk
-SAVE_PHSC (3)        - save a layout on disk
-SAV_GENPAT, GENPAT Package
-SC_BOTTOM (3)        - place an instance in the current figure at the right of the "reference instance"
-SC_LEFT (3)          - place an instance in the current figure at the right of the "reference instance"
-SC_PLACE (3)         - place an instance in the current figure at absolute coordinates
-SC_RIGHT (3)         - place an instance in the current figure at the right of the "reference instance"
-SC_TOP (3)           - place an instance in the current figure at the right of the "reference instance"
-SETTUNIT, GENPAT Package
-SYF (1)              - Finite State Machine synthesizer.
-SymbolicChannelRouter (3) - routes a given channel on a Virtual grid
-THRU_CON_H (3)       - draw an horizontal wire from side to side of the abutment box of the current figure
-THRU_CON_V (3)       - draw a vertical wire with connectors from side to side of the abutment box of the current figure
-THRU_H (3)           - draw an horizontal wire from side to side of the abutment box of the current figure
-THRU_V (3)           - draw a vertical wire from side to side of the abutment box of the current figure
-UNFLATTEN_LOFIG (3)  - creates a hierarchy level from instances in the current logical figure
-VASY (1)             - VHDL Analyzer for Synthesis
-WIDTH (3)            - compute the width of a model
-WIRE1 (3)            - place a physical segment in the current figure
-WIRE2 (3)            - place two physical segments in the current figure
-WIRE3 (3)            - place three physical segments in the current figure
-a2_dp
-a2_y
-a2p_dp
-a2p_y
-a3_dp
-a3_y
-a3p_dp
-a3p_y
-a4_dp
-a4_y
-a4p_dp
-a4p_y
-abl (1)              - Prefixed representation for boolean functions
-ablToBddCct (3)      - converts an ABL into a BDD within a circuit
-aboxmbkrds (3)       - converts MBK abutment box to RDS rectangle
-addHExpr (3)         - adds a new argument at the head of an operator expression.
-addInputCct (3)      - adds an input to a circuit
-addListBdd (3)       - adds a BDD to a chained list of BDDs
-addOuputCct (3)      - adds an ouput associated to a BDD in a circuit
-addQExpr (3)         - adds a new argument at the queue of an operator expression.
-addTH (3)            - adds a new item in a hash table.
-addablhexpr (3)      - adds a new argument in head of an expression.
-addablqexpr (3)      - adds a new argument in queue of an expression.
-addauth2elem (3)     - adds an element in the hash table.
-addauthelem (3)      - adds an element in the hash table.
-addbddassoc (3)      - creates a new association variables.
-addbddcircuitabl (3) - converts an abl expression to a bdd node.
-addbddcircuitin (3)  - adds an input in a bdd circuit.
-addbddcircuitout (3) - adds an output in a bdd circuit.
-addbddnode (3)       - adds a new bdd node in the bdd system.
-addbddnodeassoc (3)  - adds a bdd node in a variable association.
-addbddnodelist (3)   - adds a node in a chain_list.
-addbddvar (3)        - adds a new variable in the bdd system.
-addbddvarafter (3)   - adds a new variable, after an existing one.
-addbddvarbefore (3)  - adds a new variable, before an existing one.
-addbddvarfirst (3)   - adds a new variable, before all others.
-addbddvarlast (3)    - adds a new variable, after all others.
-addcapa (3)          - add a capacitance to a signal
-addchain (3)         - create a chain and add it to a list
-addht (3)            - create an hash table
-addhtitem (3)        - adds a new item in a hash table.
-addlocon (3)         - create a logical connector
-addlofig (3)         - create a new structural cell model
-addloins (3)         - create a logical instance
-addlomodel (3)       - create a tempotary logical model and add it to a list
-addlosig (3)         - create a logical signal
-addlotrs (3)         - create a logical transistor
-addnum (3)           - create a num and add it to a list
-addphcon (3)         - create a physical connector
-addphfig (3)         - create a new physical cell model
-addphins (3)         - create a physical instance
-addphref (3)         - create a physical reference
-addphseg (3)         - create a physical segment
-addphvia (3)         - create a physical via
-addptype (3)         - create a ptype and add it to a ptype_list
-addrdsfig (3)        - adds a figure
-addrdsfigrec (3)     - adds a rectangle to a figure
-addrdsins (3)        - adds an instance to a figure
-addrdsinsrec (3)     - adds a rectangle to an instance
-addrdsrecwindow (3)  - adds a rectangle in the windowing of rds structure.
-ai (5)               - Alliance icon format
-al (5)               - Alliance logical format
-alcbanner (1)        - Display a standardized banner for Alliance tools
-algue (1)            - ALliance Graphic User Environement
-ali (1)              - ALliance Information
-alliancebanner (3)   - display the standardized Alliance banner
-allocrdsfig (3)      - allocs memory for a figure
-allocrdsins (3)      - allocates memory for an instance
-allocrdsrec (3)      - allocates memory for a rectangle
-allocrdsrecwin (3)   - allocates a structure used to know windows which contains a rectangle.
-allocrdswin (3)      - allocates window's table
-allocrdswindow (3)   - allocates a window structure
-allocrdswinrec (3)   - allocates a structure used to create a list of tables of rectangles.
-annup_dp
-annup_y
-anyExpr (3)          - returns the value of a logical OR applied on the results of the application of a function on the arguments of an operator expression
-ap (5)               - Alliance physical format
-append (3)           - append a chain_list to an other chain_list
-applyBdd (3)         - applies an operator to a list of BDD.
-applyBinBdd (3)      - applies an operator to two BDD.
-applybddnode (3)     - applies an operator on two bdd nodes.
-applybddnodeite (3)  - computes the IF-THEN-ELSE logical operation.
-applybddnodelist (3) - applies an opertor to a bdd nodes list.
-applybddnodenot (3)  - complements a bdd.
-applybddnodeterm (3) - applies an operator on two bdd nodes.
-applyrdssym (3)      - applies a transformation to a rectangle from a model
-apr (3)              - routing and placement functions
-arp (3)              - routing and placement functions
-asimut (1)           - A simulation tool for hardware descriptions
-aut (1)              - Memory allocation, and hash tables management
-autallocblock (3)    - memory allocator
-autallocheap (3)     - heap memory allocator
-autfreeblock (3)     - releases a memory block
-autfreeheap (3)      - releases a memory block, and put it on the heap.
-auth2elem (3)        - element in an hash table with two keys.
-auth2table (3)       - hash table structure
-authelem (3)         - element in an hash table
-authtable (3)        - hash table structure
-autresizeblock (3)   - resizes a memory block
-b1_dp
-b1_y
-bbr (1)              - A pitchless channel router for preplaced two blocks floorplan
-bdd (1)              - Mutli Reduced Ordered Binary Decision Diagrams
-bdd (1)              - Ordered binary decision diagrams representation
-bddToAblCct (3)      - converts a BDD into an ABL within a circuit
-beaux (3)            - BEH data structure
-bebus (3)            - BEH data structure
-bebux (3)            - BEH data structure
-befig (3)            - BEH data structure
-begen (3)            - BEH data structure
-beh_addbeaux, beh_delbeaux, beh_rmvbeaux, beh_frebeaux
-beh_addbebus, beh_delbebus, beh_rmvbebus, beh_frebebus
-beh_addbebux, beh_delbebux, beh_rmvbebux, beh_frebebux
-beh_addbefig, beh_delbefig, beh_rmvbefig, beh_frebefig
-beh_addbegen, beh_delbegen, beh_rmvbegen, beh_frebegen
-beh_addbemsg, beh_delbemsg, beh_rmvbemsg, beh_frebemsg
-beh_addbeout, beh_delbeout, beh_rmvbeout, beh_frebeout
-beh_addbepor, beh_delbepor, beh_rmvbepor, beh_frebepor
-beh_addbereg, beh_delbereg, beh_rmvbereg, beh_frebereg
-beh_addberin, beh_delberin, beh_rmvberin, beh_freberin
-beh_addbiabl, beh_delbiabl, beh_frebiabl
-beh_addbinode, beh_delbinode, beh_frebinode
-beh_debug (3)        - BEH structures displayer-debugger
-beh_depend (3)       - compute forward dependencies in a description
-beh_error
-beh_makbdd (3)       - create a BDD for each expression in a description
-beh_makgex (3)       - create a GEX for each expression in a description
-beh_message
-bemsg (3)            - BEH data structure
-beout (3)            - BEH data structure
-bepor (3)            - BEH data structure
-bereg (3)            - BEH data structure
-berin (3)            - BEH data structure
-bgd (1)              - register file generator
-biabl (3)            - BEH data structure
-bigvia (3)           - draws a non minimal via as a bunch of vias
-binode (3)           - BEH data structure
-bop (1)              - boolean optimization of a logic level behavioural description (VHDL data flow)
-bsg (1)              - Barrel Shifter Generator
-buildrdswindow (3)   - builds windowing of a figure
-buseg (1)            - Tristate generator for FITPATH data-path compiler.
-c4map (1)            - mapping of a behavioural description with the CMOS Complex Cell Compiler : C4.
-catal (5)            - catalog file format
-chain (3)            - mbk lisp-like service structure
-changeOperExpr (3)   - changes the operator of the head of an expression.
-charToExpr (3)       - converts a string into an expression
-charToOper (3)       - converts an operator string into an operator number
-checkloconorder (3)  - checks the consistency of a list of logical connectors
-clearbddsystemref (3) - clears the references for all bdd nodes.
-clearbddsystemrefext (3) - clears the external references for all bdd nodes.
-clearbddsystemrefint (3) - clears the internal references for all bdd nodes.
-cmx2_y
-cofactorbddnode (3)  - computes the generalized cofactor.
-comment, GENPAT Package
-composeBdd (3)       - substitutes an index by a BDD in another BDD
-composeCct (3)       - composes all the outputs within a circuit with a BDD
-composebddnode (3)   - substitutes a variable by a bdd in another bdd.
-concatname (3)       - concatenate two names with user separator
-conmbkrds (3)        - converts MBK connector to RDS rectangle
-constraintBdd (3)    - restricts a BDD to another BDD
-constraintCct (3)    - restricts all the outputs within a circuit with a BDD constraint
-conv, GENPAT Package
-convcmp, GENPAT Package
-convertbddcircuitabl (3) - converts a bdd node to an abl expression.
-convertbddcircuitsumabl (3) - converts a bdd node to an abl expression.
-convertbddindexabl (3) - converts a bdd index to an abl expression.
-convertbddmuxabl (3) - converts two bdd nodes to an abl multiplexor expression.
-convertbddnodeabl (3) - converts a bdd node to an abl expression.
-convertbddnodesumabl (3) - converts a bdd node to an abl expression.
-copyExpr (3)         - copies an expression
-cpOrderCct (3)       - copies the association order of the inputs with the indexes in another circuit
-createAtom (3)       - creates an atomic expression.
-createBinExpr (3)    - creates a binary operator expression with an eventual merging of the operators.
-createExpr (3)       - creates the head of an operator expression.
-createNodeTermBdd (3) - creates a terminal node of variable.
-createTH (3)         - create a hash table
-createablatom (3)    - creates an atomic expression.
-createablbinexpr (3) - creates a binary operator expression.
-createablnotexpr (3) - complements an expression.
-createabloper (3)    - creates the head of an operator expression.
-createablunaryexpr (3) - creates an unary operator expression.
-createablxorbinexpr (3) - creates an 'xor' or 'xnor' operator expression.
-createauth2table (3) - creates an hash table with two keys.
-createauthtable (3)  - creates a simple hash table.
-createbddcircuit (3) - creates a bdd circuit.
-createbddsystem (3)  - creates a bdd system.
-cry_dp
-cry_y
-d1_y
-decbddrefext (3)     - decrements the external reference of a bdd node.
-decbddrefint (3)     - decrements the internal reference of a bdd node.
-defab (3)            - defines the abutment box of a phfig
-delablexpr (3)       - deletes an expression.
-delablexprnum (3)    - deletes an operand in an expression.
-delauth2elem (3)     - deletes an element in the hash table.
-delauthelem (3)      - deletes an element in the hash table.
-delbddassoc (3)      - deletes a variable association.
-delbddcircuitout (3) - deletes an output in a bdd circuit.
-delbddnode (3)       - deletes an unused bdd node.
-delbddnodeassoc (3)  - deletes a bdd node in a variable association.
-delbddnodelist (3)   - deletes a list of bdd nodes.
-delchain (3)         - delete an element of a chain_list
-deleteNumExpr (3)    - removes the i-th argument of an operator expression.
-deleteTH (3)         - removes an item in a hash table.
-delht (3)            - removes an hash table
-delhtitem (3)        - removes an item in an hash table
-dellocon (3)         - delete a logical connector
-dellofig (3)         - delete and free a logical figure
-delloins (3)         - delete a logical instance
-dellosig (3)         - delete a logical signal
-dellotrs (3)         - delete a logical transistor
-delnum (3)           - delete an element of a num_list
-delphcon (3)         - delete a physical connector
-delphfig (3)         - delete and free a physical figure
-delphins (3)         - delete a physical instance
-delphref (3)         - delete a physical reference
-delphseg (3)         - delete a physical segment
-delphvia (3)         - delete a physical via
-delptype (3)         - delete an element of a ptype_list
-delrdsfig (3)        - deletes a figure
-delrdsfigrec (3)     - deletes a rectangle of a figure
-delrdsins (3)        - deletes an instance of a figure
-delrdsinsrec (3)     - deletes a rectangle of an instance
-delrdsrecwindow (3)  - deletes a rectangle from the windowing of rds structure.
-destroyBdd (3)       - removes the BDDs system
-destroyCct (3)       - removes a circuit
-destroyTH (3)        - removes a hash table
-destroyauth2table (3) - destroys an hash table with two keys.
-destroyauthtable (3) - destroys a simple hash table.
-destroybddassoc (3)  - frees all the variable associations.
-destroybddcircuit (3) - destroys a bdd circuit.
-destroybddsystem (3) - destroys a bdd system.
-destroyrdswindow (3) - destroys windowing of a figure
-devXor2Expr (3)      - converts XOR 2 to OR-AND
-devXorExpr (3)       - removes XOR in an expression
-devablxorexpr (3)    - develops 'xor', 'nxor' in an expression.
-devdupablxorexpr (3) - duplicates and develops 'xor', 'nxor'.
-displayBdd (3)       - displays a BDD
-displayCct (3)       - displays a circuit
-displayExpr (3)      - displays an expression in a prefixed notation.
-displayInfExpr (3)   - displays an expression in infixed notation.
-displayTH (3)        - displays a hash table
-downstr (3)          - convert a string to lower case
-dplib (5)            - Cell library for data-path custom operators.
-dpp (1)              - DataPath Placement tool
-dreal (1)            - Graphic real layout viewer
-dtv (5)              - The timing analyzer tas report : 'detailed perfmodule' format.
-dupablexpr (3)       - duplicates an expression.
-equalExpr (3)        - checks that two expressions are strictly equal
-equalVarExpr (3)     - checks that two expressions are syntactically equal
-etas (1)             - A timing file .dtx and .ttx browser
-everyExpr (3)        - returns the value of a logical AND applied on the results of the application of a function on the argument of an operator expression.
-existbddnodeassocoff (3) - computes an existantial quantification.
-existbddnodeassocon (3) - computes an existantial quantification.
-exprToChar (3)       - converts an expression into a string
-figmbkrds (3)        - converts MBK figure to RDS figure
-filepath (3)         - return the whole search path of a file
-flatArityExpr (3)    - flattens the operators of an expression
-flatPolarityExpr (3) - translates the inverters of an expression to the level of atomic expressions
-flatablexpr (3)      - merges the operators of an expression
-flatbeh (1)          - Synthetize a behavioral description from a structural description
-flatenphfig (3)      - flatten a instance in a figure
-flattenlofig (3)     - flatten a instance in a logical figure
-fmi (1)              - FSM state miminization
-fpgen (1)            - Procedural language for Data-Path synthesis based upon C.
-fpmap (1)            - fpga mapper of a logic level behavioural description (VHDL data flow)
-freeExpr (3)         - frees an expression.
-freeablexpr (3)      - frees an expression.
-freechain (3)        - free a chain_list
-freelomodel (3)      - free a lofig_list for temporary models
-freenum (3)          - free a num_list
-freeptype (3)        - free a ptype_list
-freerdsfig (3)       - frees memory associated to a figure
-freerdsins (3)       - frees memory associated to an instance
-freerdsrec (3)       - free memory associated to a rectangle
-fsm (1)              - Finite State Machine representation.
-fsm (5)              - Alliance VHDL Finite State Machine description subset.
-fsp (1)              - Formal proof between two FSM descriptions
-garbagebddsystem (3) - Forces a bdd garbage collection.
-gcNodeBdd (3)        - does a garbage collection
-gcNodeCct (3)        - does a garbage collection
-genbs (1)            - A IEEE 1149.1 Boundary-Scan Architecture Generator
-genlib (1)           - Procedural design language based upon C, along with its compiler
-genpat, A procedural pattern file generator
-genscan (1)          - scan path generator
-genview (1)          - genlib graphical source level debugger
-getablexprdepth (3)  - gives the depth of an expression.
-getablexprlength (3) - gives the length of an expression.
-getablexprmax (3)    - applies a function to all operands.
-getablexprmin (3)    - applies a function to all operands.
-getablexprnum (3)    - gives a specified operand of an expression.
-getablexprnumatom (3) - gives the number of atom in an expression.
-getablexprnumbinoper (3) - gives the number of binary operators in an expression.
-getablexprnumocc (3) - how many times a name appears in an expression.
-getablexprsupport (3) - gives the expression's support.
-getbddnodenum (3)    - gets the number of nodes in a bdd.
-getbddnodesize (3)   - gets the number of nodes in a bdd.
-getbddnodesupport (3) - gives the variable support of a bdd node.
-getbddvarbyindex (3) - converts bdd index to a variable number.
-getbddvarindex (3)   - converts a variable number in a bdd index.
-getbddvarnode (3)    - gives the bdd node of a variable.
-gethtitem (3)        - searches an item in a hash table
-getlocon (3)         - retrieve a logical connector
-getlofig (3)         - give back a pointer to a lofig
-getloins (3)         - retrieve a logical instance
-getlomodel (3)       - retrieve a model from a lofig_list
-getlosig (3)         - retrieve a logical signal
-getphcon (3)         - retrieve a physical connector
-getphfig (3)         - give back a pointer to a phfig
-getphins (3)         - retrieve a physical instance
-getphref (3)         - retrieve a physical reference
-getptype (3)         - retrieve a ptype from a ptype_list
-getrdsfig (3)        - gets a pointer to a figure called by its name.
-getrdsmodellist (3)  - gets model list of the instances of a figure
-getsigname (3)       - choose a signal name in alias list
-givelosig (3)        - give a logical signal
-glop (1)             - Fanout optimizer, global optimizer and timing analyzer of a gate netlist
-graal (1)            - symbolic layout editor
-grog (1)             - a generic ROM generator
-grog (3)             - call the ROM generator
-guessextdir (3)      - guess external connectors directions from internal connectors directions
-htv (5)              - The timing analyzer tas report : 'detailed perfmodule' format.
-identExpr (3)        - gives an ident from an operator expression.
-implybddnode (3)     - computes a bdd that implies a conjonction of two bdd nodes.
-incatalog (3)        - test if cell belongs to the catalog file
-incatalogdelete (3)  - test if cell belongs to the catalog file
-incatalogfeed (3)    - test if cell belongs to the catalog file
-incataloggds (3)     - test if cell belongs to the catalog file
-incbddrefext (3)     - increments the external reference of a bdd node.
-incbddrefint (3)     - increments the internal reference of a bdd node.
-initializeBdd (3)    - initializes the BDDs system
-initializeCct (3)    - creates a circuit
-insconmbkrds (3)     - adds in RDS instance all the connectors of MBK instance
-insmbkrds (3)        - converts MBK figure to RDS figure
-insrefmbkrds (3)     - adds in RDS instance all the references of MBK instance.
-inssegmbkrds (3)     - adds in RDS instance all the segments of MBK instance
-instanceface (3)     - returns the face of a connector in a placed instance
-instr (3)            - find an occurence of a string in a string, starting at a specified character.
-insviambkrds (3)     - adds to RDS instance all the contacts from MBK instance
-intersectbddnode (3) - tests for an intersection between two bdd nodes.
-isablbinaryoper (3)  - tests if an operator is binary.
-isablequalexpr (3)   - tests if two expressions are strictly identicals.
-isabloperinexpr (3)  - tests if an operator appears in an expression.
-isablsimilarexpr (3) - tests if two expressions have the same morphology.
-isablunaryoper (3)   - tests if an operator is unary.
-isbddvarinsupport (3) - tests if a variable appears in a bdd.
-isvdd -tells if a name contains the pattern defined by the user
-isvss -tells if a name contains the pattern defined by the user
-k2f, FSM translator ALLIANCE format from/to Berkeley format
-l1_y
-l1n_y
-l1x_y
-l2_y
-l2n_y
-l2p (1)              - Creates a PostScript file from a symbolic layout file, or from a physical layout file.
-l3_y
-l3r_y
-l3s_y
-l4_y
-l4r_y
-l4s_y
-l5_y
-l5r_y
-l5s_y
-l6r_y
-l6s_y
-lax (5)              - Parameter file for logic synthesis
-lengthExpr (3)       - returns the number of arguments in an expression
-librds (1)           - rds library description
-librfm (1)           - rfm library description
-librpr (1)           - rpr library description
-librtl (1)           - rtl library description
-librut (1)           - rut library description
-librwi (1)           - rwi library description
-loadlofig (3)        - load a new logical cell model from disk
-loadphfig (3)        - load a new physical cell model from disk
-loadrdsfig (3)       - give back a pointer to a figure
-loadrdsparam (3)     - load parameters from symbolic to real conversion.
-locon (3)            - mbk logical connector
-lofig (3)            - mbk logical figure
-lofigchain (3)       - creates a netlist in terms of connectors on signals
-log (1)              - logical representations for boolean functions and utilities.
-log (3)              - logical representations for boolean functions and utilities.
-loins (3)            - mbk logical instance
-losig (3)            - mbk logical signal
-lotrs (3)            - mbk logical transistor
-lvx (1)              - Logical Versus eXtracted net-list comparator
-lynx (1)             - Hierarchical netlist extractor
-mapCarExpr (3)       - creates a new expression by applying a function to all the arguments of an operator expression
-mapExpr (3)          - applies a procedure to all arguments of an operator expression
-mapablanyexpr (3)    - applies a function to all operands.
-mapableveryexpr (3)  - applies a function to all operands.
-mapablexpr (3)       - applies a function to all operands.
-mapabloperexpr (3)   - applies a function to all operands.
-markAllBdd (3)       - marks all the nodes of the BDDs system
-markBdd (3)          - marks all nodes of a BDD
-markbddnode (3)      - marks bdd node with a specified mask.
-maxExpr (3)          - returns the highest argument of an operator expression.
-mbk (1)              - generic layout and netlist data structures
-mbk (3)              - Generic layout, netlist and utility data structures
-mbk2ps (1)           - Creates a PostScript file from a symbolic layout cell
-mbkalloc (3)         - mbk memory allocator
-mbkcif (1)           - mbk cif translater
-mbkenv (3)           - set user preferences
-mbkfopen (3)         - open a file with several search pathes
-mbkfree (3)          - mbk memory allocator
-mbkps (3)            - mbk process state
-mbkrealloc (3)       - mbk memory reallocator
-mbkunlink (3)        - delete a file in the WORK_LIBP.
-minExpr (3)          - returns the lowest argument of an operator expression.
-mlodebug (3)         - logical data structure contents debug function
-modelmbkrds (3)      - gets all models of instances contained in a figure.
-mphdebug (3)         - physical data structure contents debug function
-ms2_dp
-ms2_y
-ms2n_dp
-ms2n_y
-ms2rx_dp
-ms2rx_y
-ms2sx_dp
-ms2sx_y
-ms2x_dp
-ms2x_y
-ms_dp
-ms_y
-msn_dp
-msn_y
-msrx_dp
-msrx_y
-mssx_dp
-mssx_y
-msx_dp
-msx_y
-mx2_dp
-mx2_y
-mx2p_dp
-mx2p_y
-mx3_dp
-mx3_y
-mx4_y
-n1_dp
-n1_y
-na2_dp
-na2_y
-na2p_dp
-na2p_y
-na3_dp
-na3_y
-na3p_dp
-na3p_y
-na4_dp
-na4_y
-namealloc (3)        - hash table for strings
-namefind (3)         - hash table for strings
-nameindex (3)        - concatenate a name and index with user separator
-nao3_dp
-nao3_y
-nao4_dp
-nao4_y
-naturalstrcmp (3)    - compare string in alphabetical order for letters and numerical for digits.
-ndrv_dp
-ndrv_y
-neou4_dp
-nmx2_dp
-nmx2_y
-no2_dp
-no2_y
-no3_dp
-no3_y
-noa3_dp
-noa3_y
-noa4_dp
-noa4_y
-nop2_dp
-nop2_y
-nop3_dp
-nop3_y
-normExpr (3)         - normalizes an expression
-notBdd (3)           - complements a BDD
-notExpr (3)          - complements an expressio and eventually does a simplification
-noue4_dp
-noue4_y
-np1_dp
-np1_y
-num (3)              - mbk list of number
-numberAtomExpr (3)   - returns the number of atoms in an expression
-numberNodeAllBdd (3) - count the number of nodes used in the BDD system
-numberNodeBdd (3)    - computes the number of nodes used in a BDD
-numberNodeCct (3)    - counts the number of nodes used within a circuit
-numberOccExpr (3)    - returns the number of time an atom appears in an expression.
-numberOperBinExpr (3) - returns the number of equivalent binary operators in an expression
-nxr2_dp
-nxr2_y
-o2_dp
-o2_y
-o3_dp
-o3_y
-one_dp
-one_y
-op2_dp
-op2_y
-op3_dp
-op3_y
-operToChar (3)       - converts an operator number into an operator string
-p1_dp
-p1_y
-pacom (3)            - PAT data structure
-paevt (3)            - PAT data structure
-pagrp (3)            - PAT data structure
-paini (3)            - PAT data structure
-paiol (3)            - PAT data structure
-papat (3)            - PAT data structure
-paseq (3)            - PAT data structure
-pat2dwl, pattern translator from ALLIANCE CAD SYSTEM to HILO CAD SYSTEM
-pat_addpacom, pat_frepacom
-pat_addpaevt, pat_frepaevt
-pat_addpagrp
-pat_addpaini, pat_frepaini
-pat_addpaiol, pat_crtpaiol, pat_frepaiol
-pat_addpapat, pat_frepapat
-pat_addpaseq
-pat_debug (3)        - PAT structures displayer-debugger
-pat_lodpaseq (3)     - pattern file compiler
-pat_savpaseq (3)     - save pattern structures in a pattern description file
-patest, a pattern translator for test.
-pck_sp
-phcon (3)            - mbk physical connector
-phfig (3)            - mbk physical figure
-phins (3)            - mbk physical instance
-phref (3)            - mbk physical reference
-phseg (3)            - mbk physical segment
-phvia (3)            - mbk physical contact
-pi_sp
-piot_sp
-piotw_sp
-po_sp
-polarablexpr (3)     - moves inverters to the atomic level.
-polardupablexpr (3)  - duplicates an expression and moves down the inverters.
-port, GENPAT Package
-pot_sp
-potw_sp
-pow_sp
-process, GENPAT Package
-profAOExpr (3)       - returns the depth of an expression without taking the inverters into account.
-profExpr (3)         - returns the depth of an expression.
-prol (5)             - define the rules for symbolic to real layout translation
-proof (1)            - Formal proof between two behavioural descriptions
-proofCct (3)         - checks the equivalence of two circuits
-ptype (3)            - mbk list of typed pointers
-pvdde_sp
-pvddeck_sp
-pvddi_sp
-pvddick_sp
-pvsse_sp
-pvsseck_sp
-pvssi_sp
-pvssick_sp
-rage (1)             - Random Acess Memory(RAM) Generator
-rds (1)              - rds package
-rdsalloc (3)         - memory allocation function
-rdsenv (3)           - set user preference
-rdsfree (3)          - free memory place
-refmbkrds (3)        - adds to RDS figure a references from a MBK figure
-register, GENPAT Package
-relprodbddnodeassoc (3) - computes a relational product.
-reorderbddsystemdynamic (3) - specifies the dynamic bdd reorder parameters.
-reorderbddsystemsimple (3) - reorders the bdd nodes of a bdd system.
-reorderbddsystemtop (3) - reorders the bdd nodes of a bdd system.
-reorderbddsystemwindow (3) - reorders the bdd nodes of a bdd system.
-resetBdd (3)         - resets the BDDs system
-resetCct (3)         - resets a circuit
-resetauth2table (3)  - resets an hash table with two keys.
-resetauthtable (3)   - resets a simple hash table.
-resetbddcircuit (3)  - resets a bdd circuit.
-resetbddsystem (3)   - resets a bdd system.
-restorealldir (3)    - restore all instances' connectors directions
-restoredirvbe (3)    - restore connectors directions from behavioral view
-restrictbddnode (3)  - substitutes a variable by a zero or one, in a bdd.
-reverse (3)          - reverse a list of chained elements
-rfg (1)              - register file generator - version 6.05
-rflattenlofig (3)    - recursivly flatten a figure
-rflattenphfig (3)    - recursivly flatten a figure
-roundrdsrec (3)      - adjusts a rectangle to lambda grid step
-rsa (1)              - Recurrence Solver Adder generator
-rsa (3)              - call the Recurrence Solver Adder generator
-s2r (1)              - Process mapping from symbolic layout to physical layout
-satisfybddnode (3)   - finds a satisfying path for a bdd node.
-savelofig (3)        - save a logical figure on disk
-savephfig (3)        - save a physical figure on disk
-saverdsfig (3)       - save a physical figure on disk.
-scapin (1)           - Scan path insertion
-sclib (5)            - a portable CMOS Standard Cell Library
-scmap (1)            - mapping of a behavioural description onto a standard cell library.
-scr (1)              - Standard Cell Router
-searchExpr (3)       - searches for a specific atom in an expression.
-searchInputCct (3)   - searches for the index number associated to an input.
-searchNumExpr (3)    - fetches the i-th argument in an operator expression.
-searchOperExpr (3)   - searches for an operator in an expression.
-searchOuputCct (3)   - searches for the BDD associated to an output
-searchTH (3)         - searches an item in a hash table.
-searchauth2elem (3)  - searches an element in the hash table.
-searchauthelem (3)   - searches an element in the hash table.
-searchbddcircuitin (3) - searchs an input in a bdd circuit.
-searchbddcircuitout (3) - searchs an output in a bdd circuit.
-searchrdsfig (3)     - searchs by name a figure in the list of figures
-segmbkrds (3)        - adds to RDS figure a segment from a MBK figure
-setbddrefext (3)     - increments the external reference, and decrements the internal reference of a bdd node.
-sethtitem (3)        - test and set an item in an hash table.
-signal, GENPAT Package
-simpablexpr (3)      - simplies an expression.
-simpbddnodedcoff (3) - simplifies a bdd with don't cares on its off-set part.
-simpbddnodedcon (3)  - simplifies a bdd with don't cares on its on-set part.
-simpdupablexpr (3)   - duplicates and simplies an expression.
-simplif10Expr (3)    - makes simplifications on an expression including constant atomic expressions
-simplifDcOneBdd (3)  - simplifies a BDD with don't cares on its on-set part
-simplifDcZeroBdd (3) - simplifies a BDD with don't cares on its off-set part
-simplifNotExpr (3)   - makes simplifications on an expression including inverters
-sortExpr (3)         - sorts an expression
-sortautarray (3)     - heap sort.
-sortlocon (3)        - sort the logical connectors of a figure by name
-sortlosig (3)        - sort the logical signals of a figure by name
-spi (5)              - Alliance parser and driver for Spice netlist.
-substExpr (3)        - copies an expression by substituting a given atom by an expression
-substPhyExpr (3)     - substitutes an atomic expression by an expression within an operator expression
-substablexpr (3)     - substitutes a given atom by an expression.
-substbddnodeassoc (3) - substitutes a set of variables with a set of bdd node.
-substdupablexpr (3)  - substitutes a given atom by an expression.
-sum_dp
-sum_y
-supportChain_listBdd (3) - returns a chained list of nodes that are used in a given BDD.
-supportChain_listExpr (3) - returns the support of an expression in a chain_list.
-supportPtype_listExpr (3) - returns the support of an expression in a ptype_list.
-swapbddvar (3)       - swaps two contiguous variables.
-sxlib (5)            - a portable CMOS Standard Cell Library
-tas (1)              - A switch level static timing analyzer for CMOS circuits
-testbddcircuit (3)   - debugs a bdd circuit.
-tie_y
-tpl (5)              - LV500 Template description format.
-ts_dp
-ts_y
-tsn_dp
-tsn_y
-tsp_y
-ttv (5)              - The timing analyzer tas report : 'general perfmodule' format.
-unflatablexpr (3)    - unflats the operators of an expression
-unflattenlofig (3)   - creates a hierarchy level from instances of a figure
-unmarkbddnode (3)    - unmarks bdd node with a specified mask.
-unsetbddrefext (3)   - increments the internal reference, and decrements the external reference of a bdd node.
-upVarBdd (3)         - brings up an index in a BDD
-upVarCct (3)         - brings up the index of a primary input within a circuit
-upstr (3)            - convert a string to upper case
-vasy VHDL RTL subset.
-vbe VHDL behavioural subset.
-vhdlablname (3)      - returns a compatible VHDL name.
-vhdlablvector (3)    - gives the index and the name of a vectorized name.
-viambkrds (3)        - adds to RDS figure a contact from a MBK figure
-viewablexpr (3)      - displays an expression.
-viewablexprfile (3)  - displays an expression in a file.
-viewablexprstr (3)   - displays an expression in a str.
-viewbddcircuit (3)   - displays a bdd circuit.
-viewbddnode (3)      - displays a bdd node.
-viewbddsystem (3)    - displays a bdd system.
-viewbddsysteminfo (3) - displays statistical informations.
-viewht (3)           - displays a hash table contents
-viewlo (3)           - scan all lofig_lists and display their elements
-viewlofig (3)        - display elements of a lofig_list
-viewlofigcon (3)     - display elements of a locon_list attached to a figure
-viewloins (3)        - display elements of a loins_list
-viewloinscon (3)     - display elements of a locon_list attached to an instance
-viewlosig (3)        - display elements of a losig_list
-viewlotrs (3)        - display elements of a lotrs_list
-viewph (3)           - display all the phfig_lists and their elements
-viewphcon (3)        - display elements of a phcon_list
-viewphfig (3)        - display elements of a phfig_list
-viewphins (3)        - display elements of a phins_list
-viewphref (3)        - display elements of a phref_list
-viewphseg (3)        - display elements of a phseg_list
-viewphvia (3)        - display elements of a phvia_list
-viewrdsfig (3)       - view caracteristics of a figure
-viewrdsins (3)       - Displays caracteristics of an instance
-viewrdsparam (3)     - displays tables in memory filled by loadrdsparam function.
-viewrdsrec (3)       - Displays caracteristics of a rectangle
-viewrdswindow (3)    - displays caracteristics of the windowing.
-viewrfmcon (3)       - displays connector caracteristics in MBK and RDS format.
-viewrfmfig (3)       - displays figure caracteristics in MBK and RDS format.
-viewrfmins (3)       - displays instance caracteristics in MBK and RDS format.
-viewrfmrec (3)       - displays rectangle caracteristics in RDS format.
-viewrfmref (3)       - displays reference caracteristics in MBK and RDS format.
-viewrfmseg (3)       - displays segment caracteristics in MBK and RDS format.
-viewrfmvia (3)       - displays contact caracteristics in MBK and RDS format.
-vst VHDL structural subset.
-xmbk (1)             - A simple way to set alliance environnement variables
-xpat (1)             - graphic pattern viewer
-xr2_dp
-xr2_y
-xsch (1)             - graphical schematic viewer
-xyflat (3)           - compute hierarchical coordinates
-yagle (1)            - Disassembly and functional abstraction of CMOS circuits
-zbli_y
-zero_dp
-zero_y
diff --git a/alliance/share/tutorials/README.tutorials b/alliance/share/tutorials/README.tutorials
deleted file mode 100644
index d372f9d3..00000000
--- a/alliance/share/tutorials/README.tutorials
+++ /dev/null
@@ -1,37 +0,0 @@
-
-You will find here 5 separate tutorials :
-(Please read overview.ps before)
-
-WARNING : These tutorials are not fully working and must be modified to
-          work with Alliance 4.0 (especially the dlx), but we have 
-          decided to release them even though they are not fully 
-          functional. They will be upgraded as soon as we have time.
-
-1/ ADDACCU
-   The design of a very simple chip (adder/accumulator) to get started
-   with the ALLIANCE tools.
-
-   >cd tutorials/addaccu
-
-2/ AMD2901
-   The design of the 4 bits AMD2901 processor, from the VHDL specification to
-   the CIF layout, using the ALLIANCE portable standard cells library.
-
-   >cd tutorials/amd2901
-
-4/ Synthesis
-   Building simple door code using the Finite State Machine synthesizer (syf).
-
-   >cd tutorials/synth
-
-4/ Data Path
-   Building simple data paths using on a procedural data path generator
-   (fpgen) and a data path place and route tool (dpr).
-
-   >cd tutorials/fitpath
-
-5/ DlxM
-   A complete tutorial based on the design of the 32 bit microprocessor DLX.
-
-
-
diff --git a/alliance/share/tutorials/addaccu/Makefile b/alliance/share/tutorials/addaccu/Makefile
deleted file mode 100644
index 68af2ed6..00000000
--- a/alliance/share/tutorials/addaccu/Makefile
+++ /dev/null
@@ -1,254 +0,0 @@
-ASIMUT = $(ALLIANCE_TOP)/bin/asimut
-GENLIB = $(ALLIANCE_TOP)/bin/genlib
-SCR    = $(ALLIANCE_TOP)/bin/scr
-RING   = $(ALLIANCE_TOP)/bin/ring
-LYNX   = $(ALLIANCE_TOP)/bin/lynx
-LVX    = $(ALLIANCE_TOP)/bin/lvx
-YAGLE  = $(ALLIANCE_TOP)/bin/yagle
-PROOF  = $(ALLIANCE_TOP)/bin/proof
-DRUC   = $(ALLIANCE_TOP)/bin/druc
-GRAAL  = $(ALLIANCE_TOP)/bin/graal
-DREAL  = $(ALLIANCE_TOP)/bin/dreal
-S2R    = $(ALLIANCE_TOP)/bin/s2r
-TOUCH  = touch
-
-
-# ###
-# goal of the Makefile: doing the whole chip design and verification
-#
-# ###
-
-all: specifications.pat addaccu.proof addaccu.cif
-	@echo "################################################"
-	@echo "##                                            ##" 
-	@echo "##                 D O N E                    ##" 
-	@echo "##                                            ##" 
-	@echo "################################################"
-	@echo " " 
-	@echo "Run 'make dreal' to see the layout." 
-	@echo " " 
-
-# ###---------------------------------------------------------###
-# check the correctness of specifications (Data-FLow VHDL)      #
-# running the logic simulation                                  #
-# ###---------------------------------------------------------###
-
-specifications.pat : addaccu.vbe addaccu.pat
-	$(ASIMUT) -b addaccu addaccu specifications
-
-# ###---------------------------------------------------------###
-# generate structural description of the circuit's core         #
-# core.c is the schematic capture of the core, using            #
-# the genlib language                                           #
-# the environment variable specify the structural VHDL format   #
-# ###---------------------------------------------------------###
-
-core.vst : core.c
-	MBK_IN_LO=vst ;\
-	MBK_OUT_LO=vst ;\
-	MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/padlib ;\
-	export MBK_IN_LO MBK_OUT_LO MBK_CATA_LIB ;\
-	$(GENLIB) core
-
-
-# ###---------------------------------------------------------###
-# generate structural description of the complete circuit       #
-# addaccu.c is the schematic capture of the circuit, using      #
-# the genlib language                                           #
-# the circuit can be generated only if the core is generated    #
-# the environment variable specify the structural VHDL format   #
-# ###---------------------------------------------------------###
-addaccu.vst : addaccu.c core.vst
-	MBK_IN_LO=vst ;\
-	MBK_OUT_LO=vst ;\
-	MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/padlib ;\
-	export MBK_IN_LO MBK_OUT_LO MBK_CATA_LIB ;\
-	$(GENLIB) addaccu
-
-# ###---------------------------------------------------------###
-# check the correctness of the generated structural             #
-# description running the logic simulation                      #
-# ###---------------------------------------------------------###
-
-schema.pat : addaccu.vst addaccu.pat
-	MBK_IN_LO=vst ;\
-	MBK_OUT_LO=vst ;\
-	MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/padlib ;\
-	export MBK_IN_LO MBK_OUT_LO MBK_CATA_LIB ;\
-	$(ASIMUT) addaccu addaccu schema
-
-# ###---------------------------------------------------------###
-# place and route the circuit's core                            #
-# ###---------------------------------------------------------###
-
-core.ap : core.vst
-	MBK_IN_LO=vst ;\
-	MBK_IN_PH=ap ;\
-	MBK_OUT_PH=ap ;\
-	MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/padlib ;\
-	export MBK_IN_LO MBK_IN_PH MBK_OUT_PH MBK_CATA_LIB ; \
-	$(SCR) -p -r core 
-
-# ###---------------------------------------------------------###
-# extract net-list from symbolic layout for the core            #
-# ###---------------------------------------------------------###
-
-core.al : core.ap
-	MBK_IN_PH=ap ;\
-	MBK_OUT_LO=al ;\
-	RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/cmos_11.rds ;\
-	MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/padlib ;\
-	export MBK_IN_PH MBK_OUT_LO RDS_TECHNO_NAME MBK_CATA_LIB ;\
-	$(LYNX) -v core core
-
-# ###---------------------------------------------------------###
-# compare extracted net-list and structural description         #
-# to check that the standard cell router performed correctly    #
-# ###---------------------------------------------------------###
-
-core.lvx : core.al core.vst
-	MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/padlib ;\
-	export MBK_CATA_LIB ;\
-	$(LVX) vst al core core -f
-	$(TOUCH) core.lvx
-
-# ###---------------------------------------------------------###
-# place and route the circuit (core and pads)                   #
-# this can be done only if the extracted netlist is correct     #
-# ###---------------------------------------------------------###
-
-addaccu.ap : core.ap core.lvx addaccu.vst 
-	MBK_IN_LO=vst ;\
-	MBK_IN_PH=ap ;\
-	MBK_OUT_PH=ap ;\
-	MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/padlib ;\
-	export MBK_IN_PH MBK_OUT_PH MBK_IN_LO MBK_CATA_LIB ;\
-	$(RING) addaccu addaccu
-
-# ###---------------------------------------------------------###
-# extract net-list from symbolic layout for the circuit         #
-# ###---------------------------------------------------------###
-
-addaccu.al : addaccu.ap
-	MBK_IN_PH=ap ;\
-	MBK_OUT_LO=al ;\
-	RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/cmos_11.rds ;\
-	MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/padlib ;\
-	export MBK_IN_PH MBK_OUT_LO RDS_TECHNO_NAME MBK_CATA_LIB ;\
-	$(LYNX) -v addaccu addaccu
-
-# ###---------------------------------------------------------###
-# compare extracted net-list and structural description         #
-# to check that the ring router performed correctly             #
-# ###---------------------------------------------------------###
-
-addaccu.lvx : addaccu.al addaccu.vst
-	$(LVX) vst al addaccu addaccu > addaccu.lvx
-
-# ###---------------------------------------------------------###
-# simulate the extracted net-list                               #
-# ###---------------------------------------------------------###
-
-extracted.pat : addaccu.al
-	MBK_IN_LO=al ;\
-	MBK_OUT_LO=al ;\
-	MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/padlib ;\
-	export MBK_IN_LO MBK_OUT_LO MBK_CATA_LIB ;\
-	$(ASIMUT) addaccu addaccu extracted
-
-# ###---------------------------------------------------------###
-# generate a Data-Flow description from the transistor level    #
-# extracted net-list                                            #
-# ###---------------------------------------------------------###
-
-addaccue.vbe : addaccu.ap addaccue.inf
-	MBK_IN_PH=ap ;\
-	MBK_IN_LO=al ;\
-	MBK_OUT_LO=al ;\
-	RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/cmos_11.rds ;\
-	MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/padlib ;\
-	export MBK_IN_PH MBK_IN_LO MBK_OUT_LO RDS_TECHNO_NAME MBK_CATA_LIB ;\
-	$(LYNX) -v -t addaccu addaccue ;\
-	$(YAGLE) addaccue -i -v
-
-# ###---------------------------------------------------------###
-# simulate the extracted data_flow description                  #
-# ###---------------------------------------------------------###
-
-abstracted.pat : addaccue.vbe
-	MBK_IN_LO=vst ;\
-	MBK_OUT_LO=vst ;\
-	MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/padlib ;\
-	export MBK_IN_LO MBK_OUT_LO MBK_CATA_LIB ;\
-	$(ASIMUT) -b addaccue addaccu abstracted
-
-# ###---------------------------------------------------------###
-# check the correctness of the extracted data_flow              #
-# description running the formal proover                        #
-# ###----------------------------------------------------------##
-
-addaccu.proof : addaccue.vbe addaccu.vbe
-	$(PROOF) -d -p addaccue addaccu
-	$(TOUCH) addaccu.proof
-
-# ###---------------------------------------------------------###
-# check design rules                                            #
-# ###---------------------------------------------------------###
-
-addaccu.drc : addaccu.ap
-	MBK_IN_PH=ap ;\
-	RDS_OUT=cif  ;\
-	RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/cmos_11.rds ;\
-	MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/padlib ;\
-	export MBK_IN_PH RDS_OUT RDS_TECHNO_NAME MBK_CATA_LIB ;\
-	$(DRUC) addaccu
-
-# ###---------------------------------------------------------###
-# generates CIF description for 1.0 um process                  #
-# ###---------------------------------------------------------###
-
-addaccu.cif : addaccu.ap addaccu.drc
-	MBK_IN_PH=ap ;\
-	MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/padlib ;\
-	RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/prol10_11.rds ;\
-	RDS_OUT=cif  ;\
-	RDS_IN=cif ;\
-	export MBK_IN_PH RDS_IN RDS_OUT RDS_TECHNO_NAME MBK_CATA_LIB ;\
-	$(S2R) -v addaccu
-
-# ###---------------------------------------------------------###
-# clean up the directory for tutorial re-run                    #
-# ###---------------------------------------------------------###
-
-clean:
-	-rm specifications.pat \
-	   core.vst schema.pat core.ap core.al core.lvx \
-	   addaccu.vst addaccu.ap addaccu.al extracted.pat \
-	   addaccue.al addaccue.vbe addaccue.dsbr addaccue.fcf \
-	   abstracted.pat addaccu.proof \
-	   addaccu.drc addaccu*.cif 2> /dev/null
-
-# ###---------------------------------------------------------###
-# look at the circuit under graal                               #
-# ###---------------------------------------------------------###
-
-graal : addaccu.ap
-	MBK_IN_PH=ap ;\
-	RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/cmos_11.rds ;\
-	MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/padlib ;\
-	export MBK_IN_PH RDS_TECHNO_NAME MBK_CATA_LIB ;\
-	$(GRAAL) -l addaccu
-
-# ###---------------------------------------------------------###
-# look at the circuit under dreal                               #
-# ###---------------------------------------------------------###
-
-dreal : addaccu.cif
-	MBK_IN_PH=ap ;\
-	MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/padlib ;\
-	RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/prol10_11.rds ;\
-	RDS_OUT=cif  ;\
-	RDS_IN=cif ;\
-	export MBK_IN_PH RDS_IN RDS_OUT RDS_TECHNO_NAME MBK_CATA_LIB ;\
-	$(DREAL) -l addaccu
-
diff --git a/alliance/share/tutorials/addaccu/addaccu.c b/alliance/share/tutorials/addaccu/addaccu.c
deleted file mode 100644
index a86b02e0..00000000
--- a/alliance/share/tutorials/addaccu/addaccu.c
+++ /dev/null
@@ -1,68 +0,0 @@
-#include <genlib.h>
-
-main()
-{
-int i;
-
-   GENLIB_DEF_LOFIG("addaccu");
-
-   GENLIB_LOCON("a[0:3]",  IN,  "a[0:3]"); /* input bus a       */
-   GENLIB_LOCON("b[0:3]",  IN,  "b[0:3]"); /* input bus b       */
-   GENLIB_LOCON("sel",     IN,  "sel"   ); /* selection switch  */
-   GENLIB_LOCON("ck",      IN,  "ck"    ); /* clock             */
-   GENLIB_LOCON("vdd",     IN,  "vdd"   ); /* core power supply */
-   GENLIB_LOCON("vss",     IN,  "vss"   ); /* core ground       */
-   GENLIB_LOCON("vdde",    IN,  "vdde"  ); /* pads power supply */
-   GENLIB_LOCON("vsse",    IN,  "vsse"  ); /* pads ground       */
-   GENLIB_LOCON("s[0:3]",  OUT, "s[0:3]"); /* output            */
-
-/*
-   power supplies:
-   pxxxe_p are external power supplies, ie used only by the buffers
-       inside the pads.
-   pxxxi_p are internal power supplies, for core logic only.
-*/
-
-   GENLIB_LOINS ("pvsse_sp", "p15", "cki", "vdde", "vdd", "vsse", "vss", 0);
-   GENLIB_LOINS ("pvdde_sp", "p16", "cki", "vdde", "vdd", "vsse", "vss", 0);
-   GENLIB_LOINS ("pvddeck_sp", "p17", "clock", "cki", "vdde", "vdd", "vsse", "vss", 0);
-   GENLIB_LOINS ("pvssi_sp", "p18", "cki", "vdde", "vdd", "vsse", "vss", 0);
-   GENLIB_LOINS ("pvddi_sp", "p19", "cki", "vdde", "vdd", "vsse", "vss", 0);
-
-/*
-   core to pads connections are point to point connections in the case
-   of this circuit, because no three state ouput pads are used.
-   We use a loop to avoid copy/paste kind of things that may lead to
-   errors easilly.
-*/
-   for (i = 0; i < 4; i++)
-    GENLIB_LOINS("pi_sp", GENLIB_NAME("p%d", i), 
-          GENLIB_NAME("a[%d]", i), GENLIB_NAME("aa[%d]", i), 
-          "cki", "vdde", "vdd", "vsse", "vss", 0);
-
-   for (i = 0; i < 4; i++)
-    GENLIB_LOINS("pi_sp", GENLIB_NAME("p%d", i + 4), 
-          GENLIB_NAME("b[%d]", i), GENLIB_NAME("bb[%d]", i), 
-          "cki", "vdde", "vdd", "vsse", "vss", 0);
-
-   for (i = 0; i < 4; i++)
-    GENLIB_LOINS("po_sp", GENLIB_NAME("p%d", i + 8), 
-          GENLIB_NAME("ss[%d]", i), GENLIB_NAME("s[%d]", i),
-          "cki", "vdde", "vdd", "vsse", "vss", 0);
-
-
-   GENLIB_LOINS("pi_sp", "p12",
-         "sel", "selsel",
-         "cki", "vdde", "vdd", "vsse", "vss", 0);
-
-   GENLIB_LOINS("pck_sp", "p13",
-         "ck",
-         "cki", "vdde", "vdd", "vsse", "vss", 0);
-
-   GENLIB_LOINS("core", "core",
-         "aa[0:3]", "bb[0:3]", "selsel", "clock", "ss[0:3]",
-         "vdd", "vss", 0);
-
-   GENLIB_SAVE_LOFIG();
-   exit(0); /* necessary for the proper run of the Makefile */
-}
diff --git a/alliance/share/tutorials/addaccu/addaccu.pat b/alliance/share/tutorials/addaccu/addaccu.pat
deleted file mode 100644
index fdc265cf..00000000
--- a/alliance/share/tutorials/addaccu/addaccu.pat
+++ /dev/null
@@ -1,27 +0,0 @@
-in vdde ;
-in vsse ;
-in vdd;
-in vss;
-in a(3 to 0);
-in b(3 to 0);
-in sel;;
-in ck;;;
-out s(3 to 0);
-begin
-
-# a=0, b=3, sel=direct input, we expect value 3 on s
-pat_1 : 1 0 1 0  0000  0011  0 0  ?0011 ;
-# a=1, b=3, sel=direct input, we expect value 4 on s
-pat_2 : 1 0 1 0  0001  0011  0 0  ?0100 ;
-# a=7, b=3, sel=direct input, we expect value bin 1010 on s
-pat_3 : 1 0 1 0  0111  0011  0 0  ?1010 ;
-# a=7, b=3, sel=direct input, we set ck to 1, we still expect bin 1010 on s 
-pat_4 : 1 0 1 0  0111  0011  0 1  ?1010 ;
-# when ck falls to 0, the computed value (7+3=bin 1010) is stored in accu
-pat_5 : 1 0 1 0  0111  0011  0 0  ?1010 ;
-# if we choose sel=accu output, we expect value bin 1010 + 4= bin 1110 on s 
-# even if a=1111
-pat_6 : 1 0 1 0  1111  0100  1 0  ?1110 ;
-# back to normal mode, 5+4=9
-pat_7 : 1 0 1 0  0101  0100  0 0  **** ;
-end;
diff --git a/alliance/share/tutorials/addaccu/addaccu.pdf b/alliance/share/tutorials/addaccu/addaccu.pdf
deleted file mode 100644
index e52b939f..00000000
Binary files a/alliance/share/tutorials/addaccu/addaccu.pdf and /dev/null differ
diff --git a/alliance/share/tutorials/addaccu/addaccu.ps b/alliance/share/tutorials/addaccu/addaccu.ps
deleted file mode 100644
index d50f020a..00000000
--- a/alliance/share/tutorials/addaccu/addaccu.ps
+++ /dev/null
@@ -1,2091 +0,0 @@
-%!PS-Adobe-2.0
-%%Creator: dvips(k) 5.85 Copyright 1999 Radical Eye Software
-%%Title: addaccu.dvi
-%%Pages: 28
-%%PageOrder: Ascend
-%%BoundingBox: 0 0 596 842
-%%DocumentFonts: Palatino-Roman Palatino-Bold Courier-Bold
-%%+ Palatino-Italic Palatino-BoldItalic Courier-Oblique Courier
-%%EndComments
-%DVIPSWebPage: (www.radicaleye.com)
-%DVIPSCommandLine: dvips addaccu.dvi -o addaccu.ps
-%DVIPSParameters: dpi=600, compressed
-%DVIPSSource:  TeX output 2000.01.20:1132
-%%BeginProcSet: texc.pro
-%!
-/TeXDict 300 dict def TeXDict begin/N{def}def/B{bind def}N/S{exch}N/X{S
-N}B/A{dup}B/TR{translate}N/isls false N/vsize 11 72 mul N/hsize 8.5 72
-mul N/landplus90{false}def/@rigin{isls{[0 landplus90{1 -1}{-1 1}ifelse 0
-0 0]concat}if 72 Resolution div 72 VResolution div neg scale isls{
-landplus90{VResolution 72 div vsize mul 0 exch}{Resolution -72 div hsize
-mul 0}ifelse TR}if Resolution VResolution vsize -72 div 1 add mul TR[
-matrix currentmatrix{A A round sub abs 0.00001 lt{round}if}forall round
-exch round exch]setmatrix}N/@landscape{/isls true N}B/@manualfeed{
-statusdict/manualfeed true put}B/@copies{/#copies X}B/FMat[1 0 0 -1 0 0]
-N/FBB[0 0 0 0]N/nn 0 N/IEn 0 N/ctr 0 N/df-tail{/nn 8 dict N nn begin
-/FontType 3 N/FontMatrix fntrx N/FontBBox FBB N string/base X array
-/BitMaps X/BuildChar{CharBuilder}N/Encoding IEn N end A{/foo setfont}2
-array copy cvx N load 0 nn put/ctr 0 N[}B/sf 0 N/df{/sf 1 N/fntrx FMat N
-df-tail}B/dfs{div/sf X/fntrx[sf 0 0 sf neg 0 0]N df-tail}B/E{pop nn A
-definefont setfont}B/Cw{Cd A length 5 sub get}B/Ch{Cd A length 4 sub get
-}B/Cx{128 Cd A length 3 sub get sub}B/Cy{Cd A length 2 sub get 127 sub}
-B/Cdx{Cd A length 1 sub get}B/Ci{Cd A type/stringtype ne{ctr get/ctr ctr
-1 add N}if}B/id 0 N/rw 0 N/rc 0 N/gp 0 N/cp 0 N/G 0 N/CharBuilder{save 3
-1 roll S A/base get 2 index get S/BitMaps get S get/Cd X pop/ctr 0 N Cdx
-0 Cx Cy Ch sub Cx Cw add Cy setcachedevice Cw Ch true[1 0 0 -1 -.1 Cx
-sub Cy .1 sub]/id Ci N/rw Cw 7 add 8 idiv string N/rc 0 N/gp 0 N/cp 0 N{
-rc 0 ne{rc 1 sub/rc X rw}{G}ifelse}imagemask restore}B/G{{id gp get/gp
-gp 1 add N A 18 mod S 18 idiv pl S get exec}loop}B/adv{cp add/cp X}B
-/chg{rw cp id gp 4 index getinterval putinterval A gp add/gp X adv}B/nd{
-/cp 0 N rw exit}B/lsh{rw cp 2 copy get A 0 eq{pop 1}{A 255 eq{pop 254}{
-A A add 255 and S 1 and or}ifelse}ifelse put 1 adv}B/rsh{rw cp 2 copy
-get A 0 eq{pop 128}{A 255 eq{pop 127}{A 2 idiv S 128 and or}ifelse}
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-Fe(alliance-support@lip6.fr)p Fk(.)1907 6122 y(28)p eop
-%%Trailer
-end
-userdict /end-hook known{end-hook}if
-%%EOF
diff --git a/alliance/share/tutorials/addaccu/addaccu.rin b/alliance/share/tutorials/addaccu/addaccu.rin
deleted file mode 100644
index be8123c3..00000000
--- a/alliance/share/tutorials/addaccu/addaccu.rin
+++ /dev/null
@@ -1,7 +0,0 @@
-west (p0 p1 p2 p3 p4)
-
-north (p5 p6 p7 p8 p9)
-
-east (p10 p11 p12 p13)
-
-south (p15 p16 p18 p19 p17)
diff --git a/alliance/share/tutorials/addaccu/addaccu.vbe b/alliance/share/tutorials/addaccu/addaccu.vbe
deleted file mode 100644
index f51eb121..00000000
--- a/alliance/share/tutorials/addaccu/addaccu.vbe
+++ /dev/null
@@ -1,56 +0,0 @@
-ENTITY addaccu IS
-
-PORT( 
-  a                    : in BIT_VECTOR(0 TO 3) ;
-  b                    : in BIT_VECTOR(0 TO 3) ;
-  sel                  : in BIT ;
-  ck                   : in BIT ;
-  s                    : out BIT_VECTOR(0 TO 3) ; 
-  vdd, vss, vdde, vsse : in BIT
-);
-
-END addaccu;
-
-ARCHITECTURE fonctional OF addaccu IS
-
-SIGNAL outmux, outreg, sum : BIT_VECTOR(0 TO 3) ;
-SIGNAL carry               : BIT_VECTOR(0 TO 2) ;
-SIGNAL reg                 : REG_VECTOR(0 TO 3) REGISTER;
-
-BEGIN
-
-ASSERT(vdd = '1' and vss = '0')
-   REPORT "Wrong power supplies"
-   SEVERITY WARNING;
-
-ASSERT(vdde = '1' and vsse = '0')
-   REPORT "Wrong power external supplies"
-   SEVERITY WARNING;
-
-  WITH sel SELECT
-    outmux <= a WHEN '0', outreg WHEN '1' ;
-
-  sum(0) <= outmux(0) xor b(0) ;
-  carry(0) <= outmux(0) and b(0) ;
-
-  sum(1) <= outmux(1) xor b(1) xor carry(0) ;
-  carry(1) <= (outmux(1) and b(1)) or
-              (outmux(1) and carry(0)) or
-              (b(1) and carry(0)) ;
-
-  sum(2) <= outmux(2) xor b(2) xor carry(1) ;
-  carry(2) <= (outmux(2) and b(2)) or
-              (outmux(2) and carry(1)) or
-              (b(2) and carry(1)) ;
-
-  sum(3) <= outmux(3) xor b(3) xor carry(2) ;
-
-  s <= sum;
-
-  L0 : BLOCK ((ck = '0') and not ck'STABLE)
-     BEGIN
-     reg <= GUARDED not sum ;
-  END BLOCK ;
-
-  outreg <= not reg;
-END; 
diff --git a/alliance/share/tutorials/addaccu/addaccue.inf b/alliance/share/tutorials/addaccu/addaccue.inf
deleted file mode 100644
index dded4133..00000000
--- a/alliance/share/tutorials/addaccu/addaccue.inf
+++ /dev/null
@@ -1,6 +0,0 @@
-rename
-core.l0.dff_s_reg.sff_m : reg(0);
-core.l1.dff_s_reg.sff_m : reg(1);
-core.l2.dff_s_reg.sff_m : reg(2);
-core.l3.dff_s_reg.sff_m : reg(3);
-end
diff --git a/alliance/share/tutorials/addaccu/core.c b/alliance/share/tutorials/addaccu/core.c
deleted file mode 100644
index 150f453d..00000000
--- a/alliance/share/tutorials/addaccu/core.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
-   genlib.h is required for all genlib programs.
-   it defines the set of functions we will use for schematic capture
-*/
-#include <genlib.h>
-
-/*
-   core.c is to become the `core' executable program. So we must
-   define a main procedure main()
-*/
-
-main()
-{
-int i; /* We will build regular structure using a loop,  i is its index */
-
-/*
-   When executed,  the addaccu program opens the netlist view 
-   "core". Operations performed after opening "accu" are
-   taken into account.
-*/
-
-   GENLIB_DEF_LOFIG("core");
-
-/*
-   The description of the addaccu netlist begins with the
-   instanciation of input/output terminals
-*/
-
-/*
-   We start with the input terminals.
-   Note that `a[0:3]' defines a[0],  a[1],  a[2] and a[3] as if three
-   calls to `GENLIB_LOCON' had been performed.
-   Only signals and connectors can be vectorized.
-*/
-   GENLIB_LOCON("a[0:3]",   IN,  "a[0:3]");  /* input bus a      */
-   GENLIB_LOCON("b[0:3]",   IN,  "b[0:3]");  /* input bus b      */
-   GENLIB_LOCON("sel",      IN,  "sel"   );  /* selection switch */
-   GENLIB_LOCON("ck",       IN,  "ck"    );  /* clock            */
-
-/*
-   Then,  the output terminals.
-*/
-
-   GENLIB_LOCON("s[0:3]", INOUT, "s[0:3]"); /* output bus       */
-
-/*
-   Then the supplies.
-   They are inputs, but we like them better at the end of the
-   description.
-*/
-   GENLIB_LOCON("vdd",      IN,  "vdd"   );  /* power supply     */
-   GENLIB_LOCON("vss",      IN,  "vss"   );  /* ground           */
-
-/*
-   Now we describe the circuit's schematic in instanciating
-   standard cells.
-
-*/
-
-/*
-   bit 0
-*/
-   GENLIB_LOINS("xr2_y", "xr0",
-         "mux[0]", "b[0]", "s[0]",
-         "vdd", "vss", 0);
- 
-   GENLIB_LOINS("a2_y", "an0",
-         "mux[0]", "b[0]", "carry[0]",
-         "vdd", "vss", 0);
- 
-/*
-    bit 1
-*/
- 
-   GENLIB_LOINS("xr2_y", "xr1",
-         "mux[1]", "b[1]", "int[1]",
-         "vdd", "vss", 0);
- 
-   GENLIB_LOINS("xr2_y", "xr2",
-         "int[1]", "carry[0]", "s[1]",
-         "vdd", "vss", 0);
- 
-   GENLIB_LOINS("a2_y",  "an1",
-         "mux[1]", "b[1]", "int[2]",
-         "vdd", "vss", 0);
- 
-   GENLIB_LOINS("a2_y",  "an2",
-         "mux[1]", "carry[0]", "int[3]",
-         "vdd", "vss", 0);
- 
-   GENLIB_LOINS("a2_y",  "an3",
-         "b[1]", "carry[0]", "int[4]",
-         "vdd", "vss", 0);
- 
-   GENLIB_LOINS("o3_y",  "an4",
-         "int[2]", "int[3]", "int[4]", "carry[1]",
-         "vdd", "vss", 0);
- 
-/*
-   bit 2
-*/
- 
-   GENLIB_LOINS("xr2_y", "xr3",
-         "mux[2]", "b[2]", "int[5]",
-         "vdd", "vss", 0);
- 
-   GENLIB_LOINS("xr2_y", "xr4",
-         "int[5]", "carry[1]", "s[2]",
-         "vdd", "vss", 0);
- 
-   GENLIB_LOINS("a2_y",  "an5",
-         "mux[2]", "b[2]", "int[6]",
-         "vdd", "vss", 0);
- 
-   GENLIB_LOINS("a2_y",  "an6",
-         "mux[2]", "carry[1]", "int[7]",
-         "vdd", "vss", 0);
- 
-   GENLIB_LOINS("a2_y",  "an7",
-         "b[2]", "carry[1]", "int[8]",
-         "vdd", "vss", 0);
- 
-   GENLIB_LOINS("o3_y",  "an8",
-         "int[6]", "int[7]", "int[8]", "carry[2]",
-         "vdd", "vss", 0);
- 
-/*
-   bit 3
-*/
-   GENLIB_LOINS("xr2_y", "xr5",
-         "mux[3]", "b[3]", "int[9]",
-         "vdd", "vss", 0);
- 
-   GENLIB_LOINS("xr2_y", "xr6",
-         "int[9]", "carry[2]", "s[3]",
-         "vdd", "vss", 0);
- 
-/*
-   mux 2 to 1
-*/
-   GENLIB_LOINS("n1_y",  "n10", "sel", "nsel", "vdd", "vss", 0);
-
-/*
-  The `GENLIB_NAME' function allows to indice a name automatically
-*/
-   for (i = 0; i < 4; i++) {
-     GENLIB_LOINS("mx2_y", GENLIB_NAME("mux%d", i),
-            GENLIB_NAME("a[%d]", i), "nsel", GENLIB_NAME("regout[%d]", i),
-            "sel", GENLIB_NAME("mux[%d]", i),
-            "vdd", "vss", 0);
-
-     GENLIB_LOINS("msdp2_y",  GENLIB_NAME("l%d", i),
-           GENLIB_NAME("s[%d]", i), "ck", GENLIB_NAME("regout[%d]", i),
-           "vdd", "vss", 0);
-   }
-
-   GENLIB_SAVE_LOFIG();
-   exit(0); /* necessary for the proper run of the Makefile */
-}
diff --git a/alliance/share/tutorials/addaccu/genvect.c b/alliance/share/tutorials/addaccu/genvect.c
deleted file mode 100644
index 624ef8dd..00000000
--- a/alliance/share/tutorials/addaccu/genvect.c
+++ /dev/null
@@ -1,111 +0,0 @@
-#include <genpat.h>
-#include <stdio.h>
-/*#include <mut315.h> */
-
-char *
-inttostr (entier)
-     int entier;
-{
-  char *str;
-  str = (char *) mbkalloc (32 * sizeof (char));
-  sprintf (str, "%d", entier);
-  return (str);
-}
-/*------------------------------*/
-	/* end of the description       */
-/*------------------------------*/
-main ()
-{
-  int i;
-  int j;
-  int numvect;
-  int CKcour;
-  int test;
-  numvect = 0;
-  test = 0;
-  CKcour = 0;
-
-
-  DEF_GENPAT ("genvect");
-
-
-/* Declaration de l'interface */
-
-  DECLAR ("A", ":2", "X", IN, "3 downto 0");
-  DECLAR ("B", ":2", "X", IN, "3 downto 0");
-  DECLAR ("SEL", ":2", "B", IN, "");
-  DECLAR ("s", ":2", "X", OUT, "3 downto 0");
-  DECLAR ("CK", ":2", "B", IN, "");
-  DECLAR ("vdd", ":2", "B", IN, "");
-  DECLAR ("vss", ":2", "B", IN, "");
-  LABEL ("additionneur");
-  AFFECT ("0", "SEL", "0b0");
-  AFFECT ("0", "A", "0X0");
-  AFFECT ("0", "vdd", "0b1");
-  AFFECT ("0", "vss", "0b0");
-  AFFECT ("0", "B", "0X0");
-/* Boucle d'affectation des vecteurs */
-
-  while (numvect < 768)
-    {
-      if (test == 1)
-	{
-	  AFFECT (inttostr (numvect), "A", inttostr (i));
-	  AFFECT (inttostr (numvect), "B", inttostr (j));
-	  AFFECT (inttostr (numvect), "CK", "0b1");
-	  CKcour = 1;
-	  numvect++;
-	  if (j == 16)
-	    i++;
-	  if (j == 16)
-	    j = 0;
-	  else
-	    j++;
-	  test = 0;
-	}
-      else
-	{
-	  if (CKcour == 0 && test == 0)
-	    test = 1;
-	  AFFECT (inttostr (numvect), "CK", "0b0");
-	  CKcour = 0;
-	  numvect++;
-	}
-    }
-  i = 0;
-  j = 0;
-  AFFECT (inttostr (numvect), "SEL", "0b1");
-
-/* Boucle d'affectation des vecteurs */
-
-
-  while (numvect < 1536)
-    {
-      if (test == 1)
-	{
-	  AFFECT (inttostr (numvect), "A", inttostr (i));
-	  AFFECT (inttostr (numvect), "B", inttostr (j));
-	  AFFECT (inttostr (numvect), "CK", "0b1");
-	  CKcour = 1;
-	  numvect++;
-	  if (j == 16)
-	    i++;
-	  if (j == 16)
-	    j = 0;
-	  else
-	    j++;
-	  test = 0;
-	}
-      else
-	{
-	  if (CKcour == 0 && test == 0)
-	    test = 1;
-	  AFFECT (inttostr (numvect), "CK", "0b0");
-	  numvect++;
-	  CKcour = 0;
-	}
-    }
-
-  SAV_GENPAT ();
-}
-
diff --git a/alliance/share/tutorials/addaccu/tex/Makefile b/alliance/share/tutorials/addaccu/tex/Makefile
deleted file mode 100644
index 1fa654fd..00000000
--- a/alliance/share/tutorials/addaccu/tex/Makefile
+++ /dev/null
@@ -1,24 +0,0 @@
-# Generic Makefile for TeTeX projet
-# (C) 1999, Czo
-# $Id: Makefile,v 1.1 2000/01/20 16:09:58 czo Exp $
-
-MYFILE=addaccu
-
-%.eps : %.fig
-	fig2dev -L ps -c -p dummy $*.fig $*.eps
-
-view : ps
-	gv $(MYFILE).ps
-        
-ps   : $(MYFILE).tex
-	latex $(MYFILE).tex
-	dvips $(MYFILE).dvi -o $(MYFILE).ps
-
-distrib : clean ps        
-	ps2pdf $(MYFILE).ps
-	cp -f $(MYFILE).ps ..
-	cp -f $(MYFILE).pdf ..
-	$(MAKE) clean
-
-clean :
-	rm -f $(MYFILE).ps $(MYFILE).pdf *.log *.dvi *.aux
diff --git a/alliance/share/tutorials/addaccu/tex/addaccu.eps b/alliance/share/tutorials/addaccu/tex/addaccu.eps
deleted file mode 100644
index 8b116d1b..00000000
--- a/alliance/share/tutorials/addaccu/tex/addaccu.eps
+++ /dev/null
@@ -1,197 +0,0 @@
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-n 1126 2116 m 1576 2116 l  gs col-1 s gr 
-% Polyline
-n 901 811 m 2206 811 l  gs col-1 s gr 
-/Courier-Bold findfont 180.00 scalefont setfont
-225 855 m
-gs 1 -1 sc (b[3:0]) col-1 show gr
-/Courier-Bold findfont 180.00 scalefont setfont
-225 3330 m
-gs 1 -1 sc (ck) col-1 show gr
-/Courier-Bold findfont 180.00 scalefont setfont
-4185 1395 m
-gs 1 -1 sc (s[3:0]) col-1 show gr
-/Courier-Bold findfont 180.00 scalefont setfont
-4230 585 m
-gs 1 -1 sc (cout) col-1 show gr
-/Courier-Bold findfont 180.00 scalefont setfont
-225 1800 m
-gs 1 -1 sc (a[3:0]) col-1 show gr
-/Courier-Bold findfont 180.00 scalefont setfont
-225 1395 m
-gs 1 -1 sc (sel) col-1 show gr
-% Polyline
-n 2881 1351 m 4141 1351 l  gs col-1 s gr 
-$F2psEnd
-restore
diff --git a/alliance/share/tutorials/addaccu/tex/addaccu.fig b/alliance/share/tutorials/addaccu/tex/addaccu.fig
deleted file mode 100644
index 279845b1..00000000
--- a/alliance/share/tutorials/addaccu/tex/addaccu.fig
+++ /dev/null
@@ -1,88 +0,0 @@
-#FIG 3.1
-Portrait
-Center
-Metric
-1200 2
-6 1214 1214 1574 1529
-1 3 0 1 -1 -1 5 0 0 0.0000000 1 0.000 1532 1352 37 37 1532 1352 1558 1379
-2 1 0 1 -1 -1 5 0 0 0.000 0 0 7 0 0 4
-	 1488 1353 1217 1217 1217 1487 1488 1353
--6
-6 1619 1529 1934 2294
-2 2 0 1 -1 -1 10 0 20 0.000 0 0 7 0 0 5
-	 1622 1532 1892 1532 1892 2252 1622 2252 1622 1532
-2 1 0 1 -1 -1 10 0 20 0.000 0 0 7 0 0 3
-	 1622 1532 1892 1892 1622 2252
--6
-6 2249 404 2969 2294
-2 1 0 1 -1 -1 10 0 20 0.000 0 0 7 0 0 8
-	 2252 1553 2252 2273 2927 1553 2927 1103 2252 428 2252 1103
-	 2522 1328 2252 1553
-4 0 -1 10 0 14 12 0.0000000 4 75 105 2657 1426 +\001
--6
-6 1259 1169 1619 1484
-1 3 0 1 -1 -1 10 0 20 0.0000000 1 0.000 1578 1308 37 37 1578 1308 1604 1335
-2 1 0 1 -1 -1 10 0 20 0.000 0 0 7 0 0 4
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--6
-2 1 0 1 -1 7 0 0 -1 0.000 0 0 -1 0 0 2
-	 1846 1936 2206 1936
-2 1 0 1 -1 7 0 0 -1 0.000 0 0 -1 0 0 1
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-	 2881 1351 4141 1351
-2 1 0 1 -1 7 0 0 -1 0.000 0 0 -1 0 0 2
-	 901 811 2206 811
-2 1 0 1 -1 7 0 0 -1 0.000 0 0 -1 0 0 2
-	 1126 2116 1576 2116
-2 1 0 1 -1 7 0 0 -1 0.000 0 0 -1 0 0 2
-	 901 1756 1576 1756
-2 1 0 1 -1 7 0 0 -1 0.000 0 0 -1 0 0 3
-	 1126 2116 1126 2791 2206 2791
-2 1 0 1 -1 7 0 0 -1 0.000 0 0 -1 0 0 3
-	 2476 2791 3556 2791 3556 1351
-2 1 0 1 -1 7 0 0 -1 0.000 0 0 -1 0 0 3
-	 901 3286 2341 3286 2341 3151
-2 1 0 1 -1 7 0 0 -1 0.000 0 0 -1 0 0 3
-	 2566 856 2566 541 4141 541
-2 1 0 1 -1 7 0 0 -1 0.000 0 0 -1 0 0 3
-	 1711 1576 1711 1351 1576 1351
-2 1 0 1 -1 7 0 0 -1 0.000 0 0 -1 0 0 2
-	 1216 1351 901 1351
-2 2 0 1 -1 -1 5 0 0 0.000 0 0 7 0 0 5
-	 1576 1576 1846 1576 1846 2296 1576 2296 1576 1576
-2 2 0 1 -1 -1 10 0 20 0.000 0 0 7 0 0 5
-	 2253 2388 2523 2388 2523 3108 2253 3108 2253 2388
-2 1 0 1 -1 -1 0 0 -1 0.000 0 0 7 1 0 2
-	1 1 1.00 60.00 120.00
-	 2340 2565 2340 2790
-2 1 0 1 -1 -1 1 0 -1 0.000 0 0 7 0 0 3
-	 1576 1576 1846 1936 1576 2296
-2 1 0 1 -1 -1 3 0 0 0.000 0 0 7 0 0 4
-	 2252 2522 2342 2522 2342 2927 2432 2927
-2 2 0 1 -1 -1 4 0 0 0.000 0 0 7 0 0 5
-	 2207 2432 2477 2432 2477 3152 2207 3152 2207 2432
-2 1 0 1 -1 -1 3 0 -1 0.000 0 0 7 0 0 3
-	 2207 3152 2342 2972 2477 3152
-2 1 0 1 -1 -1 5 0 0 0.000 0 0 7 0 0 8
-	 2206 1597 2206 2317 2881 1597 2881 1147 2206 472 2206 1147
-	 2476 1372 2206 1597
-2 1 0 1 -1 7 0 0 -1 0.000 0 0 -1 0 0 3
-	 2476 2790 3556 2790 3556 1350
-2 1 0 3 7 7 2 0 20 0.000 0 0 -1 0 0 2
-	 2476 2790 2745 2790
-2 1 0 3 7 7 2 0 20 0.000 0 0 -1 0 0 2
-	 2881 1350 3150 1350
-2 1 0 3 7 7 2 0 20 0.000 0 0 -1 0 0 2
-	 1846 1935 2115 1935
-2 1 0 3 7 7 2 0 20 0.000 0 0 -1 0 0 2
-	 2565 855 2565 586
-2 1 0 3 7 7 2 0 20 0.000 0 0 -1 0 0 2
-	 1576 1350 1845 1350
-4 0 -1 0 0 14 12 0.0000000 4 165 630 225 855 b[3:0]\001
-4 0 -1 0 0 14 12 0.0000000 4 135 210 225 3330 ck\001
-4 0 -1 0 0 14 12 0.0000000 4 165 630 4185 1395 s[3:0]\001
-4 0 -1 0 0 14 12 0.0000000 4 120 420 4230 585 cout\001
-4 0 -1 0 0 14 12 0.0000000 4 165 630 225 1800 a[3:0]\001
-4 0 -1 0 0 14 12 0.0000000 4 135 315 225 1395 sel\001
-4 0 -1 1 0 14 18 0.0000000 4 150 165 2565 1440 +\001
diff --git a/alliance/share/tutorials/addaccu/tex/addaccu.tex b/alliance/share/tutorials/addaccu/tex/addaccu.tex
deleted file mode 100644
index 766c48bf..00000000
--- a/alliance/share/tutorials/addaccu/tex/addaccu.tex
+++ /dev/null
@@ -1,1590 +0,0 @@
-%%%%%%%%%%%%%%%%%%%%
-%
-% The addaccu tutorial.
-% Original Version 1.0 in text form by Francois Pecheux
-% Version for Alliance releases 2.0 and up by Frederic Petrot
-% Modified by czo for Alliance release 4.0 (01/2000)
-% TODO : no fully working, needs some adjustements
-% $Id: addaccu.tex,v 1.1 2000/01/20 16:09:58 czo Exp $
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\documentclass{article}
-\usepackage{palatino,doublespace,here,psfig,fancybox}
-\textwidth 15cm
-\textheight 23cm
-\oddsidemargin  +0.75cm
-\evensidemargin -0.75cm
-\setstretch{1.2}
-%%%%%%%%%%%%%%%
-% Setting the width of the verbatim parts according to 80 tt chars
-% Since it is tt, any char is fine
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\newlength{\verbatimbox}
-\settowidth{\verbatimbox}{\scriptsize\tt 
-xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
-}
-\newenvironment{framedverbatim}
- {\VerbatimEnvironment\par\noindent\scriptsize
-  \begin{Sbox}\begin{minipage}{\verbatimbox}\begin{Verbatim}}%
- {\end{Verbatim}\end{minipage}\end{Sbox}
-  \setlength{\fboxsep}{3mm}\center\shadowbox{\TheSbox}\normalsize\par\noindent}
-\newenvironment{phraseverbatim}
- {\VerbatimEnvironment\par\vspace*{2mm}\noindent\footnotesize
-  \begin{Sbox}\begin{minipage}{.979\textwidth}\begin{Verbatim}}%
- {\end{Verbatim}\end{minipage}\end{Sbox}\setlength{\shadowsize}{2pt}%
- \shadowbox{\TheSbox}\normalsize\par\noindent}
- 
- 
-
-%%%%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\begin{document}
-
-\begin{center}
-\Huge First steps in using \bf Alliance\\
-\Huge the \texttt{addaccu} tutorial
-\end{center}
-\vspace{2cm}
-\begin{center}
-Abstract
-
-\begin{quote}
-\em
-This tutorial introduces the design flow to be used in the
-\textbf{Alliance} CAD framework for the design and verification of a 
-standard cells circuit, including the pads.
-Each step of the desgin flow is supported by one or more specific 
-tools, whose use is briefly explained.
-
-This text is meant to be simple and comprehensive, and is to be used
-to get \emph{into} the system.
-Should something be unclear or wrong, please indicate this by sending
-an e-mail to \texttt{alliance-support@lip6.fr}.
-\rm
-\end{quote}
-\end{center}
-
-%%%%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\section{Introduction}
-
-In this tutorial, you will learn the practical use of some basic
-\textbf{Alliance} tools by building a very simple circuit from scratch.
-It is recommended that you read the \texttt{overview.ps} file before
-proceeding, as it describes the main steps of the design conceptually.
-
-Before we proceed to the tutorial, you must make sure that the
-\textbf{Alliance} tools are readilly available when invoking them at the 
-prompt.
-The prompt in represented in the following text by the symbol~:
-\begin{phraseverbatim}
-~fred/addaccu %-)
-\end{phraseverbatim}
-In this system, \texttt{fred} is the user, \texttt{addaccu} is the current
-directory, and \texttt{\%-)} is supposed to give us courage!
-
-Try issuing the following command to check that \textbf{Alliance} is
-correctly installed:
-
-\begin{phraseverbatim}
-~fred/addaccu %-) yagle
-\end{phraseverbatim}
-
-If everything is working, you get the following result:
-
-\begin{framedverbatim}
-YAGLE 2.00
-Usage   : yagle [options] <file1> [file2]
-Options : -i     reads the '.inf' file
-          -v     vectorises the vhdl description
-          -p=n   n is the depth for functional analysis
-          -nc    no detection of complex gates
-          -nl    no latch detection
-          -fcl   transistor netlist detection
-          -elp   use the technology file '.elp'
-          -d     generates a .cns file
-          -b     transistor orientation
-          -z     functional analysis through HZ nodes
-          -os    only one vdd and vss in the vhdl description
-          -nh    generates a hierarchical cone netlist
-          file2  is the vhdl file to be generated (default is file1)
-          -t     display execution trace
-\end{framedverbatim}
-
-If it does not work, please abort the tutorial and fix the pathnames.
-
-We will assume that the user is running a \texttt{c-like} shell, like
-\texttt{csh} or \texttt{tcsh}.
-If you run a \texttt{sh-like} shell, please refer to your
-documentation.
-
-Typically do:
-
-\begin{phraseverbatim}
-~fred/addaccu %-) setenv ALLIANCE_TOP  /usr/local/cad/alliance
-~fred/addaccu %-) setenv PATH $ALLIANCE_TOP/bin:$PATH
-\end{phraseverbatim}
-Where we assume that \textbf{Alliance} has been installed under
-\texttt{/usr/local/cad/alliance} directory.
-In the sequel, we will assume that the \verb+$ALLIANCE_TOP+ variable is
-properly set up.
-
-All the tools used in this tutorial are documented at least with a
-manual page.
-Each manual can be accessed using the \texttt{man \it tool} command.
-You may have to do a:
-\small
-\begin{phraseverbatim}
-~fred/addaccu %-) setenv MANPATH $ALLIANCE_TOP/man:$MANPATH
-\end{phraseverbatim}
-\normalsize
-in order to have the manual accessible.
-
-The tutorial is organized around the following sections:
-\begin{itemize}
-\item Chip overview (page~\pageref{chip});
-\item Design flow (page~\pageref{desginflow});
-\item Execution environment set-up (page~\pageref{setup});
-\item Behavioral capture and simulation (page~\pageref{beh});
-\item Netlist capture (page~\pageref{netlist});
-\item Core layout generation (page~\pageref{layout});
-\item Core layout verification (page~\pageref{lv});
-\item Core to pads routing (page~\pageref{pads});
-\item Chip visualization (page~\pageref{graal});
-\item Functional abstraction (page~\pageref{fa});
-\item Further verifications (page~\pageref{verif});
-\item Symbolic to real technology conversion (page~\pageref{sr}).
-\end{itemize}
-
-
-%%%%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\section{Chip overview}
-\label{chip}
-The picture in the Figure~\ref{archi} shows the architecture of the 
-small chip that will be our example all along this tutorial.
-As you can see, the circuit is pretty small: it mostly consists in a 
-four bit adder, a four bit register, and a 2 to 1 four bit multiplexer.
-
-\begin{figure}\center
-\leavevmode\psfig{figure=addaccu.eps,width=8cm,angle=-90}
-\caption{\label{archi}Architecture of the \texttt{addaccu} circuit.}
-\end{figure}
-
-Inputs are located on the left side of the picture, and outputs are 
-located on the right side.
-We did not represent the power supplies on this schematic, but you'll
-need them in order for the chip to work!
-
-The circuit performs an addition between either the \texttt{b[3:0]} and 
-\texttt{a[3:0]} inputs when \texttt{sel} is set to 0, or between
-\texttt{b[3:0]} and the contents of the four bit register when \texttt{sel} 
-is set to 1.
-The content of the register is overwriten by the value of the outputs 
-\texttt{s[3:0]} on each falling edge of the clock, \texttt{ck}.
-
-%%%%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\section{Design flow}
-\label{desginflow}
-
-You are now ready to actually design the chip and use the
-\textbf{Alliance} tools.
-The design flow for this little example is composed of 5 main 
-steps:
-\begin{enumerate}
-\item behavioral capture and simulation;
-\item netlist capture and validation;
-\item physical layout generation;
-\item design validation;
-\item symbolic to real conversion.
-\end{enumerate}
-
-As you will see, points 2 and 3 must be performed for each level of 
-hierarchy.
-In this example we distinguish two levels of hierarchy: the core 
-level and the chip level.
-At the core level, the leaf cells of the design belong to the
-\textbf{Alliance} standard cells library.
-At the chip level, the previous core and pads belonging to the
-\textbf{Alliance} pad library are used.
-
-The Figure~\ref{hier} below describes the circuit's hierarchy.
-
-\begin{figure}\center
-\leavevmode\psfig{figure=hierarchy.eps,width=14cm}
-\caption{\label{hier}Hierarchical partitionning.}
-\end{figure}
-
-%%%%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\section{Execution environment set-up}
-\label{setup}
-
-Before you start examining the first phase of the design methodology, 
-you first have to set up an execution environment for the
-\textbf{Alliance} tools.
-
-If the \textbf{Alliance} installation is set up properly, most of the 
-tools can be executed without problem.
-If the installation is only 
-partial, or if you want to set a special feature of a tool, you will 
-have to set some environment variables up.
-
-The environment variables upon the which each tool depends are 
-documented in each tool manual page.
-However, some variables are really useful, and are in part documented 
-here.
-
-%%%%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{Cell libraries path}
-
-The first thing to know for this circuit is the actual location of 
-the standard-cell library.
-This library is located into \texttt{\$ALLIANCE\_TOP/cells/sclib}.
-But indicating only one library is not enough, and as you can see in 
-doing a \texttt{ls \$ALLIANCE\_TOP/cells}, several libraries are available.
-
-The other library of interest here is the pad library, located in
-\texttt{\$ALLIANCE\_TOP/cells/ring}.
-
-To set up the cell library path, the following command is required:
-\small
-\begin{phraseverbatim}
-~fred/addaccu %-) setenv MBK_CATA_LIB $ALLIANCE_TOP/cells/scr:$ALLIANCE_TOP/cells/ring
-\end{phraseverbatim}
-\normalsize
-
-This \texttt{setenv} instructs \textbf{Alliance} tools to search its cells 
-in \texttt{/alliance/cells/scr} and then in \texttt{/alliance/cells/ring},
-that respectively contains the standard cells and the pads.
-
-%%%%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{User working directory}
-
-You must specify the directory where the files generated by an
-\textbf{Alliance} tool are to be located.
-
-Please enter the following command:
-\small
-\begin{phraseverbatim}
-~fred/addaccu %-) setenv MBK_WORK_LIB .
-\end{phraseverbatim}
-\normalsize
-
-In this case, the working directory is the current directory.
-This library is scanned before the ones set in 
-\texttt{MBK\_CATA\_LIB} when a tool loads a cell, and the only one 
-used for writing a cell.
-Note that \texttt{.} is the default value of this variable, so it is
-not required to set it up usually.
-
-%%%%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{File formats}
-
-One of the interesting features of \textbf{Alliance} is that different 
-file formats can be used for both netlist and layout view.
-However, 
-in the design methodology we wish to promote, some formats are 
-recommended.
-The \texttt{vst}, structural \textbf{VHDL}, is dedicated to netlist 
-specification.
-The \texttt{al} format is dedicated to extracted layout representation.
-The \texttt{ap} format is the usual layout format.
-
-So, prior to generate a specification netlist, you shall type:
-\begin{phraseverbatim}
-~fred/addaccu %-) setenv MBK_OUT_LO vst
-\end{phraseverbatim}
-
-But if you wish to extract a netlist from the layout then you'll do:
-\begin{phraseverbatim}
-~fred/addaccu %-) setenv MBK_OUT_LO al
-\end{phraseverbatim}
-
-%%%%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\section{Behavioral capture and simulation}
-\label{beh}
-
-When designing a chip, the first thing to do is to write its 
-behavior, based on its functional specifications.
-In our example \texttt{addaccu}, we have to modelize an adder, a 
-register and a multiplexer.
-We also have to specify in the resulting behavior file that the adder 
-may take as an input the result of a previous calculation or a new 
-input stimuli.
-
-Modern behavioral descriptions are written using the \textbf{VHDL} 
-language, the most promoted and supported hardware description 
-language.
-
-Let us now edit the behavioral description of addaccu by issuing the 
-following command:
-\begin{phraseverbatim}
-~fred/addaccu %-) vi addaccu.vbe
-\end{phraseverbatim}
-
-The \texttt{addaccu.vbe} file contains the behavioral description of the
-circuit.
-\texttt{Vbe} stands for \textbf{VHDL} behavioral description.
-Although this tutorial does no intend to explain the arcanes of \textbf{VHDL} 
-programming, it's worth noting some interesting points:
-\begin{enumerate}
-\item notice that the entity name, \texttt{addaccu}, identifies the circuit;
-\item examine the circuit interface.
-      You can recognize the terminals of the previous picture, plus 4 
-      special terminals, known as supply terminals.
-      The supply terminals are needed for the last stage of the 
-      design, as the original behavioral description must be matched 
-      with an "extracted" behavior.
-      If this does not make immediate sense to you, do not panic, 
-      everything will be clear in a moment;
-\item take a look to the functional architecture of \texttt{addaccu}.
-      When examining it, pay attention to the \texttt{reg\_bit~register} 
-      names of the accumulator \texttt{reg}, as they will be used later 
-      in the validation stage;
-\item read carefully the functional description.
-      With a little work, you can recognize the description of the 
-      multiplexer, the equations of the adder, and the accumulator.
-      It is very important to notice that the functional description 
-      of the circuit assumes that edge-triggered latches are used.
-\end{enumerate}
-
-Once you have carefully examined this file, close it and get back to 
-the shell prompt, for the \textbf{VHDL} compilation stage.
-
-%%%%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{Behavior compilation}
-
-Once the behavioral description of the circuit is written, it is time 
-for \textbf{VHDL} compilation.
-
-You are now ready to compile \texttt{addaccu.vbe}.
-As we do not have written simulation patterns yet, the only thing we 
-can do is to test the syntax of the file we have just edited.
-
-At the shell prompt level, please type:
-\begin{phraseverbatim}
-~fred/addaccu %-) asimut -b -c addaccu
-\end{phraseverbatim}
-
-This command instructs \texttt{asimut} to compile the behavioral file 
-\texttt{addaccu.vbe}.
-Option \texttt{-b} means behavioral description, and \texttt{-c} means
-compilation only, i.e no simulation.
-\begin{figure}[H]\center\leavevmode
-\begin{framedverbatim}
-~fred/addaccu %-) asimut -b -c addaccu
-
-             @        @@@@ @     @                            @@@@@@@@@@ 
-             @       @    @@    @@@                           @   @@   @ 
-            @@@     @@     @     @                           @    @@    @
-            @@@     @@@              @@@ @@ @@@   @@@  @@@@       @@     
-           @  @@     @@@@     @@@@    @@@ @@  @@   @@    @@       @@     
-           @  @@       @@@@     @@    @@  @@  @@   @@    @@       @@     
-          @    @@        @@@    @@    @@  @@  @@   @@    @@       @@     
-          @@@@@@@   @      @@   @@    @@  @@  @@   @@    @@       @@     
-         @      @@  @@     @@   @@    @@  @@  @@   @@    @@       @@     
-         @      @@  @@@    @    @@    @@  @@  @@   @@   @@@       @@     
-       @@@@    @@@@ @  @@@@   @@@@@@ @@@@ @@@ @@@   @@@@  @@    @@@@@@   
-
-                                A SIMUlation Tool
-
-                 Alliance CAD System 3.2,         asimut v2.01
-                 Copyright (c) 1991-1997,       ASIM/LIP6/UPMC
-                 E-mail support: alliance-support@asim.lip6.fr
-
-        Paris, France, Europe, Earth, Solar system, Milky Way, ...
-Initializing ...
-Searching addaccu ...
-BEH : Compiling addaccu.vbe (Behaviour) ...
-Making GEX ...
-\end{framedverbatim}
-\caption{\texttt{Asimut} compiling the behavioral specifications.}
-\label{compil}
-\end{figure}
-
-%%%%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{Behavioral simulation and validation}
-
-A behavioral description without simulation patterns is useless.  
-In order to see if the behavior you have just written is functionally 
-correct, you must write simulation patterns and use the \texttt{asimut}
-simulator function.
-
-Simulation patterns are contained in a plain text file, 
-\texttt{addaccu.pat}.
-For more informations about the \texttt{pat} format you can read the 
-appropriate on-line manual --- \texttt{man~5~pat} --- or read the 
-printed documentation.
-
-
-To get acquainted with \texttt{addaccu.pat}, please issue the following 
-command:
-\begin{phraseverbatim}
-~fred/addaccu %-) vi addaccu.pat
-\end{phraseverbatim}
-
-There are several interesting things here.
-First, you can recognize the circuit interface again.
-Second, you can see that output terminals are now located at the end 
-of the interface.
-Ordering terminals is very important for \texttt{pat} files.
-The order you use to specify terminals greatly influences the way you 
-will have to write simulation patterns.
-It is important to notice that simulation patterns contain both input 
-and output values.
-The behavior must be checked using these values.
-Comments are prefixed by a \texttt{\#}, and are of much interest here.
-
-Once you have understood the structure of this file, you are able to 
-simulate the previous behavioral description.
-
-In order to simulate, please type:
-\begin{phraseverbatim}
-~fred/addaccu %-) asimut -b addaccu addaccu specifications
-\end{phraseverbatim}
-to obtain:
-\small
-\begin{figure}[H]\center\leavevmode
-\begin{framedverbatim}
-~fred/addaccu %-) asimut -b addaccu addaccu specifications
-
-             @        @@@@ @     @                            @@@@@@@@@@ 
-             @       @    @@    @@@                           @   @@   @ 
-            @@@     @@     @     @                           @    @@    @
-            @@@     @@@              @@@ @@ @@@   @@@  @@@@       @@     
-           @  @@     @@@@     @@@@    @@@ @@  @@   @@    @@       @@     
-           @  @@       @@@@     @@    @@  @@  @@   @@    @@       @@     
-          @    @@        @@@    @@    @@  @@  @@   @@    @@       @@     
-          @@@@@@@   @      @@   @@    @@  @@  @@   @@    @@       @@     
-         @      @@  @@     @@   @@    @@  @@  @@   @@    @@       @@     
-         @      @@  @@@    @    @@    @@  @@  @@   @@   @@@       @@     
-       @@@@    @@@@ @  @@@@   @@@@@@ @@@@ @@@ @@@   @@@@  @@    @@@@@@   
-
-                                A SIMUlation Tool
-
-
-                 Alliance CAD System 3.2,         asimut v2.01
-                 Copyright (c) 1991-1997,       ASIM/LIP6/UPMC
-                 E-mail support: alliance-support@asim.lip6.fr
-
-        Paris, France, Europe, Earth, Solar system, Milky Way, ...
-Initializing ...
-Searching addaccu ...
-BEH : Compiling addaccu.vbe (Behaviour) ...
-Making GEX ...
-
-Searching pattern file : addaccu ...
-Restoring ...
-
-Linking ...
-###----- processing pattern 0 -----###
-###----- processing pattern 1 -----###
-###----- processing pattern 2 -----###
-###----- processing pattern 3 -----###
-###----- processing pattern 4 -----###
-###----- processing pattern 5 -----###
-###----- processing pattern 6 -----###
-\end{framedverbatim}
-\caption{\texttt{Asimut} checking the behavior with a few functionnal test vectors.}
-\label{specs}
-\end{figure}
-\normalsize
-
-Feel free to add new simulation vectors, as it's a very good practice.
-You can also write obviously wrong patterns to see how \texttt{asimut}
-behaves when it encounters errors.
-
-%%%%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\section{Netlist capture and validation}
-\label{netlist}
-
-You are now about to capture the logical view of \texttt{addaccu}, 
-commonly known as netlist.
-The design methodology prevents the designer from building the entire 
-netlist in one shot, including pads.
-VLSI design is based on hierarchy and incremental approaches.
-
-%%%%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{Netlist capture}
-
-The circuit netlist you have to write will be captured in two steps:
-\begin{enumerate}
-\item capture of the core netlist;
-\item capture of the chip netlist, linking the core with pads.
-\end{enumerate}
-
-The core netlist contains standard-cells describing the logical 
-functions needed to design the adder, the multiplexer and the
-accumulator, and the internal wires.
-
-We do not use a schematic editor for netlist capture, but rather a 
-textual approach.
-\begin{phraseverbatim}
-~fred/addaccu %-) vi core.c
-\end{phraseverbatim}
-
-The core netlist is nothing more than a \textbf{C} file containing 
-specific function calls for the creation of VLSI objects.
-Notice that the include file \texttt{genlib.h} must systematically be 
-included at the top of \textbf{genlib}'s files.
-
-The description of a netlist in \textbf{C} is mainly based on the
-\texttt{DEF\_LOFIG, LOCON} and \texttt{LOINS} functions.
-\texttt{DEF\_LOFIG} defines the name of the resulting netlist view,
-\texttt{LOCON} instanciates a new terminal in the currently opened 
-figure, and \texttt{LOINS} instanciates pre-existing cells or blocks.
-For more informations, please read the on-line manual associated with 
-each function.
-
-To compile and run the \textbf{C} file, you must use the \texttt{genlib} 
-program.
-
-You must specify the input format of cells that are instanciated in 
-the \textbf{genlib}'s code.
-
-Therefore enter the following command:
-\begin{phraseverbatim}
-~fred/addaccu %-) setenv MBK_IN_LO vst
-~fred/addaccu %-) setenv MBK_OUT_LO vst
-\end{phraseverbatim}
-
-These \texttt{setenv} define the input and output formats for the 
-specification netlist.
-
-\texttt{vst} stands for structural \textbf{VHDL} description.  
-The design methodology assumes that user defined netlists must use 
-extension \texttt{vst} as we've already said.
-The \texttt{al} format is mostly used for extracted netlist with 
-specific informations like capacitances that cannot be coded in \textbf{VHDL}.
-
-At last, you can execute the genlib program:
-\begin{phraseverbatim}
-~fred/addaccu %-) genlib -v core
-\end{phraseverbatim}
-to get:
-\small
-\begin{figure}[H]\center\leavevmode
-\begin{framedverbatim}
-~fred/addaccu %-) setenv MBK_IN_LO vst
-~fred/addaccu %-) setenv MBK_OUT_LO vst
-~fred/addaccu %-) setenv MBK_CATA_LIB /alliance/cells/scr
-~fred/addaccu %-) genlib -v core
-
-             @@@@ @                        @@@@@@         @   @@@      
-           @@    @@                          @@          @@@   @@      
-          @@      @                          @@           @    @@      
-         @@             @@@@@   @@@ @@@      @@                @@ @@   
-         @@            @     @   @@@   @     @@        @@@@    @@@  @@ 
-         @@     @@@@@ @@     @@  @@    @@    @@          @@    @@    @@
-         @@     @ @@  @@@@@@@@@  @@    @@    @@          @@    @@    @@
-         @@    @  @@  @@         @@    @@    @@          @@    @@    @@
-          @@      @@  @@      @  @@    @@    @@      @   @@    @@    @@
-           @@    @@    @@    @@  @@    @@    @@     @    @@    @@@  @@ 
-             @@@@        @@@@   @@@@  @@@@ @@@@@@@@@@  @@@@@@ @@@ @@   
-
-                         Procedural Generation Language
-
-                 Alliance CAD System 3.2,           genlib 3.3
-                 Copyright (c) 1991-1998,       ASIM/LIP6/UPMC
-                 E-mail support: alliance-support@asim.lip6.fr
-
-Generating the Makefile
-Compiling, ...
-Current execution environment
-MBK_CATA_LIB   : /users/soft5/newlabo/Solaris/cells/sclib
-MBK_WORK_LIB   : :
-MBK_IN_LO      : vst
-MBK_OUT_LO     : vst
-MBK_IN_PH      : ap
-MBK_OUT_PH     : ap
-MBK_CATAL_NAME : CATAL
-Executing ...
-Removing tmp files ...
-\end{framedverbatim}
-\caption{Netlist core generation using \texttt{genlib}.}
-\label{core}
-\end{figure}
-\normalsize
-
-You can now look in the current directory for a file named 
-\texttt{core.vst}.
-This file contains the resulting description of the core.
-
-The \texttt{addaccu.c} file contains the actual chip netlist.  
-You can edit it to see how pads are instanciated.
-
-Running the following command:
-\begin{phraseverbatim}
-~fred/addaccu %-) genlib -v addaccu
-\end{phraseverbatim}
-produces:
-\small
-\begin{figure}[H]\center\leavevmode
-\begin{framedverbatim}
-~fred/addaccu %-) setenv MBK_IN_LO vst
-~fred/addaccu %-) setenv MBK_OUT_LO vst
-~fred/addaccu %-) setenv MBK_CATA_LIB /alliance/cells/scr:/alliance/cells/ring
-~fred/addaccu %-) genlib addaccu
-
-             @@@@ @                        @@@@@@         @   @@@      
-           @@    @@                          @@          @@@   @@      
-          @@      @                          @@           @    @@      
-         @@             @@@@@   @@@ @@@      @@                @@ @@   
-         @@            @     @   @@@   @     @@        @@@@    @@@  @@ 
-         @@     @@@@@ @@     @@  @@    @@    @@          @@    @@    @@
-         @@     @ @@  @@@@@@@@@  @@    @@    @@          @@    @@    @@
-         @@    @  @@  @@         @@    @@    @@          @@    @@    @@
-          @@      @@  @@      @  @@    @@    @@      @   @@    @@    @@
-           @@    @@    @@    @@  @@    @@    @@     @    @@    @@@  @@ 
-             @@@@        @@@@   @@@@  @@@@ @@@@@@@@@@  @@@@@@ @@@ @@   
-
-                         Procedural Generation Language
-
-                 Alliance CAD System 3.2,           genlib 3.3
-                 Copyright (c) 1991-1998,       ASIM/LIP6/UPMC
-                 E-mail support: alliance-support@asim.lip6.fr
-\end{framedverbatim}
-\caption{Core to pad netlist generation using \texttt{genlib}.}
-\label{addaccu}
-\end{figure}
-\normalsize
-
-This creates \texttt{addaccu.vst}, the resulting netlist, in the current 
-directory.
-
-%%%%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{Simulation of the specification netlist}
-
-Once the complete netlist has been captured, we can simulate the 
-whole chip with the previous simulation patterns.
-
-You can run asimut by entering the following command: 
-\begin{phraseverbatim}
-~fred/addaccu %-) asimut addaccu addaccu schema
-\end{phraseverbatim}
-It produces the output of Figure~\ref{schema}.
-
-The first \texttt{addaccu} stands for \texttt{addaccu.vst}.
-The second \texttt{addaccu} stands \texttt{addaccu.pat}, the pattern 
-file with input and output values.
-\texttt{schema} stands for \texttt{schema.pat}, the generated list of 
-patterns.
-
-Because option \texttt{-b} is not set and because \texttt{MBK\_IN\_LO} 
-contains \texttt{vst}, \texttt{asimut} simulates the specification 
-netlist we have captured with \texttt{genlib}.
-
-Errors during this execution mean that something went wrong between 
-your current position in the design flow and the behavioral 
-simulation stage.
-
-\small
-\begin{figure}[H]\center
-\begin{framedverbatim}
-~fred/addaccu %-) setenv MBK_IN_LO vst
-~fred/addaccu %-) setenv MBK_CATA_LIB /alliance/cells/scr:/alliance/cells/ringxx
-~fred/addaccu %-) asimut addaccu addaccu schema
-Warning 2 : consistency checks will be disabled
-
-             @        @@@@ @     @                            @@@@@@@@@@ 
-             @       @    @@    @@@                           @   @@   @ 
-            @@@     @@     @     @                           @    @@    @
-            @@@     @@@              @@@ @@ @@@   @@@  @@@@       @@     
-           @  @@     @@@@     @@@@    @@@ @@  @@   @@    @@       @@     
-           @  @@       @@@@     @@    @@  @@  @@   @@    @@       @@     
-          @    @@        @@@    @@    @@  @@  @@   @@    @@       @@     
-          @@@@@@@   @      @@   @@    @@  @@  @@   @@    @@       @@     
-         @      @@  @@     @@   @@    @@  @@  @@   @@    @@       @@     
-         @      @@  @@@    @    @@    @@  @@  @@   @@   @@@       @@     
-       @@@@    @@@@ @  @@@@   @@@@@@ @@@@ @@@ @@@   @@@@  @@    @@@@@@   
-
-                                A SIMUlation Tool
-
-                 Alliance CAD System 3.2,         asimut v2.01
-                 Copyright (c) 1991-1997,       ASIM/LIP6/UPMC
-                 E-mail support: alliance-support@asim.lip6.fr
-
-        Paris, France, Europe, Earth, Solar system, Milky Way, ...
-Initializing ...
-Searching addaccu ...
-Compiling addaccu (Structural) ...
-
-Flattening the root figure ...
-
-Searching a2_y ...
-BEH : Compiling a2_y.vbe (Behaviour) ...
-Making GEX ...
-.
-.
-.
-Searching pi_sp ...
-BEH : Compiling pi_sp.vbe (Behaviour) ...
-Making GEX ...
-
-Searching pck_sp ...
-BEH : Compiling pck_sp.vbe (Behaviour) ...
-Making GEX ...
-
-Searching pattern file : addaccu ...
-Restoring ...
-
-Linking ...
-###----- processing pattern 0 -----###
-###----- processing pattern 1 -----###
-###----- processing pattern 2 -----###
-###----- processing pattern 3 -----###
-###----- processing pattern 4 -----###
-###----- processing pattern 5 -----###
-###----- processing pattern 6 -----###
-\end{framedverbatim}
-\caption{\texttt{Asimut} checking the netlist description.}
-\label{schema}
-\end{figure}
-\normalsize
-
-%%%%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\section{Core layout generation}
-\label{layout}
-
-Incremental design relies on hierarchy.  
-Before you design the core to pads netlist, the circuit core must be 
-successfully built.
-In this example, the layout generation relies on:
-\begin{enumerate}
-\item standard-cells placement (automatic or manual);
-\item automatic routing of standard-cells.
-\end{enumerate}
-
-\texttt{scr} is a place and route tool that can produce automatically 
-the layout view from a netlist description.
-
-As stated in the previous section, before you run \texttt{scr}, you must 
-specify environment variables.
-Needless to say that these variables will deal with physical aspects 
-of the circuit.
-
-
-First, you must specify the input layout format you use for the 
-standard-cells.
-The \textbf{Alliance} distribution only contains \texttt{ap} symbolic 
-layout files so you must issue the following command:
-\begin{phraseverbatim}
-~fred/addaccu %-) setenv MBK_IN_PH ap
-\end{phraseverbatim}
-
-This command instructs \texttt{scr} to use the \texttt{ap} cell layout 
-format as input.
-Remember that the variable \texttt{MBK\_CATA\_LIB} is still set, so 
-\textbf{Alliance} tools know where to find cells.
-
-Second, you must accordingly specify the output layout format.  
-Again, the format is \texttt{ap}, so:
-\begin{phraseverbatim}
-~fred/addaccu %-) setenv MBK_OUT_PH ap
-\end{phraseverbatim}
-
-This command instructs \texttt{scr} to use \texttt{ap} representation of 
-cells as an output.
-
-Everything is now ready for the place and route phase.
-The command is:
-\begin{phraseverbatim}
-~fred/addaccu %-) scr -p -r core core
-\end{phraseverbatim}
-
-Option \texttt{-p} means automatic placement, and option \texttt{-r} means 
-automatic routing.
-
-Once \texttt{scr} has been executed, the core layout is completed.
-\small
-\begin{figure}[H]\center\leavevmode
-\begin{framedverbatim}
-~fred/addaccu %-) setenv MBK_IN_LO vst
-~fred/addaccu %-) setenv MBK_IN_PH ap
-~fred/addaccu %-) setenv MBK_OUT_PH ap
-~fred/addaccu %-) setenv MBK_CATA_LIB /alliance/cells/scr
-~fred/addaccu %-) scr -p -r core 
-
-                          @@@@ @      @@@@ @ @@@@@@@    
-                         @    @@    @@    @@   @@   @@  
-                        @@     @   @@      @   @@    @@ 
-                        @@@       @@       @   @@    @@ 
-                         @@@@     @@           @@   @@  
-                           @@@@   @@           @@@@@    
-                             @@@  @@           @@  @@   
-                        @      @@ @@           @@   @@  
-                        @@     @@  @@      @   @@   @@  
-                        @@@    @    @@    @@   @@    @@ 
-                        @  @@@@       @@@@   @@@@@   @@@
-
-                              Standard Cell router
-
-                 Alliance CAD System 3.2,              scr 5.2
-                 Copyright (c) 1991-1997,       ASIM/LIP6/UPMC
-                 E-mail support: alliance-support@asim.lip6.fr
-
-Loading logical view : core
-Placing logical view : core
-Loading SCP data base ...
-Generating initial placement ... 
-25 cells 37 nets in 2 rows
-Placement in process of treatment :   100%
-49% saved in  0.3 s
-Saving placement   100%
-Checking consistency between logical and physical views
-Loading SCR data base ...
-Deleting MBK data base ...
-Global routing ...
-Channel routing ...
-|_____Routing Channel : scr_p2 
-|_____Routing Channel : scr_p4 
-|_____Routing Channel : scr_p6 
-Making vertical power and ground wires  
-Saving layout : core
-\end{framedverbatim}
-\caption{Placing and Routing the core netlist with \texttt{scr}.}
-\label{scr}
-\end{figure}
-\normalsize
-
-Note that \texttt{scr} knows how to place and route only cells having a
-standard cell topology.
-
-%%%%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\section{Core layout verification}
-\label{lv}
-
-Routers may have bugs, and produce shorts or open circuits.
-So serious checks must be made on the produced layout.
-To check the layout, we use two \textbf{Alliance} tools, \texttt{lynx} and 
-\texttt{lvx}.
-
-\texttt{lynx} is the \textbf{Alliance} netlist extractor.
-From a physical layout it extracts a netlist representation of the
-circuit, in terms of blocks, gates or transistors.  
-In our case, we want to extract the core netlist at the gate level.
-
-\texttt{lvx} is the \textbf{Alliance} netlist comparator.
-Its main function is to verify that an extracted netlist corresponds 
-to the specification netlist.
-
-Hence, the design methodology is quite simple.
-We must extract the core \texttt{core.ap} with \texttt{lynx} and check the
-resulting netlist with the original \texttt{addaccu.vst}
-file using \texttt{lvx}.
-
-%%%%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{Extraction of the core netlist}
-
-Now, back to practice.
-You have to extract the layout using \texttt{lynx}.
-Remember two things:
-\begin{enumerate}
-\item \textbf{Alliance} tools deeply rely on appropriate environment 
-      variables.
-      For instance, you have to specify the format the extracted 
-      netlist will be generated with.
-\item in the usual design flow, extracted netlist files are written
-      in \texttt{al} format.
-\end{enumerate}
-
-So you must:
-\begin{phraseverbatim}
-~fred/addaccu %-) setenv MBK_OUT_LO al
-\end{phraseverbatim}
-to generate a extracted netlist file called \texttt{core.al}.
-
-The actual execution of lynx is quite easy.
-Just type:
-\begin{phraseverbatim}
-~fred/addaccu %-) lynx -v core
-\end{phraseverbatim}
-and you get your extracted netlist in terms of interconnected 
-standard cells.
-\small
-\begin{figure}[H]\center\leavevmode
-\begin{framedverbatim}
-~fred/addaccu %-) setenv MBK_IN_PH ap
-~fred/addaccu %-) setenv MBK_OUT_LO al
-~fred/addaccu %-) setenv RDS_TECHNO_NAME /alliance/etc/cmos_5.rds
-~fred/addaccu %-) setenv MBK_CATA_LIB /alliance/cells/scr:/alliance/cells/ring
-~fred/addaccu %-) lynx -v core core
-
-                   @@@@@@                                    
-                     @@                                      
-                     @@                                      
-                     @@        @@@@@ @@@ @@@ @@@    @@@@  @@@
-                     @@         @@    @   @@@   @    @@    @ 
-                     @@          @@   @   @@    @@    @@  @  
-                     @@          @@  @    @@    @@     @@@   
-                     @@           @@ @    @@    @@     @@@   
-                     @@      @    @@@     @@    @@    @  @@  
-                     @@     @      @@     @@    @@   @    @@ 
-                   @@@@@@@@@@  @@  @     @@@@  @@@@ @@@  @@@@
-                               @@  @                         
-                                @@@                          
-
-                                Netlist extractor
-
-                  Alliance CAD System 3.2,            lynx 1.16
-                  Copyright (c) 1993-1997,       ASIM/LIP6/UPMC
-                  E-mail support: alliance-support@asim.lip6.fr
-
-
-
-        ---> Extracts symbolic figure core
-
-                ---> Translate Mbk -> Rds
-                ---> Build windows
-                <--- 108
-
-                ---> Rectangles    : 894
-                ---> Figure size   : (    -50,   -100 )
-                                     (  55250,  16600 )
-
-                ---> Cut transistors
-                <--- 0
-                ---> Build equis
-                <--- 37
-                ---> Delete windows
-                ---> Build signals
-                <--- 37
-                ---> Build instances
-                <--- 29
-                ---> Build transistors
-                <--- 0
-                ---> Save netlist
-
-        <--- done !
-\end{framedverbatim}
-\caption{Extracting a hierarchical netlist in terms of standard cells with \texttt{lynx}.}
-\label{lynx}
-\end{figure}
-\normalsize
-
-%%%%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{Netlist cross-checking}
-
-Now it's time for netlist verifications.
-Since \texttt{lvx} takes two netlist in input, the formats have to be 
-specified on the command line.
-
-\begin{phraseverbatim}
-~fred/addaccu %-) lvx vst al core core
-\end{phraseverbatim}
-
-\texttt{lvx} works somewhat differently from other tools.
-Its two former arguments are the formats of the first netlist, here
-\texttt{vst} (for the original netlist)  and \texttt{al} (for the extracted 
-netlist).
-The two following arguments are the names of the netlist.
-We have done our best to make these names identical.
-Once again, remember that specification files are postfixed with
-\texttt{vst} and extracted files with \texttt{al}.
-\small
-\begin{figure}[H]\center\leavevmode
-\begin{framedverbatim}
-~fred/addaccu %-) setenv MBK_CATA_LIB /alliance/cells/scr:/alliance/cells/ring
-~fred/addaccu %-) lvx vst al core core -f
-
-                       @@@@@@      @@@@    @@@ @@@@   @@@@
-                         @@         @@      @   @@     @  
-                         @@         @@      @    @@   @   
-                         @@          @@    @      @@ @    
-                         @@          @@    @       @@     
-                         @@           @@  @        @@     
-                         @@           @@  @        @@@    
-                         @@            @@@        @  @@   
-                         @@      @     @@@       @    @@  
-                         @@     @       @       @      @@ 
-                       @@@@@@@@@@       @      @@@    @@@@
-
-                             Gate Netlist Comparator
-
-                  Alliance CAD System 3.2,             lvx 2.23
-                  Copyright (c) 1992-1997,       ASIM/LIP6/UPMC
-                  E-mail support: alliance-support@asim.lip6.fr
-
-***** Loading and flattening core (vst)...
-
-***** Loading and flattening core (al)...
-
-***** Compare Terminals ..............
-***** O.K.      (0 sec)
-
-***** Compare Instances ..........
-***** O.K.      (0 sec)
-
-***** Compare Connections ............
-***** O.K.      (0 sec)
-
-===== Terminals .......... 16    
-===== Instances .......... 25    
-===== Connectors ......... 150   
-
-***** Netlists are Identical. *****     (0 sec)
-\end{framedverbatim}
-\caption{Doing the specification netlist versus extracted netlist
-         compaison with \texttt{lvx}.}
-\label{lvx}
-\end{figure}
-\normalsize
-
-As a result, you now have a correct \texttt{al} file for the circuit's 
-core.
-Its name is \texttt{core.al}.  
-This file may now be simulated with \texttt{asimut}, but this is only 
-for cross checking.  
-
-Execution environment is set by issuing:
-\begin{phraseverbatim}
-~fred/addaccu %-) setenv MBK_IN_LO al
-\end{phraseverbatim}
-because we want to use the extracted \texttt{core.al} file as input to 
-\texttt{asimut}.
-
-Then you can run asimut by entering the following command:
-\begin{phraseverbatim}
-~fred/addaccu %-) asimut core addaccu result
-\end{phraseverbatim}
-
-%%%%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\section{Core to pads routing}
-\label{pads}
-
-Having built and checked the core layout, you can run the 
-core-to-pads router.
-Its function is to locate pads appropriately around the core and to 
-create wiring segments between pads and chip terminals.
-
-Before we set up the execution environment, take a look at the
-\texttt{addaccu.rin} file.
-This file instructs \texttt{ring}, the core to pads router, to place pads
-according to designer's wishes.
-It also instructs \texttt{ring} to use segments with reasonable width 
-for power routing.
-
-The syntax of this file is quite simple.
-The names mentioned here are pads' instance names.
-
-Run:
-\begin{phraseverbatim}
-~fred/addaccu %-) ring addaccu addaccu
-\end{phraseverbatim}
-
-\small
-\begin{figure}[H]\center\leavevmode
-\begin{framedverbatim}
-~fred/addaccu %-) setenv MBK_IN_LO vst
-~fred/addaccu %-) setenv MBK_IN_PH ap
-~fred/addaccu %-) setenv MBK_OUT_PH ap
-~fred/addaccu %-) setenv MBK_CATA_LIB /alliance/cells/scr:/alliance/cells/ring
-~fred/addaccu %-) ring addaccu addaccu
-
-                   @@@@@@@        @                  @@@@ @  
-                     @@   @@     @@@               @@    @@  
-                     @@    @@     @               @@      @  
-                     @@    @@         @@@ @@@    @@          
-                     @@   @@   @@@@    @@@   @   @@          
-                     @@@@@       @@    @@    @@  @@     @@@@@
-                     @@  @@      @@    @@    @@  @@     @ @@ 
-                     @@   @@     @@    @@    @@  @@    @  @@ 
-                     @@   @@     @@    @@    @@   @@      @@ 
-                     @@    @@    @@    @@    @@    @@    @@  
-                   @@@@@   @@@ @@@@@@ @@@@  @@@@     @@@@    
-
-                                 PAD ring router
-
-                 Alliance CAD System 3.2,             ring 2.9
-                 Copyright (c) 1991-1997,       ASIM/LIP6/UPMC
-                 E-mail support: alliance-support@asim.lip6.fr
-
-        o reading netlists, layout views of core and pads.
-Warning 2 : consistency checks will be disabled
-        o reading file of parameters, including the placements of pads.
-        o making equipotential list.
-        o making the first placement of pads.
-        o filling data internal structures.
-        o reading the connectors positions of the core.
-        o computing the best placement of the pads.
-        o reading the connectors positions of the pads.
-        o routing deportation of connectors.
-        o routing supply tracks.
-        o routing equipotentials.
-        o compressing channels.
-        o saving in MBK data structure.
-lucky, no error.
-\end{framedverbatim}
-\caption{\texttt{Ring} routes the core to pad netlist.}
-\label{ring}
-\end{figure}
-\normalsize
-
-Like for the core, the core to pad routing must be verified.
-Using the same approach leads to:
-\begin{phraseverbatim}
-~fred/addaccu %-) setenv MBK_OUT_LO al
-~fred/addaccu %-) setenv MBK_IN_PH ap
-~fred/addaccu %-) lynx -v addaccu
-~fred/addaccu %-) lvx vst al addaccu
-\end{phraseverbatim}
-
-It is possible to check both core a core to pad routing at once also:
-\begin{phraseverbatim}
-~fred/addaccu %-) setenv MBK_OUT_LO al
-~fred/addaccu %-) setenv MBK_IN_PH ap
-~fred/addaccu %-) lynx -v -f addaccu
-~fred/addaccu %-) lvx vst al addaccu -f
-\end{phraseverbatim}
-
-Here the \texttt{-f} option indicate the tools to express the netlist in 
-terms of leaf cells --- either pads or standard cells ---.
-Obtaining a transistor netlist from the layout is possible using the
-\texttt{-t} option of \texttt{lynx}, but this is more time and memory
-consuming, and fairly useless as we rely on correct cells.
-
-%%%%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\section{Chip layout visualization}
-\label{graal}
-
-At that point, you are able to see the actual layout by executing the 
-symbolic layout editor \texttt{graal}.
-You can run the editor by issuing the following command:
-\begin{phraseverbatim}
-~fred/addaccu %-) graal -l addaccu
-\end{phraseverbatim}
-
-Now, the screen should be filled with the \texttt{graal} window, and 
-should contain the whole layout.
-The graphical interface of \texttt{graal} is meant to be self 
-explanatory.
-
-%%%%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\section{Functional abstraction}
-\label{fa}
-
-\texttt{yagle}, a functional asbtractor that extracts a behavior from a 
-transistor netlist can relieve the designer from many headaches.
-From a transistor netlist,\texttt{yagle} finally outputs a 
-\textbf{VHDL} file that can be simulated.
-
-The command is: 
-\begin{phraseverbatim}
-~fred/addaccu %-) setenv MBK_IN_LO al
-~fred/addaccu %-) yagle -i -v addaccu
-\end{phraseverbatim}
-\begin{figure}[H]\center\leavevmode
-\begin{framedverbatim}
-~fred/addaccu %-) setenv MBK_IN_LO al
-~fred/addaccu %-) yagle addaccue -i -v
-
-                                               @@@@            
-                                                 @@            
-                                                 @@            
-                  @@@@@ @@@   @@@@      @@@@@@   @@     @@@@@  
-                   @@    @   @@   @    @@  @@    @@    @     @ 
-                    @@   @   @@   @@   @   @@    @@   @@     @@
-                    @@  @      @@@@@   @   @     @@   @@@@@@@@@
-                     @@ @    @@   @@    @@@      @@   @@       
-                     @@@    @@    @@   @@        @@   @@      @
-                      @@    @@   @@@   @@@@@@    @@    @@    @@
-                  @@  @      @@@@  @@ @@   @@@ @@@@@@    @@@@  
-                  @@  @                @     @                 
-                   @@@                  @@@@@                  
-
-                        Yet Another Gate Level Extractor
-
-                 Alliance CAD System 3.2,           yagle 2.01
-                 Copyright (c) 1994-1997,       ASIM/LIP6/UPMC
-                 E-mail support: alliance-support@asim.lip6.fr
-
-[YAG MES] Reading file 'addaccue.inf'
-[YAG MES] Loading the figure addaccue              00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Transistor netlist checking              00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Extracting CMOS duals                    00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Extracting bleeders                      00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Making gates                             00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Latches detection                        00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Making cells                             00m00s  u:00m00.0  s:00m00.0
-[YAG MES] External connector verification          00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Checking the yagle figure                00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Building the behavioural figure          00m00s  u:00m00.0  s:00m00.0
-TOTAL DISASSEMBLY TIME                             00m00s  u:00m00.0  s:00m00.0
-------------------------------------------------------------
-[YAG MES] Erasing the transistor netlist
-[YAG MES] Generating the VHDL Data Flow
-[YAG MES] Execution COMPLETED 
-------------------------------------------------------------
-[YAG WAR 04] 80 transistors are always off
-[YAG WAR 07] 80 transistors are not used 
-[YAG WAR 09] 8 latches detected
-See file 'addaccue.rep' for more information
-\end{framedverbatim}
-\caption{\texttt{Desb} abstract the extracted netlist into boolean
-         equations.}
-\label{yagle}
-\end{figure}
-\normalsize
-
-Then, you can simulate the resulting behavior file by issuing:
-\begin{phraseverbatim}
-~fred/addaccu %-) asimut -b addaccu addaccu result
-\end{phraseverbatim}
-
-Simulation of extracted behavior with asimut is not the only mean to 
-see if the chip is correct.
-The extracted behavior can also be used for formal proof.
-
-In \textbf{Alliance}, formal proof is the ultimate way to validate your 
-circuit.
-
-Before you can use \texttt{proof}, the formal prover, you must get
-acquainted with some specific concepts of the formal proof theory.
-
-If you look at the extracted behavior, \texttt{chip.vbe}, you can notice 
-that \texttt{yagle} has found four memorizing elements, specified as
-\texttt{reg\_bit register}.
-In the formal proof, these four elements must match the four 
-edge-triggered latches of the former behavioral specification, 
-because \texttt{proof} can only compare combinatorial logic between 
-external connectors and/or sequential elements.  
-
-If you examine the current directory, you will find a file called 
-\texttt{addaccu.inf}.
-
-This file contains specific informations for \texttt{yagle}.
-It instructs \texttt{yagle} to rename the internal node name of every 
-latch \textit{core.l*} by its corresponding name in the first behavior 
-file.
-In the \texttt{cells/scr} directory you can see that the name of the
-internal node of the used latch, \texttt{ms\_y.vbe}, is \textit{dff\_s}.
-
-The equivalent name in \texttt{addaccu.vbe} is \textit{reg}.
-
-When you run \texttt{yagle} with option \texttt{-i}, the program searches 
-for the file \texttt{chip.inf}, builds the gate netlist and replaces the 
-node names by their equivalent names in the behavior file, in order 
-to make \texttt{proof} work.
-
-Then, you can run \texttt{proof}, the formal prover:
-\begin{phraseverbatim}
-~fred/addaccu %-) proof -d -p addaccu addaccue
-\end{phraseverbatim}
-\small
-\begin{figure}[H]\center\leavevmode
-\begin{framedverbatim}
-~fred/addaccu %-) proof -d addaccue addaccu
-
-                @@@@@@@                                     @@@ 
-                  @@   @@                                  @  @@
-                  @@    @@                                @@  @@
-                  @@    @@ @@@ @@@     @@@       @@@      @@    
-                  @@   @@   @@@  @@  @@   @@   @@   @@  @@@@@@@@
-                  @@@@@     @@   @@ @@     @@ @@     @@   @@    
-                  @@        @@      @@     @@ @@     @@   @@    
-                  @@        @@      @@     @@ @@     @@   @@    
-                  @@        @@      @@     @@ @@     @@   @@    
-                  @@        @@       @@   @@   @@   @@    @@    
-                @@@@@@     @@@@        @@@       @@@    @@@@@@  
-
-                                  Formal Proof
-
-                 Alliance CAD System 3.2,          proof 3.158
-                 Copyright (c) 90-97,           ASIM/LIP6/UPMC
-                 E-mail support: alliance-support@asim.lip6.fr
-
-================================  Environment  ================================
-MBK_WORK_LIB            = .
-MBK_CATA_LIB            = /labo/cells/grog
-=======================  Files, Options and Parameters  =======================
-First VHDL file         = addaccue.vbe
-Second VHDL file        = addaccu.vbe
-The auxiliary signals are erased
-Errors are displayed
-===============================================================================
-
-Compiling 'addaccue' ...
-Compiling 'addaccu' ...
-
-Running abl ordonnancer on addaccue
-........
-
-Running Abl2Bdd on addaccue
----> final number of nodes = 664(404)
-
-Running Abl2Bdd on addaccu
---------------------------------------------------------------------------------
-             Formal proof with Ordered Binary Decision Diagrams between   
-
-             './addaccue'  and  './addaccu'
---------------------------------------------------------------------------------
-==============================  PRIMARY OUTPUT  ===============================
-=============================  AUXILIARY SIGNAL  ==============================
-==============================  REGISTER SIGNAL  ==============================
-===============================  EXTERNAL BUS =================================
-================================ INTERNAL BUS =================================
-
-                            Formal Proof : OK
-
-pppppppppppppppppppppppprrrrrrrrrrrrooooooooooooooooooooooooooooofffffffffffffff
---------------------------------------------------------------------------------
-\end{framedverbatim}
-\caption{Doing a formal proof between the abstracted behavior and the
-         specifications using \texttt{proof}.}
-\label{proof}
-\end{figure}
-\normalsize
-
-Option \texttt{-d} displays the logical functions that do not match, and 
-the \texttt{-p} option tells \texttt{proof} to ignore the internal polarity
-of the flip-flops: we described our behavioral with a register 
-%%%%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\section{Further verifications}
-\label{verif}
-
-The last verification concerns design rules.  
-Before the chip can actually be targetted on a process, a symbolic 
-design rule check --- DRC --- must be performed.
-
-In \textbf{Alliance}, the design rule checker is \texttt{druc}.
-
-You just have to type:
-\begin{phraseverbatim}
-~fred/addaccu %-) setenv MBK_IN_PH ap
-~fred/addaccu %-) setenv RDS_TECHNO_NAME /alliance/etc/cmos_5.rds
-~fred/addaccu %-) druc addaccu
-\end{phraseverbatim}
-
-The file pointed to by the \texttt{RDS\_TECHNO\_NAME} environement variable
-contains many technological information including the desription of 
-the design rules.
-\begin{figure}[H]\center\leavevmode
-\begin{framedverbatim}
-~fred/addaccu %-) setenv MBK_IN_PH ap
-~fred/addaccu %-) setenv RDS_OUT cif 
-~fred/addaccu %-) setenv RDS_TECHNO_NAME /alliance/etc/cmos_5.rds
-~fred/addaccu %-) setenv MBK_CATA_LIB /alliance/cells/scr:/alliance/cells/ring
-~fred/addaccu %-) druc addaccu
-
-                  @@@@@@@     @@@@@@@                    @@@@ @
-                    @@   @@     @@   @@                @@    @@
-                    @@    @@    @@    @@              @@      @
-                    @@     @@   @@    @@  @@@  @@@@  @@       @
-                    @@     @@   @@   @@    @@    @@  @@        
-                    @@     @@   @@@@@      @@    @@  @@        
-                    @@     @@   @@  @@     @@    @@  @@        
-                    @@     @@   @@   @@    @@    @@  @@        
-                    @@    @@    @@   @@    @@    @@   @@      @
-                    @@   @@     @@    @@   @@   @@@    @@    @@
-                  @@@@@@@     @@@@@   @@@   @@@@  @@     @@@@  
-
-                               Design Rule Checker
-
-                  Alliance CAD System 3.2,            druc 3.00
-                  Copyright (c) 1993-1997,       ASIM/LIP6/UPMC
-                  E-mail support: alliance-support@asim.lip6.fr
-
-Flatten DRC on: addaccu
-Delete MBK figure : addaccu
-Load Flatten Rules : /usr/local/cad/alliance/etc/cmos_7.rds
-
-Unify : addaccu
-
-Create Ring : addaccu_rng
-Merge Errorfiles: 
-
-Merge Error Instances:
-instructionCourante : 50
-End DRC on: addaccu
-Saving the Error file figure
-Done
-  0
-
-File: addaccu.drc is empty: no errors detected.
-\end{framedverbatim}
-\caption{Symbolic design rule checking using \texttt{druc}.}
-\label{druc}
-\end{figure}
-
-This layout level verification has been optimized for speed.
-So it is fast, even on large circuits, but requires quite a few megs
-then.
-
-%%%%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\section{Symbolic to real technology translation}
-\label{sr}
-
-The purpose of \textbf{Alliance} symbolic layout approach is to allow 
-the designs to be targetted on several technologies.
-The whole chip is conceived with symbolic cells.
-
-In order to send the chip to a specified foundry, the designer must 
-perform the symbolic to real conversion.
-This stage is the last stage of the design methodology.
-
-The only things you have to specify is the target technology and some 
-environment variables.
-
-The only target technology available in the distribution is
-\texttt{prol10}, a fake 1.0 process.
-You can choose it by setting the \texttt{RDS\_TECHNO\_NAME} environment 
-variable.
-\begin{phraseverbatim}
-~fred/addaccu %-)setenv RDS_TECHNO_NAME /alliance/etc/prol10.rds
-\end{phraseverbatim}
-
-You also have to specify the format of the output file that will
-represent the foundry layout.
-\textbf{Alliance} provides two distinct formats: \texttt{gds} and \texttt{cif}.
-\begin{phraseverbatim}
-~fred/addaccu %-) setenv RDS_OUT cif
-\end{phraseverbatim}
-
-This command instructs the converter to output the chip in the 
-Caltech Intermediat Form.
-This form is an \texttt{ascii} format, that can include connectors,
-whereas \texttt{gds} is binary and doesn't include connectors.
-
-A tricky thing is that the \textit{pad} part of the symbolic IO pads must 
-be replaced by its "real" equivalent.
-This is indeed the only technology dependant part of a circuit
-designed with our symbolic approach.
-
-So you also have to set the \texttt{RDS\_IN} environment variable, to
-indicate the format of the substitution pad.
-\begin{phraseverbatim}
-~fred/addaccu %-) setenv RDS_IN cif
-\end{phraseverbatim}
-
-At last, you run the symbolic to real converter, \texttt{s2r}.
-\begin{phraseverbatim}
-~fred/addaccu %-) s2r -cv addaccu
-\end{phraseverbatim}
-
-Your chip is now ready for the foundry that provides the prol10 
-technology.
-\begin{figure}[H]\center\leavevmode
-\begin{framedverbatim}
-~fred/addaccu %-) setenv MBK_IN_PH ap
-~fred/addaccu %-) setenv MBK_CATA_LIB /alliance/cells/scr:/alliance/cells/ring
-~fred/addaccu %-) setenv RDS_TECHNO_NAME /alliance/etc/prol10.rds
-~fred/addaccu %-) setenv RDS_OUT cif 
-~fred/addaccu %-) setenv RDS_IN cif
-~fred/addaccu %-) s2r -v addaccu
-
-                                      @@@@           
-                                     @   @@          
-                                    @@    @@         
-                            @@@@@@  @@@   @@ @@@ @@@ 
-                           @@    @   @   @@   @@@  @@
-                           @@@           @    @@   @@
-                            @@@@        @     @@     
-                              @@@@     @      @@     
-                           @    @@@   @    @  @@     
-                           @@    @@  @@@@@@   @@     
-                           @ @@@@@  @@@@@@@  @@@@    
-
-                        Symbolic to Real layout converter
-
-                 Alliance CAD System 3.2,              s2r 3.6
-                 Copyright (c) 1991-1997,       ASIM/LIP6/UPMC
-                 E-mail support: alliance-support@asim.lip6.fr
-
-
-        o loading technology file : /usr/local/cad/alliance/etc/prol10_7.rds
-        o loading all level of symbolic layout : addaccu
-        o removing symbolic data structure 
-        o layout post-treating with connectors, with scotchs.
-        --> post-treating model palo_sp
-            rectangle merging : 
-            . RDS_NWELL .................................
-            . RDS_NIMP .................................
-            . RDS_PIMP .................................
-            . RDS_ACTIV .................................
-            . RDS_POLY .................................
-            . RDS_ALU1 .................................
-            . RDS_ALU2 .................................
-            .
-            .
-            .
-        o replacing black boxes
-        --> replace cell padreal 
-        o saving addaccu.cif
-        o memory allocation informations
-        --> required rectangles = 7318  really allocated = 7
-        --> required scotchs = 3  really created = 3
-        --> Number of allocated bytes: 341231
-\end{framedverbatim}
-\caption{Translating the symbolic layout into process layout with \texttt{s2r}.}
-\label{s2r}
-\end{figure}
-\normalsize
-
-%%%%%%%%%%%%%%%%%%%%%%%%
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\section{Conclusion}
-
-If you actually arrived here doing all the previous steps,
-congratulation!
-
-You can see an automatic replay of this tutorial by
-executing the \texttt{Makefile} in the current directory by issuing the
-command:
-\begin{phraseverbatim}
-~fred/addaccu %-) make
-\end{phraseverbatim}
-Note that the \texttt{Makefile} uses Bourne-shell commands.
-
-If you plan to design a chip with \textbf{Alliance}, it is a good idea to
-use \texttt{Makefile}s to ensure the consistency between the design and
-verifications of the differents views and hierarchies, but this is
-another story.
-
-If anything went wrong or if you have any question, you can contact
-us by sending a mail to the support team of \textbf{Alliance}, located 
-at \texttt{alliance-support@lip6.fr}.
-\end{document}
diff --git a/alliance/share/tutorials/addaccu/tex/hierarchy.eps b/alliance/share/tutorials/addaccu/tex/hierarchy.eps
deleted file mode 100644
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diff --git a/alliance/share/tutorials/addaccu/tex/hierarchy.fig b/alliance/share/tutorials/addaccu/tex/hierarchy.fig
deleted file mode 100644
index 4d114662..00000000
--- a/alliance/share/tutorials/addaccu/tex/hierarchy.fig
+++ /dev/null
@@ -1,98 +0,0 @@
-#FIG 3.1
-Portrait
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--6
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--6
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--6
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-4 0 0 6 0 14 12 0.0000000 4 180 630 5131 3468 pi_sp \001
--6
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--6
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--6
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--6
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-4 0 0 6 0 14 12 0.0000000 4 30 315 10103 3481 ...\001
--6
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--6
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--6
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--6
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--6
--6
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-	 4410 2115 8325 3105
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-	 2565 4050 1530 4995
-2 1 0 1 -1 7 0 0 -1 0.000 0 0 -1 1 0 2
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-2 1 0 1 -1 7 0 0 -1 0.000 0 0 -1 1 0 2
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-2 1 0 1 -1 7 0 0 -1 0.000 0 0 -1 1 0 2
-	1 1 1.00 60.00 120.00
-	 3735 2160 3015 3060
-4 0 -1 0 0 14 12 0.0000000 4 135 420 1229 5556 ms_y\001
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-4 0 -1 0 0 14 12 0.0000000 4 180 420 4334 5579 n1_y\001
-4 0 -1 0 0 14 12 0.0000000 4 135 735 3681 1776 addaccu\001
-4 0 -1 0 0 14 12 0.0000000 4 180 735 6652 3577 piot_sp\001
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-4 0 -1 0 0 14 12 0.0000000 4 30 315 10011 3569 ...\001
-4 0 -1 0 0 14 12 0.0000000 4 90 420 2534 3599 core\001
diff --git a/alliance/share/tutorials/addaccu/vecteurs.pat b/alliance/share/tutorials/addaccu/vecteurs.pat
deleted file mode 100644
index be4e29ba..00000000
--- a/alliance/share/tutorials/addaccu/vecteurs.pat
+++ /dev/null
@@ -1,284 +0,0 @@
-
--- description generated by Pat driver v104
---			date : Wed May 28 12:25:39 1997
-
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diff --git a/alliance/share/tutorials/amd2901/AMD2901-doc.tgz b/alliance/share/tutorials/amd2901/AMD2901-doc.tgz
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diff --git a/alliance/share/tutorials/amd2901/Makefile b/alliance/share/tutorials/amd2901/Makefile
deleted file mode 100644
index 90b81903..00000000
--- a/alliance/share/tutorials/amd2901/Makefile
+++ /dev/null
@@ -1,254 +0,0 @@
-SHELL    = /bin/sh
-
-# ASIMUT   = $(ALLIANCE_TOP)/bin/asimut -zd -i 0 -bdd
-ASIMUT   = echo
-YAGLE    = $(ALLIANCE_TOP)/bin/yagle
-DRUC     = $(ALLIANCE_TOP)/bin/druc
-
-GRAAL    = $(ALLIANCE_TOP)/bin/graal
-DREAL    = $(ALLIANCE_TOP)/bin/dreal
-GRAAL    = echo
-DREAL    = echo
-TOUCH    = touch
-
-GENLIB   = $(ALLIANCE_TOP)/bin/genlib
-LVX      = $(ALLIANCE_TOP)/bin/lvx
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-PROOF    = $(ALLIANCE_TOP)/bin/proof
-RING     = $(ALLIANCE_TOP)/bin/ring
-S2R      = $(ALLIANCE_TOP)/bin/s2r -v
-SCR      = $(ALLIANCE_TOP)/bin/scr
-TAS      = $(ALLIANCE_TOP)/bin/tas
-
-#################################################################
-#   S2R is the final step of the conception, it generates the   # 
-#   real layout description using the desired technology        #
-#################################################################
-
-all : amd2901.cif chip.ttv
-
-chip.ttv : chip.al
-	MBK_IN_LO=al; \
-	MBK_CATA_LIB=.:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/padlib; \
-	export MBK_IN_LO MBK_CATA_LIB; \
-	$(TAS) chip
-
-amd2901.cif : proof_end
-	MBK_IN_PH=ap ;\
-	MBK_WORK_LIB=. ;\
-	MBK_CATA_LIB=.:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/padlib;\
-	RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/prol10_8.rds ;\
-	RDS_IN=cif ;\
-	RDS_OUT=cif ;\
-	export MBK_IN_PH MBK_WORK_LIB MBK_CATA_LIB RDS_TECHNO_NAME RDS_IN RDS_OUT;\
-	$(S2R) -c chip amd2901;\
-	$(DREAL) -l amd2901
-
-#################################################################
-# PROOF between amd.vbe chip.vbe				#
-#################################################################
-
-proof_end : chip.vbe 
-	MBK_WORK_LIB=. ;\
-	export MBK_WORK_LIB;\
-	$(PROOF) -a -d amd chip
-	$(TOUCH) proof_end
-
-#################################################################
-# YAGLE on the chip						#
-#################################################################
-
-chip.vbe : asimut_end
-	MBK_IN_LO=al ;\
-	MBK_WORK_LIB=. ;\
-	MBK_CATA_LIB=.:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/padlib ;\
-	export MBK_IN_LO MBK_WORK_LIB MBK_CATA_LIB;\
-	$(YAGLE) chip -i -v
-
-#################################################################
-# asimut of the chip						#
-#################################################################
-
-asimut_end : lvx_chip
-	MBK_IN_LO=al ;\
-	MBK_WORK_LIB=. ;\
-	MBK_CATA_LIB=.:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/padlib ;\
-	export MBK_IN_LO MBK_WORK_LIB MBK_CATA_LIB;\
-	VH_PATSFX=pat; export VH_PATSFX;\
-	VH_MAXERR=10000; export VH_MAXERR;\
-	$(ASIMUT) chip pattern res_pattern
-	$(TOUCH) asimut_end
-
-#################################################################
-#   LVX of the chip                                             #
-#################################################################
-
-lvx_chip : chip.al
-	MBK_WORK_LIB=. ;\
-	MBK_CATA_LIB=.:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/padlib;\
-	export MBK_WORK_LIB MBK_CATA_LIB;\
-	$(LVX) vst al chip chip
-	$(TOUCH) lvx_chip
-
-#################################################################
-#   LYNX of the chip                                            #
-#################################################################
-
-chip.al : druc_chip
-	MBK_OUT_LO=al ;\
-	MBK_IN_PH=ap ;\
-	MBK_WORK_LIB=. ;\
-	MBK_CATA_LIB=.:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/padlib;\
-	export MBK_OUT_LO MBK_IN_PH MBK_WORK_LIB MBK_CATA_LIB;\
-	$(LYNX) chip 
-
-#################################################################
-#   DRUC is a design rules checker, it looks for design         #
-#   in the layout description "chip.ap"                         #
-#################################################################
-
-druc_chip : chip.ap 
-	MBK_IN_PH=ap ;\
-	MBK_WORK_LIB=. ;\
-	MBK_CATA_LIB=.:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/padlib;\
-	RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/cmos_8.rds ;\
-        RDS_IN=cif; RDS_OUT=cif;\
-	export MBK_IN_PH MBK_WORK_LIB MBK_CATA_LIB RDS_TECHNO_NAME RDS_IN RDS_OUT;\
-	$(DRUC) chip
-	$(TOUCH) druc_chip
-
-
-#################################################################
-#   RING routes the connections between the pads and the heart. #
-#################################################################
-
-chip.ap : lvx_heart chip.rin
-	MBK_IN_LO=vst ;\
-	MBK_IN_PH=ap ;\
-	MBK_OUT_PH=ap ;\
-	MBK_WORK_LIB=. ;\
-	MBK_CATA_LIB=.:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/padlib;\
-	export MBK_IN_LO MBK_IN_PH MBK_OUT_PH MBK_WORK_LIB MBK_CATA_LIB;\
-	$(RING) chip chip;\
-	$(GRAAL) -l chip
-
-#################################################################
-#   LVX of the heart                                            #
-#################################################################
-
-lvx_heart : heart.al
-	MBK_WORK_LIB=. ;\
-	MBK_CATA_LIB=.:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/padlib;\
-	export MBK_WORK_LIB MBK_CATA_LIB;\
-	$(LVX) vst al heart heart -f
-	$(TOUCH) lvx_heart
-
-#################################################################
-#   LYNX of the heart                                           #
-#################################################################
-
-heart.al : druc_heart
-	MBK_OUT_LO=al ;\
-	MBK_IN_PH=ap ;\
-	MBK_WORK_LIB=. ;\
-	MBK_CATA_LIB=.:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/padlib ;\
-	export MBK_OUT_LO MBK_IN_PH MBK_WORK_LIB MBK_CATA_LIB;\
-	$(LYNX) heart 
-
-#################################################################
-#   DRUC is a design rules checker, it looks for design         #
-#   in the layout description "heart.ap"                        #
-#################################################################
-
-druc_heart : heart.ap
-	MBK_IN_PH=ap ;\
-	MBK_WORK_LIB=. ;\
-	MBK_CATA_LIB=.:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/padlib ;\
-	RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/cmos_8.rds ;\
-        RDS_IN=cif; RDS_OUT=cif;\
-	export MBK_IN_PH MBK_WORK_LIB MBK_CATA_LIB RDS_TECHNO_NAME RDS_IN RDS_OUT;\
-	$(DRUC) heart
-	$(TOUCH) druc_heart
-
-#################################################################
-#   SCR is a standard cells router, it makes an automatic       #
-#   placement and routing of the "heart.al" and gives the       #
-#   corresponding layout description "heart.ap".                #
-#################################################################
-
-heart.ap : asimut_vst
-	MBK_IN_PH=ap ;\
-	MBK_OUT_PH=ap ;\
-	MBK_IN_LO=vst ;\
-	MBK_WORK_LIB=. ;\
-	MBK_CATA_LIB=.:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/padlib;\
-	export MBK_IN_PH MBK_OUT_PH MBK_IN_LO MBK_WORK_LIB MBK_CATA_LIB ;\
-	$(SCR) -p -r heart;\
-#	$(GRAAL) -l heart
-
-#################################################################
-#   ASIMUT                                                      #
-#   This time the "chip.vst" is                                 #
-#   simulated by ASIMUT, using the test patternss "pattern.pat" #
-#   previously generated in the behaviour step.                 #
-#################################################################
-
-asimut_vst : chip.vst
-	MBK_IN_LO=vst ;\
-	MBK_WORK_LIB=. ;\
-	MBK_CATA_LIB=.:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/padlib ;\
-	VH_PATSFX=pat; export VH_PATSFX;\
-	VH_MAXERR=10000; export VH_MAXERR;\
-	export MBK_IN_LO MBK_WORK_LIB MBK_CATA_LIB;\
-	$(ASIMUT) chip pattern result_str
-	$(TOUCH) asimut_vst
-
-#################################################################
-#   GENLIB is a procedural design language upon C.              #
-#   every netlist source files with a ".c" extension are compiled
-#   by GENLIB which gives the corresponding gate netlists ended #
-#   by ".vst" extension                                         #
-#################################################################
-
-chip.vst : asimut_vbe chip.c
-	(MBK_IN_LO=vst ;\
-	MBK_OUT_LO=vst ;\
-	MBK_WORK_LIB=. ;\
-	MBK_CATA_LIB=.:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/padlib ;\
-	export MBK_IN_LO MBK_OUT_LO MBK_WORK_LIB MBK_CATA_LIB;\
-	$(GENLIB) -v chip)
-
-#################################################################
-#   ASIMUT                                                      #
-#   the  hardware behaviour description "amd.vbe" is            #
-#   simulated by ASIMUT, using the test patterns                #
-#   previously generated in "pattern.pat".                      #
-#################################################################
-
-
-asimut_vbe : asimut_first
-	MBK_WORK_LIB=. ;\
-	MBK_CATA_LIB=.:$(ALLIANCE_TOP)/cells/sc2sxlib:$(ALLIANCE_TOP)/cells/sxlib:$(ALLIANCE_TOP)/cells/padlib;\
-	export MBK_WORK_LIB MBK_CATA_LIB;\
-	$(ASIMUT) -b amd pattern result_beh
-	$(TOUCH) asimut_vbe
-
-#################################################################
-#  Asimut compilation						#
-#################################################################
-
-asimut_first : amd.vbe
-	MBK_WORK_LIB=. ;\
-	MBK_CATA_LIB=. ; \
-	export MBK_WORK_LIB MBK_CATA_LIB;\
-	VH_PATSFX=pat; export VH_PATSFX;\
-	VH_MAXERR=10000; export VH_MAXERR;\
-	$(ASIMUT) -b -c amd
-	$(TOUCH) asimut_first
-
-clean :
-	rm -f *.vst r*.pat *.al *.ap *.grr *.err
-	rm -f *.o asimut_* druc_* lvx_* proof_*
-	rm -f *.lis *.cif chip.vbe chip.d* *.SHP
-	rm -f chip.fcf *.drc *.ttv
-	rm -f chip.rep chip.ttx  chip_drc.gds chip_rng.gds heart_drc.gds heart_rng.gds *~
diff --git a/alliance/share/tutorials/amd2901/amd.vbe b/alliance/share/tutorials/amd2901/amd.vbe
deleted file mode 100644
index 69aa2137..00000000
--- a/alliance/share/tutorials/amd2901/amd.vbe
+++ /dev/null
@@ -1,507 +0,0 @@
--- AMD2901's behavioral description 
---
--- Connector's declaration
---
-ENTITY amd IS
-PORT (
-       cke        : IN BIT;
-       fonc      : IN BIT;
-       test      : IN BIT;
-       scin      : IN BIT;
-       scout     : OUT BIT;
-       i         : IN BIT_VECTOR (8 DOWNTO 0);
-       a         : IN BIT_VECTOR (3 DOWNTO 0);
-       b         : IN BIT_VECTOR (3 DOWNTO 0);
-       d         : IN BIT_VECTOR (3 DOWNTO 0);
-       noe       : IN BIT;
-       r0        : INOUT MUX_BIT bus;
-       r3        : INOUT MUX_BIT bus;
-       q0        : INOUT MUX_BIT bus;
-       q3        : INOUT MUX_BIT bus;
-       ovr       : OUT BIT;
-       zero      : OUT BIT;
-       signe     : OUT BIT;
-       np        : OUT BIT;
-       ng        : OUT BIT;
-       cin       : IN BIT;
-       cout      : OUT BIT;
-       y         : OUT MUX_VECTOR (3 DOWNTO 0) bus;
-       vddi       : IN BIT;
-       vssi       : IN BIT;
-       vdde      : IN BIT;
-       vsse      : IN BIT
-     );
-END amd;
---
-ARCHITECTURE data_flow OF amd IS
---
--- Internal registers
---
---
-SIGNAL accu      : REG_VECTOR (3 DOWNTO 0) register;
-SIGNAL ram0      : REG_VECTOR (3 DOWNTO 0) register; 
-SIGNAL ram1      : REG_VECTOR (3 DOWNTO 0) register; 
-SIGNAL ram2      : REG_VECTOR (3 DOWNTO 0) register; 
-SIGNAL ram3      : REG_VECTOR (3 DOWNTO 0) register; 
-SIGNAL ram4      : REG_VECTOR (3 DOWNTO 0) register; 
-SIGNAL ram5      : REG_VECTOR (3 DOWNTO 0) register; 
-SIGNAL ram6      : REG_VECTOR (3 DOWNTO 0) register; 
-SIGNAL ram7      : REG_VECTOR (3 DOWNTO 0) register; 
-SIGNAL ram8      : REG_VECTOR (3 DOWNTO 0) register; 
-SIGNAL ram9      : REG_VECTOR (3 DOWNTO 0) register; 
-SIGNAL ram10     : REG_VECTOR (3 DOWNTO 0) register; 
-SIGNAL ram11     : REG_VECTOR (3 DOWNTO 0) register; 
-SIGNAL ram12     : REG_VECTOR (3 DOWNTO 0) register; 
-SIGNAL ram13     : REG_VECTOR (3 DOWNTO 0) register; 
-SIGNAL ram14     : REG_VECTOR (3 DOWNTO 0) register; 
-SIGNAL ram15     : REG_VECTOR (3 DOWNTO 0) register; 
---
--- Internal signals
---
---
-SIGNAL r         : BIT_VECTOR (3 DOWNTO 0);
-SIGNAL s         : BIT_VECTOR (3 DOWNTO 0);
-SIGNAL alu_out   : BIT_VECTOR (3 DOWNTO 0);
-SIGNAL sumrs     : BIT_VECTOR (3 DOWNTO 0);
-SIGNAL difrs     : BIT_VECTOR (3 DOWNTO 0);
-SIGNAL difsr     : BIT_VECTOR (3 DOWNTO 0);
-SIGNAL c_sumrs   : BIT_VECTOR (3 DOWNTO 0);
-SIGNAL c_difrs   : BIT_VECTOR (3 DOWNTO 0);
-SIGNAL c_difsr   : BIT_VECTOR (3 DOWNTO 0);
-SIGNAL waccu     : BIT;
-SIGNAL fonc_mode : BIT;
-SIGNAL test_mode : BIT;
-sIGNAL shift_n   : BIT;
-SIGNAL shift_l   : BIT;
-SIGNAL shift_r   : BIT;
-SIGNAL sh_acc    : BIT_VECTOR (3 DOWNTO 0);
-SIGNAL sh_ram    : BIT_VECTOR (3 DOWNTO 0);
-SIGNAL wram      : BIT;
-SIGNAL wck0      : BIT ;
-SIGNAL wck1      : BIT ;
-SIGNAL wck2      : BIT ;
-SIGNAL wck3      : BIT ;
-SIGNAL wck4      : BIT ;
-SIGNAL wck5      : BIT ;
-SIGNAL wck6      : BIT ;
-SIGNAL wck7      : BIT ;
-SIGNAL wck8      : BIT ;
-SIGNAL wck9      : BIT ;
-SIGNAL wck10     : BIT ;
-SIGNAL wck11     : BIT ;
-SIGNAL wck12     : BIT ;
-SIGNAL wck13     : BIT ;
-SIGNAL wck14     : BIT ;
-SIGNAL wck15     : BIT ;
-SIGNAL wckaccu   : BIT ;
-SIGNAL accu_in   : BIT_VECTOR ( 3 DOWNTO 0 ) ;
-SIGNAL ra        : BIT_VECTOR ( 3 DOWNTO 0 ) ;
-SIGNAL rb        : BIT_VECTOR ( 3 DOWNTO 0 ) ;
---
-BEGIN
---
---
--- ALU-INPUT MULTIPLEXER 
---
-WITH i(2 DOWNTO 0) SELECT
-     s <= ra       WHEN "100",
-          ra       WHEN "101",
-          rb       WHEN "001",
-          rb       WHEN "011",
-          NOT accu WHEN "000",
-          NOT accu WHEN "010",
-          NOT accu WHEN "110",
-          "0000"   WHEN "111";
---
---
-WITH i(2 DOWNTO 0) SELECT
-     r <= ra       WHEN "000",
-          ra       WHEN "001",
-          "0000"   WHEN "010",
-          "0000"   WHEN "011",
-          "0000"   WHEN "100",
-          d        WHEN "101", 
-          d WHEN "110", 
-          d WHEN "111"; 
---
---
---
---
---  THREE-STATE OUTPUT MULTIPLEXER 
---
-muxs: BLOCK (noe='0')
-BEGIN
-WITH i(8 DOWNTO 6) SELECT
-     y <= GUARDED ra WHEN "010",
-          alu_out WHEN "000",
-          alu_out WHEN "001",
-          alu_out WHEN "011",
-          alu_out WHEN "100",
-          alu_out WHEN "101",
-          alu_out WHEN "110",
-          alu_out WHEN "111";
-END BLOCK;
---
---
---
---
--- Arithmetic and Logic Unit 
---
---  r+s
---
-sumrs(3 DOWNTO 0)   <=  r(3 DOWNTO 0) XOR 
-                        s(3 DOWNTO 0) XOR 
-                       (c_sumrs(2 DOWNTO 0) & cin);
-c_sumrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR 
-                       (r(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin)) OR
-                       (s(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin));
---
---  r-s
---
-difrs(3 DOWNTO 0)   <=  r(3 DOWNTO 0) XOR 
-                        NOT s(3 DOWNTO 0) XOR 
-                       (c_difrs(2 DOWNTO 0) & cin);
-c_difrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND NOT s(3 DOWNTO 0)) OR 
-                       (r(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin)) OR
-                       (NOT s(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin));
---
---  s-r
---
-difsr(3 DOWNTO 0)   <=  NOT r(3 DOWNTO 0) XOR 
-                        s(3 DOWNTO 0) XOR 
-                       (c_difsr(2 DOWNTO 0) & cin);
-c_difsr(3 DOWNTO 0) <= (NOT r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR 
-                       (NOT r(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin)) OR
-                       (s(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin));
---
--- P &G FLAGS
---
-WITH i(5 DOWNTO 3) SELECT
-ng <= NOT ((r(3) AND s(3)) OR ((r(3) OR s(3)) AND (r(2) AND s(2))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) AND s(1))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) AND s(0)))) WHEN "000",
-      NOT ((NOT r(3) AND s(3)) OR ((NOT r(3) OR s(3)) AND (NOT r(2) AND s(2))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) AND s(1))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) AND s(0)))) WHEN "001",
-      NOT ((r(3) AND NOT s(3)) OR ((r(3) OR NOT s(3)) AND (r(2) AND NOT s(2))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) AND NOT s(1))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) AND NOT s(0))))WHEN "010",
-      "1" WHEN OTHERS;
---
---
-WITH i(5 DOWNTO 3) SELECT
-np <= NOT ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) OR s(0))) WHEN "000",
-      NOT ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) OR s(0))) WHEN "001",
-      NOT ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) OR NOT s(0))) WHEN "010",
-      "1" WHEN OTHERS;
---
---
-signe <= alu_out(3);
-zero <= NOT (alu_out(3) OR alu_out(2) OR alu_out(1) OR alu_out(0));
---
---
-WITH i(5 DOWNTO 3) SELECT
-ovr <= c_sumrs(3) XOR c_sumrs(2) WHEN "000",
-       c_difsr(3) XOR c_difsr(2) WHEN "001",
-       c_difrs(3) XOR c_difrs(2) WHEN "010",
-       '0'                       WHEN OTHERS;
---
---
-WITH i(5 DOWNTO 3) SELECT
-alu_out <= sumrs         WHEN "000",
-           difsr         WHEN "001",
-           difrs         WHEN "010",
-           r OR s        WHEN "011",
-           r AND s       WHEN "100",
-           NOT(r) AND s  WHEN "101",
-           r XOR s       WHEN "110",
-           NOT(r XOR s)  WHEN "111";
---
---
-WITH i(5 DOWNTO 3) SELECT
-cout <= c_sumrs(3) WHEN "000",
-        c_difsr(3) WHEN "001",
-        c_difrs(3) WHEN "010",
-        "0"        WHEN OTHERS;
---
---
---
---
--- CONTROL SIGNALS
---
---
-wram <= (i(8) OR i(7)) AND fonc_mode;
-waccu <= NOT (i(6)) AND ((NOT i(7)) OR i(8));
-fonc_mode <= fonc AND (NOT test);
-test_mode <= test AND (NOT fonc);
-shift_r <= i(8) AND (NOT i(7));  
-shift_l <= i(8) AND i(7);  
-shift_n <= NOT i(8);  
---
---
---
---
--- SHIFTER ACCU
---
-WITH i(8 DOWNTO 6) SELECT
-     sh_acc(3) <= alu_out(3)        WHEN "000",
-                  NOT accu(2)       WHEN "110",
-                  NOT accu(2)       WHEN "111",
-                  q3                WHEN "100",
-                  q3                WHEN "101",
-                  "0"               WHEN OTHERS;
---
-WITH i(8 DOWNTO 6) SELECT
-     sh_acc(2) <= alu_out(2)        WHEN "000",
-                  NOT accu(1)       WHEN "110",
-                  NOT accu(1)       WHEN "111",
-                  NOT accu(3)       WHEN "100",
-                  NOT accu(3)       WHEN "101",
-                  "0"               WHEN OTHERS;
---
-WITH i(8 DOWNTO 6) SELECT
-     sh_acc(1) <= alu_out(1)        WHEN "000",
-                  NOT accu(0)       WHEN "110",
-                  NOT accu(0)       WHEN "111",
-                  NOT accu(2)       WHEN "100",
-                  NOT accu(2)       WHEN "101",
-                  "0"               WHEN OTHERS;
---
-WITH i(8 DOWNTO 6) SELECT
-     sh_acc(0) <= alu_out(0)        WHEN "000",
-                  q0                WHEN "110",
-                  q0                WHEN "111",
-                  NOT accu(1)       WHEN "100",
-                  NOT accu(1)       WHEN "101",
-                  "0"               WHEN OTHERS;
---
---
---
---
-esq3 : BLOCK (i(8 DOWNTO 6)="110" OR i(8 DOWNTO 6)="111")
-BEGIN
-     q3 <=  GUARDED NOT accu(3);
-END BLOCK;
---
-esq0 : BLOCK (i(8 DOWNTO 6)="100" OR i(8 DOWNTO 6)="101")
-BEGIN
-     q0 <=  GUARDED NOT accu(0);
-END BLOCK;
---
---
---
---
--- WRITING ACCU
---
-wckaccu <= cke AND (test_mode OR (waccu AND fonc_mode));
-WITH test_mode SELECT
-accu_in(3 DOWNTO 0) <= sh_acc(3 DOWNTO 0) WHEN "0" ,
-                       (NOT accu(2 DOWNTO 0)) & scin WHEN "1" ;
-
-accu : BLOCK ((wckaccu='0') AND NOT wckaccu'STABLE)
-BEGIN
-accu <= GUARDED NOT accu_in;
-END BLOCK accu;
---
---
-scout <= NOT accu(3) AND test_mode ;
---
---
---
---
--- SHIFTER - RAM 
---
---
-WITH shift_n & shift_l & shift_r SELECT
-       sh_ram(3) <= alu_out(3) WHEN "100",
-                    alu_out(2) WHEN "010",
-                    r3         WHEN "001",
-                    "0"        WHEN OTHERS;
---
-WITH shift_n & shift_l & shift_r SELECT
-       sh_ram(2) <= alu_out(2) WHEN "100",
-                    alu_out(1) WHEN "010",
-                    alu_out(3) WHEN "001",
-                    "0"        WHEN OTHERS;
---
-WITH shift_n & shift_l & shift_r SELECT
-       sh_ram(1) <= alu_out(1) WHEN "100",
-                    alu_out(0) WHEN "010",
-                    alu_out(2) WHEN "001",
-                    "0"        WHEN OTHERS;
---
-WITH shift_n & shift_l & shift_r SELECT
-       sh_ram(0) <= alu_out(0) WHEN "100",
-                    r0         WHEN "010",
-                    alu_out(1) WHEN "001",
-                    "0"        WHEN OTHERS;
---
---
---
---
-esr3 : BLOCK (shift_l='1')
-BEGIN
-     r3 <=  GUARDED alu_out(3);
-END BLOCK;
---
-esr0 : BLOCK (shift_r='1')
-BEGIN
-     r0 <=  GUARDED alu_out(0);
-END BLOCK;
---
---
--- Writing RAM adress b
---
-
--- b="0000"
-wck0 <= cke AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
-RM0 : BLOCK ((wck0='0') AND NOT wck0'STABLE)
-BEGIN
-ram0 <= GUARDED NOT sh_ram;
-END BLOCK;
-
--- b="0001"
-wck1 <= cke AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND b(0);
-RM1 : BLOCK ((wck1='0') AND NOT wck1'STABLE)
-BEGIN
-ram1 <= GUARDED NOT sh_ram;  
-END BLOCK;
- 
--- b="0010"
-wck2 <= cke AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND NOT b(0);
-RM2 : BLOCK ((wck2='0') AND NOT wck2'STABLE)
-BEGIN
-ram2 <= GUARDED NOT sh_ram;
-END BLOCK;
-
--- b="0011"
-wck3 <= cke AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND b(0);
-RM3 : BLOCK ((wck3='0') AND NOT wck3'STABLE)
-BEGIN
-ram3 <= GUARDED NOT sh_ram;  
-END BLOCK;
-
--- b="0100"
-wck4 <= cke AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND NOT b(0);
-RM4 : BLOCK ((wck4='0') AND NOT wck4'STABLE)
-BEGIN
-ram4 <= GUARDED NOT sh_ram;
-END BLOCK;
-
--- b="0101"
-wck5 <= cke AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND b(0);
-RM5 : BLOCK ((wck5='0') AND NOT wck5'STABLE)
-BEGIN
-ram5 <= GUARDED NOT sh_ram;  
-END BLOCK;
-
--- b="0110"
-wck6 <= cke AND wram AND NOT b(3) AND b(2) AND b(1) AND NOT b(0);
-RM6 : BLOCK ((wck6='0') AND NOT wck6'STABLE)
-BEGIN
-ram6 <= GUARDED NOT sh_ram;
-END BLOCK;
-
--- b="0111"
-wck7 <= cke AND wram AND NOT b(3) AND b(2) AND b(1) AND b(0);
-RM7 : BLOCK ((wck7='0') AND NOT wck7'STABLE)
-BEGIN
-ram7 <= GUARDED NOT sh_ram;  
-END BLOCK;
-
--- b="1000"
-wck8 <= cke AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
-RM8 : BLOCK ((wck8='0') AND NOT wck8'STABLE)
-BEGIN
-ram8 <= GUARDED NOT sh_ram;
-END BLOCK;
-
--- b="1001"
-wck9 <= cke AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND b(0);
-RM9 : BLOCK ((wck9='0') AND NOT wck9'STABLE)
-BEGIN
-ram9 <= GUARDED NOT sh_ram;  
-END BLOCK;
-
--- b="1010"
-wck10 <= cke AND wram AND b(3) AND NOT b(2) AND b(1) AND NOT b(0);
-RM10 : BLOCK ((wck10='0') AND NOT wck10'STABLE)
-BEGIN
-ram10 <= GUARDED NOT sh_ram;
-END BLOCK;
-
--- b="1011"
-wck11 <= cke AND wram AND b(3) AND NOT b(2) AND b(1) AND b(0);
-RM11 : BLOCK ((wck11='0') AND NOT wck11'STABLE)
-BEGIN
-ram11 <= GUARDED NOT sh_ram;  
-END BLOCK;
-
--- b="1100"
-wck12 <= cke AND wram AND b(3) AND b(2) AND NOT b(1) AND NOT b(0);
-RM12 : BLOCK ((wck12='0') AND NOT wck12'STABLE)
-BEGIN
-ram12 <= GUARDED NOT sh_ram;
-END BLOCK;
-
--- b="1101"
-wck13 <= cke AND WRAM and b(3) AND b(2) AND NOT b(1) AND b(0);
-RM13 : BLOCK ((wck13='0') AND NOT wck13'STABLE)
-BEGIN
-ram13 <= GUARDED NOT sh_ram;  
-END BLOCK;
-
--- b="1110"
-wck14 <= cke AND WRAM and b(3) AND b(2) AND b(1) AND NOT b(0);
-RM14 : BLOCK ((wck14='0') AND NOT wck14'STABLE)
-BEGIN
-ram14 <= GUARDED NOT sh_ram;
-END BLOCK;
-
--- b="1111"
-wck15 <= cke AND WRAM and b(3) AND b(2) AND b(1) AND b(0);
-RM15 : BLOCK ((wck15='0') AND NOT wck15'STABLE)
-BEGIN
-ram15 <= GUARDED NOT sh_ram;  
-END BLOCK;
---
---
---
--- Reading RAM address b
---
-with b select 
-    rb <= NOT ram0  WHEN "0000",
-          NOT ram1  WHEN "0001",
-          NOT ram2  WHEN "0010",
-          NOT ram3  WHEN "0011",
-          NOT ram4  WHEN "0100",
-          NOT ram5  WHEN "0101",
-          NOT ram6  WHEN "0110",
-          NOT ram7  WHEN "0111",
-          NOT ram8  WHEN "1000",
-          NOT ram9  WHEN "1001",
-          NOT ram10 WHEN "1010",
-          NOT ram11 WHEN "1011",
-          NOT ram12 WHEN "1100",
-          NOT ram13 WHEN "1101",
-          NOT ram14 WHEN "1110",
-          NOT ram15 WHEN "1111";
---
---
---
--- Reading RAM address a
---
-with a select 
-    ra <= NOT ram0  WHEN "0000",
-          NOT ram1  WHEN "0001",
-          NOT ram2  WHEN "0010",
-          NOT ram3  WHEN "0011",
-          NOT ram4  WHEN "0100",
-          NOT ram5  WHEN "0101",
-          NOT ram6  WHEN "0110",
-          NOT ram7  WHEN "0111",
-          NOT ram8  WHEN "1000",
-          NOT ram9  WHEN "1001",
-          NOT ram10 WHEN "1010",
-          NOT ram11 WHEN "1011",
-          NOT ram12 WHEN "1100",
-          NOT ram13 WHEN "1101",
-          NOT ram14 WHEN "1110",
-          NOT ram15 WHEN "1111";
---
---
-END data_flow;  
diff --git a/alliance/share/tutorials/amd2901/amd2901.pdf b/alliance/share/tutorials/amd2901/amd2901.pdf
deleted file mode 100644
index 82aea2d4..00000000
Binary files a/alliance/share/tutorials/amd2901/amd2901.pdf and /dev/null differ
diff --git a/alliance/share/tutorials/amd2901/amd2901.ps b/alliance/share/tutorials/amd2901/amd2901.ps
deleted file mode 100644
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-e(sym)m(b)s(olic)g(la)m(y)m(out)i(\(all)e(co)s(ordinates)h(in)f
-Ff(lam)m(b)s(da)p Fg(-units\).)80 b(W)-8 b(e)270 4276
-y(should)29 b(no)m(w)h(con)m(v)m(ert)j(them)d(to)i(real)e(dimensions,)e
-(creating)j(the)g(ph)m(ysical)f(la)m(y)m(out)h(\(t)m(w)m(o)270
-4389 y(output)c(formats)h(are)g(supp)s(orted)d(:)40 b(CIF)27
-b(and)g(GDSI)s(I\).)g(This)f(last)h(step)h(is)e(done)i(b)m(y)f
-Ff(s2r)p Fg(.)270 4502 y Ff(s2r)22 b Fg(p)s(erforms)e(sym)m(b)s(olic)g
-(to)i(real)f(expansion,)h(gap)g(\014lling,)f(denotc)m(hing)g(and)g
-(instan)m(tiates)270 4615 y(preexisting)29 b(ph)m(ysical)g(cells)g
-(\(this)h(is)f(necessary)i(for)f(the)h(pads\).)411 4728
-y(Y)-8 b(ou)31 b(m)m(ust)f(de\014ne)g(3)h(new)f(en)m(vironmen)m(t)f(v)
--5 b(ariables)30 b(:)p 270 4853 2966 4 v 270 5098 4 246
-v 329 4946 a Fd(>)k Ff(RDS)p 656 4946 32 4 v 38 w(TECHNO)p
-1155 4946 V 36 w(NAME=/$ALLIANCE)p 2256 4946 V 37 w(TOP/etc/prol10.rds)
-329 5056 y Fd(>)g Ff(exp)s(ort)h(RDS)p 991 5056 V 38
-w(TECHNO)p 1490 5056 V 36 w(NAME)p 3233 5098 4 246 v
-270 5101 2966 4 v 270 5281 a Fg(The)25 b Ff(prol10.rds)i
-Fg(is)d(the)i(tec)m(hnology)h(\014le)d(that)j(con)m(tains)e(the)h
-(parameters)g(corresp)s(ond-)270 5394 y(ing)k(to)h(the)f(target)i(pro)s
-(cess.)40 b(\(In)30 b(this)g(case)h(the)g(target)h(pro)s(cess)d(is)h(1)
-h(micron.\))1785 5841 y(10)p eop
-%%Page: 11 11
-11 10 bop 270 311 1014 4 v 270 532 4 222 v 329 399 a
-Fd(>)34 b Ff(RDS)p 656 399 32 4 v 38 w(OUT=)h(cif)329
-489 y Fd(>)f Ff(exp)s(ort)h(RDS)p 991 489 V 38 w(OUT)p
-1280 532 4 222 v 270 535 1014 4 v 270 715 a Fg(De\014nes)30
-b(the)h(output)f(format.)p 270 840 903 4 v 270 1061 4
-222 v 329 928 a Fd(>)k Ff(RDS)p 656 928 32 4 v 38 w(IN=cif)329
-1019 y Fd(>)g Ff(exp)s(ort)h(RDS)p 991 1019 V 38 w(IN)p
-1170 1061 4 222 v 270 1064 903 4 v 270 1244 a Fg(De\014nes)30
-b(the)h(input)d(format)j(for)f(the)h(preexisting)e(la)m(y)m(out)i
-(cells)e(\(pads\).)411 1357 y(Y)-8 b(ou)31 b(will)d(en)m(ter)j(:)p
-270 1482 4860 4 v 270 2539 4 1058 v 329 1575 a Ff([)j
-Fd(>)h Ff(MBK)p 759 1575 32 4 v 38 w(IN)p 919 1575 V
-37 w(PH=ap)h(])329 1691 y([)e Fd(>)h Ff(MBK)p 759 1691
-V 38 w(W)m(ORK)p 1141 1691 V 38 w(LIB=.)47 b(])329 1807
-y([)34 b Fd(>)h Ff(MBK)p 759 1807 V 38 w(CA)-9 b(T)g(A)p
-1086 1807 V 38 w(LIB=.:/$ALLIANCE)p 2095 1807 V 37 w
-(TOP/cells/sclib/prol10:/$ALLIANCE)p 3877 1807 V 39 w
-(TOP/cells/ring/padsym)m(b])329 1922 y([)34 b Fd(>)h
-Ff(RDS)p 720 1922 V 38 w(TECHNO)p 1219 1922 V 36 w(NAME=/$ALLIANCE)p
-2320 1922 V 37 w(TOP/etc/prol10.rds)h(])329 2038 y([)e
-Fd(>)h Ff(RDS)p 720 2038 V 38 w(IN=cif)g(])329 2154 y([)f
-Fd(>)h Ff(RDS)p 720 2154 V 38 w(OUT=cif)10 b(])329 2270
-y([)34 b Fd(>)h Ff(exp)s(ort)g(RDS)p 1055 2270 V 38 w(OUT)g(MBK)p
-1615 2270 V 38 w(IN)p 1775 2270 V 37 w(PH)g(MBK)p 2255
-2270 V 38 w(W)m(ORK)p 2637 2270 V 38 w(LIB)509 2386 y(MBK)p
-770 2386 V 38 w(CA)-9 b(T)g(A)p 1097 2386 V 37 w(LIB)35
-b(RDS)p 1562 2386 V 38 w(TECHNO)p 2061 2386 V 36 w(NAME)g(RDS)p
-2677 2386 V 38 w(IN])329 2496 y Fd(>)f Ff(s2r)h(-c)h(c)m(hip)f(amd2901)
-p 5126 2539 4 1058 v 270 2542 4860 4 v 406 2684 a Fe(\017)46
-b Ff(-c)31 b Fg(deletes)f(connectors)i(at)f(the)f(highest)g(lev)m(el)g
-(of)h(hierarc)m(h)m(y)-8 b(.)411 2872 y(Y)g(ou)31 b(did)e(it...)270
-2985 y(The)h(\014le)f(pro)s(duced)g(is)g Ff(amd2901.cif)p
-Fg(.)42 b(It)30 b(is)g(ready)g(for)g(the)h(foundry)-8
-b(.)1785 5841 y(11)p eop
-%%Trailer
-end
-userdict /end-hook known{end-hook}if
-%%EOF
diff --git a/alliance/share/tutorials/amd2901/chip.c b/alliance/share/tutorials/amd2901/chip.c
deleted file mode 100644
index 1cbba7bf..00000000
--- a/alliance/share/tutorials/amd2901/chip.c
+++ /dev/null
@@ -1,938 +0,0 @@
-# include <genlib.h>
-main ()
-{
-DEF_LOFIG ("alu");
-/* declaration of the cell's external connectors */
-LOCON ("R[3:0]",'I',"r[3:0]");
-LOCON ("S[3:0]",'I',"s[3:0]");
-LOCON ("ALU_OUT[3:0]",'O',"alu_out[3:0]");
-LOCON ("CIN",'I',"cin");
-LOCON ("COUT",'O',"cout");
-LOCON ("NP",'O',"np");
-LOCON ("NG",'O',"ng");
-LOCON ("SIGNE",'O',"signe");
-LOCON ("ZERO",'O',"zero");
-LOCON ("OVR",'O',"ovr");
-LOCON ("I[5:3]",'I',"i[5:3]");
-LOCON ("VDD",'I',"vdd");
-LOCON ("VSS",'I',"vss");
-
-/* bit slice 0 */ 
-
-LOINS ("xr2_y","xor0_A0","r[0]","n0","x00","vdd","vss",0);
-LOINS ("xr2_y","xor1_A0","s[0]","n1","x10","vdd","vss",0);
-LOINS ("na2_y","nand0_A0","x00","x10","gb0","vdd","vss",0);
-LOINS ("no2_y","nor1_A0","x00","x10","pb0","vdd","vss",0);
-LOINS ("na2_y","nand1_A0","gb0","na20","cout0","vdd","vss",0);
-LOINS ("n1_y","not_A0","pb0","not0","vdd","vss",0);
-LOINS ("na2_y","nand2_A0","not0","cin","na20","vdd","vss",0);
-LOINS ("no2_y","nor2_A0","n2","gb0","no20","vdd","vss",0);
-LOINS ("no2_y","nor3_A0","n3","pb0","no30","vdd","vss",0);
-LOINS ("no2_y","nor4_A0","n4","cin","no40","vdd","vss",0);
-LOINS ("xr2_y","xor2_A0","no20","no30","x20","vdd","vss",0);
-LOINS ("xr2_y","xor3_A0","x20","no40","fb0","vdd","vss",0);
-
-/* bit slice 1 */
-
-LOINS ("xr2_y","xor0_A1","r[1]","n0","x01","vdd","vss",0);
-LOINS ("xr2_y","xor1_A1","s[1]","n1","x11","vdd","vss",0);
-LOINS ("na2_y","nand0_A1","x01","x11","gb1","vdd","vss",0);
-LOINS ("no2_y","nor1_A1","x01","x11","pb1","vdd","vss",0);
-LOINS ("na2_y","nand1_A1","gb1","na21","cout1","vdd","vss",0);
-LOINS ("n1_y","not_A1","pb1","not1","vdd","vss",0);
-LOINS ("na2_y","nand2_A1","not1","cout0","na21","vdd","vss",0);
-LOINS ("no2_y","nor2_A1","n2","gb1","no21","vdd","vss",0);
-LOINS ("no2_y","nor3_A1","n3","pb1","no31","vdd","vss",0);
-LOINS ("no2_y","nor4_A1","n4","cout0","no41","vdd","vss",0);
-LOINS ("xr2_y","xor2_A1","no21","no31","x21","vdd","vss",0);
-LOINS ("xr2_y","xor3_A1","x21","no41","fb1","vdd","vss",0);
-
-/* bit slice 2 */
-
-LOINS ("xr2_y","xor0_A2","r[2]","n0","x02","vdd","vss",0);
-LOINS ("xr2_y","xor1_A2","s[2]","n1","x12","vdd","vss",0);
-LOINS ("na2_y","nand0_A2","x02","x12","gb2","vdd","vss",0);
-LOINS ("no2_y","nor1_A2","x02","x12","pb2","vdd","vss",0);
-LOINS ("na2_y","nand1_A2","gb2","na22","cout2","vdd","vss",0);
-LOINS ("n1_y","not_A2","pb2","not2","vdd","vss",0);
-LOINS ("na2_y","nand2_A2","not2","cout1","na22","vdd","vss",0);
-LOINS ("no2_y","nor2_A2","n2","gb2","no22","vdd","vss",0);
-LOINS ("no2_y","nor3_A2","n3","pb2","no32","vdd","vss",0);
-LOINS ("no2_y","nor4_A2","n4","cout1","no42","vdd","vss",0);
-LOINS ("xr2_y","xor2_A2","no22","no32","x22","vdd","vss",0);
-LOINS ("xr2_y","xor3_A2","x22","no42","fb2","vdd","vss",0);
-
-/* bit slice 3 */
-
-LOINS ("xr2_y","xor0_A3","r[3]","n0","x03","vdd","vss",0);
-LOINS ("xr2_y","xor1_A3","s[3]","n1","x13","vdd","vss",0);
-LOINS ("na2_y","nand0_A3","x03","x13","gb3","vdd","vss",0);
-LOINS ("no2_y","nor1_A3","x03","x13","pb3","vdd","vss",0);
-LOINS ("na2_y","nand1_A3","gb3","na23","couta","vdd","vss",0);
-LOINS ("n1_y","not_A3","pb3","not3","vdd","vss",0);
-LOINS ("na2_y","nand2_A3","not3","cout2","na23","vdd","vss",0);
-LOINS ("no2_y","nor2_A3","n2","gb3","no23","vdd","vss",0);
-LOINS ("no2_y","nor3_A3","n3","pb3","no33","vdd","vss",0);
-LOINS ("no2_y","nor4_A3","n4","cout2","no43","vdd","vss",0);
-LOINS ("xr2_y","xor2_A3","no23","no33","x23","vdd","vss",0);
-LOINS ("xr2_y","xor3_A3","x23","no43","signea","vdd","vss",0);
-
-/* microinsruction decoder */
-
-LOINS ("n1_y","not5_D","i[5]","ni5","vdd","vss",0);
-LOINS ("na3_y","nand3_D","i[3]","i[4]","ni5","nn3","vdd","vss",0);
-LOINS ("no2_y","nor_D","i[4]","ni5","n2","vdd","vss",0);
-LOINS ("nxr2_y","nxor4_D","i[4]","i[5]","nn1","vdd","vss",0);
-LOINS ("nxr2_y","nxor3_D","i[3]","i[5]","nn0","vdd","vss",0);
-LOINS ("na2_y","nand_D","ni5","nn3","n4","vdd","vss",0);
-LOINS ("n1_y","not0_D","nn3","n3","vdd","vss",0);
-LOINS ("np1_y","notp4_D","nn1","n1","vdd","vss",0);
-LOINS ("np1_y","notp3_D","nn0","n0","vdd","vss",0);
-
-/* output cicuitery */
-/* "flag" command for signals used only in case of arithmetic operations */
-
-LOINS ("na2_y","naflag1","i[4]","i[3]","flag1","vdd","vss",0);
-LOINS ("a2_y","naflag","ni5","flag1","flag","vdd","vss",0);
-
-/* generation of prop and gen) */
-
-LOINS ("n1_y","not0_csh","pb0","npb0","vdd","vss",0); 
-LOINS ("n1_y","not1_csh","gb0","ngb0","vdd","vss",0); 
-LOINS ("n1_y","not2_csh","gb3","ngb3","vdd","vss",0);
-LOINS ("n1_y","npf","nprop","propf","vdd","vss",0);
-LOINS ("n1_y","npg","ngen","genf","vdd","vss",0);
-LOINS ("a2_y","npflag","propf","flag","p","vdd","vss",0); 
-LOINS ("a2_y","ngflag","genf","flag","g","vdd","vss",0); 
-
-LOINS ("no3_y","nor0_csh","pb3","pb2","pb1","no30_csh","vdd","vss",0);
-LOINS ("no3_y","nor1_csh","gb1","pb2","pb3","no31_csh","vdd","vss",0);
-LOINS ("no3_y","nor2_csh","no2_csh","no31_csh","ngb3","no32_csh","vdd","vss",0);
-
-LOINS ("na2_y","nand0_csh","npb0","no30_csh","nprop","vdd","vss",0);
-LOINS ("na2_y","nand1_csh","ngb0","no30_csh","na_csh","vdd","vss",0);
-
-LOINS ("no2_y","nor_csh","gb2","pb3","no2_csh","vdd","vss",0);
-LOINS ("a2_y","and_csh","na_csh","no32_csh","ngen","vdd","vss",0);
-
-/* others flags */
-
-LOINS ("na2_y","nand0_csb","fb0","fb1","na0_csb","vdd","vss",0);
-LOINS ("na2_y","nand1_csb","fb2","signea","na1_csb","vdd","vss",0);
-LOINS ("no2_y","nor_csb","na0_csb","na1_csb","zero","vdd","vss",0);
-LOINS ("xr2_y","xor_csb","cout2","couta","ovr","vdd","vss",0);
-
-/* inversion of signals in conformity with the data sheet */
-
-LOINS ("n1_y","not0_csb","fb0","alu_out[0]","vdd","vss",0);
-LOINS ("n1_y","not1_csb","fb1","alu_out[1]","vdd","vss",0);
-LOINS ("n1_y","not2_csb","fb2","alu_out[2]","vdd","vss",0);
-LOINS ("n1_y","not3_csb","signea","alu_out[3]","vdd","vss",0);
-
-LOINS ("n1_y","not4_csb","signea","signe","vdd","vss",0);
-LOINS ("n1_y","not0_p","p","np","vdd","vss",0);
-LOINS ("n1_y","not0_g","g","ng","vdd","vss",0);
-LOINS ("a2_y","coutflag","couta","flag","cout","vdd","vss",0);
-
-SAVE_LOFIG();
-
-DEF_LOFIG ("accu");
-/* declaration of the cell's external connectors */
-LOCON ("ALU_OUT[3:0]",'I',"alu_out[3:0]");
-LOCON ("Q0",'I',"q0");
-LOCON ("Q3",'I',"q3");
-LOCON ("FONC",'I',"fonc");
-LOCON ("TEST",'I',"test");
-LOCON ("FONC_MODE",'X',"fonc_mode");
-LOCON ("SCIN",'I',"scin");
-LOCON ("SCOUT",'O',"scout");
-LOCON ("F0",'O',"f0");
-LOCON ("F3",'O',"f3");
-LOCON ("DECALD",'O',"decald");
-LOCON ("DECALG",'O',"decalg");
-LOCON ("Q[3:0]",'X',"q[3:0]");
-LOCON ("I[8:6]",'I',"i[8:6]");
-LOCON ("CK",'I',"ck");
-LOCON ("VDD",'I',"vdd");
-LOCON ("VSS",'I',"vss");
-
-/* generation of the multiplexing and shifting commands */
-
-LOINS ("n1_y","n11sa","i[8]","decaln","vdd","vss",0);
-LOINS ("n1_y","n12sa","i[7]","ni7","vdd","vss",0);
-LOINS ("n1_y","n13sa","i[6]","ni6","vdd","vss",0);
-LOINS ("n1_y","n14sa","fonc","n14s","vdd","vss",0);
-LOINS ("n1_y","n15sa","test","n15s","vdd","vss",0);
-LOINS ("b1_y","BDECALD","decalda","decald","vdd","vss",0);
-LOINS ("b1_y","BDECALG","decalga","decalg","vdd","vss",0);
-
-LOINS ("a2_y","a21sa","i[8]","ni7","decalda","vdd","vss",0);
-LOINS ("a2_y","a22sa","i[8]","i[7]","decalga","vdd","vss",0);
-LOINS ("a3_y","a31sa","decaln","ni7","ni6","selalu","vdd","vss",0);
-LOINS ("o2_y","o21sa","i[8]","ni7","o21s","vdd","vss",0);
-LOINS ("a2_y","a24sa","fonc","n15s","fonc_mode","vdd","vss",0);
-LOINS ("a2_y","a25sa","test","n14s","test_mode","vdd","vss",0);
-LOINS ("a2_y","a26sa","o21s","ni6","waccu","vdd","vss",0);
-
-/* taking in account of the above commands */
-
-LOINS ("a2_y","a27sa","alu_out[3]","selalu","a27s","vdd","vss",0);
-LOINS ("a2_y","a28sa","alu_out[2]","selalu","a28s","vdd","vss",0);
-LOINS ("a2_y","a29sa","alu_out[1]","selalu","a29s","vdd","vss",0);
-LOINS ("a2_y","a210sa","alu_out[0]","selalu","a210s","vdd","vss",0);
-
-LOINS ("a2_y","a211sa","q[3]","i[8]","a211s","vdd","vss",0);
-LOINS ("a2_y","a212sa","q[2]","i[8]","a212s","vdd","vss",0);
-LOINS ("a2_y","a213sa","q[1]","i[8]","a213s","vdd","vss",0);
-LOINS ("a2_y","a214sa","q[0]","i[8]","a214s","vdd","vss",0);
-
-LOINS ("o2_y","o22sa","a27s","a211s","insh3","vdd","vss",0);
-LOINS ("o2_y","o23sa","a28s","a212s","insh2","vdd","vss",0);
-LOINS ("o2_y","o24sa","a29s","a213s","insh1","vdd","vss",0);
-LOINS ("o2_y","o25sa","a210s","a214s","insh0","vdd","vss",0);
-
-
-LOINS ("a2_y","a215sa","decalga","insh3","f3","vdd","vss",0);
-LOINS ("a2_y","a228sa","decalda","insh0","f0","vdd","vss",0);
-
-
-/* shifter */
-
-/* bit slice 3 */
-LOINS ("a2_y","a216sa","q3","decalda","a216s","vdd","vss",0);
-LOINS ("a2_y","a217sa","insh3","decaln","a217s","vdd","vss",0);
-LOINS ("a2_y","a218sa","insh2","decalga","a218s","vdd","vss",0);
-
-/* bit slice 2 */
-LOINS ("a2_y","a219sa","insh3","decalda","a219s","vdd","vss",0);
-LOINS ("a2_y","a220sa","insh2","decaln","a220s","vdd","vss",0);
-LOINS ("a2_y","a221sa","insh1","decalga","a221s","vdd","vss",0);
-
-/* bit slice 1 */
-LOINS ("a2_y","a222sa","insh2","decalda","a222s","vdd","vss",0);
-LOINS ("a2_y","a223sa","insh1","decaln","a223s","vdd","vss",0);
-LOINS ("a2_y","a224sa","insh0","decalga","a224s","vdd","vss",0);
-
-/* bit slice 0 */
-LOINS ("a2_y","a225sa","insh1","decalda","a225s","vdd","vss",0);
-LOINS ("a2_y","a226sa","insh0","decaln","a226s","vdd","vss",0);
-LOINS ("a2_y","a227sa","q0","decalga","a227s","vdd","vss",0);
-
-
-/* register input */
-
-
-LOINS ("o3_y","o31sa","a216s","a217s","a218s","shacc3","vdd","vss",0);
-LOINS ("o3_y","o32sa","a219s","a220s","a221s","shacc2","vdd","vss",0);
-LOINS ("o3_y","o33sa","a222s","a223s","a224s","shacc1","vdd","vss",0);
-LOINS ("o3_y","o34sa","a225s","a226s","a227s","shacc0","vdd","vss",0);
-
-
-/* writing in the register */
-
-LOINS ("a2_y","a229sa","ck","w","ckin","vdd","vss",0);
-LOINS ("a2_y","a230sa","test_mode","q[3]","scout","vdd","vss",0);
-LOINS ("a2_y","a231sa","fonc_mode","waccu","a231s","vdd","vss",0);
-LOINS ("o2_y","o26sa","test_mode","a231s","w","vdd","vss",0);
-
-
-LOINS ("ms2dp2_y","m3","shacc3","q[2]","test_mode","ckin","q[3]","vdd","vss",0);
-LOINS ("ms2dp2_y","m2","shacc2","q[1]","test_mode","ckin","q[2]","vdd","vss",0);
-LOINS ("ms2dp2_y","m1","shacc1","q[0]","test_mode","ckin","q[1]","vdd","vss",0);
-LOINS ("ms2dp2_y","m0","shacc0","scin","test_mode","ckin","q[0]","vdd","vss",0);
-
-SAVE_LOFIG();
-
-DEF_LOFIG ("muxe");
-/* declaration of the cell's external connectors */
-LOCON ("RA[3:0]",'I',"ra[3:0]");
-LOCON ("RB[3:0]",'I',"rb[3:0]");
-LOCON ("Q[3:0]",'I',"q[3:0]");
-LOCON ("D[3:0]",'I',"d[3:0]");
-LOCON ("R[3:0]",'O',"r[3:0]");
-LOCON ("S[3:0]",'O',"s[3:0]");
-LOCON ("I[2:0]",'I',"i[2:0]");
-LOCON ("VDD",'I',"vdd");
-LOCON ("VSS",'I',"vss");
-
-/* generation of the multiplexing commands */
-
-LOINS ("n1_y","n11me","i[2]","ni2","vdd","vss",0);
-LOINS ("n1_y","n12me","i[1]","ni1","vdd","vss",0);
-LOINS ("n1_y","n13me","i[0]","ni0","vdd","vss",0);
-
-/* ra ->  ALU's S-input */
-
-LOINS ("a2_y","a21me","ni1","i[2]","selas","vdd","vss",0);
-
-/* rb ->  ALU's S-input */
-
-LOINS ("a2_y","a22me","ni2","i[0]","selbs","vdd","vss",0);
-LOINS ("o2_y","o21me","i[1]","ni2","o21s","vdd","vss",0);
-
-/* ra ->  ALU's R-input */
-
-LOINS ("a2_y","a23me","ni2","ni1","selar","vdd","vss",0);
-LOINS ("o2_y","o22me","i[1]","i[0]","o22s","vdd","vss",0);
-
-/* q ->  ALU's R-input */
-
-LOINS ("a2_y","a24me","o21s","ni0","selqs","vdd","vss",0);
-
-/* d ->  ALU's R-input */
-
-LOINS ("a2_y","a25me","o22s","i[2]","seldr","vdd","vss",0);
-
-/* taking in account of the above commands */
-
-/* rb(3 downto 0) -> s(3 downto 0) */
-
-LOINS ("a2_y","a26ms","rb[0]","selbs","srb0","vdd","vss",0);
-LOINS ("a2_y","a27ms","rb[1]","selbs","srb1","vdd","vss",0);
-LOINS ("a2_y","a28ms","rb[2]","selbs","srb2","vdd","vss",0);
-LOINS ("a2_y","a29ms","rb[3]","selbs","srb3","vdd","vss",0);
-
-/* ra(3 downto 0) -> s(3 downto 0) */
-
-LOINS ("a2_y","a210ms","ra[0]","selas","sra0","vdd","vss",0);
-LOINS ("a2_y","a211ms","ra[1]","selas","sra1","vdd","vss",0);
-LOINS ("a2_y","a212ms","ra[2]","selas","sra2","vdd","vss",0);
-LOINS ("a2_y","a213ms","ra[3]","selas","sra3","vdd","vss",0);
-
-/* ra(3 downto 0) -> r(3 downto 0) */
-
-LOINS ("a2_y","a214ms","ra[0]","selar","ssa0","vdd","vss",0);
-LOINS ("a2_y","a215ms","ra[1]","selar","ssa1","vdd","vss",0);
-LOINS ("a2_y","a216ms","ra[2]","selar","ssa2","vdd","vss",0);
-LOINS ("a2_y","a217ms","ra[3]","selar","ssa3","vdd","vss",0);
-
-/* q(3 downto 0) -> r(3 downto 0) */
-
-LOINS ("a2_y","a218ms","q[0]","selqs","srq0","vdd","vss",0);
-LOINS ("a2_y","a219ms","q[1]","selqs","srq1","vdd","vss",0);
-LOINS ("a2_y","a220ms","q[2]","selqs","srq2","vdd","vss",0);
-LOINS ("a2_y","a221ms","q[3]","selqs","srq3","vdd","vss",0);
-
-/* d(3 downto 0) -> r(3 downto 0) */
-
-LOINS ("a2_y","a222ms","d[0]","seldr","ssd0","vdd","vss",0);
-LOINS ("a2_y","a223ms","d[1]","seldr","ssd1","vdd","vss",0);
-LOINS ("a2_y","a224ms","d[2]","seldr","ssd2","vdd","vss",0);
-LOINS ("a2_y","a225ms","d[3]","seldr","ssd3","vdd","vss",0);
-
-/* last stage of the multiplexer : r and s ALU-inputs */
-
-LOINS ("o3_y","o31ms","srb0","sra0","srq0","s[0]","vdd","vss",0);
-LOINS ("o3_y","o32ms","srb1","sra1","srq1","s[1]","vdd","vss",0);
-LOINS ("o3_y","o33ms","srb2","sra2","srq2","s[2]","vdd","vss",0);
-LOINS ("o3_y","o34ms","srb3","sra3","srq3","s[3]","vdd","vss",0);
-
-LOINS ("o2_y","o23ms","ssa0","ssd0","r[0]","vdd","vss",0);
-LOINS ("o2_y","o24ms","ssa1","ssd1","r[1]","vdd","vss",0);
-LOINS ("o2_y","o25ms","ssa2","ssd2","r[2]","vdd","vss",0);
-LOINS ("o2_y","o26ms","ssa3","ssd3","r[3]","vdd","vss",0);
-
-SAVE_LOFIG();
-
-DEF_LOFIG ("muxout");
-
-/* declaration of the cell's external connectors */
-
-LOCON ("RA[3:0]",'I',"ra[3:0]");
-LOCON ("ALU_OUT[3:0]",'I',"alu_out[3:0]");
-LOCON ("NOE",'I',"noe");
-LOCON ("OE",'O',"oe");
-LOCON ("Y[3:0]",'O',"y[3:0]");
-LOCON ("I[8:6]",'I',"i[8:6]");
-LOCON ("VDD",'I',"vdd");
-LOCON ("VSS",'I',"vss");
-
-/* generation of the multiplexing commands */
-
-LOINS ("n1_y","n11ms","i[8]","ni8","vdd","vss",0);
-LOINS ("n1_y","n12ms","i[6]","ni6","vdd","vss",0);
-/* ra -> y */ 
-LOINS ("a3_y","a31ms","i[7]","ni6","ni8","selray","vdd","vss",0);
-/* ALU's output -> y */ 
-LOINS ("n1_y","n13ms","selray","selaluy","vdd","vss",0);
-
-/* taking in account of the above commands */
-
-/* ra(3 downto 0) -> y(3 downto 0) */ 
-
-LOINS ("a2_y","a21ms","ra[0]","selray","syra0","vdd","vss",0);
-LOINS ("a2_y","a22ms","ra[1]","selray","syra1","vdd","vss",0);
-LOINS ("a2_y","a23ms","ra[2]","selray","syra2","vdd","vss",0);
-LOINS ("a2_y","a24ms","ra[3]","selray","syra3","vdd","vss",0);
-
-/* alu_out(3 downto 0) -> y(3 downto 0) */ 
-
-LOINS ("a2_y","a25ms","alu_out[0]","selaluy","syalu0","vdd","vss",0);
-LOINS ("a2_y","a26ms","alu_out[1]","selaluy","syalu1","vdd","vss",0);
-LOINS ("a2_y","a27ms","alu_out[2]","selaluy","syalu2","vdd","vss",0);
-LOINS ("a2_y","a28ms","alu_out[3]","selaluy","syalu3","vdd","vss",0);
-
-/* last stage of the multiplexer : amd's y output */
-
-LOINS ("o2_y","o21ms","syra0","syalu0","y[0]","vdd","vss",0);
-LOINS ("o2_y","o22ms","syra1","syalu1","y[1]","vdd","vss",0);
-LOINS ("o2_y","o23ms","syra2","syalu2","y[2]","vdd","vss",0);
-LOINS ("o2_y","o24ms","syra3","syalu3","y[3]","vdd","vss",0);
-
-/* oe is the command for the 3 state output pad */
-
-LOINS ("n1_y","n1oe","noe","oe","vdd","vss",0);
-
-SAVE_LOFIG();
-DEF_LOFIG ("ram");
-/* declaration of the cell's external connectors */
-LOCON ("A[3:0]",'I',"a[3:0]");
-LOCON ("B[3:0]",'I',"b[3:0]");
-LOCON ("ALU_OUT[3:0]",'I',"alu_out[3:0]");
-LOCON ("FONC_MODE",'I',"fonc_mode");
-LOCON ("R0",'I',"r0");
-LOCON ("R3",'I',"r3");
-LOCON ("S0",'O',"s0");
-LOCON ("S3",'O',"s3");
-LOCON ("DECALDR",'O',"decaldr");
-LOCON ("DECALGR",'O',"decalgr");
-LOCON ("RA[3:0]",'O',"ra[3:0]");
-LOCON ("RB[3:0]",'O',"rb[3:0]");
-LOCON ("I[8:7]",'I',"i[8:7]");
-LOCON ("CK",'I',"ck");
-LOCON ("VDD",'I',"vdd");
-LOCON ("VSS",'I',"vss");
-
-/* generation of the shifting and writing commands */
-
-LOINS ("n1_y","n11ra","i[8]","decalnr","vdd","vss",0);
-LOINS ("n1_y","n12ra","i[7]","ni7","vdd","vss",0);
-
-LOINS ("a2_y","a21r","i[8]","ni7","decaldra","vdd","vss",0);
-LOINS ("b1_y","bufdecaldr","decaldra","decaldr","vdd","vss",0);
-LOINS ("b1_y","bufdecalgr","decalgra","decalgr","vdd","vss",0);
-LOINS ("a2_y","a22r","i[8]","i[7]","decalgra","vdd","vss",0);
-LOINS ("o2_y","o21r","i[8]","i[7]","o21s","vdd","vss",0);
-/* writing operations only have to occure when fonc_mode is chosen: */
-LOINS ("a2_y","a215r","fonc_mode","o21s","wram","vdd","vss",0);
-LOINS ("a2p_y","a216r","ck","wram","enable","vdd","vss",0);
-
-
-
-LOINS ("a2_y","a232r","decalgra","alu_out[3]","s3","vdd","vss",0);
-LOINS ("a2_y","a233r","decaldra","alu_out[0]","s0","vdd","vss",0);
-
-
-/* shifter */
-
-/* bit slice 3 */
-LOINS ("a2_y","a23r","alu_out[2]","decalgra","a23sh","vdd","vss",0);
-LOINS ("a2_y","a24r","alu_out[3]","decalnr","a24sh","vdd","vss",0);
-LOINS ("a2_y","a25r","r3","decaldra","a25sh","vdd","vss",0);
-
-/* bit slice 2 */
-LOINS ("a2_y","a26r","alu_out[1]","decalgra","a26sh","vdd","vss",0);
-LOINS ("a2_y","a27r","alu_out[2]","decalnr","a27sh","vdd","vss",0);
-LOINS ("a2_y","a28r","alu_out[3]","decaldra","a28sh","vdd","vss",0);
-
-/* bit slice 1 */
-LOINS ("a2_y","a29r","alu_out[0]","decalgra","a29sh","vdd","vss",0);
-LOINS ("a2_y","a210r","alu_out[1]","decalnr","a210sh","vdd","vss",0);
-LOINS ("a2_y","a211r","alu_out[2]","decaldra","a211sh","vdd","vss",0);
-
-/* bit slice 0 */
-LOINS ("a2_y","a212r","r0","decalgra","a212sh","vdd","vss",0);
-LOINS ("a2_y","a213r","alu_out[0]","decalnr","a213sh","vdd","vss",0);
-LOINS ("a2_y","a214r","alu_out[1]","decaldra","a214sh","vdd","vss",0);
-
-/* RAM input */
-LOINS ("o3_y","o31r","a23sh","a24sh","a25sh","shram3","vdd","vss",0);
-LOINS ("o3_y","o32r","a26sh","a27sh","a28sh","shram2","vdd","vss",0);
-LOINS ("o3_y","o33r","a29sh","a210sh","a211sh","shram1","vdd","vss",0);
-LOINS ("o3_y","o34r","a212sh","a213sh","a214sh","shram0","vdd","vss",0);
-
-/* a and b address-decoders */
-
-
-/* a address */
-LOINS ("np1_y","n15r","a[0]","na0","vdd","vss",0);
-LOINS ("np1_y","n16r","a[1]","na1","vdd","vss",0);
-LOINS ("np1_y","n17r","a[2]","na2","vdd","vss",0);
-LOINS ("np1_y","n18r","a[3]","na3","vdd","vss",0);
-
-LOINS ("a4_y","a41r","na3","na2","na1","na0","a1","vdd","vss",0);
-LOINS ("a4_y","a42r","na3","na2","na1","a[0]","a2","vdd","vss",0);
-LOINS ("a4_y","a43r","na3","na2","a[1]","na0","a3","vdd","vss",0);
-LOINS ("a4_y","a44r","na3","na2","a[1]","a[0]","a4","vdd","vss",0);
-LOINS ("a4_y","a45r","na3","a[2]","na1","na0","a5","vdd","vss",0);
-LOINS ("a4_y","a46r","na3","a[2]","na1","a[0]","a6","vdd","vss",0);
-LOINS ("a4_y","a47r","na3","a[2]","a[1]","na0","a7","vdd","vss",0);
-LOINS ("a4_y","a48r","na3","a[2]","a[1]","a[0]","a8","vdd","vss",0);
-LOINS ("a4_y","a49r","a[3]","na2","na1","na0","a9","vdd","vss",0);
-LOINS ("a4_y","a410r","a[3]","na2","na1","a[0]","a10","vdd","vss",0);
-LOINS ("a4_y","a411r","a[3]","na2","a[1]","na0","a11","vdd","vss",0);
-LOINS ("a4_y","a412r","a[3]","na2","a[1]","a[0]","a12","vdd","vss",0);
-LOINS ("a4_y","a413r","a[3]","a[2]","na1","na0","a13","vdd","vss",0);
-LOINS ("a4_y","a414r","a[3]","a[2]","na1","a[0]","a14","vdd","vss",0);
-LOINS ("a4_y","a415r","a[3]","a[2]","a[1]","na0","a15","vdd","vss",0);
-LOINS ("a4_y","a416r","a[3]","a[2]","a[1]","a[0]","a16","vdd","vss",0);
-
-/* b address */
-LOINS ("n1_y","n111r","b[0]","nb0","vdd","vss",0);
-LOINS ("n1_y","n112r","b[1]","nb1","vdd","vss",0);
-LOINS ("n1_y","n113r","b[2]","nb2","vdd","vss",0);
-LOINS ("n1_y","n114r","b[3]","nb3","vdd","vss",0);
-
-LOINS ("a4_y","b41r","nb3","nb2","nb1","nb0","b1","vdd","vss",0);
-LOINS ("a4_y","b42r","nb3","nb2","nb1","b[0]","b2","vdd","vss",0);
-LOINS ("a4_y","b43r","nb3","nb2","b[1]","nb0","b3","vdd","vss",0);
-LOINS ("a4_y","b44r","nb3","nb2","b[1]","b[0]","b4","vdd","vss",0);
-LOINS ("a4_y","b45r","nb3","b[2]","nb1","nb0","b5","vdd","vss",0);
-LOINS ("a4_y","b46r","nb3","b[2]","nb1","b[0]","b6","vdd","vss",0);
-LOINS ("a4_y","b47r","nb3","b[2]","b[1]","nb0","b7","vdd","vss",0);
-LOINS ("a4_y","b48r","nb3","b[2]","b[1]","b[0]","b8","vdd","vss",0);
-LOINS ("a4_y","b49r","b[3]","nb2","nb1","nb0","b9","vdd","vss",0);
-LOINS ("a4_y","b410r","b[3]","nb2","nb1","b[0]","b10","vdd","vss",0);
-LOINS ("a4_y","b411r","b[3]","nb2","b[1]","nb0","b11","vdd","vss",0);
-LOINS ("a4_y","b412r","b[3]","nb2","b[1]","b[0]","b12","vdd","vss",0);
-LOINS ("a4_y","b413r","b[3]","b[2]","nb1","nb0","b13","vdd","vss",0);
-LOINS ("a4_y","b414r","b[3]","b[2]","nb1","b[0]","b14","vdd","vss",0);
-LOINS ("a4_y","b415r","b[3]","b[2]","b[1]","nb0","b15","vdd","vss",0);
-LOINS ("a4_y","b416r","b[3]","b[2]","b[1]","b[0]","b16","vdd","vss",0);
-
-/* selection of the b-addressed word for the writing */
-
-LOINS ("a2_y","c16","enable","b16","ck16","vdd","vss",0);
-LOINS ("a2_y","c15","enable","b15","ck15","vdd","vss",0);
-LOINS ("a2_y","c14","enable","b14","ck14","vdd","vss",0);
-LOINS ("a2_y","c13","enable","b13","ck13","vdd","vss",0);
-LOINS ("a2_y","c12","enable","b12","ck12","vdd","vss",0);
-LOINS ("a2_y","c11","enable","b11","ck11","vdd","vss",0);
-LOINS ("a2_y","c10","enable","b10","ck10","vdd","vss",0);
-LOINS ("a2_y","c9","enable","b9","ck9","vdd","vss",0);
-LOINS ("a2_y","c8","enable","b8","ck8","vdd","vss",0);
-LOINS ("a2_y","c7","enable","b7","ck7","vdd","vss",0);
-LOINS ("a2_y","c6","enable","b6","ck6","vdd","vss",0);
-LOINS ("a2_y","c5","enable","b5","ck5","vdd","vss",0);
-LOINS ("a2_y","c4","enable","b4","ck4","vdd","vss",0);
-LOINS ("a2_y","c3","enable","b3","ck3","vdd","vss",0);
-LOINS ("a2_y","c2","enable","b2","ck2","vdd","vss",0);
-LOINS ("a2_y","c1","enable","b1","ck1","vdd","vss",0);
-
-/* building of the "memory-space" */
-
-/* bit slice 3 */
-LOINS ("msdp2_y","m_16_3","shram3","ck16","s316","vdd","vss",0);
-LOINS ("msdp2_y","m_15_3","shram3","ck15","s315","vdd","vss",0);
-LOINS ("msdp2_y","m_14_3","shram3","ck14","s314","vdd","vss",0);
-LOINS ("msdp2_y","m_13_3","shram3","ck13","s313","vdd","vss",0);
-LOINS ("msdp2_y","m_12_3","shram3","ck12","s312","vdd","vss",0);
-LOINS ("msdp2_y","m_11_3","shram3","ck11","s311","vdd","vss",0);
-LOINS ("msdp2_y","m_10_3","shram3","ck10","s310","vdd","vss",0);
-LOINS ("msdp2_y","m_9_3","shram3","ck9","s39","vdd","vss",0);
-LOINS ("msdp2_y","m_8_3","shram3","ck8","s38","vdd","vss",0);
-LOINS ("msdp2_y","m_7_3","shram3","ck7","s37","vdd","vss",0);
-LOINS ("msdp2_y","m_6_3","shram3","ck6","s36","vdd","vss",0);
-LOINS ("msdp2_y","m_5_3","shram3","ck5","s35","vdd","vss",0);
-LOINS ("msdp2_y","m_4_3","shram3","ck4","s34","vdd","vss",0);
-LOINS ("msdp2_y","m_3_3","shram3","ck3","s33","vdd","vss",0);
-LOINS ("msdp2_y","m_2_3","shram3","ck2","s32","vdd","vss",0);
-LOINS ("msdp2_y","m_1_3","shram3","ck1","s31","vdd","vss",0);
-
-/* bit slice 2 */
-LOINS ("msdp2_y","m_16_2","shram2","ck16","s216","vdd","vss",0);
-LOINS ("msdp2_y","m_15_2","shram2","ck15","s215","vdd","vss",0);
-LOINS ("msdp2_y","m_14_2","shram2","ck14","s214","vdd","vss",0);
-LOINS ("msdp2_y","m_13_2","shram2","ck13","s213","vdd","vss",0);
-LOINS ("msdp2_y","m_12_2","shram2","ck12","s212","vdd","vss",0);
-LOINS ("msdp2_y","m_11_2","shram2","ck11","s211","vdd","vss",0);
-LOINS ("msdp2_y","m_10_2","shram2","ck10","s210","vdd","vss",0);
-LOINS ("msdp2_y","m_9_2","shram2","ck9","s29","vdd","vss",0);
-LOINS ("msdp2_y","m_8_2","shram2","ck8","s28","vdd","vss",0);
-LOINS ("msdp2_y","m_7_2","shram2","ck7","s27","vdd","vss",0);
-LOINS ("msdp2_y","m_6_2","shram2","ck6","s26","vdd","vss",0);
-LOINS ("msdp2_y","m_5_2","shram2","ck5","s25","vdd","vss",0);
-LOINS ("msdp2_y","m_4_2","shram2","ck4","s24","vdd","vss",0);
-LOINS ("msdp2_y","m_3_2","shram2","ck3","s23","vdd","vss",0);
-LOINS ("msdp2_y","m_2_2","shram2","ck2","s22","vdd","vss",0);
-LOINS ("msdp2_y","m_1_2","shram2","ck1","s21","vdd","vss",0);
-
-/* bit slice 1 */
-LOINS ("msdp2_y","m_16_1","shram1","ck16","s116","vdd","vss",0);
-LOINS ("msdp2_y","m_15_1","shram1","ck15","s115","vdd","vss",0);
-LOINS ("msdp2_y","m_14_1","shram1","ck14","s114","vdd","vss",0);
-LOINS ("msdp2_y","m_13_1","shram1","ck13","s113","vdd","vss",0);
-LOINS ("msdp2_y","m_12_1","shram1","ck12","s112","vdd","vss",0);
-LOINS ("msdp2_y","m_11_1","shram1","ck11","s111","vdd","vss",0);
-LOINS ("msdp2_y","m_10_1","shram1","ck10","s110","vdd","vss",0);
-LOINS ("msdp2_y","m_9_1","shram1","ck9","s19","vdd","vss",0);
-LOINS ("msdp2_y","m_8_1","shram1","ck8","s18","vdd","vss",0);
-LOINS ("msdp2_y","m_7_1","shram1","ck7","s17","vdd","vss",0);
-LOINS ("msdp2_y","m_6_1","shram1","ck6","s16","vdd","vss",0);
-LOINS ("msdp2_y","m_5_1","shram1","ck5","s15","vdd","vss",0);
-LOINS ("msdp2_y","m_4_1","shram1","ck4","s14","vdd","vss",0);
-LOINS ("msdp2_y","m_3_1","shram1","ck3","s13","vdd","vss",0);
-LOINS ("msdp2_y","m_2_1","shram1","ck2","s12","vdd","vss",0);
-LOINS ("msdp2_y","m_1_1","shram1","ck1","s11","vdd","vss",0);
-
-/* bit slice 0 */
-LOINS ("msdp2_y","m_16_0","shram0","ck16","s016","vdd","vss",0);
-LOINS ("msdp2_y","m_15_0","shram0","ck15","s015","vdd","vss",0);
-LOINS ("msdp2_y","m_14_0","shram0","ck14","s014","vdd","vss",0);
-LOINS ("msdp2_y","m_13_0","shram0","ck13","s013","vdd","vss",0);
-LOINS ("msdp2_y","m_12_0","shram0","ck12","s012","vdd","vss",0);
-LOINS ("msdp2_y","m_11_0","shram0","ck11","s011","vdd","vss",0);
-LOINS ("msdp2_y","m_10_0","shram0","ck10","s010","vdd","vss",0);
-LOINS ("msdp2_y","m_9_0","shram0","ck9","s09","vdd","vss",0);
-LOINS ("msdp2_y","m_8_0","shram0","ck8","s08","vdd","vss",0);
-LOINS ("msdp2_y","m_7_0","shram0","ck7","s07","vdd","vss",0);
-LOINS ("msdp2_y","m_6_0","shram0","ck6","s06","vdd","vss",0);
-LOINS ("msdp2_y","m_5_0","shram0","ck5","s05","vdd","vss",0);
-LOINS ("msdp2_y","m_4_0","shram0","ck4","s04","vdd","vss",0);
-LOINS ("msdp2_y","m_3_0","shram0","ck3","s03","vdd","vss",0);
-LOINS ("msdp2_y","m_2_0","shram0","ck2","s02","vdd","vss",0);
-LOINS ("msdp2_y","m_1_0","shram0","ck1","s01","vdd","vss",0);
-
-/* reading of the a-addressed word */
-
-/* bit slice 3 */
-/* selection of 1 out of the 16 outputs of the D-latches */
-LOINS ("na2_y","am316","a16","s316","a316s","vdd","vss",0);
-LOINS ("na2_y","am315","a15","s315","a315s","vdd","vss",0);
-LOINS ("na2_y","am314","a14","s314","a314s","vdd","vss",0);
-LOINS ("na2_y","am313","a13","s313","a313s","vdd","vss",0);
-LOINS ("na2_y","am312","a12","s312","a312s","vdd","vss",0);
-LOINS ("na2_y","am311","a11","s311","a311s","vdd","vss",0);
-LOINS ("na2_y","am310","a10","s310","a310s","vdd","vss",0);
-LOINS ("na2_y","am39","a9","s39","a39s","vdd","vss",0);
-LOINS ("na2_y","am38","a8","s38","a38s","vdd","vss",0);
-LOINS ("na2_y","am37","a7","s37","a37s","vdd","vss",0);
-LOINS ("na2_y","am36","a6","s36","a36s","vdd","vss",0);
-LOINS ("na2_y","am35","a5","s35","a35s","vdd","vss",0);
-LOINS ("na2_y","am34","a4","s34","a34s","vdd","vss",0);
-LOINS ("na2_y","am33","a3","s33","a33s","vdd","vss",0);
-LOINS ("na2_y","am32","a2","s32","a32s","vdd","vss",0);
-LOINS ("na2_y","am31","a1","s31","a31s","vdd","vss",0);
-
-LOINS ("a4_y","oa413","a316s","a315s","a314s","a313s","oa413s","vdd","vss",0);
-LOINS ("a4_y","oa423","a312s","a311s","a310s","a39s","oa423s","vdd","vss",0);
-LOINS ("a4_y","oa433","a38s","a37s","a36s","a35s","oa433s","vdd","vss",0);
-LOINS ("a4_y","oa443","a34s","a33s","a32s","a31s","oa443s","vdd","vss",0);
-LOINS ("na4_y","oa453","oa413s","oa423s","oa433s","oa443s","ra[3]","vdd","vss",0);
-
-/* bit slice 2 */
-/* selection of 1 out of the 16 outputs of the D-latches */
-LOINS ("na2_y","am216","a16","s216","a216s","vdd","vss",0);
-LOINS ("na2_y","am215","a15","s215","a215s","vdd","vss",0);
-LOINS ("na2_y","am214","a14","s214","a214s","vdd","vss",0);
-LOINS ("na2_y","am213","a13","s213","a213s","vdd","vss",0);
-LOINS ("na2_y","am212","a12","s212","a212s","vdd","vss",0);
-LOINS ("na2_y","am211","a11","s211","a211s","vdd","vss",0);
-LOINS ("na2_y","am210","a10","s210","a210s","vdd","vss",0);
-LOINS ("na2_y","am29","a9","s29","a29s","vdd","vss",0);
-LOINS ("na2_y","am28","a8","s28","a28s","vdd","vss",0);
-LOINS ("na2_y","am27","a7","s27","a27s","vdd","vss",0);
-LOINS ("na2_y","am26","a6","s26","a26s","vdd","vss",0);
-LOINS ("na2_y","am25","a5","s25","a25s","vdd","vss",0);
-LOINS ("na2_y","am24","a4","s24","a24s","vdd","vss",0);
-LOINS ("na2_y","am23","a3","s23","a23s","vdd","vss",0);
-LOINS ("na2_y","am22","a2","s22","a22s","vdd","vss",0);
-LOINS ("na2_y","am21","a1","s21","a21s","vdd","vss",0);
-
-LOINS ("a4_y","oa412","a216s","a215s","a214s","a213s","oa412s","vdd","vss",0);
-LOINS ("a4_y","oa422","a212s","a211s","a210s","a29s","oa422s","vdd","vss",0);
-LOINS ("a4_y","oa432","a28s","a27s","a26s","a25s","oa432s","vdd","vss",0);
-LOINS ("a4_y","oa442","a24s","a23s","a22s","a21s","oa442s","vdd","vss",0);
-LOINS ("na4_y","oa452","oa412s","oa422s","oa432s","oa442s","ra[2]","vdd","vss",0);
-
-/* bit slice 1 */
-/* selection of 1 out of the 16 outputs of the D-latches */
-LOINS ("na2_y","am116","a16","s116","a116s","vdd","vss",0);
-LOINS ("na2_y","am115","a15","s115","a115s","vdd","vss",0);
-LOINS ("na2_y","am114","a14","s114","a114s","vdd","vss",0);
-LOINS ("na2_y","am113","a13","s113","a113s","vdd","vss",0);
-LOINS ("na2_y","am112","a12","s112","a112s","vdd","vss",0);
-LOINS ("na2_y","am111","a11","s111","a111s","vdd","vss",0);
-LOINS ("na2_y","am110","a10","s110","a110s","vdd","vss",0);
-LOINS ("na2_y","am19","a9","s19","a19s","vdd","vss",0);
-LOINS ("na2_y","am18","a8","s18","a18s","vdd","vss",0);
-LOINS ("na2_y","am17","a7","s17","a17s","vdd","vss",0);
-LOINS ("na2_y","am16","a6","s16","a16s","vdd","vss",0);
-LOINS ("na2_y","am15","a5","s15","a15s","vdd","vss",0);
-LOINS ("na2_y","am14","a4","s14","a14s","vdd","vss",0);
-LOINS ("na2_y","am13","a3","s13","a13s","vdd","vss",0);
-LOINS ("na2_y","am12","a2","s12","a12s","vdd","vss",0);
-LOINS ("na2_y","am11","a1","s11","a11s","vdd","vss",0);
-
-LOINS ("a4_y","oa411","a116s","a115s","a114s","a113s","oa411s","vdd","vss",0);
-LOINS ("a4_y","oa421","a112s","a111s","a110s","a19s","oa421s","vdd","vss",0);
-LOINS ("a4_y","oa431","a18s","a17s","a16s","a15s","oa431s","vdd","vss",0);
-LOINS ("a4_y","oa441","a14s","a13s","a12s","a11s","oa441s","vdd","vss",0);
-LOINS ("na4_y","oa451","oa411s","oa421s","oa431s","oa441s","ra[1]","vdd","vss",0);
-
-/* bit slice 0 */
-/* selection of 1 out of the 16 outputs of the D-latches */
-LOINS ("na2_y","am016","a16","s016","a016s","vdd","vss",0);
-LOINS ("na2_y","am015","a15","s015","a015s","vdd","vss",0);
-LOINS ("na2_y","am014","a14","s014","a014s","vdd","vss",0);
-LOINS ("na2_y","am013","a13","s013","a013s","vdd","vss",0);
-LOINS ("na2_y","am012","a12","s012","a012s","vdd","vss",0);
-LOINS ("na2_y","am011","a11","s011","a011s","vdd","vss",0);
-LOINS ("na2_y","am010","a10","s010","a010s","vdd","vss",0);
-LOINS ("na2_y","am09","a9","s09","a09s","vdd","vss",0);
-LOINS ("na2_y","am08","a8","s08","a08s","vdd","vss",0);
-LOINS ("na2_y","am07","a7","s07","a07s","vdd","vss",0);
-LOINS ("na2_y","am06","a6","s06","a06s","vdd","vss",0);
-LOINS ("na2_y","am05","a5","s05","a05s","vdd","vss",0);
-LOINS ("na2_y","am04","a4","s04","a04s","vdd","vss",0);
-LOINS ("na2_y","am03","a3","s03","a03s","vdd","vss",0);
-LOINS ("na2_y","am02","a2","s02","a02s","vdd","vss",0);
-LOINS ("na2_y","am01","a1","s01","a01s","vdd","vss",0);
-
-LOINS ("a4_y","oa410","a016s","a015s","a014s","a013s","oa410s","vdd","vss",0);
-LOINS ("a4_y","oa420","a012s","a011s","a010s","a09s","oa420s","vdd","vss",0);
-LOINS ("a4_y","oa430","a08s","a07s","a06s","a05s","oa430s","vdd","vss",0);
-LOINS ("a4_y","oa440","a04s","a03s","a02s","a01s","oa440s","vdd","vss",0);
-LOINS ("na4_y","oa450","oa410s","oa420s","oa430s","oa440s","ra[0]","vdd","vss",0);
-
-/* reading of the b-addressed word */
-
-/* bit slice 3 */
-/* selection of 1 out of the 16 outputs of the D-latches */
-LOINS ("na2_y","bm316","b16","s316","b316s","vdd","vss",0);
-LOINS ("na2_y","bm315","b15","s315","b315s","vdd","vss",0);
-LOINS ("na2_y","bm314","b14","s314","b314s","vdd","vss",0);
-LOINS ("na2_y","bm313","b13","s313","b313s","vdd","vss",0);
-LOINS ("na2_y","bm312","b12","s312","b312s","vdd","vss",0);
-LOINS ("na2_y","bm311","b11","s311","b311s","vdd","vss",0);
-LOINS ("na2_y","bm310","b10","s310","b310s","vdd","vss",0);
-LOINS ("na2_y","bm39","b9","s39","b39s","vdd","vss",0);
-LOINS ("na2_y","bm38","b8","s38","b38s","vdd","vss",0);
-LOINS ("na2_y","bm37","b7","s37","b37s","vdd","vss",0);
-LOINS ("na2_y","bm36","b6","s36","b36s","vdd","vss",0);
-LOINS ("na2_y","bm35","b5","s35","b35s","vdd","vss",0);
-LOINS ("na2_y","bm34","b4","s34","b34s","vdd","vss",0);
-LOINS ("na2_y","bm33","b3","s33","b33s","vdd","vss",0);
-LOINS ("na2_y","bm32","b2","s32","b32s","vdd","vss",0);
-LOINS ("na2_y","bm31","b1","s31","b31s","vdd","vss",0);
-
-LOINS ("a4_y","ob413","b316s","b315s","b314s","b313s","ob413s","vdd","vss",0);
-LOINS ("a4_y","ob423","b312s","b311s","b310s","b39s","ob423s","vdd","vss",0);
-LOINS ("a4_y","ob433","b38s","b37s","b36s","b35s","ob433s","vdd","vss",0);
-LOINS ("a4_y","ob443","b34s","b33s","b32s","b31s","ob443s","vdd","vss",0);
-LOINS ("na4_y","ob453","ob413s","ob423s","ob433s","ob443s","rb[3]","vdd","vss",0);
-
-/* bit slice 2 */
-/* selection of 1 out of the 16 outputs of the D-latches */
-LOINS ("na2_y","bm216","b16","s216","b216s","vdd","vss",0);
-LOINS ("na2_y","bm215","b15","s215","b215s","vdd","vss",0);
-LOINS ("na2_y","bm214","b14","s214","b214s","vdd","vss",0);
-LOINS ("na2_y","bm213","b13","s213","b213s","vdd","vss",0);
-LOINS ("na2_y","bm212","b12","s212","b212s","vdd","vss",0);
-LOINS ("na2_y","bm211","b11","s211","b211s","vdd","vss",0);
-LOINS ("na2_y","bm210","b10","s210","b210s","vdd","vss",0);
-LOINS ("na2_y","bm29","b9","s29","b29s","vdd","vss",0);
-LOINS ("na2_y","bm28","b8","s28","b28s","vdd","vss",0);
-LOINS ("na2_y","bm27","b7","s27","b27s","vdd","vss",0);
-LOINS ("na2_y","bm26","b6","s26","b26s","vdd","vss",0);
-LOINS ("na2_y","bm25","b5","s25","b25s","vdd","vss",0);
-LOINS ("na2_y","bm24","b4","s24","b24s","vdd","vss",0);
-LOINS ("na2_y","bm23","b3","s23","b23s","vdd","vss",0);
-LOINS ("na2_y","bm22","b2","s22","b22s","vdd","vss",0);
-LOINS ("na2_y","bm21","b1","s21","b21s","vdd","vss",0);
-
-LOINS ("a4_y","ob412","b216s","b215s","b214s","b213s","ob412s","vdd","vss",0);
-LOINS ("a4_y","ob422","b212s","b211s","b210s","b29s","ob422s","vdd","vss",0);
-LOINS ("a4_y","ob432","b28s","b27s","b26s","b25s","ob432s","vdd","vss",0);
-LOINS ("a4_y","ob442","b24s","b23s","b22s","b21s","ob442s","vdd","vss",0);
-LOINS ("na4_y","ob452","ob412s","ob422s","ob432s","ob442s","rb[2]","vdd","vss",0);
-
-/* bit slice 1 */
-/* selection of 1 out of the 16 outputs of the D-latches */
-LOINS ("na2_y","bm116","b16","s116","b116s","vdd","vss",0);
-LOINS ("na2_y","bm115","b15","s115","b115s","vdd","vss",0);
-LOINS ("na2_y","bm114","b14","s114","b114s","vdd","vss",0);
-LOINS ("na2_y","bm113","b13","s113","b113s","vdd","vss",0);
-LOINS ("na2_y","bm112","b12","s112","b112s","vdd","vss",0);
-LOINS ("na2_y","bm111","b11","s111","b111s","vdd","vss",0);
-LOINS ("na2_y","bm110","b10","s110","b110s","vdd","vss",0);
-LOINS ("na2_y","bm19","b9","s19","b19s","vdd","vss",0);
-LOINS ("na2_y","bm18","b8","s18","b18s","vdd","vss",0);
-LOINS ("na2_y","bm17","b7","s17","b17s","vdd","vss",0);
-LOINS ("na2_y","bm16","b6","s16","b16s","vdd","vss",0);
-LOINS ("na2_y","bm15","b5","s15","b15s","vdd","vss",0);
-LOINS ("na2_y","bm14","b4","s14","b14s","vdd","vss",0);
-LOINS ("na2_y","bm13","b3","s13","b13s","vdd","vss",0);
-LOINS ("na2_y","bm12","b2","s12","b12s","vdd","vss",0);
-LOINS ("na2_y","bm11","b1","s11","b11s","vdd","vss",0);
-
-LOINS ("a4_y","ob411","b116s","b115s","b114s","b113s","ob411s","vdd","vss",0);
-LOINS ("a4_y","ob421","b112s","b111s","b110s","b19s","ob421s","vdd","vss",0);
-LOINS ("a4_y","ob431","b18s","b17s","b16s","b15s","ob431s","vdd","vss",0);
-LOINS ("a4_y","ob441","b14s","b13s","b12s","b11s","ob441s","vdd","vss",0);
-LOINS ("na4_y","ob451","ob411s","ob421s","ob431s","ob441s","rb[1]","vdd","vss",0);
-
-/* bit slice 0 */
-/* selection of 1 out of the 16 outputs of the D-latches */
-LOINS ("na2_y","bm016","b16","s016","b016s","vdd","vss",0);
-LOINS ("na2_y","bm015","b15","s015","b015s","vdd","vss",0);
-LOINS ("na2_y","bm014","b14","s014","b014s","vdd","vss",0);
-LOINS ("na2_y","bm013","b13","s013","b013s","vdd","vss",0);
-LOINS ("na2_y","bm012","b12","s012","b012s","vdd","vss",0);
-LOINS ("na2_y","bm011","b11","s011","b011s","vdd","vss",0);
-LOINS ("na2_y","bm010","b10","s010","b010s","vdd","vss",0);
-LOINS ("na2_y","bm09","b9","s09","b09s","vdd","vss",0);
-LOINS ("na2_y","bm08","b8","s08","b08s","vdd","vss",0);
-LOINS ("na2_y","bm07","b7","s07","b07s","vdd","vss",0);
-LOINS ("na2_y","bm06","b6","s06","b06s","vdd","vss",0);
-LOINS ("na2_y","bm05","b5","s05","b05s","vdd","vss",0);
-LOINS ("na2_y","bm04","b4","s04","b04s","vdd","vss",0);
-LOINS ("na2_y","bm03","b3","s03","b03s","vdd","vss",0);
-LOINS ("na2_y","bm02","b2","s02","b02s","vdd","vss",0);
-LOINS ("na2_y","bm01","b1","s01","b01s","vdd","vss",0);
-
-LOINS ("a4_y","ob410","b016s","b015s","b014s","b013s","ob410s","vdd","vss",0);
-LOINS ("a4_y","ob420","b012s","b011s","b010s","b09s","ob420s","vdd","vss",0);
-LOINS ("a4_y","ob430","b08s","b07s","b06s","b05s","ob430s","vdd","vss",0);
-LOINS ("a4_y","ob440","b04s","b03s","b02s","b01s","ob440s","vdd","vss",0);
-LOINS ("na4_y","ob450","ob410s","ob420s","ob430s","ob440s","rb[0]","vdd","vss",0);
-
-SAVE_LOFIG();
-
-DEF_LOFIG ("heart");
-/* declaration of the cell's external connectors */
-LOCON ("A[3:0]",'I',"a[3:0]");
-LOCON ("B[3:0]",'I',"b[3:0]");
-LOCON ("D[3:0]",'I',"d[3:0]");
-LOCON ("CIN",'X',"cin");
-LOCON ("COUT",'X',"cout");
-LOCON ("NP",'O',"np");
-LOCON ("NG",'O',"ng");
-LOCON ("SIGNE",'X',"signe");
-LOCON ("ZERO",'O',"zero");
-LOCON ("OVR",'O',"ovr");
-LOCON ("I[8:0]",'I',"i[8:0]");
-LOCON ("Q0",'I',"q0");
-LOCON ("Q3",'I',"q3");
-LOCON ("F0",'O',"f0");
-LOCON ("F3",'O',"f3");
-LOCON ("FONC",'I',"fonc");
-LOCON ("TEST",'I',"test");
-LOCON ("SCIN",'I',"scin");
-LOCON ("SCOUT",'O',"scout");
-LOCON ("DECALD",'O',"decald");
-LOCON ("DECALG",'O',"decalg");
-LOCON ("DECALDR",'O',"decaldr");
-LOCON ("DECALGR",'O',"decalgr");
-LOCON ("R0",'I',"r0");
-LOCON ("R3",'I',"r3");
-LOCON ("S0",'O',"s0");
-LOCON ("S3",'O',"s3");
-LOCON ("CK",'I',"ck");
-LOCON ("Y[3:0]",'O',"y[3:0]");
-LOCON ("NOE",'I',"noe");
-LOCON ("OE",'O',"oe");
-LOCON ("VDD",'I',"vdd");
-LOCON ("VSS",'I',"vss");
-
-/* calling of all previously defined blocks */
-
-LOINS ("muxe","block1","ra[3:0]","rb[3:0]","q[3:0]","d[3:0]","r[3:0]","s[3:0]","i[2:0]","vdd","vss",0);
-
-LOINS ("muxout","block2","ra[3:0]","alu_out[3:0]","noe","oe","y[3:0]","i[8:6]","vdd","vss",0);
-
-LOINS ("alu","block3","r[3:0]","s[3:0]","alu_out[3:0]","cin","cout","np","ng","signe","zero","ovr","i[5:3]","vdd","vss",0);
-
-LOINS ("accu","block4","alu_out[3:0]","q0","q3","fonc","test","fonc_mode","scin","scout","f0","f3","decald","decalg","q[3:0]","i[8:6]","ck","vdd","vss",0);
-LOINS ("ram","block5","a[3:0]","b[3:0]","alu_out[3:0]","fonc_mode","r0","r3","s0","s3","decaldr","decalgr","ra[3:0]","rb[3:0]","i[8:7]","ck","vdd","vss",0);
-
-SAVE_LOFIG();
-
-DEF_LOFIG ("chip");
-
-LOCON ("A[3:0]",'I',"a[3:0]");
-LOCON ("B[3:0]",'I',"b[3:0]");
-LOCON ("D[3:0]",'I',"d[3:0]");
-LOCON ("CIN",'X',"cin");
-LOCON ("COUT",'X',"cout");
-LOCON ("NP",'O',"np");
-LOCON ("NG",'O',"ng");
-LOCON ("SIGNE",'X',"signe");
-LOCON ("ZERO",'O',"zero");
-LOCON ("OVR",'O',"ovr");
-LOCON ("I[8:0]",'I',"i[8:0]");
-LOCON ("Q0",'X',"q0");
-LOCON ("Q3",'X',"q3");
-LOCON ("R0",'X',"r0");
-LOCON ("R3",'X',"r3");
-LOCON ("NOE",'I',"noe");
-LOCON ("FONC",'I',"fonc");
-LOCON ("TEST",'I',"test");
-LOCON ("SCIN",'I',"scin");
-LOCON ("SCOUT",'O',"scout");
-LOCON ("CKE",'I',"cke");
-LOCON ("VDDE",'I',"vdde");
-LOCON ("VSSE",'I',"vsse");
-LOCON ("VDDI",'I',"vddi");
-LOCON ("VSSI",'I',"vssi");
-LOCON ("Y[3:0]",'X',"y[3:0]");
-
-/* ring of pads alimentation */
-
-LOINS ("pvdde_sp","vdde_p0","ck","vdde","vddi","vsse","vssi",0); 
-LOINS ("pvsse_sp","vsse_p0","ck","vdde","vddi","vsse","vssi",0); 
-LOINS ("pvsseck_sp","vsse_ck","cko","ck","vdde","vddi","vsse","vssi",0); 
-/* heart alimentation */
-
-LOINS ("pvddi_sp","vddi_p1","ck","vdde","vddi","vsse","vssi",0); 
-LOINS ("pvssi_sp","vssi_p1","ck","vdde","vddi","vsse","vssi",0); 
-
-LOINS ("pi_sp","a3","a[3]","ai[3]","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("pi_sp","a2","a[2]","ai[2]","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("pi_sp","a1","a[1]","ai[1]","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("pi_sp","a0","a[0]","ai[0]","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("pi_sp","b3","b[3]","bi[3]","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("pi_sp","b2","b[2]","bi[2]","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("pi_sp","b1","b[1]","bi[1]","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("pi_sp","b0","b[0]","bi[0]","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("pi_sp","d3","d[3]","di[3]","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("pi_sp","d2","d[2]","di[2]","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("pi_sp","d1","d[1]","di[1]","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("pi_sp","d0","d[0]","di[0]","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("pi_sp","cin","cin","cini","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("po_sp","scout","scoutc","scout","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("po_sp","cout","coutc","cout","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("po_sp","np","npc","np","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("po_sp","ng","ngc","ng","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("po_sp","signe","signec","signe","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("po_sp","zero","zeroc","zero","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("po_sp","ovr","ovrc","ovr","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("piot_sp","q0","f0c","decaldc","q0i","q0","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("piot_sp","q3","f3c","decalgc","q3i","q3","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("piot_sp","r0","s0c","decaldrc","r0i","r0","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("piot_sp","r3","s3c","decalgrc","r3i","r3","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("pi_sp","noe","noe","noei","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("pi_sp","fonc","fonc","fonci","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("pi_sp","test","test","testi","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("pi_sp","scin","scin","scini","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("pi_sp","i8","i[8]","ii[8]","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("pi_sp","i7","i[7]","ii[7]","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("pi_sp","i6","i[6]","ii[6]","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("pi_sp","i5","i[5]","ii[5]","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("pi_sp","i4","i[4]","ii[4]","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("pi_sp","i3","i[3]","ii[3]","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("pi_sp","i2","i[2]","ii[2]","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("pi_sp","i1","i[1]","ii[1]","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("pi_sp","i0","i[0]","ii[0]","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("pck_sp","ck","cke","ck","vdde","vddi","vsse","vssi",0);
-
-LOINS ("pot_sp","y0","yc[0]","oec","y[0]","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("pot_sp","y1","yc[1]","oec","y[1]","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("pot_sp","y2","yc[2]","oec","y[2]","ck","vdde","vddi","vsse","vssi",0);
-LOINS ("pot_sp","y3","yc[3]","oec","y[3]","ck","vdde","vddi","vsse","vssi",0);
-
-LOINS ("heart","heart","ai[3:0]","bi[3:0]","di[3:0]","cini","coutc","npc","ngc","signec","zeroc","ovrc","ii[8:0]","q0i","q3i","f0c","f3c","fonci","testi","scini","scoutc","decaldc","decalgc","decaldrc","decalgrc","r0i","r3i","s0c","s3c","cko","yc[3:0]","noei","oec","vddi","vssi",0);
-
-SAVE_LOFIG();
-exit(0);
-}
diff --git a/alliance/share/tutorials/amd2901/chip.inf b/alliance/share/tutorials/amd2901/chip.inf
deleted file mode 100644
index 53e9b7f2..00000000
--- a/alliance/share/tutorials/amd2901/chip.inf
+++ /dev/null
@@ -1,27 +0,0 @@
-
-RENAME
-# -------- RAM --------
-heart.block5.m_16_*.dff_s : ram15(*) ;
-heart.block5.m_15_*.dff_s : ram14(*) ;
-heart.block5.m_14_*.dff_s : ram13(*) ;
-heart.block5.m_13_*.dff_s : ram12(*) ;
-heart.block5.m_12_*.dff_s : ram11(*) ;
-heart.block5.m_11_*.dff_s : ram10(*) ;
-heart.block5.m_10_*.dff_s : ram9(*) ;
-heart.block5.m_9_*.dff_s : ram8(*) ;
-heart.block5.m_8_*.dff_s : ram7(*) ;
-heart.block5.m_7_*.dff_s : ram6(*) ;
-heart.block5.m_6_*.dff_s : ram5(*) ;
-heart.block5.m_5_*.dff_s : ram4(*) ;
-heart.block5.m_4_*.dff_s : ram3(*) ;
-heart.block5.m_3_*.dff_s : ram2(*) ;
-heart.block5.m_2_*.dff_s : ram1(*) ;
-heart.block5.m_1_*.dff_s : ram0(*) ;
-
-# -------- ACCU --------
-heart.block4.m*.dff_s : accu(*) ;
-
-# -------- ALU --------
-heart.r_* : r_* ;
-heart.s_* : s_* ;
-END 
diff --git a/alliance/share/tutorials/amd2901/chip.rin b/alliance/share/tutorials/amd2901/chip.rin
deleted file mode 100644
index f432e1da..00000000
--- a/alliance/share/tutorials/amd2901/chip.rin
+++ /dev/null
@@ -1,9 +0,0 @@
-# file used by the RING tool 
-# placement of the pads on the different sides of the chip 
-
-north(a3 a2 a1 a0 b3 b2 b1 b0 vdde_p0 d3 d2 d1 d0)
-west(cin np ng r0 r3 vddi_p1  y0 y1 y2 y3 vsse_p0 noe )
-south(  scout i8 i7 i6 vsse_ck i5 i4 i3 i2 i1 i0 ck)
-# east(vsse_ck  signe ovr cout zero fonc vssi_p1 test  scin q0 q3)
-east(signe ovr cout zero fonc  vssi_p1 test  scin q0 q3)
-
diff --git a/alliance/share/tutorials/amd2901/heart.scr b/alliance/share/tutorials/amd2901/heart.scr
deleted file mode 100644
index 8bedff42..00000000
--- a/alliance/share/tutorials/amd2901/heart.scr
+++ /dev/null
@@ -1,51 +0,0 @@
-PLACE_PHCON_NORTH a[3]  1;
-PLACE_PHCON_NORTH a[2]  2;
-PLACE_PHCON_NORTH a[1]  3;
-PLACE_PHCON_NORTH a[0]  4;
-PLACE_PHCON_NORTH b[3]  5;
-PLACE_PHCON_NORTH b[2]  6;
-PLACE_PHCON_NORTH b[1]  7;
-PLACE_PHCON_NORTH b[0]  8;
-PLACE_PHCON_NORTH d[3]  9;
-PLACE_PHCON_NORTH d[2] 10;
-PLACE_PHCON_NORTH d[1] 11;
-PLACE_PHCON_NORTH d[0] 12;
-PLACE_PHCON_WEST cin -1;
-PLACE_PHCON_EAST cout -1;
-PLACE_PHCON_WEST np -1;
-PLACE_PHCON_WEST ng -1;
-PLACE_PHCON_EAST signe -1;
-PLACE_PHCON_EAST zero -1;
-PLACE_PHCON_EAST ovr -1;
-PLACE_PHCON_EAST q0 -1;
-PLACE_PHCON_EAST q3 -1;
-PLACE_PHCON_EAST f0 -1;
-PLACE_PHCON_EAST f3 -1;
-PLACE_PHCON_EAST fonc -1;
-PLACE_PHCON_EAST test -1;
-PLACE_PHCON_EAST scin -1;
-PLACE_PHCON_SOUTH scout -1;
-PLACE_PHCON_SOUTH i[8]  1;
-PLACE_PHCON_SOUTH i[7]  2;
-PLACE_PHCON_SOUTH i[6]  3;
-PLACE_PHCON_SOUTH i[5]  4;
-PLACE_PHCON_SOUTH i[4]  5;
-PLACE_PHCON_SOUTH i[3]  6;
-PLACE_PHCON_SOUTH i[2]  7;
-PLACE_PHCON_SOUTH i[1]  8;
-PLACE_PHCON_SOUTH i[0]  9;
-PLACE_PHCON_EAST decald -1;
-PLACE_PHCON_EAST decalg -1;
-PLACE_PHCON_WEST decaldr -1;
-PLACE_PHCON_WEST decalgr -1;
-PLACE_PHCON_WEST r0 -1;
-PLACE_PHCON_WEST r3 -1;
-PLACE_PHCON_WEST s0 -1;
-PLACE_PHCON_WEST s3 -1;
-PLACE_PHCON_SOUTH ck -1;
-PLACE_PHCON_WEST y[3]  1;
-PLACE_PHCON_WEST y[2]  2;
-PLACE_PHCON_WEST y[1]  3;
-PLACE_PHCON_WEST y[0]  4;
-PLACE_PHCON_WEST noe -1;
-PLACE_PHCON_WEST oe -1;
diff --git a/alliance/share/tutorials/amd2901/pattern.pat b/alliance/share/tutorials/amd2901/pattern.pat
deleted file mode 100644
index f4f37681..00000000
--- a/alliance/share/tutorials/amd2901/pattern.pat
+++ /dev/null
@@ -1,548 +0,0 @@
-
--- Pattern description generated by Pat driver v102
---		date : Thu Oct 14 16:51:16 1993
-
--- input / output list :
-in       a (3 downto 0) X;;
-in       b (3 downto 0) X;;
-in       d (3 downto 0) X;;
-in       i (8 downto 0) O;;
-in       fonc B;;
-in       test B;;
-in       scin B;;
-in       noe B;;
-in       cke B;;
-in       cin B;;
-inout    r0 B;;
-inout    r3 B;;
-inout    q0 B;;
-inout    q3 B;;
-out      y (3 downto 0) X;;
-out      zero B;;
-out      signe B;;
-out      scout B;;
-out      ovr B;;
-out      np B;;
-out      ng B;;
-out      cout B;;
-in       vdde B;;
-in       vsse B;;
-in       vddi B;;
-in       vssi B;;
-
-begin
-
--- Pattern description :
-
---           a b d i   f t s n c c  r  r  q  q  y  z  s  s  o  n  n  c v v v v  
---                     o e c o k i  0  3  0  3     e  i  c  v  p  g  o d s d s  
---                     n s i e   n                 r  g  o  r        u d s d s  
---                     c t n                       o  n  u           t     p p  
---                                                    e  t                      
-
-
--- Beware : unprocessed patterns
-
-accu_0     : 0 0 5 007 1 0 0 0 0 0  1  1  1  1 ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
-           : 0 0 5 007 1 0 0 0 1 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 0 0 5 007 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 0 0 5 462 1 0 0 0 0 0 ?1  1 ?1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 0 0 5 462 1 0 0 0 1 0 ?1  1 ?1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 0 0 5 462 1 0 0 0 0 0 ?0  1 ?0  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 0 1 5 462 1 0 0 0 0 0 ?0  0 ?0  0 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 0 1 5 462 1 0 0 0 1 0 ?0  0 ?0  0 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 0 1 5 462 1 0 0 0 0 0 ?1  0 ?1  0 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 0 2 5 432 1 0 0 0 0 0 ?1  1 ?1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 0 2 5 432 1 0 0 0 1 0 ?1  1 ?1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 0 2 5 432 1 0 0 0 0 0 ?0  1 ?0  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 0 3 5 432 1 0 0 0 0 0 ?0  0 ?0  0 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 0 3 5 432 1 0 0 0 1 0 ?0  0 ?0  0 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 0 3 5 432 1 0 0 0 0 0 ?1  0 ?1  0 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 1 4 5 564 1 0 0 0 0 0 ?1  1 ?1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 1 4 5 564 1 0 0 0 1 0 ?1  1 ?1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 1 4 5 564 1 0 0 0 0 0 ?1  1 ?1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 2 5 5 564 1 0 0 0 0 0 ?0  0 ?1  0 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 2 5 5 564 1 0 0 0 1 0 ?0  0 ?1  0 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 2 5 5 564 1 0 0 0 0 0 ?0  0 ?1  0 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 3 6 5 534 1 0 0 0 0 0 ?1  1 ?1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 3 6 5 534 1 0 0 0 1 0 ?1  1 ?1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 3 6 5 534 1 0 0 0 0 0 ?1  1 ?1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 7 5 534 1 0 0 0 0 0 ?0  0 ?1  0 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 7 5 534 1 0 0 0 1 0 ?0  0 ?1  0 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 7 5 534 1 0 0 0 0 0 ?0  0 ?1  0 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 0 5 163 1 0 0 0 0 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 0 5 163 1 0 0 0 1 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 0 5 163 1 0 0 0 0 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 1 5 163 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 1 5 163 1 0 0 0 1 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 1 5 163 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 2 5 163 1 0 0 0 0 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 2 5 163 1 0 0 0 1 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 2 5 163 1 0 0 0 0 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 3 5 163 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 3 5 163 1 0 0 0 1 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 3 5 163 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 4 5 163 1 0 0 0 0 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 4 5 163 1 0 0 0 1 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 4 5 163 1 0 0 0 0 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 5 5 163 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 5 5 163 1 0 0 0 1 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 5 5 163 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 6 5 163 1 0 0 0 0 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 6 5 163 1 0 0 0 1 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 6 5 163 1 0 0 0 0 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 7 5 163 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 7 5 163 1 0 0 0 1 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 7 5 163 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 0 7 5 034 1 0 0 0 0 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 0 7 5 034 1 0 0 0 1 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 0 7 5 034 1 0 0 0 0 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 0 0 5 662 1 0 0 0 0 0  1 ?1  1 ?1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 0 0 5 662 1 0 0 0 1 0  1 ?1  1 ?1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 0 0 5 662 1 0 0 0 0 0  1 ?0  1 ?0 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 0 1 5 662 1 0 0 0 0 0  0 ?0  0 ?0 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 0 1 5 662 1 0 0 0 1 0  0 ?0  0 ?0 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 0 1 5 662 1 0 0 0 0 0  0 ?1  0 ?1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 0 2 5 632 1 0 0 0 0 0  1 ?1  1 ?1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 0 2 5 632 1 0 0 0 1 0  1 ?1  1 ?1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 0 2 5 632 1 0 0 0 0 0  1 ?0  1 ?0 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 0 3 5 632 1 0 0 0 0 0  0 ?0  0 ?0 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 0 3 5 632 1 0 0 0 1 0  0 ?0  0 ?0 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 0 3 5 632 1 0 0 0 0 0  0 ?1  0 ?1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 1 4 5 764 1 0 0 0 0 0  1 ?1  1 ?1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 1 4 5 764 1 0 0 0 1 0  1 ?1  1 ?1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 1 4 5 764 1 0 0 0 0 0  1 ?1  1 ?1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 2 5 5 764 1 0 0 0 0 0  0 ?0  0 ?1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 2 5 5 764 1 0 0 0 1 0  0 ?0  0 ?1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 2 5 5 764 1 0 0 0 0 0  0 ?0  0 ?1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 3 6 5 734 1 0 0 0 0 0  1 ?1  1 ?1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 3 6 5 734 1 0 0 0 1 0  1 ?1  1 ?1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 3 6 5 734 1 0 0 0 0 0  1 ?1  1 ?1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 7 5 734 1 0 0 0 0 0  0 ?0  0 ?1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 7 5 734 1 0 0 0 1 0  0 ?0  0 ?1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 7 5 734 1 0 0 0 0 0  0 ?0  0 ?1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 0 5 163 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 0 5 163 1 0 0 0 1 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 0 5 163 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 1 5 163 1 0 0 0 0 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 1 5 163 1 0 0 0 1 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 1 5 163 1 0 0 0 0 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 2 5 163 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 2 5 163 1 0 0 0 1 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 2 5 163 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
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-           : 4 3 5 163 1 0 0 0 1 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 3 5 163 1 0 0 0 0 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 4 5 163 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 4 5 163 1 0 0 0 1 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 4 5 163 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 5 5 163 1 0 0 0 0 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 5 5 163 1 0 0 0 1 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 5 5 163 1 0 0 0 0 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 6 5 163 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 6 5 163 1 0 0 0 1 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 6 5 163 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 7 5 163 1 0 0 0 0 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 7 5 163 1 0 0 0 1 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 7 5 163 1 0 0 0 0 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
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-           : 4 0 f 367 1 0 0 0 1 0  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 0 f 367 1 0 0 0 0 0  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 0 1 e 267 1 0 0 0 0 0  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 0 1 e 267 1 0 0 0 1 0  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 0 1 e 267 1 0 0 0 0 0  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 1 2 d 267 1 0 0 0 0 0  1  1  1  1 ?e ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 1 2 d 267 1 0 0 0 1 0  1  1  1  1 ?e ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 1 2 d 267 1 0 0 0 0 0  1  1  1  1 ?e ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 2 3 c 267 1 0 0 0 0 0  1  1  1  1 ?d ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 2 3 c 267 1 0 0 0 1 0  1  1  1  1 ?d ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 2 3 c 267 1 0 0 0 0 0  1  1  1  1 ?d ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 3 4 b 267 1 0 0 0 0 0  1  1  1  1 ?c ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 3 4 b 267 1 0 0 0 1 0  1  1  1  1 ?c ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 3 4 b 267 1 0 0 0 0 0  1  1  1  1 ?c ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 5 a 267 1 0 0 0 0 0  1  1  1  1 ?b ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 5 a 267 1 0 0 0 1 0  1  1  1  1 ?b ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 5 a 267 1 0 0 0 0 0  1  1  1  1 ?b ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
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-           : 5 6 9 267 1 0 0 0 1 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 6 9 267 1 0 0 0 0 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
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-           : 6 7 8 267 1 0 0 0 1 0  1  1  1  1 ?9 ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 6 7 8 267 1 0 0 0 0 0  1  1  1  1 ?9 ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 7 8 7 267 1 0 0 0 0 0  1  1  1  1 ?8 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 7 8 7 267 1 0 0 0 1 0  1  1  1  1 ?8 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 7 8 7 267 1 0 0 0 0 0  1  1  1  1 ?8 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 8 9 6 267 1 0 0 0 0 0  1  1  1  1 ?7 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 8 9 6 267 1 0 0 0 1 0  1  1  1  1 ?7 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 8 9 6 267 1 0 0 0 0 0  1  1  1  1 ?7 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
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-           : 9 a 5 267 1 0 0 0 1 0  1  1  1  1 ?6 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 9 a 5 267 1 0 0 0 0 0  1  1  1  1 ?6 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a b 4 267 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a b 4 267 1 0 0 0 1 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a b 4 267 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : b c 3 267 1 0 0 0 0 0  1  1  1  1 ?4 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : b c 3 267 1 0 0 0 1 0  1  1  1  1 ?4 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : b c 3 267 1 0 0 0 0 0  1  1  1  1 ?4 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : c d 2 267 1 0 0 0 0 0  1  1  1  1 ?3 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : c d 2 267 1 0 0 0 1 0  1  1  1  1 ?3 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : c d 2 267 1 0 0 0 0 0  1  1  1  1 ?3 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : d e 1 267 1 0 0 0 0 0  1  1  1  1 ?2 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : d e 1 267 1 0 0 0 1 0  1  1  1  1 ?2 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : d e 1 267 1 0 0 0 0 0  1  1  1  1 ?2 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : e f 0 267 1 0 0 0 0 0  1  1  1  1 ?1 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : e f 0 267 1 0 0 0 1 0  1  1  1  1 ?1 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : e f 0 267 1 0 0 0 0 0  1  1  1  1 ?1 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 267 1 0 0 0 0 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 267 1 0 0 0 1 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 267 1 0 0 0 0 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
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-           : f 8 0 163 1 0 0 0 1 0  1  1  1  1 ?7 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f 8 0 163 1 0 0 0 0 0  1  1  1  1 ?7 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f 9 0 163 1 0 0 0 0 0  1  1  1  1 ?6 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f 9 0 163 1 0 0 0 1 0  1  1  1  1 ?6 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f 9 0 163 1 0 0 0 0 0  1  1  1  1 ?6 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
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-           : f a 0 163 1 0 0 0 1 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f a 0 163 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f b 0 163 1 0 0 0 0 0  1  1  1  1 ?4 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f b 0 163 1 0 0 0 1 0  1  1  1  1 ?4 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f b 0 163 1 0 0 0 0 0  1  1  1  1 ?4 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f c 0 163 1 0 0 0 0 0  1  1  1  1 ?3 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f c 0 163 1 0 0 0 1 0  1  1  1  1 ?3 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f c 0 163 1 0 0 0 0 0  1  1  1  1 ?3 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f d 0 163 1 0 0 0 0 0  1  1  1  1 ?2 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f d 0 163 1 0 0 0 1 0  1  1  1  1 ?2 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f d 0 163 1 0 0 0 0 0  1  1  1  1 ?2 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f e 0 163 1 0 0 0 0 0  1  1  1  1 ?1 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f e 0 163 1 0 0 0 1 0  1  1  1  1 ?1 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f e 0 163 1 0 0 0 0 0  1  1  1  1 ?1 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 163 1 0 0 0 0 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 163 1 0 0 0 1 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 163 1 0 0 0 0 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
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-           : f 0 0 337 1 0 0 0 1 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f 0 0 337 1 0 0 0 0 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
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-           : 0 1 1 237 1 0 0 0 0 0  1  1  1  1 ?0 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
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-           : 1 2 2 237 1 0 0 0 1 0  1  1  1  1 ?1 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 1 2 2 237 1 0 0 0 0 0  1  1  1  1 ?1 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
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-           : 2 3 3 237 1 0 0 0 0 0  1  1  1  1 ?2 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
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-           : 3 4 4 237 1 0 0 0 1 0  1  1  1  1 ?3 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 3 4 4 237 1 0 0 0 0 0  1  1  1  1 ?3 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
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-           : 4 5 5 237 1 0 0 0 1 0  1  1  1  1 ?4 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 4 5 5 237 1 0 0 0 0 0  1  1  1  1 ?4 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 6 6 237 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 6 6 237 1 0 0 0 1 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 6 6 237 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?* ?1 ?1 ?0 1 0 1 0 ;
-           : 6 7 7 237 1 0 0 0 0 0  1  1  1  1 ?6 ?0 ?0 ?* ?* ?1 ?1 ?0 1 0 1 0 ;
-           : 6 7 7 237 1 0 0 0 1 0  1  1  1  1 ?6 ?0 ?0 ?* ?* ?1 ?1 ?0 1 0 1 0 ;
-           : 6 7 7 237 1 0 0 0 0 0  1  1  1  1 ?6 ?0 ?0 ?* ?* ?1 ?1 ?0 1 0 1 0 ;
-           : 7 8 8 237 1 0 0 0 0 0  1  1  1  1 ?7 ?0 ?1 ?* ?* ?1 ?1 ?0 1 0 1 0 ;
-           : 7 8 8 237 1 0 0 0 1 0  1  1  1  1 ?7 ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 7 8 8 237 1 0 0 0 0 0  1  1  1  1 ?7 ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 8 9 9 237 1 0 0 0 0 0  1  1  1  1 ?8 ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 8 9 9 237 1 0 0 0 1 0  1  1  1  1 ?8 ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 8 9 9 237 1 0 0 0 0 0  1  1  1  1 ?8 ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 9 a a 237 1 0 0 0 0 0  1  1  1  1 ?9 ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 9 a a 237 1 0 0 0 1 0  1  1  1  1 ?9 ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 9 a a 237 1 0 0 0 0 0  1  1  1  1 ?9 ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a b b 237 1 0 0 0 0 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a b b 237 1 0 0 0 1 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a b b 237 1 0 0 0 0 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : b c c 237 1 0 0 0 0 0  1  1  1  1 ?b ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : b c c 237 1 0 0 0 1 0  1  1  1  1 ?b ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : b c c 237 1 0 0 0 0 0  1  1  1  1 ?b ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : c d d 237 1 0 0 0 0 0  1  1  1  1 ?c ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : c d d 237 1 0 0 0 1 0  1  1  1  1 ?c ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : c d d 237 1 0 0 0 0 0  1  1  1  1 ?c ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : d e e 237 1 0 0 0 0 0  1  1  1  1 ?d ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : d e e 237 1 0 0 0 1 0  1  1  1  1 ?d ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : d e e 237 1 0 0 0 0 0  1  1  1  1 ?d ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : e f f 237 1 0 0 0 0 0  1  1  1  1 ?e ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : e f f 237 1 0 0 0 1 0  1  1  1  1 ?e ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : e f f 237 1 0 0 0 0 0  1  1  1  1 ?e ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f f 267 1 0 0 0 0 0  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f f 267 1 0 0 0 1 0  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f f 267 1 0 0 0 0 0  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f 8 f 133 1 0 0 0 0 0  1  1  1  1 ?8 ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f 8 f 133 1 0 0 0 1 0  1  1  1  1 ?8 ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f 8 f 133 1 0 0 0 0 0  1  1  1  1 ?8 ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f 9 f 133 1 0 0 0 0 0  1  1  1  1 ?9 ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f 9 f 133 1 0 0 0 1 0  1  1  1  1 ?9 ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f 9 f 133 1 0 0 0 0 0  1  1  1  1 ?9 ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f a f 133 1 0 0 0 0 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f a f 133 1 0 0 0 1 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f a f 133 1 0 0 0 0 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f b f 133 1 0 0 0 0 0  1  1  1  1 ?b ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f b f 133 1 0 0 0 1 0  1  1  1  1 ?b ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f b f 133 1 0 0 0 0 0  1  1  1  1 ?b ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f c f 133 1 0 0 0 0 0  1  1  1  1 ?c ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f c f 133 1 0 0 0 1 0  1  1  1  1 ?c ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f c f 133 1 0 0 0 0 0  1  1  1  1 ?c ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f d f 133 1 0 0 0 0 0  1  1  1  1 ?d ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f d f 133 1 0 0 0 1 0  1  1  1  1 ?d ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f d f 133 1 0 0 0 0 0  1  1  1  1 ?d ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f e f 133 1 0 0 0 0 0  1  1  1  1 ?e ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f e f 133 1 0 0 0 1 0  1  1  1  1 ?e ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f e f 133 1 0 0 0 0 0  1  1  1  1 ?e ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f f 133 1 0 0 0 0 0  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f f 133 1 0 0 0 1 0  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f f 133 1 0 0 0 0 0  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 164 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 164 1 0 0 0 1 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 164 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
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-           : 5 f f 134 1 0 0 0 1 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 134 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 135 1 0 0 0 0 0  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 135 1 0 0 0 1 0  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 135 1 0 0 0 0 0  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 144 1 0 0 0 0 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 144 1 0 0 0 1 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 144 1 0 0 0 0 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 145 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 145 1 0 0 0 1 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 145 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 154 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 154 1 0 0 0 1 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 154 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 155 1 0 0 0 0 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 155 1 0 0 0 1 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 155 1 0 0 0 0 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 164 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 164 1 0 0 0 1 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 164 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 165 1 0 0 0 0 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 165 1 0 0 0 1 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 165 1 0 0 0 0 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 174 1 0 0 0 0 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 174 1 0 0 0 1 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 174 1 0 0 0 0 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 175 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 175 1 0 0 0 1 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 175 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 104 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 104 1 0 0 0 1 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 104 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 105 1 0 0 0 0 0  1  1  1  1 ?4 ?0 ?0 ?* ?0 ?0 ?0 ?1 1 0 1 0 ;
-           : 5 f f 105 1 0 0 0 1 0  1  1  1  1 ?4 ?0 ?0 ?* ?0 ?0 ?0 ?1 1 0 1 0 ;
-           : 5 f f 105 1 0 0 0 0 0  1  1  1  1 ?4 ?0 ?0 ?* ?0 ?0 ?0 ?1 1 0 1 0 ;
-           : 5 f f 114 1 0 0 0 0 0  1  1  1  1 ?4 ?0 ?0 ?* ?0 ?0 ?0 ?1 1 0 1 0 ;
-           : 5 f f 114 1 0 0 0 1 0  1  1  1  1 ?4 ?0 ?0 ?* ?0 ?0 ?0 ?1 1 0 1 0 ;
-           : 5 f f 114 1 0 0 0 0 0  1  1  1  1 ?4 ?0 ?0 ?* ?0 ?0 ?0 ?1 1 0 1 0 ;
-           : 5 f f 115 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 115 1 0 0 0 1 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 115 1 0 0 0 0 0  1  1  1  1 ?5 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 124 1 0 0 0 0 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 124 1 0 0 0 1 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 124 1 0 0 0 0 0  1  1  1  1 ?a ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : 5 f f 125 1 0 0 0 0 0  1  1  1  1 ?9 ?0 ?1 ?* ?0 ?0 ?0 ?1 1 0 1 0 ;
-           : 5 f f 125 1 0 0 0 1 0  1  1  1  1 ?9 ?0 ?1 ?* ?0 ?0 ?0 ?1 1 0 1 0 ;
-           : 5 f f 125 1 0 0 0 0 0  1  1  1  1 ?9 ?0 ?1 ?* ?0 ?0 ?0 ?1 1 0 1 0 ;
-           : a f 3 037 1 0 0 0 0 0  1  1  1  1 ?3 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 037 1 0 0 0 1 0  1  1  1  1 ?3 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 037 1 0 0 0 0 0  1  1  1  1 ?3 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 100 1 0 0 0 0 0  1  1  1  1 ?d ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 100 1 0 0 0 1 0  1  1  1  1 ?d ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 100 1 0 0 0 0 0  1  1  1  1 ?d ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 102 1 0 0 0 0 0  1  1  1  1 ?3 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 102 1 0 0 0 1 0  1  1  1  1 ?3 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 102 1 0 0 0 0 0  1  1  1  1 ?3 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 110 1 0 0 0 0 0  1  1  1  1 ?8 ?0 ?1 ?* ?1 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 110 1 0 0 0 1 0  1  1  1  1 ?8 ?0 ?1 ?* ?1 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 110 1 0 0 0 0 0  1  1  1  1 ?8 ?0 ?1 ?* ?1 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 112 1 0 0 0 0 0  1  1  1  1 ?2 ?0 ?0 ?* ?0 ?0 ?0 ?1 1 0 1 0 ;
-           : a f 3 112 1 0 0 0 1 0  1  1  1  1 ?2 ?0 ?0 ?* ?0 ?0 ?0 ?1 1 0 1 0 ;
-           : a f 3 112 1 0 0 0 0 0  1  1  1  1 ?2 ?0 ?0 ?* ?0 ?0 ?0 ?1 1 0 1 0 ;
-           : a f 3 120 1 0 0 0 0 0  1  1  1  1 ?6 ?0 ?0 ?* ?1 ?1 ?0 ?1 1 0 1 0 ;
-           : a f 3 120 1 0 0 0 1 0  1  1  1  1 ?6 ?0 ?0 ?* ?1 ?1 ?0 ?1 1 0 1 0 ;
-           : a f 3 120 1 0 0 0 0 0  1  1  1  1 ?6 ?0 ?0 ?* ?1 ?1 ?0 ?1 1 0 1 0 ;
-           : a f 3 122 1 0 0 0 0 0  1  1  1  1 ?c ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 122 1 0 0 0 1 0  1  1  1  1 ?c ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 122 1 0 0 0 0 0  1  1  1  1 ?c ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 130 1 0 0 0 0 0  1  1  1  1 ?b ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 130 1 0 0 0 1 0  1  1  1  1 ?b ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 130 1 0 0 0 0 0  1  1  1  1 ?b ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 132 1 0 0 0 0 0  1  1  1  1 ?3 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 132 1 0 0 0 1 0  1  1  1  1 ?3 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 132 1 0 0 0 0 0  1  1  1  1 ?3 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 140 1 0 0 0 0 0  1  1  1  1 ?2 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 140 1 0 0 0 1 0  1  1  1  1 ?2 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 140 1 0 0 0 0 0  1  1  1  1 ?2 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 142 1 0 0 0 0 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 142 1 0 0 0 1 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 142 1 0 0 0 0 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 150 1 0 0 0 0 0  1  1  1  1 ?1 ?0 ?0 ?* ?* ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 150 1 0 0 0 1 0  1  1  1  1 ?1 ?0 ?0 ?* ?* ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 150 1 0 0 0 0 0  1  1  1  1 ?1 ?0 ?0 ?* ?* ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 152 1 0 0 0 0 0  1  1  1  1 ?3 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 152 1 0 0 0 1 0  1  1  1  1 ?3 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 152 1 0 0 0 0 0  1  1  1  1 ?3 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 160 1 0 0 0 0 0  1  1  1  1 ?9 ?0 ?1 ?* ?* ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 160 1 0 0 0 1 0  1  1  1  1 ?9 ?0 ?1 ?* ?* ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 160 1 0 0 0 0 0  1  1  1  1 ?9 ?0 ?1 ?* ?* ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 162 1 0 0 0 0 0  1  1  1  1 ?3 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 162 1 0 0 0 1 0  1  1  1  1 ?3 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 162 1 0 0 0 0 0  1  1  1  1 ?3 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 170 1 0 0 0 0 0  1  1  1  1 ?6 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 170 1 0 0 0 1 0  1  1  1  1 ?6 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 170 1 0 0 0 0 0  1  1  1  1 ?6 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 172 1 0 0 0 0 0  1  1  1  1 ?c ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 172 1 0 0 0 1 0  1  1  1  1 ?c ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 3 172 1 0 0 0 0 0  1  1  1  1 ?c ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f c 037 1 0 0 0 0 0  1  1  1  1 ?c ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f c 037 1 0 0 0 1 0  1  1  1  1 ?c ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f c 037 1 0 0 0 0 0  1  1  1  1 ?c ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 136 1 0 0 0 0 0  1  1  1  1 ?c ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 136 1 0 0 0 1 0  1  1  1  1 ?c ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 136 1 0 0 0 0 0  1  1  1  1 ?c ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 137 1 0 0 0 0 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 137 1 0 0 0 1 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 137 1 0 0 0 0 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 146 1 0 0 0 0 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 146 1 0 0 0 1 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 146 1 0 0 0 0 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 147 1 0 0 0 0 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 147 1 0 0 0 1 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 147 1 0 0 0 0 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 156 1 0 0 0 0 0  1  1  1  1 ?c ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 156 1 0 0 0 1 0  1  1  1  1 ?c ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 156 1 0 0 0 0 0  1  1  1  1 ?c ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 157 1 0 0 0 0 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 157 1 0 0 0 1 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 157 1 0 0 0 0 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 166 1 0 0 0 0 0  1  1  1  1 ?c ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 166 1 0 0 0 1 0  1  1  1  1 ?c ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 166 1 0 0 0 0 0  1  1  1  1 ?c ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 167 1 0 0 0 0 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 167 1 0 0 0 1 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 167 1 0 0 0 0 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 176 1 0 0 0 0 0  1  1  1  1 ?3 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 176 1 0 0 0 1 0  1  1  1  1 ?3 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 176 1 0 0 0 0 0  1  1  1  1 ?3 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 177 1 0 0 0 0 0  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 177 1 0 0 0 1 0  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 177 1 0 0 0 0 0  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 106 1 0 0 0 0 0  1  1  1  1 ?c ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 106 1 0 0 0 1 0  1  1  1  1 ?c ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 106 1 0 0 0 0 0  1  1  1  1 ?c ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 107 1 0 0 0 0 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 107 1 0 0 0 1 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 107 1 0 0 0 0 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 116 1 0 0 0 0 0  1  1  1  1 ?b ?0 ?1 ?* ?0 ?0 ?0 ?1 1 0 1 0 ;
-           : a f 0 116 1 0 0 0 1 0  1  1  1  1 ?b ?0 ?1 ?* ?0 ?0 ?0 ?1 1 0 1 0 ;
-           : a f 0 116 1 0 0 0 0 0  1  1  1  1 ?b ?0 ?1 ?* ?0 ?0 ?0 ?1 1 0 1 0 ;
-           : a f 0 117 1 0 0 0 0 0  1  1  1  1 ?f ?0 ?1 ?* ?0 ?0 ?1 ?0 1 0 1 0 ;
-           : a f 0 117 1 0 0 0 1 0  1  1  1  1 ?f ?0 ?1 ?* ?0 ?0 ?1 ?0 1 0 1 0 ;
-           : a f 0 117 1 0 0 0 0 0  1  1  1  1 ?f ?0 ?1 ?* ?0 ?0 ?1 ?0 1 0 1 0 ;
-           : a f 0 126 1 0 0 0 0 0  1  1  1  1 ?3 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 126 1 0 0 0 1 0  1  1  1  1 ?3 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 126 1 0 0 0 0 0  1  1  1  1 ?3 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : a f 0 127 1 0 0 0 0 0  1  1  1  1 ?f ?0 ?1 ?* ?0 ?0 ?1 ?0 1 0 1 0 ;
-           : a f 0 127 1 0 0 0 1 0  1  1  1  1 ?f ?0 ?1 ?* ?0 ?0 ?1 ?0 1 0 1 0 ;
-           : a f 0 127 1 0 0 0 0 0  1  1  1  1 ?f ?0 ?1 ?* ?0 ?0 ?1 ?0 1 0 1 0 ;
-           : f f 0 101 1 0 0 0 0 0  1  1  1  1 ?e ?0 ?1 ?* ?0 ?0 ?0 ?1 1 0 1 0 ;
-           : f f 0 101 1 0 0 0 1 0  1  1  1  1 ?e ?0 ?1 ?* ?0 ?0 ?0 ?1 1 0 1 0 ;
-           : f f 0 101 1 0 0 0 0 0  1  1  1  1 ?e ?0 ?1 ?* ?0 ?0 ?0 ?1 1 0 1 0 ;
-           : f f 0 103 1 0 0 0 0 0  1  1  1  1 ?f ?0 ?1 ?* ?0 ?0 ?1 ?0 1 0 1 0 ;
-           : f f 0 103 1 0 0 0 1 0  1  1  1  1 ?f ?0 ?1 ?* ?0 ?0 ?1 ?0 1 0 1 0 ;
-           : f f 0 103 1 0 0 0 0 0  1  1  1  1 ?f ?0 ?1 ?* ?0 ?0 ?1 ?0 1 0 1 0 ;
-           : f f 0 111 1 0 0 0 0 0  1  1  1  1 ?f ?0 ?1 ?* ?0 ?0 ?1 ?0 1 0 1 0 ;
-           : f f 0 111 1 0 0 0 1 0  1  1  1  1 ?f ?0 ?1 ?* ?0 ?0 ?1 ?0 1 0 1 0 ;
-           : f f 0 111 1 0 0 0 0 0  1  1  1  1 ?f ?0 ?1 ?* ?0 ?0 ?1 ?0 1 0 1 0 ;
-           : f f 0 113 1 0 0 0 0 0  1  1  1  1 ?e ?0 ?1 ?* ?0 ?0 ?0 ?1 1 0 1 0 ;
-           : f f 0 113 1 0 0 0 1 0  1  1  1  1 ?e ?0 ?1 ?* ?0 ?0 ?0 ?1 1 0 1 0 ;
-           : f f 0 113 1 0 0 0 0 0  1  1  1  1 ?e ?0 ?1 ?* ?0 ?0 ?0 ?1 1 0 1 0 ;
-           : f f 0 121 1 0 0 0 0 0  1  1  1  1 ?f ?0 ?1 ?* ?0 ?0 ?1 ?0 1 0 1 0 ;
-           : f f 0 121 1 0 0 0 1 0  1  1  1  1 ?f ?0 ?1 ?* ?0 ?0 ?1 ?0 1 0 1 0 ;
-           : f f 0 121 1 0 0 0 0 0  1  1  1  1 ?f ?0 ?1 ?* ?0 ?0 ?1 ?0 1 0 1 0 ;
-           : f f 0 123 1 0 0 0 0 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 123 1 0 0 0 1 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 123 1 0 0 0 0 0  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 101 1 0 0 0 0 1  1  1  1  1 ?f ?0 ?1 ?* ?0 ?0 ?0 ?1 1 0 1 0 ;
-           : f f 0 101 1 0 0 0 1 1  1  1  1  1 ?f ?0 ?1 ?* ?0 ?0 ?0 ?1 1 0 1 0 ;
-           : f f 0 101 1 0 0 0 0 1  1  1  1  1 ?f ?0 ?1 ?* ?0 ?0 ?0 ?1 1 0 1 0 ;
-           : f f 0 103 1 0 0 0 0 1  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?0 ?1 ?1 1 0 1 0 ;
-           : f f 0 103 1 0 0 0 1 1  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?0 ?1 ?1 1 0 1 0 ;
-           : f f 0 103 1 0 0 0 0 1  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?0 ?1 ?1 1 0 1 0 ;
-           : f f 0 111 1 0 0 0 0 1  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?0 ?1 ?1 1 0 1 0 ;
-           : f f 0 111 1 0 0 0 1 1  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?0 ?1 ?1 1 0 1 0 ;
-           : f f 0 111 1 0 0 0 0 1  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?0 ?1 ?1 1 0 1 0 ;
-           : f f 0 113 1 0 0 0 0 1  1  1  1  1 ?f ?0 ?1 ?* ?0 ?0 ?0 ?1 1 0 1 0 ;
-           : f f 0 113 1 0 0 0 1 1  1  1  1  1 ?f ?0 ?1 ?* ?0 ?0 ?0 ?1 1 0 1 0 ;
-           : f f 0 113 1 0 0 0 0 1  1  1  1  1 ?f ?0 ?1 ?* ?0 ?0 ?0 ?1 1 0 1 0 ;
-           : f f 0 121 1 0 0 0 0 1  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?0 ?1 ?1 1 0 1 0 ;
-           : f f 0 121 1 0 0 0 1 1  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?0 ?1 ?1 1 0 1 0 ;
-           : f f 0 121 1 0 0 0 0 1  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?0 ?1 ?1 1 0 1 0 ;
-           : f f 0 123 1 0 0 0 0 1  1  1  1  1 ?1 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 123 1 0 0 0 1 1  1  1  1  1 ?1 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 123 1 0 0 0 0 1  1  1  1  1 ?1 ?0 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 131 1 0 0 0 0 1  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 131 1 0 0 0 1 1  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 131 1 0 0 0 0 1  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 133 1 0 0 0 0 1  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 133 1 0 0 0 1 1  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 133 1 0 0 0 0 1  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 141 1 0 0 0 0 1  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 141 1 0 0 0 1 1  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 141 1 0 0 0 0 1  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 143 1 0 0 0 0 1  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 143 1 0 0 0 1 1  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 143 1 0 0 0 0 1  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 151 1 0 0 0 0 1  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 151 1 0 0 0 1 1  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 151 1 0 0 0 0 1  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 153 1 0 0 0 0 1  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 153 1 0 0 0 1 1  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 153 1 0 0 0 0 1  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 161 1 0 0 0 0 1  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 161 1 0 0 0 1 1  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 161 1 0 0 0 0 1  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 163 1 0 0 0 0 1  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 163 1 0 0 0 1 1  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 163 1 0 0 0 0 1  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 171 1 0 0 0 0 1  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 171 1 0 0 0 1 1  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 171 1 0 0 0 0 1  1  1  1  1 ?f ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 173 1 0 0 0 0 1  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 173 1 0 0 0 1 1  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f 0 173 1 0 0 0 0 1  1  1  1  1 ?0 ?1 ?0 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-scan_471   : f f e 067 1 0 0 0 0 1  1  1  1  1 ?e ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f e 067 1 0 0 0 1 1  1  1  1  1 ?e ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f e 067 1 0 0 0 0 1  1  1  1  1 ?e ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f e 162 1 0 0 0 0 1  1  1  1  1 ?e ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f e 162 1 0 0 0 1 1  1  1  1  1 ?e ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f e 162 1 0 0 0 0 1  1  1  1  1 ?e ?0 ?1 ?* ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f e 162 0 1 0 0 0 1  1  1  1  1 ?e ?0 ?1 ?1 ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f e 162 0 1 0 0 1 1  1  1  1  1 ?e ?0 ?1 ?1 ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f e 162 0 1 0 0 0 1  1  1  1  1 ?c ?0 ?1 ?1 ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f e 162 0 1 1 0 0 1  1  1  1  1 ?c ?0 ?1 ?1 ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f e 162 0 1 1 0 1 1  1  1  1  1 ?c ?0 ?1 ?1 ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f e 162 0 1 1 0 0 1  1  1  1  1 ?9 ?0 ?1 ?1 ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f e 162 0 1 0 0 0 1  1  1  1  1 ?9 ?0 ?1 ?1 ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f e 162 0 1 0 0 1 1  1  1  1  1 ?9 ?0 ?1 ?1 ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f e 162 0 1 0 0 0 1  1  1  1  1 ?2 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f e 162 0 1 0 0 0 1  1  1  1  1 ?2 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f e 162 0 1 0 0 1 1  1  1  1  1 ?2 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f e 162 0 1 0 0 0 1  1  1  1  1 ?4 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f e 162 0 1 0 0 0 1  1  1  1  1 ?4 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f e 162 0 1 0 0 1 1  1  1  1  1 ?4 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f e 162 0 1 0 0 0 1  1  1  1  1 ?8 ?0 ?1 ?1 ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f e 162 0 1 0 0 0 1  1  1  1  1 ?8 ?0 ?1 ?1 ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f e 162 0 1 0 0 1 1  1  1  1  1 ?8 ?0 ?1 ?1 ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f e 162 0 1 0 0 0 1  1  1  1  1 ?0 ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f e 162 0 1 0 0 0 1  1  1  1  1 ?0 ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f e 162 0 1 0 0 1 1  1  1  1  1 ?0 ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f e 162 0 1 0 0 0 1  1  1  1  1 ?0 ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
-high_z_498 : f f e 162 0 1 0 1 0 1  1  1  1  1 ?* ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f e 162 0 1 0 1 1 1  1  1  1  1 ?* ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
-           : f f e 162 0 1 0 1 0 1  1  1  1  1 ?* ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
-
-end;
diff --git a/alliance/share/tutorials/amd2901/tex/Makefile b/alliance/share/tutorials/amd2901/tex/Makefile
deleted file mode 100644
index ab46bfb4..00000000
--- a/alliance/share/tutorials/amd2901/tex/Makefile
+++ /dev/null
@@ -1,21 +0,0 @@
-# Generic Makefile for TeTeX projet
-# (C) 1999, Czo
-# $Id: Makefile,v 1.1 2000/01/20 16:10:03 czo Exp $
-
-MYFILE=amd2901
-
-view : ps
-	gv $(MYFILE).ps
-        
-ps   : $(MYFILE).tex
-	latex $(MYFILE).tex
-	dvips $(MYFILE).dvi -o $(MYFILE).ps
-
-distrib : clean ps        
-	ps2pdf $(MYFILE).ps
-	cp -f $(MYFILE).ps ..
-	cp -f $(MYFILE).pdf ..
-	$(MAKE) clean
-
-clean :
-	rm -f $(MYFILE).ps $(MYFILE).pdf *.log *.dvi *.aux
diff --git a/alliance/share/tutorials/amd2901/tex/amd2901.tex b/alliance/share/tutorials/amd2901/tex/amd2901.tex
deleted file mode 100644
index 5681f3e7..00000000
--- a/alliance/share/tutorials/amd2901/tex/amd2901.tex
+++ /dev/null
@@ -1,647 +0,0 @@
-%%%%%%%%%%%%%%%%%%%%
-%
-% The amd2901 tutorial.
-% Modified by czo for Alliance release 4.0 (01/2000)
-% TODO : no fully working, needs some adjustements
-% $Id: amd2901.tex,v 1.1 2000/01/20 16:10:03 czo Exp $
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\documentclass[11pt,a4]{article}
-
-\textwidth  21.0cm
-
-\oddsidemargin  -5.0cm
-\evensidemargin -2.5in
-
-\usepackage{picinpar}
-\usepackage{a4}
-\def\S#1{\protect\makebox[\mylength][l]{\noindent#1}}
-
-
-
-\begin{document} 
-
-\begin{center}
-\Huge\bf TUTORIAL : AMD 2901
-\end{center}
-
-Welcome to the {\bf ALLIANCE} CAD system.\\
-The goal of this tutorial is to present a typical design-flow of a
-simple 4 bits processor (AMD2901), using the {\bf ALLIANCE} tools.
-
-The tools used here are :
-
-\begin{itemize}
-\item {\bf asimut} :	{\bf VHDL} compiler and simulator.
-\item {\bf genlib} :	Net-List capture.
-\item {\bf scr} :	Standard Cell placer and router.
-\item {\bf ring} :	Core to pads router.
-\item {\bf lynx} :	Symbolic layout extractor.
-\item {\bf lvx} :	Net-List comparator.
-\item {\bf druc} :	Design rule checker.
-\item {\bf graal} :	Graphic layout editor.
-\item {\bf yagle} :	Functional abstractor.
-\item {\bf proof} :	Formal proof between two behavioral descriptions.
-\item {\bf s2r} :	Symbolic to real layout converter.
-\item {\bf tas} :	Timing Analysis static.
-\end{itemize}
-At any time you can get information on any {\bf ALLIANCE} tool using 
-the command :\\
-\\
-\fbox{
-{\bf $>$ man $<$tool name$>$} 
-}\\
-\\
-All the available documentation is described in the {\bf README} file.
-This tutorial doesn't contain a description of the {\bf AMD2901}, but
-the methodology used in {\bf ALLIANCE} to produce it.
-Nevertheless, you will find in the file {\bf AMD2901\_doc.ps.tar},
- the original data-sheet of the circuit.
-To uncompress the sheets, use the {\bf UNIX} command :\\
-\\
-\fbox{
-\shortstack[l]{
-{\bf $>$tar xvf  AMD2901\_doc.ps.tar} \\
-{\bf $>$uncompress AMD2901*.Z} 
-}}\\
-A GIF format of the data-sheet is also available in the file  {\bf AMD2901\_doc.gif.tar}.
-\\
-The design-flow used in this tutorial is composed of five steps :
-\begin{itemize}
-\item {\bf Step 1} : Behavioural description ({\bf VHDL} model) and simulation.
-\item {\bf Step 2} : Generation and validation of the structural description 
-(gate net-list).
-\item {\bf Step 3} : Physical design layout (Place and route).
-\item {\bf Step 4} : Extraction and verification.
-\item {\bf Step 5} : Timing analysis.
-\item {\bf Step 6} : Chip finishing.
-\end{itemize}
-
-In order to build the chip in about two hours, all the source files
-are provided with this tutorial : 
-\begin{itemize}
-\item {\bf amd.vbe} : {\bf VHDL} behavioural model.
-\item {\bf pattern.pat} : Simulation Patterns.
-\item {\bf chip.c} : Chip structural description.
-\item {\bf chip.rin} : Pads placement (for {\bf ring}).
-\item {\bf heart.scr} : Connectors placement (for {\bf scr}).
-\item {\bf chip.inf} : Registers renaming (for {\bf desb}).
-\end{itemize}
-
-You will use the {\bf ALLIANCE} tools to validate these input files
-and to build the physical layout. 
-The output is a {\bf CIF} layout file ready for the foundry.
-
-To build the chip you can :
-\begin{itemize}
-\item - run the {\bf UNIX} commands in the order indicated by this tutorial.
-\item - build automatically the entire {\bf AMD2901 CHIP} using the command : \\
-\\
-\fbox{
-{\bf $>$ make} 
-}\\
-\\
-If you want to start again this example from the begining,
-you just have to type :\\
-\\
-\fbox{
-\shortstack[l]{
-{\bf $>$ make clean} \ \\
-{\bf $>$ make} 
-}}
-\end{itemize}
-
-All {\bf ALLIANCE} tools use a set of {\bf UNIX} environment variables.
-These variables are set by the {\bf UNIX} command ``export''.\\
-\\
-\fbox{
-\shortstack[l]{
-{\bf $>$ MBK\_WORK\_LIB=.} \\
-{\bf $>$ MBK\_CATA\_LIB=.:/\$ALLIANCE\_TOP/cells/sclib/prol10:/\$ALLIANCE\_TOP/cells/ring/padsymb} \\
-{\bf $>$ export MBK\_WORK\_LIB MBK\_CATA\_LIB}
-}}
-
-\begin{itemize}
-\item{\bf MBK\_CATA\_LIB :} This variable defines all paths to the directories
-containing the {\bf ALLIANCE} predefined cell libraries.
-\item{\bf MBK\_WORK\_LIB :} This variable defines the working directory : 
-all user files will be written in this directory.
-\end{itemize}
-Some of the path names have to be modified in order to correspond to your particular installation of Alliance, in this tutorial we will assume that the directory structure of the sources files has not been altered
-In this tutorial, the commands which are inside [ ] are preset. 
-If you stay in  the same shell during the making of the {\bf AMD2901},
- you don't have to set again these environment variables.
-
-\section{Behavioural specification}
-
-\subsection{Behavioural model}
-
-The circuit behaviour is described in the amd.vbe file using the 
-{\bf ALLIANCE VHDL} subset (see {\it man vhdl} and {\it man vbe}).
-You must run the {\bf VHDL} compiler to validate the {\bf VHDL}
-file syntax.\\
-\\
-\fbox{
-\shortstack[l]{
-{\bf [$>$ MBK\_WORK\_LIB=.]}\\
-{\bf [$>$ MBK\_CATA\_LIB=.:/\$ALLIANCE\_TOP/cells/sclib/prol10:/\$ALLIANCE\_TOP/cells/ring/padsymb]}\\
-{\bf [$>$ export MBK\_CATA\_LIB MBK\_WORK\_LIB]}\\
-{\bf $>$ asimut -b -c amd}
-}
-}
-\begin{itemize}
-\item {\bf amd} is the filename of the behavioural description ({\bf amd.vbe}).
-\item {\bf -b} means that the file is a pure behavioural description.
-\item {\bf -c} stands for compilation only (compilability is checked, 
-no simulation is performed).
-\end{itemize}
-
-\subsection{Simulation patterns}
-As you have specified a formal specification,
-you have to define a set of simulation patterns.
-The same patterns will be used to validate each design step
-from specification to physical layout.
-\\
-The file {\bf pattern.pat} is given as an example.
-
-\subsection{Simulation}
-You have now a logical description of your circuit, and a list of patterns.
-You can run the zero-delay VHDL simulator {\bf asimut}.
-You have to set up some new environment variables specific to {\bf asimut}.\\
-\fbox{
-\shortstack[l]{
-{\bf $>$ VH\_MAXERR=10}\\
-{\bf $>$ export VH\_MAXERR}
-}
-}
-
-\begin{itemize}
-\item 
-{\bf VH\_MAXERR} : The maximum number of errors accepted before {\bf asimut} stops simulation.
-\end{itemize}
-
-\fbox{
-\shortstack[l]{
-{\bf  $>$ VH\_PATSFX=pat] }\\
-{\bf  $>$ export VH\_PATSFX]}
-}}
-
-\begin{itemize}
-\item {\bf VH\_PATSFX} the extension of simulation patterns file.
-\end{itemize}
-
-\fbox{
-\shortstack[l]{
-{\bf [$>$ VH\_MAXERR=10]}\\
-{\bf [$>$ VH\_PATSFX=pat]}\\
-{\bf [$>$ MBK\_WORK\_LIB=.]}\\
-{\bf [$>$ MBK\_CATA\_LIB=.:/\$ALLIANCE\_TOP/cells/sclib/prol10:/\$ALLIANCE\_TOP/cells/ring/padsymb]}\\
-{\bf [$>$ export MBK\_CATA\_LIB VH\_MAXERR VH\_PATSFX MBK\_WORK\_LIB]}\\
-{\bf $>$ asimut -b amd pattern result\_beh}
-}
-}
-\begin{itemize}
-\item {\bf amd} : is the filename of the description ({\bf amd.vbe}).
-\item {\bf pattern} : is the filename for the input patterns ({\bf pattern.pat}).
-\item {\bf result\_beh} : is the filename for the resulting patterns ({\bf result\_beh.pat}).
-\item {\bf -b} : means that the {\bf amd} file is a pure behavioural description.
-\end{itemize}
-
-The input pattern file can provide the expected outputs.
-Any difference between predicted outputs in {\bf pattern.pat} and simulation 
-results will be reported as commentary
-on the screen and in {\bf result\_beh.pat}. This output file may be used again
-for an another simulation, since it has the same format as the input file.
-
-\section{Structural Description}
-
-\subsection{Structural Design}
-
-The aim of this step is to build the gate level schematic 
-corresponding to the behavioural specification.
-
-We must instantiate and connect logical gates and pads,
-supplied in the standard cell library {\bf scr} and the pad 
-library {\bf ring}. 
-To do this, {\bf ALLIANCE} doesn't use a schematic editor
-but the procedural language {\bf genlib}
-which is a set of C functions (see {\it man genlib}).
-
-The structural description of the {\bf AMD2901} follows a hierarchical
-approach.
-
-\begin{itemize}
-\item First, each functionnal block is described as a separate gate net-list.
-There are five blocks : {\bf accu, alu, ram, muxe, muxout}.
-\item The next hierarchical level is the {\bf heart} 
-that interconnects these five blocks among each others.
-\item The final hierarchical level is the {\bf chip}
-that connects the {\bf heart} to the {\bf pads}.
-\end {itemize}
-
-The {\bf chip.c} file uses the {\bf genlib} language to describe
-these 7 hierarchical blocs.
-
-The {\bf ALLIANCE} system accepts several external file formats for net-list
-(EDIF, VHDL, SPICE, ALLIANCE, VLSI).
-Environment variables allow to set the formats.
-The {\bf .vst} extension corresponds to the structural {\bf VHDL}.\\
-\\
-\fbox{
-\shortstack[l]{
-{\bf $>$ MBK\_IN\_LO=vst}\\
-{\bf $>$ MBK\_OUT\_LO=vst} \\
-{\bf $>$ export MBK\_OUT\_LO MBK\_IN\_LO} 
-}}
-
-All net-list files created and used by {\bf genlib} will now
-be structural {\bf VHDL}.\\
-\\
-\fbox{
-\shortstack[l]{
-{\bf [ $>$ MBK\_IN\_LO=vst ]}\\
-{\bf [ $>$ MBK\_OUT\_LO=vst ]}\\
-{\bf [ $>$ MBK\_WORK\_LIB=. ]}\\
-{\bf [ $>$ MBK\_CATA\_LIB=.:/\$ALLIANCE\_TOP/cells/sclib/prol10:/\$ALLIANCE\_TOP/cells/ring/padsymb]}\\
-{\bf [ $>$ export MBK\_CATA\_LIB MBK\_IN\_LO MBK\_OUT\_LO MBK\_WORK\_LIB]}\\
-{\bf $>$ genlib -v  chip}
-}}
-
-The 7 files {\bf alu.vst accu.vst ram.vst muxe.vst muxout.vst 
-heart.vst chip.vst} have been created.
-
-\subsection{Structural Model Simulation}
-
-The various net-list files we have created represent the structural 
-description that should be validated by simulation, using the same patterns as in step 1.\\
-\\
-\fbox{
-\shortstack[l]{
-{\bf [ $>$ MBK\_IN\_LO=vst ]}\\
-{\bf [ $>$ VH\_PATSFX=pat ]}\\
-{\bf [ $>$ VH\_MAXERR=10 ]}\\
-{\bf [ $>$ MBK\_WORK\_LIB=. ]}\\
-{\bf [ $>$ MBK\_CATA\_LIB=.:/\$ALLIANCE\_TOP/cells/sclib/prol10:/\$ALLIANCE\_TOP/cells/ring/padsymb]}\\
-{\bf [ $>$ export MBK\_CATA\_LIB MBK\_IN\_LO VH\_PATSFX}\\
-\hspace*{0.3 in}\bf VH\_MAXERR MBK\_WORK\_LIB ]\\
-{\bf $>$ asimut chip pattern result\_str}
-}
-}
-
-\begin{itemize}
-\item {\bf chip} is the structural input file ({\bf chip.vst}).
-\item {\bf pattern} : is the filename for the input patterns ({\bf pattern.pat}).
-\item {\bf result\_str} : is filename for the resulting patterns
-({\bf result\_str.pat}).
-\end{itemize}
-
-Note the {\bf -b} option does not appear any more, since we now have a 
-structural model.
-
-Any new error appearing will be reported in the {\bf result\_str.pat} file.
-You can try to introduce a schematic error by modifying the {\bf chip.c} file,
-running {\bf genlib} and {\bf asimut} to see the errors.
-\section{Physical Design}
-
-Building the heart, and routing the heart to the pads are quite different jobs.
-So we use different tools.
-
-\subsection{Routing the heart}
-
-{\bf Scr} is a standard cell placing and routing tool.
-
-Here again {\bf ALLIANCE} accepts several external file formats
-for the symbolic layout.
-Environment variables allow to set the formats.\\
-\\
-\fbox{
-\shortstack[l]{
-{\bf $>$ MBK\_IN\_PH=ap}\\
-{\bf $>$ MBK\_OUT\_PH=ap}\\
-{\bf [ $>$ export  MBK\_IN\_PH MBK\_OUT\_PH }
-}
-}
-\\
-The hierarchical net-list will be flattenned before routing.\\
-\\
-\fbox{
-\shortstack[l]{
-{\bf [ $>$ MBK\_IN\_PH=ap ]}\\
-{\bf [ $>$ MBK\_OUT\_PH=ap ]}\\
-{\bf [ $>$ MBK\_IN\_LO=vst ]}\\
-{\bf [ $>$ MBK\_WORK\_LIB=. ]}\\
-{\bf [ $>$ MBK\_CATA\_LIB=.:/\$ALLIANCE\_TOP/cells/sclib/prol10:/\$ALLIANCE\_TOP/cells/ring/padsymb]}\\
-{\bf [ $>$ export MBK\_CATA\_LIB MBK\_IN\_PH  MBK\_OUT\_PH}\\
-\hspace*{0.3 in}\bf MBK\_IN\_LO MBK\_WORK\_LIB]\\
-{\bf $>$ scr -p -r heart} 
-}}
-\begin{itemize}
-\item {\bf heart}     is the input net-list (heart.vst ) and  the connector placement (heart.scr). The output layout will be heart.ap.
-\item {\bf -p}        automatic placement.
-\item {\bf -r}        routing required.
-
-\end{itemize}
-The symbolic layout file {\bf heart.ap} has been created.
-
-\subsection{Heart verification}
-
-\begin{itemize}
-\item {DRC} : Druc checks the symbolic layout rules
-(see {\it man druc})\\
-\\
-\fbox{
-\shortstack[l]{
-{\bf [ $>$ MBK\_IN\_PH=ap ]}\\
-{\bf [ $>$ MBK\_WORK\_LIB=. ]}\\
-{\bf [ $>$ MBK\_CATA\_LIB=.:/\$ALLIANCE\_TOP/cells/sclib/prol10:/\$ALLIANCE\_TOP/cells/ring/padsymb]}\\
-{\bf  $>$ RDS\_TECHNO\_NAME=\$ALLIANCE\_TOP/etc/cmos\_7.rds }\\
-{\bf  $>$ RDS\_IN=cif }\\
-{\bf  $>$ RDS\_OUT=cif }\\
-{\bf [ $>$ export MBK\_CATA\_LIB MBK\_IN\_PH MBK\_WORK\_LIB}\\
-\hspace*{0.3 in}\bf RDS\_TECHNO\_NAME RDS\_IN RDS\_OUT]\\
-{\bf $>$ druc heart} 
-}}\\
-\\
-If necessary, {\bf druc} generates an error file ({\bf core.err}).
-
-\item {Net-list extraction}.
-
-{\bf Lynx} is a hierarchical extractor that provides a gate net-list.\\
-In order to avoid name collision, we use another file format
-for extracted net-list ({\bf .al} format). This new format is used
-to support additional data : extracted parasitic capacitances.\\
-\\
-\fbox{
-\shortstack[l]{
-{\bf $>$ MBK\_OUT\_LO=al}\\
-{\bf $>$ export MBK\_OUT\_LO}
-}}\\
-\
-Then we run the {\bf lynx extractor} :\\
-\\
-\fbox{
-\shortstack[l]{
-{\bf [ $>$ MBK\_OUT\_LO=al ]}\\
-{\bf [ $>$ MBK\_IN\_PH=ap ]}\\
-{\bf [ $>$ MBK\_WORK\_LIB=. ]}\\
-{\bf [ $>$ MBK\_CATA\_LIB=.:/\$ALLIANCE\_TOP/cells/sclib/prol10:/\$ALLIANCE\_TOP/cells/ring/padsymb]}\\
-{\bf [ $>$ export MBK\_CATA\_LIB MBK\_OUT\_LO MBK\_IN\_PH MBK\_WORK\_LIB]}\\
-{\bf $>$ lynx heart}
-}}\\
-\\
-The extracted net-list file {\bf heart.al} is created at this level.
-\item {Net-compare}.
-
-The next tool is the net-compare {\bf lvx} that performs a netlist comparison 
-between the input net-list {\bf heart.vst} and the extracted net-list
-{\bf heart.al}, after flattening to the gate level.\\
-\\
-\fbox{
-\shortstack[l]{
-{\bf [ $>$ MBK\_WORK\_LIB=. ]}\\
-{\bf [ $>$ MBK\_CATA\_LIB=.:/\$ALLIANCE\_TOP/cells/sclib/prol10:/\$ALLIANCE\_TOP/cells/ring/padsymb]}\\
-{\bf [ $>$ export MBK\_CATA\_LIB MBK\_WORK\_LIB]}\\
-{\bf $>$ lvx vst al heart heart -f}
-}}
-
-\end{itemize}
-
-\subsection{Routing the chip}
-
-The pad placement depends on external constraints.
-The file {\bf chip.rin} defines the pads placement constraints
-(see {\it man ring}).\\
-\\
-\fbox{
-\shortstack[l]{
-{\bf [ $>$ MBK\_IN\_LO=vst ]}\\
-{\bf [ $>$ MBK\_IN\_PH=ap ]}\\
-{\bf [ $>$ MBK\_OUT\_PH=ap ]}\\
-{\bf [ $>$ MBK\_WORK\_LIB=. ]}\\
-{\bf [ $>$ MBK\_CATA\_LIB=.:/\$ALLIANCE\_TOP/cells/sclib/prol10:/\$ALLIANCE\_TOP/cells/ring/padsymb]}\\
-{\bf [ $>$ export MBK\_CATA\_LIB MBK\_IN\_LO}\\
-\hspace*{0.3 in}\bf MBK\_IN\_PH MBK\_OUT\_PH MBK\_WORK\_LIB]\\
-{\bf $>$ ring chip chip}
-}}
-\begin{itemize}
-\item {\bf chip} The input files chip.vst and chip.rin (the same name
-{\bf chip} must be used for the two files).
-\item {\bf chip} The output physical file chip.ap.
-\end{itemize}
-
-The symbolic layout file {\bf chip.ap} has been created.
-At this point, you can display the chip with the layout editor {\bf graal}.\\
-You can see the chip and the instantiated heart, using the {\bf graal} commands to
-go through the hierarchy levels.\\
-\\
-\fbox{
-\shortstack[l]{
-{\bf [ $>$ MBK\_WORK\_LIB=. ]}\\
-{\bf [ $>$ MBK\_CATA\_LIB=.:/\$ALLIANCE\_TOP/cells/sclib/prol10:/\$ALLIANCE\_TOP/cells/ring/padsymb]}\\
-{\bf [ $>$ export MBK\_CATA\_LIB MBK\_WORK\_LIB]}\\
-{\bf $>$ graal}
-}}
-
-\section{Physical Validation}
-
-The {\bf ALLIANCE} verification tools allow both flat and hierarchical
-verification. We will use a hierarchical approach.
-
-\subsection{Chip verification}
-
-The same procedure used for the heart applies for the entire chip.\\
-\\
-\fbox{
-\shortstack[l]{
-{\bf [ $>$ MBK\_IN\_PH=ap ]}\\
-{\bf [ $>$ MBK\_WORK\_LIB=. ]}\\
-{\bf [ $>$ MBK\_CATA\_LIB=.:/\$ALLIANCE\_TOP/cells/sclib/prol10:/\$ALLIANCE\_TOP/cells/ring/padsymb]}\\
-{\bf [ $>$ RDS\_TECHNO\_NAME=\$ALLIANCE\_TOP/etc/cmos\_7.rds]}\\
-{\bf [ $>$ RDS\_IN=cif]}\\
-{\bf [ $>$ RDS\_OUT=cif] }\\
-{\bf [ $>$ export MBK\_CATA\_LIB MBK\_IN\_PH MBK\_WORK\_LIB}\\
-\hspace*{0.3 in}\bf RDS\_TECHNO\_NAME RDS\_IN RDS\_OUT]\\
-{\bf $>$ druc chip}
-}}\\
-\\
-Eventually, {\bf druc} generates an error file ({\bf chip.err}).\\
-\\
-\fbox{
-\shortstack[l]{
-{\bf [ $>$ MBK\_OUT\_LO=al ]}\\
-{\bf [ $>$ MBK\_IN\_PH=ap ]}\\
-{\bf [ $>$ MBK\_WORK\_LIB=. ]}\\
-{\bf [ $>$ export MBK\_CATA\_LIB MBK\_OUT\_LO MBK\_IN\_PH]}\\
-{\bf $>$ lynx chip}
-}}\\
-\\
-The extracted net-list file {\bf chip.al} is created by this step
-(This net-list instantiates the heart).\\
-\\
-\fbox{
-\shortstack[l]{
-{\bf [ $>$ MBK\_WORK\_LIB=. ]}\\
-{\bf [ $>$ MBK\_CATA\_LIB=.:/\$ALLIANCE\_TOP/cells/sclib/prol10:/\$ALLIANCE\_TOP/cells/ring/padsymb]}\\
-{\bf [ $>$ export MBK\_CATA\_LIB MBK\_WORK\_LIB]}\\
-{\bf $>$ lvx vst al chip chip}
-}}\\
-\\
-Both net-lists {\bf chip.vst} and {\bf chip.al} are flattened to the gate level
-by {\bf lvx} before comparison (see {\it man catal}).
-
-\subsection{Chip simulation}
-
-Finally you can check globally the extracted net-list
-by applying the original patterns to the extracted net-list.
-Thanks to the multiformat approach the simulator {\bf asimut}
-accepts {\bf .al} format as structural input description.\\
-\\
-\fbox{
-\shortstack[l]{
-{\bf $>$ MBK\_IN\_LO=al}\\
-{\bf $>$ export MBK\_IN\_LO}
-}}\\
-\\
-Then you have to run {\bf asimut}.\\
-\\
-\fbox{
-\shortstack[l]{
-{\bf [ $>$ MBK\_IN\_LO=al]}\\
-{\bf [ $>$ VH\_PATSFX=pat]}\\
-{\bf [ $>$ VH\_MAXERR=10]}\\
-{\bf [ $>$ MBK\_WORK\_LIB=. ]}\\
-{\bf [ $>$ MBK\_CATA\_LIB=.:/\$ALLIANCE\_TOP/cells/sclib/prol10:/\$ALLIANCE\_TOP/cells/ring/padsymb]}\\
-{\bf [ $>$ export MBK\_CATA\_LIB MBK\_IN\_LO}\\
-\hspace*{0.3 in}\bf VH\_PATSFX VH\_MAXERR  MBK\_WORK\_LIB]\\
-{\bf $>$ asimut chip pattern res\_pattern}
-}}\\
-\\
-To complete the validation of our chip, the functional abstraction followed
-by the proof must be done.
-
-\subsection{Functionnal abstraction and formal proof}
-
-The functional abstraction of the transitor net-list is realized by the tool
-{\bf yagle} (see {\it man yagle}). {\bf yagle} flattens the chip ({\bf chip.al})
-to obtain a transistor level description, and abstract then a behavioral description ({\bf chip.vbe}).
-To keep the coherence of register names between the behavioral description
-given by {\bf yagle} ({\bf chip.vbe}) and the initial behavioral description
-({\bf amd.vbe}), a file describing the name's transformation is required.
-This file is {\bf chip.inf}.\\
-\\
-\fbox{
-\shortstack[l]{
-{\bf [ $>$ MBK\_IN\_LO=al ]}\\
-{\bf [ $>$ MBK\_WORK\_LIB=. ]}\\
-{\bf [ $>$ MBK\_CATA\_LIB=.:/\$ALLIANCE\_TOP/cells/sclib/prol10:/\$ALLIANCE\_TOP/cells/ring/padsymb]}\\
-{\bf [ $>$ export MBK\_CATA\_LIB MBK\_IN\_LO MBK\_WORK\_LIB]}\\
-{\bf $>$ yagle chip -i -v}
-}}
-\begin{itemize}
-\item {\bf chip}	is the input layout ({\bf chip.al}).
-\item {\bf -i}		read the {\bf chip.inf} file.   
-\item {\bf -v}		to vectorize the interface of behavioral description.
-\end{itemize}
-
-The VHDL DATA FLOW description as been generated : {\bf chip.vbe}\\
-
-Now you have the abstracted behavioral description ({\bf chip.vbe})
-and the initial behavioral description ({\bf amd.vbe}).
-With {\bf proof} (see {\it man proof}), you can check the formal equivalence
-between the two descriptions.\\
-\\
-\fbox{
-\shortstack[l]{
-{\bf [ $>$ MBK\_WORK\_LIB=. ]}\\
-{\bf [ $>$ export MBK\_WORK\_LIB]}\\
-{\bf $>$ proof -d amd chip}
-}}
-\begin{itemize}
-\item {\bf chip}	is the abstracted file ({\bf chip.vbe}).
-\item {\bf amd}		is the initial behavioral description ({\bf amd.vbe}).
-\item {\bf -d}		displays errors.
-\end{itemize}
-
-If you want to see an error you can change one line in the file {\bf amd.vbe}.
-For example, change the line 301 :\\
- scout $<=$ NOT accu(3) AND test\_mode ;\\
-and try {\bf proof} again.
-
-\section{Timing analysis}
-With the extracted net list chip.al TAs analyses each path of the circuit taking account of the various capacitances. These results are summarize in a file .ttv In this file we can see the critical path and the correspnding time. So it is possible to know the period of the chip
-
-You will enter :\\
-\\
-\fbox{
-\shortstack[l]{
-{\bf [ $>$ MBK\_IN\_PH=ap ]}\\
-{\bf [ $>$ MBK\_IN\_LO=al ]}\\
-{\bf [ $>$ MBK\_WORK\_LIB=. ]}\\
-{\bf [ $>$ MBK\_CATA\_LIB=.:/\$ALLIANCE\_TOP/cells/sclib/prol10:/\$ALLIANCE\_TOP/cells/ring/padsymb]}\\
-{\bf [ $>$ export  MBK\_IN\_PH MBK\_WORK\_LIB MBK\_CATA\_LIB ]}\\
-{\bf $>$ tas chip }
-}}\\
-
-\section{Chip finishing}
-
-Until now we used symbolic layout (all coordinates in {\bf lambda}-units).
-We should now convert them to real dimensions, creating the physical layout
-(two output formats are supported : CIF and GDSII).
-This last step is done by {\bf s2r}.
-{\bf s2r} performs symbolic to real expansion, gap filling, denotching
-and instantiates preexisting physical cells 
-(this is necessary for the pads).
-
-You must define 3 new environment variables :\\
-\\
-\fbox{
-\shortstack[l]{
-{\bf $>$ RDS\_TECHNO\_NAME=/\$ALLIANCE\_TOP/etc/prol10.rds} \\
-{\bf $>$ export RDS\_TECHNO\_NAME}
-}}\\
-\\
-The {\bf prol10.rds} is the technology file that contains the parameters
-corresponding to the target process.
-(In this case the target process is 1 micron.)\\
-\\
-\fbox{
-\shortstack[l]{
-{\bf $>$ RDS\_OUT= cif}  \\
-{\bf $>$ export RDS\_OUT}
-}}\\
-\\
-Defines the output format.\\
-\\
-\fbox{
-\shortstack[l]{
-{\bf $>$ RDS\_IN=cif}\\
-{\bf $>$ export RDS\_IN}
-}}\\
-\\
-Defines the input format for the preexisting layout cells (pads).
-
-You will enter :\\
-\\
-\fbox{
-\shortstack[l]{
-{\bf [ $>$ MBK\_IN\_PH=ap ]}\\
-{\bf [ $>$ MBK\_WORK\_LIB=. ]}\\
-{\bf [ $>$ MBK\_CATA\_LIB=.:/\$ALLIANCE\_TOP/cells/sclib/prol10:/\$ALLIANCE\_TOP/cells/ring/padsymb]}\\
-{\bf [ $>$ RDS\_TECHNO\_NAME=/\$ALLIANCE\_TOP/etc/prol10.rds ]}\\
-{\bf [ $>$ RDS\_IN=cif ]}\\
-{\bf [ $>$ RDS\_OUT=cif]}\\
-{\bf [ $>$ export RDS\_OUT  MBK\_IN\_PH MBK\_WORK\_LIB}\\
-\hspace*{0.3 in}\bf MBK\_CATA\_LIB RDS\_TECHNO\_NAME RDS\_IN]\\
-{\bf $>$ s2r -c  chip amd2901}
-}}
-\begin{itemize}
-\item {\bf -c} deletes connectors at the highest level of hierarchy.
-\end{itemize}
-
-You did it...\\
-The file produced is {\bf amd2901.cif}.
-It is ready for the foundry.
-
-\end{document}
-
-
diff --git a/alliance/share/tutorials/dlxm/CATAL b/alliance/share/tutorials/dlxm/CATAL
deleted file mode 100644
index 0c01867e..00000000
--- a/alliance/share/tutorials/dlxm/CATAL
+++ /dev/null
@@ -1,22 +0,0 @@
-FpGen___________________                            C
-inv_32x32x0x1l_cl                                   C
-nmux2cs_32x32x0l_cl                                 C
-rfg1c0_32x32x0x32l_bk                               C
-buse_32x32x0l_cl                                    C
-pdfft_32x32x0l_cl                                   C
-nbuse_32x32x0l_cl                                   C
-adsb2f_32x32x0l_bk                                  C
-nul_32x32x0l_cl                                     C
-xor2_32x32x0x1l_cl                                  C
-nand2_32x32x0x1l_cl                                 C
-nor2_32x32x0x1l_cl                                  C
-mux2cs_32x32x0l_cl                                  C
-shift_32x32x0l_bk                                   C
-constffffffff_32x32x0l_cl                           C
-const00000000_32x32x0l_cl                           C
-const00000000_32x7x0l_cl                            C
-inv_32x20x12x1l_cl                                  C
-inv_32x2x20x3l_cl                                   C
-inv_32x24x8x1l_cl                                   C
-nmux2cs_32x16x8l_cl                                 C
-nmux2cs_32x8x12l_cl                                 C
diff --git a/alliance/share/tutorials/dlxm/CATAL_CPU_BLOCKS b/alliance/share/tutorials/dlxm/CATAL_CPU_BLOCKS
deleted file mode 100644
index 4c47efdc..00000000
--- a/alliance/share/tutorials/dlxm/CATAL_CPU_BLOCKS
+++ /dev/null
@@ -1,8 +0,0 @@
-romu C
-roms C
-sr64_1a C
-timer C
-dlxm_dec C
-dlxm_dpt C
-dlxm_seq C
-dlxm_sts C
diff --git a/alliance/share/tutorials/dlxm/CATAL_CPU_CHIP b/alliance/share/tutorials/dlxm/CATAL_CPU_CHIP
deleted file mode 100644
index d8cd43ba..00000000
--- a/alliance/share/tutorials/dlxm/CATAL_CPU_CHIP
+++ /dev/null
@@ -1,6 +0,0 @@
-dlxm_dec C
-romu C
-roms C
-sr64_1a C
-timer C
-dlxm_chip C
diff --git a/alliance/share/tutorials/dlxm/CATAL_CPU_GATES b/alliance/share/tutorials/dlxm/CATAL_CPU_GATES
deleted file mode 100644
index 26a8f6fd..00000000
--- a/alliance/share/tutorials/dlxm/CATAL_CPU_GATES
+++ /dev/null
@@ -1,5 +0,0 @@
-romu C
-roms C
-sr64_1a C
-timer C
-dlxm_dec C
diff --git a/alliance/share/tutorials/dlxm/Makefile b/alliance/share/tutorials/dlxm/Makefile
deleted file mode 100644
index dfdb5704..00000000
--- a/alliance/share/tutorials/dlxm/Makefile
+++ /dev/null
@@ -1,822 +0,0 @@
-############################
-#
-# makefile parameters
-#
-############################
-
-SHELL      = /bin/sh
-TOUCH      = touch
-
-############################
-#
-# Executable files ( Alliance Tools )
-#
-############################
-
-ASM        = $(ALLIANCE_TOP)/bin/dlx_asm_v0_2
-ASIMUT     = $(ALLIANCE_TOP)/bin/asimut
-SYF        = $(ALLIANCE_TOP)/bin/syf
-BOP        = $(ALLIANCE_TOP)/bin/bop
-SCMAP      = $(ALLIANCE_TOP)/bin/scmap
-PROOF      = $(ALLIANCE_TOP)/bin/proof
-# GLOP       = $(ALLIANCE_TOP)/bin/glop
-GLOP       = echo
-FPGEN      = $(ALLIANCE_TOP)/bin/fpgen
-GENLIB     = $(ALLIANCE_TOP)/bin/genlib
-SCR_EXE    = $(ALLIANCE_TOP)/bin/scr
-LYNX       = $(ALLIANCE_TOP)/bin/lynx
-DRUC       = $(ALLIANCE_TOP)/bin/druc
-LVX        = $(ALLIANCE_TOP)/bin/lvx
-DPR        = $(ALLIANCE_TOP)/bin/dpr
-BBR        = $(ALLIANCE_TOP)/bin/bbr
-RING_EXE   = $(ALLIANCE_TOP)/bin/ring
-S2R        = $(ALLIANCE_TOP)/bin/s2r
-
-XFSM = echo
-# XFSM       = $(ALLIANCE_TOP)/bin/xfsm
-XPAT = echo
-# XPAT       = $(ALLIANCE_TOP)/bin/xpat
-GRAAL = echo
-# GRAAL      = $(ALLIANCE_TOP)/bin/graal
-DREAL = echo
-# DREAL      = $(ALLIANCE_TOP)/bin/dreal
-
-############################
-#
-# Cells directories
-#
-#       scr  : Standard cells
-#      ring  : Pads cells
-#   fitpath  : Datapath cells
-#       rsa  : Recurence Solver Adder cells
-#       rfg  : Register File Generator cells
-#       bsg  : Barrel Shifter Generator cells
-#
-############################
-
-CELLS      = $(ALLIANCE_TOP)/cells
-
-SCR        = $(CELLS)/sxlib
-RING       = $(CELLS)/padlib
-FPLIB      = $(CELLS)/fplib
-RSA        = $(CELLS)/rsa
-RFG        = $(CELLS)/rfg
-BSG        = $(CELLS)/bsg
-
-ALL        = $(SCR):$(RING):$(FPLIB):$(RSA):$(RFG):$(BSG)
-
-############################
-#
-# Environments Variables
-#
-############################
-
-# Set the logical environment to VST
-ENV_VST      = MBK_IN_LO=vst;              export MBK_IN_LO;             \
-               MBK_OUT_LO=vst;             export MBK_OUT_LO;            \
-               MBK_WORK_LIB=.;             export MBK_WORK_LIB
-
-# Set the logical environment to AL
-ENV_AL       = MBK_IN_LO=al;               export MBK_IN_LO;             \
-               MBK_OUT_LO=al;              export MBK_OUT_LO;            \
-               MBK_WORK_LIB=.;             export MBK_WORK_LIB
-
-# Set the physical environment to AP
-ENV_AP       = MBK_IN_PH=ap;               export MBK_IN_PH;             \
-               MBK_OUT_PH=ap;              export MBK_OUT_PH;            \
-               MBK_WORK_LIB=.;             export MBK_WORK_LIB
-
-# Set the asimut environment
-ENV_VH       = VH_BEHSFX=vbe;              export VH_BEHSFX;             \
-               VH_MAXERR="10";             export VH_MAXERR;             \
-               VH_PATSFX=pat;              export VH_PATSFX
-
-# Set the Synthese Logique environment
-ENV_SL       = MBK_TARGET_LIB=$(SCR);       export MBK_TARGET_LIB;       \
-               MBK_VDD=vdd;                 export MBK_VDD;              \
-               MBK_VSS=vss;                 export MBK_VSS
-
-# Set the Rectangle Data Structure environment
-ENV_REAL     = RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/prol10_11.rds; \
-               export RDS_TECHNO_NAME
-
-ENV_SYMB     = RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/cmos_11.rds; \
-               export RDS_TECHNO_NAME
-
-ENV_RDS      = RDS_IN=cif;                 export RDS_IN; \
-               RDS_OUT=cif;                export RDS_OUT; \
-               MBK_WORK_LIB=.;             export MBK_WORK_LIB
-
-############################
-#
-# Input of Makefile
-#
-# When you just call "make", display the availables Makefile entries
-#
-############################
-
-############################
-#
-# When you call "make help", display the availables Makefile entries
-#
-############################
-
-help         :
-	@echo " "
-	@echo "          Alliance CAD System 3.0,        dlxm_make"
-	@echo "          Copyright (c) 94, MASI, CAO-VLSI Team"
-	@echo "		 URA CNRS 818 - University Pierre et Marie Curie - "
-	@echo "		 Institut Blaise Pascal "
-	@echo "          E-mail support:      cao-vlsi@masi.ibp.fr"
-
-	@echo " "
-	@echo " How to make all the dlxm with a minimal simulation subset:"
-	@echo " "
-	@echo "                   all     : Make all the dlxm"
-	@echo " "
-	@echo " this step can be done in 4 separate steps :"
-	@echo " "
-	@echo "       1    functional     : Dlxm behavioral model validation"
-	@echo "       2    structural     : Logical synthesis and validation"
-	@echo "       3      physical     : Layout generation and validation"
-	@echo " "
-	@echo " this step can be done in 4 separate steps :"
-	@echo " "
-	@echo "         3.1   ctl_routing : Routing the control"
-	@echo "         3.2   dpt_routing : Routing the data-path"
-	@echo "         3.3  core_routing : Routing the core"
-	@echo "         3.4  dlxm_routing : Routing the dlxm"
-	@echo " "
-	@echo "       4          real     : real layout file generation"
-	@echo " "
-	@echo "                 clean     : Clean the directory"
-	@echo " "
-
-############################
-#
-# When you call "make clean", the directory is cleanup
-#
-############################
-
-clean        : clean_sim      \
-               clean_struct   \
-               clean_layout   \
-               clean_real
-
-clean_sim       :
-	rm -f add000_chip_pat
-	rm -f add000_blocks_pat
-	rm -f add000_gates_pat
-	rm -f dlxm_scan_res_pat
-	rm -f add000_chip.pat
-	rm -f add000_blocks.pat
-	rm -f add000_gates.pat
-	rm -f dlxm_scan_res.pat
-	rm -f romu.vbe
-	rm -f roms.vbe
-
-clean_struct     :
-	rm -f dlxm_seq.vbe
-	rm -f dlxm_seqo.vbe
-	rm -f dlxm_seqo_vbe
-	rm -f dlxm_seq.cod
-	rm -f dlxm_seq.vst
-	rm -f dlxm_stso.vbe 
-	rm -f dlxm_stso_vbe 
-	rm -f dlxm_sts.vst 
-	rm -f dlxm_ctl.vst
-	rm -f dlxm_dpt.vst
-	rm -f ./mclib/*_32x*.vst
-	rm -f ./mclib/*_32x*.vbe
-
-clean_layout  :
-	rm -f *.ap
-	rm -f ./mclib/*.ap
-	rm -f ./mclib/CATAL
-	rm -f *.al
-	rm -f lvx_result_*
-	rm -f *.drc
-	rm -f drc_result_*
-
-clean_real      :
-	rm -f *.cif
-
-############################
-#
-# the option to make all the dlxm
-#
-############################
-
-all          : functional    \
-               structural    \
-               physical      \
-               real
-
-############################
-#
-# the option to validate the dlxm functional description
-#
-############################
-
-functional     : dlxm_chip_sim
-
-############################
-#
-# the option to validate the dlxm structural description
-#
-############################
-
-structural   : dlxm_blocks_sim   \
-               dlxm_gates_sim    \
-               dlxm_scan_sim
-
-############################
-#
-# the option to validate the dlxm physical description
-#
-############################
-
-physical     : dlxm_routing
-
-############################
-#
-# the option to make the ready to foundry dlxm file
-#
-############################
-
-real         : dlxm_real
-
-##########################################################################
-#
-#
-# Functional part :
-#
-#   - Simulate with dlxm.vbe =>
-#
-#      1) Validation of dlxm_chip.vbe
-#
-#      2) Validation of asm files
-#
-##########################################################################
-
-dlxm_chip_sim     : add000_chip_pat 
-
-#####################################
-#
-# Simulation using user rom and supervisor rom
-#
-#    - Assign the environments variables
-#    - Generate romu.vbe
-#    - Generate roms.vbe
-#    - Simulate
-#
-#
-#####################################
-
-add000_chip_pat    : add000.u add000.s dlxm_chip.vbe
-	MBK_CATA_LIB=.;                export MBK_CATA_LIB;                 \
-	MBK_CATAL_NAME=CATAL_CPU_CHIP;  export MBK_CATAL_NAME;               \
-	$(ENV_VST);                                                          \
-	$(ENV_VH);                                                           \
-	$(ASM) add000.u romu ;                                          \
-	$(ASM) add000.s roms ;                                          \
-	$(ASIMUT) -l 1 -p 50 -i 0 -zd -bdd dlxm_cpu dlxm_cpu add000_chip
-	touch add000_chip_pat
-
-##########################################################################
-#
-#
-# structural part :
-#
-#    - Generation of the core structural description
-#
-#    - Generation of the sequencer behavioral description
-#
-#    - Simulation of the dlxm with blocks
-#
-#    - Generation of the corresponding  netlists
-#
-#    - Simulation of the dlxm with gate leaf cells
-#
-#    - Simulation of the dlxm with scan-path 
-#
-##########################################################################
-
-####################################
-#
-#
-####################################
-
-
-####################################
-#
-# Creating dlxm_seq.vbe from dlxm_seq.fsm ( with syf )
-#
-#   - Generation of dlxm_seq.vbe
-#
-####################################
-
-dlxm_seq.vbe : dlxm_seq.fsm
-	$(XFSM) -l dlxm_seq
-	MBK_WORK_LIB=.;             export MBK_WORK_LIB ;   \
-	$(SYF) -a -E -P dlxm_seq dlxm_seq
-
-####################################
-# Simulation of the dlxm described with pads and core in 2 blocks
-# data path and control, 
-# with control described in 2 blocks : status and sequencer.
-# dlxm_sts.vbe dlxm_seq.vbe dlxm_dpt.vbe
-####################################
-
-dlxm_blocks_sim      : add000_blocks_pat 			
-
-#####################################
-#
-#    - Assign the environments variables
-#    - Generate romu.vbe
-#    - Generate roms.vbe
-# Creating dlxm_ctl.vst from dlxm_ctl.vst.h
-#    - Simulate
-#
-#
-#####################################
-
-add000_blocks_pat    : add000.u add000.s                    \
-                       dlxm_sts.vbe                         \
-                       dlxm_seq.vbe                         \
-                       dlxm_dpt.vbe                         \
-                       dlxm_ctl.vst.h                         \
-                       dlxm_core.vst                        \
-                       dlxm_chip.vst
-	MBK_CATA_LIB=$(RING);                      export MBK_CATA_LIB;  \
-	MBK_CATAL_NAME=CATAL_CPU_BLOCKS;             export MBK_CATAL_NAME;  \
-	$(ENV_VST);                                                          \
-	$(ENV_VH);                                                           \
-	$(ASM) add000.u romu ;                                                \
-	$(ASM) add000.s roms ;                                                \
-	cp dlxm_ctl.vst.h dlxm_ctl.vst;                        \
-	chmod 644 dlxm_ctl.vst;					\
-	$(ASIMUT) -l 1 -p 50 -i 0 -zd -bdd dlxm_cpu dlxm_cpu add000_blocks
-	touch add000_blocks_pat
-	$(XPAT) -l add000_blocks.pat
-
-####################################
-#
-# Creating dlxm_sts.vst from dlxm_sts.vbe ( with logic )
-#
-#    - Generation of dlxm_stso.vbe
-#
-#    - Generation of dlxm_sts.vst
-#
-####################################
-
-dlxm_sts.vst : dlxm_stso_vbe
-	@ $(ENV_VST);                                                        \
-	$(ENV_SL);                                                           \
-	MBK_CATA_LIB=$(SCR);    export MBK_CATA_LIB;                         \
-	$(SCMAP) dlxm_stso dlxm_sts
-
-dlxm_stso_vbe : dlxm_sts.vbe
-	@ $(ENV_VST);                                                        \
-	$(ENV_SL);                                                           \
-	MBK_CATA_LIB=$(SCR);    export MBK_CATA_LIB;                         \
-	$(BOP) -o dlxm_sts dlxm_stso
-	$(PROOF) dlxm_sts dlxm_stso
-	$(TOUCH) dlxm_stso_vbe
-
-####################################
-#
-# Creating dlxm_seq.vst from dlxm_seq.vbe ( with logic )
-#
-#    - Generation of dlxm_seqo.vbe
-#
-#    - Generation of dlxm_seq.vst
-#
-####################################
-
-dlxm_seq.vst : dlxm_seqo_vbe
-	$(ENV_VST);                                                        \
-	$(ENV_SL);                                                           \
-	MBK_CATA_LIB=$(SCR);    export MBK_CATA_LIB;                         \
-	$(SCMAP) dlxm_seqo dlxm_seq
-
-dlxm_seqo_vbe : dlxm_seq.vbe
-	$(ENV_VST);                                                        \
-	$(ENV_SL);                                                           \
-	MBK_CATA_LIB=$(SCR);    export MBK_CATA_LIB;                         \
-	$(BOP) -o dlxm_seq dlxm_seqo
-	$(PROOF) dlxm_seq dlxm_seqo
-	$(TOUCH) dlxm_seqo_vbe
-
-
-#####################################
-#
-# Restructurate control
-#
-#   - Call netoptim on control
-#
-#####################################
-
-dlxm_ctl.vst : dlxm_seq.vst             \
-               dlxm_sts.vst             
-	$(ENV_VST);                                                    \
-	MBK_VDD=vdd;           export MBK_VDD;                           \
-	MBK_VSS=vss;           export MBK_VSS;                           \
-	MBK_CATA_LIB=$(SCR);   export MBK_CATA_LIB;                      \
-	$(GLOP) -g dlxm_ctl dlxm_ctl 
-
-####################################
-#
-# Creating dlxm_dpt.vst from dlxm_dpt.c ( with fpgen )
-#
-#    - Using a subdirectory mclib to store the generated operators
-#
-#    - Generation of dlxm_dpt.vst
-#
-####################################
-
-dlxm_dpt.vst : dlxm_dpt.c
-	@MBK_CATA_LIB=./mclib:$(ALL);       export MBK_CATA_LIB;            \
-	$(ENV_VST);                                                          \
-	$(ENV_AP);                                                           \
-	FPGEN_LIB=./mclib; export FPGEN_LIB;				\
-	$(FPGEN) -v dlxm_dpt
-
-####################################
-# Simulation of dlxm_sts.vst dlxm_seq.vst dlxm_dpt.vst
-####################################
-
-dlxm_gates_sim      : add000_gates_pat 
-
-#####################################
-#
-# Always the same method :
-#
-#    - Assign the environments variables
-#    - Generate romu.vbe
-#    - Generate roms.vbe
-#    - Simulate
-#
-#
-#####################################
-
-add000_gates_pat    : add000.u  add000.s                \
-                      dlxm_core.vst                     \
-                      dlxm_chip.vst                     \
-                      dlxm_ctl.vst                      \
-                      dlxm_seq.vst                      \
-                      dlxm_sts.vst                      \
-                      dlxm_dpt.vst
-	MBK_CATA_LIB=./mclib:$(ALL);    export MBK_CATA_LIB;     \
-	MBK_CATAL_NAME=CATAL_CPU_GATES;    export MBK_CATAL_NAME;   \
-	$(ENV_VST);                                                 \
-	$(ENV_VH);                                                  \
-	$(ASM) add000.u romu ;                                 \
-	$(ASM) add000.s roms ;                                 \
-	$(ASIMUT) -l 1 -p 50 -i 0 -zd -bdd dlxm_cpu dlxm_cpu add000_gates
-	touch add000_gates_pat
-
-##########################################################################
-#
-# Validation of the scan-path
-#
-#         Simulate ( ASIMUT )
-#
-##########################################################################
-
-dlxm_scan_sim : dlxm_scan_res_pat
-
-####################################
-#
-# Simulate for testing scan-path
-#
-#    - Call ASIMUT
-#
-####################################
-
-dlxm_scan_res_pat : dlxm_scan.pat                     \
-                    add000.u add000.s                 \
-                    dlxm_ctl.vst                          \
-                    dlxm_core.vst                          \
-                    dlxm_chip.vst                          \
-                    dlxm_sts.vst                      \
-                    dlxm_seq.vst                      \
-                    dlxm_dpt.vst
-	MBK_CATA_LIB=./mclib:$(ALL);             export MBK_CATA_LIB;   \
-	MBK_CATAL_NAME=CATAL_CPU_GATES;    export MBK_CATAL_NAME;   \
-	$(ENV_VST);                                                 \
-	$(ENV_VH);                                                  \
-	$(ASM) add000.u romu ;                                 \
-	$(ASM) add000.s roms ;                                 \
-	$(ASIMUT) -l 10 -p 50 -zd -bdd dlxm_cpu dlxm_scan dlxm_scan_res
-	touch dlxm_scan_res_pat
-
-##########################################################################
-#
-# Physical part :
-#
-#    - Route control
-#
-#    - Route datapath
-#
-#    - Route core
-#
-#    - Route chip
-#
-##########################################################################
-
-#####################################
-#
-# How to make control
-#
-#   - Call the router SCR
-#
-#   - Extract the netlist from layout ( LYNX )
-#
-#   - Compare the netlist ( LVX )
-#
-#####################################
-
-ctl_routing : lvx_result_ctl
-
-#####################################
-#
-# Routing control
-#
-#    - Call SCR
-#
-#####################################
-
-dlxm_ctl.ap : dlxm_ctl.vst dlxm_ctl.scr
-	@ MBK_CATA_LIB=$(SCR);   export MBK_CATA_LIB;                        \
-	MBK_VDD=vdd;           export MBK_VDD;                               \
-	MBK_VSS=vss;           export MBK_VSS;                               \
-	$(ENV_VST);                                                          \
-	$(ENV_AP);                                                           \
-	$(SCR_EXE) -p -r -i 3000 -l 5 -a 5 dlxm_ctl; \
-	$(ENV_RDS);  $(ENV_SYMB); \
-	$(GRAAL) -l dlxm_ctl
-
-#####################################
-#
-# Extracting control
-#
-#    - Call LYNX
-#
-#####################################
-
-dlxm_ctl.al : dlxm_ctl.ap
-	@ MBK_CATA_LIB=$(SCR);   export MBK_CATA_LIB;                        \
-	$(ENV_AL);                                                           \
-	$(ENV_AP);                                                           \
-	$(ENV_RDS);  $(ENV_SYMB); \
-	$(LYNX) -v dlxm_ctl dlxm_ctl
-
-#####################################
-#
-# Netlist comparison
-#
-#    - Call LVX
-#
-#   - Create a file for makefile dependances
-#
-#####################################
-
-lvx_result_ctl : dlxm_ctl.al
-	@ MBK_CATA_LIB=$(SCR);   export MBK_CATA_LIB;                          \
-	$(LVX) vst al dlxm_ctl dlxm_ctl -f
-	touch lvx_result_ctl
-
-#####################################
-#
-# How to make data-path
-#
-#   - Call DPR
-#
-#   - Extract the netlist from layout ( LYNX )
-#
-#   - Compare the netlist ( LVX )
-#
-#####################################
-
-dpt_routing : lvx_result_dpt
-
-#####################################
-#
-# Routing data-path
-#
-#   - Call DPR
-#
-#####################################
-
-dlxm_dpt.ap : dlxm_dpt.vst dlxm_dpt.dpr
-	@ MBK_CATA_LIB=./mclib:$(ALL);     export MBK_CATA_LIB;             \
-	$(ENV_VST);                                                          \
-	$(ENV_AP);                                                           \
-	$(DPR) -o -p -r dlxm_dpt dlxm_dpt
-
-#####################################
-#
-# Extracting data-path
-#
-#   - Call LYNX
-#
-#####################################
-
-dlxm_dpt.al : dlxm_dpt.ap
-	@ MBK_CATA_LIB=./mclib:$(ALL);               export MBK_CATA_LIB;    \
-	$(ENV_AL);                                                           \
-	$(ENV_AP);                                                           \
-	$(ENV_RDS);  $(ENV_SYMB); \
-	$(LYNX) -v dlxm_dpt dlxm_dpt
-
-#####################################
-#
-# Netlist comparison
-#
-#   - Call LVX
-#
-#   - Create a file for makefile dependances
-#
-#####################################
-
-lvx_result_dpt : dlxm_dpt.al
-	@ MBK_CATA_LIB=./mclib:$(ALL);               export MBK_CATA_LIB;   \
-	$(LVX) vst al dlxm_dpt dlxm_dpt 
-	touch lvx_result_dpt
-
-#####################################
-#
-# How to make core
-#
-#   - Call BBR
-#
-#   - Extract the netlist from layout ( LYNX )
-#
-#   - Compare the netlist ( LVX )
-#
-#####################################
-
-core_routing : dpt_routing ctl_routing lvx_result_core
-
-#####################################
-#
-# Routing core
-#
-#   - Create the placement ( GENLIB )
-#
-#   - Call BBR
-#
-#####################################
-
-dlxm_core.ap : dlxm_core.c dlxm_dpt.ap dlxm_ctl.ap
-	@ MBK_CATA_LIB=./maclib:$(ALL);   export MBK_CATA_LIB;                        \
-	$(ENV_VST);                                                          \
-	$(ENV_AP);                                                           \
-	$(GENLIB) -v dlxm_core;                                              \
-	$(BBR) dlxm_core -v -o dlxm_core vdd 12 vss 12; \
-	$(ENV_RDS);  $(ENV_SYMB); \
-	$(GRAAL) -l dlxm_core
-
-#####################################
-#
-# Extracting core
-#
-#   - Call LYNX
-#
-#####################################
-
-dlxm_core.al : dlxm_core.ap
-	@ MBK_CATA_LIB=./mclib:$(ALL);   export MBK_CATA_LIB;                \
-	$(ENV_AL);                                                           \
-	$(ENV_AP);                                                           \
-	$(ENV_RDS);  $(ENV_SYMB); \
-	$(LYNX) -v dlxm_core dlxm_core
-
-#####################################
-#
-# Netlist comparison
-#
-#   - Call LVX
-#
-#   - Create a file for makefile dependances
-#
-#####################################
-
-lvx_result_core : dlxm_core.al
-	@ MBK_CATA_LIB=$(ALL);   export MBK_CATA_LIB;                          \
-	$(LVX) vst al dlxm_core dlxm_core
-	touch lvx_result_core
-
-#####################################
-#
-# How to make dlxm
-#
-#   - Call RING
-#
-#   - Extract the netlist from layout ( LYNX )
-#
-#   - Compare the netlist ( LVX )
-#
-#####################################
-
-dlxm_routing : core_routing lvx_result_dlxm drc_result_dlxm
-
-#####################################
-#
-# Routing dlxm
-#
-#   - Call RING
-#
-#####################################
-
-dlxm_chip.ap : dlxm_core.ap dlxm_chip.rin
-	@ MBK_CATA_LIB=$(ALL);     export MBK_CATA_LIB;                    \
-	$(ENV_VST);                                                          \
-	$(ENV_AP);                                                           \
-	$(RING_EXE) dlxm_chip dlxm_chip; \
-	$(ENV_RDS);  $(ENV_SYMB); \
-	$(GRAAL) -l dlxm_chip
-
-#####################################
-#
-# Extracting dlxm
-#
-#   - Call LYNX
-#
-#####################################
-
-dlxm_chip.al : dlxm_chip.ap
-	@ MBK_CATA_LIB=$(ALL);   export MBK_CATA_LIB;                        \
-	$(ENV_AL);                                                           \
-	$(ENV_AP);                                                           \
-	$(ENV_RDS);  $(ENV_SYMB); \
-	$(LYNX) -v dlxm_chip dlxm_chip
-
-#####################################
-#
-# Netlist comparison
-#
-#   - Call LVX
-#
-#   - Create a file for makefile dependances
-#
-#####################################
-
-lvx_result_dlxm : dlxm_chip.al
-	@ MBK_CATA_LIB=$(ALL); export MBK_CATA_LIB;                      \
-	$(LVX) vst al dlxm_chip dlxm_chip
-	touch lvx_result_dlxm
-
-#####################################
-#
-# Design Rules Check
-#
-#   - Call DRUC
-#
-#   - Create a file for makefile dependances
-#
-#####################################
-
-drc_result_dlxm : dlxm_chip.ap
-	@MBK_CATA_LIB=./mclib:$(ALL); export MBK_CATA_LIB; \
-	$(ENV_RDS); $(ENV_SYMB);                        \
-	$(ENV_AP);                                      \
-	$(DRUC) dlxm_chip
-	touch drc_result_dlxm
-
-
-#####################################
-#
-# How to make real view of dlxm
-#
-#    - Call S2R : Generate the real view ( cif )
-#
-#####################################
-
-dlxm_real : physical dlxm_chip.cif
-
-#####################################
-#
-# Creation of real view of dlxm
-#
-#   - Call S2R
-#
-#####################################
-
-dlxm_chip.cif : dlxm_chip.ap
-	@ MBK_CATA_LIB=./mclib:$(ALL);        export MBK_CATA_LIB;           \
-	$(ENV_REAL); \
-	$(ENV_RDS);                                                          \
-	$(ENV_AP);                                                           \
-	$(S2R) dlxm_chip; \
-	$(DREAL) -l dlxm_chip
-
-#####################################
-#
-#       ... The End ...
-#
-#   - Pirouz . Julien . Mariem . Ludovic . Czo - 
-#
-#####################################
-
diff --git a/alliance/share/tutorials/dlxm/NO_CATAL b/alliance/share/tutorials/dlxm/NO_CATAL
deleted file mode 100644
index eab57edc..00000000
--- a/alliance/share/tutorials/dlxm/NO_CATAL
+++ /dev/null
@@ -1 +0,0 @@
-no_catal	C
diff --git a/alliance/share/tutorials/dlxm/add000.s b/alliance/share/tutorials/dlxm/add000.s
deleted file mode 100644
index de7abfe5..00000000
--- a/alliance/share/tutorials/dlxm/add000.s
+++ /dev/null
@@ -1,65 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: add000.s						#
-;  # date	: Oct 21 1994						#
-;  #									#
-;  # origin	: this description has been developed by CAO-VLSI team	#
-;  #		  at MASI laboratory, University Pierre et Marie Curie	#
-;  #		  URA CNRS 818, Institut Blaise Pascal			#
-;  #		  4 Place Jussieu 75252 Paris Cedex 05 - France		#
-;  # E-mail      :      cao-vlsi@masi.ibp.fr                            #
-;  #									#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (RESET)				#
-	;  ###--------------------------------------------------------###
-
-reset_mask	equ	X"0008"
-system_stack	equ	X"80000000"
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler:
-		j	handler_body
-		nop
-return:
-		rfe				; return from exception
-		nop
-
-
-		org	X"ffffff00"
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-other_causes 	j	other_causes
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog
-		movi2s	iar, r29
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/add000.u b/alliance/share/tutorials/dlxm/add000.u
deleted file mode 100644
index 90663551..00000000
--- a/alliance/share/tutorials/dlxm/add000.u
+++ /dev/null
@@ -1,43 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: add000.u						#
-;  # date	: Apr  1 1993						#
-;  #									#
-;  # origin	: this description has been developed by CAO-VLSI team	#
-;  #		  at MASI laboratory, University Pierre et Marie Curie	#
-;  #		  URA CNRS 818, Institut Blaise Pascal			#
-;  #		  4 Place Jussieu 75252 Paris Cedex 05 - France		#
-;  # E-mail      :      cao-vlsi@masi.ibp.fr                            #
-;  #									#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   signed addition						#
-	;  ###--------------------------------------------------------###
-
-val1		equ	X"000a"
-val2		equ	X"0002"
-
-		org	X"7fffff00"
-		start	init
-
-init:
-
-		addi	r1 , r0 , val1
-		addi	r2 , r0 , val2
-		add	r3 , r2 , r1
-
-		seqi	r5 , r3 , (val1 + val2)
-		bnez	r5      , good
-		nop
-		j	bad
-		nop
-
-		org	X"7ffffff0"
-good 		j	good
-		nop
-bad 		j	bad
-		nop
-		end
diff --git a/alliance/share/tutorials/dlxm/dlxm.pdf b/alliance/share/tutorials/dlxm/dlxm.pdf
deleted file mode 100644
index 980b2b61..00000000
Binary files a/alliance/share/tutorials/dlxm/dlxm.pdf and /dev/null differ
diff --git a/alliance/share/tutorials/dlxm/dlxm.ps b/alliance/share/tutorials/dlxm/dlxm.ps
deleted file mode 100644
index d8e32cee..00000000
--- a/alliance/share/tutorials/dlxm/dlxm.ps
+++ /dev/null
@@ -1,1354 +0,0 @@
-%!PS-Adobe-2.0
-%%Creator: dvips(k) 5.85 Copyright 1999 Radical Eye Software
-%%Title: dlxm.dvi
-%%Pages: 15
-%%PageOrder: Ascend
-%%BoundingBox: 0 0 596 842
-%%DocumentFonts: Palatino-Bold Palatino-Roman Palatino-Italic
-%%EndComments
-%DVIPSWebPage: (www.radicaleye.com)
-%DVIPSCommandLine: dvips dlxm.dvi -o dlxm.ps
-%DVIPSParameters: dpi=600, compressed
-%DVIPSSource:  TeX output 2000.01.20:1123
-%%BeginProcSet: texc.pro
-%!
-/TeXDict 300 dict def TeXDict begin/N{def}def/B{bind def}N/S{exch}N/X{S
-N}B/A{dup}B/TR{translate}N/isls false N/vsize 11 72 mul N/hsize 8.5 72
-mul N/landplus90{false}def/@rigin{isls{[0 landplus90{1 -1}{-1 1}ifelse 0
-0 0]concat}if 72 Resolution div 72 VResolution div neg scale isls{
-landplus90{VResolution 72 div vsize mul 0 exch}{Resolution -72 div hsize
-mul 0}ifelse TR}if Resolution VResolution vsize -72 div 1 add mul TR[
-matrix currentmatrix{A A round sub abs 0.00001 lt{round}if}forall round
-exch round exch]setmatrix}N/@landscape{/isls true N}B/@manualfeed{
-statusdict/manualfeed true put}B/@copies{/#copies X}B/FMat[1 0 0 -1 0 0]
-N/FBB[0 0 0 0]N/nn 0 N/IEn 0 N/ctr 0 N/df-tail{/nn 8 dict N nn begin
-/FontType 3 N/FontMatrix fntrx N/FontBBox FBB N string/base X array
-/BitMaps X/BuildChar{CharBuilder}N/Encoding IEn N end A{/foo setfont}2
-array copy cvx N load 0 nn put/ctr 0 N[}B/sf 0 N/df{/sf 1 N/fntrx FMat N
-df-tail}B/dfs{div/sf X/fntrx[sf 0 0 sf neg 0 0]N df-tail}B/E{pop nn A
-definefont setfont}B/Cw{Cd A length 5 sub get}B/Ch{Cd A length 4 sub get
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-B/Cdx{Cd A length 1 sub get}B/Ci{Cd A type/stringtype ne{ctr get/ctr ctr
-1 add N}if}B/id 0 N/rw 0 N/rc 0 N/gp 0 N/cp 0 N/G 0 N/CharBuilder{save 3
-1 roll S A/base get 2 index get S/BitMaps get S get/Cd X pop/ctr 0 N Cdx
-0 Cx Cy Ch sub Cx Cw add Cy setcachedevice Cw Ch true[1 0 0 -1 -.1 Cx
-sub Cy .1 sub]/id Ci N/rw Cw 7 add 8 idiv string N/rc 0 N/gp 0 N/cp 0 N{
-rc 0 ne{rc 1 sub/rc X rw}{G}ifelse}imagemask restore}B/G{{id gp get/gp
-gp 1 add N A 18 mod S 18 idiv pl S get exec}loop}B/adv{cp add/cp X}B
-/chg{rw cp id gp 4 index getinterval putinterval A gp add/gp X adv}B/nd{
-/cp 0 N rw exit}B/lsh{rw cp 2 copy get A 0 eq{pop 1}{A 255 eq{pop 254}{
-A A add 255 and S 1 and or}ifelse}ifelse put 1 adv}B/rsh{rw cp 2 copy
-get A 0 eq{pop 128}{A 255 eq{pop 127}{A 2 idiv S 128 and or}ifelse}
-ifelse put 1 adv}B/clr{rw cp 2 index string putinterval adv}B/set{rw cp
-fillstr 0 4 index getinterval putinterval adv}B/fillstr 18 string 0 1 17
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-/p{show}N/RMat[1 0 0 -1 0 0]N/BDot 260 string N/Rx 0 N/Ry 0 N/V{}B/RV/v{
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-w(CPU)p 698 2051 V 30 w(CHIP)29 b Fg(:)f(List)h(of)g(behavioural)g
-(models)g(r)o(equir)o(ed)f(for)h(a)f(simulation)i(using)g(the)f
-(behavioural)g(model)g(of)208 2151 y(DLXm.)125 2317 y
-Fe(\017)41 b Ff(dlxm)p 408 2317 V 28 w(cpu.pat)19 b Fg(:)25
-b(Pattern)c(input)g(\002le)g(for)f(testing)i(various)f(views)g(of)f
-(dlxm)h(chip.)1781 2483 y Ff(structural)e(design)125
-2716 y Fe(\017)41 b Ff(dlxm)p 408 2716 V 28 w(chip.vst)19
-b Fg(:)26 b(VHDL)21 b(str)o(uctural)f(model)h(of)g(the)g(dlxm)g
-(instantiating)g(cor)o(e)f(and)h(pads.)125 2882 y Fe(\017)41
-b Ff(dlxm)p 408 2882 V 28 w(core.vst)20 b Fg(:)26 b(VHDL)20
-b(str)o(uctural)h(model)g(of)g(the)g(cor)o(e)f(instantiating)i(the)e
-(data)g(path)h(and)f(the)h(contr)o(ol.)125 3048 y Fe(\017)41
-b Ff(dlxm)p 408 3048 V 28 w(ctl.vst.h)19 b Fg(:)25 b(VHDL)c(str)o
-(uctural)g(model)g(of)g(the)g(contr)o(ol)g(instantiating)g(the)g
-(sequencer)g(and)f(the)h(status.)125 3214 y Fe(\017)41
-b Ff(dlxm)p 408 3214 V 28 w(seq.fsm)20 b Fg(:)25 b(Finite)d(State)d
-(Machine)i(description)g(for)f(sequencer)-6 b(.)125 3380
-y Fe(\017)41 b Ff(dlxm)p 408 3380 V 28 w(dpt.vbe)19 b
-Fg(:)26 b(Behavioural)20 b(description)h(for)f(data)g(path.)125
-3546 y Fe(\017)41 b Ff(CA)-8 b(T)g(AL)p 493 3546 V 29
-w(CPU)p 698 3546 V 30 w(BLOCKS)19 b Fg(:)h(List)g(of)g(behavioural)f
-(models)h(r)o(equir)o(ed)f(for)h(a)f(simulation)i(using)g(behavioural)f
-(descriptions)208 3645 y(for)g(data)g(path,)g(sequencer)h(and)f
-(status.)125 3811 y Fe(\017)41 b Ff(dlxm)p 408 3811 V
-28 w(dpt.c)20 b Fg(:)25 b(Sour)o(ce)20 b(code)g(for)h(data)e(path)i
-(generator)-6 b(.)125 3977 y Fe(\017)41 b Ff(./mclib)e
-Fg(:)26 b(Subdir)o(ectiry)19 b(used)h(by)h Ff(fpgen)f
-Fg(to)i(stor)o(e)e(the)h(generated)e(data)h(path)h(operators.)125
-4144 y Fe(\017)41 b Ff(dlxm)p 408 4144 V 28 w(sts.vbe)19
-b Fg(:)26 b(Behavioural)20 b(description)h(for)f(status)h(and)g(interr)
-o(upts.)125 4310 y Fe(\017)41 b Ff(CA)-8 b(T)g(AL)p 493
-4310 V 29 w(CPU)p 698 4310 V 30 w(GA)g(TES)21 b Fg(:)h(List)g(of)g
-(behavioural)f(models)i(r)o(equir)o(ed)d(for)i(a)f(simulation)i(using)g
-(str)o(uctural)f(descriptions)g(for)208 4409 y(data)d(path,)h
-(sequencer)h(and)g(status.)125 4575 y Fe(\017)41 b Ff(dlxm)p
-408 4575 V 28 w(scan.pat)18 b Fg(:)26 b(Pattern)20 b(input)i(\002le)f
-(for)f(scan)h(path)f(simulation.)1811 4741 y Ff(physical)f(layout)125
-4974 y Fe(\017)41 b Ff(dlxm)p 408 4974 V 28 w(dpt.dpr)19
-b Fg(:)26 b(Placement)21 b(\002le)g(for)f(data)g(path)g(block)h
-(connectors)h(\()p Ff(dpr)e Fg(tool\))125 5140 y Fe(\017)41
-b Ff(dlxm)p 408 5140 V 28 w(ctl.scr)20 b Fg(:)25 b(Placement)c(\002le)g
-(for)f(contr)o(ol)i(block)f(connectors)g(\()p Ff(scr)g
-Fg(tool\))125 5306 y Fe(\017)41 b Ff(dlxm)p 408 5306
-V 28 w(core.c)20 b Fg(:)26 b(Placement)20 b(\002le)h(for)g(contr)o(ol)g
-(and)f(data)g(path)g(\()p Ff(bbr)h Fg(tool\))125 5472
-y Fe(\017)41 b Ff(dlxm)p 408 5472 V 28 w(chip.rin)19
-b Fg(:)26 b(Placement)20 b(\002le)h(for)g(dlxm)g(pads)f(\()p
-Ff(ring)g Fg(tool\))2058 5956 y(15)p eop
-%%Trailer
-end
-userdict /end-hook known{end-hook}if
-%%EOF
diff --git a/alliance/share/tutorials/dlxm/dlxm_chip.rin b/alliance/share/tutorials/dlxm/dlxm_chip.rin
deleted file mode 100644
index 4c43ea91..00000000
--- a/alliance/share/tutorials/dlxm/dlxm_chip.rin
+++ /dev/null
@@ -1,134 +0,0 @@
-#
-#								
-# file	: dlxm_chip.rin							
-# date	: February 1995							
-# version	: v0.0							
-#									
-# origin	: this description has been developed by CAO-VLSI team	
-#		  at MASI laboratory, University Pierre et Marie Curie	
-#		  URA CNRS 818, Institut Blaise Pascal			
-#		  4 Place Jussieu 75252 Paris Cedex 05 - France		
-# E-mail      :      cao-vlsi@masi.ibp.fr                            
-#									
-# descr.	: Placement file for dlxm pads				
-#									
-#
-
-# NORTH
-north(
-ad_out_pl30
-ad_out_pl31
-ck_vsse_pl_0
-test_pl
-scout_pl
-vdde_pl_0
-frz_pl
-reset_pl
-vssi_pl_0
-it_in_pl0
-it_in_pl1
-it_in_pl2
-it_in_pl3
-vddi_pl_0
-rw_pl
-byte_pl0
-byte_pl1
-byte_pl2
-byte_pl3
-vsse_pl_1
-dat_inout_pl31
-dat_inout_pl30
-vdde_pl_1
-dat_inout_pl29
-dat_inout_pl28
-)
-
-# EAST
-east(
-dat_inout_pl10
-dat_inout_pl11
-dat_inout_pl12
-dat_inout_pl13
-vdde_pl_3
-dat_inout_pl14
-dat_inout_pl15
-vsse_pl_3
-dat_inout_pl16
-dat_inout_pl17
-dat_inout_pl18
-dat_inout_pl19
-vddi_pl_1
-clock_ring
-dat_inout_pl20
-dat_inout_pl21
-vssi_pl_1
-dat_inout_pl22
-dat_inout_pl23
-vdde_pl_2
-dat_inout_pl24
-dat_inout_pl25
-vsse_pl_2
-dat_inout_pl26
-dat_inout_pl27
-)
-
-# SOUTH
-south(
-ad_out_pl7
-ad_out_pl6
-vdde_pl_5
-ad_out_pl5
-ad_out_pl4
-scin_pl
-vsse_pl_5
-ad_out_pl3
-ad_out_pl2
-vddi_pl_2
-ad_out_pl1
-ad_out_pl0
-vssi_pl_2
-dat_inout_pl0
-dat_inout_pl1
-dat_inout_pl2
-dat_inout_pl3
-vdde_pl_4
-dat_inout_pl4
-dat_inout_pl5
-vsse_pl_4
-dat_inout_pl6
-dat_inout_pl7
-dat_inout_pl8
-dat_inout_pl9
-)
-
-# WEST
-west(
-ad_out_pl8
-ad_out_pl9
-ad_out_pl10
-ad_out_pl11
-vsse_pl_6
-ad_out_pl12
-ad_out_pl13
-vdde_pl_6
-ad_out_pl14
-ad_out_pl15
-ad_out_pl16
-ad_out_pl17
-vddi_pl_3
-ad_out_pl18
-ad_out_pl19
-ck_vssi_pl_3
-ad_out_pl20
-ad_out_pl21
-ad_out_pl22
-ad_out_pl23
-vdde_pl_7
-ad_out_pl24
-ad_out_pl25
-vsse_pl_7
-ad_out_pl26
-ad_out_pl27
-ad_out_pl28
-ad_out_pl29
-)
diff --git a/alliance/share/tutorials/dlxm/dlxm_chip.vbe b/alliance/share/tutorials/dlxm/dlxm_chip.vbe
deleted file mode 100644
index d6c36db8..00000000
--- a/alliance/share/tutorials/dlxm/dlxm_chip.vbe
+++ /dev/null
@@ -1,1233 +0,0 @@
-
--- ###----------------------------------------------------------------###
--- #									#
--- # file	: dlxm_chip.vbe						#
--- # date	: February  5 1995		       			#
--- # version	: v0.3							#
--- #									#
--- # origin	: this description has been developed by CAO-VLSI team	#
--- #		  at MASI laboratory, University Pierre et Marie Curie	#
--- #		  URA CNRS 818, Institut Blaise Pascal			#
--- #		  4 Place Jussieu 75252 Paris Cedex 05 - France		#
--- # E-mail      :      cao-vlsi@masi.ibp.fr                            #
--- #									#
--- # descr.	: VHDL description of the DLX's processor (micro-      	#
--- #		  programmed implementation)				#
--- ###----------------------------------------------------------------###
-
-entity DLXM_CHIP is
-
-  port (
-       CK      : in    bit                         ;
-       RESET   : in    bit                         ;
-       FRZ     : in    bit                         ;
-       IT      : in    bit_vector ( 3 downto 0)    ;
-       DATA    : inout mux_vector (31 downto 0) bus;
-       BYTE    : out   bit_vector ( 0     to 3)    ;
-       RW      : out   bit                         ;
-       ADR     : out   mux_vector(31 downto 0)  bus;
-       SCIN    : in    bit                         ;
-       TEST    : in    bit                         ;
-       SCOUT   : out   bit                         ;
-       VDD     : in    bit                         ;
-       VSS     : in    bit                         ;
-       VDDP    : in    bit                         ;
-       VSSP    : in    bit
-       ) ;
-
-end DLXM_CHIP ;
-
-
-
-
-
-architecture BEHAVIOURAL of DLXM_CHIP is
-
-signal CKFRZ_S   : bit                              ;	-- internal clock
-signal CK_S      : bit                              ;	-- internal clock
-signal CKDLY0_S  : bit                              ;	-- internal clock
-signal CKDLY1_S  : bit                              ;	-- internal clock
-signal CKDLY2_S  : bit                              ;	-- internal clock
-signal CKDLY3_S  : bit                              ;	-- internal clock
-signal CKDLY4_S  : bit                              ;	-- internal clock
-signal CKDLY5_S  : bit                              ;	-- internal clock
-signal CKDLY6_S  : bit                              ;	-- internal clock
-
-signal SHRTBCH_S : bit_vector ( 6 downto 0)         ;
-signal LONGBCH_S : bit_vector ( 6 downto 0)         ;
-signal STRTADR_S : bit_vector ( 6 downto 0)         ;
-signal BCHNUL_S  : bit_vector ( 6 downto 0)         ;
-signal BCHOP4_S  : bit_vector ( 6 downto 0)         ;
-signal BCHOP16_S : bit_vector ( 6 downto 0)         ;
-signal BCHIN8_S  : bit_vector ( 6 downto 0)         ;
-
-signal MICADR_S  : bit_vector ( 6 downto 0)         ;	-- next micro ins. adr.
-signal MICADR_R  : reg_vector ( 6 downto 0) register;	-- micro ins. adr reg.
-signal MICINS_S  : bit_vector (26 downto 0)         ;	-- next  micro ins.
-signal RESTMI_X  : bit_vector (26 downto 0)         ;	-- reset micro ins.
-signal MICINS_R  : reg_vector (26 downto 0) register;	-- micro ins. reg.
-
-signal CTLEXC_S  : bit                              ;	-- operand x  field
-signal CTLOPX_S  : bit_vector ( 3 downto 0)         ;	-- operand x  field
-signal CTLOPY_S  : bit_vector ( 2 downto 0)         ;	-- operand y  field
-signal CTLALU_S  : bit_vector ( 3 downto 0)         ;	-- alu        field
-signal CTLRES_S  : bit_vector ( 3 downto 0)         ;	-- result     field
-signal CTLMEM_S  : bit_vector ( 3 downto 0)         ;	-- read/write field
-signal CTLSEQ_S  : bit_vector ( 2 downto 0)         ;	-- sequencer  field
-signal CTLDAT_S  : bit_vector ( 3 downto 0)         ;	-- constante  field
-
-signal REDPNT_S  : bit_vector ( 4 downto 0)         ;	-- read pointer
-signal WRTPNT_S  : bit_vector ( 4 downto 0)         ;	-- write pointer
-signal REDREG_S  : bit_vector (31 downto 0)         ;	-- value read from reg.
-signal IFORMT_S  : bit                              ;	-- i format instr.
-
-signal IR_R      : reg_vector (31 downto 0) register;	-- instruction reg.
-signal OPCOD_S   : bit_vector ( 5 downto 0)         ;	-- oper. code
-
-signal R1_R      : reg_vector (31 downto 0) register;	-- integer reg #1
-signal R2_R      : reg_vector (31 downto 0) register;	-- integer reg #2
-signal R3_R      : reg_vector (31 downto 0) register;	-- integer reg #3
-signal R4_R      : reg_vector (31 downto 0) register;	-- integer reg #4
-signal R5_R      : reg_vector (31 downto 0) register;	-- integer reg #5
-signal R6_R      : reg_vector (31 downto 0) register;	-- integer reg #6
-signal R7_R      : reg_vector (31 downto 0) register;	-- integer reg #7
-signal R8_R      : reg_vector (31 downto 0) register;	-- integer reg #8
-signal R9_R      : reg_vector (31 downto 0) register;	-- integer reg #9
-signal R10_R     : reg_vector (31 downto 0) register;	-- integer reg #10
-signal R11_R     : reg_vector (31 downto 0) register;	-- integer reg #11
-signal R12_R     : reg_vector (31 downto 0) register;	-- integer reg #12
-signal R13_R     : reg_vector (31 downto 0) register;	-- integer reg #13
-signal R14_R     : reg_vector (31 downto 0) register;	-- integer reg #14
-signal R15_R     : reg_vector (31 downto 0) register;	-- integer reg #15
-signal R16_R     : reg_vector (31 downto 0) register;	-- integer reg #16
-signal R17_R     : reg_vector (31 downto 0) register;	-- integer reg #17
-signal R18_R     : reg_vector (31 downto 0) register;	-- integer reg #18
-signal R19_R     : reg_vector (31 downto 0) register;	-- integer reg #19
-signal R20_R     : reg_vector (31 downto 0) register;	-- integer reg #20
-signal R21_R     : reg_vector (31 downto 0) register;	-- integer reg #21
-signal R22_R     : reg_vector (31 downto 0) register;	-- integer reg #22
-signal R23_R     : reg_vector (31 downto 0) register;	-- integer reg #23
-signal R24_R     : reg_vector (31 downto 0) register;	-- integer reg #24
-signal R25_R     : reg_vector (31 downto 0) register;	-- integer reg #25
-signal R26_R     : reg_vector (31 downto 0) register;	-- integer reg #26
-signal R27_R     : reg_vector (31 downto 0) register;	-- integer reg #27
-signal R28_R     : reg_vector (31 downto 0) register;	-- integer reg #28
-signal R29_R     : reg_vector (31 downto 0) register;	-- integer reg #29
-signal R30_R     : reg_vector (31 downto 0) register;	-- integer reg #30
-signal R31_R     : reg_vector (31 downto 0) register;	-- integer reg #31
-
-signal PC_R      : reg_vector (31 downto 0) register;	-- progr. counter
-signal AD_R      : reg_vector (31 downto 0) register;	-- address register
-signal IAR_R     : reg_vector (31 downto 0) register;	-- intr. adr. reg.
-signal SR_R      : reg_vector (31 downto 0) register;	-- status register
-signal TVR_R     : reg_vector (31 downto 0) register;	-- trap vector reg.
-signal DT_R      : reg_vector (31 downto 0) register;	-- data register
-
-signal OPERY_S   : bit_vector (31 downto 0)         ;	-- y operand
-signal OPERX_S   : bit_vector (31 downto 0)         ;	-- x operand
-
-signal ADDY_S    : bit_vector (31 downto 0)         ;	-- adder's y operand
-signal ADDX_S    : bit_vector (31 downto 0)         ;	-- adder's x operand
-signal ADDRES_S  : bit_vector (31 downto 0)         ;	-- adder's result
-signal ADDCRY_S  : bit_vector (32 downto 0)         ;	-- adder's carry
-signal ADDOVR_S  : bit                              ;	-- adder's overflow
-
-signal SEQ_S     : bit                              ;	-- x  = y arith.
-signal SNE_S     : bit                              ;	-- x /= y arith.
-signal SGE_S     : bit                              ;	-- x >= y arith.
-signal SGT_S     : bit                              ;	-- x  > y arith.
-signal SLE_S     : bit                              ;	-- x <= y arith.
-signal SLT_S     : bit                              ;	-- x  < y arith.
-
-signal SHIN_S    : bit_vector (31 downto 0)         ;	-- shift right in
-signal SHRIT_S   : bit_vector (31 downto 0)         ;	-- shift result (right)
-signal SHLFT_S   : bit_vector (31 downto 0)         ;	-- shift result (left)
-
-signal RESULT_S  : bit_vector (31 downto 0)         ;	-- alu's result
-signal RESNUL_S  : bit                              ;	-- alu's result = 0
-
-signal IMD16_S   : bit_vector (31 downto 0)         ;	-- signed 16 bit imd
-signal IMD18_S   : bit_vector (31 downto 0)         ;	-- short branch offset
-signal IMD28_S   : bit_vector (31 downto 0)         ;	-- long  branch offset
-
-signal WORD_S    : bit                              ;
-signal BYTE_S    : bit                              ;
-signal BYTSEL_S  : bit_vector ( 0     to 3)         ;
-
-signal REDDAT_S  : bit_vector (31 downto 0)         ;	-- aligned data
-signal NEWSR_X   : bit_vector (15 downto 0)         ;	-- new status
-
-signal WENSR_S   : bit                              ;	-- status reg. wen.
-signal WENIAR_S  : bit                              ;	-- it. adr. reg. wen.
-signal WENTVR_S  : bit                              ;	-- trap vec. reg. wen.
-signal WENPC_S   : bit                              ;	-- progr. counter wen.
-signal WENAD_S   : bit                              ;	-- address reg. wen.
-signal WENREG_S  : bit                              ;	-- integer reg. wen.
-signal WENDT_S   : bit                              ;	-- data reg. wen.
-signal WENIR_S   : bit                              ;	-- ins. reg. wen.
-
-signal INTRQS_X  : bit                              ;	-- interrupt request
-signal EXCRQS_X  : bit                              ;	-- exception request
-signal RQS_X     : bit                              ;	-- request
-
-signal PRVINS_X  : bit                              ;	-- privileged instr.
-signal ILLINS_X  : bit                              ;	-- illegal instruction
-signal OPVIOL_X  : bit                              ;	-- ins. violation
-signal OVRFLO_X  : bit                              ;	-- overflow
-signal DAALGN_X  : bit                              ;	-- data adr. algn.
-signal DASGMT_X  : bit                              ;	-- data adr. segment
-signal IAALGN_X  : bit                              ;	-- ins. adr. algn.
-signal IASGMT_X  : bit                              ;	-- ins. adr. segment
-
-signal FRZ_R     : reg_bit                  register;	-- freeze
-signal RESET_R   : reg_bit                  register;	-- reset register
-signal CPURST_R  : reg_bit                  register;	-- CPU reseted
-signal IAV_R     : reg_bit                  register;	-- ins. adr. viol.
-signal DAV_R     : reg_bit                  register;	-- data adr. viol.
-signal ICO_R     : reg_bit                  register;	-- opcode viol.
-signal OVR_R     : reg_bit                  register;	-- overflow
-signal IT_R      : reg_vector ( 3 downto 0) register;	-- external it
-
-constant R0_R     : bit_vector (31 downto 0) :=X"00000000"; 	-- reg #0 = 0
-
-constant add_i    : bit_vector (5 downto 0) := B"000_000"  ;	-- add
-constant addu_i   : bit_vector (5 downto 0) := B"000_001"  ;	-- addu
-constant sub_i    : bit_vector (5 downto 0) := B"000_010"  ;	-- sub
-constant subu_i   : bit_vector (5 downto 0) := B"000_011"  ;	-- subu
-constant addi_i   : bit_vector (5 downto 0) := B"000_100"  ;	-- addi
-constant addui_i  : bit_vector (5 downto 0) := B"000_101"  ;	-- addui
-constant subi_i   : bit_vector (5 downto 0) := B"000_110"  ;	-- subi
-constant subui_i  : bit_vector (5 downto 0) := B"000_111"  ;	-- subui
-constant sll_i    : bit_vector (5 downto 0) := B"001_000"  ;	-- sll
-constant srl_i    : bit_vector (5 downto 0) := B"001_001"  ;	-- srl
-constant sra_i    : bit_vector (5 downto 0) := B"001_010"  ;	-- sra
-constant slli_i   : bit_vector (5 downto 0) := B"001_100"  ;	-- slli
-constant srli_i   : bit_vector (5 downto 0) := B"001_101"  ;	-- srli
-constant srai_i   : bit_vector (5 downto 0) := B"001_110"  ;	-- srai
-constant lhi_i    : bit_vector (5 downto 0) := B"001_111"  ;	-- lhi
-constant seq_i    : bit_vector (5 downto 0) := B"010_000"  ;	-- seq
-constant sne_i    : bit_vector (5 downto 0) := B"010_001"  ;	-- sne
-constant sge_i    : bit_vector (5 downto 0) := B"010_010"  ;	-- sge
-constant sle_i    : bit_vector (5 downto 0) := B"010_011"  ;	-- sle
-constant seqi_i   : bit_vector (5 downto 0) := B"010_100"  ;	-- seqi
-constant snei_i   : bit_vector (5 downto 0) := B"010_101"  ;	-- snei
-constant sgei_i   : bit_vector (5 downto 0) := B"010_110"  ;	-- sgei
-constant slei_i   : bit_vector (5 downto 0) := B"010_111"  ;	-- slei
-constant sgt_i    : bit_vector (5 downto 0) := B"011_010"  ;	-- sgt
-constant slt_i    : bit_vector (5 downto 0) := B"011_011"  ;	-- slt
-constant sgti_i   : bit_vector (5 downto 0) := B"011_110"  ;	-- sgti
-constant slti_i   : bit_vector (5 downto 0) := B"011_111"  ;	-- slti
-constant and_i    : bit_vector (5 downto 0) := B"100_000"  ;	-- and
-constant or_i     : bit_vector (5 downto 0) := B"100_001"  ;	-- or
-constant xor_i    : bit_vector (5 downto 0) := B"100_011"  ;	-- xor
-constant andi_i   : bit_vector (5 downto 0) := B"100_100"  ;	-- andi
-constant ori_i    : bit_vector (5 downto 0) := B"100_101"  ;	-- ori
-constant xori_i   : bit_vector (5 downto 0) := B"100_111"  ;	-- xori
-
-constant sw_i     : bit_vector (5 downto 0) := B"101_000"  ;	-- sw
-constant sh_i     : bit_vector (5 downto 0) := B"101_001"  ;	-- sh
-constant sb_i     : bit_vector (5 downto 0) := B"101_010"  ;	-- sb
-constant lbu_i    : bit_vector (5 downto 0) := B"101_011"  ;	-- lbu
-constant lw_i     : bit_vector (5 downto 0) := B"101_100"  ;	-- lw
-constant lh_i     : bit_vector (5 downto 0) := B"101_101"  ;	-- lh
-constant lb_i     : bit_vector (5 downto 0) := B"101_110"  ;	-- lb
-constant lhu_i    : bit_vector (5 downto 0) := B"101_111"  ;	-- lhu
-
-constant jr_i     : bit_vector (5 downto 0) := B"110_000"  ;	-- jr
-constant jalr_i   : bit_vector (5 downto 0) := B"110_001"  ;	-- jalr
-constant movs2i_i : bit_vector (5 downto 0) := B"110_010"  ;	-- movi2s
-constant movi2s_i : bit_vector (5 downto 0) := B"110_011"  ;	-- movs2i
-constant beqz_i   : bit_vector (5 downto 0) := B"110_100"  ;	-- beqz
-constant bnez_i   : bit_vector (5 downto 0) := B"110_101"  ;	-- bnez
-constant j_i      : bit_vector (5 downto 0) := B"111_000"  ;	-- j
-constant jal_i    : bit_vector (5 downto 0) := B"111_001"  ;	-- jal
-constant rfe_i    : bit_vector (5 downto 0) := B"111_010"  ;	-- rfe
-constant trap_i   : bit_vector (5 downto 0) := B"111_011"  ;	-- trap
-
-constant c0     : bit_vector (31 downto 0) := X"00000000";
-constant c1     : bit_vector (31 downto 0) := X"00000001";
-constant c4     : bit_vector (31 downto 0) := X"00000004";
-constant c16    : bit_vector (31 downto 0) := X"00000010";
-constant cb     : bit_vector (31 downto 0) := X"000000ff";
-constant ch     : bit_vector (31 downto 0) := X"0000ffff";
-
-constant e_no   : bit                     := '0' ;
-constant e_il   : bit                     := '1' ;
-
-constant x_rs   : bit_vector (3 downto 0) := B"0000" ;
-constant x_rt   : bit_vector (3 downto 0) := B"0001" ;
-constant x_pc   : bit_vector (3 downto 0) := B"0100" ;
-constant x_ad   : bit_vector (3 downto 0) := B"0101" ;
-constant x_sr   : bit_vector (3 downto 0) := B"0110" ;
-constant x_tv   : bit_vector (3 downto 0) := B"0010" ;
-constant x_ia   : bit_vector (3 downto 0) := B"0111" ;
-constant x_c0   : bit_vector (3 downto 0) := B"1000" ;
-constant x_cb   : bit_vector (3 downto 0) := B"1100" ;
-constant x_ch   : bit_vector (3 downto 0) := B"1111" ;
-
-constant y_i16  : bit_vector (2 downto 0) := B"000" ;
-constant y_i18  : bit_vector (2 downto 0) := B"001" ;
-constant y_i28  : bit_vector (2 downto 0) := B"010" ;
-constant y_dt   : bit_vector (2 downto 0) := B"011" ;
-constant y_ad   : bit_vector (2 downto 0) := B"100" ;
-constant y_c0   : bit_vector (2 downto 0) := B"101" ;
-constant y_c4   : bit_vector (2 downto 0) := B"110" ;
-constant y_c16  : bit_vector (2 downto 0) := B"111" ;
-
-constant a_sum  : bit_vector (3 downto 0) := B"0000" ;
-constant a_smv  : bit_vector (3 downto 0) := B"0001" ;
-constant a_dif  : bit_vector (3 downto 0) := B"0010" ;
-constant a_dfv  : bit_vector (3 downto 0) := B"0011" ;
-constant a_and  : bit_vector (3 downto 0) := B"0100" ;
-constant a_or   : bit_vector (3 downto 0) := B"0101" ;
-constant a_xor  : bit_vector (3 downto 0) := B"0110" ;
-constant a_sll  : bit_vector (3 downto 0) := B"0111" ;
-constant a_srl  : bit_vector (3 downto 0) := B"1000" ;
-constant a_sra  : bit_vector (3 downto 0) := B"1001" ;
-constant a_seq  : bit_vector (3 downto 0) := B"1010" ;
-constant a_sne  : bit_vector (3 downto 0) := B"1011" ;
-constant a_sge  : bit_vector (3 downto 0) := B"1100" ;
-constant a_sgt  : bit_vector (3 downto 0) := B"1101" ;
-constant a_sle  : bit_vector (3 downto 0) := B"1110" ;
-constant a_slt  : bit_vector (3 downto 0) := B"1111" ;
-
-constant r_no   : bit_vector (3 downto 0) := B"0000" ;
-constant r_pc   : bit_vector (3 downto 0) := B"0001" ;
-constant r_ad   : bit_vector (3 downto 0) := B"0010" ;
-constant r_rd   : bit_vector (3 downto 0) := B"0100" ;
-constant r_31   : bit_vector (3 downto 0) := B"0101" ;
-constant r_ia   : bit_vector (3 downto 0) := B"1000" ;
-constant r_si   : bit_vector (3 downto 0) := B"1001" ;
-constant r_tv   : bit_vector (3 downto 0) := B"1010" ;
-constant r_sr   : bit_vector (3 downto 0) := B"1100" ;
-constant r_ss   : bit_vector (3 downto 0) := B"1101" ;
-
-constant m_no   : bit_vector (3 downto 0) := B"0011" ;
-constant m_fch  : bit_vector (3 downto 0) := B"1010" ;
-constant m_rw   : bit_vector (3 downto 0) := B"0010" ;
-constant m_ww   : bit_vector (3 downto 0) := B"0000" ;
-constant m_rb   : bit_vector (3 downto 0) := B"0110" ;
-constant m_wb   : bit_vector (3 downto 0) := B"0100" ;
-
-constant s_bo16 : bit_vector (2 downto 0) := B"000" ;
-constant s_bo4  : bit_vector (2 downto 0) := B"001" ;
-constant s_bi8  : bit_vector (2 downto 0) := B"010" ;
-constant s_sb   : bit_vector (2 downto 0) := B"011" ;
-constant s_lb   : bit_vector (2 downto 0) := B"100" ;
-constant s_nul  : bit_vector (2 downto 0) := B"101" ;
-constant s_strt : bit_vector (2 downto 0) := B"110" ;
-
-begin
-
-	-- ###--------------------------------------------------------###
-	-- #   checking power supplies					#
-	-- ###--------------------------------------------------------###
-
-power : assert ((VDD and VDDP) = '1' and (VSS or VSSP) = '0')
-        report  "power supply missing on `dlx_m` processor"
-        severity WARNING;
-
-	-- ###--------------------------------------------------------###
-	-- #   internal clocks						#
-	-- ###--------------------------------------------------------###
-
-CKFRZ_S  <= CK and not FRZ;
-CK_S     <= CK            ;
-CKDLY0_S <= CK            ;
-CKDLY1_S <= CKDLY0_S      ;
-CKDLY2_S <= CKDLY1_S      ;
-CKDLY3_S <= CKDLY2_S      ;
-CKDLY4_S <= CKDLY3_S      ;
-CKDLY5_S <= CKDLY4_S      ;
-CKDLY6_S <= CKDLY5_S      ;
-
-	-- ###--------------------------------------------------------###
-	-- #   hardware interrupt requests				#
-	-- #     - interrupt request					#
-	-- #     - exception request					#
-	-- #     - global interrupt request signal			#
-	-- ###--------------------------------------------------------###
-
-INTRQS_X <= (IT_R (0) or IT_R (1) or IT_R (2) or IT_R (3)) and SR_R (1);
-
-EXCRQS_X <= OVRFLO_X or             OVR_R or
-            DAALGN_X or DASGMT_X or DAV_R or
-            OPVIOL_X or ILLINS_X or ICO_R or
-            IAALGN_X or IASGMT_X or IAV_R ;
-
-RQS_X   <= INTRQS_X or EXCRQS_X or CPURST_R;
-
-	-- ###--------------------------------------------------------###
-	-- #   extract control fields from the micro-instruction	#
-	-- # register							#
-	-- ###--------------------------------------------------------###
-
-CTLEXC_S <= MICINS_R (          26);
-CTLOPX_S <= MICINS_R (25 downto 22);
-CTLOPY_S <= MICINS_R (21 downto 19);
-CTLALU_S <= MICINS_R (18 downto 15);
-CTLRES_S <= MICINS_R (14 downto 11);
-CTLMEM_S <= MICINS_R (10 downto  7);
-CTLSEQ_S <= MICINS_R ( 6 downto  4);
-CTLDAT_S <= MICINS_R ( 3 downto  0);
-
-	-- ###--------------------------------------------------------###
-	-- #   extract the operation code from the instruction		#
-	-- ###--------------------------------------------------------###
-
-OPCOD_S  <= IR_R (31 downto 26) ;
-
-	-- ###--------------------------------------------------------###
-	-- #   detect privileged instructions				#
-	-- ###--------------------------------------------------------###
-
-with OPCOD_S select
-PRVINS_X <= '1' when rfe_i | movi2s_i | movs2i_i ,
-            '0' when others                      ;
-
-	-- ###--------------------------------------------------------###
-	-- #   compute next micro-instruction's address			#
-	-- ###--------------------------------------------------------###
-
-SHRTBCH_S <= MICADR_R (6) & CTLDAT_S (3) & CTLDAT_S (2) &
-             MICADR_R (3) & CTLDAT_S (1) & CTLDAT_S (0) & '0';
-
-LONGBCH_S <= CTLDAT_S (3) & CTLDAT_S (2) & CTLDAT_S (1) &
-             CTLDAT_S (0) & MICADR_R (2) & MICADR_R (1) & '0';
-
-STRTADR_S <= '1'          & '1'          & CTLDAT_S (2) &
-             CTLDAT_S (1) & CTLDAT_S (0) & RQS_X        & '0';
-
-BCHNUL_S  <= MICADR_R (6) & RESNUL_S     & CTLDAT_S (2) &
-             MICADR_R (3) & CTLDAT_S (1) & CTLDAT_S (0) & '0';
-
-BCHOP4_S  <= MICADR_R (6) & MICADR_R (5) & MICADR_R (4) &
-             MICADR_R (3) & OPCOD_S  (1) & OPCOD_S  (0) & '1';
-
-BCHOP16_S <= OPCOD_S  (5) & OPCOD_S  (4) & OPCOD_S  (3) &
-             OPCOD_S  (2) & '0'          & '0'          & '0';
-
-BCHIN8_S  <= CTLDAT_S (2) & IR_R     (2) & IR_R     (1) &
-             CTLDAT_S (1) & IR_R     (0) & CTLDAT_S (0) & '0';
-
-with CTLSEQ_S select
-MICADR_S <= SHRTBCH_S  when s_sb  ,
-            LONGBCH_S  when s_lb  ,
-            STRTADR_S  when s_strt,
-            BCHNUL_S   when s_nul ,
-            BCHOP4_S   when s_bo4 ,
-            BCHOP16_S  when s_bo16,
-            BCHIN8_S   when s_bi8 ,
-            "000_0000" when others;
-
-	-- ###--------------------------------------------------------###
-	-- #   read the next micro-instruction from the control store	#
-	-- ###--------------------------------------------------------###
-
-with "0" & MICADR_S (6 downto 0) select
-MICINS_S <=
-
-  e_no & x_rt & y_c0  & a_sum & r_ad & m_no  & s_bo4  & X"0" when X"00",-- rdrt
-  e_no & x_rs & y_ad  & a_smv & r_rd & m_fch & s_strt & X"7" when X"01",-- add
-  e_no & x_rs & y_ad  & a_dfv & r_rd & m_fch & s_strt & X"7" when X"05",-- sub
-  e_no & x_rs & y_c0  & a_sum & r_ia & m_fch & s_strt & X"7" when X"06",-- i2ia
-
-  e_no & x_c0 & y_i16 & a_sum & r_ad & m_no  & s_bo4  & X"0" when X"08",-- rdsi
-  e_no & x_rs & y_ad  & a_smv & r_rd & m_fch & s_strt & X"7" when X"09",-- add
-  e_no & x_rs & y_ad  & a_dfv & r_rd & m_fch & s_strt & X"7" when X"0d",-- sub
-  e_no & x_ia & y_c0  & a_sum & r_rd & m_fch & s_strt & X"7" when X"0e",-- ia2i
-
-  e_no & x_rt & y_c0  & a_sum & r_ad & m_no  & s_bo4  & X"0" when X"10",-- rdrt
-  e_no & x_rs & y_ad  & a_sll & r_rd & m_fch & s_strt & X"7" when X"11",-- sll
-  e_no & x_rs & y_c0  & a_sum & r_sr & m_fch & s_strt & X"7" when X"12",-- i2sr
-  e_no & x_rs & y_ad  & a_srl & r_rd & m_fch & s_strt & X"7" when X"13",-- srl
-  e_no & x_rs & y_ad  & a_sra & r_rd & m_fch & s_strt & X"7" when X"15",-- sra
-
-  e_no & x_c0 & y_i16 & a_sum & r_ad & m_no  & s_bo4  & X"0" when X"18",-- rdsi
-  e_no & x_rs & y_ad  & a_sll & r_rd & m_fch & s_strt & X"7" when X"19",-- sll
-  e_no & x_sr & y_c0  & a_sum & r_rd & m_fch & s_strt & X"7" when X"1a",-- sr2i
-  e_no & x_rs & y_ad  & a_srl & r_rd & m_fch & s_strt & X"7" when X"1b",-- srl
-  e_no & x_rs & y_ad  & a_sra & r_rd & m_fch & s_strt & X"7" when X"1d",-- sra
-  e_no & x_ad & y_c16 & a_sll & r_rd & m_fch & s_strt & X"7" when X"1f",-- lhi
-
-  e_no & x_rt & y_c0  & a_sum & r_ad & m_no  & s_bo4  & X"0" when X"20",-- rdrt
-  e_no & x_rs & y_ad  & a_seq & r_rd & m_fch & s_strt & X"7" when X"21",-- seq
-  e_no & x_rs & y_c0  & a_sum & r_tv & m_fch & s_strt & X"7" when X"22",-- i2tv
-  e_no & x_rs & y_ad  & a_sne & r_rd & m_fch & s_strt & X"7" when X"23",-- sne
-  e_no & x_rs & y_ad  & a_sge & r_rd & m_fch & s_strt & X"7" when X"25",-- sge
-  e_no & x_rs & y_ad  & a_sle & r_rd & m_fch & s_strt & X"7" when X"27",-- sle
-
-  e_no & x_c0 & y_i16 & a_sum & r_ad & m_no  & s_bo4  & X"0" when X"28",-- rdsi
-  e_no & x_rs & y_ad  & a_seq & r_rd & m_fch & s_strt & X"7" when X"29",-- seq
-  e_no & x_tv & y_c0  & a_sum & r_rd & m_fch & s_strt & X"7" when X"2a",-- tv2i
-  e_no & x_rs & y_ad  & a_sne & r_rd & m_fch & s_strt & X"7" when X"2b",-- sne
-  e_no & x_rs & y_ad  & a_sge & r_rd & m_fch & s_strt & X"7" when X"2d",-- sge
-  e_no & x_rs & y_ad  & a_sle & r_rd & m_fch & s_strt & X"7" when X"2f",-- sle
-
-  e_no & x_rt & y_c0  & a_sum & r_ad & m_no  & s_bo4  & X"0" when X"30",-- rdrt
-  e_no & x_rs & y_ad  & a_sgt & r_rd & m_fch & s_strt & X"7" when X"35",-- sgt
-  e_no & x_rs & y_ad  & a_slt & r_rd & m_fch & s_strt & X"7" when X"37",-- slt
-
-  e_no & x_c0 & y_i16 & a_sum & r_ad & m_no  & s_bo4  & X"0" when X"38",-- rdsi
-  e_no & x_rs & y_ad  & a_sgt & r_rd & m_fch & s_strt & X"7" when X"3d",-- sgt
-  e_no & x_rs & y_ad  & a_slt & r_rd & m_fch & s_strt & X"7" when X"3f",-- slt
-
-  e_no & x_rt & y_c0  & a_sum & r_ad & m_no  & s_bo4  & X"0" when X"40",-- rdrt
-  e_no & x_rs & y_ad  & a_and & r_rd & m_fch & s_strt & X"7" when X"41",-- and
-  e_no & x_rs & y_ad  & a_or  & r_rd & m_fch & s_strt & X"7" when X"43",-- or
-  e_no & x_c0 & y_c0  & a_sum & r_no & m_fch & s_strt & X"7" when X"44",-- ftch
-  e_no & x_rs & y_ad  & a_xor & r_rd & m_fch & s_strt & X"7" when X"47",-- xor
-
-  e_no & x_ch & y_i16 & a_and & r_ad & m_no  & s_bo4  & X"0" when X"48",-- rdui
-  e_no & x_rs & y_ad  & a_and & r_rd & m_fch & s_strt & X"7" when X"49",-- and
-  e_no & x_pc & y_i18 & a_sum & r_pc & m_no  & s_sb   & X"9" when X"4a",-- brch
-  e_no & x_rs & y_ad  & a_or  & r_rd & m_fch & s_strt & X"7" when X"4b",-- or
-  e_no & x_c0 & y_c0  & a_sum & r_no & m_fch & s_strt & X"7" when X"4c",-- ftch
-  e_no & x_rs & y_ad  & a_xor & r_rd & m_fch & s_strt & X"7" when X"4f",-- xor
-
-  e_no & x_rs & y_i16 & a_sum & r_ad & m_no  & s_bo4  & X"0" when X"50",-- rssi
-  e_no & x_rt & y_c0  & a_sum & r_no & m_ww  & s_sb   & X"2" when X"51",-- sw0
-  e_no & x_rt & y_c0  & a_sum & r_no & m_wb  & s_sb   & X"2" when X"55",-- sb0
-  e_no & x_cb & y_dt  & a_and & r_rd & m_fch & s_strt & X"7" when X"56",-- lbu1
-  e_no & x_c0 & y_c0  & a_sum & r_no & m_rb  & s_sb   & X"7" when X"57",-- lbu0
-
-  e_no & x_rs & y_i16 & a_sum & r_ad & m_no  & s_bo4  & X"0" when X"58",-- rssi
-  e_no & x_c0 & y_c0  & a_sum & r_no & m_rw  & s_sb   & X"5" when X"59",-- lw0
-  e_no & x_c0 & y_dt  & a_sum & r_rd & m_fch & s_strt & X"7" when X"5a",-- lw1
-  e_no & x_c0 & y_c16 & a_dif & r_pc & m_no  & s_sb   & X"9" when X"5e",-- req2
-
-  e_no & x_c0 & y_c0  & a_sum & r_no & m_no  & s_bo4  & X"0" when X"60",-- nop
-  e_no & x_rs & y_c0  & a_sum & r_pc & m_no  & s_sb   & X"2" when X"61",-- jr0
-  e_no & x_pc & y_c0  & a_sum & r_31 & m_no  & s_sb   & X"a" when X"63",-- jlr0
-  e_no & x_rs & y_c0  & a_sum & r_pc & m_no  & s_sb   & X"2" when X"64",-- jlr1
-  e_no & x_c0 & y_c0  & a_sum & r_no & m_no  & s_bi8  & X"3" when X"65",-- mvi0
-  e_no & x_c0 & y_c0  & a_sum & r_no & m_no  & s_bi8  & X"1" when X"67",-- mvs0
-
-  e_no & x_c0 & y_c0  & a_sum & r_no & m_no  & s_bo4  & X"0" when X"68",-- nop
-  e_no & x_rs & y_c0  & a_sum & r_no & m_no  & s_nul  & X"2" when X"69",-- beq0
-  e_no & x_c0 & y_c0  & a_sum & r_no & m_fch & s_strt & X"7" when X"6a",-- ftch
-  e_no & x_rs & y_c0  & a_sum & r_no & m_no  & s_nul  & X"1" when X"6b",-- bne0
-  e_no & x_pc & y_i18 & a_sum & r_pc & m_no  & s_sb   & X"2" when X"6c",-- brch
-  e_no & x_sr & y_c16 & a_sll & r_ss & m_no  & s_sb   & X"7" when X"6e",-- req1
-
-  e_no & x_c0 & y_c0  & a_sum & r_no & m_no  & s_bo4  & X"0" when X"70",-- nop
-  e_no & x_pc & y_i28 & a_sum & r_pc & m_no  & s_sb   & X"2" when X"71",-- j0
-  e_no & x_pc & y_c0  & a_sum & r_31 & m_no  & s_sb   & X"e" when X"73",-- jl0
-  e_no & x_pc & y_i28 & a_sum & r_pc & m_no  & s_sb   & X"2" when X"74",-- jl1
-  e_no & x_ia & y_c0  & a_sum & r_pc & m_no  & s_sb   & X"f" when X"75",-- rfe0
-  e_no & x_sr & y_c16 & a_srl & r_sr & m_no  & s_sb   & X"2" when X"76",-- rfe1
-  e_no & x_c0 & y_i28 & a_sum & r_tv & m_no  & s_lb   & X"f" when X"77",-- trp0
-
-  e_no & x_pc & y_c4  & a_sum & r_pc & m_no  & s_bo16 & X"0" when X"7c",-- init
-  e_no & x_pc & y_c0  & a_sum & r_si & m_no  & s_sb   & X"b" when X"7e",-- req0
-
-  e_il & x_c0 & y_c0  & a_sum & r_no & m_no  & s_strt & X"0" when others;
-
-	-- ###--------------------------------------------------------###
-	-- #   define the micro-instruction's value in case of reset	#
-	-- ###--------------------------------------------------------###
-
-  RESTMI_X <= e_no & x_c0 & y_c0 & a_sum & r_no & m_fch & s_strt & X"7";
-
-	-- ###--------------------------------------------------------###
-	-- #   assign micro-instruction and micro-instruction's address	#
-	-- # registers							#
-	-- #     - in any case if the firmware is not freezed save	#
-	-- #       the address in the address register			#
-	-- #								#
-	-- #     - if the firmware is not freezed depending on the	#
-	-- #       reset condition write either the output of the	#
-	-- #       micro-ROM or the reset micro-instruction in the	#
-	-- #       register						#
-	-- ###--------------------------------------------------------###
-
-mic_ins : block (CKFRZ_S = '0' and not CKFRZ_S'STABLE)
-begin
- MICADR_R <= guarded MICADR_S ;
-
- MICINS_R <= guarded RESTMI_X when (RESET_R = '1') else
-                     MICINS_S ;
-end block ;
-
-	-- ###--------------------------------------------------------###
-	-- #   extract the immediate from in the instruction register	#
-	-- #								#
-	-- #     imd16 : 16-bit immediate with sign extension		#
-	-- #     imd18 : 16-bit short branch offset with sign extension	#
-	-- #     imd28 : 26-bit long  branch offset with sign extension	#
-	-- ###--------------------------------------------------------###
-
-IMD16_S (15 downto  0) <= IR_R (15 downto 0) ;
-IMD16_S (31 downto 16) <= X"ffff" when (IR_R (15) = '1') else
-                          X"0000" ;
-
-IMD18_S (17 downto  0) <= IR_R (15 downto 0) & B"00";
-IMD18_S (31 downto 18) <= X"fff" & B"11" when (IR_R (15) = '1') else
-                          X"000" & B"00" ;
-
-IMD28_S (27 downto  0) <= IR_R (25 downto 0) & B"00";
-IMD28_S (31 downto 28) <= X"f" when (IR_R (25) = '1') else
-                          X"0" ;
-
-	-- ###--------------------------------------------------------###
-	-- #   i format instructions					#
-	-- ###--------------------------------------------------------###
-
-with OPCOD_S select
-IFORMT_S <= '1' when addi_i | subi_i |
-                     slli_i | srli_i | srai_i   | lhi_i    |
-                     seqi_i | snei_i | sgei_i   | slei_i   |
-                     sgti_i | slti_i |
-                     andi_i | ori_i  | xori_i   |
-                     sw_i   | sb_i   | lbu_i    |
-                     lw_i   |
-                     beqz_i | bnez_i                       ,
-            '0' when others                                ;
-
-	-- ###--------------------------------------------------------###
-	-- #   read and write pointers from register file		#
-	-- ###--------------------------------------------------------###
-
-WRTPNT_S <= B"11111"            when (CTLRES_S = r_31) else
-            IR_R (20 downto 16) when (IFORMT_S = '1'  ) else
-            IR_R (15 downto 11) ;
-
-with CTLOPX_S select
-REDPNT_S <= IR_R (25 downto 21) when x_rs  ,
-            IR_R (20 downto 16) when others;
-
-	-- ###--------------------------------------------------------###
-	-- #   register read from the register file			#
-	-- ###--------------------------------------------------------###
-
-with REDPNT_S select
-REDREG_S <= R0_R  when B"00000" ,
-            R1_R  when B"00001" ,
-            R2_R  when B"00010" ,
-            R3_R  when B"00011" ,
-            R4_R  when B"00100" ,
-            R5_R  when B"00101" ,
-            R6_R  when B"00110" ,
-            R7_R  when B"00111" ,
-            R8_R  when B"01000" ,
-            R9_R  when B"01001" ,
-            R10_R when B"01010" ,
-            R11_R when B"01011" ,
-            R12_R when B"01100" ,
-            R13_R when B"01101" ,
-            R14_R when B"01110" ,
-            R15_R when B"01111" ,
-            R16_R when B"10000" ,
-            R17_R when B"10001" ,
-            R18_R when B"10010" ,
-            R19_R when B"10011" ,
-            R20_R when B"10100" ,
-            R21_R when B"10101" ,
-            R22_R when B"10110" ,
-            R23_R when B"10111" ,
-            R24_R when B"11000" ,
-            R25_R when B"11001" ,
-            R26_R when B"11010" ,
-            R27_R when B"11011" ,
-            R28_R when B"11100" ,
-            R29_R when B"11101" ,
-            R30_R when B"11110" ,
-            R31_R when B"11111" ;
-
-	-- ###--------------------------------------------------------###
-	-- #   x and y operands						#
-	-- ###--------------------------------------------------------###
-
-with CTLOPX_S select
-OPERX_S <= REDREG_S when x_rs   ,
-           REDREG_S when x_rt   ,
-           PC_R     when x_pc   ,
-           AD_R     when x_ad   ,
-           SR_R     when x_sr   ,
-           IAR_R    when x_ia   ,
-           TVR_R    when x_tv   ,
-           c0       when x_c0   ,
-           cb       when x_cb   ,
-           ch       when x_ch   ,
-           c0       when others ;
-
-with CTLOPY_S select
-OPERY_S <= IMD16_S when y_i16  ,
-           IMD18_S when y_i18  ,
-           IMD28_S when y_i28  ,
-           DT_R    when y_dt   ,
-           AD_R    when y_ad   ,
-           c0      when y_c0   ,
-           c4      when y_c4   ,
-           c16     when y_c16  ,
-           c0      when others ;
-
-	-- ###--------------------------------------------------------###
-	-- #   adder's x and y operands					#
-	-- ###--------------------------------------------------------###
-
-ADDX_S <= OPERX_S;
-
-with CTLALU_S select
-ADDY_S (31 downto 0) <=      OPERY_S  when a_sum | a_smv,
-                        not (OPERY_S) when others;
-
-	-- ###--------------------------------------------------------###
-	-- #   adder's carry and result					#
-	-- ###--------------------------------------------------------###
-
-with CTLALU_S select
-ADDCRY_S (0) <= '0'  when a_sum | a_smv,
-                '1'  when others;
-
-ADDCRY_S (32 downto 1) <= (ADDX_S and ADDY_S                ) or
-                          (ADDX_S and ADDCRY_S (31 downto 0)) or
-                          (ADDY_S and ADDCRY_S (31 downto 0)) ;
-
-ADDRES_S <=  ADDX_S xor ADDY_S xor ADDCRY_S (31 downto 0);
-
-	-- ###--------------------------------------------------------###
-	-- #   adder's overflow						#
-	-- ###--------------------------------------------------------###
-
-ADDOVR_S <= ADDCRY_S (32) xor ADDCRY_S (31);
-
-	-- ###--------------------------------------------------------###
-	-- #   test and set bits :					#
-	-- #     seq : x  = y						#
-	-- ###--------------------------------------------------------###
-
-  SEQ_S <= '1' when (ADDRES_S = X"00000000") else
-           '0' ;
-
-  SGT_S <= '1' when ((OPERX_S (31) xor OPERY_S (31) ='0') and
-                     (ADDRES_S (31) = '0') and (SEQ_S = '0')) else
-         '1' when (OPERX_S (31) = '0' and OPERY_S (31) = '1')  else
-         '0' ;
-
-  SNE_S <= not (SEQ_S) ;
-  SGE_S <=      SEQ_S or SGT_S;
-  SLE_S <=      SEQ_S or SLT_S;
-  SLT_S <= not (SGE_S);
-
-	-- ###--------------------------------------------------------###
-	-- #   shifter							#
-	-- ###--------------------------------------------------------###
-
-  SHIN_S   <= X"00000000" when CTLALU_S     = a_srl else	-- logical
-              X"ffffffff" when OPERX_S (31) = '1'   else	-- arithm.
-              X"00000000" ;					-- arithm.
-
-  with OPERY_S (4 downto 0) select
-  SHLFT_S <= OPERX_S (31 downto 0)                     when B"00000" ,
-             OPERX_S (30 downto 0) & c0 (31)           when B"00001" ,
-             OPERX_S (29 downto 0) & c0 (31 downto 30) when B"00010" ,
-             OPERX_S (28 downto 0) & c0 (31 downto 29) when B"00011" ,
-             OPERX_S (27 downto 0) & c0 (31 downto 28) when B"00100" ,
-             OPERX_S (26 downto 0) & c0 (31 downto 27) when B"00101" ,
-             OPERX_S (25 downto 0) & c0 (31 downto 26) when B"00110" ,
-             OPERX_S (24 downto 0) & c0 (31 downto 25) when B"00111" ,
-             OPERX_S (23 downto 0) & c0 (31 downto 24) when B"01000" ,
-             OPERX_S (22 downto 0) & c0 (31 downto 23) when B"01001" ,
-             OPERX_S (21 downto 0) & c0 (31 downto 22) when B"01010" ,
-             OPERX_S (20 downto 0) & c0 (31 downto 21) when B"01011" ,
-             OPERX_S (19 downto 0) & c0 (31 downto 20) when B"01100" ,
-             OPERX_S (18 downto 0) & c0 (31 downto 19) when B"01101" ,
-             OPERX_S (17 downto 0) & c0 (31 downto 18) when B"01110" ,
-             OPERX_S (16 downto 0) & c0 (31 downto 17) when B"01111" ,
-             OPERX_S (15 downto 0) & c0 (31 downto 16) when B"10000" ,
-             OPERX_S (14 downto 0) & c0 (31 downto 15) when B"10001" ,
-             OPERX_S (13 downto 0) & c0 (31 downto 14) when B"10010" ,
-             OPERX_S (12 downto 0) & c0 (31 downto 13) when B"10011" ,
-             OPERX_S (11 downto 0) & c0 (31 downto 12) when B"10100" ,
-             OPERX_S (10 downto 0) & c0 (31 downto 11) when B"10101" ,
-             OPERX_S (9  downto 0) & c0 (31 downto 10) when B"10110" ,
-             OPERX_S (8  downto 0) & c0 (31 downto  9) when B"10111" ,
-             OPERX_S (7  downto 0) & c0 (31 downto  8) when B"11000" ,
-             OPERX_S (6  downto 0) & c0 (31 downto  7) when B"11001" ,
-             OPERX_S (5  downto 0) & c0 (31 downto  6) when B"11010" ,
-             OPERX_S (4  downto 0) & c0 (31 downto  5) when B"11011" ,
-             OPERX_S (3  downto 0) & c0 (31 downto  4) when B"11100" ,
-             OPERX_S (2  downto 0) & c0 (31 downto  3) when B"11101" ,
-             OPERX_S (1  downto 0) & c0 (31 downto  2) when B"11110" ,
-             OPERX_S (0)           & c0 (31 downto  1) when B"11111" ;
-
-  with OPERY_S (4 downto 0) select
-  SHRIT_S <=                        OPERX_S (31 downto  0) when B"00000" ,
-             SHIN_S ( 0         ) & OPERX_S (31 downto  1) when B"00001" ,
-             SHIN_S ( 1 downto 0) & OPERX_S (31 downto  2) when B"00010" ,
-             SHIN_S ( 2 downto 0) & OPERX_S (31 downto  3) when B"00011" ,
-             SHIN_S ( 3 downto 0) & OPERX_S (31 downto  4) when B"00100" ,
-             SHIN_S ( 4 downto 0) & OPERX_S (31 downto  5) when B"00101" ,
-             SHIN_S ( 5 downto 0) & OPERX_S (31 downto  6) when B"00110" ,
-             SHIN_S ( 6 downto 0) & OPERX_S (31 downto  7) when B"00111" ,
-             SHIN_S ( 7 downto 0) & OPERX_S (31 downto  8) when B"01000" ,
-             SHIN_S ( 8 downto 0) & OPERX_S (31 downto  9) when B"01001" ,
-             SHIN_S ( 9 downto 0) & OPERX_S (31 downto 10) when B"01010" ,
-             SHIN_S (10 downto 0) & OPERX_S (31 downto 11) when B"01011" ,
-             SHIN_S (11 downto 0) & OPERX_S (31 downto 12) when B"01100" ,
-             SHIN_S (12 downto 0) & OPERX_S (31 downto 13) when B"01101" ,
-             SHIN_S (13 downto 0) & OPERX_S (31 downto 14) when B"01110" ,
-             SHIN_S (14 downto 0) & OPERX_S (31 downto 15) when B"01111" ,
-             SHIN_S (15 downto 0) & OPERX_S (31 downto 16) when B"10000" ,
-             SHIN_S (16 downto 0) & OPERX_S (31 downto 17) when B"10001" ,
-             SHIN_S (17 downto 0) & OPERX_S (31 downto 18) when B"10010" ,
-             SHIN_S (18 downto 0) & OPERX_S (31 downto 19) when B"10011" ,
-             SHIN_S (19 downto 0) & OPERX_S (31 downto 20) when B"10100" ,
-             SHIN_S (20 downto 0) & OPERX_S (31 downto 21) when B"10101" ,
-             SHIN_S (21 downto 0) & OPERX_S (31 downto 22) when B"10110" ,
-             SHIN_S (22 downto 0) & OPERX_S (31 downto 23) when B"10111" ,
-             SHIN_S (23 downto 0) & OPERX_S (31 downto 24) when B"11000" ,
-             SHIN_S (24 downto 0) & OPERX_S (31 downto 25) when B"11001" ,
-             SHIN_S (25 downto 0) & OPERX_S (31 downto 26) when B"11010" ,
-             SHIN_S (26 downto 0) & OPERX_S (31 downto 27) when B"11011" ,
-             SHIN_S (27 downto 0) & OPERX_S (31 downto 28) when B"11100" ,
-             SHIN_S (28 downto 0) & OPERX_S (31 downto 29) when B"11101" ,
-             SHIN_S (29 downto 0) & OPERX_S (31 downto 30) when B"11110" ,
-             SHIN_S (30 downto 0) & OPERX_S (31)           when B"11111" ;
-
-	-- ###--------------------------------------------------------###
-	-- #   result out of alu					#
-	-- ###--------------------------------------------------------###
-
-  with CTLALU_S select
-  RESULT_S <= ADDRES_S                  when a_sum | a_smv,
-              ADDRES_S                  when a_dif | a_dfv,
-              OPERX_S and OPERY_S       when a_and        ,
-              OPERX_S or  OPERY_S       when a_or         ,
-              OPERX_S xor OPERY_S       when a_xor        ,
-              SHLFT_S                   when a_sll        ,
-              SHRIT_S                   when a_srl        ,
-              SHRIT_S                   when a_sra        ,
-              c0 (31 downto 1) & SEQ_S  when a_seq        ,
-              c0 (31 downto 1) & SNE_S  when a_sne        ,
-              c0 (31 downto 1) & SGE_S  when a_sge        ,
-              c0 (31 downto 1) & SGT_S  when a_sgt        ,
-              c0 (31 downto 1) & SLE_S  when a_sle        ,
-              c0 (31 downto 1) & SLT_S  when a_slt        ,
-              c0                        when others       ;
-
-	-- ###--------------------------------------------------------###
-	-- #   checking the result out of alu				#
-	-- ###--------------------------------------------------------###
-
-RESNUL_S <= '1' when (RESULT_S = X"00000000") else
-            '0' ;
-
-	-- ###--------------------------------------------------------###
-	-- #   external storage access :				#
-	-- #     - access type (word, byte)				#
-	-- #     - valid bytes						#
-	-- ###--------------------------------------------------------###
-
-WORD_S <= '1' when (CTLMEM_S = m_fch or CTLMEM_S = m_rw or CTLMEM_S = m_ww) else
-          '0' ;
-
-BYTE_S <= '1' when (CTLMEM_S = m_rb  or CTLMEM_S = m_wb                   ) else
-          '0' ;
-
-BYTSEL_S <= "1111" when (WORD_S = '1'                             ) else
-            "0001" when (BYTE_S = '1' and AD_R (1 downto 0) = "11") else
-            "0010" when (BYTE_S = '1' and AD_R (1 downto 0) = "10") else
-            "0100" when (BYTE_S = '1' and AD_R (1 downto 0) = "01") else
-            "1000" when (BYTE_S = '1' and AD_R (1 downto 0) = "00") else
-            "0000" ;
-
-	-- ###--------------------------------------------------------###
-	-- #   data from external storage read and aligned		#
-	-- ###--------------------------------------------------------###
-
-REDDAT_S (31 downto 8) <= DATA (31 downto  8) ;
-REDDAT_S ( 7 downto 0) <= DATA ( 7 downto  0) when (BYTSEL_S (3) = '1') else
-                          DATA (15 downto  8) when (BYTSEL_S (2) = '1') else
-                          DATA (23 downto 16) when (BYTSEL_S (1) = '1') else
-                          DATA (31 downto 24) ;
-
-	-- ###--------------------------------------------------------###
-	-- #   prepare the new status to be written into the 16 least	#
-	-- # significant bits of sr in case of interruption or exception#
-	-- ###--------------------------------------------------------###
-
-NEWSR_X <= IT_R & OVR_R & DAV_R & ICO_R & IAV_R & "0000" & CPURST_R & "000";
-
-	-- ###--------------------------------------------------------###
-	-- #   registers' write enable					#
-	-- ###--------------------------------------------------------###
-
-with CTLRES_S select
-WENSR_S  <= not EXCRQS_X when r_sr  ,
-            '1'          when r_ss  ,
-            '0'          when others;
-
-with CTLRES_S select
-WENIAR_S <= not EXCRQS_X when r_ia  ,
-            '1'          when r_si  ,
-            '0'          when others;
-
-WENTVR_S <= not EXCRQS_X when (CTLRES_S = r_tv                    ) else
-            '0'          ;
-WENPC_S  <= not EXCRQS_X when (CTLRES_S = r_pc                    ) else
-            '0'          ;
-WENAD_S  <= not EXCRQS_X when (CTLRES_S = r_ad                    ) else
-            '0'          ;
-WENREG_S <= not EXCRQS_X when (CTLRES_S = r_rd  or CTLRES_S = r_31) else
-            '0'          ;
-WENDT_S  <= not EXCRQS_X when (CTLMEM_S = m_rw  or CTLMEM_S = m_rb) else
-            '0'          ;
-WENIR_S  <= not EXCRQS_X when (CTLMEM_S = m_fch                   ) else
-            '0'          ;
-
-	-- ###--------------------------------------------------------###
-	-- #   write the result into registers :			#
-	-- #     sr  : status register					#
-	-- #     iar : interrupt address register			#
-	-- #     tvr : trap vector register				#
-	-- #     pc  : program counter					#
-	-- #     ad  : internal address register			#
-	-- ###--------------------------------------------------------###
-
-status : block (CKFRZ_S = '0' and not CKFRZ_S'STABLE and WENSR_S = '1')
-begin
-  SR_R <= guarded RESULT_S (31 downto  0)           when CTLRES_S = r_sr else
-                  RESULT_S (31 downto 16) & NEWSR_X;
-end block;
-
-it_adr : block (CKFRZ_S = '0' and not CKFRZ_S'STABLE and WENIAR_S = '1')
-begin
-  IAR_R <= guarded RESULT_S;
-end block;
-
-trap_v : block (CKFRZ_S = '0' and not CKFRZ_S'STABLE and WENTVR_S = '1')
-begin
-  TVR_R <= guarded RESULT_S;
-end block;
-
-prg_cnt : block (CKFRZ_S = '0' and not CKFRZ_S'STABLE and WENPC_S = '1')
-begin
-  PC_R <= guarded RESULT_S;
-end block;
-
-address : block (CKFRZ_S = '0' and not CKFRZ_S'STABLE and WENAD_S = '1')
-begin
-  AD_R <= guarded RESULT_S;
-end block;
-
-	-- ###--------------------------------------------------------###
-	-- #   write the value read on data bus into registers :	#
-	-- #     dt  : data register					#
-	-- #     ir  : instruction register				#
-	-- ###--------------------------------------------------------###
-
-data_in : block (CKFRZ_S = '0' and not CKFRZ_S'STABLE and WENDT_S = '1')
-begin
-  DT_R <= guarded REDDAT_S;
-end block ;
-
-instruc : block (CKFRZ_S = '0' and not CKFRZ_S'STABLE and WENIR_S = '1')
-begin
-  IR_R  <= guarded REDDAT_S;
-end block ;
-
-	-- ###--------------------------------------------------------###
-	-- #   write integre registers					#
-	-- ###--------------------------------------------------------###
-
-r1  : block (CKFRZ_S  = '0' and not CKFRZ_S'STABLE and WRTPNT_S = "00001" and
-             WENREG_S = '1')
-begin
-  R1_R  <= guarded RESULT_S;
-end block;
-
-r2  : block (CKFRZ_S  = '0' and not CKFRZ_S'STABLE and WRTPNT_S = "00010" and
-             WENREG_S = '1')
-begin
-  R2_R  <= guarded RESULT_S;
-end block;
-
-r3  : block (CKFRZ_S  = '0' and not CKFRZ_S'STABLE and WRTPNT_S = "00011" and
-             WENREG_S = '1')
-begin
-  R3_R  <= guarded RESULT_S;
-end block;
-
-r4  : block (CKFRZ_S  = '0' and not CKFRZ_S'STABLE and WRTPNT_S = "00100" and
-             WENREG_S = '1')
-begin
-  R4_R  <= guarded RESULT_S;
-end block;
-
-r5  : block (CKFRZ_S  = '0' and not CKFRZ_S'STABLE and WRTPNT_S = "00101" and
-             WENREG_S = '1')
-begin
-  R5_R  <= guarded RESULT_S;
-end block;
-
-r6  : block (CKFRZ_S  = '0' and not CKFRZ_S'STABLE and WRTPNT_S = "00110" and
-             WENREG_S = '1')
-begin
-  R6_R  <= guarded RESULT_S;
-end block;
-
-r7  : block (CKFRZ_S  = '0' and not CKFRZ_S'STABLE and WRTPNT_S = "00111" and
-             WENREG_S = '1')
-begin
-  R7_R  <= guarded RESULT_S;
-end block;
-
-r8  : block (CKFRZ_S  = '0' and not CKFRZ_S'STABLE and WRTPNT_S = "01000" and
-             WENREG_S = '1')
-begin
-  R8_R  <= guarded RESULT_S;
-end block;
-
-r9  : block (CKFRZ_S  = '0' and not CKFRZ_S'STABLE and WRTPNT_S = "01001" and
-             WENREG_S = '1')
-begin
-  R9_R  <= guarded RESULT_S;
-end block;
-
-r10 : block (CKFRZ_S  = '0' and not CKFRZ_S'STABLE and WRTPNT_S = "01010" and
-             WENREG_S = '1')
-begin
-  R10_R <= guarded RESULT_S;
-end block;
-
-r11 : block (CKFRZ_S  = '0' and not CKFRZ_S'STABLE and WRTPNT_S = "01011" and
-             WENREG_S = '1')
-begin
-  R11_R <= guarded RESULT_S;
-end block;
-
-r12 : block (CKFRZ_S  = '0' and not CKFRZ_S'STABLE and WRTPNT_S = "01100" and
-             WENREG_S = '1')
-begin
-  R12_R <= guarded RESULT_S;
-end block;
-
-r13 : block (CKFRZ_S  = '0' and not CKFRZ_S'STABLE and WRTPNT_S = "01101" and
-             WENREG_S = '1')
-begin
-  R13_R <= guarded RESULT_S;
-end block;
-
-r14 : block (CKFRZ_S  = '0' and not CKFRZ_S'STABLE and WRTPNT_S = "01110" and
-             WENREG_S = '1')
-begin
-  R14_R <= guarded RESULT_S;
-end block;
-
-r15 : block (CKFRZ_S  = '0' and not CKFRZ_S'STABLE and WRTPNT_S = "01111" and
-             WENREG_S = '1')
-begin
-  R15_R <= guarded RESULT_S;
-end block;
-
-r16 : block (CKFRZ_S  = '0' and not CKFRZ_S'STABLE and WRTPNT_S = "10000" and
-             WENREG_S = '1')
-begin
-  R16_R <= guarded RESULT_S;
-end block;
-
-r17 : block (CKFRZ_S  = '0' and not CKFRZ_S'STABLE and WRTPNT_S = "10001" and
-             WENREG_S = '1')
-begin
-  R17_R <= guarded RESULT_S;
-end block;
-
-r18 : block (CKFRZ_S  = '0' and not CKFRZ_S'STABLE and WRTPNT_S = "10010" and
-             WENREG_S = '1')
-begin
-  R18_R <= guarded RESULT_S;
-end block;
-
-r19 : block (CKFRZ_S  = '0' and not CKFRZ_S'STABLE and WRTPNT_S = "10011" and
-             WENREG_S = '1')
-begin
-  R19_R <= guarded RESULT_S;
-end block;
-
-r20 : block (CKFRZ_S  = '0' and not CKFRZ_S'STABLE and WRTPNT_S = "10100" and
-             WENREG_S = '1')
-begin
-  R20_R <= guarded RESULT_S;
-end block;
-
-r21 : block (CKFRZ_S  = '0' and not CKFRZ_S'STABLE and WRTPNT_S = "10101" and
-             WENREG_S = '1')
-begin
-  R21_R <= guarded RESULT_S;
-end block;
-
-r22 : block (CKFRZ_S  = '0' and not CKFRZ_S'STABLE and WRTPNT_S = "10110" and
-             WENREG_S = '1')
-begin
-  R22_R <= guarded RESULT_S;
-end block;
-
-r23 : block (CKFRZ_S  = '0' and not CKFRZ_S'STABLE and WRTPNT_S = "10111" and
-             WENREG_S = '1')
-begin
-  R23_R <= guarded RESULT_S;
-end block;
-
-r24 : block (CKFRZ_S  = '0' and not CKFRZ_S'STABLE and WRTPNT_S = "11000" and
-             WENREG_S = '1')
-begin
-  R24_R <= guarded RESULT_S;
-end block;
-
-r25 : block (CKFRZ_S  = '0' and not CKFRZ_S'STABLE and WRTPNT_S = "11001" and
-             WENREG_S = '1')
-begin
-  R25_R <= guarded RESULT_S;
-end block;
-
-r26 : block (CKFRZ_S  = '0' and not CKFRZ_S'STABLE and WRTPNT_S = "11010" and
-             WENREG_S = '1')
-begin
-  R26_R <= guarded RESULT_S;
-end block;
-
-r27 : block (CKFRZ_S  = '0' and not CKFRZ_S'STABLE and WRTPNT_S = "11011" and
-             WENREG_S = '1')
-begin
-  R27_R <= guarded RESULT_S;
-end block;
-
-r28 : block (CKFRZ_S  = '0' and not CKFRZ_S'STABLE and WRTPNT_S = "11100" and
-             WENREG_S = '1')
-begin
-  R28_R <= guarded RESULT_S;
-end block;
-
-r29 : block (CKFRZ_S  = '0' and not CKFRZ_S'STABLE and WRTPNT_S = "11101" and
-             WENREG_S = '1')
-begin
-  R29_R <= guarded RESULT_S;
-end block;
-
-r30 : block (CKFRZ_S  = '0' and not CKFRZ_S'STABLE and WRTPNT_S = "11110" and
-             WENREG_S = '1')
-begin
-  R30_R <= guarded RESULT_S ;
-end block;
-
-r31 : block (CKFRZ_S  = '0' and not CKFRZ_S'STABLE and WRTPNT_S = "11111" and
-             WENREG_S = '1')
-begin
-  R31_R <= guarded RESULT_S;
-end block;
-
-	-- ###--------------------------------------------------------###
-	-- #   exceptions						#
-	-- ###--------------------------------------------------------###
-
-with CTLALU_S select
-OVRFLO_X <= ADDOVR_S when a_smv | a_dfv ,
-            '0'      when others          ;
-
-ILLINS_X <= '1' when (CTLEXC_S = e_il) else
-            '0';
-
-OPVIOL_X <= SR_R (0)  and PRVINS_X when (CTLSEQ_S = s_bo16) else
-            '0'                   ;
-
-IAALGN_X <= PC_R (1)  or  PC_R (0) when (CTLMEM_S = m_fch) else
-            '0'                  ;
-
-IASGMT_X <= PC_R (31) and SR_R (0) when (CTLMEM_S = m_fch) else
-            '0'                    ;
-
-with CTLMEM_S select
-DAALGN_X <= AD_R (1) or AD_R (0) when m_ww  | m_rw,
-            '0'                  when others;
-
-with CTLMEM_S select
-DASGMT_X <= AD_R (31) and SR_R (0) when m_ww  | m_wb | m_rw | m_rb,
-            '0'                    when others;
-
-	-- ###--------------------------------------------------------###
-	-- #   assign exception registers				#
-	-- ###--------------------------------------------------------###
-
-except : block (CKFRZ_S = '0' and not CKFRZ_S'STABLE)
-begin
-
-  OVR_R <= guarded OVRFLO_X                      when (CTLRES_S = r_ss) else
-                   OVRFLO_X or OVR_R             ;
-
-  DAV_R <= guarded DAALGN_X or DASGMT_X          when (CTLRES_S = r_ss) else
-                   DAALGN_X or DASGMT_X or DAV_R ;
-
-  ICO_R <= guarded OPVIOL_X or ILLINS_X          when (CTLRES_S = r_ss) else
-                   OPVIOL_X or ILLINS_X or ICO_R ;
-
-  IAV_R <= guarded IAALGN_X or IASGMT_X          when (CTLRES_S = r_ss) else
-                   IAALGN_X or IASGMT_X or IAV_R ;
-end block;
-
-	-- ###--------------------------------------------------------###
-	-- #   assign registers (set a register to indicate effective	#
-	-- # reset at firmware level)					#
-	-- ###--------------------------------------------------------###
-
-cpu_reseted : block (CKFRZ_S = '0' and not CKFRZ_S'STABLE)
-begin
-  CPURST_R <= guarded RESET_R             when ((CTLRES_S = r_ss) and
-                                                (FRZ      = '0' )) else
-                      RESET_R or CPURST_R ;
-end block;
-
-	-- ###--------------------------------------------------------###
-	-- #   assign registers (those independent from the execution	#
-	-- # of an instruction)						#
-	-- ###--------------------------------------------------------###
-
-ext_it : block (CK_S = '0' and not CK_S'STABLE)
-begin
-  FRZ_R   <= guarded FRZ              ;
-  RESET_R <= guarded RESET            when (FRZ = '0') else
-                     RESET or RESET_R ;
-
-  IT_R    <= guarded "0000" when RESET='1' else
-                     not IT           when ((CTLRES_S = r_ss) and
-                                            (FRZ      = '0' )    ) else
-                     not IT or IT_R   ;
-end block;
-
-	-- ###--------------------------------------------------------###
-	-- #   assign outputs :						#
-	-- #     - desable write accesses on exception			#
-	-- #     - enable output tristate buffers of data bus only on	#
-	-- #       high level of (delayed) ck to avoid conflicts	#
-	-- #     - enable output tristate buffers only if the chip is	#
-	-- #       not freezed						#
-	-- #     - align datas before writing on data bus		#
-	-- ### ------------------------------------------------------ ###
-
-data : block ( CKDLY6_S = '1'   and (FRZ and FRZ_R) = '0' and
-              (CTLMEM_S = m_ww  or   CTLMEM_S       = m_wb))
-begin
-  with CTLMEM_S select
-  DATA <= guarded RESULT_S                                        when m_ww,
-                  RESULT_S (7 downto 0) & RESULT_S (7 downto 0) &
-                  RESULT_S (7 downto 0) & RESULT_S (7 downto 0)   when others;
-end block ;
-
-adr : block ((FRZ and FRZ_R) = '0')
-begin
-  with CTLMEM_S select
-  ADR <= guarded AD_R when m_ww | m_wb | m_rw | m_rb,
-                 PC_R when others;
-end block;
-
-SCOUT <= '0';
-
-BYTE  <= BYTSEL_S when (EXCRQS_X = '0') else
-         "0000"   ;
-
-RW    <= '0' when (CTLMEM_S = m_ww or CTLMEM_S = m_wb) else
-         '1' ;
-
-
-end BEHAVIOURAL;
diff --git a/alliance/share/tutorials/dlxm/dlxm_chip.vst b/alliance/share/tutorials/dlxm/dlxm_chip.vst
deleted file mode 100644
index 3aa5591b..00000000
--- a/alliance/share/tutorials/dlxm/dlxm_chip.vst
+++ /dev/null
@@ -1,1310 +0,0 @@
-
--- ### -------------------------------------------------------------- ###
--- #									#
--- # file	: dlxm_chip.vst						#
--- # date	: February 1995						#
--- # version	: v0.2							#
--- #									#
--- # origin	: this description has been developed by CAO-VLSI team	#
--- #		  at MASI laboratory, University Pierre et Marie Curie	#
--- #		  URA CNRS 818, Institut Blaise Pascal			#
--- #		  4 Place Jussieu 75252 Paris Cedex 05 - France		#
--- # E-mail      :      cao-vlsi@masi.ibp.fr                            #
--- #									#
--- # descr.	: structural description of the DLXm chip               #
--- #              instantiating core and symbolic pads                  #
--- #              the external clock ck drives 2 internal clock         #
--- #              one to the control : ck_ctl and                       #
--- #              one to the datapath : ck_dpt                          #
--- #									#
--- ### -------------------------------------------------------------- ###
-
-
-ENTITY dlxm_chip IS
-  PORT (
-  ck    : in bit;				-- external clock
-  reset : in bit;				-- external reset
-  frz   : in bit;				-- freeze
-  it    : in bit_vector(3 downto 0);		-- external interrupts
-  data  : inout mux_vector(31 downto 0) bus;	-- inout data
-  byte  : out bit_vector(0 to 3);		-- select data byte
-  rw    : out bit;				-- read or write
-  adr   : out mux_vector(31 downto 0) bus;	-- address word
-  scin  : in bit;				-- scan in
-  test  : in bit;				-- test mode
-  scout : out bit;				-- scan out
-  vdd   : in bit;				-- core supply
-  vss   : in bit;				-- core supply
-  vddp  : in bit;				-- pad supply
-  vssp  : in bit				-- pad supply
-  );
-END dlxm_chip;
-
-
-ARCHITECTURE structural_view OF dlxm_chip IS
-  COMPONENT dlxm_core
-    port (
-    addr       : out bit_vector(31 downto 0);	-- address word
-    datain_dpt  : in bit_vector(31 downto 0);	-- in data word
-    dataout_dpt : out bit_vector(31 downto 0);	-- out data word
-    it        : in bit_vector(3 downto 0);	-- external interrupts
-    scin      : in bit;				-- scan in
-    scout     : out bit;			-- scan out
-    test      : in bit;				-- test mode
-    reset     : in bit;				-- external reset
-    frz       : in bit;				-- freeze
-    byte      : out bit_vector(0 to 3);		-- select data byte
-    rw        : out bit;			-- read or write
-    rw_ctl    : out bit_vector(15 downto 0);	-- tristate data control
-    frz_ctl   : out bit_vector(15 downto 0);	-- tristate address control	
-    ck_ctl    : in bit;				-- core control clock
-    ck_dpt    : in bit;				-- core dpt clock
-    vdd       : in bit;				-- core supply
-    vss       : in bit				-- core supply
-    );
-  END COMPONENT;
-
-  COMPONENT piot_sp
-    port (
-    i    : in BIT;
-    b    : in BIT;
-    t    : out BIT;
-    pad  : inout MUX_BIT bus;	
-    ck   : in BIT;
-    vdde : in BIT;
-    vddi : in BIT;
-    vsse : in BIT;
-    vssi : in BIT	
-    );
-  END COMPONENT;
-
-  COMPONENT pot_sp
-    port (
-    i    : in BIT;
-    b    : in BIT;
-    pad  : out MUX_BIT BUS;
-    ck   : in BIT;
-    vdde : in BIT;
-    vddi : in BIT;
-    vsse : in BIT;
-    vssi : in BIT
-    );
-  END COMPONENT;
-
-  COMPONENT po_sp
-    port (
-    i    : in BIT;	
-    pad  : out BIT;	
-    ck   : in BIT;
-    vdde : in BIT;	
-    vddi : in BIT;	
-    vsse : in BIT;	
-    vssi : in BIT	
-    );
-  END COMPONENT;
-
-  COMPONENT pi_sp
-    port (
-    pad  : in BIT;	
-    t    : out BIT;	
-    ck   : in BIT;
-    vdde : in BIT;	
-    vddi : in BIT;	
-    vsse : in BIT;	
-    vssi : in BIT	
-    );
-  END COMPONENT;
-
-  COMPONENT pck_sp
-    port (
-    pad  : in BIT;
-    ck   : out BIT;
-    vdde : in BIT;
-    vddi : in BIT;
-    vsse : in BIT;
-    vssi : in BIT
-    );
-   END COMPONENT;
-	
-  COMPONENT pvddi_sp
-    port (
-    ck   : in BIT;
-    vdde : in BIT;	
-    vddi : in BIT;	
-    vsse : in BIT;	
-    vssi : in BIT	
-    );
-  END COMPONENT;
-
-  COMPONENT pvssick_sp
-    port (
-    cko  : out WOR_BIT BUS;
-    ck   : in BIT;
-    vdde : in BIT;	
-    vddi : in BIT;	
-    vsse : in BIT;	
-    vssi : in BIT	
-    );
-  END COMPONENT;
-
-  COMPONENT pvssi_sp
-    port (
-    ck   : in BIT;
-    vdde : in BIT;	
-    vddi : in BIT;	
-    vsse : in BIT;	
-    vssi : in BIT	
-    );
-  END COMPONENT;
-
-  COMPONENT pvdde_sp
-    port (
-    ck   : in BIT;
-    vdde : in BIT;	
-    vddi : in BIT;	
-    vsse : in BIT;	
-    vssi : in BIT	
-    );
-  END COMPONENT;
-
-  COMPONENT pvsse_sp
-    port (
-    ck   : in BIT;
-    vdde : in BIT;	
-    vddi : in BIT;	
-    vsse : in BIT;	
-    vssi : in BIT	
-    );
-  END COMPONENT;
-
-  COMPONENT pvsseck_sp
-    port (
-    cko  : out WOR_BIT BUS;
-    ck   : in BIT;
-    vdde : in BIT;	
-    vddi : in BIT;	
-    vsse : in BIT;	
-    vssi : in BIT	
-    );
-  END COMPONENT;
-
-  SIGNAL ck_ctl_c     : bit;                          -- core clock
-  SIGNAL ck_dpt_c     : bit;                          -- core clock
-  SIGNAL frz_c    : bit;
-  SIGNAL it_c     : bit_vector(3 downto 0);
-  SIGNAL adr_c    : bit_vector(31 downto 0);      -- core address signal
-  SIGNAL byte_c   : bit_vector(0 to 3);	
-  SIGNAL datain_c : bit_vector(31 downto 0);	
-  SIGNAL dataout_c : bit_vector(31 downto 0);	
-  SIGNAL rw_c     : bit;	
-  SIGNAL scout_c  : bit;
-  SIGNAL reset_c  : bit;
-  SIGNAL rw_ctl_c : bit_vector(15 downto 0);	 -- data tristate control
-  SIGNAL frz_ctl_c  : bit_vector(15 downto 0);     -- address tristate control
-  SIGNAL scin_c   : bit;
-  SIGNAL test_c   : bit;
-  SIGNAL ck_ring  : bit;                         -- pad ring clock
-						
-BEGIN
-
-  core : dlxm_core
-    PORT MAP (
-    vss       => vss,				 -- core supply
-    vdd       => vdd,				 -- core supply
-    ck_ctl    => ck_ctl_c,				 -- core control clock
-    ck_dpt    => ck_dpt_c,				 -- core dpt clock
-    rw_ctl    => rw_ctl_c,			 -- inout data cntrol
-    frz_ctl   => frz_ctl_c,			 -- out address control
-    rw        => rw_c,
-    byte      => byte_c,
-    frz       => frz_c,
-    reset     => reset_c,
-    test      => test_c,
-    scout     => scout_c,
-    scin      => scin_c,
-    it        => it_c,
-    dataout_dpt => dataout_c,
-    datain_dpt  => datain_c,
-    addr       => adr_c
-    );
-
-  clock_ring : pck_sp
-    PORT MAP (
-    pad => ck,
-    ck  => ck_ring,
-    vdde => vddp,
-    vddi => vdd,
-    vsse => vssp,
-    vssi => vss);
-
-  ad_out_pl0 : pot_sp
-    PORT MAP (
-    ck  => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => adr(0),
-    b => frz_ctl_c(0),
-    i => adr_c(0));
-
-  ad_out_pl1 : pot_sp
-    PORT MAP (
-    ck  => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => adr(1),
-    b => frz_ctl_c(0),
-    i => adr_c(1));
-
-  ad_out_pl2 : pot_sp
-    PORT MAP (
-    ck  => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => adr(2),
-    b => frz_ctl_c(1),
-    i => adr_c(2));
-
-  ad_out_pl3 : pot_sp
-    PORT MAP (
-    ck  => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => adr(3),
-    b => frz_ctl_c(1),
-    i => adr_c(3));
-
-  ad_out_pl4 : pot_sp
-    PORT MAP (
-    ck  => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => adr(4),
-    b => frz_ctl_c(2),
-    i => adr_c(4));
-
-  ad_out_pl5 : pot_sp
-    PORT MAP (
-    ck  => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => adr(5),
-    b => frz_ctl_c(2),
-    i => adr_c(5));
-
-  ad_out_pl6 : pot_sp
-    PORT MAP (
-    ck  => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => adr(6),
-    b => frz_ctl_c(3),
-    i => adr_c(6));
-
-  ad_out_pl7 : pot_sp
-    PORT MAP (
-    ck  => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => adr(7),
-    b => frz_ctl_c(3),
-    i => adr_c(7));
-
-  ad_out_pl8 : pot_sp
-    PORT MAP (
-    ck  => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => adr(8),
-    b => frz_ctl_c(4),
-    i => adr_c(8));
-
-  ad_out_pl9 : pot_sp
-    PORT MAP (
-    ck  => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => adr(9),
-    b => frz_ctl_c(4),
-    i => adr_c(9));
-
-  ad_out_pl10 : pot_sp
-    PORT MAP (
-    ck  => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => adr(10),
-    b => frz_ctl_c(5),
-    i => adr_c(10));
-
-  ad_out_pl11 : pot_sp
-    PORT MAP (
-    ck  => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => adr(11),
-    b => frz_ctl_c(5),
-    i => adr_c(11));
-
-  ad_out_pl12 : pot_sp
-    PORT MAP (
-    ck  => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => adr(12),
-    b => frz_ctl_c(6),
-    i => adr_c(12));
-
-  ad_out_pl13 : pot_sp
-    PORT MAP (
-    ck  => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => adr(13),
-    b => frz_ctl_c(6),
-    i => adr_c(13));
-
-  ad_out_pl14 : pot_sp
-    PORT MAP (
-    ck  => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => adr(14),
-    b => frz_ctl_c(7),
-    i => adr_c(14));
-
-  ad_out_pl15 : pot_sp
-    PORT MAP (
-    ck  => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => adr(15),
-    b => frz_ctl_c(7),
-    i => adr_c(15));
-
-  ad_out_pl16 : pot_sp
-    PORT MAP (
-    ck  => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => adr(16),
-    b => frz_ctl_c(8),
-    i => adr_c(16));
-
-  ad_out_pl17 : pot_sp
-    PORT MAP (
-    ck  => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => adr(17),
-    b => frz_ctl_c(8),
-    i => adr_c(17));
-
-  ad_out_pl18 : pot_sp
-    PORT MAP (
-    ck  => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => adr(18),
-    b => frz_ctl_c(9),
-    i => adr_c(18));
-
-  ad_out_pl19 : pot_sp
-    PORT MAP (
-    ck  => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => adr(19),
-    b => frz_ctl_c(9),
-    i => adr_c(19));
-
-  ad_out_pl20 : pot_sp
-    PORT MAP (
-    ck  => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => adr(20),
-    b => frz_ctl_c(10),
-    i => adr_c(20));
-
-  ad_out_pl21 : pot_sp
-    PORT MAP (
-    ck  => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => adr(21),
-    b => frz_ctl_c(10),
-    i => adr_c(21));
-
-  ad_out_pl22 : pot_sp
-    PORT MAP (
-    ck  => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => adr(22),
-    b => frz_ctl_c(11),
-    i => adr_c(22));
-
-  ad_out_pl23 : pot_sp
-    PORT MAP (
-    ck  => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => adr(23),
-    b => frz_ctl_c(11),
-    i => adr_c(23));
-
-  ad_out_pl24 : pot_sp
-    PORT MAP (
-    ck  => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => adr(24),
-    b => frz_ctl_c(12),
-    i => adr_c(24));
-
-  ad_out_pl25 : pot_sp
-    PORT MAP (
-    ck  => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => adr(25),
-    b => frz_ctl_c(12),
-    i => adr_c(25));
-
-  ad_out_pl26 : pot_sp
-    PORT MAP (
-    ck  => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => adr(26),
-    b => frz_ctl_c(13),
-    i => adr_c(26));
-
-  ad_out_pl27 : pot_sp
-    PORT MAP (
-    ck  => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => adr(27),
-    b => frz_ctl_c(13),
-    i => adr_c(27));
-
-  ad_out_pl28 : pot_sp
-    PORT MAP (
-    ck  => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => adr(28),
-    b => frz_ctl_c(14),
-    i => adr_c(28));
-
-  ad_out_pl29 : pot_sp
-    PORT MAP (
-    ck  => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => adr(29),
-    b => frz_ctl_c(14),
-    i => adr_c(29));
-
-  ad_out_pl30 : pot_sp
-    PORT MAP (
-    ck  => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => adr(30),
-    b => frz_ctl_c(15),
-    i => adr_c(30));
-
-  ad_out_pl31 : pot_sp
-    PORT MAP (
-    ck  => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => adr(31),
-    b => frz_ctl_c(15),
-    i => adr_c(31));
-
-  dat_inout_pl0 : piot_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => data(0),
-    t => datain_c(0),
-    b => rw_ctl_c(0),
-    i => dataout_c(0));
-
-  dat_inout_pl1 : piot_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => data(1),
-    t => datain_c(1),
-    b => rw_ctl_c(0),
-    i => dataout_c(1));
-
-  dat_inout_pl2 : piot_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => data(2),
-    t => datain_c(2),
-    b => rw_ctl_c(1),
-    i => dataout_c(2));
-
-  dat_inout_pl3 : piot_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => data(3),
-    t => datain_c(3),
-    b => rw_ctl_c(1),
-    i => dataout_c(3));
-
-  dat_inout_pl4 : piot_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => data(4),
-    t => datain_c(4),
-    b => rw_ctl_c(2),
-    i => dataout_c(4));
-
-  dat_inout_pl5 : piot_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => data(5),
-    t => datain_c(5),
-    b => rw_ctl_c(2),
-    i => dataout_c(5));
-
-  dat_inout_pl6 : piot_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => data(6),
-    t => datain_c(6),
-    b => rw_ctl_c(3),
-    i => dataout_c(6));
-
-  dat_inout_pl7 : piot_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => data(7),
-    t => datain_c(7),
-    b => rw_ctl_c(3),
-    i => dataout_c(7));
-
-  dat_inout_pl8 : piot_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => data(8),
-    t => datain_c(8),
-    b => rw_ctl_c(4),
-    i => dataout_c(8));
-
-  dat_inout_pl9 : piot_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => data(9),
-    t => datain_c(9),
-    b => rw_ctl_c(4),
-    i => dataout_c(9));
-
-  dat_inout_pl10 : piot_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => data(10),
-    t => datain_c(10),
-    b => rw_ctl_c(5),
-    i => dataout_c(10));
-
-  dat_inout_pl11 : piot_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => data(11),
-    t => datain_c(11),
-    b => rw_ctl_c(5),
-    i => dataout_c(11));
-
-  dat_inout_pl12 : piot_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => data(12),
-    t => datain_c(12),
-    b => rw_ctl_c(6),
-    i => dataout_c(12));
-
-  dat_inout_pl13 : piot_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => data(13),
-    t => datain_c(13),
-    b => rw_ctl_c(6),
-    i => dataout_c(13));
-
-  dat_inout_pl14 : piot_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => data(14),
-    t => datain_c(14),
-    b => rw_ctl_c(7),
-    i => dataout_c(14));
-
-  dat_inout_pl15 : piot_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => data(15),
-    t => datain_c(15),
-    b => rw_ctl_c(7),
-    i => dataout_c(15));
-
-  dat_inout_pl16 : piot_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => data(16),
-    t => datain_c(16),
-    b => rw_ctl_c(8),
-    i => dataout_c(16));
-
-  dat_inout_pl17 : piot_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => data(17),
-    t => datain_c(17),
-    b => rw_ctl_c(8),
-    i => dataout_c(17));
-
-  dat_inout_pl18 : piot_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => data(18),
-    t => datain_c(18),
-    b => rw_ctl_c(9),
-    i => dataout_c(18));
-
-  dat_inout_pl19 : piot_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => data(19),
-    t => datain_c(19),
-    b => rw_ctl_c(9),
-    i => dataout_c(19));
-
-  dat_inout_pl20 : piot_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => data(20),
-    t => datain_c(20),
-    b => rw_ctl_c(10),
-    i => dataout_c(20));
-
-  dat_inout_pl21 : piot_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => data(21),
-    t => datain_c(21),
-    b => rw_ctl_c(10),
-    i => dataout_c(21));
-
-  dat_inout_pl22 : piot_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => data(22),
-    t => datain_c(22),
-    b => rw_ctl_c(11),
-    i => dataout_c(22));
-
-  dat_inout_pl23 : piot_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => data(23),
-    t => datain_c(23),
-    b => rw_ctl_c(11),
-    i => dataout_c(23));
-
-  dat_inout_pl24 : piot_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => data(24),
-    t => datain_c(24),
-    b => rw_ctl_c(12),
-    i => dataout_c(24));
-
-  dat_inout_pl25 : piot_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => data(25),
-    t => datain_c(25),
-    b => rw_ctl_c(12),
-    i => dataout_c(25));
-
-  dat_inout_pl26 : piot_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => data(26),
-    t => datain_c(26),
-    b => rw_ctl_c(13),
-    i => dataout_c(26));
-
-  dat_inout_pl27 : piot_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => data(27),
-    t => datain_c(27),
-    b => rw_ctl_c(13),
-    i => dataout_c(27));
-
-  dat_inout_pl28 : piot_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => data(28),
-    t => datain_c(28),
-    b => rw_ctl_c(14),
-    i => dataout_c(28));
-
-  dat_inout_pl29 : piot_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => data(29),
-    t => datain_c(29),
-    b => rw_ctl_c(14),
-    i => dataout_c(29));
-
-  dat_inout_pl30 : piot_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => data(30),
-    t => datain_c(30),
-    b => rw_ctl_c(15),
-    i => dataout_c(30));
-
-  dat_inout_pl31 : piot_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => data(31),
-    t => datain_c(31),
-    b => rw_ctl_c(15),
-    i => dataout_c(31));
-
-  it_in_pl0 : pi_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    t => it_c(0),
-    pad => it(0));
-
-  it_in_pl1 : pi_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    t => it_c(1),
-    pad => it(1));
-
-  it_in_pl2 : pi_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    t => it_c(2),
-    pad => it(2));
-
-  it_in_pl3 : pi_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    t => it_c(3),
-    pad => it(3));
-
-  scin_pl : pi_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    t => scin_c,
-    pad => scin);
-
-  scout_pl : po_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => scout,
-    i => scout_c);
-
-  test_pl : pi_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    t => test_c,
-    pad => test);
-
-  reset_pl : pi_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    t => reset_c,
-    pad => reset);
-
-  frz_pl : pi_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    t => frz_c,
-    pad => frz);
-
-  byte_pl0 : po_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => byte(0),
-    i => byte_c(0));
-
-  byte_pl1 : po_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => byte(1),
-    i => byte_c(1));
-
-  byte_pl2 : po_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => byte(2),
-    i => byte_c(2));
-
-  byte_pl3 : po_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => byte(3),
-    i => byte_c(3));
-
-  rw_pl : po_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    pad => rw,
-    i => rw_c);
-
-  vddi_pl_0 : pvddi_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp);
-
-  vddi_pl_1 : pvddi_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp);
-
-  vddi_pl_2 : pvddi_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp);
-
-  vddi_pl_3 : pvddi_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp);
-
-  ck_vssi_pl_3 : pvssick_sp
-    PORT MAP (
-    cko  => ck_dpt_c,
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp);
-
-  vssi_pl_1 : pvssi_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp);
-
-  vssi_pl_2 : pvssi_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp);
-
-  vssi_pl_0 : pvssi_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp);
-
-  vdde_pl_0 : pvdde_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vdde => vddp,
-    vddi => vdd);
-
-  vdde_pl_1 : pvdde_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vdde => vddp,
-    vddi => vdd);
-
-  vdde_pl_2 : pvdde_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vdde => vddp,
-    vddi => vdd);
-
-  vdde_pl_3 : pvdde_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vdde => vddp,
-    vddi => vdd);
-
-  vdde_pl_4 : pvdde_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vdde => vddp,
-    vddi => vdd);
-
-  vdde_pl_5 : pvdde_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vdde => vddp,
-    vddi => vdd);
-
-  vdde_pl_6 : pvdde_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vdde => vddp,
-    vddi => vdd);
-
-  vdde_pl_7 : pvdde_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vssi => vss,
-    vsse => vssp,
-    vdde => vddp,
-    vddi => vdd);
-
-ck_vsse_pl_0 : pvsseck_sp
-    PORT MAP (
-    ck   => ck_ring,
-    cko  => ck_ctl_c,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    vssi => vss);
-
-  vsse_pl_1 : pvsse_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    vssi => vss);
-
-  vsse_pl_2 : pvsse_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vsse => vssp,
-    vddi => vdd,
-    vdde => vddp,
-    vssi => vss);
-
-  vsse_pl_3 : pvsse_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vsse => vssp,
-    vssi => vss,
-    vddi => vdd,
-    vdde => vddp);
-
-  vsse_pl_4 : pvsse_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vsse => vssp,
-    vssi => vss,
-    vddi => vdd,
-    vdde => vddp);
-
-  vsse_pl_5 : pvsse_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vsse => vssp,
-    vssi => vss,
-    vddi => vdd,
-    vdde => vddp);
-
-  vsse_pl_6 : pvsse_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vsse => vssp,
-    vssi => vss,
-    vddi => vdd,
-    vdde => vddp);
-
-  vsse_pl_7 : pvsse_sp
-    PORT MAP (
-    ck   => ck_ring,
-    vsse => vssp,
-    vssi => vss,
-    vddi => vdd,
-    vdde => vddp);
-
-end structural_view;
diff --git a/alliance/share/tutorials/dlxm/dlxm_core.c b/alliance/share/tutorials/dlxm/dlxm_core.c
deleted file mode 100644
index 267e38a8..00000000
--- a/alliance/share/tutorials/dlxm/dlxm_core.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
-### ----------------------------------------------------------------- ###
-#									#
-# file	: dlxm_core.c							#
-# date	: February 1995							#
-# version	: v0.0							#
-#									#
-# origin	: this description has been developed by CAO-VLSI team	#
-#		  at MASI laboratory, University Pierre et Marie Curie	#
-#		  URA CNRS 818, Institut Blaise Pascal			#
-#		  4 Place Jussieu 75252 Paris Cedex 05 - France		#
-# E-mail      :      cao-vlsi@masi.ibp.fr                               #
-#									#
-# descr.	: Placement file for control and datapath		#
-#									#
-### ----------------------------------------------------------------- ###
-*/
-
-#include <genlib.h>
-#include <mgn328.h>
-
-main()
-  {
-  DEF_PHFIG ("dlxm_core");
-  PLACE ("dlxm_dpt","dpt",NOSYM, 0, 0);
-  PLACE ("dlxm_ctl","ctl",NOSYM,
-         (WIDTH("dlxm_dpt") - WIDTH("dlxm_ctl")) /2, HEIGHT("dlxm_dpt"));
-  DEF_AB (0, 0, 0, 0);
-  SAVE_PHFIG();
-  exit(0);
-  }
-
-
diff --git a/alliance/share/tutorials/dlxm/dlxm_core.vst b/alliance/share/tutorials/dlxm/dlxm_core.vst
deleted file mode 100644
index 0d59f9e6..00000000
--- a/alliance/share/tutorials/dlxm/dlxm_core.vst
+++ /dev/null
@@ -1,444 +0,0 @@
-
--- ### -------------------------------------------------------------- ###
--- #									#
--- # file	: dlxm_core.vst         				#
--- # date	: February 1995						#
--- # version	: v0.0							#
--- #									#
--- # origin	: this description has been developed by CAO-VLSI team	#
--- #		  at MASI laboratory, University Pierre et Marie Curie	#
--- #		  URA CNRS 818 - Institut Blaise Pascal			#
--- #		  4 Place Jussieu 75252 Paris Cedex 05 - France		#
--- # E-mail      :      cao-vlsi@masi.ibp.fr                            #
--- #									#
--- # descr.	: structural model of the core instantiating		#	
--- # 		  the datapath and the control				#
--- #									#
--- ### -------------------------------------------------------------- ###
-
-
--- Entity Declaration
-
-ENTITY dlxm_core IS
-  PORT (
-  addr : out BIT_VECTOR(31 DOWNTO 0);		-- address bus
-  datain_dpt : in BIT_VECTOR(31 DOWNTO 0);	-- datain_dpt
-  dataout_dpt : out BIT_VECTOR(31 DOWNTO 0);	-- dataout_dpt
-  it : in BIT_VECTOR(3 DOWNTO 0);		-- it
-  scin : in BIT;				-- scin
-  scout : out BIT;				-- scout
-  test : in BIT;				-- test
-  reset : in BIT;				-- external reset
-  frz : in BIT;					-- frz
-  byte : out BIT_VECTOR(0 to 3);		-- byte
-  rw : out BIT;					-- rw
-  rw_ctl : out BIT_VECTOR(15 downto 0);		-- tristate data control
-  frz_ctl : out BIT_VECTOR(15 downto 0);	-- tristate address control
-  ck_ctl : in BIT;				-- internal clock to control
-  ck_dpt : in BIT;				-- internal clock to datapath
-  vdd : in BIT;					-- vdd
-  vss : in BIT					-- vss
-  );
-END dlxm_core;
-
--- Architecture Declaration
-
-ARCHITECTURE structural_view OF dlxm_core IS
-
-  COMPONENT dlxm_ctl
-    PORT (
-  it : in BIT_VECTOR(3 DOWNTO 0);       	-- it
-  scin : in BIT;        			-- scin
-  scout : out BIT;      			-- scout
-  test : in BIT;        			-- test
-  reset : in BIT;       			-- external reset
-  frz : in BIT; 				-- frz
-  byte : out BIT_VECTOR(0 to 3);    		-- byte
-  rw : out BIT; 				-- rw
-  rw_ctl : out BIT_VECTOR(15 downto 0);         -- tristate data control
-  frz_ctl : out BIT_VECTOR(15 downto 0);        -- tristate address control
-  ck : in BIT;  				-- ck
-
--- Partie interface avec le DataPath
-
-seq_ctladr : out BIT;
-sts_zero : out BIT;
-sts_sr_cpurst : inout BIT;    -- flag reset to datapath
-sts_sr_it3 : out BIT;      -- sts_sr_it
-sts_sr_it2 : out BIT;      -- sts_sr_it
-sts_sr_it1 : out BIT;      -- sts_sr_it
-sts_sr_it0 : out BIT;      -- sts_sr_it
-sts_sr_ico : out BIT;      -- sts_sr_ico
-sts_sr_iav : out BIT;      -- sts_sr_iav
-sts_sr_dav : out BIT;      -- sts_sr_dav
-sts_sr_ovr : out BIT;      -- sts_sr_ovr
-sts_wrtpnt : out BIT_VECTOR(4 downto 0);  
-sts_redpnt : out BIT_VECTOR (4 downto 0);
-sts_alu_test : out BIT;    -- sts_alu_test
-dp_alu_sign : in BIT;     -- dp_alu_sign
-dp_alu_nul : in BIT;      -- dp_alu_nul
-dp_alu_c30 : in BIT;    -- dp_alu_c30_n
-dp_alu_c31 : in BIT;    -- dp_alu_c31_n
-dp_opy_sign : in BIT;     -- dp_opy_sign
-dp_ir_sr : in BIT;        -- dp_ir_sr
-dp_ir_iar : in BIT;       -- dp_ir_iar
-dp_ir_tvr : in BIT;       -- dp_ir_tvr
-dp_rd : in BIT_VECTOR(4 downto 0);   -- dp_rd 
-dp_rdrt : in BIT_VECTOR(4 downto 0); -- dp_rdrt
-dp_rs : in BIT_VECTOR(4 downto 0); -- dp_rs
-dp_codop : in BIT_VECTOR(5 downto 0);-- dp_codop
-dp_opx_sign : in BIT;     -- dp_opx_sign
-dp_sr_mode : in BIT;      -- dp_sr_mode
-dp_sr_mask : in BIT;      -- dp_sr_mask
-sts_ctlrw : out BIT_VECTOR(3 downto 2);     -- sts_ctlrw 
-sts_wenable : out BIT_VECTOR(5 downto 0);   -- sts_wenable 
-seq_ctlopy : out BIT_VECTOR(4 downto 0);      -- seq_ctlopy
-seq_ctlopx : out BIT_VECTOR(5 downto 0);    -- seq_ctlopx
-ad_n_31:in bit;
-ad_n_1:in bit;
-ad_n_0:in bit;
-
-  -- Connecteur utilises en interne ET le datapath
-seq_ctlrw: inout bit_vector(3 downto 0);
-seq_ctlalu: inout bit_vector(4 downto 0);
-seq_wenable: inout bit_vector(8 downto 0);
- 
-  vdd : in BIT; -- vdd
-  vss : in BIT  -- vss
-  );
-
-  END Component;
-
-  COMPONENT dlxm_dpt
-    port (
-    vdd : in BIT;	-- vdd
-    vss : in BIT;	-- vss
-    pc_test : in BIT;	-- pc_test
-    ad_test : in BIT;	-- ad_test
-    tvr_test : in BIT;	-- tvr_test
-    iar_test : in BIT;	-- iar_test
-    sr_test : in BIT;	-- sr_test
-    ir_test : in BIT;	-- ir_test
-    dt_test : in BIT;	-- dt_test
-    pc_scin : in BIT;	-- pc_scin
-    ad_scin : in BIT;	-- ad_scin
-    tvr_scin : in BIT;	-- tvr_scin
-    iar_scin : in BIT;	-- iar_scin
-    sr_scin : in BIT;	-- sr_scin
-    ir_scin : in BIT;	-- ir_scin
-    dt_scin : in BIT;	-- dt_scin
-    pc_scout : out BIT;	-- pc_scout
-    ad_scout : out BIT;	-- ad_scout
-    tvr_scout : out BIT;	-- tvr_scout
-    iar_scout : out BIT;	-- iar_scout
-    sr_scout : out BIT;	-- sr_scout
-    ir_scout : out BIT;	-- ir_scout
-    dt_scout : out BIT;	-- dt_scout
-    pc_ck : in BIT;	-- pc_ck
-    ad_ck : in BIT;	-- ad_ck
-    tvr_ck : in BIT;	-- tvr_ck
-    iar_ck : in BIT;	-- iar_ck
-    sr_ck : in BIT;	-- sr_ck
-    ir_ck : in BIT;	-- ir_ck
-    dt_ck : in BIT;	-- dt_ck
-    pc_wen : in BIT;	-- pc_wen
-    ad_wen : in BIT;	-- ad_wen
-    tvr_wen : in BIT;	-- tvr_wen
-    iar_wen : in BIT;	-- iar_wen
-    sr_wen : in BIT;	-- sr_wen
-    ir_wen : in BIT;	-- ir_wen
-    dt_wen : in BIT;	-- dt_wen
-    rf_ck : in BIT;	-- rf_ck
-    rf_wen : in BIT;	-- rf_wen
-    rf_aw : in BIT_VECTOR(4 DOWNTO 0);	-- rf_aw
-    rf_ar : in BIT_VECTOR(4 DOWNTO 0);	-- rf_ar
-    sr_mx : in BIT;	-- sr_mx
-    sr_mode : out BIT;	-- sr_mode
-    sr_mask : out BIT;	-- sr_mask
-    sr_cpurst : in BIT;	-- flag cpureset from ctrl
-    sr_iav : in BIT;	-- sr_iav
-    sr_ico : in BIT;	-- sr_ico
-    sr_dav : in BIT;	-- sr_dav
-    sr_ovr : in BIT;	-- sr_ovr
-    sr_it0 : in BIT;	-- sr_it
-    sr_it1 : in BIT;	-- sr_it
-    sr_it2 : in BIT;	-- sr_it
-    sr_it3 : in BIT;	-- sr_it
-    opx_ts4 : in BIT;	-- opx_ts4
-    opx_ts3 : in BIT;	-- opx_ts3
-    opx_ts2 : in BIT;	-- opx_ts2
-    opx_ts1 : in BIT;	-- opx_ts1
-    opx_ts0 : in BIT;	-- opx_ts0
-    opx_mx4 : in BIT;	-- opx_mx4
-    opx_mx3 : in BIT;	-- opx_mx3
-    opx_mx2 : in BIT;	-- opx_mx2
-    opx_mx1 : in BIT;	-- opx_mx1
-    opx_sign : out BIT;	-- opx_sign
-    opy_ts4 : in BIT;	-- opy_ts4
-    opy_ts3 : in BIT;	-- opy_ts3
-    opy_ts2 : in BIT;	-- opy_ts2
-    opy_ts1 : in BIT;	-- opy_ts1
-    opy_mx4 : in BIT;	-- opy_mx4
-    opy_mx3 : in BIT;	-- opy_mx3
-    opy_mx2 : in BIT;	-- opy_mx2
-    opy_mx1 : in BIT;	-- opy_mx1
-    adrw_byte : in BIT;	-- adrw_byte
-    adrw_rb1 : in BIT;	-- adrw_rb1
-    adrw_rb0 : in BIT;	-- adrw_rb0
-    opy_codop : out BIT_VECTOR(5 DOWNTO 0);	-- opy_codop
-    opy_rs : out BIT_VECTOR(4 DOWNTO 0);	-- opy_rs
-    opy_rdrt : out BIT_VECTOR(4 DOWNTO 0);	-- opy_rdrt
-    opy_rd : out BIT_VECTOR(4 DOWNTO 0);	-- opy_rd
-    opy_tvr : out BIT;	-- opy_tvr
-    opy_sr : out BIT;	-- opy_sr
-    opy_iar : out BIT;	-- opy_iar
-    opy_sign : out BIT;	-- opy_sign
-    data_in_dpt : in BIT_VECTOR(31 DOWNTO 0);	-- data_in_dpt
-    alu_mx4i0 : in BIT;	-- alu_mx4i0
-    alu_mx3i0 : in BIT;	-- alu_mx3i0
-    alu_mx2i1 : in BIT;	-- alu_mx2i1
-    alu_mx2i0 : in BIT;	-- alu_mx2i0
-    alu_mx1i2 : in BIT;	-- alu_mx1i2
-    alu_mx1i1 : in BIT;	-- alu_mx1i1
-    alu_mx1i0 : in BIT;	-- alu_mx1i0
-    alu_mx0i0 : in BIT;	-- alu_mx0i0
-    alu_byte : in BIT;	-- alu_byte
-    alu_shrot : in BIT;	-- alu_shrot
-    alu_test_n : in BIT;	-- alu_test_n
-    alu_c31 : out BIT;	-- alu_c31_n
-    alu_c30 : out BIT;	-- alu_c30_n
-    alu_nul : out BIT;	-- alu_nul
-    alu_sign : out BIT;	-- alu_sign
-    data_out_dpt : out BIT_VECTOR(31 DOWNTO 0);	-- data_out_dpt
-    out_mx0i0 : in BIT;	-- out_mx0i0
-    out_adr : out BIT_VECTOR(31 DOWNTO 0); 	-- out_adr
-    adr_n_31 : inout BIT ; 			-- vers status
-    adr_n_1  :  inout BIT ;			-- vers status et dpt
-    adr_n_0  :  inout BIT 			-- vers status et dpt
-
-    );
-  END COMPONENT;
-
-  SIGNAL dp_adr_n_31 : BIT;			-- address to status
-  SIGNAL dp_adr_n_1 : BIT;			-- address to status
-  SIGNAL dp_adr_n_0 : BIT;			-- address to status
-  SIGNAL seq_ctladr : BIT;	-- seq_ctladr
-  SIGNAL sts_zero : BIT;	-- sts_zero
-  SIGNAL dp_scout : BIT;	-- dp_scout
-  SIGNAL ir_scout : BIT;	-- ir_scout
-  SIGNAL sr_scout : BIT;	-- sr_scout
-  SIGNAL iar_scout : BIT;	-- iar_scout
-  SIGNAL tvr_scout : BIT;	-- tvr_scout
-  SIGNAL ad_scout : BIT;	-- ad_scout
-  SIGNAL pc_scout : BIT;	-- pc_scout
-  SIGNAL sts_sr_cpurst : BIT;	-- sts_sr_cpurst
-  SIGNAL sts_sr_it3 : BIT;	-- sts_sr_it
-  SIGNAL sts_sr_it2 : BIT;	-- sts_sr_it
-  SIGNAL sts_sr_it1 : BIT;	-- sts_sr_it
-  SIGNAL sts_sr_it0 : BIT;	-- sts_sr_it
-  SIGNAL sts_sr_ico : BIT;	-- sts_sr_ico
-  SIGNAL sts_sr_iav : BIT;	-- sts_sr_iav
-  SIGNAL sts_sr_dav : BIT;	-- sts_sr_dav
-  SIGNAL sts_sr_ovr : BIT;	-- sts_sr_ovr
-  SIGNAL sts_wrtpnt : BIT_VECTOR(4 downto 0);	-- sts_wrtpnt
-  SIGNAL sts_redpnt : BIT_VECTOR(4 downto 0);	-- sts_redpnt
-  SIGNAL sts_alu_test : BIT;	-- sts_alu_test
-  SIGNAL dp_alu_sign : BIT;	-- dp_alu_sign
-  SIGNAL dp_alu_nul : BIT;	-- dp_alu_nul
-  SIGNAL dp_alu_c30 : BIT;	-- dp_alu_c30_n
-  SIGNAL dp_alu_c31 : BIT;	-- dp_alu_c31_n
-  SIGNAL dp_opy_sign : BIT;	-- dp_opy_sign
-  SIGNAL dp_ir_sr : BIT;	-- dp_ir_sr
-  SIGNAL dp_ir_iar : BIT;	-- dp_ir_iar
-  SIGNAL dp_ir_tvr : BIT;	-- dp_ir_tvr
-  SIGNAL dp_rd : BIT_VECTOR(4 downto 0);	-- dp_rd 
-  SIGNAL dp_rdrt : BIT_VECTOR(4 downto 0);	-- dp_rdrt
-  SIGNAL dp_rs : BIT_VECTOR(4 downto 0);	-- dp_rs
-  SIGNAL dp_codop : BIT_VECTOR(5 downto 0);	-- dp_codop 
-  SIGNAL dp_opx_sign : BIT;	-- dp_opx_sign
-  SIGNAL dp_sr_mode : BIT;	-- dp_sr_mode
-  SIGNAL dp_sr_mask : BIT;	-- dp_sr_mask
-  SIGNAL sts_ctlrw : BIT_VECTOR(3 downto 2);	-- sts_ctlrw 
-  SIGNAL sts_wenable : BIT_VECTOR(5 downto 0);	-- sts_wenable
-  SIGNAL seq_ctlopy : BIT_VECTOR(4 downto 0);	-- seq_ctlopy
-  SIGNAL seq_ctlopx : BIT_VECTOR(5 downto 0);	-- seq_ctlopx
-
-  SIGNAL seq_ctlrw: bit_vector(3 downto 0);
-  SIGNAL seq_ctlalu: bit_vector(4 downto 0);
-  SIGNAL seq_wenable:
-bit_vector(8 downto 0);
-
-
-BEGIN
-
-
-  dpt : dlxm_dpt
-    PORT MAP (
-    out_adr => addr,
-    adr_n_31 => dp_adr_n_31,
-    adr_n_1  => dp_adr_n_1,
-    adr_n_0  => dp_adr_n_0,
-    out_mx0i0 => seq_ctladr,
-    data_out_dpt => dataout_dpt,
-    alu_sign => dp_alu_sign,
-    alu_nul => dp_alu_nul,
-    alu_c30 => dp_alu_c30,
-    alu_c31 => dp_alu_c31,
-    alu_test_n => sts_alu_test,
-    alu_shrot => sts_zero,
-    alu_byte => seq_ctlrw(1),
-    alu_mx0i0 => seq_ctlalu(0),
-    alu_mx1i0 => seq_ctlalu(1),
-    alu_mx1i1 => seq_ctlalu(1),
-    alu_mx1i2 => seq_ctlalu(1),
-    alu_mx2i0 => seq_ctlalu(2),
-    alu_mx2i1 => seq_ctlalu(2),
-    alu_mx3i0 => seq_ctlalu(3),
-    alu_mx4i0 => seq_ctlalu(4),
-    data_in_dpt => datain_dpt,
-    opy_sign => dp_opy_sign,
-    opy_iar => dp_ir_iar,
-    opy_sr => dp_ir_sr,
-    opy_tvr => dp_ir_tvr,
-    opy_rd => dp_rd,
-    opy_rdrt => dp_rdrt,
-    opy_rs => dp_rs,
-    opy_codop => dp_codop,
-    adrw_rb0 => dp_adr_n_0,
-    adrw_rb1 => dp_adr_n_1,
-    adrw_byte => seq_ctlrw(1),
-    opy_mx1 => seq_ctlopy(0),
-    opy_mx2 => seq_ctlopy(0),
-    opy_mx3 => seq_ctlopy(0),
-    opy_mx4 => seq_ctlopy(0),
-    opy_ts1 => seq_ctlopy(1),
-    opy_ts2 => seq_ctlopy(2),
-    opy_ts3 => seq_ctlopy(3),
-    opy_ts4 => seq_ctlopy(4),
-    opx_sign => dp_opx_sign,
-    opx_mx1 => seq_ctlopx(0),
-    opx_mx2 => seq_ctlopx(0),
-    opx_mx3 => seq_ctlopx(0),
-    opx_mx4 => seq_ctlopx(0),
-    opx_ts0 => seq_ctlopx(1),
-    opx_ts1 => seq_ctlopx(2),
-    opx_ts2 => seq_ctlopx(3),
-    opx_ts3 => seq_ctlopx(4),
-    opx_ts4 => seq_ctlopx(5),
-    sr_it3 => sts_sr_it3,
-    sr_it2 => sts_sr_it2,
-    sr_it1 => sts_sr_it1,
-    sr_it0 => sts_sr_it0,
-    sr_ovr => sts_sr_ovr,
-    sr_dav => sts_sr_dav,
-    sr_ico => sts_sr_ico,
-    sr_iav => sts_sr_iav,
-    sr_cpurst => sts_sr_cpurst,			-- cpureset flag from status
-    sr_mask => dp_sr_mask,
-    sr_mode => dp_sr_mode,
-    sr_mx => seq_wenable(7),
-    rf_ar => sts_redpnt,
-    rf_aw => sts_wrtpnt,
-    rf_wen => sts_wenable(2),
-    rf_ck => ck_dpt,
-    dt_wen => sts_ctlrw(2),
-    ir_wen => sts_ctlrw(3),
-    sr_wen => sts_wenable(5),
-    iar_wen => sts_wenable(3),
-    tvr_wen => sts_wenable(4),
-    ad_wen => sts_wenable(1),
-    pc_wen => sts_wenable(0),
-    dt_ck => ck_dpt,
-    ir_ck => ck_dpt,
-    sr_ck => ck_dpt,
-    iar_ck => ck_dpt,
-    tvr_ck => ck_dpt,
-    ad_ck => ck_dpt,
-    pc_ck => ck_dpt,
-    dt_scout => dp_scout,
-    ir_scout => ir_scout,
-    sr_scout => sr_scout,
-    iar_scout => iar_scout,
-    tvr_scout => tvr_scout,
-    ad_scout => ad_scout,
-    pc_scout => pc_scout,
-    dt_scin => ir_scout,
-    ir_scin => sr_scout,
-    sr_scin => iar_scout,
-    iar_scin => tvr_scout,
-    tvr_scin => ad_scout,
-    ad_scin => pc_scout,
-    pc_scin => scin,
-    dt_test => test,
-    ir_test => test,
-    sr_test => test,
-    iar_test => test,
-    tvr_test => test,
-    ad_test => test,
-    pc_test => test,
-    vss => vss,
-    vdd => vdd);
-
-
-  ctl : dlxm_ctl 
-    PORT MAP (
-  it => it,
-  scin => dp_scout,
-  scout => scout,
-  test => test,
-  reset => reset,				-- external reset
-  frz => frz,
-  byte => byte,
-  rw => rw,
-  rw_ctl => rw_ctl,
-  frz_ctl => frz_ctl,
-  ck => ck_ctl,
-
--- Partie interace avec de DataPath
-
-seq_ctladr => seq_ctladr,
-sts_zero => sts_zero, 
-sts_sr_cpurst => sts_sr_cpurst,			-- cpureset flag to datapath
-sts_sr_it3 => sts_sr_it3,
-sts_sr_it2 => sts_sr_it2,
-sts_sr_it1 => sts_sr_it1,
-sts_sr_it0 => sts_sr_it0,
-sts_sr_ico =>  sts_sr_ico,
-sts_sr_iav  => sts_sr_iav,
-sts_sr_dav  => sts_sr_dav,
-sts_sr_ovr  => sts_sr_ovr,
-sts_wrtpnt => sts_wrtpnt,
-sts_redpnt => sts_redpnt,
-sts_alu_test => sts_alu_test,
-dp_alu_sign => dp_alu_sign,
-dp_alu_nul  => dp_alu_nul,
-dp_alu_c30 => dp_alu_c30,
-dp_alu_c31 => dp_alu_c31,
-dp_opy_sign =>  dp_opy_sign,
-dp_ir_sr => dp_ir_sr,
-dp_ir_iar => dp_ir_iar,
-dp_ir_tvr =>  dp_ir_tvr,
-dp_rd => dp_rd,
-dp_rdrt  => dp_rdrt,
-dp_rs  => dp_rs,
-dp_codop  => dp_codop,
-dp_opx_sign => dp_opx_sign,
-dp_sr_mode  => dp_sr_mode,
-dp_sr_mask  => dp_sr_mask,
-sts_ctlrw  => sts_ctlrw,
-sts_wenable  => sts_wenable,
-seq_ctlopy  => seq_ctlopy,
-seq_ctlopx  => seq_ctlopx,
-ad_n_31 => dp_adr_n_31,
-ad_n_1 => dp_adr_n_1,	
-ad_n_0 => dp_adr_n_0,
-
-seq_ctlrw=> seq_ctlrw,
-seq_ctlalu=> seq_ctlalu,
-seq_wenable=> seq_wenable,
-  vdd => vdd,
-  vss => vss
-);
-  
-  
-end structural_view;
diff --git a/alliance/share/tutorials/dlxm/dlxm_cpu.pat b/alliance/share/tutorials/dlxm/dlxm_cpu.pat
deleted file mode 100644
index bb51f9dc..00000000
--- a/alliance/share/tutorials/dlxm/dlxm_cpu.pat
+++ /dev/null
@@ -1,1054 +0,0 @@
-
--- ### -------------------------------------------------------------- ###
--- #									#
--- # file	: dlxm_cpu.pat						#
--- # date	: February 1995						#
--- # version	: v0.0							#
--- #									#
--- # origin	: this description has been developed by CAO-VLSI team	#
--- #		  at MASI laboratory, University Pierre et Marie Curie	#
--- #		  URA CNRS 818, Institut Blaise Pascal			#
--- #		  4 Place Jussieu 75252 Paris Cedex 05 - France		#
--- # E-mail      :      cao-vlsi@masi.ibp.fr                            #
--- #									#
--- # descr.	: pattern input file for simulating various views of    #
--- #	          the dlxm chip inside  the board dlxm_cpu.vst		#
--- #									#
--- ### -------------------------------------------------------------- ###
-
-in       ck;;
-in       divers            (vss, vdd, frz, test, scin) O;;
-in       intrpt            (reset , it (2 downto 0)      ) O;;
-signal   it0 ;;
-out      acces             (rw    , byte (0 to 3)        ) X;;
-inout    data_adr          (31 downto 0) X;;
-inout    data              (31 downto 0) X;;
-
-begin
-
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-  : 0 10 07 ?* ?** ?******** ?******** ;
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-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
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-  : 0 10 07 ?* ?** ?******** ?******** ;
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-  : 1 10 07 ?* ?** ?******** ?******** ;
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-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
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-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
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-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
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-  : 0 10 07 ?* ?** ?******** ?******** ;
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-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
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-  : 0 10 07 ?* ?** ?******** ?******** ;
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-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
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-  : 0 10 07 ?* ?** ?******** ?******** ;
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-  : 0 10 07 ?* ?** ?******** ?******** ;
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-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
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-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
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-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
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-  : 1 10 07 ?* ?** ?******** ?******** ;
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-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
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-  : 1 10 07 ?* ?** ?******** ?******** ;
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-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
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-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-  : 1 10 07 ?* ?** ?******** ?******** ;
-  : 0 10 07 ?* ?** ?******** ?******** ;
-end;
diff --git a/alliance/share/tutorials/dlxm/dlxm_cpu.vst b/alliance/share/tutorials/dlxm/dlxm_cpu.vst
deleted file mode 100644
index 4245eca3..00000000
--- a/alliance/share/tutorials/dlxm/dlxm_cpu.vst
+++ /dev/null
@@ -1,216 +0,0 @@
--- ### -------------------------------------------------------------- ###
--- #									#
--- # file	: dlxm_cpu.vst						#
--- # date	: February 1995           				#
--- # version	: v0.2							#
--- # author	: Pirouz BAZARGAN SABET					#
--- #		  at MASI laboratory, University Pierre et Marie Curie	#
--- #		  URA CNRS 818, Institut Blaise Pascal			#
--- #		  4 Place Jussieu 75252 Paris Cedex 05 - France		#
--- # Email	: cao-vlsi@masi.ibp.fr					#
--- #									#
--- # descr.	: DLXp cpu board with on board ram (512 bytes), rom	#
--- #		  (512 bytes = 128 instructions) and, timer		#
--- #									#
--- ### -------------------------------------------------------------- ###
-
-entity dlxp_cpu is
-  port (
-       CK       : in    bit                         ;
-       TEST     : in    bit                         ;
-       SCIN     : in    bit                         ;
-       SCOUT    : out   bit                         ;
-       IT       : in    bit_vector ( 2 downto 0)    ;
-       RESET    : in    bit                         ;
-       FRZ      : in    bit                         ;
-       RW       : inout bit                         ;
-       BYTE     : inout bit_vector ( 0     to 3)    ;
-       DATA     : inout mux_vector (31 downto 0) bus;
-       DATA_ADR : inout mux_vector (31 downto 0) bus;
-       VDD      : in    bit                         ;
-       VSS      : in    bit
-       );
-
-end dlxp_cpu;
-
-architecture structral of dlxp_cpu is
-
-  signal E_RAMU_N : bit_vector ( 0     to 3)    ;
-  signal E_RAMS_N : bit_vector ( 0     to 3)    ;
-  signal E_ROMU_N : bit                         ;
-  signal E_ROMS_N : bit                         ;
-  signal E_TIME_N : bit                         ;
-
-  signal IT0      : wor_bit                  bus;
-
-  component dlxm_chip
-    port ( 
-         CK      : in    bit                          ;
-         RESET   : in    bit                          ;
-         FRZ     : in    bit                          ;
-         IT      : in    bit_vector ( 3 downto 0)     ;
-         DATA    : inout mux_vector (31 downto 0) bus ;
-         BYTE    : out   bit_vector ( 0     to 3)     ;
-         RW      : out   bit                          ;
-         ADR     : out   mux_vector (31 downto 0) bus ;
-         SCIN    : in    bit                          ;
-         TEST    : in    bit                          ;
-         SCOUT   : out   bit                          ;
-         VDD     : in    bit                          ;
-         VSS     : in    bit                          ;
-         VDDP    : in    bit                          ;
-         VSSP    : in    bit
-         ) ;
-  end component;
-
-  component dlxm_dec
-    port (
-         CK          : in    bit                         ;
-         DLX_DADR    : in    bit_vector (31 downto 0)    ;
-         RW          : in    bit                         ;
-         BYTE        : in    bit_vector ( 0     to 3)    ;
-         SEL_ROMU_N  : out   bit                         ;
-         SEL_RAMU_N  : out   bit_vector ( 0     to 3)    ;
-         SEL_ROMS_N  : out   bit                         ;
-         SEL_RAMS_N  : out   bit_vector ( 0     to 3)    ;
-         SEL_TIMER_N : out   bit                         ;
-         VDD         : in    bit                         ;
-         VSS         : in    bit
-         );
-  end component;
-
-  component sr64_32a
-    port (
-         E_N         : in    bit_vector ( 0     to 3)    ;
-         W_N         : in    bit                         ;
-         DAT         : inout mux_vector (31 downto 0) bus;
-         ADR         : in    bit_vector ( 5 downto 0)    ;
-         VDD         : in    bit                         ;
-         VSS         : in    bit
-         );
-  end component;
-
-  component romu
-    port (
-         ADDRESS : in  bit_vector (5  downto 0)    ;
-         E_N     : in  bit                         ;
-         DATA    : out mux_vector (31 downto 0) bus;
-         VDD     : in  bit                         ;
-         VSS     : in  bit
-         );
-  end component;
-
-  component roms
-    port (
-         ADDRESS : in  bit_vector (5  downto 0)    ;
-         E_N     : in  bit                         ;
-         DATA    : out mux_vector (31 downto 0) bus;
-         VDD     : in  bit                         ;
-         VSS     : in  bit
-         );
-  end component;
-
-  component timer
-    port (
-      CK      : in    bit                         ;
-      FRZ     : in    bit                         ;
-      RESET   : in    bit                         ;
-      SEL     : in    bit_vector ( 2 downto 0)    ;
-      DATA    : inout mux_vector (31 downto 0) bus;
-      RW      : in    bit                         ;
-      E_N     : in    bit                         ;
-      IRQ_N   : out   wor_bit                  bus;
-      VDD     : in    bit                         ;
-      VSS     : in    bit
-      );
-  end component;
-
-begin
-
-  dlxm_chip : dlxm_chip
-    port map (
-             IT    => IT & IT0 ,
-             TEST  => TEST     ,
-             SCIN  => SCIN     ,
-             SCOUT => SCOUT    ,
-             FRZ   => FRZ      ,
-             RESET => RESET    ,
-             ADR   => DATA_ADR ,
-             BYTE  => BYTE     ,
-             RW    => RW       ,
-             CK    => CK       ,
-             DATA  => DATA     ,
-             VDDP  => VDD      ,
-             VSSP  => VSS      ,
-             VDD   => VDD      ,
-             VSS   => VSS
-             );
-
-  dlxm_dec : dlxm_dec
-    port map (
-             CK          => CK       ,
-             DLX_DADR    => DATA_ADR ,
-             RW          => RW       ,
-             BYTE        => BYTE     ,
-             SEL_ROMU_N  => E_ROMU_N ,
-             SEL_RAMU_N  => E_RAMU_N ,
-             SEL_ROMS_N  => E_ROMS_N ,
-             SEL_RAMS_N  => E_RAMS_N ,
-             SEL_TIMER_N => E_TIME_N ,
-             VDD         => VDD      ,
-             VSS         => VSS
-             );
-
-  timer : timer
-    port map (
-      CK      => CK                    ,
-      FRZ     => VSS                   ,
-      RESET   => RESET                 ,
-      SEL     => DATA_ADR (4 downto 2) ,
-      DATA    => DATA                  ,
-      RW      => RW                    ,
-      E_N     => E_TIME_N              ,
-      IRQ_N   => IT0                   ,
-      VDD     => VDD                   ,
-      VSS     => VSS
-      );
-
-  ramu : sr64_32a
-    port map (
-             E_N => E_RAMU_N               ,
-             W_N => RW                     ,
-             DAT => DATA                   ,
-             ADR => DATA_ADR ( 7 downto 2) ,
-             VDD => VDD                    ,
-             VSS => VSS
-             );
-
-  romu : romu
-    port map (
-             ADDRESS => DATA_ADR (7 downto 2) ,
-             E_N     => E_ROMU_N              ,
-             DATA    => DATA                  ,
-             VDD     => VDD                   ,
-             VSS     => VSS
-             );
-
-  rams : sr64_32a
-    port map (
-             E_N => E_RAMS_N               ,
-             W_N => RW                     ,
-             DAT => DATA                   ,
-             ADR => DATA_ADR ( 7 downto 2) ,
-             VDD => VDD                    ,
-             VSS => VSS
-             );
-
-  roms : roms
-    port map (
-             ADDRESS => DATA_ADR (7 downto 2) ,
-             E_N     => E_ROMS_N              ,
-             DATA    => DATA                  ,
-             VDD     => VDD                   ,
-             VSS     => VSS
-             );
-
-end;
diff --git a/alliance/share/tutorials/dlxm/dlxm_ctl.scr b/alliance/share/tutorials/dlxm/dlxm_ctl.scr
deleted file mode 100644
index a79a0633..00000000
--- a/alliance/share/tutorials/dlxm/dlxm_ctl.scr
+++ /dev/null
@@ -1,74 +0,0 @@
-### ----------------------------------------------------------------- ###
-#									#
-# file		: dlxm_ctl.scr						#
-# date		: February 1995						#
-# version	: v0.0							#
-#									#
-# origin	: this description has been developed by CAO-VLSI team	#
-#		  at MASI laboratory, University Pierre et Marie Curie	#
-#		  URA CNRS 818, Institut Blaise Pascal			#
-#		  4 Place Jussieu 75252 Paris Cedex 05 - France		#
-# E-mail       :      cao-vlsi@masi.ibp.fr                              #
-#									#
-# descr.	: placement file for control block connectors		#
-#									#
-### ----------------------------------------------------------------- ###
-
-
-
-PLACE_PHCON_NORTH  frz_ctl[15:0] 1:16    ;# frz_ctl
-PLACE_PHCON_NORTH  frz -1         ;# frz
-PLACE_PHCON_NORTH  ck -1          ;# ck
-PLACE_PHCON_NORTH  it[3:0] -1     ;# it
-PLACE_PHCON_NORTH  scout -1       ;# scout
-PLACE_PHCON_NORTH  reset -1       ;# reset
-PLACE_PHCON_NORTH  byte[3:0] -1   ;# byte
-PLACE_PHCON_NORTH  rw -1          ;# rw
-
-# control of data bus
-PLACE_PHCON_EAST  rw_ctl[15:0] -1      ;# rw_ctl
-
-# interface with DataPath
-
-PLACE_PHCON_SOUTH  test -1        ;# test
-PLACE_PHCON_SOUTH  seq_ctladr -1;
-PLACE_PHCON_SOUTH  scin -1        ;# scin
-PLACE_PHCON_SOUTH  sts_zero -1;
-PLACE_PHCON_SOUTH  sts_sr_cpurst -1;    # sts_sr_cpurst
-PLACE_PHCON_SOUTH  sts_sr_it3 -1;      # sts_sr_it
-PLACE_PHCON_SOUTH  sts_sr_it2 -1;      # sts_sr_it
-PLACE_PHCON_SOUTH  sts_sr_it1 -1;      # sts_sr_it
-PLACE_PHCON_SOUTH  sts_sr_it0 -1;      # sts_sr_it
-PLACE_PHCON_SOUTH  sts_sr_ico -1;      # sts_sr_ico
-PLACE_PHCON_SOUTH  sts_sr_iav -1;      # sts_sr_iav
-PLACE_PHCON_SOUTH  sts_sr_dav -1;      # sts_sr_dav
-PLACE_PHCON_SOUTH  sts_sr_ovr -1;      # sts_sr_ovr
-PLACE_PHCON_SOUTH  sts_wrtpnt[4:0] -1;
-PLACE_PHCON_SOUTH  sts_redpnt[4:0] -1;
-PLACE_PHCON_SOUTH  sts_alu_test -1;    # sts_alu_test
-PLACE_PHCON_SOUTH  dp_alu_sign -1;     # dp_alu_sign
-PLACE_PHCON_SOUTH  dp_alu_nul -1;      # dp_alu_nul
-PLACE_PHCON_SOUTH  dp_alu_c30 -1;    # dp_alu_c30_n
-PLACE_PHCON_SOUTH  dp_alu_c31 -1;    # dp_alu_c31_n
-PLACE_PHCON_SOUTH  dp_opy_sign -1;     # dp_opy_sign
-PLACE_PHCON_SOUTH  dp_ir_sr -1;        # dp_ir_sr
-PLACE_PHCON_SOUTH  dp_ir_iar -1;       # dp_ir_iar
-PLACE_PHCON_SOUTH  dp_ir_tvr -1;       # dp_ir_tvr
-PLACE_PHCON_SOUTH  dp_rd[4:0] -1;      # dp_rd
-PLACE_PHCON_SOUTH  dp_rdrt[4:0] -1;    # dp_rdrt
-PLACE_PHCON_SOUTH  dp_rs[4:0] -1;      # dp_rs
-PLACE_PHCON_SOUTH  dp_codop[5:0] -1;   # dp_codop
-PLACE_PHCON_SOUTH  dp_opx_sign -1;     # dp_opx_sign
-PLACE_PHCON_SOUTH  dp_sr_mode -1;      # dp_sr_mode
-PLACE_PHCON_SOUTH  dp_sr_mask -1;      # dp_sr_mask
-PLACE_PHCON_SOUTH  sts_ctlrw[3:2] -1;     # sts_ctlrw
-PLACE_PHCON_SOUTH  sts_wenable[5:0] -1;   # sts_wenable
-PLACE_PHCON_SOUTH  seq_ctlopy[4:0] -1;    # seq_ctlopy
-PLACE_PHCON_SOUTH  seq_ctlopx[5:0] -1;    # seq_ctlopx
-PLACE_PHCON_SOUTH  ad_n_31 -1;
-PLACE_PHCON_SOUTH  ad_n_1 -1;
-PLACE_PHCON_SOUTH  ad_n_0 -1;
-     # Connectors used for control and datapath
-PLACE_PHCON_SOUTH  seq_ctlrw[3:0] -1;
-PLACE_PHCON_SOUTH  seq_ctlalu[4:0] -1;
-PLACE_PHCON_SOUTH  seq_wenable[8:0] -1;
diff --git a/alliance/share/tutorials/dlxm/dlxm_ctl.vst.h b/alliance/share/tutorials/dlxm/dlxm_ctl.vst.h
deleted file mode 100644
index cb07cd5c..00000000
--- a/alliance/share/tutorials/dlxm/dlxm_ctl.vst.h
+++ /dev/null
@@ -1,281 +0,0 @@
-
--- ### -------------------------------------------------------------- ###
--- #									#
--- # file	: dlxm_ctl.vst.h					#
--- # date	: February 1995						#
--- # version	: v0.0							#
--- #									#
--- # origin	: this description has been developed by CAO-VLSI team	#
--- #		  at MASI laboratory, University Pierre et Marie Curie	#
--- #		  URA CNRS 818, Institut Blaise Pascal			#
--- #		  4 Place Jussieu 75252 Paris Cedex 05 - France		#
--- # E-mail      :      cao-vlsi@masi.ibp.fr                            #
--- #									#
--- # descr.	: structural model of the control instantiating		#
--- #		  the sequencer and the status				#
--- #		  2*16 output control signals for data and address bus	#
--- #									#
--- ### -------------------------------------------------------------- ###
-
-
-
-
--- Entity Declaration
-
-Entity dlxm_ctl is
-PORT(
-  it : in BIT_VECTOR(3 DOWNTO 0);       	-- it
-  scin : in BIT;        			-- scin
-  scout : out BIT;      			-- scout
-  test : in BIT;        			-- test
-  reset : in BIT;       			-- external reset
-  frz : in BIT; 				-- frz
-  byte : out BIT_VECTOR(0 to 3);    		-- byte
-  rw : out BIT; 				-- rw
-  rw_ctl : out BIT_VECTOR(15 downto 0);         -- tristate data control
-  frz_ctl : out BIT_VECTOR(15 downto 0);        -- tristate address control
-  ck : in BIT;  				-- ck
-
--- Interface with data path
-
-seq_ctladr : out BIT;
-sts_zero : out BIT;
-sts_sr_cpurst : inout BIT;    -- cpureset flag to datapath
-sts_sr_it3 : out BIT;      -- sts_sr_it
-sts_sr_it2 : out BIT;      -- sts_sr_it
-sts_sr_it1 : out BIT;      -- sts_sr_it
-sts_sr_it0 : out BIT;      -- sts_sr_it
-sts_sr_ico : out BIT;      -- sts_sr_ico
-sts_sr_iav : out BIT;      -- sts_sr_iav
-sts_sr_dav : out BIT;      -- sts_sr_dav
-sts_sr_ovr : out BIT;      -- sts_sr_ovr
-sts_wrtpnt : out BIT_VECTOR(4 downto 0);
-sts_redpnt : out BIT_VECTOR (4 downto 0);
-sts_alu_test : out BIT;    -- sts_alu_test
-dp_alu_sign : in BIT;     -- dp_alu_sign
-dp_alu_nul : in BIT;      -- dp_alu_nul
-dp_alu_c30 : in BIT;    -- dp_alu_c30_n
-dp_alu_c31 : in BIT;    -- dp_alu_c31_n
-dp_opy_sign : in BIT;     -- dp_opy_sign
-dp_ir_sr : in BIT;        -- dp_ir_sr
-dp_ir_iar : in BIT;       -- dp_ir_iar
-dp_ir_tvr : in BIT;       -- dp_ir_tvr
-dp_rd : in BIT_VECTOR(4 downto 0);   -- dp_rd
-dp_rdrt : in BIT_VECTOR(4 downto 0); -- dp_rdrt
-dp_rs : in BIT_VECTOR(4 downto 0); -- dp_rs
-dp_codop : in BIT_VECTOR(5 downto 0);-- dp_codop
-dp_opx_sign : in BIT;     -- dp_opx_sign
-dp_sr_mode : in BIT;      -- dp_sr_mode
-dp_sr_mask : in BIT;      -- dp_sr_mask
-sts_ctlrw : out BIT_VECTOR(3 downto 2);     -- sts_ctlrw
-sts_wenable : out BIT_VECTOR(5 downto 0);   -- sts_wenable
-seq_ctlopy : out BIT_VECTOR(4 downto 0);      -- seq_ctlopy
-seq_ctlopx : out BIT_VECTOR(5 downto 0);    -- seq_ctlopx
-ad_n_31:in bit;
-ad_n_1:in bit;
-ad_n_0:in bit;
-  -- Connecteur utilises en interne ET le datapath
-seq_ctlrw: inout bit_vector(3 downto 0);
-seq_ctlalu: inout bit_vector(4 downto 0);
-seq_wenable: inout bit_vector(8 downto 0);
-
-  vdd : in BIT; -- vdd
-  vss : in BIT  -- vss
-
-  );
-
-END dlxm_ctl;
-
--- Architecture Declaration
-
-ARCHITECTURE structural_view OF dlxm_ctl IS
-  COMPONENT dlxm_seq
-    port (
-    ck : in BIT;	-- ck
-    frz : in BIT;	-- frz
-    rqs : in BIT;	-- rqs
-    reset : in BIT;	-- reset flag from status
-    resnul : in BIT;	-- resnul
-    ir_opcod : in BIT_VECTOR(5 DOWNTO 0);	-- ir_opcod
-    ir_tvr : in BIT;	-- ir_tvr
-    ir_iar : in BIT;	-- ir_iar
-    ir_sr : in BIT;	-- ir_sr
-    vdd : in BIT;	-- vdd
-    vss : in BIT;	-- vss
-    scin : in BIT;	-- scin
-    test : in BIT;	-- test
-    ovr_en : out BIT;	-- ovr_en
-    ico : out BIT;      -- ico
-    priv : out BIT;	-- priv 
-    iformt : out BIT;	-- iformt 
-    riformt : out BIT;	-- iformt 
-    ctlopx : out BIT_VECTOR(5 DOWNTO 0);	-- ctlopx
-    ctlopy : out BIT_VECTOR(4 DOWNTO 0);	-- ctlopy
-    ctlalu : out BIT_VECTOR(4 DOWNTO 0);	-- ctlalu
-    wenable : out BIT_VECTOR(8 DOWNTO 0);	-- wenable
-    ctlrw : out BIT_VECTOR(3 DOWNTO 0);	-- ctlrw
-    ctladr : out BIT;	-- ctladr
-    scout : out BIT	-- scout
-    );
-  END COMPONENT;
-
-  COMPONENT dlxm_sts
-    port (
-    ck : in BIT;	-- ck
-    frz : in BIT;	-- frz
-    reset : in BIT;	-- external reset
-    test : in BIT;	-- test
-    ctlalu : in BIT_VECTOR(4 DOWNTO 0);	-- ctlalu
-    opx_sign : in BIT;	-- opx_sign
-    opy_sign : in BIT;	-- opy_sign
-    alu_sign : in BIT;	-- alu_sign
-    alu_nul : in BIT;	-- alu_nul
-    alu_c31 : in BIT;	-- alu_c31_n
-    alu_c30 : in BIT;	-- alu_c30_n
-    ovr_en : in BIT;	-- ovr_en
-    ico : in BIT;   -- illegal codop
-    priv : in BIT;  -- privil 
-    iformt : in BIT;  -- format i 
-    riformt : in BIT;  -- format i 
-    rs : in BIT_VECTOR(4 DOWNTO 0);	-- rs
-    rd : in BIT_VECTOR(4 DOWNTO 0);	-- rd
-    rdrt : in BIT_VECTOR(4 DOWNTO 0);	-- rdrt
-    mxrs_rdrt : in BIT;	-- mxrs_rdrt
-    wenable_in : in BIT_VECTOR(8 DOWNTO 0);	-- wenable_in
-    ctlrw_in : in BIT_VECTOR(3 DOWNTO 0);	-- ctlrw_in
-    sr_mode : in BIT;	-- sr_mode
-    sr_mask : in BIT;	-- sr_mask
-    adr0 : in BIT;	-- adr0
-    adr1 : in BIT;	-- adr1
-    adr31 : in BIT;	-- adr31
-    intrqs : in BIT_VECTOR(3 DOWNTO 0);	-- intrqs
-    scin : in BIT;	-- scin
-    alu_test : out BIT;	-- alu_test
-    redpnt : out BIT_VECTOR(4 DOWNTO 0);	-- redpnt
-    wrtpnt : out BIT_VECTOR(4 DOWNTO 0);	-- wrtpnt
-    wenable_out : out BIT_VECTOR(5 DOWNTO 0);	-- wenable_out
-    ctlrw_out : out BIT_VECTOR(3 DOWNTO 2);	-- ctlrw_out
-    sr_ovr : out BIT;	-- sr_ovr
-    sr_dav : out BIT;	-- sr_dav
-    sr_iav : out BIT;	-- sr_iav
-    sr_ico : out BIT;	-- sr_ico
-    sr_it0 : out BIT;	-- sr_it0
-    sr_it1 : out BIT;	-- sr_it1
-    sr_it2 : out BIT;	-- sr_it2
-    sr_it3 : out BIT;	-- sr_it3
-    sr_cpurst : out BIT;	-- cpureset flag to datapath
-    sts_reset : out BIT;        -- reset flag to sequencer
-    rqs : out BIT;	-- rqs
-    rw : out BIT;	-- rw
-    rw_ctl : out BIT_VECTOR(15 DOWNTO 0);	-- data control
-    frz_ctl : out BIT_VECTOR(15 DOWNTO 0);	-- address control
-    byte : out BIT_VECTOR(0 to 3);	-- byte
-    scout : out BIT;	-- scout
-    zero : out BIT;	-- zero
-    vdd : in BIT;	-- vdd
-    vss : in BIT	-- vss
-    );
-  END COMPONENT;
-
-  COMPONENT dlxm_boost
-  port(i : in bit;
-       o : out bit_vector(15 downto 0);
-       vss,vdd:in bit);
-  END COMPONENT;
-
-  SIGNAL sts_rqs : BIT;	-- sts_rqs
-  SIGNAL seq_scout : BIT;	-- seq_scout
-  SIGNAL seq_ico : BIT;	-- seq_ico_en
-  SIGNAL seq_priv : BIT;
-  SIGNAL seq_iformt : BIT;
-  SIGNAL seq_riformt : BIT;
-  SIGNAL seq_ovr_en : BIT;	-- seq_ovr_en
-  SIGNAL sts_reset_seq : BIT ;			-- reset flag from status to seq
-
-BEGIN
-
-  seq : dlxm_seq
-    PORT MAP (
-    scout => seq_scout,
-    ctladr => seq_ctladr,
-    ctlrw => seq_ctlrw,
-    wenable => seq_wenable,
-    ctlalu => seq_ctlalu,
-    ctlopy => seq_ctlopy,
-    ctlopx => seq_ctlopx,
-    ico => seq_ico,
-    priv => seq_priv,
-    iformt => seq_iformt,
-    riformt => seq_riformt,
-    ovr_en => seq_ovr_en,
-    test => test,
-    scin => scin,
-    vss => vss,
-    vdd => vdd,
-    ir_sr => dp_ir_sr,
-    ir_iar => dp_ir_iar,
-    ir_tvr => dp_ir_tvr,
-    ir_opcod => dp_codop,
-    resnul => dp_alu_nul,
-    reset => sts_reset_seq,			-- reset flag from status
-    rqs => sts_rqs,
-    frz => frz,
-    ck => ck);
-  
-  sts : dlxm_sts
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    zero => sts_zero,
-    scout => scout,
-    byte => byte(0)& byte(1)& byte(2)& byte(3),
-    frz_ctl => frz_ctl,			-- adress ctl, with buffer
-    rw_ctl => rw_ctl,			-- data ctl, with buffer
-    rw => rw,
-    rqs => sts_rqs,
-    sts_reset => sts_reset_seq,			-- reset flag to sequencer
-    sr_cpurst => sts_sr_cpurst,			-- reset flag to dpt
-    sr_it3 => sts_sr_it3,
-    sr_it2 => sts_sr_it2,
-    sr_it1 => sts_sr_it1,
-    sr_it0 => sts_sr_it0,
-    sr_ico => sts_sr_ico,
-    sr_iav => sts_sr_iav,
-    sr_dav => sts_sr_dav,
-    sr_ovr => sts_sr_ovr,
-    ctlrw_out => sts_ctlrw,
-    wenable_out => sts_wenable,
-    wrtpnt => sts_wrtpnt,
-    redpnt => sts_redpnt,
-    alu_test => sts_alu_test,
-    scin => seq_scout,
-    intrqs => it(3)& it(2)& it(1)& it(0),
-    adr31 => ad_n_31,
-    adr1 => ad_n_1,
-    adr0 => ad_n_0,
-    sr_mask => dp_sr_mask,
-    sr_mode => dp_sr_mode,
-    ctlrw_in => seq_ctlrw,
-    wenable_in => seq_wenable,
-    mxrs_rdrt => seq_ctlopx(0),
-    rdrt => dp_rdrt,
-    rd => dp_rd,
-    rs => dp_rs,
-    ico => seq_ico,
-    priv => seq_priv,
-    iformt => seq_iformt,
-    riformt => seq_riformt,
-    ovr_en => seq_ovr_en,
-    alu_c30 => dp_alu_c30,
-    alu_c31 => dp_alu_c31,
-    alu_nul => dp_alu_nul,
-    alu_sign => dp_alu_sign,
-    opy_sign => dp_opy_sign,
-    opx_sign => dp_opx_sign,
-    ctlalu => seq_ctlalu,
-    test => test,
-    reset => reset,			-- external reset
-    frz => frz,
-    ck => ck);
-
-end structural_view;
diff --git a/alliance/share/tutorials/dlxm/dlxm_dec.vbe b/alliance/share/tutorials/dlxm/dlxm_dec.vbe
deleted file mode 100644
index 9526ef83..00000000
--- a/alliance/share/tutorials/dlxm/dlxm_dec.vbe
+++ /dev/null
@@ -1,178 +0,0 @@
--- ### -------------------------------------------------------------- ###
--- #									#
--- # file	: dlxm_dec.vbe						#
--- # date	: Dec 31 1994						#
--- # version	: v0.2							#
--- # author	: Pirouz BAZARGAN SABET					#
--- #		  at MASI laboratory, University Pierre et Marie Curie	#
--- #		  URA CNRS 818, Institut Blaise Pascal			#
--- #		  4 Place Jussieu 75252 Paris Cedex 05 - France		#
--- # E-mail      :      cao-vlsi@masi.ibp.fr                            #
--- #									#
--- # descr.	: data flow description of an address decoder for DLX	#
--- #									#
--- ### -------------------------------------------------------------- ###
-
-entity dlxm_dec is
-
-port (
-   ck          : in    bit                         ;	-- external clock
-   dlx_dadr    : in    bit_vector (31 downto 0)    ;	-- data address
-   rw          : in    bit                         ;	-- read write
-   byte        : in    bit_vector ( 0     to 3)    ;	-- valid bytes
-   sel_romu_n  : out   bit                         ;	-- user rom
-   sel_ramu_n  : out   bit_vector ( 0     to 3)    ;	-- user ram
-   sel_roms_n  : out   bit                         ;	-- system rom
-   sel_rams_n  : out   bit_vector ( 0     to 3)    ;	-- system ram
-   sel_timer_n : out   bit                         ;	-- timer
-   vdd         : in    bit                         ;	--
-   vss         : in    bit				--
-  );
-
-end dlxm_dec;
-
-architecture FUNCTIONAL of dlxm_dec is
-
-  signal rams     : bit                              ;	-- select system ram
-  signal ramu     : bit                              ;	-- select user ram
-  signal roms     : bit                              ;	-- select system rom
-  signal romu     : bit                              ;	-- select user rom
-  signal timer    : bit                              ;	-- select system timer
-  signal dly0_ck  : bit                              ;	-- delayed clock
-  signal dly1_ck  : bit                              ;	-- delayed clock
-  signal dly2_ck  : bit                              ;	-- delayed clock
-  signal dly3_ck  : bit                              ;	-- delayed clock
-  signal dly4_ck  : bit                              ;	-- delayed clock
-  signal dly5_ck  : bit                              ;	-- delayed clock
-  signal dlyd_ck  : bit                              ;	-- delayed clock
-
-  signal bad_cry  : bit_vector ( 3 downto 0)         ;	-- adder's carry
-  signal bad_add  : bit_vector ( 2 downto 0)         ;	-- bad counter's adder
-  signal bad_cnt  : reg_vector ( 2 downto 0) register;	-- bad address counter
-  signal good_cry : bit_vector ( 3 downto 0)         ;	-- adder's carry
-  signal good_add : bit_vector ( 2 downto 0)         ;	-- good counter's adder
-  signal good_cnt : reg_vector ( 2 downto 0) register;	-- good address counter
-
-  constant BAD    : bit_vector (31 downto 0) := X"7ffffff8";	-- bad  address
-  constant GOOD   : bit_vector (31 downto 0) := X"7ffffff0";	-- good address
-
-begin
-
-  dly0_ck      <= ck;
-  dly1_ck      <= dly0_ck;
-  dly2_ck      <= dly1_ck;
-  dly3_ck      <= dly2_ck;
-  dly4_ck      <= dly3_ck;
-  dly5_ck      <= dly4_ck;
-  dlyd_ck      <= dly5_ck;
-
-	-- ### ------------------------------------------------------ ###
-	-- #   select on board user/system ram-rom depending on data	#
-	-- # addresses :						#
-	-- #								#
-	-- #     0000_0000 - user ram					#
-	-- #     0000_00FF - user ram					#
-	-- #								#
-	-- #     0000_0100 - off board ram extension			#
-	-- #     7FFF_FEFF - off board ram extension			#
-	-- #								#
-	-- #     7FFF_FF00 - user rom					#
-	-- #     7FFF_FFFF - user rom					#
-	-- #								#
-	-- #     8000_0000 - system ram					#
-	-- #     8000_00FF - system ram					#
-	-- #								#
-	-- #     8000_0100 - system timer				#
-	-- #     8000_01FF - system timer				#
-	-- #								#
-	-- #     8000_0200 - off board ram extension			#
-	-- #     FFFF_FFFF - off board ram extension			#
-	-- #								#
-	-- #     FFFF_FF00 - system rom					#
-	-- #     FFFF_FFFF - system rom					#
-	-- ### ------------------------------------------------------ ###
-
-  with dlx_dadr (31 downto 8) select
-  ramu  <= '1' when X"0000_00",
-           '0' when others;
-
-  with dlx_dadr (31 downto 8) select
-  romu  <= '1' when X"7FFF_FF",
-           '0' when others;
-
-  with dlx_dadr (31 downto 8) select
-  rams  <= '1' when X"8000_00",
-           '0' when others;
-
-  with dlx_dadr (31 downto 8) select
-  timer  <= '1' when X"8000_01",
-            '0' when others;
-
-  with dlx_dadr (31 downto 8) select
-  roms  <= '1' when X"FFFF_FF",
-           '0' when others;
-
-	-- ### ------------------------------------------------------ ###
-	-- #   assign outputs						#
-	-- #     - effective selection of ram chips (on high level of	#
-	-- #       clock to avoid conflicts)				#
-	-- #     - effective selection of rom chips			#
-	-- #     - effective selection of timer				#
-	-- ### ------------------------------------------------------ ###
-
-  sel_ramu_n (0) <= not (ramu  and ck and byte (0));
-  sel_ramu_n (1) <= not (ramu  and ck and byte (1));
-  sel_ramu_n (2) <= not (ramu  and ck and byte (2));
-  sel_ramu_n (3) <= not (ramu  and ck and byte (3));
-
-  sel_rams_n (0) <= not (rams  and ck and byte (0));
-  sel_rams_n (1) <= not (rams  and ck and byte (1));
-  sel_rams_n (2) <= not (rams  and ck and byte (2));
-  sel_rams_n (3) <= not (rams  and ck and byte (3));
-
-  sel_timer_n    <= not (timer and ck and byte(0)
-                                      and byte(1)
-                                      and byte(2)
-                                      and byte(3));
-
-  sel_romu_n     <= not (romu  and ck and byte(0)
-                                      and byte(1)
-                                      and byte(2)
-                                      and byte(3));
-
-  sel_roms_n     <= not (roms  and ck and byte(0)
-                                      and byte(1)
-                                      and byte(2)
-                                      and byte(3));
-
-	-- ### ------------------------------------------------------ ###
-	-- #   watching the address bus to detect the fetch of the	#
-	-- # GOOD or the BAD address (simulation aborts when the	#
-	-- # instruction has been fetched 3 times)			#
-	-- ### ------------------------------------------------------ ###
-
-  bad_cry  (0)          <= '1';
-  bad_cry  (3 downto 1) <= bad_cnt and bad_cry (2 downto 0);
-  bad_add               <= bad_cnt xor bad_cry (2 downto 0);
-
-  good_cry (0)          <= '1';
-  good_cry (3 downto 1) <= good_cnt and good_cry (2 downto 0);
-  good_add              <= good_cnt xor good_cry (2 downto 0);
-
-  bad  : block (ck = '0' and not ck'STABLE and rw = '1' and byte = "1111")
-  begin
-    bad_cnt  <= guarded bad_add  when (dlx_dadr = BAD ) else
-                        "000"      ;
-    good_cnt <= guarded good_add when (dlx_dadr = GOOD) else
-                        "000"      ;
-  end block;
-
-  assert (not (bad_cnt = "011"))
-  report  "==== KO : Simulation has ended with functional test BAD  ===="
-  severity ERROR;
-
-  assert (not (good_cnt = "011"))
-  report  "==== OK : Simulation has ended with functional test GOOD ===="
-  severity ERROR;
-
-end FUNCTIONAL;
diff --git a/alliance/share/tutorials/dlxm/dlxm_dpt.c b/alliance/share/tutorials/dlxm/dlxm_dpt.c
deleted file mode 100644
index b6c980ac..00000000
--- a/alliance/share/tutorials/dlxm/dlxm_dpt.c
+++ /dev/null
@@ -1,956 +0,0 @@
-/*
--- ### -------------------------------------------------------------- ###
--- #									#
--- # file	: dlxm_dpt.c						#
--- # date	: February 1995						#
--- # version	: v0.0							#
--- #									#
--- # origin	: this description has been developed by CAO-VLSI team	#
--- #		  at MASI laboratory, University Pierre et Marie Curie	#
--- #		  URA CNRS 818, Institut Blaise Pascal			#
--- #		  4 Place Jussieu 75252 Paris Cedex 05 - France		#
--- # E-mail      :      cao-vlsi@masi.ibp.fr                            #
--- #									#
--- # descr.	: source code for datapath generator FPGEN		#
--- #									#
--- ### -------------------------------------------------------------- ###
-*/
-
-#include <genlib.h>
-#include <fpgen.h>
-
-main()
-{
-
-DP_DEFLOFIG("dlxm_dpt", 32L, LSB_INDEX_ZERO);
-
-/*        -- Power supply terminals.
-*/
-DP_LOCON("VDD", IN   ,"vdd");
-DP_LOCON("VSS",   OUT,"vss");
-
-/*    -- Control connectors of registers PC, IAR, AD, IR, DT.
-**    -- Select the function mode (enable SCAN mode when set to one).
-*/
-DP_LOCON("pc_test", IN   ,"pc_test");
-DP_LOCON("ad_test", IN   ,"ad_test");
-DP_LOCON("tvr_test", IN   ,"tvr_test");
-DP_LOCON("iar_test", IN   ,"iar_test");
-DP_LOCON("sr_test", IN   ,"sr_test");
-DP_LOCON("ir_test", IN   ,"ir_test");
-DP_LOCON("dt_test", IN   ,"dt_test");
-
-/*    -- Scan-Path connectors.
-*/
-DP_LOCON("pc_scin", IN   ,"pc_scin");
-DP_LOCON("ad_scin", IN   ,"ad_scin");
-DP_LOCON("tvr_scin", IN   ,"tvr_scin");
-DP_LOCON("iar_scin", IN   ,"iar_scin");
-DP_LOCON("sr_scin", IN   ,"sr_scin");
-DP_LOCON("ir_scin", IN   ,"ir_scin");
-DP_LOCON("dt_scin", IN   ,"dt_scin");
-DP_LOCON("pc_scout",   OUT,"pc_s[31]");
-DP_LOCON("ad_scout",   OUT,"ad_s[31]");
-DP_LOCON("tvr_scout",   OUT,"tvr_s[31]");
-DP_LOCON("iar_scout",   OUT,"iar_s[31]");
-DP_LOCON("sr_scout",   OUT,"sr_s[31]");
-DP_LOCON("ir_scout",   OUT,"ir_s[31]");
-DP_LOCON("dt_scout",   OUT,"dt_s[31]");
-
-/*    -- Clock connectors.
-*/
-DP_LOCON("pc_ck", IN   ,"pc_ck");
-DP_LOCON("ad_ck", IN   ,"ad_ck");
-DP_LOCON("tvr_ck", IN   ,"tvr_ck");
-DP_LOCON("iar_ck", IN   ,"iar_ck");
-DP_LOCON("sr_ck", IN   ,"sr_ck");
-DP_LOCON("ir_ck", IN   ,"ir_ck");
-DP_LOCON("dt_ck", IN   ,"dt_ck");
-
-/*    -- Write enable, active only in normal mode.
-**    -- (enable writing when set to one)
-*/
-DP_LOCON("pc_wen", IN   ,"pc_wen");
-DP_LOCON("ad_wen", IN   ,"ad_wen");
-DP_LOCON("tvr_wen", IN   ,"tvr_wen");
-DP_LOCON("iar_wen", IN   ,"iar_wen");
-DP_LOCON("sr_wen", IN   ,"sr_wen");
-DP_LOCON("ir_wen", IN   ,"ir_wen");
-DP_LOCON("dt_wen", IN   ,"dt_wen");
-
-/*    -- Control connectors of the register file.
-*/
-DP_LOCON("rf_ck", IN   ,"rf_ck");
-DP_LOCON("rf_wen", IN   ,"rf_wen");
-DP_LOCON("rf_aw[4:0]", IN   ,"rf_aw[4:0]");
-DP_LOCON("rf_ar[4:0]", IN   ,"rf_ar[4:0]");
-
-/*    -- Controls connectors of the SR block.
-*/
-DP_LOCON("sr_mx", IN   ,"sr_mx");
-
-/*    -- Flags to write in SR from the CTRL block.
-*/
-DP_LOCON("sr_mode",   OUT,"sr_s[0]");
-DP_LOCON("sr_mask",   OUT,"sr_s[1]");
-DP_LOCON("sr_cpurst", IN   ,"sr_cpurst");
-DP_LOCON("sr_iav", IN   ,"sr_iav");
-DP_LOCON("sr_ico", IN   ,"sr_ico");
-DP_LOCON("sr_dav", IN   ,"sr_dav");
-DP_LOCON("sr_ovr", IN   ,"sr_ovr");
-DP_LOCON("sr_it0", IN   ,"sr_it0");
-DP_LOCON("sr_it1", IN   ,"sr_it1");
-DP_LOCON("sr_it2", IN   ,"sr_it2");
-DP_LOCON("sr_it3", IN   ,"sr_it3");
-
-/*    -- Control connectors of X multiplexer.
-**    -- Select between CH , CB , C0 , R[i] , SR , TVR, IAR , AD , PC.
-*/
-DP_LOCON("opx_ts4", IN   ,"opx_ts4");
-DP_LOCON("opx_ts3", IN   ,"opx_ts3");
-DP_LOCON("opx_ts2", IN   ,"opx_ts2");
-DP_LOCON("opx_ts1", IN   ,"opx_ts1");
-DP_LOCON("opx_ts0", IN   ,"opx_ts0");
-DP_LOCON("opx_mx4", IN   ,"opx_mx4");
-DP_LOCON("opx_mx3", IN   ,"opx_mx3");
-DP_LOCON("opx_mx2", IN   ,"opx_mx2");
-DP_LOCON("opx_mx1", IN   ,"opx_mx1");
-
-/*    -- Sign of X operand ( opx_out[31] )
-*/
-DP_LOCON("opx_sign",   OUT,"opx_ots[31]");
-
-/*    -- Control connectors of Y multiplexer.
-**    -- Select between C16, C4, C0, I16, I18, I28, DT, AD.
-*/
-DP_LOCON("opy_ts4", IN   ,"opy_ts4");
-DP_LOCON("opy_ts3", IN   ,"opy_ts3");
-DP_LOCON("opy_ts2", IN   ,"opy_ts2");
-DP_LOCON("opy_ts1", IN   ,"opy_ts1");
-DP_LOCON("opy_mx4", IN   ,"opy_mx4");
-DP_LOCON("opy_mx3", IN   ,"opy_mx3");
-DP_LOCON("opy_mx2", IN   ,"opy_mx2");
-DP_LOCON("opy_mx1", IN   ,"opy_mx1");
-
-/*    -- When one byte is read, tells which one in a word.
-**    -- (according to the two last bits of "out_adr_n").
-*/
-DP_LOCON("adrw_byte", IN   ,"adrw_byte");
-DP_LOCON("adrw_rb1", IN   ,"adrw_rb1");
-DP_LOCON("adrw_rb0", IN   ,"adrw_rb0");
-
-/*    -- Fields of the IR register.
-*/
-DP_LOCON("opy_codop[5:0]",   OUT,"opy_codop[5:0]");
-DP_LOCON("opy_rs[4:0]",   OUT,"opy_rs[4:0]");
-DP_LOCON("opy_rdrt[4:0]",   OUT,"opy_rdrt[4:0]");
-DP_LOCON("opy_rd[4:0]",   OUT,"opy_rd[4:0]");
-DP_LOCON("opy_tvr",   OUT,"opy_tvr");
-DP_LOCON("opy_sr",   OUT,"opy_sr");
-DP_LOCON("opy_iar",   OUT,"opy_iar");
-
-/*    -- Sign of Y operand ( opy_out[31] )
-*/
-DP_LOCON("opy_sign", OUT,"opy_ots[31]");
-
-/*    -- Main data bus input, from the non inverting pads.
-*/
-/* DP_LOCON("data_in_n[31:0]", IN   ,"data_in_n[31:0]");
-*/
-DP_LOCON("data_in_dpt[31:0]", IN   ,"data_in_dpt[31:0]");
-
-/*    -- Control connectors of ALU multiplexer.
-*/
-DP_LOCON("alu_mx4i0", IN   ,"alu_mx4i0");
-DP_LOCON("alu_mx3i0", IN   ,"alu_mx3i0");
-DP_LOCON("alu_mx2i1", IN   ,"alu_mx2i1");
-DP_LOCON("alu_mx2i0", IN   ,"alu_mx2i0");
-DP_LOCON("alu_mx1i2", IN   ,"alu_mx1i2");
-DP_LOCON("alu_mx1i1", IN   ,"alu_mx1i1");
-DP_LOCON("alu_mx1i0", IN   ,"alu_mx1i0");
-DP_LOCON("alu_mx0i0", IN   ,"alu_mx0i0");
-
-/*    -- Auxiliary ALU inputs/outputs.
-*/
-DP_LOCON("alu_byte", IN   ,"alu_byte");
-DP_LOCON("alu_shrot", IN   ,"alu_shrot");
-DP_LOCON("alu_test_n", IN   ,"alu_test_n");
-DP_LOCON("alu_c31",   OUT,"alu_c31");
-DP_LOCON("alu_c30",   OUT,"alu_c30");
-DP_LOCON("alu_nul",   OUT,"alu_nul");
-DP_LOCON("alu_sign",   OUT,"sum_alu[31]");
-
-/*    -- Main data bus output, to the non inverting pads.
-*/
-DP_LOCON("data_out_dpt[31:0]",   OUT,"data_out_dpt[31:0]");
-
-/*    -- Control connectors of ADROUT multiplexer.
-*/
-DP_LOCON("out_mx0i0",   OUT,"out_mx0i0");
-
-
-/*    -- Main address bus output, to the non inverting pads.
-*/
-DP_LOCON("out_adr[31:0]",   OUT,"out_adr[31:0]");
-
-/*    -- Address bus inverted output, to the status and datapath.
-*/
-
-DP_LOCON("adr_n_31",   INOUT,"out_adr_n[31]");
-DP_LOCON("adr_n_1",   INOUT,"out_adr_n[1]");
-DP_LOCON("adr_n_0",   INOUT,"out_adr_n[0]");
-
-
-/*********************************************************************
-*
-*     Bus ADR OUT Multiplexor 
-*
-*********************************************************************/
-
-#ifdef DPT_DEBUG
-printf(" INV_OUT_ADR \n");
-#endif
-DP_INV(		"INV_OUT_ADR",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		1,
-		"out_adr_n[31:0]",
-		"out_adr[31:0]",
-		EOL);
-
-printf("\n Bus ADR OUT  Multiplexor \n");
-
-DP_NMUX2CS(	"MX_ADR",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"out_mx0i0",
-		"pc_s[31:0]",
-		"ad_s[31:0]",
-		"out_adr_n[31:0]",
-		EOL);
-
-
-/*********************************************************************
-*
-*     Register File R0 = 0 , R1 --> R31
-*
-*********************************************************************/
-
-printf("\n Register File R0 = 0 , R1 --> R31 \n");
-
-DP_RFG1C0(	"RF",
-		32,
-		"rf_ar[4:0]",
-		"rf_wen",
-		"rf_aw[4:0]",
-		"alu_out[31:0]",
-		"rf_s[31:0]",
-		"rf_ck",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" Multiplexor op. X TR_RF_X \n");
-#endif
-DP_BUSE(	"TR_RF_X",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"opx_ts0",
-		"rf_s[31:0]",
-		"opx_ots[31:0]",
-		EOL);
-
-
-/*********************************************************************
-*
-*     Register TVR
-*
-*********************************************************************/
-
-printf("\n Register TVR \n");
-
-DP_PDFFT(	"TVR",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"tvr_scin",
-		"tvr_test",
-		"tvr_wen",
-		"tvr_ck",
-		"alu_out[31:0]",
-		"tvr_s[31:0]",
-        "tvr_ns[31:0]",
-		EOL);
-
-
-/*********************************************************************
-*
-*     Register IAR
-*
-*********************************************************************/
-
-printf("\n Register IAR \n");
-
-DP_PDFFT(	"IAR",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"iar_scin",
-		"iar_test",
-		"iar_wen",
-		"iar_ck",
-		"alu_out[31:0]",
-		"iar_s[31:0]",
-		"iar_ns[31:0]",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" Multiplexor op. X MX_TVR_IAR_X \n");
-#endif
-DP_NMUX2CS(	"MX_TVR_IAR_X",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"opx_mx2",
-		"tvr_s[31:0]",
-		"iar_s[31:0]",
-		"x_tvr_iar[31:0]",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" Multiplexor op. X TR_TVR_IAR_X \n");
-#endif
-DP_NBUSE(	"TR_TVR_IAR_X",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"opx_ts2",
-		"x_tvr_iar[31:0]",
-		"opx_ots[31:0]",
-		EOL);
-
-
-/*********************************************************************
-*
-*     Register PC
-*
-*********************************************************************/
-
-printf("\n Register PC \n");
-
-DP_PDFFT(	"PC",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"pc_scin",
-		"pc_test",
-		"pc_wen",
-		"pc_ck",
-		"alu_out[31:0]",
-		"pc_s[31:0]",
-		"pc_ns[31:0]",
-		EOL);
-
-
-/*********************************************************************
-*
-*     ALU
-*
-*********************************************************************/
-
-printf("\n ALU \n");
-
-#ifdef DPT_DEBUG
-printf(" ADD_ALU \n");
-#endif
-DP_ADSB2F(	"ADD_ALU",
-		"opx_ots[31:0]",
-		"opy_ots[31:0]",
-		"alu_c31",
-		"alu_c30",
-		"sum_alu[31:0]",
-		"alu_mx0i0",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" NUL_ALU \n");
-#endif
-DP_NUL(	"NUL_ALU",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"sum_alu[31:0]",
-		"alu_nul",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" XR_ALU \n");
-#endif
-DP_XOR2(	"XR_ALU",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"opx_ots[31:0]",
-		"opy_ots[31:0]",
-		"xor_alu[31:0]",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" MX_SUM_XOR \n");
-#endif
-DP_NMUX2CS(	"MX_SUM_XOR",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"alu_mx1i2",
-		"sum_alu[31:0]",
-		"xor_alu[31:0]",
-		"sum_xor[31:0]",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" NA_ALU \n");
-#endif
-DP_NAND2(	"NA_ALU",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		1,
-		"opx_ots[31:0]",
-		"opy_ots[31:0]",
-		"nand_alu[31:0]",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" NR_ALU \n");
-#endif
-DP_NOR2(	"NR_ALU",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		1,
-		"opx_ots[31:0]",
-		"opy_ots[31:0]",
-		"nor_alu[31:0]",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" MX_AND_OR \n");
-#endif
-DP_MUX2CS(	"MX_AND_OR",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"alu_mx1i1",
-		"nand_alu[31:0]",
-		"nor_alu[31:0]",
-		"nand_nor[31:0]",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" MX_OP_ALU \n");
-#endif
-DP_NMUX2CS(	"MX_OP_ALU",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"alu_mx2i1",
-		"sum_xor[31:0]",
-		"nand_nor[31:0]",
-		"al_op[31:0]",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" SHF_ALU \n");
-#endif
-DP_SHIFT(	"SHF_ALU",
-		"opy_ots[4:0]",
-		"alu_mx2i0","alu_shrot","alu_mx1i0",
-		"opx_ots[31:0]",
-		"shift_alu[31:0]",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" MX_ALU_SH \n");
-#endif
-DP_NMUX2CS(	"MX_ALU_SH",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"alu_mx3i0",
-		"al_op[31:0]",
-		"shift_alu[31:0]",
-		"op_shift[31:0]",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" MX_ALU_OUT \n");
-#endif
-DP_NMUX2CS(	"MX_ALU_OUT",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"alu_mx4i0",
-		"op_shift[31:0]",
-		"C_n0[31:1]","alu_test_n",
-		"alu_out[31:0]",
-		EOL);
-
-
-/*********************************************************************
-*
-*     Constants
-*
-*********************************************************************/
-
-printf("\n Constants \n");
-
-#ifdef DPT_DEBUG
-printf(" Multiplexor op. Y TR_C16_C04_Y \n");
-#endif
-DP_NBUSE(	"TR_C16_C04_Y",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"opy_ts4",
-		"y_c16_c4[31:0]",
-		"opy_ots[31:0]",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" Multiplexor op. Y MX_C16_C04_Y \n");
-#endif
-DP_NMUX2CS(	"MX_C16_C04_Y",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"opy_mx4",
-		"opy_C0[31:5]","C_n0[0]","opy_C0[3:0]",
-		"opy_C0[31:3]","C_n0[0]","opy_C0[1:0]",
-		"y_c16_c4[31:0]",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" Cst_n0 \n");
-#endif
-DP_CONST(	"Cst_n0",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"0xFFFFFFFF",
-		"C_n0[31:0]",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" C0_Y \n");
-#endif
-DP_CONST(	"C0_Y",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"0x0",
-		"opy_C0[31:0]",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" Multiplexor op. Y TR_C0_I16_Y \n");
-#endif
-DP_NBUSE(	"TR_C0_I16_Y",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"opy_ts3",
-		"y_c0_i16[31:0]",
-		"opy_ots[31:0]",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" Multiplexor op. Y MX_C0_I16_Y \n");
-#endif
-DP_NMUX2CS(	"MX_C0_I16_Y",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"opy_mx3",
-		"opy_C0[31:0]",
-		"se_i16[31:16]","ir_s[15:0]",
-		"y_c0_i16[31:0]",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" Multiplexor op. X TR_C0_SR_X \n");
-#endif
-DP_NBUSE(	"TR_C0_SR_X",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"opx_ts3",
-		"x_c0_sr[31:0]",
-		"opx_ots[31:0]",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" Multiplexor op. X TR_CH_CB_X \n");
-#endif
-DP_NBUSE(	"TR_CH_CB_X",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"opx_ts4",
-		"x_ch_cb[31:0]",
-		"opx_ots[31:0]",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" Multiplexor op. X MX_CH_CB_X \n");
-#endif
-DP_NMUX2CS(	"MX_CH_CB_X",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"opx_mx4",
-		"opx_C0[31:16]","C_n0[24:9]",
-		"opx_C0[23:0]","C_n0[8:1]",
-		"x_ch_cb[31:0]",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" C0_X \n");
-#endif
-DP_CONST(	"C0_X",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"0x0",
-		"opx_C0[31:0]",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" Multiplexor op. X MX_C0_SR_X \n");
-#endif
-DP_NMUX2CS(	"MX_C0_SR_X",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"opx_mx3",
-		"opx_C0[31:0]",
-		"sr_s[31:0]",
-		"x_c0_sr[31:0]",
-		EOL);
-
-
-/*********************************************************************
-*
-*     Register AD
-*
-*********************************************************************/
-
-printf("\n Register AD \n");
-
-#ifdef DPT_DEBUG
-printf(" Multiplexor op. Y TR_DT_AD_Y \n");
-#endif
-DP_NBUSE(	"TR_DT_AD_Y",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"opy_ts1",
-		"y_dt_ad[31:0]",
-		"opy_ots[31:0]",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" Multiplexor op. X TR_AD_PC_X \n");
-#endif
-DP_NBUSE(	"TR_AD_PC_X",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"opx_ts1",
-		"x_ad_pc[31:0]",
-		"opx_ots[31:0]",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" Multiplexor op. X MX_AD_PC_X \n");
-#endif
-DP_NMUX2CS(	"MX_AD_PC_X",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"opx_mx1",
-		"ad_s[31:0]",
-		"pc_s[31:0]",
-		"x_ad_pc[31:0]",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" Multiplexor op. Y MX_DT_AD_Y \n");
-#endif
-DP_NMUX2CS(	"MX_DT_AD_Y",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"opy_mx1",
-		"dt_s[31:0]",
-		"ad_s[31:0]",
-		"y_dt_ad[31:0]",
-		EOL);
-
-DP_PDFFT(	"AD",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"ad_scin",
-		"ad_test",
-		"ad_wen",
-		"ad_ck",
-		"alu_out[31:0]",
-		"ad_s[31:0]",
-		"ad_ns[31:0]",
-		EOL);
-
-
-/*********************************************************************
-*
-*     Register SR
-*
-*********************************************************************/
-
-printf("\n Register SR \n");
-
-#ifdef DPT_DEBUG
-printf(" Cst_SR_0 \n");
-#endif
-DP_CONST(       "Cst_SR_0",
-                7,
-                DEFAULT_SLICE,
-                "0x0",
-                "C_SR0[6:0]",
-                EOL);
-
-#ifdef DPT_DEBUG
-printf(" MX_SR \n");
-#endif
-DP_MUX2CS(	"MX_SR",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"sr_mx",
-		"alu_out[31:16]",	"sr_it3","sr_it2","sr_it1","sr_it0",
-					"sr_ovr","sr_dav","sr_ico","sr_iav",
-					"C_SR0[6:3]",
-					"sr_cpurst","C_SR0[2:0]",
-		"alu_out[31:0]",
-		"sr_in[31:0]",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" SR \n");
-#endif
-DP_PDFFT(	"SR",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"sr_scin",
-		"sr_test",
-		"sr_wen",
-		"sr_ck",
-		"sr_in[31:0]",
-		"sr_s[31:0]",
-		"sr_ns[31:0]",
-		EOL);
-
-
-/*********************************************************************
-*
-*     Immediates
-*
-*********************************************************************/
-
-printf("\n Immediates \n");
-
-#ifdef DPT_DEBUG
-printf(" Multiplexor op. Y TR_I18_I28_Y \n");
-#endif
-DP_NBUSE(	"TR_I18_I28_Y",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"opy_ts2",
-		"y_i18_i28[31:0]",
-		"opy_ots[31:0]",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" Multiplexor op. Y MX_I18_I28_Y \n");
-#endif
-DP_NMUX2CS(	"MX_I18_I28_Y",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"opy_mx2",
-		"se_i16[31:18]","ir_s[15:0]","opy_C0[1:0]",
-		"se_i28[31:28]","ir_s[25:0]","opy_C0[1:0]",
-		"y_i18_i28[31:0]",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" INV_I16_I28 \n");
-#endif
-DP_INV(		"INV_I16_I28",
-		20,
-		12,
-		1,
-		"s_n_i28","s_n_i28","s_n_i28","s_n_i28",
-                "s_n_i16","s_n_i16","s_n_i16","s_n_i16",
-		"s_n_i16","s_n_i16","s_n_i16","s_n_i16",
-		"s_n_i16","s_n_i16","s_n_i16","s_n_i16",
-		"s_n_i16","s_n_i16","s_n_i16","s_n_i16",
-		"se_i28[31:28]","se_i16[31:16]",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" INV_IMD \n");
-#endif
-DP_INV(		"INV_IMD",
-		2,
-		20,
-		3,
-		"ir_s[25]","ir_s[15]",
-		"s_n_i28","s_n_i16",
-		EOL);
-
-
-/*********************************************************************
-*
-*     Register IR
-*
-*********************************************************************/
-
-printf("\n Register IR \n");
-
-#ifdef DPT_DEBUG
-printf(" INV_IR_N \n");
-#endif
-DP_INV(		"INV_IR_N",
-		24,
-		8,
-		1,
-		"ir_s[31:11]","ir_s[2:0]",
-		"ir_s_n[31:11]","ir_s_n[2:0]",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" INV_CODOP \n");
-#endif
-DP_INV(		"INV_CODOP",
-		24,
-		8,
-		1,
-		"ir_s_n[31:11]","ir_s_n[2:0]",
-		"opy_codop[5:0]",
-			"opy_rs[4:0]","opy_rdrt[4:0]","opy_rd[4:0]",
-			"opy_tvr","opy_sr","opy_iar",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" IR \n");
-#endif
-DP_PDFFT(	"IR",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"ir_scin",
-		"ir_test",
-		"ir_wen",
-		"ir_ck",
-		"data_in[31:0]",
-		"ir_s[31:0]",
-		"ir_ns[31:0]",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" INV_IR \n");
-#endif
-DP_INV(		"INV_IR",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		1,
-		"data_in_n[31:0]",
-		"data_in[31:0]",
-		EOL);
-
-
-/************************************************************
-*
-*  Data in inversion
-*
-************************************************************/
-
-#ifdef DPT_DEBUG
-printf(" INV_IN_DPT \n");
-#endif
-DP_INV(		"INV_DATA_IN_DPT",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		1,
-		"data_in_dpt[31:0]",
-		"data_in_n[31:0]",
-		EOL);
-
-/*********************************************************************
-*
-*     Register DT
-*
-*********************************************************************/
-
-printf("\n Register DT \n");
-
-#ifdef DPT_DEBUG
-printf(" MX_Hx_Lx_DT \n");
-#endif
-DP_NMUX2CS(	"MX_Hx_Lx_DT",
-		16,
-		8,
-		"adrw_rb1",
-		"data_in_n[31:24]","data_in_n[23:16]",
-		"data_in_n[15:8]","data_in_n[7:0]",
-		"data_in_hmx[7:0]","data_in_lmx[7:0]",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" MX_H_L_DT \n");
-#endif
-DP_NMUX2CS(	"MX_H_L_DT",
-		8,
-		12,
-		"adrw_rb0",
-		"data_in_hmx[7:0]",
-		"data_in_lmx[7:0]",
-		"data_in_mx[7:0]",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" MX_LB_DT \n");
-#endif
-DP_NMUX2CS(	"MX_LB_DT",
-		8,
-		12,
-		"adrw_byte",
-		"data_in_mx[7:0]",
-		"data_in_n[7:0]",
-		"data_in_lb[7:0]",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" DT \n");
-#endif
-DP_PDFFT(	"DT",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"dt_scin",
-		"dt_test",
-		"dt_wen",
-		"dt_ck",
-		"data_in[31:8]","data_in_lb[7:0]",
-		"dt_s[31:0]",
-		"dt_ns[31:0]",
-		EOL);
-
-
-/*********************************************************************
-*
-*     Multiplexor Bus DATA OUT
-*
-*********************************************************************/
-
-printf("\n Multiplexor Bus DATA OUT \n");
-
-DP_NMUX2CS(	"MX_DATA",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		"alu_byte",
-		"alu_out[7:0]","alu_out[7:0]","alu_out[7:0]","alu_out[7:0]",
-		"alu_out[31:0]",
-		"data_out_n[31:0]",
-		EOL);
-
-#ifdef DPT_DEBUG
-printf(" INV_DATA_OUT_DPT \n");
-#endif
-DP_INV(		"INV_OUT_DPT",
-		DEFAULT_WIDTH,
-		DEFAULT_SLICE,
-		1,
-		"data_out_n[31:0]",
-		"data_out_dpt[31:0]",
-		EOL);
-
-DP_SAVLOFIG();
-exit (0);
-}
diff --git a/alliance/share/tutorials/dlxm/dlxm_dpt.dpr b/alliance/share/tutorials/dlxm/dlxm_dpt.dpr
deleted file mode 100644
index ac3ef2bf..00000000
--- a/alliance/share/tutorials/dlxm/dlxm_dpt.dpr
+++ /dev/null
@@ -1,55 +0,0 @@
-### ----------------------------------------------------------------- ###
-#									#
-# file	: dlxm_dpt.dpr							#
-# date	: February 1995							#
-# version	: v0.0							#
-#									#
-# origin	: this description has been developed by CAO-VLSI team	#
-#		  at MASI laboratory, University Pierre et Marie Curie	#
-#		  URA CNRS 818, Institut Blaise Pascal			#
-#		  4 Place Jussieu 75252 Paris Cedex 05 - France		#
-# E-mail      :      cao-vlsi@masi.ibp.fr                               #
-#									#
-# descr.	: Placement file for datapath block connectors		#
-#									#
-### ----------------------------------------------------------------- ###
-
-DP_LOCON rf_wen NORTH DEFAULT DEFAULT
-DP_LOCON rf_aw[4:0] NORTH DEFAULT DEFAULT
-DP_LOCON rf_ar[4:0] NORTH DEFAULT DEFAULT
-DP_LOCON sr_mode NORTH DEFAULT DEFAULT
-DP_LOCON sr_mask NORTH DEFAULT DEFAULT
-DP_LOCON sr_cpurst NORTH DEFAULT DEFAULT
-DP_LOCON sr_iav NORTH DEFAULT DEFAULT
-DP_LOCON sr_ico NORTH DEFAULT DEFAULT
-DP_LOCON sr_dav NORTH DEFAULT DEFAULT
-DP_LOCON sr_ovr NORTH DEFAULT DEFAULT
-DP_LOCON sr_it0 NORTH DEFAULT DEFAULT
-DP_LOCON sr_it1 NORTH DEFAULT DEFAULT
-DP_LOCON sr_it2 NORTH DEFAULT DEFAULT
-DP_LOCON sr_it3 NORTH DEFAULT DEFAULT
-DP_LOCON opx_sign NORTH DEFAULT DEFAULT
-DP_LOCON opy_codop[5:0] NORTH DEFAULT DEFAULT
-DP_LOCON opy_rs[4:0] NORTH DEFAULT DEFAULT
-DP_LOCON opy_rdrt[4:0] NORTH DEFAULT DEFAULT
-DP_LOCON opy_rd[4:0] NORTH DEFAULT DEFAULT
-DP_LOCON opy_tvr NORTH DEFAULT DEFAULT
-DP_LOCON opy_sr NORTH DEFAULT DEFAULT
-DP_LOCON opy_iar NORTH DEFAULT DEFAULT
-DP_LOCON opy_sign NORTH DEFAULT DEFAULT
-DP_LOCON alu_test_n NORTH DEFAULT DEFAULT
-DP_LOCON alu_nul NORTH DEFAULT DEFAULT
-DP_LOCON alu_sign NORTH DEFAULT DEFAULT
-
-DP_LOCON adr_n_0 NORTH DEFAULT DEFAULT
-DP_LOCON adr_n_1 NORTH DEFAULT DEFAULT
-DP_LOCON adr_n_31 NORTH DEFAULT DEFAULT
-
-DP_LOCON data_in_dpt[31:0] EAST DEFAULT DEFAULT
-DP_LOCON data_out_dpt[31:0] EAST DEFAULT DEFAULT
-DP_LOCON out_adr[31:0] WEST DEFAULT DEFAULT
-
-DP_POWER 1 50
-
-DP_DEFAB -10 +10
-
diff --git a/alliance/share/tutorials/dlxm/dlxm_dpt.vbe b/alliance/share/tutorials/dlxm/dlxm_dpt.vbe
deleted file mode 100644
index 778ba6d1..00000000
--- a/alliance/share/tutorials/dlxm/dlxm_dpt.vbe
+++ /dev/null
@@ -1,833 +0,0 @@
-
--- ###----------------------------------------------------------------###
--- #                                                                    #
--- #         Alliance CAD System 3.0                                    #
--- #          FitPath Package V.RR                                      #
--- #                                                                    #
--- # Copyright(c) 94-AA, MASI, CAO-VLSI Team                            #
--- #                                                                    #
--- # Author      :          Jean-Paul CHAPUT                            #
--- #		  at MASI laboratory, University Pierre et Marie Curie	#
--- #		  URA CNRS 818, Institut Blaise Pascal			#
--- #		  4 Place Jussieu 75252 Paris Cedex 05 - France		#
--- # E-mail      :      cao-vlsi@masi.ibp.fr                            #
--- # ****************************************************************** #
--- # File        :      "dlxm_dpt.vbe"                                  #
--- #                                                                    #
--- #     VHDL Behavioral description of micro-programmed DLX data-      #
--- # path. This model is derived from the 1992/93 DLX project, see      #
--- # file "s_dpt.vbe" of the structural description one.                #
--- #     This version implements multiplexers with three states.        #
--- #                                                                    #
--- #     Date of initial design : october 26, 1994.                     #
--- # ---------------------------------------------------------------    #
--- # Modified : october 26, 1994.                                       #
--- #     1) When writing to DT from the plots in byte mode, the         #
--- #        three upper octets are not forced to zero. This             #
--- #        operation is done while using the value stored in DT.       #
--- #     2) The name of the followings terminals have change :          #
--- #            - opy_byte --> adrw_byte                                #
--- #            - opy_rb0  --> adrw_rb0                                 #
--- #            - opy_rb1  --> adrw_rb1                                 #
--- # --------------------------------------------------------------     #
--- # Modified January 1995          				        #
--- #	 1) Take care that the symbolic pads are non inverting pads     #
--- #     2) 3 new connectors :					        #
--- #		adr_n_31 : inout   to the status		        #
--- #		adr_n_0 : inout to the status and the datapath	        #
--- #		adr_n_1 : inout to the status and the datapath	        #
--- ###----------------------------------------------------------------###
-
-
-ENTITY  dlxm_dpt  IS
-
-PORT(
-	-- Power supply terminals.
-    vdd : in    bit;
-    vss : in    bit;
-
-    -- Control connectors of registers PC, IAR, AD, IR, DT.
-    -- Select the function mode (enable SCAN mode when set to one).
-     pc_test  : in    bit;
-     ad_test  : in    bit;
-    tvr_test  : in    bit;
-    iar_test  : in    bit;
-     sr_test  : in    bit;
-     ir_test  : in    bit;
-     dt_test  : in    bit;
-    -- Scan-Path connectors.
-     pc_scin  : in    bit;
-     ad_scin  : in    bit;
-    tvr_scin  : in    bit;
-    iar_scin  : in    bit;
-     sr_scin  : in    bit;
-     ir_scin  : in    bit;
-     dt_scin  : in    bit;
-     pc_scout :   out bit;
-     ad_scout :   out bit;
-    tvr_scout :   out bit;
-    iar_scout :   out bit;
-     sr_scout :   out bit;
-     ir_scout :   out bit;
-     dt_scout :   out bit;
-    -- Clock connectors.
-     pc_ck    : in    bit;
-     ad_ck    : in    bit;
-    tvr_ck    : in    bit;
-    iar_ck    : in    bit;
-     sr_ck    : in    bit;
-     ir_ck    : in    bit;
-     dt_ck    : in    bit;
-    -- Write enable, active only in normal mode.
-	-- (enable writing when set to one)
-     pc_wen   : in    bit;
-     ad_wen   : in    bit;
-    tvr_wen   : in    bit;
-    iar_wen   : in    bit;
-     sr_wen   : in    bit;
-     ir_wen   : in    bit;
-     dt_wen   : in    bit;
-
-    -- Control connectors of the register file.
-    rf_ck  : in    bit;  -- Clock connector.
-    rf_wen : in    bit;  -- Write enable (active to high level).
-    rf_aw  : in    bit_vector(4 downto 0); -- Write address.
-    rf_ar  : in    bit_vector(4 downto 0); -- Read adress.
-
-	-- Controls connectors of the SR block.
-	sr_mx    : in    bit; -- Select what to write in SR[15:0].
-	-- Flags to write in SR from the CTRL block.
-	sr_mode  :   out bit; -- SR(0)
-	sr_mask  :   out bit; -- SR(1)
-	sr_cpurst : in    bit; -- SR(3)  cpureset flag from status
-	sr_iav   : in    bit; -- SR(8)
-	sr_ico   : in    bit; -- SR(9)
-	sr_dav   : in    bit; -- SR(10)
-	sr_ovr   : in    bit; -- SR(11)
-	sr_it0   : in    bit; -- SR(12)
-	sr_it1   : in    bit; -- SR(13)
-	sr_it2   : in    bit; -- SR(14)
-	sr_it3   : in    bit; -- SR(15)
-
-    -- Control connectors of X multiplexer.
-    -- Select between CH , CB , C0 , R[i] , SR , TVR, IAR , AD , PC.
-    opx_ts4 : in    bit; -- Set  CH, CB  on the X bus.
-    opx_ts3 : in    bit; -- Set  C0, SR  on the X bus.
-    opx_ts2 : in    bit; -- Set TVR, IAR on the X bus.
-    opx_ts1 : in    bit; -- Set  AD, PC  on the X bus.
-    opx_ts0 : in    bit; -- Set   R[i]   on the X bus.
-    opx_mx4 : in    bit; -- Select between  CH/CB.
-    opx_mx3 : in    bit; -- Select between  C0/SR.
-    opx_mx2 : in    bit; -- Select between TVR/IAR.
-    opx_mx1 : in    bit; -- Select between  AD/PC.
-	-- Sign of X operand ( opx_out[31] )
-    opx_sign :   out bit;
-
-    -- Control connectors of Y multiplexer.
-    -- Select between C16, C4, C0, I16, I18, I28, DT, AD.
-    opy_ts4 : in    bit; -- Set C16, C4  on the Y bus.
-    opy_ts3 : in    bit; -- Set  C0, I16 on the Y bus.
-    opy_ts2 : in    bit; -- Set I18, I28 on the Y bus.
-    opy_ts1 : in    bit; -- Set  DT, AD  on the Y bus.
-    opy_mx4 : in    bit; -- Select between C16/C4.
-    opy_mx3 : in    bit; -- Select between  C0/I16.
-    opy_mx2 : in    bit; -- Select between I18/I28.
-    opy_mx1 : in    bit; -- Select between  DT/AD.
-	-- When one byte is read, tells which one in a word.
-	-- (according to the two last bits of "adr_out").
-    adrw_byte : in    bit; -- Select the BYTE mode when set to '1'.
-    adrw_rb1  : in    bit; -- "out_adr_n[1]"
-    adrw_rb0  : in    bit; -- "out_adr_n[0]"
-	-- Fields of the IR register.
-    opy_codop :   out bit_vector( 5 downto 0); -- IR[31:26]
-    opy_rs    :   out bit_vector( 4 downto 0); -- IR[25:21]
-    opy_rdrt  :   out bit_vector( 4 downto 0); -- IR[20:16]
-    opy_rd    :   out bit_vector( 4 downto 0); -- IR[15:11]
-	opy_tvr   :   out bit;                     -- IR[2]
-	opy_sr    :   out bit;                     -- IR[1]
-	opy_iar   :   out bit;                     -- IR[0]
-	-- Sign of Y operand ( opy_out[31] )
-    opy_sign  :   out bit;
-	-- Main data bus input, from the padt.
-    data_in_dpt : in    bit_vector(31 downto 0);
-
-    -- Control connectors of ALU multiplexer.
-    alu_mx4i0  : in    bit;  -- (shifts,arith,logic)/tests
-    alu_mx3i0  : in    bit;  --        (arith,logic)/shifts
-    alu_mx2i1  : in    bit;  --      (X + Y,X xor Y)/(X and Y,X or Y)
-    alu_mx2i0  : in    bit;  -- command 'left' of shifter
-    alu_mx1i2  : in    bit;  --            (X +/- Y)/(X xor Y)
-    alu_mx1i1  : in    bit;  --            (X and Y)/(X  or Y)
-    alu_mx1i0  : in    bit;  -- command 'ext' of shifter
-    alu_mx0i0  : in    bit;  -- select arythmetic operation add/sub
-    -- Auxiliary ALU inputs/outputs.
-	alu_byte   : in    bit;  -- Select the byte mode (same as "opy_byte").
-    alu_shrot  : in    bit;  -- 'rot' command of shifter (to VSS)
-    alu_test_n : in    bit;  -- Test results (inverted polarity)
-    alu_c31  :   out bit;  -- Carry 31 (inverted polarity)
-    alu_c30  :   out bit;  -- Carry 30 (inverted polarity)
-    alu_nul    :   out bit;  -- Flag NUL
-    alu_sign   :   out bit;  -- Sign of arithmetic result X+Y/X-Y
-	-- Main data bus output, to the pads.
-    data_out_dpt :   out bit_vector(31 downto 0);
-
-    -- Control connectors of ADROUT multiplexer.
-    out_mx0i0 : in    bit; -- Select between AD and PC.
-    -- Main adress bus output, to the pads.
-    out_adr : out   bit_vector(31 downto 0);	-- to the pads
-    adr_n_31 : inout bit ; 			-- to the status
-    adr_n_1 :  inout bit ;			-- to the status and datapath
-    adr_n_0 :  inout bit 			-- to the status and datapath
-    );
-
-END  dlxm_dpt;
-
-
-ARCHITECTURE  fonctional  OF  dlxm_dpt IS
-        -- Adress inversion
-	SIGNAL out_adr_n  :  bit_vector(31 downto 0);
-
-	-- Data inversion
-	SIGNAL data_in_n : bit_vector(31 downto 0);
-	SIGNAL data_out_n : bit_vector(31 downto 0);
-	-- Declaration of 31 register file masters (suffixed by "_m").
-	-- Register ZERO is hard wired to 0.
-    CONSTANT r0    : bit_vector(31 downto 0) :=X"00000000";
-	SIGNAL rf_m1   : reg_vector(31 downto 0) REGISTER;
-	SIGNAL rf_m2   : reg_vector(31 downto 0) REGISTER;
-	SIGNAL rf_m3   : reg_vector(31 downto 0) REGISTER;
-	SIGNAL rf_m4   : reg_vector(31 downto 0) REGISTER;
-	SIGNAL rf_m5   : reg_vector(31 downto 0) REGISTER;
-	SIGNAL rf_m6   : reg_vector(31 downto 0) REGISTER;
-	SIGNAL rf_m7   : reg_vector(31 downto 0) REGISTER;
-	SIGNAL rf_m8   : reg_vector(31 downto 0) REGISTER;
-	SIGNAL rf_m9   : reg_vector(31 downto 0) REGISTER;
-	SIGNAL rf_m10  : reg_vector(31 downto 0) REGISTER;
-	SIGNAL rf_m11  : reg_vector(31 downto 0) REGISTER;
-	SIGNAL rf_m12  : reg_vector(31 downto 0) REGISTER;
-	SIGNAL rf_m13  : reg_vector(31 downto 0) REGISTER;
-	SIGNAL rf_m14  : reg_vector(31 downto 0) REGISTER;
-	SIGNAL rf_m15  : reg_vector(31 downto 0) REGISTER;
-	SIGNAL rf_m16  : reg_vector(31 downto 0) REGISTER;
-	SIGNAL rf_m17  : reg_vector(31 downto 0) REGISTER;
-	SIGNAL rf_m18  : reg_vector(31 downto 0) REGISTER;
-	SIGNAL rf_m19  : reg_vector(31 downto 0) REGISTER;
-	SIGNAL rf_m20  : reg_vector(31 downto 0) REGISTER;
-	SIGNAL rf_m21  : reg_vector(31 downto 0) REGISTER;
-	SIGNAL rf_m22  : reg_vector(31 downto 0) REGISTER;
-	SIGNAL rf_m23  : reg_vector(31 downto 0) REGISTER;
-	SIGNAL rf_m24  : reg_vector(31 downto 0) REGISTER;
-	SIGNAL rf_m25  : reg_vector(31 downto 0) REGISTER;
-	SIGNAL rf_m26  : reg_vector(31 downto 0) REGISTER;
-	SIGNAL rf_m27  : reg_vector(31 downto 0) REGISTER;
-	SIGNAL rf_m28  : reg_vector(31 downto 0) REGISTER;
-	SIGNAL rf_m29  : reg_vector(31 downto 0) REGISTER;
-	SIGNAL rf_m30  : reg_vector(31 downto 0) REGISTER;
-	SIGNAL rf_m31  : reg_vector(31 downto 0) REGISTER;
-    -- Register file slave (suffixed by "_s").
-	SIGNAL rf_s    : reg_vector(31 downto 0) REGISTER;
-	SIGNAL rf_ckd  : bit;
-
-    -- Signals and registers associated to PC, AD, IAR, IR and DT.
-	-- Master registers (suffix "_m").
-	SIGNAL  pc_m    : reg_vector (31 downto 0) REGISTER;
-	SIGNAL tvr_m    : reg_vector (31 downto 0) REGISTER;
-	SIGNAL iar_m    : reg_vector (31 downto 0) REGISTER;
-	SIGNAL  ad_m    : reg_vector (31 downto 0) REGISTER;
-	SIGNAL  sr_m    : reg_vector (31 downto 0) REGISTER;
-	SIGNAL  ir_m    : reg_vector (31 downto 0) REGISTER;
-	SIGNAL  dt_m    : reg_vector (31 downto 0) REGISTER;
-	-- Slave registers (suffix "_s").
-	SIGNAL  pc_s     : reg_vector (31 downto 0) REGISTER;
-	SIGNAL tvr_s     : reg_vector (31 downto 0) REGISTER;
-	SIGNAL iar_s     : reg_vector (31 downto 0) REGISTER;
-	SIGNAL  ad_s     : reg_vector (31 downto 0) REGISTER;
-	SIGNAL  sr_s     : reg_vector (31 downto 0) REGISTER;
-	SIGNAL  ir_s     : reg_vector (31 downto 0) REGISTER;
-	SIGNAL  dt_s     : reg_vector (31 downto 0) REGISTER;
-	-- Write master register while in SCAN mode.
-	SIGNAL  pc_ckt   : bit;
-	SIGNAL tvr_ckt   : bit;
-	SIGNAL iar_ckt   : bit;
-	SIGNAL  ad_ckt   : bit;
-	SIGNAL  sr_ckt   : bit;
-	SIGNAL  ir_ckt   : bit;
-	SIGNAL  dt_ckt   : bit;
-	-- Write master register while in NORMAL mode.
-	SIGNAL  pc_ckd   : bit;
-	SIGNAL tvr_ckd   : bit;
-	SIGNAL iar_ckd   : bit;
-	SIGNAL  ad_ckd   : bit;
-	SIGNAL  sr_ckd   : bit;
-	SIGNAL  ir_ckd   : bit;
-	SIGNAL  dt_ckd   : bit;
-
-    -- Signals for Y multiplexer.
-	SIGNAL opy_conflict : bit;
-	SIGNAL opy_nodriver : bit;
-	SIGNAL opy_its4     : bit_vector(31 downto 0);
-	SIGNAL opy_its3     : bit_vector(31 downto 0);
-	SIGNAL opy_its2     : bit_vector(31 downto 0);
-	SIGNAL opy_its1     : bit_vector(31 downto 0);
-	SIGNAL opy_ots      : mux_vector(31 downto 0) bus;
-	SIGNAL opy_out      : bit_vector(31 downto 0);
-	-- Value to write in DT.
-	SIGNAL opy_dt_n     : bit_vector( 7 downto 0);
-	SIGNAL opy_dt       : bit_vector(31 downto 0);
-	-- Fields of IR register.
-	SIGNAL opy_ir16     : bit_vector(31 downto 0);
-	SIGNAL opy_ir18     : bit_vector(31 downto 0);
-	SIGNAL opy_ir28     : bit_vector(31 downto 0);
-    -- Signals for X multiplexer.
-	SIGNAL opx_conflict : bit;
-	SIGNAL opx_nodriver : bit;
-	SIGNAL opx_its4     : bit_vector(31 downto 0);
-	SIGNAL opx_its3     : bit_vector(31 downto 0);
-	SIGNAL opx_its2     : bit_vector(31 downto 0);
-	SIGNAL opx_its1     : bit_vector(31 downto 0);
-	SIGNAL opx_ots      : mux_vector(31 downto 0) bus;
-	SIGNAL opx_out      : bit_vector(31 downto 0);
-	-- Signals for the ALU multiplexer.
-	SIGNAL alu_out      : bit_vector(31 downto 0);
-	-- Auxiliary signals for arythmetics operations.
-	SIGNAL alu_yop      : bit_vector(31 downto 0);
-	SIGNAL alu_cry      : bit_vector(32 downto 0);
-	SIGNAL alu_sum      : bit_vector(31 downto 0);
-	-- Auxiliary signals for shifts operations.
-	-- ('alu_shsign' is used for arythmeticals shifts)
-	SIGNAL alu_shsign   : bit_vector(31 downto 0);
-	SIGNAL alu_shright  : bit_vector(31 downto 0);
-	SIGNAL alu_shleft   : bit_vector(31 downto 0);
-	SIGNAL alu_shout    : bit_vector(31 downto 0);
-
-BEGIN
-
-
-	-- ********************* Power Supply Check **********************
-
-	ASSERT(vss = '0')  
-		REPORT "Power supply VSS badly connected." SEVERITY  WARNING;
-	ASSERT(vdd = '1')  
-		REPORT "Power supply VDD badly connected." SEVERITY  WARNING;
-
-
-    	--
-	data_in_n <= NOT data_in_dpt;
-	--
-
-	-- ******************* X Operand  Description ********************
-
-
-	-- Check X operand multiplexer commands.
-	-- Ckeck if there is more than one driver.
-	WITH opx_ts4 & opx_ts3 & opx_ts2 & opx_ts1 & opx_ts0 SELECT
-		opx_conflict <= '1' WHEN  B"00000"
-								 |B"00001"
-								 |B"00010"
-								 |B"00100"
-								 |B"01000"
-								 |B"10000",
-						'0' WHEN OTHERS;
-	-- Check if there is at least one driver.
-	opx_nodriver <= '0' WHEN   opx_ts4
-							 & opx_ts3
-							 & opx_ts2
-							 & opx_ts1
-							 & opx_ts0 = B"00000" ELSE '1';
-								 
-	-- Print warning messages associated to the X operand.
-	ASSERT(opx_conflict)
-		REPORT "More than one driver on the X operand three-state."
-		SEVERITY WARNING;
-	ASSERT(opx_nodriver)
-		REPORT "No driver on the X operand three-state."
-		SEVERITY WARNING;
-
-	-- Outputs of X operand.
-	opx_out   <= opx_ots;
-	opx_sign  <= opx_out(31);
-
-	-- Multiplexer part (pseudo CMOS multiplexers)
-	opx_its4 <= X"FFFF0000" WHEN opx_mx4 ELSE  X"FFFFFF00";
-	opx_its3 <= X"FFFFFFFF" WHEN opx_mx3 ELSE not  sr_s;
-	opx_its2 <= not tvr_s   WHEN opx_mx2 ELSE not iar_s;
-	opx_its1 <= not  ad_s   WHEN opx_mx1 ELSE not  pc_s;
-
-	-- Multiplexer part (three state).
-ts_x4:BLOCK(opx_ts4) BEGIN opx_ots <= GUARDED not opx_its4; END BLOCK ts_x4;
-ts_x3:BLOCK(opx_ts3) BEGIN opx_ots <= GUARDED not opx_its3; END BLOCK ts_x3;
-ts_x2:BLOCK(opx_ts2) BEGIN opx_ots <= GUARDED not opx_its2; END BLOCK ts_x2;
-ts_x1:BLOCK(opx_ts1) BEGIN opx_ots <= GUARDED not opx_its1; END BLOCK ts_x1;
-ts_x0:BLOCK(opx_ts0) BEGIN opx_ots <= GUARDED      rf_s;    END BLOCK ts_x0;
-
-
-	-- ******************** Y Operand Description ********************
-
-
-	-- Check Y operand multiplexer commands.
-	-- Ckeck if there is more than one driver.
-	WITH opy_ts4 & opy_ts3 & opy_ts2 & opy_ts1 SELECT
-		opy_conflict <= '1' WHEN  B"0000"
-								 |B"0001"
-								 |B"0010"
-								 |B"0100"
-								 |B"1000",
-						'0' WHEN OTHERS;
-	-- Check if there is at least one driver.
-	opy_nodriver <= '0' WHEN   opy_ts4
-							 & opy_ts3
-							 & opy_ts2
-							 & opy_ts1 = B"0000" ELSE '1';
-								 
-	-- Print warning messages associated to the Y operand.
-	ASSERT(opy_conflict)
-		REPORT "More than one driver on the Y operand three-state."
-		SEVERITY WARNING;
-	ASSERT(opy_nodriver)
-		REPORT "No driver on the Y operand three-state."
-		SEVERITY WARNING;
-
-    -- Affect IR fiedls outputs.
-	opy_codop(5 downto 0) <= ir_s(31 downto 26);
-	opy_rs   (4 downto 0) <= ir_s(25 downto 21);
-	opy_rdrt (4 downto 0) <= ir_s(20 downto 16);
-	opy_rd   (4 downto 0) <= ir_s(15 downto 11);
-	opy_tvr               <= ir_s(2);
-	opy_sr                <= ir_s(1);
-	opy_iar               <= ir_s(0);
-
-	-- Affect "opy_ir16", with sign extention.
-	opy_ir16(15 downto  0) <=              ir_s(15 downto 0);
-	opy_ir16(31 downto 16) <= X"FFFF" WHEN ir_s(15) = '1'
-						 ELSE X"0000";
-
-    -- Affect "alu_ir18", with sign extention.
-	opy_ir18( 1 downto  0) <= B"00";
-	opy_ir18(17 downto  2) <=                     ir_s(15 downto 0);
-	opy_ir18(31 downto 18) <= X"FFF" & B"11" WHEN ir_s(15) = '1'
-						ELSE  X"000" & B"00";
-
-    -- Affect "alu_ir28", with sign extention.
-	opy_ir28( 1 downto  0) <= B"00";
-	opy_ir28(27 downto  2) <=           ir_s(25 downto 0);
-	opy_ir28(31 downto 28) <= X"F" WHEN ir_s(25) = '1'
-						ELSE  X"0";
-
-	-- Set the value to write in DT.
-	-- When in BYTE mode select the good byte and put in on the LSB.
-	WITH adrw_rb1 & adrw_rb0 SELECT
-		opy_dt_n <= data_in_n( 7 downto  0) WHEN B"00",
-					data_in_n(15 downto  8) WHEN B"01",
-					data_in_n(23 downto 16) WHEN B"10",
-					data_in_n(31 downto 24) WHEN B"11";
-	-- When in BYTE mode, force the 24 MSB to zero.
-	opy_dt <=      not (data_in_n(31 downto 8) & opy_dt_n) WHEN adrw_byte
-			  ELSE not  data_in_n;
-
-	-- Multiplexer part (pseudo CMOS multiplexers)
-	opy_its4 <=  X"FFFFFFEF" WHEN opy_mx4 ELSE  X"FFFFFFFB";
-	opy_its3 <=  X"FFFFFFFF" WHEN opy_mx3 ELSE not opy_ir16;
-	opy_its2 <= not opy_ir18 WHEN opy_mx2 ELSE not opy_ir28;
-	opy_its1 <= not  dt_s    WHEN opy_mx1 ELSE not  ad_s;
-
-	-- Multiplexer part (three state).
-ts_y4:BLOCK(opy_ts4) BEGIN opy_ots <= GUARDED not opy_its4; END BLOCK ts_y4;
-ts_y3:BLOCK(opy_ts3) BEGIN opy_ots <= GUARDED not opy_its3; END BLOCK ts_y3;
-ts_y2:BLOCK(opy_ts2) BEGIN opy_ots <= GUARDED not opy_its2; END BLOCK ts_y2;
-ts_y1:BLOCK(opy_ts1) BEGIN opy_ots <= GUARDED not opy_its1; END BLOCK ts_y1;
-
-	-- Affect the value of the final Y multiplexer output.
-	opy_out  <= opy_ots;
-	opy_sign <= opy_ots(31);
-
-
-	-- ******************* ALU Shifter Description *******************
-
-
-	-- Sign extention, for arythmetic right shift (SRA).
-	WITH alu_mx1i0 & opx_out(31) SELECT
-		alu_shsign <= X"00000000" WHEN  B"00"
-									  | B"01"
-									  | B"10",
-					 X"FFFFFFFF"  WHEN  B"11";
-
-	-- Result of left shift affected to signal 'alu_shleft'.
-	WITH opy_out(4 downto 0) SELECT
-		alu_shleft  <=
-			opx_out(31 downto 0)                        WHEN  B"00000",
-			opx_out(30 downto 0) & B"0"                 WHEN  B"00001",
-			opx_out(29 downto 0) & B"00"                WHEN  B"00010",
-			opx_out(28 downto 0) & B"000"               WHEN  B"00011",
-			opx_out(27 downto 0) & X"0"                 WHEN  B"00100",
-			opx_out(26 downto 0) & X"0" & B"0"          WHEN  B"00101",
-			opx_out(25 downto 0) & X"0" & B"00"         WHEN  B"00110",
-			opx_out(24 downto 0) & X"0" & B"000"        WHEN  B"00111",
-			opx_out(23 downto 0) & X"00"                WHEN  B"01000",
-			opx_out(22 downto 0) & X"00" & B"0"         WHEN  B"01001",
-			opx_out(21 downto 0) & X"00" & B"00"        WHEN  B"01010",
-			opx_out(20 downto 0) & X"00" & B"000"       WHEN  B"01011",
-			opx_out(19 downto 0) & X"000"               WHEN  B"01100",
-			opx_out(18 downto 0) & X"000" & B"0"        WHEN  B"01101",
-			opx_out(17 downto 0) & X"000" & B"00"       WHEN  B"01110",
-			opx_out(16 downto 0) & X"000" & B"000"      WHEN  B"01111",
-			opx_out(15 downto 0) & X"0000"              WHEN  B"10000",
-			opx_out(14 downto 0) & X"0000" & B"0"       WHEN  B"10001",
-			opx_out(13 downto 0) & X"0000" & B"00"      WHEN  B"10010",
-			opx_out(12 downto 0) & X"0000" & B"000"     WHEN  B"10011",
-			opx_out(11 downto 0) & X"00000"             WHEN  B"10100",
-			opx_out(10 downto 0) & X"00000" & B"0"      WHEN  B"10101",
-			opx_out(9  downto 0) & X"00000" & B"00"     WHEN  B"10110",
-			opx_out(8  downto 0) & X"00000" & B"000"    WHEN  B"10111",
-			opx_out(7  downto 0) & X"000000"            WHEN  B"11000",
-			opx_out(6  downto 0) & X"000000" & B"0"     WHEN  B"11001",
-			opx_out(5  downto 0) & X"000000" & B"00"    WHEN  B"11010",
-			opx_out(4  downto 0) & X"000000" & B"000"   WHEN  B"11011",
-			opx_out(3  downto 0) & X"0000000"           WHEN  B"11100",
-			opx_out(2  downto 0) & X"0000000" & B"0"    WHEN  B"11101",
-			opx_out(1  downto 0) & X"0000000" & B"00"   WHEN  B"11110",
-			opx_out(0)           & X"0000000" & B"000"  WHEN  B"11111";
-
-	-- Result of right shift affected to signal 'alu_shright'.
-	WITH opy_out(4 downto 0) SELECT
-		alu_shright  <=
-								  opx_out(31 downto 0)   WHEN  B"00000",
-			alu_shsign(0)       & opx_out(31 downto 1)   WHEN  B"00001",
-			alu_shsign(0 to  1) & opx_out(31 downto 2)   WHEN  B"00010",
-			alu_shsign(0 to  2) & opx_out(31 downto 3)   WHEN  B"00011",
-			alu_shsign(0 to  3) & opx_out(31 downto 4)   WHEN  B"00100",
-			alu_shsign(0 to  4) & opx_out(31 downto 5)   WHEN  B"00101",
-			alu_shsign(0 to  5) & opx_out(31 downto 6)   WHEN  B"00110",
-			alu_shsign(0 to  6) & opx_out(31 downto 7)   WHEN  B"00111",
-			alu_shsign(0 to  7) & opx_out(31 downto 8)   WHEN  B"01000",
-			alu_shsign(0 to  8) & opx_out(31 downto 9)   WHEN  B"01001",
-			alu_shsign(0 to  9) & opx_out(31 downto 10)  WHEN  B"01010",
-			alu_shsign(0 to 10) & opx_out(31 downto 11)  WHEN  B"01011",
-			alu_shsign(0 to 11) & opx_out(31 downto 12)  WHEN  B"01100",
-			alu_shsign(0 to 12) & opx_out(31 downto 13)  WHEN  B"01101",
-			alu_shsign(0 to 13) & opx_out(31 downto 14)  WHEN  B"01110",
-			alu_shsign(0 to 14) & opx_out(31 downto 15)  WHEN  B"01111",
-			alu_shsign(0 to 15) & opx_out(31 downto 16)  WHEN  B"10000",
-			alu_shsign(0 to 16) & opx_out(31 downto 17)  WHEN  B"10001",
-			alu_shsign(0 to 17) & opx_out(31 downto 18)  WHEN  B"10010",
-			alu_shsign(0 to 18) & opx_out(31 downto 19)  WHEN  B"10011",
-			alu_shsign(0 to 19) & opx_out(31 downto 20)  WHEN  B"10100",
-			alu_shsign(0 to 20) & opx_out(31 downto 21)  WHEN  B"10101",
-			alu_shsign(0 to 21) & opx_out(31 downto 22)  WHEN  B"10110",
-			alu_shsign(0 to 22) & opx_out(31 downto 23)  WHEN  B"10111",
-			alu_shsign(0 to 23) & opx_out(31 downto 24)  WHEN  B"11000",
-			alu_shsign(0 to 24) & opx_out(31 downto 25)  WHEN  B"11001",
-			alu_shsign(0 to 25) & opx_out(31 downto 26)  WHEN  B"11010",
-			alu_shsign(0 to 26) & opx_out(31 downto 27)  WHEN  B"11011",
-			alu_shsign(0 to 27) & opx_out(31 downto 28)  WHEN  B"11100",
-			alu_shsign(0 to 28) & opx_out(31 downto 29)  WHEN  B"11101",
-			alu_shsign(0 to 29) & opx_out(31 downto 30)  WHEN  B"11110",
-			alu_shsign(0 to 30) & opx_out(31)            WHEN  B"11111";
-
-	-- Select the output of the shifter (left or right).
-	alu_shout <= alu_shleft WHEN alu_mx2i0 = '1' ELSE alu_shright;
-
-
-	-- ************ ALU Arythmetic Operations Description ************
-
-
-	alu_yop(31 downto 0) <= not opy_out WHEN alu_mx0i0 ELSE opy_out;
-
-	alu_cry(0)           <= alu_mx0i0;
-	alu_cry(32 downto 1) <= (opx_out and alu_yop             )
-						 or (opx_out and alu_cry(31 downto 0))
-						 or (alu_yop and alu_cry(31 downto 0));
-	alu_sum(31 downto 0) <=  opx_out xor alu_cry(31 downto 0) xor alu_yop;
-
-
-	-- ***************** ALU Multiplexer Description *****************
-
-
-	-- Check ALU multiplexer commands.
-	ASSERT(not (alu_mx2i1 xor alu_mx2i0))
-		REPORT "alu_mx2i1:0 must have the same value."
-		SEVERITY WARNING;
-	ASSERT(not((alu_mx1i2 xor alu_mx1i1) and (alu_mx1i1 xor alu_mx1i0)) )
-		REPORT "alu_mx1i2:1:0 must have the same value."
-		SEVERITY WARNING;
-
-	WITH alu_mx4i0 & alu_mx3i0 & alu_mx2i1 & alu_mx1i2
-										   & alu_mx1i1 SELECT
-		alu_out <= X"0000000" & B"000" & (not alu_test_n)
-							  WHEN  B"00000"
-								   |B"00001"
-								   |B"00010"
-								   |B"00011"
-								   |B"00100"
-								   |B"00101"
-								   |B"00110"
-								   |B"00111"
-								   |B"01000"
-								   |B"01001"
-								   |B"01010"
-								   |B"01011"
-								   |B"01100"
-								   |B"01101"
-								   |B"01110"
-								   |B"01111",
-					alu_shout WHEN  B"10000"
-								   |B"10001"
-								   |B"10010"
-								   |B"10011"
-								   |B"10100"
-								   |B"10101"
-								   |B"10110"
-								   |B"10111",
-		  opx_out  or opy_out WHEN  B"11000"
-								   |B"11010",
-		  opx_out and opy_out WHEN  B"11001"
-								   |B"11011",
-		  opx_out xor opy_out WHEN  B"11100"
-								   |B"11101",
-					  alu_sum WHEN  B"11110"
-								   |B"11111";
-
-								   
-	-- ************* ALU Auxiliary Outputs Affectations **************
-
-
-	-- Flag affectations.
-	alu_nul   <= '1' WHEN (alu_sum(31 downto 0) = X"00000000") ELSE  '0';
-	alu_sign  <=     alu_sum(31);
-	alu_c31 <= not alu_cry(32);
-	alu_c30 <= not alu_cry(31);
-	-- Main data bus output, to the pads.
-	WITH alu_byte SELECT
-		data_out_n <= not ( alu_out( 7 downto 0)
-						  & alu_out( 7 downto 0)
-						  & alu_out( 7 downto 0)
-						  & alu_out( 7 downto 0)) WHEN '1',
-					  not   alu_out(31 downto 0)  WHEN '0';
-
-
-	data_out_dpt <= not data_out_n;
-
-	-- *************** ADROUT Multiplexer Description ****************
--- modif les plots ne sont plus inverseurs
-
-
-	WITH out_mx0i0 SELECT
-		out_adr_n <= not pc_s WHEN B"1",
-					 not ad_s WHEN B"0";
-
--- nouveaux connecteurs
-
-	out_adr <=  NOT out_adr_n ;
-
-	adr_n_0  <= out_adr_n(0) ;
-	adr_n_1  <= out_adr_n(1) ;
-	adr_n_31  <= out_adr_n(31) ;
-
-	-- ******************* PC Register Description *******************
-
-
-	pc_ckt   <= pc_ck and      pc_test;
-	pc_ckd   <= pc_ck and (not pc_test) and pc_wen;
-	pc_scout <= pc_s(31);
-
-	wmt_pc:BLOCK(pc_ckt = '1')
-	BEGIN
-		pc_m <= GUARDED pc_s(30 downto 0) & pc_scin;
-	END BLOCK wmt_pc;
-
-	wmd_pc:BLOCK(pc_ckd = '1') BEGIN pc_m <= GUARDED alu_out; END BLOCK wmd_pc;
-	 ws_pc:BLOCK(pc_ck  = '0') BEGIN pc_s <= GUARDED  pc_m  ; END BLOCK  ws_pc;
-
-
-	-- ******************* AD Register Description *******************
-
-
-	ad_ckt   <= ad_ck and      ad_test;
-	ad_ckd   <= ad_ck and (not ad_test) and ad_wen;
-	ad_scout <= ad_s(31);
-
-	wmt_ad:BLOCK(ad_ckt = '1')
-	BEGIN
-		ad_m <= GUARDED ad_s(30 downto 0) & ad_scin;
-	END BLOCK wmt_ad;
-
-	wmd_ad:BLOCK(ad_ckd = '1') BEGIN ad_m <= GUARDED alu_out; END BLOCK wmd_ad;
-	 ws_ad:BLOCK(ad_ck  = '0') BEGIN ad_s <= GUARDED  ad_m  ; END BLOCK  ws_ad;
-
-
-	-- ******************* TVR Register Description *******************
-
-
-	tvr_ckt   <= tvr_ck and      tvr_test;
-	tvr_ckd   <= tvr_ck and (not tvr_test) and tvr_wen;
-	tvr_scout <= tvr_s(31);
-
-	wmt_tvr:BLOCK(tvr_ckt = '1')
-	BEGIN
-		tvr_m <= GUARDED tvr_s(30 downto 0) & tvr_scin;
-	END BLOCK wmt_tvr;
-
-wmd_tvr:BLOCK(tvr_ckd = '1') BEGIN tvr_m <= GUARDED alu_out; END BLOCK wmd_tvr;
- ws_tvr:BLOCK(tvr_ck  = '0') BEGIN tvr_s <= GUARDED tvr_m  ; END BLOCK  ws_tvr;
-
-
-	-- ******************* IAR Register Description *******************
-
-
-	iar_ckt   <= iar_ck and      iar_test;
-	iar_ckd   <= iar_ck and (not iar_test) and iar_wen;
-	iar_scout <= iar_s(31);
-
-	wmt_iar:BLOCK(iar_ckt = '1')
-	BEGIN
-		iar_m <= GUARDED iar_s(30 downto 0) & iar_scin;
-	END BLOCK wmt_iar;
-
-wmd_iar:BLOCK(iar_ckd = '1') BEGIN iar_m <= GUARDED alu_out; END BLOCK wmd_iar;
- ws_iar:BLOCK(iar_ck  = '0') BEGIN iar_s <= GUARDED iar_m  ; END BLOCK  ws_iar;
-
-
-	-- ******************* SR Register Description *******************
-
-
-	sr_ckt   <= sr_ck and      sr_test;
-	sr_ckd   <= sr_ck and (not sr_test) and sr_wen;
-	sr_scout <= sr_s(31);
-	sr_mask  <= sr_s( 1);
-	sr_mode  <= sr_s( 0);
-
-	wmt_sr:BLOCK(sr_ckt = '1')
-	BEGIN
-		sr_m <= GUARDED sr_s(30 downto 0) & sr_scin;
-	END BLOCK wmt_sr;
-
-wmd_sr:BLOCK(sr_ckd='1')
-BEGIN
-	WITH sr_mx SELECT
-		sr_m <= GUARDED alu_out(31 downto  0)            WHEN '0',
-						alu_out(31 downto 16) & sr_it3
-											  & sr_it2
-											  & sr_it1
-											  & sr_it0
-											  & sr_ovr
-											  & sr_dav
-											  & sr_ico
-											  & sr_iav
-											  & B"0000"
-											  & sr_cpurst
-											  & B"000"   WHEN '1';
-END BLOCK wmd_sr;
- ws_sr:BLOCK(sr_ck ='0') BEGIN sr_s <= GUARDED  sr_m;   END BLOCK  ws_sr;
-
-
-	-- ******************* IR Register Description *******************
-
-
-	ir_ckt   <= ir_ck and      ir_test;
-	ir_ckd   <= ir_ck and (not ir_test) and ir_wen;
-	ir_scout <= ir_s(31);
-
-	wmt_ir:BLOCK(ir_ckt = '1')
-	BEGIN
-		ir_m <= GUARDED ir_s(30 downto 0) & ir_scin;
-	END BLOCK wmt_ir;
-
-wmd_ir:BLOCK(ir_ckd='1') BEGIN ir_m <= GUARDED not data_in_n; END BLOCK wmd_ir;
- ws_ir:BLOCK(ir_ck ='0') BEGIN ir_s <= GUARDED       ir_m;    END BLOCK  ws_ir;
-
-
-	-- ******************* DT Register Description *******************
-
-
-	dt_ckt   <= dt_ck and      dt_test;
-	dt_ckd   <= dt_ck and (not dt_test) and dt_wen;
-	dt_scout <= dt_s(31);
-
-	wmt_dt:BLOCK(dt_ckt = '1')
-	BEGIN
-		dt_m <= GUARDED dt_s(30 downto 0) & dt_scin;
-	END BLOCK wmt_dt;
-
-wmd_dt:BLOCK(dt_ckd='1') BEGIN dt_m <= GUARDED opy_dt; END BLOCK wmd_dt;
- ws_dt:BLOCK(dt_ck ='0') BEGIN dt_s <= GUARDED  dt_m;  END BLOCK  ws_dt;
-
-
-	-- *************** Register File (RF) Description ****************
-
-
-	rf_ckd <= rf_ck and rf_wen;
-
-	-- Write masters description.
-	wm_rf:BLOCK(rf_ckd)
-	BEGIN
-		rf_m1  <= GUARDED alu_out WHEN  rf_aw = B"00001"  ELSE  rf_m1;
-		rf_m2  <= GUARDED alu_out WHEN  rf_aw = B"00010"  ELSE  rf_m2;
-		rf_m3  <= GUARDED alu_out WHEN  rf_aw = B"00011"  ELSE  rf_m3;
-		rf_m4  <= GUARDED alu_out WHEN  rf_aw = B"00100"  ELSE  rf_m4;
-		rf_m5  <= GUARDED alu_out WHEN  rf_aw = B"00101"  ELSE  rf_m5;
-		rf_m6  <= GUARDED alu_out WHEN  rf_aw = B"00110"  ELSE  rf_m6;
-		rf_m7  <= GUARDED alu_out WHEN  rf_aw = B"00111"  ELSE  rf_m7;
-		rf_m8  <= GUARDED alu_out WHEN  rf_aw = B"01000"  ELSE  rf_m8;
-		rf_m9  <= GUARDED alu_out WHEN  rf_aw = B"01001"  ELSE  rf_m9;
-		rf_m10 <= GUARDED alu_out WHEN  rf_aw = B"01010"  ELSE  rf_m10;
-		rf_m11 <= GUARDED alu_out WHEN  rf_aw = B"01011"  ELSE  rf_m11;
-		rf_m12 <= GUARDED alu_out WHEN  rf_aw = B"01100"  ELSE  rf_m12;
-		rf_m13 <= GUARDED alu_out WHEN  rf_aw = B"01101"  ELSE  rf_m13;
-		rf_m14 <= GUARDED alu_out WHEN  rf_aw = B"01110"  ELSE  rf_m14;
-		rf_m15 <= GUARDED alu_out WHEN  rf_aw = B"01111"  ELSE  rf_m15;
-		rf_m16 <= GUARDED alu_out WHEN  rf_aw = B"10000"  ELSE  rf_m16;
-		rf_m17 <= GUARDED alu_out WHEN  rf_aw = B"10001"  ELSE  rf_m17;
-		rf_m18 <= GUARDED alu_out WHEN  rf_aw = B"10010"  ELSE  rf_m18;
-		rf_m19 <= GUARDED alu_out WHEN  rf_aw = B"10011"  ELSE  rf_m19;
-		rf_m20 <= GUARDED alu_out WHEN  rf_aw = B"10100"  ELSE  rf_m20;
-		rf_m21 <= GUARDED alu_out WHEN  rf_aw = B"10101"  ELSE  rf_m21;
-		rf_m22 <= GUARDED alu_out WHEN  rf_aw = B"10110"  ELSE  rf_m22;
-		rf_m23 <= GUARDED alu_out WHEN  rf_aw = B"10111"  ELSE  rf_m23;
-		rf_m24 <= GUARDED alu_out WHEN  rf_aw = B"11000"  ELSE  rf_m24;
-		rf_m25 <= GUARDED alu_out WHEN  rf_aw = B"11001"  ELSE  rf_m25;
-		rf_m26 <= GUARDED alu_out WHEN  rf_aw = B"11010"  ELSE  rf_m26;
-		rf_m27 <= GUARDED alu_out WHEN  rf_aw = B"11011"  ELSE  rf_m27;
-		rf_m28 <= GUARDED alu_out WHEN  rf_aw = B"11100"  ELSE  rf_m28;
-		rf_m29 <= GUARDED alu_out WHEN  rf_aw = B"11101"  ELSE  rf_m29;
-		rf_m30 <= GUARDED alu_out WHEN  rf_aw = B"11110"  ELSE  rf_m30;
-		rf_m31 <= GUARDED alu_out WHEN  rf_aw = B"11111"  ELSE  rf_m31;
-	END BLOCK wm_rf;
-
-	-- Write slave description.
-	ws_rf:BLOCK(rf_ck = '0')
-	BEGIN
-		WITH  rf_ar  SELECT
-			rf_s <= GUARDED X"00000000"  WHEN  B"00000",
-								 rf_m1   WHEN  B"00001",
-								 rf_m2   WHEN  B"00010",
-								 rf_m3   WHEN  B"00011",
-								 rf_m4   WHEN  B"00100",
-								 rf_m5   WHEN  B"00101",
-								 rf_m6   WHEN  B"00110",
-								 rf_m7   WHEN  B"00111",
-								 rf_m8   WHEN  B"01000",
-								 rf_m9   WHEN  B"01001",
-								 rf_m10  WHEN  B"01010",
-								 rf_m11  WHEN  B"01011",
-								 rf_m12  WHEN  B"01100",
-								 rf_m13  WHEN  B"01101",
-								 rf_m14  WHEN  B"01110",
-								 rf_m15  WHEN  B"01111",
-								 rf_m16  WHEN  B"10000",
-								 rf_m17  WHEN  B"10001",
-								 rf_m18  WHEN  B"10010",
-								 rf_m19  WHEN  B"10011",
-								 rf_m20  WHEN  B"10100",
-								 rf_m21  WHEN  B"10101",
-								 rf_m22  WHEN  B"10110",
-								 rf_m23  WHEN  B"10111",
-								 rf_m24  WHEN  B"11000",
-								 rf_m25  WHEN  B"11001",
-								 rf_m26  WHEN  B"11010",
-								 rf_m27  WHEN  B"11011",
-								 rf_m28  WHEN  B"11100",
-								 rf_m29  WHEN  B"11101",
-								 rf_m30  WHEN  B"11110",
-								 rf_m31  WHEN  B"11111";
-	END BLOCK ws_rf;
-
-END  fonctional;
diff --git a/alliance/share/tutorials/dlxm/dlxm_scan.pat b/alliance/share/tutorials/dlxm/dlxm_scan.pat
deleted file mode 100644
index 08112d73..00000000
--- a/alliance/share/tutorials/dlxm/dlxm_scan.pat
+++ /dev/null
@@ -1,1503 +0,0 @@
--- ### -------------------------------------------------------------- ###
--- #									#
--- # file	: dlxm_scan.pat						#
--- # date	: February 1995 					#
--- # version	: v0.0							#
--- #									#
--- # origin	: this description has been developed by CAO-VLSI team	#
--- #		  at MASI laboratory, University Pierre et Marie Curie	#
--- #		  URA CNRS 818, Institut Blaise Pascal			#
--- #		  4 Place Jussieu 75252 Paris Cedex 05 - France		#
--- # E-mail      :      cao-vlsi@masi.ibp.fr                            #
--- #									#
--- # descr.	: pattern input file for scan path simulation of the    #
--- # 		  DLXm chip inside the dlxm_cpu board			#
--- #									#
--- ### -------------------------------------------------------------- ###
-
-
-
-
---		sequence : pattern
-
--- input / output list :
-in       scin B;;
-in       ck B;;
-in       reset B;;
-in       frz B;;
-out      rw B;;
-out      byte (0 to 3) X;;
-inout    data (31 downto 0) X;;
-inout    data_adr (31 downto 0) X;;
-in       vdd B;;
-in       vss B;;
-in       test B;;
-out      scout B;;
-
-begin
-
--- Pattern description :
-
---                s c r f  r  b  d         d        v v t  s  
---                c k e r  w  y  a         a        d s e  c  
---                i   s z     t  t         t        d s s  o  
---                n   e       e  a         a            t  u  
---                    t                    _               t  
---                                         a                  
---                                         d                  
---                                         r                  
-
-                : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_1            : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_2            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_3            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_4            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_5            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_1            : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_2            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_3            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_4            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_5            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_1            : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_2            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_3            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_4            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_5            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_1            : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_2            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_3            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_4            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_5            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_1            : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_2            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_3            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_4            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_5            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_1            : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_2            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_3            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_4            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_5            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_1            : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_2            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_3            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_4            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_5            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_1            : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_2            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_3            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_4            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_5            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_1            : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_2            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_3            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_4            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_5            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_1            : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_2            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_3            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_4            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_5            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_1            : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_2            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_3            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_4            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_5            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_1            : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_2            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_3            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_4            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_5            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_1            : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_2            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_3            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_4            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_5            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_1            : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_2            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_3            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_4            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_5            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_1            : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_2            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_3            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_4            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_5            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_1            : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_2            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_3            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_4            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_5            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_1            : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_2            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_3            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_4            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_5            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_1            : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_2            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_3            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_4            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_5            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_1            : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_2            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_3            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_4            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_5            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 0 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_1            : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_2            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_3            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-ck_4            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?* ;
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-ck_3            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_4            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_5            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 0 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_1            : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_2            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?0 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?0 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?0 ;
-ck_3            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_4            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_5            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 0 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_1            : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_2            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?0 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?0 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?0 ;
-ck_3            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_4            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_5            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 0 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_1            : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_2            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?0 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?0 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?0 ;
-ck_3            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_4            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_5            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 0 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_1            : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_2            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?0 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?0 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?0 ;
-ck_3            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_4            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_5            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 0 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_1            : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_2            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?0 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?0 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?0 ;
-ck_3            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_4            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_5            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 0 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_1            : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_2            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?0 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?0 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?0 ;
-ck_3            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_4            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_5            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 0 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_1            : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_2            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?0 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?0 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?0 ;
-ck_3            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_4            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_5            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 0 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_1            : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_2            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?0 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?0 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?0 ;
-ck_3            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_4            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_5            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 0 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_1            : 0 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_2            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?0 ;
-                : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?0 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?0 ;
-ck_3            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-cycle_484       : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-                : 1 1 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-ck_4            : 1 0 0 0 ?* ?0 ?******** ?******** 1 0 1 ?1 ;
-
-end;
diff --git a/alliance/share/tutorials/dlxm/dlxm_seq.enc b/alliance/share/tutorials/dlxm/dlxm_seq.enc
deleted file mode 100644
index 5cfd719e..00000000
--- a/alliance/share/tutorials/dlxm/dlxm_seq.enc
+++ /dev/null
@@ -1,51 +0,0 @@
-# Encoding figure "dlxm_seq"
--a 6
-pct	1
-sr16l	3E
-irq	0
-ifetch	10
-lbu2	16
-lw2	26
-sb	39
-sw	25
-lbu	3
-lw	2D
-adr	11
-i2iar	1A
-iar2i	2A
-i2tvr	A
-tvr2i	32
-i2sr	6
-sr2i	3A
-i2s	3D
-s2i	1D
-trap	22
-sr16r	1E
-rfe	D
-jr	29
-jalr	35
-j	E
-jal	15
-branch	2E
-beqz	19
-bnez	5
-lxor	34
-land	38
-lor	C
-imdu	31
-lhi	12
-slt	4
-sgt	3C
-sle	1C
-sge	2C
-sne	14
-seq	18
-sra	8
-srl	28
-sll	30
-sub	24
-add	2
-imd	21
-reg	9
-ico1	20
-init	36
diff --git a/alliance/share/tutorials/dlxm/dlxm_seq.fsm b/alliance/share/tutorials/dlxm/dlxm_seq.fsm
deleted file mode 100644
index 1036f1e1..00000000
--- a/alliance/share/tutorials/dlxm/dlxm_seq.fsm
+++ /dev/null
@@ -1,1638 +0,0 @@
-
--- ### -------------------------------------------------------------- ###
--- #									#
--- # file	: dlxm_seq.fsm						#
--- # date	: 14 February 1995					#
--- # version	: v0.0							#
--- #									#
--- # origin	: this description has been developed by CAO-VLSI team	#
--- #		  at MASI laboratory, University Pierre et Marie Curie	#
--- #		  URA CNRS 818, Institut Blaise Pascal			#
--- #		  4 Place Jussieu 75252 Paris Cedex 05 - France		#
--- # E-mail      :      cao-vlsi@masi.ibp.fr                            #
--- #									#
--- # descr.	: Finite State Machine desciption of the sequencer	#
--- #		  Reset input is coming from the status			#
--- #									#
--- ### -------------------------------------------------------------- ###
-
-
-entity dlxm_seq is
-
--- Declaration de l'interface ( copie par coeur.vst )
-
-  PORT (
-  ck            : in BIT;                       -- ck
-  frz           : in BIT;                       -- frz
-  rqs           : in BIT;                       -- int,rqs,reset
-  reset		: in BIT;			-- status reset register
-  resnul        : in BIT;                       -- resnul
-  ir_opcod      : in bit_vector(5 DOWNTO 0) ;   -- ir_opcod
-  ir_tvr        : in BIT;                       -- ir_tvr
-  ir_iar        : in BIT;                       -- ir_iar
-  ir_sr         : in BIT;                       -- ir_sr
-  vdd           : in BIT;                       -- vdd
-  vss           : in BIT;                       -- vss
-  scin          : in BIT;                       -- scin
-  test          : in BIT;                       -- test
-  ovr_en        : out BIT;                      -- ovr_en
-  ico           : out BIT;                      -- ico
-  priv          : out BIT;                      -- priv
-  iformt	: out BIT;			-- iformt 
-  riformt	: out BIT;			-- iformt 
-  ctlopx        : out bit_vector(5 DOWNTO 0) ;  -- ctlopx
-  ctlopy        : out bit_vector(4 DOWNTO 0) ;  -- ctlopy
-  ctlalu        : out bit_vector(4 DOWNTO 0) ;  -- ctlalu
-  wenable       : out bit_vector(8 DOWNTO 0) ;  -- wenable
-  ctlrw         : out bit_vector(3 DOWNTO 0) ;  -- ctlrw
-  ctladr	: out bit ;			-- ctladr
-  scout         : out BIT                       -- scout
-  );
-
-end dlxm_seq;
-
-
-architecture STATE_MACHINE of dlxm_seq is
-
--- Declaration des etats du microsequencer possibles ( un etat pour chaque m-instr )
-
-type ETAT_TYPE is ( init, ico1,  reg, imd, add, sub, sll, srl, sra, seq, sne, sge,
-		    sle, sgt, slt, lhi, imdu, lor, land, lxor, bnez, beqz, branch, jal,
-		    j, jalr, jr, rfe, sr16r, trap, s2i, i2s, sr2i, i2sr, tvr2i, i2tvr,
-		    iar2i, i2iar, adr, lw, lbu, sw, sb, lw2, lbu2, ifetch, irq, sr16l, pct );
-
-	signal EF, EP:ETAT_TYPE;
-
-	--pragma CURRENT_STATE EP
-	--pragma NEXT_STATE EF
-        --pragma SCAN_TEST test
-	--pragma SCAN_IN scin
-	--pragma SCAN_OUT scout
-        --pragma CLOCK ck
-
-	-- Declaration des OPCODES des instructions
-
-	constant add_i    : bit_vector (5 downto 0) := B"000_000"  ;    -- add
-	constant addu_i   : bit_vector (5 downto 0) := B"000_001"  ;    -- addu
-	constant sub_i    : bit_vector (5 downto 0) := B"000_010"  ;    -- sub
-	constant subu_i   : bit_vector (5 downto 0) := B"000_011"  ;    -- subu
-	constant addi_i   : bit_vector (5 downto 0) := B"000_100"  ;    -- addi
-	constant addui_i  : bit_vector (5 downto 0) := B"000_101"  ;    -- addui
-	constant subi_i   : bit_vector (5 downto 0) := B"000_110"  ;    -- subi
-	constant subui_i  : bit_vector (5 downto 0) := B"000_111"  ;    -- subui
-	constant sll_i    : bit_vector (5 downto 0) := B"001_000"  ;    -- sll
-	constant srl_i    : bit_vector (5 downto 0) := B"001_001"  ;    -- srl
-	constant sra_i    : bit_vector (5 downto 0) := B"001_010"  ;    -- sra
-	constant slli_i   : bit_vector (5 downto 0) := B"001_100"  ;    -- slli
-	constant srli_i   : bit_vector (5 downto 0) := B"001_101"  ;    -- srli
-	constant srai_i   : bit_vector (5 downto 0) := B"001_110"  ;    -- srai
-	constant lhi_i    : bit_vector (5 downto 0) := B"001_111"  ;    -- lhi
-	constant seq_i    : bit_vector (5 downto 0) := B"010_000"  ;    -- seq
-	constant sne_i    : bit_vector (5 downto 0) := B"010_001"  ;    -- sne
-	constant sge_i    : bit_vector (5 downto 0) := B"010_010"  ;    -- sge
-	constant sle_i    : bit_vector (5 downto 0) := B"010_011"  ;    -- sle
-	constant seqi_i   : bit_vector (5 downto 0) := B"010_100"  ;    -- seqi
-	constant snei_i   : bit_vector (5 downto 0) := B"010_101"  ;    -- snei
-	constant sgei_i   : bit_vector (5 downto 0) := B"010_110"  ;    -- sgei
-	constant slei_i   : bit_vector (5 downto 0) := B"010_111"  ;    -- slei
-	constant sgt_i    : bit_vector (5 downto 0) := B"011_010"  ;    -- sgt
-	constant slt_i    : bit_vector (5 downto 0) := B"011_011"  ;    -- slt
-	constant sgti_i   : bit_vector (5 downto 0) := B"011_110"  ;    -- sgti
-	constant slti_i   : bit_vector (5 downto 0) := B"011_111"  ;    -- slti
-	constant and_i    : bit_vector (5 downto 0) := B"100_000"  ;    -- and
-	constant or_i     : bit_vector (5 downto 0) := B"100_001"  ;    -- or
-	constant xor_i    : bit_vector (5 downto 0) := B"100_011"  ;    -- xor
-	constant andi_i   : bit_vector (5 downto 0) := B"100_100"  ;    -- andi
-	constant ori_i    : bit_vector (5 downto 0) := B"100_101"  ;    -- ori
-	constant xori_i   : bit_vector (5 downto 0) := B"100_111"  ;    -- xori
-
-	constant sw_i     : bit_vector (5 downto 0) := B"101_000"  ;    -- sw
-	constant sh_i     : bit_vector (5 downto 0) := B"101_001"  ;    -- sh
-	constant sb_i     : bit_vector (5 downto 0) := B"101_010"  ;    -- sb
-	constant lbu_i    : bit_vector (5 downto 0) := B"101_011"  ;    -- lbu
-	constant lw_i     : bit_vector (5 downto 0) := B"101_100"  ;    -- lw
-	constant lh_i     : bit_vector (5 downto 0) := B"101_101"  ;    -- lh
-	constant lb_i     : bit_vector (5 downto 0) := B"101_110"  ;    -- lb
-	constant lhu_i    : bit_vector (5 downto 0) := B"101_111"  ;    -- lhu
-
-	constant jr_i     : bit_vector (5 downto 0) := B"110_000"  ;    -- jr
-	constant jalr_i   : bit_vector (5 downto 0) := B"110_001"  ;    -- jalr
-	constant movs2i_i : bit_vector (5 downto 0) := B"110_010"  ;    -- movi2s
-	constant movi2s_i : bit_vector (5 downto 0) := B"110_011"  ;    -- movs2i
-	constant beqz_i   : bit_vector (5 downto 0) := B"110_100"  ;    -- beqz
-	constant bnez_i   : bit_vector (5 downto 0) := B"110_101"  ;    -- bnez
-	constant j_i      : bit_vector (5 downto 0) := B"111_000"  ;    -- j
-	constant jal_i    : bit_vector (5 downto 0) := B"111_001"  ;    -- jal
-	constant rfe_i    : bit_vector (5 downto 0) := B"111_010"  ;    -- rfe
-	constant trap_i   : bit_vector (5 downto 0) := B"111_011"  ;    -- trap
-
-
-        -- Description des operations de l'Alu
-	constant a_sum  : bit_vector (4 downto 0) := B"11110" ;
-	constant a_sumv : bit_vector (4 downto 0) := B"11110" ;
-	constant a_dif  : bit_vector (4 downto 0) := B"11111" ;
-	constant a_difv : bit_vector (4 downto 0) := B"11111" ;
-	constant a_and  : bit_vector (4 downto 0) := B"11010" ;
-	constant a_or   : bit_vector (4 downto 0) := B"11000" ;
-	constant a_xor  : bit_vector (4 downto 0) := B"11100" ;
-	constant a_sll  : bit_vector (4 downto 0) := B"10100" ;
-	constant a_srl  : bit_vector (4 downto 0) := B"10000" ;
-	constant a_sra  : bit_vector (4 downto 0) := B"10010" ;
-	constant a_seq  : bit_vector (4 downto 0) := B"00011" ;
-	constant a_sne  : bit_vector (4 downto 0) := B"00101" ;
-	constant a_sge  : bit_vector (4 downto 0) := B"00111" ;
-	constant a_sgt  : bit_vector (4 downto 0) := B"01001" ;
-	constant a_sle  : bit_vector (4 downto 0) := B"01011" ;
-	constant a_slt  : bit_vector (4 downto 0) := B"01101" ;
-
-        -- Description de l'operande X
-
-	constant x_rs   : bit_vector (5 downto 0) := B"000011" ;
-	constant x_rt   : bit_vector (5 downto 0) := B"000010" ;
-	constant x_pc   : bit_vector (5 downto 0) := B"000100" ;
-	constant x_ad   : bit_vector (5 downto 0) := B"000101" ;
-	constant x_sr   : bit_vector (5 downto 0) := B"010000" ;
-	constant x_tvr  : bit_vector (5 downto 0) := B"001001" ;
-	constant x_iar  : bit_vector (5 downto 0) := B"001000" ;
-	constant x_c0   : bit_vector (5 downto 0) := B"010001" ;
-	constant x_cb   : bit_vector (5 downto 0) := B"100000" ;
-	constant x_ch   : bit_vector (5 downto 0) := B"100001" ;
-       
-        -- Description de l'operande Y
-
-	constant y_i16  : bit_vector (4 downto 0) := B"01000" ;
-	constant y_i18  : bit_vector (4 downto 0) := B"00101" ;
-	constant y_i28  : bit_vector (4 downto 0) := B"00100" ;
-	constant y_dt   : bit_vector (4 downto 0) := B"00011" ;
-	constant y_ad   : bit_vector (4 downto 0) := B"00010" ;
-	constant y_c0   : bit_vector (4 downto 0) := B"01001" ;
-	constant y_c4   : bit_vector (4 downto 0) := B"10000" ;
-	constant y_c16  : bit_vector (4 downto 0) := B"10001" ;
-        
-        -- Description du registre destination
-
-	constant r_no   : bit_vector (8 downto 0) := B"000000000" ;
-	constant r_pc   : bit_vector (8 downto 0) := B"000000001" ;
-	constant r_ad   : bit_vector (8 downto 0) := B"000000010" ;
-	constant r_rd   : bit_vector (8 downto 0) := B"000000100" ;
-	constant r_r31  : bit_vector (8 downto 0) := B"000001100" ;
-	constant r_iar  : bit_vector (8 downto 0) := B"000010000" ;
-	constant r_siar : bit_vector (8 downto 0) := B"100010000" ;
-	constant r_tvr  : bit_vector (8 downto 0) := B"000100000" ;
-	constant r_sr   : bit_vector (8 downto 0) := B"001000000" ;
-	constant r_ssr  : bit_vector (8 downto 0) := B"011000000" ;
-
-        -- Description des modes d'acces memoire
-
-	constant m_no    : bit_vector (3 downto 0) := B"0001" ;
-	constant m_fetch : bit_vector (3 downto 0) := B"1001" ;
-	constant m_rw    : bit_vector (3 downto 0) := B"0101" ;
-	constant m_ww    : bit_vector (3 downto 0) := B"0000" ;
-	constant m_rb    : bit_vector (3 downto 0) := B"0111" ;
-	constant m_wb    : bit_vector (3 downto 0) := B"0010" ;
-
-        constant o_no    : bit := '1';
-        constant o_fetch : bit := '1';
-        constant o_rw    : bit := '0';
-        constant o_ww    : bit := '0';
-        constant o_rb	 : bit := '0';
-        constant o_wb    : bit := '0';
-
-
-	-- Description du graphe de transitions
-	begin
-
-	process ( EP   , ir_opcod, resnul, frz  , rqs,
-                  reset, ir_tvr  , ir_iar, ir_sr      )
-
-	begin
-
-	if (reset = '1' or test='1') then
-		EF      <= ifetch;
-  		ovr_en  <= '0'   ;
-  		ico     <= '0'   ;
-  		priv    <= '0'   ;
-  		iformt  <= '0';	
-  		riformt <= '0';	
-  		ctlopx  <= x_c0  ;
-  		ctlopy  <= y_c0  ;
-  		ctlalu  <= a_sum ;
-		wenable <= r_no  ;
-		ctlrw   <= m_no  ;
-		ctladr  <= o_no   ;
-	else
-
-	case EP is
--- ***********************************************************************
-		when init =>
-                   	if frz then EF <= init;
-			elsif ir_opcod = ori_i		then EF <= imdu	  ;		
-			elsif ir_opcod = andi_i		then EF <= imdu	  ;		
-			elsif ir_opcod = xori_i		then EF <= imdu	  ;		
-			elsif ir_opcod = or_i		then EF <= reg	  ;		
-			elsif ir_opcod = and_i		then EF <= reg	  ;		
-			elsif ir_opcod = xor_i		then EF <= reg	  ;		
-			elsif ir_opcod = add_i		then EF <= reg	  ;		
-			elsif ir_opcod = sub_i		then EF <= reg	  ;		
-			elsif ir_opcod = sll_i		then EF <= reg	  ;		
-			elsif ir_opcod = srl_i		then EF <= reg	  ;		
-			elsif ir_opcod = sra_i		then EF <= reg	  ;		
-			elsif ir_opcod = seq_i		then EF <= reg	  ;		
-			elsif ir_opcod = sne_i		then EF <= reg	  ;		
-			elsif ir_opcod = sge_i		then EF <= reg	  ;		
-			elsif ir_opcod = sle_i		then EF <= reg	  ;		
-			elsif ir_opcod = sgt_i		then EF <= reg	  ;		
-			elsif ir_opcod = slt_i		then EF <= reg	  ;  		
-			elsif ir_opcod = addi_i		then EF <= imd	  ;		
-			elsif ir_opcod = subi_i		then EF <= imd	  ;		
-			elsif ir_opcod = slli_i		then EF <= imd	  ;		
-			elsif ir_opcod = srli_i		then EF <= imd	  ;		
-			elsif ir_opcod = srai_i		then EF <= imd	  ;		
-			elsif ir_opcod = lhi_i		then EF <= imd	  ;		
-			elsif ir_opcod = seqi_i		then EF <= imd	  ;		
-			elsif ir_opcod = snei_i		then EF <= imd	  ;		
-			elsif ir_opcod = sgei_i		then EF <= imd	  ;		
-			elsif ir_opcod = slei_i		then EF <= imd	  ;		
-			elsif ir_opcod = sgti_i		then EF <= imd	  ;		
-			elsif ir_opcod = slti_i		then EF <= imd	  ;		
-			elsif ir_opcod = jal_i		then EF <= jal	  ;		
-			elsif ir_opcod = j_i		then EF <= j	  ;	 
-			elsif ir_opcod = jalr_i		then EF <= jalr	  ;		
-			elsif ir_opcod = jr_i		then EF <= jr	  ;	
-			elsif ir_opcod = rfe_i		then EF <= rfe    ;		
-			elsif ir_opcod = trap_i		then EF <= trap	  ;		
-			elsif ir_opcod = movs2i_i	then EF <= s2i    ;		
-			elsif ir_opcod = movi2s_i	then EF <= i2s    ;		
-			elsif ir_opcod = lw_i 		then EF <= adr    ;		
-			elsif ir_opcod = lbu_i		then EF <= adr    ;		
-			elsif ir_opcod = sw_i		then EF <= adr    ;		
-			elsif ir_opcod = sb_i		then EF <= adr    ;		
-			elsif ir_opcod = bnez_i		then EF <= bnez   ;		
-			elsif ir_opcod = beqz_i		then EF <= beqz	  ;	
-			else	EF <= ico1; 		
-	
-                    end if;
-
-        
-	-- mins INIT produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0' ;
-  			priv     <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '1';	
-			ctlopx  <= x_pc ;
-  			ctlopy  <= y_c4 ;
-  			ctlalu  <= a_sum ;
-                        ctlrw   <= m_no;
-			ctladr  <= o_no;
-
-                          if NOT frz then
-                                   wenable <= r_pc;
-                          else
-                                   wenable <= r_no;
-                          end if;
-
-  			
--- ***********************************************************************
-		
-		when imdu =>
-                   if frz then EF <= imdu;
-                   else
-			if ir_opcod = ori_i	then EF <= lor	;	end if;	
-			if ir_opcod = andi_i	then EF <= land	;	end if;	
-			if ir_opcod = xori_i	then EF <= lxor	;	end if;	
-                   end if;
-
-	-- mins IMDU produit les signaux suivants :
-  			ovr_en  <= '0';
-  			ico     <= '0';
-  			priv     <= '0' ;
-  			iformt <= '1';	
-  			riformt <= '0';	
-  			ctlopx  <= x_ch ;
-  			ctlopy  <= y_i16 ;
-  			ctlalu  <= a_and ;
-                        ctlrw   <= m_no;
-			ctladr  <= o_no;
-                          if NOT frz then
-                                   wenable <= r_ad;
-                          else
-                                   wenable <= r_no;
-                          end if;
-
--- ***********************************************************************
-
-		when reg =>
-                   if frz then EF <= reg;
-                   else
-			if ir_opcod = or_i	then EF <= lor	;	end if;	
-			if ir_opcod = and_i	then EF <= land	;	end if;	
-			if ir_opcod = xor_i	then EF <= lxor	;	end if;	
-			if ir_opcod = add_i	then EF <= add	;	end if;	
-			if ir_opcod = sub_i	then EF <= sub	;	end if;	
-			if ir_opcod = sll_i	then EF <= sll	;	end if;	
-			if ir_opcod = srl_i	then EF <= srl	;	end if;	
-			if ir_opcod = sra_i	then EF <= sra	;	end if;	
-			if ir_opcod = seq_i	then EF <= seq	;	end if;	
-			if ir_opcod = sne_i	then EF <= sne	;	end if;	
-			if ir_opcod = sge_i	then EF <= sge	;	end if;	
-			if ir_opcod = sle_i	then EF <= sle	;	end if;	
-			if ir_opcod = sgt_i	then EF <= sgt	;	end if;	
-			if ir_opcod = slt_i	then EF <= slt	;	end if;	
-                    end if;
-
-	-- mins REG produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0' ;
-  			priv     <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_rt ;
-  			ctlopy  <= y_c0 ;
-  			ctlalu  <= a_sum ;
-                        ctlrw   <= m_no;
-			ctladr  <= o_no;
-                           if NOT frz then
-                                   wenable <= r_ad;
-                          else
-                                   wenable <= r_no;
-                          end if;
--- ***********************************************************************
-
-		when imd =>
-                   if frz then EF <= imd;
-                   else
-			if ir_opcod = addi_i	then EF <= add	;	end if;	
-			if ir_opcod = subi_i	then EF <= sub	;	end if;	
-			if ir_opcod = slli_i	then EF <= sll	;	end if;	
-			if ir_opcod = srli_i	then EF <= srl	;	end if;	
-			if ir_opcod = srai_i	then EF <= sra	;	end if;	
-			if ir_opcod = lhi_i	then EF <= lhi	;	end if;	
-			if ir_opcod = seqi_i	then EF <= seq	;	end if;	
-			if ir_opcod = snei_i	then EF <= sne	;	end if;	
-			if ir_opcod = sgei_i	then EF <= sge	;	end if;	
-			if ir_opcod = slei_i	then EF <= sle	;	end if;	
-			if ir_opcod = sgti_i	then EF <= sgt	;	end if;	
-			if ir_opcod = slti_i	then EF <= slt	;	end if;	
-                    end if;
-
-	-- mins IMD produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0' ;
-  			priv     <= '0' ;
-  			iformt <= '1';	
-  			riformt <= '0';	
-  			ctlopx  <= x_c0 ;
-  			ctlopy  <= y_i16 ;
-  			ctlalu  <= a_sum ;
-                        ctlrw   <= m_no;
-			ctladr  <= o_no;
-                           if NOT frz then
-                                   wenable <= r_ad;
-                          else
-                                   wenable <= r_no;
-                          end if;
-
-  			
--- ***********************************************************************
-
-		when lor =>
-                   if frz then EF <= lor;
-                   else
-			if rqs then EF <= irq;
-					else EF <= init	;	end if;	
-                    end if;
-
-	-- mins LOR produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0' ;
-  			priv     <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_rs ;
-  			ctlopy  <= y_ad ;
-  			ctlalu  <= a_or ;
-                          if frz='0' then  
-  			           wenable <= r_rd ;
-  			           ctlrw   <= m_fetch ;
-  			           ctladr  <= o_fetch ;
-                          else
-  			           wenable <= r_no ;
-  			           ctlrw   <= m_no ;
-				   ctladr  <= o_no;
-                          end if;
--- ***********************************************************************
-
-		when land =>
-                   if frz then EF <= land;
-                   else
-			if rqs then EF <= irq;
-					else EF <= init	;	end if;	
-                    end if;
-
-	-- mins LAND produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0' ;
-  			priv     <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <=  x_rs;
-  			ctlopy  <=  y_ad;
-  			ctlalu  <=  a_and;
-                           if NOT frz then
-                                   wenable <= r_rd;
-                                   ctlrw   <= m_fetch;
-  			           ctladr  <= o_fetch ;
-                          else
-                                   wenable <= r_no;
-                                   ctlrw   <= m_no;
-				   ctladr  <= o_no;
-                          end if;
-
-  			
--- ***********************************************************************
-
-		when lxor =>
-                   if frz then EF <= lxor;
-                   else
-			if rqs then EF <= irq;
-					else EF <= init	;	end if;	
-                    end if;
-
-	-- mins LXOR produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0' ;
-  			priv     <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_rs ;
-  			ctlopy  <= y_ad ;
-  			ctlalu  <= a_xor ;
-                           if NOT frz then
-                                   wenable <= r_rd;
-                                   ctlrw   <= m_fetch;
-  			           ctladr  <= o_fetch ;
-                          else
-                                   wenable <= r_no;
-                                   ctlrw   <= m_no;
-			           ctladr  <= o_no;
-                          end if;
-
--- ***********************************************************************
-
-		when add =>
-                   if frz then EF <= add;
-                   else
-			if rqs then EF <= irq;
-					else EF <= init	;	end if;	
-                    end if;
-
-	-- mins ADD produit les signaux suivants :
-  			ovr_en  <=  '1';
-  			ico     <=  '0';
-  			priv     <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <=  x_rs;
-  			ctlopy  <=  y_ad;
-  			ctlalu  <=  a_sumv;
-                           if NOT frz then
-                                   wenable <= r_rd;
-                                   ctlrw   <= m_fetch;
-  			           ctladr  <= o_fetch ;
-                          else
-                                   wenable <= r_no;
-                                   ctlrw   <= m_no;
-			           ctladr  <= o_no;
-                          end if;
-
--- ***********************************************************************
-
-		when sub =>
-                   if frz then EF <= sub;
-                   else
-			if rqs then EF <= irq;
-					else EF <= init	;	end if;	
-                    end if;
-
-	-- mins SUB produit les signaux suivants :
-  			ovr_en  <= '1' ;
-  			ico     <= '0' ;
-  			priv     <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <=  x_rs;
-  			ctlopy  <=  y_ad;
-  			ctlalu  <=  a_difv;
-                           if NOT frz then
-                                   wenable <= r_rd ;
-                                   ctlrw   <= m_fetch;
-  			           ctladr  <= o_fetch ;
-                          else
-                                   wenable <= r_no;
-                                   ctlrw   <= m_no;
-			           ctladr  <= o_no;
-                          end if;
-
--- ***********************************************************************
-
-		when sll =>
-                   if frz then EF <= sll;
-                   else
-			if rqs then EF <= irq;
-					else EF <= init	;	end if;	
-                    end if;
-
-	-- mins SLL produit les signaux suivants :
-  			ovr_en  <=  '0';
-  			ico     <=  '0';
-  			priv     <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_rs ;
-  			ctlopy  <= y_ad ;
-  			ctlalu  <= a_sll ;
-                            if NOT frz then
-                                   wenable <= r_rd;
-                                   ctlrw   <= m_fetch;
-  			           ctladr  <= o_fetch ;
-                          else
-                                   wenable <= r_no;
-                                   ctlrw   <= m_no;
-			           ctladr  <= o_no;
-                          end if;
-
--- ***********************************************************************
-
-		when srl =>
-                   if frz then EF <= srl;
-                   else
-			if rqs then EF <= irq;
-					else EF <= init	;	end if;	
-                    end if;
-
-	-- mins SRL produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0' ;
-  			priv     <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_rs ;
-  			ctlopy  <= y_ad ;
-  			ctlalu  <=  a_srl;
-                           if NOT frz then
-                                   wenable <= r_rd;
-                                   ctlrw   <= m_fetch;
-  			           ctladr  <= o_fetch ;
-                           else
-				   wenable <= r_no;
-                                   ctlrw   <= m_no;
-				   ctladr  <= o_no;
-                          end if;
-
--- ***********************************************************************
-
-		when sra =>
-                   if frz then EF <= sra;
-                   else
-			if rqs then EF <= irq;
-					else EF <= init	;	end if;	
-                    end if;
-
-	-- mins SRA produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0' ;
-  			priv     <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_rs ;
-  			ctlopy  <= y_ad ;
-  			ctlalu  <= a_sra ;
-                           if NOT frz then
-                                   wenable <= r_rd;
-                                   ctlrw   <= m_fetch;
-  			           ctladr  <= o_fetch ;
-                          else
-                                   wenable <= r_no;
-                                   ctlrw   <= m_no;
-			           ctladr  <= o_no;
-                          end if;
-
-  			
--- ***********************************************************************
-
-		when lhi =>
-                   if frz then EF <= lhi;
-                   else
-			if rqs then EF <= irq;
-					else EF <= init	;	end if;	
-                    end if;
-
-	-- mins LHI produit les signaux suivants :
-  			ovr_en  <=  '0';
-  			ico     <=  '0';
-  			priv     <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <=  x_ad;
-  			ctlopy  <=  y_c16;
-  			ctlalu  <=  a_sll;
-                           if NOT frz then
-                                   wenable <= r_rd;
-                                   ctlrw   <= m_fetch;
-  			           ctladr  <= o_fetch ;
-                          else
-                                   wenable <= r_no;
-                                   ctlrw   <= m_no;
-			           ctladr  <= o_no;
-                          end if;
-
-  			
--- ***********************************************************************
-
-		when seq =>
-                   if frz then EF <= seq;
-                   else
-			if rqs then EF <= irq;
-					else EF <= init	;	end if;	
-                    end if;
-
-	-- mins SEQ produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0' ;
-  			priv     <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_rs ;
-  			ctlopy  <= y_ad ;
-  			ctlalu  <= a_seq ;
-                           if NOT frz then
-                                   wenable <= r_rd;
-                                   ctlrw   <= m_fetch;
-  			           ctladr  <= o_fetch ;
-                          else
-                                   wenable <= r_no;
-                                   ctlrw   <= m_no;
-			           ctladr  <= o_no;
-                          end if;
- 
--- ***********************************************************************
-
-		when sne =>
-                   if frz then EF <= sne;
-                   else
-			if rqs then EF <= irq;
-					else EF <= init	;	end if;	
-                    end if;
-
-	-- mins SNE produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0' ;
-  			priv     <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_rs ;
-  			ctlopy  <= y_ad ;
-  			ctlalu  <= a_sne ;
-                           if NOT frz then
-                                   wenable <= r_rd;
-                                   ctlrw   <= m_fetch;
-  			           ctladr  <= o_fetch ;
-                          else
-                                   wenable <= r_no;
-                                   ctlrw   <= m_no;
-			           ctladr  <= o_no;
-                          end if;
-
-  			
--- ***********************************************************************
-
-		when sge =>
-                   if frz then EF <= sge;
-                   else
-			if rqs then EF <= irq;
-					else EF <= init	;	end if;	
-                    end if;
-
-	-- mins SGE produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0' ;
-  			priv     <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_rs ;
-  			ctlopy  <= y_ad ;
-  			ctlalu  <= a_sge ;
-                           if NOT frz then
-                                   wenable <= r_rd;
-                                   ctlrw   <= m_fetch;
-  			           ctladr  <= o_fetch ;
-                          else
-                                   wenable <= r_no;
-                                   ctlrw   <= m_no;
-			           ctladr  <= o_no;
-                          end if;
-
--- ***********************************************************************
-
-		when sle =>
-                   if frz then EF <= sle;
-                   else
-			if rqs then EF <= irq;
-					else EF <= init	;	end if;	
-                    end if;
-
-	-- mins SLE produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0' ;
-  			priv     <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_rs ;
-  			ctlopy  <= y_ad ;
-  			ctlalu  <= a_sle ;
-                           if NOT frz then
-                                   wenable <= r_rd;
-                                   ctlrw   <= m_fetch;
-  			           ctladr  <= o_fetch ;
-                          else
-                                   wenable <= r_no;
-                                   ctlrw   <= m_no;
-			           ctladr  <= o_no;
-                          end if;
-
-  			
--- ***********************************************************************
-
-		when sgt =>
-                   if frz then EF <= sgt;
-                   else
-			if rqs then EF <= irq;
-					else EF <= init	;	end if;	
-                    end if;
-
-	-- mins SGT produit les signaux suivants :
-  			ovr_en  <= '0'  ;
-  			ico     <= '0' ;
-  			priv     <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_rs ;
-  			ctlopy  <= y_ad ;
-  			ctlalu  <= a_sgt ;
-                           if NOT frz then
-                                   wenable <= r_rd;
-                                   ctlrw   <= m_fetch;
-  			           ctladr  <= o_fetch ;
-                          else
-                                   wenable <= r_no;
-                                   ctlrw   <= m_no;
-			           ctladr  <= o_no;
-                          end if;
-
-  			
--- ***********************************************************************
-
-		when slt =>
-                   if frz then EF <= slt;
-                   else
-			if rqs then EF <= irq;
-					else EF <= init	;	end if;	
-                    end if;
-
-	-- mins SLT produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0' ;
-  			priv     <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_rs ;
-  			ctlopy  <= y_ad ;
-  			ctlalu  <= a_slt ;
-                           if NOT frz then
-                                   wenable <= r_rd;
-                                   ctlrw   <= m_fetch;
-  			           ctladr  <= o_fetch ;
-                          else
-                                   wenable <= r_no;
-                                   ctlrw   <= m_no;
-			           ctladr  <= o_no;
-                          end if;
-
--- ***********************************************************************
-
-		when bnez =>
-                   if frz then EF <= bnez;
-                   else
-			if resnul='0' then EF <= branch ;	end if;	
-			if resnul='1' then EF <= ifetch ;	end if;	
-                    end if;
-
-	-- mins BNEZ produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0' ;
-  			priv     <= '0' ;
-  			iformt <= '1';	
-  			riformt <= '0';	
-  			ctlopx  <= x_rs ;
-  			ctlopy  <= y_c0 ;
-  			ctlalu  <= a_sum ;
-                        wenable <= r_no;
-                        ctlrw   <= m_no;
-			ctladr  <= o_no;
-
--- ***********************************************************************
-
-		when beqz =>
-                   if frz then EF <= beqz;
-                   else
-			if resnul='1' then EF <= branch ;	end if;	
-			if resnul='0' then EF <= ifetch ;	end if;	
-                    end if;
-
-	-- mins BEQZ produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0' ;
-  			priv     <= '0' ;
-  			iformt <= '1';	
-  			riformt <= '0';	
-  			ctlopx  <= x_rs ;
-  			ctlopy  <= y_c0 ;
-  			ctlalu  <= a_sum ;
-                        wenable <= r_no;
-                        ctlrw   <= m_no;
-			ctladr  <= o_no;
-
--- ***********************************************************************
-
-		when branch =>
-                   if frz then EF <= branch;
-                   else
-			EF <= ifetch	;
-                    end if;
-
-	-- mins BRANCH produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0';
-  			priv     <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_pc ;
-  			ctlopy  <= y_i18 ;
-  			ctlalu  <= a_sum ;
-                        ctlrw   <= m_no;
-			ctladr  <= o_no;
-                           if NOT frz then
-                                   wenable <= r_pc;
-                          else
-                                   wenable <= r_no;
-                          end if;
-
-  			
--- ***********************************************************************
-
-		when jal =>
-                   if frz then EF <= jal;
-                   else
-			EF <= j	;
-                    end if;
-
-	-- mins JAL produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0' ;
-  			priv     <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_pc ;
-  			ctlopy  <= y_c0 ;
-  			ctlalu  <= a_sum ;
-                        ctlrw   <= m_no;
-			ctladr  <= o_no;
-                           if NOT frz then
-                                   wenable <= r_r31;
-                          else
-                                   wenable <= r_no;
-                          end if;
-
--- ***********************************************************************
-
-		when j =>
-                   if frz then EF <= j;
-                   else
-			EF <= ifetch	;
-                    end if;
-
-	-- mins J produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0' ;
-  			priv     <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_pc ;
-  			ctlopy  <= y_i28 ;
-  			ctlalu  <= a_sum ;
-                        ctlrw   <= m_no;
-			ctladr  <= o_no;
-                           if NOT frz then
-                                   wenable <= r_pc;
-                          else
-                                   wenable <= r_no;
-                          end if;
-
-  			
--- ***********************************************************************
-
-		when jalr =>
-                   if frz then EF <= jalr;
-                   else
-			EF <= jr ;
-                    end if;
-
-	-- mins JALR produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0' ;
-  			priv     <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_pc ;
-  			ctlopy  <= y_c0 ;
-  			ctlalu  <= a_sum ;
-                        ctlrw   <= m_no;
-			ctladr  <= o_no;
-                            if NOT frz then
-                                   wenable <= r_r31;
-                          else
-                                   wenable <= r_no;
-                          end if;
-
-  			
--- ***********************************************************************
-
-		when jr =>
-                   if frz then EF <= jr;
-                   else
-			EF <= ifetch	;
-                    end if;
-
-	-- mins JR produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0' ;
-  			priv     <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_rs ;
-  			ctlopy  <= y_c0 ;
-  			ctlalu  <= a_sum ;
-                        ctlrw   <= m_no;
-			ctladr  <= o_no;
-                           if NOT frz then
-                                   wenable <= r_pc;
-                          else
-                                   wenable <= r_no;
-                          end if;
-
--- ***********************************************************************
-
-		when rfe =>
-                   if frz then EF <= rfe;
-                   else
-			EF <= sr16r	;
-                    end if;
-
-	-- mins RFE produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0' ;
-  			priv    <= '1' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_iar ;
-  			ctlopy  <= y_c0 ;
-  			ctlalu  <= a_sum ;
-                        ctlrw   <= m_no;
-			ctladr  <= o_no;
-                           if NOT frz then
-                                   wenable <= r_pc;
-                          else
-                                   wenable <= r_no;
-                          end if;
-
--- ***********************************************************************
-
-		when sr16r =>
-                   if frz then EF <= sr16r;
-                   else
-			EF <= ifetch	;
-                    end if;
-
-	-- mins SR16R produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0';
-  			priv     <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_sr ;
-  			ctlopy  <= y_c16 ;
-  			ctlalu  <= a_srl ;
-                        ctlrw   <= m_no;
-			ctladr  <= o_no;
-                           if NOT frz then
-                                   wenable <= r_sr;
-                          else
-                                   wenable <= r_no;
-                          end if;
-
--- ***********************************************************************
-
-		when trap =>
-                   if frz then EF <= trap;
-                   else
-			EF <= irq	;
-                    end if;
-
-	-- mins TRAP produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0' ;
-  			priv     <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_c0 ;
-  			ctlopy  <= y_i28 ;
-  			ctlalu  <= a_sum ;
-                        ctlrw   <= m_no;
-			ctladr  <= o_no;
-                           if NOT frz then
-                                   wenable <= r_tvr;
-                          else
-                                   wenable <= r_no;
-                          end if;
-
--- ***********************************************************************
-
-		when s2i =>
-                   if frz then EF <= s2i;
-                   else
-			if ir_sr 	then EF <= sr2i	 ;	end if;	
-			if ir_tvr 	then EF <= tvr2i ;	end if;	
-			if ir_iar 	then EF <= iar2i ;	end if;	
-                    end if;
-
-	-- mins S2I produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0' ;
-  			priv    <= '1' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_c0 ;
-  			ctlopy  <= y_c0 ;
-  			ctlalu  <= a_sum ;
-                        ctlrw   <= m_no;
-			ctladr  <= o_no;
-                        wenable <= r_no;
-     
--- ***********************************************************************
-
-		when i2s =>
-                   if frz then EF <= i2s;
-                   else
-			if ir_sr 	then EF <= i2sr	 ;	end if;	
-			if ir_tvr 	then EF <= i2tvr ;	end if;	
-			if ir_iar 	then EF <= i2iar ;	end if;	
-                    end if;
-
-	-- mins I2S produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0' ;
-  			priv    <= '1' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_c0 ;
-  			ctlopy  <= y_c0 ;
-  			ctlalu  <= a_sum ;
-                        ctlrw   <= m_no;
-			ctladr  <= o_no;
-                        wenable <= r_no;
-     
--- ***********************************************************************
-
-		when sr2i =>
-                   if frz then EF <= sr2i;
-                   else
-			if rqs then EF <= irq;
-					else EF <= init	;	end if;	
-                    end if;
-
-	-- mins SR2I produit les signaux suivants :
-  			ovr_en  <= '0'  ;
-  			ico     <= '0' ;
-  			priv     <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_sr ;
-  			ctlopy  <= y_c0 ;
-  			ctlalu  <= a_sum ;
-                            if NOT frz then
-                                   wenable <= r_rd;
-                                   ctlrw   <= m_fetch;
-  			           ctladr  <= o_fetch ;
-                          else
-                                   wenable <= r_no;
-                                   ctlrw   <= m_no;
-			           ctladr  <= o_no;
-                          end if;
-
--- ***********************************************************************
-
-		when i2sr =>
-                   if frz then EF <= i2sr;
-                   else
-			if rqs then EF <= irq;
-					else EF <= init	;	end if;	
-                    end if;
-
-	-- mins I2SR produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0' ;
-  			priv    <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_rs ;
-  			ctlopy  <= y_c0 ;
-  			ctlalu  <= a_sum ;
-                           if NOT frz then
-                                   wenable <= r_sr;
-                                   ctlrw   <= m_fetch;
-  			           ctladr  <= o_fetch ;
-                          else
-                                   wenable <= r_no;
-                                   ctlrw   <= m_no;
-			           ctladr  <= o_no;
-                          end if;
-
--- ***********************************************************************
-
-		when tvr2i =>
-                   if frz then EF <= tvr2i;
-                   else
-			if rqs then EF <= irq;
-					else EF <= init	;	end if;	
-                    end if;
-
-	-- mins TVR2I produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0' ;
-  			priv    <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_tvr ;
-  			ctlopy  <= y_c0 ;
-  			ctlalu  <= a_sum ;
-                            if NOT frz then
-                                   wenable <= r_rd;
-                                   ctlrw   <= m_fetch;
-  			           ctladr  <= o_fetch ;
-                          else
-                                   wenable <= r_no;
-                                   ctlrw   <= m_no;
-			           ctladr  <= o_no;
-                          end if;
-
--- ***********************************************************************
-
-		when i2tvr =>
-                   if frz then EF <= i2tvr;
-                   else
-			if rqs then EF <= irq;
-					else EF <= init	;	end if;	
-                    end if;
-
-	-- mins I2TVR produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0' ;
-  			priv    <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_rs ;
-  			ctlopy  <= y_c0 ;
-  			ctlalu  <= a_sum ;
-                            if NOT frz then
-                                   wenable <= r_tvr;
-                                   ctlrw   <= m_fetch;
-  			           ctladr  <= o_fetch ;
-                          else
-                                   wenable <= r_no;
-                                   ctlrw   <= m_no;
-			           ctladr  <= o_no;
-                          end if;
-
--- ***********************************************************************
-
-		when i2iar =>
-                   if frz then EF <= i2iar;
-                   else
-			if rqs then EF <= irq;
-					else EF <= init	;	end if;	
-                    end if;
-
-	-- mins I2IAR produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0' ;
-  			priv    <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_rs ;
-  			ctlopy  <= y_c0 ;
-  			ctlalu  <= a_sum ;
-                            if NOT frz then
-                                   wenable <= r_iar;
-                                   ctlrw   <= m_fetch;
-  			           ctladr  <= o_fetch ;
-                          else
-                                   wenable <= r_no;
-                                   ctlrw   <= m_no;
-			           ctladr  <= o_no;
-                          end if;
-
--- ***********************************************************************
-
-		when iar2i =>
-                   if frz then EF <= iar2i;
-                   else
-			if rqs then EF <= irq;
-					else EF <= init	;	end if;	
-                    end if;
-
-	-- mins IAR2I produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0' ;
-  			priv    <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_iar;
-  			ctlopy  <= y_c0 ;
-  			ctlalu  <= a_sum ;
-                           if NOT frz then
-                                   wenable <= r_rd;
-                                   ctlrw   <= m_fetch;
-  			           ctladr  <= o_fetch ;
-                          else
-                                   wenable <= r_no;
-                                   ctlrw   <= m_no;
-			           ctladr  <= o_no;
-                          end if;
-
--- ***********************************************************************
-
-		when adr =>
-                   if frz then EF <= adr;
-                   else
-			if ir_opcod = lw_i 	then EF <= lw	;	end if;	
-			if ir_opcod = lbu_i 	then EF <= lbu	;	end if;	
-			if ir_opcod = sw_i 	then EF <= sw	;	end if;	
-			if ir_opcod = sb_i	then EF <= sb	;	end if;	
-                    end if;
-
-	-- mins ADR produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0' ;
-  			priv    <= '0' ;
-  			iformt <= '1';	
-  			riformt <= '0';	
-  			ctlopx  <= x_rs ;
-  			ctlopy  <= y_i16 ;
-  			ctlalu  <= a_sum ;
-                        ctlrw   <= m_no;
-			ctladr  <= o_no;
-                            if NOT frz then
-                                   wenable <= r_ad;
-                          else
-                                   wenable <= r_no;
-                          end if;
-     
--- ***********************************************************************
-
-		when lw =>
-                   if frz then EF <= lw;
-                   else
-			EF <= lw2 ;
-                    end if;
-
-	-- mins LW produit les signaux suivants :
-  			ovr_en  <=  '0';
-  			ico     <=  '0';
-  			priv    <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <=  x_c0;
-  			ctlopy  <=  y_c0;
-  			ctlalu  <=  a_sum;
-                        wenable <= r_no;
-                            if NOT frz then
-                                   ctlrw   <= m_rw;
-			           ctladr  <= o_rw;
-                          else
-                                   ctlrw   <= m_no;
-			           ctladr  <= o_no;
-                          end if;
-
--- ***********************************************************************
-
-		when lw2 =>
-                   if frz then EF <= lw2;
-                   else
-			if rqs then EF <= irq;
-					else EF <= init	;	end if;	
-                    end if;
-
-	-- mins LW2 produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0' ;
-  			priv    <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_c0 ;
-  			ctlopy  <= y_dt ;
-  			ctlalu  <= a_sum ;
-                           if NOT frz then
-                                   wenable <= r_rd;
-                                   ctlrw   <= m_fetch;
-  			           ctladr  <= o_fetch ;
-                          else
-                                   wenable <= r_no;
-                                   ctlrw   <= m_no;
-			           ctladr  <= o_no;
-                          end if;
-
--- ***********************************************************************
-
-		when lbu =>
-                   if frz then EF <= lbu;
-                   else
-			EF <= lbu2 ;
-                    end if;
-
-	-- mins LBU produit les signaux suivants :
-  			ovr_en  <=  '0';
-  			ico     <=  '0';
-  			priv    <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <=  x_c0;
-  			ctlopy  <=  y_c0;
-  			ctlalu  <=  a_sum;
-                        wenable <= r_no;
-                           if NOT frz then
-                                   ctlrw   <= m_rb;
-			           ctladr  <= o_rb;
-                          else
-                                   ctlrw   <= m_no;
-			           ctladr  <= o_no;
-                          end if;
-
--- ***********************************************************************
-
-		when lbu2 =>
-
-                   if frz then EF <= lbu2;
-                   else
-			if rqs then EF <= irq;
-					else EF <= init	;	end if;	
-                    end if;
-
-	-- mins LBU2 produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0' ;
-  			priv    <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_cb ;
-  			ctlopy  <= y_dt ;
-  			ctlalu  <= a_and ;
-                           if NOT frz then
-                                   wenable <= r_rd;
-                                   ctlrw   <= m_fetch;
-  			           ctladr  <= o_fetch ;
-                          else
-                                   wenable <= r_no;
-                                   ctlrw   <= m_no;
-			           ctladr  <= o_no;
-                          end if;
-
--- ***********************************************************************
-
-		when sw =>
-                   if frz then EF <= sw;
-                   else
-			EF <= ifetch	;
-                    end if;
-
-	-- mins SW produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0';
-  			priv    <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_rt ;
-  			ctlopy  <= y_c0 ;
-  			ctlalu  <= a_sum ;
-                        wenable <= r_no;
-                           if NOT frz then
-                                   ctlrw   <= m_ww;
-			           ctladr  <= o_ww;
-                          else
-                                   ctlrw   <= m_no;
-			           ctladr  <= o_no;
-                          end if;
-
--- ***********************************************************************
-
-		when sb =>
-                   if frz then EF <= sb;
-                   else
-			EF <= ifetch	;
-                    end if;
-
-	-- mins SB produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0';
-  			priv    <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_rt ;
-  			ctlopy  <= y_c0 ;
-  			ctlalu  <= a_sum ;
-                        wenable <= r_no;
-                           if NOT frz then
-                                   ctlrw   <= m_wb;
-			           ctladr  <= o_wb;
-                          else
-                                   ctlrw   <= m_no;
-			           ctladr  <= o_no;
-                          end if;
-
--- ***********************************************************************
-
---		when ico1 =>
- --                  if frz then EF <= ico1;
-  --                 else
---			EF <= ico2;
- --                   end if;
---
-	-- mins ICO produit les signaux suivants :
- -- 			ovr_en  <= '0' ;
-  --			ico     <= '0' ;
-  --			priv    <= '0' ;
-  --			iformt <= '0';	
-  --			riformt <= '0';	
-  --			ctlopx  <= x_pc ;
-  --			ctlopy  <= y_c4 ;
-  --			ctlalu  <= a_dif ;
-  --			ctlrw   <= m_no ;
---			ctladr  <= o_no;
- --                         if frz='0' then 
-  --			        wenable <= r_pc ;
-   --                       else 
-  --			        wenable <=  r_no;
-   --                       end if;
-
-  			
--- ***********************************************************************
-
-		when ico1 =>
-                   if frz then EF <= ico1;
-                   else
-			EF <= irq;
-                    end if;
-
-	-- mins ICO produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '1' ;
-  			priv    <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_c0 ;
-  			ctlopy  <= y_c0 ;
-  			ctlalu  <= a_sum ;
-  			ctlrw   <= m_no ;
-			ctladr  <= o_no;
-  		        wenable <= r_no;
-
-  			
--- ***********************************************************************
-
-		when irq =>
-                   if frz then EF <= irq;
-                   else
-			EF <= sr16l;
-                    end if;
-
-	-- mins IRQ produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0' ;
-  			priv    <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_pc ;
-  			ctlopy  <= y_c0 ;
-  			ctlalu  <= a_sum ;
-  			ctlrw   <= m_no ;
-			ctladr  <= o_no;
-                          if frz='0' then 
-  			        wenable <= r_siar ;
-                          else 
-  			        wenable <=  r_no;
-                          end if;
-
-  			
--- ***********************************************************************
-
-		when sr16l =>
-                   if frz then EF <= sr16l;
-                   else
-			EF <= pct ;
-                    end if;
-
-	-- mins SR16L produit les signaux suivants :
-  			ovr_en  <=  '0';
-  			ico     <=  '0';
-  			priv    <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <= x_sr ;
-  			ctlopy  <= y_c16 ;
-  			ctlalu  <= a_sll ;
-  			ctlrw   <= m_no ;
-			ctladr  <= o_no;
-                            if NOT frz then
-                                   wenable <= r_ssr;
-                          else
-                                   wenable <= r_no;
-                          end if;
-
--- ***********************************************************************
-
-		when pct =>
-                   if frz then EF <= pct;
-                   else
-			EF <= ifetch ;
-                    end if;
-
-	-- mins PCT produit les signaux suivants :
-  			ovr_en  <= '0' ;
-  			ico     <= '0';
-  			priv    <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <=  x_c0;
-  			ctlopy  <=  y_c16;
-  			ctlalu  <=  a_dif;
-  			ctlrw   <= m_no ;
-			ctladr  <= o_no;
-                            if NOT frz then
-                                   wenable <= r_pc;
-                          else
-                                   wenable <= r_no;
-                          end if;
-
--- ***********************************************************************
-
-		when ifetch =>
-                   if frz then EF <= ifetch;
-                   else
-			if rqs then EF <= irq;
-					else EF <= init	;	end if;	
-                    end if;
-
-	-- mins IFETCH produit les signaux suivants :
-  			ovr_en  <=  '0';
-  			ico     <=  '0';
-  			priv    <= '0' ;
-  			iformt <= '0';	
-  			riformt <= '0';	
-  			ctlopx  <=  x_c0;
-  			ctlopy  <=  y_c0 ;
-  			ctlalu  <=  a_sum ;
-                        wenable <= r_no;
-                           if NOT frz then
-                                   ctlrw   <= m_fetch;
-  			           ctladr  <= o_fetch ;
-                          else
-                                   ctlrw   <= m_no;
-			           ctladr  <= o_no;
-                          end if;
-  			
-	end case;
-
-	end if;			-- end if of reset = '1'
-
-	end process;
-
-  process (ck)
-  begin
-
-    if (ck = '0' and not ck'stable) then
-      EP <= EF;
-    end if;
-
-  end process;
-
-end STATE_MACHINE;
diff --git a/alliance/share/tutorials/dlxm/dlxm_sts.vbe b/alliance/share/tutorials/dlxm/dlxm_sts.vbe
deleted file mode 100644
index 6037ffb7..00000000
--- a/alliance/share/tutorials/dlxm/dlxm_sts.vbe
+++ /dev/null
@@ -1,567 +0,0 @@
-
--- ### -------------------------------------------------------------- ###
--- #									#
--- # file	: dlxm_sts.vbe						#
--- # date	: Febuary 1995						#
--- # version	: v0.0							#
--- #									#
--- # origin	: this description has been developed by CAO-VLSI team	#
--- #		  at MASI laboratory, University Pierre et Marie Curie	#
--- #		  URA CNRS 818, Institut Blaise Pascal			#
--- #		  4 Place Jussieu 75252 Paris Cedex 05 - France		#
--- # E-mail      :      cao-vlsi@masi.ibp.fr                            #
--- #									#
--- # descr.	: Behavioural description for status and interrupts	#
--- #		  New register cpurst_r					#
--- # 		  output control to tristate pads 2*16			#
--- #									#
--- ### -------------------------------------------------------------- ###
-
---
---  order of the registers in the scan-path 
---
---    OVR
---    ICO
---    DAV
---    IAV
---    IT0
---    IT1
---    IT2
---    IT3
---    FREEZE
---    RESET
---    CPURST
---    IFORMT
---
---
--------------------------------------------------------
-
-ENTITY dlxm_sts IS
-  PORT( ck          : IN  BIT ;                      -- clock
-        frz         : IN  BIT ;                      -- external freeze
-        reset       : IN  BIT ;                      -- external reset 
-        test        : IN  BIT ;                      -- test mode 
-
-        ctlalu      : IN  BIT_VECTOR(4 DOWNTO 0) ;   -- ALU operations
-        opx_sign    : IN  BIT ;                      -- operdan's signs and 
-        opy_sign    : IN  BIT ;                      -- result sign to
-        alu_sign    : IN  BIT ;                      -- check the
-        alu_nul     : IN  BIT ;                      -- alu result
-
-        alu_c31     : IN  BIT ;                      -- carry 31 and carry 30 to 
-        alu_c30     : IN  BIT ;                      -- compute ovr
-
-        ovr_en      : IN  BIT ;                      -- ovr computation enable 
-        ico         : IN  BIT ;                      -- illegal OPCOD
-        priv        : IN  BIT ;                      -- privileged instruction 
-        iformt      : IN  BIT ;                      -- instruction format i
-        riformt     : IN  BIT ;                      -- reset iformat 
-
-        rs          : IN  BIT_VECTOR(4 DOWNTO 0);    -- register RS
-        rd          : IN  BIT_VECTOR(4 DOWNTO 0);    -- register RD
-        rdrt        : IN  BIT_VECTOR(4 DOWNTO 0);    -- register RD or RT
-        mxrs_rdrt   : IN  BIT ;                      -- RD or RT  selection 
-
-	wenable_in  : IN  BIT_VECTOR(8 DOWNTO 0) ;   -- wenable from sequencer
-        ctlrw_in    : IN  BIT_VECTOR(3 DOWNTO 0) ;   -- MEM from SEQ
-
-        sr_mode     : IN  BIT ;                      -- mode 1-user 0-superuser
-        sr_mask     : IN  BIT ;                      -- interrupt mask
-        adr0        : IN  BIT ;                      -- adr(0)
-        adr1        : IN  BIT ;                      -- adr(1)
-        adr31       : IN  BIT ;                      -- adr(31)
-
-        intrqs      : IN  BIT_VECTOR(3 DOWNTO 0) ;   --  external interrupts
-
-        scin        : IN  BIT ;                      -- seq_scout
-
-        alu_test    : OUT BIT ;                      -- check the alu result
-
-        redpnt      : OUT BIT_VECTOR(4 DOWNTO 0) ;   -- read register
-        wrtpnt      : OUT BIT_VECTOR(4 DOWNTO 0) ;   -- write register 
-
-	wenable_out : OUT BIT_VECTOR(5 DOWNTO 0) ;   -- wenable to datapath
-        ctlrw_out   : OUT BIT_VECTOR(3 DOWNTO 2) ;   -- ctlrw to datapath
-
-        sr_ovr      : OUT BIT ;                      -- exception's flags
-        sr_dav      : OUT BIT ;
-        sr_iav      : OUT BIT ;
-        sr_ico      : OUT BIT ;
-        sr_it0      : OUT BIT ;                      -- interrupt's flags
-        sr_it1      : OUT BIT ;
-        sr_it2      : OUT BIT ;
-        sr_it3      : OUT BIT ;
-        sr_cpurst   : OUT BIT ;                      -- cpureset flag to dpt 
-
-	sts_reset   : OUT BIT ;			     -- reset flag to seq	
-
-        rqs         : OUT BIT ;                      -- request to SEQ 
-
-        rw          : OUT BIT ;                      -- ext read write
-        rw_ctl      : OUT BIT_VECTOR(15 DOWNTO 0) ;  -- inout data ctl
-        frz_ctl     : OUT BIT_VECTOR(15 DOWNTO 0) ;  -- out address ctl
-
-        byte        : OUT BIT_VECTOR(0 to 3) ;       -- ext byte
-        scout       : OUT BIT ;                      -- scout ext
-
-        zero        : OUT BIT ;                      -- zero ext
-        vdd         : IN  BIT ;
-        vss         : IN  BIT );
-
-END dlxm_sts;
-
-ARCHITECTURE behavioural of dlxm_sts is
-
-  -- 'freezed' clock
-
-  SIGNAL ckfrz_s                    : BIT;
-
-  -- signals to alu_test output
-
-  SIGNAL seq_s                      : BIT;
-  SIGNAL sne_s                      : BIT;
-  SIGNAL sgt_s                      : BIT;
-  SIGNAL slt_s                      : BIT;
-  SIGNAL sge_s                      : BIT;
-  SIGNAL sle_s                      : BIT;
-
-
-  -- exceptions
-
-  --SIGNAL unkopc_s                   : BIT;
-  --SIGNaL prvins_s                   : BIT;
-  SIGNAL ovr_s                      : BIT;
-  SIGNAL illins_s                   : BIT;
-  SIGNAL opviol_s                   : BIT;
-  SIGNAL iaalgn_s                   : BIT;
-  SIGNAL iasgmt_s                   : BIT;
-  SIGNAL daalgn_s                   : BIT;
-  SIGNAL dasgmt_s                   : BIT;
-  SIGNAL dasgmt_en                  : BIT;
-  SIGNAL daalgn_en                  : BIT;
-  SIGNAL iav_en                     : BIT;
-  SIGNAL ovr_x                      : BIT;
-  SIGNAL ico_x                      : BIT;
-  SIGNAL dav_x                      : BIT;
-  SIGNAL iav_x                      : BIT;
-  SIGNAL ovrreg_x                   : BIT;
-  SIGNAL icoreg_x                   : BIT;
-  SIGNAL davreg_x                   : BIT;
-  SIGNAL iavreg_x                   : BIT;
-  SIGNAL ovr_r                      : REG_BIT REGISTER;
-  SIGNAL ico_r                      : REG_BIT REGISTER;
-  SIGNAL dav_r                      : REG_BIT REGISTER;
-  SIGNAL iav_r                      : REG_BIT REGISTER;
-
-  -- interrupts
-
-  SIGNAL it0_s                      : BIT;
-  SIGNAL it1_s                      : BIT;
-  SIGNAL it2_s                      : BIT;
-  SIGNAL it3_s                      : BIT;
-  SIGNAL it0_r                      : REG_BIT REGISTER;
-  SIGNAL it1_r                      : REG_BIT REGISTER;
-  SIGNAL it2_r                      : REG_BIT REGISTER;
-  SIGNAL it3_r                      : REG_BIT REGISTER;
-
-  --  freeze and reset
-
-  SIGNAL reset_s                    : BIT;
-  SIGNAL freeze_s                   : BIT;
-  SIGNAL reset_r                    : REG_BIT REGISTER;
-  SIGNAL freeze_r                   : REG_BIT REGISTER;
-  SIGNAL cpurst_r		    : REG_BIT REGISTER;
-  SIGNAL cpurst_s		    : BIT;
-
-  -- interrupt and exception and reset request ...
-
-  SIGNAL intrqs_s                   : BIT;
-  SIGNAL excrqs_s                   : BIT;
-
-  --  byte
-
-  SIGNAL byte_s                     : BIT_VECTOR( 0 to 3);
- 
-  SIGNAL iformt_r                   : REG_BIT REGISTER;
-  SIGNAL iformt_x                : BIT ;
-
-  -- Inout data and out address control
-
-  SIGNAL  rw_ctl_n			: BIT;
-  SIGNAL  frz_ctl_n			: BIT;
-
-  CONSTANT add_i    : BIT_VECTOR (5 DOWNTO 0) := B"000_000"  ; -- add
-  CONSTANT addu_i   : BIT_VECTOR (5 DOWNTO 0) := B"000_001"  ; -- addu
-  CONSTANT sub_i    : BIT_VECTOR (5 DOWNTO 0) := B"000_010"  ; -- sub
-  CONSTANT subu_i   : BIT_VECTOR (5 DOWNTO 0) := B"000_011"  ; -- subu
-  CONSTANT addi_i   : BIT_VECTOR (5 DOWNTO 0) := B"000_100"  ; -- addi
-  CONSTANT addui_i  : BIT_VECTOR (5 DOWNTO 0) := B"000_101"  ; -- addui
-  CONSTANT subi_i   : BIT_VECTOR (5 DOWNTO 0) := B"000_110"  ; -- subi
-  CONSTANT subui_i  : BIT_VECTOR (5 DOWNTO 0) := B"000_111"  ; -- subui
-  CONSTANT sll_i    : BIT_VECTOR (5 DOWNTO 0) := B"001_000"  ; -- sll
-  CONSTANT srl_i    : BIT_VECTOR (5 DOWNTO 0) := B"001_001"  ; -- srl
-  CONSTANT sra_i    : BIT_VECTOR (5 DOWNTO 0) := B"001_010"  ; -- sra
-  CONSTANT slli_i   : BIT_VECTOR (5 DOWNTO 0) := B"001_100"  ; -- slli
-  CONSTANT srli_i   : BIT_VECTOR (5 DOWNTO 0) := B"001_101"  ; -- srli
-  CONSTANT srai_i   : BIT_VECTOR (5 DOWNTO 0) := B"001_110"  ; -- srai
-  CONSTANT lhi_i    : BIT_VECTOR (5 DOWNTO 0) := B"001_111"  ; -- lhi
-  CONSTANT seq_i    : BIT_VECTOR (5 DOWNTO 0) := B"010_000"  ; -- seq
-  CONSTANT sne_i    : BIT_VECTOR (5 DOWNTO 0) := B"010_001"  ; -- sne
-  CONSTANT sge_i    : BIT_VECTOR (5 DOWNTO 0) := B"010_010"  ; -- sge
-  CONSTANT sle_i    : BIT_VECTOR (5 DOWNTO 0) := B"010_011"  ; -- sle
-  CONSTANT seqi_i   : BIT_VECTOR (5 DOWNTO 0) := B"010_100"  ; -- seqi
-  CONSTANT snei_i   : BIT_VECTOR (5 DOWNTO 0) := B"010_101"  ; -- snei
-  CONSTANT sgei_i   : BIT_VECTOR (5 DOWNTO 0) := B"010_110"  ; -- sgei
-  CONSTANT slei_i   : BIT_VECTOR (5 DOWNTO 0) := B"010_111"  ; -- slei
-  CONSTANT sgt_i    : BIT_VECTOR (5 DOWNTO 0) := B"011_010"  ; -- sgt
-  CONSTANT slt_i    : BIT_VECTOR (5 DOWNTO 0) := B"011_011"  ; -- slt
-  CONSTANT sgti_i   : BIT_VECTOR (5 DOWNTO 0) := B"011_110"  ; -- sgti
-  CONSTANT slti_i   : BIT_VECTOR (5 DOWNTO 0) := B"011_111"  ; -- slti
-  CONSTANT and_i    : BIT_VECTOR (5 DOWNTO 0) := B"100_000"  ; -- and
-  CONSTANT or_i     : BIT_VECTOR (5 DOWNTO 0) := B"100_001"  ; -- or
-  CONSTANT xor_i    : BIT_VECTOR (5 DOWNTO 0) := B"100_011"  ; -- xor
-  CONSTANT andi_i   : BIT_VECTOR (5 DOWNTO 0) := B"100_100"  ; -- andi
-  CONSTANT ori_i    : BIT_VECTOR (5 DOWNTO 0) := B"100_101"  ; -- ori
-  CONSTANT xori_i   : BIT_VECTOR (5 DOWNTO 0) := B"100_111"  ; -- xori
-
-  CONSTANT sw_i     : BIT_VECTOR (5 DOWNTO 0) := B"101_000"  ; -- sw
-  CONSTANT sh_i     : BIT_VECTOR (5 DOWNTO 0) := B"101_001"  ; -- sh
-  CONSTANT sb_i     : BIT_VECTOR (5 DOWNTO 0) := B"101_010"  ; -- sb
-  CONSTANT lbu_i    : BIT_VECTOR (5 DOWNTO 0) := B"101_011"  ; -- lbu
-  CONSTANT lw_i     : BIT_VECTOR (5 DOWNTO 0) := B"101_100"  ; -- lw
-  CONSTANT lh_i     : BIT_VECTOR (5 DOWNTO 0) := B"101_101"  ; -- lh
-  CONSTANT lb_i     : BIT_VECTOR (5 DOWNTO 0) := B"101_110"  ; -- lb
-  CONSTANT lhu_i    : BIT_VECTOR (5 DOWNTO 0) := B"101_111"  ; -- lhu
-
-  CONSTANT jr_i     : BIT_VECTOR (5 DOWNTO 0) := B"110_000"  ; -- jr
-  CONSTANT jalr_i   : BIT_VECTOR (5 DOWNTO 0) := B"110_001"  ; -- jalr
-  CONSTANT movs2i_i : BIT_VECTOR (5 DOWNTO 0) := B"110_010"  ; -- movi2s
-  CONSTANT movi2s_i : BIT_VECTOR (5 DOWNTO 0) := B"110_011"  ; -- movs2i
-  CONSTANT beqz_i   : BIT_VECTOR (5 DOWNTO 0) := B"110_100"  ; -- beqz
-  CONSTANT bnez_i   : BIT_VECTOR (5 DOWNTO 0) := B"110_101"  ; -- bnez
-  CONSTANT j_i      : BIT_VECTOR (5 DOWNTO 0) := B"111_000"  ; -- j
-  CONSTANT jal_i    : BIT_VECTOR (5 DOWNTO 0) := B"111_001"  ; -- jal
-  CONSTANT rfe_i    : BIT_VECTOR (5 DOWNTO 0) := B"111_010"  ; -- rfe
-  CONSTANT trap_i   : BIT_VECTOR (5 DOWNTO 0) := B"111_011"  ; -- trap
-
-  -- Description of the memory access modes
-
-  CONSTANT m_no     : BIT_VECTOR (3 DOWNTO 0) := B"0001" ;
-  CONSTANT m_fetch  : BIT_VECTOR (3 DOWNTO 0) := B"1001" ;
-  CONSTANT m_rw     : BIT_VECTOR (3 DOWNTO 0) := B"0101" ;
-  CONSTANT m_ww     : BIT_VECTOR (3 DOWNTO 0) := B"0000" ;
-  CONSTANT m_rb     : BIT_VECTOR (3 DOWNTO 0) := B"0111" ;
-  CONSTANT m_wb     : BIT_VECTOR (3 DOWNTO 0) := B"0010" ;
-
-BEGIN
-
-  --  freezed clock
-
-  ckfrz_s <= ck AND NOT( frz );
-
-  -- alu_test
-
-  seq_s <= alu_nul;
-
-  sne_s <= NOT( seq_s );
-
-  sgt_s <= '1' WHEN (   ( opx_sign XOR opy_sign = '0' )
-                    AND ( alu_sign = '0' )
-                    AND ( seq_s    = '0' ) )              ELSE
-           '1' WHEN ( opx_sign = '0' AND opy_sign = '1' ) ELSE
-           '0';
-
-  slt_s <= NOT ( sge_s );
-
-  sge_s <= seq_s or sgt_s;
-
-  sle_s <= seq_s OR slt_s;
-
-  --  alu_test output
-
-      WITH ctlalu SELECT
-      alu_test <= NOT seq_s WHEN "00011",
-                  NOT sne_s WHEN "00101",
-                  NOT sge_s WHEN "00111",
-                  NOT sgt_s WHEN "01001",
-                  NOT sle_s WHEN "01011",
-                  NOT slt_s WHEN "01101",
-                  '1'   WHEN OTHERS;
-
-
-
-  --  register file addresses
-
-  redpnt <= rs WHEN mxrs_rdrt = '1' ELSE
-            rdrt;
-
-  wrtpnt <= B"11111" WHEN wenable_in( 3 )  = '1' ELSE
-            rdrt     WHEN iformt_r   = '1'         ELSE
-            rd;
-
-  --  wenable_out output
-
-  wenable_out <= wenable_in( 6 DOWNTO 4 ) & wenable_in( 2 DOWNTO 0 )
-                 WHEN ( excrqs_s = '0' OR wenable_in( 7 ) OR wenable_in( 8 ) ) ELSE
-                 "000000";
-
-  -- ctlrw_out output
-
-  ctlrw_out(3 DOWNTO 2 ) <= ctlrw_in( 3 DOWNTO 2 )
-                 WHEN ( excrqs_s = '0' OR wenable_in( 7 ) OR wenable_in( 8 ) ) ELSE
-                 "00";
-
-
-  -- exceptions
-
-  ovr_s     <= alu_c31 XOR alu_c30;
-  illins_s  <= ico;
-  opviol_s  <= sr_mode AND priv;
-  iaalgn_s  <= NOT( adr0 AND adr1 );
-  iasgmt_s  <= sr_mode AND NOT( adr31 );
-  daalgn_s  <= NOT( adr0 AND adr1 ) AND ctlrw_in( 1 ) = '0';
-  dasgmt_s  <= sr_mode AND NOT( adr31 );
-
-  daalgn_en <= ctlrw_in=m_rw OR ctlrw_in=m_ww;
-  dasgmt_en <= ctlrw_in=m_rw OR ctlrw_in=m_ww OR ctlrw_in=m_rb OR ctlrw_in=m_wb;
-  iav_en    <= ctlrw_in=m_fetch;
-
-  ovr_x     <=   ovr_s                  AND ovr_en;
-  ico_x     <= ( illins_s OR opviol_s );
-  dav_x     <= ( daalgn_s AND daalgn_en ) OR ( dasgmt_s AND dasgmt_en );
-  iav_x     <= ( iaalgn_s OR iasgmt_s ) AND iav_en;
-
-  -- exception signals for registers 
-
-  ovrreg_x  <= ovr_x OR ( ovr_r AND NOT( wenable_in( 7 ) ) );
-  icoreg_x  <= ico_x OR ( ico_r AND NOT( wenable_in( 7 ) ) );
-  davreg_x  <= dav_x OR ( dav_r AND NOT( wenable_in( 7 ) ) );
-  iavreg_x  <= iav_x OR ( iav_r AND NOT( wenable_in( 7 ) ) );
-
-  -- exception's registers 
-
-
-  ovr : BLOCK( ckfrz_s = '0' AND NOT ckfrz_s'STABLE )
-
-  BEGIN
-    ovr_r <= GUARDED ovrreg_x WHEN test = '0' ELSE scin;
-  END BLOCK;
-
-  ico : BLOCK( ckfrz_s = '0' AND NOT ckfrz_s'STABLE )
-
-  BEGIN
-    ico_r <= GUARDED icoreg_x WHEN test = '0' ELSE ovr_r;
-  END BLOCK;
-
-
-  dav : BLOCK( ckfrz_s = '0' AND NOT ckfrz_s'STABLE )
-
-  BEGIN
-    dav_r <= GUARDED davreg_x WHEN test = '0' ELSE ico_r;
-  END BLOCK;
-
-
-  iav : BLOCK( ckfrz_s = '0' AND NOT ckfrz_s'STABLE )
-
-  BEGIN
-    iav_r <= GUARDED iavreg_x WHEN test = '0' ELSE dav_r;
-  END BLOCK;
-
-  -- exception's output
-
-  sr_ovr  <= ovr_r;
-
-  sr_ico  <= ico_r;
-
-  sr_dav  <= dav_r;
-
-  sr_iav  <= iav_r;
-
-  -- interrupts
-
-  it0_s <= NOT( intrqs( 0 ) ) OR ( it0_r AND NOT( wenable_in( 7 ) ) );
-
-  it1_s <= NOT( intrqs( 1 ) ) OR ( it1_r AND NOT( wenable_in( 7 ) ) );
-
-  it2_s <= NOT( intrqs( 2 ) ) OR ( it2_r AND NOT( wenable_in( 7 ) ) );
-
-  it3_s <= NOT( intrqs( 3 ) ) OR ( it3_r AND NOT( wenable_in( 7 ) ) );
-
-  -- interrupt's  registers
-
-  it0 : BLOCK( ck = '0' AND NOT ck'STABLE )
-
-  BEGIN
-    it0_r <= GUARDED it0_s WHEN test = '0' ELSE iav_r;
-  END BLOCK;
-
-
-  it1 : BLOCK( ck = '0' AND NOT ck'STABLE )
-
-  BEGIN
-    it1_r <= GUARDED it1_s WHEN test = '0' ELSE it0_r;
-  END BLOCK;
-
-
-  it2 : BLOCK( ck = '0' AND NOT ck'STABLE )
-
-  BEGIN
-    it2_r <= GUARDED it2_s WHEN test = '0' ELSE it1_r;
-  END BLOCK;
-
-
-  it3 : BLOCK( ck = '0' AND NOT ck'STABLE )
-
-  BEGIN
-    it3_r <= GUARDED it3_s WHEN test = '0' ELSE it2_r;
-  END BLOCK;
-
-  -- interrupt's registers
-
-  sr_it0 <= it0_r;
-  sr_it1 <= it1_r;
-  sr_it2 <= it2_r;
-  sr_it3 <= it3_r;
-
-  --  freeze
-
-  frz : BLOCK( ck = '0' AND NOT ck'STABLE )
-
-  BEGIN
-    freeze_r <= GUARDED frz WHEN test = '0' ELSE it3_r;
-  END BLOCK;
-
-  --  freeze output
-
-  freeze_s <= frz AND freeze_r;
-
-  -- hardware reset
-
-  reset_s <= reset OR ( reset_r AND (frz));
-
-
-  rst : BLOCK( ck = '0' AND NOT ck'STABLE )
-
-  BEGIN
-  reset_r <= GUARDED reset_s WHEN test = '0' ELSE freeze_r;
-
-
-  END BLOCK;
-
-  -- reset output to sequencer
-
-  sts_reset <= reset_r;
-
-  -- cpureset 
-
-  cpurst_s <= reset_r OR ( cpurst_r AND NOT( wenable_in(7)) ) ;
-
-  cpu_reseted  : BLOCK( ckfrz_s = '0' AND NOT ckfrz_s'STABLE )
-
-  BEGIN
-	
-  cpurst_r <= GUARDED cpurst_s WHEN test='0' ELSE reset_r ;
-
-  END BLOCK;
-
-
-  -- cpureset output to datapath
-
-  sr_cpurst <= cpurst_r ;
- 
-  --  iformt
-  
-  iformt_x <= (iformt_r or iformt) and not (riformt);
- 
-  ift: BLOCK( ck = '0' AND NOT ck'STABLE)
-
-  BEGIN 
- 
-  iformt_r <= GUARDED iformt_x WHEN test = '0' ELSE cpurst_r;
-
-  END BLOCK;
-
-
-  --  rqs output 
-
-  intrqs_s <= ( it0_r OR it1_r OR it2_r OR it3_r ) AND sr_mask;
-
-  excrqs_s <= ovr_x OR ovr_r OR
-              ico_x OR ico_r OR
-              dav_x OR dav_r OR
-              iav_x OR iav_r;
-
-  rqs      <= cpurst_r OR excrqs_s OR intrqs_s;
-
-  -- rw, frz_ctl  and rw_ctl output
-
-  rw_ctl_n   <= ctlrw_in( 0 ) OR freeze_s OR NOT( CK ) OR test;
-
-  frz_ctl_n <= freeze_s OR test;
-
-  rw_ctl(15)	<= NOT rw_ctl_n ;
-  rw_ctl(14)	<= NOT rw_ctl_n ;
-  rw_ctl(13)	<= NOT rw_ctl_n ;
-  rw_ctl(12)	<= NOT rw_ctl_n ;
-  rw_ctl(11)	<= NOT rw_ctl_n ;
-  rw_ctl(10)	<= NOT rw_ctl_n ;
-  rw_ctl(9)	<= NOT rw_ctl_n ;
-  rw_ctl(8)	<= NOT rw_ctl_n ;
-  rw_ctl(7)	<= NOT rw_ctl_n ;
-  rw_ctl(6)	<= NOT rw_ctl_n ;
-  rw_ctl(5)	<= NOT rw_ctl_n ;
-  rw_ctl(4)	<= NOT rw_ctl_n ;
-  rw_ctl(3)	<= NOT rw_ctl_n ;
-  rw_ctl(2)	<= NOT rw_ctl_n ;
-  rw_ctl(1)	<= NOT rw_ctl_n ;
-  rw_ctl(0)	<= NOT rw_ctl_n ;
-
-  frz_ctl(15)	<= NOT frz_ctl_n ;
-  frz_ctl(14)	<= NOT frz_ctl_n ;
-  frz_ctl(13)	<= NOT frz_ctl_n ;
-  frz_ctl(12)	<= NOT frz_ctl_n ;
-  frz_ctl(11)	<= NOT frz_ctl_n ;
-  frz_ctl(10)	<= NOT frz_ctl_n ;
-  frz_ctl(9)	<= NOT frz_ctl_n ;
-  frz_ctl(8)	<= NOT frz_ctl_n ;
-  frz_ctl(7)	<= NOT frz_ctl_n ;
-  frz_ctl(6)	<= NOT frz_ctl_n ;
-  frz_ctl(5)	<= NOT frz_ctl_n ;
-  frz_ctl(4)	<= NOT frz_ctl_n ;
-  frz_ctl(3)	<= NOT frz_ctl_n ;
-  frz_ctl(2)	<= NOT frz_ctl_n ;
-  frz_ctl(1)	<= NOT frz_ctl_n ;
-  frz_ctl(0)	<= NOT frz_ctl_n ;
-
-  -- rw is not inverted
-
-  rw       <= ctlrw_in( 0 ) when reset='0' else '0';
-
-  -- byte
-  -- non inverted
-  -- adr1 et adr are inverted
-
-  byte_s  <= "1111" WHEN ( ctlrw_in=m_rw OR ctlrw_in=m_ww OR ctlrw_in=m_fetch ) ELSE
-             "1000" WHEN ( adr1&adr0= "11" AND ( ctlrw_in=m_rb OR ctlrw_in=m_wb ) ) ELSE
-
-             "0100" WHEN ( adr1&adr0= "10" AND ( ctlrw_in=m_rb OR ctlrw_in=m_wb ) ) ELSE
-
-             "0010" WHEN ( adr1&adr0= "01" AND ( ctlrw_in=m_rb OR ctlrw_in=m_wb ) ) ELSE
-
-             "0001" WHEN ( adr1&adr0= "00" AND ( ctlrw_in=m_rb OR ctlrw_in=m_wb ) ) ELSE
-
-             "0000" ;
-
-
-  byte   <= byte_s WHEN (excrqs_s = '0') ELSE
-            B"0000";
-
-  --  scout output ( non inverted )
-
-  scout <= iformt_r;
-
-  --  zero output
-
-  zero <= '0';
-
-END behavioural;
diff --git a/alliance/share/tutorials/dlxm/latex/Makefile b/alliance/share/tutorials/dlxm/latex/Makefile
deleted file mode 100644
index 215d6830..00000000
--- a/alliance/share/tutorials/dlxm/latex/Makefile
+++ /dev/null
@@ -1,21 +0,0 @@
-# Generic Makefile for TeTeX projet
-# (C) 1999, Czo
-# $Id: Makefile,v 1.1 2000/01/20 10:24:50 czo Exp $
-
-MYFILE=dlxm
-
-view : ps
-	gv $(MYFILE).ps
-        
-ps   : $(MYFILE).tex
-	latex $(MYFILE).tex
-	dvips $(MYFILE).dvi -o $(MYFILE).ps
-
-distrib : clean ps        
-	ps2pdf $(MYFILE).ps
-	cp -f $(MYFILE).ps ..
-	cp -f $(MYFILE).pdf ..
-	$(MAKE) clean
-
-clean :
-	rm -f $(MYFILE).ps $(MYFILE).pdf *.log *.dvi *.aux
diff --git a/alliance/share/tutorials/dlxm/latex/dlxm.tex b/alliance/share/tutorials/dlxm/latex/dlxm.tex
deleted file mode 100644
index b049094b..00000000
--- a/alliance/share/tutorials/dlxm/latex/dlxm.tex
+++ /dev/null
@@ -1,1153 +0,0 @@
-% Dlxm Tutorial
-% Modified by czo (01/2000)
-% TODO : change old tools names logic/bop netoptim/glop
-% $Id: dlxm.tex,v 1.1 2000/01/20 10:24:51 czo Exp $
-
-\documentstyle[palatino]{article} 
-\special{papersize=210mm,297mm}     % A4 paper is what my printer likes
-\textheight 9.0in
-\textwidth  7.0in
-\topmargin  -0.0in
-\oddsidemargin  +0in
-\evensidemargin -0in
-\marginparwidth +0in
-\parskip 8pt plus 2pt minus 2pt     % space beetween paragraphe
-\parindent 2em                      % indentation of the first line
-\topsep 0pt                         % space beetween list and text
-\parsep 6pt                         % space beetween 2 par. in item
-\partopsep 0pt                      % space beetween 2 par. in item
-\itemsep 0pt                        % space beetween 2 items
-\def\Sup{\verb+>+}
-\def\Inf{\verb+<+}
-\newlength{\mylength}
-\def\S#1{\protect\makebox[\mylength][l]{\noindent#1}}
-\begin{document} 
-
-
-\begin{center}
-{\Large \bf DLX TUTORIAL}\\
-\today \\
-This tutorial requires about 6 hours in batch mode on a Sparc Station
-\end{center}
-
-\section{Introduction}
-
-\hspace{\parindent}
- Welcome to the {\bf ALLIANCE CAD} system.
-This file contains a complete tutorial based on the design of the 32 bit microprocessor DLX.
-This tutorial does not focus on the processor architecture. The
-goal is to present the available CAD tools in the ALLIANCE 3.0 release (especially
-logic synthesis and the data path compiler).
-Beginners who are not familiar with ALLIANCE should start using the
-ADDACCU tutorial or the AMD tutorial.
-Each {\bf ALLIANCE} tool can operate as a standalone program but in this
-tutorial the tools are used according to a precise design flow.
-The starting point is a behavioural VHDL model. The output is a CIF file.
-
-The tools used in the design are:
-\begin {itemize}
-\item {\bf asimut} : {\bf VHDL} compiler and simulator.
-\item {\bf dlx\_asm} : DLX assembler.
-\item {\bf syf} : Finite State Machine compiler.
-\item {\bf logic} : Logic synthesizer
-\item {\bf netoptim} : Net list optimizer
-\item {\bf scr} : Standard Cell placer and router.
-\item {\bf fpgen} : Data path net list capture.
-\item {\bf dpr} : Data path placer and router.
-\item {\bf genlib} : Net list capture.
-\item {\bf bbr} : Block to block router.
-\item {\bf ring} : Core to pads router.
-\item {\bf lynx} : Layout to net list extractor.
-\item {\bf lvx} : Net list comparator.
-%\item {\bf tas} : Timing Analyser.
-\item {\bf s2r} : Symbolic to real layout converter.
-\end{itemize}
-
-You can get on-line information on any {\bf ALLIANCE} tool using the command :
-
-\fbox {
-\shortstack[l] {
-\bf man $<$tool name$>$
-}
-}
-
-DLXm is a 32 bit microprocessor with a micro-programmed internal architecture. The description of the DLX is given by J.L.Hennessy and D.A.Patterson in ``Computer Architecture, A quantitative Approach'', Morgan Kaufman Publishers, Inc. 1990.                                                            
-
-In order to simplify the task of validating the chip, an entire CPU board has been described in {\bf VHDL}. 
-
-Thus the simulations are done using small
-assembler programs which are stored in the CPU board's external memory.
-This tutorial shows you how to create the DLXm into four steps, 
-which must be followed in order to produce a valid chip.
-
-\begin {itemize}
-\item {\bf Step 1} : Behavioural Specification and Validation 
-\item {\bf Step 2} : Gate Level net list generation and validation 
-\item {\bf Step 3} : Physical place and route with extraction and validation 
-%\item {\bf Step 4} : Timing analysis
-\item {\bf Step 4} : Translation from symbolic layout to the target
-process
-\end{itemize}
-
-In order to build the chip, all source files are included with this tutorial (see Appendix).
-
-You will use the {\bf ALLIANCE} tools to validate these sources and to generate 
-first the gate level net list, then 
-the physical layout of the DLXm. The final output is a {\bf CIF} format physical layout file. This can be sent directly to a manufacturer for fabrication.
-
-All you have to do to build the chip is type the commands given in this tutorial. If you are feeling too lazy to type these commands by hand, you can build the entire chip automatically using the command :
-
-\fbox {
-\shortstack[l] {
-\bf $>$ make
-}
-}
-
-If you want to start again from scratch, you can type the command :
-
-\fbox {
-\shortstack[l] {
-\bf $>$ make clean
-}
-}
-
-which will remove all the generated files.
-
-The fully automatic chip generation requires about 6 hours on a SPARC station.
-If you have less time, you can also run separately the four main steps listed above, thanks to special entries in the makefile.
-These entries are referenced all along this tutorial.
-
-
-The {\bf ALLIANCE} tools use {\bf UNIX} environment variables. They are accessed by the {\bf UNIX} command {\em setenv}. For example:
-
-\fbox {
-\shortstack[l] {
-\bf $>$ setenv MBK\_IN\_LO vst\\
-\bf $>$ setenv MBK\_OUT\_LO vst\\
-\bf $>$ setenv MBK\_IN\_PH ap\\
-\bf $>$ setenv MBK\_OUT\_PH ap\\
-\bf $>$ setenv MBK\_WORK\_LIB .\\
-\bf $>$ setenv MBK\_CATAL\_NAME CATAL\\
-\bf $>$ setenv MBK\_CATA\_LIB \\
-\hspace*{0.2in}\bf \$(ALLIANCE\_TOP)/cells/scr:\\
-\hspace*{0.2in}\bf \$(ALLIANCE\_TOP)/cells/bsg:
-\$(ALLIANCE\_TOP)/cells/rfg:
-\$(ALLIANCE\_TOP)/cells/rsa:\\
-\hspace*{0.2 in}\bf  \$(ALLIANCE\_TOP)/cells/fitpath/fplib:\\
-\hspace*{0.2 in}\bf \$(ALLIANCE\_TOP)/cells/ring
-}
-}
-
-
-\begin{itemize}
-\item {\bf MBK\_IN\_LO}      : Logical input file format (and filename extension).
-\item {\bf MBK\_OUT\_LO}     : Logical output file format (and filename extension).
-\item {\bf MBK\_IN\_PH}      : Physical input file format (and filename extension).
-\item {\bf MBK\_OUT\_PH}     : Physical output file format (and filename extension).
-\item {\bf MBK\_CATAL\_NAME} : Name of the catalogue file in
-{\bf MBK\_WORK\_LIB} directory.
-\item {\bf MBK\_CATA\_LIB}   : Paths to the directories that are to be searched for read-only cell libraries.
-\item {\bf MBK\_WORK\_LIB}   : Directory where are saved the output files.
-\end{itemize}
-
-You can get on-line information on {\bf ALLIANCE } environment variables using the command :
-
-\fbox {
-\shortstack[l] {
-\bf man $<$ envir $>$
-}
-}
-
-Some of the path names may have to be modified, in order to correspond to your particular installation of {\bf ALLIANCE}. In this tutorial we will assume that the directory structure of the source files has not been altered.
-
-In this tutorial, the commands which are inside [ ] are preset. If you make the DLXm from the beginning to the end, you do not have to set again these environment variables.
-All operations should be executed in the root directory.
-
-
-
-
-\section{Simulation method for design validation}
-
-    \subsection{Behavioural model}
-
-The specification of the chip which you are going to build is given in
-the file {\bf dlxm\_chip.vbe} in the form of a {\bf VHDL} behavioural description. This allows simulations to be performed immediately.
-
-In order to simplify the task of validating the chip, an entire CPU board has been described in {\bf VHDL}. The CPU board interconnections are described in the file {\bf dlxm\_cpu.vst} using VHDL structural syntax. Each component is described in a separate file using VHDL behavioural syntax :
-
-\begin {itemize}
-\item {\bf dlxm\_dec.vbe} : Address decoder.
-\item {\bf sr64\_1a.vbe} : RAM.
-\item {\bf timer.vbe} : timer for external interrupts.
-\item {\bf roms.vbe} : Supervisor ROM.
-\item {\bf romu.vbe} : User ROM.
-\end{itemize}
-
-	\subsection{Validation Technique}
-
-In order to test the chip, a large number of short assembly language
-programs have been written. The programs were each designed to test
-one particular aspect of the chip (e.g. an instruction, or a
-register). Each works on the same principle: a test is performed, if
-test is OK, the program branches to a fixed address (defined as {\bf
-good}) and stops with the following message :\\
-{\bf ERROR : `` assert violation on cell dlxm\_dec : " ==== ok :
-simulation has ended with functional test good ===="\\}
-, if not, the program branches to another fixed address and stops with
-the following message :\\
-{\bf ERROR : `` assert violation on cell dlxm\_dec : " ==== ko :
-simulation has ended with functional test bad ===="\\}
-
-The programs are assembled using the command {\bf dlx\_asm}, which assembles the DLX mnemonics but, instead of generating object code as output, it generates the {\bf VHDL} behavioural description of a 256 byte ROM. It is therefore used to produce the {\bf romu.vbe} and {\bf roms.vbe} files for the board.
-
-
-
-    	\subsection{Simulation}
-
-
-The VHDL simulator {\bf asimut} can mix structural and behavioural descriptions :
-a special file,
-defined by the environment variable {\bf MBK\_CATAL\_NAME} (see {\em man catal}), tells the simulator which behavioural models are to be taken as leaf cells. 
-
-Simulation is used to check the initial behavioural description of the DLXm processor and the output results for each phase . 
- However as simulation is time greedy, simulation is done in the tutorial with a single assembly program, to show the design flow and the tools as quickly as possible.
-Yet the reader must feel free to use all the provided programs for simulation.
-
-
-\section{Interactive Design}
-
-	\subsection{Behavioural Specification}
-
-Before starting the chip design, remember that all operations should be executed in the root directory.
-
-
-The circuit behaviour is described in the *.vbe files using the {\bf ALLIANCE} VHDL subset (see {\it man vhdl} and {\it man vbe}). 
-
-The assembly language program add000.u is used. To assemble it, do :
-
-\fbox {
-\shortstack[l] {
-\bf $>$ setenv MBK\_WORK\_LIB .\\
-\bf $>$ dlx\_asm add000.u romu\\
-\bf $>$ dlx\_asm add000.s roms
-}
-}
-
-\begin{itemize}
-\item
-{\bf add000.u} and {\bf add000.s} are the chosen example of assembly
-source files.
-\item
-{\bf romu} and {\bf roms} are the target files ({\bf romu.vbe} and
-{\bf roms.vbe}).
-\end{itemize}
-
-You can now perform the simulation :
-
-\fbox {
-\shortstack[l] {
-\bf $>$ setenv VH\_BEHSFX vbe\\ 
-\bf $>$ setenv MBK\_MAXERR 10 \\ 
-\bf $>$ setenv VH\_PATSFX pat \\ 
-\bf $>$ setenv MBK\_IN\_LO vst \\ 
-\bf $>$ setenv MBK\_CATAL\_NAME CATAL\_CPU\_CHIP \\ 
-\bf [$>$ setenv MBK\_WORK\_LIB .]\\ 
-\bf $>$ setenv MBK\_CATA\_LIB \\ 
-\hspace*{0.2in}\bf \$(ALLIANCE\_TOP)/cells/scr:\\ 
-\hspace*{0.2in}\bf \$(ALLIANCE\_TOP)/cells/bsg: \$(ALLIANCE\_TOP)/cells/rfg: \$(ALLIANCE\_TOP)/cells/rsa:\\ 
-\hspace*{0.2 in}\bf  \$(ALLIANCE\_TOP)/cells/fitpath/fplib:./mclib:\\ 
-\hspace*{0.2 in}\bf \$(ALLIANCE\_TOP)/cells/ring\\ 
-\bf $>$ asimut -l 1 -p 50 -bdd dlxm\_cpu dlxm\_cpu add000\_chip
-} 
-} 
-
-\begin{itemize} 
-\item
-{\bf -l 1} : size of the label in the {\bf dlxm\_cpu.pat} and the {\bf
-add000\_chip.pat} files.
-\item 
-{\bf -p 50} : simulation will use sets of 50 patterns (see {\it man
-asimut})
-\item
-{\bf -bdd} : simulation uses bdd representation
-\item
-{\bf dlxm\_cpu} : structural description of the board  ({\bf dlxm\_cpu.vst}) 
-\item
-{\bf dlxm\_cpu} : pattern input filename ({\bf dlxm\_cpu.pat}) 
-\item
-{\bf add000\_chip} : result filename ({\bf add000\_chip.pat}) 
-\end{itemize}
-
-You should get the message : \\
-{\bf ERROR : `` assert violation on cell dlxm\_dec : " ==== ok :
-simulation has ended with functional test good ===="}\\
-which means that the test has been performed correctly.
-
-The Status Register and the Program Counter are initialized thanks to
-the RESET input on the board and convenient assembly instructions in
-the superuser rom (see {\bf add000.s}).
-
-The result of the simulation is placed in the {\bf pat} file called
-{\bf add000\_chip.pat} . You can take a look at this file using your favorite viewer/editor. 
-
-The reader who is willing to do more simulation test should follow the same procedure :
-
-\begin{itemize}
-\item
-select a new assembly program (user and supervisor) in the {\bf stock\_asm} directory and copy it into the root directory    
-\item
-create a new romu.vbe and a new roms.vbe by assembling a source file.
-
-\item
-run asimut
-\item
-check the simulation result : \\
-{\bf ERROR : `` assert violation on cell dlxm\_dec : " ==== ok :
-simulation has ended with functional test good ===="\\}
-\end{itemize}
-
-
-All the output files resulting from operations of the paragraph 3.1 can be written automatically using the target {\bf functional} of the Makefile by typing :
-
-\fbox {
-\shortstack[l] {
-\bf $>$ Make functional 
-}
-}
-
-
-	\subsection{Structural Design}
-
-    		\subsubsection{Design Hierarchy}
-
-
-In this step, the structural descriptions of the chip ({\bf dlxm.vst}), and the core ({\bf core.vst}) are used.
-The chip is described as a core surrounded by pads.
- The core is divided into two structural blocks: control and data
- path, the control block being also divided into two structural blocks
- : sequencer and status, each of which must be represented by its own behavioural description. The following source files are provided :
-
-\begin {itemize}
-\item
-{\bf dlxm\_chip.vst} : VHDL structural model of the dlxm chip instantiating core and pads.
-\item
-{\bf dlxm\_core.vst} : VHDL structural model of the core instantiating the data path,
-and the control.
-\item
-{\bf dlxm\_ctl.vst.h} : VHDL structural model of the control instantiating the 
-sequencer and the status (the control model ({\bf dlxm\_ctl.vst} being saved in the file
-{\bf dlxm\_ctl.vst.h} to prevent future erasing) .
-\item {\bf dlxm\_seq.fsm} : VHDL finite state machine model of the sequencer.
-\item {\bf dlxm\_sts.vbe} : VHDL behavioural model of the status.
-\item {\bf dlxm\_dpt.vbe} : VHDL behavioural model of the data path.
-\end{itemize}
-
-    		\subsubsection{Sequencer state assignment}
-
-The sequencer is written using a subset of {\bf VHDL} specifically designed for the description of finite state machines. You must therefore compile this into a VHDL data-flow behavioural model ({\bf vbe}) using the {\bf ALLIANCE} tool {\bf syf} :
-
-\fbox {
-\shortstack[l] {
-\bf [$>$ setenv MBK\_WORK\_LIB . ]\\
-\bf $>$ syf -s dlxm\_seq -of dlxm\_seq -scan -save
-}
-}
-
-\begin {itemize}
-\item {\bf -s} : uses a vertical encoding algorithm
-\item
-{\bf dlxm\_seq} : fsm source file ({\bf dlxm\_seq.fsm)}
-\item  
-{\bf -of dlxm\_seq} : output behavioural description ({\bf dlxm\_seq.vbe})
-\item
-{\bf -scan} : adds a scan-path to the state register.
-\item
-{\bf -save} : saves encoding result in {\bf dlxm\_seq.cod} file
-\end{itemize}
-
-		\subsubsection{Validation of the DLXm block view}
-
-You can then simulate the resulting model after having copied the
-structural description of the control in two blocks {\bf
-dlxm\_core.vst.h} :
-
-
-\fbox {
-\shortstack[l] {
-\bf $>$ cp dlxm\_ctl.vst.h dlxm\_ctl.vst \\
-\bf $>$ chmod 644 dlxm\_ctl.vst
-}
-}
-
-\fbox {
-\shortstack[l] {
-\bf [$>$ setenv VH\_BEHSFX vbe]\\
-\bf [$>$ setenv MBK\_MAXERR 10]\\
-\bf [$>$ setenv VH\_PATSFX pat]\\
-\bf [$>$ setenv MBK\_IN\_LO vst]\\
-\bf [$>$ setenv MBK\_WORK\_LIB . ]\\
-\bf [$>$ setenv MBK\_CATA\_LIB ...]\\
-\bf $>$ setenv MBK\_CATAL\_NAME CATAL\_CPU\_BLOCKS\\
-\bf $>$ asimut -l 1 -p 50 -bdd dlxm\_cpu dlxm\_cpu add000\_blocks
-} 
-} 
-
-\begin{itemize} 
-\item
-{\bf -l 1} : size of the label in the {\bf dlxm\_cpu.pat} and the {\bf
-add000\_blocks.pat} files.
-\item 
-{\bf -p 50} : simulation will use sets of 50 patterns (see {\it man
-asimut})
-\item
-{\bf -bdd} : simulation uses bdd representation
-\item
-{\bf dlxm\_cpu} : structural description of the board  ({\bf dlxm\_cpu.vst}) 
-\item
-{\bf dlxm\_cpu} : pattern input filename ({\bf dlxm\_cpu.pat}) 
-\item
-{\bf add000\_blocks} : result filename ({\bf add000\_blocks.pat}) 
-\end{itemize}
-
-You should get the message : \\
-{\bf ERROR : `` assert violation on cell dlxm\_dec : " ==== ok :
-simulation has ended with functional test good ===="}\\
-which means that the test has been performed correctly.
-
-The {\bf CATAL\_CPU\_BLOCKS} file tells {\bf asimut} to use the behavioural models for the three blocks data path, sequencer and status.
-
-
-    		\subsubsection{Data path compilation}
-
-The first stage in the synthesis of the structural description of the chip is the generation of the data path. The structural description of the data path is given in the source file {\bf dlxm\_dpt.c}.
-This textual description is equivalent to a schematic capture of the data path.
-This description uses a set of predefined macros (see {\em man fpgen}).
- You must compile this using the {\bf ALLIANCE} data path generator
- {\bf fpgen},
- you will thus use the provided subdirectory {\bf mclib} to store the
- generated operators:
-
-\fbox {
-\shortstack[l] {
-\bf [$>$ setenv MBK\_WORK\_LIB . ]\\
-\bf [$>$ setenv MBK\_CATA\_LIB ...]\\
-\bf [$>$ setenv MBK\_IN\_LO vst]\\
-\bf $>$ setenv MBK\_OUT\_LO vst\\
-\bf $>$ setenv MBK\_IN\_PH ap\\
-\bf $>$ setenv MBK\_OUT\_PH ap\\
-%\bf mkdir mclib\\
-\bf $>$ setenv FPGEN\_LIB ./mclib\\
-\bf $>$ fpgen dlxm\_dpt
-}
-}
-
-\begin{itemize}
-\item
-{\bf dlxm\_dpt} : input filename ({\bf dlxm\_dpt.c})
-\end{itemize}
-
-This generates a hierarchical {\bf VHDL}  net list of the
-data path {\bf dlxm\_dpt.vst} . The generated operators ({\bf
-vbe}, {\bf ap} and {\bf vst} formats) instantiated in {\bf
-dlxm\_dpt.vst} are stored 
-with their associated CATAL into
-the subdirectory {\bf ./mclib} defined by 
-the environment variable {\bf FPGEN\_LIB}.
-
-
-    		\subsubsection{Sequencer synthesis}
-
-A standard cell net list of the sequencer is synthesized by the logic synthesis tool {\bf logic}
-from the behavioural description contained in {\bf dlxm\_seq.vbe} :
-
-\fbox {
-\shortstack[l] {
-\bf [$>$ setenv MBK\_IN\_LO vst]\\
-\bf [$>$ setenv MBK\_OUT\_LO vst]\\
-\bf [$>$ setenv MBK\_WORK\_LIB . ]\\
-\bf $>$ setenv MBK\_TARGET\_LIB \$(ALLIANCE\_TOP)/cells/scr\\
-\bf $>$ logic -o dlxm\_seq dlxm\_seqo\\
-\bf $>$ logic -s dlxm\_seqo dlxm\_seq
-}
-}
-
-\begin{itemize}
-\item
-{\bf -o } : activates the behavioural optimizer and creates {\bf dlxm\_seqo.vbe}
-\item
-{\bf -s } : activates the standard cells mapper and creates {\bf dlxm\_seq.vst}
-\item
-{\bf dlxm\_seq} : input behavioural description for logic behavioural optimiser ({\bf dlxm\_seq.vbe})
-\item
-{\bf dlxm\_seqo} : behavioural optimized description ({\bf dlxm\_seqo.vbe})
-\item
-{\bf dlxm\_seq} : output gate net list description by logic ({\bf dlxm\_seq.vst})
-\end{itemize}
-
-
-This generates a VHDL gate net list {\bf dlxm\_seq.vst} using the
-standard cell library defined by the environment variable
-{\bf MBK\_TARGET\_LIB}.
-
-
-		\subsubsection{Status synthesis}
-
-A standard cell net list of the status block is synthesized from the
-behavioural description contained in {\bf dlxm\_sts.vbe}. This is
-done using {\bf logic} as for the sequencer.
-
-
-\fbox {
-\shortstack[l] {
-\bf [$>$ setenv MBK\_IN\_LO vst]\\
-\bf [$>$ setenv MBK\_OUT\_LO vst]\\
-\bf [$>$ setenv MBK\_WORK\_LIB . ]\\
-\bf [$>$ setenv MBK\_TARGET\_LIB \$(ALLIANCE\_TOP)/cells/scr]\\
-\bf $>$ logic -o dlxm\_sts dlxm\_stso\\
-\bf $>$ logic -s dlxm\_stso dlxm\_sts
-}
-}
-
-\begin{itemize}
-\item
-{\bf -o } : activates the behavioural optimizer and creates {\bf dlxm\_stso.vbe}
-\item
-{\bf -s } : activates the standard cells mapper and creates {\bf dlxm\_sts.vst}
-\item
-{\bf dlxm\_sts} : input behavioural description for logic behavioural optimiser ({\bf dlxm\_sts.vbe})
-\item
-{\bf dlxm\_stso} : behavioural optimized description ({\bf dlxm\_stso.vbe})
-\item
-{\bf dlxm\_sts} : output gate net list description by logic ({\bf dlxm\_sts.vst})
-\end{itemize}
-
-
-
-This generates a VHDL gate net list {\bf dlxm\_sts.vst} using the
-standard cell library defined by the environment variable
-{\bf MBK\_TARGET\_LIB}.
-
-    		\subsubsection{Control block generation }
-
-
-
-The logic synthesizer does not take care of fanout constraints. 
-In order to minimize delays
-you now use the {\bf ALLIANCE} tool {\bf netoptim}. This performs
-fan-out optimisation and buffering of a structural description in
-order to minimise propagation delays of critical paths. {\bf netoptim} 
-operates on the hierarchical view {\bf dlxm\_ctl.vst} and flattens it
-to the gate level, thus creating the gate-level {\bf dlxm\_ctl.vst}
-model (and erasing the hierarchical view {\bf dlxm\_ctl.vst}):
-
-\fbox {
-\shortstack[l] {
-\bf [$>$ setenv MBK\_WORK\_LIB . ]\\
-\bf [$>$ setenv MBK\_CATA\_LIB ...]\\
-\bf [$>$ setenv MBK\_IN\_LO vst]\\
-\bf [$>$ setenv MBK\_OUT\_LO vst]\\
-\bf $>$ setenv MBK\_VDD vdd \\
-\bf $>$ setenv MBK\_VSS vss \\
-\bf $>$ netoptim -g dlxm\_ctl dlxm\_ctl
-}
-}
-
-\begin{itemize}
-\item
-{\bf -g} : netoptim performs a global optimization
-\item
-{\bf dlxm\_ctl} : input structural description ({\bf dlxm\_ctl.vst})
-\item
-{\bf dlxm\_ctl} : output optimised structural description ({\bf dlxm\_ctl.vst})
-flattened to gate level.
-\end{itemize}
-
-		
-		\subsubsection{DLXm structural view validation}
-
-
-We have now a complete gate-level net list of the processor.
-This stage can be validated using {\bf asimut} :
-
-\fbox {
-\shortstack[l] {
-\bf [$>$ setenv MBK\_WORK\_LIB . ]\\
-\bf [$>$ setenv MBK\_CATA\_LIB ...]\\
-\bf [ $>$ setenv VH\_BEHSFX vbe]\\
-\bf [$>$ setenv MBK\_MAXERR 10]\\
-\bf [$>$ setenv VH\_PATSFX pat]\\
-\bf [$>$ setenv MBK\_IN\_LO vst]\\
-\bf $>$ setenv MBK\_CATAL\_NAME CATAL\_CPU\_GATES\\
-\bf $>$ asimut -l 1 -p 50 -bdd dlxm\_cpu dlxm\_cpu add000\_gates
-}
-}
-
-\begin{itemize} 
-\item
-{\bf -l 1} : size of the label in the {\bf dlxm\_cpu.pat} and the {\bf
-add000\_gates.pat} files.
-\item 
-{\bf -p 50} : simulation will use sets of 50 patterns (see {\it man
-asimut})
-\item
-{\bf -bdd} : simulation uses bdd representation
-\item
-{\bf dlxm\_cpu} : structural description of the board  ({\bf dlxm\_cpu.vst}) 
-\item
-{\bf dlxm\_cpu} : pattern input filename ({\bf dlxm\_cpu.pat}) 
-\item
-{\bf add000\_gates} : result filename ({\bf add000\_gates.pat}) 
-\end{itemize}
-
-You should get the message : \\
-{\bf ERROR : `` assert violation on cell dlxm\_dec : " ==== ok :
-simulation has ended with functional test good ===="}\\
-which means that the test has been performed correctly.
-
-The {\bf CATAL\_CPU\_GATES} file tells {\bf asimut} to use the
-behavioural models for the gates and for the generated blocks.
-
-
-		\subsubsection{Design for testability}
-
-All registers, except the 32 word register file, are in the scan-path :
-
-\begin{itemize}
-\item
-{\bf data path }: The structural description uses scanable registers.
-\item
-{\bf sequencer }: SYF has been used with the option {\bf -scan} that automatically uses scanable registers.
-\item
-{\bf status }: The behavioural description explicitly describes scanable registers.
-\end{itemize}
-
-Here we check the scan path with the simulator {\bf asimut} with a
-dedicated file that fills in the scan path and check the scan output.
-
-\fbox {
-\shortstack[l] {
-\bf [$>$ setenv VH\_PATSFX pat]\\
-\bf [ $>$ setenv VH\_BEHSFX vbe]\\
-\bf [$>$ setenv MBK\_MAXERR 10]\\
-\bf [$>$ setenv VH\_PATSFX pat]\\
-\bf [$>$ setenv MBK\_IN\_LO vst]\\
-\bf [$>$ setenv MBK\_CATAL\_NAME CATAL\_CPU\_GATES]\\
-\bf [$>$ setenv MBK\_WORK\_LIB . ]\\
-\bf [$>$ setenv MBK\_CATA\_LIB ...]\\
-\bf $>$ asimut -l 10 -p 50 -bdd dlxm\_cpu dlxm\_scan dlxm\_scan\_res
-}
-}
-
-\begin{itemize}
-\item
-{\bf -l 10} : size of the label in the {\bf dlxm\_scan.pat} and the {\bf
-dlxm\_scan\_res.pat} files.
-\item 
-{\bf -p 50} : simulation will use sets of 50 patterns (see {\it man
-asimut})
-\item
-{\bf -bdd} : simulation uses bdd representation
-\item
-{\bf dlxm\_cpu} : structural description of the board ({\bf dlxm\_cpu.vst})
-\item
-{\bf dlxm\_scan} : pattern input filename ({\bf dlxm\_scan.pat})
-\item
-{\bf dlxm\_scan\_res } : result filename ({\bf dlxm\_scan\_res.pat})
-\end{itemize}
-
-The output files resulting from commands of the paragraph 3.2, can be created automatically using the target {\bf structural} of the Makefile by typing:
-
-\fbox {
-\shortstack[l] {
-\bf $>$ Make structural
-}
-}
-
-	\subsection{Physical Layout}
-
-
-
-To get the symbolic layout description of the chip, you will :
-
-\begin{itemize}
-\item
-route the control block with the standard cells router {\bf scr}
-\item
-route the data path with  the specialized router {\bf dpr}
-\item
-route the data path and the control together with {\bf bbr} (block to
-block channel router)
-\item
-route the core to the pads with the {\bf ring} router
-\end{itemize}
-
-Each place and route step will be validated using the following method :
-
-\begin{itemize}
-\item
-extracting a net list from the symbolic layout file using {\bf lynx}
-\item
-comparing input net list and extracted net list with {\bf lvx}
-\end{itemize}
-
-
-
-    		\subsubsection{Control block routing}
-
-
-You must now use {\bf scr} (Standard Cell Router) to generate the physical layout
-of the control.
-We will use the ALLIANCE format for input and output symbolic layout by setting the appropriate environment variables :
-
-\fbox {
-\shortstack[l] {
-\bf [$>$ setenv MBK\_WORK\_LIB . ]\\
-\bf [$>$ setenv MBK\_CATA\_LIB ...]\\
-\bf [$>$ setenv MBK\_VDD vdd]\\
-\bf [$>$ setenv MBK\_VSS vss]\\
-\bf [$>$ setenv MBK\_IN\_LO vst]\\
-\bf [$>$ setenv MBK\_OUT\_LO vst]\\
-\bf [$>$ setenv MBK\_IN\_PH ap]\\
-\bf [$>$ setenv MBK\_OUT\_PH ap]\\
-\bf $>$ scr -p -r -l 5 -i 3000 -a 5 dlxm\_ctl
-}
-}
-
-\begin {itemize}
-\item {\bf -p} : Automatic placement.
-\item {\bf -r} : Perform routing.
-\item {\bf -l 5} : Number of rows.
-\item {\bf -i 3000} : Number of iterations.
-\item {\bf -a 5} : Number of vertical supplies (power and ground
-wires).
-\item {\bf dlxm\_ctl} : Input net list ({\bf dlxm\_ctl.vst})
-and connector placement parameter file ({\bf dlxm\_ctl.scr})
-\end{itemize}
-
-The router takes the net list specified in the file {\bf
-dlxm\_ctl.vst} and generates a physical layout in the file {\bf
-dlxm\_ctl.ap} following the connector
-parameter file requirements.
-
-In order to verify that no errors occured in the generation of the physical layout, we extract a net list from the layout using the {\bf ALLIANCE} tool {\bf lynx}, and then compare the result with the original net list using {\bf lvx}. 
-
-To avoid confusion between original and extracted net lists we use the {\bf al} format to represent extracted net lists. For {\bf lynx} to generate its output in this format, you must set the appropriate environment variable :
-
-\fbox {
-\shortstack[l] {
-\bf [$>$ setenv MBK\_WORK\_LIB . ]\\
-\bf [$>$ setenv MBK\_CATA\_LIB ...]\\
-\bf [$>$ setenv MBK\_IN\_PH ap]\\
-\bf $>$ setenv MBK\_OUT\_LO al\\
-%\bf $>$ setenv RDS\_TECHNO\_NAME $(ALLIANCE\_TOP)/etc/prol10.rds\\
-\bf $>$ lynx  dlxm\_ctl dlxm\_ctl
-}
-}
-
-\begin{itemize}
-\item
-{\bf dlxm\_ctl} : input file (symbolic layout) {\bf dlxm\_ctl.ap}
-\item
-{\bf dlxm\_ctl} : output file (extracted net list) {\bf dlxm\_ctl.al}
-\end{itemize}
-
-Then compare :
-
-\fbox {
-\shortstack[l] {
-\bf [$>$ setenv MBK\_WORK\_LIB . ]\\
-\bf [$>$ setenv MBK\_CATA\_LIB ...]\\
-\bf $>$ lvx vst al dlxm\_ctl dlxm\_ctl
-}
-}
-
-\begin{itemize}
-\item
-{\bf vst} and {\bf dlxm\_ctl} : input net list {\bf dlxm\_ctl.vst}
-\item
-{\bf al} and {\bf dlxm\_ctl} : extracted net list {\bf dlxm\_ctl.al}
-\end{itemize}
-
-And you should get the reply ``Net Lists are Identical''.
-
-
-    		\subsubsection{Routing the Data Path}
-
-The data path uses a special type of cell library which is designed to allow routing over the cells, thus saving a considerable amount of space compared with standard-cell implementation. For this routing you must use the {\bf ALLIANCE} tool {\bf dpr} (Data Path Router).
-
-
-
-\fbox {
-\shortstack[l] {
-\bf [$>$ setenv MBK\_WORK\_LIB . ]\\
-\bf [$>$ setenv MBK\_CATA\_LIB ...]\\
-\bf [$>$ setenv MBK\_VDD vdd]\\
-\bf [$>$ setenv MBK\_VSS vss]\\
-\bf [$>$ setenv MBK\_IN\_LO vst]\\
-\bf [$>$ setenv MBK\_IN\_PH ap]\\
-\bf [$>$ setenv MBK\_OUT\_PH ap]\\
-\bf $>$ dpr -o -p -r dlxm\_dpt dlxm\_dpt
-}
-}
-
-\begin {itemize}
-\item {\bf -o} : Placement optimizatiom.
-\item {\bf -p} : Automatic placement .
-\item {\bf -r} : Automatic  routing.
-\item {\bf dlxm\_dpt} : Output net list ({\bf dlxm\_dpt.ap}).
-\item {\bf dlxm\_dpt} : Input net list ({\bf dlxm\_dpt.vst}) and
-Connector placement parameter file {\bf
-dlxm\_dpt.dpr}.
-\end{itemize}
-
-The router takes the net list specified in the file {\bf
-dlxm\_dpt.vst} and generates a physical layout in the file {\bf
-dlxm\_dpt.ap} following the connector parameter file requirements. 
-
-
-Now repeat the verification procedure for the data path. 
-First the extraction :
-
-\fbox {
-\shortstack[l] {
-\bf [$>$ setenv MBK\_WORK\_LIB . ]\\
-\bf [$>$ setenv MBK\_CATA\_LIB ...]\\
-\bf [$>$ setenv MBK\_IN\_PH ap]\\
-\bf [$>$ setenv MBK\_OUT\_LO al]\\
-%\bf [$>$ setenv RDS\_TECHNO\_NAME $(ALLIANCE\_TOP)/etc/prol10.rds]\\
-\bf $>$ lynx dlxm\_dpt dlxm\_dpt
-}
-}
-
-\begin{itemize}
-\item
-{\bf dlxm\_dpt} : input file (symbolic layout) {\bf dlxm\_dpt.ap}
-\item
-{\bf dlxm\_dpt} : output file (extracted net list) {\bf dlxm\_dpt.al}
-\end{itemize}
-
-Then compare :
-
-\fbox {
-\shortstack[l] {
-\bf [$>$ setenv MBK\_WORK\_LIB . ]\\
-\bf [$>$ setenv MBK\_CATA\_LIB ...]\\
-\bf $>$ lvx vst al dlxm\_dpt dlxm\_dpt 
-}
-}
-
-\begin{itemize}
-\item
-{\bf vst} and {\bf dlxm\_dpt} : input net list {\bf dlxm\_dpt.vst}
-\item
-{\bf al} and {\bf dlxm\_dpt} : extracted net list {\bf dlxm\_dpt.al}
-\end{itemize}
-
-
-
-    		\subsubsection{Routing the Core}
-
-You must now interconnect the control block and the data path in order to generate the core.
-You will use {\bf ALLIANCE} tool {\bf bbr} to route them together.
-
-
-First of all, you generate a ``placement'' file, which tells {\bf bbr}
-how the blocks are physically orientated with respect to each other.
-The simplest way for you to do this is to use {\bf genlib} with the
-source file {\bf dlxm\_core.c}, which is provided:
-
-\fbox {
-\shortstack[l] {
-\bf [$>$ setenv MBK\_WORK\_LIB . ]\\
-\bf [$>$ setenv MBK\_CATA\_LIB ...]\\
-\bf $>$ genlib dlxm\_core
-}
-}
-
-\begin{itemize}
-\item
-{\bf dlxm\_core} : input file name {\bf dlxm\_core.c}
-\end{itemize}
-
-This generates the placement file {\bf dlxm\_core.ap}.
-
-
-The file format environment variables remain the same as before, so to produce a routed core all you have to do is :
-
-\fbox {
-\shortstack[l] {
-\bf [$>$ setenv MBK\_WORK\_LIB . ]\\
-\bf [$>$ setenv MBK\_CATA\_LIB ...]\\
-\bf [$>$ setenv MBK\_IN\_LO vst]\\
-\bf [$>$ setenv MBK\_IN\_PH ap]\\
-\bf [$>$ setenv MBK\_OUT\_PH ap]\\
-\bf $>$ bbr dlxm\_core -o dlxm\_core vdd 12 vss 12
-}
-}
-
-\begin {itemize}
-\item {\bf dlxm\_core} : Input net list {\bf dlxm\_core.vst} and
-placement file {\bf dlxm\_core.ap}.
-\item {\bf -o } : Output file {\bf dlxm\_core.ap} (erasing placement file).
-\item {\bf vdd 12 vss 12} : Width of power and ground wires.
-\end{itemize}
-
-
-You now have the file {\bf dlxm\_core.ap} containing the physical layout of the core.
-
-{\bf Verification of the Core}
-
-Now you perform the same verification process at the core level :
-
-\fbox {
-\shortstack[l] {
-\bf [$>$ setenv MBK\_WORK\_LIB . ]\\
-\bf [$>$ setenv MBK\_CATA\_LIB ...]\\
-\bf [$>$ setenv MBK\_IN\_PH ap]\\
-\bf [$>$ setenv MBK\_OUT\_LO al]\\
-%\bf [$>$ setenv RDS\_TECHNO\_NAME $(ALLIANCE\_TOP)/etc/prol10.rds]\\
-\bf $>$ lynx dlxm\_core dlxm\_core
-}
-}
-
-\begin{itemize}
-\item
-{\bf dlxm\_core} : input file (symbolic layout) {\bf dlxm\_core.ap}
-\item
-{\bf dlxm\_core} : output file (extracted net list) {\bf dlxm\_core.al}
-\end{itemize}
-
-Then compare :
-
-\fbox {
-\shortstack[l] {
-\bf [$>$ setenv MBK\_WORK\_LIB . ]\\
-\bf [$>$ setenv MBK\_CATA\_LIB ...]\\
-\bf $>$ lvx vst al dlxm\_core dlxm\_core
-}
-}
-
-\begin{itemize}
-\item
-{\bf vst} and {\bf dlxm\_core} : input net list {\bf dlxm\_core.vst}
-\item
-{\bf al} and {\bf dlxm\_core} : extracted net list {\bf dlxm\_core.al}
-\end{itemize}
-
-And again you should get the reply ``Net Lists are Identical''.
-
-
-
-    		\subsubsection{Routing the Chip}
-
-The final stage in generating the physical layout of the chip is to
-route the core to the pads using {\bf ring}. The pad placement depends
-on external constraints (see {\em man ring}) and is therefore defined
-in the file {\bf dlxm\_chip.rin}.
-
-Again the file format variables remain unchanged so you can now perform the routing :
-
-\fbox {
-\shortstack[l] {
-\bf [$>$ setenv MBK\_WORK\_LIB . ]\\
-\bf [$>$ setenv MBK\_CATAL\_NAME CATAL\\
-\bf [$>$ setenv MBK\_CATA\_LIB ...]\\
-\bf [$>$ setenv MBK\_IN\_LO vst]\\
-\bf [$>$ setenv MBK\_IN\_PH ap]\\
-\bf [$>$ setenv MBK\_OUT\_PH ap]\\
-\bf $>$ ring dlxm\_chip dlxm\_chip
-}
-}
-
-\begin{itemize}
-\item
-{\bf dlxm\_chip} : input netlist {\bf dlxm\_chip.vst} and placement
-file {\bf dlxm\_chip.rin}
-\item
-{\bf dlxm\_chip} : output symbolic layout file name {\bf
-dlxm\_chip.ap}
-\end{itemize}
-
-Thus a physical layout of the chip is generated in the file {\bf
-dlxm\_chip.ap}.
-
- 
-{\bf Verification of the Chip}
-
-Finally you must verify at the chip level :
-
-\fbox {
-\shortstack[l] {
-\bf [$>$ setenv MBK\_WORK\_LIB . ]\\
-\bf [$>$ setenv MBK\_CATA\_LIB ...]\\
-\bf [$>$ setenv MBK\_IN\_PH ap]\\
-\bf [$>$ setenv MBK\_OUT\_LO al]\\
-%\bf [$>$ setenv RDS\_TECHNO\_NAME $(ALLIANCE\_TOP)/etc/prol10.rds]\\
-\bf $>$ lynx dlxm\_chip dlxm\_chip
-}
-}
-
-\begin{itemize}
-\item
-{\bf dlxm\_chip} : input file (symbolic layout) {\bf dlxm\_chip.ap}
-\item
-{\bf dlxm\_chip} : output file (extracted net list) {\bf dlxm\_chip.al}
-\end{itemize}
-
-
-Then compare :
-
-\fbox {
-\shortstack[l] {
-\bf [$>$ setenv MBK\_WORK\_LIB . ]\\
-\bf [$>$ setenv MBK\_CATA\_LIB ...]\\
-\bf $>$ lvx vst al dlxm\_chip dlxm\_chip
-}
-}
-
-
-\begin{itemize}
-\item
-{\bf vst} and {\bf dlxm\_chip} : input net list {\bf dlxm\_chip.vst}
-\item
-{\bf al} and {\bf dlxm\_chip} : extracted net list {\bf dlxm\_chip.al}
-\end{itemize}
-
-And if you get the reply ``Net Lists are Identical'' your entire chip has been correctly routed.
-
-You can visualize the chip using {\bf graal}. Use for example:
-
-\fbox {
-\shortstack[l] {
-\bf [$>$ setenv MBK\_CATA\_LIB ...]\\
-%\bf $>$ setenv RDS\_TECHNO\_NAME \$(ALLIANCE\_TOP)/etc/cmos\_5.rds\\
-\bf $>$ graal dlxm\_chip
-}
-}
-
-
-
-The output files resulting from commands of the paragraph 3.3 can be created automatically using the target {\bf physical} of the Makefile by typing:
-
-\fbox {
-\shortstack[l] {
-\bf $>$ Make physical
-}
-}
-
-
-\subsection{The Final Touch}
-
-The last step is to translate the symbolic layout (coordinates in lambda units) into a physical layout for the target CMOS process (two output formats are supported : CIF and GDSII). This task is done by {\bf s2r}, which performs symbolic to real expansion, gap filling, denotching, and instantiates preexisting layout cells (necessary for the pads).
-
-You must first define an environment variable with the name of a file containing the parameters of the target process (in our case a 1 micron process) 
-and then specify the cif format :
-
-
-\fbox {
-\shortstack[l] {
-\bf [$>$ setenv MBK\_WORK\_LIB . ]\\
-\bf [$>$ setenv MBK\_CATAL\_NAME CATAL\_CPU\_GATES]\\
-\bf [$>$ setenv MBK\_CATA\_LIB .:...]\\
-\bf [$>$ setenv MBK\_IN\_PH ap]\\
-\bf $>$ setenv RDS\_TECHNO\_NAME \$(ALLIANCE\_TOP)/etc/prol10.rds\\
-\bf $>$ setenv RDS\_OUT cif\\
-\bf $>$ setenv RDS\_IN cif
-}
-}
-
-The variable {\bf RDS\_IN} is required to specify the format of preexisting layout cells.
-
-Then to perform the conversion :
-
-\fbox {
-\shortstack[l] {
-\bf $>$ s2r  dlxm\_chip dlxm\_chip
-}
-}
-
-\begin{itemize}
-\item
-{\bf dlxm\_chip} : input symbolic layout file ({\bf dlxm\_chip.ap}).
-\item
-{\bf dlxm\_chip} : output physical layout file ({\bf dlxm\_chip.cif}).
-\end{itemize}
-
-The output files resulting from commands of the paragraph 3.4 can be written automatically using the target {\bf real} of the Makefile by typing:
-
-\fbox {
-\shortstack[l] {
-\bf $>$ Make real
-}
-}
-
-Congratulations$!$ The chip is ready for the foundry.
-
-
-\newpage
-
-\begin{center}
-{\Large \bf DLX TUTORIAL - APPENDIX}\\
-\today \\
-\end{center}
-
-You can find below all the source files for the DLX microprocessor.
-
-\begin{center}
-{\bf functional specification} 
-\end{center}
-\begin{itemize}
-\item {\bf dlxm\_cpu.vst} : VHDL structural model of the board instantiating RAM, ROM, timer, decoder, dlxm. 
-\item {\bf sr64\_1a.vbe}, 
-{\bf sr64\_8a.vst}  and
-{\bf sr64\_32a.vst} : Behavioural and structural description for the RAM .
-\item {\bf dlxm\_dec.vbe}  : VHDL behavioural description of the address decoder.
-\item {\bf timer.vbe}     : VHDL behavioural description of the timer.
-\item {\bf dlxm\_chip.vbe}        : VHDL behavioural description of the dlxm.
-\item {\bf add000.u and add000.s} : Short assembly language programs.
-\item {\bf CATAL\_CPU\_CHIP}    : List of behavioural models required for a simulation using the behavioural
-model of DLXm.
-\item {\bf dlxm\_cpu.pat}   : Pattern input file for testing various
-views of dlxm chip.
-\end{itemize}
-
-\begin{center}
-{\bf structural design} 
-\end{center}
-\begin{itemize}
-\item
-{\bf dlxm\_chip.vst} : VHDL structural model of the dlxm instantiating core and pads.
-\item
-{\bf dlxm\_core.vst} : VHDL structural model of the core instantiating
-the data path and the control.
-\item
-{\bf dlxm\_ctl.vst.h} : VHDL structural model of the control
-instantiating the sequencer and the status.
-\item
-{\bf dlxm\_seq.fsm} : Finite State Machine description for sequencer.
-\item {\bf dlxm\_dpt.vbe} : Behavioural description for data path.
-\item {\bf CATAL\_CPU\_BLOCKS}    : List of behavioural models required for a simulation using 
-behavioural descriptions  for data path, sequencer and status.
-\item {\bf dlxm\_dpt.c}   : Source code for data path generator.
-\item {\bf ./mclib } : Subdirectiry used by {\bf fpgen} to store
-the generated data path operators.
-\item {\bf dlxm\_sts.vbe} : Behavioural description for status and interrupts.
-%\item {\bf dlxm\_ctl.lax}        : Parameter file for {\bf netoptim}
-\item {\bf CATAL\_CPU\_GATES}    : List of behavioural models required for a simulation using 
-structural descriptions for data path, sequencer and status.
-\item {\bf dlxm\_scan.pat} : Pattern input file for scan path simulation.
-\end{itemize}
-
-\begin{center}
-{\bf physical layout} 
-\end{center}
-\begin{itemize}
-\item {\bf dlxm\_dpt.dpr} : Placement file for data path block
-connectors ({\bf dpr} tool)
-\item {\bf dlxm\_ctl.scr} : Placement file for control block connectors ({\bf scr} tool)
-\item {\bf dlxm\_core.c}        : Placement file for control and data path ({\bf bbr} tool)
-\item {\bf dlxm\_chip.rin}      : Placement file for dlxm pads ({\bf ring} tool)
-\end{itemize}
-
-\end{document}
-
diff --git a/alliance/share/tutorials/dlxm/mbkenv b/alliance/share/tutorials/dlxm/mbkenv
deleted file mode 100644
index e80436aa..00000000
--- a/alliance/share/tutorials/dlxm/mbkenv
+++ /dev/null
@@ -1 +0,0 @@
-setenv MBK_CATA_LIB /asim/alliance/cells/bsg:/asim/alliance/cells/fplib:/asim/alliance/cells/padlib:/asim/alliance/cells/rfg:/asim/alliance/cells/rsa:/asim/alliance/cells/amg:/asim/alliance/cells/sxlib:./mclib
diff --git a/alliance/share/tutorials/dlxm/roms2.vbe b/alliance/share/tutorials/dlxm/roms2.vbe
deleted file mode 100644
index b285dbba..00000000
--- a/alliance/share/tutorials/dlxm/roms2.vbe
+++ /dev/null
@@ -1,25 +0,0 @@
-entity roms2 is
-  port (
-    address : in  bit_vector (5 downto 0);
-    e_n     : in  bit;
-    data    : out mux_vector (7 downto 0) bus;
-    vdd     : in bit;
-    vss     : in bit);
-end roms2;
-
-architecture VBE of roms2 is
-
-  signal rom_out : bit_vector (7 downto 0);
-
-begin
-
-  write_out : block (e_n = '0')
-  begin
-    data <= guarded rom_out;
-  end block;
-
-  with address (5 downto 0) select
-  rom_out <=
-          X"00" when others;
-
-end;
diff --git a/alliance/share/tutorials/dlxm/romu2.vbe b/alliance/share/tutorials/dlxm/romu2.vbe
deleted file mode 100644
index 4e3af07f..00000000
--- a/alliance/share/tutorials/dlxm/romu2.vbe
+++ /dev/null
@@ -1,25 +0,0 @@
-entity romu2 is
-  port (
-    address : in  bit_vector (5 downto 0);
-    e_n     : in  bit;
-    data    : out mux_vector (7 downto 0) bus;
-    vdd     : in bit;
-    vss     : in bit);
-end romu2;
-
-architecture VBE of romu2 is
-
-  signal rom_out : bit_vector (7 downto 0);
-
-begin
-
-  write_out : block (e_n = '0')
-  begin
-    data <= guarded rom_out;
-  end block;
-
-  with address (5 downto 0) select
-  rom_out <=
-          X"00" when others;
-
-end;
diff --git a/alliance/share/tutorials/dlxm/sr64_1a.vbe b/alliance/share/tutorials/dlxm/sr64_1a.vbe
deleted file mode 100644
index 7b9ae71b..00000000
--- a/alliance/share/tutorials/dlxm/sr64_1a.vbe
+++ /dev/null
@@ -1,447 +0,0 @@
--- ### -------------------------------------------------------------- ###
--- #									#
--- # file	: sr64_1a.vbe						#
--- # date	: 1993					        	#
--- # version	: v0.0							#
--- #									#
--- # origin	: this description has been developed by CAO-VLSI team	#
--- #		  at MASI laboratory, University Pierre et Marie Curie	#
--- #		  URA CNRS 818, Institut Blaise Pascal			#
--- #		  4 Place Jussieu 75252 Paris Cedex 05 - France		#
--- # E-mail      :      cao-vlsi@masi.ibp.fr                            #
--- #									#
--- # descr.	: data flow description of a ram 64*1.        		#
--- #									#
--- ### -------------------------------------------------------------- ###
-
-entity sr64_1a is
-
-  port (
-       E_N         : in  bit                        ;
-       W_N         : in  bit                        ;
-       D           : in  bit                        ;
-       Q           : out mux_bit                 bus;
-       A           : in  bit_vector (5 downto 0)    ;
-       VDD         : in  bit                        ;
-       VSS         : in  bit
-       );
-
-end sr64_1a;
-
-
-architecture FUNCTIONAL of sr64_1a is
-
-  signal RAM0_RX , RAM1_RX , RAM2_RX , RAM3_RX , RAM4_RX  : reg_bit register;
-  signal RAM5_RX , RAM6_RX , RAM7_RX , RAM8_RX , RAM9_RX  : reg_bit register;
-  signal RAM10_RX, RAM11_RX, RAM12_RX, RAM13_RX, RAM14_RX : reg_bit register;
-  signal RAM15_RX, RAM16_RX, RAM17_RX, RAM18_RX, RAM19_RX : reg_bit register;
-  signal RAM20_RX, RAM21_RX, RAM22_RX, RAM23_RX, RAM24_RX : reg_bit register;
-  signal RAM25_RX, RAM26_RX, RAM27_RX, RAM28_RX, RAM29_RX : reg_bit register;
-  signal RAM30_RX, RAM31_RX, RAM32_RX, RAM33_RX, RAM34_RX : reg_bit register;
-  signal RAM35_RX, RAM36_RX, RAM37_RX, RAM38_RX, RAM39_RX : reg_bit register;
-  signal RAM40_RX, RAM41_RX, RAM42_RX, RAM43_RX, RAM44_RX : reg_bit register;
-  signal RAM45_RX, RAM46_RX, RAM47_RX, RAM48_RX, RAM49_RX : reg_bit register;
-  signal RAM50_RX, RAM51_RX, RAM52_RX, RAM53_RX, RAM54_RX : reg_bit register;
-  signal RAM55_RX, RAM56_RX, RAM57_RX, RAM58_RX, RAM59_RX : reg_bit register;
-  signal RAM60_RX, RAM61_RX, RAM62_RX, RAM63_RX           : reg_bit register;
-
-  signal READ_SX                                          : bit;
-  signal WRTEN_SX                                         : bit;
-
-begin
-
-  WRTEN_SX <= E_N nor W_N;
-
-  wr_0 : block (WRTEN_SX = '1' and A = "000000")
-  begin
-    RAM0_RX <= guarded D;
-  end block;
-
-  wr_1 : block (WRTEN_SX = '1' and A = "000001")
-  begin
-    RAM1_RX <= guarded D;
-  end block;
-
-  wr_2 : block (WRTEN_SX = '1' and A = "000010")
-  begin
-    RAM2_RX <= guarded D;
-  end block;
-
-  wr_3: block (WRTEN_SX = '1' and A = "000011")
-  begin
-    RAM3_RX <= guarded D;
-  end block;
-
-  wr_4: block (WRTEN_SX = '1' and A = "000100")
-  begin
-    RAM4_RX <= guarded D;
-  end block;
-
-  wr_5: block (WRTEN_SX = '1' and A = "000101")
-  begin
-    RAM5_RX <= guarded D;
-  end block;
-
-  wr_6: block (WRTEN_SX = '1' and A = "000110")
-  begin
-    RAM6_RX <= guarded D;
-  end block;
-
-  wr_7: block (WRTEN_SX = '1' and A = "000111")
-  begin
-    RAM7_RX <= guarded D;
-  end block;
-
-  wr_8: block (WRTEN_SX = '1' and A = "001000")
-  begin
-    RAM8_RX <= guarded D;
-  end block;
-
-  wr_9: block (WRTEN_SX = '1' and A = "001001")
-  begin
-    RAM9_RX <= guarded D;
-  end block;
-
-  wr_10: block (WRTEN_SX = '1' and A = "001010")
-  begin
-    RAM10_RX <= guarded D;
-  end block;
-
-  wr_11: block (WRTEN_SX = '1' and A = "001011")
-  begin
-    RAM11_RX <= guarded D;
-  end block;
-
-  wr_12: block (WRTEN_SX = '1' and A = "001100")
-  begin
-    RAM12_RX <= guarded D;
-  end block;
-
-  wr_13: block (WRTEN_SX = '1' and A = "001101")
-  begin
-    RAM13_RX <= guarded D;
-  end block;
-
-  wr_14: block (WRTEN_SX = '1' and A = "001110")
-  begin
-    RAM14_RX <= guarded D;
-  end block;
-
-  wr_15: block (WRTEN_SX = '1' and A = "001111")
-  begin
-    RAM15_RX <= guarded D;
-  end block;
-
-  wr_16: block (WRTEN_SX = '1' and A = "010000")
-  begin
-    RAM16_RX <= guarded D;
-  end block;
-
-  wr_17: block (WRTEN_SX = '1' and A = "010001")
-  begin
-    RAM17_RX <= guarded D;
-  end block;
-
-  wr_18: block (WRTEN_SX = '1' and A = "010010")
-  begin
-    RAM18_RX <= guarded D;
-  end block;
-
-  wr_19: block (WRTEN_SX = '1' and A = "010011")
-  begin
-    RAM19_RX <= guarded D;
-  end block;
-
-  wr_20: block (WRTEN_SX = '1' and A = "010100")
-
-  begin
-    RAM20_RX <= guarded D;
-  end block;
-
-  wr_21: block (WRTEN_SX = '1' and A = "010101")
-  begin
-    RAM21_RX <= guarded D;
-  end block;
-
-  wr_22: block (WRTEN_SX = '1' and A = "010110")
-  begin
-    RAM22_RX <= guarded D;
-  end block;
-
-  wr_23: block (WRTEN_SX = '1' and A = "010111")
-  begin
-    RAM23_RX <= guarded D;
-  end block;
-
-  wr_24: block (WRTEN_SX = '1' and A = "011000")
-  begin
-    RAM24_RX <= guarded D;
-  end block;
-
-  wr_25: block (WRTEN_SX = '1' and A = "011001")
-  begin
-    RAM25_RX <= guarded D;
-  end block;
-
-  wr_26: block (WRTEN_SX = '1' and A = "011010")
-  begin
-    RAM26_RX <= guarded D;
-  end block;
-
-  wr_27: block (WRTEN_SX = '1' and A = "011011")
-  begin
-    RAM27_RX <= guarded D;
-  end block;
-
-  wr_28: block (WRTEN_SX = '1' and A = "011100")
-  begin
-    RAM28_RX <= guarded D;
-  end block;
-
-  wr_29: block (WRTEN_SX = '1' and A = "011101")
-  begin
-    RAM29_RX <= guarded D;
-  end block;
-
-  wr_30: block (WRTEN_SX = '1' and A = "011110")
-  begin
-    RAM30_RX <= guarded D;
-  end block;
-
-  wr_31: block (WRTEN_SX = '1' and A = "011111")
-  begin
-    RAM31_RX <= guarded D;
-  end block;
-
-  wr_32: block (WRTEN_SX = '1' and A = "100000")
-  begin
-    RAM32_RX <= guarded D;
-  end block;
-
-  wr_33: block (WRTEN_SX = '1' and A = "100001")
-  begin
-    RAM33_RX <= guarded D;
-  end block;
-
-  wr_34: block (WRTEN_SX = '1' and A = "100010")
-  begin
-    RAM34_RX <= guarded D;
-  end block;
-
-  wr_35: block (WRTEN_SX = '1' and A = "100011")
-  begin
-    RAM35_RX <= guarded D;
-  end block;
-
-  wr_36: block (WRTEN_SX = '1' and A = "100100")
-  begin
-    RAM36_RX <= guarded D;
-  end block;
-
-  wr_37: block (WRTEN_SX = '1' and A = "100101")
-  begin
-    RAM37_RX <= guarded D;
-  end block;
-
-  wr_38: block (WRTEN_SX = '1' and A = "100110")
-  begin
-    RAM38_RX <= guarded D;
-  end block;
-
-  wr_39: block (WRTEN_SX = '1' and A = "100111")
-  begin
-    RAM39_RX <= guarded D;
-  end block;
-
-  wr_40: block (WRTEN_SX = '1' and A = "101000")
-  begin
-    RAM40_RX <= guarded D;
-  end block;
-
-  wr_41: block (WRTEN_SX = '1' and A = "101001")
-  begin
-    RAM41_RX <= guarded D;
-  end block;
-
-  wr_42: block (WRTEN_SX = '1' and A = "101010")
-  begin
-    RAM42_RX <= guarded D;
-  end block;
-
-  wr_43: block (WRTEN_SX = '1' and A = "101011")
-  begin
-    RAM43_RX <= guarded D;
-  end block;
-
-  wr_44: block (WRTEN_SX = '1' and A = "101100")
-  begin
-    RAM44_RX <= guarded D;
-  end block;
-
-  wr_45: block (WRTEN_SX = '1' and A = "101101")
-  begin
-    RAM45_RX <= guarded D;
-  end block;
-
-  wr_46: block (WRTEN_SX = '1' and A = "101110")
-  begin
-    RAM46_RX <= guarded D;
-  end block;
-
-  wr_47: block (WRTEN_SX = '1' and A = "101111")
-  begin
-    RAM47_RX <= guarded D;
-  end block;
-
-  wr_48: block (WRTEN_SX = '1' and A = "110000")
-  begin
-    RAM48_RX <= guarded D;
-  end block;
-
-  wr_49: block (WRTEN_SX = '1' and A = "110001")
-  begin
-    RAM49_RX <= guarded D;
-  end block;
-  wr_50: block (WRTEN_SX = '1' and A = "110010")
-  begin
-    RAM50_RX <= guarded D;
-  end block;
-
-  wr_51: block (WRTEN_SX = '1' and A = "110011")
-  begin
-    RAM51_RX <= guarded D;
-  end block;
-
-  wr_52: block (WRTEN_SX = '1' and A = "110100")
-  begin
-    RAM52_RX <= guarded D;
-  end block;
-
-  wr_53: block (WRTEN_SX = '1' and A = "110101")
-  begin
-    RAM53_RX <= guarded D;
-  end block;
-
-  wr_54: block (WRTEN_SX = '1' and A = "110110")
-  begin
-    RAM54_RX <= guarded D;
-  end block;
-
-  wr_55: block (WRTEN_SX = '1' and A = "110111")
-  begin
-    RAM55_RX <= guarded D;
-  end block;
-
-  wr_56: block (WRTEN_SX = '1' and A = "111000")
-  begin
-    RAM56_RX <= guarded D;
-  end block;
-
-  wr_57: block (WRTEN_SX = '1' and A = "111001")
-  begin
-    RAM57_RX <= guarded D;
-  end block;
-
-  wr_58: block (WRTEN_SX = '1' and A = "111010")
-  begin
-    RAM58_RX <= guarded D;
-  end block;
-
-  wr_59: block (WRTEN_SX = '1' and A = "111011")
-  begin
-    RAM59_RX <= guarded D;
-  end block;
-
-  wr_60: block (WRTEN_SX = '1' and A = "111100")
-  begin
-    RAM60_RX <= guarded D;
-  end block;
-
-  wr_61: block (WRTEN_SX = '1' and A = "111101")
-  begin
-    RAM61_RX <= guarded D;
-  end block;
-
-  wr_62: block (WRTEN_SX = '1' and A = "111110")
-  begin
-    RAM62_RX <= guarded D;
-  end block;
-
-  wr_63: block (WRTEN_SX = '1' and A = "111111")
-  begin
-    RAM63_RX <= guarded D;
-  end block;
-
-  with A (5 downto 0)  select
-  READ_SX <= RAM0_RX  when "000000",
-             RAM1_RX  when "000001",
-             RAM2_RX  when "000010",
-             RAM3_RX  when "000011",
-             RAM4_RX  when "000100",
-             RAM5_RX  when "000101",
-             RAM6_RX  when "000110",
-             RAM7_RX  when "000111",
-             RAM8_RX  when "001000",
-             RAM9_RX  when "001001",
-             RAM10_RX when "001010",
-             RAM11_RX when "001011",
-             RAM12_RX when "001100",
-             RAM13_RX when "001101",
-             RAM14_RX when "001110",
-             RAM15_RX when "001111",
-             RAM16_RX when "010000",
-             RAM17_RX when "010001",
-             RAM18_RX when "010010",
-             RAM19_RX when "010011",
-             RAM20_RX when "010100",
-             RAM21_RX when "010101",
-             RAM22_RX when "010110",
-             RAM23_RX when "010111",
-             RAM24_RX when "011000",
-             RAM25_RX when "011001",
-             RAM26_RX when "011010",
-             RAM27_RX when "011011",
-             RAM28_RX when "011100",
-             RAM29_RX when "011101",
-             RAM30_RX when "011110",
-             RAM31_RX when "011111",
-             RAM32_RX when "100000",
-             RAM33_RX when "100001",
-             RAM34_RX when "100010",
-             RAM35_RX when "100011",
-             RAM36_RX when "100100",
-             RAM37_RX when "100101",
-             RAM38_RX when "100110",
-             RAM39_RX when "100111",
-             RAM40_RX when "101000",
-             RAM41_RX when "101001",
-             RAM42_RX when "101010",
-             RAM43_RX when "101011",
-             RAM44_RX when "101100",
-             RAM45_RX when "101101",
-             RAM46_RX when "101110",
-             RAM47_RX when "101111",
-             RAM48_RX when "110000",
-             RAM49_RX when "110001",
-             RAM50_RX when "110010",
-             RAM51_RX when "110011",
-             RAM52_RX when "110100",
-             RAM53_RX when "110101",
-             RAM54_RX when "110110",
-             RAM55_RX when "110111",
-             RAM56_RX when "111000",
-             RAM57_RX when "111001",
-             RAM58_RX when "111010",
-             RAM59_RX when "111011",
-             RAM60_RX when "111100",
-             RAM61_RX when "111101",
-             RAM62_RX when "111110",
-             RAM63_RX when "111111",
-             '0'      when others;
-
-  wr_q : block (E_N = '0' and W_N = '1')
-  begin
-   Q <= guarded READ_SX;
-  end block;
-
-end FUNCTIONAL ;
diff --git a/alliance/share/tutorials/dlxm/sr64_32a.vst b/alliance/share/tutorials/dlxm/sr64_32a.vst
deleted file mode 100644
index 113e61ac..00000000
--- a/alliance/share/tutorials/dlxm/sr64_32a.vst
+++ /dev/null
@@ -1,86 +0,0 @@
-
--- ### -------------------------------------------------------------- ###
--- #									#
--- # file	: sr64_32a.vst                                          #
--- # date	: 1993		               				#
--- # version	: v0.0							#
--- #									#
--- # origin	: this description has been developed by CAO-VLSI team	#
--- #		  at MASI laboratory, University Pierre et Marie Curie	#
--- #		  URA CNRS 818, Institut Blaise Pascal			#
--- #		  4 Place Jussieu 75252 Paris Cedex 05 - France		#
--- # E-mail      :      cao-vlsi@masi.ibp.fr                            #
--- #									#
--- # descr.	: structural description of a ram 64*32.       		#
--- #									#
--- ### -------------------------------------------------------------- ###
-
-entity sr64_32a is
-
-  port (
-       E_N         : in    bit_vector ( 0     to 3)    ;
-       W_N         : in    bit                         ;
-       DAT         : inout mux_vector (31 downto 0) bus;
-       ADR         : in    bit_vector ( 5 downto 0)    ;
-       VDD         : in    bit                         ;
-       VSS         : in    bit
-       );
-
-end sr64_32a;
-
-architecture STRUCTURAL of sr64_32a is
-
-  component sr64_8a
-    port (
-         E_N         : in    bit                        ;
-         W_N         : in    bit                        ;
-         DAT         : inout mux_vector (7 downto 0) bus;
-         ADR         : in    bit_vector (5 downto 0)    ;
-         VDD         : in    bit                        ;
-         VSS         : in    bit
-         );
-  end component;
-  
-begin
-
-  byte0 : sr64_8a
-    port map(
-            E_N => E_N (0)            ,
-            W_N => W_N                ,
-            DAT => DAT (31 downto 24) ,
-            ADR => ADR                ,
-            VDD => VDD                ,
-            VSS => VSS
-         );
-
-  byte1 : sr64_8a
-    port map(
-            E_N => E_N (1)            ,
-            W_N => W_N                ,
-            DAT => DAT (23 downto 16) ,
-            ADR => ADR                ,
-            VDD => VDD                ,
-            VSS => VSS
-         );
-
-  byte2 : sr64_8a
-    port map(
-            E_N => E_N (2)            ,
-            W_N => W_N                ,
-            DAT => DAT (15 downto  8) ,
-            ADR => ADR                ,
-            VDD => VDD                ,
-            VSS => VSS
-         );
-
-  byte3 : sr64_8a
-    port map(
-            E_N => E_N (3)            ,
-            W_N => W_N                ,
-            DAT => DAT ( 7 downto  0) ,
-            ADR => ADR                ,
-            VDD => VDD                ,
-            VSS => VSS
-         );
-
-end ;
diff --git a/alliance/share/tutorials/dlxm/sr64_8a.vst b/alliance/share/tutorials/dlxm/sr64_8a.vst
deleted file mode 100644
index 6e964a66..00000000
--- a/alliance/share/tutorials/dlxm/sr64_8a.vst
+++ /dev/null
@@ -1,135 +0,0 @@
-
--- ### -------------------------------------------------------------- ###
--- #									#
--- # file	: sr64_8a.vst                                           #
--- # date	: 1993   						#
--- # version	: v0.0							#
--- #									#
--- # origin	: this description has been developed by CAO-VLSI team	#
--- #		  at MASI laboratory, University Pierre et Marie Curie	#
--- #		  URA CNRS 818, Institut Blaise Pascal			#
--- #		  4 Place Jussieu 75252 Paris Cedex 05 - France		#
--- # E-mail      :      cao-vlsi@masi.ibp.fr                            #
--- #									#
--- # descr.	: structural description of a ram 64*8.                 # 
--- #									#
--- ### -------------------------------------------------------------- ###
-
-entity sr64_8a is
-
-  port (
-       E_N         : in    bit                         ;
-       W_N         : in    bit                         ;
-       DAT         : inout mux_vector ( 7 downto 0) bus;
-       ADR         : in    bit_vector ( 5 downto 0)    ;
-       VDD         : in    bit                         ;
-       VSS         : in    bit
-       );
-
-end sr64_8a;
-
-architecture STRUCTURAL of sr64_8a is
-
-  component sr64_1a
-    port (
-         E_N         : in  bit                        ;
-         W_N         : in  bit                        ;
-         D           : in  bit                        ;
-         Q           : out mux_bit                 bus;
-         A           : in  bit_vector (5 downto 0)    ;
-         VDD         : in  bit                        ;
-         VSS         : in  bit
-         );
-  end component;
-  
-begin
-
-  bit7 : sr64_1a
-    port map (
-             E_N => E_N     ,
-             W_N => W_N     ,
-             D   => DAT (7) ,
-             Q   => DAT (7) ,
-             A   => ADR     ,
-             VDD => VDD     ,
-             VSS => VSS
-             );
-
-  bit6 : sr64_1a
-    port map (
-             E_N => E_N     ,
-             W_N => W_N     ,
-             D   => DAT (6) ,
-             Q   => DAT (6) ,
-             A   => ADR     ,
-             VDD => VDD     ,
-             VSS => VSS
-             );
-
-  bit5 : sr64_1a
-    port map (
-             E_N => E_N     ,
-             W_N => W_N     ,
-             D   => DAT (5) ,
-             Q   => DAT (5) ,
-             A   => ADR     ,
-             VDD => VDD     ,
-             VSS => VSS
-             );
-
-  bit4 : sr64_1a
-    port map (
-             E_N => E_N     ,
-             W_N => W_N     ,
-             D   => DAT (4) ,
-             Q   => DAT (4) ,
-             A   => ADR     ,
-             VDD => VDD     ,
-             VSS => VSS
-             );
-
-  bit3 : sr64_1a
-    port map (
-             E_N => E_N     ,
-             W_N => W_N     ,
-             D   => DAT (3) ,
-             Q   => DAT (3) ,
-             A   => ADR     ,
-             VDD => VDD     ,
-             VSS => VSS
-             );
-
-  bit2 : sr64_1a
-    port map (
-             E_N => E_N     ,
-             W_N => W_N     ,
-             D   => DAT (2) ,
-             Q   => DAT (2) ,
-             A   => ADR     ,
-             VDD => VDD     ,
-             VSS => VSS
-             );
-
-  bit1 : sr64_1a
-    port map (
-             E_N => E_N     ,
-             W_N => W_N     ,
-             D   => DAT (1) ,
-             Q   => DAT (1) ,
-             A   => ADR     ,
-             VDD => VDD     ,
-             VSS => VSS
-             );
-
-  bit0 : sr64_1a
-    port map (
-             E_N => E_N     ,
-             W_N => W_N     ,
-             D   => DAT (0) ,
-             Q   => DAT (0) ,
-             A   => ADR     ,
-             VDD => VDD     ,
-             VSS => VSS
-             );
-
-end ;
diff --git a/alliance/share/tutorials/dlxm/stock_asm/add000.s b/alliance/share/tutorials/dlxm/stock_asm/add000.s
deleted file mode 100644
index 7a7c15c2..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/add000.s
+++ /dev/null
@@ -1,58 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: add000.s						#
-;  # date	: Oct 21 1994						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (RESET)				#
-	;  ###--------------------------------------------------------###
-
-reset_mask	equ	X"0008"
-system_stack	equ	X"80000000"
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler:
-		j	handler_body
-		nop
-return:
-		rfe				; return from exception
-		nop
-
-
-		org	X"ffffff00"
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-other_causes	j	other_causes
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog
-		movi2s	iar, r29
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/add000.u b/alliance/share/tutorials/dlxm/stock_asm/add000.u
deleted file mode 100644
index ddd7ff99..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/add000.u
+++ /dev/null
@@ -1,36 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: add000.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   signed addition						#
-	;  ###--------------------------------------------------------###
-
-val1		equ	X"000a"
-val2		equ	X"0002"
-
-		org	X"7fffff00"
-		start	init
-
-init:
-
-		addi	r1 , r0 , val1
-		addi	r2 , r0 , val2
-		add	r3 , r2 , r1
-
-		seqi	r5 , r3 , (val1 + val2)
-		bnez	r5      , good
-		nop
-		j	bad
-		nop
-
-		org	X"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/add001.s b/alliance/share/tutorials/dlxm/stock_asm/add001.s
deleted file mode 100644
index 6603fd46..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/add001.s
+++ /dev/null
@@ -1,58 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: add001.s						#
-;  # date	: Oct 21 1994						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (RESET)				#
-	;  ###--------------------------------------------------------###
-
-reset_mask	equ	X"0008"
-system_stack	equ	X"80000000"
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler:
-		j	handler_body
-		nop
-return:
-		rfe				; return from exception
-		nop
-
-
-		org	X"ffffff00"
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-other_causes	j	other_causes
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog
-		movi2s	iar, r29
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/add001.u b/alliance/share/tutorials/dlxm/stock_asm/add001.u
deleted file mode 100644
index ddaa56db..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/add001.u
+++ /dev/null
@@ -1,34 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: add001.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   signed addition						#
-	;  ###--------------------------------------------------------###
-
-val		equ	X"0002"
-
-		org	X"7fffff00"
-		start	init
-
-init:
-		addi	r1 , r0 , val
-		addi	r2 , r0 , val
-		add	r3 , r2 , r1
-
-		seqi	r11, r3 , (val + val)
-		bnez	r11     , good
-		nop
-		j	bad
-		nop
-
-		org	X"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/add002.s b/alliance/share/tutorials/dlxm/stock_asm/add002.s
deleted file mode 100644
index cae22b60..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/add002.s
+++ /dev/null
@@ -1,58 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: add002.s						#
-;  # date	: Oct 21 1994						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (RESET)				#
-	;  ###--------------------------------------------------------###
-
-reset_mask	equ	X"0008"
-system_stack	equ	X"80000000"
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler:
-		j	handler_body
-		nop
-return:
-		rfe				; return from exception
-		nop
-
-
-		org	X"ffffff00"
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-other_causes	j	other_causes
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog
-		movi2s	iar, r29
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/add002.u b/alliance/share/tutorials/dlxm/stock_asm/add002.u
deleted file mode 100644
index 5dda8d81..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/add002.u
+++ /dev/null
@@ -1,35 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: add002.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   signed addition						#
-	;  ###--------------------------------------------------------###
-
-val1		equ	X"1000"
-val2		equ	X"f000"
-
-		org	X"7fffff00"
-		start	init
-
-init:
-		addi	r11, r0 , val1
-		addi	r12, r0 , val2
-		add	r13, r12, r11
-
-		seqi	r6 , r13, (val1 + val2)
-		bnez	r6 , good
-		nop
-		j	bad
-		nop
-
-		org	X"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/add003.s b/alliance/share/tutorials/dlxm/stock_asm/add003.s
deleted file mode 100644
index 7ff56610..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/add003.s
+++ /dev/null
@@ -1,58 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: add003.s						#
-;  # date	: Oct 21 1994						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (RESET)				#
-	;  ###--------------------------------------------------------###
-
-reset_mask	equ	X"0008"
-system_stack	equ	X"80000000"
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler:
-		j	handler_body
-		nop
-return:
-		rfe				; return from exception
-		nop
-
-
-		org	X"ffffff00"
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-other_causes	j	other_causes
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog
-		movi2s	iar, r29
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/add003.u b/alliance/share/tutorials/dlxm/stock_asm/add003.u
deleted file mode 100644
index 8467ee68..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/add003.u
+++ /dev/null
@@ -1,41 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: add003.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   signed addition						#
-	;  ###--------------------------------------------------------###
-
-val1		equ	X"f1c1"
-val2		equ	X"1112"
-
-		org	X"7fffff00"
-		start	init
-
-init:
-		addi	r1 , r0 , val1
-		addi	r2 , r0 , val2
-
-		addi	r3 , r1 , 1
-		addi	r4 , r2 , 2
-		add	r17, r3 , r4
-
-		lhi	r29     , (val1 + val2) + 3
-		srli	r29, r29, 16
-		seq	r20, r17, r29
-
-		bnez	r20, good
-		nop
-		j	bad
-		nop
-
-		org	X"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/add004.s b/alliance/share/tutorials/dlxm/stock_asm/add004.s
deleted file mode 100644
index b708be2d..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/add004.s
+++ /dev/null
@@ -1,58 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: add004.s						#
-;  # date	: Oct 21 1994						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (RESET)				#
-	;  ###--------------------------------------------------------###
-
-reset_mask	equ	X"0008"
-system_stack	equ	X"80000000"
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler:
-		j	handler_body
-		nop
-return:
-		rfe				; return from exception
-		nop
-
-
-		org	X"ffffff00"
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-other_causes	j	other_causes
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog
-		movi2s	iar, r29
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/add004.u b/alliance/share/tutorials/dlxm/stock_asm/add004.u
deleted file mode 100644
index c3795b9e..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/add004.u
+++ /dev/null
@@ -1,40 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: add004.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   signed substraction					#
-	;  ###--------------------------------------------------------###
-
-limit		equ	 7
-first		equ	10
-
-		org	X"7fffff00"
-		start	init
-
-init :
-		loadi	r1      , limit
-		loadi	r2      , first
-
-loop :
-		subi	r2 , r2 , 1
-		sgt	r3 , r2 , r1
-		bnez	r3 , loop
-		nop
-
-		seq	r10, r2, r1
-		beqz	r10, bad
-		nop
-		j	good
-		nop
-
-		org	X"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/add005.s b/alliance/share/tutorials/dlxm/stock_asm/add005.s
deleted file mode 100644
index c520051d..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/add005.s
+++ /dev/null
@@ -1,58 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: add005.s						#
-;  # date	: Oct 21 1994						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (RESET)				#
-	;  ###--------------------------------------------------------###
-
-reset_mask	equ	X"0008"
-system_stack	equ	X"80000000"
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler:
-		j	handler_body
-		nop
-return:
-		rfe				; return from exception
-		nop
-
-
-		org	X"ffffff00"
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-other_causes	j	other_causes
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog
-		movi2s	iar, r29
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/add005.u b/alliance/share/tutorials/dlxm/stock_asm/add005.u
deleted file mode 100644
index 64a93672..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/add005.u
+++ /dev/null
@@ -1,63 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: add005.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   signed addition						#
-	;  #      each register is initialized with its number		#
-	;  ###--------------------------------------------------------###
-
-increment	equ	1
-
-		org	X"7fffff00"
-		start	init
-
-init:
-		addi	r1 , r0 , increment
-		addi	r2 , r1 , increment
-		addi	r3 , r2 , increment
-		addi	r4 , r3 , increment
-		addi	r5 , r4 , increment
-		addi	r6 , r5 , increment
-		addi	r7 , r6 , increment
-		addi	r8 , r7 , increment
-		addi	r9 , r8 , increment
-		addi	r10, r9 , increment
-		addi	r11, r10, increment
-		addi	r12, r11, increment
-		addi	r13, r12, increment
-		addi	r14, r13, increment
-		addi	r15, r14, increment
-		addi	r16, r15, increment
-		addi	r17, r16, increment
-		addi	r18, r17, increment
-		addi	r19, r18, increment
-		addi	r20, r19, increment
-		addi	r21, r20, increment
-		addi	r22, r21, increment
-		addi	r23, r22, increment
-		addi	r24, r23, increment
-		addi	r25, r24, increment
-		addi	r26, r25, increment
-		addi	r27, r26, increment
-		addi	r28, r27, increment
-		addi	r29, r28, increment
-		addi	r30, r29, increment
-		addi	r31, r30, increment
-
-		seqi	r31, r31, (increment * 31)
-		bnez	r31     , good
-		nop
-		j	bad
-		nop
-
-		org	X"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/and000.s b/alliance/share/tutorials/dlxm/stock_asm/and000.s
deleted file mode 100644
index 36bbe1d7..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/and000.s
+++ /dev/null
@@ -1,58 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: and000.s						#
-;  # date	: Oct 21 1994						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (RESET)				#
-	;  ###--------------------------------------------------------###
-
-reset_mask	equ	X"0008"
-system_stack	equ	X"80000000"
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler:
-		j	handler_body
-		nop
-return:
-		rfe				; return from exception
-		nop
-
-
-		org	X"ffffff00"
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-other_causes	j	other_causes
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog
-		movi2s	iar, r29
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/and000.u b/alliance/share/tutorials/dlxm/stock_asm/and000.u
deleted file mode 100644
index 054b977f..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/and000.u
+++ /dev/null
@@ -1,65 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: adn000.u						#
-;  # date	: Nov  3 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-		org	X"7fffff00"
-		start   init	
-
-	;  ###--------------------------------------------------------###
-	;  #   Test of AND instruction in 4 step                        #
-	;  ###--------------------------------------------------------###
-
-un		equ	1
-deux		equ	2
-trois		equ	3
-mask		equ	X"ffffffff"	;mask = -1
-
-init:
-		addi	r5 , r0 , mask	;r5 = -1
-		addi	r6 , r0 , un	;r6 = 1
-	
-		and	r7 , r6 , r5	;r7 = 1
-		
-		seqi	r3 , r7 , un	;r10 = 1 if r7 = 1 , r7 = 0 else
-		beqz	r3 , bad        
-		nop		
-
-		addi	r8 , r0 , deux
-
-		and	r9 , r3 , r8	;r9 = 0
-		
-		seq	r10, r9 , r0	;r10 = 1 if r9 = 0, r10 = 0 else
-		beqz	r10, bad        
-		nop		
-
-		addi	r5 , r0 , un	;r5 = 1
-		addi	r6 , r0 , trois	;r6 = 3
-
-		and	r8 , r6 , r5	;r8 = 1
-
-		seq	r10, r8 , r5	;r10 = 1 if r8 = 1, r10 = 0 else
-		beqz	r10, bad
-		nop		
-
-		addi	r7 , r0 , deux	;r7 = 2
-		addi	r9 , r0 , trois	;r9 = 3
-
-		and	r6 , r9 , r7	;r6 = 2
-		
-		seq	r10, r6 , r7	;r10 = 1 if r6 = 2, r10 = 0 else
-		beqz	r10, bad	
-		nop		
-
-		j	good
-		nop		
-
-		org	X"7ffffff0"
-good		j 	good
-		nop		
-bad		j	bad
-		nop		
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/bne000.s b/alliance/share/tutorials/dlxm/stock_asm/bne000.s
deleted file mode 100644
index 03c7d759..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/bne000.s
+++ /dev/null
@@ -1,58 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: bne000.s						#
-;  # date	: Oct 21 1994						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (RESET)				#
-	;  ###--------------------------------------------------------###
-
-reset_mask	equ	X"0008"
-system_stack	equ	X"80000000"
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler:
-		j	handler_body
-		nop
-return:
-		rfe				; return from exception
-		nop
-
-
-		org	X"ffffff00"
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-other_causes	j	other_causes
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog
-		movi2s	iar, r29
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/bne000.u b/alliance/share/tutorials/dlxm/stock_asm/bne000.u
deleted file mode 100644
index 8b1aa21d..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/bne000.u
+++ /dev/null
@@ -1,37 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: bne000.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   conditional branch					#
-	;  ###--------------------------------------------------------###
-
-val1		equ	X"000057a1"
-val2		equ	X"3409a339"
-
-		org	X"7fffff00"
-		start	init
-
-init :
-		loadi	r7 , VAL1
-		loadi	r8 , VAL2
-		loadi	r9 , (VAL1 - VAL2)
-
-		sub	r10 , r7 , r8
-
-		sne	r20 , r9 , r10
-		bnez	r20 , bad
-		nop
-		j	good
-		nop
-
-		org	X"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/exc000.s b/alliance/share/tutorials/dlxm/stock_asm/exc000.s
deleted file mode 100644
index dcb99399..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/exc000.s
+++ /dev/null
@@ -1,78 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: exc000.s						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   exceptions :						#
-	;  #     - data address miss alignment (when loading a word)	#
-	;  ###--------------------------------------------------------###
-
-data_adr_viol	equ	X"0400"			; data address violation
-reset_mask	equ	X"0008"			; reset
-
-system_stack	equ	X"80000000"		; system stack address
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler :
-		j	handler_body
-		nop
-return		rfe
-		nop
-
-		org	X"ffffff00"
-
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-		movs2i	r29, sr
-		andi	r29, r29, data_adr_viol	; data address violation ?
-		bnez	r29, restore_return_adr
-		nop
-
-other_causes	j	other_causes
-		nop
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog		; prepare return address
-		movi2s	iar, r29		; copy user program address
-						;+into IAR
-		j	return
-		nop
-
-	;  ###--------------------------------------------------------###
-	;  #   restore return address before returning (from EXCEPTION)	#
-	;  # to the user program (address must be saved by the user	#
-	;  # prior to the EXCEPTION in r31)				#
-	;  ###--------------------------------------------------------###
-
-restore_return_adr:
-		movi2s	iar, r31
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/exc000.u b/alliance/share/tutorials/dlxm/stock_asm/exc000.u
deleted file mode 100644
index a9f0915f..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/exc000.u
+++ /dev/null
@@ -1,51 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: exc000.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   exceptions :						#
-	;  #     - data address miss alignment (when loading a word)	#
-	;  ###--------------------------------------------------------###
-
-adr		equ	X"00000051"		; miss aligned word address
-data		equ	X"9043ad6b"		; data
-
-		org	X"7fffff00"
-		start	init
-
-init:
-		loadi	r31, back_from_exception
-		loadi	r1 , adr		; word's address
-		loadi	r2 , data		; init. r2 with a data
-		loadi	r3 , data		; init. r3 with the same value
-
-	;  ###--------------------------------------------------------###
-	;  #   load a word at a miss aligned address (data address	#
-	;  # alignment exception)					#
-	;  ###--------------------------------------------------------###
-
-		lw	r2 , r1 , 0		; EXCEPTION (alignement)
-
-	;  ###--------------------------------------------------------###
-	;  #   check that the load has faild and the content of the	#
-	;  # register has not been altered				#
-	;  ###--------------------------------------------------------###
-
-back_from_exception:
-		seq	r4 , r2 , r3		; check that the lw has failed
-		bnez	r4 , good		; jump to good if OK
-		nop
-		j	bad
-		nop
-
-		org	X"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/exc001.s b/alliance/share/tutorials/dlxm/stock_asm/exc001.s
deleted file mode 100644
index 883165ef..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/exc001.s
+++ /dev/null
@@ -1,78 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: exc001.s						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   exceptions :						#
-	;  #     - data address miss alignment (when storing a word)	#
-	;  ###--------------------------------------------------------###
-
-data_adr_viol	equ	X"0400"			; data address violation
-reset_mask	equ	X"0008"			; reset
-
-system_stack	equ	X"80000000"		; system stack address
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler :
-		j	handler_body
-		nop
-return		rfe
-		nop
-
-		org	X"ffffff00"
-
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-		movs2i	r29, sr
-		andi	r29, r29, data_adr_viol	; data address violation ?
-		bnez	r29, restore_return_adr
-		nop
-
-other_causes	j	other_causes
-		nop
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog		; prepare return address
-		movi2s	iar, r29		; copy user program address
-						;+into IAR
-		j	return
-		nop
-
-	;  ###--------------------------------------------------------###
-	;  #   restore return address before returning (from EXCEPTION)	#
-	;  # to the user program (address must be saved by the user	#
-	;  # prior to the EXCEPTION in r31)				#
-	;  ###--------------------------------------------------------###
-
-restore_return_adr:
-		movi2s	iar, r31
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/exc001.u b/alliance/share/tutorials/dlxm/stock_asm/exc001.u
deleted file mode 100644
index f4219484..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/exc001.u
+++ /dev/null
@@ -1,79 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: exc001.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   exceptions :						#
-	;  #     - data address miss alignment (when storing a word)	#
-	;  ###--------------------------------------------------------###
-
-adr		equ	X"00000051"		; miss aligned word address
-data		equ	X"9043ad6b"		; data
-
-		org	X"7fffff00"
-		start	init
-
-init:
-		loadi	r31, back_from_exception
-		loadi	r1 , adr		; word's address in r1
-		loadi	r2 , data		; data in r2
-		loadi	r3 , data		; same data in r3
-		loadi	r4 , data ^ X"ffffffff"	; complemented data in r4
-
-	;  ###--------------------------------------------------------###
-	;  #   store the word byte by byte to initialize the memory	#
-	;  # location							#
-	;  ###--------------------------------------------------------###
-
-		sb	r2 , r1 , 3
-		srli	r2 , r2 , 8
-		sb	r2 , r1 , 2
-		srli	r2 , r2 , 8
-		sb	r2 , r1 , 1
-		srli	r2 , r2 , 8
-		sb	r2 , r1 , 0
-
-	;  ###--------------------------------------------------------###
-	;  #   store word at a miss aligned address			#
-	;  ###--------------------------------------------------------###
-
-		sw	r4 , r1 , 0		; EXCEPTION (alignment)
-
-	;  ###--------------------------------------------------------###
-	;  #   after returning from exception, read byte by byte the	#
-	;  # memory location and rebuild the word to check that the	#
-	;  # faulty store word has not modified the memory		#
-	;  ###--------------------------------------------------------###
-
-back_from_exception:
-		lbu	r2 , r1 , 0
-		slli	r5 , r2 , 8
-		lbu	r2 , r1 , 1
-		or	r5 , r5 , r2
-		slli	r5 , r5 , 8
-		lbu	r2 , r1 , 2
-		or	r5 , r5 , r2
-		slli	r5 , r5 , 8
-		lbu	r2 , r1 , 3
-		or	r5 , r5 , r2
-
-	;  ###--------------------------------------------------------###
-	;  #   if the read word is correct branch to good		#
-	;  ###--------------------------------------------------------###
-
-		seq	r11, r5, r3
-		beqz	r11, bad
-		nop
-		j	good
-		nop
-
-		org	X"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/exc002.s b/alliance/share/tutorials/dlxm/stock_asm/exc002.s
deleted file mode 100644
index c7e372bf..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/exc002.s
+++ /dev/null
@@ -1,78 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: exc002.s						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   exceptions :						#
-	;  #     - overflow (when adding positive numbers)		#
-	;  ###--------------------------------------------------------###
-
-overflow	equ	X"0800"			; arithmetic overflow
-reset_mask	equ	X"0008"			; reset
-
-system_stack	equ	X"80000000"		; system stack address
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler :
-		j	handler_body
-		nop
-return		rfe
-		nop
-
-		org	X"ffffff00"
-
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-		movs2i	r29, sr
-		andi	r29, r29, overflow	; arithmetic overflow ?
-		bnez	r29, restore_return_adr
-		nop
-
-other_causes	j	other_causes
-		nop
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog		; prepare return address
-		movi2s	iar, r29		; copy user program address
-						;+into IAR
-		j	return
-		nop
-
-	;  ###--------------------------------------------------------###
-	;  #   restore return address before returning (from EXCEPTION)	#
-	;  # to the user program (address must be saved by the user	#
-	;  # prior to the EXCEPTION in r31)				#
-	;  ###--------------------------------------------------------###
-
-restore_return_adr:
-		movi2s	iar, r31
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/exc002.u b/alliance/share/tutorials/dlxm/stock_asm/exc002.u
deleted file mode 100644
index ee92f416..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/exc002.u
+++ /dev/null
@@ -1,47 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: exc002.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   exceptions :						#
-	;  #     - arithmetic overflow (addition)			#
-	;  ###--------------------------------------------------------###
-
-data		equ	X"6234fe80"		; a big positive data
-
-		org	X"7fffff00"
-		start	init
-
-init:
-		loadi	r31, back_from_exception
-		loadi	r10, data		; big positive data in r10
-		loadi	r11, data		; same data in r11
-
-	;  ###--------------------------------------------------------###
-	;  #   addtion generating an overflow				#
-	;  ###--------------------------------------------------------###
-
-		add	r10, r10, r10		; EXCEPTION (overflow)
-
-	;  ###--------------------------------------------------------###
-	;  #   after returning from exception check that r10 has not	#
-	;  # been altered						#
-	;  ###--------------------------------------------------------###
-
-back_from_exception:
-		sne	r20, r10, r11		; check that add has failed
-		bnez	r20, bad
-		nop
-		j	good
-		nop
-
-		org	X"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/exc003.s b/alliance/share/tutorials/dlxm/stock_asm/exc003.s
deleted file mode 100644
index db101a6e..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/exc003.s
+++ /dev/null
@@ -1,78 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: exc003.s						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   exceptions :						#
-	;  #     - overflow (when substracting)				#
-	;  ###--------------------------------------------------------###
-
-overflow	equ	X"0800"			; arithmetic overflow
-reset_mask	equ	X"0008"			; reset
-
-system_stack	equ	X"80000000"		; system stack address
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler :
-		j	handler_body
-		nop
-return		rfe
-		nop
-
-		org	X"ffffff00"
-
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-		movs2i	r29, sr
-		andi	r29, r29, overflow	; arithmetic overflow ?
-		bnez	r29, restore_return_adr
-		nop
-
-other_causes	j	other_causes
-		nop
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog		; prepare return address
-		movi2s	iar, r29		; copy user program address
-						;+into IAR
-		j	return
-		nop
-
-	;  ###--------------------------------------------------------###
-	;  #   restore return address before returning (from EXCEPTION)	#
-	;  # to the user program (address must be saved by the user	#
-	;  # prior to the EXCEPTION in r31)				#
-	;  ###--------------------------------------------------------###
-
-restore_return_adr:
-		movi2s	iar, r31
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/exc003.u b/alliance/share/tutorials/dlxm/stock_asm/exc003.u
deleted file mode 100644
index f23d639f..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/exc003.u
+++ /dev/null
@@ -1,48 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: exc002.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   exceptions :						#
-	;  #     - arithmetic overflow (substract)			#
-	;  ###--------------------------------------------------------###
-
-data		equ	X"52d4aec6"		; a big positive data
-
-		org	X"7fffff00"
-		start	init
-
-init:
-		loadi	r31, back_from_exception
-		loadi	r10, data		; big positive data in r10
-		loadi	r11, data		; same data in r11
-
-	;  ###--------------------------------------------------------###
-	;  #   substract generating an overflow				#
-	;  ###--------------------------------------------------------###
-
-		sub	r12, r0 , r10
-		sub	r10, r12, r10		; EXCEPTION (overflow)
-
-	;  ###--------------------------------------------------------###
-	;  #   after returning from exception check that r10 has not	#
-	;  # been altered						#
-	;  ###--------------------------------------------------------###
-
-back_from_exception:
-		sne	r20, r10, r11		; check that add has failed
-		bnez	r20, bad
-		nop
-		j	good
-		nop
-
-		org	X"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/exc004.s b/alliance/share/tutorials/dlxm/stock_asm/exc004.s
deleted file mode 100644
index 4da15bcd..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/exc004.s
+++ /dev/null
@@ -1,78 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: exc004.s						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   exceptions :						#
-	;  #     - overflow (when adding negative numbers)		#
-	;  ###--------------------------------------------------------###
-
-overflow	equ	X"0800"			; arithmetic overflow
-reset_mask	equ	X"0008"			; reset
-
-system_stack	equ	X"80000000"		; system stack address
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler :
-		j	handler_body
-		nop
-return		rfe
-		nop
-
-		org	X"ffffff00"
-
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-		movs2i	r29, sr
-		andi	r29, r29, overflow	; arithmetic overflow ?
-		bnez	r29, restore_return_adr
-		nop
-
-other_causes	j	other_causes
-		nop
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog		; prepare return address
-		movi2s	iar, r29		; copy user program address
-						;+into IAR
-		j	return
-		nop
-
-	;  ###--------------------------------------------------------###
-	;  #   restore return address before returning (from EXCEPTION)	#
-	;  # to the user program (address must be saved by the user	#
-	;  # prior to the EXCEPTION in r31)				#
-	;  ###--------------------------------------------------------###
-
-restore_return_adr:
-		movi2s	iar, r31
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/exc004.u b/alliance/share/tutorials/dlxm/stock_asm/exc004.u
deleted file mode 100644
index 97df795d..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/exc004.u
+++ /dev/null
@@ -1,47 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: exc004.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   exceptions :						#
-	;  #     - arithmetic overflow (addition)			#
-	;  ###--------------------------------------------------------###
-
-data		equ	X"b2305ec0"		; a big negative data
-
-		org	X"7fffff00"
-		start	init
-
-init:
-		loadi	r31, back_from_exception
-		loadi	r10, data		; big positive data in r10
-		loadi	r11, data		; same data in r11
-
-	;  ###--------------------------------------------------------###
-	;  #   addtion generating an overflow				#
-	;  ###--------------------------------------------------------###
-
-		add	r10, r10, r10		; EXCEPTION (overflow)
-
-	;  ###--------------------------------------------------------###
-	;  #   after returning from exception check that r10 has not	#
-	;  # been altered						#
-	;  ###--------------------------------------------------------###
-
-back_from_exception:
-		sne	r20, r10, r11		; check that add has failed
-		bnez	r20, bad
-		nop
-		j	good
-		nop
-
-		org	X"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/exc005.s b/alliance/share/tutorials/dlxm/stock_asm/exc005.s
deleted file mode 100644
index faf1aa15..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/exc005.s
+++ /dev/null
@@ -1,78 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: exc005.s						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   exceptions :						#
-	;  #     - overflow (when substracting)				#
-	;  ###--------------------------------------------------------###
-
-overflow	equ	X"0800"			; arithmetic overflow
-reset_mask	equ	X"0008"			; reset
-
-system_stack	equ	X"80000000"		; system stack address
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler :
-		j	handler_body
-		nop
-return		rfe
-		nop
-
-		org	X"ffffff00"
-
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-		movs2i	r29, sr
-		andi	r29, r29, overflow	; arithmetic overflow ?
-		bnez	r29, restore_return_adr
-		nop
-
-other_causes	j	other_causes
-		nop
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog		; prepare return address
-		movi2s	iar, r29		; copy user program address
-						;+into IAR
-		j	return
-		nop
-
-	;  ###--------------------------------------------------------###
-	;  #   restore return address before returning (from EXCEPTION)	#
-	;  # to the user program (address must be saved by the user	#
-	;  # prior to the EXCEPTION in r31)				#
-	;  ###--------------------------------------------------------###
-
-restore_return_adr:
-		movi2s	iar, r31
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/exc005.u b/alliance/share/tutorials/dlxm/stock_asm/exc005.u
deleted file mode 100644
index 55815f2c..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/exc005.u
+++ /dev/null
@@ -1,48 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: exc005.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   exceptions :						#
-	;  #     - arithmetic overflow (substract)			#
-	;  ###--------------------------------------------------------###
-
-data		equ	X"946e3d0f"		; a big negative data
-
-		org	X"7fffff00"
-		start	init
-
-init:
-		loadi	r31, back_from_exception
-		loadi	r10, data		; big positive data in r10
-		loadi	r11, data		; same data in r11
-
-	;  ###--------------------------------------------------------###
-	;  #   substract generating an overflow				#
-	;  ###--------------------------------------------------------###
-
-		sub	r12, r0 , r10
-		sub	r10, r12, r10		; EXCEPTION (overflow)
-
-	;  ###--------------------------------------------------------###
-	;  #   after returning from exception check that r10 has not	#
-	;  # been altered						#
-	;  ###--------------------------------------------------------###
-
-back_from_exception:
-		sne	r20, r10, r11		; check that add has failed
-		bnez	r20, bad
-		nop
-		j	good
-		nop
-
-		org	X"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/exc006.s b/alliance/share/tutorials/dlxm/stock_asm/exc006.s
deleted file mode 100644
index c08e4aef..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/exc006.s
+++ /dev/null
@@ -1,79 +0,0 @@
-
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: exc006.s						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   exceptions :						#
-	;  #     - illegal instruction address (alignment)		#
-	;  ###--------------------------------------------------------###
-
-inst_adr_viol	equ	X"0100"			; instruction adr violation
-reset_mask	equ	X"0008"			; reset
-
-system_stack	equ	X"80000000"		; system stack address
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler :
-		j	handler_body
-		nop
-return		rfe
-		nop
-
-		org	X"ffffff00"
-
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-		movs2i	r29, sr
-		andi	r29, r29, inst_adr_viol	; instruction adr violation ?
-		bnez	r29, restore_return_adr
-		nop
-
-other_causes	j	other_causes
-		nop
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog		; prepare return address
-		movi2s	iar, r29		; copy user program address
-						;+into IAR
-		j	return
-		nop
-
-	;  ###--------------------------------------------------------###
-	;  #   restore return address before returning (from EXCEPTION)	#
-	;  # to the user program (address must be saved by the user	#
-	;  # prior to the EXCEPTION in r31)				#
-	;  ###--------------------------------------------------------###
-
-restore_return_adr:
-		movi2s	iar, r31
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/exc006.u b/alliance/share/tutorials/dlxm/stock_asm/exc006.u
deleted file mode 100644
index fdd1c3d3..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/exc006.u
+++ /dev/null
@@ -1,36 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: exc006.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #  illegal instruction address (alignment)			#
-	;  ###--------------------------------------------------------###
-
-		org	X"7fffff00"
-		start	init
-
-init:
-		loadi	r31, back_from_exception
-		loadi	r20, target_adr + 1	; missaligned address in r20
-target_adr:
-		jr	r20			; EXCEPTION (alignment)
-		nop
-
-	;  ###--------------------------------------------------------###
-	;  #   jump to good if returned from exception			#
-	;  ###--------------------------------------------------------###
-
-back_from_exception:
-		j	good
-		nop
-		
-		org	X"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/exc007.s b/alliance/share/tutorials/dlxm/stock_asm/exc007.s
deleted file mode 100644
index 3d0af752..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/exc007.s
+++ /dev/null
@@ -1,78 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: exc007.s						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   exceptions :						#
-	;  #     - illegal instruction address (segment)		#
-	;  ###--------------------------------------------------------###
-
-inst_adr_viol	equ	X"0100"			; instruction adr violation
-reset_mask	equ	X"0008"			; reset
-
-system_stack	equ	X"80000000"		; system stack address
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler :
-		j	handler_body
-		nop
-return		rfe
-		nop
-
-		org	X"ffffff00"
-
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-		movs2i	r29, sr
-		andi	r29, r29, inst_adr_viol	; instruction adr violation ?
-		bnez	r29, restore_return_adr
-		nop
-
-other_causes	j	other_causes
-		nop
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog		; prepare return address
-		movi2s	iar, r29		; copy user program address
-						;+into IAR
-		j	return
-		nop
-
-	;  ###--------------------------------------------------------###
-	;  #   restore return address before returning (from EXCEPTION)	#
-	;  # to the user program (address must be saved by the user	#
-	;  # prior to the EXCEPTION in r31)				#
-	;  ###--------------------------------------------------------###
-
-restore_return_adr:
-		movi2s	iar, r31
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/exc007.u b/alliance/share/tutorials/dlxm/stock_asm/exc007.u
deleted file mode 100644
index cadfd5ea..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/exc007.u
+++ /dev/null
@@ -1,37 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: exc007.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #  illegal instruction address (segment)			#
-	;  ###--------------------------------------------------------###
-
-it_handler	equ	X"fffffff0"
-
-		org	X"7fffff00"
-		start	init
-
-init:
-		loadi	r31, back_from_exception
-		loadi	r20, it_handler
-		jr	r20			; EXCEPTION (segment)
-		nop
-
-	;  ###--------------------------------------------------------###
-	;  #   jump to good if returned from exception			#
-	;  ###--------------------------------------------------------###
-
-back_from_exception:
-		j	good
-		nop
-		
-		org	X"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/exc008.s b/alliance/share/tutorials/dlxm/stock_asm/exc008.s
deleted file mode 100644
index 0e9f2b22..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/exc008.s
+++ /dev/null
@@ -1,78 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: exc008.s						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   exceptions :						#
-	;  #     - illegal data address (segment)			#
-	;  ###--------------------------------------------------------###
-
-data_adr_viol	equ	X"0400"			; data address violation
-reset_mask	equ	X"0008"			; reset
-
-system_stack	equ	X"80000000"		; system stack address
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler :
-		j	handler_body
-		nop
-return		rfe
-		nop
-
-		org	X"ffffff00"
-
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-		movs2i	r29, sr
-		andi	r29, r29, data_adr_viol	; data address violation ?
-		bnez	r29, restore_return_adr
-		nop
-
-other_causes	j	other_causes
-		nop
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog		; prepare return address
-		movi2s	iar, r29		; copy user program address
-						;+into IAR
-		j	return
-		nop
-
-	;  ###--------------------------------------------------------###
-	;  #   restore return address before returning (from EXCEPTION)	#
-	;  # to the user program (address must be saved by the user	#
-	;  # prior to the EXCEPTION in r31)				#
-	;  ###--------------------------------------------------------###
-
-restore_return_adr:
-		movi2s	iar, r31
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/exc008.u b/alliance/share/tutorials/dlxm/stock_asm/exc008.u
deleted file mode 100644
index 7cab52d4..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/exc008.u
+++ /dev/null
@@ -1,51 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: exc008.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   exceptions :						#
-	;  #     - llegal data address (segment when loading)		#
-	;  ###--------------------------------------------------------###
-
-adr		equ	X"8000003c"		; data adr in system segment
-data		equ	X"9043ad6b"		; data
-
-		org	X"7fffff00"
-		start	init
-
-init:
-		loadi	r31, back_from_exception
-		loadi	r1 , adr		; word's address
-		loadi	r2 , data		; init. r2 with a data
-		loadi	r3 , data		; init. r3 with the same value
-
-	;  ###--------------------------------------------------------###
-	;  #   load a word at a miss aligned address (data address	#
-	;  # alignment exception)					#
-	;  ###--------------------------------------------------------###
-
-		lw	r2 , r1 , 0		; EXCEPTION (segment)
-
-	;  ###--------------------------------------------------------###
-	;  #   check that the load has faild and the content of the	#
-	;  # register has not been altered				#
-	;  ###--------------------------------------------------------###
-
-back_from_exception:
-		seq	r4 , r2 , r3		; check that the lw has failed
-		bnez	r4 , good		; jump to good if OK
-		nop
-		j	bad
-		nop
-
-		org	X"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/exc009.s b/alliance/share/tutorials/dlxm/stock_asm/exc009.s
deleted file mode 100644
index e6fe1a85..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/exc009.s
+++ /dev/null
@@ -1,78 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: exc009.s						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   exceptions :						#
-	;  #     - illegal instruction (when executing a movs2i)	#
-	;  ###--------------------------------------------------------###
-
-illegal_opcod	equ	X"0200"			; illegal instruction
-reset_mask	equ	X"0008"			; reset
-
-system_stack	equ	X"80000000"		; system stack address
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler :
-		j	handler_body
-		nop
-return		rfe
-		nop
-
-		org	X"ffffff00"
-
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-		movs2i	r29, sr
-		andi	r29, r29, illegal_opcod	; illegal instruction ?
-		bnez	r29, restore_return_adr
-		nop
-
-other_causes	j	other_causes
-		nop
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog		; prepare return address
-		movi2s	iar, r29		; copy user program address
-						;+into IAR
-		j	return
-		nop
-
-	;  ###--------------------------------------------------------###
-	;  #   restore return address before returning (from EXCEPTION)	#
-	;  # to the user program (address must be saved by the user	#
-	;  # prior to the EXCEPTION in r31)				#
-	;  ###--------------------------------------------------------###
-
-restore_return_adr:
-		movi2s	iar, r31
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/exc009.u b/alliance/share/tutorials/dlxm/stock_asm/exc009.u
deleted file mode 100644
index 9d6a7b49..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/exc009.u
+++ /dev/null
@@ -1,50 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: exc009.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   exceptions :						#
-	;  #     - illegal instruction (when executing a movs2i)	#
-	;  ###--------------------------------------------------------###
-
-data		equ	X"324f6b71"
-		org	X"7fffff00"
-		start	init
-
-init:
-		loadi	r31, back_from_exception
-		loadi	r1 , data		; init. r2 with a data
-		loadi	r2 , data		; init. r3 with the same value
-
-	;  ###--------------------------------------------------------###
-	;  #   move SR into r1. This must generate an exception		#
-	;  # (privileged instruction)					#
-	;  ###--------------------------------------------------------###
-
-		movs2i	r1 , sr			; EXCEPTION (privileged)
-		j	bad
-		nop
-
-	;  ###--------------------------------------------------------###
-	;  #   check that the load has faild and the content of the	#
-	;  # register has not been altered				#
-	;  ###--------------------------------------------------------###
-
-back_from_exception:
-		seq	r4 , r1 , r2		; check that the move has failed
-		bnez	r4 , good		; jump to good if OK
-		nop
-		j	bad
-		nop
-
-		org	X"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/exc010.s b/alliance/share/tutorials/dlxm/stock_asm/exc010.s
deleted file mode 100644
index f11a6067..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/exc010.s
+++ /dev/null
@@ -1,78 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: exc010.s						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   exceptions :						#
-	;  #     - illegal instruction (when executing a movs2i)	#
-	;  ###--------------------------------------------------------###
-
-illegal_opcod	equ	X"0200"			; illegal instruction
-reset_mask	equ	X"0008"			; reset
-
-system_stack	equ	X"80000000"		; system stack address
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler :
-		j	handler_body
-		nop
-return		rfe
-		nop
-
-		org	X"ffffff00"
-
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-		movs2i	r29, sr
-		andi	r29, r29, illegal_opcod	; illegal instruction ?
-		bnez	r29, restore_return_adr
-		nop
-
-other_causes	j	other_causes
-		nop
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog		; prepare return address
-		movi2s	iar, r29		; copy user program address
-						;+into IAR
-		j	return
-		nop
-
-	;  ###--------------------------------------------------------###
-	;  #   restore return address before returning (from EXCEPTION)	#
-	;  # to the user program (address must be saved by the user	#
-	;  # prior to the EXCEPTION in r31)				#
-	;  ###--------------------------------------------------------###
-
-restore_return_adr:
-		movi2s	iar, r31
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/exc010.u b/alliance/share/tutorials/dlxm/stock_asm/exc010.u
deleted file mode 100644
index 17d9ec3e..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/exc010.u
+++ /dev/null
@@ -1,47 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: exc010.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   exceptions :						#
-	;  #     - illegal instruction (when executing a movi2s)	#
-	;  ###--------------------------------------------------------###
-
-new_sr		equ	X"00000000"		; try to set system mode
-		org	X"7fffff00"
-		start	init
-
-init:
-		loadi	r31, back_from_exception
-		loadi	r1 , new_sr		; init. r2 with the desired
-						;+value of sr
-
-	;  ###--------------------------------------------------------###
-	;  #   move r1 into sr. This must generate an exception		#
-	;  # (privileged instruction)					#
-	;  ###--------------------------------------------------------###
-
-		movi2s	sr , r1			; EXCEPTION (privileged)
-		j	bad
-		nop
-
-back_from_exception:
-		loadi	r31, good
-		movi2s	sr , r1			; EXCEPTION (privileged)
-		j	bad
-		nop
-
-	;  ###--------------------------------------------------------###
-	;  ###--------------------------------------------------------###
-
-		org	X"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/jal000.s b/alliance/share/tutorials/dlxm/stock_asm/jal000.s
deleted file mode 100644
index 63a3dc02..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/jal000.s
+++ /dev/null
@@ -1,58 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: jal000.s						#
-;  # date	: Oct 21 1994						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (RESET)				#
-	;  ###--------------------------------------------------------###
-
-reset_mask	equ	X"0008"
-system_stack	equ	X"80000000"
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler:
-		j	handler_body
-		nop
-return:
-		rfe				; return from exception
-		nop
-
-
-		org	X"ffffff00"
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-other_causes	j	other_causes
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog
-		movi2s	iar, r29
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/jal000.u b/alliance/share/tutorials/dlxm/stock_asm/jal000.u
deleted file mode 100644
index bb7318b3..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/jal000.u
+++ /dev/null
@@ -1,43 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: jal000.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   jump and link						#
-	;  ###--------------------------------------------------------###
-
-const		equ	X"14feb445"
-
-		org	X"7fffff00"
-		start	init
-
-init:
-		loadi	r23, const
-		loadi	r24, (4 * const)
-
-		jal	mul2
-		nop
-		jal	mul2
-		nop
-
-		seq	r1 , r23, r24
-		beqz	r1 , bad
-		nop
-		j	good
-		nop
-
-mul2 :
-		add	r23, r23, r23
-		jr	r31
-		nop
-
-		org	X"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/jal001.s b/alliance/share/tutorials/dlxm/stock_asm/jal001.s
deleted file mode 100644
index 7b244f14..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/jal001.s
+++ /dev/null
@@ -1,58 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: jal001.s						#
-;  # date	: Oct 21 1994						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (RESET)				#
-	;  ###--------------------------------------------------------###
-
-reset_mask	equ	X"0008"
-system_stack	equ	X"80000000"
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler:
-		j	handler_body
-		nop
-return:
-		rfe				; return from exception
-		nop
-
-
-		org	X"ffffff00"
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-other_causes	j	other_causes
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog
-		movi2s	iar, r29
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/jal001.u b/alliance/share/tutorials/dlxm/stock_asm/jal001.u
deleted file mode 100644
index 9cf3390f..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/jal001.u
+++ /dev/null
@@ -1,44 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: jal000.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   jump and link						#
-	;  ###--------------------------------------------------------###
-
-data		equ	X"14feb445"
-
-		org	X"7fffff00"
-		start	init
-
-init:
-		loadi	r15, sub_prog
-		loadi	r16, data
-		loadi	r17, (data << 2)
-
-		jalr	r15
-		nop
-		jalr	r15
-		nop
-
-		seq	r30, r16, r17
-		beqz	r30, bad
-		nop
-		j	good
-		nop
-
-sub_prog :
-		slli	r16, r16, 1
-		jr	r31
-		nop
-
-		org	x"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/lb000.s b/alliance/share/tutorials/dlxm/stock_asm/lb000.s
deleted file mode 100644
index de0dfabb..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/lb000.s
+++ /dev/null
@@ -1,58 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: lb000.s						#
-;  # date	: Oct 21 1994						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (RESET)				#
-	;  ###--------------------------------------------------------###
-
-reset_mask	equ	X"0008"
-system_stack	equ	X"80000000"
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler:
-		j	handler_body
-		nop
-return:
-		rfe				; return from exception
-		nop
-
-
-		org	X"ffffff00"
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-other_causes	j	other_causes
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog
-		movi2s	iar, r29
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/lb000.u b/alliance/share/tutorials/dlxm/stock_asm/lb000.u
deleted file mode 100644
index 0e8e11cb..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/lb000.u
+++ /dev/null
@@ -1,49 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: lb000.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   load byte unsigned					#
-	;  ###--------------------------------------------------------###
-
-address		equ	X"000000a8"
-data		equ	X"dbf95ba0"
-
-		org	X"7fffff00"
-		start	init
-
-init:
-		loadi	r9 , address
-		loadi	r10, data
-		sw	r10, r9, 0
-
-		lbu	r11, r9 , 0
-		slli	r13, r11, 24
-
-		lbu	r11, r9 , 1
-		slli	r11, r11, 16
-		or	r13, r13, r11
-
-		lbu	r11, r9 , 2
-		slli	r11, r11, 8
-		or	r13, r13, r11
-
-		lbu	r11, r9 , 3
-		or	r13, r13, r11
-
-		seq	r14, r13, r10
-		beqz	r14, bad
-		nop
-		j	good
-		nop
-
-		org	X"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/or000.s b/alliance/share/tutorials/dlxm/stock_asm/or000.s
deleted file mode 100644
index 155c7d20..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/or000.s
+++ /dev/null
@@ -1,58 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: or000.s						#
-;  # date	: Oct 21 1994						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (RESET)				#
-	;  ###--------------------------------------------------------###
-
-reset_mask	equ	X"0008"
-system_stack	equ	X"80000000"
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler:
-		j	handler_body
-		nop
-return:
-		rfe				; return from exception
-		nop
-
-
-		org	X"ffffff00"
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-other_causes	j	other_causes
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog
-		movi2s	iar, r29
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/or000.u b/alliance/share/tutorials/dlxm/stock_asm/or000.u
deleted file mode 100644
index 6ac92969..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/or000.u
+++ /dev/null
@@ -1,36 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: or000.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   logic or							#
-	;  ###--------------------------------------------------------###
-
-const1		equ	X"a5de56457"
-const2		equ	X"878f0105b"
-
-		org	X"7fffff00"
-		start	init
-
-init:
-		loadi	r14, const1
-		loadi	r19, const2
-		loadi	r9 , (const1 | const2)
-
-		or	r20, r14, r19
-		seq	r7 , r9 , r20
-		bnez	r7      , good
-		nop
-		j	bad
-		nop
-
-		org	X"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/or001.s b/alliance/share/tutorials/dlxm/stock_asm/or001.s
deleted file mode 100644
index b54d3734..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/or001.s
+++ /dev/null
@@ -1,58 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: or001.s						#
-;  # date	: Oct 21 1994						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (RESET)				#
-	;  ###--------------------------------------------------------###
-
-reset_mask	equ	X"0008"
-system_stack	equ	X"80000000"
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler:
-		j	handler_body
-		nop
-return:
-		rfe				; return from exception
-		nop
-
-
-		org	X"ffffff00"
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-other_causes	j	other_causes
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog
-		movi2s	iar, r29
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/or001.u b/alliance/share/tutorials/dlxm/stock_asm/or001.u
deleted file mode 100644
index 75675b46..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/or001.u
+++ /dev/null
@@ -1,38 +0,0 @@
-
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: or001.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   logic or							#
-	;  ###--------------------------------------------------------###
-
-const1		equ	X"5555"
-const2		equ	X"aaaa"
-
-		org	X"7fffff00"
-		start	init
-
-init:
-		ori	r13, r0 , const1
-		ori	r21, r0 , const2
-		ori	r22, r0 , (const1 | const2)
-
-		or	r23, r13, r21
-
-		seq	r20, r23, r22
-		bnez	r20     , good
-		nop
-		j	bad
-		nop
-
-		org	X"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/reg000.s b/alliance/share/tutorials/dlxm/stock_asm/reg000.s
deleted file mode 100644
index c0917f51..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/reg000.s
+++ /dev/null
@@ -1,58 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: reg000.s						#
-;  # date	: Oct 21 1994						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (RESET)				#
-	;  ###--------------------------------------------------------###
-
-reset_mask	equ	X"0008"
-system_stack	equ	X"80000000"
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler:
-		j	handler_body
-		nop
-return:
-		rfe				; return from exception
-		nop
-
-
-		org	X"ffffff00"
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-other_causes	j	other_causes
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog
-		movi2s	iar, r29
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/reg000.u b/alliance/share/tutorials/dlxm/stock_asm/reg000.u
deleted file mode 100644
index f5df2aad..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/reg000.u
+++ /dev/null
@@ -1,36 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: reg000.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   signed addition						#
-	;  ###--------------------------------------------------------###
-
-val		equ	3429
-
-		org	X"7fffff00"
-		start	init
-
-init:
-		add	r25, r0 , r0
-		bnez	r25, bad
-		nop
-
-		subi	r25, r25, val
-		addi	r25, r25, val
-		bnez	r25, bad
-		nop
-		j	good
-		nop
-
-		org	X"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-		end
-
diff --git a/alliance/share/tutorials/dlxm/stock_asm/seq000.s b/alliance/share/tutorials/dlxm/stock_asm/seq000.s
deleted file mode 100644
index d90b9dc8..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/seq000.s
+++ /dev/null
@@ -1,58 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: seq000.s						#
-;  # date	: Oct 21 1994						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (RESET)				#
-	;  ###--------------------------------------------------------###
-
-reset_mask	equ	X"0008"
-system_stack	equ	X"80000000"
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler:
-		j	handler_body
-		nop
-return:
-		rfe				; return from exception
-		nop
-
-
-		org	X"ffffff00"
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-other_causes	j	other_causes
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog
-		movi2s	iar, r29
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/seq000.u b/alliance/share/tutorials/dlxm/stock_asm/seq000.u
deleted file mode 100644
index d10dc4f6..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/seq000.u
+++ /dev/null
@@ -1,28 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: seq000.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   comparaison						#
-	;  ###--------------------------------------------------------###
-
-		org	X"7fffff00"
-		start	init
-
-init:
-		seq	r1 , r1 , r1
-		bnez	r1 , good
-		nop
-		j	bad
-		nop
-
-		org	X"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/seq001.s b/alliance/share/tutorials/dlxm/stock_asm/seq001.s
deleted file mode 100644
index 72e8a929..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/seq001.s
+++ /dev/null
@@ -1,58 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: seq001.s						#
-;  # date	: Oct 21 1994						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (RESET)				#
-	;  ###--------------------------------------------------------###
-
-reset_mask	equ	X"0008"
-system_stack	equ	X"80000000"
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler:
-		j	handler_body
-		nop
-return:
-		rfe				; return from exception
-		nop
-
-
-		org	X"ffffff00"
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-other_causes	j	other_causes
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog
-		movi2s	iar, r29
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/seq001.u b/alliance/share/tutorials/dlxm/stock_asm/seq001.u
deleted file mode 100644
index 96d432a0..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/seq001.u
+++ /dev/null
@@ -1,28 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: seq001.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   comparaison						#
-	;  ###--------------------------------------------------------###
-
-		org	X"7fffff00"
-		start	init
-
-init:
-		seq	r0 , r0 , r0
-		beqz	r0 , good
-		nop
-		j	bad
-		nop
-
-		org	X"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/seq002.s b/alliance/share/tutorials/dlxm/stock_asm/seq002.s
deleted file mode 100644
index 63ede867..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/seq002.s
+++ /dev/null
@@ -1,58 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: seq002.s						#
-;  # date	: Oct 21 1994						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (RESET)				#
-	;  ###--------------------------------------------------------###
-
-reset_mask	equ	X"0008"
-system_stack	equ	X"80000000"
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler:
-		j	handler_body
-		nop
-return:
-		rfe				; return from exception
-		nop
-
-
-		org	X"ffffff00"
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-other_causes	j	other_causes
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog
-		movi2s	iar, r29
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/seq002.u b/alliance/share/tutorials/dlxm/stock_asm/seq002.u
deleted file mode 100644
index 870d927a..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/seq002.u
+++ /dev/null
@@ -1,31 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: seq002.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   comparaison						#
-	;  ###--------------------------------------------------------###
-
-const		equ	X"2045"
-
-		org	X"7fffff00"
-		start	init
-
-init:
-		ori	r1 , r0 , const
-		seqi	r2 , r1 , const
-		beqz	r2 , bad
-		nop
-		j	good
-		nop
-
-		org	X"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/sge000.s b/alliance/share/tutorials/dlxm/stock_asm/sge000.s
deleted file mode 100644
index 4be7758e..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/sge000.s
+++ /dev/null
@@ -1,58 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: sge000.s						#
-;  # date	: Oct 21 1994						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (RESET)				#
-	;  ###--------------------------------------------------------###
-
-reset_mask	equ	X"0008"
-system_stack	equ	X"80000000"
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler:
-		j	handler_body
-		nop
-return:
-		rfe				; return from exception
-		nop
-
-
-		org	X"ffffff00"
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-other_causes	j	other_causes
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog
-		movi2s	iar, r29
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/sge000.u b/alliance/share/tutorials/dlxm/stock_asm/sge000.u
deleted file mode 100644
index 271f5c13..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/sge000.u
+++ /dev/null
@@ -1,31 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: sge000.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   set if greater or equal					#
-	;  ###--------------------------------------------------------###
-
-data		equ	31703
-
-		org	X"7fffff00"
-		start	init
-
-init:
-		addi	r13, r0 ,  data
-		sgei	r14, r13, (data - 1)
-		bnez	r14, good
-		nop
-		j	bad
-		nop
-
-		org	x"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/sle000.s b/alliance/share/tutorials/dlxm/stock_asm/sle000.s
deleted file mode 100644
index 67aa13e9..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/sle000.s
+++ /dev/null
@@ -1,58 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: sle000.s						#
-;  # date	: Oct 21 1994						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (RESET)				#
-	;  ###--------------------------------------------------------###
-
-reset_mask	equ	X"0008"
-system_stack	equ	X"80000000"
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler:
-		j	handler_body
-		nop
-return:
-		rfe				; return from exception
-		nop
-
-
-		org	X"ffffff00"
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-other_causes	j	other_causes
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog
-		movi2s	iar, r29
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/sle000.u b/alliance/share/tutorials/dlxm/stock_asm/sle000.u
deleted file mode 100644
index 9b864266..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/sle000.u
+++ /dev/null
@@ -1,31 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: sle000.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   set if less or equal					#
-	;  ###--------------------------------------------------------###
-
-data		equ	4907
-
-		org	X"7fffff00"
-		start	init
-
-init:
-		addi	r13, r0 ,  data
-		slei	r14, r13, (data - 1)
-		beqz	r14, good
-		nop
-		j	bad
-		nop
-
-		org	x"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/sne000.s b/alliance/share/tutorials/dlxm/stock_asm/sne000.s
deleted file mode 100644
index 29a355cf..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/sne000.s
+++ /dev/null
@@ -1,58 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: sne000.s						#
-;  # date	: Oct 21 1994						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (RESET)				#
-	;  ###--------------------------------------------------------###
-
-reset_mask	equ	X"0008"
-system_stack	equ	X"80000000"
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler:
-		j	handler_body
-		nop
-return:
-		rfe				; return from exception
-		nop
-
-
-		org	X"ffffff00"
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-other_causes	j	other_causes
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog
-		movi2s	iar, r29
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/sne000.u b/alliance/share/tutorials/dlxm/stock_asm/sne000.u
deleted file mode 100644
index aadd762c..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/sne000.u
+++ /dev/null
@@ -1,31 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: sne000.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   comparaison						#
-	;  ###--------------------------------------------------------###
-
-val		equ	X"df48fac2"
-
-		org	X"7fffff00"
-		start	init
-
-init:
-		loadi	r1 , val
-		sne	r1 , r1 , r1
-		beqz	r1 , good
-		nop
-		j	bad
-		nop
-
-		org	X"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/sne001.s b/alliance/share/tutorials/dlxm/stock_asm/sne001.s
deleted file mode 100644
index bb0c8e49..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/sne001.s
+++ /dev/null
@@ -1,58 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: sne001.s						#
-;  # date	: Oct 21 1994						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (RESET)				#
-	;  ###--------------------------------------------------------###
-
-reset_mask	equ	X"0008"
-system_stack	equ	X"80000000"
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler:
-		j	handler_body
-		nop
-return:
-		rfe				; return from exception
-		nop
-
-
-		org	X"ffffff00"
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-other_causes	j	other_causes
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog
-		movi2s	iar, r29
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/sne001.u b/alliance/share/tutorials/dlxm/stock_asm/sne001.u
deleted file mode 100644
index fda06241..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/sne001.u
+++ /dev/null
@@ -1,31 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: sne001.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   comparaison						#
-	;  ###--------------------------------------------------------###
-
-const1		equ	X"a47a"
-
-		org	X"7fffff00"
-		start	init
-
-init:
-		addi	r1 , r0 , const1
-		snei	r2 , r1 , const1
-		beqz	r2 , good
-		nop
-		j	bad
-		nop
-
-		org	X"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/trp000.s b/alliance/share/tutorials/dlxm/stock_asm/trp000.s
deleted file mode 100644
index 1c3967f7..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/trp000.s
+++ /dev/null
@@ -1,80 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: trp000.s						#
-;  # date	: Oct 21 1994						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (RESET)				#
-	;  ###--------------------------------------------------------###
-
-not_trap_mask	equ	X"ff08"
-
-reset_mask	equ	X"0008"
-system_stack	equ	X"80000000"
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler:
-		j	handler_body
-		nop
-return:
-		rfe				; return from exception
-		nop
-
-		org	X"ffffff00"
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, not_trap_mask ; any other cause ?
-		beqz	r29, software_interrupt
-		nop
-
-other_causes	j	other_causes
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog
-		movi2s	iar, r29
-		j	return
-		nop
-
-	;  ###--------------------------------------------------------###
-	;  #   software interrupt (Trap instruction)			#
-	;  #								#
-	;  #   restore return address before returning (from EXCEPTION)	#
-	;  # to the user program (address must be saved by the user	#
-	;  # prior to the EXCEPTION in r31)				#
-	;  ###--------------------------------------------------------###
-
-software_interrupt:
-		movs2i	r1 , tvr
-		slli	r1 , r1 , 4
-		srli	r1 , r1 , 6
-		movi2s	iar, r31
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/trp000.u b/alliance/share/tutorials/dlxm/stock_asm/trp000.u
deleted file mode 100644
index 7d77bba2..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/trp000.u
+++ /dev/null
@@ -1,49 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: trp000.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   software interrupt :					#
-	;  ###--------------------------------------------------------###
-
-trap_nbr	equ	X"32f0ba"		; trap number
-
-		org	X"7fffff00"
-		start	init
-
-init:
-		loadi	r31, back_from_exception
-		loadi	r1 , trap_nbr ^ X"ffffffff"
-		loadi	r2 , trap_nbr
-
-	;  ###--------------------------------------------------------###
-	;  #  sotware interrupt						#
-	;  ###--------------------------------------------------------###
-
-		trap	trap_nbr
-		j	bad
-		nop
-
-	;  ###--------------------------------------------------------###
-	;  #   check that the the trap has been done (r1 must contain	#
-	;  # the trap number)						#
-	;  ###--------------------------------------------------------###
-
-back_from_exception:
-		seq	r4 , r2 , r1		; check that the lw has failed
-		bnez	r4 , good		; jump to good if OK
-		nop
-		j	bad
-		nop
-
-		org	X"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/xor000.s b/alliance/share/tutorials/dlxm/stock_asm/xor000.s
deleted file mode 100644
index 488a2293..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/xor000.s
+++ /dev/null
@@ -1,58 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: xor000.s						#
-;  # date	: Oct 21 1994						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (RESET)				#
-	;  ###--------------------------------------------------------###
-
-reset_mask	equ	X"0008"
-system_stack	equ	X"80000000"
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler:
-		j	handler_body
-		nop
-return:
-		rfe				; return from exception
-		nop
-
-
-		org	X"ffffff00"
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-other_causes	j	other_causes
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog
-		movi2s	iar, r29
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/xor000.u b/alliance/share/tutorials/dlxm/stock_asm/xor000.u
deleted file mode 100644
index ff7ea365..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/xor000.u
+++ /dev/null
@@ -1,36 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: xor000.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   logical exclusive or					#
-	;  ###--------------------------------------------------------###
-
-data1		equ	X"11111111"
-data2		equ	X"00000000"
-		
-		org	X"7fffff00"
-		start	init
-init:
-		loadi	r1 , data1
-		loadi	r2 , data2
-		loadi	r4 , (data1 ^ data2)
-		
-		xor	r3 , r1 , r2
-
-		sne	r31, r4 , r3
-		bnez	r31, bad
-		nop
-		j	good
-		nop
-
-		org	X"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/xor001.s b/alliance/share/tutorials/dlxm/stock_asm/xor001.s
deleted file mode 100644
index c5cb687d..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/xor001.s
+++ /dev/null
@@ -1,58 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: xor001.s						#
-;  # date	: Oct 21 1994						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (RESET)				#
-	;  ###--------------------------------------------------------###
-
-reset_mask	equ	X"0008"
-system_stack	equ	X"80000000"
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler:
-		j	handler_body
-		nop
-return:
-		rfe				; return from exception
-		nop
-
-
-		org	X"ffffff00"
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-other_causes	j	other_causes
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog
-		movi2s	iar, r29
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/xor001.u b/alliance/share/tutorials/dlxm/stock_asm/xor001.u
deleted file mode 100644
index b663b5fc..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/xor001.u
+++ /dev/null
@@ -1,35 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: xor001.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   logical exclusive or					#
-	;  ###--------------------------------------------------------###
-
-data1		equ	X"1234db11"
-data2		equ	X"0089dac0"
-
-		org	X"7fffff00"
-		start	init
-init:
-		loadi	r10, data1
-		loadi	r11, data2
-		loadi	r13, (data1 ^ data2)
-
-		xor	r12 , r10 , r11
-		sne	r31 , r13 , r12
-		bnez	r31 , bad
-		nop
-		j	good
-		nop
-
-		org	X"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/xor002.s b/alliance/share/tutorials/dlxm/stock_asm/xor002.s
deleted file mode 100644
index 7f9ee3db..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/xor002.s
+++ /dev/null
@@ -1,58 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: xor002.s						#
-;  # date	: Oct 21 1994						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (RESET)				#
-	;  ###--------------------------------------------------------###
-
-reset_mask	equ	X"0008"
-system_stack	equ	X"80000000"
-
-user_status	equ	X"0003"
-user_prog	equ	X"7fffff00"
-
-		org	X"fffffff0"
-		start	it_handler
-
-it_handler:
-		j	handler_body
-		nop
-return:
-		rfe				; return from exception
-		nop
-
-
-		org	X"ffffff00"
-handler_body:
-		movs2i	r29, sr			; read Status to test it
-		andi	r29, r29, reset_mask	; reset ?
-		bnez	r29, hardware_reset
-		nop
-
-other_causes	j	other_causes
-
-	;  ###--------------------------------------------------------###
-	;  #   initialization prgram (hardware RESET)			#
-	;  ###--------------------------------------------------------###
-
-hardware_reset:
-		loadi	r30, system_stack	; init system stack pointer
-
-		movs2i	r29, sr			; load Status to initialize
-		ori	r28, r0 , X"ffff"	; clear high order bits of
-		and	r29, r29, r28		;+the status register
-		lhi     r28, user_status	; init status register
-		or	r29, r29, r28		;
-		movi2s	sr , r29
-
-		loadi	r29, user_prog
-		movi2s	iar, r29
-		j	return
-		nop
-
-		end
diff --git a/alliance/share/tutorials/dlxm/stock_asm/xor002.u b/alliance/share/tutorials/dlxm/stock_asm/xor002.u
deleted file mode 100644
index d2a854a9..00000000
--- a/alliance/share/tutorials/dlxm/stock_asm/xor002.u
+++ /dev/null
@@ -1,31 +0,0 @@
-;  ###----------------------------------------------------------------###
-;  #									#
-;  # file	: xor002.u						#
-;  # date	: Apr  1 1993						#
-;  # descr.	: functional test for dlx				#
-;  #									#
-;  ###----------------------------------------------------------------###
-
-	;  ###--------------------------------------------------------###
-	;  #   logical exclusive or					#
-	;  ###--------------------------------------------------------###
-
-const		equ	45
-
-		org	X"7fffff00"
-		start	init
-
-init:
-		xori	r1 , r0 , const
-		slei	r30, r1 , const
-		bnez	r30, good
-		nop
-		j	bad
-		nop
-
-		org	X"7ffffff0"
-good		j	good
-		nop
-bad		j	bad
-		nop
-		end
diff --git a/alliance/share/tutorials/dlxm/timer.vbe b/alliance/share/tutorials/dlxm/timer.vbe
deleted file mode 100644
index 981d7daf..00000000
--- a/alliance/share/tutorials/dlxm/timer.vbe
+++ /dev/null
@@ -1,50 +0,0 @@
--- ### -------------------------------------------------------------- ###
--- #									#
--- # file	: timer.vbe						#
--- # date	: Mar 23 1993						#
--- # version	: v0.0							#
--- #									#
--- # origin	: this description has been developed by CAO-VLSI team	#
--- #		  at MASI laboratory, University Pierre et Marie Curie	#
--- #		  URA CNRS 818, Institut Blaise Pascal			#
--- #		  4 Place Jussieu 75252 Paris Cedex 05 - France		#
--- # E-mail      :      cao-vlsi@masi.ibp.fr                            #
--- #									#
--- # descr.	: data flow description of a programable timer.		#
--- #		  The timer includes a programmable clock divider (by	#
--- #		  16 or 256), 4 configurable 32 bits counters, a	#
--- #		  configuration and a status register.			#
--- #									#
--- ### -------------------------------------------------------------- ###
-
-entity TIMER is
-
-  port (
-    CK      : in    bit                         ;	-- external clock
-    FRZ     : in    bit                         ;	-- freeze
-    RESET   : in    bit                         ;	-- reset
-    SEL     : in    bit_vector ( 2 downto 0)    ;	-- register selection
-    DATA    : inout mux_vector (31 downto 0) bus;	-- data
-    RW      : in    bit                         ;	-- access mode
-    E_N     : in    bit                         ;	-- chip enable
-    IRQ_N   : out   wor_bit                  bus;	-- interrupt request
-    VDD     : in    bit                         ;	--
-    VSS     : in    bit                         	--
-    );
-
-end;
-
-architecture FUNCTIONAL of TIMER is
-begin
-
-  read : block ('0')
-  begin
-      DATA <= guarded X"0000_0000";
-  end block;
-
-  bl : block ('1')
-  begin
-     IRQ_N <= guarded '1';
-  end block;
-
-end;
diff --git a/alliance/share/tutorials/fitpath/Makefile b/alliance/share/tutorials/fitpath/Makefile
deleted file mode 100644
index 69eadc6e..00000000
--- a/alliance/share/tutorials/fitpath/Makefile
+++ /dev/null
@@ -1,525 +0,0 @@
-
-#
-# %% \textrm{This File Looks Nicer with\textsf{ LGrind} and \LaTeXe.}        %%
-# %|                                                                         |%
-# %| /---------------------------------------------------------------------\ |%
-# %| |                                                                     | |%
-# %| |          Alliance CAD System V.R                                    | |%
-# %| |     F p G e n   P a c k a g e   V.RR                                | |%
-# %| |                                                                     | |%
-# %| |  Copyright(c) 95-AA, MASI, CAO-VLSI Team                            | |%
-# %| |                                                                     | |%
-# %| |  Author    :            Jean-Paul CHAPUT                            | |%
-# %| | =================================================================== | |%
-# %| |  File      :  "Makefile"                                            | |%
-# %| | ******************************************************************* | |%
-# %| |  FpGen / DPR examples.                                              | |%
-# %| |                                                                     | |%
-# %| \---------------------------------------------------------------------/ |%
-#
-
-# Installation Dependent Variables.
-     TOP_LAB = $(ALLIANCE_TOP)
-     TOP_LIB = $(ALLIANCE_TOP)
-
-# Alliance binary access paths.
-ALLIANCE_BIN =$(ALLIANCE_TOP)/bin
- FITPATH_BIN =$(ALLIANCE_TOP)/bin
-    USER_BIN =$(ALLIANCE_TOP)/bin
-     DPR_BIN =$(ALLIANCE_TOP)/bin
-
-
-## ************************* Various MBK environment *************************
-
-
-#
-#
-# Alliance leaf cells libraries paths.
-# ====================================
-#
-  RSA_LIB = $(TOP_LIB)/cells/rsa
-    DPLIB = $(TOP_LAB)/cells/dplib
-    FPLIB = $(TOP_LAB)/cells/fplib
-FPGEN_LIB = ./mclib
-
- CATA_LIB = $(FPGEN_LIB):$(RSA_LIB):$(FPLIB):$(DPLIB)
-
-
-#
-#
-# MBK environment common to all Alliance tools.
-# =============================================
-#
-MBK_STD  = MBK_WORK_LIB=.;           export MBK_WORK_LIB;   \
-		   MBK_CATA_LIB=$(CATA_LIB); export MBK_CATA_LIB;   \
-		   MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; \
-		   MBK_SEPAR=.;              export MBK_SEPAR;      \
-		   MBK_VDD=vdd;              export MBK_VDD;        \
-		   MBK_VSS=vss;              export MBK_VSS;        \
-           MBK_TARGET_LIB=$(DPLIB);  export MBK_TARGET_LIB; \
-           MBK_LOG_NAME="";          export MBK_LOG_NAME;   \
-           FPGEN_LIB=$(FPGEN_LIB);   export FPGEN_LIB
-
-
-#
-#
-# Avalaibles MBK netlist and layout formats.
-# ==========================================
-#
-MBK_FNE  = MBK_OUT_LO=fne; export MBK_OUT_LO; MBK_IN_LO=fne; export MBK_IN_LO
-MBK_HNS  = MBK_OUT_LO=hns; export MBK_OUT_LO; MBK_IN_LO=hns; export MBK_IN_LO
-MBK_CP   = MBK_OUT_PH=cp;  export MBK_OUT_PH; MBK_IN_PH=cp;  export MBK_IN_PH
-MBK_VST  = MBK_OUT_LO=vst; export MBK_OUT_LO; MBK_IN_LO=vst; export MBK_IN_LO
-MBK_AL   = MBK_OUT_LO=al;  export MBK_OUT_LO; MBK_IN_LO=al;  export MBK_IN_LO
-MBK_AP   = MBK_OUT_PH=ap;  export MBK_OUT_PH; MBK_IN_PH=ap;  export MBK_IN_PH
-
-
-#
-#
-# Alliance Tools with the correct MBK environment.
-# ================================================
-#
-     BOP = $(MBK_STD); $(MBK_VST); $(MBK_AP); $(ALLIANCE_BIN)/bop
-   SCMAP = $(MBK_STD); $(MBK_VST); $(MBK_AP); $(ALLIANCE_BIN)/scmap
-  FPGEN = $(MBK_STD); $(MBK_VST); $(MBK_AP); $(ALLIANCE_BIN)/fpgen
-#    DPR = $(MBK_STD); $(MBK_VST); $(MBK_AP); $(ALLIANCE_BIN)/dpr
-    DRUC = $(MBK_STD); $(MBK_VST); $(MBK_AP); $(ALLIANCE_BIN)/druc
-    LYNX = $(MBK_STD); $(MBK_AL);  $(MBK_AP); $(ALLIANCE_BIN)/lynx
-    DESB = $(MBK_STD); $(MBK_AL);             $(ALLIANCE_BIN)/yagle
-   PROOF = $(MBK_STD);                        $(ALLIANCE_BIN)/proof
-     LVX = $(MBK_STD);                        $(ALLIANCE_BIN)/lvx
-
-#   FPGEN = $(MBK_STD); $(MBK_VST); $(MBK_AP);  $(FITPATH_BIN)/fpgen
-#    DPR = $(MBK_STD); $(MBK_VST); $(MBK_AP);  $(FITPATH_BIN)/dpr
-     DPR = $(MBK_STD); $(MBK_VST); $(MBK_AP);      $(DPR_BIN)/dpr
-#    DPR = $(MBK_STD); $(MBK_VST); $(MBK_AP);     $(LABO_BIN)/dpr
-#    LVX = $(MBK_STD);                            $(USER_BIN)/sparc/lvx-2.23
-#   DESB = $(MBK_STD); $(MBK_AL);                 $(USER_BIN)/sparc/desb-2.91
-
-
-## ***************************** Starting Rules ******************************
-
-
-help:
-	@mkdir $(FPGEN_LIB) ;\
-         echo 'Makefile:'; \
-	 echo '';          \
-	 echo '  "$$ make all"       : run all examples.';                \
-	 echo '  "$$ make sample"    : run the more sample example.';     \
-	 echo '  "$$ make place"     : run optimized placement example.'; \
-	 echo '  "$$ make usercol"   : run operator customized example.'; \
-	 echo '  "$$ make hierarchy" : run hierarchical design example.'; \
-     echo '  "$$ make clean"     : delete all generated files.';      \
-	 echo ''
-
-
-all: sample place usercol hierarchy synthesis
-
-sample:       sample_druc    sample_lvx    sample_proof
-place:         place_druc     place_lvx     place_proof
-usercol:     usercol_druc   usercol_lvx   usercol_proof
-synthesis: synthesis_druc synthesis_lvx synthesis_proof
-hierarchy: hierarchy_druc hierarchy_lvx hierarchy_proof
-
-
-bench: all
-
-
-## *********************** Rules for sample Data-Path ************************
-
-
-#
-#
-# FpGen : Generation of the Netlist.
-# ==================================
-#
-sample_dpt.vst: sample_dpt.c
-	$(FPGEN) -v sample_dpt
-
-
-#
-#
-# DPR : Routing the data-path.
-# ============================
-#
-sample_dpt.ap: sample_dpt.dpr sample_dpt.vst
-	$(DPR) -V -p -r sample_dpt sample_dpt
-
-
-#
-#
-# DRUC : Symbolic Design RUles Checker.
-# =====================================
-#
-sample_druc: sample_dpt.ap
-	$(DRUC) sample_dpt
-
-
-#
-#
-# LYNX : Gate level netlist extraction.
-# =====================================
-#
-sample_dpt_gates.al: sample_dpt.ap
-	$(LYNX) -v -f sample_dpt sample_dpt_gates
-
-
-#
-#
-# LVX : Netlist comparison.
-# =========================
-#
-sample_lvx: sample_dpt.vst sample_dpt_gates.al
-	$(LVX) vst al sample_dpt sample_dpt_gates -f
-
-
-#
-#
-# LYNX : Transistor netlist extraction.
-# =====================================
-#
-sample_dpt.al: sample_dpt.ap
-	$(LYNX) -v -t sample_dpt sample_dpt
-
-
-#
-#
-# DESB : Behavioral exctraction.
-# ==============================
-#
-sample_dpt_desb.vbe: sample_dpt.inf sample_dpt.al
-	$(DESB) sample_dpt sample_dpt_desb -v -i
-
-
-#
-#
-# PROOF : Formal proof.
-# =====================
-#
-sample_proof: sample_dpt.vbe sample_dpt_desb.vbe
-	$(PROOF) -d sample_dpt sample_dpt_desb
-
-
-## ************** Rules for Data-Path using optimized placement **************
-
-
-#
-#
-# FpGen : Generation of the Netlist.
-# ==================================
-#
-place_dpt.vst: place_dpt.c
-	$(FPGEN) -v place_dpt
-
-
-#
-#
-# DPR : Routing the data-path.
-# ============================
-#
-place_dpt.ap: place_dpt.dpr place_dpt.vst
-	$(DPR) -V -o -p -r place_dpt place_dpt
-
-
-#
-#
-# DRUC : Symbolic Design RUles Checker.
-# =====================================
-#
-place_druc: place_dpt.ap
-	$(DRUC) place_dpt
-
-
-#
-#
-# LYNX : Gate level netlist extraction.
-# =====================================
-#
-place_dpt_gates.al: place_dpt.ap
-	$(LYNX) -v -f place_dpt place_dpt_gates
-
-
-#
-#
-# LVX : Netlist comparison.
-# =========================
-#
-place_lvx: place_dpt.vst place_dpt_gates.al
-	$(LVX) vst al place_dpt place_dpt_gates -f
-
-
-#
-#
-# LYNX : Transistor netlist extraction.
-# =====================================
-#
-place_dpt.al: place_dpt.ap
-	$(LYNX) -v -t place_dpt place_dpt
-
-
-#
-#
-# DESB : Behavioral exctraction.
-# ==============================
-#
-place_dpt_desb.vbe: place_dpt.inf place_dpt.al
-	$(DESB) place_dpt place_dpt_desb -v -i
-
-
-#
-#
-# PROOF : Formal proof.
-# =====================
-#
-place_proof: sample_dpt.vbe place_dpt_desb.vbe
-	$(PROOF) -d sample_dpt place_dpt_desb
-
-
-## *********** Rules for Data-Path using Hierarchical description ************
-
-
-#
-#
-# FpGen : Generation of the Netlist.
-# ==================================
-#
-hierarchy_dpt.vst: hierarchy_dpt.c
-	$(FPGEN) -v hierarchy_dpt
-
-
-#
-#
-# DPR : Routing the data-path.
-# ============================
-#
-hierarchy_dpt.ap: hierarchy_dpt.dpr hierarchy_dpt.vst
-	$(DPR) -V -p -r hierarchy_dpt hierarchy_dpt
-
-
-#
-#
-# DRUC : Symbolic Design RUles Checker.
-# =====================================
-#
-hierarchy_druc: hierarchy_dpt.ap
-	$(DRUC) hierarchy_dpt
-
-
-#
-#
-# LYNX : Gate level netlist extraction.
-# =====================================
-#
-hierarchy_dpt_gates.al: hierarchy_dpt.ap
-	$(LYNX) -v -f hierarchy_dpt hierarchy_dpt_gates
-
-
-#
-#
-# LVX : Netlist comparison.
-# =========================
-#
-hierarchy_lvx: hierarchy_dpt.vst hierarchy_dpt_gates.al
-	$(LVX) vst al hierarchy_dpt hierarchy_dpt_gates -f
-
-
-#
-#
-# LYNX : Transistor netlist extraction.
-# =====================================
-#
-hierarchy_dpt.al: hierarchy_dpt.ap
-	$(LYNX) -v -t hierarchy_dpt hierarchy_dpt
-
-
-#
-#
-# DESB : Behavioral exctraction.
-# ==============================
-#
-hierarchy_dpt_desb.vbe: hierarchy_dpt.inf hierarchy_dpt.al
-	$(DESB) hierarchy_dpt hierarchy_dpt_desb -v -i
-
-
-#
-#
-# PROOF : Formal proof.
-# =====================
-#
-hierarchy_proof: sample_dpt.vbe hierarchy_dpt_desb.vbe
-	$(PROOF) -d sample_dpt hierarchy_dpt_desb
-
-
-
-
-## ******************* Rules for Data-Path using synthesis *******************
-
-
-#
-#
-# Logic : Synthesis of the Adder.
-# ===============================
-#
-adder_us.vst: adder_us.vbe
-	$(BOP)   -o adder_us     adder_us_opt
-	$(SCMAP)    adder_us_opt adder_us
-
-
-#
-#
-# FpGen : Generation of the Netlist.
-# ==================================
-#
-synthesis_dpt.vst: adder_us.vst synthesis_dpt.c
-	$(FPGEN) -v synthesis_dpt
-
-
-#
-#
-# DPR : Routing the data-path.
-# ============================
-#
-synthesis_dpt.ap: synthesis_dpt.dpr synthesis_dpt.vst
-	$(DPR) -V -p -r synthesis_dpt synthesis_dpt
-
-
-#
-#
-# DRUC : Symbolic Design RUles Checker.
-# =====================================
-#
-synthesis_druc: synthesis_dpt.ap
-	$(DRUC) synthesis_dpt
-
-
-#
-#
-# LYNX : Gate level netlist extraction.
-# =====================================
-#
-synthesis_dpt_gates.al: synthesis_dpt.ap
-	$(LYNX) -v -f synthesis_dpt synthesis_dpt_gates
-
-
-#
-#
-# LVX : Netlist comparison.
-# =========================
-#
-synthesis_lvx: synthesis_dpt.vst synthesis_dpt_gates.al
-	$(LVX) vst al synthesis_dpt synthesis_dpt_gates -f
-
-
-#
-#
-# LYNX : Transistor netlist extraction.
-# =====================================
-#
-synthesis_dpt.al: synthesis_dpt.ap
-	$(LYNX) -v -t synthesis_dpt synthesis_dpt
-
-
-#
-#
-# DESB : Behavioral exctraction.
-# ==============================
-#
-synthesis_dpt_desb.vbe: synthesis_dpt.inf synthesis_dpt.al
-	$(DESB) synthesis_dpt synthesis_dpt_desb -v -i
-
-
-#
-#
-# PROOF : Formal proof.
-# =====================
-#
-synthesis_proof: sample_dpt.vbe synthesis_dpt_desb.vbe
-	$(PROOF) -d sample_dpt synthesis_dpt_desb
-
-
-## ************** Rules for Data-Path using user defined column **************
-
-
-#
-#
-# FpGen : Generation of the Netlist.
-# ==================================
-#
-usercol_dpt.vst: usercol_dpt.c
-	$(FPGEN) -v usercol_dpt
-
-
-#
-#
-# DPR : Routing the data-path.
-# ============================
-#
-usercol_dpt.ap: usercol_dpt.dpr usercol_dpt.vst
-	$(DPR) -V -p -r usercol_dpt usercol_dpt
-
-
-#
-#
-# DRUC : Symbolic Design RUles Checker.
-# =====================================
-#
-usercol_druc: usercol_dpt.ap
-	$(DRUC) usercol_dpt
-
-
-#
-#
-# LYNX : Gate level netlist extraction.
-# =====================================
-#
-usercol_dpt_gates.al: usercol_dpt.ap
-	$(LYNX) -v -f usercol_dpt usercol_dpt_gates
-
-
-#
-#
-# LVX : Netlist comparison.
-# =========================
-#
-usercol_lvx: usercol_dpt.vst usercol_dpt_gates.al
-	$(LVX) vst al usercol_dpt usercol_dpt_gates -f
-
-
-#
-#
-# LYNX : Transistor netlist extraction.
-# =====================================
-#
-usercol_dpt.al: usercol_dpt.ap
-	$(LYNX) -v -t usercol_dpt usercol_dpt
-
-
-#
-#
-# DESB : Behavioral exctraction.
-# ==============================
-#
-usercol_dpt_desb.vbe: usercol_dpt.inf usercol_dpt.al
-	$(DESB) usercol_dpt usercol_dpt_desb -v -i
-
-
-#
-#
-# PROOF : Formal proof.
-# =====================
-#
-usercol_proof: sample_dpt.vbe usercol_dpt_desb.vbe
-	$(PROOF) -d sample_dpt usercol_dpt_desb
-
-
-## *************************** Miscellaneous Rules ***************************
-
-
-#
-# Removing all generated files.
-# =============================
-#
-clean:
-	rm -Rf *_desb.vbe  *_opt.vbe  *_bk.vbe  *_cl.vbe  *.vst  *.hns  *.fne \
-        *.err  *.grr  *.frr  *.rep  *.drc  *.gds  *.cif  *.fcf  *.deb  *.dsbr \
-        *.al   *.ap   *.cp   CATAL      core      Makefile-* $(FPGEN_LIB)/*
diff --git a/alliance/share/tutorials/fitpath/README b/alliance/share/tutorials/fitpath/README
deleted file mode 100644
index 32dabaa6..00000000
--- a/alliance/share/tutorials/fitpath/README
+++ /dev/null
@@ -1,24 +0,0 @@
-
-6. FpGen/DPR (Data-Path package) in the subdirectory "datapath".
-
-This tutorial presents tools and methodology to design data-path with
-Alliance. The two tools are:
-
-    1 - FpGen : Data-Path netlists description language based upon C.
-                (similar to GenLib)
-    2 - DPR   : Place and route tool dedicated to Data-Path.
-
-The Data-Path choosen as example is derivated from the "ADDACCU" tutorial.
-We show five differents ways to build this Data-Path. Each way using a
-specific Data-Path features. The five examples are the followings:
-
-    1 -    sample_dpt : Basic Data-Path, use only standart features.
-    2 -     place_dpt : Data-Path using optimized placement.
-    3 -   usercol_dpt : Data-Path using a customized operator.
-    4 - synthesis_dpt : Using logical synthesis to design a Data-Path
-                          operator.
-    5 - hierarchy_dpt : Using a hierarchical approach to describe a
-                          datapath netlist.
-
-To automatically build the examples fives shell scripts and a makefile
-are provided.
diff --git a/alliance/share/tutorials/fitpath/adder_us.vbe b/alliance/share/tutorials/fitpath/adder_us.vbe
deleted file mode 100644
index 7e21bf38..00000000
--- a/alliance/share/tutorials/fitpath/adder_us.vbe
+++ /dev/null
@@ -1,53 +0,0 @@
-
-
--- ###---------------------------------------------------------------------###
--- #                                                                         #
--- #          Alliance CAD System V.R                                        #
--- #             FpGen Package V.RR                                          #
--- #                                                                         #
--- #  Copyright(c) 93-AA, MASI, CAO-VLSI Team                                #
--- #                                                                         #
--- #  Author      :          Jean-Paul CHAPUT                                #
--- #  E-mail      :      cao-vlsi@masi.ibp.fr                                #
--- # ======================================================================= #
--- #  File        :      "adder_us.vbe"                                      #
--- # *********************************************************************** #
--- #  Adder behavioral description.                                          #
--- #                                                                         #
--- ###---------------------------------------------------------------------###
-
-
-ENTITY  adder_us  IS
-  -- The order of the terminals must be the same as in the FpGen
-  -- Macro-Function : DP_ADD2F (that generate "add2f_8x8x0l_bk").
-  PORT(
-         a   : in    BIT_VECTOR(7 downto 0);
-         b   : in    BIT_VECTOR(7 downto 0);
-      cout_n :   out BIT;
-      over_n :   out BIT;
-         s   :   out BIT_VECTOR(7 downto 0);
-       vdd   : in    BIT;
-       vss   : in    BIT
-      );
-END  adder_us;
-
-
-ARCHITECTURE  behavior_data_flow  OF  adder_us  IS
-
-	SIGNAL cry : BIT_VECTOR(8 downto 0);
-
-BEGIN
-  cry(0) <= '0';
-  cry(8 downto 1) <=    (a and b)
-                     or (a and cry(7 downto 0))
-                     or (b and cry(7 downto 0));
-
-  s      <= a xor b xor cry(7 downto 0);
-  over_n <= not cry(7);
-  cout_n <= not cry(8);
-
-
-  ASSERT((vdd = '1') and (vss = '0'))
-    REPORT "Power supply is missing on adder_us"
-    SEVERITY WARNING;
-END  behavior_data_flow;
diff --git a/alliance/share/tutorials/fitpath/fitpath.pdf b/alliance/share/tutorials/fitpath/fitpath.pdf
deleted file mode 100644
index 699e9bb2..00000000
Binary files a/alliance/share/tutorials/fitpath/fitpath.pdf and /dev/null differ
diff --git a/alliance/share/tutorials/fitpath/fitpath.ps b/alliance/share/tutorials/fitpath/fitpath.ps
deleted file mode 100644
index 682f909f..00000000
--- a/alliance/share/tutorials/fitpath/fitpath.ps
+++ /dev/null
@@ -1,28813 +0,0 @@
-%!PS-Adobe-2.0
-%%Creator: dvips(k) 5.85 Copyright 1999 Radical Eye Software
-%%Title: fitpath.dvi
-%%Pages: 34
-%%PageOrder: Ascend
-%%BoundingBox: 0 0 596 842
-%%EndComments
-%DVIPSWebPage: (www.radicaleye.com)
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-  } % end of proc
-  image
-} bind def
-
-
-612 792 8			% dimensions of data
-[612 0 0 -792 0 792]		% mapping matrix
-rlecmapimage
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-
-%
-% Compression made this file 10.26% of the uncompressed size.
-%
-
-
-showpage
-
-% stop using temporary dictionary
-end
-
-% restore original state
-origstate restore
-
-%%Trailer
-
-%%EndDocument
- @endspecial 1839 5919 a Fp(14)p eop
-%%Page: 15 16
-15 15 bop 118 390 a Fo(Lynx)33 b(:)42 b Fm(netlist)k
-Fo(extraction)p 354 518 3155 4 v 354 668 4 151 v 410
-625 a Fi($)d(lynx)f(-v)h(-f)g(sample)p 1246 625 27 4
-v 29 w(dpt)f(sample)p 1713 625 V 29 w(dpt)p 1874 625
-V 30 w(gates)p 3506 668 4 151 v 354 671 3155 4 v 911
-3371 a @beginspecial 0 @llx 0 @lly 612 @urx 792 @ury
-2326 @rwi @setspecial
-%%BeginDocument: ./trace-lynx-1.ps
-%!PS-Adobe-2.0 EPSF-2.0
-%%Title: /users/outil2/fitpath/ln.S/tutorial/trace-lynx-1.ps
-%%Creator: XV Version 3.10a  Rev: 12/29/94  -  by John Bradley
-%%BoundingBox: 0 0 612 792
-%%Pages: 1
-%%DocumentFonts:
-%%EndComments
-%%EndProlog
-
-%%Page: 1 1
-
-% remember original state
-/origstate save def
-
-% build a temporary dictionary
-20 dict begin
-
-% define space for color conversions
-/grays 612 string def  % space for gray scale line
-/npixls 0 def
-/rgbindx 0 def
-
-% lower left corner
-0 0 translate
-
-% size of image (on paper, in 1/72inch coords)
-612.00000 792.00000 scale
-
-% define the colormap
-/cmap 6 string def
-
-
-% load up the colormap
-currentfile cmap readhexstring
-00 44 88 bf e5 ff 
-pop pop   % lose return values from readhexstring
-
-
-% rlecmapimage expects to have 'w h bits matrix' on stack
-/rlecmapimage {
-  /buffer 1 string def
-  /rgbval 3 string def
-  /block  384 string def
-
-  % proc to read a block from file, and return RGB data
-  { currentfile buffer readhexstring pop
-    /bcount exch 0 get store
-    bcount 128 ge
-    {  % it's a non-run block
-      0 1 bcount 128 sub
-      { currentfile buffer readhexstring pop pop
-
-        % look up value in gray map
-        /rgbval cmap buffer 0 get 1 getinterval store
-
-        % and put it in position i in block
-        block exch rgbval putinterval
-      } for
-      block  0  bcount 127 sub  getinterval
-    }
-
-    { % else it's a run block
-      currentfile buffer readhexstring pop pop
-
-      % look up value in graymap
-      /rgbval cmap buffer 0 get 1 getinterval store
-
-      0 1 bcount { block exch rgbval putinterval } for
-
-      block 0 bcount 1 add getinterval
-    } ifelse
-  } % end of proc
-  image
-} bind def
-
-
-612 792 8			% dimensions of data
-[612 0 0 -792 0 792]		% mapping matrix
-rlecmapimage
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-
-%
-% Compression made this file 11.07% of the uncompressed size.
-%
-
-
-showpage
-
-% stop using temporary dictionary
-end
-
-% restore original state
-origstate restore
-
-%%Trailer
-
-%%EndDocument
- @endspecial 1839 5919 a Fp(15)p eop
-%%Page: 16 17
-16 16 bop 118 390 a Fo(L)-11 b(VX)33 b(:)e Fm(netlist)46
-b Fo(comparisons)p 354 518 3155 4 v 354 668 4 151 v 410
-625 a Fi($)d(lvx)g(vst)f(al)h(sample)p 1246 625 27 4
-v 29 w(dpt)f(sample)p 1713 625 V 29 w(dpt)p 1874 625
-V 30 w(gates)g(-f)p 3506 668 4 151 v 354 671 3155 4 v
-911 3371 a @beginspecial 0 @llx 0 @lly 612 @urx 792 @ury
-2326 @rwi @setspecial
-%%BeginDocument: ./trace-lvx-1.ps
-%!PS-Adobe-2.0 EPSF-2.0
-%%Title: /users/outil2/fitpath/ln.S/tutorial/trace-lvx-1.ps
-%%Creator: XV Version 3.10a  Rev: 12/29/94  -  by John Bradley
-%%BoundingBox: 0 0 612 792
-%%Pages: 1
-%%DocumentFonts:
-%%EndComments
-%%EndProlog
-
-%%Page: 1 1
-
-% remember original state
-/origstate save def
-
-% build a temporary dictionary
-20 dict begin
-
-% define space for color conversions
-/grays 612 string def  % space for gray scale line
-/npixls 0 def
-/rgbindx 0 def
-
-% lower left corner
-0 0 translate
-
-% size of image (on paper, in 1/72inch coords)
-612.00000 792.00000 scale
-
-% define the colormap
-/cmap 6 string def
-
-
-% load up the colormap
-currentfile cmap readhexstring
-00 44 88 bf e5 ff 
-pop pop   % lose return values from readhexstring
-
-
-% rlecmapimage expects to have 'w h bits matrix' on stack
-/rlecmapimage {
-  /buffer 1 string def
-  /rgbval 3 string def
-  /block  384 string def
-
-  % proc to read a block from file, and return RGB data
-  { currentfile buffer readhexstring pop
-    /bcount exch 0 get store
-    bcount 128 ge
-    {  % it's a non-run block
-      0 1 bcount 128 sub
-      { currentfile buffer readhexstring pop pop
-
-        % look up value in gray map
-        /rgbval cmap buffer 0 get 1 getinterval store
-
-        % and put it in position i in block
-        block exch rgbval putinterval
-      } for
-      block  0  bcount 127 sub  getinterval
-    }
-
-    { % else it's a run block
-      currentfile buffer readhexstring pop pop
-
-      % look up value in graymap
-      /rgbval cmap buffer 0 get 1 getinterval store
-
-      0 1 bcount { block exch rgbval putinterval } for
-
-      block 0 bcount 1 add getinterval
-    } ifelse
-  } % end of proc
-  image
-} bind def
-
-
-612 792 8			% dimensions of data
-[612 0 0 -792 0 792]		% mapping matrix
-rlecmapimage
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-%
-
-
-showpage
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-% stop using temporary dictionary
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-% restore original state
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-%%Trailer
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-%%Page: 17 18
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-3506 668 4 151 v 354 671 3155 4 v 911 3371 a @beginspecial
-0 @llx 0 @lly 612 @urx 792 @ury 2326 @rwi @setspecial
-%%BeginDocument: ./trace-lynx-2.ps
-%!PS-Adobe-2.0 EPSF-2.0
-%%Title: /users/outil2/fitpath/ln.S/tutorial/trace-lynx-2.ps
-%%Creator: XV Version 3.10a  Rev: 12/29/94  -  by John Bradley
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-%%Pages: 1
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-%%EndProlog
-
-%%Page: 1 1
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-% remember original state
-/origstate save def
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-% build a temporary dictionary
-20 dict begin
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-% define space for color conversions
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-% lower left corner
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-% define the colormap
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-% load up the colormap
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-  % proc to read a block from file, and return RGB data
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-      0 1 bcount 128 sub
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-
-        % look up value in gray map
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-
-        % and put it in position i in block
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-    } ifelse
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-
-612 792 8			% dimensions of data
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-
-%
-% Compression made this file 11.07% of the uncompressed size.
-%
-
-
-showpage
-
-% stop using temporary dictionary
-end
-
-% restore original state
-origstate restore
-
-%%Trailer
-
-%%EndDocument
- @endspecial 1839 5919 a Fp(17)p eop
-%%Page: 18 19
-18 18 bop 118 390 a Fo(DESB)32 b(:)f(F)-8 b(unctional)32
-b(abstraction)p 354 501 3155 4 v 354 652 4 151 v 410
-609 a Fi($)43 b(desb)f(sample)p 984 609 27 4 v 29 w(dpt)h(sample)p
-1452 609 V 28 w(dpt)p 1612 609 V 31 w(desb)f(-v)g(-i)p
-3506 652 4 151 v 354 655 3155 4 v 911 3355 a @beginspecial
-0 @llx 0 @lly 612 @urx 792 @ury 2326 @rwi @setspecial
-%%BeginDocument: ./trace-desb-1.ps
-%!PS-Adobe-2.0 EPSF-2.0
-%%Title: /users/outil2/fitpath/ln.S/tutorial/trace-desb-1.ps
-%%Creator: XV Version 3.10a  Rev: 12/29/94  -  by John Bradley
-%%BoundingBox: 0 0 612 792
-%%Pages: 1
-%%DocumentFonts:
-%%EndComments
-%%EndProlog
-
-%%Page: 1 1
-
-% remember original state
-/origstate save def
-
-% build a temporary dictionary
-20 dict begin
-
-% define space for color conversions
-/grays 612 string def  % space for gray scale line
-/npixls 0 def
-/rgbindx 0 def
-
-% lower left corner
-0 0 translate
-
-% size of image (on paper, in 1/72inch coords)
-612.00000 792.00000 scale
-
-% define the colormap
-/cmap 6 string def
-
-
-% load up the colormap
-currentfile cmap readhexstring
-00 44 88 bf e5 ff 
-pop pop   % lose return values from readhexstring
-
-
-% rlecmapimage expects to have 'w h bits matrix' on stack
-/rlecmapimage {
-  /buffer 1 string def
-  /rgbval 3 string def
-  /block  384 string def
-
-  % proc to read a block from file, and return RGB data
-  { currentfile buffer readhexstring pop
-    /bcount exch 0 get store
-    bcount 128 ge
-    {  % it's a non-run block
-      0 1 bcount 128 sub
-      { currentfile buffer readhexstring pop pop
-
-        % look up value in gray map
-        /rgbval cmap buffer 0 get 1 getinterval store
-
-        % and put it in position i in block
-        block exch rgbval putinterval
-      } for
-      block  0  bcount 127 sub  getinterval
-    }
-
-    { % else it's a run block
-      currentfile buffer readhexstring pop pop
-
-      % look up value in graymap
-      /rgbval cmap buffer 0 get 1 getinterval store
-
-      0 1 bcount { block exch rgbval putinterval } for
-
-      block 0 bcount 1 add getinterval
-    } ifelse
-  } % end of proc
-  image
-} bind def
-
-
-612 792 8			% dimensions of data
-[612 0 0 -792 0 792]		% mapping matrix
-rlecmapimage
-
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-% stop using temporary dictionary
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-% restore original state
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-%%Trailer
-
-%%EndDocument
- @endspecial 1839 5919 a Fp(18)p eop
-%%Page: 19 20
-19 19 bop 118 390 a Fo(Pro)s(of)32 b(:)42 b(F)-8 b(ormal)30
-b(pro)s(of)p 354 518 3155 4 v 354 668 4 151 v 410 625
-a Fi($)43 b(proof)f(-d)h(sample)p 1159 625 27 4 v 29
-w(dpt)f(sample)p 1626 625 V 29 w(dpt)p 1787 625 V 30
-w(desb)p 3506 668 4 151 v 354 671 3155 4 v 911 3371 a
-@beginspecial 0 @llx 0 @lly 612 @urx 792 @ury 2326 @rwi
-@setspecial
-%%BeginDocument: ./trace-proof-1.ps
-%!PS-Adobe-2.0 EPSF-2.0
-%%Title: /users/outil2/fitpath/ln.S/tutorial/trace-proof-1.ps
-%%Creator: XV Version 3.10a  Rev: 12/29/94  -  by John Bradley
-%%BoundingBox: 0 0 612 792
-%%Pages: 1
-%%DocumentFonts:
-%%EndComments
-%%EndProlog
-
-%%Page: 1 1
-
-% remember original state
-/origstate save def
-
-% build a temporary dictionary
-20 dict begin
-
-% define space for color conversions
-/grays 612 string def  % space for gray scale line
-/npixls 0 def
-/rgbindx 0 def
-
-% lower left corner
-0 0 translate
-
-% size of image (on paper, in 1/72inch coords)
-612.00000 792.00000 scale
-
-% define the colormap
-/cmap 6 string def
-
-
-% load up the colormap
-currentfile cmap readhexstring
-00 44 88 bf e5 ff 
-pop pop   % lose return values from readhexstring
-
-
-% rlecmapimage expects to have 'w h bits matrix' on stack
-/rlecmapimage {
-  /buffer 1 string def
-  /rgbval 3 string def
-  /block  384 string def
-
-  % proc to read a block from file, and return RGB data
-  { currentfile buffer readhexstring pop
-    /bcount exch 0 get store
-    bcount 128 ge
-    {  % it's a non-run block
-      0 1 bcount 128 sub
-      { currentfile buffer readhexstring pop pop
-
-        % look up value in gray map
-        /rgbval cmap buffer 0 get 1 getinterval store
-
-        % and put it in position i in block
-        block exch rgbval putinterval
-      } for
-      block  0  bcount 127 sub  getinterval
-    }
-
-    { % else it's a run block
-      currentfile buffer readhexstring pop pop
-
-      % look up value in graymap
-      /rgbval cmap buffer 0 get 1 getinterval store
-
-      0 1 bcount { block exch rgbval putinterval } for
-
-      block 0 bcount 1 add getinterval
-    } ifelse
-  } % end of proc
-  image
-} bind def
-
-
-612 792 8			% dimensions of data
-[612 0 0 -792 0 792]		% mapping matrix
-rlecmapimage
-
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-
-    { % else it's a run block
-      currentfile buffer readhexstring pop pop
-
-      % look up value in graymap
-      /rgbval cmap buffer 0 get 1 getinterval store
-
-      0 1 bcount { block exch rgbval putinterval } for
-
-      block 0 bcount 1 add getinterval
-    } ifelse
-  } % end of proc
-  image
-} bind def
-
-
-612 792 8			% dimensions of data
-[612 0 0 -792 0 792]		% mapping matrix
-rlecmapimage
-
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-
-%
-% Compression made this file 13.31% of the uncompressed size.
-%
-
-
-showpage
-
-% stop using temporary dictionary
-end
-
-% restore original state
-origstate restore
-
-%%Trailer
-
-%%EndDocument
- @endspecial 1839 5919 a Fp(26)p eop
-%%Page: 27 28
-27 27 bop 118 390 a Fo(Logic)25 b Fp(:)35 b(Logical)23
-b(syn)n(thesis)h(of)h(the)g Fm(netlist)38 b Fp(starting)24
-b(from)g(previously)f(optimized)i(b)r(eha)n(vioral)e(description.)p
-354 518 3155 4 v 354 668 4 151 v 410 625 a Fi($)43 b(logic)f(-s)h
-(adder)p 1115 625 27 4 v 29 w(us)p 1232 625 V 31 w(opt)f(adder)p
-1657 625 V 29 w(us)p 3506 668 4 151 v 354 671 3155 4
-v 911 3371 a @beginspecial 0 @llx 0 @lly 612 @urx 792
-@ury 2326 @rwi @setspecial
-%%BeginDocument: ./trace-logic-2.ps
-%!PS-Adobe-2.0 EPSF-2.0
-%%Title: /users/outil2/fitpath/ln.S/tutorial/trace-logic-2.ps
-%%Creator: XV Version 3.10a  Rev: 12/29/94  -  by John Bradley
-%%BoundingBox: 0 0 612 792
-%%Pages: 1
-%%DocumentFonts:
-%%EndComments
-%%EndProlog
-
-%%Page: 1 1
-
-% remember original state
-/origstate save def
-
-% build a temporary dictionary
-20 dict begin
-
-% define space for color conversions
-/grays 612 string def  % space for gray scale line
-/npixls 0 def
-/rgbindx 0 def
-
-% lower left corner
-0 0 translate
-
-% size of image (on paper, in 1/72inch coords)
-612.00000 792.00000 scale
-
-% define the colormap
-/cmap 6 string def
-
-
-% load up the colormap
-currentfile cmap readhexstring
-00 44 88 bf e5 ff 
-pop pop   % lose return values from readhexstring
-
-
-% rlecmapimage expects to have 'w h bits matrix' on stack
-/rlecmapimage {
-  /buffer 1 string def
-  /rgbval 3 string def
-  /block  384 string def
-
-  % proc to read a block from file, and return RGB data
-  { currentfile buffer readhexstring pop
-    /bcount exch 0 get store
-    bcount 128 ge
-    {  % it's a non-run block
-      0 1 bcount 128 sub
-      { currentfile buffer readhexstring pop pop
-
-        % look up value in gray map
-        /rgbval cmap buffer 0 get 1 getinterval store
-
-        % and put it in position i in block
-        block exch rgbval putinterval
-      } for
-      block  0  bcount 127 sub  getinterval
-    }
-
-    { % else it's a run block
-      currentfile buffer readhexstring pop pop
-
-      % look up value in graymap
-      /rgbval cmap buffer 0 get 1 getinterval store
-
-      0 1 bcount { block exch rgbval putinterval } for
-
-      block 0 bcount 1 add getinterval
-    } ifelse
-  } % end of proc
-  image
-} bind def
-
-
-612 792 8			% dimensions of data
-[612 0 0 -792 0 792]		% mapping matrix
-rlecmapimage
-
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-$F2psEnd
-rs
-
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-%%EOF
diff --git a/alliance/share/tutorials/fitpath/hierarchy_dpt.c b/alliance/share/tutorials/fitpath/hierarchy_dpt.c
deleted file mode 100644
index 37d0de5b..00000000
--- a/alliance/share/tutorials/fitpath/hierarchy_dpt.c
+++ /dev/null
@@ -1,158 +0,0 @@
-
-
-/*          Alliance CAD System V.R                                         */
-/*             FpGen Package V.RR                                           */
-/*                                                                          */
-/*  Copyright(c) 93-AA, MASI, CAO-VLSI Team                                 */
-/*                                                                          */
-/*  Author      :          Jean-Paul CHAPUT                                 */
-/*  E-mail      :      cao-vlsi@masi.ibp.fr                                 */
-/* ======================================================================== */
-/*  File        :      "hierarchy_dpt.c"                                    */
-/* ************************************************************************ */
-/*  Data-Path sample example.                                               */
-
-
-#include  <genlib.h>
-#include  <fpgen.h>
-
-
-static void  mkSubDP();
-
-
-static void  mkSubDP()
-{
-  /* Open the ALU part of the Data-Path.
-   * ===================================
-   */
-  DP_DEFLOFIG( "alu_dpt", 8, LSB_INDEX_ZERO );
-
-
-  /* Interface description.
-   * ======================
-   */
-
-  /* Control terminals declarations. */
-  DP_LOCON( "ctrl_ncout",   OUT, "ctrl_ncout" );
-  DP_LOCON( "ctrl_nover",   OUT, "ctrl_nover" );
-  DP_LOCON( "ctrl_zero" ,   OUT, "ctrl_zero"  );
-
-  /* Data terminals declarations. */
-  DP_LOCON( "data_a[7:0]" , IN   , "data_a[7:0]" );
-  DP_LOCON( "data_b[7:0]" , IN   , "data_b[7:0]" );
-  DP_LOCON( "data_s[7:0]" , INOUT, "data_s[7:0]" );
-
-  /* Power supplies terminals. */
-  DP_LOCON( "vdd", IN   , "vdd" );
-  DP_LOCON( "vss", IN   , "vss" );
-
-
-  /* Data-Path netlist description.
-   * ==============================
-   */
-
-  /* Fast Adder. */
-  DP_ADD2F( "adder",
-            "data_a[7:0]",
-            "data_b[7:0]",
-            "ctrl_ncout",
-            "ctrl_nover",
-            "data_s[7:0]",
-            EOL );
-
-  /* Zero Detect. */
-  DP_NUL( "zero", 8, 0,
-          "data_s[7:0]",
-          "ctrl_zero",
-          EOL );
-
-
-  /* Terminate the netlist description, and save on disk.
-   * ====================================================
-   */
-  DP_SAVLOFIG();
-}
-
-
-main()
-{
-  /* Generate the Zero Detect Column.
-   * ================================
-   */
-  mkSubDP();
-
-
-  /* Open a new Data-Path figure.
-   * ============================
-   */
-  DP_DEFLOFIG( "hierarchy_dpt", 8, LSB_INDEX_ZERO );
-
-
-  /* Interface description.
-   * ======================
-   */
-
-  /* Control terminals declarations. */
-  DP_LOCON( "ctrl_sel"  , IN   , "ctrl_sel"   );
-  DP_LOCON( "ctrl_ck"   , IN   , "ctrl_ck"    );
-  DP_LOCON( "ctrl_wen"  , IN   , "ctrl_wen"   );
-  DP_LOCON( "ctrl_ncout",   OUT, "ctrl_ncout" );
-  DP_LOCON( "ctrl_nover",   OUT, "ctrl_nover" );
-  DP_LOCON( "ctrl_zero" ,   OUT, "ctrl_zero"  );
-
-  /* Data terminals declarations. */
-  DP_LOCON( "data_a[7:0]" , IN   , "data_a[7:0]" );
-  DP_LOCON( "data_b[7:0]" , IN   , "data_b[7:0]" );
-  DP_LOCON( "data_s[7:0]" , INOUT, "data_s[7:0]" );
-
-  /* Power supplies terminals. */
-  DP_LOCON( "vdd", IN   , "vdd" );
-  DP_LOCON( "vss", IN   , "vss" );
-
-
-  /* Data-Path netlist description.
-   * ==============================
-   */
-
-  DP_TRACE( TRACE_ON );
-
-  /* Multiplexer. */
-  DP_MUX2CS( "multiplexer", 8, 0,
-             "ctrl_sel",
-             "data_b[7:0]",
-             "data_q[7:0]",
-             "data_m[7:0]",
-             EOL );
-
-  /* Fast Adder. */
-  DP_IMPORT( "alu_dpt",
-             "alu",
-             "ctrl_ncout",
-             "ctrl_nover",
-             "ctrl_zero",
-             "data_a[7:0]",
-             "data_m[7:0]",
-             "data_s[7:0]",
-             EOL );
-
-  /* Register. */
-  DP_PDFF( "memory", 8, 0,
-           "ctrl_wen",
-           "ctrl_ck",
-           "data_s[7:0]",
-           "data_q[7:0]",
-           "data_u[7:0]",  /* This bus is unused. */
-           EOL );
-
-
-  DP_TRACE( TRACE_OFF );
-
-  /* Terminate the netlist description, and save on disk.
-   * ====================================================
-   */
-  DP_SAVLOFIG();
-
-
-  /* A good C program must always terminate by an "exit(0)". */
-  exit(0);
-}
diff --git a/alliance/share/tutorials/fitpath/hierarchy_dpt.dpr b/alliance/share/tutorials/fitpath/hierarchy_dpt.dpr
deleted file mode 100644
index 14147641..00000000
--- a/alliance/share/tutorials/fitpath/hierarchy_dpt.dpr
+++ /dev/null
@@ -1,27 +0,0 @@
-#
-#
-# /*          Alliance CAD System V.R                                       */
-# /*             FpGen Package V.RR                                         */
-# /*                                                                        */
-# /*  Copyright(c) 93-AA, MASI, CAO-VLSI Team                               */
-# /*                                                                        */
-# /*  Author      :          Jean-Paul CHAPUT                               */
-# /*  E-mail      :      cao-vlsi@masi.ibp.fr                               */
-# /* ====================================================================== */
-# /*  File        :      "hierarchy_dpt.dpr"                                */
-# /* ********************************************************************** */
-# /*  Hierarchical Data-Path example.                                       */
-#
-#
-#           Terminal :  Side  :  Slice  :  Track
-DP_LOCON   ctrl_zero   NORTH    DEFAULT   DEFAULT
-#
-#
-#           Terminal :  Side  :  Slice  :  Track
-DP_LOCON  data_a[7:0]   WEST    DEFAULT   DEFAULT
-DP_LOCON  data_b[7:0]   WEST    DEFAULT   DEFAULT
-DP_LOCON  data_s[7:0]   EAST    DEFAULT   DEFAULT
-#
-#
-# Number of vertical power refreshment.
-DP_POWER  1  50
diff --git a/alliance/share/tutorials/fitpath/hierarchy_dpt.inf b/alliance/share/tutorials/fitpath/hierarchy_dpt.inf
deleted file mode 100644
index 8403b3dd..00000000
--- a/alliance/share/tutorials/fitpath/hierarchy_dpt.inf
+++ /dev/null
@@ -1,4 +0,0 @@
-RENAME
-  memory.pdff_*.memm_s : memory_m(*) ;
-  memory.pdff_*.mems_s : memory_s(*) ;
-END
diff --git a/alliance/share/tutorials/fitpath/hierarchy_dpt.sh b/alliance/share/tutorials/fitpath/hierarchy_dpt.sh
deleted file mode 100755
index 8ca5c06a..00000000
--- a/alliance/share/tutorials/fitpath/hierarchy_dpt.sh
+++ /dev/null
@@ -1,105 +0,0 @@
-#!/bin/sh
-
-
-#
-#
-# /*          Alliance CAD System V.R                                       */
-# /*             FpGen Package V.RR                                         */
-# /*                                                                        */
-# /*  Copyright(c) 93-AA, MASI, CAO-VLSI Team                               */
-# /*                                                                        */
-# /*  Author      :          Jean-Paul CHAPUT                               */
-# /*  E-mail      :      cao-vlsi@masi.ibp.fr                               */
-# /* ====================================================================== */
-# /*  File        :      "hierarchy_dpt.sh"                                 */
-# /* ********************************************************************** */
-# /*  Data-Path using hierarchical description.                             */
-#
-#
-
-
-# Installation Dependent Variables.
-#           ALLIANCE_TOP=/labo
-
-
-# FpGen Macro-Operators Library.
-     FPGEN_LIB=./mclib; export FPGEN_LIB
-
-
-# MBK Enviroment variables settings.
-     MBK_IN_PH=ap;      export MBK_IN_PH
-     MBK_IN_LO=vst;     export MBK_IN_LO
-    MBK_OUT_PH=ap;      export MBK_OUT_PH
-    MBK_OUT_LO=vst;     export MBK_OUT_LO
-  MBK_WORK_LIB=.;       export MBK_WORK_LIB
-  MBK_CATA_LIB=$ALLIANCE_TOP/cells/fitpath/fplib:$ALLIANCE_TOP/cells/rsa:$FPGEN_LIB
-                        export MBK_CATA_LIB
-MBK_CATAL_NAME=CATAL;   export MBK_CATAL_NAME
-       MBK_VDD=vdd;     export MBK_VDD
-       MBK_VSS=vss;     export MBK_VSS
-
-#
-#
-# FpGen : Generation of the Netlist.
-# ==================================
-#
-fpgen -v hierarchy_dpt
-
-
-#
-#
-# DPR : Routing the data-path.
-# ============================
-#
-dpr -V -p -o -r hierarchy_dpt hierarchy_dpt
-
-
-#
-#
-# DRUC : Symbolic Design RUles Checker.
-# =====================================
-#
-druc sample_dpt
-
-
-#
-#
-# LYNX : Gate level netlist extraction.
-# =====================================
-#
-MBK_OUT_LO=al
- MBK_IN_LO=al
-
-lynx -v -f hierarchy_dpt hierarchy_dpt_gates
-
-
-#
-#
-# LVX : Netlist comparison.
-# =========================
-#
-lvx vst al hierarchy_dpt hierarchy_dpt_gates -f
-
-
-#
-#
-# LYNX : Transistor netlist extraction.
-# =====================================
-#
-lynx -v -t hierarchy_dpt hierarchy_dpt
-
-
-#
-#
-# DESB : Behavioral exctraction.
-# ==============================
-#
-desb hierarchy_dpt hierarchy_dpt_desb -v -i
-
-
-#
-#
-# PROOF : Formal proof.
-# =====================
-#
-proof -d sample_dpt hierarchy_dpt_desb
diff --git a/alliance/share/tutorials/fitpath/make.LOG b/alliance/share/tutorials/fitpath/make.LOG
deleted file mode 100644
index ff03b0fb..00000000
--- a/alliance/share/tutorials/fitpath/make.LOG
+++ /dev/null
@@ -1,3024 +0,0 @@
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB; MBK_OUT_LO=vst; export MBK_OUT_LO; MBK_IN_LO=vst; export MBK_IN_LO; MBK_OUT_PH=ap;  export MBK_OUT_PH; MBK_IN_PH=ap;  export MBK_IN_PH;  /users/outil2/fitpath/dev/Solaris/bin/fpgen -v sample_dpt
-
-             @@@@@@@@@                @@@@ @                        
-               @@    @              @@    @@                        
-               @@     @            @@      @                        
-               @@       @@@ @@@   @@             @@@@@   @@@ @@@    
-               @@   @    @@@  @@  @@            @     @   @@@   @   
-               @@@@@@    @@    @@ @@     @@@@@ @@     @@  @@    @@  
-               @@   @    @@    @@ @@     @ @@  @@@@@@@@@  @@    @@  
-               @@        @@    @@ @@    @  @@  @@         @@    @@  
-               @@        @@    @@  @@      @@  @@      @  @@    @@  
-               @@        @@@  @@    @@    @@    @@    @@  @@    @@  
-             @@@@@@      @@ @@@       @@@@        @@@@   @@@@  @@@@ 
-                         @@                                         
-                        @@@@                                        
-
-                           Fitpath Generation Language         
-
-                 Alliance CAD System V.R,           fpgen V.RR 
-                 Copyright (c) 93-AA,           ASIM/LIP6/UPMC 
-                 E-mail support: alliance-support@asim.lip6.fr 
-
-
-  o  Alliance Devellopment environment:
-     - DEVEL_TOP       : /users/outil2/fitpath/dev/Solaris
-     - DEVEL_VERSION   : 113
-  o  Current Alliance environment:
-     - ALLIANCE_TOP    : not set
-     -      MACHINE    : Solaris
-  o  Current MBK environment:
-     - MBK_IN_LO       : vst
-     - MBK_OUT_LO      : vst
-     - MBK_IN_PH       : ap
-     - MBK_OUT_PH      : ap
-     - MBK_WORK_LIB    : .
-     - MBK_CATA_LIB    : ./mclib
-                         /users/soft5/newlabo/Solaris/cells/rsa
-                         /users/outil2/fitpath/labo/cells/fplib
-                         /users/outil2/fitpath/labo/cells/dplib
-     - MBK_CATAL_NAME  : CATAL
-     - MBK_VDD         : vdd
-     - MBK_VSS         : vss
-     - RDS_TECHNO_NAME : not set
-  o  FpGen Macro-Functions library:
-     - FPGEN_LIB       : ./mclib
-
-  o  Program generation.
-     - Creating Makefile.
-     - Running Makefile.
-  o  Execute program...
-     - Exit code := 0.
-
-  o  Remove temporary file.
-
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB; MBK_OUT_LO=vst; export MBK_OUT_LO; MBK_IN_LO=vst; export MBK_IN_LO; MBK_OUT_PH=ap;  export MBK_OUT_PH; MBK_IN_PH=ap;  export MBK_IN_PH;      /users/outil3/dpr/labo/Solaris/bin/dpr -V -p -r sample_dpt sample_dpt
-
-                       @@@@@@@     @@@@@@@    @@@@@@@    
-                         @@   @@     @@   @@    @@   @@  
-                         @@    @@    @@    @@   @@    @@ 
-                         @@     @@   @@    @@   @@    @@ 
-                         @@     @@   @@   @@    @@   @@  
-                         @@     @@   @@@@@      @@@@@    
-                         @@     @@   @@         @@  @@   
-                         @@     @@   @@         @@   @@  
-                         @@    @@    @@         @@   @@  
-                         @@   @@     @@         @@    @@ 
-                       @@@@@@@     @@@@@@     @@@@@   @@@
-
-                       Placer-Router for Datapath Compiler
-
-                  Alliance CAD System 3.2b,             dpr 6.2
-                  Copyright (c) 1994-1997,       ASIM/LIP6/UPMC
-                  E-mail support: alliance-support@asim.lip6.fr
-
-
- * MBK parameters :
-
-       MBK_WORK_LIB   : .
-       MBK_CATA_LIB   : ./mclib
-                      : /users/soft5/newlabo/Solaris/cells/rsa
-                      : /users/outil2/fitpath/labo/cells/fplib
-                      : /users/outil2/fitpath/labo/cells/dplib
-       MBK_IN_PH      : ap
-       MBK_OUT_PH     : ap
-       MBK_IN_LO      : vst
-       MBK_OUT_LO     : vst
-       TECHNO         : CMOS
-
- * Placement step.
-   o Getting netlist.
-   o Getting dpr file.
-   o Building symbolic grid.
-     -> Routed bloc : 'memory' (pdff_8x8x0l_cl).
-     -> Routed bloc : 'zero' (nul_8x8x0l_cl).
-     -> Routed bloc : 'adder' (add2f_8x8x0l_bk).
-     -> Routed bloc : 'multiplexer' (mux2cs_8x8x0l_cl).
-   o Ckecking slices heights.
-
-   o Nb slices : 10.
-   o Nb cols   : 4.
-
-   o Creating column.
-   o Creating glue logic blocs.
-   o Checking alims correspondances.
-   o Creating global phfig view.
-     Moving connector data_s 0 on EAST side, slice 0, default track.
-     Moving connector data_s 1 on EAST side, slice 1, default track.
-     Moving connector data_s 2 on EAST side, slice 2, default track.
-     Moving connector data_s 3 on EAST side, slice 3, default track.
-     Moving connector data_s 4 on EAST side, slice 4, default track.
-     Moving connector data_s 5 on EAST side, slice 5, default track.
-     Moving connector data_s 6 on EAST side, slice 6, default track.
-     Moving connector data_s 7 on EAST side, slice 7, default track.
-     Moving connector data_b 0 on WEST side, slice 0, default track.
-     Moving connector data_b 1 on WEST side, slice 1, default track.
-     Moving connector data_b 2 on WEST side, slice 2, default track.
-     Moving connector data_b 3 on WEST side, slice 3, default track.
-     Moving connector data_b 4 on WEST side, slice 4, default track.
-     Moving connector data_b 5 on WEST side, slice 5, default track.
-     Moving connector data_b 6 on WEST side, slice 6, default track.
-     Moving connector data_b 7 on WEST side, slice 7, default track.
-     Moving connector data_a 0 on WEST side, slice 0, default track.
-     Moving connector data_a 1 on WEST side, slice 1, default track.
-     Moving connector data_a 2 on WEST side, slice 2, default track.
-     Moving connector data_a 3 on WEST side, slice 3, default track.
-     Moving connector data_a 4 on WEST side, slice 4, default track.
-     Moving connector data_a 5 on WEST side, slice 5, default track.
-     Moving connector data_a 6 on WEST side, slice 6, default track.
-     Moving connector data_a 7 on WEST side, slice 7, default track.
-   o Freeing symbolic grid.
- * Placement done.
-
- * Routing step.
-   o Loading physical and logical views.
-   o Setting access types.
-      -> pdff_8x8x0l_cl.
-      -> nul_8x8x0l_cl.
-      -> add2f_8x8x0l_bk.
-      -> mux2cs_8x8x0l_cl.
-   o Checking logical and physical correspondance.
-      -> Signal data_u_7 not connected to any other terminal.
-      -> Signal data_u_6 not connected to any other terminal.
-      -> Signal data_u_5 not connected to any other terminal.
-      -> Signal data_u_4 not connected to any other terminal.
-      -> Signal data_u_3 not connected to any other terminal.
-      -> Signal data_u_2 not connected to any other terminal.
-      -> Signal data_u_1 not connected to any other terminal.
-      -> Signal data_u_0 not connected to any other terminal.
-   o Making DPR data structure.
-     -> External North/South terminal ctrl_zero replaced.
-   o Global routing.
-   o Bit-slice symbolic routing.
-     -> Bit-slice 0.
-     -> Bit-slice 1.
-     -> Bit-slice 2.
-     -> Bit-slice 3.
-     -> Bit-slice 4.
-     -> Bit-slice 5.
-     -> Bit-slice 6.
-     -> Bit-slice 7.
-     -> Bit-slice 8.
-     -> Bit-slice 9.
-   o Multi-bit net symbolic routing.
-     -> Left connectors column.
-     -> Column 1.
-     -> Column 2.
-     -> Column 3.
-     -> Column 4.
-     -> Right connectors column.
-   o Channel routing.
-     -> Channel 1.
-     -> Channel 2.
-     -> Channel 3.
-     -> Channel 4.
-     -> Channel 5.
-   o Saving physical figure sample_dpt.
-     -> Column 1.
-     -> Column 2.
-     -> Column 3.
-     -> Column 4.
-   o Checking for short cut.
-     -> Instance memory(pdff_8x8x0l_cl).
-     -> Instance zero(nul_8x8x0l_cl).
-     -> Instance adder(add2f_8x8x0l_bk).
-     -> Instance multiplexer(mux2cs_8x8x0l_cl).
-   o Total routing time: 1 seconds.
- * Routing step done.
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB; MBK_OUT_LO=vst; export MBK_OUT_LO; MBK_IN_LO=vst; export MBK_IN_LO; MBK_OUT_PH=ap;  export MBK_OUT_PH; MBK_IN_PH=ap;  export MBK_IN_PH; /users/soft5/newlabo/Solaris/bin/druc sample_dpt
-
-                  @@@@@@@     @@@@@@@                    @@@@ @
-                    @@   @@     @@   @@                @@    @@
-                    @@    @@    @@    @@              @@      @
-                    @@     @@   @@    @@  @@@  @@@@  @@       @
-                    @@     @@   @@   @@    @@    @@  @@        
-                    @@     @@   @@@@@      @@    @@  @@        
-                    @@     @@   @@  @@     @@    @@  @@        
-                    @@     @@   @@   @@    @@    @@  @@        
-                    @@    @@    @@   @@    @@    @@   @@      @
-                    @@   @@     @@    @@   @@   @@@    @@    @@
-                  @@@@@@@     @@@@@   @@@   @@@@  @@     @@@@  
-
-                               Design Rule Checker
-
-                     Alliance CAD System 3.2,      druc 3.00
-                     Copyright (c) 1993, MASI, CAO-VLSI Team
-                     E-mail support:    cao-vlsi@masi.ibp.fr
-
-Flatten DRC on: sample_dpt
-Delete MBK figure : sample_dpt
-Load Flatten Rules : /users/alc/distrib/dev/alliance-3.2b/etc/cmos_7.rds
-
-Unify : sample_dpt
-
-Create Ring : sample_dpt_rng
-Merge Errorfiles: 
-
-Merge Error Instances:
-instructionCourante : 000  0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
-End DRC on: sample_dpt
-Saving the Error file figure
-Done
-  0
-
-File: sample_dpt.drc is empty: no errors detected.
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB; MBK_OUT_LO=al;  export MBK_OUT_LO; MBK_IN_LO=al;  export MBK_IN_LO;  MBK_OUT_PH=ap;  export MBK_OUT_PH; MBK_IN_PH=ap;  export MBK_IN_PH; /users/soft5/newlabo/Solaris/bin/lynx -v -f sample_dpt sample_dpt_gates
-
-                   @@@@@@                                    
-                     @@                                      
-                     @@                                      
-                     @@        @@@@@ @@@ @@@ @@@    @@@@  @@@
-                     @@         @@    @   @@@   @    @@    @ 
-                     @@          @@   @   @@    @@    @@  @  
-                     @@          @@  @    @@    @@     @@@   
-                     @@           @@ @    @@    @@     @@@   
-                     @@      @    @@@     @@    @@    @  @@  
-                     @@     @      @@     @@    @@   @    @@ 
-                   @@@@@@@@@@  @@  @     @@@@  @@@@ @@@  @@@@
-                               @@  @                         
-                                @@@                          
-
-                                Netlist extractor
-
-                     Alliance CAD System 3.2,      lynx 1.16
-                     Copyright (c) 1997, MASI, CAO-VLSI Team
-                     E-mail support:    cao-vlsi@masi.ibp.fr
-
-
-
-	---> Extracts symbolic figure sample_dpt
-
-		---> Flatten figure
-
-		---> Translate Mbk -> Rds
-		---> Build windows
-		<--- 280
-
-		---> Rectangles    : 3113
-		---> Figure size   : (   -100,   -400 )
-		                     (  43400,  60400 )
-
-		---> Cut transistors
-		<--- 0
-		---> Build equis
-		<--- 56
-		---> Delete windows
-		---> Build signals
-		<--- 56
-		---> Build instances
-		<--- 4
-		---> Build transistors
-		<--- 0
-		---> Save netlist
-
-	<--- done !
-
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB;                        /users/soft5/newlabo/Solaris/bin/lvx vst al sample_dpt sample_dpt_gates -f
-
-                       @@@@@@      @@@@    @@@ @@@@   @@@@
-                         @@         @@      @   @@     @  
-                         @@         @@      @    @@   @   
-                         @@          @@    @      @@ @    
-                         @@          @@    @       @@     
-                         @@           @@  @        @@     
-                         @@           @@  @        @@@    
-                         @@            @@@        @  @@   
-                         @@      @     @@@       @    @@  
-                         @@     @       @       @      @@ 
-                       @@@@@@@@@@       @      @@@    @@@@
-
-                             Gate Netlist Comparator
-
-                   Alliance CAD System 3.2,          lvx 2.23
-                   Copyright (c) 1992-93, MASI, CAO-VLSI Team
-                   E-mail support:       cao-vlsi@masi.ibp.fr
-
-
-
-***** Loading and flattening sample_dpt (vst)...
-
-***** Loading and flattening sample_dpt_gates (al)...
-
-
-***** Compare Terminals ..................
-***** O.K.	(0 sec)
-
-***** Compare Instances ..........
-***** O.K.	(0 sec)
-
-***** Compare Connections ............
-***** O.K.	(0 sec)
-
-===== Terminals .......... 32    
-===== Instances .......... 4     
-===== Connectors ......... 151   
-
-
-***** Netlists are Identical. *****	(0 sec)
-
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB; MBK_OUT_LO=al;  export MBK_OUT_LO; MBK_IN_LO=al;  export MBK_IN_LO;  MBK_OUT_PH=ap;  export MBK_OUT_PH; MBK_IN_PH=ap;  export MBK_IN_PH; /users/soft5/newlabo/Solaris/bin/lynx -v -t sample_dpt sample_dpt
-
-                   @@@@@@                                    
-                     @@                                      
-                     @@                                      
-                     @@        @@@@@ @@@ @@@ @@@    @@@@  @@@
-                     @@         @@    @   @@@   @    @@    @ 
-                     @@          @@   @   @@    @@    @@  @  
-                     @@          @@  @    @@    @@     @@@   
-                     @@           @@ @    @@    @@     @@@   
-                     @@      @    @@@     @@    @@    @  @@  
-                     @@     @      @@     @@    @@   @    @@ 
-                   @@@@@@@@@@  @@  @     @@@@  @@@@ @@@  @@@@
-                               @@  @                         
-                                @@@                          
-
-                                Netlist extractor
-
-                     Alliance CAD System 3.2,      lynx 1.16
-                     Copyright (c) 1997, MASI, CAO-VLSI Team
-                     E-mail support:    cao-vlsi@masi.ibp.fr
-
-
-
-	---> Extracts symbolic figure sample_dpt
-
-		---> Flatten figure
-
-		---> Translate Mbk -> Rds
-		---> Build windows
-		<--- 280
-
-		---> Rectangles    : 16653
-		---> Figure size   : (   -100,   -400 )
-		                     (  43400,  60400 )
-
-		---> Cut transistors
-		<--- 20
-		---> Build equis
-		<--- 315
-		---> Delete windows
-		---> Build signals
-		<--- 315
-		---> Build instances
-		<--- 0
-		---> Build transistors
-		<--- 600
-		---> Save netlist
-
-	<--- done !
-
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB; MBK_OUT_LO=al;  export MBK_OUT_LO; MBK_IN_LO=al;  export MBK_IN_LO;             /users/soft5/newlabo/Solaris/bin/yagle sample_dpt sample_dpt_desb -v -i
-
-                                               @@@@            
-                                                 @@            
-                                                 @@            
-                  @@@@@ @@@   @@@@      @@@@@@   @@     @@@@@  
-                   @@    @   @@   @    @@  @@    @@    @     @ 
-                    @@   @   @@   @@   @   @@    @@   @@     @@
-                    @@  @      @@@@@   @   @     @@   @@@@@@@@@
-                     @@ @    @@   @@    @@@      @@   @@       
-                     @@@    @@    @@   @@        @@   @@      @
-                      @@    @@   @@@   @@@@@@    @@    @@    @@
-                  @@  @      @@@@  @@ @@   @@@ @@@@@@    @@@@  
-                  @@  @                @     @                 
-                   @@@                  @@@@@                  
-
-                        Yet Another Gate Level Extractor
-
-                  Alliance CAD System 3.2,           yagle 2.02
-                  Copyright (c) 94-97-1997,      ASIM/LIP6/UPMC
-                  E-mail support: alliance-support@asim.lip6.fr
-
-[YAG MES] Reading file 'sample_dpt.inf'
-[YAG MES] Loading the figure sample_dpt            00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Transistor netlist checking              00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Extracting CMOS duals                    00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Extracting bleeders                      00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Making gates                             00m01s  u:00m00.3  s:00m00.0
-[YAG MES] Latches detection                        00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Making cells                             00m00s  u:00m00.0  s:00m00.0
-[YAG MES] External connector verification          00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Checking the yagle figure                00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Building the behavioural figure          00m00s  u:00m00.0  s:00m00.0
-TOTAL DISASSEMBLY TIME                             00m01s  u:00m00.3  s:00m00.0
-------------------------------------------------------------
-[YAG MES] Erasing the transistor netlist
-[YAG MES] Generating the VHDL Data Flow
-[YAG MES] Execution COMPLETED 
-------------------------------------------------------------
-[YAG WAR 07] 16 transistors are not used 
-[YAG WAR 09] 16 latches detected
-[YAG WAR 14] 1 conflicts may occur in the circuit
-See file 'sample_dpt.rep' for more information
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB;                        /users/soft5/newlabo/Solaris/bin/proof -d sample_dpt sample_dpt_desb
-
-                @@@@@@@                                     @@@ 
-                  @@   @@                                  @  @@
-                  @@    @@                                @@  @@
-                  @@    @@ @@@ @@@     @@@       @@@      @@    
-                  @@   @@   @@@  @@  @@   @@   @@   @@  @@@@@@@@
-                  @@@@@     @@   @@ @@     @@ @@     @@   @@    
-                  @@        @@      @@     @@ @@     @@   @@    
-                  @@        @@      @@     @@ @@     @@   @@    
-                  @@        @@      @@     @@ @@     @@   @@    
-                  @@        @@       @@   @@   @@   @@    @@    
-                @@@@@@     @@@@        @@@       @@@    @@@@@@  
-
-                                  Formal Proof
-
-                Alliance CAD System 3.2b, proof 4.20 [1997/10/09]
-                Copyright (c) 1990-1997,           ASIM/LIP6/UPMC
-                E-mail support:     alliance-support@asim.lip6.fr
-
-================================  Environment  ================================
-MBK_WORK_LIB		= .
-MBK_CATA_LIB		= ./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib
-=======================  Files, Options and Parameters  =======================
-First VHDL file		= sample_dpt.vbe
-Second VHDL file	= sample_dpt_desb.vbe
-The auxiliary signals are erased
-Errors are displayed
-===============================================================================
-
-Compiling 'sample_dpt' ...
-Compiling 'sample_dpt_desb' ...
-WARNING : data_s_0 is considered as an output signal
-WARNING : data_s_1 is considered as an output signal
-WARNING : data_s_2 is considered as an output signal
-WARNING : data_s_3 is considered as an output signal
-WARNING : data_s_4 is considered as an output signal
-WARNING : data_s_5 is considered as an output signal
-WARNING : data_s_6 is considered as an output signal
-WARNING : data_s_7 is considered as an output signal
-WARNING : data_s_0 is considered as an output signal
-WARNING : data_s_1 is considered as an output signal
-WARNING : data_s_2 is considered as an output signal
-WARNING : data_s_3 is considered as an output signal
-WARNING : data_s_4 is considered as an output signal
-WARNING : data_s_5 is considered as an output signal
-WARNING : data_s_6 is considered as an output signal
-WARNING : data_s_7 is considered as an output signal
-WARNING : ctrl_nover is considered as an output signal
-
-Running abl ordonnancer on `sample_dpt`
-...........................
-
-Running Abl2Bdd on `sample_dpt`
----> final number of nodes = 1008(633)
-
-Warning : Input 'mbk_sig285' only exists in the second description
-Running Abl2Bdd on `sample_dpt_desb`
-
-Running abl ordonnancer on `sample_dpt`
-...........................
-
-Running Abl2Bdd on `sample_dpt`
----> final number of nodes = 2055(633)
-
-Running Abl2Bdd on `sample_dpt_desb`
---------------------------------------------------------------------------------
-             Formal proof with Ordered Binary Decision Diagrams between   
-
-             './sample_dpt'  and  './sample_dpt_desb'
---------------------------------------------------------------------------------
-==============================  PRIMARY OUTPUT  ===============================
-=============================  AUXILIARY SIGNAL  ==============================
-==============================  REGISTER SIGNAL  ==============================
-===============================  EXTERNAL BUS =================================
-================================ INTERNAL BUS =================================
-
-                            Formal Proof : OK
-
-pppppppppppppppppppppppprrrrrrrrrrrrooooooooooooooooooooooooooooofffffffffffffff
---------------------------------------------------------------------------------
-
-
-
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB; MBK_OUT_LO=vst; export MBK_OUT_LO; MBK_IN_LO=vst; export MBK_IN_LO; MBK_OUT_PH=ap;  export MBK_OUT_PH; MBK_IN_PH=ap;  export MBK_IN_PH;  /users/outil2/fitpath/dev/Solaris/bin/fpgen -v place_dpt
-
-             @@@@@@@@@                @@@@ @                        
-               @@    @              @@    @@                        
-               @@     @            @@      @                        
-               @@       @@@ @@@   @@             @@@@@   @@@ @@@    
-               @@   @    @@@  @@  @@            @     @   @@@   @   
-               @@@@@@    @@    @@ @@     @@@@@ @@     @@  @@    @@  
-               @@   @    @@    @@ @@     @ @@  @@@@@@@@@  @@    @@  
-               @@        @@    @@ @@    @  @@  @@         @@    @@  
-               @@        @@    @@  @@      @@  @@      @  @@    @@  
-               @@        @@@  @@    @@    @@    @@    @@  @@    @@  
-             @@@@@@      @@ @@@       @@@@        @@@@   @@@@  @@@@ 
-                         @@                                         
-                        @@@@                                        
-
-                           Fitpath Generation Language         
-
-                 Alliance CAD System V.R,           fpgen V.RR 
-                 Copyright (c) 93-AA,           ASIM/LIP6/UPMC 
-                 E-mail support: alliance-support@asim.lip6.fr 
-
-
-  o  Alliance Devellopment environment:
-     - DEVEL_TOP       : /users/outil2/fitpath/dev/Solaris
-     - DEVEL_VERSION   : 113
-  o  Current Alliance environment:
-     - ALLIANCE_TOP    : not set
-     -      MACHINE    : Solaris
-  o  Current MBK environment:
-     - MBK_IN_LO       : vst
-     - MBK_OUT_LO      : vst
-     - MBK_IN_PH       : ap
-     - MBK_OUT_PH      : ap
-     - MBK_WORK_LIB    : .
-     - MBK_CATA_LIB    : ./mclib
-                         /users/soft5/newlabo/Solaris/cells/rsa
-                         /users/outil2/fitpath/labo/cells/fplib
-                         /users/outil2/fitpath/labo/cells/dplib
-     - MBK_CATAL_NAME  : CATAL
-     - MBK_VDD         : vdd
-     - MBK_VSS         : vss
-     - RDS_TECHNO_NAME : not set
-  o  FpGen Macro-Functions library:
-     - FPGEN_LIB       : ./mclib
-
-  o  Program generation.
-     - Creating Makefile.
-     - Running Makefile.
-  o  Execute program...
-FpGen:DP_TRACE:Trace mode ON at line 54 of file "place_dpt.c".
-*** FpGen Trace ***:
-      Macro-Function : DP_NUL.
-    (char *)InstName : (0x000E0C30) "zero".
-         (long)Width : (0x--------)  8.
-         (long)Slice : (0x--------)  0.
-             [ Model : "nul_8x8x0l_cl" : Generated on memory ]
-      (char *)Signal : (0x000E0C00) "data_s[7:0]".
-      (char *)Signal : (0x000E0BD0) "ctrl_zero".
-      (char *)Signal : (0x00000000) --> EOL.
-*** FpGen xvLoins ***:MBK terminals assigments (reverse order):
-                   o => ctrl_zero
-             i0[0:7] => data_s[0:7]
-*** FpGen Trace ***:
-      Macro-Function : DP_MUX2CS.
-    (char *)InstName : (0x000E0C38) "multiplexer".
-         (long)Width : (0x--------)  8.
-         (long)Slice : (0x--------)  0.
-             [ Model : "mux2cs_8x8x0l_cl" : Generated on memory ]
-      (char *)Signal : (0x000E0B88) "ctrl_sel".
-      (char *)Signal : (0x000E0BF0) "data_b[7:0]".
-      (char *)Signal : (0x000E0C48) "data_q[7:0]".
-      (char *)Signal : (0x000E0C58) "data_m[7:0]".
-      (char *)Signal : (0x00000000) --> EOL.
-*** FpGen xvLoins ***:MBK terminals assigments (reverse order):
-              o[0:7] => data_m[0:7]
-             i0[0:7] => data_q[0:7]
-             i1[0:7] => data_b[0:7]
-                 sel => ctrl_sel
-*** FpGen Trace ***:
-      Macro-Function : DP_ADD2F.
-    (char *)InstName : (0x000E0C68) "adder".
-             [ Model : "add2f_8x8x0l_bk" : Generated on memory ]
-      (char *)Signal : (0x000E0BE0) "data_a[7:0]".
-      (char *)Signal : (0x000E0C58) "data_m[7:0]".
-      (char *)Signal : (0x000E0BB0) "ctrl_ncout".
-      (char *)Signal : (0x000E0BC0) "ctrl_nover".
-      (char *)Signal : (0x000E0C00) "data_s[7:0]".
-      (char *)Signal : (0x00000000) --> EOL.
-*** FpGen xvLoins ***:MBK terminals assigments (reverse order):
-              s[0:7] => data_s[0:7]
-              over_n => ctrl_nover
-              cout_n => ctrl_ncout
-              b[0:7] => data_m[0:7]
-              a[0:7] => data_a[0:7]
-*** FpGen Trace ***:
-      Macro-Function : DP_PDFF.
-    (char *)InstName : (0x000E0C70) "memory".
-         (long)Width : (0x--------)  8.
-         (long)Slice : (0x--------)  0.
-             [ Model : "pdff_8x8x0l_cl" : Generated on memory ]
-      (char *)Signal : (0x000E0BA0) "ctrl_wen".
-      (char *)Signal : (0x000E0B98) "ctrl_ck".
-      (char *)Signal : (0x000E0C00) "data_s[7:0]".
-      (char *)Signal : (0x000E0C48) "data_q[7:0]".
-      (char *)Signal : (0x000E0C78) "data_u[7:0]".
-      (char *)Signal : (0x00000000) --> EOL.
-*** FpGen xvLoins ***:MBK terminals assigments (reverse order):
-             nq[0:7] => data_u[0:7]
-              q[0:7] => data_q[0:7]
-              d[0:7] => data_s[0:7]
-                  ck => ctrl_ck
-                 wen => ctrl_wen
-FpGen:DP_TRACE:Trace mode OFF at line 89 of file "place_dpt.c".
-     - Exit code := 0.
-
-  o  Remove temporary file.
-
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB; MBK_OUT_LO=vst; export MBK_OUT_LO; MBK_IN_LO=vst; export MBK_IN_LO; MBK_OUT_PH=ap;  export MBK_OUT_PH; MBK_IN_PH=ap;  export MBK_IN_PH;      /users/outil3/dpr/labo/Solaris/bin/dpr -V -o -p -r place_dpt place_dpt
-
-                       @@@@@@@     @@@@@@@    @@@@@@@    
-                         @@   @@     @@   @@    @@   @@  
-                         @@    @@    @@    @@   @@    @@ 
-                         @@     @@   @@    @@   @@    @@ 
-                         @@     @@   @@   @@    @@   @@  
-                         @@     @@   @@@@@      @@@@@    
-                         @@     @@   @@         @@  @@   
-                         @@     @@   @@         @@   @@  
-                         @@    @@    @@         @@   @@  
-                         @@   @@     @@         @@    @@ 
-                       @@@@@@@     @@@@@@     @@@@@   @@@
-
-                       Placer-Router for Datapath Compiler
-
-                  Alliance CAD System 3.2b,             dpr 6.2
-                  Copyright (c) 1994-1997,       ASIM/LIP6/UPMC
-                  E-mail support: alliance-support@asim.lip6.fr
-
-
- * MBK parameters :
-
-       MBK_WORK_LIB   : .
-       MBK_CATA_LIB   : ./mclib
-                      : /users/soft5/newlabo/Solaris/cells/rsa
-                      : /users/outil2/fitpath/labo/cells/fplib
-                      : /users/outil2/fitpath/labo/cells/dplib
-       MBK_IN_PH      : ap
-       MBK_OUT_PH     : ap
-       MBK_IN_LO      : vst
-       MBK_OUT_LO     : vst
-       TECHNO         : CMOS
-
- * Placement step.
-   o Getting netlist.
-   o Getting dpr file.
-   o Building symbolic grid.
-     -> Routed bloc : 'memory' (pdff_8x8x0l_cl).
-     -> Routed bloc : 'adder' (add2f_8x8x0l_bk).
-     -> Routed bloc : 'multiplexer' (mux2cs_8x8x0l_cl).
-     -> Routed bloc : 'zero' (nul_8x8x0l_cl).
-   o Ckecking slices heights.
-
-   o Nb slices : 10.
-   o Nb cols   : 4.
-
-   o Creating column.
-   o Creating glue logic blocs.
-   o Checking alims correspondances.
-   o Creating global phfig view.
-     Moving connector data_s 0 on EAST side, slice 0, default track.
-     Moving connector data_s 1 on EAST side, slice 1, default track.
-     Moving connector data_s 2 on EAST side, slice 2, default track.
-     Moving connector data_s 3 on EAST side, slice 3, default track.
-     Moving connector data_s 4 on EAST side, slice 4, default track.
-     Moving connector data_s 5 on EAST side, slice 5, default track.
-     Moving connector data_s 6 on EAST side, slice 6, default track.
-     Moving connector data_s 7 on EAST side, slice 7, default track.
-     Moving connector data_b 0 on WEST side, slice 0, default track.
-     Moving connector data_b 1 on WEST side, slice 1, default track.
-     Moving connector data_b 2 on WEST side, slice 2, default track.
-     Moving connector data_b 3 on WEST side, slice 3, default track.
-     Moving connector data_b 4 on WEST side, slice 4, default track.
-     Moving connector data_b 5 on WEST side, slice 5, default track.
-     Moving connector data_b 6 on WEST side, slice 6, default track.
-     Moving connector data_b 7 on WEST side, slice 7, default track.
-     Moving connector data_a 0 on WEST side, slice 0, default track.
-     Moving connector data_a 1 on WEST side, slice 1, default track.
-     Moving connector data_a 2 on WEST side, slice 2, default track.
-     Moving connector data_a 3 on WEST side, slice 3, default track.
-     Moving connector data_a 4 on WEST side, slice 4, default track.
-     Moving connector data_a 5 on WEST side, slice 5, default track.
-     Moving connector data_a 6 on WEST side, slice 6, default track.
-     Moving connector data_a 7 on WEST side, slice 7, default track.
-   o Freeing symbolic grid.
- * Placement done.
-
- * Routing step.
-   o Loading physical and logical views.
-   o Setting access types.
-      -> pdff_8x8x0l_cl.
-      -> add2f_8x8x0l_bk.
-      -> mux2cs_8x8x0l_cl.
-      -> nul_8x8x0l_cl.
-   o Checking logical and physical correspondance.
-      -> Signal data_u_7 not connected to any other terminal.
-      -> Signal data_u_6 not connected to any other terminal.
-      -> Signal data_u_5 not connected to any other terminal.
-      -> Signal data_u_4 not connected to any other terminal.
-      -> Signal data_u_3 not connected to any other terminal.
-      -> Signal data_u_2 not connected to any other terminal.
-      -> Signal data_u_1 not connected to any other terminal.
-      -> Signal data_u_0 not connected to any other terminal.
-   o Making DPR data structure.
-   o Optimizing column ordering.
-     -> Totalwidth before : 192
-     -> Totalwidth after:   160
-     -> Totalwidth before : 160
-     -> Totalwidth after:   144
-     -> Totalwidth before : 144
-     -> Totalwidth after:   144
-   o Finishing data structure.
-     -> External North/South terminal ctrl_zero replaced.
-   o Global routing.
-   o Bit-slice symbolic routing.
-     -> Bit-slice 0.
-     -> Bit-slice 1.
-     -> Bit-slice 2.
-     -> Bit-slice 3.
-     -> Bit-slice 4.
-     -> Bit-slice 5.
-     -> Bit-slice 6.
-     -> Bit-slice 7.
-     -> Bit-slice 8.
-     -> Bit-slice 9.
-   o Multi-bit net symbolic routing.
-     -> Left connectors column.
-     -> Column 1.
-     -> Column 2.
-     -> Column 3.
-     -> Column 4.
-     -> Right connectors column.
-   o Channel routing.
-     -> Channel 1.
-     -> Channel 2.
-     -> Channel 3.
-     -> Channel 4.
-     -> Channel 5.
-   o Saving physical figure place_dpt.
-     -> Column 1.
-     -> Column 2.
-     -> Column 3.
-     -> Column 4.
-   o Checking for short cut.
-     -> Instance zero(nul_8x8x0l_cl).
-     -> Instance memory(pdff_8x8x0l_cl).
-     -> Instance multiplexer(mux2cs_8x8x0l_cl).
-     -> Instance adder(add2f_8x8x0l_bk).
-   o Total routing time: 1 seconds.
- * Routing step done.
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB; MBK_OUT_LO=vst; export MBK_OUT_LO; MBK_IN_LO=vst; export MBK_IN_LO; MBK_OUT_PH=ap;  export MBK_OUT_PH; MBK_IN_PH=ap;  export MBK_IN_PH; /users/soft5/newlabo/Solaris/bin/druc place_dpt
-
-                  @@@@@@@     @@@@@@@                    @@@@ @
-                    @@   @@     @@   @@                @@    @@
-                    @@    @@    @@    @@              @@      @
-                    @@     @@   @@    @@  @@@  @@@@  @@       @
-                    @@     @@   @@   @@    @@    @@  @@        
-                    @@     @@   @@@@@      @@    @@  @@        
-                    @@     @@   @@  @@     @@    @@  @@        
-                    @@     @@   @@   @@    @@    @@  @@        
-                    @@    @@    @@   @@    @@    @@   @@      @
-                    @@   @@     @@    @@   @@   @@@    @@    @@
-                  @@@@@@@     @@@@@   @@@   @@@@  @@     @@@@  
-
-                               Design Rule Checker
-
-                     Alliance CAD System 3.2,      druc 3.00
-                     Copyright (c) 1993, MASI, CAO-VLSI Team
-                     E-mail support:    cao-vlsi@masi.ibp.fr
-
-Flatten DRC on: place_dpt
-Delete MBK figure : place_dpt
-Load Flatten Rules : /users/alc/distrib/dev/alliance-3.2b/etc/cmos_7.rds
-
-Unify : place_dpt
-
-Create Ring : place_dpt_rng
-Merge Errorfiles: 
-
-Merge Error Instances:
-instructionCourante : 000  0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
-End DRC on: place_dpt
-Saving the Error file figure
-Done
-  0
-
-File: place_dpt.drc is empty: no errors detected.
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB; MBK_OUT_LO=al;  export MBK_OUT_LO; MBK_IN_LO=al;  export MBK_IN_LO;  MBK_OUT_PH=ap;  export MBK_OUT_PH; MBK_IN_PH=ap;  export MBK_IN_PH; /users/soft5/newlabo/Solaris/bin/lynx -v -f place_dpt place_dpt_gates
-
-                   @@@@@@                                    
-                     @@                                      
-                     @@                                      
-                     @@        @@@@@ @@@ @@@ @@@    @@@@  @@@
-                     @@         @@    @   @@@   @    @@    @ 
-                     @@          @@   @   @@    @@    @@  @  
-                     @@          @@  @    @@    @@     @@@   
-                     @@           @@ @    @@    @@     @@@   
-                     @@      @    @@@     @@    @@    @  @@  
-                     @@     @      @@     @@    @@   @    @@ 
-                   @@@@@@@@@@  @@  @     @@@@  @@@@ @@@  @@@@
-                               @@  @                         
-                                @@@                          
-
-                                Netlist extractor
-
-                     Alliance CAD System 3.2,      lynx 1.16
-                     Copyright (c) 1997, MASI, CAO-VLSI Team
-                     E-mail support:    cao-vlsi@masi.ibp.fr
-
-
-
-	---> Extracts symbolic figure place_dpt
-
-		---> Flatten figure
-
-		---> Translate Mbk -> Rds
-		---> Build windows
-		<--- 280
-
-		---> Rectangles    : 3107
-		---> Figure size   : (   -100,   -400 )
-		                     (  43400,  60400 )
-
-		---> Cut transistors
-		<--- 0
-		---> Build equis
-		<--- 56
-		---> Delete windows
-		---> Build signals
-		<--- 56
-		---> Build instances
-		<--- 4
-		---> Build transistors
-		<--- 0
-		---> Save netlist
-
-	<--- done !
-
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB;                        /users/soft5/newlabo/Solaris/bin/lvx vst al place_dpt place_dpt_gates -f
-
-                       @@@@@@      @@@@    @@@ @@@@   @@@@
-                         @@         @@      @   @@     @  
-                         @@         @@      @    @@   @   
-                         @@          @@    @      @@ @    
-                         @@          @@    @       @@     
-                         @@           @@  @        @@     
-                         @@           @@  @        @@@    
-                         @@            @@@        @  @@   
-                         @@      @     @@@       @    @@  
-                         @@     @       @       @      @@ 
-                       @@@@@@@@@@       @      @@@    @@@@
-
-                             Gate Netlist Comparator
-
-                   Alliance CAD System 3.2,          lvx 2.23
-                   Copyright (c) 1992-93, MASI, CAO-VLSI Team
-                   E-mail support:       cao-vlsi@masi.ibp.fr
-
-
-
-***** Loading and flattening place_dpt (vst)...
-
-***** Loading and flattening place_dpt_gates (al)...
-
-
-***** Compare Terminals ..................
-***** O.K.	(0 sec)
-
-***** Compare Instances ..........
-***** O.K.	(0 sec)
-
-***** Compare Connections ............
-***** O.K.	(0 sec)
-
-===== Terminals .......... 32    
-===== Instances .......... 4     
-===== Connectors ......... 151   
-
-
-***** Netlists are Identical. *****	(0 sec)
-
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB; MBK_OUT_LO=al;  export MBK_OUT_LO; MBK_IN_LO=al;  export MBK_IN_LO;  MBK_OUT_PH=ap;  export MBK_OUT_PH; MBK_IN_PH=ap;  export MBK_IN_PH; /users/soft5/newlabo/Solaris/bin/lynx -v -t place_dpt place_dpt
-
-                   @@@@@@                                    
-                     @@                                      
-                     @@                                      
-                     @@        @@@@@ @@@ @@@ @@@    @@@@  @@@
-                     @@         @@    @   @@@   @    @@    @ 
-                     @@          @@   @   @@    @@    @@  @  
-                     @@          @@  @    @@    @@     @@@   
-                     @@           @@ @    @@    @@     @@@   
-                     @@      @    @@@     @@    @@    @  @@  
-                     @@     @      @@     @@    @@   @    @@ 
-                   @@@@@@@@@@  @@  @     @@@@  @@@@ @@@  @@@@
-                               @@  @                         
-                                @@@                          
-
-                                Netlist extractor
-
-                     Alliance CAD System 3.2,      lynx 1.16
-                     Copyright (c) 1997, MASI, CAO-VLSI Team
-                     E-mail support:    cao-vlsi@masi.ibp.fr
-
-
-
-	---> Extracts symbolic figure place_dpt
-
-		---> Flatten figure
-
-		---> Translate Mbk -> Rds
-		---> Build windows
-		<--- 280
-
-		---> Rectangles    : 16647
-		---> Figure size   : (   -100,   -400 )
-		                     (  43400,  60400 )
-
-		---> Cut transistors
-		<--- 20
-		---> Build equis
-		<--- 315
-		---> Delete windows
-		---> Build signals
-		<--- 315
-		---> Build instances
-		<--- 0
-		---> Build transistors
-		<--- 600
-		---> Save netlist
-
-	<--- done !
-
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB; MBK_OUT_LO=al;  export MBK_OUT_LO; MBK_IN_LO=al;  export MBK_IN_LO;             /users/soft5/newlabo/Solaris/bin/yagle place_dpt place_dpt_desb -v -i
-
-                                               @@@@            
-                                                 @@            
-                                                 @@            
-                  @@@@@ @@@   @@@@      @@@@@@   @@     @@@@@  
-                   @@    @   @@   @    @@  @@    @@    @     @ 
-                    @@   @   @@   @@   @   @@    @@   @@     @@
-                    @@  @      @@@@@   @   @     @@   @@@@@@@@@
-                     @@ @    @@   @@    @@@      @@   @@       
-                     @@@    @@    @@   @@        @@   @@      @
-                      @@    @@   @@@   @@@@@@    @@    @@    @@
-                  @@  @      @@@@  @@ @@   @@@ @@@@@@    @@@@  
-                  @@  @                @     @                 
-                   @@@                  @@@@@                  
-
-                        Yet Another Gate Level Extractor
-
-                  Alliance CAD System 3.2,           yagle 2.02
-                  Copyright (c) 94-97-1997,      ASIM/LIP6/UPMC
-                  E-mail support: alliance-support@asim.lip6.fr
-
-[YAG MES] Reading file 'place_dpt.inf'
-[YAG MES] Loading the figure place_dpt             00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Transistor netlist checking              00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Extracting CMOS duals                    00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Extracting bleeders                      00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Making gates                             00m00s  u:00m00.3  s:00m00.0
-[YAG MES] Latches detection                        00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Making cells                             00m00s  u:00m00.0  s:00m00.0
-[YAG MES] External connector verification          00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Checking the yagle figure                00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Building the behavioural figure          00m00s  u:00m00.0  s:00m00.0
-TOTAL DISASSEMBLY TIME                             00m00s  u:00m00.4  s:00m00.0
-------------------------------------------------------------
-[YAG MES] Erasing the transistor netlist
-[YAG MES] Generating the VHDL Data Flow
-[YAG MES] Execution COMPLETED 
-------------------------------------------------------------
-[YAG WAR 07] 16 transistors are not used 
-[YAG WAR 09] 16 latches detected
-[YAG WAR 14] 1 conflicts may occur in the circuit
-See file 'place_dpt.rep' for more information
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB;                        /users/soft5/newlabo/Solaris/bin/proof -d sample_dpt place_dpt_desb
-
-                @@@@@@@                                     @@@ 
-                  @@   @@                                  @  @@
-                  @@    @@                                @@  @@
-                  @@    @@ @@@ @@@     @@@       @@@      @@    
-                  @@   @@   @@@  @@  @@   @@   @@   @@  @@@@@@@@
-                  @@@@@     @@   @@ @@     @@ @@     @@   @@    
-                  @@        @@      @@     @@ @@     @@   @@    
-                  @@        @@      @@     @@ @@     @@   @@    
-                  @@        @@      @@     @@ @@     @@   @@    
-                  @@        @@       @@   @@   @@   @@    @@    
-                @@@@@@     @@@@        @@@       @@@    @@@@@@  
-
-                                  Formal Proof
-
-                Alliance CAD System 3.2b, proof 4.20 [1997/10/09]
-                Copyright (c) 1990-1997,           ASIM/LIP6/UPMC
-                E-mail support:     alliance-support@asim.lip6.fr
-
-================================  Environment  ================================
-MBK_WORK_LIB		= .
-MBK_CATA_LIB		= ./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib
-=======================  Files, Options and Parameters  =======================
-First VHDL file		= sample_dpt.vbe
-Second VHDL file	= place_dpt_desb.vbe
-The auxiliary signals are erased
-Errors are displayed
-===============================================================================
-
-Compiling 'sample_dpt' ...
-Compiling 'place_dpt_desb' ...
-WARNING : data_s_0 is considered as an output signal
-WARNING : data_s_1 is considered as an output signal
-WARNING : data_s_2 is considered as an output signal
-WARNING : data_s_3 is considered as an output signal
-WARNING : data_s_4 is considered as an output signal
-WARNING : data_s_5 is considered as an output signal
-WARNING : data_s_6 is considered as an output signal
-WARNING : data_s_7 is considered as an output signal
-WARNING : data_s_0 is considered as an output signal
-WARNING : data_s_1 is considered as an output signal
-WARNING : data_s_2 is considered as an output signal
-WARNING : data_s_3 is considered as an output signal
-WARNING : data_s_4 is considered as an output signal
-WARNING : data_s_5 is considered as an output signal
-WARNING : data_s_6 is considered as an output signal
-WARNING : data_s_7 is considered as an output signal
-WARNING : ctrl_nover is considered as an output signal
-
-Running abl ordonnancer on `sample_dpt`
-...........................
-
-Running Abl2Bdd on `sample_dpt`
----> final number of nodes = 1008(633)
-
-Warning : Input 'mbk_sig281' only exists in the second description
-Running Abl2Bdd on `place_dpt_desb`
-
-Running abl ordonnancer on `sample_dpt`
-...........................
-
-Running Abl2Bdd on `sample_dpt`
----> final number of nodes = 2055(633)
-
-Running Abl2Bdd on `place_dpt_desb`
---------------------------------------------------------------------------------
-             Formal proof with Ordered Binary Decision Diagrams between   
-
-             './sample_dpt'  and  './place_dpt_desb'
---------------------------------------------------------------------------------
-==============================  PRIMARY OUTPUT  ===============================
-=============================  AUXILIARY SIGNAL  ==============================
-==============================  REGISTER SIGNAL  ==============================
-===============================  EXTERNAL BUS =================================
-================================ INTERNAL BUS =================================
-
-                            Formal Proof : OK
-
-pppppppppppppppppppppppprrrrrrrrrrrrooooooooooooooooooooooooooooofffffffffffffff
---------------------------------------------------------------------------------
-
-
-
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB; MBK_OUT_LO=vst; export MBK_OUT_LO; MBK_IN_LO=vst; export MBK_IN_LO; MBK_OUT_PH=ap;  export MBK_OUT_PH; MBK_IN_PH=ap;  export MBK_IN_PH;  /users/outil2/fitpath/dev/Solaris/bin/fpgen -v usercol_dpt
-
-             @@@@@@@@@                @@@@ @                        
-               @@    @              @@    @@                        
-               @@     @            @@      @                        
-               @@       @@@ @@@   @@             @@@@@   @@@ @@@    
-               @@   @    @@@  @@  @@            @     @   @@@   @   
-               @@@@@@    @@    @@ @@     @@@@@ @@     @@  @@    @@  
-               @@   @    @@    @@ @@     @ @@  @@@@@@@@@  @@    @@  
-               @@        @@    @@ @@    @  @@  @@         @@    @@  
-               @@        @@    @@  @@      @@  @@      @  @@    @@  
-               @@        @@@  @@    @@    @@    @@    @@  @@    @@  
-             @@@@@@      @@ @@@       @@@@        @@@@   @@@@  @@@@ 
-                         @@                                         
-                        @@@@                                        
-
-                           Fitpath Generation Language         
-
-                 Alliance CAD System V.R,           fpgen V.RR 
-                 Copyright (c) 93-AA,           ASIM/LIP6/UPMC 
-                 E-mail support: alliance-support@asim.lip6.fr 
-
-
-  o  Alliance Devellopment environment:
-     - DEVEL_TOP       : /users/outil2/fitpath/dev/Solaris
-     - DEVEL_VERSION   : 113
-  o  Current Alliance environment:
-     - ALLIANCE_TOP    : not set
-     -      MACHINE    : Solaris
-  o  Current MBK environment:
-     - MBK_IN_LO       : vst
-     - MBK_OUT_LO      : vst
-     - MBK_IN_PH       : ap
-     - MBK_OUT_PH      : ap
-     - MBK_WORK_LIB    : .
-     - MBK_CATA_LIB    : ./mclib
-                         /users/soft5/newlabo/Solaris/cells/rsa
-                         /users/outil2/fitpath/labo/cells/fplib
-                         /users/outil2/fitpath/labo/cells/dplib
-     - MBK_CATAL_NAME  : CATAL
-     - MBK_VDD         : vdd
-     - MBK_VSS         : vss
-     - RDS_TECHNO_NAME : not set
-  o  FpGen Macro-Functions library:
-     - FPGEN_LIB       : ./mclib
-
-  o  Program generation.
-     - Creating Makefile.
-     - Running Makefile.
-  o  Execute program...
-FpGen:DP_TRACE:Trace mode ON at line 101 of file "usercol_dpt.c".
-*** FpGen Trace ***:
-      Macro-Function : DP_MUX2CS.
-    (char *)InstName : (0x000E0F90) "multiplexer".
-         (long)Width : (0x--------)  8.
-         (long)Slice : (0x--------)  0.
-             [ Model : "mux2cs_8x8x0l_cl" : Generated on memory ]
-      (char *)Signal : (0x000E0EF8) "ctrl_sel".
-      (char *)Signal : (0x000E0F60) "data_b[7:0]".
-      (char *)Signal : (0x000E0FA0) "data_q[7:0]".
-      (char *)Signal : (0x000E0FB0) "data_m[7:0]".
-      (char *)Signal : (0x00000000) --> EOL.
-*** FpGen xvLoins ***:MBK terminals assigments (reverse order):
-              o[0:7] => data_m[0:7]
-             i0[0:7] => data_q[0:7]
-             i1[0:7] => data_b[0:7]
-                 sel => ctrl_sel
-*** FpGen Trace ***:
-      Macro-Function : DP_ADD2F.
-    (char *)InstName : (0x000E0FC0) "adder".
-             [ Model : "add2f_8x8x0l_bk" : Generated on memory ]
-      (char *)Signal : (0x000E0F50) "data_a[7:0]".
-      (char *)Signal : (0x000E0FB0) "data_m[7:0]".
-      (char *)Signal : (0x000E0F20) "ctrl_ncout".
-      (char *)Signal : (0x000E0F30) "ctrl_nover".
-      (char *)Signal : (0x000E0F70) "data_s[7:0]".
-      (char *)Signal : (0x00000000) --> EOL.
-*** FpGen xvLoins ***:MBK terminals assigments (reverse order):
-              s[0:7] => data_s[0:7]
-              over_n => ctrl_nover
-              cout_n => ctrl_ncout
-              b[0:7] => data_m[0:7]
-              a[0:7] => data_a[0:7]
-*** FpGen Trace ***:
-      Macro-Function : DP_IMPORT.
-   (char *)ModelName : (0x000E0E08) "nul_us".
-    (char *)InstName : (0x000E0E18) "zero".
-      (char *)Signal : (0x000E0F70) "data_s[7:0]".
-      (char *)Signal : (0x000E0F40) "ctrl_zero".
-      (char *)Signal : (0x00000000) --> EOL.
-*** FpGen xvLoins ***:MBK terminals assigments (reverse order):
-                zero => ctrl_zero
-             i0[0:7] => data_s[0:7]
-*** FpGen Trace ***:
-      Macro-Function : DP_PDFF.
-    (char *)InstName : (0x000E0FC8) "memory".
-         (long)Width : (0x--------)  8.
-         (long)Slice : (0x--------)  0.
-             [ Model : "pdff_8x8x0l_cl" : Generated on memory ]
-      (char *)Signal : (0x000E0F10) "ctrl_wen".
-      (char *)Signal : (0x000E0F08) "ctrl_ck".
-      (char *)Signal : (0x000E0F70) "data_s[7:0]".
-      (char *)Signal : (0x000E0FA0) "data_q[7:0]".
-      (char *)Signal : (0x000E0FD0) "data_u[7:0]".
-      (char *)Signal : (0x00000000) --> EOL.
-*** FpGen xvLoins ***:MBK terminals assigments (reverse order):
-             nq[0:7] => data_u[0:7]
-              q[0:7] => data_q[0:7]
-              d[0:7] => data_s[0:7]
-                  ck => ctrl_ck
-                 wen => ctrl_wen
-FpGen:DP_TRACE:Trace mode OFF at line 137 of file "usercol_dpt.c".
-     - Exit code := 0.
-
-  o  Remove temporary file.
-
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB; MBK_OUT_LO=vst; export MBK_OUT_LO; MBK_IN_LO=vst; export MBK_IN_LO; MBK_OUT_PH=ap;  export MBK_OUT_PH; MBK_IN_PH=ap;  export MBK_IN_PH;      /users/outil3/dpr/labo/Solaris/bin/dpr -V -p -r usercol_dpt usercol_dpt
-
-                       @@@@@@@     @@@@@@@    @@@@@@@    
-                         @@   @@     @@   @@    @@   @@  
-                         @@    @@    @@    @@   @@    @@ 
-                         @@     @@   @@    @@   @@    @@ 
-                         @@     @@   @@   @@    @@   @@  
-                         @@     @@   @@@@@      @@@@@    
-                         @@     @@   @@         @@  @@   
-                         @@     @@   @@         @@   @@  
-                         @@    @@    @@         @@   @@  
-                         @@   @@     @@         @@    @@ 
-                       @@@@@@@     @@@@@@     @@@@@   @@@
-
-                       Placer-Router for Datapath Compiler
-
-                  Alliance CAD System 3.2b,             dpr 6.2
-                  Copyright (c) 1994-1997,       ASIM/LIP6/UPMC
-                  E-mail support: alliance-support@asim.lip6.fr
-
-
- * MBK parameters :
-
-       MBK_WORK_LIB   : .
-       MBK_CATA_LIB   : ./mclib
-                      : /users/soft5/newlabo/Solaris/cells/rsa
-                      : /users/outil2/fitpath/labo/cells/fplib
-                      : /users/outil2/fitpath/labo/cells/dplib
-       MBK_IN_PH      : ap
-       MBK_OUT_PH     : ap
-       MBK_IN_LO      : vst
-       MBK_OUT_LO     : vst
-       TECHNO         : CMOS
-
- * Placement step.
-   o Getting netlist.
-   o Getting dpr file.
-   o Building symbolic grid.
-     -> Routed bloc : 'memory' (pdff_8x8x0l_cl).
-     -> Glue bloc   : 'zero' (nul_us).
-     -> Routed bloc : 'adder' (add2f_8x8x0l_bk).
-     -> Routed bloc : 'multiplexer' (mux2cs_8x8x0l_cl).
-   o Ckecking slices heights.
-
-   o Nb slices : 10.
-   o Nb cols   : 4.
-
-   o Creating column.
-     -> Indexed column     : 'zero'.
-   o Creating glue logic blocs.
-   o Checking alims correspondances.
-   o Creating global phfig view.
-     Moving connector data_s 0 on EAST side, slice 0, default track.
-     Moving connector data_s 1 on EAST side, slice 1, default track.
-     Moving connector data_s 2 on EAST side, slice 2, default track.
-     Moving connector data_s 3 on EAST side, slice 3, default track.
-     Moving connector data_s 4 on EAST side, slice 4, default track.
-     Moving connector data_s 5 on EAST side, slice 5, default track.
-     Moving connector data_s 6 on EAST side, slice 6, default track.
-     Moving connector data_s 7 on EAST side, slice 7, default track.
-     Moving connector data_b 0 on WEST side, slice 0, default track.
-     Moving connector data_b 1 on WEST side, slice 1, default track.
-     Moving connector data_b 2 on WEST side, slice 2, default track.
-     Moving connector data_b 3 on WEST side, slice 3, default track.
-     Moving connector data_b 4 on WEST side, slice 4, default track.
-     Moving connector data_b 5 on WEST side, slice 5, default track.
-     Moving connector data_b 6 on WEST side, slice 6, default track.
-     Moving connector data_b 7 on WEST side, slice 7, default track.
-     Moving connector data_a 0 on WEST side, slice 0, default track.
-     Moving connector data_a 1 on WEST side, slice 1, default track.
-     Moving connector data_a 2 on WEST side, slice 2, default track.
-     Moving connector data_a 3 on WEST side, slice 3, default track.
-     Moving connector data_a 4 on WEST side, slice 4, default track.
-     Moving connector data_a 5 on WEST side, slice 5, default track.
-     Moving connector data_a 6 on WEST side, slice 6, default track.
-     Moving connector data_a 7 on WEST side, slice 7, default track.
-   o Freeing symbolic grid.
- * Placement done.
-
- * Routing step.
-   o Loading physical and logical views.
-   o Setting access types.
-      -> na2_dp.
-      -> no2_dp.
-      -> pdff_8x8x0l_cl.
-      -> add2f_8x8x0l_bk.
-      -> mux2cs_8x8x0l_cl.
-   o Checking logical and physical correspondance.
-      -> Signal data_u_7 not connected to any other terminal.
-      -> Signal data_u_6 not connected to any other terminal.
-      -> Signal data_u_5 not connected to any other terminal.
-      -> Signal data_u_4 not connected to any other terminal.
-      -> Signal data_u_3 not connected to any other terminal.
-      -> Signal data_u_2 not connected to any other terminal.
-      -> Signal data_u_1 not connected to any other terminal.
-      -> Signal data_u_0 not connected to any other terminal.
-   o Making DPR data structure.
-     -> External North/South terminal ctrl_zero replaced.
-   o Global routing.
-   o Bit-slice symbolic routing.
-     -> Bit-slice 0.
-     -> Bit-slice 1.
-     -> Bit-slice 2.
-     -> Bit-slice 3.
-     -> Bit-slice 4.
-     -> Bit-slice 5.
-     -> Bit-slice 6.
-     -> Bit-slice 7.
-     -> Bit-slice 8.
-     -> Bit-slice 9.
-   o Multi-bit net symbolic routing.
-     -> Left connectors column.
-     -> Column 1.
-     -> Column 2.
-     -> Column 3.
-     -> Column 4.
-     -> Right connectors column.
-   o Channel routing.
-     -> Channel 1.
-     -> Channel 2.
-     -> Channel 3.
-     -> Channel 4.
-     -> Channel 5.
-   o Saving physical figure usercol_dpt.
-     -> Column 1.
-     -> Column 2.
-     -> Column 3.
-     -> Column 4.
-   o Checking for short cut.
-     -> Instance memory(pdff_8x8x0l_cl).
-     -> Instance zero.no2_0(no2_dp).
-     -> Instance zero.na2_1(na2_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance zero.no2_2(no2_dp).
-     -> Instance zero.no2_3(no2_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance zero.no2_4(no2_dp).
-     -> Instance zero.na2_5(na2_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance zero.no2_6(no2_dp).
-     -> Instance adder(add2f_8x8x0l_bk).
-     -> Instance multiplexer(mux2cs_8x8x0l_cl).
-   o Total routing time: 2 seconds.
- * Routing step done.
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB; MBK_OUT_LO=vst; export MBK_OUT_LO; MBK_IN_LO=vst; export MBK_IN_LO; MBK_OUT_PH=ap;  export MBK_OUT_PH; MBK_IN_PH=ap;  export MBK_IN_PH; /users/soft5/newlabo/Solaris/bin/druc usercol_dpt
-
-                  @@@@@@@     @@@@@@@                    @@@@ @
-                    @@   @@     @@   @@                @@    @@
-                    @@    @@    @@    @@              @@      @
-                    @@     @@   @@    @@  @@@  @@@@  @@       @
-                    @@     @@   @@   @@    @@    @@  @@        
-                    @@     @@   @@@@@      @@    @@  @@        
-                    @@     @@   @@  @@     @@    @@  @@        
-                    @@     @@   @@   @@    @@    @@  @@        
-                    @@    @@    @@   @@    @@    @@   @@      @
-                    @@   @@     @@    @@   @@   @@@    @@    @@
-                  @@@@@@@     @@@@@   @@@   @@@@  @@     @@@@  
-
-                               Design Rule Checker
-
-                     Alliance CAD System 3.2,      druc 3.00
-                     Copyright (c) 1993, MASI, CAO-VLSI Team
-                     E-mail support:    cao-vlsi@masi.ibp.fr
-
-Flatten DRC on: usercol_dpt
-Delete MBK figure : usercol_dpt
-Load Flatten Rules : /users/alc/distrib/dev/alliance-3.2b/etc/cmos_7.rds
-
-Unify : usercol_dpt
-
-Create Ring : usercol_dpt_rng
-Merge Errorfiles: 
-
-Merge Error Instances:
-instructionCourante : 000  0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
-End DRC on: usercol_dpt
-Saving the Error file figure
-Done
-  0
-
-File: usercol_dpt.drc is empty: no errors detected.
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB; MBK_OUT_LO=al;  export MBK_OUT_LO; MBK_IN_LO=al;  export MBK_IN_LO;  MBK_OUT_PH=ap;  export MBK_OUT_PH; MBK_IN_PH=ap;  export MBK_IN_PH; /users/soft5/newlabo/Solaris/bin/lynx -v -f usercol_dpt usercol_dpt_gates
-
-                   @@@@@@                                    
-                     @@                                      
-                     @@                                      
-                     @@        @@@@@ @@@ @@@ @@@    @@@@  @@@
-                     @@         @@    @   @@@   @    @@    @ 
-                     @@          @@   @   @@    @@    @@  @  
-                     @@          @@  @    @@    @@     @@@   
-                     @@           @@ @    @@    @@     @@@   
-                     @@      @    @@@     @@    @@    @  @@  
-                     @@     @      @@     @@    @@   @    @@ 
-                   @@@@@@@@@@  @@  @     @@@@  @@@@ @@@  @@@@
-                               @@  @                         
-                                @@@                          
-
-                                Netlist extractor
-
-                     Alliance CAD System 3.2,      lynx 1.16
-                     Copyright (c) 1997, MASI, CAO-VLSI Team
-                     E-mail support:    cao-vlsi@masi.ibp.fr
-
-
-
-	---> Extracts symbolic figure usercol_dpt
-
-		---> Flatten figure
-
-		---> Translate Mbk -> Rds
-		---> Build windows
-		<--- 280
-
-		---> Rectangles    : 3482
-		---> Figure size   : (   -100,   -400 )
-		                     (  43800,  60400 )
-
-		---> Cut transistors
-		<--- 0
-		---> Build equis
-		<--- 62
-		---> Delete windows
-		---> Build signals
-		<--- 62
-		---> Build instances
-		<--- 10
-		---> Build transistors
-		<--- 0
-		---> Save netlist
-
-	<--- done !
-
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB;                        /users/soft5/newlabo/Solaris/bin/lvx vst al usercol_dpt usercol_dpt_gates -f
-
-                       @@@@@@      @@@@    @@@ @@@@   @@@@
-                         @@         @@      @   @@     @  
-                         @@         @@      @    @@   @   
-                         @@          @@    @      @@ @    
-                         @@          @@    @       @@     
-                         @@           @@  @        @@     
-                         @@           @@  @        @@@    
-                         @@            @@@        @  @@   
-                         @@      @     @@@       @    @@  
-                         @@     @       @       @      @@ 
-                       @@@@@@@@@@       @      @@@    @@@@
-
-                             Gate Netlist Comparator
-
-                   Alliance CAD System 3.2,          lvx 2.23
-                   Copyright (c) 1992-93, MASI, CAO-VLSI Team
-                   E-mail support:       cao-vlsi@masi.ibp.fr
-
-
-
-***** Loading and flattening usercol_dpt (vst)...
-
-***** Loading and flattening usercol_dpt_gates (al)...
-
-
-***** Compare Terminals ..................
-***** O.K.	(0 sec)
-
-***** Compare Instances ..........
-***** O.K.	(0 sec)
-
-***** Compare Connections ............
-***** O.K.	(0 sec)
-
-===== Terminals .......... 32    
-===== Instances .......... 10    
-===== Connectors ......... 168   
-
-
-***** Netlists are Identical. *****	(0 sec)
-
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB; MBK_OUT_LO=al;  export MBK_OUT_LO; MBK_IN_LO=al;  export MBK_IN_LO;  MBK_OUT_PH=ap;  export MBK_OUT_PH; MBK_IN_PH=ap;  export MBK_IN_PH; /users/soft5/newlabo/Solaris/bin/lynx -v -t usercol_dpt usercol_dpt
-
-                   @@@@@@                                    
-                     @@                                      
-                     @@                                      
-                     @@        @@@@@ @@@ @@@ @@@    @@@@  @@@
-                     @@         @@    @   @@@   @    @@    @ 
-                     @@          @@   @   @@    @@    @@  @  
-                     @@          @@  @    @@    @@     @@@   
-                     @@           @@ @    @@    @@     @@@   
-                     @@      @    @@@     @@    @@    @  @@  
-                     @@     @      @@     @@    @@   @    @@ 
-                   @@@@@@@@@@  @@  @     @@@@  @@@@ @@@  @@@@
-                               @@  @                         
-                                @@@                          
-
-                                Netlist extractor
-
-                     Alliance CAD System 3.2,      lynx 1.16
-                     Copyright (c) 1997, MASI, CAO-VLSI Team
-                     E-mail support:    cao-vlsi@masi.ibp.fr
-
-
-
-	---> Extracts symbolic figure usercol_dpt
-
-		---> Flatten figure
-
-		---> Translate Mbk -> Rds
-		---> Build windows
-		<--- 280
-
-		---> Rectangles    : 16544
-		---> Figure size   : (   -100,   -400 )
-		                     (  43800,  60400 )
-
-		---> Cut transistors
-		<--- 20
-		---> Build equis
-		<--- 315
-		---> Delete windows
-		---> Build signals
-		<--- 315
-		---> Build instances
-		<--- 0
-		---> Build transistors
-		<--- 600
-		---> Save netlist
-
-	<--- done !
-
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB; MBK_OUT_LO=al;  export MBK_OUT_LO; MBK_IN_LO=al;  export MBK_IN_LO;             /users/soft5/newlabo/Solaris/bin/yagle usercol_dpt usercol_dpt_desb -v -i
-
-                                               @@@@            
-                                                 @@            
-                                                 @@            
-                  @@@@@ @@@   @@@@      @@@@@@   @@     @@@@@  
-                   @@    @   @@   @    @@  @@    @@    @     @ 
-                    @@   @   @@   @@   @   @@    @@   @@     @@
-                    @@  @      @@@@@   @   @     @@   @@@@@@@@@
-                     @@ @    @@   @@    @@@      @@   @@       
-                     @@@    @@    @@   @@        @@   @@      @
-                      @@    @@   @@@   @@@@@@    @@    @@    @@
-                  @@  @      @@@@  @@ @@   @@@ @@@@@@    @@@@  
-                  @@  @                @     @                 
-                   @@@                  @@@@@                  
-
-                        Yet Another Gate Level Extractor
-
-                  Alliance CAD System 3.2,           yagle 2.02
-                  Copyright (c) 94-97-1997,      ASIM/LIP6/UPMC
-                  E-mail support: alliance-support@asim.lip6.fr
-
-[YAG MES] Reading file 'usercol_dpt.inf'
-[YAG MES] Loading the figure usercol_dpt           00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Transistor netlist checking              00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Extracting CMOS duals                    00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Extracting bleeders                      00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Making gates                             00m00s  u:00m00.3  s:00m00.0
-[YAG MES] Latches detection                        00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Making cells                             00m00s  u:00m00.0  s:00m00.0
-[YAG MES] External connector verification          00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Checking the yagle figure                00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Building the behavioural figure          00m00s  u:00m00.0  s:00m00.0
-TOTAL DISASSEMBLY TIME                             00m00s  u:00m00.3  s:00m00.0
-------------------------------------------------------------
-[YAG MES] Erasing the transistor netlist
-[YAG MES] Generating the VHDL Data Flow
-[YAG MES] Execution COMPLETED 
-------------------------------------------------------------
-[YAG WAR 07] 16 transistors are not used 
-[YAG WAR 09] 16 latches detected
-[YAG WAR 14] 1 conflicts may occur in the circuit
-See file 'usercol_dpt.rep' for more information
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB;                        /users/soft5/newlabo/Solaris/bin/proof -d sample_dpt usercol_dpt_desb
-
-                @@@@@@@                                     @@@ 
-                  @@   @@                                  @  @@
-                  @@    @@                                @@  @@
-                  @@    @@ @@@ @@@     @@@       @@@      @@    
-                  @@   @@   @@@  @@  @@   @@   @@   @@  @@@@@@@@
-                  @@@@@     @@   @@ @@     @@ @@     @@   @@    
-                  @@        @@      @@     @@ @@     @@   @@    
-                  @@        @@      @@     @@ @@     @@   @@    
-                  @@        @@      @@     @@ @@     @@   @@    
-                  @@        @@       @@   @@   @@   @@    @@    
-                @@@@@@     @@@@        @@@       @@@    @@@@@@  
-
-                                  Formal Proof
-
-                Alliance CAD System 3.2b, proof 4.20 [1997/10/09]
-                Copyright (c) 1990-1997,           ASIM/LIP6/UPMC
-                E-mail support:     alliance-support@asim.lip6.fr
-
-================================  Environment  ================================
-MBK_WORK_LIB		= .
-MBK_CATA_LIB		= ./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib
-=======================  Files, Options and Parameters  =======================
-First VHDL file		= sample_dpt.vbe
-Second VHDL file	= usercol_dpt_desb.vbe
-The auxiliary signals are erased
-Errors are displayed
-===============================================================================
-
-Compiling 'sample_dpt' ...
-Compiling 'usercol_dpt_desb' ...
-WARNING : data_s_0 is considered as an output signal
-WARNING : data_s_1 is considered as an output signal
-WARNING : data_s_2 is considered as an output signal
-WARNING : data_s_3 is considered as an output signal
-WARNING : data_s_4 is considered as an output signal
-WARNING : data_s_5 is considered as an output signal
-WARNING : data_s_6 is considered as an output signal
-WARNING : data_s_7 is considered as an output signal
-WARNING : data_s_0 is considered as an output signal
-WARNING : data_s_1 is considered as an output signal
-WARNING : data_s_2 is considered as an output signal
-WARNING : data_s_3 is considered as an output signal
-WARNING : data_s_4 is considered as an output signal
-WARNING : data_s_5 is considered as an output signal
-WARNING : data_s_6 is considered as an output signal
-WARNING : data_s_7 is considered as an output signal
-WARNING : ctrl_nover is considered as an output signal
-
-Running abl ordonnancer on `sample_dpt`
-...........................
-
-Running Abl2Bdd on `sample_dpt`
----> final number of nodes = 1008(633)
-
-Warning : Input 'mbk_sig285' only exists in the second description
-Running Abl2Bdd on `usercol_dpt_desb`
-
-Running abl ordonnancer on `sample_dpt`
-...........................
-
-Running Abl2Bdd on `sample_dpt`
----> final number of nodes = 2055(633)
-
-Running Abl2Bdd on `usercol_dpt_desb`
---------------------------------------------------------------------------------
-             Formal proof with Ordered Binary Decision Diagrams between   
-
-             './sample_dpt'  and  './usercol_dpt_desb'
---------------------------------------------------------------------------------
-==============================  PRIMARY OUTPUT  ===============================
-=============================  AUXILIARY SIGNAL  ==============================
-==============================  REGISTER SIGNAL  ==============================
-===============================  EXTERNAL BUS =================================
-================================ INTERNAL BUS =================================
-
-                            Formal Proof : OK
-
-pppppppppppppppppppppppprrrrrrrrrrrrooooooooooooooooooooooooooooofffffffffffffff
---------------------------------------------------------------------------------
-
-
-
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB; MBK_OUT_LO=vst; export MBK_OUT_LO; MBK_IN_LO=vst; export MBK_IN_LO; MBK_OUT_PH=ap;  export MBK_OUT_PH; MBK_IN_PH=ap;  export MBK_IN_PH;  /users/outil2/fitpath/dev/Solaris/bin/fpgen -v hierarchy_dpt
-
-             @@@@@@@@@                @@@@ @                        
-               @@    @              @@    @@                        
-               @@     @            @@      @                        
-               @@       @@@ @@@   @@             @@@@@   @@@ @@@    
-               @@   @    @@@  @@  @@            @     @   @@@   @   
-               @@@@@@    @@    @@ @@     @@@@@ @@     @@  @@    @@  
-               @@   @    @@    @@ @@     @ @@  @@@@@@@@@  @@    @@  
-               @@        @@    @@ @@    @  @@  @@         @@    @@  
-               @@        @@    @@  @@      @@  @@      @  @@    @@  
-               @@        @@@  @@    @@    @@    @@    @@  @@    @@  
-             @@@@@@      @@ @@@       @@@@        @@@@   @@@@  @@@@ 
-                         @@                                         
-                        @@@@                                        
-
-                           Fitpath Generation Language         
-
-                 Alliance CAD System V.R,           fpgen V.RR 
-                 Copyright (c) 93-AA,           ASIM/LIP6/UPMC 
-                 E-mail support: alliance-support@asim.lip6.fr 
-
-
-  o  Alliance Devellopment environment:
-     - DEVEL_TOP       : /users/outil2/fitpath/dev/Solaris
-     - DEVEL_VERSION   : 113
-  o  Current Alliance environment:
-     - ALLIANCE_TOP    : not set
-     -      MACHINE    : Solaris
-  o  Current MBK environment:
-     - MBK_IN_LO       : vst
-     - MBK_OUT_LO      : vst
-     - MBK_IN_PH       : ap
-     - MBK_OUT_PH      : ap
-     - MBK_WORK_LIB    : .
-     - MBK_CATA_LIB    : ./mclib
-                         /users/soft5/newlabo/Solaris/cells/rsa
-                         /users/outil2/fitpath/labo/cells/fplib
-                         /users/outil2/fitpath/labo/cells/dplib
-     - MBK_CATAL_NAME  : CATAL
-     - MBK_VDD         : vdd
-     - MBK_VSS         : vss
-     - RDS_TECHNO_NAME : not set
-  o  FpGen Macro-Functions library:
-     - FPGEN_LIB       : ./mclib
-
-  o  Program generation.
-     - Creating Makefile.
-     - Running Makefile.
-  o  Execute program...
-FpGen:DP_TRACE:Trace mode ON at line 117 of file "hierarchy_dpt.c".
-*** FpGen Trace ***:
-      Macro-Function : DP_MUX2CS.
-    (char *)InstName : (0x000E0DB0) "multiplexer".
-         (long)Width : (0x--------)  8.
-         (long)Slice : (0x--------)  0.
-             [ Model : "mux2cs_8x8x0l_cl" : Generated on memory ]
-      (char *)Signal : (0x000E0D78) "ctrl_sel".
-      (char *)Signal : (0x000E0D28) "data_b[7:0]".
-      (char *)Signal : (0x000E0DC0) "data_q[7:0]".
-      (char *)Signal : (0x000E0DD0) "data_m[7:0]".
-      (char *)Signal : (0x00000000) --> EOL.
-*** FpGen xvLoins ***:MBK terminals assigments (reverse order):
-              o[0:7] => data_m[0:7]
-             i0[0:7] => data_q[0:7]
-             i1[0:7] => data_b[0:7]
-                 sel => ctrl_sel
-*** FpGen Trace ***:
-      Macro-Function : DP_IMPORT.
-   (char *)ModelName : (0x000E0CE0) "alu_dpt".
-    (char *)InstName : (0x000E0DE0) "alu".
-      (char *)Signal : (0x000E0CE8) "ctrl_ncout".
-      (char *)Signal : (0x000E0CF8) "ctrl_nover".
-      (char *)Signal : (0x000E0D08) "ctrl_zero".
-      (char *)Signal : (0x000E0D18) "data_a[7:0]".
-      (char *)Signal : (0x000E0DD0) "data_m[7:0]".
-      (char *)Signal : (0x000E0D38) "data_s[7:0]".
-      (char *)Signal : (0x00000000) --> EOL.
-*** FpGen xvLoins ***:MBK terminals assigments (reverse order):
-         data_s[0:7] => data_s[0:7]
-         data_b[0:7] => data_m[0:7]
-         data_a[0:7] => data_a[0:7]
-           ctrl_zero => ctrl_zero
-          ctrl_nover => ctrl_nover
-          ctrl_ncout => ctrl_ncout
-*** FpGen Trace ***:
-      Macro-Function : DP_PDFF.
-    (char *)InstName : (0x000E0DE8) "memory".
-         (long)Width : (0x--------)  8.
-         (long)Slice : (0x--------)  0.
-             [ Model : "pdff_8x8x0l_cl" : Generated on memory ]
-      (char *)Signal : (0x000E0D90) "ctrl_wen".
-      (char *)Signal : (0x000E0D88) "ctrl_ck".
-      (char *)Signal : (0x000E0D38) "data_s[7:0]".
-      (char *)Signal : (0x000E0DC0) "data_q[7:0]".
-      (char *)Signal : (0x000E0DF0) "data_u[7:0]".
-      (char *)Signal : (0x00000000) --> EOL.
-*** FpGen xvLoins ***:MBK terminals assigments (reverse order):
-             nq[0:7] => data_u[0:7]
-              q[0:7] => data_q[0:7]
-              d[0:7] => data_s[0:7]
-                  ck => ctrl_ck
-                 wen => ctrl_wen
-FpGen:DP_TRACE:Trace mode OFF at line 148 of file "hierarchy_dpt.c".
-     - Exit code := 0.
-
-  o  Remove temporary file.
-
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB; MBK_OUT_LO=vst; export MBK_OUT_LO; MBK_IN_LO=vst; export MBK_IN_LO; MBK_OUT_PH=ap;  export MBK_OUT_PH; MBK_IN_PH=ap;  export MBK_IN_PH;      /users/outil3/dpr/labo/Solaris/bin/dpr -V -p -r hierarchy_dpt hierarchy_dpt
-
-                       @@@@@@@     @@@@@@@    @@@@@@@    
-                         @@   @@     @@   @@    @@   @@  
-                         @@    @@    @@    @@   @@    @@ 
-                         @@     @@   @@    @@   @@    @@ 
-                         @@     @@   @@   @@    @@   @@  
-                         @@     @@   @@@@@      @@@@@    
-                         @@     @@   @@         @@  @@   
-                         @@     @@   @@         @@   @@  
-                         @@    @@    @@         @@   @@  
-                         @@   @@     @@         @@    @@ 
-                       @@@@@@@     @@@@@@     @@@@@   @@@
-
-                       Placer-Router for Datapath Compiler
-
-                  Alliance CAD System 3.2b,             dpr 6.2
-                  Copyright (c) 1994-1997,       ASIM/LIP6/UPMC
-                  E-mail support: alliance-support@asim.lip6.fr
-
-
- * MBK parameters :
-
-       MBK_WORK_LIB   : .
-       MBK_CATA_LIB   : ./mclib
-                      : /users/soft5/newlabo/Solaris/cells/rsa
-                      : /users/outil2/fitpath/labo/cells/fplib
-                      : /users/outil2/fitpath/labo/cells/dplib
-       MBK_IN_PH      : ap
-       MBK_OUT_PH     : ap
-       MBK_IN_LO      : vst
-       MBK_OUT_LO     : vst
-       TECHNO         : CMOS
-
- * Placement step.
-   o Getting netlist.
-   o Getting dpr file.
-   o Building symbolic grid.
-     -> Routed bloc : 'memory' (pdff_8x8x0l_cl).
-     -> Routed bloc : 'alu_zero' (nul_8x8x0l_cl).
-     -> Routed bloc : 'alu_adder' (add2f_8x8x0l_bk).
-     -> Routed bloc : 'multiplexer' (mux2cs_8x8x0l_cl).
-   o Ckecking slices heights.
-
-   o Nb slices : 10.
-   o Nb cols   : 4.
-
-   o Creating column.
-   o Creating glue logic blocs.
-   o Checking alims correspondances.
-   o Creating global phfig view.
-     Moving connector data_s 0 on EAST side, slice 0, default track.
-     Moving connector data_s 1 on EAST side, slice 1, default track.
-     Moving connector data_s 2 on EAST side, slice 2, default track.
-     Moving connector data_s 3 on EAST side, slice 3, default track.
-     Moving connector data_s 4 on EAST side, slice 4, default track.
-     Moving connector data_s 5 on EAST side, slice 5, default track.
-     Moving connector data_s 6 on EAST side, slice 6, default track.
-     Moving connector data_s 7 on EAST side, slice 7, default track.
-     Moving connector data_b 0 on WEST side, slice 0, default track.
-     Moving connector data_b 1 on WEST side, slice 1, default track.
-     Moving connector data_b 2 on WEST side, slice 2, default track.
-     Moving connector data_b 3 on WEST side, slice 3, default track.
-     Moving connector data_b 4 on WEST side, slice 4, default track.
-     Moving connector data_b 5 on WEST side, slice 5, default track.
-     Moving connector data_b 6 on WEST side, slice 6, default track.
-     Moving connector data_b 7 on WEST side, slice 7, default track.
-     Moving connector data_a 0 on WEST side, slice 0, default track.
-     Moving connector data_a 1 on WEST side, slice 1, default track.
-     Moving connector data_a 2 on WEST side, slice 2, default track.
-     Moving connector data_a 3 on WEST side, slice 3, default track.
-     Moving connector data_a 4 on WEST side, slice 4, default track.
-     Moving connector data_a 5 on WEST side, slice 5, default track.
-     Moving connector data_a 6 on WEST side, slice 6, default track.
-     Moving connector data_a 7 on WEST side, slice 7, default track.
-   o Freeing symbolic grid.
- * Placement done.
-
- * Routing step.
-   o Loading physical and logical views.
-   o Setting access types.
-      -> pdff_8x8x0l_cl.
-      -> nul_8x8x0l_cl.
-      -> add2f_8x8x0l_bk.
-      -> mux2cs_8x8x0l_cl.
-   o Checking logical and physical correspondance.
-      -> Signal data_u_7 not connected to any other terminal.
-      -> Signal data_u_6 not connected to any other terminal.
-      -> Signal data_u_5 not connected to any other terminal.
-      -> Signal data_u_4 not connected to any other terminal.
-      -> Signal data_u_3 not connected to any other terminal.
-      -> Signal data_u_2 not connected to any other terminal.
-      -> Signal data_u_1 not connected to any other terminal.
-      -> Signal data_u_0 not connected to any other terminal.
-   o Making DPR data structure.
-     -> External North/South terminal ctrl_zero replaced.
-   o Global routing.
-   o Bit-slice symbolic routing.
-     -> Bit-slice 0.
-     -> Bit-slice 1.
-     -> Bit-slice 2.
-     -> Bit-slice 3.
-     -> Bit-slice 4.
-     -> Bit-slice 5.
-     -> Bit-slice 6.
-     -> Bit-slice 7.
-     -> Bit-slice 8.
-     -> Bit-slice 9.
-   o Multi-bit net symbolic routing.
-     -> Left connectors column.
-     -> Column 1.
-     -> Column 2.
-     -> Column 3.
-     -> Column 4.
-     -> Right connectors column.
-   o Channel routing.
-     -> Channel 1.
-     -> Channel 2.
-     -> Channel 3.
-     -> Channel 4.
-     -> Channel 5.
-   o Saving physical figure hierarchy_dpt.
-     -> Column 1.
-     -> Column 2.
-     -> Column 3.
-     -> Column 4.
-   o Checking for short cut.
-     -> Instance memory(pdff_8x8x0l_cl).
-     -> Instance alu_zero(nul_8x8x0l_cl).
-     -> Instance alu_adder(add2f_8x8x0l_bk).
-     -> Instance multiplexer(mux2cs_8x8x0l_cl).
-   o Total routing time: 1 seconds.
- * Routing step done.
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB; MBK_OUT_LO=vst; export MBK_OUT_LO; MBK_IN_LO=vst; export MBK_IN_LO; MBK_OUT_PH=ap;  export MBK_OUT_PH; MBK_IN_PH=ap;  export MBK_IN_PH; /users/soft5/newlabo/Solaris/bin/druc hierarchy_dpt
-
-                  @@@@@@@     @@@@@@@                    @@@@ @
-                    @@   @@     @@   @@                @@    @@
-                    @@    @@    @@    @@              @@      @
-                    @@     @@   @@    @@  @@@  @@@@  @@       @
-                    @@     @@   @@   @@    @@    @@  @@        
-                    @@     @@   @@@@@      @@    @@  @@        
-                    @@     @@   @@  @@     @@    @@  @@        
-                    @@     @@   @@   @@    @@    @@  @@        
-                    @@    @@    @@   @@    @@    @@   @@      @
-                    @@   @@     @@    @@   @@   @@@    @@    @@
-                  @@@@@@@     @@@@@   @@@   @@@@  @@     @@@@  
-
-                               Design Rule Checker
-
-                     Alliance CAD System 3.2,      druc 3.00
-                     Copyright (c) 1993, MASI, CAO-VLSI Team
-                     E-mail support:    cao-vlsi@masi.ibp.fr
-
-Flatten DRC on: hierarchy_dpt
-Delete MBK figure : hierarchy_dpt
-Load Flatten Rules : /users/alc/distrib/dev/alliance-3.2b/etc/cmos_7.rds
-
-Unify : hierarchy_dpt
-
-Create Ring : hierarchy_dpt_rng
-Merge Errorfiles: 
-
-Merge Error Instances:
-instructionCourante : 000  0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
-End DRC on: hierarchy_dpt
-Saving the Error file figure
-Done
-  0
-
-File: hierarchy_dpt.drc is empty: no errors detected.
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB; MBK_OUT_LO=al;  export MBK_OUT_LO; MBK_IN_LO=al;  export MBK_IN_LO;  MBK_OUT_PH=ap;  export MBK_OUT_PH; MBK_IN_PH=ap;  export MBK_IN_PH; /users/soft5/newlabo/Solaris/bin/lynx -v -f hierarchy_dpt hierarchy_dpt_gates
-
-                   @@@@@@                                    
-                     @@                                      
-                     @@                                      
-                     @@        @@@@@ @@@ @@@ @@@    @@@@  @@@
-                     @@         @@    @   @@@   @    @@    @ 
-                     @@          @@   @   @@    @@    @@  @  
-                     @@          @@  @    @@    @@     @@@   
-                     @@           @@ @    @@    @@     @@@   
-                     @@      @    @@@     @@    @@    @  @@  
-                     @@     @      @@     @@    @@   @    @@ 
-                   @@@@@@@@@@  @@  @     @@@@  @@@@ @@@  @@@@
-                               @@  @                         
-                                @@@                          
-
-                                Netlist extractor
-
-                     Alliance CAD System 3.2,      lynx 1.16
-                     Copyright (c) 1997, MASI, CAO-VLSI Team
-                     E-mail support:    cao-vlsi@masi.ibp.fr
-
-
-
-	---> Extracts symbolic figure hierarchy_dpt
-
-		---> Flatten figure
-
-		---> Translate Mbk -> Rds
-		---> Build windows
-		<--- 280
-
-		---> Rectangles    : 3113
-		---> Figure size   : (   -100,   -400 )
-		                     (  43400,  60400 )
-
-		---> Cut transistors
-		<--- 0
-		---> Build equis
-		<--- 56
-		---> Delete windows
-		---> Build signals
-		<--- 56
-		---> Build instances
-		<--- 4
-		---> Build transistors
-		<--- 0
-		---> Save netlist
-
-	<--- done !
-
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB;                        /users/soft5/newlabo/Solaris/bin/lvx vst al hierarchy_dpt hierarchy_dpt_gates -f
-
-                       @@@@@@      @@@@    @@@ @@@@   @@@@
-                         @@         @@      @   @@     @  
-                         @@         @@      @    @@   @   
-                         @@          @@    @      @@ @    
-                         @@          @@    @       @@     
-                         @@           @@  @        @@     
-                         @@           @@  @        @@@    
-                         @@            @@@        @  @@   
-                         @@      @     @@@       @    @@  
-                         @@     @       @       @      @@ 
-                       @@@@@@@@@@       @      @@@    @@@@
-
-                             Gate Netlist Comparator
-
-                   Alliance CAD System 3.2,          lvx 2.23
-                   Copyright (c) 1992-93, MASI, CAO-VLSI Team
-                   E-mail support:       cao-vlsi@masi.ibp.fr
-
-
-
-***** Loading and flattening hierarchy_dpt (vst)...
-
-***** Loading and flattening hierarchy_dpt_gates (al)...
-
-
-***** Compare Terminals ..................
-***** O.K.	(0 sec)
-
-***** Compare Instances ..........
-***** O.K.	(0 sec)
-
-***** Compare Connections ............
-***** O.K.	(0 sec)
-
-===== Terminals .......... 32    
-===== Instances .......... 4     
-===== Connectors ......... 151   
-
-
-***** Netlists are Identical. *****	(0 sec)
-
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB; MBK_OUT_LO=al;  export MBK_OUT_LO; MBK_IN_LO=al;  export MBK_IN_LO;  MBK_OUT_PH=ap;  export MBK_OUT_PH; MBK_IN_PH=ap;  export MBK_IN_PH; /users/soft5/newlabo/Solaris/bin/lynx -v -t hierarchy_dpt hierarchy_dpt
-
-                   @@@@@@                                    
-                     @@                                      
-                     @@                                      
-                     @@        @@@@@ @@@ @@@ @@@    @@@@  @@@
-                     @@         @@    @   @@@   @    @@    @ 
-                     @@          @@   @   @@    @@    @@  @  
-                     @@          @@  @    @@    @@     @@@   
-                     @@           @@ @    @@    @@     @@@   
-                     @@      @    @@@     @@    @@    @  @@  
-                     @@     @      @@     @@    @@   @    @@ 
-                   @@@@@@@@@@  @@  @     @@@@  @@@@ @@@  @@@@
-                               @@  @                         
-                                @@@                          
-
-                                Netlist extractor
-
-                     Alliance CAD System 3.2,      lynx 1.16
-                     Copyright (c) 1997, MASI, CAO-VLSI Team
-                     E-mail support:    cao-vlsi@masi.ibp.fr
-
-
-
-	---> Extracts symbolic figure hierarchy_dpt
-
-		---> Flatten figure
-
-		---> Translate Mbk -> Rds
-		---> Build windows
-		<--- 280
-
-		---> Rectangles    : 16653
-		---> Figure size   : (   -100,   -400 )
-		                     (  43400,  60400 )
-
-		---> Cut transistors
-		<--- 20
-		---> Build equis
-		<--- 315
-		---> Delete windows
-		---> Build signals
-		<--- 315
-		---> Build instances
-		<--- 0
-		---> Build transistors
-		<--- 600
-		---> Save netlist
-
-	<--- done !
-
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB; MBK_OUT_LO=al;  export MBK_OUT_LO; MBK_IN_LO=al;  export MBK_IN_LO;             /users/soft5/newlabo/Solaris/bin/yagle hierarchy_dpt hierarchy_dpt_desb -v -i
-
-                                               @@@@            
-                                                 @@            
-                                                 @@            
-                  @@@@@ @@@   @@@@      @@@@@@   @@     @@@@@  
-                   @@    @   @@   @    @@  @@    @@    @     @ 
-                    @@   @   @@   @@   @   @@    @@   @@     @@
-                    @@  @      @@@@@   @   @     @@   @@@@@@@@@
-                     @@ @    @@   @@    @@@      @@   @@       
-                     @@@    @@    @@   @@        @@   @@      @
-                      @@    @@   @@@   @@@@@@    @@    @@    @@
-                  @@  @      @@@@  @@ @@   @@@ @@@@@@    @@@@  
-                  @@  @                @     @                 
-                   @@@                  @@@@@                  
-
-                        Yet Another Gate Level Extractor
-
-                  Alliance CAD System 3.2,           yagle 2.02
-                  Copyright (c) 94-97-1997,      ASIM/LIP6/UPMC
-                  E-mail support: alliance-support@asim.lip6.fr
-
-[YAG MES] Reading file 'hierarchy_dpt.inf'
-[YAG MES] Loading the figure hierarchy_dpt         00m01s  u:00m00.0  s:00m00.0
-[YAG MES] Transistor netlist checking              00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Extracting CMOS duals                    00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Extracting bleeders                      00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Making gates                             00m00s  u:00m00.3  s:00m00.0
-[YAG MES] Latches detection                        00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Making cells                             00m00s  u:00m00.0  s:00m00.0
-[YAG MES] External connector verification          00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Checking the yagle figure                00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Building the behavioural figure          00m00s  u:00m00.0  s:00m00.0
-TOTAL DISASSEMBLY TIME                             00m00s  u:00m00.3  s:00m00.0
-------------------------------------------------------------
-[YAG MES] Erasing the transistor netlist
-[YAG MES] Generating the VHDL Data Flow
-[YAG MES] Execution COMPLETED 
-------------------------------------------------------------
-[YAG WAR 07] 16 transistors are not used 
-[YAG WAR 09] 16 latches detected
-[YAG WAR 14] 1 conflicts may occur in the circuit
-See file 'hierarchy_dpt.rep' for more information
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB;                        /users/soft5/newlabo/Solaris/bin/proof -d sample_dpt hierarchy_dpt_desb
-
-                @@@@@@@                                     @@@ 
-                  @@   @@                                  @  @@
-                  @@    @@                                @@  @@
-                  @@    @@ @@@ @@@     @@@       @@@      @@    
-                  @@   @@   @@@  @@  @@   @@   @@   @@  @@@@@@@@
-                  @@@@@     @@   @@ @@     @@ @@     @@   @@    
-                  @@        @@      @@     @@ @@     @@   @@    
-                  @@        @@      @@     @@ @@     @@   @@    
-                  @@        @@      @@     @@ @@     @@   @@    
-                  @@        @@       @@   @@   @@   @@    @@    
-                @@@@@@     @@@@        @@@       @@@    @@@@@@  
-
-                                  Formal Proof
-
-                Alliance CAD System 3.2b, proof 4.20 [1997/10/09]
-                Copyright (c) 1990-1997,           ASIM/LIP6/UPMC
-                E-mail support:     alliance-support@asim.lip6.fr
-
-================================  Environment  ================================
-MBK_WORK_LIB		= .
-MBK_CATA_LIB		= ./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib
-=======================  Files, Options and Parameters  =======================
-First VHDL file		= sample_dpt.vbe
-Second VHDL file	= hierarchy_dpt_desb.vbe
-The auxiliary signals are erased
-Errors are displayed
-===============================================================================
-
-Compiling 'sample_dpt' ...
-Compiling 'hierarchy_dpt_desb' ...
-WARNING : data_s_0 is considered as an output signal
-WARNING : data_s_1 is considered as an output signal
-WARNING : data_s_2 is considered as an output signal
-WARNING : data_s_3 is considered as an output signal
-WARNING : data_s_4 is considered as an output signal
-WARNING : data_s_5 is considered as an output signal
-WARNING : data_s_6 is considered as an output signal
-WARNING : data_s_7 is considered as an output signal
-WARNING : data_s_0 is considered as an output signal
-WARNING : data_s_1 is considered as an output signal
-WARNING : data_s_2 is considered as an output signal
-WARNING : data_s_3 is considered as an output signal
-WARNING : data_s_4 is considered as an output signal
-WARNING : data_s_5 is considered as an output signal
-WARNING : data_s_6 is considered as an output signal
-WARNING : data_s_7 is considered as an output signal
-WARNING : ctrl_nover is considered as an output signal
-
-Running abl ordonnancer on `sample_dpt`
-...........................
-
-Running Abl2Bdd on `sample_dpt`
----> final number of nodes = 1008(633)
-
-Warning : Input 'mbk_sig285' only exists in the second description
-Running Abl2Bdd on `hierarchy_dpt_desb`
-
-Running abl ordonnancer on `sample_dpt`
-...........................
-
-Running Abl2Bdd on `sample_dpt`
----> final number of nodes = 2055(633)
-
-Running Abl2Bdd on `hierarchy_dpt_desb`
---------------------------------------------------------------------------------
-             Formal proof with Ordered Binary Decision Diagrams between   
-
-             './sample_dpt'  and  './hierarchy_dpt_desb'
---------------------------------------------------------------------------------
-==============================  PRIMARY OUTPUT  ===============================
-=============================  AUXILIARY SIGNAL  ==============================
-==============================  REGISTER SIGNAL  ==============================
-===============================  EXTERNAL BUS =================================
-================================ INTERNAL BUS =================================
-
-                            Formal Proof : OK
-
-pppppppppppppppppppppppprrrrrrrrrrrrooooooooooooooooooooooooooooofffffffffffffff
---------------------------------------------------------------------------------
-
-
-
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB; MBK_OUT_LO=vst; export MBK_OUT_LO; MBK_IN_LO=vst; export MBK_IN_LO; MBK_OUT_PH=ap;  export MBK_OUT_PH; MBK_IN_PH=ap;  export MBK_IN_PH; /users/soft5/newlabo/Solaris/bin/bop   -o adder_us     adder_us_opt
-
-                         @@@           @@@              
-                          @@         @@   @@            
-                          @@        @@     @@           
-                          @@ @@    @@       @@ @@@ @@@  
-                          @@@  @@  @@       @@  @@@  @@ 
-                          @@    @@ @@       @@  @@    @@
-                          @@    @@ @@       @@  @@    @@
-                          @@    @@ @@       @@  @@    @@
-                          @@    @@  @@     @@   @@    @@
-                          @@@  @@    @@   @@    @@@  @@ 
-                         @@@ @@        @@@      @@ @@@  
-                                                @@      
-                                               @@@@     
-
-                              Boolean OPtimization
-
-                 Alliance CAD System 3.2b, bop 4.20 [1997/10/09]
-                 Copyright (c) 1990-1997,         ASIM/LIP6/UPMC
-                 E-mail support:   alliance-support@asim.lip6.fr
-
-================================  Environment  ================================
-MBK_WORK_LIB        = .
-MBK_CATA_LIB        = ./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib
-=======================  Files, Options and Parameters  =======================
-VHDL file           = adder_us.vbe
-output file         = adder_us_opt.vbe
-Parameter file      = default.lax
-Mode                = Global optimization
-Optimization mode   = 50% area - 50% delay optimization
-Optimization level  = 2
-===============================================================================
-
-Compiling 'adder_us' ...
-
-Running abl ordonnancer on `adder_us`
-..........
-
-Running Abl2Bdd on `adder_us`
-
----> Final number of nodes = 108(70)
-
-Running Global Optimizer on `adder_us`
-
-=============================  INITIAL COST  ==================================
-Total number of literals    = 3171
-Number of reduced literals  = 75
-Number of latches           = 0
-Maximum logical depth       = 25
-Maximum delay               = 8.500
-===============================================================================
-................
-................
-................
-................
-..........
-==============================  FINAL COST  ===================================
-Total number of literals    = 170
-Number of reduced literals  = 61
-Number of latches           = 0
-Maximum logical depth       = 18
-Maximum delay               = 7.666
-===============================================================================
-BEH : Saving 'adder_us_opt' in a vhdl file (vbe)
-
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB; MBK_OUT_LO=vst; export MBK_OUT_LO; MBK_IN_LO=vst; export MBK_IN_LO; MBK_OUT_PH=ap;  export MBK_OUT_PH; MBK_IN_PH=ap;  export MBK_IN_PH; /users/soft5/newlabo/Solaris/bin/scmap    adder_us_opt adder_us
-
-                @@@@ @      @@@@ @                                 
-               @    @@    @@    @@                                 
-              @@     @   @@      @                                 
-              @@@       @@       @ @@@ @@ @@@     @@@@    @@@ @@@  
-               @@@@     @@          @@@ @@  @@   @@   @    @@@  @@ 
-                 @@@@   @@          @@  @@  @@   @@   @@   @@    @@
-                   @@@  @@          @@  @@  @@     @@@@@   @@    @@
-              @      @@ @@          @@  @@  @@   @@   @@   @@    @@
-              @@     @@  @@      @  @@  @@  @@  @@    @@   @@    @@
-              @@@    @    @@    @@  @@  @@  @@  @@   @@@   @@@  @@ 
-              @  @@@@       @@@@   @@@@ @@@ @@@  @@@@  @@  @@ @@@  
-                                                           @@      
-                                                          @@@@     
-
-                             Mapping Standard Cells
-
-                Alliance CAD System 3.2b, scmap 4.20 [1997/10/09]
-                Copyright (c) 1990-1997,           ASIM/LIP6/UPMC
-                E-mail support:     alliance-support@asim.lip6.fr
-
-================================  Environment  ================================
-MBK_WORK_LIB        = .
-MBK_CATA_LIB        = ./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib
-MBK_TARGET_LIB      = /users/outil2/fitpath/labo/cells/dplib
-MBK_IN_LO           = vst
-MBK_OUT_LO          = vst
-=======================  Files, Options and Parameters  =======================
-VHDL file           = adder_us_opt.vbe
-output file         = adder_us.vst
-Parameter file      = default.lax
-Mode                = Mapping standard cell
-Optimization mode   = 50% area - 50% delay optimization
-Optimization level  = 2
-===============================================================================
-
-Compiling 'adder_us_opt' ...
-Running Standard Cell Mapping
-=============================  INITIAL COST  ==================================
-Total number of literals    = 170
-Number of reduced literals  = 61
-Number of latches           = 0
-Maximum logical depth       = 18
-Maximum delay               = 7.666
-===============================================================================
-Compiling library '/users/outil2/fitpath/labo/cells/dplib'
-Generating Expert System ...
-Cell 'cry_dp' Unused
-Cell 'sum_dp' Unused
-126 rules generated
-...............
-
-==============================  FINAL COST  ===================================
-Number of cells used  = 10
-Number of gates used  = 66
-Number of inverters   = 16
-Number of grids       = 102240
-Depth max. (gates)          = 11
-           (eq. neg. gates) = 15
-===============================================================================
-
-MBK Driving './adder_us.vst'...
-
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB; MBK_OUT_LO=vst; export MBK_OUT_LO; MBK_IN_LO=vst; export MBK_IN_LO; MBK_OUT_PH=ap;  export MBK_OUT_PH; MBK_IN_PH=ap;  export MBK_IN_PH;  /users/outil2/fitpath/dev/Solaris/bin/fpgen -v synthesis_dpt
-
-             @@@@@@@@@                @@@@ @                        
-               @@    @              @@    @@                        
-               @@     @            @@      @                        
-               @@       @@@ @@@   @@             @@@@@   @@@ @@@    
-               @@   @    @@@  @@  @@            @     @   @@@   @   
-               @@@@@@    @@    @@ @@     @@@@@ @@     @@  @@    @@  
-               @@   @    @@    @@ @@     @ @@  @@@@@@@@@  @@    @@  
-               @@        @@    @@ @@    @  @@  @@         @@    @@  
-               @@        @@    @@  @@      @@  @@      @  @@    @@  
-               @@        @@@  @@    @@    @@    @@    @@  @@    @@  
-             @@@@@@      @@ @@@       @@@@        @@@@   @@@@  @@@@ 
-                         @@                                         
-                        @@@@                                        
-
-                           Fitpath Generation Language         
-
-                 Alliance CAD System V.R,           fpgen V.RR 
-                 Copyright (c) 93-AA,           ASIM/LIP6/UPMC 
-                 E-mail support: alliance-support@asim.lip6.fr 
-
-
-  o  Alliance Devellopment environment:
-     - DEVEL_TOP       : /users/outil2/fitpath/dev/Solaris
-     - DEVEL_VERSION   : 113
-  o  Current Alliance environment:
-     - ALLIANCE_TOP    : not set
-     -      MACHINE    : Solaris
-  o  Current MBK environment:
-     - MBK_IN_LO       : vst
-     - MBK_OUT_LO      : vst
-     - MBK_IN_PH       : ap
-     - MBK_OUT_PH      : ap
-     - MBK_WORK_LIB    : .
-     - MBK_CATA_LIB    : ./mclib
-                         /users/soft5/newlabo/Solaris/cells/rsa
-                         /users/outil2/fitpath/labo/cells/fplib
-                         /users/outil2/fitpath/labo/cells/dplib
-     - MBK_CATAL_NAME  : CATAL
-     - MBK_VDD         : vdd
-     - MBK_VSS         : vss
-     - RDS_TECHNO_NAME : not set
-  o  FpGen Macro-Functions library:
-     - FPGEN_LIB       : ./mclib
-
-  o  Program generation.
-     - Creating Makefile.
-     - Running Makefile.
-  o  Execute program...
-FpGen:DP_TRACE:Trace mode ON at line 54 of file "synthesis_dpt.c".
-*** FpGen Trace ***:
-      Macro-Function : DP_MUX2CS.
-    (char *)InstName : (0x000E0C38) "multiplexer".
-         (long)Width : (0x--------)  8.
-         (long)Slice : (0x--------)  0.
-             [ Model : "mux2cs_8x8x0l_cl" : Generated on memory ]
-      (char *)Signal : (0x000E0B90) "ctrl_sel".
-      (char *)Signal : (0x000E0BF8) "data_b[7:0]".
-      (char *)Signal : (0x000E0C48) "data_q[7:0]".
-      (char *)Signal : (0x000E0C58) "data_m[7:0]".
-      (char *)Signal : (0x00000000) --> EOL.
-*** FpGen xvLoins ***:MBK terminals assigments (reverse order):
-              o[0:7] => data_m[0:7]
-             i0[0:7] => data_q[0:7]
-             i1[0:7] => data_b[0:7]
-                 sel => ctrl_sel
-*** FpGen Trace ***:
-      Macro-Function : DP_IMPORT.
-   (char *)ModelName : (0x000E0C68) "adder_us".
-    (char *)InstName : (0x000E0C78) "adder".
-      (char *)Signal : (0x000E0BE8) "data_a[7:0]".
-      (char *)Signal : (0x000E0C58) "data_m[7:0]".
-      (char *)Signal : (0x000E0BB8) "ctrl_ncout".
-      (char *)Signal : (0x000E0BC8) "ctrl_nover".
-      (char *)Signal : (0x000E0C08) "data_s[7:0]".
-      (char *)Signal : (0x00000000) --> EOL.
-*** FpGen xvLoins ***:MBK terminals assigments (reverse order):
-              s[0:7] => data_s[0:7]
-              over_n => ctrl_nover
-              cout_n => ctrl_ncout
-              b[0:7] => data_m[0:7]
-              a[0:7] => data_a[0:7]
-*** FpGen Trace ***:
-      Macro-Function : DP_NUL.
-    (char *)InstName : (0x000E0C80) "zero".
-         (long)Width : (0x--------)  8.
-         (long)Slice : (0x--------)  0.
-             [ Model : "nul_8x8x0l_cl" : Generated on memory ]
-      (char *)Signal : (0x000E0C08) "data_s[7:0]".
-      (char *)Signal : (0x000E0BD8) "ctrl_zero".
-      (char *)Signal : (0x00000000) --> EOL.
-*** FpGen xvLoins ***:MBK terminals assigments (reverse order):
-                   o => ctrl_zero
-             i0[0:7] => data_s[0:7]
-*** FpGen Trace ***:
-      Macro-Function : DP_PDFF.
-    (char *)InstName : (0x000E0C88) "memory".
-         (long)Width : (0x--------)  8.
-         (long)Slice : (0x--------)  0.
-             [ Model : "pdff_8x8x0l_cl" : Generated on memory ]
-      (char *)Signal : (0x000E0BA8) "ctrl_wen".
-      (char *)Signal : (0x000E0BA0) "ctrl_ck".
-      (char *)Signal : (0x000E0C08) "data_s[7:0]".
-      (char *)Signal : (0x000E0C48) "data_q[7:0]".
-      (char *)Signal : (0x000E0C90) "data_u[7:0]".
-      (char *)Signal : (0x00000000) --> EOL.
-*** FpGen xvLoins ***:MBK terminals assigments (reverse order):
-             nq[0:7] => data_u[0:7]
-              q[0:7] => data_q[0:7]
-              d[0:7] => data_s[0:7]
-                  ck => ctrl_ck
-                 wen => ctrl_wen
-FpGen:DP_TRACE:Trace mode OFF at line 90 of file "synthesis_dpt.c".
-     - Exit code := 0.
-
-  o  Remove temporary file.
-
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB; MBK_OUT_LO=vst; export MBK_OUT_LO; MBK_IN_LO=vst; export MBK_IN_LO; MBK_OUT_PH=ap;  export MBK_OUT_PH; MBK_IN_PH=ap;  export MBK_IN_PH;      /users/outil3/dpr/labo/Solaris/bin/dpr -V -p -r synthesis_dpt synthesis_dpt
-
-                       @@@@@@@     @@@@@@@    @@@@@@@    
-                         @@   @@     @@   @@    @@   @@  
-                         @@    @@    @@    @@   @@    @@ 
-                         @@     @@   @@    @@   @@    @@ 
-                         @@     @@   @@   @@    @@   @@  
-                         @@     @@   @@@@@      @@@@@    
-                         @@     @@   @@         @@  @@   
-                         @@     @@   @@         @@   @@  
-                         @@    @@    @@         @@   @@  
-                         @@   @@     @@         @@    @@ 
-                       @@@@@@@     @@@@@@     @@@@@   @@@
-
-                       Placer-Router for Datapath Compiler
-
-                  Alliance CAD System 3.2b,             dpr 6.2
-                  Copyright (c) 1994-1997,       ASIM/LIP6/UPMC
-                  E-mail support: alliance-support@asim.lip6.fr
-
-
- * MBK parameters :
-
-       MBK_WORK_LIB   : .
-       MBK_CATA_LIB   : ./mclib
-                      : /users/soft5/newlabo/Solaris/cells/rsa
-                      : /users/outil2/fitpath/labo/cells/fplib
-                      : /users/outil2/fitpath/labo/cells/dplib
-       MBK_IN_PH      : ap
-       MBK_OUT_PH     : ap
-       MBK_IN_LO      : vst
-       MBK_OUT_LO     : vst
-       TECHNO         : CMOS
-
- * Placement step.
-   o Getting netlist.
-   o Getting dpr file.
-   o Building symbolic grid.
-     -> Routed bloc : 'memory' (pdff_8x8x0l_cl).
-     -> Routed bloc : 'zero' (nul_8x8x0l_cl).
-     -> Glue bloc   : 'adder' (adder_us).
-     -> Routed bloc : 'multiplexer' (mux2cs_8x8x0l_cl).
-   o Ckecking slices heights.
-
-   o Nb slices : 10.
-   o Nb cols   : 4.
-
-   o Creating column.
-   o Creating glue logic blocs.
-     -> Logic Bloc  : 'adder'.
-     -> over_n place to the north side.
-     -> cout_n place to the north side.
-     -> s 0 connected with zero on slice 0 on east side.
-     -> s 1 connected with zero on slice 1 on east side.
-     -> s 2 connected with zero on slice 2 on east side.
-     -> s 3 connected with zero on slice 3 on east side.
-     -> s 4 connected with zero on slice 4 on east side.
-     -> s 5 connected with zero on slice 5 on east side.
-     -> s 6 connected with zero on slice 6 on east side.
-     -> s 7 connected with zero on slice 7 on east side.
-     -> b 0 connected with multiplexer on slice 0 on west side.
-     -> b 1 connected with multiplexer on slice 1 on west side.
-     -> b 2 connected with multiplexer on slice 2 on west side.
-     -> b 3 connected with multiplexer on slice 3 on west side.
-     -> b 4 connected with multiplexer on slice 4 on west side.
-     -> b 5 connected with multiplexer on slice 5 on west side.
-     -> b 6 connected with multiplexer on slice 6 on west side.
-     -> b 7 connected with multiplexer on slice 7 on west side.
-     -> Loading netlist.
-     -> Symbolic placement
-
-        netlist        : adder_us
-        iterations     : 5000
-        rows           : 8
-        cells_per_cols : 2
-
-     -> Checking cells height.
-     -> Number of track per slice : 10.
-     -> placing.
-
-Loading SCP data base ...
-Generating initial placement ... 
-66 cells 84 nets in 8 rows
-Placement in process of treatment :   0%  2%  3%  4%  5%  6%  8%  9% 10% 11% 12% 13% 15% 16% 17% 18% 19% 20% 22% 23% 24% 25% 26% 28% 29% 30% 31% 32% 33% 35% 36% 37% 38% 39% 40% 42% 43% 44% 45% 46% 48% 49% 50% 51% 52% 53% 55% 56% 57% 58% 59% 60% 62% 63% 64% 65% 66% 68% 69% 70% 71% 72% 73% 75% 76% 77% 78% 79% 80% 82% 83% 84% 85% 86% 88% 89% 90% 91% 92% 93% 95% 96% 97% 98% 99%100%
-70% saved in 42.4 s
-
-     -> initialising structure.
-     -> making channel.
-     -> nb columns : 5.
-     -> Done.
-
-   o Checking alims correspondances.
-   o Creating global phfig view.
-     Moving connector data_s 0 on EAST side, slice 0, default track.
-     Moving connector data_s 1 on EAST side, slice 1, default track.
-     Moving connector data_s 2 on EAST side, slice 2, default track.
-     Moving connector data_s 3 on EAST side, slice 3, default track.
-     Moving connector data_s 4 on EAST side, slice 4, default track.
-     Moving connector data_s 5 on EAST side, slice 5, default track.
-     Moving connector data_s 6 on EAST side, slice 6, default track.
-     Moving connector data_s 7 on EAST side, slice 7, default track.
-     Moving connector data_b 0 on WEST side, slice 0, default track.
-     Moving connector data_b 1 on WEST side, slice 1, default track.
-     Moving connector data_b 2 on WEST side, slice 2, default track.
-     Moving connector data_b 3 on WEST side, slice 3, default track.
-     Moving connector data_b 4 on WEST side, slice 4, default track.
-     Moving connector data_b 5 on WEST side, slice 5, default track.
-     Moving connector data_b 6 on WEST side, slice 6, default track.
-     Moving connector data_b 7 on WEST side, slice 7, default track.
-     Moving connector data_a 0 on WEST side, slice 0, default track.
-     Moving connector data_a 1 on WEST side, slice 0, default track.
-     Moving connector data_a 2 on WEST side, slice 1, default track.
-     Moving connector data_a 3 on WEST side, slice 1, default track.
-     Moving connector data_a 4 on WEST side, slice 3, default track.
-     Moving connector data_a 5 on WEST side, slice 3, default track.
-     Moving connector data_a 6 on WEST side, slice 5, default track.
-     Moving connector data_a 7 on WEST side, slice 7, default track.
-   o Freeing symbolic grid.
- * Placement done.
-
- * Routing step.
-   o Loading physical and logical views.
-   o Setting access types.
-      -> noa3_dp.
-      -> nao3_dp.
-      -> annup_dp.
-      -> xr2_dp.
-      -> noa4_dp.
-      -> o2_dp.
-      -> a2_dp.
-      -> na2_dp.
-      -> no2_dp.
-      -> n1_dp.
-      -> pdff_8x8x0l_cl.
-      -> nul_8x8x0l_cl.
-      -> mux2cs_8x8x0l_cl.
-   o Checking logical and physical correspondance.
-      -> Signal data_u_7 not connected to any other terminal.
-      -> Signal data_u_6 not connected to any other terminal.
-      -> Signal data_u_5 not connected to any other terminal.
-      -> Signal data_u_4 not connected to any other terminal.
-      -> Signal data_u_3 not connected to any other terminal.
-      -> Signal data_u_2 not connected to any other terminal.
-      -> Signal data_u_1 not connected to any other terminal.
-      -> Signal data_u_0 not connected to any other terminal.
-   o Making DPR data structure.
-     -> External North/South terminal ctrl_ncout replaced.
-     -> External North/South terminal ctrl_nover replaced.
-     -> External North/South terminal ctrl_zero replaced.
-   o Global routing.
-   o Bit-slice symbolic routing.
-     -> Bit-slice 0.
-     -> Bit-slice 1.
-     -> Bit-slice 2.
-     -> Bit-slice 3.
-     -> Bit-slice 4.
-     -> Bit-slice 5.
-     -> Bit-slice 6.
-     -> Bit-slice 7.
-     -> Bit-slice 8.
-     -> Bit-slice 9.
-   o Multi-bit net symbolic routing.
-     -> Left connectors column.
-     -> Column 1.
-     -> Column 2.
-     -> Column 3.
-     -> Column 4.
-     -> Column 5.
-     -> Column 6.
-     -> Column 7.
-     -> Column 8.
-     -> Right connectors column.
-   o Channel routing.
-     -> Channel 1.
-     -> Channel 2.
-     -> Channel 3.
-     -> Channel 4.
-     -> Channel 5.
-     -> Channel 6.
-     -> Channel 7.
-     -> Channel 8.
-     -> Channel 9.
-   o Saving physical figure synthesis_dpt.
-     -> Column 1.
-     -> Column 2.
-     -> Column 3.
-     -> Column 4.
-     -> Column 5.
-     -> Column 6.
-     -> Column 7.
-     -> Column 8.
-   o Checking for short cut.
-     -> Instance memory(pdff_8x8x0l_cl).
-     -> Instance zero(nul_8x8x0l_cl).
-     -> Instance adder.s_0(xr2_dp).
-     -> Instance adder.auxsc26(a2_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance adder.auxsc16(n1_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance adder.auxsc15(n1_dp).
-     -> Instance adder.s_4(xr2_dp).
-     -> Instance adder.s_5(xr2_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance adder.s_7(xr2_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance adder.auxsc6(na2_dp).
-     -> Instance adder.auxsc95(n1_dp).
-     -> Instance adder.auxsc27(no2_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance adder.auxsc9(a2_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance adder.auxsc101(no2_dp).
-     -> Instance adder.s_2(xr2_dp).
-     -> Instance adder.auxsc98(xr2_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance adder.auxsc67(o2_dp).
-     -> Instance adder.auxsc108(no2_dp).
-     -> Instance adder.auxsc107(xr2_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance adder.auxsc76(no2_dp).
-     -> Instance adder.aux27_a(o2_dp).
-     -> Instance adder.auxsc75(xr2_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance adder.aux22_a(annup_dp).
-     -> Instance adder.auxsc91(a2_dp).
-     -> Instance adder.auxsc4(n1_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance adder.s_1(xr2_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance adder.auxsc105(noa3_dp).
-     -> Instance adder.auxsc30(o2_dp).
-     -> Instance adder.auxsc45(n1_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance adder.s_3(xr2_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance adder.auxsc51(o2_dp).
-     -> Instance adder.auxsc68(noa3_dp).
-     -> Instance adder.aux26_a(annup_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance adder.auxsc50(a2_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance adder.auxsc63(a2_dp).
-     -> Instance adder.s_6(xr2_dp).
-     -> Instance adder.auxsc88(na2_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance adder.auxsc74(n1_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance adder.auxsc97(noa4_dp).
-     -> Instance adder.auxsc94(n1_dp).
-     -> Instance adder.auxsc92(xr2_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance adder.auxsc24(n1_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance adder.aux24_a(annup_dp).
-     -> Instance adder.auxsc104(o2_dp).
-     -> Instance adder.auxsc48(no2_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance adder.auxsc100(xr2_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance adder.auxsc103(xr2_dp).
-     -> Instance adder.auxsc57(n1_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance adder.auxsc64(no2_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance adder.auxsc85(na2_dp).
-     -> Instance adder.auxsc66(xr2_dp).
-     -> Instance adder.cout_n(nao3_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance adder.auxsc90(no2_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance adder.auxsc5(n1_dp).
-     -> Instance adder.auxsc7(no2_dp).
-     -> Instance adder.auxsc96(na2_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance adder.auxsc23(n1_dp).
-     -> Instance adder.auxsc29(a2_dp).
-     -> Instance adder.auxsc32(a2_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance adder.auxsc35(n1_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance adder.auxsc34(n1_dp).
-     -> Instance adder.auxsc47(a2_dp).
-     -> Instance adder.auxsc44(n1_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance adder.auxsc86(o2_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance adder.auxsc56(n1_dp).
-     -> Instance adder.auxsc53(a2_dp).
-     -> Instance adder.auxsc73(n1_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance adder.auxsc89(a2_dp).
-*** dpr warning *** : instance with transformation in SeekNotCon(ignored)
-     -> Instance multiplexer(mux2cs_8x8x0l_cl).
-   o Total routing time: 4 seconds.
- * Routing step done.
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB; MBK_OUT_LO=vst; export MBK_OUT_LO; MBK_IN_LO=vst; export MBK_IN_LO; MBK_OUT_PH=ap;  export MBK_OUT_PH; MBK_IN_PH=ap;  export MBK_IN_PH; /users/soft5/newlabo/Solaris/bin/druc synthesis_dpt
-
-                  @@@@@@@     @@@@@@@                    @@@@ @
-                    @@   @@     @@   @@                @@    @@
-                    @@    @@    @@    @@              @@      @
-                    @@     @@   @@    @@  @@@  @@@@  @@       @
-                    @@     @@   @@   @@    @@    @@  @@        
-                    @@     @@   @@@@@      @@    @@  @@        
-                    @@     @@   @@  @@     @@    @@  @@        
-                    @@     @@   @@   @@    @@    @@  @@        
-                    @@    @@    @@   @@    @@    @@   @@      @
-                    @@   @@     @@    @@   @@   @@@    @@    @@
-                  @@@@@@@     @@@@@   @@@   @@@@  @@     @@@@  
-
-                               Design Rule Checker
-
-                     Alliance CAD System 3.2,      druc 3.00
-                     Copyright (c) 1993, MASI, CAO-VLSI Team
-                     E-mail support:    cao-vlsi@masi.ibp.fr
-
-Flatten DRC on: synthesis_dpt
-Delete MBK figure : synthesis_dpt
-Load Flatten Rules : /users/alc/distrib/dev/alliance-3.2b/etc/cmos_7.rds
-
-Unify : synthesis_dpt
-
-Create Ring : synthesis_dpt_rng
-Merge Errorfiles: 
-
-Merge Error Instances:
-instructionCourante : 000  0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
-End DRC on: synthesis_dpt
-Saving the Error file figure
-Done
-  0
-
-File: synthesis_dpt.drc is empty: no errors detected.
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB; MBK_OUT_LO=al;  export MBK_OUT_LO; MBK_IN_LO=al;  export MBK_IN_LO;  MBK_OUT_PH=ap;  export MBK_OUT_PH; MBK_IN_PH=ap;  export MBK_IN_PH; /users/soft5/newlabo/Solaris/bin/lynx -v -f synthesis_dpt synthesis_dpt_gates
-
-                   @@@@@@                                    
-                     @@                                      
-                     @@                                      
-                     @@        @@@@@ @@@ @@@ @@@    @@@@  @@@
-                     @@         @@    @   @@@   @    @@    @ 
-                     @@          @@   @   @@    @@    @@  @  
-                     @@          @@  @    @@    @@     @@@   
-                     @@           @@ @    @@    @@     @@@   
-                     @@      @    @@@     @@    @@    @  @@  
-                     @@     @      @@     @@    @@   @    @@ 
-                   @@@@@@@@@@  @@  @     @@@@  @@@@ @@@  @@@@
-                               @@  @                         
-                                @@@                          
-
-                                Netlist extractor
-
-                     Alliance CAD System 3.2,      lynx 1.16
-                     Copyright (c) 1997, MASI, CAO-VLSI Team
-                     E-mail support:    cao-vlsi@masi.ibp.fr
-
-
-
-	---> Extracts symbolic figure synthesis_dpt
-
-		---> Flatten figure
-
-		---> Translate Mbk -> Rds
-		---> Build windows
-		<--- 420
-
-		---> Rectangles    : 9263
-		---> Figure size   : (   -100,   -400 )
-		                     (  64100,  60400 )
-
-		---> Cut transistors
-		<--- 0
-		---> Build equis
-		<--- 112
-		---> Delete windows
-		---> Build signals
-		<--- 112
-		---> Build instances
-		<--- 69
-		---> Build transistors
-		<--- 0
-		---> Save netlist
-
-	<--- done !
-
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB;                        /users/soft5/newlabo/Solaris/bin/lvx vst al synthesis_dpt synthesis_dpt_gates -f
-
-                       @@@@@@      @@@@    @@@ @@@@   @@@@
-                         @@         @@      @   @@     @  
-                         @@         @@      @    @@   @   
-                         @@          @@    @      @@ @    
-                         @@          @@    @       @@     
-                         @@           @@  @        @@     
-                         @@           @@  @        @@@    
-                         @@            @@@        @  @@   
-                         @@      @     @@@       @    @@  
-                         @@     @       @       @      @@ 
-                       @@@@@@@@@@       @      @@@    @@@@
-
-                             Gate Netlist Comparator
-
-                   Alliance CAD System 3.2,          lvx 2.23
-                   Copyright (c) 1992-93, MASI, CAO-VLSI Team
-                   E-mail support:       cao-vlsi@masi.ibp.fr
-
-
-
-***** Loading and flattening synthesis_dpt (vst)...
-
-***** Loading and flattening synthesis_dpt_gates (al)...
-
-
-***** Compare Terminals ..................
-***** O.K.	(0 sec)
-
-***** Compare Instances ...........
-***** O.K.	(0 sec)
-
-***** Compare Connections .................
-***** O.K.	(0 sec)
-
-===== Terminals .......... 32    
-===== Instances .......... 69    
-===== Connectors ......... 448   
-
-
-***** Netlists are Identical. *****	(0 sec)
-
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB; MBK_OUT_LO=al;  export MBK_OUT_LO; MBK_IN_LO=al;  export MBK_IN_LO;  MBK_OUT_PH=ap;  export MBK_OUT_PH; MBK_IN_PH=ap;  export MBK_IN_PH; /users/soft5/newlabo/Solaris/bin/lynx -v -t synthesis_dpt synthesis_dpt
-
-                   @@@@@@                                    
-                     @@                                      
-                     @@                                      
-                     @@        @@@@@ @@@ @@@ @@@    @@@@  @@@
-                     @@         @@    @   @@@   @    @@    @ 
-                     @@          @@   @   @@    @@    @@  @  
-                     @@          @@  @    @@    @@     @@@   
-                     @@           @@ @    @@    @@     @@@   
-                     @@      @    @@@     @@    @@    @  @@  
-                     @@     @      @@     @@    @@   @    @@ 
-                   @@@@@@@@@@  @@  @     @@@@  @@@@ @@@  @@@@
-                               @@  @                         
-                                @@@                          
-
-                                Netlist extractor
-
-                     Alliance CAD System 3.2,      lynx 1.16
-                     Copyright (c) 1997, MASI, CAO-VLSI Team
-                     E-mail support:    cao-vlsi@masi.ibp.fr
-
-
-
-	---> Extracts symbolic figure synthesis_dpt
-
-		---> Flatten figure
-
-		---> Translate Mbk -> Rds
-		---> Build windows
-		<--- 420
-
-		---> Rectangles    : 20952
-		---> Figure size   : (   -100,   -400 )
-		                     (  64100,  60400 )
-
-		---> Cut transistors
-		<--- 8
-		---> Build equis
-		<--- 378
-		---> Delete windows
-		---> Build signals
-		<--- 378
-		---> Build instances
-		<--- 0
-		---> Build transistors
-		<--- 706
-		---> Save netlist
-
-	<--- done !
-
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB; MBK_OUT_LO=al;  export MBK_OUT_LO; MBK_IN_LO=al;  export MBK_IN_LO;             /users/soft5/newlabo/Solaris/bin/yagle synthesis_dpt synthesis_dpt_desb -v -i
-
-                                               @@@@            
-                                                 @@            
-                                                 @@            
-                  @@@@@ @@@   @@@@      @@@@@@   @@     @@@@@  
-                   @@    @   @@   @    @@  @@    @@    @     @ 
-                    @@   @   @@   @@   @   @@    @@   @@     @@
-                    @@  @      @@@@@   @   @     @@   @@@@@@@@@
-                     @@ @    @@   @@    @@@      @@   @@       
-                     @@@    @@    @@   @@        @@   @@      @
-                      @@    @@   @@@   @@@@@@    @@    @@    @@
-                  @@  @      @@@@  @@ @@   @@@ @@@@@@    @@@@  
-                  @@  @                @     @                 
-                   @@@                  @@@@@                  
-
-                        Yet Another Gate Level Extractor
-
-                  Alliance CAD System 3.2,           yagle 2.02
-                  Copyright (c) 94-97-1997,      ASIM/LIP6/UPMC
-                  E-mail support: alliance-support@asim.lip6.fr
-
-[YAG MES] Reading file 'synthesis_dpt.inf'
-[YAG MES] Loading the figure synthesis_dpt         00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Transistor netlist checking              00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Extracting CMOS duals                    00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Extracting bleeders                      00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Making gates                             00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Latches detection                        00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Making cells                             00m00s  u:00m00.0  s:00m00.0
-[YAG MES] External connector verification          00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Checking the yagle figure                00m00s  u:00m00.0  s:00m00.0
-[YAG MES] Building the behavioural figure          00m00s  u:00m00.0  s:00m00.0
-TOTAL DISASSEMBLY TIME                             00m00s  u:00m00.1  s:00m00.0
-------------------------------------------------------------
-[YAG MES] Erasing the transistor netlist
-[YAG MES] Generating the VHDL Data Flow
-[YAG MES] Execution COMPLETED 
-------------------------------------------------------------
-[YAG WAR 07] 16 transistors are not used 
-[YAG WAR 09] 16 latches detected
-See file 'synthesis_dpt.rep' for more information
-MBK_WORK_LIB=.;           export MBK_WORK_LIB; MBK_CATA_LIB=./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib; export MBK_CATA_LIB; MBK_CATAL_NAME=CATAL;     export MBK_CATAL_NAME; MBK_SEPAR=.;              export MBK_SEPAR; MBK_VDD=vdd;              export MBK_VDD; MBK_VSS=vss;              export MBK_VSS; MBK_TARGET_LIB=/users/outil2/fitpath/labo/cells/dplib;  export MBK_TARGET_LIB; MBK_LOG_NAME="";          export MBK_LOG_NAME; FPGEN_LIB=./mclib;   export FPGEN_LIB;                        /users/soft5/newlabo/Solaris/bin/proof -d sample_dpt synthesis_dpt_desb
-
-                @@@@@@@                                     @@@ 
-                  @@   @@                                  @  @@
-                  @@    @@                                @@  @@
-                  @@    @@ @@@ @@@     @@@       @@@      @@    
-                  @@   @@   @@@  @@  @@   @@   @@   @@  @@@@@@@@
-                  @@@@@     @@   @@ @@     @@ @@     @@   @@    
-                  @@        @@      @@     @@ @@     @@   @@    
-                  @@        @@      @@     @@ @@     @@   @@    
-                  @@        @@      @@     @@ @@     @@   @@    
-                  @@        @@       @@   @@   @@   @@    @@    
-                @@@@@@     @@@@        @@@       @@@    @@@@@@  
-
-                                  Formal Proof
-
-                Alliance CAD System 3.2b, proof 4.20 [1997/10/09]
-                Copyright (c) 1990-1997,           ASIM/LIP6/UPMC
-                E-mail support:     alliance-support@asim.lip6.fr
-
-================================  Environment  ================================
-MBK_WORK_LIB		= .
-MBK_CATA_LIB		= ./mclib:/users/soft5/newlabo/Solaris/cells/rsa:/users/outil2/fitpath/labo/cells/fplib:/users/outil2/fitpath/labo/cells/dplib
-=======================  Files, Options and Parameters  =======================
-First VHDL file		= sample_dpt.vbe
-Second VHDL file	= synthesis_dpt_desb.vbe
-The auxiliary signals are erased
-Errors are displayed
-===============================================================================
-
-Compiling 'sample_dpt' ...
-Compiling 'synthesis_dpt_desb' ...
-WARNING : data_s_0 is considered as an output signal
-WARNING : data_s_1 is considered as an output signal
-WARNING : data_s_2 is considered as an output signal
-WARNING : data_s_3 is considered as an output signal
-WARNING : data_s_4 is considered as an output signal
-WARNING : data_s_5 is considered as an output signal
-WARNING : data_s_6 is considered as an output signal
-WARNING : data_s_7 is considered as an output signal
-WARNING : data_s_0 is considered as an output signal
-WARNING : data_s_1 is considered as an output signal
-WARNING : data_s_2 is considered as an output signal
-WARNING : data_s_3 is considered as an output signal
-WARNING : data_s_4 is considered as an output signal
-WARNING : data_s_5 is considered as an output signal
-WARNING : data_s_6 is considered as an output signal
-WARNING : data_s_7 is considered as an output signal
-
-Running abl ordonnancer on `sample_dpt`
-...........................
-
-Running Abl2Bdd on `sample_dpt`
----> final number of nodes = 1008(633)
-
-Running Abl2Bdd on `synthesis_dpt_desb`
---------------------------------------------------------------------------------
-             Formal proof with Ordered Binary Decision Diagrams between   
-
-             './sample_dpt'  and  './synthesis_dpt_desb'
---------------------------------------------------------------------------------
-==============================  PRIMARY OUTPUT  ===============================
-=============================  AUXILIARY SIGNAL  ==============================
-==============================  REGISTER SIGNAL  ==============================
-===============================  EXTERNAL BUS =================================
-================================ INTERNAL BUS =================================
-
-                            Formal Proof : OK
-
-pppppppppppppppppppppppprrrrrrrrrrrrooooooooooooooooooooooooooooofffffffffffffff
---------------------------------------------------------------------------------
-
-
-
diff --git a/alliance/share/tutorials/fitpath/place_dpt.c b/alliance/share/tutorials/fitpath/place_dpt.c
deleted file mode 100644
index b7d9669f..00000000
--- a/alliance/share/tutorials/fitpath/place_dpt.c
+++ /dev/null
@@ -1,99 +0,0 @@
-
-
-/*          Alliance CAD System V.R                                         */
-/*             FpGen Package V.RR                                           */
-/*                                                                          */
-/*  Copyright(c) 93-AA, MASI, CAO-VLSI Team                                 */
-/*                                                                          */
-/*  Author      :          Jean-Paul CHAPUT                                 */
-/*  E-mail      :      cao-vlsi@masi.ibp.fr                                 */
-/* ======================================================================== */
-/*  File        :      "sample_dpt.c"                                       */
-/* ************************************************************************ */
-/*  Data-Path sample example.                                               */
-
-
-#include  <genlib.h>
-#include  <fpgen.h>
-
-
-main()
-{
-  /* Open a new Data-Path figure.
-   * ============================
-   */
-  DP_DEFLOFIG( "place_dpt", 8, LSB_INDEX_ZERO );
-
-
-  /* Interface description.
-   * ======================
-   */
-
-  /* Control terminals declarations. */
-  DP_LOCON( "ctrl_sel"  , IN   , "ctrl_sel"   );
-  DP_LOCON( "ctrl_ck"   , IN   , "ctrl_ck"    );
-  DP_LOCON( "ctrl_wen"  , IN   , "ctrl_wen"   );
-  DP_LOCON( "ctrl_ncout",   OUT, "ctrl_ncout" );
-  DP_LOCON( "ctrl_nover",   OUT, "ctrl_nover" );
-  DP_LOCON( "ctrl_zero" ,   OUT, "ctrl_zero"  );
-
-  /* Data terminals declarations. */
-  DP_LOCON( "data_a[7:0]" , IN   , "data_a[7:0]" );
-  DP_LOCON( "data_b[7:0]" , IN   , "data_b[7:0]" );
-  DP_LOCON( "data_s[7:0]" , INOUT, "data_s[7:0]" );
-
-  /* Power supplies terminals. */
-  DP_LOCON( "vdd", IN   , "vdd" );
-  DP_LOCON( "vss", IN   , "vss" );
-
-
-  /* Data-Path netlist description.
-   * ==============================
-   */
-
-  DP_TRACE( TRACE_ON );
-
-  /* Zero Detect. */
-  DP_NUL( "zero", 8, 0,
-          "data_s[7:0]",
-          "ctrl_zero",
-          EOL );
-
-  /* Multiplexer. */
-  DP_MUX2CS( "multiplexer", 8, 0,
-             "ctrl_sel",
-             "data_b[7:0]",
-             "data_q[7:0]",
-             "data_m[7:0]",
-             EOL );
-
-  /* Fast Adder. */
-  DP_ADD2F( "adder",
-            "data_a[7:0]",
-            "data_m[7:0]",
-            "ctrl_ncout",
-            "ctrl_nover",
-            "data_s[7:0]",
-            EOL );
-
-  /* Register. */
-  DP_PDFF( "memory", 8, 0,
-           "ctrl_wen",
-           "ctrl_ck",
-           "data_s[7:0]",
-           "data_q[7:0]",
-           "data_u[7:0]",  /* This bus is unused. */
-           EOL );
-
-
-  DP_TRACE( TRACE_OFF );
-
-  /* Terminate the netlist description, and save on disk.
-   * ====================================================
-   */
-  DP_SAVLOFIG();
-
-
-  /* A good C program must always terminate by an "exit(0)". */
-  exit(0);
-}
diff --git a/alliance/share/tutorials/fitpath/place_dpt.dpr b/alliance/share/tutorials/fitpath/place_dpt.dpr
deleted file mode 100644
index 4f391022..00000000
--- a/alliance/share/tutorials/fitpath/place_dpt.dpr
+++ /dev/null
@@ -1,27 +0,0 @@
-#
-#
-# /*          Alliance CAD System V.R                                       */
-# /*             FpGen Package V.RR                                         */
-# /*                                                                        */
-# /*  Copyright(c) 93-AA, MASI, CAO-VLSI Team                               */
-# /*                                                                        */
-# /*  Author      :          Jean-Paul CHAPUT                               */
-# /*  E-mail      :      cao-vlsi@masi.ibp.fr                               */
-# /* ====================================================================== */
-# /*  File        :      "place_dpt.dpr"                                    */
-# /* ********************************************************************** */
-# /*  Data-Path sample example.                                             */
-#
-#
-#           Terminal :  Side  :  Slice  :  Track
-DP_LOCON   ctrl_zero   NORTH    DEFAULT   DEFAULT
-#
-#
-#           Terminal :  Side  :  Slice  :  Track
-DP_LOCON  data_a[7:0]   WEST    DEFAULT   DEFAULT
-DP_LOCON  data_b[7:0]   WEST    DEFAULT   DEFAULT
-DP_LOCON  data_s[7:0]   EAST    DEFAULT   DEFAULT
-#
-#
-# Number of vertical power refreshment.
-DP_POWER  1  50
diff --git a/alliance/share/tutorials/fitpath/place_dpt.inf b/alliance/share/tutorials/fitpath/place_dpt.inf
deleted file mode 100644
index 8403b3dd..00000000
--- a/alliance/share/tutorials/fitpath/place_dpt.inf
+++ /dev/null
@@ -1,4 +0,0 @@
-RENAME
-  memory.pdff_*.memm_s : memory_m(*) ;
-  memory.pdff_*.mems_s : memory_s(*) ;
-END
diff --git a/alliance/share/tutorials/fitpath/place_dpt.sh b/alliance/share/tutorials/fitpath/place_dpt.sh
deleted file mode 100755
index fce9bea2..00000000
--- a/alliance/share/tutorials/fitpath/place_dpt.sh
+++ /dev/null
@@ -1,105 +0,0 @@
-#!/bin/sh
-
-
-#
-#
-# /*          Alliance CAD System V.R                                       */
-# /*             FpGen Package V.RR                                         */
-# /*                                                                        */
-# /*  Copyright(c) 93-AA, MASI, CAO-VLSI Team                               */
-# /*                                                                        */
-# /*  Author      :          Jean-Paul CHAPUT                               */
-# /*  E-mail      :      cao-vlsi@masi.ibp.fr                               */
-# /* ====================================================================== */
-# /*  File        :      "place_dpt.sh"                                     */
-# /* ********************************************************************** */
-# /*  Data-Path using optimized placement example.                          */
-#
-#
-
-
-# Installation Dependent Variables.
-#           ALLIANCE_TOP=/labo
-
-
-# FpGen Macro-Operators Library.
-     FPGEN_LIB=./mclib; export FPGEN_LIB
-
-
-# MBK Enviroment variables settings.
-     MBK_IN_PH=ap;      export MBK_IN_PH
-     MBK_IN_LO=vst;     export MBK_IN_LO
-    MBK_OUT_PH=ap;      export MBK_OUT_PH
-    MBK_OUT_LO=vst;     export MBK_OUT_LO
-  MBK_WORK_LIB=.;       export MBK_WORK_LIB
-  MBK_CATA_LIB=$ALLIANCE_TOP/cells/fitpath/fplib:$ALLIANCE_TOP/cells/rsa:$FPGEN_LIB
-                        export MBK_CATA_LIB
-MBK_CATAL_NAME=CATAL;   export MBK_CATAL_NAME
-       MBK_VDD=vdd;     export MBK_VDD
-       MBK_VSS=vss;     export MBK_VSS
-
-#
-#
-# FpGen : Generation of the Netlist.
-# ==================================
-#
-fpgen -v place_dpt
-
-
-#
-#
-# DPR : Routing the data-path.
-# ============================
-#
-dpr -V -p -o -r place_dpt place_dpt
-
-
-#
-#
-# DRUC : Symbolic Design RUles Checker.
-# =====================================
-#
-druc sample_dpt
-
-
-#
-#
-# LYNX : Gate level netlist extraction.
-# =====================================
-#
-MBK_OUT_LO=al
- MBK_IN_LO=al
-
-lynx -v -f place_dpt place_dpt_gates
-
-
-#
-#
-# LVX : Netlist comparison.
-# =========================
-#
-lvx vst al place_dpt place_dpt_gates -f
-
-
-#
-#
-# LYNX : Transistor netlist extraction.
-# =====================================
-#
-lynx -v -t place_dpt place_dpt
-
-
-#
-#
-# DESB : Behavioral exctraction.
-# ==============================
-#
-desb place_dpt place_dpt_desb -v -i
-
-
-#
-#
-# PROOF : Formal proof.
-# =====================
-#
-proof -d sample_dpt place_dpt_desb
diff --git a/alliance/share/tutorials/fitpath/sample_dpt.c b/alliance/share/tutorials/fitpath/sample_dpt.c
deleted file mode 100644
index d97d72b0..00000000
--- a/alliance/share/tutorials/fitpath/sample_dpt.c
+++ /dev/null
@@ -1,103 +0,0 @@
-
-
-/*          Alliance CAD System V.R                                         */
-/*             FpGen Package V.RR                                           */
-/*                                                                          */
-/*  Copyright(c) 93-AA, MASI, CAO-VLSI Team                                 */
-/*                                                                          */
-/*  Author      :          Jean-Paul CHAPUT                                 */
-/*  E-mail      :      cao-vlsi@masi.ibp.fr                                 */
-/* ======================================================================== */
-/*  File        :      "sample_dpt.c"                                       */
-/* ************************************************************************ */
-/*  Data-Path sample example.                                               */
-
-
-#include  <genlib.h>
-#include  <fpgen.h>
-
-
-main()
-{
-  /* DP_TRACE( TRACE_OFF ); */
-
-
-  /* Open a new Data-Path figure.
-   * ============================
-   */
-  DP_DEFLOFIG( "sample_dpt", 8, LSB_INDEX_ZERO );
-
-
-  /* Interface description.
-   * ======================
-   */
-
-  /* Control terminals declarations. */
-  DP_LOCON( "ctrl_sel"  , IN   , "ctrl_sel"   );
-  DP_LOCON( "ctrl_ck"   , IN   , "ctrl_ck"    );
-  DP_LOCON( "ctrl_wen"  , IN   , "ctrl_wen"   );
-  DP_LOCON( "ctrl_ncout",   OUT, "ctrl_ncout" );
-  DP_LOCON( "ctrl_nover",   OUT, "ctrl_nover" );
-  DP_LOCON( "ctrl_zero" ,   OUT, "ctrl_zero"  );
-
-  /* Data terminals declarations. */
-  DP_LOCON( "data_a[7:0]" , IN   , "data_a[7:0]" );
-  DP_LOCON( "data_b[7:0]" , IN   , "data_b[7:0]" );
-  DP_LOCON( "data_s[7:0]" , INOUT, "data_s[7:0]" );
-
-  /* Power supplies terminals. */
-  DP_LOCON( "vdd", IN   , "vdd" );
-  DP_LOCON( "vss", IN   , "vss" );
-
-
-  /* Data-Path netlist description.
-   * ==============================
-   */
-
-
-  /* Multiplexer. */
-  DP_MUX2CS( "multiplexer", 8, 0,
-             "ctrl_sel",
-             "data_b[7:0]",
-             "data_q[7:0]",
-             "data_m[7:0]",
-             EOL );
-
-  /* Fast Adder. */
-  DP_ADD2F( "adder",
-            "data_a[7:0]",
-            "data_m[7:0]",
-            "ctrl_ncout",
-            "ctrl_nover",
-            "data_s[7:0]",
-            EOL );
-
-  /* Zero Detect. */
-  DP_NUL( "zero", 8, 0,
-          "data_s[7:0]",
-          "ctrl_zero",
-          EOL );
-
-  /* Register. */
-  DP_PDFF( "memory", 8, 0,
-           "ctrl_wen",
-           "ctrl_ck",
-           "data_s[7:0]",
-           "data_q[7:0]",
-           "data_u[7:0]",  /* This bus is unused. */
-           EOL );
-
-
-
-  /* Terminate the netlist description, and save on disk.
-   * ====================================================
-   */
-  DP_SAVLOFIG();
-
-
-  /* DP_TRACE( TRACE_OFF ); */
-
-
-  /* A good C program must always terminate by an "exit(0)". */
-  exit(0);
-}
diff --git a/alliance/share/tutorials/fitpath/sample_dpt.dpr b/alliance/share/tutorials/fitpath/sample_dpt.dpr
deleted file mode 100644
index a43e6b69..00000000
--- a/alliance/share/tutorials/fitpath/sample_dpt.dpr
+++ /dev/null
@@ -1,27 +0,0 @@
-#
-#
-# /*          Alliance CAD System V.R                                       */
-# /*             FpGen Package V.RR                                         */
-# /*                                                                        */
-# /*  Copyright(c) 93-AA, MASI, CAO-VLSI Team                               */
-# /*                                                                        */
-# /*  Author      :          Jean-Paul CHAPUT                               */
-# /*  E-mail      :      cao-vlsi@masi.ibp.fr                               */
-# /* ====================================================================== */
-# /*  File        :      "sample_dpt.dpr"                                   */
-# /* ********************************************************************** */
-# /*  Data-Path sample example.                                             */
-#
-#
-#           Terminal :  Side  :  Slice  :  Track
-DP_LOCON   ctrl_zero   NORTH    DEFAULT   DEFAULT
-#
-#
-#           Terminal :  Side  :  Slice  :  Track
-DP_LOCON  data_a[7:0]   WEST    DEFAULT   DEFAULT
-DP_LOCON  data_b[7:0]   WEST    DEFAULT   DEFAULT
-DP_LOCON  data_s[7:0]   EAST    DEFAULT   DEFAULT
-#
-#
-# Number of vertical power refreshment.
-DP_POWER  1  50
diff --git a/alliance/share/tutorials/fitpath/sample_dpt.inf b/alliance/share/tutorials/fitpath/sample_dpt.inf
deleted file mode 100644
index 8403b3dd..00000000
--- a/alliance/share/tutorials/fitpath/sample_dpt.inf
+++ /dev/null
@@ -1,4 +0,0 @@
-RENAME
-  memory.pdff_*.memm_s : memory_m(*) ;
-  memory.pdff_*.mems_s : memory_s(*) ;
-END
diff --git a/alliance/share/tutorials/fitpath/sample_dpt.pat b/alliance/share/tutorials/fitpath/sample_dpt.pat
deleted file mode 100644
index 8e5a8ee0..00000000
--- a/alliance/share/tutorials/fitpath/sample_dpt.pat
+++ /dev/null
@@ -1,69 +0,0 @@
--- 
--- 
--- /*          Alliance CAD System V.R                                      */
--- /*             FpGen Package V.RR                                        */
--- /*                                                                       */
--- /*  Copyright(c) 93-AA, MASI, CAO-VLSI Team                              */
--- /*                                                                       */
--- /*  Author      :          Jean-Paul CHAPUT                              */
--- /*  E-mail      :      cao-vlsi@masi.ibp.fr                              */
--- /* ===================================================================== */
--- /*  File        :      "sample_dpt.c"                                    */
--- /* ********************************************************************* */
--- /*  Data-Path sample example.                                            */
--- 
--- 
-
-
-in     ctrl_sel;;
-in     ctrl_ck;
-in     ctrl_wen;;
-  out  ctrl_ncout;
-  out  ctrl_nover;
-  out  ctrl_zero;;
-
-in     data_a(7 downto 0) X;;
-in     data_b(7 downto 0) X;;
-  out  data_s(7 downto 0) X;;
-
-in     vdd;
-in     vss;;
-
-
-BEGIN
-check_adder: 1 00 ?1?1?1 00 00 ?00 10;
-           : 1 00 ?1?1?0 01 00 ?01 10;
-           : 1 00 ?1?1?0 02 00 ?02 10;
-           : 1 00 ?1?1?0 03 00 ?03 10;
-           : 1 00 ?1?1?0 04 00 ?04 10;
-           : 1 00 ?1?1?0 05 00 ?05 10;
-           : 1 00 ?1?1?0 06 00 ?06 10;
-           : 1 00 ?1?1?0 07 00 ?07 10;
-           : 1 00 ?1?1?0 08 00 ?08 10;
-           : 1 00 ?1?1?0 09 00 ?09 10;
-           : 1 00 ?1?1?0 0A 00 ?0A 10;
-           : 1 00 ?1?1?0 0B 00 ?0B 10;
-           : 1 00 ?1?1?0 0C 00 ?0C 10;
-           : 1 00 ?1?1?0 0D 00 ?0D 10;
-           : 1 00 ?1?1?0 0E 00 ?0E 10;
-           : 1 00 ?1?1?0 0F 00 ?0F 10;
-           : 1 00 ?1?1?0 10 00 ?10 10;
-           : 1 00 ?1?1?0 20 00 ?20 10;
-           : 1 00 ?1?1?0 30 00 ?30 10;
-           : 1 00 ?1?1?0 40 00 ?40 10;
-           : 1 00 ?1?1?0 50 00 ?50 10;
-           : 1 00 ?1?1?0 60 00 ?60 10;
-           : 1 00 ?1?1?0 70 00 ?70 10;
-           : 1 00 ?1?1?0 80 00 ?80 10;
-           : 1 00 ?1?1?0 90 00 ?90 10;
-           : 1 00 ?1?1?0 A0 00 ?A0 10;
-           : 1 00 ?1?1?0 B0 00 ?B0 10;
-           : 1 00 ?1?1?0 C0 00 ?C0 10;
-           : 1 00 ?1?1?0 D0 00 ?D0 10;
-           : 1 00 ?1?1?0 E0 00 ?E0 10;
-           : 1 00 ?1?1?0 F0 00 ?F0 10;
-           : 1 00 ?1?1?0 FE 00 ?FE 10;
-           : 1 00 ?1?1?0 FF 00 ?FF 10;
-check_ncout: 1 00 ?0?1?0 FF 80 ?7F 10;
-check_nover: 1 00 ?0?0?0 FF 40 ?3F 10;
-END;
diff --git a/alliance/share/tutorials/fitpath/sample_dpt.sh b/alliance/share/tutorials/fitpath/sample_dpt.sh
deleted file mode 100755
index ffa0187a..00000000
--- a/alliance/share/tutorials/fitpath/sample_dpt.sh
+++ /dev/null
@@ -1,105 +0,0 @@
-#!/bin/sh
-
-
-#
-#
-# /*          Alliance CAD System V.R                                       */
-# /*             FpGen Package V.RR                                         */
-# /*                                                                        */
-# /*  Copyright(c) 93-AA, MASI, CAO-VLSI Team                               */
-# /*                                                                        */
-# /*  Author      :          Jean-Paul CHAPUT                               */
-# /*  E-mail      :      cao-vlsi@masi.ibp.fr                               */
-# /* ====================================================================== */
-# /*  File        :      "sample_dpt.sh"                                    */
-# /* ********************************************************************** */
-# /*  Data-Path sample example.                                             */
-#
-#
-
-
-# Installation Dependent Variables.
-#           ALLIANCE_TOP=/labo
-
-
-# FpGen Macro-Operators Library.
-     FPGEN_LIB=./mclib; export FPGEN_LIB
-
-
-# MBK Enviroment variables settings.
-     MBK_IN_PH=ap;      export MBK_IN_PH
-     MBK_IN_LO=vst;     export MBK_IN_LO
-    MBK_OUT_PH=ap;      export MBK_OUT_PH
-    MBK_OUT_LO=vst;     export MBK_OUT_LO
-  MBK_WORK_LIB=.;       export MBK_WORK_LIB
-  MBK_CATA_LIB=$ALLIANCE_TOP/cells/fitpath/fplib:$ALLIANCE_TOP/cells/rsa:$FPGEN_LIB
-                        export MBK_CATA_LIB
-MBK_CATAL_NAME=MON_CATAL;   export MBK_CATAL_NAME
-       MBK_VDD=vdd;     export MBK_VDD
-       MBK_VSS=vss;     export MBK_VSS
-
-#
-#
-# FpGen : Generation of the Netlist.
-# ==================================
-#
-fpgen -v --dev sample_dpt
-
-
-#
-#
-# DPR : Routing the data-path.
-# ============================
-#
-dpr -V -p -r sample_dpt sample_dpt
-
-
-#
-#
-# DRUC : Symbolic Design RUles Checker.
-# =====================================
-#
-druc sample_dpt
-
-
-#
-#
-# LYNX : Gate level netlist extraction.
-# =====================================
-#
-MBK_OUT_LO=al
- MBK_IN_LO=al
-
-lynx -v -f sample_dpt sample_dpt_gates
-
-
-#
-#
-# LVX : Netlist comparison.
-# =========================
-#
-lvx vst al sample_dpt sample_dpt_gates -f
-
-
-#
-#
-# LYNX : Transistor netlist extraction.
-# =====================================
-#
-lynx -v -t sample_dpt sample_dpt
-
-
-#
-#
-# DESB : Behavioral exctraction.
-# ==============================
-#
-desb sample_dpt sample_dpt_desb -v -i
-
-
-#
-#
-# PROOF : Formal proof.
-# =====================
-#
-proof -d sample_dpt sample_dpt_desb
diff --git a/alliance/share/tutorials/fitpath/sample_dpt.vbe b/alliance/share/tutorials/fitpath/sample_dpt.vbe
deleted file mode 100644
index 1362e11a..00000000
--- a/alliance/share/tutorials/fitpath/sample_dpt.vbe
+++ /dev/null
@@ -1,96 +0,0 @@
-
-
--- ###---------------------------------------------------------------------###
--- #                                                                         #
--- #          Alliance CAD System V.R                                        #
--- #             FpGen Package V.RR                                          #
--- #                                                                         #
--- #  Copyright(c) 93-AA, MASI, CAO-VLSI Team                                #
--- #                                                                         #
--- #  Author      :          Jean-Paul CHAPUT                                #
--- #  E-mail      :      cao-vlsi@masi.ibp.fr                                #
--- # ======================================================================= #
--- #  File        :      "sample_dpt.vbe"                                    #
--- # *********************************************************************** #
--- #  Data-Path sample example.                                              #
--- #                                                                         #
--- ###---------------------------------------------------------------------###
-
-
-ENTITY  sample_dpt  IS
-  PORT(
-      -- Control terminals declarations.
-      ctrl_sel   : in    BIT;
-      ctrl_ck    : in    BIT;
-      ctrl_wen   : in    BIT;
-      ctrl_ncout :   out BIT;
-      ctrl_nover :   out BIT;
-      ctrl_zero  :   out BIT;
-
-      -- Data terminals declarations.
-      data_a : in    BIT_VECTOR(7 downto 0);
-      data_b : in    BIT_VECTOR(7 downto 0);
-      data_s : inout BIT_VECTOR(7 downto 0);
-
-      -- Power supplies terminals.
-      vdd : in    BIT;
-      vss : in    BIT
-      );
-END  sample_dpt;
-
-
-ARCHITECTURE  behavior_data_flow  OF  sample_dpt  IS
-
-	SIGNAL wmd      : BIT;
-	SIGNAL ws       : BIT;
-
-	SIGNAL memory_m : REG_VECTOR(7 downto 0) REGISTER;
-	SIGNAL memory_s : REG_VECTOR(7 downto 0) REGISTER;
-
-	SIGNAL cry      : BIT_VECTOR(8 downto 0);
-	SIGNAL dwen     : BIT_VECTOR(7 downto 0);
-	SIGNAL data_m   : BIT_VECTOR(7 downto 0);
-	SIGNAL data_q   : BIT_VECTOR(7 downto 0);
-
-BEGIN
-  -- Multiplexer (related to DP_MUX2CS).
-  WITH  ctrl_sel  SELECT
-    data_m <= data_b  WHEN '1',
-              data_q  WHEN '0';
-
-
-  -- Fast Adder (related to ADD2F).
-  cry(0) <= '0';
-  cry(8 downto 1) <=    (data_m and data_a)
-                     or (data_m and cry(7 downto 0))
-                     or (data_a and cry(7 downto 0));
-
-  data_s     <= data_m xor data_a xor cry(7 downto 0);
-  ctrl_nover <= not cry(7);
-  ctrl_ncout <= not cry(8);
-
-
-  -- Zero Detect (related to DP_NUL).
-  WITH  data_s  SELECT
-    ctrl_zero <= '1' WHEN  B"00000000",
-                 '0' WHEN  OTHERS;
-
-
-  -- Register (related to DP_PDFF).
-  wmd <=     ctrl_ck;
-  ws  <= not ctrl_ck;
-
-  WITH ctrl_wen SELECT
-    dwen <= data_s WHEN '1',
-            data_q WHEN '0'; 
-
-  wmd:BLOCK( wmd ) BEGIN memory_m <= GUARDED not dwen; END BLOCK wmd;
-  ws :BLOCK( ws  ) BEGIN memory_s <= GUARDED memory_m; END BLOCK ws;
-
-  data_q <= not memory_s;
-
-
-  ASSERT((vdd = '1') and (vss = '0'))
-    REPORT "Power supply is missing on sample_dpt"
-    SEVERITY WARNING;
-END  behavior_data_flow;
diff --git a/alliance/share/tutorials/fitpath/sample_dpt.vbe.old b/alliance/share/tutorials/fitpath/sample_dpt.vbe.old
deleted file mode 100644
index c0887f03..00000000
--- a/alliance/share/tutorials/fitpath/sample_dpt.vbe.old
+++ /dev/null
@@ -1,96 +0,0 @@
-
-
--- ###---------------------------------------------------------------------###
--- #                                                                         #
--- #          Alliance CAD System V.R                                        #
--- #             FpGen Package V.RR                                          #
--- #                                                                         #
--- #  Copyright(c) 93-AA, MASI, CAO-VLSI Team                                #
--- #                                                                         #
--- #  Author      :          Jean-Paul CHAPUT                                #
--- #  E-mail      :      cao-vlsi@masi.ibp.fr                                #
--- # ======================================================================= #
--- #  File        :      "sample_dpt.vbe"                                    #
--- # *********************************************************************** #
--- #  Data-Path sample example.                                              #
--- #                                                                         #
--- ###---------------------------------------------------------------------###
-
-
-ENTITY  sample_dpt  IS
-  PORT(
-      -- Control terminals declarations.
-      ctrl_sel   : in    BIT;
-      ctrl_ck    : in    BIT;
-      ctrl_wen   : in    BIT;
-      ctrl_ncout :   out BIT;
-      ctrl_nover :   out BIT;
-      ctrl_zero  :   out BIT;
-
-      -- Data terminals declarations.
-      data_a : in    BIT_VECTOR(7 downto 0);
-      data_b : in    BIT_VECTOR(7 downto 0);
-      data_s : inout BIT_VECTOR(7 downto 0);
-
-      -- Power supplies terminals.
-      vdd : in    BIT;
-      vss : in    BIT
-      );
-END  sample_dpt;
-
-
-ARCHITECTURE  behavior_data_flow  OF  sample_dpt  IS
-
-	SIGNAL wmd      : BIT;
-	SIGNAL ws       : BIT;
-
-	SIGNAL memory_m : REG_VECTOR(7 downto 0) REGISTER;
-	SIGNAL memory_s : REG_VECTOR(7 downto 0) REGISTER;
-
-	SIGNAL cry      : BIT_VECTOR(8 downto 0);
-	SIGNAL dwen     : BIT_VECTOR(7 downto 0);
-	SIGNAL data_m   : BIT_VECTOR(7 downto 0);
-	SIGNAL data_q   : BIT_VECTOR(7 downto 0);
-
-BEGIN
-  -- Multiplexer (related to DP_MUX2CS).
-  WITH  ctrl_sel  SELECT
-    data_m <= data_b  WHEN '1',
-              data_q  WHEN '0';
-
-
-  -- Fast Adder (related to ADD2F).
-  cry(0) <= '0';
-  cry(8 downto 1) <=    (data_m and data_a)
-                     or (data_m and cry(7 downto 0))
-                     or (data_a and cry(7 downto 0));
-
-  data_s     <= data_m xor data_a xor cry(7 downto 0);
-  ctrl_nover <= not cry(7);
-  ctrl_ncout <= not cry(8);
-
-
-  -- Zero Detect (related to DP_NUL).
-  WITH  data_s  SELECT
-    ctrl_zero <= '1' WHEN  B"00000000",
-                 '0' WHEN  OTHERS;
-
-
-  -- Register (related to DP_PDFF).
-  wmd <=   not (not (ctrl_ck) or not (ctrl_wen))  ;
-  ws  <= not ctrl_ck;
-
-  WITH ctrl_wen SELECT
-    dwen <= data_s WHEN '1',
-            data_q WHEN '0'; 
-
-  wmd:BLOCK( wmd ) BEGIN memory_m <= GUARDED not data_s; END BLOCK wmd;
-  ws :BLOCK( ws  ) BEGIN memory_s <= GUARDED memory_m; END BLOCK ws;
-
-  data_q <= not memory_s;
-
-
-  ASSERT((vdd = '1') and (vss = '0'))
-    REPORT "Power supply is missing on sample_dpt"
-    SEVERITY WARNING;
-END  behavior_data_flow;
diff --git a/alliance/share/tutorials/fitpath/synthesis_dpt.c b/alliance/share/tutorials/fitpath/synthesis_dpt.c
deleted file mode 100644
index 34702329..00000000
--- a/alliance/share/tutorials/fitpath/synthesis_dpt.c
+++ /dev/null
@@ -1,100 +0,0 @@
-
-
-/*          Alliance CAD System V.R                                         */
-/*             FpGen Package V.RR                                           */
-/*                                                                          */
-/*  Copyright(c) 93-AA, MASI, CAO-VLSI Team                                 */
-/*                                                                          */
-/*  Author      :          Jean-Paul CHAPUT                                 */
-/*  E-mail      :      cao-vlsi@masi.ibp.fr                                 */
-/* ======================================================================== */
-/*  File        :      "synthesis_dpt.c"                                    */
-/* ************************************************************************ */
-/*  Example of synthesis inside a Data-Path.                                */
-
-
-#include  <genlib.h>
-#include  <fpgen.h>
-
-
-main()
-{
-  /* Open a new Data-Path figure.
-   * ============================
-   */
-  DP_DEFLOFIG( "synthesis_dpt", 8, LSB_INDEX_ZERO );
-
-
-  /* Interface description.
-   * ======================
-   */
-
-  /* Control terminals declarations. */
-  DP_LOCON( "ctrl_sel"  , IN   , "ctrl_sel"   );
-  DP_LOCON( "ctrl_ck"   , IN   , "ctrl_ck"    );
-  DP_LOCON( "ctrl_wen"  , IN   , "ctrl_wen"   );
-  DP_LOCON( "ctrl_ncout",   OUT, "ctrl_ncout" );
-  DP_LOCON( "ctrl_nover",   OUT, "ctrl_nover" );
-  DP_LOCON( "ctrl_zero" ,   OUT, "ctrl_zero"  );
-
-  /* Data terminals declarations. */
-  DP_LOCON( "data_a[7:0]" , IN   , "data_a[7:0]" );
-  DP_LOCON( "data_b[7:0]" , IN   , "data_b[7:0]" );
-  DP_LOCON( "data_s[7:0]" , INOUT, "data_s[7:0]" );
-
-  /* Power supplies terminals. */
-  DP_LOCON( "vdd", IN   , "vdd" );
-  DP_LOCON( "vss", IN   , "vss" );
-
-
-  /* Data-Path netlist description.
-   * ==============================
-   */
-
-  DP_TRACE( TRACE_ON );
-
-  /* Multiplexer. */
-  DP_MUX2CS( "multiplexer", 8, 0,
-             "ctrl_sel",
-             "data_b[7:0]",
-             "data_q[7:0]",
-             "data_m[7:0]",
-             EOL );
-
-  /* Synthetized Adder. */
-  DP_IMPORT( "adder_us",
-             "adder",
-             "data_a[7:0]",
-             "data_m[7:0]",
-             "ctrl_ncout",
-             "ctrl_nover",
-             "data_s[7:0]",
-             EOL );
-
-  /* Zero Detect. */
-  DP_NUL( "zero", 8, 0,
-          "data_s[7:0]",
-          "ctrl_zero",
-          EOL );
-
-  /* Register. */
-  DP_PDFF( "memory", 8, 0,
-           "ctrl_wen",
-           "ctrl_ck",
-           "data_s[7:0]",
-           "data_q[7:0]",
-           "data_u[7:0]",  /* This bus is unused. */
-           EOL );
-
-
-  DP_TRACE( TRACE_OFF );
-
-  /* Terminate the netlist description, and save on disk.
-   * ====================================================
-   */
-  DP_SAVLOFIG();
-
-
-  /* A good C program must always terminate by an "exit(0)". */
-  exit(0);
-}
diff --git a/alliance/share/tutorials/fitpath/synthesis_dpt.dpr b/alliance/share/tutorials/fitpath/synthesis_dpt.dpr
deleted file mode 100644
index 8306969e..00000000
--- a/alliance/share/tutorials/fitpath/synthesis_dpt.dpr
+++ /dev/null
@@ -1,33 +0,0 @@
-#
-#
-# /*          Alliance CAD System V.R                                       */
-# /*             FpGen Package V.RR                                         */
-# /*                                                                        */
-# /*  Copyright(c) 93-AA, MASI, CAO-VLSI Team                               */
-# /*                                                                        */
-# /*  Author      :          Jean-Paul CHAPUT                               */
-# /*  E-mail      :      cao-vlsi@masi.ibp.fr                               */
-# /* ====================================================================== */
-# /*  File        :      "synthesis_dpt.dpr"                                */
-# /* ********************************************************************** */
-# /*  Data-Path sample example.                                             */
-#
-#
-#           Terminal :  Side  :  Slice  :  Track
-DP_LOCON   ctrl_zero   NORTH    DEFAULT   DEFAULT
-DP_LOCON   ctrl_ncout  NORTH    DEFAULT   DEFAULT
-DP_LOCON   ctrl_nover  NORTH    DEFAULT   DEFAULT
-#
-#
-#           Terminal :  Side  :  Slice  :  Track
-DP_LOCON  data_a[7:0]   WEST    DEFAULT   DEFAULT
-DP_LOCON  data_b[7:0]   WEST    DEFAULT   DEFAULT
-DP_LOCON  data_s[7:0]   EAST    DEFAULT   DEFAULT
-#
-#
-#         Model Name : Iterations : Height : CPC
-DP_GLUE    adder_us       5000         8      2
-#
-#
-# Number and wide of vertical power refreshment.
-DP_POWER  1  50
diff --git a/alliance/share/tutorials/fitpath/synthesis_dpt.inf b/alliance/share/tutorials/fitpath/synthesis_dpt.inf
deleted file mode 100644
index 8403b3dd..00000000
--- a/alliance/share/tutorials/fitpath/synthesis_dpt.inf
+++ /dev/null
@@ -1,4 +0,0 @@
-RENAME
-  memory.pdff_*.memm_s : memory_m(*) ;
-  memory.pdff_*.mems_s : memory_s(*) ;
-END
diff --git a/alliance/share/tutorials/fitpath/synthesis_dpt.sh b/alliance/share/tutorials/fitpath/synthesis_dpt.sh
deleted file mode 100755
index 740b7c94..00000000
--- a/alliance/share/tutorials/fitpath/synthesis_dpt.sh
+++ /dev/null
@@ -1,124 +0,0 @@
-#!/bin/sh
-
-
-#
-#
-# /*          Alliance CAD System V.R                                       */
-# /*             FpGen Package V.RR                                         */
-# /*                                                                        */
-# /*  Copyright(c) 93-AA, MASI, CAO-VLSI Team                               */
-# /*                                                                        */
-# /*  Author      :          Jean-Paul CHAPUT                               */
-# /*  E-mail      :      cao-vlsi@masi.ibp.fr                               */
-# /* ====================================================================== */
-# /*  File        :      "synthesis_dpt.sh"                                 */
-# /* ********************************************************************** */
-# /*  Data-Path using synthetized block example.                            */
-#
-#
-
-
-# Installation Dependent Variables.
-           ALLIANCE_TOP=/labo
-
-# FpGen Macro-Operators Library.
-     FPGEN_LIB=./mclib; export FPGEN_LIB
-
-# MBK Enviroment Variables Settings.
-     MBK_IN_PH=cp;      export MBK_IN_PH
-     MBK_IN_LO=hns;     export MBK_IN_LO
-    MBK_OUT_PH=cp;      export MBK_OUT_PH
-    MBK_OUT_LO=hns;     export MBK_OUT_LO
-  MBK_WORK_LIB=.;       export MBK_WORK_LIB
-  MBK_CATA_LIB=$FPGEN_LIB
-  MBK_CATA_LIB=$MBK_CATA_LIB:$ALLIANCE_TOP/cells/fitpath/fplib
-  MBK_CATA_LIB=$MBK_CATA_LIB:$ALLIANCE_TOP/cells/fitpath/dplib
-                        export MBK_CATA_LIB
-MBK_CATAL_NAME=CATAL;   export MBK_CATAL_NAME
-       MBK_VDD=vdd;     export MBK_VDD
-       MBK_VSS=vss;     export MBK_VSS
-
-# LOGIC Environment Variables.
-MBK_TARGET_LIB=$ALLIANCE_TOP/cells/fitpath/dplib
-                        export MBK_TARGET_LIB
-  MBK_NAME_LOG="";      export MBK_NAME_LOG
-
-
-#
-#
-# Logic : Synthesis of the Adder.
-# ===============================
-# Two steps :
-#     1) Optimise data-flow equations.
-#     2) Synthesis, using TARGET library.
-#
-logic -o adder_us     adder_us_opt
-logic -s adder_us_opt adder_us
-
-
-#
-#
-# FpGen : Generation of the Netlist.
-# ==================================
-#
-fpgen --dev -v synthesis_dpt
-
-
-#
-#
-# DPR : Routing the data-path.
-# ============================
-#
-dpr -V -p -r synthesis_dpt synthesis_dpt
-
-
-#
-#
-# DRUC : Symbolic Design RUles Checker.
-# =====================================
-#
-druc synthesis_dpt
-
-
-
-#
-#
-# LYNX : Gate level netlist extraction.
-# =====================================
-#
-MBK_OUT_LO=al
- MBK_IN_LO=al
-
-lynx -v -f synthesis_dpt synthesis_dpt_gates
-
-
-#
-#
-# LVX : Netlist comparison.
-# =========================
-#
-lvx hns al synthesis_dpt synthesis_dpt_gates -f
-
-
-#
-#
-# LYNX : Transistor netlist extraction.
-# =====================================
-#
-lynx -v -t synthesis_dpt synthesis_dpt
-
-
-#
-#
-# DESB : Behavioral exctraction.
-# ==============================
-#
-desb synthesis_dpt synthesis_dpt_desb -v -i
-
-
-#
-#
-# PROOF : Formal proof.
-# =====================
-#
-proof -d sample_dpt synthesis_dpt_desb
diff --git a/alliance/share/tutorials/fitpath/tex/Makefile b/alliance/share/tutorials/fitpath/tex/Makefile
deleted file mode 100644
index b1877d39..00000000
--- a/alliance/share/tutorials/fitpath/tex/Makefile
+++ /dev/null
@@ -1,50 +0,0 @@
-# Generic Makefile for TeTeX projet
-# (C) 1999, Czo
-# $Id: Makefile,v 1.1 2000/01/20 15:19:50 czo Exp $
-
-
-EPSS =  sample_dpt-1.eps \
-	sample_dpt-2.eps \
-	sample_dpt-3.eps \
-	sample_dpt-4.eps \
-	sample_dpt-5.eps \
-	sample_dpt-6.eps \
-	usercol_dpt-2.eps \
-	hierarchy_dpt-1.eps
-
-MYFILE=fitpath
-
-%.eps : %.fig
-	fig2dev -L ps -c -p dummy $*.fig $*.eps
-
-
-%.dvi : %.tex 
-	latex $*.tex
-
-
-%.ps : %.dvi 
-	dvips -o $*.ps $*.dvi
-
-
-
-view : ps
-	gv $(MYFILE).ps
-        
-ps   : $(MYFILE).tex $(EPSS)
-	latex $(MYFILE).tex
-	dvips $(MYFILE).dvi -o $(MYFILE).ps
-
-distrib : clean ps        
-	ps2pdf $(MYFILE).ps
-	cp -f $(MYFILE).ps ..
-	cp -f $(MYFILE).pdf ..
-	$(MAKE) clean
-
-clean :
-	rm -f $(MYFILE).ps $(MYFILE).pdf *.log *.lof *.dvi *.aux *.toc *.eps
-
-
-
-all: fitpath.ps
-
-
diff --git a/alliance/share/tutorials/fitpath/tex/fitpath.tex b/alliance/share/tutorials/fitpath/tex/fitpath.tex
deleted file mode 100644
index 6dfcea93..00000000
--- a/alliance/share/tutorials/fitpath/tex/fitpath.tex
+++ /dev/null
@@ -1,1410 +0,0 @@
-%%%%%%%%%%%%%%%%%%%%
-%
-% Data-Path tutorial.
-% Author : Jean-Paul CHAPUT
-% Modified by czo for Alliance release 4.0 (01/2000)
-% TODO : no fully working, needs some adjustements
-% $Id: fitpath.tex,v 1.1 2000/01/20 15:19:51 czo Exp $
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-
-\documentstyle[epsf,a4,here]{article}
-%\documentstyle[epsf,a4]{article}
-%
-%
-% New Variables.
-%
-\def\at{\string @}
-\newlength{\sizeindentation}
-\setlength{\sizeindentation}{1cm}
-%
-%
-% Predefined Variables.
-%
-\setlength{\marginparwidth}{0cm}
-\setlength{\marginparsep}{0cm}
-\setlength{\oddsidemargin}{0.5cm}
-\setlength{\evensidemargin}{0.5cm}
-\setlength{\textwidth}{14.92cm}
-\setlength{\parindent}{\sizeindentation}
-%
-%
-% New Macros.
-%
-\newcommand{\doubleindent}{\indent\indent}
-\newcommand{\forceindent}{\hspace*{\sizeindentation}}
-%
-%
-% Predefined Words and Sentences.
-%
-\newcommand                {\C} {{\bf C}}
-\newcommand           {\column} {{\bf column}}
-\newcommand         {\operator} {{\bf operator}}
-\newcommand        {\operators} {{\bf operators}}
-\newcommand              {\dpr} {{\bf DPR}}
-\newcommand              {\lvx} {{\bf LVX}}
-\newcommand             {\lynx} {{\bf Lynx}}
-\newcommand             {\desb} {{\bf desb}}
-\newcommand             {\druc} {{\bf DRuC}}
-\newcommand            {\logic} {{\bf Logic}}
-\newcommand            {\proof} {{\bf proof}}
-\newcommand            {\fpgen} {{\bf FpGen}}
-\newcommand           {\genlib} {{\bf GenLib}}
-\newcommand           {\asimut} {{\bf ASimuT}}
-\newcommand         {\alliance} {{\bf Alliance}}
-\newcommand            {\dplib} {{\bf DPLib}}
-\newcommand            {\sclib} {{\bf SCLib}}
-\newcommand             {\EAST} {{\bf East}}
-\newcommand             {\WEST} {{\bf West}}
-\newcommand            {\NORTH} {{\bf North}}
-\newcommand          {\addaccu} {{\tt addaccu}}
-\newcommand              {\fal} {{\tt .al}}
-\newcommand             {\fvst} {{\tt .vst}}
-\newcommand          {\dprfile} {{\tt .dpr}}
-\newcommand         {\desbfile} {{\tt .inf}}
-\newcommand        {\sampledpt} {{\tt sample\_dpt}}
-\newcommand  {\sampledptsource} {{\tt sample\_dpt.c}}
-\newcommand         {\fpgenlib} {{\tt FPGEN\_LIB}}
-\newcommand       {\mbkcatalib} {{\tt MBK\_CATA\_LIB}}
-\newcommand         {\dpaddiif} {{\tt DP\_ADD2F}}
-\newcommand         {\DPADDIIF} {{\tt DP\_ADD2F}}
-\newcommand        {\DPMUXIICS} {{\tt DP\_MUX2CS}}
-\newcommand            {\DPNUL} {{\tt DP\_NUL}}
-\newcommand           {\DPPDFF} {{\tt DP\_PDFF}}
-\newcommand         {\DPIMPORT} {{\tt DP\_IMPORT}}
-\newcommand       {\DPDEFLOFIG} {{\tt DP\_DEFLOFIG}}
-\newcommand       {\DPSAVLOFIG} {{\tt DP\_SAVLOFIG}}
-\newcommand          {\netlist} {{\it netlist\,}}
-\newcommand           {\layout} {{\it layout\,}}
-\newcommand   {\layoutsymbolic} {{\it symbolic layout\,}}
-\newcommand         {\symbolic} {{\it symbolic\,}}
-\newcommand       {\behavioral} {{\it behavioral\,}}
-\newcommand     {\standartcell} {{\it Standart Cell\,}}
-\newcommand              {\drc} {{\it DRC\,}}
-\newcommand         {\datapath} {{\it data-path\,}}
-\newcommand        {\datapaths} {{\it data-paths\,}}
-\newcommand        {\gluelogic} {{\it glue logic\,}}
-\newcommand     {\datapathcomp} {{\it data-path compiler\,}}
-\newcommand            {\slice} {{\it slice\,}}
-\newcommand           {\slices} {{\it slices\,}}
-\newcommand            {\track} {{\it track\,}}
-\newcommand           {\tracks} {{\it tracks\,}}
-\newcommand            {\Width} {{\it Width\,}}
-\newcommand            {\Slice} {{\it Slice\,}}
-\newcommand      {\bourneshell} {{\it Bourne Shell\,}}
-%
-%
-% **************************** Corps du Document *****************************
-%
- \begin{document}
- \sloppy %\flushbottom
-  %
-  %
-  % ******************************** Title ********************************
-  %
-   \begin{titlepage}
-   {
-     \begin{center}
-       {\LARGE {\bf Alliance} {\sc CAD} System {\bf V.R}}\\*[0.3cm]
-       {\LARGE e-mail: {\tt cao-vlsi{\at}masi.ibp.fr}}\\*[8cm]
-       {\Huge Tutorial for the}\\*[0.4cm]
-       {\Huge Data-Path Compiler}\\*[8cm]
-       {\Large Jean-Paul C\sc{haput}}\\*[0.2cm]
-       {\Large February 24, 1995}
-     \end{center}
-   }
-   \end{titlepage}
-  %
-  %
-  % ************************* Table des Matieres **************************
-  %
-   \tableofcontents
-   \vfill
-   \listoffigures
-   \newpage
-  %
-  %
-  % **************************** Introduction *****************************
-  %
-   \section{Introduction}
-   \forceindent
-     This tutorial aims at teaching how to use \alliance\ {\sc CAD} tools
-   dedicated to the design of \datapaths. These tools are the followings~:
-   \begin{description}
-     \item[\fpgen]
-       : \netlist\ capture using textual mode, thanks to a
-       set of predefined \C\ functions.
-     \item[\dpr]
-       : Placer/Router associated with the \datapaths.
-   \end{description}
-   \forceindent
-     From this point on, the environment variable {\bf ALLIANCE\_TOP} represents the root
-   directory where the \alliance\ package is located.
-  %
-  %
-  % ************************** Premiere Partie ****************************
-  %
-   \section{{\it Data-Path}\ basics}
-  %
-  %
-  %  Data-Path Structure
-  % =====================
-  %
-   \subsection{Structure of a \datapath}
-   \forceindent
-     \datapathcomp\ are tools which are dedicated to the design of
-   microproccessor operative units. Inside a \datapath\ the basic
-   concept is no more the scalar cell (on 1 bit), but the \operator\
-   carrying out a vectorial treatment (on {\bf n bits}).\\
-   \indent
-     From a logical point of view, an \operator\ is made of a repetition
-   of {\bf n} cells more or less identical, each of those executing a one
-   bit treatment. It may also contain a cell dedicated to the amplification
-   of control signals. Physically, each cell is stacked vertically and
-   fill one \slice. The last two \slices are reserved to an amplification
-   cell, if needed. It can be talked about either \operator\ or \column,
-   this last term receiving a physical acceptance.\\
-   \indent
-     A \datapath\ is made of \operators\ stacked horizontally. It can be
-   represented as a bidimentionnal table in which columns are called
-   \operators\ and rows \slices.\\
-   \indent
-     Figure~\ref{schemadatapath} shows \datapaths\ structure.
-   \begin{figure}[hbtp]
-     \begin{center}
-       \leavevmode\epsfxsize.99\textwidth\epsffile{./sample_dpt-4.eps}
-     \end{center}
-     \caption{
-       \label{schemadatapath}
-       {\it \datapaths\ structure.}}
-   \end{figure}
-  %
-  %
-  %  Controls and Data Signals 
-  % ===========================
-  %
-   \subsection{Controls and datas signals}
-   \label{refctrldataterm}
-   \forceindent
-     In a \datapath, signals associated with \operator\ input/output buses
-   are called {\it datas} signals. They propagate horizontally through the
-   \datapath.\\
-   \indent
-     On the contrary, {\it control} signals are signals which command the
-   \operators, for instance, the bus select of a multiplexer ({\it ctrl\_sel}
-   of operator \DPMUXIICS). They propagate vertically inside a column.\\
-   \indent
-     Figure~\ref{ctrldata} shows the difference between {\it control terminals}
-   and {\it data terminals}.
-   \begin{figure}[H]
-     \begin{center}
-       \leavevmode\epsfxsize.6\textwidth\epsffile{./sample_dpt-6.eps}
-     \end{center}
-     \caption{
-       \label{ctrldata}
-       {\it Data terminals and control terminals.}}
-   \end{figure}
-   \indent
-     Data signals are routed horizontally, over \slices, thanks to 10
-   routing \tracks\ ({\tt cf} figure~\ref{schemadatapath}).
-   \\*[\bigskipamount]
-   {\bf Remark~:}\\*[\bigskipamount]
-   \indent
-     Only data terminals can be set on any side of the \datapath, using the
-   \dprfile\ file. Control terminals always appear on the \NORTH\ side of
-   the \datapath, at a predefined place.\\
-   \forceindent
-     Data terminals sets on the \NORTH\ side of the \datapath\ are also called
-   {\it Pseudo control terminals}.
-  %
-  %
-  %  structural Parameters Width and Slices
-  % ========================================
-  %
-   \subsection{Structural Parameters \Width\ and \Slice}
-   \begin{minipage}[t]{\textwidth}
-     \forceindent
-       In some cases we only wish to perform a treatment on a part of data
-     bus. We have to use a smaller scaled \operator\ in which empty \slices\
-     are to be found. In order to place cells inside the \column, we need
-     two values~:
-     \begin{tabbing}
-       \hspace{\sizeindentation} \= %
-       \hspace{1.5cm}      \= %
-       \hspace{0.4cm}      \= \kill
-       \> \Slice \> : \> The \slice\ were the first cell is put in the
-                         \column.\\
-       \> \Width \> : \> Effective width of the \operator.
-     \end{tabbing}
-    %\bigskip
-     Default values~:
-     \begin{tabbing}
-       \hspace{\sizeindentation} \= %
-       \hspace{2.5cm}      \= %
-       \hspace{0.4cm}      \= \kill
-       \> {\tt DEFAULT\_SLICE} \> : \> Null.\\
-       \> {\tt DEFAULT\_WIDTH} \> : \> Full width of the \datapath.\\
-       \> \> \> (set by the former \DPDEFLOFIG\ function call).
-     \end{tabbing}
-   \end{minipage}
-   \begin{figure}[H]
-     \begin{center}
-       \leavevmode\epsfysize.9\textwidth\epsffile{./sample_dpt-5.eps}
-     \end{center}
-     \nopagebreak
-     \caption{
-       \label{paramstruct}
-       {\it Structural parameters \Width\ and \Slice.}}
-   \end{figure}
-  %
-  %
-  % ************************** Deuxieme Partie ****************************
-  %
-   \section{First example~: \sampledpt}
-  %
-  %
-  %  Example Presentation
-  % ======================
-  %
-   \subsection{Presentation of the adder accumulator}
-   \forceindent
-     The given example in the \datapath\ tutorial is driven from the adder
-   accumulator showed in the \addaccu\ tutorial.\\*[\bigskipamount]
-   \forceindent
-     Differences from \addaccu\ tutorial~:
-   \begin{enumerate}
-     \samepage
-     \item
-       Data buses width are set from 4 to 8 bits.
-     \item
-       In order to show some special features of the \datapathcomp, a zero
-       detect has been implemented.
-     \item
-       The operator implementing sample register elements (\DPPDFF)
-       obligatory provide a {\it Write ENable} terminal and dual outputs
-       {\it q} and {\it nq}. So we add a {\it ctrl\_wen} terminal to the
-       circuit interface and a unused {\it data\_u} signal which doesn't
-       appear on the interface (for {\it nq}).
-     \item
-       As the former operator, the fast adder generator (\DPADDIIF)
-       obligatory provide {\it ncout} and {\it nover} outputs.
-   \end{enumerate}
-   \nopagebreak
-     Figure~\ref{schemasample} shows the whole architecture of the adder
-   accumulator.
-   \begin{figure}[H]
-     \vspace*{0.5cm}
-     \begin{center}
-       \leavevmode\epsfxsize.9\textwidth\epsffile{./sample_dpt-1.eps}
-     \end{center}
-     \nopagebreak
-     \caption{
-       \label{schemasample}
-       {\it Architecture of the adder accumulator.}}
-   \end{figure}
-  %
-  %
-  %  Simplificated Methodology
-  % ===========================
-  %
-   \subsection{Methodology}
-   \forceindent
-     As we wish not to present the whole design methodology of a circuit but
-   only the part related to \datapath, only a partial validation will be
-   given.\\
-   \nopagebreak
-   \indent
-     Figure~\ref{methosample}\ describe the partial methodology.\\
-   \begin{figure}[hbtp]
-     \begin{center}
-       \leavevmode\epsfysize.90\textheight\epsffile{./sample_dpt-3.eps}
-     \end{center}
-     \nopagebreak
-     \caption{
-       \label{methosample}
-       {\it Partial methodology of validation.}}
-   \end{figure}
-  %
-  %
-  %  Environment Set-Up
-  % ====================
-  %
-   \subsection{Environment set-up}
-   \forceindent
-     Before running any tool of the \alliance\ CAD system, some environment
-   variables must be set up\footnote{
-     Commands are given in \bourneshell.
-     }.
-   \begin{enumerate}
-     \item Input/output formats~:\\
-       \fbox{ \shortstack[l]{
-         \hspace*{13cm} \\
-         {\tt \$ MBK\_IN\_LO=vst} \\
-         {\tt \$ MBK\_OUT\_LO=vst} \\
-         {\tt \$ MBK\_IN\_PH=ap} \\
-         {\tt \$ MBK\_OUT\_PH=ap} \\
-         {\tt \$ export MBK\_IN\_LO MBK\_OUT\_LO MBK\_IN\_PH MBK\_OUT\_PH}
-       }}
-     \item Working directories~:\\
-       \fbox{ \shortstack[l]{
-         \hspace*{13cm} \\
-         {\tt \$ MBK\_WORK\_LIB=.} \\
-         {\tt \$ FPGEN\_LIB=./mclib} \\
-         {\tt \$ export MBK\_WORK\_LIB FPGEN\_LIB}
-       }}
-     \item Cell library paths~:\\
-       \fbox{ \shortstack[l]{
-         \hspace*{13cm} \\
-         {\tt \$ MBK\_CATA\_LIB=\$ALLIANCE\_TOP/cells/fitpath/fplib:\$ALLIANCE\_TOP/cells/rsa:\$FPGEN\_LIB} \\
-         {\tt \$ export MBK\_CATA\_LIB}
-       }}
-   \end{enumerate}
-  %
-  %
-  %  FpGen : Netlist Capture, Using Textual Mode
-  % =============================================
-  %
-   \subsection{FpGen : \netlist\ capture}
-       The \datapath\ \netlist\ is described thanks to a \C\ source file
-     which must contain the following sections~:
-     \begin{enumerate}
-       \Roman{enumi}
-       \setlength{\itemsep}{0cm}
-       \samepage
-       \item Header files to include~:
-       { \tt \begin{verbatim}
-#include  <genlib.h>
-#include  <fpgen.h>
-       \end{verbatim} \rm }
-       \pagebreak[1]
-       \item Opening the \datapath\ model (\netlist)~:
-       { \tt \begin{verbatim}
-main()
-{
-  DP_DEFLOFIG( "sample_dpt", 8, LSB_INDEX_ZERO );
-       \end{verbatim} \rm }
-       \DPDEFLOFIG\ parameters:
-       \begin{tabbing}
-         \hspace{\sizeindentation} \= %
-         \hspace{2.5cm}            \= %
-         \hspace{0.4cm}            \= \kill
-         \> {\tt "sample\_dpt"} \> : \> {\bf model name} of the \datapath.\\
-         \> {\tt 8} \> : \>  \datapath\ bus wide.\\
-         \> {\tt LSB\_INDEX\_ZERO} \> : \> Always set to this value.\\
-       \end{tabbing}
-       \pagebreak[1]
-       \item Terminal declarations~:
-       { \tt \begin{verbatim}
-  /* Control terminals declarations. */
-  DP_LOCON( "ctrl_sel"  , IN   , "ctrl_sel"   );
-  DP_LOCON( "ctrl_ck"   , IN   , "ctrl_ck"    );
-  DP_LOCON( "ctrl_wen"  , IN   , "ctrl_wen"   );
-  DP_LOCON( "ctrl_ncout",   OUT, "ctrl_ncout" );
-  DP_LOCON( "ctrl_nover",   OUT, "ctrl_nover" );
-  DP_LOCON( "ctrl_zero" ,   OUT, "ctrl_zero"  );
-
-  /* Data terminals declarations. */
-  DP_LOCON( "data_a[7:0]" , IN   , "data_a[7:0]" );
-  DP_LOCON( "data_b[7:0]" , IN   , "data_b[7:0]" );
-  DP_LOCON( "data_s[7:0]" , INOUT, "data_s[7:0]" );
-
-  /* Power supplies terminals. */
-  DP_LOCON( "vdd", IN   , "vdd" );
-  DP_LOCON( "vss", IN   , "vss" );
-       \end{verbatim} \rm }
-       \forceindent
-         The first string is associated to a terminal model name and the
-       second to the internal signal name to which it is connected. The
-       behavior of this function is similar to the {\tt LOCON} of \genlib.
-       \pagebreak[1]
-       \item Instanciation of the various \datapath\ \operators~:
-       { \tt \begin{verbatim}
-  /* Multiplexer. */
-  DP_MUX2CS( "multiplexer", 8, 0,
-             "ctrl_sel",
-             "data_b[7:0]",
-             "data_q[7:0]",
-             "data_m[7:0]",
-             EOL );
-
-  /* Fast Adder. */
-  DP_ADD2F( "adder",
-            "data_a[7:0]",
-            "data_m[7:0]",
-            "ctrl_ncout",
-            "ctrl_nover",
-            "data_s[7:0]",
-            EOL );
-
-  /* Zero Detect. */
-  DP_NUL( "zero", 8, 0,
-          "data_s[7:0]",
-          "ctrl_zero",
-          EOL );
-
-  /* Register. */
-  DP_PDFF( "memory", 8, 0,
-           "ctrl_wen",
-           "ctrl_ck",
-           "data_s[7:0]",
-           "data_q[7:0]",
-           "data_u[7:0]",  /* This bus is unused. */
-           EOL );
-       \end{verbatim} \rm }
-       \pagebreak[1]
-       \item Complete the model and save to the disk~:
-       { \tt \begin{verbatim}
-  DP_SAVLOFIG();
-
-  /* A good C program must always terminate by an "exit(0)". */
-  exit( 0 );
-}
-       \end{verbatim} \rm }
-     \end{enumerate}
-  %
-  %
-  %  FpGen : Netlist Generation
-  % ============================
-  %
-   \subsection{Generation of the \netlist}
-   \forceindent
-     After having writen the \C\ source file which describe the \netlist\ 
-   and correctly set up the environment, we just have to compile and
-   execute the former file. The \fpgen\ script file will do it for us,
-   so lets type the command~:
-   \\*[\bigskipamount]
-   \nopagebreak
-   \indent
-   \fbox{
-     \shortstack[l]{
-       \hspace*{13cm}\\
-       {\tt fpgen -v sample\_dpt }
-   }}\\*[\bigskipamount]
-   \nopagebreak
-   \indent
-     Which normally gives you~:%\\*[\bigskipamount]
-   \nopagebreak
-   \begin{figure}[H]
-     \begin{center}
-       \leavevmode\epsfxsize.55\textwidth\epsffile{./trace-fpgen-1.ps}
-     \end{center}
-   \end{figure}
-  %\centerline{\LARGE Trace de FpGen.}\\*[1cm]
-   {\bf Back to \mbkcatalib\ and \fpgenlib}
-   \\*[\bigskipamount]
-   \nopagebreak
-   \indent
-     Most of the \operators\ avalaible in \fpgen\ are built using
-   the leaf cell library {\tt \$ALLIANCE\_TOP/cells/fitpath/fplib}. However, some
-   \operators\, as \DPADDIIF, requires additionnal leaf cell
-   libraries. These dedicated libraries are noticed in the {\bf UNIX manual
-   pages} associated with \operators. In the case of \DPADDIIF\ the needed
-   library is {\tt \$ALLIANCE\_TOP/cells/rsa}.\\
-   \nopagebreak
-   \indent
-     So, \mbkcatalib\ must contain~:\\
-   \nopagebreak
-   \doubleindent
-       {\tt \$ALLIANCE\_TOP/cells/fitpath/fplib:\$ALLIANCE\_TOP/cells/rsa}\\*[\bigskipamount]
-   \indent
-     On the other hand, \fpgen\ creates not only the \datapath\ \netlist\ but
-   also the various views (\layout, \behavioral) of the \operators\
-   These auxiliary views are stored in the library pointed out
-   by the \fpgenlib\ environment variable. In our case, we choose
-   {\tt ./mclib}.
-  %
-  %
-  %  DPR : Placing and Routing
-  % ===========================
-  %
-   \subsection{Place and Route}
-   \begin{minipage}[t]{\textwidth}
-     \forceindent
-       To make \datapath\ \layout, run the place and route tool \dpr. The
-     command is~:\\*[\bigskipamount]
-     \forceindent
-     \fbox{
-       \shortstack[l]{
-         \hspace*{13cm}\\
-         {\tt dpr -v -p -r sample\_dpt sample\_dpt}
-     }}\\
-     \bigskip
-   \end{minipage}
-   \begin{minipage}[t]{\textwidth}
-     \forceindent
-       \dpr\ command line arguments\footnotemark~:
-     \begin{tabbing}
-       \samepage
-       \hspace{\sizeindentation} \= %
-       \hspace{0.5cm}      \= %
-       \hspace{2cm}        \= %
-       \hspace{0.4cm}      \= \kill
-       \> {\bf -v} \> \> : \> Verbose mode.\\
-       \> {\bf -p} \> \> : \> Activate the placement step.\\
-       \> {\bf -r} \> {\tt sample\_dpt} \> : \> Ask routing on \netlist\
-                                             {\tt sample\_dpt.vst}.\\
-       \> \> {\tt sample\_dpt} \> : \> Name of the file that holds the
-                                       place and routed \layout.
-     \end{tabbing}
-   \end{minipage}
-   \footnotetext{
-     For a more detailed description of \dpr\ command line arguments,
-     please refer to the {\bf UNIX} on line manual.
-     }
-   \forceindent
-     This normally produces~:\\*[1cm]
-   \nopagebreak
-   \begin{figure}[H]
-     \begin{center}
-       \leavevmode\epsfxsize.55\textwidth\epsffile{./trace-dpr-1.ps}
-     \end{center}
-   \end{figure}
-  %\centerline{\LARGE Trace de DPR.}\\*[1cm]
-   {\bf External terminal placement, \dprfile\ file}
-   \\*[\bigskipamount]
-   \nopagebreak
-   \indent
-     In addition to the \netlist, \dpr\ attempts to load an optional file
-   which contains some instruction about the way to place external data
-   terminals
-   \footnote{
-      For the definitions of data terminals and control terminals, please
-      refer~to~\S~\ref{refctrldataterm}.
-   }. The \dprfile\ file allows the designer to choose on which side put
-   the terminal, and for \EAST\ and \WEST\ sides, which \slice\ and which
-   \track.\\
-   \nopagebreak
-   \indent
-     file {\tt sample\_dpt.dpr} used in our example~:\\
-   \begin{minipage}[t]{\textwidth}
-   \begin{verbatim}
-#           Terminal :  Side  :  Slice  :  Track
-DP_LOCON   ctrl_zero   NORTH    DEFAULT   DEFAULT
-#
-#
-#           Terminal :  Side  :  Slice  :  Track
-DP_LOCON  data_a[7:0]   WEST    DEFAULT   DEFAULT
-DP_LOCON  data_b[7:0]   WEST    DEFAULT   DEFAULT
-DP_LOCON  data_s[7:0]   EAST    DEFAULT   DEFAULT
-#
-#
-# Number of vertical power refreshment.
-DP_POWER  1  50
-   \end{verbatim}
-   \end{minipage}
-   {\bf Back to \mbkcatalib}
-   \\*[\bigskipamount]
-   \nopagebreak
-   \indent
-     Place and route tool \dpr\ uses the various views of the operators
-   formerly stored by \fpgen\ inside the \fpgenlib\ library. This library
-   access path must be present in \mbkcatalib.
-   \nopagebreak
-   \indent
-     At the end, the complete \mbkcatalib\ is:\\
-   \doubleindent
-   \nopagebreak
-       {\tt \$ALLIANCE\_TOP/cells/fitpath/fplib:\$ALLIANCE\_TOP/cells/rsa:\$FPGEN\_LIB}
-  %
-  %
-  %  LYNX, LVX and DESB : Routage Validation
-  % =========================================
-  %
-   \subsection{Validation}
-    %
-    %
-    % Environnement set up for extraction.
-    %
-     \subsubsection{Environnement set up and validation}
-     \nopagebreak
-     \forceindent
-       All along the generation phasis we have used the \netlist\ format \fvst,
-     which stands for {\bf V}{\it HDL}\, {\bf ST}{\it ructural}\,. For the
-     validation phasis, we will use the \fal\ format. The \fal\ format is
-     dedicated to the extractions steps because it holds, in addition to
-     the logical informations (\netlist), some information driven from
-     the \layout, such as routing wire capacitances.
-     \\*[\bigskipamount]
-     \indent
-       Setting the new \netlist\ format~:\\
-     \nopagebreak
-     \indent
-     \fbox{ \shortstack[l]{
-       \hspace*{13cm} \\
-       {\tt \$ MBK\_IN\_LO=al} \\
-       {\tt \$ MBK\_OUT\_LO=al}
-     }}\\*[\bigskipamount]
-     \nopagebreak
-     \indent
-       Of course, the \layout\ file format remains unchanged.
-    %
-    %
-    % Routage Checking
-    %
-     \subsubsection{Routage Checking}
-     \begin{minipage}[t]{\textwidth}
-       \forceindent
-         The goal of this step is to ensure that the result of the
-       routing phasis is correct. This will be done in three steps~:
-       \begin{enumerate}
-         \item
-           Design rule checking, using the \symbolic\ \drc\ tool \druc.
-         \item
-           Extration of the gate \netlist\ from the \layout\ using \lynx.
-         \item
-           Checking coherency between the extracted \netlist\ (\fal\ format)
-           and the reference \netlist\ (\fvst\ format).
-       \end{enumerate}
-       \bigskip
-     \end{minipage}
-     {\bf Hierarchy management}
-     \\*[\bigskipamount]
-     \nopagebreak
-     \indent
-       In some cases, the routing tool \dpr\ is allowed to perform flattening
-     in the \layout\ view. As a consequence, \netlist\ extracted from the
-     \layout may have a different hierarchy than the reference \netlist.
-     In order to process to the validations, we ask to the tools involved
-     in the check to work at a gate level.
-     \\[\bigskipamount]
-     \begin{minipage}[t]{\textwidth}
-       {\bf DRuC : \symbolic\ desing rules checking}
-       \\*[\bigskipamount]
-       \forceindent
-       \fbox{ \shortstack[l]{
-         \hspace*{13cm} \\
-         {\tt \$ druc sample\_dpt}
-       }}%\\*[\bigskipamount]
-      %\vspace*{1cm}
-       \begin{figure}[H]
-         \begin{center}
-           \leavevmode\epsfxsize.55\textwidth\epsffile{./trace-druc-1.ps}
-         \end{center}
-       \end{figure}
-      %\centerline{\LARGE Trace de DRuC.}%\\*[1cm]
-     \end{minipage}
-     \begin{minipage}[t]{\textwidth}
-       {\bf Lynx : \netlist\ extraction}
-       \\*[\bigskipamount]
-       \forceindent
-       \fbox{ \shortstack[l]{
-         \hspace*{13cm} \\
-         {\tt \$ lynx -v -f sample\_dpt sample\_dpt\_gates}
-       }}%\\*[\bigskipamount]
-      %\vspace*{1cm}
-       \begin{figure}[H]
-         \begin{center}
-           \leavevmode\epsfxsize.55\textwidth\epsffile{./trace-lynx-1.ps}
-         \end{center}
-       \end{figure}
-      %\centerline{\LARGE Trace de Lynx.}\\*[1cm]
-     \end{minipage}
-     \begin{minipage}[t]{\textwidth}
-       {\bf LVX : \netlist\ comparisons}
-       \\*[\bigskipamount]
-       \forceindent
-       \fbox{ \shortstack[l]{
-         \hspace*{13cm} \\
-         {\tt \$ lvx vst al sample\_dpt sample\_dpt\_gates -f}
-       }}%\\*[\bigskipamount]
-      %\vspace*{1cm}
-       \begin{figure}[H]
-         \begin{center}
-           \leavevmode\epsfxsize.55\textwidth\epsffile{./trace-lvx-1.ps}
-         \end{center}
-       \end{figure}
-      %\centerline{\LARGE Trace de LVX.}
-     \end{minipage}
-    %
-    %
-    % Formal Proof.
-    %
-     \subsubsection{Formal proof}
-     \begin{minipage}[t]{\textwidth}
-       \forceindent
-         The goal of this phasis is to ensure that the \datapath\ we have
-       designed here is consistent with its specification. In our case,
-       the specification is the {\it VHDL behavioral} view
-       {\tt sample\_dpt.vbe}. Three steps are needed~:
-       \begin{enumerate}
-         \item
-            {\bf transistor} \netlist\ extraction from the \layout\ with
-            the \lynx\ tool.
-         \item
-            Restoration of a behavioral view {\tt sample\_dpt\_desb.vbe}
-            using the functional abstractor \desb.
-         \item
-            Formal proof between the behavioral model ({\tt sample\_dpt.vbe})
-            and the regenerated model ({\tt sample\_dpt\_desb.vbe}) using
-            the formal proofer tool \proof.
-       \end{enumerate}
-       \bigskip
-     \end{minipage}
-     \begin{minipage}[t]{\textwidth}
-       {\bf Register identification}
-       \\*[\bigskipamount]
-       \forceindent
-         The formal proof tool enforces that the memory elements of both
-       behavioral views must have the same names. As these names have
-       changed in the \layout, we must rename them. Fortunatly, the
-       functional abstractor \desb\ allow us to do so, via an
-       auxiliary file \desbfile.\\
-       \forceindent
-         The file {\tt sample\_dpt.inf} is supplied with the tutorial.
-     \end{minipage}
-     \begin{minipage}[t]{\textwidth}
-       {\bf Lynx : transistor \netlist\ extraction }
-       \\*[\bigskipamount]
-       \forceindent
-       \fbox{ \shortstack[l]{
-         \hspace*{13cm} \\
-         {\tt \$ lynx -v -t sample\_dpt sample\_dpt}
-       }}%\\*[\bigskipamount]
-      %\vspace*{1cm}
-       \begin{figure}[H]
-         \begin{center}
-           \leavevmode\epsfxsize.55\textwidth\epsffile{./trace-lynx-2.ps}
-         \end{center}
-       \end{figure}
-      %\centerline{\LARGE Trace de Lynx.}%\\*[1cm]
-     \end{minipage}
-     \begin{minipage}[t]{\textwidth}
-       {\bf DESB : Functional abstraction}\\*[\bigskipamount]
-       \forceindent
-       \fbox{ \shortstack[l]{
-         \hspace*{13cm} \\
-         {\tt \$ desb sample\_dpt sample\_dpt\_desb -v -i}
-       }}%\\*[\bigskipamount]
-      %\vspace*{1cm}
-       \begin{figure}[H]
-         \begin{center}
-           \leavevmode\epsfxsize.55\textwidth\epsffile{./trace-desb-1.ps}
-         \end{center}
-       \end{figure}
-      %\centerline{\LARGE Trace de DESB.}%\\*[1cm]
-     \end{minipage}
-     \begin{minipage}[t]{\textwidth}
-       {\bf Proof : Formal proof}\\*[\bigskipamount]
-       \forceindent
-       \fbox{ \shortstack[l]{
-         \hspace*{13cm} \\
-         {\tt \$ proof -d sample\_dpt sample\_dpt\_desb}
-       }}%\\*[\bigskipamount]
-      %\vspace*{1cm}
-       \begin{figure}[H]
-         \begin{center}
-           \leavevmode\epsfxsize.55\textwidth\epsffile{./trace-proof-1.ps}
-         \end{center}
-       \end{figure}
-      %\centerline{\LARGE Trace de Proof.}
-     \end{minipage}
-  %
-  %
-  % ************************* Troisieme Partie ****************************
-  %
-   \section{Advanced features}
-   \begin{minipage}[t]{\textwidth}
-     \forceindent
-       This section aims to present you some advanced features of \fpgen\ 
-     and \dpr\ tools. In the following examples, we do not describe the
-     whole procedure given for \sampledpt. We will limits ourselves to show
-     differences or novelties from the former methodology.
-   \end{minipage}
-  %
-  %  Placement
-  % ===========
-  %
-   \subsection{Placement}
-    %
-    %
-    % Initial Placement.
-    %
-     \subsubsection{Initial placement}
-     \begin{minipage}[t]{\textwidth}
-     \forceindent
-         The initial placement of \datapath\ operators is made from left to
-       rigth, following the order of instanciation used in the file
-       \sampledptsource. We have, starting from the left, the
-       followings operators~:
-       \begin{enumerate}
-         \item
-            Multiplexer generated by \DPMUXIICS.
-         \item
-            Adder generated by \DPADDIIF.
-         \item
-            Zero detect generated by \DPNUL.
-         \item
-            D flip-flop generated by \DPPDFF.
-       \end{enumerate}
-       Figure~\ref{placesample} shows initial placement.
-     \end{minipage}
-     \vspace*{0.5cm}
-     \begin{figure}[H]
-       \begin{center}
-         \leavevmode\epsfxsize.9\textwidth\epsffile{./sample_dpt-2.eps}
-       \end{center}
-       \nopagebreak
-       \caption{
-         \label{placesample}
-         {\it Initial placement.}}
-     \end{figure}
-     \indent
-       {\bf The order of instanciation of the operators in \C\ source file
-     is meaningful.} A \C\ source file intended to \fpgen/\dpr\ that
-     ignores it could produce \underline{non routable configurations}.\\
-     \forceindent
-       To avoid this kind of problems, we just have to group together the
-     instanciations of operators strongly connected.
-    %
-    %
-    % Placement Optimisation.
-    %
-     \subsubsection{Placement optimization}
-     \begin{minipage}[t]{\textwidth}
-       \forceindent
-         In the case of complex \datapath\ where the designer does not want
-       to check precisely the order of operators, placement optimizer inside
-       the router tool \dpr\ is avalaible. Roughly, the placement
-       optimizer swap operators trying to reduce the total length of
-       routing wires. This option is also interresting when the initial
-       placement is a non routable configuration. The optimizer is able
-       to detect such configuration in which case it attempts to reduce
-       the track density to make possible routage.\\
-       \forceindent
-         File {\tt place\_dpt.*} gives an example of placement optimization.
-       \bigskip
-     \end{minipage}
-     \begin{minipage}[t]{\textwidth}
-         Command to invoke \dpr\ in optimization mode~:
-       \\*[\bigskipamount]
-       \forceindent
-       \fbox{
-         \shortstack[l]{
-           \hspace*{13cm}\\
-           {\tt dpr -v -o -r -p place\_dpt place\_dpt}
-       }}\\*[\bigskipamount]
-       \forceindent
-         Arguments given to \dpr\footnotemark~:
-       \begin{tabbing}
-         \samepage
-         \hspace{\sizeindentation} \= %
-         \hspace{0.5cm}      \= %
-         \hspace{2cm}        \= %
-         \hspace{0.4cm}      \= \kill
-         \> {\bf -o} \> \> : \> Activate the placement optimizer.\\
-       \end{tabbing}
-     \end{minipage}
-     \footnotetext{
-       For a more detailed description of \dpr\ command line arguments,
-       please refer to the {\bf UNIX} on line manual.
-     }
-  %
-  %  User Customized Operators
-  % ===========================
-  %
-   \subsection{Designing customized operators}
-   \begin{minipage}[t]{\textwidth}
-     \forceindent
-       In this part we present the features allowing the user to design
-     his own \datapath\ operators. To build his operators the user must
-     resort to a dedicated leaf cell library~: \dplib\footnotemark.
-     \dplib\ offers the same functionnalities than the \standartcell\ library
-     \sclib.
-   \end{minipage}
-   \footnotetext{
-     On line manual of \dplib~: {\tt man dplib}, on line manuals of
-     cells~: {\tt man n1\_dp, man ms\_dp, ...}
-   }\\
-   \begin{minipage}[t]{\textwidth}
-     \forceindent
-       From a methodological point of view, using customized operators is
-     unfolding itself into two distinct phases~:
-     \begin{enumerate}
-       \item
-         Making of the operator using one of the following three methods~:
-       \begin{enumerate}
-         \item
-           Explicit building of a column using \genlib. The model name
-         must received a {\tt "\_us"} suffix.
-         \item
-           Synthesis of a block, using \logic. The model name must
-         received a {\tt "\_us"} suffix.
-         \item
-           Buiding a sub-\datapath\ using \fpgen. The model name must not
-         have a {\tt "\_us"}, {\tt "\_cl"} or {\tt "\_bk"} suffix.
-       \end{enumerate}
-       \item
-         Instanciation of the newly created operator inside the current
-       \datapath\ thanks to the \DPIMPORT\ function.
-     \end{enumerate}
-   \end{minipage}
-    %
-    %
-    % Environnement Variables.
-    %
-     \subsubsection{Environnement set up}
-     \doubleindent
-       We must add to \mbkcatalib\ the access path to the \dplib\ library~:\\
-     \nopagebreak
-     \indent
-     \fbox{ \shortstack[l]{
-       \hspace*{13cm} \\
-       { \tt \$ MBK\_CATA\_LIB=\$ALLIANCE\_TOP/cells/fitpath/dplib/ecpd10 }\\
-       { \tt \$ MBK\_CATA\_LIB=\$MBK\_CATA\_LIB:\$ALLIANCE\_TOP/cells/fitpath/fplib }\\
-       { \tt \$ MBK\_CATA\_LIB=\$MBK\_CATA\_LIB:\$ALLIANCE\_TOP/cells/rsa }\\
-       { \tt \$ MBK\_CATA\_LIB=\$MBK\_CATA\_LIB:\$FPGEN\_LIB }\\
-       { \tt \$ export MBK\_CATA\_LIB }
-     } }
-    %
-    %
-    % Single Column Operator.
-    %
-     \subsubsection{Single Column Operator}
-     \begin{minipage}[t]{\textwidth}
-       \forceindent
-         As an example, let us replace the zero detect provided by \fpgen\ 
-       (\DPNUL\ macro-function), by a designer build column.\\
-       \forceindent
-         The diagram of the zero detect we are going to build is shown in
-       figure~\ref{usercolschema}. The files {\tt usercol\_dpt.*} gives
-       an example of implementation.
-     \end{minipage}
-     \begin{figure}[H]
-       \begin{center}
-         \leavevmode\epsfxsize.4\textwidth\epsffile{./usercol_dpt-2.eps}
-       \end{center}
-       \nopagebreak
-       \caption{
-         \label{usercolschema}
-         {\it Zero detect diagram.}}
-     \end{figure}
-     \begin{description}
-       \samepage
-       \item
-         Description of zero detect using \genlib\ language~:
-         { \tt \begin{verbatim}
-static void  mkZeroDetect()
-{
-  DEF_LOFIG( "nul_us" );
-
-  LOCON(   "i0[7:0]", IN   ,   "i0[7:0]" );
-  LOCON( "zero"     ,   OUT, "zero"      );
-  LOCON(  "vdd"     , IN   ,  "vdd"      );
-  LOCON(  "vss"     , IN   ,  "vss"      );
-
-  LOINS( "no2_dp", "no2_0", "i0[0]", "i0[1]", "z2_0", "vdd", "vss", 0L );
-  LOINS( "no2_dp", "no2_2", "i0[2]", "i0[3]", "z2_1", "vdd", "vss", 0L );
-  LOINS( "no2_dp", "no2_4", "i0[4]", "i0[5]", "z2_2", "vdd", "vss", 0L );
-  LOINS( "no2_dp", "no2_6", "i0[6]", "i0[7]", "z2_3", "vdd", "vss", 0L );
-
-  LOINS( "na2_dp", "na2_1",  "z2_0",  "z2_1", "z4_0", "vdd", "vss", 0L );
-  LOINS( "na2_dp", "na2_5",  "z2_2",  "z2_3", "z4_1", "vdd", "vss", 0L );
-
-  LOINS( "no2_dp", "no2_3",  "z4_0",  "z4_1", "zero", "vdd", "vss", 0L );
-
-  SAVE_LOFIG();
-}
-         \end{verbatim} \rm }
-         \pagebreak[1]
-         \forceindent
-           As we can see, instance names of the zero detect must conform to
-         a specific syntax. The semantic of this syntax is that the suffix
-         of the instance name indicates to the \dpr\ placement stage on
-         which slice to set each instance. This agreement is recalled on the
-         figure~\ref{usercolschema}.
-         \pagebreak[3]
-       \item
-         Modification of the \C\ function describing the \datapath\ \netlist~:
-         { \tt \begin{verbatim}
-main()
-{
-  /* Generate the Zero Detect Column. */
-  mkZeroDetect();
-
-  /* Open a new Data-Path figure. */
-  DP_DEFLOFIG( "usercol_dpt", 8, LSB_INDEX_ZERO );
-
-  /* Interface description. */
-  /* ... */
-
-  /* Data-Path netlist description. */ 
-  /* Multiplexer ... */
-  /* Fast Adder ...  */
-
-  /* Zero Detect.    */
-  DP_IMPORT( "nul_us",
-             "zero",
-             "data_s[7:0]",
-             "ctrl_zero",
-             EOL );
-
-  /* Register ...    */
-
-  /* Terminate the netlist description, and save on disk. */
-  DP_SAVLOFIG();
-
-  exit(0);
-}
-       \end{verbatim} \rm }
-     \end{description}
-     \begin{minipage}[t]{\textwidth}
-       {\bf Remark~:}\\*[\bigskipamount]
-       \forceindent
-         The \fpgen\ and \genlib\ languages are made so that only one
-       \netlist\ is taken in the course of the description proccess. On the
-       other hand, to instanciate the model of zero detect with \DPIMPORT,
-       this model must be defined before. As a conclusion, we must call
-       the {\tt mkZeroDetect} function before the call to \DPDEFLOFIG.
-       \\*[\bigskipamount]
-       \forceindent
-         The sequence of commands invoked to generate and check this
-       example is the same as the one used in \sampledpt.
-     \end{minipage}
-    %
-    %
-    % Logical Synthesis of an operator.
-    %
-     \subsubsection{Logical synthesis of an operator}
-     \begin{minipage}[t]{\textwidth}
-       \forceindent
-         In this section we are going to replace the fast adder provided
-       by \DPADDIIF\ by a block generated by logical synthesis. The files
-       associated with this example are named {\tt synthese\_dpt.*}.
-       \bigskip
-     \end{minipage}
-     \begin{minipage}[t]{\textwidth}
-     {\bf Behavioral description of the adder~:}
-       { \tt \begin{verbatim}
-ENTITY  adder_us  IS
-  PORT(
-         a   : in    BIT_VECTOR(7 downto 0);
-         b   : in    BIT_VECTOR(7 downto 0);
-      cout_n :   out BIT;
-      over_n :   out BIT;
-         s   :   out BIT_VECTOR(7 downto 0);
-       vdd   : in    BIT;
-       vss   : in    BIT
-      );
-END  adder_us;
-
-ARCHITECTURE  behavior_data_flow  OF  adder_us  IS
-
-	SIGNAL cry : BIT_VECTOR(8 downto 0);
-
-BEGIN
-  cry(0) <= '0';
-  cry(8 downto 1) <=    (a and b)
-                     or (a and cry(7 downto 0))
-                     or (b and cry(7 downto 0));
-
-  s      <= a xor b xor cry(7 downto 0);
-  over_n <= not cry(7);
-  cout_n <= not cry(8);
-
-  ASSERT((vdd = '1') and (vss = '0'))
-    REPORT "Power supply is missing on adder_us"
-    SEVERITY WARNING;
-END  behavior_data_flow;
-       \end{verbatim} \rm }
-       \bigskip
-     \end{minipage}
-     \noindent
-     {\bf Remark~:}\\*[\bigskipamount]
-     \nopagebreak
-     \indent
-       As the terminal ordering is meaningful for instanciation with
-     \DPIMPORT, we adopt for the interface of {\tt adder\_us} the same
-     order as the one used in the operator provided by \DPADDIIF
-     \footnote{
-       For curious people, this operator is named {\tt "add2f\_8x8x0l\_bk"}.
-     }.\\*[\bigskipamount]
-     \begin{minipage}[t]{\textwidth}
-       {\bf Environment set up for logical synthesis~:}\\
-       \forceindent
-       \fbox{ \shortstack[l]{
-         \hspace*{13cm} \\
-         {\tt \$ MBK\_TARGET\_LIB=\$ALLIANCE\_TOP/cells/fitpath/dplib/ecpd10 }\\
-         {\tt \$ MBK\_NAME\_LOG="" }\\
-         {\tt \$ export MBK\_TARGET\_LIB MBK\_NAME\_LOG }
-       } }%\\*[\bigskipamount]
-     \bigskip
-     \end{minipage}
-     \begin{minipage}[t]{\textwidth}
-       {\bf Logic} : Optimization of behavioral equations.
-       \\*[\bigskipamount]
-       \forceindent
-       \fbox{ \shortstack[l]{
-         \hspace*{13cm} \\
-         {\tt \$ logic -o adder\_us adder\_us\_opt }
-       }}%\\*[\bigskipamount]
-      %\vspace*{1cm}
-       \begin{figure}[H]
-         \begin{center}
-           \leavevmode\epsfxsize.55\textwidth\epsffile{./trace-logic-1.ps}
-         \end{center}
-       \end{figure}
-      %\centerline{\LARGE Trace de Logic.}%\\*[1cm]
-     \end{minipage}
-     \begin{minipage}[t]{\textwidth}
-       {\bf Logic} : Logical synthesis of the \netlist\ starting from
-         previously optimized behavioral description.
-       \\*[\bigskipamount]
-       \forceindent
-       \fbox{ \shortstack[l]{
-         \hspace*{13cm} \\
-         {\tt \$ logic -s adder\_us\_opt adder\_us }
-       }}%\\*[\bigskipamount]
-      %\vspace*{1cm}
-       \begin{figure}[H]
-         \begin{center}
-           \leavevmode\epsfxsize.55\textwidth\epsffile{./trace-logic-2.ps}
-         \end{center}
-       \end{figure}
-      %\centerline{\LARGE Trace de Logic.}
-     \bigskip
-     \end{minipage}
-     \pagebreak[3]
-     \begin{description}
-       \samepage
-       \item
-         Modification of the \C\ function describing the \datapath\ \netlist~:
-         { \tt \begin{verbatim}
-main()
-{
-  /* Open a new Data-Path figure. */
-  DP_DEFLOFIG( "synthese_dpt", 8, LSB_INDEX_ZERO );
-
-  /* Interface description. */
-  /* ... */
-
-  /* Data-Path netlist description. */ 
-  /* Multiplexer ... */
-
-  /* Synthetized Adder. */
-  DP_IMPORT( "adder_us",
-             "adder",
-             "data_a[7:0]",
-             "data_m[7:0]",
-             "ctrl_ncout",
-             "ctrl_nover",
-             "data_s[7:0]",
-             EOL );
-
-  /* Zero Detect ... */
-  /* Register ...    */
-
-  /* Terminate the netlist description, and save on disk. */
-  DP_SAVLOFIG();
-
-  exit(0);
-}
-       \end{verbatim} \rm }
-       Further commands are the same as for \sampledpt.
-     \end{description}
-    %
-    %
-    % Sub-Data-Path.
-    %
-     \subsubsection{Hierarchical design~: sub-\datapath}
-     \begin{minipage}[t]{\textwidth}
-       \forceindent
-         As an illustration of the hierarchical design capabilities, we
-       have reshape the \netlist\ of the adder accumulator. In this new
-       \netlist, the adder (\DPADDIIF) and the zero detect have been put
-       together to make a sub-\datapath\ which we call {\tt alu\_dpt}.\\
-       \forceindent
-         Diagram of figure~\ref{schemahierarchy} shows modifications done to
-       the hierarchy. Files related to this example are named
-       {\tt "hierarchy\_dpt.*"}.
-     \end{minipage}
-     \vspace*{0.5cm}
-     \begin{figure}[H]
-       \begin{center}
-         \leavevmode\epsfxsize.90\textwidth\epsffile{./hierarchy_dpt-1.eps}
-       \end{center}
-       \nopagebreak
-       \caption{
-         \label{schemahierarchy}
-         {\it \netlist\ hierarchy.}}
-     \end{figure}
-     \begin{description}
-       \samepage
-       \item
-         Description of the sub-\datapath~:
-         { \tt \begin{verbatim}
-static void  mkSubDP()
-{
-  /* Open the ALU part of the Data-Path. */
-  DP_DEFLOFIG( "alu_dpt", 8, LSB_INDEX_ZERO );
-
-  /* Interface description. */
-
-  /* Control terminals declarations. */
-  DP_LOCON( "ctrl_ncout",   OUT, "ctrl_ncout" );
-  DP_LOCON( "ctrl_nover",   OUT, "ctrl_nover" );
-  DP_LOCON( "ctrl_zero" ,   OUT, "ctrl_zero"  );
-  /* Data terminals declarations. */
-  DP_LOCON( "data_a[7:0]" , IN   , "data_a[7:0]" );
-  DP_LOCON( "data_b[7:0]" , IN   , "data_b[7:0]" );
-  DP_LOCON( "data_s[7:0]" , INOUT, "data_s[7:0]" );
-  /* Power supplies terminals. */
-  DP_LOCON( "vdd", IN   , "vdd" );
-  DP_LOCON( "vss", IN   , "vss" );
-
-  /* Data-Path netlist description. */
-
-  /* Fast Adder. */
-  DP_ADD2F( "adder",
-            "data_a[7:0]",
-            "data_b[7:0]",
-            "ctrl_ncout",
-            "ctrl_nover",
-            "data_s[7:0]",
-            EOL );
-
-  /* Zero Detect. */
-  DP_NUL( "zero", 8, 0,
-          "data_s[7:0]",
-          "ctrl_zero",
-          EOL );
-
-
-  /* Terminate the netlist description, and save on disk. */
-  DP_SAVLOFIG();
-}
-         \end{verbatim} \rm }
-         \pagebreak[1]
-       \item
-         Modification of the \C\ function describing the \datapath\ \netlist~:
-         { \tt \begin{verbatim}
-main()
-{
-  /* Generate the Zero Detect Column. */
-  mkSubDP();
-
-  /* Open a new Data-Path figure. */
-  DP_DEFLOFIG( "hierarchy_dpt", 8, LSB_INDEX_ZERO );
-
-  /* Interface description. */
-  /* ... */
-
-  /* Data-Path netlist description. */ 
-  /* Multiplexer ... */
-
-  /* Sub-Data-Path. */
-  DP_IMPORT( "alu_dpt",
-             "alu",
-             "ctrl_ncout",
-             "ctrl_nover",
-             "ctrl_zero",
-             "data_a[7:0]",
-             "data_m[7:0]",
-             "data_s[7:0]",
-             EOL );
-
-  /* Register ...    */
-
-  /* Terminate the netlist description, and save on disk. */
-  DP_SAVLOFIG();
-
-  exit(0);
-}
-         \end{verbatim} \rm }
-         \pagebreak[1]
-       \item
-         Modification of the \dprfile\ file, add the following lines~:
-         { \tt \begin{verbatim}
-#         Model Name : Iterations : Height : CPC
-DP_GLUE    adder_us       5000         8      2
-         \end{verbatim} \rm }
-         \forceindent
-           The placement of \gluelogic\ blocks is automatically performed by
-         the router \dpr. The {\tt DP\_GLUE} command of the \dprfile\
-         allows a control on the way this placement will be done.\\
-         \forceindent
-           Parameters meanings~:
-         \begin{description}
-           \item[Iterations] gives the number of iteration the placement
-             algorithm will do.
-           \item[Height] height of the block (in \slices).
-           \item[CPC] Number of cells per \slice\ (inside a \column).
-             The greater the number, the smaller the surface used for the
-           block, on the other hand the routing becomes more difficult.
-           A good value is generally around 2--3.
-         \end{description}
-         \pagebreak[3]
-         \forceindent
-           Placement of \gluelogic\ blocks is systemetically performed at
-         each call of the router \dpr. As the placement of blocks coming
-         from logical synthesis can take a long time, and in the case
-         where we do several successive routing, we can prevent \dpr\ 
-         to place the block at each routing phasis. The router will use
-         the placement generated at a former iteration. To prevent
-         \dpr\ to place a block, just add in the \dprfile~:
-         { \tt \begin{verbatim}
-#         Model Name
-DP_KEEP    adder_us
-         \end{verbatim} \rm }
-         \forceindent
-           Further command are the same as for \sampledpt.
-     \end{description}
-     \begin{minipage}[t]{\textwidth}
-       {\bf Remark~:}\\*[\bigskipamount]
-       \forceindent
-         By the time the \DPDEFLOFIG\ function saves the \netlist\ on disk,
-       this \netlist is automatically flattened at "operator" level. In
-       our example, the sub-\datapath\ {\tt "alu\_dpt"} included
-       inside {\tt "hierarchy\_dpt"} will be flattened when the whole
-       \datapath\ will be terminated.\\
-       \forceindent
-         This behavior is needed by the fact that the router \dpr\ is not
-       able to manage the hierarchy. It only can route a \netlist\ made of
-       operators.\\
-       \forceindent
-         For the sake of clarity regarding the description of the \netlist\ 
-       we have chosen to adopt a hierarchical concept at \fpgen\ level.
-     \end{minipage}
-  %
-  %
-  % ************************* Quatrieme Partie ****************************
-  %
-   \newpage
-   \appendix
-   \section{Files provided with the tutorial}
-     Summary of the five examples~:
-   \begin{center}
-     \begin{tabular}[t]{|c|c|}
-       \hline
-       fichiers   & exemple                           \\
-       \hline
-       \hline
-       {\tt    sample\_dpt} & first exemple           \\
-       {\tt     place\_dpt} & placement optimization  \\
-       {\tt   usercol\_dpt} & customized column       \\
-       {\tt synthesis\_dpt} & syntesized block        \\
-       {\tt hierarchy\_dpt} & hierarchical design     \\
-       \hline
-     \end{tabular}\\
-     \bigskip
-   \end{center}
-     File associated to each example~:
-   \begin{center}
-     \begin{tabular}[t]{|c|c|}
-       \hline
-       extention  & type of file                \\
-       \hline
-       \hline
-       {\tt .sh}  & script in \bourneshell      \\
-       {\tt .c}   & \C\ source file for \fpgen  \\
-       {\tt .dpr} & auxiliary file for \dpr     \\
-       {\tt .inf} & auxiliary file for \desb    \\
-       \hline
-     \end{tabular}\\
-     \bigskip
-   \end{center}
-   In addition to the five shell scripts, a {\tt Makefile} is also provided.
-
-
- \end{document}
-
diff --git a/alliance/share/tutorials/fitpath/tex/gates.fig b/alliance/share/tutorials/fitpath/tex/gates.fig
deleted file mode 100644
index 16657907..00000000
--- a/alliance/share/tutorials/fitpath/tex/gates.fig
+++ /dev/null
@@ -1,105 +0,0 @@
-#FIG 2.1
-80 2
-6 194 29 244 89
-5 1 0 4 -1 0 0 0 0.000 0 0 0 203.375 59.000 209 34 229 59 209 84
-1 4 0 4 -1 0 0 0 0.00000 1 0.000 234 59 5 5 229 59 239 59
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 209 34 199 34 199 84 209 84 9999 9999
--6
-6 274 29 324 89
-1 4 0 4 -1 0 0 0 0.00000 1 0.000 314 59 5 5 309 59 319 59
-3 2 0 4 -1 0 0 0 0.000 0 0
-	 279 34 289 59 279 84 9999 9999
-	 -320.000 -220.000 286.500 47.355 289.000 53.605 289.000 64.395
-	 286.500 70.645 -320.000 -220.000
-3 2 0 4 -1 0 0 0 0.000 0 0
-	 279 34 299 44 309 59 9999 9999
-	 -320.000 -220.000 290.904 38.767 295.904 41.267 301.496 46.203
-	 303.996 49.953 -320.000 -220.000
-3 2 0 4 -1 0 0 0 0.000 0 0
-	 279 84 299 74 309 59 9999 9999
-	 -320.000 -220.000 290.904 79.233 295.904 76.733 301.496 71.797
-	 303.996 68.047 -320.000 -220.000
--6
-6 354 29 414 89
-1 4 0 4 -1 0 0 0 0.00000 1 0.000 404 59 5 5 399 59 409 59
-2 2 0 4 -1 0 0 0 0.000 0 0 0
-	 399 84 399 34 359 34 359 84 399 84 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 359 34 399 59 359 84 9999 9999
--6
-6 434 29 484 89
-2 2 0 4 -1 0 0 0 0.000 0 0 0
-	 479 84 479 34 439 34 439 84 479 84 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 439 34 449 44 459 34 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 444 49 449 49 449 59 454 59 9999 9999
--6
-6 354 109 404 169
-2 2 0 4 -1 0 0 0 0.000 0 0 0
-	 399 164 399 114 359 114 359 164 399 164 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 359 114 399 139 359 164 9999 9999
--6
-6 274 109 314 169
-3 2 0 4 -1 0 0 0 0.000 0 0
-	 279 114 289 139 279 164 9999 9999
-	 -320.000 -140.000 286.500 127.355 289.000 133.605 289.000 144.395
-	 286.500 150.645 -320.000 -140.000
-3 2 0 4 -1 0 0 0 0.000 0 0
-	 279 164 299 154 309 139 9999 9999
-	 -320.000 -140.000 290.904 159.233 295.904 156.733 301.496 151.797
-	 303.996 148.047 -320.000 -140.000
-3 2 0 4 -1 0 0 0 0.000 0 0
-	 279 114 299 124 309 139 9999 9999
-	 -320.000 -140.000 290.904 118.767 295.904 121.267 301.496 126.203
-	 303.996 129.953 -320.000 -140.000
--6
-6 194 109 244 169
-5 1 0 4 -1 0 0 0 0.000 0 0 0 203.375 139.000 209 114 229 139 209 164
-1 4 0 4 -1 0 0 0 0.00000 1 0.000 234 139 5 5 229 139 239 139
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 209 114 199 114 199 164 209 164 9999 9999
--6
-6 514 34 544 84
-1 4 0 4 -1 0 0 0 0.00000 1 0.000 529 74 5 5 529 69 529 79
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 519 39 529 59 539 39 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 529 39 519 39 519 49 529 69 539 49 539 39 529 39 9999 9999
--6
-6 514 114 544 154
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 529 119 519 119 519 129 529 149 539 129 539 119 529 119 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 519 119 529 139 539 119 9999 9999
--6
-6 594 34 624 74
-1 4 0 4 -1 0 0 0 0.00000 1 0.000 609 64 5 5 609 59 609 69
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 599 39 619 39 609 59 599 39 609 39 9999 9999
--6
-6 594 114 624 144
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 599 119 619 119 609 139 599 119 609 119 9999 9999
--6
-6 654 29 684 49
-1 4 0 4 -1 0 0 0 0.00000 1 0.000 674 39 5 5 674 34 674 44
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 659 34 659 44 669 39 659 34 659 39 9999 9999
--6
-6 694 29 724 49
-1 4 0 4 -1 0 0 0 0.00000 1 0.000 704 39 5 5 704 34 704 44
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 719 34 719 44 709 39 719 34 719 39 9999 9999
--6
-6 654 109 674 129
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 659 114 659 124 669 119 659 114 659 119 9999 9999
--6
-6 704 109 724 129
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 719 114 719 124 709 119 719 114 719 119 9999 9999
--6
-4 0 4 16 0 -1 10 0.00000 0 19 85 39 59 Un petit texte

diff --git a/alliance/share/tutorials/fitpath/tex/hierarchy_dpt-1.fig b/alliance/share/tutorials/fitpath/tex/hierarchy_dpt-1.fig
deleted file mode 100644
index baeaf476..00000000
--- a/alliance/share/tutorials/fitpath/tex/hierarchy_dpt-1.fig
+++ /dev/null
@@ -1,379 +0,0 @@
-#FIG 2.1
-80 2
-6 774 994 864 1164
-2 1 0 2 -1 0 0 0 0.000 7 0 0
-	 789 999 799 1019 809 999 9999 9999
-2 1 0 2 -1 0 0 0 0.000 7 0 0
-	 789 1024 799 1024 799 1044 809 1044 9999 9999
-2 1 0 2 -1 0 0 0 0.000 7 0 0
-	 794 1029 799 1039 804 1029 9999 9999
-2 2 0 4 -1 0 0 0 0.000 0 0 0
-	 859 1159 859 999 779 999 779 1159 859 1159 9999 9999
--6
-6 414 994 464 1164
-2 2 0 4 -1 0 0 0 0.000 0 0 0
-	 459 1159 459 999 419 999 419 1159 459 1159 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 419 999 459 1079 419 1159 9999 9999
--6
-6 429 789 449 809
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 434 794 444 804 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 444 794 434 804 9999 9999
--6
-6 329 869 349 889
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 334 874 344 884 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 344 874 334 884 9999 9999
--6
-6 329 1029 349 1049
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 334 1034 344 1044 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 344 1034 334 1044 9999 9999
--6
-6 789 789 809 809
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 794 794 804 804 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 804 794 794 804 9999 9999
--6
-6 829 789 849 809
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 834 794 844 804 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 844 794 834 804 9999 9999
--6
-6 929 949 949 969
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 934 954 944 964 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 944 954 934 964 9999 9999
--6
-6 889 1029 909 1049
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 894 1034 904 1044 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 904 1034 894 1044 9999 9999
--6
-6 579 789 599 809
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 584 794 594 804 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 594 794 584 804 9999 9999
--6
-6 619 789 639 809
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 624 794 634 804 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 634 794 624 804 9999 9999
--6
-6 489 869 509 899
-2 1 0 2 -1 0 0 21 0.000 -1 0 0
-	 504 874 494 884 9999 9999
-4 1 4 16 0 -1 0 0.00000 0 19 8 499 899 8

--6
-6 659 789 679 809
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 664 794 674 804 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 674 794 664 804 9999 9999
--6
-6 614 504 764 554
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 659 509 619 529 659 549 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 719 509 759 529 719 549 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 639 519 739 519 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 639 539 739 539 9999 9999
--6
-6 304 434 374 604
-2 2 0 4 -1 0 0 0 0.000 0 0 0
-	 369 599 369 439 309 439 309 599 369 599 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 339 509 339 529 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 329 519 349 519 9999 9999
--6
-6 404 434 434 604
-2 2 0 4 -1 0 0 0 0.000 0 0 0
-	 429 599 429 439 409 439 409 599 429 599 9999 9999
-4 1 2 20 0 -1 0 0.00000 0 21 9 419 524 0

--6
-6 259 469 279 489
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 264 474 274 484 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 274 474 264 484 9999 9999
--6
-6 259 549 279 569
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 264 554 274 564 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 274 554 264 564 9999 9999
--6
-6 499 549 519 569
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 504 554 514 564 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 514 554 504 564 9999 9999
--6
-6 309 389 329 409
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 314 394 324 404 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 324 394 314 404 9999 9999
--6
-6 349 389 369 409
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 354 394 364 404 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 364 394 354 404 9999 9999
--6
-6 449 389 469 409
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 454 394 464 404 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 464 394 454 404 9999 9999
--6
-6 869 559 889 579
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 874 564 884 574 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 884 564 874 574 9999 9999
--6
-6 869 479 889 499
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 874 484 884 494 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 884 484 874 494 9999 9999
--6
-6 899 429 919 449
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 904 434 914 444 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 914 434 904 444 9999 9999
--6
-6 939 429 959 449
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 944 434 954 444 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 954 434 944 444 9999 9999
--6
-6 1009 519 1029 539
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 1014 524 1024 534 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 1024 524 1014 534 9999 9999
--6
-6 979 429 999 449
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 984 434 994 444 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 994 434 984 444 9999 9999
--6
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 579 879 339 879 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 739 959 739 1099 779 1099 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 799 999 799 799 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 439 999 439 799 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 839 999 839 799 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 459 1079 539 1079 539 959 579 959 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 419 1039 339 1039 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 419 1119 379 1119 379 1199 899 1199 899 1119 859 1119 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 859 1039 899 1039 9999 9999
-2 2 1 2 -1 0 0 0 6.000 0 0 0
-	 939 1239 939 799 339 799 339 1239 939 1239 9999 9999
-2 1 0 2 -1 0 0 21 0.000 -1 0 0
-	 504 1074 494 1084 9999 9999
-2 1 0 2 -1 0 0 21 0.000 -1 0 0
-	 884 954 874 964 9999 9999
-2 1 0 2 -1 0 0 21 0.000 -1 0 0
-	 884 1034 874 1044 9999 9999
-2 1 0 2 -1 0 0 21 0.000 -1 0 0
-	 664 1194 654 1204 9999 9999
-2 1 0 2 -1 0 0 21 0.000 -1 0 0
-	 434 814 444 824 9999 9999
-2 1 0 2 -1 0 0 21 0.000 -1 0 0
-	 794 814 804 824 9999 9999
-2 1 0 2 -1 0 0 21 0.000 -1 0 0
-	 834 814 844 824 9999 9999
-2 1 0 2 -1 0 0 21 0.000 -1 0 0
-	 384 1034 374 1044 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 679 959 939 959 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 589 799 589 839 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 629 799 629 839 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 669 799 669 839 9999 9999
-2 1 0 2 -1 0 0 21 0.000 -1 0 0
-	 584 814 594 824 9999 9999
-2 1 0 2 -1 0 0 21 0.000 -1 0 0
-	 624 814 634 824 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 424 1044 414 1044 414 1034 424 1034 424 1044 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 744 964 734 964 734 954 744 954 744 964 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 424 1124 414 1124 414 1114 424 1114 424 1124 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 464 1084 454 1084 454 1074 464 1074 464 1084 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 784 1104 774 1104 774 1094 784 1094 784 1104 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 864 1044 854 1044 854 1034 864 1034 864 1044 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 844 1004 834 1004 834 994 844 994 844 1004 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 804 1004 794 1004 794 994 804 994 804 1004 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 864 1124 854 1124 854 1114 864 1114 864 1124 9999 9999
-2 2 0 4 -1 0 0 0 0.000 0 0 0
-	 679 979 679 839 579 839 579 979 679 979 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 609 859 609 899 629 909 609 919 609 959 649 939 649 879 609 859 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 584 884 574 884 574 874 584 874 584 884 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 584 964 574 964 574 954 584 954 584 964 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 684 964 674 964 674 954 684 954 684 964 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 674 844 664 844 664 834 674 834 674 844 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 634 844 624 844 624 834 634 834 634 844 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 594 844 584 844 584 834 594 834 594 844 9999 9999
-2 1 0 2 -1 0 0 21 0.000 -1 0 0
-	 664 814 674 824 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 269 479 309 479 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 269 559 309 559 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 369 559 509 559 9999 9999
-2 1 0 2 -1 0 0 21 0.000 -1 0 0
-	 314 414 324 424 9999 9999
-2 1 0 2 -1 0 0 21 0.000 -1 0 0
-	 354 414 364 424 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 319 399 319 439 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 359 399 359 439 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 459 399 459 479 429 479 9999 9999
-2 2 1 2 -1 0 0 0 6.000 0 0 0
-	 509 659 509 399 269 399 269 659 509 659 9999 9999
-2 1 0 2 -1 0 0 21 0.000 -1 0 0
-	 454 414 464 424 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 314 564 304 564 304 554 314 554 314 564 9999 9999
-2 2 0 0 -1 0 0 21 0.000 7 0 0
-	 314 484 314 474 304 474 304 484 314 484 9999 9999
-2 2 0 0 -1 0 0 21 0.000 7 0 0
-	 324 444 324 434 314 434 314 444 324 444 9999 9999
-2 2 0 0 -1 0 0 21 0.000 7 0 0
-	 364 444 364 434 354 434 354 444 364 444 9999 9999
-2 2 0 0 -1 0 0 21 0.000 7 0 0
-	 434 484 434 474 424 474 424 484 434 484 9999 9999
-2 2 0 0 -1 0 0 21 0.000 7 0 0
-	 414 564 414 554 404 554 404 564 414 564 9999 9999
-2 2 0 0 -1 0 0 21 0.000 7 0 0
-	 374 564 374 554 364 554 364 564 374 564 9999 9999
-2 1 0 2 -1 0 0 21 0.000 -1 0 0
-	 294 554 284 564 9999 9999
-2 1 0 2 -1 0 0 21 0.000 -1 0 0
-	 294 474 284 484 9999 9999
-2 1 0 2 -1 0 0 21 0.000 -1 0 0
-	 474 554 464 564 9999 9999
-2 2 0 4 -1 0 0 0 0.000 0 0 0
-	 999 599 999 459 899 459 899 599 999 599 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 929 479 929 519 949 529 929 539 929 579 969 559 969 499 929 479 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 994 464 984 464 984 454 994 454 994 464 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 954 464 944 464 944 454 954 454 954 464 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 914 464 904 464 904 454 914 454 914 464 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 904 494 894 494 894 484 904 484 904 494 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 904 574 894 574 894 564 904 564 904 574 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 1004 534 994 534 994 524 1004 524 1004 534 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 879 489 899 489 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 879 569 899 569 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 909 439 909 459 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 949 439 949 459 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 989 439 989 459 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 1019 529 999 529 9999 9999
-4 1 4 16 0 -1 0 0.00000 0 19 48 499 1069 data_m

-4 2 4 16 0 -1 0 0.00000 0 19 71 319 1044 data_b[7:0]

-4 2 4 16 0 -1 0 0.00000 0 19 71 319 884 data_a[7:0]

-4 0 4 16 0 -1 0 0.00000 0 19 71 959 964 data_s[7:0]

-4 1 4 16 0 -1 0 0.00000 0 19 44 899 1029 data_u

-4 0 4 16 0 -1 0 1.57080 0 19 47 444 779 ctrl_sel

-4 0 4 16 0 -1 0 1.57080 0 19 43 804 779 ctrl_ck

-4 0 4 16 0 -1 0 1.57080 0 19 53 844 779 ctrl_wen

-4 1 4 16 0 -1 0 0.00000 0 19 44 659 1189 data_q

-4 1 4 16 0 -1 0 0.00000 0 19 8 499 1099 8

-4 1 4 16 0 -1 0 0.00000 0 19 8 659 1219 8

-4 1 4 16 0 -1 0 0.00000 0 19 8 879 1059 8

-4 1 4 16 0 -1 0 0.00000 0 19 8 879 979 8

-4 1 4 16 0 -1 0 0.00000 0 19 8 379 1059 8

-4 1 4 16 0 -1 0 1.57080 0 19 8 459 819 1

-4 1 4 16 0 -1 0 1.57080 0 19 8 819 819 1

-4 1 4 16 0 -1 0 1.57080 0 19 8 859 819 1

-4 1 2 16 0 -1 0 0.00000 0 19 89 439 1179 DP_MUX2CS

-4 1 2 16 0 -1 0 0.00000 0 19 71 819 1179 DP_PDFF

-4 1 2 16 0 -1 0 0.00000 0 19 92 629 999 DP_IMPORT

-4 0 4 16 0 -1 0 1.57080 0 19 64 594 779 ctrl_ncout

-4 0 4 16 0 -1 0 1.57080 0 19 65 634 779 ctrl_nover

-4 1 4 16 0 -1 0 1.57080 0 19 8 609 819 1

-4 1 4 16 0 -1 0 1.57080 0 19 8 649 819 1

-4 1 2 16 0 -1 0 0.00000 0 19 46 629 974 alu_dpt

-4 0 4 16 0 -1 0 1.57080 0 19 56 674 779 ctrl_zero

-4 1 4 16 0 -1 0 1.57080 0 19 8 689 819 1

-4 1 2 16 0 -1 0 0.00000 0 19 81 339 619 DP_ADD2F

-4 1 2 16 0 -1 0 0.00000 0 19 57 419 619 DP_NUL

-4 0 4 16 0 -1 0 1.57080 0 19 64 324 379 ctrl_ncout

-4 0 4 16 0 -1 0 1.57080 0 19 65 364 379 ctrl_nover

-4 1 4 16 0 -1 0 1.57080 0 19 8 339 419 1

-4 1 4 16 0 -1 0 1.57080 0 19 8 379 419 1

-4 2 4 16 0 -1 0 0.00000 0 19 71 249 484 data_a[7:0]

-4 0 4 16 0 -1 0 0.00000 0 19 71 529 564 data_s[7:0]

-4 2 4 16 0 -1 0 0.00000 0 19 71 249 564 data_b[7:0]

-4 1 2 16 0 -1 0 0.00000 0 19 46 389 654 alu_dpt

-4 0 4 16 0 -1 0 1.57080 0 19 56 464 379 ctrl_zero

-4 1 4 16 0 -1 0 1.57080 0 19 8 479 419 1

-4 1 4 16 0 -1 0 0.00000 0 19 8 289 579 8

-4 1 4 16 0 -1 0 0.00000 0 19 8 289 499 8

-4 1 4 16 0 -1 0 0.00000 0 19 8 469 579 8

-4 1 2 16 0 -1 0 0.00000 0 19 46 949 594 alu_dpt

-4 2 4 16 0 -1 0 0.00000 0 19 71 859 574 data_b[7:0]

-4 2 4 16 0 -1 0 0.00000 0 19 71 859 494 data_a[7:0]

-4 0 4 16 0 -1 0 0.00000 0 19 71 1039 534 data_s[7:0]

-4 0 4 16 0 -1 0 1.57080 0 19 56 994 419 ctrl_zero

-4 0 4 16 0 -1 0 1.57080 0 19 65 954 419 ctrl_nover

-4 0 4 16 0 -1 0 1.57080 0 19 64 914 419 ctrl_ncout

diff --git a/alliance/share/tutorials/fitpath/tex/sample_dpt-1.fig b/alliance/share/tutorials/fitpath/tex/sample_dpt-1.fig
deleted file mode 100644
index a8be8edf..00000000
--- a/alliance/share/tutorials/fitpath/tex/sample_dpt-1.fig
+++ /dev/null
@@ -1,203 +0,0 @@
-#FIG 2.1
-80 2
-6 574 254 644 424
-2 2 0 4 -1 0 0 0 0.000 0 0 0
-	 639 419 639 259 579 259 579 419 639 419 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 609 329 609 349 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 599 339 619 339 9999 9999
--6
-6 674 254 704 424
-2 2 0 4 -1 0 0 0 0.000 0 0 0
-	 699 419 699 259 679 259 679 419 699 419 9999 9999
-4 1 2 20 0 -1 0 0.00000 0 21 9 689 344 0

--6
-6 774 414 864 584
-2 1 0 2 -1 0 0 0 0.000 7 0 0
-	 789 419 799 439 809 419 9999 9999
-2 1 0 2 -1 0 0 0 0.000 7 0 0
-	 789 444 799 444 799 464 809 464 9999 9999
-2 1 0 2 -1 0 0 0 0.000 7 0 0
-	 794 449 799 459 804 449 9999 9999
-2 2 0 4 -1 0 0 0 0.000 0 0 0
-	 859 579 859 419 779 419 779 579 859 579 9999 9999
--6
-6 414 414 464 584
-2 2 0 4 -1 0 0 0 0.000 0 0 0
-	 459 579 459 419 419 419 419 579 459 579 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 419 419 459 499 419 579 9999 9999
--6
-6 429 209 449 229
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 434 214 444 224 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 444 214 434 224 9999 9999
--6
-6 329 289 349 309
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 334 294 344 304 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 344 294 334 304 9999 9999
--6
-6 329 449 349 469
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 334 454 344 464 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 344 454 334 464 9999 9999
--6
-6 579 209 599 229
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 584 214 594 224 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 594 214 584 224 9999 9999
--6
-6 619 209 639 229
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 624 214 634 224 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 634 214 624 224 9999 9999
--6
-6 729 209 749 229
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 734 214 744 224 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 744 214 734 224 9999 9999
--6
-6 789 209 809 229
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 794 214 804 224 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 804 214 794 224 9999 9999
--6
-6 829 209 849 229
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 834 214 844 224 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 844 214 834 224 9999 9999
--6
-6 929 369 949 389
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 934 374 944 384 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 944 374 934 384 9999 9999
--6
-6 889 449 909 469
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 894 454 904 464 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 904 454 894 464 9999 9999
--6
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 579 299 339 299 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 589 219 589 259 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 629 219 629 259 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 739 379 739 519 779 519 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 799 419 799 219 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 439 419 439 219 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 839 419 839 219 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 459 499 539 499 539 379 579 379 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 419 459 339 459 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 419 539 379 539 379 619 899 619 899 539 859 539 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 859 459 899 459 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 639 379 939 379 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 699 299 739 299 739 219 9999 9999
-2 2 1 2 -1 0 0 0 6.000 0 0 0
-	 939 659 939 219 339 219 339 659 939 659 9999 9999
-2 1 0 2 -1 0 0 21 0.000 -1 0 0
-	 504 294 494 304 9999 9999
-2 1 0 2 -1 0 0 21 0.000 -1 0 0
-	 504 494 494 504 9999 9999
-2 1 0 2 -1 0 0 21 0.000 -1 0 0
-	 884 374 874 384 9999 9999
-2 1 0 2 -1 0 0 21 0.000 -1 0 0
-	 884 454 874 464 9999 9999
-2 1 0 2 -1 0 0 21 0.000 -1 0 0
-	 664 614 654 624 9999 9999
-2 1 0 2 -1 0 0 21 0.000 -1 0 0
-	 434 234 444 244 9999 9999
-2 1 0 2 -1 0 0 21 0.000 -1 0 0
-	 584 234 594 244 9999 9999
-2 1 0 2 -1 0 0 21 0.000 -1 0 0
-	 624 234 634 244 9999 9999
-2 1 0 2 -1 0 0 21 0.000 -1 0 0
-	 734 234 744 244 9999 9999
-2 1 0 2 -1 0 0 21 0.000 -1 0 0
-	 794 234 804 244 9999 9999
-2 1 0 2 -1 0 0 21 0.000 -1 0 0
-	 834 234 844 244 9999 9999
-2 1 0 2 -1 0 0 21 0.000 -1 0 0
-	 384 454 374 464 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 424 464 424 454 414 454 414 464 424 464 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 424 544 424 534 414 534 414 544 424 544 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 464 504 464 494 454 494 454 504 464 504 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 584 384 584 374 574 374 574 384 584 384 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 584 304 584 294 574 294 574 304 584 304 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 634 264 634 254 624 254 624 264 634 264 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 704 304 704 294 694 294 694 304 704 304 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 784 524 784 514 774 514 774 524 784 524 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 744 384 744 374 734 374 734 384 744 384 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 804 424 804 414 794 414 794 424 804 424 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 844 424 844 414 834 414 834 424 844 424 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 864 544 864 534 854 534 854 544 864 544 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 594 264 594 254 584 254 584 264 594 264 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 644 384 644 374 634 374 634 384 644 384 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 684 384 684 374 674 374 674 384 684 384 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 864 464 864 454 854 454 854 464 864 464 9999 9999
-4 1 4 16 0 -1 0 0.00000 0 19 48 499 489 data_m

-4 2 4 16 0 -1 0 0.00000 0 19 71 319 464 data_b[7:0]

-4 2 4 16 0 -1 0 0.00000 0 19 71 319 304 data_a[7:0]

-4 0 4 16 0 -1 0 0.00000 0 19 71 959 384 data_s[7:0]

-4 1 4 16 0 -1 0 0.00000 0 19 44 899 449 data_u

-4 0 4 16 0 -1 0 1.57080 0 19 47 444 199 ctrl_sel

-4 0 4 16 0 -1 0 1.57080 0 19 64 594 199 ctrl_ncout

-4 0 4 16 0 -1 0 1.57080 0 19 65 634 199 ctrl_nover

-4 0 4 16 0 -1 0 1.57080 0 19 56 744 199 ctrl_zero

-4 0 4 16 0 -1 0 1.57080 0 19 43 804 199 ctrl_ck

-4 0 4 16 0 -1 0 1.57080 0 19 53 844 199 ctrl_wen

-4 1 4 16 0 -1 0 0.00000 0 19 44 659 609 data_q

-4 1 4 16 0 -1 0 0.00000 0 19 8 499 319 8

-4 1 4 16 0 -1 0 0.00000 0 19 8 499 519 8

-4 1 4 16 0 -1 0 0.00000 0 19 8 659 639 8

-4 1 4 16 0 -1 0 0.00000 0 19 8 879 479 8

-4 1 4 16 0 -1 0 0.00000 0 19 8 879 399 8

-4 1 4 16 0 -1 0 0.00000 0 19 8 379 479 8

-4 1 4 16 0 -1 0 1.57080 0 19 8 459 239 1

-4 1 4 16 0 -1 0 1.57080 0 19 8 609 239 1

-4 1 4 16 0 -1 0 1.57080 0 19 8 649 239 1

-4 1 4 16 0 -1 0 1.57080 0 19 8 759 239 1

-4 1 4 16 0 -1 0 1.57080 0 19 8 819 239 1

-4 1 4 16 0 -1 0 1.57080 0 19 8 859 239 1

-4 1 2 16 0 -1 0 0.00000 0 19 89 439 599 DP_MUX2CS

-4 1 2 16 0 -1 0 0.00000 0 19 81 609 439 DP_ADD2F

-4 1 2 16 0 -1 0 0.00000 0 19 71 819 599 DP_PDFF

-4 1 2 16 0 -1 0 0.00000 0 19 57 689 439 DP_NUL

diff --git a/alliance/share/tutorials/fitpath/tex/sample_dpt-2.fig b/alliance/share/tutorials/fitpath/tex/sample_dpt-2.fig
deleted file mode 100644
index 36e2335b..00000000
--- a/alliance/share/tutorials/fitpath/tex/sample_dpt-2.fig
+++ /dev/null
@@ -1,129 +0,0 @@
-#FIG 2.1
-80 2
-6 329 449 349 469
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 334 454 344 464 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 344 454 334 464 9999 9999
--6
-6 329 369 349 389
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 334 374 344 384 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 344 374 334 384 9999 9999
--6
-6 389 129 409 149
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 394 134 404 144 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 404 134 394 144 9999 9999
--6
-6 509 129 529 149
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 514 134 524 144 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 524 134 514 144 9999 9999
--6
-6 589 129 609 149
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 594 134 604 144 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 604 134 594 144 9999 9999
--6
-6 769 129 789 149
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 774 134 784 144 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 784 134 774 144 9999 9999
--6
-6 829 129 849 149
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 834 134 844 144 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 844 134 834 144 9999 9999
--6
-6 909 129 929 149
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 914 134 924 144 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 924 134 914 144 9999 9999
--6
-6 969 409 989 429
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 974 414 984 424 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 984 414 974 424 9999 9999
--6
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 819 459 419 459 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 339 459 379 459 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 419 419 459 419 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 339 379 459 379 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 659 419 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 659 419 979 419 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 739 379 779 379 779 139 9999 9999
-2 2 1 2 -1 0 0 0 6.000 0 0 0
-	 979 619 979 139 339 139 339 619 979 619 9999 9999
-2 2 0 4 -1 0 0 0 0.000 0 0 0
-	 419 579 419 179 379 179 379 579 419 579 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 399 139 399 179 9999 9999
-2 2 0 4 -1 0 0 0 0.000 0 0 0
-	 659 579 659 259 459 259 459 579 659 579 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 519 139 519 259 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 599 139 599 259 9999 9999
-2 2 0 4 -1 0 0 0 0.000 0 0 0
-	 739 579 739 259 699 259 699 579 739 579 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 839 139 839 179 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 919 139 919 179 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 464 384 464 374 454 374 454 384 464 384 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 424 424 424 414 414 414 414 424 424 424 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 464 424 464 414 454 414 454 424 464 424 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 384 464 384 454 374 454 374 464 384 464 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 424 464 424 454 414 454 414 464 424 464 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 664 424 664 414 654 414 654 424 664 424 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 704 424 704 414 694 414 694 424 704 424 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 824 424 824 414 814 414 814 424 824 424 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 744 384 744 374 734 374 734 384 744 384 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 824 464 824 454 814 454 814 464 824 464 9999 9999
-2 2 0 4 -1 0 0 0 0.000 0 0 0
-	 939 579 939 179 819 179 819 579 939 579 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 339 649 339 669 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 1 0
-	0 0 2.000 8.000 16.000
-	 339 659 1019 659 9999 9999
-4 0 2 20 0 -1 0 1.57080 0 21 115 406 559 DP_MUX2CS

-4 0 2 20 0 -1 0 1.57080 0 21 98 564 559 DP_ADD2F

-4 0 2 20 0 -1 0 1.57080 0 21 76 725 560 DP_NUL

-4 0 2 20 0 -1 0 1.57080 0 21 85 887 560 DP_PDFF

-4 2 4 16 0 -1 0 0.00000 0 19 71 319 459 data_b[7:0]

-4 2 4 16 0 -1 0 0.00000 0 19 71 319 384 data_a[7:0]

-4 0 4 16 0 -1 0 1.57080 0 19 53 924 119 ctrl_wen

-4 0 4 16 0 -1 0 1.57080 0 19 43 844 119 ctrl_ck

-4 0 4 16 0 -1 0 1.57080 0 19 56 784 119 ctrl_zero

-4 0 4 16 0 -1 0 1.57080 0 19 65 604 119 ctrl_nover

-4 0 4 16 0 -1 0 1.57080 0 19 64 524 119 ctrl_ncout

-4 0 4 16 0 -1 0 1.57080 0 19 47 404 119 ctrl_sel

-4 0 4 16 0 -1 0 0.00000 0 19 71 999 424 data_s[7:0]

-4 1 2 16 0 -1 0 0.00000 0 19 185 939 679 Operators instanciation order

diff --git a/alliance/share/tutorials/fitpath/tex/sample_dpt-3.fig b/alliance/share/tutorials/fitpath/tex/sample_dpt-3.fig
deleted file mode 100644
index 328fa31f..00000000
--- a/alliance/share/tutorials/fitpath/tex/sample_dpt-3.fig
+++ /dev/null
@@ -1,379 +0,0 @@
-#FIG 2.1
-80 2
-6 634 269 764 334
-1 1 0 2 -1 2 0 0 0.00000 1 0.000 699 319 60 10 699 319 759 329
-1 1 0 2 -1 0 0 0 0.00000 1 0.000 699 279 60 10 699 279 759 289
-2 2 0 0 -1 1 0 1 0.000 0 0 0
-	 759 319 759 279 639 279 639 319 759 319 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 639 279 639 319 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 759 279 759 319 9999 9999
--6
-6 794 269 924 334
-1 1 0 2 -1 2 0 0 0.00000 1 0.000 859 319 60 10 859 319 919 329
-1 1 0 2 -1 0 0 0 0.00000 1 0.000 859 279 60 10 859 279 919 289
-2 2 0 0 -1 1 0 1 0.000 0 0 0
-	 919 319 919 279 799 279 799 319 919 319 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 799 279 799 319 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 919 279 919 319 9999 9999
--6
-6 634 489 764 554
-1 1 0 2 -1 2 0 0 0.00000 1 0.000 699 539 60 10 699 539 759 549
-1 1 0 2 -1 0 0 0 0.00000 1 0.000 699 499 60 10 699 499 759 509
-2 2 0 0 -1 1 0 1 0.000 0 0 0
-	 759 539 759 499 639 499 639 539 759 539 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 639 499 639 539 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 759 499 759 539 9999 9999
--6
-6 634 729 764 794
-1 1 0 2 -1 2 0 0 0.00000 1 0.000 699 779 60 10 699 779 759 789
-1 1 0 2 -1 0 0 0 0.00000 1 0.000 699 739 60 10 699 739 759 749
-2 2 0 0 -1 1 0 1 0.000 0 0 0
-	 759 779 759 739 639 739 639 779 759 779 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 639 739 639 779 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 759 739 759 779 9999 9999
--6
-6 954 269 1084 334
-1 1 0 2 -1 2 0 0 0.00000 1 0.000 1019 319 60 10 1019 319 1079 329
-1 1 0 2 -1 0 0 0 0.00000 1 0.000 1019 279 60 10 1019 279 1079 289
-2 2 0 0 -1 1 0 1 0.000 0 0 0
-	 1079 319 1079 279 959 279 959 319 1079 319 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 959 279 959 319 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 1079 279 1079 319 9999 9999
--6
-6 334 529 404 574
-1 1 0 2 -1 0 0 0 0.00000 1 0.000 369 539 30 5 369 539 399 544
-1 1 0 2 -1 2 0 0 0.00000 1 0.000 369 564 30 5 369 564 399 569
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 339 539 339 564 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 399 539 399 564 9999 9999
-2 2 0 0 -1 1 0 1 0.000 0 0 0
-	 399 564 399 539 339 539 339 564 399 564 9999 9999
--6
-6 414 529 484 574
-1 1 0 2 -1 0 0 0 0.00000 1 0.000 449 539 30 5 449 539 479 544
-1 1 0 2 -1 2 0 0 0.00000 1 0.000 449 564 30 5 449 564 479 569
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 419 539 419 564 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 479 539 479 564 9999 9999
-2 2 0 0 -1 1 0 1 0.000 0 0 0
-	 479 564 479 539 419 539 419 564 479 564 9999 9999
--6
-6 494 529 564 574
-1 1 0 2 -1 0 0 0 0.00000 1 0.000 529 539 30 5 529 539 559 544
-1 1 0 2 -1 2 0 0 0.00000 1 0.000 529 564 30 5 529 564 559 569
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 499 539 499 564 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 559 539 559 564 9999 9999
-2 2 0 0 -1 1 0 1 0.000 0 0 0
-	 559 564 559 539 499 539 499 564 559 564 9999 9999
--6
-6 829 1249 889 1309
-1 4 0 2 -1 0 0 0 0.00000 1 0.000 859 1279 25 25 834 1279 884 1279
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 834 1279 884 1279 9999 9999
-4 1 4 16 0 -1 0 0.00000 0 19 23 859 1274 OK

-4 1 4 16 0 -1 0 0.00000 0 19 23 859 1294 KO

--6
-6 474 1409 604 1474
-1 1 0 2 -1 2 0 0 0.00000 1 0.000 539 1459 60 10 539 1459 599 1469
-1 1 0 2 -1 0 0 0 0.00000 1 0.000 539 1419 60 10 539 1419 599 1429
-2 2 0 0 -1 1 0 1 0.000 0 0 0
-	 599 1459 599 1419 479 1419 479 1459 599 1459 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 479 1419 479 1459 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 599 1419 599 1459 9999 9999
--6
-6 669 1789 729 1849
-1 4 0 2 -1 0 0 0 0.00000 1 0.000 699 1819 25 25 674 1819 724 1819
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 674 1819 724 1819 9999 9999
-4 1 4 16 0 -1 0 0.00000 0 19 23 699 1814 OK

-4 1 4 16 0 -1 0 0.00000 0 19 23 699 1834 KO

--6
-6 634 1409 764 1474
-1 1 0 2 -1 2 0 0 0.00000 1 0.000 699 1459 60 10 699 1459 759 1469
-1 1 0 2 -1 0 0 0 0.00000 1 0.000 699 1419 60 10 699 1419 759 1429
-2 2 0 0 -1 1 0 1 0.000 0 0 0
-	 759 1459 759 1419 639 1419 639 1459 759 1459 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 639 1419 639 1459 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 759 1419 759 1459 9999 9999
--6
-6 474 1609 604 1674
-1 1 0 2 -1 5 0 0 0.00000 1 0.000 539 1619 60 10 539 1619 599 1629
-1 1 0 2 -1 7 0 0 0.00000 1 0.000 539 1659 60 10 539 1659 599 1669
-2 2 0 0 -1 6 0 1 0.000 0 0 0
-	 599 1659 479 1659 479 1619 599 1619 599 1659 9999 9999
-2 1 0 2 -1 5 0 0 0.000 -1 0 0
-	 479 1619 479 1659 9999 9999
-2 1 0 2 -1 5 0 0 0.000 -1 0 0
-	 599 1619 599 1659 9999 9999
--6
-6 1119 1729 1659 1759
-2 2 0 0 -1 10 0 2 0.000 0 0 0
-	 1659 1759 1659 1729 1119 1729 1119 1759 1659 1759 9999 9999
-4 0 5 20 0 -1 0 0.00000 0 19 407 1139 1749 $ proof -d sample_dpt sample_dpt_desb

--6
-6 1119 1529 1659 1559
-2 2 0 0 -1 10 0 2 0.000 0 0 0
-	 1659 1559 1659 1529 1119 1529 1119 1559 1659 1559 9999 9999
-4 0 5 20 0 -1 0 0.00000 0 19 440 1139 1549 $ desb sample_dpt sample_dpt_desb -v -i 

--6
-6 1119 1329 1659 1359
-2 2 0 0 -1 10 0 2 0.000 0 0 0
-	 1659 1359 1659 1329 1119 1329 1119 1359 1659 1359 9999 9999
-4 0 5 20 0 -1 0 0.00000 0 19 374 1139 1349 $ lynx -v -t sample_dpt sample_dpt

--6
-6 1119 1189 1659 1219
-6 1119 1189 1659 1219
-2 2 0 0 -1 10 0 2 0.000 0 0 0
-	 1659 1219 1659 1189 1119 1189 1119 1219 1659 1219 9999 9999
-4 0 5 20 0 -1 0 0.00000 0 19 451 1139 1209 $ lvx vst fne sample_dpt sample_dpt_gates

--6
--6
-6 634 1069 764 1134
-1 1 0 2 -1 5 0 0 0.00000 1 0.000 699 1079 60 10 699 1079 759 1089
-1 1 0 2 -1 7 0 0 0.00000 1 0.000 699 1119 60 10 699 1119 759 1129
-2 2 0 0 -1 6 0 1 0.000 0 0 0
-	 759 1119 639 1119 639 1079 759 1079 759 1119 9999 9999
-2 1 0 2 -1 5 0 0 0.000 -1 0 0
-	 639 1079 639 1119 9999 9999
-2 1 0 2 -1 5 0 0 0.000 -1 0 0
-	 759 1079 759 1119 9999 9999
--6
-6 349 909 409 969
-1 4 0 2 -1 0 0 0 0.00000 1 0.000 379 939 25 25 354 939 404 939
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 354 939 404 939 9999 9999
-4 1 4 16 0 -1 0 0.00000 0 19 23 379 934 OK

-4 1 4 16 0 -1 0 0.00000 0 19 23 379 954 KO

--6
-6 1119 389 1659 419
-2 2 0 0 -1 10 0 2 0.000 0 0 0
-	 1659 419 1659 389 1119 389 1119 419 1659 419 9999 9999
-4 0 5 20 0 -1 0 0.00000 0 19 231 1139 409 $ fpgen -v sample_dpt

--6
-6 1119 649 1659 679
-2 2 0 0 -1 10 0 2 0.000 0 0 0
-	 1659 679 1659 649 1119 649 1119 679 1659 679 9999 9999
-4 0 5 20 0 -1 0 0.00000 0 19 396 1139 669 $ dpr -V -p -r sample_dpt sample_dpt

--6
-6 1119 844 1659 879
-2 2 0 0 -1 10 0 2 0.000 0 0 0
-	 1659 879 1659 849 1119 849 1119 879 1659 879 9999 9999
-4 0 5 20 0 -1 0 0.00000 0 21 204 1139 869 $ druc sample_dpt

--6
-6 1119 929 1659 1019
-2 2 0 0 -1 10 0 2 0.000 0 0 0
-	 1659 1019 1659 989 1119 989 1119 1019 1659 1019 9999 9999
-4 0 5 20 0 -1 0 0.00000 0 19 440 1139 1009 $ lynx -v -f sample_dpt sample_dpt_gates

-4 0 5 20 0 -1 0 0.00000 0 19 154 1139 949 $ MBK_IN_LO=al

-4 0 5 20 0 -1 0 0.00000 0 19 165 1139 969 $ MBK_OUT_LO=al

--6
-1 1 0 2 -1 0 0 0 0.00000 1 0.000 449 479 130 15 449 479 579 494
-1 1 0 2 -1 5 0 0 0.00000 1 0.000 449 579 130 15 449 579 579 594
-1 4 0 0 -1 9 0 1 0.00000 1 0.000 859 1279 35 35 824 1279 894 1279
-1 4 0 0 -1 9 0 1 0.00000 1 0.000 379 939 35 35 344 939 414 939
-2 2 0 2 -1 1 0 0 0.000 0 0 0
-	 759 419 759 379 639 379 639 419 759 419 9999 9999
-2 2 0 2 -1 1 0 0 0.000 0 0 0
-	 759 679 759 639 639 639 639 679 759 679 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 699 329 699 379 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 699 419 699 499 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 699 549 699 639 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 699 679 699 739 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 659 419 449 479 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 444 594 659 639 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 859 329 859 549 739 639 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 694 619 699 639 704 619 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 694 479 699 499 704 479 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 694 359 699 379 704 359 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 694 719 699 739 704 719 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 854 744 859 764 864 744 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 1014 744 1019 764 1024 744 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 1014 1019 1019 1039 1024 1019 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 854 419 859 439 864 419 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 1014 419 1019 439 1024 419 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 549 444 532 455 552 454 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 539 619 560 619 541 609 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 1119 59 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 1659 59 279 59 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 319 479 319 579 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 579 479 579 579 9999 9999
-2 2 0 0 -1 4 0 1 0.000 0 0 0
-	 579 579 579 479 319 479 319 579 579 579 9999 9999
-2 2 0 0 -1 10 0 2 0.000 0 0 0
-	 759 419 759 379 639 379 639 419 759 419 9999 9999
-2 2 0 0 -1 10 0 2 0.000 0 0 0
-	 759 679 759 639 639 639 639 679 759 679 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 679 789 539 839 539 1319 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 756 1158 777 1161 759 1149 9999 9999
-2 2 0 2 -1 1 0 0 0.000 0 0 0
-	 919 1219 919 1179 799 1179 799 1219 919 1219 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 859 1219 859 1254 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 854 1159 859 1179 864 1159 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 854 1234 859 1254 864 1234 9999 9999
-2 2 0 0 -1 10 0 2 0.000 0 0 0
-	 919 1219 919 1179 799 1179 799 1219 919 1219 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 739 544 859 639 859 1179 9999 9999
-2 2 0 2 -1 1 0 0 0.000 0 0 0
-	 599 1359 599 1319 479 1319 479 1359 599 1359 9999 9999
-2 2 0 2 -1 1 0 0 0.000 0 0 0
-	 599 1559 599 1519 479 1519 479 1559 599 1559 9999 9999
-2 2 0 2 -1 1 0 0 0.000 0 0 0
-	 759 1759 759 1719 639 1719 639 1759 759 1759 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 539 1359 539 1419 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 539 1469 539 1519 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 539 1559 539 1619 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 539 1669 659 1719 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 699 1759 699 1794 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 534 1299 539 1319 544 1299 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 534 1399 539 1419 544 1399 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 534 1499 539 1519 544 1499 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 534 1599 539 1619 544 1599 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 694 1774 699 1794 704 1774 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 603 1701 624 1704 606 1692 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 877 1679 859 1689 879 1689 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 699 1469 579 1519 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 645 1486 629 1499 649 1495 9999 9999
-2 2 0 0 -1 4 0 1 0.000 0 0 0
-	 614 1654 614 1634 464 1634 464 1654 614 1654 9999 9999
-2 2 0 0 -1 10 0 2 0.000 0 0 0
-	 599 1359 599 1319 479 1319 479 1359 599 1359 9999 9999
-2 2 0 0 -1 10 0 2 0.000 0 0 0
-	 599 1559 599 1519 479 1519 479 1559 599 1559 9999 9999
-2 2 0 0 -1 10 0 2 0.000 0 0 0
-	 759 1759 759 1719 639 1719 639 1759 759 1759 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 1019 329 1019 1649 739 1719 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 534 1019 539 1039 544 1019 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 854 1024 859 1044 864 1024 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 1014 1304 1019 1324 1024 1304 9999 9999
-2 2 0 2 -1 0 0 0 0.000 0 0 0
-	 1659 1879 1659 19 279 19 279 1879 1659 1879 9999 9999
-2 2 0 2 -1 1 0 0 0.000 0 0 0
-	 759 1019 759 979 639 979 639 1019 759 1019 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 699 1019 699 1079 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 694 959 699 979 704 959 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 694 1059 699 1079 704 1059 9999 9999
-2 2 0 0 -1 4 0 1 0.000 0 0 0
-	 774 1114 774 1094 624 1094 624 1114 774 1114 9999 9999
-2 2 0 0 -1 10 0 2 0.000 0 0 0
-	 759 1019 759 979 639 979 639 1019 759 1019 9999 9999
-2 2 0 2 -1 1 0 0 0.000 0 0 0
-	 439 879 439 839 319 839 319 879 439 879 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 379 879 379 914 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 374 894 379 914 384 894 9999 9999
-2 2 0 0 -1 10 0 2 0.000 0 0 0
-	 439 879 439 839 319 839 319 879 439 879 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 659 784 379 839 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 699 789 699 974 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 699 1129 819 1179 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 506 808 489 819 509 818 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 1119 19 1119 1879 9999 9999
-4 1 4 20 0 -1 0 0.00000 0 22 58 699 409 FpGen

-4 1 4 16 0 -1 0 0.00000 0 19 86 699 314 sample_dpt.c

-4 1 4 16 0 -1 0 0.00000 0 19 99 859 314 sample_dpt.dpr

-4 1 4 16 0 -1 0 0.00000 0 19 98 699 534 sample_dpt.vst

-4 1 4 16 0 -1 0 0.00000 0 19 94 699 774 sample_dpt.ap

-4 1 4 20 0 -1 0 0.00000 0 22 41 699 669 DPR

-4 1 4 16 0 -1 0 0.00000 0 19 102 1019 314 sample_dpt.vbe

-4 0 5 20 0 -1 0 0.00000 0 19 176 1139 299 $ MBK_WORK_LIB=.

-4 0 5 20 0 -1 0 0.00000 0 19 165 1139 279 $ MBK_OUT_PH=ap

-4 0 5 20 0 -1 0 0.00000 0 19 154 1139 259 $ MBK_IN_PH=ap

-4 0 5 20 0 -1 0 0.00000 0 19 176 1139 239 $ MBK_OUT_LO=vst

-4 0 5 20 0 -1 0 0.00000 0 19 165 1139 219 $ MBK_IN_LO=vst

-4 0 5 20 0 -1 0 0.00000 0 19 209 1139 199 $ FPGEN_LIB=./mclib

-4 0 5 20 0 -1 0 0.00000 0 19 440 1139 319 $ MBK_CATA_LIB=$TOP/cells/fitpath/fplib\

-4 0 5 20 0 -1 0 0.00000 0 19 286 1139 339 :$TOP/cells/rsa:$FPGEN_LIB

-4 0 5 20 0 -1 0 0.00000 0 19 429 1139 119 $ export FPGEN_LIB MBK_IN_LO MBK_OUT_LO

-4 0 5 20 0 -1 0 0.00000 0 19 319 1139 139 $ export MBK_IN_PH MBK_OUT_PH

-4 0 5 20 0 -1 0 0.00000 0 19 374 1139 159 $ export MBK_WORK_LIB MBK_CATA_LIB

-4 0 5 20 0 -1 0 0.00000 0 19 253 1139 179 $ export MBK_CATAL_NAME

-4 1 2 20 0 -1 0 0.00000 0 21 174 699 49 Methology Schematic

-4 1 2 20 0 -1 0 0.00000 0 21 204 1399 49 Bourne Shell Commands

-4 0 5 20 0 -1 0 0.00000 0 19 242 1139 359 $ MBK_CATAL_NAME=CATAL

-4 1 2 16 0 -1 1 0.00000 0 19 86 449 519 FPGEN_LIB

-4 1 4 16 0 -1 0 0.00000 0 19 26 529 559 *.ap

-4 1 4 16 0 -1 0 0.00000 0 19 30 449 559 *.vst

-4 1 4 16 0 -1 0 0.00000 0 19 34 369 559 *.vbe

-4 1 4 20 0 -1 0 0.00000 0 22 37 859 1209 LVX

-4 1 4 20 0 -1 0 0.00000 0 22 63 539 1349 Lynx -t

-4 1 4 20 0 -1 0 0.00000 0 22 69 699 1749 PROOF

-4 1 4 20 0 -1 0 0.00000 0 22 53 539 1549 DESB

-4 1 4 16 0 -1 0 0.00000 0 19 142 539 1649 sample_dpt_desb.vbe

-4 1 4 16 0 -1 0 0.00000 0 19 92 699 1454 sample_dpt.inf

-4 1 4 20 0 -1 0 0.00000 0 22 63 699 1009 Lynx -f

-4 1 4 20 0 -1 0 0.00000 0 23 49 379 869 DRuC

-4 1 4 16 0 -1 0 0.00000 0 19 133 699 1109 sample_dpt_gates.al

-4 1 4 16 0 -1 0 0.00000 0 19 89 539 1454 sample_dpt.al

diff --git a/alliance/share/tutorials/fitpath/tex/sample_dpt-4.fig b/alliance/share/tutorials/fitpath/tex/sample_dpt-4.fig
deleted file mode 100644
index df122097..00000000
--- a/alliance/share/tutorials/fitpath/tex/sample_dpt-4.fig
+++ /dev/null
@@ -1,524 +0,0 @@
-#FIG 2.1
-80 2
-6 324 409 374 469
-2 2 0 4 -1 0 0 0 0.000 0 0 0
-	 369 464 369 414 329 414 329 464 369 464 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 329 414 369 439 329 464 9999 9999
--6
-6 334 334 364 384
-1 4 0 4 -1 0 0 0 0.00000 1 0.000 349 374 5 5 349 369 349 379
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 339 339 349 359 359 339 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 349 339 339 339 339 349 349 369 359 349 359 339 349 339 9999 9999
--6
-6 334 259 364 299
-1 4 0 4 -1 0 0 0 0.00000 1 0.000 349 289 5 5 349 284 349 294
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 339 264 359 264 349 284 339 264 349 264 9999 9999
--6
-6 439 419 479 459
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 444 439 474 439 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 459 424 459 454 9999 9999
--6
-6 339 229 359 249
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 344 234 354 244 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 354 234 344 244 9999 9999
--6
-6 324 709 374 769
-2 2 0 4 -1 0 0 0 0.000 0 0 0
-	 369 764 369 714 329 714 329 764 369 764 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 329 714 369 739 329 764 9999 9999
--6
-6 564 709 614 769
-5 1 0 4 -1 0 0 0 0.000 1 0 0 604.625 739.000 599 714 579 739 599 764
-1 4 0 4 -1 0 0 0 0.00000 0 -0.000 574 739 5 5 579 739 569 739
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 599 714 609 714 609 764 599 764 9999 9999
--6
-6 439 719 479 759
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 444 739 474 739 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 459 724 459 754 9999 9999
--6
-6 309 549 329 569
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 314 554 324 564 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 324 554 314 564 9999 9999
--6
-6 309 589 329 609
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 314 594 324 604 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 324 594 314 604 9999 9999
--6
-6 324 789 374 849
-2 2 0 4 -1 0 0 0 0.000 0 0 0
-	 369 844 369 794 329 794 329 844 369 844 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 329 794 369 819 329 844 9999 9999
--6
-6 564 789 614 849
-1 4 0 4 -1 0 0 0 0.00000 1 0.000 604 819 5 5 599 819 609 819
-3 2 0 4 -1 0 0 0 0.000 0 0
-	 569 794 579 819 569 844 9999 9999
-	 -30.000 540.000 576.500 807.355 579.000 813.605 579.000 824.395
-	 576.500 830.645 -30.000 540.000
-3 2 0 4 -1 0 0 0 0.000 0 0
-	 569 794 589 804 599 819 9999 9999
-	 -30.000 540.000 580.904 798.767 585.904 801.267 591.496 806.203
-	 593.996 809.953 -30.000 540.000
-3 2 0 4 -1 0 0 0 0.000 0 0
-	 569 844 589 834 599 819 9999 9999
-	 -30.000 540.000 580.904 839.233 585.904 836.733 591.496 831.797
-	 593.996 828.047 -30.000 540.000
--6
-6 439 799 479 839
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 444 819 474 819 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 459 804 459 834 9999 9999
--6
-6 324 629 374 689
-2 2 0 4 -1 0 0 0 0.000 0 0 0
-	 369 684 369 634 329 634 329 684 369 684 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 329 634 369 659 329 684 9999 9999
--6
-6 564 629 614 689
-1 4 0 4 -1 0 0 0 0.00000 1 0.000 604 659 5 5 599 659 609 659
-3 2 0 4 -1 0 0 0 0.000 0 0
-	 569 634 579 659 569 684 9999 9999
-	 -30.000 380.000 576.500 647.355 579.000 653.605 579.000 664.395
-	 576.500 670.645 -30.000 380.000
-3 2 0 4 -1 0 0 0 0.000 0 0
-	 569 634 589 644 599 659 9999 9999
-	 -30.000 380.000 580.904 638.767 585.904 641.267 591.496 646.203
-	 593.996 649.953 -30.000 380.000
-3 2 0 4 -1 0 0 0 0.000 0 0
-	 569 684 589 674 599 659 9999 9999
-	 -30.000 380.000 580.904 679.233 585.904 676.733 591.496 671.797
-	 593.996 668.047 -30.000 380.000
--6
-6 439 639 479 679
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 444 659 474 659 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 459 644 459 674 9999 9999
--6
-6 664 409 714 469
-2 2 0 4 -1 0 0 0 0.000 0 0 0
-	 709 464 709 414 669 414 669 464 709 464 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 669 414 679 424 689 414 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 674 429 679 429 679 439 684 439 9999 9999
--6
-6 659 334 689 384
-1 4 0 4 -1 0 0 0 0.00000 1 0.000 674 374 5 5 674 369 674 379
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 664 339 674 359 684 339 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 674 339 664 339 664 349 674 369 684 349 684 339 674 339 9999 9999
--6
-6 689 334 719 384
-1 4 0 4 -1 0 0 0 0.00000 1 0.000 704 374 5 5 704 369 704 379
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 694 339 704 359 714 339 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 704 339 694 339 694 349 704 369 714 349 714 339 704 339 9999 9999
--6
-6 659 259 689 299
-1 4 0 4 -1 0 0 0 0.00000 1 0.000 674 289 5 5 674 284 674 294
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 664 264 684 264 674 284 664 264 674 264 9999 9999
--6
-6 689 259 719 299
-1 4 0 4 -1 0 0 0 0.00000 1 0.000 704 289 5 5 704 284 704 294
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 694 264 714 264 704 284 694 264 704 264 9999 9999
--6
-6 664 229 684 249
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 669 234 679 244 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 679 234 669 244 9999 9999
--6
-6 694 229 714 249
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 699 234 709 244 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 709 234 699 244 9999 9999
--6
-6 664 709 714 769
-2 2 0 4 -1 0 0 0 0.000 0 0 0
-	 709 764 709 714 669 714 669 764 709 764 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 669 714 679 724 689 714 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 674 729 679 729 679 739 684 739 9999 9999
--6
-6 709 569 729 589
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 714 574 724 584 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 724 574 714 584 9999 9999
--6
-6 664 789 714 849
-2 2 0 4 -1 0 0 0 0.000 0 0 0
-	 709 844 709 794 669 794 669 844 709 844 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 669 794 679 804 689 794 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 674 809 679 809 679 819 684 819 9999 9999
--6
-6 664 629 714 689
-2 2 0 4 -1 0 0 0 0.000 0 0 0
-	 709 684 709 634 669 634 669 684 709 684 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 669 634 679 644 689 634 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 674 649 679 649 679 659 684 659 9999 9999
--6
-6 629 229 649 249
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 634 234 644 244 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 644 234 634 244 9999 9999
--6
-6 469 229 489 249
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 474 234 484 244 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 484 234 474 244 9999 9999
--6
-6 509 229 529 249
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 514 234 524 244 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 524 234 514 244 9999 9999
--6
-6 829 329 1194 829
-2 1 0 2 -1 0 0 0 0.000 7 1 0
-	0 0 2.000 8.000 16.000
-	 859 699 889 759 9999 9999
-2 1 0 2 -1 0 0 0 0.000 7 1 0
-	0 0 2.000 8.000 16.000
-	 859 699 889 719 9999 9999
-2 1 0 2 -1 0 0 0 0.000 7 1 0
-	0 0 2.000 8.000 16.000
-	 859 699 889 679 9999 9999
-2 1 0 2 -1 0 0 0 0.000 7 1 0
-	0 0 2.000 8.000 16.000
-	 859 699 889 639 9999 9999
-2 1 0 2 -1 0 0 0 0.000 7 1 0
-	0 0 2.000 8.000 16.000
-	 859 699 889 599 9999 9999
-2 2 0 2 -1 0 0 0 0.000 0 0 0
-	 929 769 929 749 909 749 909 769 929 769 9999 9999
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-2 2 0 1 -1 1 0 2 0.000 0 0 0
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-2 2 0 1 -1 1 0 2 0.000 0 0 0
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-2 2 0 1 -1 1 0 2 0.000 0 0 0
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-2 2 0 1 -1 1 0 2 0.000 0 0 0
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-2 2 0 1 -1 1 0 2 0.000 0 0 0
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-2 2 0 1 -1 1 0 2 0.000 0 0 0
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-2 2 0 1 -1 1 0 2 0.000 0 0 0
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-2 2 0 1 -1 1 0 2 0.000 0 0 0
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-2 2 0 1 -1 1 0 4 0.000 0 0 0
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-2 2 0 1 -1 1 0 4 0.000 0 0 0
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-2 2 1 2 -1 0 0 0 6.000 0 0 0
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-3 0 0 2 -1 0 0 0 0.000 0 0
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-3 0 0 2 -1 0 0 0 0.000 0 0
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-4 1 4 16 0 -1 0 1.57080 0 19 103 849 699 Virtual Terminal

-4 0 4 16 0 -1 0 0.00000 0 19 24 1059 349 vdd

-4 0 4 16 0 -1 0 0.00000 0 19 24 1059 809 vss

-4 0 2 16 0 -1 0 0.00000 0 19 93 1099 584 10 tracks/Slice

--6
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
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-	 379 239 379 489 9999 9999
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-	 559 399 559 489 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 319 239 379 239 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 319 319 379 319 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 319 599 339 599 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 359 579 399 579 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 319 559 399 559 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
-	 404 564 404 554 394 554 394 564 404 564 9999 9999
-2 2 0 0 -1 0 0 21 0.000 0 0 0
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-2 2 0 0 -1 0 0 21 0.000 0 0 0
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-2 2 0 0 -1 0 0 21 0.000 0 0 0
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-2 2 0 0 -1 0 0 21 0.000 0 0 0
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-2 2 0 0 -1 0 0 21 0.000 0 0 0
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-2 1 0 2 -1 0 0 0 0.000 -1 0 0
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-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 379 529 379 859 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 559 529 559 859 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
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-2 1 0 2 -1 0 0 0 0.000 -1 0 0
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-2 1 0 2 -1 0 0 0 0.000 -1 0 0
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-2 1 0 2 -1 0 0 0 0.000 -1 0 0
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-2 1 0 2 -1 0 0 0 0.000 -1 0 0
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-2 2 0 0 -1 0 0 21 0.000 0 0 0
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-2 1 0 2 -1 0 0 0 0.000 -1 0 0
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-2 1 0 2 -1 0 0 0 0.000 -1 0 0
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-2 1 0 2 -1 0 0 0 0.000 -1 0 0
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-2 1 0 2 -1 0 0 0 0.000 -1 0 0
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-2 1 0 2 -1 0 0 0 0.000 -1 0 0
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-2 1 0 2 -1 0 0 0 0.000 -1 0 0
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-2 1 0 2 -1 0 0 0 0.000 -1 0 0
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-2 1 0 2 -1 0 0 0 0.000 -1 0 0
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-2 1 0 1 -1 0 0 0 0.000 -1 0 0
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-2 1 0 1 -1 0 0 0 0.000 -1 0 0
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-2 1 0 1 -1 0 0 0 0.000 -1 0 0
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-2 2 0 0 -1 0 0 21 0.000 0 0 0
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-2 1 0 1 -1 0 0 0 0.000 -1 0 0
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-2 1 0 1 -1 0 0 0 0.000 -1 0 0
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-2 1 0 1 -1 0 0 0 0.000 -1 0 0
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-2 1 0 1 -1 0 0 0 0.000 -1 0 0
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-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 349 529 349 539 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 349 619 349 634 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
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-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 349 764 349 794 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 674 239 674 264 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 674 294 674 339 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
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-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 704 239 704 264 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 704 294 704 339 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 704 379 704 414 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 674 464 674 489 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 704 464 704 489 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 674 619 674 634 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
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-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 674 529 674 539 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 704 529 704 539 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 674 684 674 714 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
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-2 1 0 1 -1 0 0 0 0.000 -1 0 0
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-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 704 764 704 794 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 479 239 479 399 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 519 239 519 399 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
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-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 739 619 759 619 839 809 859 809 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 1 1
-	0 0 2.000 8.000 16.000
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-	 319 899 379 899 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 1 1
-	0 0 2.000 8.000 16.000
-	0 0 2.000 8.000 16.000
-	 379 899 559 899 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 1 1
-	0 0 2.000 8.000 16.000
-	0 0 2.000 8.000 16.000
-	 559 899 619 899 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 1 1
-	0 0 2.000 8.000 16.000
-	0 0 2.000 8.000 16.000
-	 659 899 719 899 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 319 879 319 1019 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 379 879 379 1019 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 559 879 559 1019 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 619 879 619 1019 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 659 879 659 1019 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 719 879 719 1019 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 299 859 139 859 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
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-2 1 0 1 -1 0 0 0 0.000 -1 0 0
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-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 299 699 179 699 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
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-2 1 0 1 -1 0 0 0 0.000 -1 0 0
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-2 1 0 1 -1 0 0 0 0.000 -1 0 0
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-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 139 859 139 239 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 299 779 179 779 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 179 529 179 859 9999 9999
-2 1 1 2 -1 0 0 0 6.000 -1 0 0
-	 169 529 729 529 9999 9999
-2 1 1 2 -1 0 0 0 6.000 -1 0 0
-	 169 489 729 489 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 179 239 179 489 9999 9999
-2 2 0 0 -1 10 0 2 0.000 0 0 0
-	 619 619 619 539 319 539 319 619 619 619 9999 9999
-2 2 0 0 -1 10 0 2 0.000 0 0 0
-	 719 619 719 539 659 539 659 619 719 619 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 1 0
-	0 0 2.000 8.000 16.000
-	 319 1059 759 1059 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 1 0
-	0 0 2.000 8.000 16.000
-	 99 859 99 199 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 89 859 109 859 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 319 1049 319 1069 9999 9999
-4 2 4 16 0 -1 0 0.00000 0 19 60 299 604 data_b[3]

-4 2 4 16 0 -1 0 0.00000 0 19 60 299 564 data_a[3]

-4 0 4 16 0 -1 0 0.00000 0 19 60 739 584 data_s[3]

-4 0 4 16 0 -1 0 1.57080 0 19 53 709 219 ctrl_wen

-4 0 4 16 0 -1 0 1.57080 0 19 43 679 219 ctrl_ck

-4 0 4 16 0 -1 0 1.57080 0 19 56 644 219 ctrl_zero

-4 0 4 16 0 -1 0 1.57080 0 19 65 524 219 ctrl_nover

-4 0 4 16 0 -1 0 1.57080 0 19 47 354 219 ctrl_sel

-4 0 4 16 0 -1 0 1.57080 0 19 64 484 219 ctrl_ncout

-4 0 2 16 0 -1 0 1.57080 0 19 89 359 999 DP_MUX2CS

-4 0 2 16 0 -1 0 1.57080 0 19 81 479 999 DP_ADD2F

-4 0 2 16 0 -1 0 1.57080 0 19 57 599 999 DP_NUL

-4 0 2 16 0 -1 0 1.57080 0 19 71 699 999 DP_PDFF

-4 0 4 16 0 -1 0 1.57080 0 19 106 644 999 Routing Channel

-4 1 2 20 0 -1 0 0.00000 0 21 9 199 824 0

-4 1 2 20 0 -1 0 0.00000 0 21 9 199 744 1

-4 1 2 20 0 -1 0 0.00000 0 21 9 199 664 2

-4 1 2 20 0 -1 0 0.00000 0 21 9 199 584 3

-4 1 2 20 0 -1 0 0.00000 0 21 9 199 444 7

-4 1 2 20 0 -1 0 0.00000 0 21 9 199 364 8

-4 1 2 20 0 -1 0 0.00000 0 21 9 199 284 9

-4 1 2 16 0 -1 0 1.57080 0 19 112 164 579 8 Slices for Datas

-4 1 2 16 0 -1 0 1.57080 0 19 122 164 319 2 Slices for Buffers

-4 1 2 20 0 -1 0 0.00000 0 21 81 759 1079 Operators

-4 1 2 20 0 -1 0 1.57080 0 21 45 89 199 Slices

diff --git a/alliance/share/tutorials/fitpath/tex/sample_dpt-5.fig b/alliance/share/tutorials/fitpath/tex/sample_dpt-5.fig
deleted file mode 100644
index 29de8e9d..00000000
--- a/alliance/share/tutorials/fitpath/tex/sample_dpt-5.fig
+++ /dev/null
@@ -1,178 +0,0 @@
-#FIG 2.1
-80 2
-6 394 279 424 319
-1 4 0 4 -1 0 0 0 0.00000 1 0.000 409 309 5 5 409 304 409 314
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 399 284 419 284 409 304 399 284 409 284 9999 9999
--6
-6 394 354 424 404
-1 4 0 4 -1 0 0 0 0.00000 1 0.000 409 394 5 5 409 389 409 399
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
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-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 409 359 399 359 399 369 409 389 419 369 419 359 409 359 9999 9999
--6
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-2 2 0 4 -1 0 0 0 0.000 0 0 0
-	 429 804 429 754 389 754 389 804 429 804 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 389 754 429 779 389 804 9999 9999
--6
-6 384 669 434 729
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-	 429 724 429 674 389 674 389 724 429 724 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 389 674 429 699 389 724 9999 9999
--6
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-	 429 644 429 594 389 594 389 644 429 644 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 389 594 429 619 389 644 9999 9999
--6
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-2 2 0 4 -1 0 0 0 0.000 0 0 0
-	 429 564 429 514 389 514 389 564 429 564 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 389 514 429 539 389 564 9999 9999
--6
-6 469 879 489 1004
-4 0 5 16 0 -1 0 1.57080 0 18 45 489 1004 Slice

-4 0 2 16 0 -1 0 1.57080 0 19 67 489 949 Parameter

--6
-6 509 599 529 724
-4 0 5 16 0 -1 0 1.57080 0 18 45 529 724 Width

-4 0 2 16 0 -1 0 1.57080 0 19 67 529 669 Parameter

--6
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-	 379 419 439 419 9999 9999
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-2 1 0 1 -1 0 0 0 0.000 -1 0 0
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-2 1 0 1 -1 0 0 0 0.000 -1 0 0
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-4 1 2 16 0 -1 0 0.00000 0 19 44 409 944 Empty

-4 1 2 16 0 -1 0 0.00000 0 19 44 409 1024 Empty

-4 1 2 16 0 -1 0 0.00000 0 19 44 409 864 Empty

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diff --git a/alliance/share/tutorials/fitpath/tex/sample_dpt-6.fig b/alliance/share/tutorials/fitpath/tex/sample_dpt-6.fig
deleted file mode 100644
index ad0c0a1a..00000000
--- a/alliance/share/tutorials/fitpath/tex/sample_dpt-6.fig
+++ /dev/null
@@ -1,379 +0,0 @@
-#FIG 2.1
-80 2
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-1 4 0 4 -1 0 0 0 0.00000 1 0.000 529 309 5 5 529 304 529 314
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--6
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-2 1 0 2 -1 0 0 0 0.000 -1 0 0
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--6
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--6
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--6
-6 469 989 489 1009
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--6
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--6
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--6
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--6
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--6
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--6
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--6
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--6
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--6
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--6
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--6
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-	 484 754 474 764 9999 9999
--6
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-	 474 794 484 804 9999 9999
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-	 484 794 474 804 9999 9999
--6
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--6
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-	 549 724 549 674 509 674 509 724 549 724 9999 9999
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--6
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--6
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--6
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diff --git a/alliance/share/tutorials/fitpath/tex/trace-desb-1.ps b/alliance/share/tutorials/fitpath/tex/trace-desb-1.ps
deleted file mode 100644
index 0260b04c..00000000
--- a/alliance/share/tutorials/fitpath/tex/trace-desb-1.ps
+++ /dev/null
@@ -1,2607 +0,0 @@
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-
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-    bcount 128 ge
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-      0 1 bcount 128 sub
-      { currentfile buffer readhexstring pop pop
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-        /rgbval cmap buffer 0 get 1 getinterval store
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-        % and put it in position i in block
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-%
-% Compression made this file 15.76% of the uncompressed size.
-%
-
-
-showpage
-
-% stop using temporary dictionary
-end
-
-% restore original state
-origstate restore
-
-%%Trailer
diff --git a/alliance/share/tutorials/fitpath/tex/trace-dpr-1.ps b/alliance/share/tutorials/fitpath/tex/trace-dpr-1.ps
deleted file mode 100644
index 06370a55..00000000
--- a/alliance/share/tutorials/fitpath/tex/trace-dpr-1.ps
+++ /dev/null
@@ -1,2245 +0,0 @@
-%!PS-Adobe-2.0 EPSF-2.0
-%%Title: /users/outil2/fitpath/ln.S/tutorial/trace-dpr-1.ps
-%%Creator: XV Version 3.10a  Rev: 12/29/94  -  by John Bradley
-%%BoundingBox: 0 0 612 792
-%%Pages: 1
-%%DocumentFonts:
-%%EndComments
-%%EndProlog
-
-%%Page: 1 1
-
-% remember original state
-/origstate save def
-
-% build a temporary dictionary
-20 dict begin
-
-% define space for color conversions
-/grays 612 string def  % space for gray scale line
-/npixls 0 def
-/rgbindx 0 def
-
-% lower left corner
-0 0 translate
-
-% size of image (on paper, in 1/72inch coords)
-612.00000 792.00000 scale
-
-% define the colormap
-/cmap 6 string def
-
-
-% load up the colormap
-currentfile cmap readhexstring
-00 44 88 bf e5 ff 
-pop pop   % lose return values from readhexstring
-
-
-% rlecmapimage expects to have 'w h bits matrix' on stack
-/rlecmapimage {
-  /buffer 1 string def
-  /rgbval 3 string def
-  /block  384 string def
-
-  % proc to read a block from file, and return RGB data
-  { currentfile buffer readhexstring pop
-    /bcount exch 0 get store
-    bcount 128 ge
-    {  % it's a non-run block
-      0 1 bcount 128 sub
-      { currentfile buffer readhexstring pop pop
-
-        % look up value in gray map
-        /rgbval cmap buffer 0 get 1 getinterval store
-
-        % and put it in position i in block
-        block exch rgbval putinterval
-      } for
-      block  0  bcount 127 sub  getinterval
-    }
-
-    { % else it's a run block
-      currentfile buffer readhexstring pop pop
-
-      % look up value in graymap
-      /rgbval cmap buffer 0 get 1 getinterval store
-
-      0 1 bcount { block exch rgbval putinterval } for
-
-      block 0 bcount 1 add getinterval
-    } ifelse
-  } % end of proc
-  image
-} bind def
-
-
-612 792 8			% dimensions of data
-[612 0 0 -792 0 792]		% mapping matrix
-rlecmapimage
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-
-%
-% Compression made this file 13.33% of the uncompressed size.
-%
-
-
-showpage
-
-% stop using temporary dictionary
-end
-
-% restore original state
-origstate restore
-
-%%Trailer
diff --git a/alliance/share/tutorials/fitpath/tex/trace-druc-1.ps b/alliance/share/tutorials/fitpath/tex/trace-druc-1.ps
deleted file mode 100644
index 2f3a6347..00000000
--- a/alliance/share/tutorials/fitpath/tex/trace-druc-1.ps
+++ /dev/null
@@ -1,1881 +0,0 @@
-%!PS-Adobe-2.0 EPSF-2.0
-%%Title: /users/outil2/fitpath/ln.S/tutorial/trace-druc-1.ps
-%%Creator: XV Version 3.10a  Rev: 12/29/94  -  by John Bradley
-%%BoundingBox: 0 0 612 792
-%%Pages: 1
-%%DocumentFonts:
-%%EndComments
-%%EndProlog
-
-%%Page: 1 1
-
-% remember original state
-/origstate save def
-
-% build a temporary dictionary
-20 dict begin
-
-% define space for color conversions
-/grays 612 string def  % space for gray scale line
-/npixls 0 def
-/rgbindx 0 def
-
-% lower left corner
-0 0 translate
-
-% size of image (on paper, in 1/72inch coords)
-612.00000 792.00000 scale
-
-% define the colormap
-/cmap 6 string def
-
-
-% load up the colormap
-currentfile cmap readhexstring
-00 44 88 bf e5 ff 
-pop pop   % lose return values from readhexstring
-
-
-% rlecmapimage expects to have 'w h bits matrix' on stack
-/rlecmapimage {
-  /buffer 1 string def
-  /rgbval 3 string def
-  /block  384 string def
-
-  % proc to read a block from file, and return RGB data
-  { currentfile buffer readhexstring pop
-    /bcount exch 0 get store
-    bcount 128 ge
-    {  % it's a non-run block
-      0 1 bcount 128 sub
-      { currentfile buffer readhexstring pop pop
-
-        % look up value in gray map
-        /rgbval cmap buffer 0 get 1 getinterval store
-
-        % and put it in position i in block
-        block exch rgbval putinterval
-      } for
-      block  0  bcount 127 sub  getinterval
-    }
-
-    { % else it's a run block
-      currentfile buffer readhexstring pop pop
-
-      % look up value in graymap
-      /rgbval cmap buffer 0 get 1 getinterval store
-
-      0 1 bcount { block exch rgbval putinterval } for
-
-      block 0 bcount 1 add getinterval
-    } ifelse
-  } % end of proc
-  image
-} bind def
-
-
-612 792 8			% dimensions of data
-[612 0 0 -792 0 792]		% mapping matrix
-rlecmapimage
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-
-%
-% Compression made this file 10.26% of the uncompressed size.
-%
-
-
-showpage
-
-% stop using temporary dictionary
-end
-
-% restore original state
-origstate restore
-
-%%Trailer
diff --git a/alliance/share/tutorials/fitpath/tex/trace-fpgen-1.ps b/alliance/share/tutorials/fitpath/tex/trace-fpgen-1.ps
deleted file mode 100644
index 7d6717e5..00000000
--- a/alliance/share/tutorials/fitpath/tex/trace-fpgen-1.ps
+++ /dev/null
@@ -1,2369 +0,0 @@
-%!PS-Adobe-2.0 EPSF-2.0
-%%Title: /users/outil2/fitpath/ln.S/tutorial/trace-fpgen-1.ps
-%%Creator: XV Version 3.10a  Rev: 12/29/94  -  by John Bradley
-%%BoundingBox: 0 0 612 792
-%%Pages: 1
-%%DocumentFonts:
-%%EndComments
-%%EndProlog
-
-%%Page: 1 1
-
-% remember original state
-/origstate save def
-
-% build a temporary dictionary
-20 dict begin
-
-% define space for color conversions
-/grays 612 string def  % space for gray scale line
-/npixls 0 def
-/rgbindx 0 def
-
-% lower left corner
-0 0 translate
-
-% size of image (on paper, in 1/72inch coords)
-612.00000 792.00000 scale
-
-% define the colormap
-/cmap 6 string def
-
-
-% load up the colormap
-currentfile cmap readhexstring
-00 44 88 bf e5 ff 
-pop pop   % lose return values from readhexstring
-
-
-% rlecmapimage expects to have 'w h bits matrix' on stack
-/rlecmapimage {
-  /buffer 1 string def
-  /rgbval 3 string def
-  /block  384 string def
-
-  % proc to read a block from file, and return RGB data
-  { currentfile buffer readhexstring pop
-    /bcount exch 0 get store
-    bcount 128 ge
-    {  % it's a non-run block
-      0 1 bcount 128 sub
-      { currentfile buffer readhexstring pop pop
-
-        % look up value in gray map
-        /rgbval cmap buffer 0 get 1 getinterval store
-
-        % and put it in position i in block
-        block exch rgbval putinterval
-      } for
-      block  0  bcount 127 sub  getinterval
-    }
-
-    { % else it's a run block
-      currentfile buffer readhexstring pop pop
-
-      % look up value in graymap
-      /rgbval cmap buffer 0 get 1 getinterval store
-
-      0 1 bcount { block exch rgbval putinterval } for
-
-      block 0 bcount 1 add getinterval
-    } ifelse
-  } % end of proc
-  image
-} bind def
-
-
-612 792 8			% dimensions of data
-[612 0 0 -792 0 792]		% mapping matrix
-rlecmapimage
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-
-%
-% Compression made this file 14.15% of the uncompressed size.
-%
-
-
-showpage
-
-% stop using temporary dictionary
-end
-
-% restore original state
-origstate restore
-
-%%Trailer
diff --git a/alliance/share/tutorials/fitpath/tex/trace-logic-1.ps b/alliance/share/tutorials/fitpath/tex/trace-logic-1.ps
deleted file mode 100644
index 3a58f511..00000000
--- a/alliance/share/tutorials/fitpath/tex/trace-logic-1.ps
+++ /dev/null
@@ -1,2202 +0,0 @@
-%!PS-Adobe-2.0 EPSF-2.0
-%%Title: /users/outil2/fitpath/ln.S/tutorial/trace-logic-1.ps
-%%Creator: XV Version 3.10a  Rev: 12/29/94  -  by John Bradley
-%%BoundingBox: 0 0 612 792
-%%Pages: 1
-%%DocumentFonts:
-%%EndComments
-%%EndProlog
-
-%%Page: 1 1
-
-% remember original state
-/origstate save def
-
-% build a temporary dictionary
-20 dict begin
-
-% define space for color conversions
-/grays 612 string def  % space for gray scale line
-/npixls 0 def
-/rgbindx 0 def
-
-% lower left corner
-0 0 translate
-
-% size of image (on paper, in 1/72inch coords)
-612.00000 792.00000 scale
-
-% define the colormap
-/cmap 6 string def
-
-
-% load up the colormap
-currentfile cmap readhexstring
-00 44 88 bf e5 ff 
-pop pop   % lose return values from readhexstring
-
-
-% rlecmapimage expects to have 'w h bits matrix' on stack
-/rlecmapimage {
-  /buffer 1 string def
-  /rgbval 3 string def
-  /block  384 string def
-
-  % proc to read a block from file, and return RGB data
-  { currentfile buffer readhexstring pop
-    /bcount exch 0 get store
-    bcount 128 ge
-    {  % it's a non-run block
-      0 1 bcount 128 sub
-      { currentfile buffer readhexstring pop pop
-
-        % look up value in gray map
-        /rgbval cmap buffer 0 get 1 getinterval store
-
-        % and put it in position i in block
-        block exch rgbval putinterval
-      } for
-      block  0  bcount 127 sub  getinterval
-    }
-
-    { % else it's a run block
-      currentfile buffer readhexstring pop pop
-
-      % look up value in graymap
-      /rgbval cmap buffer 0 get 1 getinterval store
-
-      0 1 bcount { block exch rgbval putinterval } for
-
-      block 0 bcount 1 add getinterval
-    } ifelse
-  } % end of proc
-  image
-} bind def
-
-
-612 792 8			% dimensions of data
-[612 0 0 -792 0 792]		% mapping matrix
-rlecmapimage
-
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-
-%
-% Compression made this file 13.31% of the uncompressed size.
-%
-
-
-showpage
-
-% stop using temporary dictionary
-end
-
-% restore original state
-origstate restore
-
-%%Trailer
diff --git a/alliance/share/tutorials/fitpath/tex/trace-logic-2.ps b/alliance/share/tutorials/fitpath/tex/trace-logic-2.ps
deleted file mode 100644
index f583791c..00000000
--- a/alliance/share/tutorials/fitpath/tex/trace-logic-2.ps
+++ /dev/null
@@ -1,2362 +0,0 @@
-%!PS-Adobe-2.0 EPSF-2.0
-%%Title: /users/outil2/fitpath/ln.S/tutorial/trace-logic-2.ps
-%%Creator: XV Version 3.10a  Rev: 12/29/94  -  by John Bradley
-%%BoundingBox: 0 0 612 792
-%%Pages: 1
-%%DocumentFonts:
-%%EndComments
-%%EndProlog
-
-%%Page: 1 1
-
-% remember original state
-/origstate save def
-
-% build a temporary dictionary
-20 dict begin
-
-% define space for color conversions
-/grays 612 string def  % space for gray scale line
-/npixls 0 def
-/rgbindx 0 def
-
-% lower left corner
-0 0 translate
-
-% size of image (on paper, in 1/72inch coords)
-612.00000 792.00000 scale
-
-% define the colormap
-/cmap 6 string def
-
-
-% load up the colormap
-currentfile cmap readhexstring
-00 44 88 bf e5 ff 
-pop pop   % lose return values from readhexstring
-
-
-% rlecmapimage expects to have 'w h bits matrix' on stack
-/rlecmapimage {
-  /buffer 1 string def
-  /rgbval 3 string def
-  /block  384 string def
-
-  % proc to read a block from file, and return RGB data
-  { currentfile buffer readhexstring pop
-    /bcount exch 0 get store
-    bcount 128 ge
-    {  % it's a non-run block
-      0 1 bcount 128 sub
-      { currentfile buffer readhexstring pop pop
-
-        % look up value in gray map
-        /rgbval cmap buffer 0 get 1 getinterval store
-
-        % and put it in position i in block
-        block exch rgbval putinterval
-      } for
-      block  0  bcount 127 sub  getinterval
-    }
-
-    { % else it's a run block
-      currentfile buffer readhexstring pop pop
-
-      % look up value in graymap
-      /rgbval cmap buffer 0 get 1 getinterval store
-
-      0 1 bcount { block exch rgbval putinterval } for
-
-      block 0 bcount 1 add getinterval
-    } ifelse
-  } % end of proc
-  image
-} bind def
-
-
-612 792 8			% dimensions of data
-[612 0 0 -792 0 792]		% mapping matrix
-rlecmapimage
-
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-05
-
-%
-% Compression made this file 14.28% of the uncompressed size.
-%
-
-
-showpage
-
-% stop using temporary dictionary
-end
-
-% restore original state
-origstate restore
-
-%%Trailer
diff --git a/alliance/share/tutorials/fitpath/tex/trace-lvx-1.ps b/alliance/share/tutorials/fitpath/tex/trace-lvx-1.ps
deleted file mode 100644
index d5f24510..00000000
--- a/alliance/share/tutorials/fitpath/tex/trace-lvx-1.ps
+++ /dev/null
@@ -1,1764 +0,0 @@
-%!PS-Adobe-2.0 EPSF-2.0
-%%Title: /users/outil2/fitpath/ln.S/tutorial/trace-lvx-1.ps
-%%Creator: XV Version 3.10a  Rev: 12/29/94  -  by John Bradley
-%%BoundingBox: 0 0 612 792
-%%Pages: 1
-%%DocumentFonts:
-%%EndComments
-%%EndProlog
-
-%%Page: 1 1
-
-% remember original state
-/origstate save def
-
-% build a temporary dictionary
-20 dict begin
-
-% define space for color conversions
-/grays 612 string def  % space for gray scale line
-/npixls 0 def
-/rgbindx 0 def
-
-% lower left corner
-0 0 translate
-
-% size of image (on paper, in 1/72inch coords)
-612.00000 792.00000 scale
-
-% define the colormap
-/cmap 6 string def
-
-
-% load up the colormap
-currentfile cmap readhexstring
-00 44 88 bf e5 ff 
-pop pop   % lose return values from readhexstring
-
-
-% rlecmapimage expects to have 'w h bits matrix' on stack
-/rlecmapimage {
-  /buffer 1 string def
-  /rgbval 3 string def
-  /block  384 string def
-
-  % proc to read a block from file, and return RGB data
-  { currentfile buffer readhexstring pop
-    /bcount exch 0 get store
-    bcount 128 ge
-    {  % it's a non-run block
-      0 1 bcount 128 sub
-      { currentfile buffer readhexstring pop pop
-
-        % look up value in gray map
-        /rgbval cmap buffer 0 get 1 getinterval store
-
-        % and put it in position i in block
-        block exch rgbval putinterval
-      } for
-      block  0  bcount 127 sub  getinterval
-    }
-
-    { % else it's a run block
-      currentfile buffer readhexstring pop pop
-
-      % look up value in graymap
-      /rgbval cmap buffer 0 get 1 getinterval store
-
-      0 1 bcount { block exch rgbval putinterval } for
-
-      block 0 bcount 1 add getinterval
-    } ifelse
-  } % end of proc
-  image
-} bind def
-
-
-612 792 8			% dimensions of data
-[612 0 0 -792 0 792]		% mapping matrix
-rlecmapimage
-
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-
-%
-% Compression made this file 9.90% of the uncompressed size.
-%
-
-
-showpage
-
-% stop using temporary dictionary
-end
-
-% restore original state
-origstate restore
-
-%%Trailer
diff --git a/alliance/share/tutorials/fitpath/tex/trace-lynx-1.ps b/alliance/share/tutorials/fitpath/tex/trace-lynx-1.ps
deleted file mode 100644
index 2965fc10..00000000
--- a/alliance/share/tutorials/fitpath/tex/trace-lynx-1.ps
+++ /dev/null
@@ -1,1909 +0,0 @@
-%!PS-Adobe-2.0 EPSF-2.0
-%%Title: /users/outil2/fitpath/ln.S/tutorial/trace-lynx-1.ps
-%%Creator: XV Version 3.10a  Rev: 12/29/94  -  by John Bradley
-%%BoundingBox: 0 0 612 792
-%%Pages: 1
-%%DocumentFonts:
-%%EndComments
-%%EndProlog
-
-%%Page: 1 1
-
-% remember original state
-/origstate save def
-
-% build a temporary dictionary
-20 dict begin
-
-% define space for color conversions
-/grays 612 string def  % space for gray scale line
-/npixls 0 def
-/rgbindx 0 def
-
-% lower left corner
-0 0 translate
-
-% size of image (on paper, in 1/72inch coords)
-612.00000 792.00000 scale
-
-% define the colormap
-/cmap 6 string def
-
-
-% load up the colormap
-currentfile cmap readhexstring
-00 44 88 bf e5 ff 
-pop pop   % lose return values from readhexstring
-
-
-% rlecmapimage expects to have 'w h bits matrix' on stack
-/rlecmapimage {
-  /buffer 1 string def
-  /rgbval 3 string def
-  /block  384 string def
-
-  % proc to read a block from file, and return RGB data
-  { currentfile buffer readhexstring pop
-    /bcount exch 0 get store
-    bcount 128 ge
-    {  % it's a non-run block
-      0 1 bcount 128 sub
-      { currentfile buffer readhexstring pop pop
-
-        % look up value in gray map
-        /rgbval cmap buffer 0 get 1 getinterval store
-
-        % and put it in position i in block
-        block exch rgbval putinterval
-      } for
-      block  0  bcount 127 sub  getinterval
-    }
-
-    { % else it's a run block
-      currentfile buffer readhexstring pop pop
-
-      % look up value in graymap
-      /rgbval cmap buffer 0 get 1 getinterval store
-
-      0 1 bcount { block exch rgbval putinterval } for
-
-      block 0 bcount 1 add getinterval
-    } ifelse
-  } % end of proc
-  image
-} bind def
-
-
-612 792 8			% dimensions of data
-[612 0 0 -792 0 792]		% mapping matrix
-rlecmapimage
-
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-
-%
-% Compression made this file 11.07% of the uncompressed size.
-%
-
-
-showpage
-
-% stop using temporary dictionary
-end
-
-% restore original state
-origstate restore
-
-%%Trailer
diff --git a/alliance/share/tutorials/fitpath/tex/trace-lynx-2.ps b/alliance/share/tutorials/fitpath/tex/trace-lynx-2.ps
deleted file mode 100644
index 0ad557f4..00000000
--- a/alliance/share/tutorials/fitpath/tex/trace-lynx-2.ps
+++ /dev/null
@@ -1,1909 +0,0 @@
-%!PS-Adobe-2.0 EPSF-2.0
-%%Title: /users/outil2/fitpath/ln.S/tutorial/trace-lynx-2.ps
-%%Creator: XV Version 3.10a  Rev: 12/29/94  -  by John Bradley
-%%BoundingBox: 0 0 612 792
-%%Pages: 1
-%%DocumentFonts:
-%%EndComments
-%%EndProlog
-
-%%Page: 1 1
-
-% remember original state
-/origstate save def
-
-% build a temporary dictionary
-20 dict begin
-
-% define space for color conversions
-/grays 612 string def  % space for gray scale line
-/npixls 0 def
-/rgbindx 0 def
-
-% lower left corner
-0 0 translate
-
-% size of image (on paper, in 1/72inch coords)
-612.00000 792.00000 scale
-
-% define the colormap
-/cmap 6 string def
-
-
-% load up the colormap
-currentfile cmap readhexstring
-00 44 88 bf e5 ff 
-pop pop   % lose return values from readhexstring
-
-
-% rlecmapimage expects to have 'w h bits matrix' on stack
-/rlecmapimage {
-  /buffer 1 string def
-  /rgbval 3 string def
-  /block  384 string def
-
-  % proc to read a block from file, and return RGB data
-  { currentfile buffer readhexstring pop
-    /bcount exch 0 get store
-    bcount 128 ge
-    {  % it's a non-run block
-      0 1 bcount 128 sub
-      { currentfile buffer readhexstring pop pop
-
-        % look up value in gray map
-        /rgbval cmap buffer 0 get 1 getinterval store
-
-        % and put it in position i in block
-        block exch rgbval putinterval
-      } for
-      block  0  bcount 127 sub  getinterval
-    }
-
-    { % else it's a run block
-      currentfile buffer readhexstring pop pop
-
-      % look up value in graymap
-      /rgbval cmap buffer 0 get 1 getinterval store
-
-      0 1 bcount { block exch rgbval putinterval } for
-
-      block 0 bcount 1 add getinterval
-    } ifelse
-  } % end of proc
-  image
-} bind def
-
-
-612 792 8			% dimensions of data
-[612 0 0 -792 0 792]		% mapping matrix
-rlecmapimage
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-%
-% Compression made this file 11.07% of the uncompressed size.
-%
-
-
-showpage
-
-% stop using temporary dictionary
-end
-
-% restore original state
-origstate restore
-
-%%Trailer
diff --git a/alliance/share/tutorials/fitpath/tex/trace-proof-1.ps b/alliance/share/tutorials/fitpath/tex/trace-proof-1.ps
deleted file mode 100644
index cfb26ebc..00000000
--- a/alliance/share/tutorials/fitpath/tex/trace-proof-1.ps
+++ /dev/null
@@ -1,2871 +0,0 @@
-%!PS-Adobe-2.0 EPSF-2.0
-%%Title: /users/outil2/fitpath/ln.S/tutorial/trace-proof-1.ps
-%%Creator: XV Version 3.10a  Rev: 12/29/94  -  by John Bradley
-%%BoundingBox: 0 0 612 792
-%%Pages: 1
-%%DocumentFonts:
-%%EndComments
-%%EndProlog
-
-%%Page: 1 1
-
-% remember original state
-/origstate save def
-
-% build a temporary dictionary
-20 dict begin
-
-% define space for color conversions
-/grays 612 string def  % space for gray scale line
-/npixls 0 def
-/rgbindx 0 def
-
-% lower left corner
-0 0 translate
-
-% size of image (on paper, in 1/72inch coords)
-612.00000 792.00000 scale
-
-% define the colormap
-/cmap 6 string def
-
-
-% load up the colormap
-currentfile cmap readhexstring
-00 44 88 bf e5 ff 
-pop pop   % lose return values from readhexstring
-
-
-% rlecmapimage expects to have 'w h bits matrix' on stack
-/rlecmapimage {
-  /buffer 1 string def
-  /rgbval 3 string def
-  /block  384 string def
-
-  % proc to read a block from file, and return RGB data
-  { currentfile buffer readhexstring pop
-    /bcount exch 0 get store
-    bcount 128 ge
-    {  % it's a non-run block
-      0 1 bcount 128 sub
-      { currentfile buffer readhexstring pop pop
-
-        % look up value in gray map
-        /rgbval cmap buffer 0 get 1 getinterval store
-
-        % and put it in position i in block
-        block exch rgbval putinterval
-      } for
-      block  0  bcount 127 sub  getinterval
-    }
-
-    { % else it's a run block
-      currentfile buffer readhexstring pop pop
-
-      % look up value in graymap
-      /rgbval cmap buffer 0 get 1 getinterval store
-
-      0 1 bcount { block exch rgbval putinterval } for
-
-      block 0 bcount 1 add getinterval
-    } ifelse
-  } % end of proc
-  image
-} bind def
-
-
-612 792 8			% dimensions of data
-[612 0 0 -792 0 792]		% mapping matrix
-rlecmapimage
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diff --git a/alliance/share/tutorials/fitpath/tex/usercol_dpt-2.fig b/alliance/share/tutorials/fitpath/tex/usercol_dpt-2.fig
deleted file mode 100644
index ba8875e0..00000000
--- a/alliance/share/tutorials/fitpath/tex/usercol_dpt-2.fig
+++ /dev/null
@@ -1,250 +0,0 @@
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-3 2 0 4 -1 0 0 0 0.000 0 0
-	 339 594 349 619 339 644 9999 9999
-	 -260.000 340.000 346.500 607.355 349.000 613.605 349.000 624.395
-	 346.500 630.645 -260.000 340.000
-3 2 0 4 -1 0 0 0 0.000 0 0
-	 339 594 359 604 369 619 9999 9999
-	 -260.000 340.000 350.904 598.767 355.904 601.267 361.496 606.203
-	 363.996 609.953 -260.000 340.000
-3 2 0 4 -1 0 0 0 0.000 0 0
-	 339 644 359 634 369 619 9999 9999
-	 -260.000 340.000 350.904 639.233 355.904 636.733 361.496 631.797
-	 363.996 628.047 -260.000 340.000
--6
-6 334 509 384 569
-1 4 0 4 -1 0 0 0 0.00000 1 0.000 374 539 5 5 369 539 379 539
-3 2 0 4 -1 0 0 0 0.000 0 0
-	 339 514 349 539 339 564 9999 9999
-	 -260.000 260.000 346.500 527.355 349.000 533.605 349.000 544.395
-	 346.500 550.645 -260.000 260.000
-3 2 0 4 -1 0 0 0 0.000 0 0
-	 339 514 359 524 369 539 9999 9999
-	 -260.000 260.000 350.904 518.767 355.904 521.267 361.496 526.203
-	 363.996 529.953 -260.000 260.000
-3 2 0 4 -1 0 0 0 0.000 0 0
-	 339 564 359 554 369 539 9999 9999
-	 -260.000 260.000 350.904 559.233 355.904 556.733 361.496 551.797
-	 363.996 548.047 -260.000 260.000
--6
-6 334 429 384 489
-1 4 0 4 -1 0 0 0 0.00000 1 0.000 374 459 5 5 369 459 379 459
-3 2 0 4 -1 0 0 0 0.000 0 0
-	 339 434 349 459 339 484 9999 9999
-	 -260.000 180.000 346.500 447.355 349.000 453.605 349.000 464.395
-	 346.500 470.645 -260.000 180.000
-3 2 0 4 -1 0 0 0 0.000 0 0
-	 339 434 359 444 369 459 9999 9999
-	 -260.000 180.000 350.904 438.767 355.904 441.267 361.496 446.203
-	 363.996 449.953 -260.000 180.000
-3 2 0 4 -1 0 0 0 0.000 0 0
-	 339 484 359 474 369 459 9999 9999
-	 -260.000 180.000 350.904 479.233 355.904 476.733 361.496 471.797
-	 363.996 468.047 -260.000 180.000
--6
-6 334 269 384 329
-1 4 0 4 -1 0 0 0 0.00000 1 0.000 374 299 5 5 369 299 379 299
-3 2 0 4 -1 0 0 0 0.000 0 0
-	 339 274 349 299 339 324 9999 9999
-	 -260.000 20.000 346.500 287.355 349.000 293.605 349.000 304.395
-	 346.500 310.645 -260.000 20.000
-3 2 0 4 -1 0 0 0 0.000 0 0
-	 339 274 359 284 369 299 9999 9999
-	 -260.000 20.000 350.904 278.767 355.904 281.267 361.496 286.203
-	 363.996 289.953 -260.000 20.000
-3 2 0 4 -1 0 0 0 0.000 0 0
-	 339 324 359 314 369 299 9999 9999
-	 -260.000 20.000 350.904 319.233 355.904 316.733 361.496 311.797
-	 363.996 308.047 -260.000 20.000
--6
-6 334 349 384 409
-5 1 0 4 -1 0 0 0 0.000 1 0 0 374.625 379.000 369 354 349 379 369 404
-1 4 0 4 -1 0 0 0 0.00000 0 -0.000 344 379 5 5 349 379 339 379
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 369 354 379 354 379 404 369 404 9999 9999
--6
-6 334 669 384 729
-5 1 0 4 -1 0 0 0 0.000 1 0 0 374.625 699.000 369 674 349 699 369 724
-1 4 0 4 -1 0 0 0 0.00000 0 -0.000 344 699 5 5 349 699 339 699
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 369 674 379 674 379 724 369 724 9999 9999
--6
-6 334 749 384 809
-1 4 0 4 -1 0 0 0 0.00000 1 0.000 374 779 5 5 369 779 379 779
-3 2 0 4 -1 0 0 0 0.000 0 0
-	 339 754 349 779 339 804 9999 9999
-	 -260.000 500.000 346.500 767.355 349.000 773.605 349.000 784.395
-	 346.500 790.645 -260.000 500.000
-3 2 0 4 -1 0 0 0 0.000 0 0
-	 339 754 359 764 369 779 9999 9999
-	 -260.000 500.000 350.904 758.767 355.904 761.267 361.496 766.203
-	 363.996 769.953 -260.000 500.000
-3 2 0 4 -1 0 0 0 0.000 0 0
-	 339 804 359 794 369 779 9999 9999
-	 -260.000 500.000 350.904 799.233 355.904 796.733 361.496 791.797
-	 363.996 788.047 -260.000 500.000
--6
-6 289 269 309 289
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 294 274 304 284 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 304 274 294 284 9999 9999
--6
-6 289 309 309 329
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 294 314 304 324 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 304 314 294 324 9999 9999
--6
-6 289 429 309 449
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 294 434 304 444 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 304 434 294 444 9999 9999
--6
-6 289 469 309 489
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 294 474 304 484 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 304 474 294 484 9999 9999
--6
-6 289 589 309 609
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 294 594 304 604 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 304 594 294 604 9999 9999
--6
-6 289 629 309 649
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 294 634 304 644 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 304 634 294 644 9999 9999
--6
-6 289 749 309 769
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 294 754 304 764 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 304 754 294 764 9999 9999
--6
-6 289 789 309 809
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 294 794 304 804 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 304 794 294 804 9999 9999
--6
-6 409 529 429 549
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 414 534 424 544 9999 9999
-2 1 0 4 -1 0 0 0 0.000 -1 0 0
-	 424 534 414 544 9999 9999
--6
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 379 299 399 299 399 359 379 359 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 379 399 399 399 399 459 379 459 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 379 619 399 619 399 679 379 679 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 339 379 319 379 319 519 344 519 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 344 559 319 559 319 699 339 699 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 299 279 344 279 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 299 319 344 319 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 299 439 344 439 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 299 479 339 479 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 299 599 344 599 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 299 639 339 639 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 299 759 339 759 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 299 799 339 799 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 379 719 399 719 399 779 379 779 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 379 539 419 539 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 299 259 419 259 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 299 339 419 339 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 299 419 419 419 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 299 499 419 499 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 299 579 419 579 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 299 659 419 659 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 299 739 419 739 9999 9999
-2 2 0 2 -1 0 0 0 0.000 0 0 0
-	 419 819 419 179 299 179 299 819 419 819 9999 9999
-4 2 4 16 0 -1 0 0.00000 0 19 27 279 644 i0[2]

-4 2 4 16 0 -1 0 0.00000 0 19 27 279 604 i0[3]

-4 2 4 16 0 -1 0 0.00000 0 19 27 279 484 i0[4]

-4 2 4 16 0 -1 0 0.00000 0 19 27 279 444 i0[5]

-4 2 4 16 0 -1 0 0.00000 0 19 27 279 324 i0[6]

-4 2 4 16 0 -1 0 0.00000 0 19 27 279 284 i0[7]

-4 0 4 16 0 -1 0 0.00000 0 19 28 439 544 zero

-4 2 4 16 0 -1 0 0.00000 0 19 27 279 764 i0[1]

-4 2 4 16 0 -1 0 0.00000 0 19 27 279 804 i0[0]

-4 1 2 16 0 -1 0 0.00000 0 19 80 359 224 Empty Slice

--6
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 279 259 99 259 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 279 179 99 179 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 279 339 99 339 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 279 419 99 419 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 279 499 99 499 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 279 579 99 579 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 279 659 99 659 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 279 739 99 739 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 279 819 99 819 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 99 99 99 819 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 139 99 139 819 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 219 99 219 819 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 99 174 279 174 9999 9999
-2 1 0 1 -1 0 0 0 0.000 -1 0 0
-	 99 99 219 99 9999 9999
-2 1 0 2 -1 0 0 0 0.000 -1 0 0
-	 174 219 189 219 9999 9999
-4 1 2 16 0 -1 0 0.00000 0 19 36 179 304 no2_6

-4 1 2 16 0 -1 0 0.00000 0 19 7 119 304 6

-4 1 2 16 0 -1 0 0.00000 0 19 54 179 139 Instance

-4 1 2 16 0 -1 0 0.00000 0 19 32 119 139 Slice

-4 1 2 16 0 -1 0 0.00000 0 19 7 119 224 7

-4 1 2 16 0 -1 0 0.00000 0 19 7 119 384 5

-4 1 2 16 0 -1 0 0.00000 0 19 7 119 464 4

-4 1 2 16 0 -1 0 0.00000 0 19 7 119 544 3

-4 1 2 16 0 -1 0 0.00000 0 19 7 119 624 2

-4 1 2 16 0 -1 0 0.00000 0 19 7 119 704 1

-4 1 2 16 0 -1 0 0.00000 0 19 7 119 784 0

-4 1 2 16 0 -1 0 0.00000 0 19 36 179 384 na2_5

-4 1 2 16 0 -1 0 0.00000 0 19 36 179 704 na2_1

-4 1 2 16 0 -1 0 0.00000 0 19 36 179 784 no2_0

-4 1 2 16 0 -1 0 0.00000 0 19 36 179 624 no2_2

-4 1 2 16 0 -1 0 0.00000 0 19 36 179 544 no2_3

-4 1 2 16 0 -1 0 0.00000 0 19 36 179 464 no2_4

-4 1 2 20 0 -1 0 0.00000 0 21 75 359 154 "nul_us"

-4 1 2 20 0 -1 0 0.00000 0 21 126 359 134 User Operator :

diff --git a/alliance/share/tutorials/fitpath/usercol_dpt.c b/alliance/share/tutorials/fitpath/usercol_dpt.c
deleted file mode 100644
index 3f8c14b4..00000000
--- a/alliance/share/tutorials/fitpath/usercol_dpt.c
+++ /dev/null
@@ -1,147 +0,0 @@
-
-
-/*          Alliance CAD System V.R                                         */
-/*             FpGen Package V.RR                                           */
-/*                                                                          */
-/*  Copyright(c) 93-AA, MASI, CAO-VLSI Team                                 */
-/*                                                                          */
-/*  Author      :          Jean-Paul CHAPUT                                 */
-/*  E-mail      :      cao-vlsi@masi.ibp.fr                                 */
-/* ======================================================================== */
-/*  File        :      "usercol_dpt.c"                                      */
-/* ************************************************************************ */
-/*  Example of synthesis inside a Data-Path.                                */
-
-
-#include  <genlib.h>
-#include  <fpgen.h>
-
-
-static void  mkZeroDetect();
-
-
-static void  mkZeroDetect()
-{
-  /* Open the GenLib figure (the user data-path column).
-   * ===================================================
-   */
-  DEF_LOFIG( "nul_us" );
-
-
-  /* Interface description.
-   * ======================
-   */
-  LOCON(   "i0[7:0]", IN   ,   "i0[7:0]" );
-  LOCON( "zero"     ,   OUT, "zero"      );
-  LOCON(  "vdd"     , IN   ,  "vdd"      );
-  LOCON(  "vss"     , IN   ,  "vss"      );
-
-
-  /* 8 bits Zero Detect netlist description.
-   * =======================================
-   */
-  LOINS( "no2_dp", "no2_0", "i0[0]", "i0[1]", "z2_0", "vdd", "vss", 0L );
-  LOINS( "no2_dp", "no2_2", "i0[2]", "i0[3]", "z2_1", "vdd", "vss", 0L );
-  LOINS( "no2_dp", "no2_4", "i0[4]", "i0[5]", "z2_2", "vdd", "vss", 0L );
-  LOINS( "no2_dp", "no2_6", "i0[6]", "i0[7]", "z2_3", "vdd", "vss", 0L );
-
-  LOINS( "na2_dp", "na2_1",  "z2_0",  "z2_1", "z4_0", "vdd", "vss", 0L );
-  LOINS( "na2_dp", "na2_5",  "z2_2",  "z2_3", "z4_1", "vdd", "vss", 0L );
-
-  LOINS( "no2_dp", "no2_3",  "z4_0",  "z4_1", "zero", "vdd", "vss", 0L );
-
-
-  /* Terminate the netlist description, and save on disk.
-   * ====================================================
-   */
-  SAVE_LOFIG();
-}
-
-
-main()
-{
-  /* Generate the Zero Detect Column.
-   * ================================
-   */
-  mkZeroDetect();
-
-
-  /* Open a new Data-Path figure.
-   * ============================
-   */
-  DP_DEFLOFIG( "usercol_dpt", 8, LSB_INDEX_ZERO );
-
-
-  /* Interface description.
-   * ======================
-   */
-
-  /* Control terminals declarations. */
-  DP_LOCON( "ctrl_sel"  , IN   , "ctrl_sel"   );
-  DP_LOCON( "ctrl_ck"   , IN   , "ctrl_ck"    );
-  DP_LOCON( "ctrl_wen"  , IN   , "ctrl_wen"   );
-  DP_LOCON( "ctrl_ncout",   OUT, "ctrl_ncout" );
-  DP_LOCON( "ctrl_nover",   OUT, "ctrl_nover" );
-  DP_LOCON( "ctrl_zero" ,   OUT, "ctrl_zero"  );
-
-  /* Data terminals declarations. */
-  DP_LOCON( "data_a[7:0]" , IN   , "data_a[7:0]" );
-  DP_LOCON( "data_b[7:0]" , IN   , "data_b[7:0]" );
-  DP_LOCON( "data_s[7:0]" , INOUT, "data_s[7:0]" );
-
-  /* Power supplies terminals. */
-  DP_LOCON( "vdd", IN   , "vdd" );
-  DP_LOCON( "vss", IN   , "vss" );
-
-
-  /* Data-Path netlist description.
-   * ==============================
-   */
-
-  DP_TRACE( TRACE_ON );
-
-  /* Multiplexer. */
-  DP_MUX2CS( "multiplexer", 8, 0,
-             "ctrl_sel",
-             "data_b[7:0]",
-             "data_q[7:0]",
-             "data_m[7:0]",
-             EOL );
-
-  /* Fast Adder. */
-  DP_ADD2F( "adder",
-            "data_a[7:0]",
-            "data_m[7:0]",
-            "ctrl_ncout",
-            "ctrl_nover",
-            "data_s[7:0]",
-            EOL );
-
-  /* Zero Detect. */
-  DP_IMPORT( "nul_us",
-             "zero",
-             "data_s[7:0]",
-             "ctrl_zero",
-             EOL );
-
-  /* Register. */
-  DP_PDFF( "memory", 8, 0,
-           "ctrl_wen",
-           "ctrl_ck",
-           "data_s[7:0]",
-           "data_q[7:0]",
-           "data_u[7:0]",  /* This bus is unused. */
-           EOL );
-
-
-  DP_TRACE( TRACE_OFF );
-
-  /* Terminate the netlist description, and save on disk.
-   * ====================================================
-   */
-  DP_SAVLOFIG();
-
-
-  /* A good C program must always terminate by an "exit(0)". */
-  exit(0);
-}
diff --git a/alliance/share/tutorials/fitpath/usercol_dpt.dpr b/alliance/share/tutorials/fitpath/usercol_dpt.dpr
deleted file mode 100644
index ff5d5225..00000000
--- a/alliance/share/tutorials/fitpath/usercol_dpt.dpr
+++ /dev/null
@@ -1,27 +0,0 @@
-#
-#
-# /*          Alliance CAD System V.R                                       */
-# /*             FpGen Package V.RR                                         */
-# /*                                                                        */
-# /*  Copyright(c) 93-AA, MASI, CAO-VLSI Team                               */
-# /*                                                                        */
-# /*  Author      :          Jean-Paul CHAPUT                               */
-# /*  E-mail      :      cao-vlsi@masi.ibp.fr                               */
-# /* ====================================================================== */
-# /*  File        :      "usercol_dpt.dpr"                                  */
-# /* ********************************************************************** */
-# /*  Data-Path sample example.                                             */
-#
-#
-#           Terminal :  Side  :  Slice  :  Track
-DP_LOCON   ctrl_zero   NORTH    DEFAULT   DEFAULT
-#
-#
-#           Terminal :  Side  :  Slice  :  Track
-DP_LOCON  data_a[7:0]   WEST    DEFAULT   DEFAULT
-DP_LOCON  data_b[7:0]   WEST    DEFAULT   DEFAULT
-DP_LOCON  data_s[7:0]   EAST    DEFAULT   DEFAULT
-#
-#
-# Number of vertical power refreshment.
-DP_POWER  1  50
diff --git a/alliance/share/tutorials/fitpath/usercol_dpt.inf b/alliance/share/tutorials/fitpath/usercol_dpt.inf
deleted file mode 100644
index 8403b3dd..00000000
--- a/alliance/share/tutorials/fitpath/usercol_dpt.inf
+++ /dev/null
@@ -1,4 +0,0 @@
-RENAME
-  memory.pdff_*.memm_s : memory_m(*) ;
-  memory.pdff_*.mems_s : memory_s(*) ;
-END
diff --git a/alliance/share/tutorials/fitpath/usercol_dpt.sh b/alliance/share/tutorials/fitpath/usercol_dpt.sh
deleted file mode 100755
index decbfa05..00000000
--- a/alliance/share/tutorials/fitpath/usercol_dpt.sh
+++ /dev/null
@@ -1,108 +0,0 @@
-#!/bin/sh
-
-
-#
-#
-# /*          Alliance CAD System V.R                                       */
-# /*             FpGen Package V.RR                                         */
-# /*                                                                        */
-# /*  Copyright(c) 93-AA, MASI, CAO-VLSI Team                               */
-# /*                                                                        */
-# /*  Author      :          Jean-Paul CHAPUT                               */
-# /*  E-mail      :      cao-vlsi@masi.ibp.fr                               */
-# /* ====================================================================== */
-# /*  File        :      "usercol_dpt.sh"                                   */
-# /* ********************************************************************** */
-# /*  Data-Path using user defined column example.                          */
-#
-#
-
-
-# Installation Dependent Variables.
-#           ALLIANCE_TOP=/labo
-
-
-# FpGen Macro-Operators Library.
-     FPGEN_LIB=./mclib; export FPGEN_LIB
-
-
-# MBK Enviroment variables settings.
-     MBK_IN_PH=ap;      export MBK_IN_PH
-     MBK_IN_LO=vst;     export MBK_IN_LO
-    MBK_OUT_PH=ap;      export MBK_OUT_PH
-    MBK_OUT_LO=vst;     export MBK_OUT_LO
-  MBK_WORK_LIB=.;       export MBK_WORK_LIB
-  MBK_CATA_LIB=$FPGEN_LIB
-  MBK_CATA_LIB=$MBK_CATA_LIB:$ALLIANCE_TOP/cells/rsa
-  MBK_CATA_LIB=$MBK_CATA_LIB:$ALLIANCE_TOP/cells/fitpath/fplib
-  MBK_CATA_LIB=$MBK_CATA_LIB:$ALLIANCE_TOP/cells/fitpath/dplib
-                        export MBK_CATA_LIB
-MBK_CATAL_NAME=CATAL;   export MBK_CATAL_NAME
-       MBK_VDD=vdd;     export MBK_VDD
-       MBK_VSS=vss;     export MBK_VSS
-
-#
-#
-# FpGen : Generation of the Netlist.
-# ==================================
-#
-fpgen -v usercol_dpt
-
-
-#
-#
-# DPR : Routing the data-path.
-# ============================
-#
-dpr -V -p -r usercol_dpt usercol_dpt
-
-
-#
-#
-# DRUC : Symbolic Design RUles Checker.
-# =====================================
-#
-druc sample_dpt
-
-
-#
-#
-# LYNX : Gate level netlist extraction.
-# =====================================
-#
-MBK_OUT_LO=al
- MBK_IN_LO=al
-
-lynx -v -f usercol_dpt usercol_dpt_gates
-
-
-#
-#
-# LVX : Netlist comparison.
-# =========================
-#
-lvx vst al usercol_dpt usercol_dpt_gates -f
-
-
-#
-#
-# LYNX : Transistor netlist extraction.
-# =====================================
-#
-lynx -v -t usercol_dpt usercol_dpt
-
-
-#
-#
-# DESB : Behavioral exctraction.
-# ==============================
-#
-desb usercol_dpt usercol_dpt_desb -v -i
-
-
-#
-#
-# PROOF : Formal proof.
-# =====================
-#
-proof -d sample_dpt usercol_dpt_desb
diff --git a/alliance/share/tutorials/power/Makefile b/alliance/share/tutorials/power/Makefile
deleted file mode 100644
index edb61097..00000000
--- a/alliance/share/tutorials/power/Makefile
+++ /dev/null
@@ -1,266 +0,0 @@
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Tool   :                      Paper                         |
-# |                                                             |
-# | File   :                    Makefile                        |
-# |                                                             |
-# | Author :                 Jacomme Ludovic                    |
-# |                         and Fred the king                   |
-# |                                                             |
-# | Date   :                    01.01.96                        |
-# |                                                             |
-# \------------------------------------------------------------*/
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                            Variables                        |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-OPTION = o
-FORMAT = fsm
-FILE   = digi
-
-FILE_NAME = $(FILE)_$(OPTION)
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                        Power Consumption                    |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-CLOCK          = clock
-FREQUENCY      = 40
-CLOCK_WAVE     = "01"
-PATTERN_STEP   = 12500ps
-PATTERN_PICO   = 25000
-SWING          = 3.3
-CAPA_OUT       = 100
-
-# CLOCK          = clock
-# FREQUENCY      = 20
-# CLOCK_WAVE     = "01"
-# PATTERN_STEP   = 25ns
-# PATTERN_PICO   = 50000
-# SWING          = 3.3
-# CAPA_OUT       = 100
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                          Alliance Tools                     |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-SYF      = $(ALLIANCE_TOP)/bin/syf -VC
-ASIMUT   = $(ALLIANCE_TOP)/bin/asimut
-LVX      = $(ALLIANCE_TOP)/bin/lvx
-SCR      = $(ALLIANCE_TOP)/bin/scr
-BOOM     = $(ALLIANCE_TOP)/bin/boom
-BOOG     = $(ALLIANCE_TOP)/bin/boog
-LOON     = $(ALLIANCE_TOP)/bin/loon
-LYNX     = $(ALLIANCE_TOP)/bin/lynx
-TAS      = $(ALLIANCE_TOP)/bin/tas
-YAGLE    = $(ALLIANCE_TOP)/bin/yagle
-
-POCPAG   = $(ALLIANCE_TOP)/bin/pocpag
-DTX2DLY  = $(ALLIANCE_TOP)/bin/dtx2dly
-SICC     = $(ALLIANCE_TOP)/bin/sicc
-EPOC     = $(ALLIANCE_TOP)/bin/epoc
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                          Unix Command                       |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-RM     = rm
-MV     = mv
-CP     = cp
-CUT    = cut
-GREP   = grep
-TOUCH  = touch
-GZIP   = gzip
-TAIL   = tail
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                          Cells libraries                    |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-CELLS      = $(ALLIANCE_TOP)/cells
-CELLS_SCR  = $(ALLIANCE_CELLS)/sxlib
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                             Techno                          |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TAS_TECHNO = $(ALLIANCE_TOP)/etc/prol05.elp
-RDS_TECHNO = $(ALLIANCE_TOP)/etc/prol05.rds
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                       Environement Variables                |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-ENV_VST = MBK_IN_LO=vst;              export MBK_IN_LO; \
-          MBK_OUT_LO=vst;             export MBK_OUT_LO; \
-          MBK_WORK_LIB=.;             export MBK_WORK_LIB; \
-          MBK_CATA_LIB=$(CELLS_SCR);  export MBK_CATA_LIB
-ENV_AL  = MBK_IN_LO=al;               export MBK_IN_LO; \
-          MBK_OUT_LO=al;              export MBK_OUT_LO; \
-          MBK_WORK_LIB=.;             export MBK_WORK_LIB; \
-          MBK_CATA_LIB=$(CELLS_SCR);  export MBK_CATA_LIB
-ENV_AP  = MBK_IN_PH=ap;               export MBK_IN_PH; \
-          MBK_OUT_PH=ap;              export MBK_OUT_PH; \
-          MBK_WORK_LIB=.;             export MBK_WORK_LIB
-ENV_VH  = VH_BEHSFX=vbe;              export VH_BEHSFX; \
-          VH_MAXERR="10";             export VH_MAXERR; \
-          VH_PATSFX=pat;              export VH_PATSFX
-ENV_SL  = MBK_TARGET_LIB=$(CELLS_SCR);export MBK_TARGET_LIB; \
-          MBK_VDD=vdd;                export MBK_VDD; \
-          MBK_VSS=vss;                export MBK_VSS
-ENV_FSM = FSM_IN=$(FORMAT);           export FSM_IN
-
-ENV_RDS = RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                                 All                         |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-all : $(FILE_NAME).pow
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                             Synthesis                       |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-$(FILE_NAME).vbe : $(FILE).$(FORMAT)
-	$(ENV_FSM); $(SYF) -$(OPTION) $(FILE) $(FILE_NAME)
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                          Optimization                       |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-$(FILE_NAME)_o.vbe : $(FILE_NAME).vbe
-	$(ENV_SL); $(BOOM) -V $(FILE_NAME) $(FILE_NAME)_o
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                             Mapping                         |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-$(FILE_NAME).vst : $(FILE_NAME)_o.vbe
-	$(ENV_SL); $(ENV_VST); $(BOOG) $(FILE_NAME)_o $(FILE_NAME)
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                             Netoptim                        |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-$(FILE_NAME)_o.vst : $(FILE_NAME).vst
-	$(ENV_SL); $(ENV_VST); $(LOON) $(FILE_NAME) $(FILE_NAME)_o 
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                              Route                          |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-$(FILE_NAME).ap : $(FILE_NAME)_o.vst
-	$(ENV_VST); $(ENV_AP); $(SCR) -p -r $(FILE_NAME)_o -o $(FILE_NAME)
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                              Extract                        |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-$(FILE_NAME)_t.al : $(FILE_NAME).ap
-	$(ENV_AL); $(ENV_AP); $(ENV_RDS); $(LYNX) -v -t -ac $(FILE_NAME) $(FILE_NAME)_t
-
-$(FILE_NAME).al : $(FILE_NAME).ap
-	$(ENV_AL); $(ENV_AP); $(ENV_RDS); $(LYNX) -v -ac $(FILE_NAME)
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                              NetCompare                     |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-$(FILE_NAME).lvx : $(FILE_NAME).al $(FILE_NAME).vst
-	$(ENV_AL); $(LVX) vst al $(FILE_NAME)_o $(FILE_NAME)
-	$(TOUCH) $(FILE_NAME).lvx
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                              Timing                         |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-$(FILE_NAME).dtx : $(FILE_NAME)_t.al $(FILE_NAME).lvx
-	ELP_TECHNO_NAME=$(TAS_TECHNO); export ELP_TECHNO_NAME;\
-	$(ENV_AL); $(TAS) -t -tec=$(TAS_TECHNO) $(FILE_NAME)_t
-	$(MV) $(FILE_NAME)_t.dtx $(FILE_NAME).dtx
-
-$(FILE_NAME)_yagh.vbe $(FILE_NAME)_t_yagh.al : $(FILE_NAME)_t.al
-	ELP_TECHNO_NAME=$(TAS_TECHNO); export ELP_TECHNO_NAME;\
-	$(ENV_AL); $(YAGLE) -v -nc -h -ffs -t -d -elp $(FILE_NAME)_t $(FILE_NAME)_yagh
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                              Conso                          |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-$(FILE_NAME).sta : $(FILE_NAME).pat $(FILE_NAME).lvx $(FILE_NAME)_yagh.vbe
-	$(ENV_AL); $(ASIMUT) -b -stat $(PATTERN_PICO) \
-	           $(FILE_NAME) $(FILE_NAME)_yagh \
-	            $(FILE_NAME) $(FILE_NAME)_res
-
-$(FILE_NAME).pat : $(FILE_NAME)_yagh.vbe
-	$(POCPAG) -clk ck $(CLOCK_WAVE) -dly $(PATTERN_STEP) -b -nbr 1000 \
-	        $(FILE_NAME) default $(FILE_NAME)
-
-$(FILE_NAME).dly : $(FILE_NAME).dtx
-	$(DTX2DLY) $(FILE_NAME)
-
-$(FILE_NAME).nrj : $(FILE_NAME).dly $(FILE_NAME)_t_yagh.al
-	$(ENV_AL); $(SICC) $(SWING) $(CAPA_OUT) $(FILE_NAME)_t_yagh $(FILE_NAME) 
-
-$(FILE_NAME).pow : $(FILE_NAME).sta $(FILE_NAME).nrj $(FILE_NAME)_yagh.vbe
-	$(ENV_AL); $(EPOC) $(FILE_NAME)_yagh $(FILE_NAME) $(FILE_NAME) $(FILE_NAME) $(FREQUENCY)
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                            Clean up                         |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-clean :
-	@$(RM) -f $(FILE_NAME)*.vbe \
-	          $(FILE_NAME)*.vst \
-	          $(FILE_NAME)*.xsc \
-	          $(FILE_NAME)*.ap  \
-	          $(FILE_NAME)*.al  \
-	          $(FILE_NAME)*.lvx \
-	          $(FILE_NAME)*.cns \
-	          $(FILE_NAME)*.dtx \
-	          $(FILE_NAME)*.ttx \
-	          $(FILE_NAME)*.dly \
-                  $(FILE_NAME)*.sta \
-	          $(FILE_NAME)*.nrj \
-                  $(FILE_NAME)*.pat \
-                  $(FILE_NAME)*.rep \
-                  $(FILE_NAME)*.stb \
-                  $(FILE_NAME)*.pow \
-		  CATAL
diff --git a/alliance/share/tutorials/power/default.prb b/alliance/share/tutorials/power/default.prb
deleted file mode 100644
index e12ce502..00000000
--- a/alliance/share/tutorials/power/default.prb
+++ /dev/null
@@ -1,7 +0,0 @@
-default density = 2500.00;
-default p('1') = 0.25;
-
-
-in vdd   : p('1') = 1.0;
-in vss   : p('1') = 0.0;
-in reset : p('1') = 0.10;
diff --git a/alliance/share/tutorials/power/digi.fsm b/alliance/share/tutorials/power/digi.fsm
deleted file mode 100644
index e316e8bf..00000000
--- a/alliance/share/tutorials/power/digi.fsm
+++ /dev/null
@@ -1,217 +0,0 @@
-ENTITY circuit is
-
-PORT 
-( 
-   ck    : in  BIT;
-   jour  : in  BIT;
-   reset : in  BIT; 
-   vdd   : in  BIT;
-   vss   : in  BIT;
-   i     : in  BIT_VECTOR(3 DOWNTO 0);
-   porte : out BIT;
-   alarm : out BIT;
-   ep_0  : out BIT;
-   ep_1  : out BIT;
-   ep_2  : out BIT;
-   ep_3  : out BIT;
-   ep_4  : out BIT;
-   ep_5  : out BIT;
-   ep_a  : out BIT
-);
-END circuit;
-
-
-ARCHITECTURE MOORE OF circuit is
-
-   TYPE ETAT_TYPE IS (E0, E1, E2, E3, E4, E5, EA);   
-
-   SIGNAL EF, CS : ETAT_TYPE;
-
-   CONSTANT digit0 : BIT_VECTOR (3 DOWNTO 0) := B"1111"  ; -- O
-
-   CONSTANT digit1 : BIT_VECTOR (3 DOWNTO 0) := B"0101"  ; -- 5
-   CONSTANT digit2 : BIT_VECTOR (3 DOWNTO 0) := B"0011"  ; -- 3
-   CONSTANT digit3 : BIT_VECTOR (3 DOWNTO 0) := B"1100"  ; -- A
-   CONSTANT digit4 : BIT_VECTOR (3 DOWNTO 0) := B"0001"  ; -- 1
-   CONSTANT digit5 : BIT_VECTOR (3 DOWNTO 0) := B"0111"  ; -- 7
-
---PRAGMA CURRENT_STATE CS
---PRAGMA NEXT_STATE EF
---PRAGMA CLOCK ck
---PRAGMA FIRST_STATE E0
-
-BEGIN
-
-PROCESS ( CS, i)
-BEGIN
-  IF ( reset = '1' )
-  THEN
-    EF    <= E0;
-    porte <= '0';
-    alarm <= '0';
-    ep_0 <= '1';
-    ep_1 <= '0';
-    ep_2 <= '0';
-    ep_3 <= '0';
-    ep_4 <= '0';
-    ep_5 <= '0';
-    ep_a <= '0';
-  ELSE
-  CASE CS is
-    WHEN E0 =>
-      porte <= '0';
-      alarm <= '0';
-      ep_0 <= '1';
-      ep_1 <= '0';
-      ep_2 <= '0';
-      ep_3 <= '0';
-      ep_4 <= '0';
-      ep_5 <= '0';
-      ep_a <= '0';
-      IF ( i = digit0 ) 
-      THEN
-        IF ( jour = '1' )
-        THEN
-          EF <= E5;
-        ELSE
-          EF <= EA;
-        END IF;
-      ELSE
-        IF ( i = digit1 )
-        THEN
-          EF <= E1;
-        ELSE
-          IF ( jour = '1' )
-          THEN
-             EF <= E0;
-          ELSE
-             EF <= EA;
-          END IF;
-        END IF;
-      END IF;
-
-    WHEN E1 =>
-      porte <= '0';
-      alarm <= '0';
-      ep_0 <= '0';
-      ep_1 <= '1';
-      ep_2 <= '0';
-      ep_3 <= '0';
-      ep_4 <= '0';
-      ep_5 <= '0';
-      ep_a <= '0';
-      IF ( i = digit2 )
-      THEN
-        EF <= E2;
-      ELSE
-        IF ( jour = '1' )
-        THEN
-          EF <= E0;
-        ELSE
-          EF <= EA;
-        END IF;
-      END IF;
-
-    WHEN E2 =>
-      porte <= '0';
-      alarm <= '0';
-      ep_0 <= '0';
-      ep_1 <= '0';
-      ep_2 <= '1';
-      ep_3 <= '0';
-      ep_4 <= '0';
-      ep_5 <= '0';
-      ep_a <= '0';
-      IF ( i = digit3 )
-      THEN
-        EF <= E3;
-      ELSE
-        IF ( jour = '1' )
-        THEN
-          EF <= E0;
-        ELSE
-          EF <= EA;
-        END IF;
-      END IF;
-
-    WHEN E3 =>
-      porte <= '0';
-      alarm <= '0';
-      ep_0 <= '0';
-      ep_1 <= '0';
-      ep_2 <= '0';
-      ep_3 <= '1';
-      ep_4 <= '0';
-      ep_5 <= '0';
-      ep_a <= '0';
-      IF ( i = digit4 )
-      THEN
-        EF <= E4;
-      ELSE
-        IF ( jour = '1' )
-        THEN
-          EF <= E0;
-        ELSE
-          EF <= EA;
-        END IF;
-      END IF;
-
-    WHEN E4 =>
-      porte <= '0';
-      alarm <= '0';
-      ep_0 <= '0';
-      ep_1 <= '0';
-      ep_2 <= '0';
-      ep_3 <= '0';
-      ep_4 <= '1';
-      ep_5 <= '0';
-      ep_a <= '0';
-      IF ( i = digit5 )
-      THEN
-        EF <= E5;
-      ELSE
-        IF ( jour = '1' )
-        THEN
-          EF <= E0;
-        ELSE
-          EF <= EA;
-        END IF;
-      END IF;
-
-    WHEN E5 =>
-      porte <= '1';
-      alarm <= '0';
-      ep_0 <= '0';
-      ep_1 <= '0';
-      ep_2 <= '0';
-      ep_3 <= '0';
-      ep_4 <= '0';
-      ep_5 <= '1';
-      ep_a <= '0';
-      EF    <= E5;
-
-    WHEN EA =>
-      porte <= '0';
-      alarm <= '1';
-      ep_0 <= '0';
-      ep_1 <= '0';
-      ep_2 <= '0';
-      ep_3 <= '0';
-      ep_4 <= '0';
-      ep_5 <= '0';
-      ep_a <= '1';
-      EF    <= EA;
-
-  END CASE;
-  END IF;
-END PROCESS;
-
-PROCESS( ck )
-BEGIN
-    IF ( ck = '1' AND NOT ck'STABLE )
-    THEN
-      CS <= EF;
-    END IF;
-END PROCESS;
-
-END MOORE;
diff --git a/alliance/share/tutorials/synth/Makefile b/alliance/share/tutorials/synth/Makefile
deleted file mode 100644
index 446c4546..00000000
--- a/alliance/share/tutorials/synth/Makefile
+++ /dev/null
@@ -1,178 +0,0 @@
-############################
-# makefile parameters
-############################
-SHELL =	/bin/sh
-
-circuit =	digicode
-CELLS_LIB =	$(ALLIANCE_TOP)/cells/sxlib
-AUTO_PATH =	.
-
-SYF_EXE       = $(ALLIANCE_TOP)/bin/syf
-BOP_EXE       = $(ALLIANCE_TOP)/bin/bop
-NETOPTIM_EXE  = $(ALLIANCE_TOP)/bin/glop
-SCMAP_EXE     = $(ALLIANCE_TOP)/bin/scmap
-SCR_EXE       = $(ALLIANCE_TOP)/bin/scr
-LYNX_EXE      = $(ALLIANCE_TOP)/bin/lynx
-PROOF_EXE     = $(ALLIANCE_TOP)/bin/proof
-YAGLE_EXE     = $(ALLIANCE_TOP)/bin/yagle
-
-SYF =	MBK_WORK_LIB=$(AUTO_PATH);		export MBK_WORK_LIB;\
-	$(SYF_EXE)
-
-OPTIM = MBK_WORK_LIB=$(AUTO_PATH);		export MBK_WORK_LIB;\
-	$(BOP_EXE) -o
-
-MAPSC = MBK_WORK_LIB=$(AUTO_PATH);		export MBK_WORK_LIB;\
-	MBK_TARGET_LIB=$(CELLS_LIB);		export MBK_TARGET_LIB;\
-	MBK_IN_LO=vst;				export MBK_IN_LO;\
-	MBK_OUT_LO=vst;				export MBK_OUT_LO;\
-	$(SCMAP_EXE)
-
-NEALLIANCE_TOPTIM = MBK_CATAL_NAME=CATAL;		export MBK_CATAL_NAME;\
-	MBK_CATA_LIB=$(CELLS_LIB);	export MBK_CATA_LIB;\
-	MBK_WORK_LIB=$(AUTO_PATH);		export MBK_WORK_LIB;\
-	MBK_VDD=vdd;				export MBK_VDD;\
-	MBK_VSS=vss;				export MBK_VSS;\
-	MBK_IN_LO=vst;				export MBK_IN_LO;\
-	MBK_OUT_LO=vst;				export MBK_OUT_LO;\
-	$(NETOPTIM_EXE) -g
-
-TIMING = MBK_CATAL_NAME=CATAL;			export MBK_CATAL_NAME;\
-	MBK_CATA_LIB=$(CELLS_LIB);	export MBK_CATA_LIB;\
-	MBK_WORK_LIB=$(AUTO_PATH);		export MBK_WORK_LIB;\
-	MBK_VDD=vdd;				export MBK_VDD;\
-	MBK_VSS=vss;				export MBK_VSS;\
-	MBK_IN_LO=vst;				export MBK_IN_LO;\
-	$(NETOPTIM_EXE) -t
-
-SCR =	MBK_CATAL_NAME=CATAL;                   export MBK_CATAL_NAME;\
-	MBK_CATA_LIB=$(CELLS_LIB);	export MBK_CATA_LIB;\
-	MBK_WORK_LIB=$(AUTO_PATH);		export MBK_WORK_LIB;\
-	MBK_IN_LO=vst;                         	export MBK_IN_LO;\
-	MBK_IN_PH=ap;                         	export MBK_IN_PH;\
-	MBK_OUT_PH=ap;                        	export MBK_OUT_PH;\
-	$(SCR_EXE) -p -r -i 1000
-
-LYNX =  MBK_CATAL_NAME=CATAL;                   export MBK_CATAL_NAME;\
-	MBK_CATA_LIB=$(CELLS_LIB);	export MBK_CATA_LIB;\
-        MBK_WORK_LIB=$(AUTO_PATH);		export MBK_WORK_LIB;\
-        MBK_IN_PH=ap;	                        export MBK_IN_PH;\
-        MBK_OUT_LO=al;    	                export MBK_OUT_LO;\
-        $(LYNX_EXE) -f
-
-YAGLE =  MBK_WORK_LIB=$(AUTO_PATH);		export MBK_WORK_LIB;\
-	 MBK_CATA_LIB=$(CELLS_LIB);	export MBK_CATA_LIB;\
-	 MBK_IN_LO=al;                         	export MBK_IN_LO;\
-         $(YAGLE_EXE) -v -i
-
-PROOF =	MBK_WORK_LIB=$(AUTO_PATH);		export MBK_WORK_LIB;\
-        $(PROOF_EXE) -d
-
-.SILENT:
-
-all : $(circuit)rg0sct.vbe $(circuit)sg0sct.vbe $(circuit)sg3sct.vbe proof_all results
-
-clean	:
-	rm -f $(AUTO_PATH)/*.cod $(AUTO_PATH)/*.vbe $(AUTO_PATH)/*.al $(AUTO_PATH)/*.vst $(AUTO_PATH)/*.rep $(AUTO_PATH)/*.ap $(AUTO_PATH)/results proof_all
-
-################################################################################
-#	State encoding by SYF
-################################################################################
-$(circuit)s.vbe : $(circuit).fsm
-	$(SYF) -E -o  $(circuit) $(circuit)s
-$(circuit)r.vbe : $(circuit).fsm
-	$(SYF) -E -r $(circuit) $(circuit)r
-
-################################################################################
-#	Delay and Area global Optimisation by LOGIC
-################################################################################
-$(circuit)sg0.vbe : $(circuit)s.vbe area.lax
-	$(OPTIM) $(circuit)s $(circuit)sg0 area
-$(circuit)rg0.vbe : $(circuit)r.vbe area.lax
-	$(OPTIM) $(circuit)r $(circuit)rg0 area
-$(circuit)sg3.vbe : $(circuit)s.vbe delay.lax
-	$(OPTIM) $(circuit)s $(circuit)sg3 delay
-
-################################################################################
-#	Mapping by LOGIC
-################################################################################
-$(circuit)sg0sc.vst : $(circuit)sg0.vbe
-	$(MAPSC) $(circuit)sg0 $(circuit)sg0sc area
-$(circuit)rg0sc.vst : $(circuit)rg0.vbe
-	$(MAPSC) $(circuit)rg0 $(circuit)rg0sc area
-$(circuit)sg3sc.vst : $(circuit)sg3.vbe
-	$(MAPSC) $(circuit)sg3 $(circuit)sg3sc delay
-
-################################################################################
-#	Delay Optimisation by NEALLIANCE_TOPTIM
-################################################################################
-$(circuit)sg0scg.vst : $(circuit)sg0sc.vst neto.lax
-	$(NEALLIANCE_TOPTIM) $(circuit)sg0sc $(circuit)sg0scg neto
-$(circuit)rg0scg.vst : $(circuit)rg0sc.vst neto.lax
-	$(NEALLIANCE_TOPTIM) $(circuit)rg0sc $(circuit)rg0scg neto
-$(circuit)sg3scg.vst : $(circuit)sg3sc.vst neto.lax
-	$(NEALLIANCE_TOPTIM) $(circuit)sg3sc $(circuit)sg3scg neto
-
-
-################################################################################
-#	Placement and Routage by SCR
-################################################################################
-$(circuit)sg0scg.ap : $(circuit)sg0scg.vst 
-	$(SCR) $(circuit)sg0scg
-$(circuit)rg0scg.ap : $(circuit)rg0scg.vst 
-	$(SCR) $(circuit)rg0scg
-$(circuit)sg3scg.ap : $(circuit)sg3scg.vst 
-	$(SCR) $(circuit)sg3scg
-
-################################################################################
-#	Area and Delay Results
-################################################################################
-results : $(circuit)sg0scg.ap $(circuit)sg3scg.ap $(circuit)rg0scg.ap
-	echo "Simulated annealing encoding and standard cell mapping with area optimisation :" > results
-	echo -n "        Area : " >> results
-	grep "^A" $(circuit)rg0scg.ap >> results
-	$(TIMING) $(circuit)rg0scg toto | grep path | grep -v Min >> results
-	echo "Vertical encoding and standard cell mapping with area optimisation :" >>results
-	echo -n "        Area : " >> results
-	grep "^A" $(circuit)sg0scg.ap >> results
-	$(TIMING) $(circuit)sg0scg toto | grep path | grep -v Min >> results
-	echo "Vertical encoding and standard cell mapping with delay optimisation :" >>results
-	echo -n "        Area : " >> results
-	grep "^A" $(circuit)sg3scg.ap >> results
-	$(TIMING) $(circuit)sg3scg toto | grep path | grep -v Min >> results
-	cat results
-
-################################################################################
-#	Netlist Extraction by LYNX
-################################################################################
-$(circuit)sg0sct.al : $(circuit)sg0scg.ap
-	$(LYNX) $(circuit)sg0scg $(circuit)sg0sct
-$(circuit)rg0sct.al : $(circuit)rg0scg.ap
-	$(LYNX) $(circuit)rg0scg $(circuit)rg0sct
-$(circuit)sg3sct.al : $(circuit)sg3scg.ap
-	$(LYNX) $(circuit)sg3scg $(circuit)sg3sct
-
-################################################################################
-#	Functional Abstraction by YAGLE
-################################################################################
-$(circuit)sg0sct.vbe : $(circuit)sg0sct.al
-	$(YAGLE) $(circuit)sg0sct
-	sed -e "s/_dff_s//g" $(circuit)sg0sct.vbe > toto
-	mv toto $(circuit)sg0sct.vbe
-$(circuit)rg0sct.vbe : $(circuit)rg0sct.al
-	$(YAGLE) $(circuit)rg0sct
-	sed -e "s/_dff_s//g" $(circuit)rg0sct.vbe > toto
-	mv toto $(circuit)rg0sct.vbe
-$(circuit)sg3sct.vbe : $(circuit)sg3sct.al
-	$(YAGLE) $(circuit)sg3sct
-	sed -e "s/_dff_s//g" $(circuit)sg3sct.vbe > toto
-	mv toto $(circuit)sg3sct.vbe
-
-################################################################################
-#	Formal Proof by PROOF
-################################################################################
-proof_all :
-	$(PROOF) $(circuit)sg0sct $(circuit)s
-	$(PROOF) $(circuit)rg0sct $(circuit)r
-	$(PROOF) $(circuit)sg3sct $(circuit)s
-	touch proof_all
diff --git a/alliance/share/tutorials/synth/area.lax b/alliance/share/tutorials/synth/area.lax
deleted file mode 100644
index 1f00a5d7..00000000
--- a/alliance/share/tutorials/synth/area.lax
+++ /dev/null
@@ -1,10 +0,0 @@
-## Mode
-#M{0}
-## Level
-#L{5}
-## Number Transistor N
-#N{4}
-## Number Transistor P
-#P{4}
-## Fanout factor
-#T{1000}
diff --git a/alliance/share/tutorials/synth/delay.lax b/alliance/share/tutorials/synth/delay.lax
deleted file mode 100644
index b6a14d4b..00000000
--- a/alliance/share/tutorials/synth/delay.lax
+++ /dev/null
@@ -1,10 +0,0 @@
-## Mode
-#M{3}
-## Level
-#L{5}
-## Number Transistor N
-#N{4}
-## Number Transistor P
-#P{4}
-## Fanout factor
-#T{1000}
diff --git a/alliance/share/tutorials/synth/digicode.fsm b/alliance/share/tutorials/synth/digicode.fsm
deleted file mode 100644
index a3962273..00000000
--- a/alliance/share/tutorials/synth/digicode.fsm
+++ /dev/null
@@ -1,135 +0,0 @@
-entity digicode is
-  port (
-	ck, reset, day, O:in bit;
-	i:in bit_vector (3 downto 0);
-	door, warn:out bit;
-	vdd, vss:in bit
-	);
-end digicode;
-
-architecture MOORE of digicode is
-type ETAT_TYPE is (S0, S1, S2, S3, S_WAIT, S_OPEN, S_WARN);
-signal NEXT_STATE, CURRENT_STATE:ETAT_TYPE;
-
--- pragma CURRENT_STATE CURRENT_STATE
--- pragma NEXT_STATE NEXT_STATE
--- pragma CLOCK ck
-
-constant CODE0 : bit_vector (3 downto 0):= X"5";
-constant CODE1 : bit_vector (3 downto 0):= X"3";
-constant CODE2 : bit_vector (3 downto 0):= X"C";
-constant CODE3 : bit_vector (3 downto 0):= X"1";
-constant CODE4 : BIT_vector (3 downto 0):= X"7";
-
-begin
-process (CURRENT_STATE, i, reset, day, O)
-begin
-if (reset = '1')
-     	then NEXT_STATE <= S_WAIT;
-		door <= '0';
-		warn <= '0';
-	else
-	case CURRENT_STATE is
-		when S_WAIT =>
-			if (O = '1')
-				then if (day = '1')
-     					then NEXT_STATE <= S_OPEN;
-						door <= '1';
-					else
-						NEXT_STATE <= S_WAIT;
-						door <= '0';
-     					end if;
-     					warn <='0';
-     				else if (i = CODE0)
-     					then NEXT_STATE <= S0;
-						warn <= '0';
-					else
-						NEXT_STATE <= S_WARN;
-						warn <= '1';
-     					end if;
-     						door <='0';
-     				end if;
-     		when S0 =>
-			if ((day = '1') and (O = '1'))
-  				then NEXT_STATE <= S_OPEN;
-					door <= '1';
-					warn <= '0';
-				else
-					if (i = CODE1)
-     						then NEXT_STATE <= S1;
-							warn <= '0';
-						else
-							NEXT_STATE <= S_WARN;
-							warn <= '1';
-     						end if;
-     					door <='0';
-     				end if;
-     		when S1 =>
-			if ((day = '1') and (O = '1'))
-  				then NEXT_STATE <= S_OPEN;
-					door <= '1';
-					warn <= '0';
-				else
-					if (i = CODE2)
-     						then NEXT_STATE <= S2;
-							warn <= '0';
-						else
-							NEXT_STATE <= S_WARN;
-							warn <= '1';
-     						end if;
-     					door <='0';
-     				end if;
-     		when S2 =>
-			if ((day = '1') and (O = '1'))
-  				then NEXT_STATE <= S_OPEN;
-					door <= '1';
-					warn <= '0';
-				else
-					if (i = CODE3)
-						then NEXT_STATE <= S3;
-							warn <= '0';
-						else
-							NEXT_STATE <= S_WARN;
-							warn <= '1';
-     						end if;
-     					door <='0';
-     				end if;
-     		when S3 =>
-			if ((day = '1') and (O = '1'))
-  				then NEXT_STATE <= S_OPEN;
-					door <= '1';
-					warn <= '0';
-				else
-					if (i = CODE4)
-     						then NEXT_STATE <= S_OPEN;
-							door <= '1';
-							warn <= '0';
-						else
-							NEXT_STATE <= S_WARN;
-							door <= '0';
-							warn <= '1';
-     						end if;
-     				end if;
-     		when S_WARN =>
-     			NEXT_STATE <= S_WARN;
-     			door <='0';
-			warn <= '1';
-
-     		when S_OPEN =>
-     			NEXT_STATE <= S_OPEN;
-			door <= '1';
-			warn <= '0';
-
-     		when others =>
-     			assert ('1')
-			report "illegal state";
-     	end case;
-     end if;
-end process;
-process (ck)
-	 begin
-	 if (ck = '1' and not ck 'stable)
-	     then CURRENT_STATE <= NEXT_STATE;
-     end if;
-end process;
-end MOORE;
diff --git a/alliance/share/tutorials/synth/digicoder.enc b/alliance/share/tutorials/synth/digicoder.enc
deleted file mode 100644
index 9c895da3..00000000
--- a/alliance/share/tutorials/synth/digicoder.enc
+++ /dev/null
@@ -1,9 +0,0 @@
-# Encoding figure "digicoder"
--r 3
-s_warn	0
-s_open	6
-s_wait	4
-s3	5
-s2	7
-s1	1
-s0	2
diff --git a/alliance/share/tutorials/synth/digicoderg0sct.inf b/alliance/share/tutorials/synth/digicoderg0sct.inf
deleted file mode 100644
index c623f8a7..00000000
--- a/alliance/share/tutorials/synth/digicoderg0sct.inf
+++ /dev/null
@@ -1,9 +0,0 @@
-rename
-current_state_6.sff_m : current_state(6);
-current_state_5.sff_m : current_state(5);
-current_state_4.sff_m : current_state(4);
-current_state_3.sff_m : current_state(3);
-current_state_2.sff_m : current_state(2);
-current_state_1.sff_m : current_state(1);
-current_state_0.sff_m : current_state(0);
-end
diff --git a/alliance/share/tutorials/synth/digicodes.enc b/alliance/share/tutorials/synth/digicodes.enc
deleted file mode 100644
index b8d897cb..00000000
--- a/alliance/share/tutorials/synth/digicodes.enc
+++ /dev/null
@@ -1,9 +0,0 @@
-# Encoding figure "digicodes"
--o 7
-s_warn	0	1
-s_open	1	2
-s_wait	2	4
-s3	3	8
-s2	4	10
-s1	5	20
-s0	6	40
diff --git a/alliance/share/tutorials/synth/digicodesg0sct.inf b/alliance/share/tutorials/synth/digicodesg0sct.inf
deleted file mode 100644
index c623f8a7..00000000
--- a/alliance/share/tutorials/synth/digicodesg0sct.inf
+++ /dev/null
@@ -1,9 +0,0 @@
-rename
-current_state_6.sff_m : current_state(6);
-current_state_5.sff_m : current_state(5);
-current_state_4.sff_m : current_state(4);
-current_state_3.sff_m : current_state(3);
-current_state_2.sff_m : current_state(2);
-current_state_1.sff_m : current_state(1);
-current_state_0.sff_m : current_state(0);
-end
diff --git a/alliance/share/tutorials/synth/digicodesg3sct.inf b/alliance/share/tutorials/synth/digicodesg3sct.inf
deleted file mode 100644
index c623f8a7..00000000
--- a/alliance/share/tutorials/synth/digicodesg3sct.inf
+++ /dev/null
@@ -1,9 +0,0 @@
-rename
-current_state_6.sff_m : current_state(6);
-current_state_5.sff_m : current_state(5);
-current_state_4.sff_m : current_state(4);
-current_state_3.sff_m : current_state(3);
-current_state_2.sff_m : current_state(2);
-current_state_1.sff_m : current_state(1);
-current_state_0.sff_m : current_state(0);
-end
diff --git a/alliance/share/tutorials/synth/neto.lax b/alliance/share/tutorials/synth/neto.lax
deleted file mode 100644
index f75ba525..00000000
--- a/alliance/share/tutorials/synth/neto.lax
+++ /dev/null
@@ -1,15 +0,0 @@
-## Mode
-#M{2}
-## Level
-#L{2}
-## Number Transistor N
-#N{4}
-## Number Transistor P
-#P{4}
-## Fanout factor
-#T{1000}
-##Outputs capacitance
-#C{
-porte:1000;
-alarme:1000;
-}
diff --git a/alliance/share/tutorials/vasy/hadamard/1 b/alliance/share/tutorials/vasy/hadamard/1
deleted file mode 100644
index 1b6034d3..00000000
--- a/alliance/share/tutorials/vasy/hadamard/1
+++ /dev/null
@@ -1,2 +0,0 @@
-rm CATAL Makefile calcul.vhdl compteur.vhdl ex0.stim ex1.stim ex2.stim ex3.stim hadamard hadamard.stim hadamard.vhdl hadamard_1.pat hadamard_2.pat hadamard_3.pat hadamard_tb.vhdl ram.vhdl rom.vhdl sequenceur.vhdl
-cvs remove CATAL Makefile calcul.vhdl compteur.vhdl ex0.stim ex1.stim ex2.stim ex3.stim hadamard hadamard.stim hadamard.vhdl hadamard_1.pat hadamard_2.pat hadamard_3.pat hadamard_tb.vhdl ram.vhdl rom.vhdl sequenceur.vhdl
diff --git a/alliance/share/tutorials/vasy/hadamard/CATAL b/alliance/share/tutorials/vasy/hadamard/CATAL
deleted file mode 100644
index 9134d162..00000000
--- a/alliance/share/tutorials/vasy/hadamard/CATAL
+++ /dev/null
@@ -1,7 +0,0 @@
-calcul	C
-compteur	C
-hadamard_model	C
-ram	C
-rom	C
-sequenceur	C
-
diff --git a/alliance/share/tutorials/vasy/hadamard/Makefile b/alliance/share/tutorials/vasy/hadamard/Makefile
deleted file mode 100644
index ab796899..00000000
--- a/alliance/share/tutorials/vasy/hadamard/Makefile
+++ /dev/null
@@ -1,107 +0,0 @@
-# /*------------------------------------------------------------\
-# |                                                             |
-# | This file is part of the Alliance CAD System Copyright      |
-# | (C) Laboratoire LIP6 - Département ASIM Universite P&M Curie|
-# |                                                             |
-# | Home page      : http://www-asim.lip6.fr/alliance/          |
-# | E-mail support : mailto:alliance-support@asim.lip6.fr       |
-# |                                                             |
-# | This progam is  free software; you can redistribute it      |
-# | and/or modify it under the  terms of the GNU General Public |
-# | License as  published by the Free Software Foundation;      |
-# | either version 2 of the License, or (at your option) any    |
-# | later version.                                              |
-# |                                                             |
-# | Alliance VLSI  CAD System  is distributed  in the hope that |
-# | it  will be useful, but WITHOUT  ANY WARRANTY;              |
-# | without even the  implied warranty of MERCHANTABILITY or    |
-# | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General       |
-# | Public License for more details.                            |
-# |                                                             |
-# | You should have received a copy  of the GNU General Public  |
-# | License along with the GNU C Library; see the file COPYING. |
-# | If not, write to the Free Software Foundation, Inc.,        |
-# | 675 Mass Ave, Cambridge, MA 02139, USA.                     |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Tool   :                      VASY                          |
-# |                                                             |
-# | File   :                    Makefile                        |
-# |                                                             |
-# | Author :                 Jacomme Ludovic                    |
-# |                                                             |
-# | Date    :                   30_01_98                        |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-include $(ALLIANCE_TOP)/etc/$(ALLIANCE_OS).mk
-include $(ALLIANCE_TOP)/etc/libraries.mk
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                              Cells                          |
-# |                                                             |
-# \------------------------------------------------------------*/
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                             Binary                          |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-# VASY   = $(ALLIANCE_TOP)/bin/vasy
-VASY = $(HOME)/dev/bin/SunOS/vasy
-ASIMUT = $(ALLIANCE_TOP)/bin/asimut
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                            Environement                     |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-ENV_VASY = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
-           MBK_CATAL_NAME=NO_CATAL; export MBK_CATAL_NAME
-
-ENV_ASIMUT = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
-             MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME;\
-             MBK_IN_LO=vst; export MBK_IN_LO;\
-	     MBK_OUT_LO=vst; export MBK_OUT_LO
-
-all : result_1.pat result_2.pat result_3.pat
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                             Asimut                          |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-result_1.pat : hadamard.vst
-	$(ENV_ASIMUT); $(ASIMUT) hadamard hadamard_1 result_1 
-result_2.pat : hadamard.vst
-	$(ENV_ASIMUT); $(ASIMUT) hadamard hadamard_2 result_2 
-result_3.pat : hadamard.vst
-	$(ENV_ASIMUT); $(ASIMUT) hadamard hadamard_3 result_3 
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                             Vasy                            |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-hadamard.vst : hadamard.vhdl
-	$(ENV_VASY); $(VASY) -a -o -I vhdl -H hadamard
-
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                              Clean                          |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-realclean : clean
-
-clean     :
-	$(RM) -f *.vst *.vbe result_1.pat result_2.pat result_3.pat
-	
diff --git a/alliance/share/tutorials/vasy/hadamard/calcul.vhdl b/alliance/share/tutorials/vasy/hadamard/calcul.vhdl
deleted file mode 100644
index 7215b4e1..00000000
--- a/alliance/share/tutorials/vasy/hadamard/calcul.vhdl
+++ /dev/null
@@ -1,106 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-entity calcul is 
-port (
-   ramout  : in  std_logic_vector( 7 downto 0);
-   hadout  : out std_logic_vector(13 downto 0); 
-
-   ope     : in  std_logic;
-   hph     : in  std_logic;
-   vaccu   : in  std_logic;
-   clraccu : in  std_logic;
-   vbreg   : in  std_logic;
-   vhadout : in  std_logic;
-   c2i     : in  std_logic;
-
-   reset   : in  std_logic;
-   ck      : in  std_logic);
-
-end calcul;
-
-
-
-architecture behavioral of calcul is
-
-   type pile is array (0 to 7) of std_logic_vector (13 downto 0);
-    
-
-  signal op      : std_logic_vector(13 downto 0);
-  signal mux     : std_logic_vector(13 downto 0);
-  signal alu     : std_logic_vector(13 downto 0);
-  signal re      : std_logic_vector(13 downto 0);
-  signal rhadout : std_logic_vector(13 downto 0);
-
-  signal accu    : std_logic_vector(13 downto 0);
-  signal breg    : pile ;
- 
-begin
-
--- le multiplexeur d'abord --
--- *********************** --
-
-   mux <= breg (7)  when hph='0' else "000000"&ramout; 
-  
--- calcul alu --
--- ********** --
-
-  op(13 downto 0) <= "11111111111111" when ope='1' else
-                     "00000000000000";
-  
-  re(0) <= (accu(0) xor ope) and mux(0);
-  re(13 downto 1) <= (mux(12 downto 0) and re(12 downto 0) ) 
-                  or (    ( accu(12 downto 0) xor op(12 downto 0)) 
-                      and ( mux(12 downto 0)   or re(12 downto 0)) ); 
-   
-  alu <= accu xor mux xor (re(13 downto 1) & '0');
-
-
--- accumulateur --
--- ************ --
-
-  process (ck)
-  begin
-    if (ck='0' and ck'event ) then
-      if (clraccu='1') then accu <= (others =>'0');
-      elsif (vaccu='1') 
-         then accu <= alu;
-        else accu <= accu;
-      end if;
-    end if;
-  end process;
-
--- registre de sortie --
--- ****************** --
-
-  process (ck)
-  begin
-    if (ck='0' and ck'event ) then
-      if (reset='1') then rhadout <= (others =>'0');
-      elsif (vhadout='1') 
-         then rhadout <= accu;
-        else rhadout <= rhadout;
-      end if;
-    end if;
-  end process;
-  hadout <= rhadout;
-
--- banc de regsitres a decalage --
--- **************************** --
-
-  process (ck)
-  begin
-    if (ck='0' and ck'event)
-    then 
-      if (c2i='1')
-      then
-        if (vbreg='1')
-        then breg(0) <= alu;
-	else breg(0) <= breg(7);
-	end if;
-        breg (1 to 7) <= breg (0 to 6);
-      end if;
-    end if;
-  end process;
-
-end behavioral;
diff --git a/alliance/share/tutorials/vasy/hadamard/compteur.vhdl b/alliance/share/tutorials/vasy/hadamard/compteur.vhdl
deleted file mode 100644
index 89ce19b3..00000000
--- a/alliance/share/tutorials/vasy/hadamard/compteur.vhdl
+++ /dev/null
@@ -1,50 +0,0 @@
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_arith.ALL;
-use IEEE.STD_LOGIC_unsigned.ALL;
-
-entity compteur is
-      port ( c1i   : in  std_logic;
-             c2i   : in  std_logic;
-             loi   : in  std_logic;
-             c1    : out std_logic_vector (2 downto 0) ;
-             c2    : out std_logic_vector (2 downto 0) ;
-             lo    : out std_logic_vector (2 downto 0) ;
-             reset : in  std_logic;
-             ck    : in  std_logic );
-end compteur;
-
-architecture behavioral of compteur is
-
-   signal rc1 :  integer range 0 to 7;
-   signal rc2 :  integer range 0 to 7;
-   signal rlo :  integer range 0 to 7;
-
-begin
-
-  process (ck)
-  begin
-    if (ck='0' and ck'event) then
-      if (reset='1') then rc1<=0; rc2<=0; rlo<=0;
-      else
-        if c1i='1' then rc1 <= (rc1 + 1) mod 8;
-                   else rc1 <= rc1;
-        end if;
-        if c2i='1' then rc2 <= (rc2 + 1) mod 8;
-                   else rc2 <= rc2;
-        end if;
-        if loi='1' then rlo <= (rlo + 1) mod 8; 
-                   else rlo <= rlo; 
-        end if;  
-      end if;
-    end if; 
-  end process;
-
-
-  c1 <= (conv_std_logic_vector(rc1,c1'length));
-  c2 <= (conv_std_logic_vector (rc2,c2'length));  
-  lo <= (conv_std_logic_vector (rlo,lo'length));
-
-end behavioral;
-
diff --git a/alliance/share/tutorials/vasy/hadamard/ex0.stim b/alliance/share/tutorials/vasy/hadamard/ex0.stim
deleted file mode 100644
index 98777ef6..00000000
--- a/alliance/share/tutorials/vasy/hadamard/ex0.stim
+++ /dev/null
@@ -1,4070 +0,0 @@
-# I --->
-#        ef        f0        f1        f2         1         2         3         4 
-#        f3        f4        f5        f6         5         6         7         8 
-#        f7        f8        f9        fa         9         a         b         c 
-#        fb        fc        fd        fe         d         e         f        10 
-#         1         2         3         4         1         2         3         4 
-#         5         6         7         8         5         6         7         8 
-#         9         a         b         c         9         a         b         c 
-#         d         e         f        10         d         e         f        10 
-# HI --->
-#      3f0      3f8      400      408       38       40       48       50 
-#      3b8      3b8      3b8      3b8        0        0        0        0 
-#        0        0        0        0        0        0        0        0 
-# ffffffe0 ffffffe0 ffffffe0 ffffffe0 ffffffe0 ffffffe0 ffffffe0 ffffffe0 
-#        0        0        0        0        0        0        0        0 
-#        0        0        0        0        0        0        0        0 
-#        0        0        0        0        0        0        0        0 
-# fffffff0 fffffff0 fffffff0 fffffff0 fffffff0 fffffff0 fffffff0 fffffff0 
-# HIH --->
-#      1100       ee0         0  ffffffc0         0         0         0  ffffffe0 
-#       ee0       ee0         0         0         0         0         0         0 
-#         0         0         0         0         0         0         0         0 
-#  ffffff00         0         0         0         0         0         0         0 
-#         0         0         0         0         0         0         0         0 
-#         0         0         0         0         0         0         0         0 
-#         0         0         0         0         0         0         0         0 
-#  ffffff80         0         0         0         0         0         0         0 
-# Reset
- 000000000001
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diff --git a/alliance/share/tutorials/vasy/hadamard/ex1.stim b/alliance/share/tutorials/vasy/hadamard/ex1.stim
deleted file mode 100644
index 7f8c7e91..00000000
--- a/alliance/share/tutorials/vasy/hadamard/ex1.stim
+++ /dev/null
@@ -1,4070 +0,0 @@
-# I --->
-#         1         2         3         4         5         6         7         0 
-#         1         2         3         4         5         6         7         0 
-#         1         2         3         4         5         6         7         0 
-#         1         2         3         4         5         6         7         0 
-#         1         2         3         4         5         6         7         0 
-#         1         2         3         4         5         6         7         0 
-#         1         2         3         4         5         6         7         0 
-#         1         2         3         4         5         6         7         0 
-# HI --->
-#        8       10       18       20       28       30       38        0 
-#        0        0        0        0        0        0        0        0 
-#        0        0        0        0        0        0        0        0 
-#        0        0        0        0        0        0        0        0 
-#        0        0        0        0        0        0        0        0 
-#        0        0        0        0        0        0        0        0 
-#        0        0        0        0        0        0        0        0 
-#        0        0        0        0        0        0        0        0 
-# HIH --->
-#        e0  ffffffc0  ffffffc0         0  ffffffc0        40  ffffffc0        20 
-#         0         0         0         0         0         0         0         0 
-#         0         0         0         0         0         0         0         0 
-#         0         0         0         0         0         0         0         0 
-#         0         0         0         0         0         0         0         0 
-#         0         0         0         0         0         0         0         0 
-#         0         0         0         0         0         0         0         0 
-#         0         0         0         0         0         0         0         0 
-# Reset
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diff --git a/alliance/share/tutorials/vasy/hadamard/ex2.stim b/alliance/share/tutorials/vasy/hadamard/ex2.stim
deleted file mode 100644
index 6abc0f59..00000000
--- a/alliance/share/tutorials/vasy/hadamard/ex2.stim
+++ /dev/null
@@ -1,4070 +0,0 @@
-# I --->
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-#         0         0         0         1         1         0         0         0 
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-#         0         0         0         0         0         0         0         0 
-# HI --->
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-#        0 ffffffff        0 fffffffe fffffffe ffffffff ffffffff        0 
-#        0 ffffffff        0        0        0        1 ffffffff        0 
-# HIH --->
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-#  ffffffff         3         1         1         1  fffffffd  ffffffff  ffffffff 
-#  fffffff1         1         7         3         7  ffffffff         1  fffffffd 
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diff --git a/alliance/share/tutorials/vasy/hadamard/ex3.stim b/alliance/share/tutorials/vasy/hadamard/ex3.stim
deleted file mode 100644
index 75dac7c0..00000000
--- a/alliance/share/tutorials/vasy/hadamard/ex3.stim
+++ /dev/null
@@ -1,4070 +0,0 @@
-# I --->
-#        11        11        11        11        11        11        11        11 
-#        11        11        11        11        11        11        11        11 
-#        11        11        11        11        11        11        11        11 
-#        11        11        11        11        11        11        11        11 
-#        11        11        11        11        11        11        11        11 
-#        11        11        11        11        11        11        11        11 
-#        11        11        11        11        11        11        11        11 
-#        11        11        11        11        11        11        11        11 
-# HI --->
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-#        0        0        0        0        0        0        0        0 
-#        0        0        0        0        0        0        0        0 
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-#        0        0        0        0        0        0        0        0 
-#        0        0        0        0        0        0        0        0 
-# HIH --->
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diff --git a/alliance/share/tutorials/vasy/hadamard/hadamard.stim b/alliance/share/tutorials/vasy/hadamard/hadamard.stim
deleted file mode 100644
index 7f8c7e91..00000000
--- a/alliance/share/tutorials/vasy/hadamard/hadamard.stim
+++ /dev/null
@@ -1,4070 +0,0 @@
-# I --->
-#         1         2         3         4         5         6         7         0 
-#         1         2         3         4         5         6         7         0 
-#         1         2         3         4         5         6         7         0 
-#         1         2         3         4         5         6         7         0 
-#         1         2         3         4         5         6         7         0 
-#         1         2         3         4         5         6         7         0 
-#         1         2         3         4         5         6         7         0 
-#         1         2         3         4         5         6         7         0 
-# HI --->
-#        8       10       18       20       28       30       38        0 
-#        0        0        0        0        0        0        0        0 
-#        0        0        0        0        0        0        0        0 
-#        0        0        0        0        0        0        0        0 
-#        0        0        0        0        0        0        0        0 
-#        0        0        0        0        0        0        0        0 
-#        0        0        0        0        0        0        0        0 
-#        0        0        0        0        0        0        0        0 
-# HIH --->
-#        e0  ffffffc0  ffffffc0         0  ffffffc0        40  ffffffc0        20 
-#         0         0         0         0         0         0         0         0 
-#         0         0         0         0         0         0         0         0 
-#         0         0         0         0         0         0         0         0 
-#         0         0         0         0         0         0         0         0 
-#         0         0         0         0         0         0         0         0 
-#         0         0         0         0         0         0         0         0 
-#         0         0         0         0         0         0         0         0 
-# Reset
- 000000000001
- 100000000001
- 000000000001
-# Ram
- 000000001000
- 100000001000
- 000000001000
- 000000001000
- 100000001000
- 000000001000
- 000000010000
- 100000010000
- 000000010000
- 000000010000
- 100000010000
- 000000010000
- 000000011000
- 100000011000
- 000000011000
- 000000011000
- 100000011000
- 000000011000
- 000000100000
- 100000100000
- 000000100000
- 000000100000
- 100000100000
- 000000100000
- 000000101000
- 100000101000
- 000000101000
- 000000101000
- 100000101000
- 000000101000
- 000000110000
- 100000110000
- 000000110000
- 000000110000
- 100000110000
- 000000110000
- 000000111000
- 100000111000
- 000000111000
- 000000111000
- 100000111000
- 000000111000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000001000
- 100000001000
- 000000001000
- 000000001000
- 100000001000
- 000000001000
- 000000010000
- 100000010000
- 000000010000
- 000000010000
- 100000010000
- 000000010000
- 000000011000
- 100000011000
- 000000011000
- 000000011000
- 100000011000
- 000000011000
- 000000100000
- 100000100000
- 000000100000
- 000000100000
- 100000100000
- 000000100000
- 000000101000
- 100000101000
- 000000101000
- 000000101000
- 100000101000
- 000000101000
- 000000110000
- 100000110000
- 000000110000
- 000000110000
- 100000110000
- 000000110000
- 000000111000
- 100000111000
- 000000111000
- 000000111000
- 100000111000
- 000000111000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000001000
- 100000001000
- 000000001000
- 000000001000
- 100000001000
- 000000001000
- 000000010000
- 100000010000
- 000000010000
- 000000010000
- 100000010000
- 000000010000
- 000000011000
- 100000011000
- 000000011000
- 000000011000
- 100000011000
- 000000011000
- 000000100000
- 100000100000
- 000000100000
- 000000100000
- 100000100000
- 000000100000
- 000000101000
- 100000101000
- 000000101000
- 000000101000
- 100000101000
- 000000101000
- 000000110000
- 100000110000
- 000000110000
- 000000110000
- 100000110000
- 000000110000
- 000000111000
- 100000111000
- 000000111000
- 000000111000
- 100000111000
- 000000111000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000001000
- 100000001000
- 000000001000
- 000000001000
- 100000001000
- 000000001000
- 000000010000
- 100000010000
- 000000010000
- 000000010000
- 100000010000
- 000000010000
- 000000011000
- 100000011000
- 000000011000
- 000000011000
- 100000011000
- 000000011000
- 000000100000
- 100000100000
- 000000100000
- 000000100000
- 100000100000
- 000000100000
- 000000101000
- 100000101000
- 000000101000
- 000000101000
- 100000101000
- 000000101000
- 000000110000
- 100000110000
- 000000110000
- 000000110000
- 100000110000
- 000000110000
- 000000111000
- 100000111000
- 000000111000
- 000000111000
- 100000111000
- 000000111000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000001000
- 100000001000
- 000000001000
- 000000001000
- 100000001000
- 000000001000
- 000000010000
- 100000010000
- 000000010000
- 000000010000
- 100000010000
- 000000010000
- 000000011000
- 100000011000
- 000000011000
- 000000011000
- 100000011000
- 000000011000
- 000000100000
- 100000100000
- 000000100000
- 000000100000
- 100000100000
- 000000100000
- 000000101000
- 100000101000
- 000000101000
- 000000101000
- 100000101000
- 000000101000
- 000000110000
- 100000110000
- 000000110000
- 000000110000
- 100000110000
- 000000110000
- 000000111000
- 100000111000
- 000000111000
- 000000111000
- 100000111000
- 000000111000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000001000
- 100000001000
- 000000001000
- 000000001000
- 100000001000
- 000000001000
- 000000010000
- 100000010000
- 000000010000
- 000000010000
- 100000010000
- 000000010000
- 000000011000
- 100000011000
- 000000011000
- 000000011000
- 100000011000
- 000000011000
- 000000100000
- 100000100000
- 000000100000
- 000000100000
- 100000100000
- 000000100000
- 000000101000
- 100000101000
- 000000101000
- 000000101000
- 100000101000
- 000000101000
- 000000110000
- 100000110000
- 000000110000
- 000000110000
- 100000110000
- 000000110000
- 000000111000
- 100000111000
- 000000111000
- 000000111000
- 100000111000
- 000000111000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000001000
- 100000001000
- 000000001000
- 000000001000
- 100000001000
- 000000001000
- 000000010000
- 100000010000
- 000000010000
- 000000010000
- 100000010000
- 000000010000
- 000000011000
- 100000011000
- 000000011000
- 000000011000
- 100000011000
- 000000011000
- 000000100000
- 100000100000
- 000000100000
- 000000100000
- 100000100000
- 000000100000
- 000000101000
- 100000101000
- 000000101000
- 000000101000
- 100000101000
- 000000101000
- 000000110000
- 100000110000
- 000000110000
- 000000110000
- 100000110000
- 000000110000
- 000000111000
- 100000111000
- 000000111000
- 000000111000
- 100000111000
- 000000111000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000001000
- 100000001000
- 000000001000
- 000000001000
- 100000001000
- 000000001000
- 000000010000
- 100000010000
- 000000010000
- 000000010000
- 100000010000
- 000000010000
- 000000011000
- 100000011000
- 000000011000
- 000000011000
- 100000011000
- 000000011000
- 000000100000
- 100000100000
- 000000100000
- 000000100000
- 100000100000
- 000000100000
- 000000101000
- 100000101000
- 000000101000
- 000000101000
- 100000101000
- 000000101000
- 000000110000
- 100000110000
- 000000110000
- 000000110000
- 100000110000
- 000000110000
- 000000111000
- 100000111000
- 000000111000
- 000000111000
- 100000111000
- 000000111000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
-# HIH 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
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- 000000000000
- 100000000000
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- 100000000000
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- 000000000000
- 100000000000
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- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
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- 000000000000
- 100000000000
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- 100000000000
- 000000000000
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- 100000000000
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- 100000000000
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- 100000000000
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- 100000000000
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- 100000000000
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- 100000000000
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- 100000000000
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- 100000000000
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- 100000000000
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- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
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- 100000000000
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- 100000000000
- 000000000000
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- 100000000000
- 000000000000
- 000000000000
- 100000000000
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- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
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- 100000000000
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- 100000000000
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- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
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- 100000000000
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- 000000000000
- 100000000000
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- 000000000000
- 100000000000
- 000000000000
- 000000000000
- 100000000000
- 000000000000
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- 100000000000
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- 100000000000
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- 100000000000
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- 100000000000
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- 100000000000
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- 100000000000
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- 100000000000
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- 100000000000
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- 100000000000
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- 100000000000
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- 100000000000
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- 100000000000
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- 100000000000
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diff --git a/alliance/share/tutorials/vasy/hadamard/hadamard.vhdl b/alliance/share/tutorials/vasy/hadamard/hadamard.vhdl
deleted file mode 100644
index a18f7acc..00000000
--- a/alliance/share/tutorials/vasy/hadamard/hadamard.vhdl
+++ /dev/null
@@ -1,159 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-entity hadamard is
-  port ( ck     : in    std_logic;
-         data   : in    std_logic_vector (7 downto 0);
-         empty  : in    std_logic;
-         full   : in    std_logic;
-         reset  : in    std_logic;
-         hadout : out   std_logic_vector (13 downto 0);
-         s_read   : out   std_logic;
-         s_write  : out   std_logic );
-end hadamard;
-
-architecture schematic of hadamard is
-
-   signal ramout   : std_logic_vector(7 downto 0);
-   signal ope      : std_logic;
-   signal hph      : std_logic;
-   signal vaccu    : std_logic;
-   signal clraccu  : std_logic;
-   signal vbreg    : std_logic;
-   signal vhadout  : std_logic;
-   signal c1       : std_logic_vector(2 downto 0);
-   signal c2       : std_logic_vector(2 downto 0);
-   signal c1c2     : std_logic_vector(5 downto 0);
-   signal lo       : std_logic_vector(2 downto 0);
-   signal loi      : std_logic;
-   signal c2i      : std_logic;
-   signal c1i      : std_logic;
-   signal readout  : std_logic;
-   signal nreadout : std_logic;
-   signal nck      : std_logic;
-
-   component calcul
-      port( ramout  : in  std_logic_vector ( 7 downto 0);
-            hadout  : out std_logic_vector (13 downto 0);
-            ope     : in  std_logic;
-            hph     : in  std_logic;
-            vaccu   : in  std_logic;
-            clraccu : in  std_logic;
-            vbreg   : in  std_logic;
-            vhadout : in  std_logic;
-            c2i     : in  std_logic;
-            reset   : in  std_logic;
-            ck      : in  std_logic );
-   end component;  
-
-   component sequenceur
-      port( c1        : in  std_logic_vector (2 downto 0);
-            c2        : in  std_logic_vector (2 downto 0);
-            lo        : in  std_logic_vector (2 downto 0);
-            ck        : in  std_logic;
-            empty     : in  std_logic;
-            full      : in  std_logic;
-            reset     : in  std_logic;
-            c1i       : out std_logic;
-            c2i       : out std_logic;
-            loi       : out std_logic;
-            clraccu   : out std_logic;
-            hph       : out std_logic;
-            s_read    : out std_logic;
-            vaccu     : out std_logic;
-            vbreg     : out std_logic;
-            vhadout   : out std_logic;
-            s_write   : out std_logic );
-   end component;
-
-   component compteur
-      port( c1i     : in  std_logic;
-            c2i     : in  std_logic;
-            loi     : in  std_logic;
-            c1      : out std_logic_vector (2 downto 0);
-            c2      : out std_logic_vector (2 downto 0);
-            lo      : out std_logic_vector (2 downto 0) ; 
-            reset   : in  std_logic;
-            ck      : in  std_logic );
-   end component;
-
-   component rom
-      port( c1      : in  std_logic_vector (2 downto 0);
-            c2      : in  std_logic_vector (2 downto 0);
-            hph     : in  std_logic;
-            lo      : in  std_logic_vector (2 downto 0);
-            ope     : out std_logic );
-   end component;  
-                   
-   component ram  
-     port ( A        : in std_logic_vector(5 downto 0);
-            CEB, WEB : in std_logic;
-            INN      : in  std_logic_vector(7 downto 0);
-            OUTT     : out std_logic_vector(7 downto 0) );
-   end component;
-   
-begin
-
-   c1c2     <= c1&c2;
-   s_read   <= readout;
-   nreadout <= not(readout);
-   nck      <= not(ck);
-
-   e_ram : ram        
-     port map( A    => c1c2
-             , CEB  => nck
-             , WEB  => nreadout
-             , INN  => data
-             , OUTT => ramout );
-
-   e_calcul : calcul
-     port map( ramout  => ramout
-             , hadout  => hadout
-             , ope     => ope
-             , hph     => hph
-             , vaccu   => vaccu
-             , clraccu => clraccu
-             , vbreg   => vbreg
-             , vhadout => vhadout
-             , c2i     => c2i
-             , reset   => reset
-             , ck      => ck );
-
-   e_sequenceur : sequenceur 
-     port map( c1      => c1
-             , c2      => c2
-             , lo      => lo
-             , ck      => ck
-             , empty   => empty
-             , full    => full
-             , reset   => reset
-             , c1i     => c1i
-             , c2i     => c2i
-             , loi     => loi
-             , clraccu => clraccu
-             , hph     => hph
-             , s_read  => readout
-             , vaccu   => vaccu
-             , vbreg   => vbreg
-             , vhadout => vhadout
-             , s_write => s_write );
-
-   e_rom : rom
-     port map( c1      => c1
-             , c2      => c2 
-             , lo      => lo 
-             , hph     => hph
-             , ope     => ope );
-                      
-   e_compteur : compteur
-     port map( c1i     => c1i 
-             , c2i     => c2i 
-             , loi     => loi 
-             , c1      => c1
-             , c2      => c2
-             , lo      => lo
-             , reset   => reset
-             , ck      => ck  );
-
-end schematic;
-
diff --git a/alliance/share/tutorials/vasy/hadamard/hadamard_1.pat b/alliance/share/tutorials/vasy/hadamard/hadamard_1.pat
deleted file mode 100644
index c58fea7f..00000000
--- a/alliance/share/tutorials/vasy/hadamard/hadamard_1.pat
+++ /dev/null
@@ -1,4056 +0,0 @@
-
-in       ck B;
-in       data (7 downto 0) B;
-in       empty B;
-in       full B;
-in       reset B;
-out      hadout (13 downto 0) X;
-out      s_read B;
-out      s_write B;
-
-begin
-
--- PATTERN DESCRIPTION :
-
- : 000000000001 ?**** ?0 ?0;
- : 100000000001 ?**** ?0 ?0;
- : 000000000001 ?0000 ?0 ?0;
- : 000000001000 ?0000 ?0 ?0;
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-
-end;
diff --git a/alliance/share/tutorials/vasy/hadamard/hadamard_2.pat b/alliance/share/tutorials/vasy/hadamard/hadamard_2.pat
deleted file mode 100644
index 1559b971..00000000
--- a/alliance/share/tutorials/vasy/hadamard/hadamard_2.pat
+++ /dev/null
@@ -1,4057 +0,0 @@
-
-in       ck B;
-in       data (7 downto 0) B;
-in       empty B;
-in       full B;
-in       reset B;
-out      hadout (13 downto 0) X;
-out      s_read B;
-out      s_write B;
-
-begin
-
--- PATTERN DESCRIPTION :
-
-
- : 000000000001 ?**** ?0 ?0;
- : 100000000001 ?**** ?0 ?0;
- : 000000000001 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
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- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?1 ?0;
- : 000000000000 ?0000 ?1 ?0;
- : 100000000000 ?0000 ?1 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?1 ?0;
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- : 100000000000 ?0001 ?0 ?0;
- : 000000000000 ?0001 ?0 ?1;
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- : 000000000000 ?0001 ?0 ?0;
- : 100000000000 ?0001 ?0 ?0;
- : 000000000000 ?0001 ?0 ?0;
- : 000000000000 ?0001 ?0 ?0;
- : 100000000000 ?0001 ?0 ?0;
- : 000000000000 ?0001 ?0 ?0;
- : 000000000000 ?0001 ?0 ?0;
- : 100000000000 ?0001 ?0 ?0;
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- : 000000000000 ?0001 ?0 ?0;
-
-end;
diff --git a/alliance/share/tutorials/vasy/hadamard/hadamard_3.pat b/alliance/share/tutorials/vasy/hadamard/hadamard_3.pat
deleted file mode 100644
index 0cfc3113..00000000
--- a/alliance/share/tutorials/vasy/hadamard/hadamard_3.pat
+++ /dev/null
@@ -1,4057 +0,0 @@
-
-in       ck B;
-in       data (7 downto 0) B;
-in       empty B;
-in       full B;
-in       reset B;
-out      hadout (13 downto 0) X;
-out      s_read B;
-out      s_write B;
-
-begin
-
--- PATTERN DESCRIPTION :
-
-
- : 000000000001 ?**** ?0 ?0;
- : 100000000001 ?**** ?0 ?0;
- : 000000000001 ?0000 ?0 ?0;
- : 000010001000 ?0000 ?0 ?0;
- : 100010001000 ?0000 ?0 ?0;
- : 000010001000 ?0000 ?1 ?0;
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- : 000010001000 ?0000 ?0 ?0;
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- : 000010001000 ?0000 ?1 ?0;
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- : 000010001000 ?0000 ?1 ?0;
- : 000010001000 ?0000 ?1 ?0;
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- : 000010001000 ?0000 ?0 ?0;
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- : 000010001000 ?0000 ?1 ?0;
- : 000010001000 ?0000 ?1 ?0;
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- : 000000000000 ?0000 ?0 ?0;
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- : 000000000000 ?0000 ?0 ?0;
- : 000010001000 ?0000 ?0 ?0;
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- : 000000000000 ?0000 ?0 ?0;
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- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?1;
- : 000000000000 ?0000 ?0 ?1;
- : 100000000000 ?0000 ?0 ?1;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?1;
- : 000000000000 ?0000 ?0 ?1;
- : 100000000000 ?0000 ?0 ?1;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?1;
- : 000000000000 ?0000 ?0 ?1;
- : 100000000000 ?0000 ?0 ?1;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?1;
- : 000000000000 ?0000 ?0 ?1;
- : 100000000000 ?0000 ?0 ?1;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?1;
- : 000000000000 ?0000 ?0 ?1;
- : 100000000000 ?0000 ?0 ?1;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
- : 100000000000 ?0000 ?0 ?0;
- : 000000000000 ?0000 ?0 ?0;
-
-end;
diff --git a/alliance/share/tutorials/vasy/hadamard/hadamard_tb.vhdl b/alliance/share/tutorials/vasy/hadamard/hadamard_tb.vhdl
deleted file mode 100644
index 1a803b9a..00000000
--- a/alliance/share/tutorials/vasy/hadamard/hadamard_tb.vhdl
+++ /dev/null
@@ -1,112 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_TEXTIO.ALL;
-
-entity hadamard_tb is
-end hadamard_tb;
-
-architecture test_bench of hadamard_tb is
-
-component hadamard
-  port ( ck     : in    std_logic;
-         data   : in    std_logic_vector (7 downto 0);
-         empty  : in    std_logic;
-         full   : in    std_logic;
-         reset  : in    std_logic;
-         hadout : out   std_logic_vector (13 downto 0);
-         s_read   : out   std_logic;
-         s_write  : out   std_logic );
-end component;
-
-  signal i_ck     : std_logic;
-  signal i_data   : std_logic_vector (7 downto 0);
-  signal i_empty  : std_logic;
-  signal i_full   : std_logic;
-  signal i_reset  : std_logic;
-  signal i_hadout : std_logic_vector (13 downto 0);
-  signal i_read   : std_logic;
-  signal i_write  : std_logic;
-
-begin
-
-  InsHadamard : hadamard 
-
-   port map( i_ck, i_data, i_empty, i_full, i_reset, 
-             i_hadout, i_read, i_write );
-
-
-  Stimulus:
-    process
---use IEEE.STD_LOGIC_TEXTIO.ALL;
-  use STD.TEXTIO.ALL;
-      FILE infile: TEXT is IN "hadamard.stim";
-        FILE outfile: TEXT is OUT "hadamard_res.stim";
-
-        VARIABLE L1, L2: LINE;
-
-  variable v_char   : character;
-  variable v_ck     : std_logic;
-  variable v_data   : std_logic_vector (7 downto 0);
-  variable v_empty  : std_logic;
-  variable v_full   : std_logic;
-  variable v_reset  : std_logic;
-  variable v_hadout : std_logic_vector (13 downto 0);
-  variable v_read   : std_logic;
-  variable v_write  : std_logic;
-
-    begin
-      While not (endfile(infile)) loop
-        readline (infile,L1);
-
-        read( L1, v_char);
-
-        if ( v_char = '#' )
-        then writeline(outfile,L1);
-             next;
-        end if;
-        
-        read( L1, v_ck);
-        read( L1, v_data);
-        read( L1, v_empty);
-        read( L1, v_full);
-        read( L1, v_reset);
-
-        i_ck <= v_ck;
-        i_data <= v_data;
-        i_empty <= v_empty;
-        i_full <= v_full;
-        i_reset <= v_reset;
-
-         wait for 100 ns;
-
-        write( L2, i_ck);
-        write( L2, i_data);
-        write( L2, i_empty);
-        write( L2, i_full);
-        write( L2, i_reset);
-        write( L2, i_hadout);
-        write( L2, i_read);
-        write( L2, i_write);
-
-        writeline (outfile,L2);
-           
-      end loop;
-
-      ASSERT FALSE REPORT "End of simulation !!!"
-      SEVERITY ERROR;
-
-      wait;  -- to terminate simulation
-    end process;
-
-end test_bench;
-
-configuration CFG_test_bench of hadamard_tb is
-use WORK.all;
-
-  for test_bench
-     FOR InsHadamard : Hadamard
-       use entity WORK.Hadamard(schematic);
-     end for;
-  end for;
-
-end CFG_test_bench;
diff --git a/alliance/share/tutorials/vasy/hadamard/ram.vhdl b/alliance/share/tutorials/vasy/hadamard/ram.vhdl
deleted file mode 100644
index 8aad25f8..00000000
--- a/alliance/share/tutorials/vasy/hadamard/ram.vhdl
+++ /dev/null
@@ -1,39 +0,0 @@
----------------------------------------------------------
-----------------    Bank  description    ----------------
----------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_arith.ALL;
-use IEEE.STD_LOGIC_unsigned.ALL;
---use IEEE.STD_LOGIC_signed.ALL;
-
-ENTITY ram IS
-  port ( A        : in std_logic_vector(5 downto 0);
-         CEB, WEB : in std_logic;
-         INN      : in  std_logic_vector(7 downto 0);
-         OUTT     : out std_logic_vector(7 downto 0)
-  );
-END ram;
-
-ARCHITECTURE dataflow_view OF ram IS
-
-  SUBTYPE TYPE_WORD IS std_logic_vector(7 downto 0);
-  TYPE TYPE_RAM IS ARRAY(63 DOWNTO 0) OF TYPE_WORD;
-  SIGNAL memory : TYPE_RAM;
-
-BEGIN
-
-  OUTT <= memory( CONV_INTEGER( A ) );
-
-  RAM_0 : PROCESS( CEB )
-  BEGIN
-   IF (CEB='0' AND CEB'EVENT )
-   THEN IF (WEB='0')
-        THEN memory( CONV_INTEGER( A ) ) <= INN;
-        END IF;
-   END IF;
-
-  END PROCESS RAM_0;
-
-END dataflow_view;
diff --git a/alliance/share/tutorials/vasy/hadamard/rom.vhdl b/alliance/share/tutorials/vasy/hadamard/rom.vhdl
deleted file mode 100644
index cd0e08f0..00000000
--- a/alliance/share/tutorials/vasy/hadamard/rom.vhdl
+++ /dev/null
@@ -1,26 +0,0 @@
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_unsigned.ALL;
-use IEEE.STD_LOGIC_arith.ALL;
-
-entity rom is
-      port ( c1  : in  std_logic_vector (2 downto 0);
-             c2  : in  std_logic_vector (2 downto 0);
-             hph : in  std_logic;
-             lo  : in  std_logic_vector (2 downto 0);
-             ope : out std_logic );
-end rom;
-
-architecture behavioral of rom is
-
-   signal adr : std_logic_vector (5 downto 0);
-   constant rom_data : std_logic_vector(0 to 63) := "0000000000001111001111000011001101100110011010010101101001010101";
-   
-   begin
-     
-     adr <= c2(2 downto 0)&c1(2 downto 0) when hph='0' else
-            lo(2 downto 0)&c1(2 downto 0) ;
-             
-     ope <= rom_data(conv_integer(Adr));
-end behavioral;
diff --git a/alliance/share/tutorials/vasy/hadamard/sequenceur.vhdl b/alliance/share/tutorials/vasy/hadamard/sequenceur.vhdl
deleted file mode 100644
index 3270b274..00000000
--- a/alliance/share/tutorials/vasy/hadamard/sequenceur.vhdl
+++ /dev/null
@@ -1,249 +0,0 @@
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-entity sequenceur is
-      port ( c1       : in  std_logic_vector (2 downto 0);
-             c2       : in  std_logic_vector (2 downto 0);
-             lo       : in  std_logic_vector (2 downto 0);
-             ck       : in  std_logic;
-             empty    : in  std_logic;
-             full     : in  std_logic;
-             reset    : in  std_logic;
-             c1i      : out std_logic;
-             c2i      : out std_logic;
-             clraccu  : out std_logic;
-             hph      : out std_logic;
-             loi      : out std_logic;
-             s_read   : out std_logic;
-             vaccu    : out std_logic;
-             vbreg    : out std_logic;
-             vhadout  : out std_logic;
-             s_write  : out std_logic );
-end sequenceur;
-
-
-architecture behavioral of sequenceur is
-
-  type etat_type is (E0,E1,E2,E3,E4,E5,E6,E7,E8,E9,E10);
-  signal next_state,current_state : etat_type;
-
-begin
-  
-process (current_state,reset,empty,full,c1,c2,lo)
- begin
-   if (reset='1') then
-   
-     next_state <= E0;
-
-     s_read  <= '0';
-     s_write <= '0';
-     clraccu <= '1';
-     hph     <= '0';
-     vhadout <= '0';
-     vaccu   <= '0';
-     vbreg   <= '0';
-     c1i     <= '0';
-     c2i     <= '0';
-     loi     <= '0';
-
-   else
-      case current_state is
-
-        when E0 =>
-
-          next_state <= E1;
-
-          s_read     <= '0';
-          s_write    <= '0';
-          clraccu    <= '1';
-          hph        <= '0';
-          vhadout    <= '0';
-          vaccu      <= '0';
-          vbreg      <= '0';
-          c1i        <= '0';
-          c2i        <= '0';
-          loi        <= '0';
-
-        when E1 =>
-
-          if (empty = '1') then next_state <= E1;
-                           else next_state <= E2;
-          end if; 
-
-          s_read  <= '1';
-          s_write <= '0';
-          clraccu <= '0';
-          hph     <= '0';
-          vhadout <= '0';
-          vaccu   <= '0';
-          vbreg   <= '0';
-          c1i     <= '0';
-          c2i     <= '0';
-          loi     <= '0';
-          
-        when E2 =>
-
-          if (c2 = "111") then next_state <= E3;
-                          else next_state <= E1;
-          end if;
-
-          s_read  <= '0';
-          s_write <= '0';
-          clraccu <= '0';
-          hph     <= '0';
-          vhadout <= '0';
-          vaccu   <= '0';
-          vbreg   <= '0';
-          c1i     <= '0';
-          c2i     <= '1';
-          loi     <= '0';
-
-        when E3 =>
-
-          if (c1 = "111") then next_state <= E4;
-                          else next_state <= E1;
-          end if;
-
-          s_read  <= '0';
-          s_write <= '0';
-          clraccu <= '0';
-          hph     <= '0';
-          vhadout <= '0';
-          vaccu   <= '0';
-          vbreg   <= '0';
-          c1i     <= '1';
-          c2i     <= '0';
-          loi     <= '0';
-
-        when E4 =>
-
-          if (c1 = "110") then next_state <= E5;
-                          else next_state <= E4;
-          end if;
-
-          s_read  <= '0';
-          s_write <= '0';
-          clraccu <= '0';
-          hph     <= '1';
-          vhadout <= '0';
-          vaccu   <= '1';
-          vbreg   <= '0';
-          c1i     <= '1';
-          c2i     <= '0';
-          loi     <= '0';
-
-        when E5 =>
-
-          if ( c2 = "111" ) then next_state <= E6;
-                            else next_state <= E4;
-          end if;
-
-          s_read    <= '0';
-          s_write   <= '0';
-          clraccu <= '1';
-          hph     <= '1';
-          vhadout <= '0';
-          vaccu   <= '0';
-          vbreg   <= '1';
-          c1i     <= '1';
-          c2i     <= '1';
-          loi     <= '0';
-
-        when E6 =>
-
-          if (c2 = "111") then next_state <= E7;
-                          else next_state <= E6;
-          end if;
-
-          s_read  <= '0';
-          s_write <= '0';
-          clraccu <= '0';
-          hph     <= '0';
-          vhadout <= '0';
-          vaccu   <= '1';
-          vbreg   <= '0';
-          c1i     <= '0';
-          c2i     <= '1';
-          loi     <= '0';
-
-        when E7 =>
-
-          next_state <= E8;
-
-          s_read  <= '0';
-          s_write <= '0';
-          clraccu <= '0';
-          hph     <= '0';
-          vhadout <= '1';
-          vaccu   <= '0';
-          vbreg   <= '0';
-          c1i     <= '0';
-          c2i     <= '0';
-          loi     <= '0';
-
-        when E8 =>
-
-          if (full = '1') then next_state <= E8;
-                          else next_state <= E9;
-          end if;
-
-          s_read  <= '0';
-          s_write <= '1';
-          clraccu <= '1';
-          hph     <= '0';
-          vhadout <= '0';
-          vaccu   <= '0';
-          vbreg   <= '0';
-          c1i     <= '0';
-          c2i     <= '0';
-          loi     <= '0';
-
-        when E9 =>
-
-          if (c1 = "111") then next_state <= E10;
-          else                 next_state <= E6;
-          end if;
-
-          s_read  <= '0';
-          s_write <= '0';
-          clraccu <= '1';
-          hph     <= '0';
-          vhadout <= '0';
-          vaccu   <= '0';
-          vbreg   <= '0';
-          c1i     <= '1';
-          c2i     <= '0';
-          loi     <= '0';
-
-        when E10 =>
-
-          if(lo = "111") then next_state <= E0;
-                         else next_state <= E4;
-          end if;
- 
-
-          s_read  <= '0';
-          s_write <= '0';
-          clraccu <= '1';
-          hph     <= '0';
-          vhadout <= '0';
-          vaccu   <= '0';
-          vbreg   <= '0';
-          c1i     <= '0';
-          c2i     <= '0';
-          loi     <= '1';
-
-      end case;
-   end if;
-end process;
-
-process(ck)
-  begin
-    if (ck='0' and ck'event) then
-      current_state <= next_state;
-    end if;
-end process;
-
-end behavioral;
-
diff --git a/alliance/share/tutorials/vasy/multi8/CATAL b/alliance/share/tutorials/vasy/multi8/CATAL
deleted file mode 100644
index a420b11d..00000000
--- a/alliance/share/tutorials/vasy/multi8/CATAL
+++ /dev/null
@@ -1,5 +0,0 @@
-addaccu		C
-multi8_model	C
-srb		C
-controller	C
-sra		C
diff --git a/alliance/share/tutorials/vasy/multi8/Makefile b/alliance/share/tutorials/vasy/multi8/Makefile
deleted file mode 100644
index d6c43c72..00000000
--- a/alliance/share/tutorials/vasy/multi8/Makefile
+++ /dev/null
@@ -1,257 +0,0 @@
-# /*------------------------------------------------------------\
-# |                                                             |
-# | This file is part of the Alliance CAD System Copyright      |
-# | (C) Laboratoire LIP6 - Département ASIM Universite P&M Curie|
-# |                                                             |
-# | Home page      : http://www-asim.lip6.fr/alliance/          |
-# | E-mail support : mailto:alliance-support@asim.lip6.fr       |
-# |                                                             |
-# | This progam is  free software; you can redistribute it      |
-# | and/or modify it under the  terms of the GNU General Public |
-# | License as  published by the Free Software Foundation;      |
-# | either version 2 of the License, or (at your option) any    |
-# | later version.                                              |
-# |                                                             |
-# | Alliance VLSI  CAD System  is distributed  in the hope that |
-# | it  will be useful, but WITHOUT  ANY WARRANTY;              |
-# | without even the  implied warranty of MERCHANTABILITY or    |
-# | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General       |
-# | Public License for more details.                            |
-# |                                                             |
-# | You should have received a copy  of the GNU General Public  |
-# | License along with the GNU C Library; see the file COPYING. |
-# | If not, write to the Free Software Foundation, Inc.,        |
-# | 675 Mass Ave, Cambridge, MA 02139, USA.                     |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# | Tool   :                      VASY                          |
-# |                                                             |
-# | File   :                    Makefile                        |
-# |                                                             |
-# | Author :                 Jacomme Ludovic                    |
-# |                                                             |
-# | Date    :                   30_05_2000                      |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-include $(ALLIANCE_TOP)/etc/$(ALLIANCE_OS).mk
-include $(ALLIANCE_TOP)/etc/libraries.mk
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                              Cells                          |
-# |                                                             |
-# \------------------------------------------------------------*/
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                             Binary                          |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-TOUCH  = touch
-VASY   = $(ALLIANCE_TOP)/bin/vasy
-ASIMUT = $(ALLIANCE_TOP)/bin/asimut
-BOP    = $(ALLIANCE_TOP)/bin/bop
-SCMAP  = $(ALLIANCE_TOP)/bin/scmap
-PROOF  = $(ALLIANCE_TOP)/bin/proof
-SCR    = $(ALLIANCE_TOP)/bin/scr
-LYNX   = $(ALLIANCE_TOP)/bin/lynx
-LVX    = $(ALLIANCE_TOP)/bin/lvx
-DRUC   = $(ALLIANCE_TOP)/bin/druc
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                            Environement                     |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-ENV_VASY = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
-           MBK_CATAL_NAME=NO_CATAL; export MBK_CATAL_NAME
-
-ENV_ASIMUT = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
-             MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME;\
-             MBK_IN_LO=vst; export MBK_IN_LO;\
-	     MBK_OUT_LO=vst; export MBK_OUT_LO
-
-ENV_SIMU_VBE = MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib; export MBK_CATA_LIB;\
-               MBK_WORK_LIB=.; export MBK_WORK_LIB;\
-               MBK_CATAL_NAME=CATAL_VBE; export MBK_CATAL_NAME;\
-               MBK_IN_LO=vst; export MBK_IN_LO;\
-	       MBK_OUT_LO=vst; export MBK_OUT_LO
-
-ENV_SIMU_VST = MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib; export MBK_CATA_LIB;\
-               MBK_WORK_LIB=.; export MBK_WORK_LIB;\
-               MBK_CATAL_NAME=NO_CATAL; export MBK_CATAL_NAME;\
-               MBK_IN_LO=vst; export MBK_IN_LO;\
-	       MBK_OUT_LO=vst; export MBK_OUT_LO
-
-ENV_SYNTH = MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib; export MBK_CATA_LIB;\
-            MBK_TARGET_LIB=$(ALLIANCE_TOP)/cells/sxlib; export MBK_TARGET_LIB;\
-            MBK_WORK_LIB=.; export MBK_WORK_LIB;\
-            MBK_CATAL_NAME=CATAL_VBE; export MBK_CATAL_NAME;\
-            MBK_IN_LO=vst; export MBK_IN_LO;\
-	    MBK_OUT_LO=vst; export MBK_OUT_LO
-
-ENV_ROUTE = MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib; export MBK_CATA_LIB;\
-            MBK_WORK_LIB=.; export MBK_WORK_LIB;\
-            MBK_CATAL_NAME=NO_CATAL; export MBK_CATAL_NAME;\
-            MBK_IN_PH=ap; export MBK_IN_PH;\
-	    MBK_OUT_PH=ap; export MBK_OUT_PH;\
-            MBK_IN_LO=vst; export MBK_IN_LO;\
-	    MBK_OUT_LO=al; export MBK_OUT_LO
-
-ENV_PHYS = MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib; export MBK_CATA_LIB;\
-           MBK_WORK_LIB=.; export MBK_WORK_LIB;\
-           MBK_CATAL_NAME=NO_CATAL; export MBK_CATAL_NAME;\
-	   RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/cmos_11.rds; \
-	   export RDS_TECHNO_NAME;\
-	   RDS_IN=cif; export RDS_IN;\
-	   RDS_OUT=cif; export RDS_OUT;\
-           MBK_IN_PH=ap; export MBK_IN_PH;\
-	   MBK_OUT_PH=ap; export MBK_OUT_PH;\
-           MBK_IN_LO=al; export MBK_IN_LO;\
-	   MBK_OUT_LO=al; export MBK_OUT_LO
-
-all : multi8_drc
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                             Vasy                            |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-multi8.vst : addaccu.vhdl controller.vhdl multi8.vhdl sra.vhdl srb.vhdl
-	$(ENV_VASY); $(VASY) -a -o -I vhdl -HLpV multi8
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                      Behavioral Simulation                  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-result_beh_pat : multi8.vst
-	$(ENV_ASIMUT); $(ASIMUT) multi8 multi8 result_beh
-	$(TOUCH) result_beh_pat
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                         Boolean Optimization                |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-srao_vbe : result_beh_pat
-	$(ENV_SYNTH); $(BOP) -o sra srao
-	$(ENV_SYNTH); $(PROOF) sra srao
-	$(TOUCH) srao_vbe
-
-srbo_vbe : result_beh_pat
-	$(ENV_SYNTH); $(BOP) -o srb srbo
-	$(ENV_SYNTH); $(PROOF) srb srbo
-	$(TOUCH) srbo_vbe
-
-addaccuo_vbe : result_beh_pat
-	$(ENV_SYNTH); $(BOP) -o addaccu addaccuo addaccu
-	$(ENV_SYNTH); $(PROOF) addaccu addaccuo
-	$(TOUCH) addaccuo_vbe
-
-controllero_vbe : result_beh_pat
-	$(ENV_SYNTH); $(BOP) -o controller controllero
-	$(ENV_SYNTH); $(PROOF) controller controllero
-	$(TOUCH) controllero_vbe
-
-multi8_modelo_vbe : result_beh_pat
-	$(ENV_SYNTH); $(BOP) -o multi8_model multi8_modelo
-	$(ENV_SYNTH); $(PROOF) multi8_model multi8_modelo
-	$(TOUCH) multi8_modelo_vbe
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                           Mapping                           |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-sra.vst : srao_vbe
-	$(ENV_SYNTH); $(SCMAP) srao sra
-
-srb.vst : srbo_vbe
-	$(ENV_SYNTH); $(SCMAP) srbo srb
-
-addaccu.vst : addaccuo_vbe
-# $(ENV_SYNTH); $(SCMAP) addaccuo addaccu
-	echo Bug with SCMAP just make a copy 
-	cp addaccu.vst.patched addaccu.vst
-	$(TOUCH) addaccu.vst
-
-controller.vst : controllero_vbe
-	$(ENV_SYNTH); $(SCMAP) controllero controller
-
-multi8_model.vst : multi8_modelo_vbe
-	$(ENV_SYNTH); $(SCMAP) multi8_modelo multi8_model
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                      Structural Simulation                  |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-result_vst_pat : addaccu.vst controller.vst multi8.vst multi8_model.vst \
-                 sra.vst srb.vst
-	$(ENV_SIMU_VST); $(ASIMUT) -zd multi8 multi8 result_vst 
-	$(TOUCH) result_vst_pat
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                        Place And Route                      |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-multi8.ap : result_vst_pat
-	$(ENV_ROUTE); $(SCR) -p -r -i 1000 multi8 multi8
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                           Extract                           |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-multi8.al : multi8.ap
-	$(ENV_PHYS); $(LYNX) -v multi8 multi8
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                           NetList Comparison                |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-multi8_lvx : multi8.al
-	$(ENV_PHYS); $(LVX) vst al multi8 multi8 -f
-	$(TOUCH) multi8_lvx
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                           Design Rules Check                |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-multi8_drc : multi8_lvx
-	$(ENV_PHYS); $(DRUC) multi8
-	$(TOUCH) multi8_drc
-
-
-
-# /*------------------------------------------------------------\
-# |                                                             |
-# |                              Clean                          |
-# |                                                             |
-# \------------------------------------------------------------*/
-
-realclean : clean
-
-clean     :
-	$(RM) -f *vst *vbe result_vst.pat  result_beh.pat
-	$(RM) -f result_vst_pat  result_beh_pat multi8_drc multi8_lvx
-	$(RM) -f *.al *.ap *.lax *.drc *.cif
-	
diff --git a/alliance/share/tutorials/vasy/multi8/addaccu.stat b/alliance/share/tutorials/vasy/multi8/addaccu.stat
deleted file mode 100644
index e69de29b..00000000
diff --git a/alliance/share/tutorials/vasy/multi8/addaccu.vhdl b/alliance/share/tutorials/vasy/multi8/addaccu.vhdl
deleted file mode 100644
index 0348abc9..00000000
--- a/alliance/share/tutorials/vasy/multi8/addaccu.vhdl
+++ /dev/null
@@ -1,34 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_arith.ALL;
-use IEEE.STD_LOGIC_unsigned.ALL;
-
-
-entity AddAccu is
-
-    port ( CLR : in Std_Logic;
-           LD : in Std_Logic;
-           OUTS : in Std_Logic_Vector(15 downto 0) ;
-           CLK : in Std_Logic;
-
-           RESULT : out Std_Logic_Vector(15 downto 0) );
-
-end AddAccu;
-
-
-----------------------------------------------------------------------
-
-architecture DataFlow OF AddAccu is
-signal resultint : Std_Logic_Vector(15 downto 0) ;
-begin
-process (CLK)
-begin
-   if CLK'event and CLK='0' then
-      if CLR = '1' then resultint  <= ( others => '0' );
-      elsif LD = '1' then resultint <= resultint + OUTS;
-      end if;
- end if;
-end process;
-RESULT <= resultint;
-end DataFlow;
-----------------------------------------------------------------------
diff --git a/alliance/share/tutorials/vasy/multi8/addaccu.vst.patched b/alliance/share/tutorials/vasy/multi8/addaccu.vst.patched
deleted file mode 100644
index f70c0014..00000000
--- a/alliance/share/tutorials/vasy/multi8/addaccu.vst.patched
+++ /dev/null
@@ -1,1932 +0,0 @@
--- VHDL structural description generated from `addaccu`
---		date : Tue May 30 19:36:46 2000
-
-
--- Entity Declaration
-
-ENTITY addaccu IS
-  PORT (
-  clr : in BIT;	-- clr
-  ld : in BIT;	-- ld
-  outs : in BIT_VECTOR (15 DOWNTO 0);	-- outs
-  clk : in BIT;	-- clk
-  result : inout BIT_VECTOR (15 DOWNTO 0);	-- result
-  vdd : in BIT;	-- vdd
-  vss : in BIT	-- vss
-  );
-END addaccu;
-
--- Architecture Declaration
-
-ARCHITECTURE VST OF addaccu IS
-  COMPONENT nao22_x1
-    port (
-    i0 : in BIT;	-- i0
-    i1 : in BIT;	-- i1
-    i2 : in BIT;	-- i2
-    nq : out BIT;	-- nq
-    vdd : in BIT;	-- vdd
-    vss : in BIT	-- vss
-    );
-  END COMPONENT;
-
-  COMPONENT o4_x2
-    port (
-    i0 : in BIT;	-- i0
-    i1 : in BIT;	-- i1
-    i2 : in BIT;	-- i2
-    i3 : in BIT;	-- i3
-    q : out BIT;	-- q
-    vdd : in BIT;	-- vdd
-    vss : in BIT	-- vss
-    );
-  END COMPONENT;
-
-  COMPONENT ao2o22_x2
-    port (
-    i0 : in BIT;	-- i0
-    i1 : in BIT;	-- i1
-    i2 : in BIT;	-- i2
-    i3 : in BIT;	-- i3
-    q : out BIT;	-- q
-    vdd : in BIT;	-- vdd
-    vss : in BIT	-- vss
-    );
-  END COMPONENT;
-
-  COMPONENT a3_x2
-    port (
-    i0 : in BIT;	-- i0
-    i1 : in BIT;	-- i1
-    i2 : in BIT;	-- i2
-    q : out BIT;	-- q
-    vdd : in BIT;	-- vdd
-    vss : in BIT	-- vss
-    );
-  END COMPONENT;
-
-  COMPONENT o3_x2
-    port (
-    i0 : in BIT;	-- i0
-    i1 : in BIT;	-- i1
-    i2 : in BIT;	-- i2
-    q : out BIT;	-- q
-    vdd : in BIT;	-- vdd
-    vss : in BIT	-- vss
-    );
-  END COMPONENT;
-
-  COMPONENT noa22_x1
-    port (
-    i0 : in BIT;	-- i0
-    i1 : in BIT;	-- i1
-    i2 : in BIT;	-- i2
-    nq : out BIT;	-- nq
-    vdd : in BIT;	-- vdd
-    vss : in BIT	-- vss
-    );
-  END COMPONENT;
-
-  COMPONENT na2_x1
-    port (
-    i0 : in BIT;	-- i0
-    i1 : in BIT;	-- i1
-    nq : out BIT;	-- nq
-    vdd : in BIT;	-- vdd
-    vss : in BIT	-- vss
-    );
-  END COMPONENT;
-
-  COMPONENT xr2_x1
-    port (
-    i0 : in BIT;	-- i0
-    i1 : in BIT;	-- i1
-    q : out BIT;	-- q
-    vdd : in BIT;	-- vdd
-    vss : in BIT	-- vss
-    );
-  END COMPONENT;
-
-  COMPONENT no2_x1
-    port (
-    i0 : in BIT;	-- i0
-    i1 : in BIT;	-- i1
-    nq : out BIT;	-- nq
-    vdd : in BIT;	-- vdd
-    vss : in BIT	-- vss
-    );
-  END COMPONENT;
-
-  COMPONENT nxr2_x1
-    port (
-    i0 : in BIT;	-- i0
-    i1 : in BIT;	-- i1
-    nq : out BIT;	-- nq
-    vdd : in BIT;	-- vdd
-    vss : in BIT	-- vss
-    );
-  END COMPONENT;
-
-  COMPONENT ao22_x2
-    port (
-    i0 : in BIT;	-- i0
-    i1 : in BIT;	-- i1
-    i2 : in BIT;	-- i2
-    q : out BIT;	-- q
-    vdd : in BIT;	-- vdd
-    vss : in BIT	-- vss
-    );
-  END COMPONENT;
-
-  COMPONENT oa2a22_x2
-    port (
-    i0 : in BIT;	-- i0
-    i1 : in BIT;	-- i1
-    i2 : in BIT;	-- i2
-    i3 : in BIT;	-- i3
-    q : out BIT;	-- q
-    vdd : in BIT;	-- vdd
-    vss : in BIT	-- vss
-    );
-  END COMPONENT;
-
-  COMPONENT on12_x1
-    port (
-    i0 : in BIT;	-- i0
-    i1 : in BIT;	-- i1
-    q : out BIT;	-- q
-    vdd : in BIT;	-- vdd
-    vss : in BIT	-- vss
-    );
-  END COMPONENT;
-
-  COMPONENT an12_x1
-    port (
-    i0 : in BIT;	-- i0
-    i1 : in BIT;	-- i1
-    q : out BIT;	-- q
-    vdd : in BIT;	-- vdd
-    vss : in BIT	-- vss
-    );
-  END COMPONENT;
-
-  COMPONENT buf_x2
-    port (
-  i	 : in  BIT;
-  q	 : out BIT;
-  vdd	 : in  BIT;
-  vss	 : in  BIT
-    );
-  END COMPONENT;
-
-  COMPONENT inv_x1
-    port (
-    i : in BIT;	-- i
-    nq : out BIT;	-- nq
-    vdd : in BIT;	-- vdd
-    vss : in BIT	-- vss
-    );
-  END COMPONENT;
-
-  COMPONENT o2_x2
-    port (
-    i0 : in BIT;	-- i0
-    i1 : in BIT;	-- i1
-    q : out BIT;	-- q
-    vdd : in BIT;	-- vdd
-    vss : in BIT	-- vss
-    );
-  END COMPONENT;
-
-  COMPONENT a2_x2
-    port (
-    i0 : in BIT;	-- i0
-    i1 : in BIT;	-- i1
-    q : out BIT;	-- q
-    vdd : in BIT;	-- vdd
-    vss : in BIT	-- vss
-    );
-  END COMPONENT;
-
-  COMPONENT oa22_x2
-    port (
-    i0 : in BIT;	-- i0
-    i1 : in BIT;	-- i1
-    i2 : in BIT;	-- i2
-    q : out BIT;	-- q
-    vdd : in BIT;	-- vdd
-    vss : in BIT	-- vss
-    );
-  END COMPONENT;
-
-  COMPONENT sff1_x4
-    port (
-    ck : in BIT;	-- ck
-    i : in BIT;	-- i
-    q : out BIT;	-- q
-    vdd : in BIT;	-- vdd
-    vss : in BIT	-- vss
-    );
-  END COMPONENT;
-
-  SIGNAL int_result : BIT_VECTOR(15 downto 0);
-  SIGNAL rtlcarry_0_14 : BIT;	-- rtlcarry_0_14
-  SIGNAL rtlcarry_0_13 : BIT;	-- rtlcarry_0_13
-  SIGNAL rtlcarry_0_12 : BIT;	-- rtlcarry_0_12
-  SIGNAL rtlcarry_0_11 : BIT;	-- rtlcarry_0_11
-  SIGNAL rtlcarry_0_10 : BIT;	-- rtlcarry_0_10
-  SIGNAL rtlcarry_0_9 : BIT;	-- rtlcarry_0_9
-  SIGNAL rtlcarry_0_8 : BIT;	-- rtlcarry_0_8
-  SIGNAL rtlcarry_0_7 : BIT;	-- rtlcarry_0_7
-  SIGNAL rtlcarry_0_6 : BIT;	-- rtlcarry_0_6
-  SIGNAL rtlcarry_0_5 : BIT;	-- rtlcarry_0_5
-  SIGNAL rtlcarry_0_4 : BIT;	-- rtlcarry_0_4
-  SIGNAL rtlcarry_0_3 : BIT;	-- rtlcarry_0_3
-  SIGNAL rtlcarry_0_2 : BIT;	-- rtlcarry_0_2
-  SIGNAL auxsc27 : BIT;	-- auxsc27
-  SIGNAL auxsc24 : BIT;	-- auxsc24
-  SIGNAL auxsc16 : BIT;	-- auxsc16
-  SIGNAL auxsc28 : BIT;	-- auxsc28
-  SIGNAL auxsc34 : BIT;	-- auxsc34
-  SIGNAL auxsc35 : BIT;	-- auxsc35
-  SIGNAL auxsc36 : BIT;	-- auxsc36
-  SIGNAL auxsc45 : BIT;	-- auxsc45
-  SIGNAL auxsc46 : BIT;	-- auxsc46
-  SIGNAL auxsc52 : BIT;	-- auxsc52
-  SIGNAL auxsc53 : BIT;	-- auxsc53
-  SIGNAL auxsc54 : BIT;	-- auxsc54
-  SIGNAL auxsc55 : BIT;	-- auxsc55
-  SIGNAL auxsc64 : BIT;	-- auxsc64
-  SIGNAL auxsc65 : BIT;	-- auxsc65
-  SIGNAL auxsc71 : BIT;	-- auxsc71
-  SIGNAL auxsc72 : BIT;	-- auxsc72
-  SIGNAL auxsc73 : BIT;	-- auxsc73
-  SIGNAL auxsc74 : BIT;	-- auxsc74
-  SIGNAL auxsc83 : BIT;	-- auxsc83
-  SIGNAL auxsc84 : BIT;	-- auxsc84
-  SIGNAL auxsc90 : BIT;	-- auxsc90
-  SIGNAL auxsc91 : BIT;	-- auxsc91
-  SIGNAL auxsc92 : BIT;	-- auxsc92
-  SIGNAL auxsc93 : BIT;	-- auxsc93
-  SIGNAL auxsc102 : BIT;	-- auxsc102
-  SIGNAL auxsc103 : BIT;	-- auxsc103
-  SIGNAL auxsc109 : BIT;	-- auxsc109
-  SIGNAL auxsc110 : BIT;	-- auxsc110
-  SIGNAL auxsc111 : BIT;	-- auxsc111
-  SIGNAL auxsc112 : BIT;	-- auxsc112
-  SIGNAL auxsc121 : BIT;	-- auxsc121
-  SIGNAL auxsc122 : BIT;	-- auxsc122
-  SIGNAL auxsc128 : BIT;	-- auxsc128
-  SIGNAL auxsc129 : BIT;	-- auxsc129
-  SIGNAL auxsc130 : BIT;	-- auxsc130
-  SIGNAL auxsc131 : BIT;	-- auxsc131
-  SIGNAL auxsc140 : BIT;	-- auxsc140
-  SIGNAL auxsc141 : BIT;	-- auxsc141
-  SIGNAL auxsc147 : BIT;	-- auxsc147
-  SIGNAL auxsc148 : BIT;	-- auxsc148
-  SIGNAL auxsc149 : BIT;	-- auxsc149
-  SIGNAL auxsc150 : BIT;	-- auxsc150
-  SIGNAL auxsc159 : BIT;	-- auxsc159
-  SIGNAL auxsc160 : BIT;	-- auxsc160
-  SIGNAL auxsc166 : BIT;	-- auxsc166
-  SIGNAL auxsc167 : BIT;	-- auxsc167
-  SIGNAL auxsc168 : BIT;	-- auxsc168
-  SIGNAL auxsc169 : BIT;	-- auxsc169
-  SIGNAL auxsc178 : BIT;	-- auxsc178
-  SIGNAL auxsc179 : BIT;	-- auxsc179
-  SIGNAL auxsc185 : BIT;	-- auxsc185
-  SIGNAL auxsc186 : BIT;	-- auxsc186
-  SIGNAL auxsc187 : BIT;	-- auxsc187
-  SIGNAL auxsc188 : BIT;	-- auxsc188
-  SIGNAL auxsc197 : BIT;	-- auxsc197
-  SIGNAL auxsc198 : BIT;	-- auxsc198
-  SIGNAL auxsc204 : BIT;	-- auxsc204
-  SIGNAL auxsc205 : BIT;	-- auxsc205
-  SIGNAL auxsc206 : BIT;	-- auxsc206
-  SIGNAL auxsc207 : BIT;	-- auxsc207
-  SIGNAL auxsc216 : BIT;	-- auxsc216
-  SIGNAL auxsc217 : BIT;	-- auxsc217
-  SIGNAL auxsc223 : BIT;	-- auxsc223
-  SIGNAL auxsc224 : BIT;	-- auxsc224
-  SIGNAL auxsc225 : BIT;	-- auxsc225
-  SIGNAL auxsc226 : BIT;	-- auxsc226
-  SIGNAL auxsc235 : BIT;	-- auxsc235
-  SIGNAL auxsc236 : BIT;	-- auxsc236
-  SIGNAL auxsc242 : BIT;	-- auxsc242
-  SIGNAL auxsc243 : BIT;	-- auxsc243
-  SIGNAL auxsc244 : BIT;	-- auxsc244
-  SIGNAL auxsc245 : BIT;	-- auxsc245
-  SIGNAL auxsc254 : BIT;	-- auxsc254
-  SIGNAL auxsc255 : BIT;	-- auxsc255
-  SIGNAL auxsc5 : BIT;	-- auxsc5
-  SIGNAL auxsc2 : BIT;	-- auxsc2
-  SIGNAL auxsc6 : BIT;	-- auxsc6
-  SIGNAL auxsc7 : BIT;	-- auxsc7
-  SIGNAL auxsc18 : BIT;	-- auxsc18
-  SIGNAL auxsc14 : BIT;	-- auxsc14
-  SIGNAL auxsc15 : BIT;	-- auxsc15
-  SIGNAL auxsc19 : BIT;	-- auxsc19
-  SIGNAL auxsc20 : BIT;	-- auxsc20
-  SIGNAL auxsc21 : BIT;	-- auxsc21
-  SIGNAL auxsc22 : BIT;	-- auxsc22
-  SIGNAL auxsc38 : BIT;	-- auxsc38
-  SIGNAL auxsc39 : BIT;	-- auxsc39
-  SIGNAL auxsc40 : BIT;	-- auxsc40
-  SIGNAL auxsc41 : BIT;	-- auxsc41
-  SIGNAL auxsc57 : BIT;	-- auxsc57
-  SIGNAL auxsc58 : BIT;	-- auxsc58
-  SIGNAL auxsc59 : BIT;	-- auxsc59
-  SIGNAL auxsc60 : BIT;	-- auxsc60
-  SIGNAL auxsc76 : BIT;	-- auxsc76
-  SIGNAL auxsc77 : BIT;	-- auxsc77
-  SIGNAL auxsc78 : BIT;	-- auxsc78
-  SIGNAL auxsc79 : BIT;	-- auxsc79
-  SIGNAL auxsc95 : BIT;	-- auxsc95
-  SIGNAL auxsc96 : BIT;	-- auxsc96
-  SIGNAL auxsc97 : BIT;	-- auxsc97
-  SIGNAL auxsc98 : BIT;	-- auxsc98
-  SIGNAL auxsc114 : BIT;	-- auxsc114
-  SIGNAL auxsc115 : BIT;	-- auxsc115
-  SIGNAL auxsc116 : BIT;	-- auxsc116
-  SIGNAL auxsc117 : BIT;	-- auxsc117
-  SIGNAL auxsc133 : BIT;	-- auxsc133
-  SIGNAL auxsc134 : BIT;	-- auxsc134
-  SIGNAL auxsc135 : BIT;	-- auxsc135
-  SIGNAL auxsc136 : BIT;	-- auxsc136
-  SIGNAL auxsc152 : BIT;	-- auxsc152
-  SIGNAL auxsc153 : BIT;	-- auxsc153
-  SIGNAL auxsc154 : BIT;	-- auxsc154
-  SIGNAL auxsc155 : BIT;	-- auxsc155
-  SIGNAL auxsc171 : BIT;	-- auxsc171
-  SIGNAL auxsc172 : BIT;	-- auxsc172
-  SIGNAL auxsc173 : BIT;	-- auxsc173
-  SIGNAL auxsc174 : BIT;	-- auxsc174
-  SIGNAL auxsc190 : BIT;	-- auxsc190
-  SIGNAL auxsc191 : BIT;	-- auxsc191
-  SIGNAL auxsc192 : BIT;	-- auxsc192
-  SIGNAL auxsc193 : BIT;	-- auxsc193
-  SIGNAL auxsc209 : BIT;	-- auxsc209
-  SIGNAL auxsc210 : BIT;	-- auxsc210
-  SIGNAL auxsc211 : BIT;	-- auxsc211
-  SIGNAL auxsc212 : BIT;	-- auxsc212
-  SIGNAL auxsc228 : BIT;	-- auxsc228
-  SIGNAL auxsc229 : BIT;	-- auxsc229
-  SIGNAL auxsc230 : BIT;	-- auxsc230
-  SIGNAL auxsc231 : BIT;	-- auxsc231
-  SIGNAL auxsc247 : BIT;	-- auxsc247
-  SIGNAL auxsc248 : BIT;	-- auxsc248
-  SIGNAL auxsc249 : BIT;	-- auxsc249
-  SIGNAL auxsc250 : BIT;	-- auxsc250
-  SIGNAL auxsc292 : BIT;	-- auxsc292
-  SIGNAL auxsc273 : BIT;	-- auxsc273
-  SIGNAL auxsc287 : BIT;	-- auxsc287
-  SIGNAL auxsc270 : BIT;	-- auxsc270
-  SIGNAL auxsc283 : BIT;	-- auxsc283
-  SIGNAL auxsc288 : BIT;	-- auxsc288
-  SIGNAL auxsc279 : BIT;	-- auxsc279
-  SIGNAL auxsc278 : BIT;	-- auxsc278
-  SIGNAL auxsc281 : BIT;	-- auxsc281
-  SIGNAL auxsc289 : BIT;	-- auxsc289
-  SIGNAL auxsc291 : BIT;	-- auxsc291
-  SIGNAL auxsc293 : BIT;	-- auxsc293
-  SIGNAL auxsc294 : BIT;	-- auxsc294
-  SIGNAL auxsc285 : BIT;	-- auxsc285
-  SIGNAL auxsc286 : BIT;	-- auxsc286
-  SIGNAL auxsc295 : BIT;	-- auxsc295
-  SIGNAL auxsc297 : BIT;	-- auxsc297
-  SIGNAL auxsc298 : BIT;	-- auxsc298
-  SIGNAL auxsc339 : BIT;	-- auxsc339
-  SIGNAL auxsc318 : BIT;	-- auxsc318
-  SIGNAL auxsc302 : BIT;	-- auxsc302
-  SIGNAL auxsc303 : BIT;	-- auxsc303
-  SIGNAL auxsc331 : BIT;	-- auxsc331
-  SIGNAL auxsc335 : BIT;	-- auxsc335
-  SIGNAL auxsc327 : BIT;	-- auxsc327
-  SIGNAL auxsc326 : BIT;	-- auxsc326
-  SIGNAL auxsc329 : BIT;	-- auxsc329
-  SIGNAL auxsc336 : BIT;	-- auxsc336
-  SIGNAL auxsc338 : BIT;	-- auxsc338
-  SIGNAL auxsc340 : BIT;	-- auxsc340
-  SIGNAL auxsc341 : BIT;	-- auxsc341
-  SIGNAL auxsc333 : BIT;	-- auxsc333
-  SIGNAL auxsc334 : BIT;	-- auxsc334
-  SIGNAL auxsc342 : BIT;	-- auxsc342
-  SIGNAL auxsc344 : BIT;	-- auxsc344
-  SIGNAL auxsc345 : BIT;	-- auxsc345
-
-BEGIN
-
-  auxsc345 : nao22_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc345,
-    i2 => auxsc344,
-    i1 => auxsc338,
-    i0 => auxsc339);
-  auxsc344 : o4_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc344,
-    i3 => auxsc342,
-    i2 => auxsc341,
-    i1 => auxsc340,
-    i0 => auxsc18);
-  auxsc342 : no2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc342,
-    i1 => auxsc334,
-    i0 => auxsc333);
-  auxsc334 : o2_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc334,
-    i1 => auxsc327,
-    i0 => auxsc326);
-  auxsc333 : no2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc333,
-    i1 => auxsc318,
-    i0 => clr);
-  auxsc341 : ao2o22_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc341,
-    i3 => auxsc326,
-    i2 => auxsc327,
-    i1 => clr,
-    i0 => outs(15));
-  auxsc340 : inv_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc340,
-    i => auxsc339);
-  auxsc338 : a3_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc338,
-    i2 => auxsc336,
-    i1 => auxsc335,
-    i0 => auxsc287);
-  auxsc336 : o3_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc336,
-    i2 => auxsc329,
-    i1 => clr,
-    i0 => outs(15));
-  auxsc329 : o2_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc329,
-    i1 => auxsc326,
-    i0 => auxsc327);
-  auxsc326 : ao22_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc326,
-    i2 => rtlcarry_0_14,
-    i1 => int_result(14),
-    i0 => outs(14));
-  auxsc327 : a2_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc327,
-    i1 => int_result(14),
-    i0 => outs(14));
-  auxsc335 : o3_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc335,
-    i2 => auxsc331,
-    i1 => auxsc318,
-    i0 => clr);
-  auxsc331 : noa22_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc331,
-    i2 => auxsc303,
-    i1 => auxsc302,
-    i0 => auxsc286);
-  auxsc303 : an12_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc303,
-    i1 => int_result(14),
-    i0 => auxsc270);
-  auxsc302 : on12_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc302,
-    i1 => int_result(14),
-    i0 => auxsc270);
-  auxsc318 : inv_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc318,
-    i => outs(15));
-  auxsc339 : inv_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc339,
-    i => int_result(15));
-  auxsc298 : nao22_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc298,
-    i2 => auxsc297,
-    i1 => auxsc291,
-    i0 => auxsc292);
-  auxsc297 : o4_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc297,
-    i3 => auxsc295,
-    i2 => auxsc294,
-    i1 => auxsc293,
-    i0 => auxsc18);
-  auxsc295 : no2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc295,
-    i1 => auxsc286,
-    i0 => auxsc285);
-  auxsc286 : o2_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc286,
-    i1 => auxsc279,
-    i0 => auxsc278);
-  auxsc285 : no2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc285,
-    i1 => auxsc270,
-    i0 => clr);
-  auxsc294 : ao2o22_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc294,
-    i3 => auxsc278,
-    i2 => auxsc279,
-    i1 => clr,
-    i0 => outs(14));
-  auxsc293 : inv_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc293,
-    i => auxsc292);
-  auxsc291 : a3_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc291,
-    i2 => auxsc289,
-    i1 => auxsc288,
-    i0 => auxsc287);
-  auxsc289 : o3_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc289,
-    i2 => auxsc281,
-    i1 => clr,
-    i0 => outs(14));
-  auxsc281 : o2_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc281,
-    i1 => auxsc278,
-    i0 => auxsc279);
-  auxsc278 : ao22_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc278,
-    i2 => rtlcarry_0_13,
-    i1 => int_result(13),
-    i0 => outs(13));
-  auxsc279 : a2_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc279,
-    i1 => int_result(13),
-    i0 => outs(13));
-  auxsc288 : o3_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc288,
-    i2 => auxsc283,
-    i1 => auxsc270,
-    i0 => clr);
-  auxsc283 : noa22_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc283,
-    i2 => auxsc255,
-    i1 => auxsc254,
-    i0 => auxsc244);
-  auxsc270 : inv_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc270,
-    i => outs(14));
-  auxsc287 : na2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc287,
-    i1 => auxsc273,
-    i0 => auxsc18);
-  auxsc273 : inv_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc273,
-    i => clr);
-  auxsc292 : inv_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc292,
-    i => int_result(14));
-  auxsc250 : no2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc250,
-    i1 => auxsc249,
-    i0 => clr);
-  auxsc249 : nxr2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc249,
-    i1 => auxsc248,
-    i0 => int_result(13));
-  auxsc248 : no2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc248,
-    i1 => auxsc247,
-    i0 => auxsc18);
-  auxsc247 : xr2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc247,
-    i1 => auxsc244,
-    i0 => auxsc245);
-  auxsc231 : no2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc231,
-    i1 => auxsc230,
-    i0 => clr);
-  auxsc230 : nxr2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc230,
-    i1 => auxsc229,
-    i0 => int_result(12));
-  auxsc229 : no2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc229,
-    i1 => auxsc228,
-    i0 => auxsc18);
-  auxsc228 : xr2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc228,
-    i1 => auxsc225,
-    i0 => auxsc226);
-  auxsc212 : no2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc212,
-    i1 => auxsc211,
-    i0 => clr);
-  auxsc211 : nxr2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc211,
-    i1 => auxsc210,
-    i0 => int_result(11));
-  auxsc210 : no2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc210,
-    i1 => auxsc209,
-    i0 => auxsc18);
-  auxsc209 : xr2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc209,
-    i1 => auxsc206,
-    i0 => auxsc207);
-  auxsc193 : no2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc193,
-    i1 => auxsc192,
-    i0 => clr);
-  auxsc192 : nxr2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc192,
-    i1 => auxsc191,
-    i0 => int_result(10));
-  auxsc191 : no2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc191,
-    i1 => auxsc190,
-    i0 => auxsc18);
-  auxsc190 : xr2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc190,
-    i1 => auxsc187,
-    i0 => auxsc188);
-  auxsc174 : no2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc174,
-    i1 => auxsc173,
-    i0 => clr);
-  auxsc173 : nxr2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc173,
-    i1 => auxsc172,
-    i0 => int_result(9));
-  auxsc172 : no2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc172,
-    i1 => auxsc171,
-    i0 => auxsc18);
-  auxsc171 : xr2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc171,
-    i1 => auxsc168,
-    i0 => auxsc169);
-  auxsc155 : no2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc155,
-    i1 => auxsc154,
-    i0 => clr);
-  auxsc154 : nxr2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc154,
-    i1 => auxsc153,
-    i0 => int_result(8));
-  auxsc153 : no2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc153,
-    i1 => auxsc152,
-    i0 => auxsc18);
-  auxsc152 : xr2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc152,
-    i1 => auxsc149,
-    i0 => auxsc150);
-  auxsc136 : no2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc136,
-    i1 => auxsc135,
-    i0 => clr);
-  auxsc135 : nxr2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc135,
-    i1 => auxsc134,
-    i0 => int_result(7));
-  auxsc134 : no2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc134,
-    i1 => auxsc133,
-    i0 => auxsc18);
-  auxsc133 : xr2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc133,
-    i1 => auxsc130,
-    i0 => auxsc131);
-  auxsc117 : no2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc117,
-    i1 => auxsc116,
-    i0 => clr);
-  auxsc116 : nxr2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc116,
-    i1 => auxsc115,
-    i0 => int_result(6));
-  auxsc115 : no2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc115,
-    i1 => auxsc114,
-    i0 => auxsc18);
-  auxsc114 : xr2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc114,
-    i1 => auxsc111,
-    i0 => auxsc112);
-  auxsc98 : no2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc98,
-    i1 => auxsc97,
-    i0 => clr);
-  auxsc97 : nxr2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc97,
-    i1 => auxsc96,
-    i0 => int_result(5));
-  auxsc96 : no2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc96,
-    i1 => auxsc95,
-    i0 => auxsc18);
-  auxsc95 : xr2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc95,
-    i1 => auxsc92,
-    i0 => auxsc93);
-  auxsc79 : no2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc79,
-    i1 => auxsc78,
-    i0 => clr);
-  auxsc78 : nxr2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc78,
-    i1 => auxsc77,
-    i0 => int_result(4));
-  auxsc77 : no2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc77,
-    i1 => auxsc76,
-    i0 => auxsc18);
-  auxsc76 : xr2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc76,
-    i1 => auxsc73,
-    i0 => auxsc74);
-  auxsc60 : no2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc60,
-    i1 => auxsc59,
-    i0 => clr);
-  auxsc59 : nxr2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc59,
-    i1 => auxsc58,
-    i0 => int_result(3));
-  auxsc58 : no2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc58,
-    i1 => auxsc57,
-    i0 => auxsc18);
-  auxsc57 : xr2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc57,
-    i1 => auxsc54,
-    i0 => auxsc55);
-  auxsc41 : no2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc41,
-    i1 => auxsc40,
-    i0 => clr);
-  auxsc40 : nxr2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc40,
-    i1 => auxsc39,
-    i0 => int_result(2));
-  auxsc39 : no2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc39,
-    i1 => auxsc38,
-    i0 => auxsc18);
-  auxsc38 : xr2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc38,
-    i1 => auxsc35,
-    i0 => auxsc36);
-  auxsc22 : no2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc22,
-    i1 => auxsc21,
-    i0 => clr);
-  auxsc21 : nxr2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc21,
-    i1 => auxsc20,
-    i0 => int_result(1));
-  auxsc20 : no2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc20,
-    i1 => auxsc19,
-    i0 => auxsc18);
-  auxsc19 : xr2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc19,
-    i1 => auxsc15,
-    i0 => auxsc16);
-  auxsc15 : an12_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc15,
-    i1 => int_result(0),
-    i0 => auxsc14);
-  auxsc14 : inv_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc14,
-    i => outs(0));
-  auxsc18 : inv_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc18,
-    i => ld);
-  auxsc7 : no2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc7,
-    i1 => auxsc6,
-    i0 => clr);
-  auxsc6 : nxr2_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc6,
-    i1 => auxsc2,
-    i0 => int_result(0));
-  auxsc2 : a2_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc2,
-    i1 => ld,
-    i0 => outs(0));
-  auxsc5 : inv_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc5,
-    i => clk);
-  auxsc255 : an12_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc255,
-    i1 => int_result(13),
-    i0 => auxsc245);
-  auxsc254 : on12_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc254,
-    i1 => int_result(13),
-    i0 => auxsc245);
-  auxsc245 : inv_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc245,
-    i => outs(13));
-  auxsc244 : o2_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc244,
-    i1 => auxsc243,
-    i0 => auxsc242);
-  auxsc243 : a2_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc243,
-    i1 => int_result(12),
-    i0 => outs(12));
-  auxsc242 : ao22_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc242,
-    i2 => rtlcarry_0_12,
-    i1 => int_result(12),
-    i0 => outs(12));
-  auxsc236 : an12_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc236,
-    i1 => int_result(12),
-    i0 => auxsc226);
-  auxsc235 : on12_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc235,
-    i1 => int_result(12),
-    i0 => auxsc226);
-  auxsc226 : inv_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc226,
-    i => outs(12));
-  auxsc225 : o2_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc225,
-    i1 => auxsc224,
-    i0 => auxsc223);
-  auxsc224 : a2_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc224,
-    i1 => int_result(11),
-    i0 => outs(11));
-  auxsc223 : ao22_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc223,
-    i2 => rtlcarry_0_11,
-    i1 => int_result(11),
-    i0 => outs(11));
-  auxsc217 : an12_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc217,
-    i1 => int_result(11),
-    i0 => auxsc207);
-  auxsc216 : on12_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc216,
-    i1 => int_result(11),
-    i0 => auxsc207);
-  auxsc207 : inv_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc207,
-    i => outs(11));
-  auxsc206 : o2_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc206,
-    i1 => auxsc205,
-    i0 => auxsc204);
-  auxsc205 : a2_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc205,
-    i1 => int_result(10),
-    i0 => outs(10));
-  auxsc204 : ao22_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc204,
-    i2 => rtlcarry_0_10,
-    i1 => int_result(10),
-    i0 => outs(10));
-  auxsc198 : an12_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc198,
-    i1 => int_result(10),
-    i0 => auxsc188);
-  auxsc197 : on12_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc197,
-    i1 => int_result(10),
-    i0 => auxsc188);
-  auxsc188 : inv_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc188,
-    i => outs(10));
-  auxsc187 : o2_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc187,
-    i1 => auxsc186,
-    i0 => auxsc185);
-  auxsc186 : a2_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc186,
-    i1 => int_result(9),
-    i0 => outs(9));
-  auxsc185 : ao22_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc185,
-    i2 => rtlcarry_0_9,
-    i1 => int_result(9),
-    i0 => outs(9));
-  auxsc179 : an12_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc179,
-    i1 => int_result(9),
-    i0 => auxsc169);
-  auxsc178 : on12_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc178,
-    i1 => int_result(9),
-    i0 => auxsc169);
-  auxsc169 : inv_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc169,
-    i => outs(9));
-  auxsc168 : o2_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc168,
-    i1 => auxsc167,
-    i0 => auxsc166);
-  auxsc167 : a2_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc167,
-    i1 => int_result(8),
-    i0 => outs(8));
-  auxsc166 : ao22_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc166,
-    i2 => rtlcarry_0_8,
-    i1 => int_result(8),
-    i0 => outs(8));
-  auxsc160 : an12_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc160,
-    i1 => int_result(8),
-    i0 => auxsc150);
-  auxsc159 : on12_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc159,
-    i1 => int_result(8),
-    i0 => auxsc150);
-  auxsc150 : inv_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc150,
-    i => outs(8));
-  auxsc149 : o2_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc149,
-    i1 => auxsc148,
-    i0 => auxsc147);
-  auxsc148 : a2_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc148,
-    i1 => int_result(7),
-    i0 => outs(7));
-  auxsc147 : ao22_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc147,
-    i2 => rtlcarry_0_7,
-    i1 => int_result(7),
-    i0 => outs(7));
-  auxsc141 : an12_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc141,
-    i1 => int_result(7),
-    i0 => auxsc131);
-  auxsc140 : on12_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc140,
-    i1 => int_result(7),
-    i0 => auxsc131);
-  auxsc131 : inv_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc131,
-    i => outs(7));
-  auxsc130 : o2_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc130,
-    i1 => auxsc129,
-    i0 => auxsc128);
-  auxsc129 : a2_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc129,
-    i1 => int_result(6),
-    i0 => outs(6));
-  auxsc128 : ao22_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc128,
-    i2 => rtlcarry_0_6,
-    i1 => int_result(6),
-    i0 => outs(6));
-  auxsc122 : an12_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc122,
-    i1 => int_result(6),
-    i0 => auxsc112);
-  auxsc121 : on12_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc121,
-    i1 => int_result(6),
-    i0 => auxsc112);
-  auxsc112 : inv_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc112,
-    i => outs(6));
-  auxsc111 : o2_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc111,
-    i1 => auxsc110,
-    i0 => auxsc109);
-  auxsc110 : a2_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc110,
-    i1 => int_result(5),
-    i0 => outs(5));
-  auxsc109 : ao22_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc109,
-    i2 => rtlcarry_0_5,
-    i1 => int_result(5),
-    i0 => outs(5));
-  auxsc103 : an12_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc103,
-    i1 => int_result(5),
-    i0 => auxsc93);
-  auxsc102 : on12_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc102,
-    i1 => int_result(5),
-    i0 => auxsc93);
-  auxsc93 : inv_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc93,
-    i => outs(5));
-  auxsc92 : o2_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc92,
-    i1 => auxsc91,
-    i0 => auxsc90);
-  auxsc91 : a2_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc91,
-    i1 => int_result(4),
-    i0 => outs(4));
-  auxsc90 : ao22_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc90,
-    i2 => rtlcarry_0_4,
-    i1 => int_result(4),
-    i0 => outs(4));
-  auxsc84 : an12_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc84,
-    i1 => int_result(4),
-    i0 => auxsc74);
-  auxsc83 : on12_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc83,
-    i1 => int_result(4),
-    i0 => auxsc74);
-  auxsc74 : inv_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc74,
-    i => outs(4));
-  auxsc73 : o2_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc73,
-    i1 => auxsc72,
-    i0 => auxsc71);
-  auxsc72 : a2_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc72,
-    i1 => int_result(3),
-    i0 => outs(3));
-  auxsc71 : ao22_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc71,
-    i2 => rtlcarry_0_3,
-    i1 => int_result(3),
-    i0 => outs(3));
-  auxsc65 : an12_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc65,
-    i1 => int_result(3),
-    i0 => auxsc55);
-  auxsc64 : on12_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc64,
-    i1 => int_result(3),
-    i0 => auxsc55);
-  auxsc55 : inv_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc55,
-    i => outs(3));
-  auxsc54 : o2_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc54,
-    i1 => auxsc53,
-    i0 => auxsc52);
-  auxsc53 : a2_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc53,
-    i1 => int_result(2),
-    i0 => outs(2));
-  auxsc52 : ao22_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc52,
-    i2 => rtlcarry_0_2,
-    i1 => int_result(2),
-    i0 => outs(2));
-  auxsc46 : an12_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc46,
-    i1 => int_result(2),
-    i0 => auxsc36);
-  auxsc45 : on12_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc45,
-    i1 => int_result(2),
-    i0 => auxsc36);
-  auxsc36 : inv_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc36,
-    i => outs(2));
-  auxsc35 : oa2a22_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc35,
-    i3 => auxsc34,
-    i2 => auxsc27,
-    i1 => int_result(1),
-    i0 => outs(1));
-  auxsc34 : on12_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc34,
-    i1 => int_result(1),
-    i0 => auxsc16);
-  auxsc28 : an12_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc28,
-    i1 => int_result(1),
-    i0 => auxsc16);
-  auxsc16 : inv_x1
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    nq => auxsc16,
-    i => outs(1));
-  auxsc24 : o2_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc24,
-    i1 => int_result(1),
-    i0 => outs(1));
-  auxsc27 : a2_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => auxsc27,
-    i1 => int_result(0),
-    i0 => outs(0));
-  rtlcarry_0_2 : oa22_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => rtlcarry_0_2,
-    i2 => auxsc28,
-    i1 => auxsc24,
-    i0 => auxsc27);
-  rtlcarry_0_3 : oa22_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => rtlcarry_0_3,
-    i2 => auxsc46,
-    i1 => auxsc45,
-    i0 => auxsc35);
-  rtlcarry_0_4 : oa22_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => rtlcarry_0_4,
-    i2 => auxsc65,
-    i1 => auxsc64,
-    i0 => auxsc54);
-  rtlcarry_0_5 : oa22_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => rtlcarry_0_5,
-    i2 => auxsc84,
-    i1 => auxsc83,
-    i0 => auxsc73);
-  rtlcarry_0_6 : oa22_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => rtlcarry_0_6,
-    i2 => auxsc103,
-    i1 => auxsc102,
-    i0 => auxsc92);
-  rtlcarry_0_7 : oa22_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => rtlcarry_0_7,
-    i2 => auxsc122,
-    i1 => auxsc121,
-    i0 => auxsc111);
-  rtlcarry_0_8 : oa22_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => rtlcarry_0_8,
-    i2 => auxsc141,
-    i1 => auxsc140,
-    i0 => auxsc130);
-  rtlcarry_0_9 : oa22_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => rtlcarry_0_9,
-    i2 => auxsc160,
-    i1 => auxsc159,
-    i0 => auxsc149);
-  rtlcarry_0_10 : oa22_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => rtlcarry_0_10,
-    i2 => auxsc179,
-    i1 => auxsc178,
-    i0 => auxsc168);
-  rtlcarry_0_11 : oa22_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => rtlcarry_0_11,
-    i2 => auxsc198,
-    i1 => auxsc197,
-    i0 => auxsc187);
-  rtlcarry_0_12 : oa22_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => rtlcarry_0_12,
-    i2 => auxsc217,
-    i1 => auxsc216,
-    i0 => auxsc206);
-  rtlcarry_0_13 : oa22_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => rtlcarry_0_13,
-    i2 => auxsc236,
-    i1 => auxsc235,
-    i0 => auxsc225);
-  rtlcarry_0_14 : oa22_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => rtlcarry_0_14,
-    i2 => auxsc255,
-    i1 => auxsc254,
-    i0 => auxsc244);
-  int_resultint_0 : sff1_x4
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => int_result(0),
-    i => auxsc7,
-    ck => auxsc5);
-  int_resultint_1 : sff1_x4
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => int_result(1),
-    i => auxsc22,
-    ck => auxsc5);
-  int_resultint_2 : sff1_x4
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => int_result(2),
-    i => auxsc41,
-    ck => auxsc5);
-  int_resultint_3 : sff1_x4
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => int_result(3),
-    i => auxsc60,
-    ck => auxsc5);
-  int_resultint_4 : sff1_x4
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => int_result(4),
-    i => auxsc79,
-    ck => auxsc5);
-  int_resultint_5 : sff1_x4
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => int_result(5),
-    i => auxsc98,
-    ck => auxsc5);
-  int_resultint_6 : sff1_x4
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => int_result(6),
-    i => auxsc117,
-    ck => auxsc5);
-  int_resultint_7 : sff1_x4
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => int_result(7),
-    i => auxsc136,
-    ck => auxsc5);
-  int_resultint_8 : sff1_x4
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => int_result(8),
-    i => auxsc155,
-    ck => auxsc5);
-  int_resultint_9 : sff1_x4
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => int_result(9),
-    i => auxsc174,
-    ck => auxsc5);
-  int_resultint_10 : sff1_x4
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => int_result(10),
-    i => auxsc193,
-    ck => auxsc5);
-  int_resultint_11 : sff1_x4
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => int_result(11),
-    i => auxsc212,
-    ck => auxsc5);
-  int_resultint_12 : sff1_x4
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => int_result(12),
-    i => auxsc231,
-    ck => auxsc5);
-  int_resultint_13 : sff1_x4
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => int_result(13),
-    i => auxsc250,
-    ck => auxsc5);
-  int_resultint_14 : sff1_x4
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => int_result(14),
-    i => auxsc298,
-    ck => auxsc5);
-  int_resultint_15 : sff1_x4
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => int_result(15),
-    i => auxsc345,
-    ck => auxsc5);
-  patch_0 : buf_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => result(0),
-    i => int_result(0));
-  patch_1 : buf_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => result(1),
-    i => int_result(1));
-  patch_2 : buf_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => result(2),
-    i => int_result(2));
-  patch_3 : buf_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => result(3),
-    i => int_result(3));
-  patch_4 : buf_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => result(4),
-    i => int_result(4));
-  patch_5 : buf_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => result(5),
-    i => int_result(5));
-  patch_6 : buf_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => result(6),
-    i => int_result(6));
-  patch_7 : buf_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => result(7),
-    i => int_result(7));
-  patch_8 : buf_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => result(8),
-    i => int_result(8));
-  patch_9 : buf_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => result(9),
-    i => int_result(9));
-  patch_10 : buf_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => result(10),
-    i => int_result(10));
-  patch_11 : buf_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => result(11),
-    i => int_result(11));
-  patch_12 : buf_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => result(12),
-    i => int_result(12));
-  patch_13 : buf_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => result(13),
-    i => int_result(13));
-  patch_14 : buf_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => result(14),
-    i => int_result(14));
-  patch_15 : buf_x2
-    PORT MAP (
-    vss => vss,
-    vdd => vdd,
-    q => result(15),
-    i => int_result(15));
-
-end VST;
diff --git a/alliance/share/tutorials/vasy/multi8/controller.vhdl b/alliance/share/tutorials/vasy/multi8/controller.vhdl
deleted file mode 100644
index c590fc31..00000000
--- a/alliance/share/tutorials/vasy/multi8/controller.vhdl
+++ /dev/null
@@ -1,59 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity Controller is
-  port (STB, CLK, LSB, Done, RST:	in	STD_LOGIC;
-	Init, Shift, Add:	out	STD_LOGIC);
-end Controller;
-
----------------------------------------------------
-
-architecture FSM of Controller is
-
-  type States is (EndS,InitS, CheckS, AddS, ShiftS);
-  signal State: States ;
-begin
-
-  -- Drive control outputs based upon State
-
-  Init  <= '1' when State = InitS  else '0';
-  Add   <= '1' when State = AddS   else '0';
-  Shift <= '1' when State = ShiftS else '0';
-
-  -- Determine Next State from control inputs
-
-  StateMachine:
-
-    process (CLK)
-    begin
-	--compass stateMachine adj State
-      if CLK'Event and CLK = '0' then
-	if RST = '1' then State <= EndS;
-	else
-	case State is
-	  when InitS =>
-	    State <= CheckS;
-	  when CheckS =>
-	    if LSB = '1' then
-	      State <= AddS;
-	    elsif Done = '0' then
-	      State <= ShiftS;
-	    else
-	      State <= EndS;
-	    end if;
-	  when AddS =>
-	    State <= ShiftS;
-	  when ShiftS =>
-	    State <= CheckS;
-	  when EndS =>
-	    if STB = '1' then
-	      State <= InitS;
-	    end if;
-	end case;
-	end if;
-      end if;
-    end process;
-
-end FSM;
-
----------------------------------------------------
diff --git a/alliance/share/tutorials/vasy/multi8/multi8.do b/alliance/share/tutorials/vasy/multi8/multi8.do
deleted file mode 100644
index 217356a2..00000000
--- a/alliance/share/tutorials/vasy/multi8/multi8.do
+++ /dev/null
@@ -1,16 +0,0 @@
-wave CLK
-wave RST
-wave STB
-wave DONE
-wave -dec A
-wave -dec B
-wave -dec RESULT
-
-force clk 1 50 , 0 100 -repeat 100
-force RST 1
-run
-force RST 0
-force STB 1
-force A   10#123
-force B   10#12
-run
diff --git a/alliance/share/tutorials/vasy/multi8/multi8.inc b/alliance/share/tutorials/vasy/multi8/multi8.inc
deleted file mode 100644
index 6e94ffed..00000000
--- a/alliance/share/tutorials/vasy/multi8/multi8.inc
+++ /dev/null
@@ -1,91 +0,0 @@
-trace /MULTI8/U3/STATE
-
-cd MULTI8
-trace A
-trace B
-trace CLK
-trace RST
-trace STB
-trace RESULT
-trace DONE
-
-assign ("00000111") A
-assign ("00000011") B
-assign ('1') RST
-
-assign ('0') CLK
-run 50
-assign ('1') CLK
-run 50
-assign ('0') CLK
-run 50
-
-assign ('0') RST
-assign ('1') STB
-
-run 50
-assign ('1') CLK
-run 50
-assign ('0') CLK
-run 50
-
-run 50
-assign ('1') CLK
-run 50
-assign ('0') CLK
-run 50
-
-assign ('1') CLK
-run 50
-assign ('0') CLK
-run 50
-
-assign ('1') CLK
-run 50
-assign ('0') CLK
-run 50
-
-assign ('1') CLK
-run 50
-assign ('0') CLK
-run 50
-
-assign ('1') CLK
-run 50
-assign ('0') CLK
-run 50
-
-assign ('1') CLK
-run 50
-assign ('0') CLK
-run 50
-
-assign ('1') CLK
-run 50
-assign ('0') CLK
-run 50
-
-assign ('1') CLK
-run 50
-assign ('0') CLK
-run 50
-
-assign ('1') CLK
-run 50
-assign ('0') CLK
-run 50
-
-assign ('1') CLK
-run 50
-assign ('0') CLK
-run 50
-
-assign ('1') CLK
-run 50
-assign ('0') CLK
-run 50
-
-assign ('1') CLK
-run 50
-assign ('0') CLK
-run 50
diff --git a/alliance/share/tutorials/vasy/multi8/multi8.pat b/alliance/share/tutorials/vasy/multi8/multi8.pat
deleted file mode 100644
index 4a01c110..00000000
--- a/alliance/share/tutorials/vasy/multi8/multi8.pat
+++ /dev/null
@@ -1,51 +0,0 @@
--- input / output list :
-
-in       clk B;;
-in       rst B;;
-in       stb B;;
-in       a (7 downto 0) X;;
-in       b (7 downto 0) X;;
-out      result (15 downto 0) X;;
-out      done B;
-
-begin
-
--- Pattern description :
-
---    C R S A  B   R     D 
---    L S T        E     O 
---    K T B        S     N 
---                 U     E 
---                 L       
---                 T       
-
-    : 0 1 0 00 00 ?**** ?u;
-    : 1 1 0 00 00 ?**** ?u;
-    : 0 1 0 00 00 ?**** ?u;
-    : 0 0 0 00 00 ?**** ?u;
-    : 0 0 1 00 00 ?**** ?u;
-    : 1 0 1 00 00 ?**** ?u;
-    : 0 0 1 00 00 ?**** ?u;
-    : 0 0 0 02 03 ?**** ?u;
-    : 1 0 0 02 03 ?**** ?u;
-    : 0 0 0 02 03 ?0000 ?0;
-    : 0 0 0 00 00 ?0000 ?0;
-    : 1 0 0 00 00 ?0000 ?0;
-    : 0 0 0 00 00 ?0000 ?0;
-    : 0 0 0 00 00 ?0000 ?0;
-    : 1 0 0 00 00 ?0000 ?0;
-    : 0 0 0 00 00 ?0000 ?0;
-    : 0 0 0 00 00 ?0000 ?0;
-    : 1 0 0 00 00 ?0000 ?0;
-    : 0 0 0 00 00 ?0000 ?0;
-    : 0 0 0 00 00 ?0000 ?0;
-    : 1 0 0 00 00 ?0000 ?0;
-    : 0 0 0 00 00 ?0006 ?0;
-    : 0 0 0 00 00 ?0006 ?0;
-    : 1 0 0 00 00 ?0006 ?0;
-    : 0 0 0 00 00 ?0006 ?1;
-    : 0 0 0 00 00 ?0006 ?1;
-    : 1 0 0 00 00 ?0006 ?1;
-    : 0 0 0 00 00 ?0006 ?1;
-
-end;
diff --git a/alliance/share/tutorials/vasy/multi8/multi8.vhdl b/alliance/share/tutorials/vasy/multi8/multi8.vhdl
deleted file mode 100644
index 32c4a68c..00000000
--- a/alliance/share/tutorials/vasy/multi8/multi8.vhdl
+++ /dev/null
@@ -1,121 +0,0 @@
--- Date of netlist generation:  Dec-6-95
-----------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-entity Multi8 is
-
-
-    port ( A : in Std_Logic_Vector(7 downto 0) ;
-           B : in Std_Logic_Vector(7 downto 0) ;
-           CLK : in Std_Logic ;
-           RST : in Std_Logic ;
-           STB : in Std_Logic ;
-
-           RESULT : out Std_Logic_Vector(15 downto 0) ;
-           DONE : out Std_Logic );
-
-end Multi8;
-
-----------------------------------------------------------------------
-
-architecture Structural OF Multi8 is
-
-    component Controller
-        port ( STB : in Std_Logic;
-               CLK : in Std_Logic;
-               LSB : in Std_Logic;
-               DONE : in Std_Logic;
-               RST : in Std_Logic;
-
-               INIT : out Std_Logic;
-               SHIFT : out Std_Logic;
-               ADD : out Std_Logic );
-    end component;
-
-    component Srb
-        port ( SHIFT : in Std_Logic;
-               LD : in Std_Logic;
-               CLK : in Std_Logic;
-               B : in Std_Logic_Vector(7 downto 0) ;
-
-               OUTS : out Std_Logic_Vector(15 downto 0)  );
-    end component;
-
-    component AddAccu
-        port ( CLR : in Std_Logic;
-               LD : in Std_Logic;
-               OUTS : in Std_Logic_Vector(15 downto 0) ;
-               CLK : in Std_Logic;
-
-               RESULT : out Std_Logic_Vector(15 downto 0)  );
-    end component;
-
-    component Sra
-        port ( SHIFT : in Std_Logic;
-               LD : in Std_Logic;
-               CLK : in Std_Logic;
-               RST : in Std_Logic;
-               A : in Std_Logic_Vector(7 downto 0) ;
-
-               DONE : out Std_Logic;
-               LSB : out Std_Logic );
-    end component;
-
-
-    signal DONE_local: Std_Logic;
-    signal U1_LSB : Std_Logic;
-    signal U3_INIT : Std_Logic;
-    signal U3_SHIFT : Std_Logic;
-    signal U3_ADD : Std_Logic;
-    signal OUT_INT : Std_Logic_vector(15 downto 0);
-
-begin
-
-
-    U3: Controller
-        port map ( STB => STB,
-                   CLK => CLK,
-                   LSB => U1_LSB,
-                   DONE => DONE_local,
-                   RST => RST,
-                   INIT => U3_INIT,
-                   SHIFT => U3_SHIFT,
-                   ADD => U3_ADD );
-
-    U2: Srb
-        port map ( SHIFT => U3_SHIFT,
-                   LD => U3_INIT,
-                   CLK => CLK,
-                   B => B,
-                   OUTS => OUT_INT );
-
-    U5: AddAccu
-        port map ( CLR => U3_INIT,
-                   LD => U3_ADD,
-                   OUTS => OUT_INT,
-                   CLK => CLK,
-                   RESULT => RESULT );
-
-    U1: Sra
-        port map ( SHIFT => U3_SHIFT,
-                   LD => U3_INIT,
-                   RST => RST,
-                   CLK => CLK,
-                   A => A,
-                   DONE => DONE_local,
-                   LSB => U1_LSB );
-
-    DONE <= DONE_local;
-
-end Structural;
-
-configuration CFG_Multi8 of Multi8 is
-   for Structural
-
-   end for;
-end CFG_Multi8;
-
-
-----------------------------------------------------------------------
diff --git a/alliance/share/tutorials/vasy/multi8/multi8_debug.pat b/alliance/share/tutorials/vasy/multi8/multi8_debug.pat
deleted file mode 100644
index 84189d70..00000000
--- a/alliance/share/tutorials/vasy/multi8/multi8_debug.pat
+++ /dev/null
@@ -1,67 +0,0 @@
-
-in       clk B;;
-in       rst B;;
-in       stb B;;
-in       A (7 downto 0) X;;
-in       B (7 downto 0) X;;
-out      result (15 downto 0) X;;
-out      done B;
-
-register u3.state(0 to 2) X;;
-register u1.outsint(7 downto 0) X;;
-
-begin
-
--- PATTERN DESCRIPTION :
-
- : 0 1 0 00 00 ?**** ?* ?* ?**;
- : 1 1 0 00 00 ?**** ?* ?* ?**;
- : 0 1 0 00 00 ?**** ?* ?* ?**;
- : 0 0 0 00 00 ?**** ?* ?* ?**;
- : 0 0 1 00 00 ?**** ?* ?* ?**;
- : 1 0 1 00 00 ?**** ?* ?* ?**;
- : 0 0 1 00 00 ?**** ?* ?* ?**;
- : 0 0 0 02 03 ?**** ?* ?* ?**;
- : 1 0 0 02 03 ?**** ?* ?* ?**;
- : 0 0 0 02 03 ?**** ?* ?* ?**;
- : 0 0 0 00 00 ?**** ?* ?* ?**;
- : 1 0 0 00 00 ?**** ?* ?* ?**;
- : 0 0 0 00 00 ?**** ?* ?* ?**;
- : 0 0 0 00 00 ?**** ?* ?* ?**;
- : 1 0 0 00 00 ?**** ?* ?* ?**;
- : 0 0 0 00 00 ?**** ?* ?* ?**;
- : 0 0 0 00 00 ?**** ?* ?* ?**;
- : 1 0 0 00 00 ?**** ?* ?* ?**;
- : 0 0 0 00 00 ?**** ?* ?* ?**;
- : 0 0 0 00 00 ?**** ?* ?* ?**;
- : 1 0 0 00 00 ?**** ?* ?* ?**;
- : 0 0 0 00 00 ?**** ?* ?* ?**;
- : 0 0 0 00 00 ?**** ?* ?* ?**;
- : 1 0 0 00 00 ?**** ?* ?* ?**;
- : 0 0 0 00 00 ?**** ?* ?* ?**;
- : 0 0 0 00 00 ?**** ?* ?* ?**;
- : 1 0 0 00 00 ?**** ?* ?* ?**;
- : 0 0 0 00 00 ?**** ?* ?* ?**;
- : 0 0 0 00 00 ?**** ?* ?* ?**;
- : 1 0 0 00 00 ?**** ?* ?* ?**;
- : 0 0 0 00 00 ?**** ?* ?* ?**;
- : 0 0 0 00 00 ?**** ?* ?* ?**;
- : 1 0 0 00 00 ?**** ?* ?* ?**;
- : 0 0 0 00 00 ?**** ?* ?* ?**;
- : 0 0 0 00 00 ?**** ?* ?* ?**;
- : 1 0 0 00 00 ?**** ?* ?* ?**;
- : 0 0 0 00 00 ?**** ?* ?* ?**;
- : 0 0 0 00 00 ?**** ?* ?* ?**;
- : 1 0 0 00 00 ?**** ?* ?* ?**;
- : 0 0 0 00 00 ?**** ?* ?* ?**;
- : 0 0 0 00 00 ?**** ?* ?* ?**;
- : 1 0 0 00 00 ?**** ?* ?* ?**;
- : 0 0 0 00 00 ?**** ?* ?* ?**;
- : 0 0 0 00 00 ?**** ?* ?* ?**;
- : 1 0 0 00 00 ?**** ?* ?* ?**;
- : 0 0 0 00 00 ?**** ?* ?* ?**;
- : 0 0 0 00 00 ?**** ?* ?* ?**;
- : 1 0 0 00 00 ?**** ?* ?* ?**;
- : 0 0 0 00 00 ?**** ?* ?* ?**;
-
-end;
diff --git a/alliance/share/tutorials/vasy/multi8/sra.vhdl b/alliance/share/tutorials/vasy/multi8/sra.vhdl
deleted file mode 100644
index 999c3efa..00000000
--- a/alliance/share/tutorials/vasy/multi8/sra.vhdl
+++ /dev/null
@@ -1,55 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_arith.ALL;
-use IEEE.STD_LOGIC_unsigned.ALL;
-
-entity Sra is
-
-    port ( Shift : in Std_Logic ;
-           LD : in Std_Logic ;
-	   RST : in Std_Logic;
-           CLK : in Std_Logic ;
-           A : in Std_Logic_Vector(7 downto 0);
-
-           Done : out Std_Logic ;
-           LSB : out Std_Logic  );
-
-end Sra;
-
-
-----------------------------------------------------------------------
-
-architecture DataFlow OF Sra is
-
-signal outsint : Std_Logic_Vector(7 downto 0);
-begin
-process (CLK)
-begin
-     if CLK'event and CLK='0' then
-         if RST ='1' then outsint <= (others => '0');
-	 elsif LD = '1' then outsint <= A ;
-         elsif Shift= '1' then
-            outsint(7 downto 0) <= '0' & outsint(7 downto 1);
-	else outsint <= outsint;
-         end if;
-     end if;
-end process;
-
-process( outsint )
-  variable RESULT : Std_Logic;
-begin
-   RESULT := '0';
-   for j in outsint'range loop
-       RESULT := outsint(j) or RESULT;
-       exit when RESULT = '1';
-   end loop;
-   RESULT := not(RESULT);
-
-   Done <= RESULT;
-end process;
-LSB <= outsint(0);
-
-end DataFlow;
-
-
-----------------------------------------------------------------------
diff --git a/alliance/share/tutorials/vasy/multi8/srb.vhdl b/alliance/share/tutorials/vasy/multi8/srb.vhdl
deleted file mode 100644
index 610a9133..00000000
--- a/alliance/share/tutorials/vasy/multi8/srb.vhdl
+++ /dev/null
@@ -1,41 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_arith.ALL;
-use IEEE.STD_LOGIC_unsigned.ALL;
-
-entity Srb is
-
-    port ( Shift : in Std_Logic ;
-           LD : in Std_Logic ;
-           CLK : in Std_Logic ;
-           B : in Std_Logic_Vector(7 downto 0);
-
-           OUTS : out Std_Logic_Vector(15 downto 0));
-
-end Srb;
-
-
-----------------------------------------------------------------------
-
-architecture DataFlow OF Srb is
-signal outsint : Std_Logic_Vector(15 downto 0);
-
-begin
-process (CLK)
-begin
-     if CLK'event and CLK='0' then
-         if LD = '1' then outsint <= 
-	    B(7)&B(7)&B(7)&B(7)&B(7)&B(7)&B(7)&B(7)&B ;
-         elsif Shift= '1' then  
-              outsint(15 downto 0) <= outsint(14 downto 0) & '0';
-	 else outsint <= outsint;
-         end if;
-     end if;
-end process;
-
-OUTS <= outsint;
-
-end DataFlow;
-
-
-----------------------------------------------------------------------