- a simple example (adder 4 bits) to see how to design a circuit from VHDL up to
CIF layout using Alliance tools. More examples are comming soon ...
This commit is contained in:
Ludovic Jacomme
parent
8d20649576
commit
af7ca9daf4
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@ -0,0 +1,346 @@
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# /*------------------------------------------------------------\
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# | |
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# | File : Makefile |
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# | |
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# | Author : Jacomme Ludovic |
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# | |
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# \------------------------------------------------------------*/
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# /*------------------------------------------------------------\
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# | |
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# | Cells |
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# | |
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# \------------------------------------------------------------*/
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# /*------------------------------------------------------------\
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# | |
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# | Binary |
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# | |
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# \------------------------------------------------------------*/
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ALLIANCE_BIN=$(ALLIANCE_TOP)/bin
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VASY = $(ALLIANCE_BIN)/vasy
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ASIMUT = $(ALLIANCE_BIN)/asimut
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BOOM = $(ALLIANCE_BIN)/boom
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BOOG = $(ALLIANCE_BIN)/boog
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LOON = $(ALLIANCE_BIN)/loon
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OCP = $(ALLIANCE_BIN)/ocp
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NERO = $(ALLIANCE_BIN)/nero
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COUGAR = $(ALLIANCE_BIN)/cougar
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LVX = $(ALLIANCE_BIN)/lvx
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DRUC = $(ALLIANCE_BIN)/druc
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S2R = $(ALLIANCE_BIN)/s2r
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BLAST = $(ALLIANCE_BIN)/sblast
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DREAL = $(ALLIANCE_BIN)/dreal
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GRAAL = $(ALLIANCE_BIN)/graal
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XSCH = $(ALLIANCE_BIN)/xsch
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XPAT = $(ALLIANCE_BIN)/xpat
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XFSM = $(ALLIANCE_BIN)/xfsm
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TOUCH = touch
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TARGET_LIB = $(ALLIANCE_TOP)/cells/sxlib
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RDS_TECHNO_SYMB = ../etc/techno-symb.rds
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RDS_TECHNO = ../etc/techno-035.rds
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SPI_MODEL = $(ALLIANCE_TOP)/etc/spimodel.cfg
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METAL_LEVEL = 2
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# /*------------------------------------------------------------\
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# | |
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# | Environement |
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# | |
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# \------------------------------------------------------------*/
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ENV_VASY = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
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MBK_CATAL_NAME=NO_CATAL; export MBK_CATAL_NAME
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ENV_BOOM = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
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ENV_BOOG = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
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MBK_IN_LO=vst; export MBK_IN_LO; \
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MBK_OUT_LO=vst; export MBK_OUT_LO; \
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MBK_TARGET_LIB=$(TARGET_LIB); export MBK_TARGET_LIB; \
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
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ENV_LOON = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
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MBK_IN_LO=vst; export MBK_IN_LO; \
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MBK_OUT_LO=vst; export MBK_OUT_LO; \
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MBK_TARGET_LIB=$(TARGET_LIB); export MBK_TARGET_LIB; \
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MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
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ENV_ASIMUT_VASY = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
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MBK_CATAL_NAME=CATAL_ASIMUT_VASY; export MBK_CATAL_NAME;\
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MBK_IN_LO=vst; export MBK_IN_LO;\
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MBK_OUT_LO=vst; export MBK_OUT_LO
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ENV_ASIMUT_SYNTH = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME;\
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MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
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MBK_IN_LO=vst; export MBK_IN_LO;\
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MBK_OUT_LO=vst; export MBK_OUT_LO
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ENV_OCP = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
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MBK_IN_LO=vst; export MBK_IN_LO; \
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MBK_OUT_LO=vst; export MBK_OUT_LO; \
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MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
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MBK_IN_PH=ap; export MBK_IN_PH; \
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MBK_OUT_PH=ap; export MBK_OUT_PH; \
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
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ENV_NERO = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
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MBK_IN_LO=vst; export MBK_IN_LO; \
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MBK_OUT_LO=vst; export MBK_OUT_LO; \
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MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
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MBK_IN_PH=ap; export MBK_IN_PH; \
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MBK_OUT_PH=ap; export MBK_OUT_PH; \
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
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ENV_COUGAR_SPI = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
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MBK_IN_LO=spi; export MBK_IN_LO; \
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MBK_OUT_LO=spi; export MBK_OUT_LO; \
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MBK_SPI_MODEL=$(SPI_MODEL); export MBK_SPI_MODEL; \
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MBK_SPI_ONE_NODE_NORC="true"; export MBK_SPI_ONE_NODE_NORC; \
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MBK_SPI_NAMEDNODES="true"; export MBK_SPI_NAMEDNODES; \
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RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME; \
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RDS_IN=cif; export RDS_IN; \
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RDS_OUT=cif; export RDS_OUT; \
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MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
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MBK_IN_PH=ap; export MBK_IN_PH; \
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MBK_OUT_PH=ap; export MBK_OUT_PH; \
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
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ENV_COUGAR = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
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MBK_IN_LO=al; export MBK_IN_LO; \
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MBK_OUT_LO=al; export MBK_OUT_LO; \
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RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME; \
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RDS_IN=cif; export RDS_IN; \
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RDS_OUT=cif; export RDS_OUT; \
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MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
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MBK_IN_PH=ap; export MBK_IN_PH; \
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MBK_OUT_PH=ap; export MBK_OUT_PH; \
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
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ENV_LVX = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
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MBK_IN_LO=vst; export MBK_IN_LO; \
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MBK_OUT_LO=vst; export MBK_OUT_LO; \
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MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
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ENV_DRUC = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
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RDS_TECHNO_NAME=$(RDS_TECHNO_SYMB); export RDS_TECHNO_NAME; \
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MBK_IN_PH=ap; export MBK_IN_PH; \
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MBK_OUT_PH=ap; export MBK_OUT_PH; \
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MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
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ENV_S2R = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
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RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME; \
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RDS_IN=cif; export RDS_IN; \
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RDS_OUT=cif; export RDS_OUT; \
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MBK_IN_PH=ap; export MBK_IN_PH; \
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MBK_OUT_PH=ap; export MBK_OUT_PH; \
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MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
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all : adder4.cif
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# /*------------------------------------------------------------\
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# | |
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# | Vasy |
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# | |
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# \------------------------------------------------------------*/
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adder4.vbe : adder4.vhdl
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$(ENV_VASY); $(VASY) -a -B -o -p -I vhdl adder4
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# /*------------------------------------------------------------\
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# | |
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# | Asimut |
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# | |
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# \------------------------------------------------------------*/
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res_vasy_1.pat : adder4.vbe
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$(ENV_ASIMUT_VASY); $(ASIMUT) -b adder4 adder4 res_vasy_1
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res_synth_1.pat : adder4.vst
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$(ENV_ASIMUT_SYNTH); $(ASIMUT) adder4 adder4 res_synth_1
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# /*------------------------------------------------------------\
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# | |
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# | Boom |
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# | |
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# \------------------------------------------------------------*/
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boom.done : adder4_o.vbe
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@$(TOUCH) boom.done
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adder4_o.vbe : adder4.vbe adder4.boom res_vasy_1.pat
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$(ENV_BOOM); $(BOOM) -VP adder4 adder4_o
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# /*------------------------------------------------------------\
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# | |
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# | Boog |
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# | |
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# \------------------------------------------------------------*/
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boog.done : adder4_o.vst
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@$(TOUCH) boog.done
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adder4_o.vst : adder4_o.vbe
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$(ENV_BOOG); $(BOOG) adder4_o
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# /*------------------------------------------------------------\
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# | |
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# | Loon |
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# | |
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# \------------------------------------------------------------*/
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loon.done : adder4.vst
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@$(TOUCH) loon.done
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adder4.vst : adder4_o.vst
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$(ENV_LOON); $(LOON) adder4_o adder4
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# /*------------------------------------------------------------\
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# | |
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# | OCP |
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# | |
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# \------------------------------------------------------------*/
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adder4_p.ap : res_synth_1.pat
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$(ENV_OCP); $(OCP) -v -gnuplot -ioc adder4 adder4 adder4_p
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# /*------------------------------------------------------------\
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# | |
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# | NERO |
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# | |
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# \------------------------------------------------------------*/
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adder4.ap : adder4_p.ap adder4.vst
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$(ENV_NERO); $(NERO) -v -$(METAL_LEVEL) -p adder4_p adder4 adder4
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# /*------------------------------------------------------------\
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# | |
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# | Cougar |
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# | |
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# \------------------------------------------------------------*/
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adder4_e.spi : adder4.ap
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$(ENV_COUGAR_SPI); $(COUGAR) -v -ac adder4 adder4_e
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adder4_erc.spi : adder4.ap
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$(ENV_COUGAR_SPI); $(COUGAR) -v -ar adder4 adder4_erc
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adder4_erc.al : adder4.ap
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$(ENV_COUGAR); $(COUGAR) -v -ar adder4 adder4_erc
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adder4_e.al : adder4.ap
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$(ENV_COUGAR); $(COUGAR) -v -ac adder4 adder4_e
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adder4_et.al : adder4.ap
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$(ENV_COUGAR); $(COUGAR) -v -ac -t adder4 adder4_et
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adder4_et.spi : adder4.ap
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$(ENV_COUGAR_SPI); $(COUGAR) -v -ac -t adder4 adder4_et
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adder4_er.al : adder4.cif
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$(ENV_COUGAR); $(COUGAR) -v -r -t adder4 adder4_er
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adder4_real.al : adder4.ap
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$(ENV_COUGAR); $(ENV_S2R); $(COUGAR) -v -ac adder4 adder4_real
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adder4_real_t.al : adder4.ap
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$(ENV_COUGAR); $(ENV_S2R); $(COUGAR) -v -t -ac adder4 adder4_real_t
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# /*------------------------------------------------------------\
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# | |
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# | Lvx |
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# | |
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# \------------------------------------------------------------*/
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lvx.done : adder4.vst adder4_e.al adder4_e.spi
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$(ENV_LVX); $(LVX) vst al adder4 adder4_e -f
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$(TOUCH) lvx.done
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# /*------------------------------------------------------------\
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# | |
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# | Druc |
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# | |
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# \------------------------------------------------------------*/
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druc.done : lvx.done adder4.ap
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$(ENV_DRUC); $(DRUC) adder4
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$(TOUCH) druc.done
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# /*------------------------------------------------------------\
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# | |
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# | S2R |
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# | |
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# \------------------------------------------------------------*/
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adder4.cif : druc.done
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$(ENV_S2R); $(S2R) -v adder4
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# /*------------------------------------------------------------\
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# | |
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# | TOOLS |
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# | |
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# \------------------------------------------------------------*/
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graal :
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$(ENV_S2R); $(GRAAL)
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graal_adder4_p : adder4_p.ap
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$(ENV_S2R); $(GRAAL) -l adder4_p
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graal_adder4 : adder4.ap
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$(ENV_S2R); $(GRAAL) -l adder4
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xsch:
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$(ENV_LOON); $(XSCH)
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xsch_adder4_o : adder4.vst
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$(ENV_LOON); $(XSCH) -l adder4_o
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xsch_adder4 : adder4.vst
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$(ENV_LOON); $(XSCH) -l adder4
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xsch_adder4_e: adder4_e.al
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$(ENV_COUGAR); $(XSCH) -l adder4_e
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xsch_adder4_et: adder4_et.al
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$(ENV_COUGAR); $(XSCH) -l adder4_et
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xpat:
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$(ENV_ASIMUT_SYNTH); $(XPAT)
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xpat_synth: res_synth_1.pat
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$(ENV_ASIMUT_SYNTH); $(XPAT) -l res_synth_1
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xpat_vasy : res_vasy_1.pat
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$(ENV_ASIMUT_SYNTH); $(XPAT) -l res_vasy_1
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dreal:
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$(ENV_S2R); $(DREAL)
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dreal_adder4 : adder4.cif
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$(ENV_S2R); $(DREAL) -l adder4
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# /*------------------------------------------------------------\
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# | |
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# | Clean |
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# | |
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# \------------------------------------------------------------*/
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realclean : clean
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clean :
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$(RM) -f *.vst adder4_e.spi adder4_et.spi *.vbe res_*.pat *.boom *.done *.xsc *.gpl \
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*.ap *.drc *.dat *.gds *.cif *.rep \
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*.log *.out *.raw *.al
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@ -0,0 +1,118 @@
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# /*------------------------------------------------------------\
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# | |
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# | File : README |
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# | |
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# | Author : Jacomme Ludovic |
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# | |
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# \------------------------------------------------------------*/
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This directory contains the VHDL description of an adder 4 bits and
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the associated stimuli file, and also a configuration file for IO
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placement (used during the Place and Route step).
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The Makefile set environement variables properly and run Alliance tools,
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following each step of the design flow from VHDL up to real layout in a
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pseudo 0.35 techno.
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The environement variable ALLIANCE_TOP as to be set.
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The main targets of the makefile are listed below (following the design flow).
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#
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# RTL SYNTHESIS
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#
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adder4.vbe : Run the VHDL analyzer (VASY) on the VHDL description
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(adder4.vhdl) and transform it into a boolean network (adder4.vbe).
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res_vasy_1.pat : Run the VHDL simulator (ASIMUT) on adder4.vbe using the pattern/stimuli file
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adder4.pat. This step checks if the adder4.vbe description is working properly.
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xpat_vasy : Run the graphical waveform viewer (XPAT) on the resulting file res_vasy_1.pat
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adder4_o.vbe : Run the Boolean network optimizer (BOOM) on the adder4.vbe and
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factorize/minimize boolean equations, and generate a new description
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adder4_o.vbe.
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adder4_o.vst : Run the boolean mapper (BOOG) on the optimized description adder4_o.vbe
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and using the sxlib standard cell library, map all boolean nodes to
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an equivalent set of standard cells.
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xsch_adder4_o : Run the schematic viewer (XSCH) on the structural netlist adder4_o.vst
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adder4.vst : Run the net optimizer (LOON) on the structural description adder4_o.vst.
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It inserts buffers on the critical path using the sxlib standard cell library
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and generates a new structural netlist adder4.vst .
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xsch_adder4 : Run the schematic viewer (XSCH) on the bufferized netlist adder4.vst .
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The critical path would be displayed in red color.
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res_synth_1.pat : Run the VHDL simulator (ASIMUT) on the structural description adder4.vst using
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the pattern/stimuli file adder4.pat and the behavioral description (.VBE) of each
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cells of the standard cell library (sxlib).
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This step checks if the adder4.vst description is still working properly.
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#
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# PLACE AND ROUTE
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#
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adder4_p.ap : Run the placement tool (OCP) on the structural description adder4.vst.
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It generates a physical placement file (adder4_p.ap) that would be given
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to the router (NERO).
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graal_adder4_p : Launch the physical layout editor (GRAAL) and display the result of the placement tool
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(adder4_p.ap).
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adder4.ap : Run the router tool (NERO). Given the structural description adder4.vst, the
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placement file (adder4_p) and the position of external connectors (adder4.ioc)
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the router generates a physical view (adder4.ap) where all nets have been routed.
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graal_adder4 : Launch the physical layout editor (GRAAL) and display the result of the router tool
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(adder4.ap).
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#
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# Netlist / parasitics extraction
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#
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adder4_e.al : Run the hierarchical netlist extractor (COUGAR) and extracts the netlist with parasitic
|
||||
informations (physical parameters are taken in the techno-035.rds file).
|
||||
This tool generates the extracted netlist adder4_e.al
|
||||
|
||||
xsch_adder4_e : Run the schematic viewer (XSCH) on the hierarchical extracted netlist (adder4_e.al).
|
||||
|
||||
adder4_et.al : Run the netlist extractor (COUGAR) and extracts the netlist at the transistor level
|
||||
with parasitics informations (adder4_et.al).
|
||||
|
||||
xsch_adder4_et : Run the schematic viewer (XSCH) on the extracted transistor netlist (adder4_et.al).
|
||||
|
||||
#
|
||||
# Netlists comparison
|
||||
#
|
||||
|
||||
lvx.done : Run the gate netlist comparator (LVX) and checks if the extracted netlist is the same as
|
||||
the structural structural netlist. This step checks if the place and route phases are ok.
|
||||
|
||||
#
|
||||
# Design rule checker
|
||||
#
|
||||
|
||||
druc.done : Launch the design rule checker on the layout generated by the router (adder4.ap). The design
|
||||
rules are specified in the RDS file (techno-symb.rds).
|
||||
|
||||
|
||||
#
|
||||
# Symbolic layout to real layout
|
||||
#
|
||||
|
||||
adder4.cif : Transforms the symbolic layout in lambda (adder4.ap) in a 0.35u real layout using the tool S2R.
|
||||
It generates a CIF file (adder4.cif).
|
||||
|
||||
dreal_adder4 : Launch the real layout editor (DREAL) and display the result of S2R
|
||||
(adder4.cif).
|
||||
|
||||
|
||||
#
|
||||
# Clean
|
||||
|
||||
The clean target remove all generated files ...
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
# Copyright (c) 1997 by Cadence. All rights reserved.
|
||||
###################################################################
|
||||
# In each of TOP()/BOTTOM()/LEFT()/RIGHT() section, there are #
|
||||
# placed IOs. In the IGNORE() section, the IOs are ignored #
|
||||
# by the IOPlacer. In every section, the IO syntax could be: #
|
||||
# for pin: (IOPIN iopinName.0 ); #
|
||||
# for pad: iopadName orientation ; #
|
||||
# for space: SPACE value; #
|
||||
# The capital words are keywords. orientation is not required. #
|
||||
# The value is the space between the IO above and the IO below it.#
|
||||
###################################################################
|
||||
|
||||
TOP ( # IOs are ordered from left to right
|
||||
(IOPIN a(3).0 );
|
||||
(IOPIN a(2).0 );
|
||||
(IOPIN a(1).0 );
|
||||
(IOPIN a(0).0 );
|
||||
(IOPIN b(3).0 );
|
||||
(IOPIN b(2).0 );
|
||||
(IOPIN b(1).0 );
|
||||
(IOPIN b(0).0 );
|
||||
)
|
||||
BOTTOM ( # IOs are ordered from left to right
|
||||
(IOPIN result(3).0 );
|
||||
(IOPIN result(2).0 );
|
||||
(IOPIN result(1).0 );
|
||||
(IOPIN result(0).0 );
|
||||
)
|
||||
IGNORE ( # IOs are ignored(not placed) by IO Placer
|
||||
)
|
||||
|
|
@ -0,0 +1,527 @@
|
|||
|
||||
in a (3 downto 0) X;;;
|
||||
in b (3 downto 0) X;;;
|
||||
out result (3 downto 0) X;;;
|
||||
in vss B;;
|
||||
in vdd B;;
|
||||
|
||||
begin
|
||||
|
||||
-- Pattern description :
|
||||
-- A B Res V V
|
||||
|
||||
< 0ns>: 0 0 ?* 0 1;
|
||||
< +10ns>: 0 0 ?* 0 1;
|
||||
< +10ns>: 0 0 ?* 0 1;
|
||||
< +10ns>: 0 1 ?* 0 1;
|
||||
< +10ns>: 0 1 ?* 0 1;
|
||||
< +10ns>: 0 2 ?* 0 1;
|
||||
< +10ns>: 0 2 ?* 0 1;
|
||||
< +10ns>: 0 3 ?* 0 1;
|
||||
< +10ns>: 0 3 ?* 0 1;
|
||||
< +10ns>: 0 4 ?* 0 1;
|
||||
< +10ns>: 0 4 ?* 0 1;
|
||||
< +10ns>: 0 5 ?* 0 1;
|
||||
< +10ns>: 0 5 ?* 0 1;
|
||||
< +10ns>: 0 6 ?* 0 1;
|
||||
< +10ns>: 0 6 ?* 0 1;
|
||||
< +10ns>: 0 7 ?* 0 1;
|
||||
< +10ns>: 0 7 ?* 0 1;
|
||||
< +10ns>: 0 8 ?* 0 1;
|
||||
< +10ns>: 0 8 ?* 0 1;
|
||||
< +10ns>: 0 9 ?* 0 1;
|
||||
< +10ns>: 0 9 ?* 0 1;
|
||||
< +10ns>: 0 a ?* 0 1;
|
||||
< +10ns>: 0 a ?* 0 1;
|
||||
< +10ns>: 0 b ?* 0 1;
|
||||
< +10ns>: 0 b ?* 0 1;
|
||||
< +10ns>: 0 c ?* 0 1;
|
||||
< +10ns>: 0 c ?* 0 1;
|
||||
< +10ns>: 0 d ?* 0 1;
|
||||
< +10ns>: 0 d ?* 0 1;
|
||||
< +10ns>: 0 e ?* 0 1;
|
||||
< +10ns>: 0 e ?* 0 1;
|
||||
< +10ns>: 0 f ?* 0 1;
|
||||
< +10ns>: 0 f ?* 0 1;
|
||||
< +10ns>: 1 0 ?* 0 1;
|
||||
< +10ns>: 1 0 ?* 0 1;
|
||||
< +10ns>: 1 1 ?* 0 1;
|
||||
< +10ns>: 1 1 ?* 0 1;
|
||||
< +10ns>: 1 2 ?* 0 1;
|
||||
< +10ns>: 1 2 ?* 0 1;
|
||||
< +10ns>: 1 3 ?* 0 1;
|
||||
< +10ns>: 1 3 ?* 0 1;
|
||||
< +10ns>: 1 4 ?* 0 1;
|
||||
< +10ns>: 1 4 ?* 0 1;
|
||||
< +10ns>: 1 5 ?* 0 1;
|
||||
< +10ns>: 1 5 ?* 0 1;
|
||||
< +10ns>: 1 6 ?* 0 1;
|
||||
< +10ns>: 1 6 ?* 0 1;
|
||||
< +10ns>: 1 7 ?* 0 1;
|
||||
< +10ns>: 1 7 ?* 0 1;
|
||||
< +10ns>: 1 8 ?* 0 1;
|
||||
< +10ns>: 1 8 ?* 0 1;
|
||||
< +10ns>: 1 9 ?* 0 1;
|
||||
< +10ns>: 1 9 ?* 0 1;
|
||||
< +10ns>: 1 a ?* 0 1;
|
||||
< +10ns>: 1 a ?* 0 1;
|
||||
< +10ns>: 1 b ?* 0 1;
|
||||
< +10ns>: 1 b ?* 0 1;
|
||||
< +10ns>: 1 c ?* 0 1;
|
||||
< +10ns>: 1 c ?* 0 1;
|
||||
< +10ns>: 1 d ?* 0 1;
|
||||
< +10ns>: 1 d ?* 0 1;
|
||||
< +10ns>: 1 e ?* 0 1;
|
||||
< +10ns>: 1 e ?* 0 1;
|
||||
< +10ns>: 1 f ?* 0 1;
|
||||
< +10ns>: 1 f ?* 0 1;
|
||||
< +10ns>: 2 0 ?* 0 1;
|
||||
< +10ns>: 2 0 ?* 0 1;
|
||||
< +10ns>: 2 1 ?* 0 1;
|
||||
< +10ns>: 2 1 ?* 0 1;
|
||||
< +10ns>: 2 2 ?* 0 1;
|
||||
< +10ns>: 2 2 ?* 0 1;
|
||||
< +10ns>: 2 3 ?* 0 1;
|
||||
< +10ns>: 2 3 ?* 0 1;
|
||||
< +10ns>: 2 4 ?* 0 1;
|
||||
< +10ns>: 2 4 ?* 0 1;
|
||||
< +10ns>: 2 5 ?* 0 1;
|
||||
< +10ns>: 2 5 ?* 0 1;
|
||||
< +10ns>: 2 6 ?* 0 1;
|
||||
< +10ns>: 2 6 ?* 0 1;
|
||||
< +10ns>: 2 7 ?* 0 1;
|
||||
< +10ns>: 2 7 ?* 0 1;
|
||||
< +10ns>: 2 8 ?* 0 1;
|
||||
< +10ns>: 2 8 ?* 0 1;
|
||||
< +10ns>: 2 9 ?* 0 1;
|
||||
< +10ns>: 2 9 ?* 0 1;
|
||||
< +10ns>: 2 a ?* 0 1;
|
||||
< +10ns>: 2 a ?* 0 1;
|
||||
< +10ns>: 2 b ?* 0 1;
|
||||
< +10ns>: 2 b ?* 0 1;
|
||||
< +10ns>: 2 c ?* 0 1;
|
||||
< +10ns>: 2 c ?* 0 1;
|
||||
< +10ns>: 2 d ?* 0 1;
|
||||
< +10ns>: 2 d ?* 0 1;
|
||||
< +10ns>: 2 e ?* 0 1;
|
||||
< +10ns>: 2 e ?* 0 1;
|
||||
< +10ns>: 2 f ?* 0 1;
|
||||
< +10ns>: 2 f ?* 0 1;
|
||||
< +10ns>: 3 0 ?* 0 1;
|
||||
< +10ns>: 3 0 ?* 0 1;
|
||||
< +10ns>: 3 1 ?* 0 1;
|
||||
< +10ns>: 3 1 ?* 0 1;
|
||||
< +10ns>: 3 2 ?* 0 1;
|
||||
< +10ns>: 3 2 ?* 0 1;
|
||||
< +10ns>: 3 3 ?* 0 1;
|
||||
< +10ns>: 3 3 ?* 0 1;
|
||||
< +10ns>: 3 4 ?* 0 1;
|
||||
< +10ns>: 3 4 ?* 0 1;
|
||||
< +10ns>: 3 5 ?* 0 1;
|
||||
< +10ns>: 3 5 ?* 0 1;
|
||||
< +10ns>: 3 6 ?* 0 1;
|
||||
< +10ns>: 3 6 ?* 0 1;
|
||||
< +10ns>: 3 7 ?* 0 1;
|
||||
< +10ns>: 3 7 ?* 0 1;
|
||||
< +10ns>: 3 8 ?* 0 1;
|
||||
< +10ns>: 3 8 ?* 0 1;
|
||||
< +10ns>: 3 9 ?* 0 1;
|
||||
< +10ns>: 3 9 ?* 0 1;
|
||||
< +10ns>: 3 a ?* 0 1;
|
||||
< +10ns>: 3 a ?* 0 1;
|
||||
< +10ns>: 3 b ?* 0 1;
|
||||
< +10ns>: 3 b ?* 0 1;
|
||||
< +10ns>: 3 c ?* 0 1;
|
||||
< +10ns>: 3 c ?* 0 1;
|
||||
< +10ns>: 3 d ?* 0 1;
|
||||
< +10ns>: 3 d ?* 0 1;
|
||||
< +10ns>: 3 e ?* 0 1;
|
||||
< +10ns>: 3 e ?* 0 1;
|
||||
< +10ns>: 3 f ?* 0 1;
|
||||
< +10ns>: 3 f ?* 0 1;
|
||||
< +10ns>: 4 0 ?* 0 1;
|
||||
< +10ns>: 4 0 ?* 0 1;
|
||||
< +10ns>: 4 1 ?* 0 1;
|
||||
< +10ns>: 4 1 ?* 0 1;
|
||||
< +10ns>: 4 2 ?* 0 1;
|
||||
< +10ns>: 4 2 ?* 0 1;
|
||||
< +10ns>: 4 3 ?* 0 1;
|
||||
< +10ns>: 4 3 ?* 0 1;
|
||||
< +10ns>: 4 4 ?* 0 1;
|
||||
< +10ns>: 4 4 ?* 0 1;
|
||||
< +10ns>: 4 5 ?* 0 1;
|
||||
< +10ns>: 4 5 ?* 0 1;
|
||||
< +10ns>: 4 6 ?* 0 1;
|
||||
< +10ns>: 4 6 ?* 0 1;
|
||||
< +10ns>: 4 7 ?* 0 1;
|
||||
< +10ns>: 4 7 ?* 0 1;
|
||||
< +10ns>: 4 8 ?* 0 1;
|
||||
< +10ns>: 4 8 ?* 0 1;
|
||||
< +10ns>: 4 9 ?* 0 1;
|
||||
< +10ns>: 4 9 ?* 0 1;
|
||||
< +10ns>: 4 a ?* 0 1;
|
||||
< +10ns>: 4 a ?* 0 1;
|
||||
< +10ns>: 4 b ?* 0 1;
|
||||
< +10ns>: 4 b ?* 0 1;
|
||||
< +10ns>: 4 c ?* 0 1;
|
||||
< +10ns>: 4 c ?* 0 1;
|
||||
< +10ns>: 4 d ?* 0 1;
|
||||
< +10ns>: 4 d ?* 0 1;
|
||||
< +10ns>: 4 e ?* 0 1;
|
||||
< +10ns>: 4 e ?* 0 1;
|
||||
< +10ns>: 4 f ?* 0 1;
|
||||
< +10ns>: 4 f ?* 0 1;
|
||||
< +10ns>: 5 0 ?* 0 1;
|
||||
< +10ns>: 5 0 ?* 0 1;
|
||||
< +10ns>: 5 1 ?* 0 1;
|
||||
< +10ns>: 5 1 ?* 0 1;
|
||||
< +10ns>: 5 2 ?* 0 1;
|
||||
< +10ns>: 5 2 ?* 0 1;
|
||||
< +10ns>: 5 3 ?* 0 1;
|
||||
< +10ns>: 5 3 ?* 0 1;
|
||||
< +10ns>: 5 4 ?* 0 1;
|
||||
< +10ns>: 5 4 ?* 0 1;
|
||||
< +10ns>: 5 5 ?* 0 1;
|
||||
< +10ns>: 5 5 ?* 0 1;
|
||||
< +10ns>: 5 6 ?* 0 1;
|
||||
< +10ns>: 5 6 ?* 0 1;
|
||||
< +10ns>: 5 7 ?* 0 1;
|
||||
< +10ns>: 5 7 ?* 0 1;
|
||||
< +10ns>: 5 8 ?* 0 1;
|
||||
< +10ns>: 5 8 ?* 0 1;
|
||||
< +10ns>: 5 9 ?* 0 1;
|
||||
< +10ns>: 5 9 ?* 0 1;
|
||||
< +10ns>: 5 a ?* 0 1;
|
||||
< +10ns>: 5 a ?* 0 1;
|
||||
< +10ns>: 5 b ?* 0 1;
|
||||
< +10ns>: 5 b ?* 0 1;
|
||||
< +10ns>: 5 c ?* 0 1;
|
||||
< +10ns>: 5 c ?* 0 1;
|
||||
< +10ns>: 5 d ?* 0 1;
|
||||
< +10ns>: 5 d ?* 0 1;
|
||||
< +10ns>: 5 e ?* 0 1;
|
||||
< +10ns>: 5 e ?* 0 1;
|
||||
< +10ns>: 5 f ?* 0 1;
|
||||
< +10ns>: 5 f ?* 0 1;
|
||||
< +10ns>: 6 0 ?* 0 1;
|
||||
< +10ns>: 6 0 ?* 0 1;
|
||||
< +10ns>: 6 1 ?* 0 1;
|
||||
< +10ns>: 6 1 ?* 0 1;
|
||||
< +10ns>: 6 2 ?* 0 1;
|
||||
< +10ns>: 6 2 ?* 0 1;
|
||||
< +10ns>: 6 3 ?* 0 1;
|
||||
< +10ns>: 6 3 ?* 0 1;
|
||||
< +10ns>: 6 4 ?* 0 1;
|
||||
< +10ns>: 6 4 ?* 0 1;
|
||||
< +10ns>: 6 5 ?* 0 1;
|
||||
< +10ns>: 6 5 ?* 0 1;
|
||||
< +10ns>: 6 6 ?* 0 1;
|
||||
< +10ns>: 6 6 ?* 0 1;
|
||||
< +10ns>: 6 7 ?* 0 1;
|
||||
< +10ns>: 6 7 ?* 0 1;
|
||||
< +10ns>: 6 8 ?* 0 1;
|
||||
< +10ns>: 6 8 ?* 0 1;
|
||||
< +10ns>: 6 9 ?* 0 1;
|
||||
< +10ns>: 6 9 ?* 0 1;
|
||||
< +10ns>: 6 a ?* 0 1;
|
||||
< +10ns>: 6 a ?* 0 1;
|
||||
< +10ns>: 6 b ?* 0 1;
|
||||
< +10ns>: 6 b ?* 0 1;
|
||||
< +10ns>: 6 c ?* 0 1;
|
||||
< +10ns>: 6 c ?* 0 1;
|
||||
< +10ns>: 6 d ?* 0 1;
|
||||
< +10ns>: 6 d ?* 0 1;
|
||||
< +10ns>: 6 e ?* 0 1;
|
||||
< +10ns>: 6 e ?* 0 1;
|
||||
< +10ns>: 6 f ?* 0 1;
|
||||
< +10ns>: 6 f ?* 0 1;
|
||||
< +10ns>: 7 0 ?* 0 1;
|
||||
< +10ns>: 7 0 ?* 0 1;
|
||||
< +10ns>: 7 1 ?* 0 1;
|
||||
< +10ns>: 7 1 ?* 0 1;
|
||||
< +10ns>: 7 2 ?* 0 1;
|
||||
< +10ns>: 7 2 ?* 0 1;
|
||||
< +10ns>: 7 3 ?* 0 1;
|
||||
< +10ns>: 7 3 ?* 0 1;
|
||||
< +10ns>: 7 4 ?* 0 1;
|
||||
< +10ns>: 7 4 ?* 0 1;
|
||||
< +10ns>: 7 5 ?* 0 1;
|
||||
< +10ns>: 7 5 ?* 0 1;
|
||||
< +10ns>: 7 6 ?* 0 1;
|
||||
< +10ns>: 7 6 ?* 0 1;
|
||||
< +10ns>: 7 7 ?* 0 1;
|
||||
< +10ns>: 7 7 ?* 0 1;
|
||||
< +10ns>: 7 8 ?* 0 1;
|
||||
< +10ns>: 7 8 ?* 0 1;
|
||||
< +10ns>: 7 9 ?* 0 1;
|
||||
< +10ns>: 7 9 ?* 0 1;
|
||||
< +10ns>: 7 a ?* 0 1;
|
||||
< +10ns>: 7 a ?* 0 1;
|
||||
< +10ns>: 7 b ?* 0 1;
|
||||
< +10ns>: 7 b ?* 0 1;
|
||||
< +10ns>: 7 c ?* 0 1;
|
||||
< +10ns>: 7 c ?* 0 1;
|
||||
< +10ns>: 7 d ?* 0 1;
|
||||
< +10ns>: 7 d ?* 0 1;
|
||||
< +10ns>: 7 e ?* 0 1;
|
||||
< +10ns>: 7 e ?* 0 1;
|
||||
< +10ns>: 7 f ?* 0 1;
|
||||
< +10ns>: 7 f ?* 0 1;
|
||||
< +10ns>: 8 0 ?* 0 1;
|
||||
< +10ns>: 8 0 ?* 0 1;
|
||||
< +10ns>: 8 1 ?* 0 1;
|
||||
< +10ns>: 8 1 ?* 0 1;
|
||||
< +10ns>: 8 2 ?* 0 1;
|
||||
< +10ns>: 8 2 ?* 0 1;
|
||||
< +10ns>: 8 3 ?* 0 1;
|
||||
< +10ns>: 8 3 ?* 0 1;
|
||||
< +10ns>: 8 4 ?* 0 1;
|
||||
< +10ns>: 8 4 ?* 0 1;
|
||||
< +10ns>: 8 5 ?* 0 1;
|
||||
< +10ns>: 8 5 ?* 0 1;
|
||||
< +10ns>: 8 6 ?* 0 1;
|
||||
< +10ns>: 8 6 ?* 0 1;
|
||||
< +10ns>: 8 7 ?* 0 1;
|
||||
< +10ns>: 8 7 ?* 0 1;
|
||||
< +10ns>: 8 8 ?* 0 1;
|
||||
< +10ns>: 8 8 ?* 0 1;
|
||||
< +10ns>: 8 9 ?* 0 1;
|
||||
< +10ns>: 8 9 ?* 0 1;
|
||||
< +10ns>: 8 a ?* 0 1;
|
||||
< +10ns>: 8 a ?* 0 1;
|
||||
< +10ns>: 8 b ?* 0 1;
|
||||
< +10ns>: 8 b ?* 0 1;
|
||||
< +10ns>: 8 c ?* 0 1;
|
||||
< +10ns>: 8 c ?* 0 1;
|
||||
< +10ns>: 8 d ?* 0 1;
|
||||
< +10ns>: 8 d ?* 0 1;
|
||||
< +10ns>: 8 e ?* 0 1;
|
||||
< +10ns>: 8 e ?* 0 1;
|
||||
< +10ns>: 8 f ?* 0 1;
|
||||
< +10ns>: 8 f ?* 0 1;
|
||||
< +10ns>: 9 0 ?* 0 1;
|
||||
< +10ns>: 9 0 ?* 0 1;
|
||||
< +10ns>: 9 1 ?* 0 1;
|
||||
< +10ns>: 9 1 ?* 0 1;
|
||||
< +10ns>: 9 2 ?* 0 1;
|
||||
< +10ns>: 9 2 ?* 0 1;
|
||||
< +10ns>: 9 3 ?* 0 1;
|
||||
< +10ns>: 9 3 ?* 0 1;
|
||||
< +10ns>: 9 4 ?* 0 1;
|
||||
< +10ns>: 9 4 ?* 0 1;
|
||||
< +10ns>: 9 5 ?* 0 1;
|
||||
< +10ns>: 9 5 ?* 0 1;
|
||||
< +10ns>: 9 6 ?* 0 1;
|
||||
< +10ns>: 9 6 ?* 0 1;
|
||||
< +10ns>: 9 7 ?* 0 1;
|
||||
< +10ns>: 9 7 ?* 0 1;
|
||||
< +10ns>: 9 8 ?* 0 1;
|
||||
< +10ns>: 9 8 ?* 0 1;
|
||||
< +10ns>: 9 9 ?* 0 1;
|
||||
< +10ns>: 9 9 ?* 0 1;
|
||||
< +10ns>: 9 a ?* 0 1;
|
||||
< +10ns>: 9 a ?* 0 1;
|
||||
< +10ns>: 9 b ?* 0 1;
|
||||
< +10ns>: 9 b ?* 0 1;
|
||||
< +10ns>: 9 c ?* 0 1;
|
||||
< +10ns>: 9 c ?* 0 1;
|
||||
< +10ns>: 9 d ?* 0 1;
|
||||
< +10ns>: 9 d ?* 0 1;
|
||||
< +10ns>: 9 e ?* 0 1;
|
||||
< +10ns>: 9 e ?* 0 1;
|
||||
< +10ns>: 9 f ?* 0 1;
|
||||
< +10ns>: 9 f ?* 0 1;
|
||||
< +10ns>: a 0 ?* 0 1;
|
||||
< +10ns>: a 0 ?* 0 1;
|
||||
< +10ns>: a 1 ?* 0 1;
|
||||
< +10ns>: a 1 ?* 0 1;
|
||||
< +10ns>: a 2 ?* 0 1;
|
||||
< +10ns>: a 2 ?* 0 1;
|
||||
< +10ns>: a 3 ?* 0 1;
|
||||
< +10ns>: a 3 ?* 0 1;
|
||||
< +10ns>: a 4 ?* 0 1;
|
||||
< +10ns>: a 4 ?* 0 1;
|
||||
< +10ns>: a 5 ?* 0 1;
|
||||
< +10ns>: a 5 ?* 0 1;
|
||||
< +10ns>: a 6 ?* 0 1;
|
||||
< +10ns>: a 6 ?* 0 1;
|
||||
< +10ns>: a 7 ?* 0 1;
|
||||
< +10ns>: a 7 ?* 0 1;
|
||||
< +10ns>: a 8 ?* 0 1;
|
||||
< +10ns>: a 8 ?* 0 1;
|
||||
< +10ns>: a 9 ?* 0 1;
|
||||
< +10ns>: a 9 ?* 0 1;
|
||||
< +10ns>: a a ?* 0 1;
|
||||
< +10ns>: a a ?* 0 1;
|
||||
< +10ns>: a b ?* 0 1;
|
||||
< +10ns>: a b ?* 0 1;
|
||||
< +10ns>: a c ?* 0 1;
|
||||
< +10ns>: a c ?* 0 1;
|
||||
< +10ns>: a d ?* 0 1;
|
||||
< +10ns>: a d ?* 0 1;
|
||||
< +10ns>: a e ?* 0 1;
|
||||
< +10ns>: a e ?* 0 1;
|
||||
< +10ns>: a f ?* 0 1;
|
||||
< +10ns>: a f ?* 0 1;
|
||||
< +10ns>: b 0 ?* 0 1;
|
||||
< +10ns>: b 0 ?* 0 1;
|
||||
< +10ns>: b 1 ?* 0 1;
|
||||
< +10ns>: b 1 ?* 0 1;
|
||||
< +10ns>: b 2 ?* 0 1;
|
||||
< +10ns>: b 2 ?* 0 1;
|
||||
< +10ns>: b 3 ?* 0 1;
|
||||
< +10ns>: b 3 ?* 0 1;
|
||||
< +10ns>: b 4 ?* 0 1;
|
||||
< +10ns>: b 4 ?* 0 1;
|
||||
< +10ns>: b 5 ?* 0 1;
|
||||
< +10ns>: b 5 ?* 0 1;
|
||||
< +10ns>: b 6 ?* 0 1;
|
||||
< +10ns>: b 6 ?* 0 1;
|
||||
< +10ns>: b 7 ?* 0 1;
|
||||
< +10ns>: b 7 ?* 0 1;
|
||||
< +10ns>: b 8 ?* 0 1;
|
||||
< +10ns>: b 8 ?* 0 1;
|
||||
< +10ns>: b 9 ?* 0 1;
|
||||
< +10ns>: b 9 ?* 0 1;
|
||||
< +10ns>: b a ?* 0 1;
|
||||
< +10ns>: b a ?* 0 1;
|
||||
< +10ns>: b b ?* 0 1;
|
||||
< +10ns>: b b ?* 0 1;
|
||||
< +10ns>: b c ?* 0 1;
|
||||
< +10ns>: b c ?* 0 1;
|
||||
< +10ns>: b d ?* 0 1;
|
||||
< +10ns>: b d ?* 0 1;
|
||||
< +10ns>: b e ?* 0 1;
|
||||
< +10ns>: b e ?* 0 1;
|
||||
< +10ns>: b f ?* 0 1;
|
||||
< +10ns>: b f ?* 0 1;
|
||||
< +10ns>: c 0 ?* 0 1;
|
||||
< +10ns>: c 0 ?* 0 1;
|
||||
< +10ns>: c 1 ?* 0 1;
|
||||
< +10ns>: c 1 ?* 0 1;
|
||||
< +10ns>: c 2 ?* 0 1;
|
||||
< +10ns>: c 2 ?* 0 1;
|
||||
< +10ns>: c 3 ?* 0 1;
|
||||
< +10ns>: c 3 ?* 0 1;
|
||||
< +10ns>: c 4 ?* 0 1;
|
||||
< +10ns>: c 4 ?* 0 1;
|
||||
< +10ns>: c 5 ?* 0 1;
|
||||
< +10ns>: c 5 ?* 0 1;
|
||||
< +10ns>: c 6 ?* 0 1;
|
||||
< +10ns>: c 6 ?* 0 1;
|
||||
< +10ns>: c 7 ?* 0 1;
|
||||
< +10ns>: c 7 ?* 0 1;
|
||||
< +10ns>: c 8 ?* 0 1;
|
||||
< +10ns>: c 8 ?* 0 1;
|
||||
< +10ns>: c 9 ?* 0 1;
|
||||
< +10ns>: c 9 ?* 0 1;
|
||||
< +10ns>: c a ?* 0 1;
|
||||
< +10ns>: c a ?* 0 1;
|
||||
< +10ns>: c b ?* 0 1;
|
||||
< +10ns>: c b ?* 0 1;
|
||||
< +10ns>: c c ?* 0 1;
|
||||
< +10ns>: c c ?* 0 1;
|
||||
< +10ns>: c d ?* 0 1;
|
||||
< +10ns>: c d ?* 0 1;
|
||||
< +10ns>: c e ?* 0 1;
|
||||
< +10ns>: c e ?* 0 1;
|
||||
< +10ns>: c f ?* 0 1;
|
||||
< +10ns>: c f ?* 0 1;
|
||||
< +10ns>: d 0 ?* 0 1;
|
||||
< +10ns>: d 0 ?* 0 1;
|
||||
< +10ns>: d 1 ?* 0 1;
|
||||
< +10ns>: d 1 ?* 0 1;
|
||||
< +10ns>: d 2 ?* 0 1;
|
||||
< +10ns>: d 2 ?* 0 1;
|
||||
< +10ns>: d 3 ?* 0 1;
|
||||
< +10ns>: d 3 ?* 0 1;
|
||||
< +10ns>: d 4 ?* 0 1;
|
||||
< +10ns>: d 4 ?* 0 1;
|
||||
< +10ns>: d 5 ?* 0 1;
|
||||
< +10ns>: d 5 ?* 0 1;
|
||||
< +10ns>: d 6 ?* 0 1;
|
||||
< +10ns>: d 6 ?* 0 1;
|
||||
< +10ns>: d 7 ?* 0 1;
|
||||
< +10ns>: d 7 ?* 0 1;
|
||||
< +10ns>: d 8 ?* 0 1;
|
||||
< +10ns>: d 8 ?* 0 1;
|
||||
< +10ns>: d 9 ?* 0 1;
|
||||
< +10ns>: d 9 ?* 0 1;
|
||||
< +10ns>: d a ?* 0 1;
|
||||
< +10ns>: d a ?* 0 1;
|
||||
< +10ns>: d b ?* 0 1;
|
||||
< +10ns>: d b ?* 0 1;
|
||||
< +10ns>: d c ?* 0 1;
|
||||
< +10ns>: d c ?* 0 1;
|
||||
< +10ns>: d d ?* 0 1;
|
||||
< +10ns>: d d ?* 0 1;
|
||||
< +10ns>: d e ?* 0 1;
|
||||
< +10ns>: d e ?* 0 1;
|
||||
< +10ns>: d f ?* 0 1;
|
||||
< +10ns>: d f ?* 0 1;
|
||||
< +10ns>: e 0 ?* 0 1;
|
||||
< +10ns>: e 0 ?* 0 1;
|
||||
< +10ns>: e 1 ?* 0 1;
|
||||
< +10ns>: e 1 ?* 0 1;
|
||||
< +10ns>: e 2 ?* 0 1;
|
||||
< +10ns>: e 2 ?* 0 1;
|
||||
< +10ns>: e 3 ?* 0 1;
|
||||
< +10ns>: e 3 ?* 0 1;
|
||||
< +10ns>: e 4 ?* 0 1;
|
||||
< +10ns>: e 4 ?* 0 1;
|
||||
< +10ns>: e 5 ?* 0 1;
|
||||
< +10ns>: e 5 ?* 0 1;
|
||||
< +10ns>: e 6 ?* 0 1;
|
||||
< +10ns>: e 6 ?* 0 1;
|
||||
< +10ns>: e 7 ?* 0 1;
|
||||
< +10ns>: e 7 ?* 0 1;
|
||||
< +10ns>: e 8 ?* 0 1;
|
||||
< +10ns>: e 8 ?* 0 1;
|
||||
< +10ns>: e 9 ?* 0 1;
|
||||
< +10ns>: e 9 ?* 0 1;
|
||||
< +10ns>: e a ?* 0 1;
|
||||
< +10ns>: e a ?* 0 1;
|
||||
< +10ns>: e b ?* 0 1;
|
||||
< +10ns>: e b ?* 0 1;
|
||||
< +10ns>: e c ?* 0 1;
|
||||
< +10ns>: e c ?* 0 1;
|
||||
< +10ns>: e d ?* 0 1;
|
||||
< +10ns>: e d ?* 0 1;
|
||||
< +10ns>: e e ?* 0 1;
|
||||
< +10ns>: e e ?* 0 1;
|
||||
< +10ns>: e f ?* 0 1;
|
||||
< +10ns>: e f ?* 0 1;
|
||||
< +10ns>: f 0 ?* 0 1;
|
||||
< +10ns>: f 0 ?* 0 1;
|
||||
< +10ns>: f 1 ?* 0 1;
|
||||
< +10ns>: f 1 ?* 0 1;
|
||||
< +10ns>: f 2 ?* 0 1;
|
||||
< +10ns>: f 2 ?* 0 1;
|
||||
< +10ns>: f 3 ?* 0 1;
|
||||
< +10ns>: f 3 ?* 0 1;
|
||||
< +10ns>: f 4 ?* 0 1;
|
||||
< +10ns>: f 4 ?* 0 1;
|
||||
< +10ns>: f 5 ?* 0 1;
|
||||
< +10ns>: f 5 ?* 0 1;
|
||||
< +10ns>: f 6 ?* 0 1;
|
||||
< +10ns>: f 6 ?* 0 1;
|
||||
< +10ns>: f 7 ?* 0 1;
|
||||
< +10ns>: f 7 ?* 0 1;
|
||||
< +10ns>: f 8 ?* 0 1;
|
||||
< +10ns>: f 8 ?* 0 1;
|
||||
< +10ns>: f 9 ?* 0 1;
|
||||
< +10ns>: f 9 ?* 0 1;
|
||||
< +10ns>: f a ?* 0 1;
|
||||
< +10ns>: f a ?* 0 1;
|
||||
< +10ns>: f b ?* 0 1;
|
||||
< +10ns>: f b ?* 0 1;
|
||||
< +10ns>: f c ?* 0 1;
|
||||
< +10ns>: f c ?* 0 1;
|
||||
< +10ns>: f d ?* 0 1;
|
||||
< +10ns>: f d ?* 0 1;
|
||||
< +10ns>: f e ?* 0 1;
|
||||
< +10ns>: f e ?* 0 1;
|
||||
< +10ns>: f f ?* 0 1;
|
||||
< +10ns>: f f ?* 0 1;
|
||||
|
||||
end;
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_arith.ALL;
|
||||
use IEEE.STD_LOGIC_unsigned.ALL;
|
||||
|
||||
|
||||
entity Adder4 is
|
||||
|
||||
port ( A : in Std_Logic_Vector(3 downto 0) ;
|
||||
B : in Std_Logic_Vector(3 downto 0) ;
|
||||
RESULT : out Std_Logic_Vector(3 downto 0) );
|
||||
|
||||
end Adder4;
|
||||
|
||||
|
||||
architecture DataFlow OF Adder4 is
|
||||
begin
|
||||
|
||||
RESULT <= std_logic_vector( unsigned(A) + unsigned(B) );
|
||||
|
||||
end DataFlow;
|
||||
|
|
@ -0,0 +1,417 @@
|
|||
#
|
||||
# Virtual 0.35 techno with 8 metal layers
|
||||
#
|
||||
DEFINE PHYSICAL_GRID 0.025
|
||||
|
||||
DEFINE LAMBDA 0.300
|
||||
|
||||
TABLE MBK_TO_RDS_SEGMENT
|
||||
|
||||
NWELL RDS_NWELL VW 0.950 1.900 0.000 ALL
|
||||
PWELL RDS_PWELL VW 0.950 1.900 0.000 ALL
|
||||
NDIF RDS_NDIF VW 0.100 -0.100 0.000 EXT\
|
||||
RDS_ACTIV VW 0.100 -0.100 0.000 DRC\
|
||||
RDS_NIMP VW 0.400 0.500 0.000 DRC\
|
||||
RDS_PWELL VW 1.200 2.100 0.000 DRC
|
||||
PDIF RDS_PDIF VW 0.100 -0.100 0.000 EXT\
|
||||
RDS_ACTIV VW 0.100 -0.100 0.000 DRC\
|
||||
RDS_PIMP VW 0.400 0.500 0.000 DRC\
|
||||
RDS_NWELL VW 1.200 2.100 0.000 DRC
|
||||
NTIE RDS_NTIE VW 0.100 -0.100 0.000 EXT\
|
||||
RDS_ACTIV VW 0.100 -0.100 0.000 DRC\
|
||||
RDS_NIMP VW 0.400 0.500 0.000 EXT\
|
||||
RDS_NWELL VW 1.200 2.100 0.000 DRC
|
||||
PTIE RDS_PTIE VW 0.100 -0.100 0.000 EXT\
|
||||
RDS_ACTIV VW 0.100 -0.100 0.000 DRC\
|
||||
RDS_PIMP VW 0.400 0.500 0.000 DRC\
|
||||
RDS_PWELL VW 1.200 2.100 0.000 DRC
|
||||
NTRANS RDS_POLY VW 0.000 0.050 0.000 ALL\
|
||||
RDS_NDIF LCW -0.500 0.750 0.025 EXT\
|
||||
RDS_NDIF RCW -0.500 0.750 0.025 EXT\
|
||||
RDS_ACTIV VW -0.500 1.350 0.000 DRC\
|
||||
RDS_NIMP VW -0.200 1.950 0.000 DRC\
|
||||
RDS_PWELL VW 0.600 3.550 0.000 ALL
|
||||
PTRANS RDS_POLY VW 0.000 0.050 0.000 ALL\
|
||||
RDS_PDIF LCW -0.500 0.750 0.025 EXT\
|
||||
RDS_PDIF RCW -0.500 0.750 0.025 EXT\
|
||||
RDS_ACTIV VW -0.500 1.350 0.000 DRC\
|
||||
RDS_PIMP VW -0.200 1.950 0.000 DRC\
|
||||
RDS_NWELL VW 0.600 3.550 0.000 ALL
|
||||
POLY RDS_POLY VW 0.175 0.050 0.000 ALL
|
||||
ALU1 RDS_ALU1 VW 0.300 0.300 0.000 ALL
|
||||
ALU2 RDS_ALU2 VW 0.350 0.100 0.000 ALL
|
||||
ALU3 RDS_ALU3 VW 0.450 0.000 0.000 ALL
|
||||
ALU4 RDS_ALU4 VW 0.450 0.000 0.000 ALL
|
||||
ALU5 RDS_ALU5 VW 0.450 0.000 0.000 ALL
|
||||
ALU6 RDS_ALU6 VW 0.450 0.000 0.000 ALL
|
||||
ALU7 RDS_ALU7 VW 0.450 0.000 0.000 ALL
|
||||
ALU8 RDS_ALU8 VW 0.450 0.000 0.000 ALL
|
||||
CALU1 RDS_ALU1 VW 0.300 0.300 0.000 ALL
|
||||
CALU2 RDS_ALU2 VW 0.350 0.100 0.000 ALL
|
||||
CALU3 RDS_ALU3 VW 0.450 0.000 0.000 ALL
|
||||
CALU4 RDS_ALU4 VW 0.450 0.000 0.000 ALL
|
||||
CALU5 RDS_ALU5 VW 0.450 0.000 0.000 ALL
|
||||
CALU6 RDS_ALU6 VW 0.450 0.000 0.000 ALL
|
||||
CALU7 RDS_ALU7 VW 0.450 0.000 0.000 ALL
|
||||
CALU8 RDS_ALU8 VW 0.450 0.000 0.000 ALL
|
||||
END
|
||||
TABLE MBK_TO_RDS_CONNECTOR
|
||||
POLY RDS_POLY 0.175 0.050
|
||||
ALU1 RDS_ALU1 0.300 0.300
|
||||
ALU2 RDS_ALU2 0.350 0.100
|
||||
ALU3 RDS_ALU3 0.450 0.000
|
||||
ALU4 RDS_ALU4 0.450 0.000
|
||||
ALU5 RDS_ALU5 0.450 0.000
|
||||
ALU6 RDS_ALU6 0.450 0.000
|
||||
ALU7 RDS_ALU7 0.450 0.000
|
||||
ALU8 RDS_ALU8 0.450 0.000
|
||||
END
|
||||
TABLE MBK_TO_RDS_REFERENCE
|
||||
REF_REF RDS_REF 0.600
|
||||
REF_CON RDS_REF 0.600
|
||||
END
|
||||
TABLE MBK_TO_RDS_VIA
|
||||
CONT_BODY_N \
|
||||
RDS_ALU1 0.900 ALL\
|
||||
RDS_CONT 0.400 ALL\
|
||||
RDS_ACTIV 0.800 DRC\
|
||||
RDS_NIMP 1.400 DRC\
|
||||
RDS_NWELL 3.000 DRC\
|
||||
RDS_NTIE 0.800 EXT
|
||||
CONT_BODY_P \
|
||||
RDS_ALU1 0.900 ALL\
|
||||
RDS_CONT 0.400 ALL\
|
||||
RDS_ACTIV 0.800 DRC\
|
||||
RDS_PIMP 1.400 DRC\
|
||||
RDS_PWELL 3.000 DRC\
|
||||
RDS_PTIE 0.800 EXT
|
||||
CONT_DIF_N \
|
||||
RDS_ALU1 0.900 ALL\
|
||||
RDS_CONT 0.400 ALL\
|
||||
RDS_ACTIV 0.800 DRC\
|
||||
RDS_NIMP 1.400 DRC\
|
||||
RDS_PWELL 3.000 DRC\
|
||||
RDS_NDIF 0.800 EXT
|
||||
CONT_DIF_P \
|
||||
RDS_ALU1 0.900 ALL\
|
||||
RDS_CONT 0.400 ALL\
|
||||
RDS_ACTIV 0.800 DRC\
|
||||
RDS_PIMP 1.400 DRC\
|
||||
RDS_NWELL 3.000 DRC\
|
||||
RDS_PDIF 0.800 EXT
|
||||
CONT_POLY \
|
||||
RDS_ALU1 0.900 ALL\
|
||||
RDS_CONT 0.400 ALL\
|
||||
RDS_POLY 0.950 ALL
|
||||
CONT_VIA \
|
||||
RDS_ALU1 0.900 ALL\
|
||||
RDS_VIA1 0.400 ALL\
|
||||
RDS_ALU2 1.000 ALL
|
||||
CONT_VIA2 \
|
||||
RDS_ALU2 1.000 ALL\
|
||||
RDS_VIA2 0.400 ALL\
|
||||
RDS_ALU3 0.900 ALL
|
||||
CONT_VIA3 \
|
||||
RDS_ALU3 0.900 ALL\
|
||||
RDS_VIA3 0.400 ALL\
|
||||
RDS_ALU4 0.900 ALL
|
||||
CONT_VIA4 \
|
||||
RDS_ALU4 0.900 ALL\
|
||||
RDS_VIA4 0.400 ALL\
|
||||
RDS_ALU5 0.900 ALL
|
||||
CONT_VIA5 \
|
||||
RDS_ALU5 0.900 ALL\
|
||||
RDS_VIA5 0.400 ALL\
|
||||
RDS_ALU6 0.900 ALL
|
||||
CONT_VIA6 \
|
||||
RDS_ALU6 0.900 ALL\
|
||||
RDS_VIA6 0.400 ALL\
|
||||
RDS_ALU7 0.900 ALL
|
||||
CONT_VIA7 \
|
||||
RDS_ALU7 0.900 ALL\
|
||||
RDS_VIA7 0.400 ALL\
|
||||
RDS_ALU8 0.900 ALL
|
||||
C_X_N \
|
||||
RDS_POLY 0.350 ALL\
|
||||
RDS_ACTIV 1.650 DRC\
|
||||
RDS_NIMP 2.250 DRC\
|
||||
RDS_PWELL 3.850 DRC\
|
||||
RDS_NDIF 1.650 EXT
|
||||
C_X_P \
|
||||
RDS_POLY 0.350 ALL\
|
||||
RDS_ACTIV 1.650 DRC\
|
||||
RDS_PIMP 2.250 DRC\
|
||||
RDS_NWELL 3.850 DRC\
|
||||
RDS_PDIF 1.650 EXT
|
||||
END
|
||||
TABLE CIF_LAYER
|
||||
RDS_NWELL NWEL
|
||||
RDS_POLY POLY
|
||||
RDS_CONT CONTACT
|
||||
RDS_ALU1 METAL1
|
||||
RDS_TALU1 ?
|
||||
RDS_VIA1 VIA1
|
||||
RDS_ALU2 METAL2
|
||||
RDS_TALU2 ?
|
||||
RDS_ACTIV ACTIVE
|
||||
RDS_NIMP NPLUS
|
||||
RDS_PIMP PPLUS
|
||||
RDS_CPAS PAD
|
||||
RDS_ALU3 METAL3
|
||||
RDS_VIA2 VIA2
|
||||
RDS_VIA3 VIA3
|
||||
RDS_VIA4 VIA4
|
||||
RDS_VIA5 VIA5
|
||||
RDS_VIA6 VIA6
|
||||
RDS_VIA7 VIA7
|
||||
RDS_ALU4 METAL4
|
||||
RDS_ALU5 METAL5
|
||||
RDS_ALU6 METAL6
|
||||
RDS_ALU7 METAL7
|
||||
RDS_ALU8 METAL8
|
||||
END
|
||||
TABLE GDS_LAYER
|
||||
RDS_NWELL 1
|
||||
RDS_POLY 13
|
||||
RDS_CONT 19
|
||||
RDS_ALU1 23
|
||||
RDS_VIA1 25
|
||||
RDS_ALU2 27
|
||||
RDS_ACTIV 2
|
||||
RDS_NIMP 16
|
||||
RDS_PIMP 17
|
||||
RDS_CPAS 31
|
||||
RDS_ALU3 34
|
||||
RDS_VIA2 32
|
||||
RDS_VIA3 35
|
||||
RDS_VIA4 37
|
||||
RDS_VIA5 39
|
||||
RDS_VIA6 41
|
||||
RDS_VIA7 43
|
||||
RDS_ALU4 36
|
||||
RDS_ALU5 38
|
||||
RDS_ALU5 40
|
||||
RDS_ALU6 42
|
||||
RDS_ALU7 44
|
||||
RDS_ALU8 46
|
||||
END
|
||||
TABLE S2R_OVERSIZE_DENOTCH
|
||||
RDS_NWELL 0.700
|
||||
RDS_PWELL 0.000
|
||||
RDS_POLY 0.250
|
||||
RDS_ALU1 -0.025
|
||||
RDS_ALU2 -0.025
|
||||
RDS_ACTIV 0.325
|
||||
RDS_NIMP 0.250
|
||||
RDS_PIMP 0.250
|
||||
RDS_ALU3 -0.025
|
||||
RDS_ALU4 -0.025
|
||||
RDS_ALU5 -0.025
|
||||
RDS_ALU6 -0.025
|
||||
RDS_ALU7 -0.025
|
||||
RDS_ALU8 -0.025
|
||||
END
|
||||
TABLE S2R_BLOC_RING_WIDTH
|
||||
RDS_NWELL 1.400
|
||||
RDS_PWELL 0.000
|
||||
RDS_POLY 0.550
|
||||
RDS_ALU1 0.000
|
||||
RDS_ALU2 0.000
|
||||
RDS_ACTIV 0.700
|
||||
RDS_NIMP 0.500
|
||||
RDS_PIMP 0.500
|
||||
RDS_ALU3 0.000
|
||||
RDS_ALU4 0.000
|
||||
RDS_ALU5 0.000
|
||||
RDS_ALU6 0.000
|
||||
RDS_ALU7 0.000
|
||||
RDS_ALU8 0.000
|
||||
END
|
||||
TABLE S2R_MINIMUM_LAYER_WIDTH
|
||||
RDS_NWELL 1.700
|
||||
RDS_PWELL 1.700
|
||||
RDS_POLY 0.350
|
||||
RDS_ALU1 0.600
|
||||
RDS_ALU2 0.700
|
||||
RDS_ACTIV 0.500
|
||||
RDS_NIMP 0.500
|
||||
RDS_PIMP 0.500
|
||||
RDS_ALU3 0.900
|
||||
RDS_ALU3 0.900
|
||||
RDS_ALU4 0.900
|
||||
RDS_ALU5 0.900
|
||||
RDS_ALU6 0.900
|
||||
RDS_ALU7 0.900
|
||||
RDS_ALU8 0.900
|
||||
END
|
||||
TABLE S2R_POST_TREAT
|
||||
RDS_NWELL TREAT NULL
|
||||
RDS_PWELL TREAT NULL
|
||||
RDS_POLY TREAT NULL
|
||||
RDS_CONT NOTREAT NULL
|
||||
RDS_ALU1 TREAT NULL
|
||||
RDS_VIA1 NOTREAT NULL
|
||||
RDS_ALU2 TREAT NULL
|
||||
RDS_ACTIV TREAT NULL
|
||||
RDS_NIMP TREAT RDS_PIMP
|
||||
RDS_PIMP TREAT RDS_NIMP
|
||||
RDS_ABOX NOTREAT NULL
|
||||
RDS_VIA2 NOTREAT NULL
|
||||
RDS_ALU3 TREAT NULL
|
||||
RDS_VIA3 NOTREAT NULL
|
||||
RDS_VIA4 NOTREAT NULL
|
||||
RDS_VIA5 NOTREAT NULL
|
||||
RDS_VIA6 NOTREAT NULL
|
||||
RDS_VIA7 NOTREAT NULL
|
||||
RDS_ALU4 TREAT NULL
|
||||
RDS_ALU5 TREAT NULL
|
||||
RDS_ALU6 TREAT NULL
|
||||
RDS_ALU7 TREAT NULL
|
||||
RDS_ALU8 TREAT NULL
|
||||
END
|
||||
TABLE LYNX_TRANSISTOR
|
||||
NTRANS NTRANS C_X_N RDS_POLY RDS_NDIF RDS_ACTIV RDS_PWELL
|
||||
PTRANS PTRANS C_X_P RDS_POLY RDS_PDIF RDS_ACTIV RDS_NWELL
|
||||
END
|
||||
TABLE LYNX_DIFFUSION
|
||||
RDS_PDIF RDS_ACTIV 1 RDS_PIMP 1 RDS_NWELL 1
|
||||
RDS_PTIE RDS_ACTIV 1 RDS_PIMP 1 RDS_PWELL 1
|
||||
RDS_NDIF RDS_ACTIV 1 RDS_NIMP 1 RDS_PWELL 1
|
||||
RDS_NTIE RDS_ACTIV 1 RDS_NIMP 1 RDS_NWELL 1
|
||||
END
|
||||
TABLE LYNX_RESISTOR
|
||||
RDS_POLY 6
|
||||
RDS_ALU1 0.087
|
||||
RDS_ALU2 0.066
|
||||
RDS_ALU3 0.066
|
||||
RDS_ALU3 0.066
|
||||
RDS_ALU4 0.066
|
||||
RDS_ALU5 0.066
|
||||
RDS_ALU6 0.066
|
||||
RDS_ALU7 0.066
|
||||
RDS_ALU8 0.066
|
||||
RDS_CONT 12
|
||||
RDS_VIA1 4
|
||||
RDS_VIA2 4
|
||||
RDS_VIA3 4
|
||||
RDS_VIA4 4
|
||||
RDS_VIA5 4
|
||||
RDS_VIA6 4
|
||||
RDS_VIA7 4
|
||||
END
|
||||
TABLE LYNX_GRAPH
|
||||
|
||||
##---------------------------
|
||||
#
|
||||
# Modifie par L.Jacomme (Pb Bulk/Alim avec Lynx)
|
||||
# 23.11.99
|
||||
#
|
||||
# RDS_NWELL RDS_NTIE RDS_NWELL
|
||||
# RDS_PWELL RDS_PTIE RDS_PWELL
|
||||
# RDS_NTIE RDS_CONT RDS_NTIE RDS_NWELL
|
||||
# RDS_PTIE RDS_CONT RDS_PTIE RDS_PWELL
|
||||
# RDS_NDIF RDS_CONT RDS_NDIF
|
||||
# RDS_PDIF RDS_CONT RDS_PDIF
|
||||
|
||||
RDS_NDIF RDS_CONT RDS_NDIF
|
||||
RDS_PDIF RDS_CONT RDS_PDIF
|
||||
RDS_NTIE RDS_CONT RDS_NTIE
|
||||
RDS_PTIE RDS_CONT RDS_PTIE
|
||||
|
||||
RDS_POLY RDS_CONT RDS_POLY
|
||||
RDS_CONT RDS_PDIF RDS_NDIF RDS_POLY RDS_PTIE RDS_NTIE RDS_ALU1 RDS_CONT
|
||||
RDS_ALU1 RDS_CONT RDS_VIA1 RDS_REF RDS_ALU1
|
||||
RDS_REF RDS_CONT RDS_VIA1 RDS_ALU1 RDS_REF
|
||||
RDS_VIA1 RDS_ALU1 RDS_ALU2 RDS_VIA1
|
||||
RDS_ALU2 RDS_VIA1 RDS_VIA2 RDS_ALU2
|
||||
RDS_VIA2 RDS_ALU2 RDS_ALU3 RDS_VIA2
|
||||
RDS_ALU3 RDS_VIA2 RDS_VIA3 RDS_ALU3
|
||||
RDS_VIA3 RDS_ALU3 RDS_ALU4 RDS_VIA3
|
||||
RDS_ALU4 RDS_VIA3 RDS_VIA4 RDS_ALU4
|
||||
RDS_VIA4 RDS_ALU4 RDS_ALU5 RDS_VIA4
|
||||
RDS_ALU5 RDS_VIA4 RDS_VIA5 RDS_ALU5
|
||||
RDS_VIA5 RDS_ALU5 RDS_ALU6 RDS_VIA5
|
||||
RDS_ALU6 RDS_VIA5 RDS_VIA6 RDS_ALU6
|
||||
RDS_VIA6 RDS_ALU6 RDS_ALU7 RDS_VIA6
|
||||
RDS_ALU7 RDS_VIA6 RDS_VIA7 RDS_ALU7
|
||||
RDS_VIA7 RDS_ALU7 RDS_ALU8 RDS_VIA7
|
||||
RDS_ALU8 RDS_VIA7 RDS_ALU8
|
||||
END
|
||||
TABLE LYNX_CAPA
|
||||
RDS_POLY 0.000101 9.8e-05
|
||||
RDS_ALU1 2.65e-05 8.6e-05
|
||||
RDS_ALU2 1.3e-05 7.6e-05
|
||||
RDS_ALU3 8.4e-06 6.8e-05
|
||||
RDS_ALU4 6.2e-06 6.34e-05
|
||||
RDS_ALU5 6.2e-06 6.34e-05
|
||||
RDS_ALU6 6.2e-06 6.34e-05
|
||||
RDS_ALU7 6.2e-06 6.34e-05
|
||||
RDS_ALU8 6.2e-06 6.34e-05
|
||||
END
|
||||
##-------------------------------------------------------------------
|
||||
# TABLE LYNX_BULK_IMPLICIT :
|
||||
#
|
||||
# RDS layer Bulk type
|
||||
# name EXPLICIT/IMPLICIT
|
||||
##-------------------------------------------------------------------
|
||||
|
||||
TABLE LYNX_BULK_IMPLICIT
|
||||
|
||||
##---------------------------
|
||||
#
|
||||
# Modifie par L.Jacomme (Pb Bulk/Alim avec Lynx)
|
||||
# 23.11.99
|
||||
#
|
||||
# NWELL EXPLICIT
|
||||
# PWELL IMPLICIT
|
||||
|
||||
END
|
||||
|
||||
##-------------------------------------------------------------------
|
||||
# TABLE MBK_TO_RDS_BIGVIA_HOLE :
|
||||
#
|
||||
# MBK via RDS Hole
|
||||
# name name side step mode
|
||||
##-------------------------------------------------------------------
|
||||
|
||||
TABLE MBK_TO_RDS_BIGVIA_HOLE
|
||||
|
||||
CONT_VIA RDS_VIA1 .4 1.1 ALL
|
||||
CONT_VIA2 RDS_VIA2 .4 1.1 ALL
|
||||
|
||||
END
|
||||
|
||||
##-------------------------------------------------------------------
|
||||
# TABLE MBK_TO_RDS_BIGVIA_METAL :
|
||||
#
|
||||
# MBK via RDS layer 1 ...
|
||||
# name name delta-width overlap mode
|
||||
##-------------------------------------------------------------------
|
||||
|
||||
TABLE MBK_TO_RDS_BIGVIA_METAL
|
||||
|
||||
CONT_VIA RDS_ALU1 .3 .0 ALL RDS_ALU2 .1 .0 ALL
|
||||
CONT_VIA2 RDS_ALU2 .1 .0 ALL RDS_ALU3 .0 .0 ALL
|
||||
|
||||
END
|
||||
|
||||
##-------------------------------------------------------------------
|
||||
# TABLE MBK_TO_RDS_TURNVIA :
|
||||
#
|
||||
# MBK via RDS layer 1 ...
|
||||
# name name delta-width overlap mode
|
||||
##-------------------------------------------------------------------
|
||||
|
||||
TABLE MBK_TO_RDS_TURNVIA
|
||||
|
||||
CONT_TURN1 RDS_ALU1 .3 ALL
|
||||
CONT_TURN2 RDS_ALU2 .1 ALL
|
||||
CONT_TURN3 RDS_ALU3 .0 ALL
|
||||
CONT_TURN3 RDS_ALU4 .0 ALL
|
||||
CONT_TURN3 RDS_ALU5 .0 ALL
|
||||
CONT_TURN3 RDS_ALU6 .0 ALL
|
||||
CONT_TURN3 RDS_ALU7 .0 ALL
|
||||
CONT_TURN3 RDS_ALU8 .0 ALL
|
||||
|
||||
END
|
||||
|
||||
|
|
@ -0,0 +1,989 @@
|
|||
# Modified version of the cmos.rds file
|
||||
#=====================================================================
|
||||
#
|
||||
# ALLIANCE VLSI CAD
|
||||
# (R)eal (D)ata (S)tructure parameter file
|
||||
# (c) copyright 1992 Laboratory UPMC/MASI/CAO-VLSI
|
||||
# all rights reserved
|
||||
# e-mail : cao-vlsi@masi.ibp.fr
|
||||
#
|
||||
# file : cmos.rds
|
||||
# version : 12
|
||||
# last modif : Apr 4, 2002
|
||||
#
|
||||
##-------------------------------------------------------------------
|
||||
# Symbolic to micron on a 'one lambda equals one micron' basis
|
||||
##-------------------------------------------------------------------
|
||||
# Refer to the documentation for more precise information.
|
||||
#=====================================================================
|
||||
# 01/11/09 ALU5/6 pitch 10
|
||||
#
|
||||
# 99/11/3 ALU5/6 rules
|
||||
# . theses rules are preliminary rules, we hope that they wil change
|
||||
# in future. For now, ALU5/6 are dedicated to supplies an clock.
|
||||
#
|
||||
# 99/3/22 new symbolics rules
|
||||
# . ALU1 width remains 1, ALU2/3/4 is 2
|
||||
# . ALU1/2/3/4 distance (edge to edge) is now 3 for all
|
||||
# . GATE to GATE distance is 3 but POLY wire to POLY wire remains 2
|
||||
# . All via stacking are allowed
|
||||
#
|
||||
# 98/12/1 drc rules were updated
|
||||
# distance VIA to POLY or gate is one rather 2
|
||||
# VIA2 and ALU3 appeared
|
||||
# . ALU3 width is 3
|
||||
# . ALU2/VIA2/ALU3 is resp. 3/1/3
|
||||
# . ALU3 edge distance is 2
|
||||
# . stacked VIA/VIA2 is allowed
|
||||
# . if they are not stacked they must distant of 2
|
||||
# . CONT/VIA2 is free
|
||||
# note
|
||||
# . stacked CONT/VIA is always not allowed
|
||||
# NWELL is automatically drawn with the DIFN and NTIE layers
|
||||
#=====================================================================
|
||||
|
||||
##-------------------------------------------------------------------
|
||||
# PHYSICAL_GRID :
|
||||
##-------------------------------------------------------------------
|
||||
|
||||
DEFINE PHYSICAL_GRID .5
|
||||
|
||||
##-------------------------------------------------------------------
|
||||
# LAMBDA :
|
||||
##-------------------------------------------------------------------
|
||||
|
||||
DEFINE LAMBDA 1
|
||||
|
||||
##-------------------------------------------------------------------
|
||||
# TABLE MBK_TO_RDS_SEGMENT :
|
||||
#
|
||||
# MBK RDS layer 1 RDS layer 2
|
||||
# name name TRANS DLR DWR OFFSET name TRANS DLR DWR OFFSET ...
|
||||
##-------------------------------------------------------------------
|
||||
|
||||
TABLE MBK_TO_RDS_SEGMENT
|
||||
|
||||
PWELL RDS_PWELL VW 0.0 0.0 0.0 EXT
|
||||
NWELL RDS_NWELL VW 0.0 0.0 0.0 ALL
|
||||
NDIF RDS_NDIF VW 0.5 0.0 0.0 ALL
|
||||
PDIF RDS_PDIF VW 0.5 0.0 0.0 ALL \
|
||||
RDS_NWELL VW 1.0 1.0 0.0 ALL
|
||||
NTIE RDS_NTIE VW 0.5 0.0 0.0 ALL \
|
||||
RDS_NWELL VW 1.0 1.0 0.0 ALL
|
||||
PTIE RDS_PTIE VW 0.5 0.0 0.0 ALL
|
||||
NTRANS RDS_POLY VW 0.0 0.0 0.0 ALL \
|
||||
RDS_NDIF LCW -1.5 2.0 0.0 EXT \
|
||||
RDS_NDIF RCW -1.5 2.0 0.0 EXT \
|
||||
RDS_NDIF VW -1.5 4.0 0.0 DRC \
|
||||
RDS_ACTIV VW -1.5 5.0 0.0 ALL \
|
||||
RDS_PWELL VW -1.5 0.0 0.0 EXT
|
||||
PTRANS RDS_POLY VW 0.0 0.0 0.0 ALL \
|
||||
RDS_PDIF LCW -1.5 2.0 0.0 EXT \
|
||||
RDS_PDIF RCW -1.5 2.0 0.0 EXT \
|
||||
RDS_PDIF VW -1.5 4.0 0.0 DRC \
|
||||
RDS_ACTIV VW -1.5 5.0 0.0 ALL \
|
||||
RDS_NWELL VW -1.0 5.0 0.0 ALL
|
||||
POLY RDS_POLY VW 0.5 0.0 0.0 ALL
|
||||
POLY2 RDS_POLY2 VW 0.5 0.0 0.0 ALL
|
||||
ALU1 RDS_ALU1 VW 0.5 0.0 0.0 ALL
|
||||
ALU2 RDS_ALU2 VW 1.0 0.0 0.0 ALL
|
||||
ALU3 RDS_ALU3 VW 1.0 0.0 0.0 ALL
|
||||
ALU4 RDS_ALU4 VW 1.0 0.0 0.0 ALL
|
||||
ALU5 RDS_ALU5 VW 1.0 0.0 0.0 ALL
|
||||
ALU6 RDS_ALU6 VW 1.0 0.0 0.0 ALL
|
||||
ALU7 RDS_ALU7 VW 1.0 0.0 0.0 ALL
|
||||
ALU8 RDS_ALU8 VW 1.0 0.0 0.0 ALL
|
||||
CALU1 RDS_ALU1 VW 1.0 0.0 0.0 ALL
|
||||
CALU2 RDS_ALU2 VW 1.0 0.0 0.0 ALL
|
||||
CALU3 RDS_ALU3 VW 1.0 0.0 0.0 ALL
|
||||
CALU4 RDS_ALU4 VW 1.0 0.0 0.0 ALL
|
||||
CALU5 RDS_ALU5 VW 1.0 0.0 0.0 ALL
|
||||
CALU6 RDS_ALU6 VW 1.0 0.0 0.0 ALL
|
||||
CALU7 RDS_ALU7 VW 1.0 0.0 0.0 ALL
|
||||
CALU8 RDS_ALU8 VW 1.0 0.0 0.0 ALL
|
||||
TPOLY RDS_TPOLY VW 0.5 0.0 0.0 ALL
|
||||
TALU1 RDS_TALU1 VW 0.5 0.0 0.0 ALL
|
||||
TALU2 RDS_TALU2 VW 1.0 0.0 0.0 ALL
|
||||
TALU3 RDS_TALU3 VW 1.0 0.0 0.0 ALL
|
||||
TALU4 RDS_TALU4 VW 1.0 0.0 0.0 ALL
|
||||
TALU5 RDS_TALU5 VW 1.0 0.0 0.0 ALL
|
||||
TALU6 RDS_TALU6 VW 1.0 0.0 0.0 ALL
|
||||
TALU7 RDS_TALU7 VW 1.0 0.0 0.0 ALL
|
||||
TALU8 RDS_TALU8 VW 1.0 0.0 0.0 ALL
|
||||
|
||||
END
|
||||
|
||||
##-------------------------------------------------------------------
|
||||
# TABLE MBK_TO_RDS_CONNECTOR :
|
||||
#
|
||||
# MBK RDS layer
|
||||
# name name DER DWR
|
||||
##-------------------------------------------------------------------
|
||||
|
||||
TABLE MBK_TO_RDS_CONNECTOR
|
||||
|
||||
POLY RDS_POLY .5 0
|
||||
POLY2 RDS_POLY2 .5 0
|
||||
ALU1 RDS_ALU1 .5 0
|
||||
ALU2 RDS_ALU2 1.0 0
|
||||
ALU3 RDS_ALU3 1.0 0
|
||||
ALU4 RDS_ALU4 1.0 0
|
||||
ALU5 RDS_ALU5 1.0 0
|
||||
ALU6 RDS_ALU6 1.0 0
|
||||
ALU7 RDS_ALU7 1.0 0
|
||||
ALU8 RDS_ALU8 1.0 0
|
||||
|
||||
END
|
||||
|
||||
##-------------------------------------------------------------------
|
||||
# TABLE MBK_TO_RDS_REFERENCE :
|
||||
#
|
||||
# MBK ref RDS layer
|
||||
# name name width
|
||||
##-------------------------------------------------------------------
|
||||
|
||||
TABLE MBK_TO_RDS_REFERENCE
|
||||
|
||||
REF_REF RDS_REF 1
|
||||
REF_CON RDS_VALU1 2 RDS_TVIA1 1 RDS_TALU2 2
|
||||
|
||||
END
|
||||
|
||||
##-------------------------------------------------------------------
|
||||
# TABLE MBK_TO_RDS_VIA1 :
|
||||
#
|
||||
# MBK via RDS layer 1 RDS layer 2 RDS layer 3 RDS layer 4
|
||||
# name name width name width name width name width
|
||||
##-------------------------------------------------------------------
|
||||
|
||||
TABLE MBK_TO_RDS_VIA
|
||||
|
||||
CONT_BODY_P RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_PTIE 3 ALL
|
||||
CONT_BODY_N RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_NTIE 3 ALL RDS_NWELL 4 ALL
|
||||
CONT_DIF_N RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_NDIF 3 ALL
|
||||
CONT_DIF_P RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_PDIF 3 ALL RDS_NWELL 4 ALL
|
||||
CONT_POLY RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_POLY 3 ALL
|
||||
CONT_POLY2 RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_POLY2 3 ALL
|
||||
CONT_VIA RDS_ALU1 2 ALL RDS_VIA1 1 ALL RDS_ALU2 2 ALL
|
||||
CONT_VIA2 RDS_ALU2 2 ALL RDS_VIA2 1 ALL RDS_ALU3 2 ALL
|
||||
CONT_VIA3 RDS_ALU3 2 ALL RDS_VIA3 1 ALL RDS_ALU4 2 ALL
|
||||
CONT_VIA4 RDS_ALU4 2 ALL RDS_VIA4 1 ALL RDS_ALU5 2 ALL
|
||||
CONT_VIA5 RDS_ALU5 2 ALL RDS_VIA5 1 ALL RDS_ALU6 2 ALL
|
||||
CONT_VIA6 RDS_ALU6 2 ALL RDS_VIA6 1 ALL RDS_ALU7 2 ALL
|
||||
CONT_VIA7 RDS_ALU7 2 ALL RDS_VIA7 1 ALL RDS_ALU8 2 ALL
|
||||
C_X_N RDS_POLY 1 ALL RDS_NDIF 5 ALL RDS_ACTIV 6 ALL
|
||||
C_X_P RDS_POLY 1 ALL RDS_PDIF 5 ALL RDS_NWELL 6 ALL RDS_ACTIV 6 ALL
|
||||
|
||||
END
|
||||
|
||||
##-------------------------------------------------------------------
|
||||
# TABLE MBK_TO_RDS_BIGVIA_HOLE :
|
||||
#
|
||||
# MBK via RDS Hole
|
||||
# name name side step mode
|
||||
##-------------------------------------------------------------------
|
||||
|
||||
TABLE MBK_TO_RDS_BIGVIA_HOLE
|
||||
|
||||
CONT_VIA RDS_VIA1 1 4 ALL
|
||||
CONT_VIA2 RDS_VIA2 1 4 ALL
|
||||
CONT_VIA3 RDS_VIA3 1 4 ALL
|
||||
CONT_VIA5 RDS_VIA3 1 9 ALL
|
||||
CONT_VIA6 RDS_VIA3 1 9 ALL
|
||||
CONT_VIA7 RDS_VIA3 1 9 ALL
|
||||
|
||||
END
|
||||
|
||||
##-------------------------------------------------------------------
|
||||
# TABLE MBK_TO_RDS_BIGVIA_METAL :
|
||||
#
|
||||
# MBK via RDS layer 1 ...
|
||||
# name name delta-width overlap mode
|
||||
##-------------------------------------------------------------------
|
||||
|
||||
TABLE MBK_TO_RDS_BIGVIA_METAL
|
||||
|
||||
CONT_VIA RDS_ALU1 0.0 0.5 ALL RDS_ALU2 0.0 0.5 ALL
|
||||
CONT_VIA2 RDS_ALU2 0.0 0.5 ALL RDS_ALU3 0.0 0.5 ALL
|
||||
CONT_VIA3 RDS_ALU3 0.0 0.5 ALL RDS_ALU4 0.0 0.5 ALL
|
||||
CONT_VIA4 RDS_ALU4 0.0 0.5 ALL RDS_ALU5 0.0 0.5 ALL
|
||||
CONT_VIA5 RDS_ALU5 0.0 0.5 ALL RDS_ALU6 0.0 0.5 ALL
|
||||
|
||||
END
|
||||
|
||||
##-------------------------------------------------------------------
|
||||
# TABLE MBK_TO_RDS_TURNVIA :
|
||||
#
|
||||
# MBK via RDS layer 1 ...
|
||||
# name name DWR MODE
|
||||
##-------------------------------------------------------------------
|
||||
|
||||
TABLE MBK_TO_RDS_TURNVIA
|
||||
|
||||
CONT_TURN1 RDS_ALU1 0 ALL
|
||||
CONT_TURN2 RDS_ALU2 0 ALL
|
||||
CONT_TURN3 RDS_ALU3 0 ALL
|
||||
CONT_TURN4 RDS_ALU4 0 ALL
|
||||
CONT_TURN5 RDS_ALU5 0 ALL
|
||||
CONT_TURN6 RDS_ALU6 0 ALL
|
||||
|
||||
END
|
||||
|
||||
|
||||
##-------------------------------------------------------------------
|
||||
# TABLE LYNX_GRAPH :
|
||||
#
|
||||
# RDS layer Rds layer 1 Rds layer 2 ...
|
||||
# name name name ...
|
||||
##-------------------------------------------------------------------
|
||||
|
||||
TABLE LYNX_GRAPH
|
||||
|
||||
##---------------------------
|
||||
#
|
||||
# Modifie par L.Jacomme (Pb Bulk/Alim avec Lynx)
|
||||
# 23.11.99
|
||||
#
|
||||
# RDS_NWELL RDS_NTIE RDS_NWELL
|
||||
# RDS_PWELL RDS_PTIE RDS_PWELL
|
||||
# RDS_NDIF RDS_CONT RDS_NDIF
|
||||
# RDS_PDIF RDS_CONT RDS_PDIF
|
||||
# RDS_NTIE RDS_CONT RDS_NTIE RDS_NWELL
|
||||
# RDS_PTIE RDS_CONT RDS_PTIE RDS_PWELL
|
||||
|
||||
RDS_NDIF RDS_CONT RDS_NDIF
|
||||
RDS_PDIF RDS_CONT RDS_PDIF
|
||||
RDS_NTIE RDS_CONT RDS_NTIE
|
||||
RDS_PTIE RDS_CONT RDS_PTIE
|
||||
|
||||
RDS_POLY RDS_CONT RDS_POLY
|
||||
RDS_POLY2 RDS_CONT RDS_POLY2
|
||||
RDS_CONT RDS_PDIF RDS_NDIF RDS_POLY RDS_PTIE RDS_NTIE RDS_ALU1 RDS_CONT
|
||||
RDS_ALU1 RDS_CONT RDS_VIA1 RDS_ALU1 RDS_VALU1 RDS_ALU1
|
||||
RDS_VALU1 RDS_CONT RDS_VIA1 RDS_ALU1 RDS_VALU1
|
||||
RDS_VIA1 RDS_ALU1 RDS_ALU2 RDS_VIA1
|
||||
RDS_VIA2 RDS_ALU2 RDS_ALU3 RDS_VIA2
|
||||
RDS_VIA3 RDS_ALU3 RDS_ALU4 RDS_VIA3
|
||||
RDS_VIA4 RDS_ALU4 RDS_ALU5 RDS_VIA4
|
||||
RDS_VIA5 RDS_ALU5 RDS_ALU6 RDS_VIA5
|
||||
RDS_VIA6 RDS_ALU6 RDS_ALU7 RDS_VIA6
|
||||
RDS_VIA7 RDS_ALU7 RDS_ALU8 RDS_VIA7
|
||||
RDS_ALU2 RDS_VIA1 RDS_VIA2 RDS_ALU2
|
||||
RDS_ALU3 RDS_VIA2 RDS_VIA3 RDS_ALU3
|
||||
RDS_ALU4 RDS_VIA3 RDS_VIA4 RDS_ALU4
|
||||
RDS_ALU5 RDS_VIA4 RDS_VIA5 RDS_ALU5
|
||||
RDS_ALU6 RDS_VIA5 RDS_VIA6 RDS_ALU6
|
||||
RDS_ALU7 RDS_VIA6 RDS_VIA7 RDS_ALU7
|
||||
RDS_ALU8 RDS_VIA7 RDS_ALU8
|
||||
|
||||
END
|
||||
|
||||
##-------------------------------------------------------------------
|
||||
# TABLE LYNX_CAPA :
|
||||
#
|
||||
# RDS layer Surface capacitance Perimetric capacitance
|
||||
# name piF / Micron^2 piF / Micron
|
||||
##-------------------------------------------------------------------
|
||||
|
||||
TABLE LYNX_CAPA
|
||||
|
||||
RDS_POLY 1.00e-04 1.00e-04
|
||||
RDS_POLY2 1.00e-04 1.00e-04
|
||||
RDS_ALU1 0.50e-04 0.90e-04
|
||||
RDS_ALU2 0.25e-04 0.95e-04
|
||||
RDS_ALU3 0.25e-04 0.95e-04
|
||||
RDS_ALU4 0.25e-04 0.95e-04
|
||||
RDS_ALU5 0.25e-04 0.95e-04
|
||||
RDS_ALU6 0.25e-04 0.95e-04
|
||||
RDS_ALU7 0.25e-04 0.95e-04
|
||||
RDS_ALU8 0.25e-04 0.95e-04
|
||||
|
||||
END
|
||||
|
||||
##-------------------------------------------------------------------
|
||||
# TABLE LYNX_RESISTOR :
|
||||
#
|
||||
# RDS layer Surface resistor
|
||||
# name Ohm / Micron^2
|
||||
##-------------------------------------------------------------------
|
||||
|
||||
TABLE LYNX_RESISTOR
|
||||
|
||||
RDS_POLY 50.0
|
||||
RDS_POLY2 50.0
|
||||
RDS_ALU1 0.1
|
||||
RDS_ALU2 0.05
|
||||
RDS_ALU3 0.05
|
||||
RDS_ALU4 0.05
|
||||
RDS_ALU5 0.05
|
||||
RDS_ALU6 0.05
|
||||
RDS_ALU7 0.05
|
||||
RDS_ALU8 0.05
|
||||
|
||||
END
|
||||
|
||||
##-------------------------------------------------------------------
|
||||
# TABLE LYNX_TRANSISTOR :
|
||||
#
|
||||
# MBK layer Transistor Type MBK via
|
||||
# name name name
|
||||
##-------------------------------------------------------------------
|
||||
|
||||
TABLE LYNX_TRANSISTOR
|
||||
|
||||
NTRANS NTRANS C_X_N RDS_POLY RDS_NDIF RDS_NDIF RDS_PWELL
|
||||
PTRANS PTRANS C_X_P RDS_POLY RDS_PDIF RDS_PDIF RDS_NWELL
|
||||
|
||||
END
|
||||
|
||||
##-------------------------------------------------------------------
|
||||
# TABLE LYNX_DIFFUSION :
|
||||
#
|
||||
# RDS layer RDS layer
|
||||
# name name
|
||||
##-------------------------------------------------------------------
|
||||
|
||||
TABLE LYNX_DIFFUSION
|
||||
END
|
||||
|
||||
##-------------------------------------------------------------------
|
||||
# TABLE LYNX_BULK_IMPLICIT :
|
||||
#
|
||||
# RDS layer Bulk type
|
||||
# name EXPLICIT/IMPLICIT
|
||||
##-------------------------------------------------------------------
|
||||
|
||||
TABLE LYNX_BULK_IMPLICIT
|
||||
|
||||
##---------------------------
|
||||
#
|
||||
# Modifie par L.Jacomme (Pb Bulk/Alim avec Lynx)
|
||||
# 23.11.99
|
||||
#
|
||||
# NWELL EXPLICIT
|
||||
# PWELL IMPLICIT
|
||||
|
||||
END
|
||||
|
||||
|
||||
|
||||
##-------------------------------------------------------------------
|
||||
# TABLE S2R_OVERSIZE_DENOTCH :
|
||||
##-------------------------------------------------------------------
|
||||
|
||||
TABLE S2R_OVERSIZE_DENOTCH
|
||||
END
|
||||
|
||||
##-------------------------------------------------------------------
|
||||
# TABLE S2R_BLOC_RING_WIDTH :
|
||||
##-------------------------------------------------------------------
|
||||
|
||||
TABLE S2R_BLOC_RING_WIDTH
|
||||
END
|
||||
|
||||
##-------------------------------------------------------------------
|
||||
# TABLE S2R_MINIMUM_LAYER_WIDTH :
|
||||
##-------------------------------------------------------------------
|
||||
|
||||
TABLE S2R_MINIMUM_LAYER_WIDTH
|
||||
|
||||
RDS_NWELL 4
|
||||
RDS_PDIF 2
|
||||
RDS_NTIE 2
|
||||
RDS_PTIE 2
|
||||
RDS_POLY 1
|
||||
RDS_POLY2 1
|
||||
RDS_TPOLY 1
|
||||
RDS_CONT 1
|
||||
RDS_ALU1 1
|
||||
RDS_TALU1 1
|
||||
RDS_VIA1 1
|
||||
RDS_ALU2 2
|
||||
RDS_TALU2 2
|
||||
RDS_VIA2 1
|
||||
RDS_ALU3 2
|
||||
RDS_TALU3 2
|
||||
RDS_VIA3 1
|
||||
RDS_ALU4 2
|
||||
RDS_TALU4 2
|
||||
RDS_VIA4 1
|
||||
RDS_ALU5 2
|
||||
RDS_TALU5 2
|
||||
RDS_VIA5 1
|
||||
RDS_ALU6 2
|
||||
RDS_TALU6 2
|
||||
RDS_VIA6 1
|
||||
RDS_ALU7 2
|
||||
RDS_TALU7 2
|
||||
RDS_VIA7 1
|
||||
RDS_ALU8 2
|
||||
RDS_TALU8 2
|
||||
|
||||
END
|
||||
|
||||
##-------------------------------------------------------------------
|
||||
# TABLE CIF_LAYER :
|
||||
##-------------------------------------------------------------------
|
||||
|
||||
TABLE CIF_LAYER
|
||||
|
||||
RDS_NWELL LNWELL
|
||||
RDS_NDIF LNDIF
|
||||
RDS_PDIF LPDIF
|
||||
RDS_NTIE LNTIE
|
||||
RDS_PTIE LPTIE
|
||||
RDS_POLY LPOLY
|
||||
RDS_POLY2 LPOLY2
|
||||
RDS_TPOLY LTPOLY
|
||||
RDS_CONT LCONT
|
||||
RDS_ALU1 LALU1
|
||||
RDS_VALU1 LVALU1
|
||||
RDS_TALU1 LTALU1
|
||||
RDS_VIA1 LVIA
|
||||
RDS_TVIA1 LTVIA1
|
||||
RDS_ALU2 LALU2
|
||||
RDS_TALU2 LTALU2
|
||||
RDS_VIA2 LVIA2
|
||||
RDS_ALU3 LALU3
|
||||
RDS_TALU3 LTALU3
|
||||
RDS_VIA3 LVIA3
|
||||
RDS_ALU4 LALU4
|
||||
RDS_TALU4 LTALU4
|
||||
RDS_VIA4 LVIA4
|
||||
RDS_ALU5 LALU5
|
||||
RDS_TALU5 LTALU5
|
||||
RDS_VIA5 LVIA5
|
||||
RDS_ALU6 LALU6
|
||||
RDS_TALU6 LTALU6
|
||||
RDS_VIA6 LVIA6
|
||||
RDS_ALU7 LALU7
|
||||
RDS_TALU7 LTALU7
|
||||
RDS_VIA7 LVIA7
|
||||
RDS_ALU8 LALU8
|
||||
RDS_TALU8 LTALU8
|
||||
RDS_REF LREF
|
||||
|
||||
END
|
||||
|
||||
##-------------------------------------------------------------------
|
||||
# TABLE GDS_LAYER :
|
||||
##-------------------------------------------------------------------
|
||||
|
||||
TABLE GDS_LAYER
|
||||
|
||||
RDS_NWELL 1
|
||||
RDS_NDIF 3
|
||||
RDS_PDIF 4
|
||||
RDS_NTIE 5
|
||||
RDS_PTIE 6
|
||||
RDS_POLY 7
|
||||
RDS_POLY2 8
|
||||
RDS_TPOLY 9
|
||||
RDS_CONT 10
|
||||
RDS_ALU1 11
|
||||
RDS_VALU1 12
|
||||
RDS_TALU1 13
|
||||
RDS_VIA1 14
|
||||
RDS_TVIA1 15
|
||||
RDS_ALU2 16
|
||||
RDS_TALU2 17
|
||||
RDS_VIA2 18
|
||||
RDS_ALU3 19
|
||||
RDS_TALU3 20
|
||||
RDS_VIA3 21
|
||||
RDS_ALU4 22
|
||||
RDS_TALU4 23
|
||||
RDS_VIA4 25
|
||||
RDS_ALU5 26
|
||||
RDS_TALU5 27
|
||||
RDS_VIA5 28
|
||||
RDS_ALU6 29
|
||||
RDS_TALU6 30
|
||||
RDS_VIA6 31
|
||||
RDS_ALU7 32
|
||||
RDS_TALU7 33
|
||||
RDS_VIA7 34
|
||||
RDS_ALU8 35
|
||||
RDS_TALU8 36
|
||||
RDS_REF 37
|
||||
|
||||
END
|
||||
|
||||
##-------------------------------------------------------------------
|
||||
# TABLE S2R_POST_TREAT :
|
||||
##-------------------------------------------------------------------
|
||||
|
||||
TABLE S2R_POST_TREAT
|
||||
|
||||
END
|
||||
DRC_RULES
|
||||
|
||||
layer RDS_NWELL 4.;
|
||||
layer RDS_NTIE 2.;
|
||||
layer RDS_PTIE 2.;
|
||||
layer RDS_NDIF 2.;
|
||||
layer RDS_PDIF 2.;
|
||||
layer RDS_ACTIV 2.;
|
||||
layer RDS_CONT 1.;
|
||||
layer RDS_VIA1 1.;
|
||||
layer RDS_VIA2 1.;
|
||||
layer RDS_VIA3 1.;
|
||||
layer RDS_VIA4 1.;
|
||||
layer RDS_VIA5 1.;
|
||||
layer RDS_VIA6 1.;
|
||||
layer RDS_VIA7 1.;
|
||||
layer RDS_POLY 1.;
|
||||
layer RDS_POLY2 1.;
|
||||
layer RDS_ALU1 1.;
|
||||
layer RDS_ALU2 2.;
|
||||
layer RDS_ALU3 2.;
|
||||
layer RDS_ALU4 2.;
|
||||
layer RDS_ALU5 2.;
|
||||
layer RDS_ALU6 2.;
|
||||
layer RDS_ALU7 2.;
|
||||
layer RDS_ALU8 2.;
|
||||
layer RDS_USER0 1.;
|
||||
layer RDS_USER1 1.;
|
||||
layer RDS_USER2 1.;
|
||||
|
||||
regles
|
||||
|
||||
# Note : ``min'' is different from ``>=''.
|
||||
# min is applied on polygons and >= is applied on rectangles.
|
||||
# There is the same difference between max and <=.
|
||||
# >= is faster than min, but min must be used where it is
|
||||
# required to consider polygons, for example distance of
|
||||
# two objects in the same layer
|
||||
#
|
||||
# There is no rule to check NTIE and PDIF are included in NWELL
|
||||
# since this is necessarily true
|
||||
#-----------------------------------------------------------
|
||||
|
||||
# Check the NWELL shapes
|
||||
#-----------------------
|
||||
caracterise RDS_NWELL (
|
||||
regle 1 : largeur >= 4. ;
|
||||
regle 2 : longueur_inter min 4. ;
|
||||
regle 3 : notch >= 12. ;
|
||||
);
|
||||
relation RDS_NWELL , RDS_NWELL (
|
||||
regle 4 : distance axiale min 12. ;
|
||||
);
|
||||
|
||||
# Check RDS_PTIE is really excluded outside NWELL
|
||||
#------------------------------------------------
|
||||
relation RDS_PTIE , RDS_NWELL (
|
||||
regle 5 : distance axiale >= 7.5;
|
||||
regle 6 : enveloppe longueur_inter < 0. ;
|
||||
regle 7 : marge longueur_inter < 0. ;
|
||||
regle 8 : croix longueur_inter < 0. ;
|
||||
regle 9 : intersection longueur_inter < 0. ;
|
||||
regle 10 : extension longueur_inter < 0. ;
|
||||
regle 11 : inclusion longueur_inter < 0. ;
|
||||
);
|
||||
|
||||
# Check RDS_NDIF is really excluded outside NWELL
|
||||
#------------------------------------------------
|
||||
relation RDS_NDIF , RDS_NWELL (
|
||||
regle 12 : distance axiale >= 7.5;
|
||||
regle 13 : enveloppe longueur_inter < 0. ;
|
||||
regle 14 : marge longueur_inter < 0. ;
|
||||
regle 15 : croix longueur_inter < 0. ;
|
||||
regle 16 : intersection longueur_inter < 0. ;
|
||||
regle 17 : extension longueur_inter < 0. ;
|
||||
regle 18 : inclusion longueur_inter < 0. ;
|
||||
);
|
||||
|
||||
# Check the RDS_PDIF shapes
|
||||
#--------------------------
|
||||
caracterise RDS_PDIF (
|
||||
regle 19 : largeur >= 2. ;
|
||||
regle 20 : longueur_inter min 2. ;
|
||||
regle 21 : notch >= 3. ;
|
||||
);
|
||||
relation RDS_PDIF , RDS_PDIF (
|
||||
regle 22 : distance axiale min 3. ;
|
||||
);
|
||||
|
||||
# Check the RDS_NDIF shapes
|
||||
#--------------------------
|
||||
caracterise RDS_NDIF (
|
||||
regle 23 : largeur >= 2. ;
|
||||
regle 24 : longueur_inter min 2. ;
|
||||
regle 25 : notch >= 3. ;
|
||||
);
|
||||
relation RDS_NDIF , RDS_NDIF (
|
||||
regle 26 : distance axiale min 3. ;
|
||||
);
|
||||
|
||||
# Check the RDS_PTIE shapes
|
||||
#--------------------------
|
||||
caracterise RDS_PTIE (
|
||||
regle 27 : largeur >= 2. ;
|
||||
regle 28 : longueur_inter min 2. ;
|
||||
regle 29 : notch >= 3. ;
|
||||
);
|
||||
relation RDS_PTIE , RDS_PTIE (
|
||||
regle 30 : distance axiale min 3. ;
|
||||
);
|
||||
|
||||
# Check the RDS_NTIE shapes
|
||||
#--------------------------
|
||||
caracterise RDS_NTIE (
|
||||
regle 31 : largeur >= 2. ;
|
||||
regle 32 : longueur_inter min 2. ;
|
||||
regle 33 : notch >= 3. ;
|
||||
);
|
||||
relation RDS_NTIE , RDS_NTIE (
|
||||
regle 34 : distance axiale min 3. ;
|
||||
);
|
||||
|
||||
define RDS_PDIF , RDS_PTIE union -> ANY_P_DIF;
|
||||
define RDS_NDIF , RDS_NTIE union -> ANY_N_DIF;
|
||||
|
||||
# Check the ANY_N_DIF ANY_P_DIFF exclusion
|
||||
#--------------------------------------
|
||||
relation ANY_N_DIF , ANY_P_DIF (
|
||||
regle 35 : distance axiale >= 3. ;
|
||||
regle 36 : enveloppe longueur_inter < 0. ;
|
||||
regle 37 : marge longueur_inter < 0. ;
|
||||
regle 38 : croix longueur_inter < 0. ;
|
||||
regle 39 : intersection longueur_inter < 0. ;
|
||||
regle 40 : extension longueur_inter < 0. ;
|
||||
regle 41 : inclusion longueur_inter < 0. ;
|
||||
);
|
||||
|
||||
undefine ANY_P_DIF;
|
||||
undefine ANY_N_DIF;
|
||||
|
||||
define RDS_NDIF , RDS_PDIF union -> NP_DIF;
|
||||
|
||||
# Check RDS_POLY related to NP_DIF
|
||||
#---------------------------------
|
||||
relation RDS_POLY , NP_DIF (
|
||||
regle 42 : distance axiale >= 1. ;
|
||||
regle 43 : intersection longueur_inter < 0. ;
|
||||
);
|
||||
|
||||
define NP_DIF , RDS_POLY intersection -> CHANNEL;
|
||||
|
||||
# Check the RDS_POLY shapes
|
||||
#--------------------------
|
||||
caracterise RDS_POLY (
|
||||
regle 44 : largeur >= 1. ;
|
||||
regle 45 : longueur_inter min 1. ;
|
||||
regle 46 : notch >= 2. ;
|
||||
);
|
||||
relation RDS_POLY , RDS_POLY (
|
||||
regle 47 : distance axiale min 2.;
|
||||
);
|
||||
|
||||
define NP_DIF , RDS_CONT intersection -> CONT_DIFF;
|
||||
# Check the CHANNEL shapes
|
||||
#--------------------------
|
||||
caracterise CHANNEL (
|
||||
regle 48 : notch >= 3. ;
|
||||
);
|
||||
relation CHANNEL , CHANNEL (
|
||||
regle 49 : distance axiale min 3.;
|
||||
);
|
||||
|
||||
undefine CHANNEL;
|
||||
|
||||
# Check RDS_POLY is distant from ACTIV ZONE of TRANSISTOR
|
||||
#--------------------------------------------------------
|
||||
relation RDS_POLY , RDS_ACTIV (
|
||||
regle 79 : distance axiale >= 1. ;
|
||||
);
|
||||
|
||||
relation RDS_POLY , CONT_DIFF (
|
||||
regle 50 : distance axiale >= 2. ;
|
||||
);
|
||||
|
||||
undefine CONT_DIFF;
|
||||
undefine NP_DIF;
|
||||
|
||||
|
||||
# Check RDS_ALU1 shapes
|
||||
#----------------------
|
||||
caracterise RDS_ALU1 (
|
||||
regle 51 : largeur >= 1. ;
|
||||
regle 52 : longueur_inter min 1. ;
|
||||
regle 53 : notch >= 3. ;
|
||||
);
|
||||
relation RDS_ALU1 , RDS_ALU1 (
|
||||
regle 54 : distance axiale min 3. ;
|
||||
);
|
||||
|
||||
# Check RDS_ALU2 shapes
|
||||
#----------------------
|
||||
caracterise RDS_ALU2 (
|
||||
regle 55 : largeur >= 2. ;
|
||||
regle 56 : longueur_inter min 2. ;
|
||||
regle 57 : notch >= 3. ;
|
||||
);
|
||||
relation RDS_ALU2 , RDS_ALU2 (
|
||||
regle 58 : distance axiale min 3. ;
|
||||
);
|
||||
|
||||
# Check RDS_ALU3 shapes
|
||||
#----------------------
|
||||
caracterise RDS_ALU3 (
|
||||
regle 59 : largeur >= 2. ;
|
||||
regle 60 : longueur_inter min 2. ;
|
||||
regle 61 : notch >= 3. ;
|
||||
);
|
||||
relation RDS_ALU3 , RDS_ALU3 (
|
||||
regle 62 : distance axiale min 3. ;
|
||||
);
|
||||
|
||||
# Check RDS_ALU4 shapes
|
||||
#----------------------
|
||||
caracterise RDS_ALU4 (
|
||||
regle 63 : largeur >= 2. ;
|
||||
regle 64 : longueur_inter min 2. ;
|
||||
regle 65 : notch >= 3. ;
|
||||
);
|
||||
relation RDS_ALU4 , RDS_ALU4 (
|
||||
regle 66 : distance axiale min 3. ;
|
||||
);
|
||||
|
||||
# Check RDS_ALU5 shapes
|
||||
#----------------------
|
||||
# caracterise RDS_ALU5 (
|
||||
# regle 80 : largeur >= 2. ;
|
||||
# regle 81 : longueur_inter min 2. ;
|
||||
# regle 82 : notch >= 8. ;
|
||||
#);
|
||||
#relation RDS_ALU5 , RDS_ALU5 (
|
||||
# regle 83 : distance axiale min 8. ;
|
||||
#);
|
||||
|
||||
# Check RDS_ALU5 shapes
|
||||
# it is not true !! LUDO
|
||||
# Only to work with OCR
|
||||
#----------------------
|
||||
caracterise RDS_ALU5 (
|
||||
regle 80 : largeur >= 2. ;
|
||||
regle 81 : longueur_inter min 2. ;
|
||||
regle 82 : notch >= 3. ;
|
||||
);
|
||||
relation RDS_ALU5 , RDS_ALU5 (
|
||||
regle 83 : distance axiale min 3. ;
|
||||
);
|
||||
|
||||
# Check RDS_ALU6 shapes
|
||||
#----------------------
|
||||
#caracterise RDS_ALU6 (
|
||||
# regle 84 : largeur >= 2. ;
|
||||
# regle 85 : longueur_inter min 2. ;
|
||||
# regle 86 : notch >= 8. ;
|
||||
#);
|
||||
#relation RDS_ALU6 , RDS_ALU6 (
|
||||
# regle 87 : distance axiale min 8. ;
|
||||
#);
|
||||
|
||||
# Check RDS_ALU6 shapes
|
||||
# it is not true !! LUDO
|
||||
# Only to work with OCR
|
||||
#----------------------
|
||||
caracterise RDS_ALU6 (
|
||||
regle 84 : largeur >= 2. ;
|
||||
regle 85 : longueur_inter min 2. ;
|
||||
regle 86 : notch >= 3. ;
|
||||
);
|
||||
relation RDS_ALU6 , RDS_ALU6 (
|
||||
regle 87 : distance axiale min 3. ;
|
||||
);
|
||||
|
||||
# Check ANY_VIA layers, stacking are free
|
||||
#----------------------------------------
|
||||
relation RDS_CONT , RDS_CONT (
|
||||
regle 67 : distance axiale >= 3. ;
|
||||
);
|
||||
relation RDS_VIA , RDS_VIA (
|
||||
regle 68 : distance axiale >= 4. ;
|
||||
);
|
||||
relation RDS_VIA2 , RDS_VIA2 (
|
||||
regle 69 : distance axiale >= 4. ;
|
||||
);
|
||||
relation RDS_VIA3 , RDS_VIA3 (
|
||||
regle 70 : distance axiale >= 4. ;
|
||||
);
|
||||
|
||||
# It's not true !! LUDO
|
||||
# only to work with OCR
|
||||
relation RDS_VIA4 , RDS_VIA4 (
|
||||
regle 88 : distance axiale >= 4. ;
|
||||
);
|
||||
|
||||
# relation RDS_VIA4 , RDS_VIA4 (
|
||||
# regle 88 : distance axiale >= 9. ;
|
||||
#);
|
||||
|
||||
# It's not true !! LUDO
|
||||
# only to work with OCR
|
||||
relation RDS_VIA5 , RDS_VIA5 (
|
||||
regle 89 : distance axiale >= 4. ;
|
||||
);
|
||||
|
||||
# relation RDS_VIA5 , RDS_VIA5 (
|
||||
# regle 89 : distance axiale >= 9. ;
|
||||
# );
|
||||
caracterise RDS_CONT (
|
||||
regle 71 : largeur >= 1. ;
|
||||
regle 72 : longueur <= 1. ;
|
||||
);
|
||||
caracterise RDS_VIA (
|
||||
regle 73 : largeur >= 1. ;
|
||||
regle 74 : longueur <= 1. ;
|
||||
);
|
||||
caracterise RDS_VIA2 (
|
||||
regle 75 : largeur >= 1. ;
|
||||
regle 76 : longueur <= 1. ;
|
||||
);
|
||||
caracterise RDS_VIA3 (
|
||||
regle 77 : largeur >= 1. ;
|
||||
regle 78 : longueur <= 1. ;
|
||||
);
|
||||
caracterise RDS_VIA4 (
|
||||
regle 90 : largeur >= 1. ;
|
||||
regle 91 : longueur <= 1. ;
|
||||
);
|
||||
caracterise RDS_VIA5 (
|
||||
regle 92 : largeur >= 1. ;
|
||||
regle 93 : longueur <= 1. ;
|
||||
);
|
||||
|
||||
# Check the POLY2 shapes
|
||||
#-----------------------
|
||||
caracterise RDS_POLY2 (
|
||||
regle 94 : largeur >= 1. ;
|
||||
regle 95 : longueur_inter min 1. ;
|
||||
regle 96 : notch >= 5. ;
|
||||
);
|
||||
relation RDS_POLY2 , RDS_POLY2 (
|
||||
regle 97 : distance axiale min 5. ;
|
||||
);
|
||||
|
||||
# Check RDS_POLY2 is really included inside RDS_POLY1
|
||||
#----------------------------------------------------
|
||||
relation RDS_POLY , RDS_POLY2 (
|
||||
regle 98 : distance axiale < 0.;
|
||||
regle 99 : enveloppe inferieure min 5. ;
|
||||
regle 100 : marge longueur_inter < 0. ;
|
||||
regle 101 : croix longueur_inter < 0. ;
|
||||
regle 102 : intersection longueur_inter < 0. ;
|
||||
regle 103 : extension longueur_inter < 0. ;
|
||||
regle 104 : inclusion longueur_inter < 0. ;
|
||||
);
|
||||
|
||||
|
||||
fin regles
|
||||
DRC_COMMENT
|
||||
1 (RDS_NWELL) minimum width 4.
|
||||
2 (RDS_NWELL) minimum width 4.
|
||||
3 (RDS_NWELL) Manhatan distance min 12.
|
||||
4 (RDS_NWELL,RDS_NWELL) Manhatan distance min 12.
|
||||
5 (RDS_PTIE,RDS_NWELL) Manhatan distance min 7.5
|
||||
6 (RDS_PTIE,RDS_NWELL) must never been in contact
|
||||
7 (RDS_PTIE,RDS_NWELL) must never been in contact
|
||||
8 (RDS_PTIE,RDS_NWELL) must never been in contact
|
||||
9 (RDS_PTIE,RDS_NWELL) must never been in contact
|
||||
10 (RDS_PTIE,RDS_NWELL) must never been in contact
|
||||
11 (RDS_PTIE,RDS_NWELL) must never been in contact
|
||||
12 (RDS_NDIF,RDS_NWELL) Manhatan distance min 7.5
|
||||
13 (RDS_NDIF,RDS_NWELL) must never been in contact
|
||||
14 (RDS_NDIF,RDS_NWELL) must never been in contact
|
||||
15 (RDS_NDIF,RDS_NWELL) must never been in contact
|
||||
16 (RDS_NDIF,RDS_NWELL) must never been in contact
|
||||
17 (RDS_NDIF,RDS_NWELL) must never been in contact
|
||||
18 (RDS_NDIF,RDS_NWELL) must never been in contact
|
||||
19 (RDS_PDIF) minimum width 2.
|
||||
20 (RDS_PDIF) minimum width 2.
|
||||
21 (RDS_PDIF) Manhatan distance min 3.
|
||||
22 (RDS_PDIF,RDS_PDIF) Manhatan distance min 3.
|
||||
23 (RDS_NDIF) minimum width 2.
|
||||
24 (RDS_NDIF) minimum width 2.
|
||||
25 (RDS_NDIF) Manhatan distance min 3.
|
||||
26 (RDS_NDIF,RDS_NDIF) Manhatan distance min 3.
|
||||
27 (RDS_PTIE) minimum width 2.
|
||||
28 (RDS_PTIE) minimum width 2.
|
||||
29 (RDS_PTIE) Manhatan distance min 3.
|
||||
30 (RDS_PTIE,RDS_PTIE) Manhatan distance min 3.
|
||||
31 (RDS_NTIE) minimum width 2.
|
||||
32 (RDS_NTIE) minimum width 2.
|
||||
33 (RDS_NTIE) Manhatan distance min 3.
|
||||
34 (RDS_NTIE,RDS_NTIE) Manhatan distance min 3.
|
||||
35 (ANY_N_DIF,ANY_P_DIF) Manhatan distance min 3.
|
||||
36 (ANY_N_DIF,ANY_P_DIF) must never been in contact
|
||||
37 (ANY_N_DIF,ANY_P_DIF) must never been in contact
|
||||
38 (ANY_N_DIF,ANY_P_DIF) must never been in contact
|
||||
39 (ANY_N_DIF,ANY_P_DIF) must never been in contact
|
||||
40 (ANY_N_DIF,ANY_P_DIF) must never been in contact
|
||||
41 (ANY_N_DIF,ANY_P_DIF) must never been in contact
|
||||
42 (RDS_POLY,ANY_N_DIF) Manhatan distance min 1.
|
||||
43 (RDS_POLY,NP_DIF) bad intersection
|
||||
44 (RDS_POLY) minimum width 1.
|
||||
45 (RDS_POLY) minimum width 1.
|
||||
46 (RDS_POLY) Manhatan distance min 2.
|
||||
47 (RDS_POLY,RDS_POLY) Manhatan distance min 2.
|
||||
48 (CHANNEL) Manhatan distance min 3.
|
||||
49 (CHANNEL,CHANNEL) Manhatan distance min 3.
|
||||
50 (RDS_POLY,CONT_DIFF) Manhatan distance min 2.
|
||||
51 (RDS_ALU1) minimum width 1.
|
||||
52 (RDS_ALU1) minimum width 1.
|
||||
53 (RDS_ALU1) Manhatan distance min 3.
|
||||
54 (RDS_ALU1,RDS_ALU1) Manhatan distance min 3.
|
||||
55 (RDS_ALU2) minimum width 2.
|
||||
56 (RDS_ALU2) minimum width 2.
|
||||
57 (RDS_ALU2) Manhatan distance min 3.
|
||||
58 (RDS_ALU2,RDS_ALU2) Manhatan distance min 3.
|
||||
59 (RDS_ALU3) minimum width 2.
|
||||
60 (RDS_ALU3) minimum width 2.
|
||||
61 (RDS_ALU3) Manhatan distance min 3.
|
||||
62 (RDS_ALU3,RDS_ALU3) Manhatan distance min 3.
|
||||
63 (RDS_ALU4) minimum width 2.
|
||||
64 (RDS_ALU4) minimum width 2.
|
||||
65 (RDS_ALU4) Manhatan distance min 3.
|
||||
66 (RDS_ALU4,RDS_ALU4) Manhatan distance min 3.
|
||||
67 (RDS_CONT,RDS_CONT) Manhatan distance min 3.
|
||||
68 (RDS_VIA,RDS_VIA) Manhatan distance min 4.
|
||||
69 (RDS_VIA2,RDS_VIA2) Manhatan distance min 4.
|
||||
70 (RDS_VIA3,RDS_VIA3) Manhatan distance min 4.
|
||||
71 (RDS_CONT) minimum width 1.
|
||||
72 (RDS_CONT) maximum length 1.
|
||||
73 (RDS_VIA) minimum width 1.
|
||||
74 (RDS_VIA) maximum length 1.
|
||||
75 (RDS_VIA2) minimum width 1.
|
||||
76 (RDS_VIA2) maximum length 1.
|
||||
77 (RDS_VIA3) minimum width 1.
|
||||
78 (RDS_VIA3) maximum length 1.
|
||||
79 (RDS_POLY,RDS_ACTIV) Manhatan distance min 1.
|
||||
80 (RDS_ALU5) minimum width 2.
|
||||
81 (RDS_ALU5) minimum width 2.
|
||||
82 (RDS_ALU5) Manhatan distance min 8.
|
||||
83 (RDS_ALU5,RDS_ALU5) Manhatan distance min 8.
|
||||
84 (RDS_ALU6) minimum width 2.
|
||||
85 (RDS_ALU6) minimum width 2.
|
||||
86 (RDS_ALU6) Manhatan distance min 8.
|
||||
87 (RDS_ALU6,RDS_ALU6) Manhatan distance min 8.
|
||||
88 (RDS_VIA4,RDS_VIA4) Manhatan distance min 9.
|
||||
89 (RDS_VIA5,RDS_VIA5) Manhatan distance min 9.
|
||||
90 (RDS_VIA4) minimum width 1.
|
||||
91 (RDS_VIA4) maximum length 1.
|
||||
92 (RDS_VIA5) minimum width 1.
|
||||
93 (RDS_VIA5) maximum length 1.
|
||||
94 (RDS_POLY2) minimum width 1.
|
||||
95 (RDS_POLY2) minimum width 1.
|
||||
96 (RDS_POLY2) Manhatan distance min 5.
|
||||
97 (RDS_POLY2,POLY2) Manhatan distance min 5.
|
||||
98 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5.
|
||||
99 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5.
|
||||
100 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5.
|
||||
101 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5.
|
||||
102 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5.
|
||||
103 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5.
|
||||
104 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5.
|
||||
END_DRC_COMMENT
|
||||
END_DRC_RULES
|
||||
Loading…
Reference in New Issue