From aec22e1e7d7f663cf7f13f34c8a3ed48096d1bb6 Mon Sep 17 00:00:00 2001
From: Ludovic Jacomme <alliance-cvs@asim.lip6.fr>
Date: Sun, 23 May 2004 17:56:51 +0000
Subject: [PATCH] - a 4 bits multiplier example

---
 .../alliance-examples/multi4b/Makefile        | 346 +++++++++++++
 .../alliance-examples/multi4b/README          | 118 +++++
 .../alliance-examples/multi4b/multi4.ioc      |  34 ++
 .../alliance-examples/multi4b/multi4.pat      | 471 ++++++++++++++++++
 .../alliance-examples/multi4b/multi4.vhdl     |  56 +++
 5 files changed, 1025 insertions(+)
 create mode 100644 alliance/src/documentation/alliance-examples/multi4b/Makefile
 create mode 100644 alliance/src/documentation/alliance-examples/multi4b/README
 create mode 100644 alliance/src/documentation/alliance-examples/multi4b/multi4.ioc
 create mode 100644 alliance/src/documentation/alliance-examples/multi4b/multi4.pat
 create mode 100644 alliance/src/documentation/alliance-examples/multi4b/multi4.vhdl

diff --git a/alliance/src/documentation/alliance-examples/multi4b/Makefile b/alliance/src/documentation/alliance-examples/multi4b/Makefile
new file mode 100644
index 00000000..61817bc2
--- /dev/null
+++ b/alliance/src/documentation/alliance-examples/multi4b/Makefile
@@ -0,0 +1,346 @@
+# /*------------------------------------------------------------\
+# |                                                             |
+# | File   :                    Makefile                        |
+# |                                                             |
+# | Author :                 Jacomme Ludovic                    |
+# |                                                             |
+# \------------------------------------------------------------*/
+# /*------------------------------------------------------------\
+# |                                                             |
+# |                              Cells                          |
+# |                                                             |
+# \------------------------------------------------------------*/
+# /*------------------------------------------------------------\
+# |                                                             |
+# |                             Binary                          |
+# |                                                             |
+# \------------------------------------------------------------*/
+
+ALLIANCE_BIN=$(ALLIANCE_TOP)/bin
+
+VASY   = $(ALLIANCE_BIN)/vasy
+ASIMUT = $(ALLIANCE_BIN)/asimut
+BOOM   = $(ALLIANCE_BIN)/boom
+BOOG   = $(ALLIANCE_BIN)/boog
+LOON   = $(ALLIANCE_BIN)/loon
+OCP    = $(ALLIANCE_BIN)/ocp
+NERO   = $(ALLIANCE_BIN)/nero
+COUGAR = $(ALLIANCE_BIN)/cougar
+LVX    = $(ALLIANCE_BIN)/lvx
+DRUC   = $(ALLIANCE_BIN)/druc
+S2R    = $(ALLIANCE_BIN)/s2r
+BLAST  = $(ALLIANCE_BIN)/sblast
+
+DREAL  = $(ALLIANCE_BIN)/dreal
+GRAAL  = $(ALLIANCE_BIN)/graal
+XSCH   = $(ALLIANCE_BIN)/xsch
+XPAT   = $(ALLIANCE_BIN)/xpat
+XFSM   = $(ALLIANCE_BIN)/xfsm
+
+TOUCH  = touch
+
+TARGET_LIB      = $(ALLIANCE_TOP)/cells/sxlib
+RDS_TECHNO_SYMB = ../etc/techno-symb.rds
+RDS_TECHNO      = ../etc/techno-035.rds
+SPI_MODEL       = $(ALLIANCE_TOP)/etc/spimodel.cfg
+METAL_LEVEL     = 2
+
+# /*------------------------------------------------------------\
+# |                                                             |
+# |                            Environement                     |
+# |                                                             |
+# \------------------------------------------------------------*/
+
+ENV_VASY = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
+           MBK_CATAL_NAME=NO_CATAL; export MBK_CATAL_NAME
+
+ENV_BOOM = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
+           MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
+
+ENV_BOOG = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
+           MBK_IN_LO=vst; export MBK_IN_LO; \
+	   MBK_OUT_LO=vst; export MBK_OUT_LO; \
+           MBK_TARGET_LIB=$(TARGET_LIB); export MBK_TARGET_LIB; \
+           MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
+
+ENV_LOON = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
+           MBK_IN_LO=vst; export MBK_IN_LO; \
+	   MBK_OUT_LO=vst; export MBK_OUT_LO; \
+           MBK_TARGET_LIB=$(TARGET_LIB); export MBK_TARGET_LIB; \
+           MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
+           MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
+
+ENV_ASIMUT_VASY = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
+             MBK_CATAL_NAME=CATAL_ASIMUT_VASY; export MBK_CATAL_NAME;\
+             MBK_IN_LO=vst; export MBK_IN_LO;\
+	     MBK_OUT_LO=vst; export MBK_OUT_LO
+
+ENV_ASIMUT_SYNTH = MBK_WORK_LIB=.; export MBK_WORK_LIB;\
+             MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME;\
+             MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
+             MBK_IN_LO=vst; export MBK_IN_LO;\
+	     MBK_OUT_LO=vst; export MBK_OUT_LO
+
+ENV_OCP =  MBK_WORK_LIB=.; export MBK_WORK_LIB; \
+           MBK_IN_LO=vst; export MBK_IN_LO; \
+	   MBK_OUT_LO=vst; export MBK_OUT_LO; \
+           MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
+           MBK_IN_PH=ap; export MBK_IN_PH; \
+           MBK_OUT_PH=ap; export MBK_OUT_PH; \
+           MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
+
+ENV_NERO =  MBK_WORK_LIB=.; export MBK_WORK_LIB; \
+           MBK_IN_LO=vst; export MBK_IN_LO; \
+	   MBK_OUT_LO=vst; export MBK_OUT_LO; \
+           MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
+           MBK_IN_PH=ap; export MBK_IN_PH; \
+           MBK_OUT_PH=ap; export MBK_OUT_PH; \
+           MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
+
+
+
+ENV_COUGAR_SPI =  MBK_WORK_LIB=.; export MBK_WORK_LIB; \
+           MBK_IN_LO=spi; export MBK_IN_LO; \
+	   MBK_OUT_LO=spi; export MBK_OUT_LO; \
+           MBK_SPI_MODEL=$(SPI_MODEL); export MBK_SPI_MODEL; \
+           MBK_SPI_ONE_NODE_NORC="true"; export MBK_SPI_ONE_NODE_NORC; \
+           MBK_SPI_NAMEDNODES="true"; export MBK_SPI_NAMEDNODES; \
+           RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME; \
+           RDS_IN=cif; export RDS_IN; \
+           RDS_OUT=cif; export RDS_OUT; \
+           MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
+           MBK_IN_PH=ap; export MBK_IN_PH; \
+           MBK_OUT_PH=ap; export MBK_OUT_PH; \
+           MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
+
+ENV_COUGAR =  MBK_WORK_LIB=.; export MBK_WORK_LIB; \
+           MBK_IN_LO=al; export MBK_IN_LO; \
+	   MBK_OUT_LO=al; export MBK_OUT_LO; \
+           RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME; \
+           RDS_IN=cif; export RDS_IN; \
+           RDS_OUT=cif; export RDS_OUT; \
+           MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
+           MBK_IN_PH=ap; export MBK_IN_PH; \
+           MBK_OUT_PH=ap; export MBK_OUT_PH; \
+           MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
+
+ENV_LVX =  MBK_WORK_LIB=.; export MBK_WORK_LIB; \
+           MBK_IN_LO=vst; export MBK_IN_LO; \
+	   MBK_OUT_LO=vst; export MBK_OUT_LO; \
+           MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
+           MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
+
+ENV_DRUC = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
+           RDS_TECHNO_NAME=$(RDS_TECHNO_SYMB); export RDS_TECHNO_NAME; \
+           MBK_IN_PH=ap; export MBK_IN_PH; \
+           MBK_OUT_PH=ap; export MBK_OUT_PH; \
+           MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
+           MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
+
+ENV_S2R  = MBK_WORK_LIB=.; export MBK_WORK_LIB; \
+           RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME; \
+           RDS_IN=cif; export RDS_IN; \
+           RDS_OUT=cif; export RDS_OUT; \
+           MBK_IN_PH=ap; export MBK_IN_PH; \
+           MBK_OUT_PH=ap; export MBK_OUT_PH; \
+           MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \
+           MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME
+
+
+all :  multi4.cif
+
+# /*------------------------------------------------------------\
+# |                                                             |
+# |                             Vasy                            |
+# |                                                             |
+# \------------------------------------------------------------*/
+
+multi4.vbe : multi4.vhdl
+	$(ENV_VASY); $(VASY) -a -B -o -p -I vhdl multi4
+
+# /*------------------------------------------------------------\
+# |                                                             |
+# |                             Asimut                          |
+# |                                                             |
+# \------------------------------------------------------------*/
+
+res_vasy_1.pat : multi4.vbe
+	$(ENV_ASIMUT_VASY); $(ASIMUT) -b multi4 multi4 res_vasy_1 
+
+res_synth_1.pat : multi4.vst 
+	$(ENV_ASIMUT_SYNTH); $(ASIMUT) multi4 multi4 res_synth_1
+
+# /*------------------------------------------------------------\
+# |                                                             |
+# |                             Boom                            |
+# |                                                             |
+# \------------------------------------------------------------*/
+
+boom.done : multi4_o.vbe
+	@$(TOUCH) boom.done
+
+multi4_o.vbe : multi4.vbe multi4.boom res_vasy_1.pat
+	$(ENV_BOOM); $(BOOM) -VP multi4 multi4_o
+
+# /*------------------------------------------------------------\
+# |                                                             |
+# |                             Boog                            |
+# |                                                             |
+# \------------------------------------------------------------*/
+
+boog.done : multi4_o.vst
+	@$(TOUCH) boog.done
+
+multi4_o.vst : multi4_o.vbe
+	$(ENV_BOOG); $(BOOG) multi4_o
+
+# /*------------------------------------------------------------\
+# |                                                             |
+# |                             Loon                            |
+# |                                                             |
+# \------------------------------------------------------------*/
+
+loon.done : multi4.vst
+	@$(TOUCH) loon.done
+
+multi4.vst : multi4_o.vst
+	$(ENV_LOON); $(LOON) multi4_o multi4
+
+# /*------------------------------------------------------------\
+# |                                                             |
+# |                             OCP                             |
+# |                                                             |
+# \------------------------------------------------------------*/
+
+multi4_p.ap : res_synth_1.pat
+	$(ENV_OCP); $(OCP) -v -gnuplot -ioc multi4  multi4 multi4_p
+
+# /*------------------------------------------------------------\
+# |                                                             |
+# |                             NERO                            |
+# |                                                             |
+# \------------------------------------------------------------*/
+
+multi4.ap : multi4_p.ap multi4.vst
+	$(ENV_NERO); $(NERO) -v -$(METAL_LEVEL) -p multi4_p multi4 multi4
+
+# /*------------------------------------------------------------\
+# |                                                             |
+# |                             Cougar                          |
+# |                                                             |
+# \------------------------------------------------------------*/
+
+multi4_e.spi : multi4.ap
+	$(ENV_COUGAR_SPI); $(COUGAR) -v -ac multi4 multi4_e
+
+multi4_erc.spi : multi4.ap
+	$(ENV_COUGAR_SPI); $(COUGAR) -v -ar multi4 multi4_erc
+
+multi4_erc.al : multi4.ap
+	$(ENV_COUGAR); $(COUGAR) -v -ar multi4 multi4_erc
+
+multi4_e.al : multi4.ap
+	$(ENV_COUGAR); $(COUGAR) -v -ac multi4 multi4_e
+
+multi4_et.al : multi4.ap
+	$(ENV_COUGAR); $(COUGAR) -v -ac -t multi4 multi4_et
+
+multi4_et.spi : multi4.ap
+	$(ENV_COUGAR_SPI); $(COUGAR) -v -ac -t multi4 multi4_et
+
+multi4_er.al : multi4.cif
+	$(ENV_COUGAR); $(COUGAR) -v -r -t multi4 multi4_er
+
+multi4_real.al : multi4.ap
+	$(ENV_COUGAR); $(ENV_S2R); $(COUGAR) -v -ac multi4 multi4_real
+
+multi4_real_t.al : multi4.ap
+	$(ENV_COUGAR); $(ENV_S2R); $(COUGAR) -v -t -ac multi4 multi4_real_t
+
+# /*------------------------------------------------------------\
+# |                                                             |
+# |                             Lvx                             |
+# |                                                             |
+# \------------------------------------------------------------*/
+
+lvx.done : multi4.vst multi4_e.al multi4_e.spi
+	$(ENV_LVX); $(LVX) vst al multi4 multi4_e -f
+	$(TOUCH) lvx.done
+
+# /*------------------------------------------------------------\
+# |                                                             |
+# |                             Druc                            |
+# |                                                             |
+# \------------------------------------------------------------*/
+
+druc.done : lvx.done multi4.ap
+	$(ENV_DRUC); $(DRUC) multi4
+	$(TOUCH) druc.done
+
+# /*------------------------------------------------------------\
+# |                                                             |
+# |                             S2R                             |
+# |                                                             |
+# \------------------------------------------------------------*/
+
+multi4.cif : druc.done
+	$(ENV_S2R); $(S2R) -v multi4
+
+# /*------------------------------------------------------------\
+# |                                                             |
+# |                             TOOLS                           |
+# |                                                             |
+# \------------------------------------------------------------*/
+
+graal :
+	$(ENV_S2R); $(GRAAL)
+
+graal_multi4_p : multi4_p.ap
+	$(ENV_S2R); $(GRAAL) -l multi4_p
+
+graal_multi4 : multi4.ap
+	$(ENV_S2R); $(GRAAL) -l multi4
+
+xsch:
+	$(ENV_LOON); $(XSCH)
+
+xsch_multi4_o : multi4.vst
+	$(ENV_LOON); $(XSCH) -l multi4_o
+
+xsch_multi4 : multi4.vst
+	$(ENV_LOON); $(XSCH) -l multi4
+
+xsch_multi4_e: multi4_e.al
+	$(ENV_COUGAR); $(XSCH) -l multi4_e
+
+xsch_multi4_et: multi4_et.al
+	$(ENV_COUGAR); $(XSCH) -l multi4_et
+
+xpat: 
+	$(ENV_ASIMUT_SYNTH); $(XPAT)
+
+xpat_synth: res_synth_1.pat
+	$(ENV_ASIMUT_SYNTH); $(XPAT) -l res_synth_1
+
+xpat_vasy : res_vasy_1.pat
+	$(ENV_ASIMUT_SYNTH); $(XPAT) -l res_vasy_1
+
+dreal: 
+	$(ENV_S2R); $(DREAL)
+
+dreal_multi4 : multi4.cif
+	$(ENV_S2R); $(DREAL) -l multi4
+
+
+# /*------------------------------------------------------------\
+# |                                                             |
+# |                              Clean                          |
+# |                                                             |
+# \------------------------------------------------------------*/
+
+realclean : clean
+
+clean     :
+	$(RM) -f *.vst multi4_e.spi multi4_et.spi *.vbe res_*.pat *.boom *.done *.xsc *.gpl \
+                 *.ap *.drc *.dat *.gds *.cif *.rep \
+		 *.log *.out *.raw *.al
diff --git a/alliance/src/documentation/alliance-examples/multi4b/README b/alliance/src/documentation/alliance-examples/multi4b/README
new file mode 100644
index 00000000..a48203c5
--- /dev/null
+++ b/alliance/src/documentation/alliance-examples/multi4b/README
@@ -0,0 +1,118 @@
+# /*------------------------------------------------------------\
+# |                                                             |
+# | File   :                     README                         |
+# |                                                             |
+# | Author :                 Jacomme Ludovic                    |
+# |                                                             |
+# \------------------------------------------------------------*/
+
+This directory contains the VHDL description of an 4 bits multiplier and
+the associated stimuli file, and also a configuration file for IO
+placement (used during the Place and Route step).
+
+The Makefile set environement variables properly and run Alliance tools, 
+following each step of the design flow from VHDL up to real layout in a
+ pseudo 0.35 techno.
+
+The environement variable ALLIANCE_TOP as to be set.
+
+The main targets of the makefile are listed below (following the design flow).
+
+#
+# RTL SYNTHESIS
+#
+
+multi4.vbe      : Run the VHDL analyzer (VASY) on the VHDL description 
+                  (multi4.vhdl) and transform it into a boolean network (multi4.vbe).
+
+res_vasy_1.pat  : Run the VHDL simulator (ASIMUT) on multi4.vbe using the pattern/stimuli file 
+                  multi4.pat. This step checks if the multi4.vbe description is working properly.
+
+xpat_vasy       : Run the graphical waveform viewer (XPAT) on the resulting file res_vasy_1.pat 
+
+multi4_o.vbe    : Run the Boolean network optimizer (BOOM) on the multi4.vbe and 
+                  factorize/minimize boolean equations, and generate a new description
+                  multi4_o.vbe.
+
+multi4_o.vst    : Run the boolean mapper (BOOG) on the optimized description multi4_o.vbe
+                  and using the sxlib standard cell library, map all boolean nodes to
+                  an equivalent set of standard cells.
+
+xsch_multi4_o   : Run the schematic viewer (XSCH) on the structural netlist multi4_o.vst
+
+
+multi4.vst      : Run the net optimizer (LOON) on the structural description multi4_o.vst.
+                  It inserts buffers on the critical path using the sxlib standard cell library
+                  and generates a new structural netlist multi4.vst .
+
+xsch_multi4     : Run the schematic viewer (XSCH) on the bufferized netlist multi4.vst .
+                  The critical path would be displayed in red color.
+
+res_synth_1.pat : Run the VHDL simulator (ASIMUT) on the structural description multi4.vst using 
+                  the pattern/stimuli file multi4.pat and the behavioral description (.VBE) of each 
+                  cells of the standard cell library (sxlib).
+                  This step checks if the multi4.vst description is still working properly.
+
+#
+# PLACE AND ROUTE
+#
+
+multi4_p.ap     : Run the placement tool (OCP) on the structural description multi4.vst. 
+                  It generates a physical placement file (multi4_p.ap) that would be given
+                  to the router (NERO).
+
+graal_multi4_p  : Launch the physical layout editor (GRAAL) and display the result of the placement tool
+                  (multi4_p.ap).
+
+multi4.ap       : Run the router tool (NERO). Given the structural description multi4.vst, the
+                  placement file (multi4_p) and the position of external connectors (multi4.ioc) 
+                  the router generates a physical view (multi4.ap) where all nets have been routed.
+
+graal_multi4    : Launch the physical layout editor (GRAAL) and display the result of the router tool
+                  (multi4.ap).
+
+#
+# Netlist / parasitics extraction
+#
+
+multi4_e.al     : Run the hierarchical netlist extractor (COUGAR) and extracts the netlist with parasitic
+                  informations (physical parameters are taken in the techno-035.rds file).
+                  This tool generates the extracted netlist multi4_e.al
+
+xsch_multi4_e   : Run the schematic viewer (XSCH) on the hierarchical extracted netlist (multi4_e.al).
+
+multi4_et.al    : Run the netlist extractor (COUGAR) and extracts the netlist at the transistor level 
+                  with parasitics informations (multi4_et.al).
+
+xsch_multi4_et  : Run the schematic viewer (XSCH) on the extracted transistor netlist (multi4_et.al).
+
+#
+# Netlists comparison
+#
+
+lvx.done        : Run the gate netlist comparator (LVX) and checks if the extracted netlist is the same as
+                  the structural structural netlist. This step checks if the place and route phases are ok.
+
+#
+# Design rule checker
+#
+
+druc.done       : Launch the design rule checker on the layout generated by the router (multi4.ap). The design
+                  rules are specified in the RDS file (techno-symb.rds).
+                  
+
+#
+# Symbolic layout to real layout
+#
+
+multi4.cif      : Transforms the symbolic layout in lambda (multi4.ap) in a 0.35u real layout using the tool S2R.
+                  It generates a CIF file (multi4.cif).
+
+dreal_multi4    : Launch the real layout editor (DREAL) and display the result of S2R
+                  (multi4.cif).
+
+
+#
+# Clean
+
+The clean target remove all generated files ...
diff --git a/alliance/src/documentation/alliance-examples/multi4b/multi4.ioc b/alliance/src/documentation/alliance-examples/multi4b/multi4.ioc
new file mode 100644
index 00000000..998c2de5
--- /dev/null
+++ b/alliance/src/documentation/alliance-examples/multi4b/multi4.ioc
@@ -0,0 +1,34 @@
+#      Copyright (c) 1997 by Cadence. All rights reserved.      
+###################################################################
+# In each of TOP()/BOTTOM()/LEFT()/RIGHT() section, there are     #
+# placed IOs. In the IGNORE() section, the IOs are ignored        #
+# by the IOPlacer. In every section, the IO syntax could be:      #
+#        for pin:       (IOPIN iopinName.0 );                       #
+#        for pad:       iopadName orientation ;                   #
+#        for space:     SPACE  value;                             #
+# The capital words are keywords. orientation is not required.    #
+# The value is the space between the IO above and the IO below it.#
+###################################################################
+
+TOP ( # IOs are ordered from left to right
+   (IOPIN x(3).0 );
+   (IOPIN x(2).0 );
+   (IOPIN x(1).0 );
+   (IOPIN x(0).0 );
+   (IOPIN y(3).0 );
+   (IOPIN y(2).0 );
+   (IOPIN y(1).0 );
+   (IOPIN y(0).0 );
+)
+BOTTOM ( # IOs are ordered from left to right
+   (IOPIN r(7).0 );
+   (IOPIN r(6).0 );
+   (IOPIN r(5).0 );
+   (IOPIN r(4).0 );
+   (IOPIN r(3).0 );
+   (IOPIN r(2).0 );
+   (IOPIN r(1).0 );
+   (IOPIN r(0).0 );
+)
+IGNORE ( # IOs are ignored(not placed) by IO Placer
+)
diff --git a/alliance/src/documentation/alliance-examples/multi4b/multi4.pat b/alliance/src/documentation/alliance-examples/multi4b/multi4.pat
new file mode 100644
index 00000000..b3e32c3e
--- /dev/null
+++ b/alliance/src/documentation/alliance-examples/multi4b/multi4.pat
@@ -0,0 +1,471 @@
+
+in       x (3 downto 0) X;;;
+in       y (3 downto 0) X;;;
+out      r (7 downto 0) X;;;
+in       vss B;;
+in       vdd B;;
+
+begin
+
+-- Pattern description :
+--         A  B   Res     V V
+
+< +10ns>: 0  0  ?**  0 1;
+< +10ns>: 0  0  ?**  0 1;
+< +10ns>: 0  1  ?**  0 1;
+< +10ns>: 0  1  ?**  0 1;
+< +10ns>: 1  0  ?**  0 1;
+< +10ns>: 1  0  ?**  0 1;
+
+< +10ns>: 1  1  ?**  0 1;
+< +10ns>: 1  1  ?**  0 1;
+< +10ns>: 1  2  ?**  0 1;
+< +10ns>: 1  2  ?**  0 1;
+< +10ns>: 1  3  ?**  0 1;
+< +10ns>: 1  3  ?**  0 1;
+< +10ns>: 1  4  ?**  0 1;
+< +10ns>: 1  4  ?**  0 1;
+< +10ns>: 1  5  ?**  0 1;
+< +10ns>: 1  5  ?**  0 1;
+< +10ns>: 1  6  ?**  0 1;
+< +10ns>: 1  6  ?**  0 1;
+< +10ns>: 1  7  ?**  0 1;
+< +10ns>: 1  7  ?**  0 1;
+< +10ns>: 1  8  ?**  0 1;
+< +10ns>: 1  8  ?**  0 1;
+< +10ns>: 1  9  ?**  0 1;
+< +10ns>: 1  9  ?**  0 1;
+< +10ns>: 1  a  ?**  0 1;
+< +10ns>: 1  a  ?**  0 1;
+< +10ns>: 1  b  ?**  0 1;
+< +10ns>: 1  b  ?**  0 1;
+< +10ns>: 1  c  ?**  0 1;
+< +10ns>: 1  c  ?**  0 1;
+< +10ns>: 1  d  ?**  0 1;
+< +10ns>: 1  d  ?**  0 1;
+< +10ns>: 1  e  ?**  0 1;
+< +10ns>: 1  e  ?**  0 1;
+< +10ns>: 1  f  ?**  0 1;
+< +10ns>: 1  f  ?**  0 1;
+< +10ns>: 2  1  ?**  0 1;
+< +10ns>: 2  1  ?**  0 1;
+< +10ns>: 2  2  ?**  0 1;
+< +10ns>: 2  2  ?**  0 1;
+< +10ns>: 2  3  ?**  0 1;
+< +10ns>: 2  3  ?**  0 1;
+< +10ns>: 2  4  ?**  0 1;
+< +10ns>: 2  4  ?**  0 1;
+< +10ns>: 2  5  ?**  0 1;
+< +10ns>: 2  5  ?**  0 1;
+< +10ns>: 2  6  ?**  0 1;
+< +10ns>: 2  6  ?**  0 1;
+< +10ns>: 2  7  ?**  0 1;
+< +10ns>: 2  7  ?**  0 1;
+< +10ns>: 2  8  ?**  0 1;
+< +10ns>: 2  8  ?**  0 1;
+< +10ns>: 2  9  ?**  0 1;
+< +10ns>: 2  9  ?**  0 1;
+< +10ns>: 2  a  ?**  0 1;
+< +10ns>: 2  a  ?**  0 1;
+< +10ns>: 2  b  ?**  0 1;
+< +10ns>: 2  b  ?**  0 1;
+< +10ns>: 2  c  ?**  0 1;
+< +10ns>: 2  c  ?**  0 1;
+< +10ns>: 2  d  ?**  0 1;
+< +10ns>: 2  d  ?**  0 1;
+< +10ns>: 2  e  ?**  0 1;
+< +10ns>: 2  e  ?**  0 1;
+< +10ns>: 2  f  ?**  0 1;
+< +10ns>: 2  f  ?**  0 1;
+< +10ns>: 3  1  ?**  0 1;
+< +10ns>: 3  1  ?**  0 1;
+< +10ns>: 3  2  ?**  0 1;
+< +10ns>: 3  2  ?**  0 1;
+< +10ns>: 3  3  ?**  0 1;
+< +10ns>: 3  3  ?**  0 1;
+< +10ns>: 3  4  ?**  0 1;
+< +10ns>: 3  4  ?**  0 1;
+< +10ns>: 3  5  ?**  0 1;
+< +10ns>: 3  5  ?**  0 1;
+< +10ns>: 3  6  ?**  0 1;
+< +10ns>: 3  6  ?**  0 1;
+< +10ns>: 3  7  ?**  0 1;
+< +10ns>: 3  7  ?**  0 1;
+< +10ns>: 3  8  ?**  0 1;
+< +10ns>: 3  8  ?**  0 1;
+< +10ns>: 3  9  ?**  0 1;
+< +10ns>: 3  9  ?**  0 1;
+< +10ns>: 3  a  ?**  0 1;
+< +10ns>: 3  a  ?**  0 1;
+< +10ns>: 3  b  ?**  0 1;
+< +10ns>: 3  b  ?**  0 1;
+< +10ns>: 3  c  ?**  0 1;
+< +10ns>: 3  c  ?**  0 1;
+< +10ns>: 3  d  ?**  0 1;
+< +10ns>: 3  d  ?**  0 1;
+< +10ns>: 3  e  ?**  0 1;
+< +10ns>: 3  e  ?**  0 1;
+< +10ns>: 3  f  ?**  0 1;
+< +10ns>: 3  f  ?**  0 1;
+< +10ns>: 4  1  ?**  0 1;
+< +10ns>: 4  1  ?**  0 1;
+< +10ns>: 4  2  ?**  0 1;
+< +10ns>: 4  2  ?**  0 1;
+< +10ns>: 4  3  ?**  0 1;
+< +10ns>: 4  3  ?**  0 1;
+< +10ns>: 4  4  ?**  0 1;
+< +10ns>: 4  4  ?**  0 1;
+< +10ns>: 4  5  ?**  0 1;
+< +10ns>: 4  5  ?**  0 1;
+< +10ns>: 4  6  ?**  0 1;
+< +10ns>: 4  6  ?**  0 1;
+< +10ns>: 4  7  ?**  0 1;
+< +10ns>: 4  7  ?**  0 1;
+< +10ns>: 4  8  ?**  0 1;
+< +10ns>: 4  8  ?**  0 1;
+< +10ns>: 4  9  ?**  0 1;
+< +10ns>: 4  9  ?**  0 1;
+< +10ns>: 4  a  ?**  0 1;
+< +10ns>: 4  a  ?**  0 1;
+< +10ns>: 4  b  ?**  0 1;
+< +10ns>: 4  b  ?**  0 1;
+< +10ns>: 4  c  ?**  0 1;
+< +10ns>: 4  c  ?**  0 1;
+< +10ns>: 4  d  ?**  0 1;
+< +10ns>: 4  d  ?**  0 1;
+< +10ns>: 4  e  ?**  0 1;
+< +10ns>: 4  e  ?**  0 1;
+< +10ns>: 4  f  ?**  0 1;
+< +10ns>: 4  f  ?**  0 1;
+< +10ns>: 5  1  ?**  0 1;
+< +10ns>: 5  1  ?**  0 1;
+< +10ns>: 5  2  ?**  0 1;
+< +10ns>: 5  2  ?**  0 1;
+< +10ns>: 5  3  ?**  0 1;
+< +10ns>: 5  3  ?**  0 1;
+< +10ns>: 5  4  ?**  0 1;
+< +10ns>: 5  4  ?**  0 1;
+< +10ns>: 5  5  ?**  0 1;
+< +10ns>: 5  5  ?**  0 1;
+< +10ns>: 5  6  ?**  0 1;
+< +10ns>: 5  6  ?**  0 1;
+< +10ns>: 5  7  ?**  0 1;
+< +10ns>: 5  7  ?**  0 1;
+< +10ns>: 5  8  ?**  0 1;
+< +10ns>: 5  8  ?**  0 1;
+< +10ns>: 5  9  ?**  0 1;
+< +10ns>: 5  9  ?**  0 1;
+< +10ns>: 5  a  ?**  0 1;
+< +10ns>: 5  a  ?**  0 1;
+< +10ns>: 5  b  ?**  0 1;
+< +10ns>: 5  b  ?**  0 1;
+< +10ns>: 5  c  ?**  0 1;
+< +10ns>: 5  c  ?**  0 1;
+< +10ns>: 5  d  ?**  0 1;
+< +10ns>: 5  d  ?**  0 1;
+< +10ns>: 5  e  ?**  0 1;
+< +10ns>: 5  e  ?**  0 1;
+< +10ns>: 5  f  ?**  0 1;
+< +10ns>: 5  f  ?**  0 1;
+< +10ns>: 6  1  ?**  0 1;
+< +10ns>: 6  1  ?**  0 1;
+< +10ns>: 6  2  ?**  0 1;
+< +10ns>: 6  2  ?**  0 1;
+< +10ns>: 6  3  ?**  0 1;
+< +10ns>: 6  3  ?**  0 1;
+< +10ns>: 6  4  ?**  0 1;
+< +10ns>: 6  4  ?**  0 1;
+< +10ns>: 6  5  ?**  0 1;
+< +10ns>: 6  5  ?**  0 1;
+< +10ns>: 6  6  ?**  0 1;
+< +10ns>: 6  6  ?**  0 1;
+< +10ns>: 6  7  ?**  0 1;
+< +10ns>: 6  7  ?**  0 1;
+< +10ns>: 6  8  ?**  0 1;
+< +10ns>: 6  8  ?**  0 1;
+< +10ns>: 6  9  ?**  0 1;
+< +10ns>: 6  9  ?**  0 1;
+< +10ns>: 6  a  ?**  0 1;
+< +10ns>: 6  a  ?**  0 1;
+< +10ns>: 6  b  ?**  0 1;
+< +10ns>: 6  b  ?**  0 1;
+< +10ns>: 6  c  ?**  0 1;
+< +10ns>: 6  c  ?**  0 1;
+< +10ns>: 6  d  ?**  0 1;
+< +10ns>: 6  d  ?**  0 1;
+< +10ns>: 6  e  ?**  0 1;
+< +10ns>: 6  e  ?**  0 1;
+< +10ns>: 6  f  ?**  0 1;
+< +10ns>: 6  f  ?**  0 1;
+< +10ns>: 7  1  ?**  0 1;
+< +10ns>: 7  1  ?**  0 1;
+< +10ns>: 7  2  ?**  0 1;
+< +10ns>: 7  2  ?**  0 1;
+< +10ns>: 7  3  ?**  0 1;
+< +10ns>: 7  3  ?**  0 1;
+< +10ns>: 7  4  ?**  0 1;
+< +10ns>: 7  4  ?**  0 1;
+< +10ns>: 7  5  ?**  0 1;
+< +10ns>: 7  5  ?**  0 1;
+< +10ns>: 7  6  ?**  0 1;
+< +10ns>: 7  6  ?**  0 1;
+< +10ns>: 7  7  ?**  0 1;
+< +10ns>: 7  7  ?**  0 1;
+< +10ns>: 7  8  ?**  0 1;
+< +10ns>: 7  8  ?**  0 1;
+< +10ns>: 7  9  ?**  0 1;
+< +10ns>: 7  9  ?**  0 1;
+< +10ns>: 7  a  ?**  0 1;
+< +10ns>: 7  a  ?**  0 1;
+< +10ns>: 7  b  ?**  0 1;
+< +10ns>: 7  b  ?**  0 1;
+< +10ns>: 7  c  ?**  0 1;
+< +10ns>: 7  c  ?**  0 1;
+< +10ns>: 7  d  ?**  0 1;
+< +10ns>: 7  d  ?**  0 1;
+< +10ns>: 7  e  ?**  0 1;
+< +10ns>: 7  e  ?**  0 1;
+< +10ns>: 7  f  ?**  0 1;
+< +10ns>: 7  f  ?**  0 1;
+< +10ns>: 8  1  ?**  0 1;
+< +10ns>: 8  1  ?**  0 1;
+< +10ns>: 8  2  ?**  0 1;
+< +10ns>: 8  2  ?**  0 1;
+< +10ns>: 8  3  ?**  0 1;
+< +10ns>: 8  3  ?**  0 1;
+< +10ns>: 8  4  ?**  0 1;
+< +10ns>: 8  4  ?**  0 1;
+< +10ns>: 8  5  ?**  0 1;
+< +10ns>: 8  5  ?**  0 1;
+< +10ns>: 8  6  ?**  0 1;
+< +10ns>: 8  6  ?**  0 1;
+< +10ns>: 8  7  ?**  0 1;
+< +10ns>: 8  7  ?**  0 1;
+< +10ns>: 8  8  ?**  0 1;
+< +10ns>: 8  8  ?**  0 1;
+< +10ns>: 8  9  ?**  0 1;
+< +10ns>: 8  9  ?**  0 1;
+< +10ns>: 8  a  ?**  0 1;
+< +10ns>: 8  a  ?**  0 1;
+< +10ns>: 8  b  ?**  0 1;
+< +10ns>: 8  b  ?**  0 1;
+< +10ns>: 8  c  ?**  0 1;
+< +10ns>: 8  c  ?**  0 1;
+< +10ns>: 8  d  ?**  0 1;
+< +10ns>: 8  d  ?**  0 1;
+< +10ns>: 8  e  ?**  0 1;
+< +10ns>: 8  e  ?**  0 1;
+< +10ns>: 8  f  ?**  0 1;
+< +10ns>: 8  f  ?**  0 1;
+< +10ns>: 9  1  ?**  0 1;
+< +10ns>: 9  1  ?**  0 1;
+< +10ns>: 9  2  ?**  0 1;
+< +10ns>: 9  2  ?**  0 1;
+< +10ns>: 9  3  ?**  0 1;
+< +10ns>: 9  3  ?**  0 1;
+< +10ns>: 9  4  ?**  0 1;
+< +10ns>: 9  4  ?**  0 1;
+< +10ns>: 9  5  ?**  0 1;
+< +10ns>: 9  5  ?**  0 1;
+< +10ns>: 9  6  ?**  0 1;
+< +10ns>: 9  6  ?**  0 1;
+< +10ns>: 9  7  ?**  0 1;
+< +10ns>: 9  7  ?**  0 1;
+< +10ns>: 9  8  ?**  0 1;
+< +10ns>: 9  8  ?**  0 1;
+< +10ns>: 9  9  ?**  0 1;
+< +10ns>: 9  9  ?**  0 1;
+< +10ns>: 9  a  ?**  0 1;
+< +10ns>: 9  a  ?**  0 1;
+< +10ns>: 9  b  ?**  0 1;
+< +10ns>: 9  b  ?**  0 1;
+< +10ns>: 9  c  ?**  0 1;
+< +10ns>: 9  c  ?**  0 1;
+< +10ns>: 9  d  ?**  0 1;
+< +10ns>: 9  d  ?**  0 1;
+< +10ns>: 9  e  ?**  0 1;
+< +10ns>: 9  e  ?**  0 1;
+< +10ns>: 9  f  ?**  0 1;
+< +10ns>: 9  f  ?**  0 1;
+< +10ns>: a  1  ?**  0 1;
+< +10ns>: a  1  ?**  0 1;
+< +10ns>: a  2  ?**  0 1;
+< +10ns>: a  2  ?**  0 1;
+< +10ns>: a  3  ?**  0 1;
+< +10ns>: a  3  ?**  0 1;
+< +10ns>: a  4  ?**  0 1;
+< +10ns>: a  4  ?**  0 1;
+< +10ns>: a  5  ?**  0 1;
+< +10ns>: a  5  ?**  0 1;
+< +10ns>: a  6  ?**  0 1;
+< +10ns>: a  6  ?**  0 1;
+< +10ns>: a  7  ?**  0 1;
+< +10ns>: a  7  ?**  0 1;
+< +10ns>: a  8  ?**  0 1;
+< +10ns>: a  8  ?**  0 1;
+< +10ns>: a  9  ?**  0 1;
+< +10ns>: a  9  ?**  0 1;
+< +10ns>: a  a  ?**  0 1;
+< +10ns>: a  a  ?**  0 1;
+< +10ns>: a  b  ?**  0 1;
+< +10ns>: a  b  ?**  0 1;
+< +10ns>: a  c  ?**  0 1;
+< +10ns>: a  c  ?**  0 1;
+< +10ns>: a  d  ?**  0 1;
+< +10ns>: a  d  ?**  0 1;
+< +10ns>: a  e  ?**  0 1;
+< +10ns>: a  e  ?**  0 1;
+< +10ns>: a  f  ?**  0 1;
+< +10ns>: a  f  ?**  0 1;
+< +10ns>: b  1  ?**  0 1;
+< +10ns>: b  1  ?**  0 1;
+< +10ns>: b  2  ?**  0 1;
+< +10ns>: b  2  ?**  0 1;
+< +10ns>: b  3  ?**  0 1;
+< +10ns>: b  3  ?**  0 1;
+< +10ns>: b  4  ?**  0 1;
+< +10ns>: b  4  ?**  0 1;
+< +10ns>: b  5  ?**  0 1;
+< +10ns>: b  5  ?**  0 1;
+< +10ns>: b  6  ?**  0 1;
+< +10ns>: b  6  ?**  0 1;
+< +10ns>: b  7  ?**  0 1;
+< +10ns>: b  7  ?**  0 1;
+< +10ns>: b  8  ?**  0 1;
+< +10ns>: b  8  ?**  0 1;
+< +10ns>: b  9  ?**  0 1;
+< +10ns>: b  9  ?**  0 1;
+< +10ns>: b  a  ?**  0 1;
+< +10ns>: b  a  ?**  0 1;
+< +10ns>: b  b  ?**  0 1;
+< +10ns>: b  b  ?**  0 1;
+< +10ns>: b  c  ?**  0 1;
+< +10ns>: b  c  ?**  0 1;
+< +10ns>: b  d  ?**  0 1;
+< +10ns>: b  d  ?**  0 1;
+< +10ns>: b  e  ?**  0 1;
+< +10ns>: b  e  ?**  0 1;
+< +10ns>: b  f  ?**  0 1;
+< +10ns>: b  f  ?**  0 1;
+< +10ns>: c  1  ?**  0 1;
+< +10ns>: c  1  ?**  0 1;
+< +10ns>: c  2  ?**  0 1;
+< +10ns>: c  2  ?**  0 1;
+< +10ns>: c  3  ?**  0 1;
+< +10ns>: c  3  ?**  0 1;
+< +10ns>: c  4  ?**  0 1;
+< +10ns>: c  4  ?**  0 1;
+< +10ns>: c  5  ?**  0 1;
+< +10ns>: c  5  ?**  0 1;
+< +10ns>: c  6  ?**  0 1;
+< +10ns>: c  6  ?**  0 1;
+< +10ns>: c  7  ?**  0 1;
+< +10ns>: c  7  ?**  0 1;
+< +10ns>: c  8  ?**  0 1;
+< +10ns>: c  8  ?**  0 1;
+< +10ns>: c  9  ?**  0 1;
+< +10ns>: c  9  ?**  0 1;
+< +10ns>: c  a  ?**  0 1;
+< +10ns>: c  a  ?**  0 1;
+< +10ns>: c  b  ?**  0 1;
+< +10ns>: c  b  ?**  0 1;
+< +10ns>: c  c  ?**  0 1;
+< +10ns>: c  c  ?**  0 1;
+< +10ns>: c  d  ?**  0 1;
+< +10ns>: c  d  ?**  0 1;
+< +10ns>: c  e  ?**  0 1;
+< +10ns>: c  e  ?**  0 1;
+< +10ns>: c  f  ?**  0 1;
+< +10ns>: c  f  ?**  0 1;
+< +10ns>: d  1  ?**  0 1;
+< +10ns>: d  1  ?**  0 1;
+< +10ns>: d  2  ?**  0 1;
+< +10ns>: d  2  ?**  0 1;
+< +10ns>: d  3  ?**  0 1;
+< +10ns>: d  3  ?**  0 1;
+< +10ns>: d  4  ?**  0 1;
+< +10ns>: d  4  ?**  0 1;
+< +10ns>: d  5  ?**  0 1;
+< +10ns>: d  5  ?**  0 1;
+< +10ns>: d  6  ?**  0 1;
+< +10ns>: d  6  ?**  0 1;
+< +10ns>: d  7  ?**  0 1;
+< +10ns>: d  7  ?**  0 1;
+< +10ns>: d  8  ?**  0 1;
+< +10ns>: d  8  ?**  0 1;
+< +10ns>: d  9  ?**  0 1;
+< +10ns>: d  9  ?**  0 1;
+< +10ns>: d  a  ?**  0 1;
+< +10ns>: d  a  ?**  0 1;
+< +10ns>: d  b  ?**  0 1;
+< +10ns>: d  b  ?**  0 1;
+< +10ns>: d  c  ?**  0 1;
+< +10ns>: d  c  ?**  0 1;
+< +10ns>: d  d  ?**  0 1;
+< +10ns>: d  d  ?**  0 1;
+< +10ns>: d  e  ?**  0 1;
+< +10ns>: d  e  ?**  0 1;
+< +10ns>: d  f  ?**  0 1;
+< +10ns>: d  f  ?**  0 1;
+< +10ns>: e  1  ?**  0 1;
+< +10ns>: e  1  ?**  0 1;
+< +10ns>: e  2  ?**  0 1;
+< +10ns>: e  2  ?**  0 1;
+< +10ns>: e  3  ?**  0 1;
+< +10ns>: e  3  ?**  0 1;
+< +10ns>: e  4  ?**  0 1;
+< +10ns>: e  4  ?**  0 1;
+< +10ns>: e  5  ?**  0 1;
+< +10ns>: e  5  ?**  0 1;
+< +10ns>: e  6  ?**  0 1;
+< +10ns>: e  6  ?**  0 1;
+< +10ns>: e  7  ?**  0 1;
+< +10ns>: e  7  ?**  0 1;
+< +10ns>: e  8  ?**  0 1;
+< +10ns>: e  8  ?**  0 1;
+< +10ns>: e  9  ?**  0 1;
+< +10ns>: e  9  ?**  0 1;
+< +10ns>: e  a  ?**  0 1;
+< +10ns>: e  a  ?**  0 1;
+< +10ns>: e  b  ?**  0 1;
+< +10ns>: e  b  ?**  0 1;
+< +10ns>: e  c  ?**  0 1;
+< +10ns>: e  c  ?**  0 1;
+< +10ns>: e  d  ?**  0 1;
+< +10ns>: e  d  ?**  0 1;
+< +10ns>: e  e  ?**  0 1;
+< +10ns>: e  e  ?**  0 1;
+< +10ns>: e  f  ?**  0 1;
+< +10ns>: e  f  ?**  0 1;
+< +10ns>: f  1  ?**  0 1;
+< +10ns>: f  1  ?**  0 1;
+< +10ns>: f  2  ?**  0 1;
+< +10ns>: f  2  ?**  0 1;
+< +10ns>: f  3  ?**  0 1;
+< +10ns>: f  3  ?**  0 1;
+< +10ns>: f  4  ?**  0 1;
+< +10ns>: f  4  ?**  0 1;
+< +10ns>: f  5  ?**  0 1;
+< +10ns>: f  5  ?**  0 1;
+< +10ns>: f  6  ?**  0 1;
+< +10ns>: f  6  ?**  0 1;
+< +10ns>: f  7  ?**  0 1;
+< +10ns>: f  7  ?**  0 1;
+< +10ns>: f  8  ?**  0 1;
+< +10ns>: f  8  ?**  0 1;
+< +10ns>: f  9  ?**  0 1;
+< +10ns>: f  9  ?**  0 1;
+< +10ns>: f  a  ?**  0 1;
+< +10ns>: f  a  ?**  0 1;
+< +10ns>: f  b  ?**  0 1;
+< +10ns>: f  b  ?**  0 1;
+< +10ns>: f  c  ?**  0 1;
+< +10ns>: f  c  ?**  0 1;
+< +10ns>: f  d  ?**  0 1;
+< +10ns>: f  d  ?**  0 1;
+< +10ns>: f  e  ?**  0 1;
+< +10ns>: f  e  ?**  0 1;
+< +10ns>: f  f  ?**  0 1;
+< +10ns>: f  f  ?**  0 1;
+
+end;
diff --git a/alliance/src/documentation/alliance-examples/multi4b/multi4.vhdl b/alliance/src/documentation/alliance-examples/multi4b/multi4.vhdl
new file mode 100644
index 00000000..1b058b8e
--- /dev/null
+++ b/alliance/src/documentation/alliance-examples/multi4b/multi4.vhdl
@@ -0,0 +1,56 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity Multi4 is
+
+
+    port ( X  : in Std_Logic_Vector(3 downto 0) ;
+           Y  : in Std_Logic_Vector(3 downto 0) ;
+           R  : out Std_Logic_Vector(7 downto 0) );
+
+end Multi4;
+
+----------------------------------------------------------------------
+
+architecture beh OF Multi4 is
+
+  signal PP1 : Std_Logic_Vector(4 downto 0);
+  signal PP2 : Std_Logic_Vector(4 downto 0);
+  signal PP3 : Std_Logic_Vector(4 downto 0);
+  signal PP4 : Std_Logic_Vector(4 downto 0);
+
+  signal PP12 : Std_Logic_Vector(5 downto 0);
+  signal PP34 : Std_Logic_Vector(5 downto 0);
+
+begin
+
+   PP1(0) <= Y(0) and X(0);
+   PP1(1) <= Y(0) and X(1);
+   PP1(2) <= Y(0) and X(2);
+   PP1(3) <= Y(0) and X(3);
+   PP1(4) <= '0';
+
+   PP2(0) <= '0';
+   PP2(1) <= Y(1) and X(0);
+   PP2(2) <= Y(1) and X(1);
+   PP2(3) <= Y(1) and X(2);
+   PP2(4) <= Y(1) and X(3);
+
+   PP3(0) <= Y(2) and X(0);
+   PP3(1) <= Y(2) and X(1);
+   PP3(2) <= Y(2) and X(2);
+   PP3(3) <= Y(2) and X(3);
+   PP3(4) <= '0';
+
+   PP4(0) <= '0';
+   PP4(1) <= Y(3) and X(0);
+   PP4(2) <= Y(3) and X(1);
+   PP4(3) <= Y(3) and X(2);
+   PP4(4) <= Y(3) and X(3);
+
+   PP12 <= PP1 + PP2;
+   PP34 <= PP3 + PP4;
+
+   R <= ("00" & PP12) + (PP34 & "00");
+
+end beh;