This commit is contained in:
The Syf Tool
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@ -440,9 +440,10 @@ figmbkrds (2) - converts MBK figure to RDS figure
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figmbkrds (3) - converts MBK figure to RDS figure
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filepath (3) - return the whole search path of a file
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flatArityExpr (3) - flattens the operators of an expression
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flatPolarityExpr (3) - translates the inverters of an expression to the level of atomic expressions
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flatablexpr (3) - merges the operators of an expression
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flatbeh (1) - Synthetizes a behavioral description from a structural description
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flatenphfig (3) - flatten a instance in a figure
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flatPolarityExpr (3) - translates the inverters of an expression to the level of atomic expressions
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flattenlofig (3) - flatten a instance in a logical figure
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fpgen (1) - Procedural language for Data-Path synthesis based upon C.
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fpmap (1) - fpga mapper of a logic level behavioural description (VHDL data flow)
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@ -577,6 +578,7 @@ lofigchain (3) - creates a netlist in terms of connectors on signals
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log (1) - logical representations for boolean functions and utilities.
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log (3) - logical representations for boolean functions and utilities.
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loins (3) - mbk logical instance
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loon (1) - Light optimizing on Nets
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losig (3) - mbk logical signal
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lotrs (3) - mbk logical transistor
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lvx (1) - Logical Versus eXtracted net-list comparator
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@ -707,6 +709,7 @@ paini (3) - PAT data structure
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paiol (3) - PAT data structure
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papat (3) - PAT data structure
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paseq (3) - PAT data structure
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pat (5) - Pattern description format
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pat2dwl, pattern translator from ALLIANCE CAD SYSTEM to HILO CAD SYSTEM
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pat_addpacom, pat_frepacom
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pat_addpaevt, pat_frepaevt
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@ -792,6 +795,7 @@ savelofig (3) - save a logical figure on disk
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savephfig (3) - save a physical figure on disk
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saverdsfig (2) - save a physical figure on disk.
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saverdsfig (3) - save a physical figure on disk.
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scapin (1) - Scan Path insertion
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sclib (5) - a portable CMOS Standard Cell Library
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scmap (1) - mapping of a behavioural description onto a standard cell library.
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scr (1) - Standard Cell Router
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@ -837,6 +841,7 @@ supportChain_listExpr (3) - returns the support of an expression in a chain_list
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supportPtype_listExpr (3) - returns the support of an expression in a ptype_list.
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swapbddvar (3) - swaps two contiguous variables.
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sxlib (5) - a portable CMOS Standard Cell Library
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syf (1) - Finite State Machine synthesizer
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tas (1) - A switch level static timing analyzer for CMOS circuits
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testbddcircuit (3) - debugs a bdd circuit.
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tie_y
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@ -907,14 +912,14 @@ viewrfmseg (2) - displays segment caracteristics in MBK and RDS format.
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viewrfmseg (3) - displays segment caracteristics in MBK and RDS format.
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viewrfmvia (2) - displays contact caracteristics in MBK and RDS format.
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viewrfmvia (3) - displays contact caracteristics in MBK and RDS format.
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vst VHDL structural subset.
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vst (5) - VHDL structural subset.
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xmbk (1) - A simple way to set alliance environnement variables
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xpat (1) - A graphical pattern viewer
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xr2_dp
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xr2_y
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xr2_dp (5)
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xr2_y (5)
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xsch (1) - A graphical schematic viewer
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xyflat (3) - compute hierarchical coordinates
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yagle (1) - Disassembly and functional abstraction of CMOS circuits
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zbli_y
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zero_dp
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zero_y
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zbli_y (5)
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zero_dp (5)
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zero_y (5)
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@ -440,9 +440,10 @@ figmbkrds (2) - converts MBK figure to RDS figure
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figmbkrds (3) - converts MBK figure to RDS figure
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filepath (3) - return the whole search path of a file
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flatArityExpr (3) - flattens the operators of an expression
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flatPolarityExpr (3) - translates the inverters of an expression to the level of atomic expressions
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flatablexpr (3) - merges the operators of an expression
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flatbeh (1) - Synthetizes a behavioral description from a structural description
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flatenphfig (3) - flatten a instance in a figure
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flatPolarityExpr (3) - translates the inverters of an expression to the level of atomic expressions
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flattenlofig (3) - flatten a instance in a logical figure
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fpgen (1) - Procedural language for Data-Path synthesis based upon C.
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fpmap (1) - fpga mapper of a logic level behavioural description (VHDL data flow)
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@ -577,6 +578,7 @@ lofigchain (3) - creates a netlist in terms of connectors on signals
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log (1) - logical representations for boolean functions and utilities.
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log (3) - logical representations for boolean functions and utilities.
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loins (3) - mbk logical instance
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loon (1) - Light optimizing on Nets
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losig (3) - mbk logical signal
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lotrs (3) - mbk logical transistor
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lvx (1) - Logical Versus eXtracted net-list comparator
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@ -707,6 +709,7 @@ paini (3) - PAT data structure
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paiol (3) - PAT data structure
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papat (3) - PAT data structure
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paseq (3) - PAT data structure
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pat (5) - Pattern description format
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pat2dwl, pattern translator from ALLIANCE CAD SYSTEM to HILO CAD SYSTEM
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pat_addpacom, pat_frepacom
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pat_addpaevt, pat_frepaevt
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@ -792,6 +795,7 @@ savelofig (3) - save a logical figure on disk
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savephfig (3) - save a physical figure on disk
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saverdsfig (2) - save a physical figure on disk.
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saverdsfig (3) - save a physical figure on disk.
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scapin (1) - Scan Path insertion
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sclib (5) - a portable CMOS Standard Cell Library
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scmap (1) - mapping of a behavioural description onto a standard cell library.
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scr (1) - Standard Cell Router
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@ -837,6 +841,7 @@ supportChain_listExpr (3) - returns the support of an expression in a chain_list
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supportPtype_listExpr (3) - returns the support of an expression in a ptype_list.
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swapbddvar (3) - swaps two contiguous variables.
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sxlib (5) - a portable CMOS Standard Cell Library
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syf (1) - Finite State Machine synthesizer
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tas (1) - A switch level static timing analyzer for CMOS circuits
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testbddcircuit (3) - debugs a bdd circuit.
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tie_y
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@ -907,14 +912,14 @@ viewrfmseg (2) - displays segment caracteristics in MBK and RDS format.
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viewrfmseg (3) - displays segment caracteristics in MBK and RDS format.
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viewrfmvia (2) - displays contact caracteristics in MBK and RDS format.
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viewrfmvia (3) - displays contact caracteristics in MBK and RDS format.
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vst VHDL structural subset.
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vst (5) - VHDL structural subset.
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xmbk (1) - A simple way to set alliance environnement variables
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xpat (1) - A graphical pattern viewer
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xr2_dp
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xr2_y
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xr2_dp (5)
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xr2_y (5)
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xsch (1) - A graphical schematic viewer
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xyflat (3) - compute hierarchical coordinates
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yagle (1) - Disassembly and functional abstraction of CMOS circuits
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zbli_y
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zero_dp
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zero_y
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zbli_y (5)
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zero_dp (5)
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zero_y (5)
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