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Generate a FIFO of regNumber words of N bits named modelname. +
How it works : +
datain0 and datain1 : the two write busses. Only one + is used to actually write the register word, it is selected by + the sel signal. +
sel : when set to '0' the datain0 is used to write + the register word, otherwise it will be datain1. +
r, rok : set r when a word is requested, rok tells + that a word has effectively been popped out of the FIFO (this is + indicate an empty FIFO). +
w, wok : set w when a word is pushed, wok tells + that the word has effectively been pushed in the FIFO (this is + indicate that the FIFO is full). +
ck : clock signal (input, 1 bit).
reset : reset signal (input, 1 bit).
r : read requested (input, 1 bits).
w : write requested (input, 1 bits).
rok : read acknowledge (output, 1 bits).
wok : write acknowledge (output, 1 bits).
sel : select the write bus (input, 1 bit).
datain0 : first write bus (input, N bits).
datain1 : second write bus (input, N bits).
dataout : read bus (output, N bits).
vdd : power.
vss : ground.
GENLIB_MACRO(DPGEN_RF1, "model_fifox8_32" + , F_BEHAV|F_PLACE + , 32 /* Words size. */ + , 8 /* Number of words. */ + ); + +GENLIB_LOINS( "model_fifox8_32" + , "instance1_fifo1_32" + , "ck" + , "r" + , "w" + , "rok" + , "wok" + , "sel" + , "datain0[31:0]" + , "datain1[31:0]" + , "dataout[31:0]" + , "vdd", "vss", NULL + ); + |
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