diff --git a/alliance/share/cells/rflib/rf_dec_bufad1r.ap b/alliance/share/cells/rflib/rf_dec_bufad1r.ap
new file mode 100644
index 00000000..94eb3154
--- /dev/null
+++ b/alliance/share/cells/rflib/rf_dec_bufad1r.ap
@@ -0,0 +1,93 @@
+V ALLIANCE : 6
+H rf_dec_bufad1r,P, 5/11/2000,10
+A 0,0,500,500
+S 100,0,100,500,120,vdd,UP,CALU3
+S 200,200,280,200,30,*,RIGHT,POLY
+S 300,200,370,200,20,*,RIGHT,ALU1
+S 250,150,320,150,20,*,RIGHT,ALU1
+S 250,100,250,400,20,*,DOWN,ALU1
+S 200,200,300,200,20,*,RIGHT,TALU2
+S 200,200,200,200,20,i,LEFT,CALU3
+S 250,200,250,200,20,nq,LEFT,CALU3
+S 300,200,300,200,20,q,LEFT,CALU3
+S 100,290,100,480,30,*,UP,NTIE
+S 100,20,100,160,30,*,DOWN,PTIE
+S 100,30,100,150,20,*,DOWN,ALU1
+S 100,300,100,470,20,*,UP,ALU1
+S 400,260,400,490,10,*,UP,PTRANS
+S 430,280,430,470,30,*,DOWN,PDIF
+S 310,280,310,470,30,*,DOWN,PDIF
+S 190,280,190,470,30,*,DOWN,PDIF
+S 340,260,340,490,10,*,UP,PTRANS
+S 370,280,370,470,30,*,DOWN,PDIF
+S 280,260,280,490,10,*,UP,PTRANS
+S 220,260,220,490,10,*,UP,PTRANS
+S 250,280,250,470,30,*,DOWN,PDIF
+S 340,10,340,140,10,*,DOWN,NTRANS
+S 400,10,400,140,10,*,DOWN,NTRANS
+S 220,10,220,140,10,*,DOWN,NTRANS
+S 280,10,280,140,10,*,DOWN,NTRANS
+S 310,30,310,120,30,*,UP,NDIF
+S 370,30,370,120,30,*,UP,NDIF
+S 190,30,190,120,30,*,UP,NDIF
+S 250,30,250,120,30,*,UP,NDIF
+S 430,30,430,120,30,*,UP,NDIF
+S 220,140,220,260,10,*,UP,POLY
+S 280,140,280,260,10,*,UP,POLY
+S 340,140,340,260,10,*,UP,POLY
+S 400,140,400,260,10,*,UP,POLY
+S 320,150,400,150,30,*,RIGHT,POLY
+S 310,300,310,450,20,*,DOWN,ALU1
+S 310,50,310,100,20,*,UP,ALU1
+S 190,50,190,100,20,*,DOWN,ALU1
+S 190,300,190,450,20,*,UP,ALU1
+S 370,100,370,400,20,*,DOWN,ALU1
+S 430,300,430,450,20,*,UP,ALU1
+S 430,50,430,100,20,*,DOWN,ALU1
+S 0,390,500,390,240,*,LEFT,NWELL
+S 0,470,500,470,60,vdd,RIGHT,CALU1
+S 0,30,500,30,60,vss,RIGHT,CALU1
+B 100,500,120,20,CONT_VIA,*
+B 100,500,120,20,CONT_VIA2,*
+V 200,200,CONT_POLY,*
+V 300,200,CONT_VIA,*
+V 250,200,CONT_VIA,*
+V 200,200,CONT_VIA,*
+V 300,200,CONT_VIA2,*
+V 250,200,CONT_VIA2,*
+V 200,200,CONT_VIA2,*
+V 100,470,CONT_BODY_N,*
+V 100,400,CONT_BODY_N,*
+V 100,350,CONT_BODY_N,*
+V 100,300,CONT_BODY_N,*
+V 100,100,CONT_BODY_P,*
+V 100,30,CONT_BODY_P,*
+V 100,150,CONT_BODY_P,*
+V 310,400,CONT_DIF_P,*
+V 370,350,CONT_DIF_P,*
+V 370,400,CONT_DIF_P,*
+V 430,400,CONT_DIF_P,*
+V 430,300,CONT_DIF_P,*
+V 430,350,CONT_DIF_P,*
+V 430,450,CONT_DIF_P,*
+V 310,300,CONT_DIF_P,*
+V 310,350,CONT_DIF_P,*
+V 190,400,CONT_DIF_P,*
+V 190,350,CONT_DIF_P,*
+V 190,300,CONT_DIF_P,*
+V 190,450,CONT_DIF_P,*
+V 250,400,CONT_DIF_P,*
+V 250,300,CONT_DIF_P,*
+V 250,350,CONT_DIF_P,*
+V 370,300,CONT_DIF_P,*
+V 310,450,CONT_DIF_P,*
+V 370,100,CONT_DIF_N,*
+V 250,100,CONT_DIF_N,*
+V 430,100,CONT_DIF_N,*
+V 430,50,CONT_DIF_N,*
+V 310,100,CONT_DIF_N,*
+V 310,50,CONT_DIF_N,*
+V 190,50,CONT_DIF_N,*
+V 190,100,CONT_DIF_N,*
+V 320,150,CONT_POLY,*
+EOF
diff --git a/alliance/share/cells/rflib/rf_dec_bufad1r.vbe b/alliance/share/cells/rflib/rf_dec_bufad1r.vbe
new file mode 100644
index 00000000..791c3a27
--- /dev/null
+++ b/alliance/share/cells/rflib/rf_dec_bufad1r.vbe
@@ -0,0 +1,21 @@
+ENTITY rf_dec_bufad1r IS
+PORT (
+  i      : in  BIT;
+  nq  	 : out BIT;
+  q  	 : out BIT;
+  vdd	 : in  BIT;
+  vss	 : in  BIT
+);
+END rf_dec_bufad1r;
+
+ARCHITECTURE VBE OF rf_dec_bufad1r IS
+
+BEGIN
+  ASSERT (vdd and not (vss))
+  REPORT "power supply is missing on rf_dec_bufad1r"
+  SEVERITY WARNING;
+
+  nq <= not i;
+  q  <= not nq;
+
+END;
diff --git a/alliance/share/cells/rflib/rf_dec_bufad2r.ap b/alliance/share/cells/rflib/rf_dec_bufad2r.ap
new file mode 100644
index 00000000..7f31206d
--- /dev/null
+++ b/alliance/share/cells/rflib/rf_dec_bufad2r.ap
@@ -0,0 +1,138 @@
+V ALLIANCE : 6
+H rf_dec_bufad2r,P, 5/11/2000,10
+A 0,0,500,500
+S 100,0,100,500,120,vdd,UP,CALU3
+S 200,200,450,200,20,*,LEFT,TALU2
+S 90,200,200,200,20,*,RIGHT,ALU1
+S 180,200,250,200,30,*,RIGHT,POLY
+S 140,150,300,150,20,*,LEFT,ALU1
+S 140,250,300,250,20,*,RIGHT,ALU1
+S 60,150,140,150,30,*,RIGHT,POLY
+S 60,250,140,250,30,*,RIGHT,POLY
+S 90,100,90,400,20,*,DOWN,ALU1
+S 250,200,250,200,20,i0,LEFT,CALU3
+S 210,250,210,400,20,*,UP,ALU1
+S 210,100,210,150,20,*,DOWN,ALU1
+S 300,150,300,250,20,*,DOWN,ALU1
+S 350,150,400,150,20,*,RIGHT,ALU1
+S 350,250,400,250,20,*,RIGHT,ALU1
+S 330,100,350,100,20,*,RIGHT,ALU1
+S 330,300,350,300,20,*,RIGHT,ALU1
+S 330,350,350,350,20,*,RIGHT,ALU1
+S 330,400,350,400,20,*,RIGHT,ALU1
+S 350,100,350,400,20,*,UP,ALU1
+S 300,200,400,200,30,*,RIGHT,POLY
+S 400,250,480,250,30,*,RIGHT,POLY
+S 400,200,400,200,20,i1,LEFT,CALU3
+S 330,280,330,470,30,*,DOWN,PDIF
+S 510,280,510,470,30,*,DOWN,PDIF
+S 420,260,420,490,10,*,UP,PTRANS
+S 390,280,390,470,30,*,DOWN,PDIF
+S 480,260,480,490,10,*,UP,PTRANS
+S 450,280,450,470,30,*,DOWN,PDIF
+S 300,260,300,490,10,*,UP,PTRANS
+S 270,280,270,470,30,*,DOWN,PDIF
+S 360,260,360,490,10,*,UP,PTRANS
+S 480,10,480,140,10,*,DOWN,NTRANS
+S 420,10,420,140,10,*,DOWN,NTRANS
+S 360,10,360,140,10,*,DOWN,NTRANS
+S 300,10,300,140,10,*,DOWN,NTRANS
+S 330,30,330,120,30,*,UP,NDIF
+S 270,30,270,120,30,*,UP,NDIF
+S 510,30,510,120,30,*,UP,NDIF
+S 450,30,450,120,30,*,UP,NDIF
+S 390,30,390,120,30,*,UP,NDIF
+S 400,150,480,150,30,*,RIGHT,POLY
+S 360,140,360,260,10,*,UP,POLY
+S 300,140,300,260,10,*,UP,POLY
+S 510,300,510,450,20,*,UP,ALU1
+S 510,50,510,100,20,*,DOWN,ALU1
+S 450,100,450,400,20,*,DOWN,ALU1
+S 270,50,270,100,20,*,DOWN,ALU1
+S 270,300,270,450,20,*,UP,ALU1
+S 0,390,500,390,240,*,LEFT,NWELL
+S 240,140,240,260,10,*,UP,POLY
+S 180,140,180,260,10,*,UP,POLY
+S 240,260,240,490,10,*,UP,PTRANS
+S 90,30,90,120,30,*,UP,NDIF
+S 30,30,30,120,30,*,UP,NDIF
+S 210,30,210,120,30,*,UP,NDIF
+S 150,30,150,120,30,*,UP,NDIF
+S 120,10,120,140,10,*,DOWN,NTRANS
+S 60,10,60,140,10,*,DOWN,NTRANS
+S 240,10,240,140,10,*,DOWN,NTRANS
+S 180,10,180,140,10,*,DOWN,NTRANS
+S 90,280,90,470,30,*,DOWN,PDIF
+S 60,260,60,490,10,*,UP,PTRANS
+S 120,260,120,490,10,*,UP,PTRANS
+S 210,280,210,470,30,*,DOWN,PDIF
+S 180,260,180,490,10,*,UP,PTRANS
+S 30,300,30,450,20,*,UP,ALU1
+S 30,50,30,100,20,*,DOWN,ALU1
+S 30,280,30,470,30,*,DOWN,PDIF
+S 150,280,150,470,30,*,DOWN,PDIF
+S 0,30,500,30,60,vss,RIGHT,CALU1
+S 0,470,500,470,60,vdd,RIGHT,CALU1
+S 200,200,200,200,20,q0,LEFT,CALU3
+S 300,200,300,200,20,nq0,LEFT,CALU3
+S 350,200,350,200,20,nq1,LEFT,CALU3
+S 450,200,450,200,20,q1,LEFT,CALU3
+B 100,500,120,20,CONT_VIA,*
+B 100,500,120,20,CONT_VIA2,*
+V 140,150,CONT_POLY,*
+V 140,250,CONT_POLY,*
+V 200,200,CONT_VIA2,*
+V 300,200,CONT_VIA2,*
+V 250,200,CONT_VIA2,*
+V 250,200,CONT_POLY,*
+V 400,200,CONT_POLY,*
+V 400,250,CONT_POLY,*
+V 300,200,CONT_VIA,*
+V 250,200,CONT_VIA,*
+V 200,200,CONT_VIA,*
+V 400,200,CONT_VIA,*
+V 450,200,CONT_VIA,*
+V 350,200,CONT_VIA,*
+V 400,200,CONT_VIA2,*
+V 450,200,CONT_VIA2,*
+V 350,200,CONT_VIA2,*
+V 270,450,CONT_DIF_P,*
+V 510,300,CONT_DIF_P,*
+V 510,350,CONT_DIF_P,*
+V 270,350,CONT_DIF_P,*
+V 270,300,CONT_DIF_P,*
+V 330,400,CONT_DIF_P,*
+V 330,350,CONT_DIF_P,*
+V 330,300,CONT_DIF_P,*
+V 270,400,CONT_DIF_P,*
+V 450,400,CONT_DIF_P,*
+V 450,350,CONT_DIF_P,*
+V 450,300,CONT_DIF_P,*
+V 390,450,CONT_DIF_P,*
+V 510,450,CONT_DIF_P,*
+V 510,400,CONT_DIF_P,*
+V 450,100,CONT_DIF_N,*
+V 390,50,CONT_DIF_N,*
+V 510,100,CONT_DIF_N,*
+V 510,50,CONT_DIF_N,*
+V 330,100,CONT_DIF_N,*
+V 270,50,CONT_DIF_N,*
+V 270,100,CONT_DIF_N,*
+V 400,150,CONT_POLY,*
+V 90,100,CONT_DIF_N,*
+V 210,100,CONT_DIF_N,*
+V 210,400,CONT_DIF_P,*
+V 210,350,CONT_DIF_P,*
+V 210,300,CONT_DIF_P,*
+V 90,350,CONT_DIF_P,*
+V 90,300,CONT_DIF_P,*
+V 90,400,CONT_DIF_P,*
+V 30,450,CONT_DIF_P,*
+V 30,100,CONT_DIF_N,*
+V 30,50,CONT_DIF_N,*
+V 30,300,CONT_DIF_P,*
+V 30,350,CONT_DIF_P,*
+V 30,400,CONT_DIF_P,*
+V 150,450,CONT_DIF_P,*
+V 150,50,CONT_DIF_N,*
+EOF
diff --git a/alliance/share/cells/rflib/rf_dec_bufad2r.vbe b/alliance/share/cells/rflib/rf_dec_bufad2r.vbe
new file mode 100644
index 00000000..05f71d9d
--- /dev/null
+++ b/alliance/share/cells/rflib/rf_dec_bufad2r.vbe
@@ -0,0 +1,26 @@
+ENTITY rf_dec_bufad2r IS
+PORT (
+  i0     : in  BIT;
+  i1     : in  BIT;
+  nq0  	 : out BIT;
+  q0   	 : out BIT;
+  nq1  	 : out BIT;
+  q1   	 : out BIT;
+  vdd	 : in  BIT;
+  vss	 : in  BIT
+);
+END rf_dec_bufad2r;
+
+ARCHITECTURE VBE OF rf_dec_bufad2r IS
+
+BEGIN
+  ASSERT (vdd and not (vss))
+  REPORT "power supply is missing on rf_dec_bufad2r"
+  SEVERITY WARNING;
+
+  nq0 <= not i0;
+  q0  <= not nq0;
+  nq1 <= not i1;
+  q1  <= not nq1;
+
+END;
diff --git a/alliance/share/cells/rflib/rf_fifo_buf.ap b/alliance/share/cells/rflib/rf_fifo_buf.ap
new file mode 100644
index 00000000..bf428a10
--- /dev/null
+++ b/alliance/share/cells/rflib/rf_fifo_buf.ap
@@ -0,0 +1,210 @@
+V ALLIANCE : 6
+H rf_fifo_buf,P, 6/11/2000,10
+A 0,0,500,1000
+S 0,530,500,530,60,vdd,RIGHT,CALU1
+S 0,470,500,470,60,vdd,RIGHT,CALU1
+S 0,610,540,610,240,*,RIGHT,NWELL
+S 0,390,540,390,240,*,RIGHT,NWELL
+S 50,100,50,400,20,xcks,DOWN,CALU1
+S 350,100,350,400,20,xckm,DOWN,CALU1
+S 250,600,250,900,20,nw,DOWN,CALU1
+S 280,750,300,750,30,*,RIGHT,POLY
+S 300,750,300,750,20,w,LEFT,CALU2
+S 50,600,50,900,20,nr,DOWN,CALU1
+S 80,850,100,850,30,*,RIGHT,POLY
+S 100,850,100,850,20,r,LEFT,CALU2
+S 110,880,110,970,30,*,DOWN,NDIF
+S 110,900,110,950,20,*,DOWN,ALU1
+S 80,740,80,860,10,*,DOWN,POLY
+S 80,860,80,990,10,*,DOWN,NTRANS
+S 50,880,50,970,30,*,UP,NDIF
+S 400,400,430,400,20,*,RIGHT,ALU1
+S 400,350,440,350,20,*,RIGHT,ALU1
+S 400,300,440,300,20,*,RIGHT,ALU1
+S 400,150,440,150,20,*,RIGHT,ALU1
+S 400,100,440,100,20,*,RIGHT,ALU1
+S 400,100,400,400,20,xreset,DOWN,CALU1
+S 450,250,470,250,30,*,RIGHT,POLY
+S 470,190,470,260,10,*,DOWN,POLY
+S 280,740,280,810,10,*,DOWN,POLY
+S 140,390,200,390,10,*,RIGHT,POLY
+S 200,110,260,110,10,*,RIGHT,POLY
+S 200,100,200,100,20,ckm,LEFT,CALU2
+S 200,400,200,400,20,cks,LEFT,CALU2
+S 300,200,320,200,30,*,RIGHT,POLY
+S 80,200,100,200,30,*,RIGHT,POLY
+S 230,200,300,200,20,*,RIGHT,ALU1
+S 320,190,320,260,10,*,DOWN,POLY
+S 260,190,260,260,10,*,DOWN,POLY
+S 230,150,230,350,20,*,DOWN,ALU1
+S 260,110,260,190,10,*,DOWN,NTRANS
+S 230,130,230,170,30,*,UP,NDIF
+S 230,280,230,370,30,*,DOWN,PDIF
+S 260,260,260,390,10,*,UP,PTRANS
+S 290,280,290,470,30,*,UP,PDIF
+S 320,260,320,490,10,*,UP,PTRANS
+S 350,280,350,470,30,*,DOWN,PDIF
+S 320,60,320,190,10,*,DOWN,NTRANS
+S 290,40,290,170,30,*,UP,NDIF
+S 350,80,350,170,30,*,UP,NDIF
+S 290,300,290,450,20,*,DOWN,ALU1
+S 290,50,290,150,20,*,DOWN,ALU1
+S 140,190,140,260,10,*,DOWN,POLY
+S 170,150,170,350,20,*,DOWN,ALU1
+S 140,110,140,190,10,*,DOWN,NTRANS
+S 170,130,170,170,30,*,UP,NDIF
+S 80,190,80,260,10,*,DOWN,POLY
+S 100,200,170,200,20,*,RIGHT,ALU1
+S 170,280,170,370,30,*,DOWN,PDIF
+S 140,260,140,390,10,*,UP,PTRANS
+S 110,40,110,170,30,*,UP,NDIF
+S 110,50,110,150,20,*,DOWN,ALU1
+S 500,50,500,150,20,*,DOWN,ALU1
+S 500,40,500,170,30,*,UP,NDIF
+S 80,60,80,190,10,*,DOWN,NTRANS
+S 470,60,470,190,10,*,DOWN,NTRANS
+S 50,80,50,170,30,*,UP,NDIF
+S 440,80,440,170,30,*,UP,NDIF
+S 80,260,80,490,10,*,UP,PTRANS
+S 50,280,50,470,30,*,DOWN,PDIF
+S 110,280,110,470,30,*,UP,PDIF
+S 470,260,470,490,10,*,UP,PTRANS
+S 500,280,500,470,30,*,UP,PDIF
+S 440,280,440,470,30,*,DOWN,PDIF
+S 110,300,110,450,20,*,DOWN,ALU1
+S 500,300,500,450,20,*,DOWN,ALU1
+S 280,510,280,740,10,*,UP,PTRANS
+S 250,530,250,720,30,*,DOWN,PDIF
+S 310,530,310,720,30,*,UP,PDIF
+S 280,810,280,940,10,*,DOWN,NTRANS
+S 310,830,310,960,30,*,DOWN,NDIF
+S 250,830,250,920,30,*,UP,NDIF
+S 310,850,310,950,20,*,DOWN,ALU1
+S 310,550,310,700,20,*,DOWN,ALU1
+S 50,530,50,720,30,*,DOWN,PDIF
+S 80,510,80,740,10,*,UP,PTRANS
+S 110,530,110,720,30,*,UP,PDIF
+S 110,550,110,700,20,*,DOWN,ALU1
+S 500,550,500,700,20,*,DOWN,ALU1
+S 440,530,440,720,30,*,DOWN,PDIF
+S 500,530,500,720,30,*,UP,PDIF
+S 470,510,470,740,10,*,UP,PTRANS
+S 0,30,500,30,60,vss,RIGHT,CALU1
+S 0,970,500,970,60,vss,RIGHT,CALU1
+S 470,740,470,860,10,*,DOWN,POLY
+S 400,800,400,800,20,reset,LEFT,CALU2
+S 400,800,470,800,30,*,RIGHT,POLY
+S 440,830,440,920,30,*,UP,NDIF
+S 470,810,470,940,10,*,DOWN,NTRANS
+S 500,830,500,960,30,*,DOWN,NDIF
+S 500,850,500,950,20,*,DOWN,ALU1
+S 450,250,450,900,20,nreset,DOWN,CALU3
+S 450,600,450,900,20,*,DOWN,ALU1
+V 250,970,CONT_BODY_P,*
+V 370,970,CONT_BODY_P,*
+V 300,750,CONT_VIA,*
+V 300,750,CONT_POLY,*
+V 100,850,CONT_VIA,*
+V 100,850,CONT_POLY,*
+V 110,950,CONT_DIF_N,*
+V 110,900,CONT_DIF_N,*
+V 50,900,CONT_DIF_N,*
+V 450,600,CONT_VIA,*
+V 450,600,CONT_VIA2,*
+V 450,250,CONT_POLY,*
+V 450,250,CONT_VIA,*
+V 450,250,CONT_VIA2,*
+V 440,30,CONT_BODY_P,*
+V 350,30,CONT_BODY_P,*
+V 230,30,CONT_BODY_P,*
+V 170,30,CONT_BODY_P,*
+V 30,30,CONT_BODY_P,*
+V 230,470,CONT_BODY_N,*
+V 170,470,CONT_BODY_N,*
+V 200,100,CONT_VIA,*
+V 200,100,CONT_POLY,*
+V 200,400,CONT_VIA,*
+V 200,400,CONT_POLY,*
+V 300,200,CONT_POLY,*
+V 230,150,CONT_DIF_N,*
+V 230,350,CONT_DIF_P,*
+V 290,450,CONT_DIF_P,*
+V 290,400,CONT_DIF_P,*
+V 290,350,CONT_DIF_P,*
+V 350,400,CONT_DIF_P,*
+V 230,300,CONT_DIF_P,*
+V 350,350,CONT_DIF_P,*
+V 290,300,CONT_DIF_P,*
+V 290,50,CONT_DIF_N,*
+V 290,100,CONT_DIF_N,*
+V 290,150,CONT_DIF_N,*
+V 350,150,CONT_DIF_N,*
+V 350,100,CONT_DIF_N,*
+V 290,50,CONT_DIF_N,*
+V 170,150,CONT_DIF_N,*
+V 100,200,CONT_POLY,*
+V 170,300,CONT_DIF_P,*
+V 110,50,CONT_DIF_N,*
+V 110,50,CONT_DIF_N,*
+V 110,150,CONT_DIF_N,*
+V 110,100,CONT_DIF_N,*
+V 50,150,CONT_DIF_N,*
+V 50,100,CONT_DIF_N,*
+V 440,150,CONT_DIF_N,*
+V 440,100,CONT_DIF_N,*
+V 500,150,CONT_DIF_N,*
+V 110,400,CONT_DIF_P,*
+V 110,450,CONT_DIF_P,*
+V 50,350,CONT_DIF_P,*
+V 50,400,CONT_DIF_P,*
+V 110,300,CONT_DIF_P,*
+V 170,350,CONT_DIF_P,*
+V 110,350,CONT_DIF_P,*
+V 500,450,CONT_DIF_P,*
+V 500,400,CONT_DIF_P,*
+V 500,350,CONT_DIF_P,*
+V 500,300,CONT_DIF_P,*
+V 440,300,CONT_DIF_P,*
+V 440,350,CONT_DIF_P,*
+V 440,400,CONT_DIF_P,*
+V 310,600,CONT_DIF_P,*
+V 310,650,CONT_DIF_P,*
+V 310,700,CONT_DIF_P,*
+V 250,600,CONT_DIF_P,*
+V 250,650,CONT_DIF_P,*
+V 250,700,CONT_DIF_P,*
+V 310,550,CONT_DIF_P,*
+V 250,900,CONT_DIF_N,*
+V 250,850,CONT_DIF_N,*
+V 310,900,CONT_DIF_N,*
+V 310,950,CONT_DIF_N,*
+V 310,850,CONT_DIF_N,*
+V 50,700,CONT_DIF_P,*
+V 50,650,CONT_DIF_P,*
+V 50,600,CONT_DIF_P,*
+V 110,700,CONT_DIF_P,*
+V 110,650,CONT_DIF_P,*
+V 110,600,CONT_DIF_P,*
+V 110,550,CONT_DIF_P,*
+V 110,950,CONT_DIF_N,*
+V 500,550,CONT_DIF_P,*
+V 500,600,CONT_DIF_P,*
+V 500,650,CONT_DIF_P,*
+V 500,700,CONT_DIF_P,*
+V 440,600,CONT_DIF_P,*
+V 500,50,CONT_DIF_N,*
+V 500,100,CONT_DIF_N,*
+V 400,800,CONT_VIA,*
+V 400,800,CONT_POLY,*
+V 440,650,CONT_DIF_P,*
+V 440,700,CONT_DIF_P,*
+V 500,850,CONT_DIF_N,*
+V 500,900,CONT_DIF_N,*
+V 440,850,CONT_DIF_N,*
+V 440,900,CONT_DIF_N,*
+V 500,950,CONT_DIF_N,*
+V 440,970,CONT_BODY_P,*
+V 180,970,CONT_BODY_P,*
+V 450,900,CONT_VIA,*
+V 450,900,CONT_VIA2,*
+EOF
diff --git a/alliance/share/cells/rflib/rf_fifo_buf.vbe b/alliance/share/cells/rflib/rf_fifo_buf.vbe
new file mode 100644
index 00000000..2d64fed8
--- /dev/null
+++ b/alliance/share/cells/rflib/rf_fifo_buf.vbe
@@ -0,0 +1,33 @@
+ENTITY rf_fifo_buf IS
+PORT (
+  cks    : in  BIT;
+  ckm    : in  BIT;
+  r      : in  BIT;
+  w      : in  BIT;
+  reset  : in  BIT;
+  xcks 	 : out BIT;
+  xckm 	 : out BIT;
+  nr   	 : out BIT;
+  nw   	 : out BIT;
+  xreset : out BIT;
+  nreset : out BIT;
+  vdd	 : in  BIT;
+  vss	 : in  BIT
+);
+END rf_fifo_buf;
+
+ARCHITECTURE VBE OF rf_fifo_buf IS
+
+BEGIN
+  ASSERT (vdd and not (vss))
+  REPORT "power supply is missing on rf_fifo_clock"
+  SEVERITY WARNING;
+
+  xcks <= cks;
+  xckm <= ckm;
+  nr   <= not r;
+  nw   <= not w;
+  xreset <= reset;
+  nreset <= not reset;
+
+END;
diff --git a/alliance/share/cells/rflib/rf_fifo_clock.ap b/alliance/share/cells/rflib/rf_fifo_clock.ap
new file mode 100644
index 00000000..2e47b3ed
--- /dev/null
+++ b/alliance/share/cells/rflib/rf_fifo_clock.ap
@@ -0,0 +1,253 @@
+V ALLIANCE : 6
+H rf_fifo_clock,P, 6/11/2000,10
+A 0,0,500,1000
+S 0,530,500,530,60,vdd,RIGHT,CALU1
+S 0,470,500,470,60,vdd,RIGHT,CALU1
+S 100,400,450,400,20,*,RIGHT,TALU2
+S 300,200,400,200,20,*,RIGHT,TALU2
+S 400,200,400,600,20,*,DOWN,TALU3
+S 350,250,350,600,20,*,DOWN,TALU3
+S 450,400,450,800,20,*,DOWN,TALU3
+S 100,850,350,850,20,*,RIGHT,TALU2
+S 300,800,450,800,20,*,RIGHT,TALU2
+S 100,400,100,850,20,ckm,UP,CALU3
+S 350,850,410,850,30,*,RIGHT,POLY
+S 100,850,350,850,20,*,LEFT,ALU2
+S 300,400,300,800,20,cks,UP,CALU3
+S 350,600,400,600,20,*,RIGHT,TALU2
+S 200,700,500,700,20,ck,RIGHT,CALU2
+S 40,550,40,600,20,*,UP,ALU1
+S 50,650,50,800,20,wok,UP,CALU1
+S 400,850,440,850,20,*,RIGHT,ALU1
+S 70,510,70,690,10,*,UP,PTRANS
+S 40,530,40,670,30,*,DOWN,PDIF
+S 290,690,290,860,10,*,UP,POLY
+S 450,400,450,800,20,*,DOWN,ALU3
+S 450,800,470,800,30,*,RIGHT,POLY
+S 200,700,230,700,30,*,RIGHT,POLY
+S 230,690,230,860,10,*,DOWN,POLY
+S 400,600,400,850,20,*,UP,ALU1
+S 320,600,350,600,20,*,RIGHT,ALU1
+S 320,600,320,750,20,*,DOWN,ALU1
+S 380,650,400,650,20,*,RIGHT,ALU1
+S 410,690,410,860,10,*,DOWN,POLY
+S 470,690,470,860,10,*,UP,POLY
+S 500,550,500,650,20,*,UP,ALU1
+S 180,530,180,670,70,*,UP,PDIF
+S 180,550,180,650,20,*,UP,ALU1
+S 500,530,500,670,30,*,UP,PDIF
+S 320,530,320,670,30,*,UP,PDIF
+S 260,530,260,670,30,*,UP,PDIF
+S 290,510,290,690,10,*,UP,PTRANS
+S 380,530,380,670,30,*,UP,PDIF
+S 410,510,410,690,10,*,UP,PTRANS
+S 440,530,440,670,30,*,UP,PDIF
+S 230,510,230,690,10,*,UP,PTRANS
+S 470,510,470,690,10,*,UP,PTRANS
+S 230,860,230,930,10,*,DOWN,NTRANS
+S 290,860,290,930,10,*,DOWN,NTRANS
+S 260,880,260,910,30,*,DOWN,NDIF
+S 470,860,470,930,10,*,DOWN,NTRANS
+S 410,860,410,930,10,*,DOWN,NTRANS
+S 440,880,440,910,30,*,DOWN,NDIF
+S 0,30,500,30,60,vss,RIGHT,CALU1
+S 0,970,500,970,60,vss,RIGHT,CALU1
+S 280,190,280,260,10,*,DOWN,POLY
+S 370,80,370,120,30,*,UP,NDIF
+S 250,80,250,170,30,*,UP,NDIF
+S 310,40,310,170,30,*,UP,NDIF
+S 280,60,280,190,10,*,DOWN,NTRANS
+S 340,60,340,140,10,*,DOWN,NTRANS
+S 310,280,310,470,30,*,UP,PDIF
+S 280,260,280,490,10,*,UP,PTRANS
+S 250,280,250,470,30,*,UP,PDIF
+S 500,330,500,470,30,*,UP,PDIF
+S 500,40,500,120,30,*,UP,NDIF
+S 310,300,310,450,20,*,DOWN,ALU1
+S 500,350,500,450,20,*,DOWN,ALU1
+S 500,50,500,100,20,*,DOWN,ALU1
+S 310,50,310,150,20,*,DOWN,ALU1
+S 90,300,90,450,20,*,DOWN,ALU1
+S 90,50,90,150,20,*,DOWN,ALU1
+S 120,190,120,260,10,*,DOWN,POLY
+S 90,40,90,170,30,*,UP,NDIF
+S 150,80,150,170,30,*,UP,NDIF
+S 30,80,30,120,30,*,UP,NDIF
+S 60,60,60,140,10,*,DOWN,NTRANS
+S 120,60,120,190,10,*,DOWN,NTRANS
+S 120,260,120,490,10,*,UP,PTRANS
+S 150,280,150,470,30,*,UP,PDIF
+S 90,280,90,470,30,*,UP,PDIF
+S 500,880,500,960,30,*,DOWN,NDIF
+S 380,880,380,920,30,*,DOWN,NDIF
+S 380,880,380,960,30,*,DOWN,NDIF
+S 320,880,320,960,30,*,DOWN,NDIF
+S 320,900,320,950,20,*,DOWN,ALU1
+S 500,900,500,950,20,*,DOWN,ALU1
+S 340,260,340,390,10,*,UP,PTRANS
+S 370,280,370,370,30,*,UP,PDIF
+S 340,140,340,260,10,*,DOWN,POLY
+S 370,100,370,350,20,*,DOWN,ALU1
+S 150,100,150,400,20,*,UP,ALU1
+S 250,100,250,400,20,*,UP,ALU1
+S 440,850,440,900,20,*,DOWN,ALU1
+S 190,750,320,750,20,*,RIGHT,ALU1
+S 70,690,70,810,10,*,DOWN,POLY
+S 130,690,130,810,10,*,DOWN,POLY
+S 130,510,130,690,10,*,UP,PTRANS
+S 100,830,100,970,30,*,DOWN,NDIF
+S 40,830,40,970,30,*,DOWN,NDIF
+S 70,810,70,990,10,*,DOWN,NTRANS
+S 130,810,130,990,10,*,DOWN,NTRANS
+S 100,530,100,670,30,*,UP,PDIF
+S 40,850,100,850,20,*,RIGHT,ALU1
+S 40,900,100,900,20,*,RIGHT,ALU1
+S 180,850,180,950,20,*,DOWN,ALU1
+S 180,880,180,920,30,*,DOWN,NDIF
+S 180,830,180,970,70,*,UP,NDIF
+S 30,200,100,200,20,*,RIGHT,ALU1
+S 60,250,80,250,30,*,RIGHT,POLY
+S 100,200,120,200,30,*,LEFT,POLY
+S 80,250,100,250,20,*,RIGHT,ALU1
+S 100,250,350,250,20,*,RIGHT,ALU2
+S 350,250,350,600,20,*,DOWN,ALU3
+S 300,250,370,250,20,*,RIGHT,ALU1
+S 280,250,300,250,30,*,RIGHT,POLY
+S 320,200,340,200,30,*,RIGHT,POLY
+S 300,200,400,200,20,*,RIGHT,ALU2
+S 300,200,320,200,20,*,RIGHT,ALU1
+S 400,200,400,600,20,*,DOWN,ALU3
+S 250,400,300,400,20,*,RIGHT,ALU2
+S 100,400,150,400,20,*,RIGHT,ALU2
+S 60,260,60,390,10,*,UP,PTRANS
+S 30,280,30,370,30,*,UP,PDIF
+S 60,140,60,260,10,*,UP,POLY
+S 30,100,30,350,20,*,DOWN,ALU1
+S 130,750,190,750,30,*,RIGHT,POLY
+S 240,750,240,900,20,*,DOWN,ALU1
+S 240,900,260,900,20,*,RIGHT,ALU1
+S 100,600,100,900,20,ckok,UP,CALU1
+S 430,100,430,400,20,*,DOWN,ALU1
+S 460,140,460,310,10,*,DOWN,POLY
+S 460,310,460,440,10,*,UP,PTRANS
+S 430,80,430,120,30,*,UP,NDIF
+S 460,60,460,140,10,*,DOWN,NTRANS
+S 430,330,430,420,30,*,UP,PDIF
+S 430,400,450,400,20,*,RIGHT,ALU1
+S 480,250,500,250,20,*,RIGHT,ALU1
+S 460,250,490,250,30,*,LEFT,POLY
+S 500,250,500,700,20,ck,DOWN,CALU3
+S 100,250,500,250,20,*,RIGHT,TALU2
+S 0,610,540,610,240,*,RIGHT,NWELL
+S 0,390,540,390,240,*,RIGHT,NWELL
+V 300,800,CONT_POLY,*
+V 300,800,CONT_VIA,*
+V 300,800,CONT_VIA2,*
+V 350,850,CONT_POLY,*
+V 350,850,CONT_VIA,*
+V 100,850,CONT_VIA2,*
+V 100,650,CONT_DIF_P,*
+V 100,600,CONT_DIF_P,*
+V 40,550,CONT_DIF_P,*
+V 40,600,CONT_DIF_P,*
+V 250,30,CONT_BODY_P,*
+V 150,30,CONT_BODY_P,*
+V 450,800,CONT_POLY,*
+V 450,800,CONT_VIA,*
+V 450,800,CONT_VIA2,*
+V 500,700,CONT_VIA2,*
+V 200,700,CONT_VIA,*
+V 200,700,CONT_POLY,*
+V 350,600,CONT_VIA,*
+V 350,600,CONT_VIA2,*
+V 400,600,CONT_VIA,*
+V 400,600,CONT_VIA2,*
+V 320,600,CONT_DIF_P,*
+V 380,650,CONT_DIF_P,*
+V 320,650,CONT_DIF_P,*
+V 180,600,CONT_DIF_P,*
+V 180,650,CONT_DIF_P,*
+V 180,550,CONT_DIF_P,*
+V 440,30,CONT_BODY_P,*
+V 500,50,CONT_DIF_N,*
+V 500,50,CONT_DIF_N,*
+V 500,450,CONT_DIF_P,*
+V 500,100,CONT_DIF_N,*
+V 370,30,CONT_BODY_P,*
+V 370,100,CONT_DIF_N,*
+V 310,50,CONT_DIF_N,*
+V 310,150,CONT_DIF_N,*
+V 310,100,CONT_DIF_N,*
+V 250,100,CONT_DIF_N,*
+V 250,150,CONT_DIF_N,*
+V 310,300,CONT_DIF_P,*
+V 310,350,CONT_DIF_P,*
+V 310,400,CONT_DIF_P,*
+V 310,450,CONT_DIF_P,*
+V 250,400,CONT_DIF_P,*
+V 250,350,CONT_DIF_P,*
+V 250,300,CONT_DIF_P,*
+V 500,350,CONT_DIF_P,*
+V 500,400,CONT_DIF_P,*
+V 30,30,CONT_BODY_P,*
+V 90,100,CONT_DIF_N,*
+V 90,50,CONT_DIF_N,*
+V 90,150,CONT_DIF_N,*
+V 150,100,CONT_DIF_N,*
+V 150,150,CONT_DIF_N,*
+V 30,100,CONT_DIF_N,*
+V 90,450,CONT_DIF_P,*
+V 90,300,CONT_DIF_P,*
+V 90,350,CONT_DIF_P,*
+V 150,350,CONT_DIF_P,*
+V 150,300,CONT_DIF_P,*
+V 150,400,CONT_DIF_P,*
+V 90,400,CONT_DIF_P,*
+V 500,550,CONT_DIF_P,*
+V 500,600,CONT_DIF_P,*
+V 500,650,CONT_DIF_P,*
+V 500,950,CONT_DIF_N,*
+V 500,900,CONT_DIF_N,*
+V 440,900,CONT_DIF_N,*
+V 380,900,CONT_DIF_N,*
+V 380,950,CONT_DIF_N,*
+V 440,970,CONT_BODY_P,*
+V 260,970,CONT_BODY_P,*
+V 260,900,CONT_DIF_N,*
+V 320,900,CONT_DIF_N,*
+V 320,950,CONT_DIF_N,*
+V 370,350,CONT_DIF_P,*
+V 370,300,CONT_DIF_P,*
+V 380,480,CONT_BODY_N,*
+V 440,480,CONT_BODY_N,*
+V 190,750,CONT_POLY,*
+V 40,900,CONT_DIF_N,*
+V 40,850,CONT_DIF_N,*
+V 30,480,CONT_BODY_N,*
+V 50,750,CONT_POLY,*
+V 180,900,CONT_DIF_N,*
+V 180,950,CONT_DIF_N,*
+V 180,850,CONT_DIF_N,*
+V 100,200,CONT_POLY,*
+V 80,250,CONT_POLY,*
+V 100,250,CONT_VIA,*
+V 350,250,CONT_VIA2,*
+V 300,250,CONT_POLY,*
+V 320,200,CONT_POLY,*
+V 400,200,CONT_VIA2,*
+V 300,200,CONT_VIA,*
+V 250,400,CONT_VIA,*
+V 300,400,CONT_VIA2,*
+V 100,400,CONT_VIA2,*
+V 150,400,CONT_VIA,*
+V 30,300,CONT_DIF_P,*
+V 30,350,CONT_DIF_P,*
+V 430,100,CONT_DIF_N,*
+V 430,400,CONT_DIF_P,*
+V 430,350,CONT_DIF_P,*
+V 450,400,CONT_VIA2,*
+V 450,400,CONT_VIA,*
+V 500,250,CONT_VIA2,*
+V 500,250,CONT_VIA,*
+V 480,250,CONT_POLY,*
+EOF
diff --git a/alliance/share/cells/rflib/rf_fifo_clock.vbe b/alliance/share/cells/rflib/rf_fifo_clock.vbe
new file mode 100644
index 00000000..27c0acf0
--- /dev/null
+++ b/alliance/share/cells/rflib/rf_fifo_clock.vbe
@@ -0,0 +1,39 @@
+ENTITY rf_fifo_clock IS
+PORT (
+  ck     : in  BIT;
+  wok    : in  BIT;
+  cks 	 : inout BIT;
+  ckm 	 : inout BIT;
+  ckok   : out BIT;
+  vdd	 : in  BIT;
+  vss	 : in  BIT
+);
+END rf_fifo_clock;
+
+ARCHITECTURE VBE OF rf_fifo_clock IS
+
+  SIGNAL nck    : BIT;
+  SIGNAL sck    : BIT;
+  SIGNAL mck    : BIT;
+  SIGNAL nsck   : BIT;
+  SIGNAL nmck   : BIT;
+
+BEGIN
+  ASSERT (vdd and not (vss))
+  REPORT "power supply is missing on rf_fifo_clock"
+  SEVERITY WARNING;
+
+  nck  <= not ck;
+  sck  <= nck nor ckm;
+  mck  <=  ck nor cks;
+  nmck <=  not mck;
+  nsck <=  not sck;
+  cks  <=  not nsck;
+  ckm  <=  not nmck;
+  ckok <= mck nand wok;
+
+--      cks <= not(ck);
+--	ckm <= ck;
+--	ckok <= ckm nand wok;
+
+END;
diff --git a/alliance/share/cells/rflib/rf_fifo_empty.ap b/alliance/share/cells/rflib/rf_fifo_empty.ap
new file mode 100644
index 00000000..d2908ef6
--- /dev/null
+++ b/alliance/share/cells/rflib/rf_fifo_empty.ap
@@ -0,0 +1,94 @@
+V ALLIANCE : 6
+H rf_fifo_empty,P,11/ 6/2000,10
+A 0,0,500,500
+S 450,150,450,400,20,empty,DOWN,CALU1
+S 100,300,100,300,20,emptynext,LEFT,CALU2
+S 90,300,120,300,30,*,RIGHT,POLY
+S 100,150,100,200,10,*,DOWN,ALU1
+S 40,200,40,400,10,*,DOWN,ALU1
+S 40,200,100,200,10,*,RIGHT,ALU1
+S 150,100,150,150,10,*,DOWN,ALU1
+S 100,150,150,150,10,*,RIGHT,ALU1
+S 40,400,90,400,10,*,LEFT,ALU1
+S 200,100,220,100,20,*,RIGHT,ALU1
+S 330,150,330,350,10,z,DOWN,ALU1
+S 220,110,300,110,10,*,RIGHT,POLY
+S 210,130,210,170,30,*,DOWN,NDIF
+S 120,140,120,360,10,*,DOWN,POLY
+S 60,140,60,360,10,*,DOWN,POLY
+S 90,380,90,470,30,*,DOWN,PDIF
+S 120,360,120,490,10,*,DOWN,PTRANS
+S 60,360,60,490,10,*,DOWN,PTRANS
+S 30,380,30,470,30,*,DOWN,PDIF
+S 150,380,150,470,30,*,DOWN,PDIF
+S 150,30,150,170,30,*,DOWN,NDIF
+S 180,110,180,190,10,*,UP,NTRANS
+S 150,200,180,200,30,*,RIGHT,POLY
+S 0,30,500,30,60,vss,RIGHT,CALU1
+S 0,470,500,470,60,vdd,RIGHT,CALU1
+S 360,190,360,310,10,*,DOWN,POLY
+S 390,30,390,170,30,*,DOWN,NDIF
+S 390,330,390,470,30,*,DOWN,PDIF
+S 180,400,230,400,50,*,RIGHT,PTRANS
+S 250,400,300,400,50,*,RIGHT,PTRANS
+S 210,300,360,300,10,*,RIGHT,POLY
+S 420,190,420,310,10,*,DOWN,POLY
+S 420,310,420,490,10,*,DOWN,PTRANS
+S 420,10,420,190,10,*,UP,NTRANS
+S 450,30,450,170,30,*,DOWN,NDIF
+S 450,330,450,470,30,*,DOWN,PDIF
+S 210,150,210,350,10,y,DOWN,ALU1
+S 400,100,400,200,10,*,DOWN,ALU1
+S 270,100,400,100,10,*,LEFT,ALU1
+S 270,100,270,350,10,t,DOWN,ALU1
+S 180,250,180,420,10,*,DOWN,POLY
+S 180,250,320,250,10,*,RIGHT,POLY
+S 0,390,500,390,240,*,RIGHT,NWELL
+S 360,310,360,390,10,*,DOWN,PTRANS
+S 330,330,330,370,30,*,DOWN,PDIF
+S 310,400,450,400,10,*,RIGHT,ALU1
+S 360,110,360,190,10,*,UP,NTRANS
+S 30,30,30,120,30,*,DOWN,NDIF
+S 90,30,90,120,30,*,DOWN,NDIF
+S 120,10,120,140,10,*,UP,NTRANS
+S 60,10,60,140,10,*,UP,NTRANS
+S 270,130,270,170,30,*,DOWN,NDIF
+S 330,130,330,170,30,*,DOWN,NDIF
+S 300,110,300,190,10,*,UP,NTRANS
+S 50,150,50,150,20,nreset,LEFT,CALU2
+S 150,200,150,200,20,ckm,LEFT,CALU2
+S 200,100,200,100,20,cks,LEFT,CALU2
+V 330,30,CONT_BODY_P,*
+V 210,30,CONT_BODY_P,*
+V 90,400,CONT_DIF_P,*
+V 150,150,CONT_DIF_N,*
+V 220,100,CONT_POLY,*
+V 200,100,CONT_VIA,*
+V 210,150,CONT_DIF_N,*
+V 50,150,CONT_POLY,*
+V 50,150,CONT_VIA,*
+V 150,200,CONT_VIA,*
+V 150,100,CONT_DIF_N,*
+V 30,50,CONT_DIF_N,*
+V 30,450,CONT_DIF_P,*
+V 150,450,CONT_DIF_P,*
+V 210,350,CONT_DIF_P,*
+V 210,450,CONT_DIF_P,*
+V 100,300,CONT_POLY,*
+V 100,300,CONT_VIA,*
+V 160,200,CONT_POLY,*
+V 390,50,CONT_DIF_N,*
+V 330,150,CONT_DIF_N,*
+V 390,450,CONT_DIF_P,*
+V 330,350,CONT_DIF_P,*
+V 270,450,CONT_DIF_P,*
+V 270,350,CONT_DIF_P,*
+V 450,350,CONT_DIF_P,*
+V 450,150,CONT_DIF_N,*
+V 400,200,CONT_POLY,*
+V 270,150,CONT_DIF_N,*
+V 320,250,CONT_POLY,*
+V 220,300,CONT_POLY,*
+V 310,400,CONT_POLY,*
+V 330,470,CONT_BODY_N,*
+EOF
diff --git a/alliance/share/cells/rflib/rf_fifo_empty.vbe b/alliance/share/cells/rflib/rf_fifo_empty.vbe
new file mode 100644
index 00000000..f0cea2dd
--- /dev/null
+++ b/alliance/share/cells/rflib/rf_fifo_empty.vbe
@@ -0,0 +1,34 @@
+ENTITY rf_fifo_empty IS
+PORT (
+  ckm 	         : in  BIT;
+  nreset         : in  BIT;
+  emptynext 	 : in  BIT;
+  cks            : in  BIT;
+  empty          : out BIT;
+  vdd	         : in  BIT;
+  vss	         : in  BIT
+);
+END rf_fifo_empty;
+
+ARCHITECTURE VBE OF rf_fifo_empty IS
+  SIGNAL latchm	 : REG_BIT REGISTER;
+  SIGNAL latchs	 : REG_BIT REGISTER;
+
+BEGIN
+  ASSERT (vdd and not (vss))
+  REPORT "power supply is missing on rf_fifo_empty"
+  SEVERITY WARNING;
+
+  label0 : BLOCK (ckm = '1')
+  BEGIN
+    latchm <= GUARDED (emptynext nand nreset);
+  END BLOCK label0;
+
+  label1 : BLOCK (cks = '1')
+  BEGIN
+    latchs <= GUARDED (not latchm);
+  END BLOCK label1;
+
+  empty <= (not latchs);
+
+END;
diff --git a/alliance/share/cells/rflib/rf_fifo_full.ap b/alliance/share/cells/rflib/rf_fifo_full.ap
new file mode 100644
index 00000000..64cf857a
--- /dev/null
+++ b/alliance/share/cells/rflib/rf_fifo_full.ap
@@ -0,0 +1,95 @@
+V ALLIANCE : 6
+H rf_fifo_full,P, 6/ 7/2000,100
+A 0,0,5000,5000
+S 900,1000,1000,1000,200,*,RIGHT,ALU1
+S 4500,1500,4500,4000,200,full,DOWN,CALU1
+S 3900,2000,4200,2000,300,*,RIGHT,POLY
+S 3300,1500,3300,3500,100,z,DOWN,ALU1
+S 1200,900,1200,2600,100,*,UP,POLY
+S 600,900,600,2600,100,*,DOWN,POLY
+S 900,2800,900,4700,300,*,DOWN,PDIF
+S 1200,2600,1200,4900,100,*,DOWN,PTRANS
+S 600,2600,600,4900,100,*,DOWN,PTRANS
+S 300,2800,300,4700,300,*,DOWN,PDIF
+S 1500,2800,1500,4700,300,*,DOWN,PDIF
+S 1000,2500,1200,2500,300,*,RIGHT,POLY
+S 300,2000,300,3000,100,*,DOWN,ALU1
+S 1600,2000,1800,2000,300,*,RIGHT,POLY
+S 2200,1100,3000,1100,100,*,RIGHT,POLY
+S 2100,1300,2100,1700,300,*,DOWN,NDIF
+S 1500,1300,1500,1700,300,*,DOWN,NDIF
+S 1800,1100,1800,1900,100,*,UP,NTRANS
+S 1500,300,1500,700,300,*,DOWN,NDIF
+S 900,300,900,1100,300,*,DOWN,NDIF
+S 1200,100,1200,900,100,*,UP,NTRANS
+S 600,100,600,900,100,*,UP,NTRANS
+S 300,300,300,700,300,*,DOWN,NDIF
+S 0,300,5000,300,600,vss,RIGHT,CALU1
+S 0,4700,5000,4700,600,vdd,RIGHT,CALU1
+S 3600,1900,3600,3100,100,*,DOWN,POLY
+S 3900,300,3900,1700,300,*,DOWN,NDIF
+S 3900,3300,3900,4700,300,*,DOWN,PDIF
+S 1800,4000,2300,4000,500,*,RIGHT,PTRANS
+S 2500,4000,3000,4000,500,*,RIGHT,PTRANS
+S 2100,3000,3600,3000,100,*,RIGHT,POLY
+S 4200,1900,4200,3100,100,*,DOWN,POLY
+S 4200,3100,4200,4900,100,*,DOWN,PTRANS
+S 4200,100,4200,1900,100,*,UP,NTRANS
+S 4500,300,4500,1700,300,*,DOWN,NDIF
+S 4500,3300,4500,4700,300,*,DOWN,PDIF
+S 2100,1500,2100,3500,100,y,DOWN,ALU1
+S 4000,1000,4000,2000,100,*,DOWN,ALU1
+S 2700,1000,4000,1000,100,*,LEFT,ALU1
+S 2700,1000,2700,3500,100,t,DOWN,ALU1
+S 1800,2500,1800,4200,100,*,DOWN,POLY
+S 1800,2500,3200,2500,100,*,RIGHT,POLY
+S 0,3900,5000,3900,2400,*,RIGHT,NWELL
+S 3600,3100,3600,3900,100,*,DOWN,PTRANS
+S 3300,3300,3300,3700,300,*,DOWN,PDIF
+S 3100,4000,4500,4000,100,*,RIGHT,ALU1
+S 3600,1100,3600,1900,100,*,UP,NTRANS
+S 2700,1300,2700,1700,300,*,DOWN,NDIF
+S 3300,1300,3300,1700,300,*,DOWN,NDIF
+S 3000,1100,3000,1900,100,*,UP,NTRANS
+S 2000,1000,2200,1000,200,*,RIGHT,ALU1
+S 500,1500,500,1500,200,reset,LEFT,CALU2
+S 1500,2000,1500,2000,200,ckm,LEFT,CALU2
+S 2000,1000,2000,1000,200,cks,LEFT,CALU2
+S 1000,2500,1000,2500,200,fullnext,LEFT,CALU2
+S 1000,1000,1000,2000,100,*,DOWN,ALU1
+S 300,2000,1000,2000,100,*,RIGHT,ALU1
+S 1000,1500,1500,1500,100,*,RIGHT,ALU1
+V 1000,2500,CONT_POLY,*
+V 1000,2500,CONT_VIA,*
+V 300,3000,CONT_DIF_P,*
+V 3300,300,CONT_BODY_P,*
+V 2100,300,CONT_BODY_P,*
+V 1600,2000,CONT_POLY,*
+V 1500,2000,CONT_VIA,*
+V 2200,1000,CONT_POLY,*
+V 500,1500,CONT_POLY,*
+V 500,1500,CONT_VIA,*
+V 2100,1500,CONT_DIF_N,*
+V 1500,1500,CONT_DIF_N,*
+V 1500,500,CONT_DIF_N,*
+V 900,1000,CONT_DIF_N,*
+V 300,500,CONT_DIF_N,*
+V 1500,4500,CONT_DIF_P,*
+V 2100,3500,CONT_DIF_P,*
+V 2100,4500,CONT_DIF_P,*
+V 3900,500,CONT_DIF_N,*
+V 3300,1500,CONT_DIF_N,*
+V 3900,4500,CONT_DIF_P,*
+V 3300,3500,CONT_DIF_P,*
+V 2700,4500,CONT_DIF_P,*
+V 2700,3500,CONT_DIF_P,*
+V 4500,3500,CONT_DIF_P,*
+V 4500,1500,CONT_DIF_N,*
+V 4000,2000,CONT_POLY,*
+V 2700,1500,CONT_DIF_N,*
+V 3200,2500,CONT_POLY,*
+V 2200,3000,CONT_POLY,*
+V 3100,4000,CONT_POLY,*
+V 3300,4700,CONT_BODY_N,*
+V 2000,1000,CONT_VIA,*
+EOF
diff --git a/alliance/share/cells/rflib/rf_fifo_full.vbe b/alliance/share/cells/rflib/rf_fifo_full.vbe
new file mode 100644
index 00000000..69a6c28c
--- /dev/null
+++ b/alliance/share/cells/rflib/rf_fifo_full.vbe
@@ -0,0 +1,34 @@
+ENTITY rf_fifo_full IS
+PORT (
+  ckm 	         : in  BIT;
+  reset          : in  BIT;
+  fullnext 	 : in  BIT;
+  cks            : in  BIT;
+  full           : out BIT;
+  vdd	         : in  BIT;
+  vss	         : in  BIT
+);
+END rf_fifo_full;
+
+ARCHITECTURE VBE OF rf_fifo_full IS
+  SIGNAL latchm	 : REG_BIT REGISTER;
+  SIGNAL latchs	 : REG_BIT REGISTER;
+
+BEGIN
+  ASSERT (vdd and not (vss))
+  REPORT "power supply is missing on rf_fifo_full"
+  SEVERITY WARNING;
+
+  label0 : BLOCK (ckm = '1')
+  BEGIN
+    latchm <= GUARDED (fullnext nor reset);
+  END BLOCK label0;
+
+  label1 : BLOCK (cks = '1')
+  BEGIN
+    latchs <= GUARDED (not latchm);
+  END BLOCK label1;
+
+  full <= (not latchs);
+
+END;
diff --git a/alliance/share/cells/rflib/rf_fifo_inc.ap b/alliance/share/cells/rflib/rf_fifo_inc.ap
new file mode 100644
index 00000000..aa9bda96
--- /dev/null
+++ b/alliance/share/cells/rflib/rf_fifo_inc.ap
@@ -0,0 +1,97 @@
+V ALLIANCE : 6
+H rf_fifo_inc,P, 6/ 7/2000,100
+A 0,0,5000,5000
+S 1100,2500,1100,3000,200,*,DOWN,ALU1
+S 1100,3000,3000,3000,200,*,RIGHT,ALU1
+S 2600,1000,2600,3000,200,*,DOWN,ALU1
+S 3000,4000,3600,4000,100,*,RIGHT,ALU1
+S 3500,4000,3800,4000,300,*,RIGHT,POLY
+S 3400,1900,4100,1900,100,*,RIGHT,ALU1
+S 3500,300,3500,700,300,*,DOWN,NDIF
+S 4100,300,4100,1100,300,*,DOWN,NDIF
+S 4100,1000,4100,4000,100,*,UP,ALU1
+S 500,1000,500,4000,200,*,UP,ALU1
+S 500,4000,500,4000,200,inc,LEFT,CALU2
+S 0,2800,0,4700,300,*,DOWN,PDIF
+S 3000,2800,3000,3700,300,*,DOWN,PDIF
+S 2400,2800,2400,3700,300,*,DOWN,PDIF
+S 3800,4100,3800,4900,100,*,UP,PTRANS
+S 3500,4300,3500,4700,300,*,UP,PDIF
+S 0,3900,5000,3900,2400,*,RIGHT,NWELL
+S 300,2600,300,4900,100,*,DOWN,PTRANS
+S 1200,2800,1200,4700,300,*,DOWN,PDIF
+S 600,2800,600,4700,300,*,DOWN,PDIF
+S 900,2600,900,4900,100,*,DOWN,PTRANS
+S 1500,2600,1500,3900,100,*,UP,PTRANS
+S 1800,2800,1800,3700,300,*,DOWN,PDIF
+S 2700,2600,2700,3900,100,*,UP,PTRANS
+S 2100,2600,2100,3900,100,*,UP,PTRANS
+S 900,600,900,1900,100,*,UP,NTRANS
+S 300,600,300,1900,100,*,UP,NTRANS
+S 1500,600,1500,1900,100,*,UP,NTRANS
+S 3800,100,3800,900,100,*,UP,NTRANS
+S 1900,600,1900,1900,100,*,UP,NTRANS
+S 2300,600,2300,1900,100,*,UP,NTRANS
+S 2600,800,2600,1700,300,*,DOWN,NDIF
+S 0,300,0,1700,300,*,DOWN,NDIF
+S 600,800,600,1700,300,*,DOWN,NDIF
+S 1200,800,1200,1700,300,*,DOWN,NDIF
+S 3800,900,3800,4100,100,*,DOWN,POLY
+S 1900,1900,1900,2600,100,*,DOWN,POLY
+S 2300,1900,3400,1900,100,*,RIGHT,POLY
+S 1500,1900,1500,2600,100,*,DOWN,POLY
+S 2700,1900,2700,2600,100,*,DOWN,POLY
+S 900,1900,900,2600,100,*,DOWN,POLY
+S 300,1900,300,2600,100,*,DOWN,POLY
+S 0,300,5000,300,600,vss,RIGHT,CALU1
+S 0,3000,0,4500,200,*,UP,ALU1
+S 0,500,0,1500,200,*,UP,ALU1
+S 1200,500,1200,1500,200,*,DOWN,ALU1
+S 0,4700,5000,4700,600,vdd,RIGHT,CALU1
+S 2400,3500,2400,4700,200,*,UP,ALU1
+S 1200,3500,1200,4500,200,*,DOWN,ALU1
+S 300,2500,1000,2500,300,*,RIGHT,POLY
+S 1500,2000,1500,2000,200,ckm,LEFT,CALU2
+S 2000,2500,2000,2500,200,nreset,LEFT,CALU2
+S 4100,3900,4100,4700,300,*,UP,PDIF
+S 3000,4000,3000,4000,200,nval,LEFT,CALU2
+V 3600,4000,CONT_POLY,*
+V 3500,500,CONT_DIF_N,*
+V 4100,1000,CONT_DIF_N,*
+V 3000,4000,CONT_VIA,*
+V 0,4000,CONT_DIF_P,*
+V 0,3500,CONT_DIF_P,*
+V 0,4500,CONT_DIF_P,*
+V 0,3000,CONT_DIF_P,*
+V 1200,4000,CONT_DIF_P,*
+V 1200,4500,CONT_DIF_P,*
+V 3000,3000,CONT_DIF_P,*
+V 1800,3000,CONT_DIF_P,*
+V 2400,3500,CONT_DIF_P,*
+V 3500,4500,CONT_DIF_P,*
+V 2400,4700,CONT_BODY_N,*
+V 1800,4700,CONT_BODY_N,*
+V 600,4000,CONT_DIF_P,*
+V 600,3500,CONT_DIF_P,*
+V 600,3000,CONT_DIF_P,*
+V 1200,3500,CONT_DIF_P,*
+V 1200,1500,CONT_DIF_N,*
+V 2600,1500,CONT_DIF_N,*
+V 2600,1000,CONT_DIF_N,*
+V 0,1000,CONT_DIF_N,*
+V 0,1500,CONT_DIF_N,*
+V 0,500,CONT_DIF_N,*
+V 600,1000,CONT_DIF_N,*
+V 600,1500,CONT_DIF_N,*
+V 1200,1000,CONT_DIF_N,*
+V 2400,300,CONT_BODY_P,*
+V 1800,300,CONT_BODY_P,*
+V 2000,2500,CONT_POLY,*
+V 3400,1900,CONT_POLY,*
+V 500,4000,CONT_VIA,*
+V 2000,2500,CONT_VIA,*
+V 1000,2500,CONT_POLY,*
+V 1500,2000,CONT_VIA,*
+V 1500,2000,CONT_POLY,*
+V 4100,4000,CONT_DIF_P,*
+EOF
diff --git a/alliance/share/cells/rflib/rf_fifo_inc.vbe b/alliance/share/cells/rflib/rf_fifo_inc.vbe
new file mode 100644
index 00000000..ee01d1c5
--- /dev/null
+++ b/alliance/share/cells/rflib/rf_fifo_inc.vbe
@@ -0,0 +1,21 @@
+ENTITY rf_fifo_inc IS
+PORT (
+  ckm    : in  BIT;
+  nreset : in  BIT;
+  nval	 : in  BIT;
+  inc    : out BIT;
+  vdd	 : in  BIT;
+  vss	 : in  BIT
+);
+END rf_fifo_inc;
+
+ARCHITECTURE VBE OF rf_fifo_inc IS
+
+BEGIN
+  ASSERT (vdd and not (vss))
+  REPORT "power supply is missing on rf_fifo_inc"
+  SEVERITY WARNING;
+
+  inc <= (not nval) and nreset and ckm;
+
+END;
diff --git a/alliance/share/cells/rflib/rf_fifo_nop.ap b/alliance/share/cells/rflib/rf_fifo_nop.ap
new file mode 100644
index 00000000..eac030ca
--- /dev/null
+++ b/alliance/share/cells/rflib/rf_fifo_nop.ap
@@ -0,0 +1,107 @@
+V ALLIANCE : 6
+H rf_fifo_nop,P, 6/ 7/2000,100
+A 0,0,5000,5000
+S 1100,2500,1100,3000,200,*,DOWN,ALU1
+S 1100,3000,3000,3000,200,*,RIGHT,ALU1
+S 2600,1000,2600,3000,200,*,DOWN,ALU1
+S 3000,4000,3000,4000,200,nval,LEFT,CALU2
+S 4000,3000,4000,3000,200,rwok,LEFT,CALU2
+S 4500,1500,4500,1500,200,rw,LEFT,CALU2
+S 3000,4000,4100,4000,100,*,RIGHT,ALU1
+S 3500,1000,3500,4000,100,*,UP,ALU1
+S 4100,3900,4100,4700,300,*,UP,PDIF
+S 2000,2500,2000,2500,200,nreset,LEFT,CALU2
+S 1500,2000,1500,2000,200,ckm,LEFT,CALU2
+S 300,2500,1000,2500,300,*,RIGHT,POLY
+S 1200,3500,1200,4500,200,*,DOWN,ALU1
+S 3800,3000,4100,3000,300,*,RIGHT,POLY
+S 500,4000,500,4000,200,nop,LEFT,CALU2
+S 2400,3500,2400,4700,200,*,UP,ALU1
+S 0,4700,5000,4700,600,vdd,RIGHT,CALU1
+S 1200,500,1200,1500,200,*,DOWN,ALU1
+S 0,500,0,1500,200,*,UP,ALU1
+S 0,3000,0,4500,200,*,UP,ALU1
+S 0,300,5000,300,600,vss,RIGHT,CALU1
+S 300,1900,300,2600,100,*,DOWN,POLY
+S 900,1900,900,2600,100,*,DOWN,POLY
+S 2700,1900,2700,2600,100,*,DOWN,POLY
+S 1500,1900,1500,2600,100,*,DOWN,POLY
+S 2300,1900,3400,1900,100,*,RIGHT,POLY
+S 1900,1900,1900,2600,100,*,DOWN,POLY
+S 4400,900,4400,4100,100,*,UP,POLY
+S 3800,900,3800,4100,100,*,DOWN,POLY
+S 1200,800,1200,1700,300,*,DOWN,NDIF
+S 600,800,600,1700,300,*,DOWN,NDIF
+S 4700,300,4700,700,300,*,DOWN,NDIF
+S 4100,300,4100,700,300,*,DOWN,NDIF
+S 0,300,0,1700,300,*,DOWN,NDIF
+S 3500,300,3500,1100,300,*,DOWN,NDIF
+S 2600,800,2600,1700,300,*,DOWN,NDIF
+S 2300,600,2300,1900,100,*,UP,NTRANS
+S 1900,600,1900,1900,100,*,UP,NTRANS
+S 3800,100,3800,900,100,*,UP,NTRANS
+S 4400,100,4400,900,100,*,UP,NTRANS
+S 1500,600,1500,1900,100,*,UP,NTRANS
+S 300,600,300,1900,100,*,UP,NTRANS
+S 900,600,900,1900,100,*,UP,NTRANS
+S 2100,2600,2100,3900,100,*,UP,PTRANS
+S 2700,2600,2700,3900,100,*,UP,PTRANS
+S 1800,2800,1800,3700,300,*,DOWN,PDIF
+S 1500,2600,1500,3900,100,*,UP,PTRANS
+S 900,2600,900,4900,100,*,DOWN,PTRANS
+S 600,2800,600,4700,300,*,DOWN,PDIF
+S 1200,2800,1200,4700,300,*,DOWN,PDIF
+S 300,2600,300,4900,100,*,DOWN,PTRANS
+S 0,3900,5000,3900,2400,*,RIGHT,NWELL
+S 4700,4300,4700,4700,300,*,UP,PDIF
+S 3500,4300,3500,4700,300,*,UP,PDIF
+S 3800,4100,3800,4900,100,*,UP,PTRANS
+S 4400,4100,4400,4900,100,*,UP,PTRANS
+S 2400,2800,2400,3700,300,*,DOWN,PDIF
+S 3000,2800,3000,3700,300,*,DOWN,PDIF
+S 0,2800,0,4700,300,*,DOWN,PDIF
+S 500,1000,500,4000,200,*,UP,ALU1
+V 3000,4000,CONT_VIA,*
+V 4100,4000,CONT_DIF_P,*
+V 1500,2000,CONT_POLY,*
+V 1500,2000,CONT_VIA,*
+V 1000,2500,CONT_POLY,*
+V 4500,1500,CONT_POLY,*
+V 4500,1500,CONT_VIA,*
+V 4000,3000,CONT_VIA,*
+V 4000,3000,CONT_POLY,*
+V 2000,2500,CONT_VIA,*
+V 500,4000,CONT_VIA,*
+V 3400,1900,CONT_POLY,*
+V 2000,2500,CONT_POLY,*
+V 1800,300,CONT_BODY_P,*
+V 2400,300,CONT_BODY_P,*
+V 1200,1000,CONT_DIF_N,*
+V 600,1500,CONT_DIF_N,*
+V 600,1000,CONT_DIF_N,*
+V 0,500,CONT_DIF_N,*
+V 0,1500,CONT_DIF_N,*
+V 0,1000,CONT_DIF_N,*
+V 4700,500,CONT_DIF_N,*
+V 3500,1000,CONT_DIF_N,*
+V 2600,1000,CONT_DIF_N,*
+V 2600,1500,CONT_DIF_N,*
+V 1200,1500,CONT_DIF_N,*
+V 1200,3500,CONT_DIF_P,*
+V 600,3000,CONT_DIF_P,*
+V 600,3500,CONT_DIF_P,*
+V 600,4000,CONT_DIF_P,*
+V 1800,4700,CONT_BODY_N,*
+V 2400,4700,CONT_BODY_N,*
+V 4700,4500,CONT_DIF_P,*
+V 3500,4500,CONT_DIF_P,*
+V 2400,3500,CONT_DIF_P,*
+V 1800,3000,CONT_DIF_P,*
+V 3000,3000,CONT_DIF_P,*
+V 1200,4500,CONT_DIF_P,*
+V 1200,4000,CONT_DIF_P,*
+V 0,3000,CONT_DIF_P,*
+V 0,4500,CONT_DIF_P,*
+V 0,3500,CONT_DIF_P,*
+V 0,4000,CONT_DIF_P,*
+EOF
diff --git a/alliance/share/cells/rflib/rf_fifo_nop.vbe b/alliance/share/cells/rflib/rf_fifo_nop.vbe
new file mode 100644
index 00000000..b032c3a1
--- /dev/null
+++ b/alliance/share/cells/rflib/rf_fifo_nop.vbe
@@ -0,0 +1,24 @@
+ENTITY rf_fifo_nop IS
+PORT (
+  ckm    : in  BIT;
+  nreset : in  BIT;
+  rw     : in  BIT;
+  rwok   : in  BIT;
+  nval	 : inout BIT;
+  nop    : out BIT;
+  vdd	 : in  BIT;
+  vss	 : in  BIT
+);
+END rf_fifo_nop;
+
+ARCHITECTURE VBE OF rf_fifo_nop IS
+
+BEGIN
+  ASSERT (vdd and not (vss))
+  REPORT "power supply is missing on rf_fifo_nop"
+  SEVERITY WARNING;
+
+  nval <= rw nand rwok;
+  nop <= nval and nreset and ckm;
+
+END;
diff --git a/alliance/share/cells/rflib/rf_fifo_ok.ap b/alliance/share/cells/rflib/rf_fifo_ok.ap
new file mode 100644
index 00000000..e36b9f07
--- /dev/null
+++ b/alliance/share/cells/rflib/rf_fifo_ok.ap
@@ -0,0 +1,100 @@
+V ALLIANCE : 6
+H rf_fifo_ok,P,11/ 6/2000,10
+A 0,0,500,500
+S 250,150,250,300,10,*,UP,ALU1
+S 250,150,330,150,10,*,RIGHT,ALU1
+S 270,300,270,400,10,*,DOWN,ALU1
+S 450,350,450,350,20,ripple,LEFT,CALU2
+S 330,400,450,400,10,*,RIGHT,ALU1
+S 270,100,450,100,10,*,RIGHT,ALU1
+S 200,150,200,150,20,nrw,LEFT,CALU2
+S 350,250,350,250,20,rw,LEFT,CALU2
+S 50,200,300,200,20,prev,RIGHT,CALU2
+S 100,100,100,400,20,ok,DOWN,CALU1
+S 210,350,210,450,20,*,UP,ALU1
+S 150,50,150,100,20,*,DOWN,ALU1
+S 30,50,30,100,20,*,DOWN,ALU1
+S 150,350,150,450,20,*,UP,ALU1
+S 30,300,30,450,20,*,DOWN,ALU1
+S 40,200,120,200,30,*,RIGHT,POLY
+S 150,300,270,300,10,*,RIGHT,ALU1
+S 450,250,450,350,10,*,DOWN,ALU1
+S 420,250,460,250,30,*,RIGHT,POLY
+S 210,290,210,470,30,*,DOWN,PDIF
+S 240,140,240,270,10,*,UP,POLY
+S 240,270,240,490,10,*,UP,PTRANS
+S 210,30,210,120,30,*,UP,NDIF
+S 240,10,240,140,10,*,DOWN,NTRANS
+S 270,290,270,470,30,*,DOWN,PDIF
+S 300,140,300,270,10,*,UP,POLY
+S 300,270,300,490,10,*,UP,PTRANS
+S 270,30,270,120,30,*,UP,NDIF
+S 300,10,300,140,10,*,DOWN,NTRANS
+S 330,290,330,470,30,*,DOWN,PDIF
+S 360,140,360,270,10,*,UP,POLY
+S 360,270,360,490,10,*,UP,PTRANS
+S 330,30,330,120,30,*,UP,NDIF
+S 360,10,360,140,10,*,DOWN,NTRANS
+S 390,290,390,470,30,*,DOWN,PDIF
+S 420,140,420,270,10,*,UP,POLY
+S 420,270,420,490,10,*,UP,PTRANS
+S 390,30,390,120,30,*,UP,NDIF
+S 420,10,420,140,10,*,DOWN,NTRANS
+S 450,290,450,470,30,*,DOWN,PDIF
+S 450,30,450,120,30,*,UP,NDIF
+S 0,390,500,390,240,,RIGHT,NWELL
+S 0,30,500,30,60,vss,RIGHT,CALU1
+S 0,470,500,470,60,vdd,RIGHT,CALU1
+S 330,100,330,150,30,,UP,NDIF
+S 60,140,60,270,10,*,UP,POLY
+S 120,140,120,270,10,*,UP,POLY
+S 30,30,30,120,30,*,UP,NDIF
+S 90,30,90,120,30,*,UP,NDIF
+S 150,30,150,120,30,*,UP,NDIF
+S 60,10,60,140,10,*,DOWN,NTRANS
+S 120,10,120,140,10,*,DOWN,NTRANS
+S 90,290,90,470,30,*,DOWN,PDIF
+S 120,270,120,490,10,*,UP,PTRANS
+S 150,290,150,470,30,*,DOWN,PDIF
+S 30,290,30,470,30,*,DOWN,PDIF
+S 60,270,60,490,10,*,UP,PTRANS
+S 190,150,240,150,30,*,RIGHT,POLY
+S 150,300,150,300,20,nextval,LEFT,CALU2
+V 150,100,CONT_DIF_N,*
+V 30,100,CONT_DIF_N,*
+V 30,300,CONT_DIF_P,*
+V 30,350,CONT_DIF_P,*
+V 30,400,CONT_DIF_P,*
+V 150,350,CONT_DIF_P,*
+V 150,400,CONT_DIF_P,*
+V 210,350,CONT_DIF_P,*
+V 210,400,CONT_DIF_P,*
+V 90,350,CONT_DIF_P,*
+V 90,300,CONT_DIF_P,*
+V 50,200,CONT_POLY,*
+V 50,200,CONT_VIA,*
+V 150,300,CONT_VIA,*
+V 450,250,CONT_POLY,*
+V 450,350,CONT_VIA,*
+V 210,450,CONT_DIF_P,*
+V 210,50,CONT_DIF_N,*
+V 270,400,CONT_DIF_P,*
+V 330,400,CONT_DIF_P,*
+V 390,450,CONT_DIF_P,*
+V 450,400,CONT_DIF_P,*
+V 330,150,CONT_DIF_N,*
+V 450,100,CONT_DIF_N,*
+V 270,100,CONT_DIF_N,*
+V 90,100,CONT_DIF_N,*
+V 30,50,CONT_DIF_N,*
+V 30,450,CONT_DIF_P,*
+V 90,400,CONT_DIF_P,*
+V 150,450,CONT_DIF_P,*
+V 150,50,CONT_DIF_N,*
+V 350,250,CONT_POLY,*
+V 300,200,CONT_POLY,*
+V 300,200,CONT_VIA,*
+V 350,250,CONT_VIA,*
+V 200,150,CONT_VIA,*
+V 200,150,CONT_POLY,*
+EOF
diff --git a/alliance/share/cells/rflib/rf_fifo_ok.vbe b/alliance/share/cells/rflib/rf_fifo_ok.vbe
new file mode 100644
index 00000000..5537c904
--- /dev/null
+++ b/alliance/share/cells/rflib/rf_fifo_ok.vbe
@@ -0,0 +1,24 @@
+ENTITY rf_fifo_ok IS
+PORT (
+  rw      : in  BIT;
+  ripple  : in  BIT;
+  nrw 	  : in  BIT;
+  prev    : in  BIT;
+  nextval : out BIT;
+  ok      : out BIT;
+  vdd	  : in  BIT;
+  vss	  : in  BIT
+);
+END rf_fifo_ok;
+
+ARCHITECTURE VBE OF rf_fifo_ok IS
+
+BEGIN
+  ASSERT (vdd and not (vss))
+  REPORT "power supply is missing on rf_fifo_ok"
+  SEVERITY WARNING;
+
+  ok <= (not prev);
+  nextval <= not(((rw and ripple) or prev) and nrw);
+
+END;
diff --git a/alliance/share/cells/rflib/rf_fifo_orand4.ap b/alliance/share/cells/rflib/rf_fifo_orand4.ap
new file mode 100644
index 00000000..dfe080d6
--- /dev/null
+++ b/alliance/share/cells/rflib/rf_fifo_orand4.ap
@@ -0,0 +1,79 @@
+V ALLIANCE : 6
+H rf_fifo_orand4,P,11/ 6/2000,10
+A 0,0,500,500
+S 150,100,290,100,10,*,RIGHT,ALU1
+S 150,350,230,350,10,*,RIGHT,ALU1
+S 150,100,150,350,10,*,DOWN,ALU1
+S 250,150,250,300,10,b1,DOWN,CALU1
+S 200,150,200,300,10,a1,DOWN,CALU1
+S 380,270,380,490,10,*,UP,PTRANS
+S 410,290,410,470,30,*,DOWN,PDIF
+S 290,290,290,470,30,*,DOWN,PDIF
+S 320,270,320,490,10,*,UP,PTRANS
+S 350,290,350,470,30,*,DOWN,PDIF
+S 290,290,290,470,30,*,DOWN,PDIF
+S 260,270,260,490,10,*,UP,PTRANS
+S 230,290,230,470,30,*,DOWN,PDIF
+S 200,270,200,490,10,*,UP,PTRANS
+S 170,290,170,470,30,*,DOWN,PDIF
+S 260,10,260,140,10,*,DOWN,NTRANS
+S 200,10,200,140,10,*,DOWN,NTRANS
+S 320,10,320,140,10,*,DOWN,NTRANS
+S 380,10,380,140,10,*,DOWN,NTRANS
+S 290,30,290,120,30,*,UP,NDIF
+S 350,30,350,120,30,*,UP,NDIF
+S 410,30,410,120,30,*,UP,NDIF
+S 290,30,290,120,30,*,UP,NDIF
+S 230,30,230,120,30,*,UP,NDIF
+S 170,30,170,120,30,*,UP,NDIF
+S 320,250,340,250,30,,LEFT,POLY
+S 320,140,320,270,10,*,UP,POLY
+S 380,140,380,270,10,*,UP,POLY
+S 380,250,400,250,30,,RIGHT,POLY
+S 260,140,260,270,10,*,UP,POLY
+S 200,140,200,270,10,*,UP,POLY
+S 400,100,400,350,10,b0,DOWN,CALU1
+S 350,100,350,350,10,a0,DOWN,CALU1
+S 290,400,410,400,10,aux11,RIGHT,ALU1
+S 170,400,290,400,10,aux12,RIGHT,ALU1
+S 100,100,100,400,10,rippleout,UP,CALU1
+S 0,470,500,470,60,vdd,RIGHT,CALU1
+S 40,30,40,100,20,*,DOWN,ALU1
+S 40,300,40,470,20,*,DOWN,ALU1
+S 0,30,500,30,60,vss,RIGHT,CALU1
+S 70,160,70,270,10,*,DOWN,POLY
+S 70,200,150,200,30,*,RIGHT,POLY
+S 100,80,100,140,30,*,DOWN,NDIF
+S 40,80,40,140,30,*,DOWN,NDIF
+S 70,60,70,160,10,*,UP,NTRANS
+S 0,390,500,390,240,,RIGHT,NWELL
+S 100,290,100,420,30,*,UP,PDIF
+S 40,290,40,420,30,*,UP,PDIF
+S 70,270,70,440,10,*,DOWN,PTRANS
+V 150,200,CONT_POLY,*
+V 200,250,CONT_POLY,*
+V 340,250,CONT_POLY,*
+V 410,400,CONT_DIF_P,*
+V 290,400,CONT_DIF_P,*
+V 230,350,CONT_DIF_P,*
+V 350,450,CONT_DIF_P,*
+V 290,400,CONT_DIF_P,*
+V 170,400,CONT_DIF_P,*
+V 410,50,CONT_DIF_N,*
+V 290,100,CONT_DIF_N,*
+V 170,50,CONT_DIF_N,*
+V 400,250,CONT_POLY,*
+V 260,250,CONT_POLY,*
+V 40,30,CONT_BODY_P,*
+V 100,30,CONT_BODY_P,*
+V 100,100,CONT_DIF_N,*
+V 40,100,CONT_DIF_N,*
+V 40,350,CONT_DIF_P,*
+V 40,470,CONT_BODY_N,*
+V 100,470,CONT_BODY_N,*
+V 40,300,CONT_DIF_P,*
+V 40,400,CONT_DIF_P,*
+V 100,300,CONT_DIF_P,*
+V 100,350,CONT_DIF_P,*
+V 100,400,CONT_DIF_P,*
+EOF
diff --git a/alliance/share/cells/rflib/rf_fifo_orand4.vbe b/alliance/share/cells/rflib/rf_fifo_orand4.vbe
new file mode 100644
index 00000000..fae9974d
--- /dev/null
+++ b/alliance/share/cells/rflib/rf_fifo_orand4.vbe
@@ -0,0 +1,22 @@
+ENTITY rf_fifo_orand4 IS
+PORT (
+  a0        : in  BIT;
+  b0        : in  BIT;
+  a1        : in  BIT;
+  b1        : in  BIT;
+  rippleout : out BIT;
+  vdd	    : in  BIT;
+  vss       : in  BIT
+);
+END rf_fifo_orand4;
+
+ARCHITECTURE VBE OF rf_fifo_orand4 IS
+
+BEGIN
+  ASSERT (vdd and not (vss))
+  REPORT "power supply is missing on rf_fifo_orand4"
+  SEVERITY WARNING;
+
+  rippleout <= (a0 and b0) or (a1 and b1);
+
+END;
diff --git a/alliance/share/cells/rflib/rf_fifo_orand5.ap b/alliance/share/cells/rflib/rf_fifo_orand5.ap
new file mode 100644
index 00000000..e49afec6
--- /dev/null
+++ b/alliance/share/cells/rflib/rf_fifo_orand5.ap
@@ -0,0 +1,86 @@
+V ALLIANCE : 6
+H rf_fifo_orand5,P,11/ 6/2000,10
+A 0,0,500,500
+S 100,100,100,400,10,rippleout,UP,CALU1
+S 250,150,250,300,10,b1,DOWN,CALU1
+S 200,150,200,300,10,a1,DOWN,CALU1
+S 450,150,450,300,10,b0,DOWN,CALU1
+S 350,150,350,300,10,a0,DOWN,CALU1
+S 300,150,300,300,10,ripplein,DOWN,CALU1
+S 280,100,460,100,10,sor,RIGHT,ALU1
+S 0,470,500,470,60,vdd,RIGHT,CALU1
+S 40,30,40,100,20,*,DOWN,ALU1
+S 40,300,40,470,20,*,DOWN,ALU1
+S 150,100,460,100,10,sor,RIGHT,ALU1
+S 150,100,150,350,10,*,DOWN,ALU1
+S 150,350,400,350,10,sor,RIGHT,ALU1
+S 160,400,280,400,10,aux12,RIGHT,ALU1
+S 340,400,460,400,10,aux11,RIGHT,ALU1
+S 0,30,500,30,60,vss,RIGHT,CALU1
+S 310,140,310,270,10,*,UP,POLY
+S 250,140,250,270,10,*,UP,POLY
+S 190,140,190,270,10,*,UP,POLY
+S 350,250,370,250,30,,LEFT,POLY
+S 430,140,430,270,10,*,UP,POLY
+S 370,140,370,270,10,*,UP,POLY
+S 70,160,70,270,10,*,DOWN,POLY
+S 70,200,150,200,30,*,RIGHT,POLY
+S 430,250,450,250,30,,RIGHT,POLY
+S 280,30,280,120,30,*,UP,NDIF
+S 220,30,220,120,30,*,UP,NDIF
+S 160,30,160,120,30,*,UP,NDIF
+S 460,30,460,120,30,*,UP,NDIF
+S 400,30,400,120,30,*,UP,NDIF
+S 340,30,340,120,30,*,UP,NDIF
+S 100,80,100,140,30,*,DOWN,NDIF
+S 40,80,40,140,30,*,DOWN,NDIF
+S 70,60,70,160,10,*,UP,NTRANS
+S 430,10,430,140,10,*,DOWN,NTRANS
+S 370,10,370,140,10,*,DOWN,NTRANS
+S 310,10,310,140,10,*,DOWN,NTRANS
+S 250,10,250,140,10,*,DOWN,NTRANS
+S 190,10,190,140,10,*,DOWN,NTRANS
+S 340,290,340,470,30,*,DOWN,PDIF
+S 310,270,310,490,10,*,UP,PTRANS
+S 280,290,280,470,30,*,DOWN,PDIF
+S 250,270,250,490,10,*,UP,PTRANS
+S 220,290,220,470,30,*,DOWN,PDIF
+S 190,270,190,490,10,*,UP,PTRANS
+S 160,290,160,470,30,*,DOWN,PDIF
+S 0,390,500,390,240,,RIGHT,NWELL
+S 100,290,100,420,30,*,UP,PDIF
+S 40,290,40,420,30,*,UP,PDIF
+S 70,270,70,440,10,*,DOWN,PTRANS
+S 460,290,460,470,30,*,DOWN,PDIF
+S 430,270,430,490,10,*,UP,PTRANS
+S 400,290,400,470,30,*,DOWN,PDIF
+S 370,270,370,490,10,*,UP,PTRANS
+V 300,250,CONT_POLY,*
+V 250,250,CONT_POLY,*
+V 200,250,CONT_POLY,*
+V 150,200,CONT_POLY,*
+V 450,250,CONT_POLY,*
+V 350,250,CONT_POLY,*
+V 40,30,CONT_BODY_P,*
+V 100,30,CONT_BODY_P,*
+V 460,100,CONT_DIF_N,*
+V 340,50,CONT_DIF_N,*
+V 280,100,CONT_DIF_N,*
+V 160,50,CONT_DIF_N,*
+V 100,100,CONT_DIF_N,*
+V 40,100,CONT_DIF_N,*
+V 40,350,CONT_DIF_P,*
+V 280,400,CONT_DIF_P,*
+V 160,400,CONT_DIF_P,*
+V 460,400,CONT_DIF_P,*
+V 40,470,CONT_BODY_N,*
+V 100,470,CONT_BODY_N,*
+V 220,450,CONT_DIF_P,*
+V 40,300,CONT_DIF_P,*
+V 40,400,CONT_DIF_P,*
+V 100,300,CONT_DIF_P,*
+V 100,350,CONT_DIF_P,*
+V 100,400,CONT_DIF_P,*
+V 400,350,CONT_DIF_P,*
+V 340,400,CONT_DIF_P,*
+EOF
diff --git a/alliance/share/cells/rflib/rf_fifo_orand5.vbe b/alliance/share/cells/rflib/rf_fifo_orand5.vbe
new file mode 100644
index 00000000..6307f9c8
--- /dev/null
+++ b/alliance/share/cells/rflib/rf_fifo_orand5.vbe
@@ -0,0 +1,23 @@
+ENTITY rf_fifo_orand5 IS
+PORT (
+  a0        : in  BIT;
+  b0        : in  BIT;
+  a1        : in  BIT;
+  b1        : in  BIT;
+  ripplein  : in  BIT;
+  rippleout : out BIT;
+  vdd	    : in  BIT;
+  vss       : in  BIT
+);
+END rf_fifo_orand5;
+
+ARCHITECTURE VBE OF rf_fifo_orand5 IS
+
+BEGIN
+  ASSERT (vdd and not (vss))
+  REPORT "power supply is missing on rf_fifo_orand5"
+  SEVERITY WARNING;
+
+  rippleout <= ripplein or (a0 and b0) or (a1 and b1);
+
+END;
diff --git a/alliance/share/cells/rflib/rf_fifo_ptreset.ap b/alliance/share/cells/rflib/rf_fifo_ptreset.ap
new file mode 100644
index 00000000..0ed7fd35
--- /dev/null
+++ b/alliance/share/cells/rflib/rf_fifo_ptreset.ap
@@ -0,0 +1,119 @@
+V ALLIANCE : 6
+H rf_fifo_ptreset,P,11/ 6/2000,10
+A 0,0,500,500
+S 100,200,400,200,20,*,RIGHT,TALU2
+S 150,200,150,200,20,cks,LEFT,CALU3
+S 350,200,350,200,20,nop,LEFT,CALU3
+S 250,200,250,200,20,reset,LEFT,CALU3
+S 300,200,300,200,20,inc,LEFT,CALU3
+S 100,200,150,200,20,*,LEFT,ALU2
+S 350,200,400,200,20,*,RIGHT,ALU2
+S 0,390,500,390,240,*,RIGHT,NWELL
+S 0,50,0,150,20,*,DOWN,ALU1
+S 500,50,500,150,20,*,UP,ALU1
+S 440,100,450,100,20,*,RIGHT,ALU1
+S 440,400,450,400,20,*,RIGHT,ALU1
+S 50,100,60,100,20,*,RIGHT,ALU1
+S 50,400,60,400,20,*,RIGHT,ALU1
+S 210,190,250,190,10,*,RIGHT,POLY
+S 450,100,450,400,20,pt,DOWN,ALU1
+S 300,100,300,100,20,ptm1,LEFT,CALU2
+S 30,250,350,250,10,*,LEFT,POLY
+S 150,300,470,300,10,*,RIGHT,POLY
+S 370,100,370,150,20,*,DOWN,ALU1
+S 350,150,350,350,20,x,UP,ALU1
+S 120,100,150,100,20,*,RIGHT,ALU1
+S 150,100,150,350,20,z,UP,ALU1
+S 50,100,50,400,20,y,DOWN,ALU1
+S 240,150,360,150,20,*,LEFT,ALU1
+S 240,100,240,150,20,*,UP,ALU1
+S 0,350,0,450,20,*,DOWN,ALU1
+S 500,350,500,450,20,*,UP,ALU1
+S 290,190,330,190,10,*,RIGHT,POLY
+S 470,190,470,310,10,*,DOWN,POLY
+S 30,190,30,310,10,*,DOWN,POLY
+S 30,310,30,490,10,*,DOWN,PTRANS
+S 0,330,0,470,30,*,DOWN,PDIF
+S 60,330,60,470,30,*,DOWN,PDIF
+S 30,10,30,190,10,*,UP,NTRANS
+S 0,30,0,170,30,*,DOWN,NDIF
+S 60,30,60,170,30,*,DOWN,NDIF
+S 500,330,500,470,30,*,DOWN,PDIF
+S 500,30,500,170,30,*,DOWN,NDIF
+S 440,330,440,470,30,*,DOWN,PDIF
+S 440,30,440,170,30,*,DOWN,NDIF
+S 470,310,470,490,10,*,DOWN,PTRANS
+S 470,10,470,190,10,*,UP,NTRANS
+S 0,470,500,470,60,vdd,RIGHT,CALU1
+S 0,30,500,30,60,vss,RIGHT,CALU1
+S 330,400,380,400,50,*,RIGHT,PTRANS
+S 120,400,170,400,50,*,RIGHT,PTRANS
+S 50,350,400,350,20,*,LEFT,ALU2
+S 180,400,440,400,20,*,RIGHT,ALU1
+S 180,380,180,420,30,*,DOWN,POLY
+S 390,380,390,420,30,*,DOWN,POLY
+S 400,350,400,420,30,*,UP,POLY
+S 330,60,330,190,10,*,UP,NTRANS
+S 300,80,300,170,30,*,DOWN,NDIF
+S 410,60,410,190,10,*,UP,NTRANS
+S 370,80,370,170,50,*,DOWN,NDIF
+S 210,60,210,190,10,*,UP,NTRANS
+S 180,40,180,170,30,*,DOWN,NDIF
+S 240,80,240,170,30,*,DOWN,NDIF
+S 90,60,90,190,10,*,UP,NTRANS
+S 120,80,120,170,30,*,DOWN,NDIF
+S 400,100,450,100,20,pt,LEFT,CALU2
+S 50,350,400,350,20,*,RIGHT,TALU2
+V 150,200,CONT_VIA2,*
+V 350,200,CONT_VIA2,*
+V 300,200,CONT_VIA2,*
+V 250,200,CONT_VIA2,*
+V 250,200,CONT_POLY,*
+V 250,200,CONT_VIA,*
+V 300,200,CONT_VIA,*
+V 400,200,CONT_VIA,*
+V 290,470,CONT_BODY_N,*
+V 210,470,CONT_BODY_N,*
+V 450,100,CONT_VIA,*
+V 370,100,CONT_DIF_N,*
+V 370,150,CONT_DIF_N,*
+V 150,300,CONT_POLY,*
+V 350,350,CONT_DIF_P,*
+V 150,350,CONT_DIF_P,*
+V 100,200,CONT_VIA,*
+V 240,100,CONT_DIF_N,*
+V 240,150,CONT_DIF_N,*
+V 0,350,CONT_DIF_P,*
+V 0,400,CONT_DIF_P,*
+V 500,400,CONT_DIF_P,*
+V 500,350,CONT_DIF_P,*
+V 0,100,CONT_DIF_N,*
+V 0,150,CONT_DIF_N,*
+V 500,100,CONT_DIF_N,*
+V 500,150,CONT_DIF_N,*
+V 300,100,CONT_VIA,*
+V 400,200,CONT_POLY,*
+V 350,250,CONT_POLY,*
+V 300,100,CONT_DIF_N,*
+V 300,200,CONT_POLY,*
+V 180,50,CONT_DIF_N,*
+V 100,200,CONT_POLY,*
+V 0,450,CONT_DIF_P,*
+V 500,450,CONT_DIF_P,*
+V 0,50,CONT_DIF_N,*
+V 500,50,CONT_DIF_N,*
+V 120,100,CONT_DIF_N,*
+V 60,400,CONT_DIF_P,*
+V 60,100,CONT_DIF_N,*
+V 440,400,CONT_DIF_P,*
+V 440,100,CONT_DIF_N,*
+V 350,450,CONT_DIF_P,*
+V 150,450,CONT_DIF_P,*
+V 180,400,CONT_POLY,*
+V 400,350,CONT_POLY,*
+V 50,350,CONT_VIA,*
+V 400,350,CONT_VIA,*
+V 300,30,CONT_BODY_P,*
+V 370,30,CONT_BODY_P,*
+V 120,30,CONT_BODY_P,*
+EOF
diff --git a/alliance/share/cells/rflib/rf_fifo_ptreset.vbe b/alliance/share/cells/rflib/rf_fifo_ptreset.vbe
new file mode 100644
index 00000000..392a043d
--- /dev/null
+++ b/alliance/share/cells/rflib/rf_fifo_ptreset.vbe
@@ -0,0 +1,45 @@
+ENTITY rf_fifo_ptreset IS
+PORT (
+  nop 	 : in  BIT;
+  inc 	 : in  BIT;
+  cks    : in  BIT;
+  reset  : in  BIT;
+  ptm1   : in  BIT;
+  pt     : inout BIT;
+  vdd	 : in  BIT;
+  vss	 : in  BIT
+);
+END rf_fifo_ptreset;
+
+ARCHITECTURE VBE OF rf_fifo_ptreset IS
+  SIGNAL latchm	 : REG_BIT REGISTER;
+  SIGNAL latchs	 : REG_BIT REGISTER;
+
+BEGIN
+  ASSERT (vdd and not (vss))
+  REPORT "power supply is missing on rf_fifo_ptreset"
+  SEVERITY WARNING;
+
+  label0 : BLOCK (inc = '1')
+  BEGIN
+    latchm <= GUARDED ptm1;
+  END BLOCK label0;
+
+  label1 : BLOCK (reset = '1')
+  BEGIN
+    latchm <= GUARDED '0';
+  END BLOCK label1;
+
+  label2 : BLOCK (nop = '1')
+  BEGIN
+    latchm <= GUARDED pt;
+  END BLOCK label2;
+
+  label3 : BLOCK (cks = '1')
+  BEGIN
+    latchs <= GUARDED (not latchm);
+  END BLOCK label3;
+
+  pt <= (not latchs);
+
+END;
diff --git a/alliance/share/cells/rflib/rf_fifo_ptset.ap b/alliance/share/cells/rflib/rf_fifo_ptset.ap
new file mode 100644
index 00000000..2bcc24cf
--- /dev/null
+++ b/alliance/share/cells/rflib/rf_fifo_ptset.ap
@@ -0,0 +1,115 @@
+V ALLIANCE : 6
+H rf_fifo_ptset,P,11/ 6/2000,10
+A 0,0,500,500
+S 50,350,400,350,20,*,RIGHT,TALU2
+S 100,200,400,200,20,*,RIGHT,TALU2
+S 350,200,350,200,20,nop,LEFT,CALU3
+S 450,100,450,400,20,*,DOWN,ALU1
+S 400,100,450,100,20,pt,LEFT,CALU2
+S 120,80,120,170,30,*,DOWN,NDIF
+S 90,60,90,190,10,*,UP,NTRANS
+S 300,80,300,170,30,*,DOWN,NDIF
+S 370,80,370,170,50,*,DOWN,NDIF
+S 410,60,410,190,10,*,UP,NTRANS
+S 330,60,330,190,10,*,UP,NTRANS
+S 180,400,440,400,20,*,RIGHT,ALU1
+S 200,150,200,300,20,*,DOWN,ALU1
+S 280,350,350,350,20,*,RIGHT,ALU1
+S 200,150,350,150,20,*,RIGHT,ALU1
+S 350,100,350,350,20,x,UP,ALU1
+S 350,100,370,100,20,*,RIGHT,ALU1
+S 180,380,180,420,30,*,DOWN,POLY
+S 390,340,390,420,30,*,UP,POLY
+S 50,400,60,400,20,*,RIGHT,ALU1
+S 50,100,60,100,20,*,RIGHT,ALU1
+S 440,100,450,100,20,*,RIGHT,ALU1
+S 440,400,450,400,20,*,RIGHT,ALU1
+S 50,350,400,350,20,*,RIGHT,ALU2
+S 330,400,380,400,50,*,RIGHT,PTRANS
+S 120,400,170,400,50,*,RIGHT,PTRANS
+S 30,300,200,300,10,*,RIGHT,POLY
+S 150,250,470,250,10,*,RIGHT,POLY
+S 220,330,220,470,30,*,DOWN,PDIF
+S 280,330,280,470,30,*,DOWN,PDIF
+S 250,310,250,490,10,*,DOWN,PTRANS
+S 0,30,500,30,60,vss,RIGHT,CALU1
+S 0,470,500,470,60,vdd,RIGHT,CALU1
+S 470,10,470,190,10,*,UP,NTRANS
+S 470,310,470,490,10,*,DOWN,PTRANS
+S 440,30,440,170,30,*,DOWN,NDIF
+S 440,330,440,470,30,*,DOWN,PDIF
+S 500,30,500,170,30,*,DOWN,NDIF
+S 500,330,500,470,30,*,DOWN,PDIF
+S 60,30,60,170,30,*,DOWN,NDIF
+S 0,30,0,170,30,*,DOWN,NDIF
+S 30,10,30,190,10,*,UP,NTRANS
+S 60,330,60,470,30,*,DOWN,PDIF
+S 0,330,0,470,30,*,DOWN,PDIF
+S 30,310,30,490,10,*,DOWN,PTRANS
+S 30,190,30,310,10,*,DOWN,POLY
+S 470,190,470,310,10,*,DOWN,POLY
+S 290,190,330,190,10,*,RIGHT,POLY
+S 500,350,500,450,20,*,UP,ALU1
+S 0,350,0,450,20,*,DOWN,ALU1
+S 50,100,50,400,20,y,DOWN,ALU1
+S 150,100,150,350,20,z,UP,ALU1
+S 120,100,150,100,20,*,RIGHT,ALU1
+S 300,100,300,100,20,ptm1,LEFT,CALU2
+S 250,200,250,300,20,*,DOWN,ALU1
+S 500,50,500,150,20,*,UP,ALU1
+S 0,50,0,150,20,*,DOWN,ALU1
+S 0,390,500,390,240,*,RIGHT,NWELL
+S 250,200,250,200,20,nreset,LEFT,CALU3
+S 150,200,150,200,20,cks,LEFT,CALU3
+S 350,200,400,200,20,*,RIGHT,ALU2
+S 100,200,150,200,20,*,LEFT,ALU2
+S 300,200,300,200,20,inc,LEFT,CALU3
+V 370,30,CONT_BODY_P,*
+V 300,30,CONT_BODY_P,*
+V 120,30,CONT_BODY_P,*
+V 400,350,CONT_POLY,*
+V 400,350,CONT_VIA,*
+V 50,350,CONT_VIA,*
+V 350,450,CONT_DIF_P,*
+V 150,450,CONT_DIF_P,*
+V 180,400,CONT_POLY,*
+V 200,300,CONT_POLY,*
+V 250,300,CONT_POLY,*
+V 150,250,CONT_POLY,*
+V 280,350,CONT_DIF_P,*
+V 220,450,CONT_DIF_P,*
+V 440,100,CONT_DIF_N,*
+V 440,400,CONT_DIF_P,*
+V 60,100,CONT_DIF_N,*
+V 60,400,CONT_DIF_P,*
+V 120,100,CONT_DIF_N,*
+V 500,50,CONT_DIF_N,*
+V 0,50,CONT_DIF_N,*
+V 500,450,CONT_DIF_P,*
+V 0,450,CONT_DIF_P,*
+V 100,200,CONT_POLY,*
+V 300,200,CONT_POLY,*
+V 300,100,CONT_DIF_N,*
+V 400,200,CONT_POLY,*
+V 300,100,CONT_VIA,*
+V 500,150,CONT_DIF_N,*
+V 500,100,CONT_DIF_N,*
+V 0,150,CONT_DIF_N,*
+V 0,100,CONT_DIF_N,*
+V 500,350,CONT_DIF_P,*
+V 500,400,CONT_DIF_P,*
+V 0,400,CONT_DIF_P,*
+V 0,350,CONT_DIF_P,*
+V 100,200,CONT_VIA,*
+V 150,350,CONT_DIF_P,*
+V 350,350,CONT_DIF_P,*
+V 370,100,CONT_DIF_N,*
+V 450,100,CONT_VIA,*
+V 250,200,CONT_VIA,*
+V 300,200,CONT_VIA,*
+V 400,200,CONT_VIA,*
+V 150,200,CONT_VIA2,*
+V 250,200,CONT_VIA2,*
+V 300,200,CONT_VIA2,*
+V 350,200,CONT_VIA2,*
+EOF
diff --git a/alliance/share/cells/rflib/rf_fifo_ptset.vbe b/alliance/share/cells/rflib/rf_fifo_ptset.vbe
new file mode 100644
index 00000000..ac804b83
--- /dev/null
+++ b/alliance/share/cells/rflib/rf_fifo_ptset.vbe
@@ -0,0 +1,45 @@
+ENTITY rf_fifo_ptset IS
+PORT (
+  nop 	 : in  BIT;
+  inc 	 : in  BIT;
+  cks    : in  BIT;
+  nreset : in  BIT;
+  ptm1   : in  BIT;
+  pt     : inout BIT;
+  vdd	 : in  BIT;
+  vss	 : in  BIT
+);
+END rf_fifo_ptset;
+
+ARCHITECTURE VBE OF rf_fifo_ptset IS
+  SIGNAL latchm	 : REG_BIT REGISTER;
+  SIGNAL latchs	 : REG_BIT REGISTER;
+
+BEGIN
+  ASSERT (vdd and not (vss))
+  REPORT "power supply is missing on rf_fifo_ptset"
+  SEVERITY WARNING;
+
+  label0 : BLOCK (inc = '1')
+  BEGIN
+    latchm <= GUARDED ptm1;
+  END BLOCK label0;
+
+  label1 : BLOCK (nreset = '0')
+  BEGIN
+    latchm <= GUARDED '1';
+  END BLOCK label1;
+
+  label2 : BLOCK (nop = '1')
+  BEGIN
+    latchm <= GUARDED pt;
+  END BLOCK label2;
+
+  label3 : BLOCK (cks = '1')
+  BEGIN
+    latchs <= GUARDED (not latchm);
+  END BLOCK label3;
+
+  pt <= (not latchs);
+
+END;
diff --git a/alliance/share/cells/rflib/rf_mid_mem_r0.ap b/alliance/share/cells/rflib/rf_mid_mem_r0.ap
new file mode 100644
index 00000000..82532efd
--- /dev/null
+++ b/alliance/share/cells/rflib/rf_mid_mem_r0.ap
@@ -0,0 +1,29 @@
+V ALLIANCE : 6
+H rf_mid_mem_r0,P, 4/11/2000,10
+A 0,0,250,500
+S 0,230,190,230,20,*,RIGHT,ALU1
+S 190,220,190,270,30,*,UP,NDIF
+S 50,300,50,300,20,read,LEFT,CALU3
+S 200,150,200,150,20,write,LEFT,CALU3
+S 220,200,220,290,10,*,UP,NTRANS
+S 0,30,0,230,20,*,UP,ALU1
+S 0,160,0,270,30,*,UP,NDIF
+S 150,290,220,290,10,*,RIGHT,POLY
+S 0,430,250,430,160,*,RIGHT,NWELL
+S 250,220,250,270,30,*,UP,NDIF
+S 50,300,150,300,20,*,RIGHT,ALU2
+S 0,30,250,30,60,vss,RIGHT,CALU1
+S 0,470,250,470,60,vdd,RIGHT,CALU1
+S 250,100,250,100,20,dinx,LEFT,CALU2
+S 50,300,150,300,20,ck,RIGHT,TALU2
+S 250,250,250,250,20,rbus,LEFT,CALU2
+V 190,230,CONT_DIF_N,*
+V 200,500,CONT_BODY_N,*
+V 250,250,CONT_DIF_N,*
+V 0,230,CONT_DIF_N,*
+V 150,300,CONT_POLY,*
+V 0,170,CONT_DIF_N,*
+V 150,300,CONT_VIA,*
+V 50,300,CONT_VIA2,*
+V 250,250,CONT_VIA,*
+EOF
diff --git a/alliance/share/cells/rflib/rf_mid_mem_r0.vbe b/alliance/share/cells/rflib/rf_mid_mem_r0.vbe
new file mode 100644
index 00000000..2290b20f
--- /dev/null
+++ b/alliance/share/cells/rflib/rf_mid_mem_r0.vbe
@@ -0,0 +1,25 @@
+ENTITY rf_mid_mem_r0 IS
+PORT (
+  dinx	 : in  BIT;
+  write  : in  BIT;
+  read   : in  BIT;
+  rbus   : out MUX_BIT BUS;
+  vdd	 : in  BIT;
+  vss	 : in  BIT
+);
+END rf_mid_mem_r0;
+
+ARCHITECTURE VBE OF rf_mid_mem_r0 IS
+  SIGNAL latch	 : REG_BIT REGISTER;
+
+BEGIN
+  ASSERT (vdd and not (vss))
+  REPORT "power supply is missing on rf_mid_mem_r0"
+  SEVERITY WARNING;
+
+  label1 : BLOCK (read = '1')
+  BEGIN
+    rbus <= GUARDED '0';
+  END BLOCK label1;
+
+END;